19 files changed, 927 insertions, 209 deletions

diff --git a/libc/sysdeps/linux/arc/bits/fenv.h b/libc/sysdeps/linux/arc/bits/fenv.h
new file mode 100644
index 000000000..c5c76cb93
--- /dev/null
+++ b/libc/sysdeps/linux/arc/bits/fenv.h
@@ -0,0 +1,75 @@
+/* Floating point environment.  ARC version.
+   Copyright (C) 2020-2025 Free Software Foundation, Inc.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library.  If not, see
+   <https://www.gnu.org/licenses/>.  */
+
+#ifndef _FENV_H
+# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
+#endif
+
+enum
+  {
+    FE_INVALID   =
+# define FE_INVALID	(0x01)
+      FE_INVALID,
+    FE_DIVBYZERO =
+# define FE_DIVBYZERO	(0x02)
+      FE_DIVBYZERO,
+    FE_OVERFLOW  =
+# define FE_OVERFLOW	(0x04)
+      FE_OVERFLOW,
+    FE_UNDERFLOW =
+# define FE_UNDERFLOW	(0x08)
+      FE_UNDERFLOW,
+    FE_INEXACT   =
+# define FE_INEXACT	(0x10)
+      FE_INEXACT
+  };
+
+# define FE_ALL_EXCEPT \
+	(FE_INVALID | FE_DIVBYZERO | FE_OVERFLOW | FE_UNDERFLOW | FE_INEXACT)
+
+enum
+  {
+    FE_TOWARDZERO =
+# define FE_TOWARDZERO	(0x0)
+      FE_TOWARDZERO,
+    FE_TONEAREST  =
+# define FE_TONEAREST	(0x1)	/* default */
+      FE_TONEAREST,
+    FE_UPWARD     =
+# define FE_UPWARD	(0x2)
+      FE_UPWARD,
+    FE_DOWNWARD   =
+# define FE_DOWNWARD	(0x3)
+      FE_DOWNWARD
+  };
+
+typedef unsigned int fexcept_t;
+
+typedef struct
+{
+  unsigned int __fpcr;
+  unsigned int __fpsr;
+} fenv_t;
+
+/* If the default argument is used we use this value.  */
+#define FE_DFL_ENV	((const fenv_t *) -1)
+
+/* Type representing floating-point control modes.  */
+typedef unsigned int femode_t;
+
+/* Default floating-point control modes.  */
+# define FE_DFL_MODE	((const femode_t *) -1L)
diff --git a/libc/sysdeps/linux/arc/fpu_control.h b/libc/sysdeps/linux/arc/fpu_control.h
new file mode 100644
index 000000000..e833de3aa
--- /dev/null
+++ b/libc/sysdeps/linux/arc/fpu_control.h
@@ -0,0 +1,104 @@
+/* FPU control word bits.  ARC version.
+   Copyright (C) 2020-2025 Free Software Foundation, Inc.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library.  If not, see
+   <https://www.gnu.org/licenses/>.  */
+
+#ifndef _FPU_CONTROL_H
+#define _FPU_CONTROL_H
+
+/* ARC FPU control register bits.
+
+  [  0] -> IVE: Enable invalid operation exception.
+           if 0, soft exception: status register IV flag set.
+           if 1, hardware exception trap (not supported in Linux yet).
+  [  1] -> DZE: Enable division by zero exception.
+           if 0, soft exception: status register IV flag set.
+           if 1, hardware exception: (not supported in Linux yet).
+  [9:8] -> RM: Rounding Mode:
+           00 - Rounding toward zero.
+           01 - Rounding to nearest (default).
+           10 - Rounding (up) toward plus infinity.
+           11 - Rounding (down)toward minus infinity.
+
+   ARC FPU status register bits.
+
+   [ 0] -> IV: flag invalid operation.
+   [ 1] -> DZ: flag division by zero.
+   [ 2] -> OV: flag Overflow operation.
+   [ 3] -> UV: flag Underflow operation.
+   [ 4] -> IX: flag Inexact operation.
+   [31] -> FWE: Flag Write Enable.
+           If 1, above flags writable explicitly (clearing),
+           else IoW and only writable indirectly via bits [12:7].  */
+
+#include <features.h>
+
+#if !defined(__ARC_FPU_SP__) &&  !defined(__ARC_FPU_DP__)
+
+# define _FPU_RESERVED 0xffffffff
+# define _FPU_DEFAULT  0x00000000
+typedef unsigned int fpu_control_t;
+# define _FPU_GETCW(cw) (cw) = 0
+# define _FPU_SETCW(cw) (void) (cw)
+# define _FPU_GETS(cw) (cw) = 0
+# define _FPU_SETS(cw) (void) (cw)
+extern fpu_control_t __fpu_control;
+
+#else
+
+#define _FPU_RESERVED		0
+
+/* The fdlibm code requires strict IEEE double precision arithmetic,
+   and no interrupts for exceptions, rounding to nearest.
+   So only RM set to b'01.  */
+# define _FPU_DEFAULT		0x00000100
+
+/* Actually default needs to have FWE bit as 1 but that is already
+   ingrained into _FPU_SETS macro below.  */
+#define  _FPU_FPSR_DEFAULT	0x00000000
+
+#define __FPU_RND_SHIFT		8
+#define __FPU_RND_MASK		0x3
+
+/* Type of the control word.  */
+typedef unsigned int fpu_control_t;
+
+/* Macros for accessing the hardware control word.  */
+#  define _FPU_GETCW(cw) __asm__ volatile ("lr %0, [0x300]" : "=r" (cw))
+#  define _FPU_SETCW(cw) __asm__ volatile ("sr %0, [0x300]" : : "r" (cw))
+
+/*  Macros for accessing the hardware status word.
+    Writing to FPU_STATUS requires a "control" bit FWE to be able to set the
+    exception flags directly (as opposed to side-effects of FP instructions).
+    That is done in the macro here to keeps callers agnostic of this detail.
+    And given FWE is write-only and RAZ, no need to "clear" it in _FPU_GETS
+    macro.  */
+#  define _FPU_GETS(cw)				\
+    __asm__ volatile ("lr   %0, [0x301]	\r\n" 	\
+                      : "=r" (cw))
+
+#  define _FPU_SETS(cw)				\
+    do {					\
+      unsigned int __fwe = 0x80000000 | (cw);	\
+      __asm__ volatile ("sr  %0, [0x301] \r\n" 	\
+                        : : "r" (__fwe));	\
+    } while (0)
+
+/* Default control word set at startup.  */
+extern fpu_control_t __fpu_control;
+
+#endif
+
+#endif /* fpu_control.h */
diff --git a/libc/sysdeps/linux/csky/bits/fenv.h b/libc/sysdeps/linux/csky/bits/fenv.h
index 3359e1f8e..1428f385a 100644
--- a/libc/sysdeps/linux/csky/bits/fenv.h
+++ b/libc/sysdeps/linux/csky/bits/fenv.h
@@ -1,65 +1,108 @@
-/*
- * Copyright (C) 2017 Hangzhou C-SKY Microsystems co.,ltd.
- *
- * Licensed under the LGPL v2.1 or later, see the file COPYING.LIB
- * in this tarball.
- */
+/* Floating point environment.  C-SKY version.
+   Copyright (C) 2018-2025 Free Software Foundation, Inc.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library.  If not, see
+   <https://www.gnu.org/licenses/>.  */
 
 #ifndef _FENV_H
 # error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
 #endif
 
-/* Define bits representing the exception.  We use the bit positions of
-   the appropriate bits in the FPSR Accrued Exception Byte.  */
+#ifdef __csky_hard_float__
+/* Define bits representing the exception.  We use the bit positions
+   of the appropriate bits in the FPU control word.  */
 enum
   {
-    FE_INEXACT = 1 << 3,
-#define FE_INEXACT	FE_INEXACT
-    FE_DIVBYZERO = 1 << 4,
-#define FE_DIVBYZERO	FE_DIVBYZERO
-    FE_UNDERFLOW = 1 << 5,
-#define FE_UNDERFLOW	FE_UNDERFLOW
-    FE_OVERFLOW = 1 << 6,
-#define FE_OVERFLOW	FE_OVERFLOW
-    FE_INVALID = 1 << 7
-#define FE_INVALID	FE_INVALID
+    FE_INVALID =
+#define FE_INVALID	0x01
+      FE_INVALID,
+    FE_DIVBYZERO =
+#define FE_DIVBYZERO	0x02
+      FE_DIVBYZERO,
+    FE_OVERFLOW =
+#define FE_OVERFLOW	0x04
+      FE_OVERFLOW,
+    FE_UNDERFLOW =
+#define FE_UNDERFLOW	0x08
+      FE_UNDERFLOW,
+    FE_INEXACT =
+#define FE_INEXACT	0x10
+      FE_INEXACT,
+    __FE_DENORMAL = 0x20
   };
 
 #define FE_ALL_EXCEPT \
 	(FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
 
-/* The csky FPU supports all of the four defined rounding modes.  We use
-   the bit positions in the FPCR Mode Control Byte as the values for the
-   appropriate macros.  */
+/* The C-SKY FPU supports all of the four defined rounding modes.  We
+   use again the bit positions in the FPU control word as the values
+   for the appropriate macros.  */
+enum
+  {
+    FE_TONEAREST =
+#define FE_TONEAREST	(0x0 << 24)
+      FE_TONEAREST,
+    FE_TOWARDZERO =
+#define FE_TOWARDZERO	(0x1 << 24)
+      FE_TOWARDZERO,
+    FE_UPWARD =
+#define FE_UPWARD	(0x2 << 24)
+      FE_UPWARD,
+    FE_DOWNWARD =
+#define FE_DOWNWARD	(0x3 << 24)
+      FE_DOWNWARD,
+    __FE_ROUND_MASK = (0x3 << 24)
+  };
+
+#else
+
+/* In the soft-float case, only rounding to nearest is supported, with
+   no exceptions.  */
+
 enum
   {
-    FE_TONEAREST = 0,
-#define FE_TONEAREST	FE_TONEAREST
-    FE_TOWARDZERO = 1 << 4,
-#define FE_TOWARDZERO	FE_TOWARDZERO
-    FE_DOWNWARD = 2 << 4,
-#define FE_DOWNWARD	FE_DOWNWARD
-    FE_UPWARD = 3 << 4
-#define FE_UPWARD	FE_UPWARD
+    __FE_UNDEFINED = -1,
+
+    FE_TONEAREST =
+# define FE_TONEAREST	0x0
+      FE_TONEAREST
   };
 
+# define FE_ALL_EXCEPT 0
+
+#endif
+
 /* Type representing exception flags.  */
 typedef unsigned int fexcept_t;
 
-/* Type representing floating-point environment.  This structure
-   corresponds to the layout of the block written by `fmovem'.  */
+/* Type representing floating-point environment.  */
 typedef struct
-  {
-    unsigned int __control_register;
-    unsigned int __status_register;
-    unsigned int __instruction_address;
-  }
-fenv_t;
+{
+  unsigned int __fpcr;
+  unsigned int __fpsr;
+} fenv_t;
 
 /* If the default argument is used we use this value.  */
-#define FE_DFL_ENV	((__const fenv_t *) -1)
+#define FE_DFL_ENV	((const fenv_t *) -1)
 
-#ifdef __USE_GNU
+#if defined __USE_GNU && defined __csky_hard_float__
 /* Floating-point environment where none of the exceptions are masked.  */
-# define FE_NOMASK_ENV	((__const fenv_t *) -2)
+# define FE_NOMASK_ENV	((const fenv_t *) -2)
 #endif
+
+/* Type representing floating-point control modes.  */
+typedef unsigned int femode_t;
+
+/* Default floating-point control modes.  */
+# define FE_DFL_MODE	((const femode_t *) -1L)
diff --git a/libc/sysdeps/linux/csky/fpu_control.h b/libc/sysdeps/linux/csky/fpu_control.h
new file mode 100644
index 000000000..a2d615554
--- /dev/null
+++ b/libc/sysdeps/linux/csky/fpu_control.h
@@ -0,0 +1,147 @@
+/* FPU control word bits.  C-SKY version.
+   Copyright (C) 2018-2025 Free Software Foundation, Inc.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library.  If not, see
+   <https://www.gnu.org/licenses/>.  */
+
+#ifndef _FPU_CONTROL_H
+#define _FPU_CONTROL_H
+
+/* C-SKY FPU floating point control register bits.
+
+   31-28  -> Reserved (read as 0, write with 0).
+   27     -> 0: Flush denormalized results to zero.
+             1: Flush denormalized results to signed minimal normal number.
+   26     -> Reserved (read as 0, write with 0).
+   25-24  -> Rounding control.
+   23-6   -> Reserved (read as 0, write with 0).
+    5     -> Enable exception for input denormalized exception.
+    4     -> Enable exception for inexact exception.
+    3     -> Enable exception for underflow exception.
+    2     -> Enable exception for overflow exception.
+    1     -> Enable exception for division by zero exception.
+    0     -> Enable exception for invalid operation exception.
+
+   Rounding Control:
+   00 - Rounding to nearest (RN).
+   01 - Rounding toward zero (RZ).
+   10 - Rounding (up) toward plus infinity (RP).
+   11 - Rounding (down)toward minus infinity (RM).
+
+   C-SKY FPU floating point exception status register bits.
+
+   15     -> Accumulate bit for any exception.
+   14     -> Reserved (read as 0, write with 0).
+   13     -> Cause bit for input denormalized exception.
+   12     -> Cause bit for inexact exception.
+   11     -> Cause bit for underflow exception.
+   10     -> Cause bit for overflow exception.
+    9     -> Cause bit for division by zero exception.
+    8     -> Cause bit for invalid operation exception.
+    7     -> Flag bit for any exception.
+    6     -> Reserved (read as 0, write with 0).
+    5     -> Flag exception for input denormalized exception.
+    4     -> Flag exception for inexact exception.
+    3     -> Flag exception for underflow exception.
+    2     -> Flag exception for overflow exception.
+    1     -> Flag exception for division by zero exception.
+    0     -> Flag exception for invalid operation exception.  */
+
+#include <features.h>
+
+#ifdef __csky_soft_float__
+
+# define _FPU_RESERVED 0xffffffff
+# define _FPU_DEFAULT  0x00000000
+typedef unsigned int fpu_control_t;
+# define _FPU_GETCW(cw) (cw) = 0
+# define _FPU_SETCW(cw) (void) (cw)
+# define _FPU_GETFPSR(cw) (cw) = 0
+# define _FPU_SETFPSR(cw) (void) (cw)
+extern fpu_control_t __fpu_control;
+
+#else /* __csky_soft_float__ */
+
+/* Masking of interrupts.  */
+# define _FPU_MASK_IDE     (1 << 5)  /* Input denormalized exception.  */
+# define _FPU_MASK_IXE     (1 << 4)  /* Inexact exception.  */
+# define _FPU_MASK_UFE     (1 << 3)  /* Underflow exception.  */
+# define _FPU_MASK_OFE     (1 << 2)  /* Overflow exception.  */
+# define _FPU_MASK_DZE     (1 << 1)  /* Division by zero exception.  */
+# define _FPU_MASK_IOE     (1 << 0)  /* Invalid operation exception.  */
+
+# define _FPU_MASK_FEA     (1 << 15) /* Case for any exception.  */
+# define _FPU_MASK_FEC     (1 << 7)  /* Flag for any exception.  */
+
+/* Flush denormalized numbers to zero.  */
+# define _FPU_FLUSH_TZ   0x8000000
+
+/* Rounding control.  */
+# define _FPU_RC_NEAREST (0x0 << 24)     /* RECOMMENDED.  */
+# define _FPU_RC_ZERO    (0x1 << 24)
+# define _FPU_RC_UP      (0x2 << 24)
+# define _FPU_RC_DOWN    (0x3 << 24)
+
+# define _FPU_RESERVED      0xf460ffc0  /* Reserved bits in cw.  */
+# define _FPU_FPSR_RESERVED 0xffff4040
+
+/* The fdlibm code requires strict IEEE double precision arithmetic,
+   and no interrupts for exceptions, rounding to nearest.  */
+
+# define _FPU_DEFAULT        0x00000000
+# define _FPU_FPSR_DEFAULT   0x00000000
+
+/* IEEE: same as above, but exceptions.  */
+# define _FPU_FPCR_IEEE     0x0000001F
+# define _FPU_FPSR_IEEE     0x00000000
+
+/* Type of the control word.  */
+typedef unsigned int fpu_control_t;
+
+/* Macros for accessing the hardware control word.  */
+# if (__CSKY__ == 2)
+#  define _FPU_GETCW(cw) __asm__ volatile ("mfcr %0, cr<1, 2>" : "=a" (cw))
+#  define _FPU_SETCW(cw) __asm__ volatile ("mtcr %0, cr<1, 2>" : : "a" (cw))
+#  define _FPU_GETFPSR(cw) __asm__ volatile ("mfcr %0, cr<2, 2>" : "=a" (cw))
+#  define _FPU_SETFPSR(cw) __asm__ volatile ("mtcr %0, cr<2, 2>" : : "a" (cw))
+# else
+#  define _FPU_GETCW(cw) __asm__ volatile ("1: cprcr  %0, cpcr2 \n"          \
+                                         "   btsti  %0, 31    \n"           \
+                                         "   bt     1b        \n"           \
+                                         "   cprcr  %0, cpcr1\n" : "=b" (cw))
+
+#  define _FPU_SETCW(cw) __asm__ volatile ("1: cprcr  r7, cpcr2 \n"          \
+                                         "   btsti  r7, 31    \n"           \
+                                         "   bt     1b        \n"           \
+                                         "   cpwcr  %0, cpcr1 \n"           \
+                                         : : "b" (cw) : "r7")
+
+#  define _FPU_GETFPSR(cw) __asm__ volatile ("1: cprcr  %0, cpcr2 \n"        \
+                                           "   btsti  %0, 31    \n"         \
+                                           "   bt     1b        \n"         \
+                                           "   cprcr  %0, cpcr4\n" : "=b" (cw))
+
+#  define _FPU_SETFPSR(cw) __asm__ volatile ("1: cprcr  r7, cpcr2 \n"        \
+                                           "   btsti  r7, 31    \n"         \
+                                           "   bt     1b        \n"         \
+                                           "   cpwcr %0, cpcr4  \n"         \
+                                           : : "b" (cw) : "r7")
+# endif /* __CSKY__ != 2 */
+
+/* Default control word set at startup.  */
+extern fpu_control_t __fpu_control;
+
+#endif /* !__csky_soft_float__ */
+
+#endif /* fpu_control.h */
diff --git a/libc/sysdeps/linux/m68k/bits/fenv.h b/libc/sysdeps/linux/m68k/bits/fenv.h
index b07f0ab51..37c5fe829 100644
--- a/libc/sysdeps/linux/m68k/bits/fenv.h
+++ b/libc/sysdeps/linux/m68k/bits/fenv.h
@@ -1,5 +1,4 @@
-/* Copyright (C) 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-   This file is part of the GNU C Library.
+/* Copyright (C) 1997-2025 Free Software Foundation, Inc.
 
    The GNU C Library is free software; you can redistribute it and/or
    modify it under the terms of the GNU Lesser General Public
@@ -12,31 +11,38 @@
    Lesser General Public License for more details.
 
    You should have received a copy of the GNU Lesser General Public
-   License along with the GNU C Library; if not, see
-   <http://www.gnu.org/licenses/>.  */
+   License along with the GNU C Library.  If not, see
+   <https://www.gnu.org/licenses/>.  */
 
 #ifndef _FENV_H
 # error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
 #endif
 
 
+#if defined __HAVE_68881__ || defined __HAVE_FPU__ || defined __mcffpu__
+
 /* Define bits representing the exception.  We use the bit positions of
    the appropriate bits in the FPSR Accrued Exception Byte.  */
 enum
   {
-    FE_INEXACT = 1 << 3,
-#define FE_INEXACT	FE_INEXACT
-    FE_DIVBYZERO = 1 << 4,
-#define FE_DIVBYZERO	FE_DIVBYZERO
-    FE_UNDERFLOW = 1 << 5,
-#define FE_UNDERFLOW	FE_UNDERFLOW
-    FE_OVERFLOW = 1 << 6,
-#define FE_OVERFLOW	FE_OVERFLOW
-    FE_INVALID = 1 << 7
-#define FE_INVALID	FE_INVALID
+    FE_INEXACT =
+# define FE_INEXACT	(1 << 3)
+      FE_INEXACT,
+    FE_DIVBYZERO =
+# define FE_DIVBYZERO	(1 << 4)
+      FE_DIVBYZERO,
+    FE_UNDERFLOW =
+# define FE_UNDERFLOW	(1 << 5)
+      FE_UNDERFLOW,
+    FE_OVERFLOW =
+# define FE_OVERFLOW	(1 << 6)
+      FE_OVERFLOW,
+    FE_INVALID =
+# define FE_INVALID	(1 << 7)
+      FE_INVALID
   };
 
-#define FE_ALL_EXCEPT \
+# define FE_ALL_EXCEPT \
 	(FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
 
 /* The m68k FPU supports all of the four defined rounding modes.  We use
@@ -44,21 +50,45 @@ enum
    appropriate macros.  */
 enum
   {
-    FE_TONEAREST = 0,
-#define FE_TONEAREST	FE_TONEAREST
-    FE_TOWARDZERO = 1 << 4,
-#define FE_TOWARDZERO	FE_TOWARDZERO
-    FE_DOWNWARD = 2 << 4,
-#define FE_DOWNWARD	FE_DOWNWARD
-    FE_UPWARD = 3 << 4
-#define FE_UPWARD	FE_UPWARD
+    FE_TONEAREST =
+# define FE_TONEAREST	0
+      FE_TONEAREST,
+    FE_TOWARDZERO =
+# define FE_TOWARDZERO	(1 << 4)
+      FE_TOWARDZERO,
+    FE_DOWNWARD =
+# define FE_DOWNWARD	(2 << 4)
+      FE_DOWNWARD,
+    FE_UPWARD =
+# define FE_UPWARD	(3 << 4)
+      FE_UPWARD
   };
 
+#else
+
+/* In the soft-float case, only rounding to nearest is supported, with
+   no exceptions.  */
+
+# define FE_ALL_EXCEPT 0
+
+enum
+  {
+    __FE_UNDEFINED = -1,
+
+    FE_TONEAREST =
+# define FE_TONEAREST	0
+      FE_TONEAREST
+  };
+
+#endif
+
 
 /* Type representing exception flags.  */
 typedef unsigned int fexcept_t;
 
 
+#if defined __HAVE_68881__ || defined __HAVE_FPU__ || defined __mcffpu__
+
 /* Type representing floating-point environment.  This structure
    corresponds to the layout of the block written by `fmovem'.  */
 typedef struct
@@ -69,10 +99,30 @@ typedef struct
   }
 fenv_t;
 
+#else
+
+/* Keep ABI compatibility with the type used in the generic
+   bits/fenv.h, formerly used for no-FPU ColdFire.  */
+typedef struct
+  {
+    fexcept_t __excepts;
+  }
+fenv_t;
+
+#endif
+
 /* If the default argument is used we use this value.  */
 #define FE_DFL_ENV	((const fenv_t *) -1)
 
-#ifdef __USE_GNU
+#if defined __USE_GNU && (defined __HAVE_68881__	\
+			  || defined __HAVE_FPU__	\
+			  || defined __mcffpu__)
 /* Floating-point environment where none of the exceptions are masked.  */
 # define FE_NOMASK_ENV	((const fenv_t *) -2)
 #endif
+
+/* Type representing floating-point control modes.  */
+typedef unsigned int femode_t;
+
+/* Default floating-point control modes.  */
+# define FE_DFL_MODE	((const femode_t *) -1L)
diff --git a/libc/sysdeps/linux/m68k/bsd-_setjmp.S b/libc/sysdeps/linux/m68k/bsd-_setjmp.S
index c963cccf5..eaabce8ed 100644
--- a/libc/sysdeps/linux/m68k/bsd-_setjmp.S
+++ b/libc/sysdeps/linux/m68k/bsd-_setjmp.S
@@ -13,7 +13,9 @@ _setjmp:
 	moveal	%sp@(4), %a0
 	movel	%sp@(0), %a0@(JB_PC)
 	moveml	%d2-%d7/%a2-%a7, %a0@(JB_REGS)
-#if defined __HAVE_68881__ || defined __UCLIBC_HAS_FPU__
+#if defined(__mcffpu__) && defined(__UCLIBC_HAS_FPU__)
+	fmovemd %fp2-%fp7, %a0@(JB_FPREGS)
+#elif defined(__HAVE_68881__)
 	fmovemx %fp2-%fp7, %a0@(JB_FPREGS)
 #endif
 	clrl	%d0
diff --git a/libc/sysdeps/linux/m68k/bsd-setjmp.S b/libc/sysdeps/linux/m68k/bsd-setjmp.S
index 9daf27713..7d76d192b 100644
--- a/libc/sysdeps/linux/m68k/bsd-setjmp.S
+++ b/libc/sysdeps/linux/m68k/bsd-setjmp.S
@@ -14,7 +14,9 @@ setjmp:
 	moveal	%sp@(4), %a0
 	movel	%sp@(0), %a0@(JB_PC)
 	moveml	%d2-%d7/%a2-%a7, %a0@(JB_REGS)
-#if defined __HAVE_68881__ || defined __UCLIBC_HAS_FPU__
+#if defined(__mcffpu__) && defined(__UCLIBC_HAS_FPU__)
+	fmovemd %fp2-%fp7, %a0@(JB_FPREGS)
+#elif defined(__HAVE_68881__)
 	fmovemx %fp2-%fp7, %a0@(JB_FPREGS)
 #endif
 	clrl	%d0
diff --git a/libc/sysdeps/linux/m68k/fpu_control.h b/libc/sysdeps/linux/m68k/fpu_control.h
index 35ad95e6d..c3a9c6326 100644
--- a/libc/sysdeps/linux/m68k/fpu_control.h
+++ b/libc/sysdeps/linux/m68k/fpu_control.h
@@ -1,6 +1,5 @@
 /* 68k FPU control word definitions.
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-   This file is part of the GNU C Library.
+   Copyright (C) 1996-2025 Free Software Foundation, Inc.
 
    The GNU C Library is free software; you can redistribute it and/or
    modify it under the terms of the GNU Lesser General Public
@@ -13,8 +12,8 @@
    Lesser General Public License for more details.
 
    You should have received a copy of the GNU Lesser General Public
-   License along with the GNU C Library; if not, see
-   <http://www.gnu.org/licenses/>.  */
+   License along with the GNU C Library.  If not, see
+   <https://www.gnu.org/licenses/>.  */
 
 #ifndef _FPU_CONTROL_H
 #define _FPU_CONTROL_H
@@ -29,9 +28,9 @@
  * 12     -> enable trap for OVFL exception
  * 11     -> enable trap for UNFL exception
  * 10     -> enable trap for DZ exception
- *  9     -> enable trap for INEX2 exception
- *  8     -> enable trap for INEX1 exception
- *  7-6   -> Precision Control
+ *  9     -> enable trap for INEX2 exception (INEX on Coldfire)
+ *  8     -> enable trap for INEX1 exception (IDE on Coldfire)
+ *  7-6   -> Precision Control (only bit 6 is used on Coldfire)
  *  5-4   -> Rounding Control
  *  3-0   -> zero (read as 0, write as 0)
  *
@@ -53,50 +52,66 @@
 
 #include <features.h>
 
+#if defined (__mcoldfire__) && !defined (__mcffpu__)
+
+# define _FPU_RESERVED 0xffffffff
+# define _FPU_DEFAULT  0x00000000
+# define _FPU_GETCW(cw) ((cw) = 0)
+# define _FPU_SETCW(cw) ((void) (cw))
+
+#else
+
 /* masking of interrupts */
-#define _FPU_MASK_BSUN  0x8000
-#define _FPU_MASK_SNAN  0x4000
-#define _FPU_MASK_OPERR 0x2000
-#define _FPU_MASK_OVFL  0x1000
-#define _FPU_MASK_UNFL  0x0800
-#define _FPU_MASK_DZ    0x0400
-#define _FPU_MASK_INEX1 0x0200
-#define _FPU_MASK_INEX2 0x0100
+# define _FPU_MASK_BSUN  0x8000
+# define _FPU_MASK_SNAN  0x4000
+# define _FPU_MASK_OPERR 0x2000
+# define _FPU_MASK_OVFL  0x1000
+# define _FPU_MASK_UNFL  0x0800
+# define _FPU_MASK_DZ    0x0400
+# define _FPU_MASK_INEX1 0x0200
+# define _FPU_MASK_INEX2 0x0100
 
 /* precision control */
-#define _FPU_EXTENDED 0x00   /* RECOMMENDED */
-#define _FPU_DOUBLE   0x80
-#define _FPU_SINGLE   0x40     /* DO NOT USE */
+# ifdef __mcoldfire__
+#  define _FPU_DOUBLE   0x00
+# else
+#  define _FPU_EXTENDED 0x00   /* RECOMMENDED */
+#  define _FPU_DOUBLE   0x80
+# endif
+# define _FPU_SINGLE   0x40     /* DO NOT USE */
 
 /* rounding control */
-#define _FPU_RC_NEAREST 0x00    /* RECOMMENDED */
-#define _FPU_RC_ZERO    0x10
-#define _FPU_RC_DOWN    0x20
-#define _FPU_RC_UP      0x30
+# define _FPU_RC_NEAREST 0x00    /* RECOMMENDED */
+# define _FPU_RC_ZERO    0x10
+# define _FPU_RC_DOWN    0x20
+# define _FPU_RC_UP      0x30
 
-#define _FPU_RESERVED 0xFFFF000F  /* Reserved bits in fpucr */
+# ifdef __mcoldfire__
+#  define _FPU_RESERVED 0xFFFF800F
+# else
+#  define _FPU_RESERVED 0xFFFF000F  /* Reserved bits in fpucr */
+# endif
 
 
 /* Now two recommended fpucr */
 
 /* The fdlibm code requires no interrupts for exceptions.  Don't
    change the rounding mode, it would break long double I/O!  */
-#define _FPU_DEFAULT  0x00000000
+# define _FPU_DEFAULT  0x00000000
 
 /* IEEE:  same as above, but exceptions.  We must make it non-zero so
    that __setfpucw works.  This bit will be ignored.  */
-#define _FPU_IEEE     0x00000001
+# define _FPU_IEEE     0x00000001
+
+/* Macros for accessing the hardware control word.  */
+# define _FPU_GETCW(cw) __asm__ ("fmove%.l %!, %0" : "=dm" (cw))
+# define _FPU_SETCW(cw) __asm__ volatile ("fmove%.l %0, %!" : : "dm" (cw))
+#endif
 
 /* Type of the control word.  */
 typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
 
-/* Macros for accessing the hardware control word.  */
-#define _FPU_GETCW(cw) __asm__ ("fmove%.l %!, %0" : "=dm" (cw))
-#define _FPU_SETCW(cw) __asm__ __volatile__ ("fmove%.l %0, %!" : : "dm" (cw))
-
-#if 0
 /* Default control word set at startup.  */
 extern fpu_control_t __fpu_control;
-#endif
 
 #endif /* _M68K_FPU_CONTROL_H */
diff --git a/libc/sysdeps/linux/m68k/setjmp.S b/libc/sysdeps/linux/m68k/setjmp.S
index 5f05b8591..d10163ec6 100644
--- a/libc/sysdeps/linux/m68k/setjmp.S
+++ b/libc/sysdeps/linux/m68k/setjmp.S
@@ -14,7 +14,9 @@ __sigsetjmp:
 	moveal	%sp@(4), %a0
 	movel	%sp@(0), %a0@(JB_PC)
 	moveml	%d2-%d7/%a2-%a7, %a0@(JB_REGS)
-#if defined __HAVE_68881__ || defined __UCLIBC_HAS_FPU__
+#if defined(__mcffpu__) && defined (__UCLIBC_HAS_FPU__)
+	fmovemd %fp2-%fp7, %a0@(JB_FPREGS)
+#elif defined(__HAVE_68881__)
 	fmovemx %fp2-%fp7, %a0@(JB_FPREGS)
 #endif
 	clrl	%d0
diff --git a/libc/sysdeps/linux/mips/bits/fenv.h b/libc/sysdeps/linux/mips/bits/fenv.h
index 944101f75..25ae4d9ca 100644
--- a/libc/sysdeps/linux/mips/bits/fenv.h
+++ b/libc/sysdeps/linux/mips/bits/fenv.h
@@ -1,5 +1,4 @@
-/* Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.
-   This file is part of the GNU C Library.
+/* Copyright (C) 1998-2025 Free Software Foundation, Inc.
 
    The GNU C Library is free software; you can redistribute it and/or
    modify it under the terms of the GNU Lesser General Public
@@ -12,31 +11,38 @@
    Lesser General Public License for more details.
 
    You should have received a copy of the GNU Lesser General Public
-   License along with the GNU C Library; if not, see
-   <http://www.gnu.org/licenses/>.  */
+   License along with the GNU C Library.  If not, see
+   <https://www.gnu.org/licenses/>.  */
 
 #ifndef _FENV_H
 # error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
 #endif
 
 
+#ifdef __mips_hard_float
+
 /* Define bits representing the exception.  We use the bit positions
    of the appropriate bits in the FPU control word.  */
 enum
   {
-    FE_INEXACT = 0x04,
-#define FE_INEXACT	FE_INEXACT
-    FE_UNDERFLOW = 0x08,
-#define FE_UNDERFLOW	FE_UNDERFLOW
-    FE_OVERFLOW = 0x10,
-#define FE_OVERFLOW	FE_OVERFLOW
-    FE_DIVBYZERO = 0x20,
-#define FE_DIVBYZERO	FE_DIVBYZERO
-    FE_INVALID = 0x40,
-#define FE_INVALID	FE_INVALID
+    FE_INEXACT =
+# define FE_INEXACT	0x04
+      FE_INEXACT,
+    FE_UNDERFLOW =
+# define FE_UNDERFLOW	0x08
+      FE_UNDERFLOW,
+    FE_OVERFLOW =
+# define FE_OVERFLOW	0x10
+      FE_OVERFLOW,
+    FE_DIVBYZERO =
+# define FE_DIVBYZERO	0x20
+      FE_DIVBYZERO,
+    FE_INVALID =
+# define FE_INVALID	0x40
+      FE_INVALID,
   };
 
-#define FE_ALL_EXCEPT \
+# define FE_ALL_EXCEPT \
 	(FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
 
 /* The MIPS FPU supports all of the four defined rounding modes.  We
@@ -44,16 +50,38 @@ enum
    for the appropriate macros.  */
 enum
   {
-    FE_TONEAREST = 0x0,
-#define FE_TONEAREST	FE_TONEAREST
-    FE_TOWARDZERO = 0x1,
-#define FE_TOWARDZERO	FE_TOWARDZERO
-    FE_UPWARD = 0x2,
-#define FE_UPWARD	FE_UPWARD
-    FE_DOWNWARD = 0x3
-#define FE_DOWNWARD	FE_DOWNWARD
+    FE_TONEAREST =
+# define FE_TONEAREST	0x0
+      FE_TONEAREST,
+    FE_TOWARDZERO =
+# define FE_TOWARDZERO	0x1
+      FE_TOWARDZERO,
+    FE_UPWARD =
+# define FE_UPWARD	0x2
+      FE_UPWARD,
+    FE_DOWNWARD =
+# define FE_DOWNWARD	0x3
+      FE_DOWNWARD
   };
 
+#else
+
+/* In the soft-float case, only rounding to nearest is supported, with
+   no exceptions.  */
+
+enum
+  {
+    __FE_UNDEFINED = -1,
+
+    FE_TONEAREST =
+# define FE_TONEAREST	0x0
+      FE_TONEAREST
+  };
+
+# define FE_ALL_EXCEPT 0
+