diff options
Diffstat (limited to 'libc/sysdeps/linux')
60 files changed, 4349 insertions, 1 deletions
diff --git a/libc/sysdeps/linux/Makefile b/libc/sysdeps/linux/Makefile index a95dd67ea..9aa585eec 100644 --- a/libc/sysdeps/linux/Makefile +++ b/libc/sysdeps/linux/Makefile @@ -19,7 +19,7 @@ TOPDIR=../../../ include $(TOPDIR)Rules.mak -ALL_SUBDIRS = arm common cris h8300 i386 m68k mips powerpc sh sh64 sparc v850 +ALL_SUBDIRS = arm common cris h8300 i386 m68k mips nios nios2 powerpc sh sh64 sparc v850 all: common $(TARGET_ARCH) diff --git a/libc/sysdeps/linux/nios/Makefile b/libc/sysdeps/linux/nios/Makefile new file mode 100644 index 000000000..ea56738dc --- /dev/null +++ b/libc/sysdeps/linux/nios/Makefile @@ -0,0 +1,86 @@ +# Makefile for uClibc +# +# Copyright (C) 2000-2003 Erik Andersen <andersen@uclibc.org> +# +# This program is free software; you can redistribute it and/or modify it under +# the terms of the GNU Library General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) any +# later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +# FOR A PARTICULAR PURPOSE. See the GNU Library General Public License for more +# details. +# +# You should have received a copy of the GNU Library General Public License +# along with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +TOPDIR=../../../../ +include $(TOPDIR)Rules.mak +ASFLAGS=$(CFLAGS) + +CRT0_SRC = crt0.S +CRT0_OBJ = crt0.o crt1.o +CTOR_TARGETS= + +SSRC= __longjmp.S bsd-_setjmp.S bsd-setjmp.S setjmp.S clone.S vfork.S +SOBJS=$(patsubst %.S,%.o, $(SSRC)) + +CSRC= brk.c crtbegin.c crtend.c +COBJS=$(patsubst %.c,%.o, $(CSRC)) + +OBJS=$(SOBJS) $(MOBJ) $(COBJS) + +all: $(OBJS) $(LIBC) + +$(LIBC): ar-target + +ar-target: $(OBJS) $(CRT0_OBJ) $(CTOR_TARGETS) + $(AR) $(ARFLAGS) $(LIBC) $(OBJS) + cp $(CRT0_OBJ) $(TOPDIR)lib/ + +$(CRT0_OBJ): $(CRT0_SRC) + $(CC) $(CFLAGS) -DL_$* $< -c -o $*.o + $(STRIPTOOL) -x -R .note -R .comment $*.o + +$(SOBJS): %.o : %.S + $(CC) $(CFLAGS) -c $< -o $@ + $(STRIPTOOL) -x -R .note -R .comment $*.o + +$(COBJS): %.o : %.c + $(CC) $(CFLAGS) -c $< -o $@ + $(STRIPTOOL) -x -R .note -R .comment $*.o + +ifeq ($(strip $(UCLIBC_CTOR_DTOR)),y) +crti.o: crti.S + $(CC) $(CFLAGS) -c crti.S -o crti.o + +$(TOPDIR)lib/crti.o: crti.o + $(INSTALL) -d $(TOPDIR)lib/ + cp crti.o $(TOPDIR)lib/ + +crtn.o: crtn.S + $(CC) $(CFLAGS) -c crtn.S -o crtn.o + +$(TOPDIR)lib/crtn.o: crtn.o + $(INSTALL) -d $(TOPDIR)lib/ + cp crtn.o $(TOPDIR)lib/ +else +$(TOPDIR)lib/crti.o: + $(INSTALL) -d $(TOPDIR)lib/ + $(AR) $(ARFLAGS) $(TOPDIR)lib/crti.o +$(TOPDIR)lib/crtn.o: + $(INSTALL) -d $(TOPDIR)lib/ + $(AR) $(ARFLAGS) $(TOPDIR)lib/crtn.o +endif + + +headers: + $(LN) -fs ../libc/sysdeps/linux/nios/fpu_control.h $(TOPDIR)/include/ + +clean: + $(RM) *.[oa] *~ core + $(RM) bits/sysnum.h + $(RM) $(TOPDIR)/include/fpu_control.h + diff --git a/libc/sysdeps/linux/nios/NM_Macros.S b/libc/sysdeps/linux/nios/NM_Macros.S new file mode 100644 index 000000000..da6136593 --- /dev/null +++ b/libc/sysdeps/linux/nios/NM_Macros.S @@ -0,0 +1,473 @@ + +;------------------------------ +; Macros I: Faux Instructions +; +; The following "faux instructions" are +; implemented here as macros: +; +; MOVIP register,constant MOVI with optional PFX & MOVHI, or BGEN +; ADDIP register,constant PFX and ADDI with optional PFX +; SUBIP register,constant PFX and SUBI with optional PFX +; CMPIP register,constant PFX and CMPI with optional PFX +; +; MOVI16 register,constant PFX and MOVI +; MOVI32 register,constant PFX, MOVI, PFX, and MOVHI +; MOVIA register,constant PFX and MOVHI on Nios32, and PFX and MOVI +; +; ANDIP register,constant PFX and ANDI +; ANDNIP register,constant PFX and ANDN +; ORIP register,constant PFX and ORI +; XORIP register,constant PFX and XORI +; +; _BSR address MOVIP address to %g7, and CALL +; _BR address MOVIP address to %g7, and JMP +; +; BEQ address SKPS cc_nz and BR, has delay slot +; BNE address SKPS cc_z and BR, has delay slot +; BLE address SKPS cc_gt and BR, has delay slot +; BLT address SKPS cc_ge and BR, has delay slot +; RESTRET RESTORE and JMP %i7 +; +;------------------------------- +; Macros II: Printing +; +; These macros are guaranteed *not* +; to have branch delay slot after them. +; +; NM_PrintChar char +; NM_Print "string" +; NM_PrintLn "string" Follows it with a carriage return +; NM_PrintRegister reg For debugging, prints register name & value +; +;------------------------------- +; Macros III: Inline Debugging +; +; These macros print various information +; using large sections of expanded inline code. +; They each use either few or no registers. +; Thus, they may be safely used in interrupt handlers. +; +; NM_D_TxChar char print char to UART, affects no registers +; NM_D_TxRegister char,char,register prints the two characters, and the hex register value + +; -------------------------------------- + + + .macro _pfx_op OP,reg,val,pForce=0 + .if (\pForce) || ((\val) > (31)) || ((\val) < (0)) + PFX %hi(\val) + .endif + \OP \reg,%lo(\val) + .endm + + .macro _bgen reg,val,bit + .if ((\val)==(1<<\bit)) + BGEN \reg,\bit + .equ _bgenBit,1 + .endif + .endm + + ;------------------------ + ; MOVIP %reg,32-bit-value + .macro MOVIP reg,val + ; Methodically test every BGEN possibility... + .equ _bgenBit,0 +.if 1 + _bgen \reg,\val,0 + _bgen \reg,\val,1 + _bgen \reg,\val,2 + _bgen \reg,\val,3 + _bgen \reg,\val,4 + _bgen \reg,\val,5 + _bgen \reg,\val,6 + _bgen \reg,\val,7 + _bgen \reg,\val,8 + _bgen \reg,\val,9 + _bgen \reg,\val,10 + _bgen \reg,\val,11 + _bgen \reg,\val,12 + _bgen \reg,\val,13 + _bgen \reg,\val,14 + _bgen \reg,\val,15 + _bgen \reg,\val,16 + _bgen \reg,\val,17 + _bgen \reg,\val,18 + _bgen \reg,\val,19 + _bgen \reg,\val,20 + _bgen \reg,\val,21 + _bgen \reg,\val,22 + _bgen \reg,\val,23 + _bgen \reg,\val,24 + _bgen \reg,\val,25 + _bgen \reg,\val,26 + _bgen \reg,\val,27 + _bgen \reg,\val,28 + _bgen \reg,\val,29 + _bgen \reg,\val,30 + _bgen \reg,\val,31 + + ; If no bgen fit... +.endif + .if !_bgenBit + .if ((\val) & 0xFFE0) + PFX %hi(\val) + .endif + MOVI \reg,%lo(\val) + .if __nios32__ + .if ((\val) & 0xffff0000) + .if ((\val) & 0xFFE00000) + PFX %xhi(\val) + .endif + MOVHI \reg,%xlo(\val) + .endif + .endif + .endif + + .endm + + ; ADDIP %reg,16-bit-value + .macro ADDIP reg,val + _pfx_op ADDI,\reg,\val + .endm + + ; SUBIP %reg,16-bit-value + .macro SUBIP reg,val + _pfx_op SUBI,\reg,\val + .endm + + ; CMPIP %reg,16-bit-value + .macro CMPIP reg,val + _pfx_op CMPI,\reg,\val + .endm + + ; ANDIP %reg,16-bit-value + .macro ANDIP reg,val + PFX %hi(\val) + AND \reg,%lo(\val) + .endm + + ; ANDNIP %reg,16-bit-value + .macro ANDNIP reg,val + PFX %hi(\val) + ANDN \reg,%lo(\val) + .endm + + ; ORIP %reg,16-bit-value + .macro ORIP reg,val + PFX %hi(\val) + OR \reg,%lo(\val) + .endm + + ; XORIP %reg,16-bit-value + .macro XORIP reg,val + PFX %hi(\val) + XOR \reg,%lo(\val) + .endm + + ; BEQ addr + .macro BEQ addr + IFS cc_eq + BR \addr + .endm + + ; BNE addr + .macro BNE addr + IFS cc_ne + BR \addr + .endm + + ; BLE addr + .macro BLE addr + SKPS cc_gt + BR \addr + .endm + + ; BLT addr + .macro BLT addr + SKPS cc_ge + BR \addr + .endm + + .macro digitToChar reg + ANDIP \reg,0x000f + CMPI \reg,10 + SKPS cc_lt + ADDI \reg,'A'-'0'-10 + PFX %hi('0') + ADDI \reg,%lo('0') + .endm + +; PUSHRET == dec sp, and stash return addr + .macro PUSHRET + SUBI %sp,2 + ST [%sp],%o7 + .endm +; POPRET == pop and jump + .macro POPRET + LD %o7,[%sp] + JMP %o7 + ADDI %sp,2 ; branch delay slot + .endm + +; RESTRET = restore & return + .macro RESTRET + JMP %i7 + RESTORE + .endm + + ;-------------------- + ; MOVI16 %reg,Address + ; + .macro MOVI16 reg,val + PFX %hi(\val) + MOVI \reg,%lo(\val) + .endm + + ;-------------------- + ; MOVI32 %reg,Address + ; + .macro MOVI32 reg,val + PFX %hi(\val) + MOVI \reg,%lo(\val) + PFX %xhi(\val) + MOVHI \reg,%xlo(\val) + .endm + + ;-------------------- + ; MOVIA %reg,Address + ; + .macro MOVIA reg,val + .if __nios32__ + MOVI32 \reg,\val + .else + MOVI16 \reg,\val + .endif + .endm + + ;-------------------- + ; _BR + + .macro _BR target,viaRegister=%g7 + MOVIA \viaRegister,\target@h + JMP \viaRegister + .endm + + ;-------------------- + ; _BSR + + .macro _BSR target,viaRegister=%g7 + MOVIA \viaRegister,\target@h + CALL \viaRegister + .endm + + ;--------------------- + ; NM_Print "Your String Here" + ; + .macro NM_Print string + + BR pastStringData\@ + NOP + +stringData\@: + .asciz "\string" + .align 1 ; aligns by 2^n +pastStringData\@: + MOVIA %o0,stringData\@ + _BSR NR_TxString + NOP + .endm + + .macro NM_PrintLn string + NM_Print "\string" + _BSR NR_TxCR + NOP + .endm + + .macro NM_PrintRegister reg ; affects %g0 & %g1 & %g7, but thrashes the CWP a bit + SAVE %sp,-16 + NM_Print "\reg = " + RESTORE + MOV %g0,\reg + SAVE %sp,-16 + MOV %o0,%g0 + _BSR NR_TxHex + NOP + _BSR NR_TxCR + NOP + RESTORE + .endm + + .macro NM_PrintChar char + MOVIP %o0,\char + _BSR NR_TxChar + NOP + .endm + + .macro NM_Print2Chars char1,char2 + MOVIP %o0,(\char2<<8)+\char1 + _BSR NR_TxChar + NOP + _BSR NR_TxChar + LSRI %o0,8 + .endm + + + +; --------------------------- +; Completely inline UART sends +; Send the char, or %g7 if not there. +; Trashes %g5 and %g6 and %g7... + + .macro NM_TxChar char=0 +;NM_D_Delay 1000 + MOVIA %g6,NA_UARTBase +txCharLoop\@: + PFX 2 +.if \char + LD %g7,[%g6] + SKP1 %g7,6 +.else + LD %g5,[%g6] + SKP1 %g5,6 +.endif + BR txCharLoop\@ + NOP +.if \char + MOVIP %g7,\char +.endif + PFX 1 + ST [%g6],%g7 +;NM_D_Delay 4 + .endm + + .macro NM_TxCR + NM_TxChar 13 + NM_TxChar 10 + .endm + + .macro NM_TxHexDigit,reg,shift + MOV %g7,\reg + LSRI %g7,\shift + ANDIP %g7,0x000f + CMPI %g7,10 + SKPS cc_lt + ADDIP %g7,'A'-'0'-10 + ADDIP %g7,'0' + NM_TxChar + .endm + + .macro NM_TxHex + + .if __nios32__ + NM_TxHexDigit %g0,28 + NM_TxHexDigit %g0,24 + NM_TxHexDigit %g0,20 + NM_TxHexDigit %g0,16 + .endif + + NM_TxHexDigit %g0,12 + NM_TxHexDigit %g0,8 + NM_TxHexDigit %g0,4 + NM_TxHexDigit %g0,0 + .endm + + + + + + + + + + +; ---------------------- +; The following macros are +; rather mighty. They expand +; to large inline code for +; printing various things to +; the serial port. They are +; useful for debugging +; trap handlers, where you +; can't just go and call +; NR_TxChar and such, because, +; well, the CWP might be +; off limits! +; +; They do, however, presume +; that the stack is in good +; working order. + + +.macro NM_D_PushGRegisters + SUBIP %sp,16+69 ; oddball number so if we accidentally see it, it looks funny. + STS [%sp,16+0],%g0 + STS [%sp,16+1],%g1 + STS [%sp,16+2],%g2 + STS [%sp,16+3],%g3 + STS [%sp,16+4],%g4 + STS [%sp,16+5],%g5 + STS [%sp,16+6],%g6 + STS [%sp,16+7],%g7 + .endm + +.macro NM_D_PopGRegisters + LDS %g0,[%sp,16+0] + LDS %g1,[%sp,16+1] + LDS %g2,[%sp,16+2] + LDS %g3,[%sp,16+3] + LDS %g4,[%sp,16+4] + LDS %g5,[%sp,16+5] + LDS %g6,[%sp,16+6] + LDS %g7,[%sp,16+7] + ADDIP %sp,16+69 ; must match the push + .endm + + +.macro NM_D_TxChar c + SUBI %sp,16+8 ; 32 or 16 bit, that's enough space + STS [%sp,16+0],%g6 + STS [%sp,16+0],%g7 + NM_TxChar \c + LDS %g6,[%sp,16+0] + LDS %g7,[%sp,16+1] + ADDI %sp,16+8 + .endm + +.macro NM_D_TxChar3 c1,c2,c3 + NM_D_TxChar '<' + NM_D_TxChar \c1 + NM_D_TxChar \c2 + NM_D_TxChar \c3 + NM_D_TxChar '>' +.endm + +.macro NM_D_TxRegister r,n,reg + NM_D_PushGRegisters + NM_TxChar '(' + NM_TxChar \r + NM_TxChar \n + NM_TxChar ':' + MOV %g0,\reg + NM_TxHex + NM_TxChar ')' + NM_D_PopGRegisters +.endm + +.macro NM_D_TxReg r,n,reg + NM_D_TxRegister \r,\n,\reg +.endm + +; Do a delay loop, affects no registers. + +.macro NM_D_Delay d + SUBI %sp,16+4 + STS [%sp,16+0],%g0 + MOVIP %g0,\d +NM_D_DelayLoop\@: + IFRnz %g0 + BR NM_D_DelayLoop\@ + SUBI %g0,1 + LDS %g0,[%sp,16+0] + ADDI %sp,16+4 +.endm + diff --git a/libc/sysdeps/linux/nios/NR_Math1.S b/libc/sysdeps/linux/nios/NR_Math1.S new file mode 100644 index 000000000..5d5169ba8 --- /dev/null +++ b/libc/sysdeps/linux/nios/NR_Math1.S @@ -0,0 +1,63 @@ + + + .include "NM_Macros.S" + + .file "okmul.c" +gcc2_compiled.: + .text + .p2align 1 + .globl __mulsi3 + .type __mulsi3,@function +__mulsi3: + + ;SKP0 %o0,31 + ;NEG %o1 + ;ABS %o0 + + .MACRO ZSTEP bit + SKP0 %o0,\bit + ADD %g0,%o1 + LSLI %o1,1 + .ENDM + + MOVI %g0,0 + ZSTEP 0 + ZSTEP 1 + ZSTEP 2 + ZSTEP 3 + ZSTEP 4 + ZSTEP 5 + ZSTEP 6 + ZSTEP 7 + ZSTEP 8 + ZSTEP 9 + ZSTEP 10 + ZSTEP 11 + ZSTEP 12 + ZSTEP 13 + ZSTEP 14 + ZSTEP 15 + ZSTEP 16 + ZSTEP 17 + ZSTEP 18 + ZSTEP 19 + ZSTEP 20 + ZSTEP 21 + ZSTEP 22 + ZSTEP 23 + ZSTEP 24 + ZSTEP 25 + ZSTEP 26 + ZSTEP 27 + ZSTEP 28 + ZSTEP 29 + ZSTEP 30 + ZSTEP 31 + ; No bit 31: we already set %o0 to positive + + JMP %o7 + MOV %o0,%g0 + +.Lfe1: + .size __mulsi3,.Lfe1-__mulsi3 + diff --git a/libc/sysdeps/linux/nios/__longjmp.S b/libc/sysdeps/linux/nios/__longjmp.S new file mode 100644 index 000000000..c2b1979cc --- /dev/null +++ b/libc/sysdeps/linux/nios/__longjmp.S @@ -0,0 +1,108 @@ +/* Copyright (C) 1997, 1998 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Library General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Library General Public License for more details. + + You should have received a copy of the GNU Library General Public + License along with the GNU C Library; see the file COPYING.LIB. If not, + write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#define _ASM +#define _SETJMP_H +#include <bits/setjmp.h> + + +;---------------------------------------- +; Name: __longjmp +; Description: Restore the current context +; as saved by a previous nr_setjmp +; Input: %o0: jmp_buf (ptr to) array to restore context from +; %o1: integer to return +; Output: %o0 = 0 the first time we're called, or +; whatever longjmp returns later +; Side Effects: uses %g0, %g1 & %g2 +; CWP Depth: 0 +; + + .align 2 + .global __longjmp +__longjmp: + ; + ; The way we'll do this is by executing + ; RESTORE instructions until the old + ; return address matches. Then we'll + ; jump to where setjmp was called from. + ; + ; Since we're moving the window pointer + ; all over the place, we'll naturally + ; only use the %g registers. + ; + + mov %g0,%o0 ; %g0 -> jmp_buf + mov %g1,%o1 ; %g1 = return value + pfx jmpbuf_callersret + ld %g2,[%g0] ; %g2 = old return address +__longjmp_loop: + cmp %g2,%i7 ; Are we there yet? + skps cc_ne + br __longjmp_done + nop ; (delay slot) + + br __longjmp_loop + restore ; (delay slot) + ; + ; One might put in a watchdog counter here, to + ; prevent a runaway stack crawl... but what would that + ; accomplish? What error can we throw? To whom? + ; + +__longjmp_done: + pfx jmpbuf_l0 ; Restore local register l0 + ld %l0,[%g0] + pfx jmpbuf_l1 ; Restore local register l1 + ld %l1,[%g0] + pfx jmpbuf_l2 ; Restore local register l2 + ld %l2,[%g0] + pfx jmpbuf_l3 ; Restore local register l3 + ld %l3,[%g0] + pfx jmpbuf_l4 ; Restore local register l4 + ld %l4,[%g0] + pfx jmpbuf_l5 ; Restore local register l5 + ld %l5,[%g0] + pfx jmpbuf_l6 ; Restore local register l6 + ld %l6,[%g0] + pfx jmpbuf_l7 ; Restore local register l7 + ld %l7,[%g0] + pfx jmpbuf_i0 ; Restore input register i0 + ld %i0,[%g0] + pfx jmpbuf_i1 ; Restore input register i1 + ld %i1,[%g0] + pfx jmpbuf_i2 ; Restore input register i2 + ld %i2,[%g0] + pfx jmpbuf_i3 ; Restore input register i3 + ld %i3,[%g0] + pfx jmpbuf_i4 ; Restore input register i4 + ld %i4,[%g0] + pfx jmpbuf_i5 ; Restore input register i5 + ld %i5,[%g0] + pfx jmpbuf_jmpret + ld %o7,[%g0] ; set fake return address + jmp %o7 ; and kinda return there. + mov %o0,%g1 ; (delay slot) return value + + + + + + + + diff --git a/libc/sysdeps/linux/nios/bits/endian.h b/libc/sysdeps/linux/nios/bits/endian.h new fi |