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-rw-r--r--libc/sysdeps/linux/m68k/bits/fenv.h98
-rw-r--r--libc/sysdeps/linux/m68k/bsd-_setjmp.S4
-rw-r--r--libc/sysdeps/linux/m68k/bsd-setjmp.S4
-rw-r--r--libc/sysdeps/linux/m68k/fpu_control.h77
-rw-r--r--libc/sysdeps/linux/m68k/setjmp.S4
-rw-r--r--libc/sysdeps/linux/or1k/bits/fenv.h84
-rw-r--r--libc/sysdeps/linux/or1k/fpu_control.h88
-rw-r--r--libc/sysdeps/linux/riscv32/bits/fenv.h2
-rw-r--r--libc/sysdeps/linux/riscv64/bits/fenv.h2
-rw-r--r--libc/sysdeps/linux/sparc/bits/fenv.h60
-rw-r--r--libc/sysdeps/linux/sparc/fpu_control.h24
11 files changed, 354 insertions, 93 deletions
diff --git a/libc/sysdeps/linux/m68k/bits/fenv.h b/libc/sysdeps/linux/m68k/bits/fenv.h
index b07f0ab51..37c5fe829 100644
--- a/libc/sysdeps/linux/m68k/bits/fenv.h
+++ b/libc/sysdeps/linux/m68k/bits/fenv.h
@@ -1,5 +1,4 @@
-/* Copyright (C) 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
+/* Copyright (C) 1997-2025 Free Software Foundation, Inc.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
@@ -12,31 +11,38 @@
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
+ License along with the GNU C Library. If not, see
+ <https://www.gnu.org/licenses/>. */
#ifndef _FENV_H
# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
#endif
+#if defined __HAVE_68881__ || defined __HAVE_FPU__ || defined __mcffpu__
+
/* Define bits representing the exception. We use the bit positions of
the appropriate bits in the FPSR Accrued Exception Byte. */
enum
{
- FE_INEXACT = 1 << 3,
-#define FE_INEXACT FE_INEXACT
- FE_DIVBYZERO = 1 << 4,
-#define FE_DIVBYZERO FE_DIVBYZERO
- FE_UNDERFLOW = 1 << 5,
-#define FE_UNDERFLOW FE_UNDERFLOW
- FE_OVERFLOW = 1 << 6,
-#define FE_OVERFLOW FE_OVERFLOW
- FE_INVALID = 1 << 7
-#define FE_INVALID FE_INVALID
+ FE_INEXACT =
+# define FE_INEXACT (1 << 3)
+ FE_INEXACT,
+ FE_DIVBYZERO =
+# define FE_DIVBYZERO (1 << 4)
+ FE_DIVBYZERO,
+ FE_UNDERFLOW =
+# define FE_UNDERFLOW (1 << 5)
+ FE_UNDERFLOW,
+ FE_OVERFLOW =
+# define FE_OVERFLOW (1 << 6)
+ FE_OVERFLOW,
+ FE_INVALID =
+# define FE_INVALID (1 << 7)
+ FE_INVALID
};
-#define FE_ALL_EXCEPT \
+# define FE_ALL_EXCEPT \
(FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
/* The m68k FPU supports all of the four defined rounding modes. We use
@@ -44,21 +50,45 @@ enum
appropriate macros. */
enum
{
- FE_TONEAREST = 0,
-#define FE_TONEAREST FE_TONEAREST
- FE_TOWARDZERO = 1 << 4,
-#define FE_TOWARDZERO FE_TOWARDZERO
- FE_DOWNWARD = 2 << 4,
-#define FE_DOWNWARD FE_DOWNWARD
- FE_UPWARD = 3 << 4
-#define FE_UPWARD FE_UPWARD
+ FE_TONEAREST =
+# define FE_TONEAREST 0
+ FE_TONEAREST,
+ FE_TOWARDZERO =
+# define FE_TOWARDZERO (1 << 4)
+ FE_TOWARDZERO,
+ FE_DOWNWARD =
+# define FE_DOWNWARD (2 << 4)
+ FE_DOWNWARD,
+ FE_UPWARD =
+# define FE_UPWARD (3 << 4)
+ FE_UPWARD
};
+#else
+
+/* In the soft-float case, only rounding to nearest is supported, with
+ no exceptions. */
+
+# define FE_ALL_EXCEPT 0
+
+enum
+ {
+ __FE_UNDEFINED = -1,
+
+ FE_TONEAREST =
+# define FE_TONEAREST 0
+ FE_TONEAREST
+ };
+
+#endif
+
/* Type representing exception flags. */
typedef unsigned int fexcept_t;
+#if defined __HAVE_68881__ || defined __HAVE_FPU__ || defined __mcffpu__
+
/* Type representing floating-point environment. This structure
corresponds to the layout of the block written by `fmovem'. */
typedef struct
@@ -69,10 +99,30 @@ typedef struct
}
fenv_t;
+#else
+
+/* Keep ABI compatibility with the type used in the generic
+ bits/fenv.h, formerly used for no-FPU ColdFire. */
+typedef struct
+ {
+ fexcept_t __excepts;
+ }
+fenv_t;
+
+#endif
+
/* If the default argument is used we use this value. */
#define FE_DFL_ENV ((const fenv_t *) -1)
-#ifdef __USE_GNU
+#if defined __USE_GNU && (defined __HAVE_68881__ \
+ || defined __HAVE_FPU__ \
+ || defined __mcffpu__)
/* Floating-point environment where none of the exceptions are masked. */
# define FE_NOMASK_ENV ((const fenv_t *) -2)
#endif
+
+/* Type representing floating-point control modes. */
+typedef unsigned int femode_t;
+
+/* Default floating-point control modes. */
+# define FE_DFL_MODE ((const femode_t *) -1L)
diff --git a/libc/sysdeps/linux/m68k/bsd-_setjmp.S b/libc/sysdeps/linux/m68k/bsd-_setjmp.S
index c963cccf5..eaabce8ed 100644
--- a/libc/sysdeps/linux/m68k/bsd-_setjmp.S
+++ b/libc/sysdeps/linux/m68k/bsd-_setjmp.S
@@ -13,7 +13,9 @@ _setjmp:
moveal %sp@(4), %a0
movel %sp@(0), %a0@(JB_PC)
moveml %d2-%d7/%a2-%a7, %a0@(JB_REGS)
-#if defined __HAVE_68881__ || defined __UCLIBC_HAS_FPU__
+#if defined(__mcffpu__) && defined(__UCLIBC_HAS_FPU__)
+ fmovemd %fp2-%fp7, %a0@(JB_FPREGS)
+#elif defined(__HAVE_68881__)
fmovemx %fp2-%fp7, %a0@(JB_FPREGS)
#endif
clrl %d0
diff --git a/libc/sysdeps/linux/m68k/bsd-setjmp.S b/libc/sysdeps/linux/m68k/bsd-setjmp.S
index 9daf27713..7d76d192b 100644
--- a/libc/sysdeps/linux/m68k/bsd-setjmp.S
+++ b/libc/sysdeps/linux/m68k/bsd-setjmp.S
@@ -14,7 +14,9 @@ setjmp:
moveal %sp@(4), %a0
movel %sp@(0), %a0@(JB_PC)
moveml %d2-%d7/%a2-%a7, %a0@(JB_REGS)
-#if defined __HAVE_68881__ || defined __UCLIBC_HAS_FPU__
+#if defined(__mcffpu__) && defined(__UCLIBC_HAS_FPU__)
+ fmovemd %fp2-%fp7, %a0@(JB_FPREGS)
+#elif defined(__HAVE_68881__)
fmovemx %fp2-%fp7, %a0@(JB_FPREGS)
#endif
clrl %d0
diff --git a/libc/sysdeps/linux/m68k/fpu_control.h b/libc/sysdeps/linux/m68k/fpu_control.h
index 35ad95e6d..c3a9c6326 100644
--- a/libc/sysdeps/linux/m68k/fpu_control.h
+++ b/libc/sysdeps/linux/m68k/fpu_control.h
@@ -1,6 +1,5 @@
/* 68k FPU control word definitions.
- Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
+ Copyright (C) 1996-2025 Free Software Foundation, Inc.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
@@ -13,8 +12,8 @@
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
+ License along with the GNU C Library. If not, see
+ <https://www.gnu.org/licenses/>. */
#ifndef _FPU_CONTROL_H
#define _FPU_CONTROL_H
@@ -29,9 +28,9 @@
* 12 -> enable trap for OVFL exception
* 11 -> enable trap for UNFL exception
* 10 -> enable trap for DZ exception
- * 9 -> enable trap for INEX2 exception
- * 8 -> enable trap for INEX1 exception
- * 7-6 -> Precision Control
+ * 9 -> enable trap for INEX2 exception (INEX on Coldfire)
+ * 8 -> enable trap for INEX1 exception (IDE on Coldfire)
+ * 7-6 -> Precision Control (only bit 6 is used on Coldfire)
* 5-4 -> Rounding Control
* 3-0 -> zero (read as 0, write as 0)
*
@@ -53,50 +52,66 @@
#include <features.h>
+#if defined (__mcoldfire__) && !defined (__mcffpu__)
+
+# define _FPU_RESERVED 0xffffffff
+# define _FPU_DEFAULT 0x00000000
+# define _FPU_GETCW(cw) ((cw) = 0)
+# define _FPU_SETCW(cw) ((void) (cw))
+
+#else
+
/* masking of interrupts */
-#define _FPU_MASK_BSUN 0x8000
-#define _FPU_MASK_SNAN 0x4000
-#define _FPU_MASK_OPERR 0x2000
-#define _FPU_MASK_OVFL 0x1000
-#define _FPU_MASK_UNFL 0x0800
-#define _FPU_MASK_DZ 0x0400
-#define _FPU_MASK_INEX1 0x0200
-#define _FPU_MASK_INEX2 0x0100
+# define _FPU_MASK_BSUN 0x8000
+# define _FPU_MASK_SNAN 0x4000
+# define _FPU_MASK_OPERR 0x2000
+# define _FPU_MASK_OVFL 0x1000
+# define _FPU_MASK_UNFL 0x0800
+# define _FPU_MASK_DZ 0x0400
+# define _FPU_MASK_INEX1 0x0200
+# define _FPU_MASK_INEX2 0x0100
/* precision control */
-#define _FPU_EXTENDED 0x00 /* RECOMMENDED */
-#define _FPU_DOUBLE 0x80
-#define _FPU_SINGLE 0x40 /* DO NOT USE */
+# ifdef __mcoldfire__
+# define _FPU_DOUBLE 0x00
+# else
+# define _FPU_EXTENDED 0x00 /* RECOMMENDED */
+# define _FPU_DOUBLE 0x80
+# endif
+# define _FPU_SINGLE 0x40 /* DO NOT USE */
/* rounding control */
-#define _FPU_RC_NEAREST 0x00 /* RECOMMENDED */
-#define _FPU_RC_ZERO 0x10
-#define _FPU_RC_DOWN 0x20
-#define _FPU_RC_UP 0x30
+# define _FPU_RC_NEAREST 0x00 /* RECOMMENDED */
+# define _FPU_RC_ZERO 0x10
+# define _FPU_RC_DOWN 0x20
+# define _FPU_RC_UP 0x30
-#define _FPU_RESERVED 0xFFFF000F /* Reserved bits in fpucr */
+# ifdef __mcoldfire__
+# define _FPU_RESERVED 0xFFFF800F
+# else
+# define _FPU_RESERVED 0xFFFF000F /* Reserved bits in fpucr */
+# endif
/* Now two recommended fpucr */
/* The fdlibm code requires no interrupts for exceptions. Don't
change the rounding mode, it would break long double I/O! */
-#define _FPU_DEFAULT 0x00000000
+# define _FPU_DEFAULT 0x00000000
/* IEEE: same as above, but exceptions. We must make it non-zero so
that __setfpucw works. This bit will be ignored. */
-#define _FPU_IEEE 0x00000001
+# define _FPU_IEEE 0x00000001
+
+/* Macros for accessing the hardware control word. */
+# define _FPU_GETCW(cw) __asm__ ("fmove%.l %!, %0" : "=dm" (cw))
+# define _FPU_SETCW(cw) __asm__ volatile ("fmove%.l %0, %!" : : "dm" (cw))
+#endif
/* Type of the control word. */
typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
-/* Macros for accessing the hardware control word. */
-#define _FPU_GETCW(cw) __asm__ ("fmove%.l %!, %0" : "=dm" (cw))
-#define _FPU_SETCW(cw) __asm__ __volatile__ ("fmove%.l %0, %!" : : "dm" (cw))
-
-#if 0
/* Default control word set at startup. */
extern fpu_control_t __fpu_control;
-#endif
#endif /* _M68K_FPU_CONTROL_H */
diff --git a/libc/sysdeps/linux/m68k/setjmp.S b/libc/sysdeps/linux/m68k/setjmp.S
index 5f05b8591..d10163ec6 100644
--- a/libc/sysdeps/linux/m68k/setjmp.S
+++ b/libc/sysdeps/linux/m68k/setjmp.S
@@ -14,7 +14,9 @@ __sigsetjmp:
moveal %sp@(4), %a0
movel %sp@(0), %a0@(JB_PC)
moveml %d2-%d7/%a2-%a7, %a0@(JB_REGS)
-#if defined __HAVE_68881__ || defined __UCLIBC_HAS_FPU__
+#if defined(__mcffpu__) && defined (__UCLIBC_HAS_FPU__)
+ fmovemd %fp2-%fp7, %a0@(JB_FPREGS)
+#elif defined(__HAVE_68881__)
fmovemx %fp2-%fp7, %a0@(JB_FPREGS)
#endif
clrl %d0
diff --git a/libc/sysdeps/linux/or1k/bits/fenv.h b/libc/sysdeps/linux/or1k/bits/fenv.h
new file mode 100644
index 000000000..4701946ff
--- /dev/null
+++ b/libc/sysdeps/linux/or1k/bits/fenv.h
@@ -0,0 +1,84 @@
+/* Floating point environment, OpenRISC version.
+ Copyright (C) 2022-2025 Free Software Foundation, Inc.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public License as
+ published by the Free Software Foundation; either version 2.1 of the
+ License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _FENV_H
+# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
+#endif
+
+#ifdef __or1k_hard_float__
+/* Define bits representing exceptions in the FPCSR status word. */
+enum
+ {
+ FE_OVERFLOW =
+#define FE_OVERFLOW (1 << 3)
+ FE_OVERFLOW,
+ FE_UNDERFLOW =
+#define FE_UNDERFLOW (1 << 4)
+ FE_UNDERFLOW,
+ FE_INEXACT =
+#define FE_INEXACT (1 << 8)
+ FE_INEXACT,
+ FE_INVALID =
+#define FE_INVALID (1 << 9)
+ FE_INVALID,
+ FE_DIVBYZERO =
+#define FE_DIVBYZERO (1 << 11)
+ FE_DIVBYZERO,
+ };
+
+/* All supported exceptions. */
+#define FE_ALL_EXCEPT \
+ (FE_INVALID | FE_DIVBYZERO | FE_OVERFLOW | FE_UNDERFLOW | FE_INEXACT)
+
+/* Define bits representing rounding modes in the FPCSR Rmode field. */
+#define FE_TONEAREST (0x0 << 1)
+#define FE_TOWARDZERO (0x1 << 1)
+#define FE_UPWARD (0x2 << 1)
+#define FE_DOWNWARD (0x3 << 1)
+
+#else
+
+/* In the soft-float case only rounding to nearest is supported, with
+ no exceptions. */
+
+enum
+ {
+ __FE_UNDEFINED = -1,
+
+ FE_TONEAREST =
+# define FE_TONEAREST 0x0
+ FE_TONEAREST
+ };
+
+# define FE_ALL_EXCEPT 0
+
+#endif /* __or1k_hard_float__ */
+
+/* Type representing exception flags. */
+typedef unsigned int fexcept_t;
+
+/* Type representing floating-point environment. */
+typedef unsigned int fenv_t;
+
+/* If the default argument is used we use this value. */
+#define FE_DFL_ENV ((const fenv_t *) -1l)
+
+/* Type representing floating-point control modes. */
+typedef unsigned int femode_t;
+
+/* Default floating-point control modes. */
+# define FE_DFL_MODE ((const femode_t *) -1L)
diff --git a/libc/sysdeps/linux/or1k/fpu_control.h b/libc/sysdeps/linux/or1k/fpu_control.h
new file mode 100644
index 000000000..9abde4f42
--- /dev/null
+++ b/libc/sysdeps/linux/or1k/fpu_control.h
@@ -0,0 +1,88 @@
+/* FPU control word bits. OpenRISC version.
+ Copyright (C) 2024-2025 Free Software Foundation, Inc.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library. If not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef _FPU_CONTROL_H
+#define _FPU_CONTROL_H
+
+#ifndef __or1k_hard_float__
+
+# define _FPU_RESERVED 0xffffffff
+# define _FPU_DEFAULT 0x00000000
+# define _FPU_GETCW(cw) (cw) = 0
+# define _FPU_SETCW(cw) (void) (cw)
+
+#else /* __or1k_hard_float__ */
+
+/* Layout of FPCSR:
+
+ The bits of the FPCSR are defined as follows, this should help
+ explain how the masks below have come to be.
+
+ +-----------+----------------------------+-----+----+
+ | 32 - 12 | 11 10 9 8 7 6 5 4 3 | 2-1 | 0 |
+ +-----------+----------------------------+-----+----+
+ | Reserved | DZ IN IV IX Z QN SN UN OV | RM | EE |
+ +-----------+----------------------------+-----+----+
+
+ Exception flags:
+
+ DZ - divide by zero flag.
+ IN - infinite flag.
+ IV - invalid flag.
+ IX - inexact flag.
+ Z - zero flag.
+ QN - qnan flag.
+ SN - snan flag.
+ UN - underflow flag.
+ OV - overflow flag.
+
+ Rounding modes:
+
+ The FPCSR bits 2-1 labeled above as RM specify the rounding mode.
+
+ 00 - round to nearest
+ 01 - round to zero
+ 10 - round to positive infinity
+ 11 - round to negative infinity
+
+ Enabling exceptions:
+
+ EE - set to enable FPU exceptions.
+
+ */
+
+# define _FPU_RESERVED 0xfffff000
+/* Default: rounding to nearest with exceptions disabled. */
+# define _FPU_DEFAULT 0
+/* IEEE: Same as above with exceptions enabled. */
+# define _FPU_IEEE (_FPU_DEFAULT | 1)
+
+# define _FPU_FPCSR_RM_MASK (0x3 << 1)
+
+/* Macros for accessing the hardware control word. */
+# define _FPU_GETCW(cw) __asm__ volatile ("l.mfspr %0,r0,20" : "=r" (cw))
+# define _FPU_SETCW(cw) __asm__ volatile ("l.mtspr r0,%0,20" : : "r" (cw))
+
+#endif /* __or1k_hard_float__ */
+
+/* Type of the control word. */
+typedef unsigned int fpu_control_t;
+
+/* Default control word set at startup. */
+extern fpu_control_t __fpu_control;
+
+#endif /* fpu_control.h */
diff --git a/libc/sysdeps/linux/riscv32/bits/fenv.h b/libc/sysdeps/linux/riscv32/bits/fenv.h
index a3f8031af..a6b828a76 100644
--- a/libc/sysdeps/linux/riscv32/bits/fenv.h
+++ b/libc/sysdeps/linux/riscv32/bits/fenv.h
@@ -64,10 +64,8 @@ typedef unsigned int fenv_t;
/* If the default argument is used we use this value. */
#define FE_DFL_ENV ((__const fenv_t *) -1)
-#if __GLIBC_USE (IEC_60559_BFP_EXT)
/* Type representing floating-point control modes. */
typedef unsigned int femode_t;
/* Default floating-point control modes. */
# define FE_DFL_MODE ((const femode_t *) -1L)
-#endif
diff --git a/libc/sysdeps/linux/riscv64/bits/fenv.h b/libc/sysdeps/linux/riscv64/bits/fenv.h
index a3f8031af..a6b828a76 100644
--- a/libc/sysdeps/linux/riscv64/bits/fenv.h
+++ b/libc/sysdeps/linux/riscv64/bits/fenv.h
@@ -64,10 +64,8 @@ typedef unsigned int fenv_t;
/* If the default argument is used we use this value. */
#define FE_DFL_ENV ((__const fenv_t *) -1)
-#if __GLIBC_USE (IEC_60559_BFP_EXT)
/* Type representing floating-point control modes. */
typedef unsigned int femode_t;
/* Default floating-point control modes. */
# define FE_DFL_MODE ((const femode_t *) -1L)
-#endif
diff --git a/libc/sysdeps/linux/sparc/bits/fenv.h b/libc/sysdeps/linux/sparc/bits/fenv.h
index 79ab8cefa..83b32cc51 100644
--- a/libc/sysdeps/linux/sparc/bits/fenv.h
+++ b/libc/sysdeps/linux/sparc/bits/fenv.h
@@ -1,4 +1,4 @@
-/* Copyright (C) 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+/* Copyright (C) 1997-2025 Free Software Foundation, Inc.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
@@ -12,26 +12,34 @@
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
+ <https://www.gnu.org/licenses/>. */
#ifndef _FENV_H
# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
#endif
+#include <bits/wordsize.h>
+
+
/* Define bits representing the exception. We use the bit positions
of the appropriate accrued exception bits from the FSR. */
enum
{
- FE_INVALID = (1 << 9),
-#define FE_INVALID FE_INVALID
- FE_OVERFLOW = (1 << 8),
-#define FE_OVERFLOW FE_OVERFLOW
- FE_UNDERFLOW = (1 << 7),
-#define FE_UNDERFLOW FE_UNDERFLOW
- FE_DIVBYZERO = (1 << 6),
-#define FE_DIVBYZERO FE_DIVBYZERO
- FE_INEXACT = (1 << 5)
-#define FE_INEXACT FE_INEXACT
+ FE_INVALID =
+#define FE_INVALID (1 << 9)
+ FE_INVALID,
+ FE_OVERFLOW =
+#define FE_OVERFLOW (1 << 8)
+ FE_OVERFLOW,
+ FE_UNDERFLOW =
+#define FE_UNDERFLOW (1 << 7)
+ FE_UNDERFLOW,
+ FE_DIVBYZERO =
+#define FE_DIVBYZERO (1 << 6)
+ FE_DIVBYZERO,
+ FE_INEXACT =
+#define FE_INEXACT (1 << 5)
+ FE_INEXACT
};
#define FE_ALL_EXCEPT \
@@ -42,14 +50,18 @@ enum
for the appropriate macros. */
enum
{
- FE_TONEAREST = (0U << 30),
-#define FE_TONEAREST FE_TONEAREST
- FE_TOWARDZERO = (1U << 30),
-#define FE_TOWARDZERO FE_TOWARDZERO
- FE_UPWARD = (2U << 30),
-#define FE_UPWARD FE_UPWARD
- FE_DOWNWARD = (3U << 30)
-#define FE_DOWNWARD FE_DOWNWARD
+ FE_TONEAREST =
+#define FE_TONEAREST (0 << 30)
+ FE_TONEAREST,
+ FE_TOWARDZERO =
+#define FE_TOWARDZERO (1 << 30)
+ FE_TOWARDZERO,
+ FE_UPWARD =
+#define FE_UPWARD (-0x7fffffff - 1) /* (2 << 30) */
+ FE_UPWARD,
+ FE_DOWNWARD =
+#define FE_DOWNWARD (-0x40000000) /* (3 << 30) */
+ FE_DOWNWARD
};
#define __FE_ROUND_MASK (3U << 30)
@@ -70,6 +82,8 @@ typedef unsigned long int fenv_t;
# define FE_NOMASK_ENV ((const fenv_t *) -2)
#endif
-/* For internal use only: access the fp state register. */
-#define __fenv_stfsr(X) __asm__ ("st %%fsr,%0" : "=m" (X))
-#define __fenv_ldfsr(X) __asm__ __volatile__ ("ld %0,%%fsr" : : "m" (X))
+/* Type representing floating-point control modes. */
+typedef unsigned long int femode_t;
+
+/* Default floating-point control modes. */
+# define FE_DFL_MODE ((const femode_t *) -1L)
diff --git a/libc/sysdeps/linux/sparc/fpu_control.h b/libc/sysdeps/linux/sparc/fpu_control.h
index 57f1dbb67..542f9fb1b 100644
--- a/libc/sysdeps/linux/sparc/fpu_control.h
+++ b/libc/sysdeps/linux/sparc/fpu_control.h
@@ -1,6 +1,5 @@
/* FPU control word bits. SPARC version.
- Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
- Contributed by Miguel de Icaza
+ Copyright (C) 1997-2025 Free Software Foundation, Inc.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
@@ -14,13 +13,14 @@
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
+ <https://www.gnu.org/licenses/>. */
#ifndef _FPU_CONTROL_H
#define _FPU_CONTROL_H 1
#include <features.h>
+#include <bits/wordsize.h>
/* masking of interrupts */
#define _FPU_MASK_IM 0x08000000
@@ -41,7 +41,7 @@
#define _FPU_RC_ZERO 0x40000000
#define _FPU_RC_NEAREST 0x0 /* RECOMMENDED */
-#define _FPU_RESERVED 0x30300000 /* Reserved bits in cw */
+#define _FPU_RESERVED 0x303e0000 /* Reserved bits in cw */
/* Now two recommended cw */
@@ -56,12 +56,20 @@
/* Type of the control word. */
typedef unsigned long int fpu_control_t;
-#define _FPU_GETCW(cw) __asm__ ("st %%fsr,%0" : "=m" (*&cw))
-#define _FPU_SETCW(cw) __asm__ ("ld %0,%%fsr" : : "m" (*&cw))
+#if __WORDSIZE == 64
+# define _FPU_GETCW(cw) __asm__ __volatile__ ("stx %%fsr,%0" : "=m" (*&cw))
+# define _FPU_SETCW(cw) __asm__ __volatile__ ("ldx %0,%%fsr" : : "m" (*&cw))
+#else
+# ifdef __leon__
+ /* Prevent stfsr from being placed directly after other fp instruction. */
+# define _FPU_GETCW(cw) __asm__ __volatile__ ("nop; st %%fsr,%0" : "=m" (*&cw))
+# else
+# define _FPU_GETCW(cw) __asm__ __volatile__ ("st %%fsr,%0" : "=m" (*&cw))
+# endif
+# define _FPU_SETCW(cw) __asm__ __volatile__ ("ld %0,%%fsr" : : "m" (*&cw))
+#endif
-#if 0
/* Default control word set at startup. */
extern fpu_control_t __fpu_control;
-#endif
#endif /* fpu_control.h */
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-27 08:28:11 +0000