diff options
| author | Khem Raj <raj.khem@gmail.com> | 2010-05-05 22:50:19 -0700 |
|---|---|---|
| committer | Khem Raj <raj.khem@gmail.com> | 2010-05-09 22:53:25 -0700 |
| commit | e3dec33ba03ef7080a39444388a01e59135bb3aa (patch) | |
| tree | 9693449a78a556a91ddba349116d9c988399071a /libc/sysdeps/linux/powerpc/bits/atomic.h | |
| parent | d2ab6ee38dd6ef107bac77f485ab1bb35b177e6c (diff) | |
powerpc: Add TLS and NPTL support
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
Diffstat (limited to 'libc/sysdeps/linux/powerpc/bits/atomic.h')
| -rw-r--r-- | libc/sysdeps/linux/powerpc/bits/atomic.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/libc/sysdeps/linux/powerpc/bits/atomic.h b/libc/sysdeps/linux/powerpc/bits/atomic.h index 1088d2f3c..3dbbb3a09 100644 --- a/libc/sysdeps/linux/powerpc/bits/atomic.h +++ b/libc/sysdeps/linux/powerpc/bits/atomic.h @@ -335,12 +335,28 @@ # define __arch_atomic_decrement_if_positive_64(mem) \ ({ abort (); (*mem)--; }) +#ifdef _ARCH_PWR4 +/* + * Newer powerpc64 processors support the new "light weight" sync (lwsync) + * So if the build is using -mcpu=[power4,power5,power5+,970] we can + * safely use lwsync. + */ +# define atomic_read_barrier() __asm ("lwsync" ::: "memory") +/* + * "light weight" sync can also be used for the release barrier. + */ +# ifndef UP +# define __ARCH_REL_INSTR "lwsync" +# endif +#else + /* * Older powerpc32 processors don't support the new "light weight" * sync (lwsync). So the only safe option is to use normal sync * for all powerpc32 applications. */ # define atomic_read_barrier() __asm__ ("sync" ::: "memory") +#endif #endif @@ -387,6 +403,13 @@ typedef uintmax_t uatomic_max_t; # endif #endif +#ifndef MUTEX_HINT_ACQ +# define MUTEX_HINT_ACQ +#endif +#ifndef MUTEX_HINT_REL +# define MUTEX_HINT_REL +#endif + #define atomic_full_barrier() __asm__ ("sync" ::: "memory") #define atomic_write_barrier() __asm__ ("eieio" ::: "memory") |