diff options
Diffstat (limited to 'libc/sysdeps')
| -rw-r--r-- | libc/sysdeps/linux/or1k/bits/fenv.h | 84 | ||||
| -rw-r--r-- | libc/sysdeps/linux/or1k/fpu_control.h | 88 |
2 files changed, 172 insertions, 0 deletions
diff --git a/libc/sysdeps/linux/or1k/bits/fenv.h b/libc/sysdeps/linux/or1k/bits/fenv.h new file mode 100644 index 000000000..4701946ff --- /dev/null +++ b/libc/sysdeps/linux/or1k/bits/fenv.h @@ -0,0 +1,84 @@ +/* Floating point environment, OpenRISC version. + Copyright (C) 2022-2025 Free Software Foundation, Inc. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public License as + published by the Free Software Foundation; either version 2.1 of the + License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <https://www.gnu.org/licenses/>. */ + +#ifndef _FENV_H +# error "Never use <bits/fenv.h> directly; include <fenv.h> instead." +#endif + +#ifdef __or1k_hard_float__ +/* Define bits representing exceptions in the FPCSR status word. */ +enum + { + FE_OVERFLOW = +#define FE_OVERFLOW (1 << 3) + FE_OVERFLOW, + FE_UNDERFLOW = +#define FE_UNDERFLOW (1 << 4) + FE_UNDERFLOW, + FE_INEXACT = +#define FE_INEXACT (1 << 8) + FE_INEXACT, + FE_INVALID = +#define FE_INVALID (1 << 9) + FE_INVALID, + FE_DIVBYZERO = +#define FE_DIVBYZERO (1 << 11) + FE_DIVBYZERO, + }; + +/* All supported exceptions. */ +#define FE_ALL_EXCEPT \ + (FE_INVALID | FE_DIVBYZERO | FE_OVERFLOW | FE_UNDERFLOW | FE_INEXACT) + +/* Define bits representing rounding modes in the FPCSR Rmode field. */ +#define FE_TONEAREST (0x0 << 1) +#define FE_TOWARDZERO (0x1 << 1) +#define FE_UPWARD (0x2 << 1) +#define FE_DOWNWARD (0x3 << 1) + +#else + +/* In the soft-float case only rounding to nearest is supported, with + no exceptions. */ + +enum + { + __FE_UNDEFINED = -1, + + FE_TONEAREST = +# define FE_TONEAREST 0x0 + FE_TONEAREST + }; + +# define FE_ALL_EXCEPT 0 + +#endif /* __or1k_hard_float__ */ + +/* Type representing exception flags. */ +typedef unsigned int fexcept_t; + +/* Type representing floating-point environment. */ +typedef unsigned int fenv_t; + +/* If the default argument is used we use this value. */ +#define FE_DFL_ENV ((const fenv_t *) -1l) + +/* Type representing floating-point control modes. */ +typedef unsigned int femode_t; + +/* Default floating-point control modes. */ +# define FE_DFL_MODE ((const femode_t *) -1L) diff --git a/libc/sysdeps/linux/or1k/fpu_control.h b/libc/sysdeps/linux/or1k/fpu_control.h new file mode 100644 index 000000000..9abde4f42 --- /dev/null +++ b/libc/sysdeps/linux/or1k/fpu_control.h @@ -0,0 +1,88 @@ +/* FPU control word bits. OpenRISC version. + Copyright (C) 2024-2025 Free Software Foundation, Inc. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + <https://www.gnu.org/licenses/>. */ + +#ifndef _FPU_CONTROL_H +#define _FPU_CONTROL_H + +#ifndef __or1k_hard_float__ + +# define _FPU_RESERVED 0xffffffff +# define _FPU_DEFAULT 0x00000000 +# define _FPU_GETCW(cw) (cw) = 0 +# define _FPU_SETCW(cw) (void) (cw) + +#else /* __or1k_hard_float__ */ + +/* Layout of FPCSR: + + The bits of the FPCSR are defined as follows, this should help + explain how the masks below have come to be. + + +-----------+----------------------------+-----+----+ + | 32 - 12 | 11 10 9 8 7 6 5 4 3 | 2-1 | 0 | + +-----------+----------------------------+-----+----+ + | Reserved | DZ IN IV IX Z QN SN UN OV | RM | EE | + +-----------+----------------------------+-----+----+ + + Exception flags: + + DZ - divide by zero flag. + IN - infinite flag. + IV - invalid flag. + IX - inexact flag. + Z - zero flag. + QN - qnan flag. + SN - snan flag. + UN - underflow flag. + OV - overflow flag. + + Rounding modes: + + The FPCSR bits 2-1 labeled above as RM specify the rounding mode. + + 00 - round to nearest + 01 - round to zero + 10 - round to positive infinity + 11 - round to negative infinity + + Enabling exceptions: + + EE - set to enable FPU exceptions. + + */ + +# define _FPU_RESERVED 0xfffff000 +/* Default: rounding to nearest with exceptions disabled. */ +# define _FPU_DEFAULT 0 +/* IEEE: Same as above with exceptions enabled. */ +# define _FPU_IEEE (_FPU_DEFAULT | 1) + +# define _FPU_FPCSR_RM_MASK (0x3 << 1) + +/* Macros for accessing the hardware control word. */ +# define _FPU_GETCW(cw) __asm__ volatile ("l.mfspr %0,r0,20" : "=r" (cw)) +# define _FPU_SETCW(cw) __asm__ volatile ("l.mtspr r0,%0,20" : : "r" (cw)) + +#endif /* __or1k_hard_float__ */ + +/* Type of the control word. */ +typedef unsigned int fpu_control_t; + +/* Default control word set at startup. */ +extern fpu_control_t __fpu_control; + +#endif /* fpu_control.h */ |