diff options
| author | Austin Foxley <austinf@cetoncorp.com> | 2009-10-17 13:17:51 -0700 |
|---|---|---|
| committer | Austin Foxley <austinf@cetoncorp.com> | 2009-10-17 13:17:51 -0700 |
| commit | 6abc8f6c7c847291a9b20cb5b84e9a2dfe3b578a (patch) | |
| tree | df8daa963a35658618b48dab01c96fbb1fa13542 /libc/sysdeps/linux/mips/sys | |
| parent | 6ffcc881dc156e1c9c0bc4b153091b4760b584cb (diff) | |
mips specific bits needed for nptl
* vfork impl with support for SAVE_PID, RESTORE_PID
* sysdep.h assembly macros
Signed-off-by: Austin Foxley <austinf@cetoncorp.com>
Diffstat (limited to 'libc/sysdeps/linux/mips/sys')
| -rw-r--r-- | libc/sysdeps/linux/mips/sys/asm.h | 16 | ||||
| -rw-r--r-- | libc/sysdeps/linux/mips/sys/regdef.h | 2 |
2 files changed, 18 insertions, 0 deletions
diff --git a/libc/sysdeps/linux/mips/sys/asm.h b/libc/sysdeps/linux/mips/sys/asm.h index 79d143975..d424ed3b1 100644 --- a/libc/sysdeps/linux/mips/sys/asm.h +++ b/libc/sysdeps/linux/mips/sys/asm.h @@ -472,4 +472,20 @@ symbol = value # define MTC0 dmtc0 #endif +/* The MIPS archtectures do not have a uniform memory model. Particular + platforms may provide additional guarantees - for instance, the R4000 + LL and SC instructions implicitly perform a SYNC, and the 4K promises + strong ordering. + + However, in the absence of those guarantees, we must assume weak ordering + and SYNC explicitly where necessary. + + Some obsolete MIPS processors may not support the SYNC instruction. This + applies to "true" MIPS I processors; most of the processors which compile + using MIPS I implement parts of MIPS II. */ + +#ifndef MIPS_SYNC +# define MIPS_SYNC sync +#endif + #endif /* sys/asm.h */ diff --git a/libc/sysdeps/linux/mips/sys/regdef.h b/libc/sysdeps/linux/mips/sys/regdef.h index 9d2c4c1c4..2d94130af 100644 --- a/libc/sysdeps/linux/mips/sys/regdef.h +++ b/libc/sysdeps/linux/mips/sys/regdef.h @@ -20,6 +20,8 @@ #ifndef _SYS_REGDEF_H #define _SYS_REGDEF_H +#include <sgidefs.h> + /* * Symbolic register names for 32 bit ABI */ |