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authorVineet Gupta <vgupta@synopsys.com>2015-02-19 19:13:59 +0530
committerBernhard Reutner-Fischer <rep.dot.nop@gmail.com>2015-02-20 11:30:20 +0100
commitafab56958f1cbb47b831ee3ebff231dfbae74af2 (patch)
treec6fdf19ecb770319d72048c7c56bd71964d52948 /libc/sysdeps/linux/arc/bits
parent89b63496e88c31c2714e42656212078388718b78 (diff)
ARCv2 ISA support
This is next gen Instruction Set Architecture from Synopsys and basis for the ARC HS family of processors. http://www.synopsys.com/dw/ipdir.php?ds=arc-hs38-processor&elq_mid=5732&elq_cid=458802 http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/arc-hs/Pages/default.aspx Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
Diffstat (limited to 'libc/sysdeps/linux/arc/bits')
-rw-r--r--libc/sysdeps/linux/arc/bits/syscalls.h10
-rwxr-xr-xlibc/sysdeps/linux/arc/bits/uClibc_arch_features.h7
2 files changed, 16 insertions, 1 deletions
diff --git a/libc/sysdeps/linux/arc/bits/syscalls.h b/libc/sysdeps/linux/arc/bits/syscalls.h
index 5da6aadb3..248ef7844 100644
--- a/libc/sysdeps/linux/arc/bits/syscalls.h
+++ b/libc/sysdeps/linux/arc/bits/syscalls.h
@@ -98,7 +98,11 @@ extern int __syscall_error (int);
* for syscall itself.
*-------------------------------------------------------------------------*/
-#define ARC_TRAP_INSN "trap0 \n\t"
+#ifdef __A7__
+#define ARC_TRAP_INSN "trap0 \n\t"
+#elif defined(__HS__)
+#define ARC_TRAP_INSN "trap_s 0 \n\t"
+#endif
#define INTERNAL_SYSCALL_NCS(nm, err, nr_args, args...) \
({ \
@@ -176,7 +180,11 @@ extern int __syscall_error (int);
#else
+#ifdef __A7__
#define ARC_TRAP_INSN trap0
+#elif defined(__HS__)
+#define ARC_TRAP_INSN trap_s 0
+#endif
#endif /* __ASSEMBLER__ */
diff --git a/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h b/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h
index 8af6eca4c..451575586 100755
--- a/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h
+++ b/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h
@@ -47,4 +47,11 @@
/* The default ';' is a comment on ARC. */
#define __UCLIBC_ASM_LINE_SEP__ `
+/* does your target align 64bit values in register pairs ? (32bit arches only) */
+#if defined(__A7__)
+#undef __UCLIBC_SYSCALL_ALIGN_64BIT__
+#else
+#define __UCLIBC_SYSCALL_ALIGN_64BIT__
+#endif
+
#endif /* _BITS_UCLIBC_ARCH_FEATURES_H */