diff options
| author | Carmelo Amoroso <carmelo.amoroso@st.com> | 2010-06-14 09:39:44 +0200 |
|---|---|---|
| committer | Carmelo Amoroso <carmelo.amoroso@st.com> | 2010-06-14 09:39:44 +0200 |
| commit | 3e0b19f27bba5c47cfe4ea836ef94aad687c14b4 (patch) | |
| tree | 6beb74824f5834a7c80cc41c3315c73b0c599efb /libc/string/sh/sh4/memset.S | |
| parent | 3acd3c649d8a1cd0e662e0125547290a58773c09 (diff) | |
sh4: Fixes for SH-4 without an FPU
This patch disables SH-4 optimizations that rely on the FPU when
building for variants that don't have an FPU, such as SH-4AL.
Signed-off-by: Andrew Stubbs <ams@codesourcery.com>
Signed-off-by: Carmelo Amoroso <carmelo.amoroso@st.com>
Diffstat (limited to 'libc/string/sh/sh4/memset.S')
| -rw-r--r-- | libc/string/sh/sh4/memset.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/libc/string/sh/sh4/memset.S b/libc/string/sh/sh4/memset.S index 1a57cb969..83f874612 100644 --- a/libc/string/sh/sh4/memset.S +++ b/libc/string/sh/sh4/memset.S @@ -17,7 +17,7 @@ #include <sysdep.h> -#ifdef __LITTLE_ENDIAN__ +#if defined (__LITTLE_ENDIAN__) && defined (__SH_FPU_ANY__) #define MEMSET_USES_FPU /* Use paired single precision load or store mode for 64-bit tranfering. * FPSCR.SZ=1,FPSCR.SZ=0 is well defined on both SH4-200 and SH4-300. |