diff options
Diffstat (limited to 'toolchain/binutils')
| -rw-r--r-- | toolchain/binutils/patches/2.38/0001-Revert-RISC-V-Updated-the-default-ISA-spec-to-201912.patch | 205 |
1 files changed, 0 insertions, 205 deletions
diff --git a/toolchain/binutils/patches/2.38/0001-Revert-RISC-V-Updated-the-default-ISA-spec-to-201912.patch b/toolchain/binutils/patches/2.38/0001-Revert-RISC-V-Updated-the-default-ISA-spec-to-201912.patch deleted file mode 100644 index 9f658c517..000000000 --- a/toolchain/binutils/patches/2.38/0001-Revert-RISC-V-Updated-the-default-ISA-spec-to-201912.patch +++ /dev/null @@ -1,205 +0,0 @@ -From 665b15088fae61aabbb85ad8dcb60c3fed6c5d50 Mon Sep 17 00:00:00 2001 -From: Waldemar Brodkorb <wbx@openadk.org> -Date: Mon, 14 Feb 2022 11:03:00 +0100 -Subject: [PATCH] Revert "RISC-V: Updated the default ISA spec to 20191213." - -This reverts commit aed44286efa8ae8717a77d94b51ac3614e2ca6dc. - -Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> ---- - bfd/elfxx-riscv.c | 4 +--- - gas/config/tc-riscv.c | 2 +- - gas/testsuite/gas/riscv/csr-version-1p10.d | 2 +- - gas/testsuite/gas/riscv/csr-version-1p11.d | 2 +- - gas/testsuite/gas/riscv/csr-version-1p12.d | 2 +- - gas/testsuite/gas/riscv/csr-version-1p9p1.d | 2 +- - gas/testsuite/gas/riscv/option-arch-03.d | 2 +- - gas/testsuite/gas/riscv/option-arch-03.s | 2 +- - ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d | 2 +- - ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s | 2 +- - ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s | 2 +- - ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d | 2 +- - ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s | 2 +- - ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s | 2 +- - ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d | 2 +- - ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s | 2 +- - ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s | 2 +- - ld/testsuite/ld-riscv-elf/call-relax.d | 2 +- - 18 files changed, 18 insertions(+), 20 deletions(-) - -diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c -index 9f52bb545ac..8409c0254e5 100644 ---- a/bfd/elfxx-riscv.c -+++ b/bfd/elfxx-riscv.c -@@ -1562,9 +1562,7 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps, - rps->error_handler - (_("x ISA extension `%s' must be set with the versions"), - subset); -- /* Allow old ISA spec can recognize zicsr and zifencei. */ -- else if (strcmp (subset, "zicsr") != 0 -- && strcmp (subset, "zifencei") != 0) -+ else - rps->error_handler - (_("cannot find default versions of the ISA extension `%s'"), - subset); -diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c -index 25908597436..ebb31ec4b5e 100644 ---- a/gas/config/tc-riscv.c -+++ b/gas/config/tc-riscv.c -@@ -104,7 +104,7 @@ struct riscv_csr_extra - - /* Need to sync the version with RISC-V compiler. */ - #ifndef DEFAULT_RISCV_ISA_SPEC --#define DEFAULT_RISCV_ISA_SPEC "20191213" -+#define DEFAULT_RISCV_ISA_SPEC "2.2" - #endif - - #ifndef DEFAULT_RISCV_PRIV_SPEC -diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d -index 88da7240a78..ee56ae31f0c 100644 ---- a/gas/testsuite/gas/riscv/csr-version-1p10.d -+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d -@@ -1,4 +1,4 @@ --#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.10 -+#as: -march=rv64i -mcsr-check -mpriv-spec=1.10 - #source: csr.s - #warning_output: csr-version-1p10.l - #objdump: -dr -Mpriv-spec=1.10 -diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d -index b40c1d5d6b9..a1d8169d7f7 100644 ---- a/gas/testsuite/gas/riscv/csr-version-1p11.d -+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d -@@ -1,4 +1,4 @@ --#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.11 -+#as: -march=rv64i -mcsr-check -mpriv-spec=1.11 - #source: csr.s - #warning_output: csr-version-1p11.l - #objdump: -dr -Mpriv-spec=1.11 -diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d -index fbc30ee2fcc..c4c211829b2 100644 ---- a/gas/testsuite/gas/riscv/csr-version-1p12.d -+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d -@@ -1,4 +1,4 @@ --#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.12 -+#as: -march=rv64i -mcsr-check -mpriv-spec=1.12 - #source: csr.s - #warning_output: csr-version-1p12.l - #objdump: -dr -Mpriv-spec=1.12 -diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d -index a96e8c9dbec..01e05ae4fbc 100644 ---- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d -+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d -@@ -1,4 +1,4 @@ --#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.9.1 -+#as: -march=rv64i -mcsr-check -mpriv-spec=1.9.1 - #source: csr.s - #warning_output: csr-version-1p9p1.l - #objdump: -dr -Mpriv-spec=1.9.1 -diff --git a/gas/testsuite/gas/riscv/option-arch-03.d b/gas/testsuite/gas/riscv/option-arch-03.d -index 62d7f7d5ed2..b621d036c29 100644 ---- a/gas/testsuite/gas/riscv/option-arch-03.d -+++ b/gas/testsuite/gas/riscv/option-arch-03.d -@@ -4,5 +4,5 @@ - - Attribute Section: riscv - File Attributes -- Tag_RISCV_arch: "rv32i2p1_c2p0" -+ Tag_RISCV_arch: "rv32i2p0_c2p0" - #... -diff --git a/gas/testsuite/gas/riscv/option-arch-03.s b/gas/testsuite/gas/riscv/option-arch-03.s -index ccdb1c354b0..d982a0b0985 100644 ---- a/gas/testsuite/gas/riscv/option-arch-03.s -+++ b/gas/testsuite/gas/riscv/option-arch-03.s -@@ -1,3 +1,3 @@ - .attribute arch, "rv64ic" - .option arch, +d2p0, -c --.option arch, rv32i2p1c2p0 -+.option arch, rv32ic -diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d -index a4b0322a3d9..c148cdbc4f4 100644 ---- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d -+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d -@@ -6,4 +6,4 @@ - - Attribute Section: riscv - File Attributes -- Tag_RISCV_arch: "rv32i2p1_m2p0" -+ Tag_RISCV_arch: "rv32i2p0_m2p0" -diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s -index ea097f99b04..acc98a53cf5 100644 ---- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s -+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s -@@ -1 +1 @@ -- .attribute arch, "rv32i2p1_m2p0" -+ .attribute arch, "rv32i2p0_m2p0" -diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s -index ea097f99b04..acc98a53cf5 100644 ---- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s -+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s -@@ -1 +1 @@ -- .attribute arch, "rv32i2p1_m2p0" -+ .attribute arch, "rv32i2p0_m2p0" -diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d -index 852fd55ae08..bc0e0fd1384 100644 ---- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d -+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d -@@ -6,4 +6,4 @@ - - Attribute Section: riscv - File Attributes -- Tag_RISCV_arch: "rv32i2p1_m2p0" -+ Tag_RISCV_arch: "rv32i2p0_m2p0" -diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s -index ea097f99b04..acc98a53cf5 100644 ---- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s -+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s -@@ -1 +1 @@ -- .attribute arch, "rv32i2p1_m2p0" -+ .attribute arch, "rv32i2p0_m2p0" -diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s -index 610c7e53c1a..65d0fefd5af 100644 ---- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s -+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s -@@ -1 +1 @@ -- .attribute arch, "rv32i2p1" -+ .attribute arch, "rv32i2p0" -diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d -index c1cf8081dc7..374a043c69e 100644 ---- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d -+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d -@@ -6,4 +6,4 @@ - - Attribute Section: riscv - File Attributes -- Tag_RISCV_arch: "rv32i2p1_m2p0_xbar2p0_xfoo2p0" -+ Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0" -diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s -index 3a9fb97ac4e..b86cc558fbf 100644 ---- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s -+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s -@@ -1 +1 @@ -- .attribute arch, "rv32i2p1_m2p0_xfoo2p0" -+ .attribute arch, "rv32i2p0_m2p0_xfoo2p0" -diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s -index 878f2de8e53..376e3737b2c 100644 ---- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s -+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s -@@ -1 +1 @@ -- .attribute arch, "rv32i2p1_xbar2p0" -+ .attribute arch, "rv32i2p0_xbar2p0" -diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d -index f8f02298232..c6022bec262 100644 ---- a/ld/testsuite/ld-riscv-elf/call-relax.d -+++ b/ld/testsuite/ld-riscv-elf/call-relax.d -@@ -3,7 +3,7 @@ - #source: call-relax-1.s - #source: call-relax-2.s - #source: call-relax-3.s --#as: -march=rv32ic_zicsr -mno-arch-attr -+#as: -march=rv32ic -mno-arch-attr - #ld: -m[riscv_choose_ilp32_emul] - #objdump: -d - #pass --- -2.30.2 - |