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-rw-r--r--target/arm/cubox-i/patches/3.10.30/exportfs-boolean.patch12
-rw-r--r--target/arm/cubox-i/patches/3.10.30/linux4kix.patch584649
-rw-r--r--target/arm/cubox-i/patches/3.10.30/regmap-boolean.patch20
-rw-r--r--target/arm/cubox-i/patches/3.10.30/snd-soc.patch43
-rw-r--r--target/arm/cubox-i/patches/3.15.2/rmk.patch (renamed from target/arm/cubox-i/patches/3.15.1/rmk.patch)0
-rw-r--r--target/arm/cubox-i/patches/3.15.2/sdma-firmware-cubox-i.patch (renamed from target/arm/cubox-i/patches/3.15.1/sdma-firmware-cubox-i.patch)0
-rw-r--r--target/arm/raspberry-pi/patches/3.10.45/raspberry-pi.patch (renamed from target/arm/raspberry-pi/patches/3.10.44/raspberry-pi.patch)0
-rw-r--r--target/arm/raspberry-pi/patches/3.12.23/raspberry-pi.patch (renamed from target/arm/raspberry-pi/patches/3.12.22/raspberry-pi.patch)0
-rw-r--r--target/arm/raspberry-pi/patches/3.14.9/raspberry-pi.patch (renamed from target/arm/raspberry-pi/patches/3.14.8/raspberry-pi.patch)0
-rw-r--r--target/arm/raspberry-pi/patches/3.15.2/raspberrypi.patch (renamed from target/arm/raspberry-pi/patches/3.15.1/raspberrypi.patch)0
10 files changed, 0 insertions, 584724 deletions
diff --git a/target/arm/cubox-i/patches/3.10.30/exportfs-boolean.patch b/target/arm/cubox-i/patches/3.10.30/exportfs-boolean.patch
deleted file mode 100644
index 39b5e1adc..000000000
--- a/target/arm/cubox-i/patches/3.10.30/exportfs-boolean.patch
+++ /dev/null
@@ -1,12 +0,0 @@
-diff -Nur linux-3.10.30.orig/fs/Kconfig linux-3.10.30/fs/Kconfig
---- linux-3.10.30.orig/fs/Kconfig 2014-02-13 22:48:15.000000000 +0100
-+++ linux-3.10.30/fs/Kconfig 2014-05-19 20:41:23.637038598 +0200
-@@ -51,7 +51,7 @@
- def_bool n
-
- config EXPORTFS
-- tristate
-+ def_bool y
-
- config FILE_LOCKING
- bool "Enable POSIX file locking API" if EXPERT
diff --git a/target/arm/cubox-i/patches/3.10.30/linux4kix.patch b/target/arm/cubox-i/patches/3.10.30/linux4kix.patch
deleted file mode 100644
index 0ad6e75f6..000000000
--- a/target/arm/cubox-i/patches/3.10.30/linux4kix.patch
+++ /dev/null
@@ -1,584649 +0,0 @@
-diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/clcd-panels.dtsi linux-3.10.30/arch/arm/boot/dts/clcd-panels.dtsi
---- linux-3.10.30.orig/arch/arm/boot/dts/clcd-panels.dtsi 1970-01-01 01:00:00.000000000 +0100
-+++ linux-3.10.30/arch/arm/boot/dts/clcd-panels.dtsi 2014-05-19 19:07:23.425304296 +0200
-@@ -0,0 +1,52 @@
-+/*
-+ * ARM Ltd. Versatile Express
-+ *
-+ */
-+
-+/ {
-+ panels {
-+ panel@0 {
-+ compatible = "panel";
-+ mode = "VGA";
-+ refresh = <60>;
-+ xres = <640>;
-+ yres = <480>;
-+ pixclock = <39721>;
-+ left_margin = <40>;
-+ right_margin = <24>;
-+ upper_margin = <32>;
-+ lower_margin = <11>;
-+ hsync_len = <96>;
-+ vsync_len = <2>;
-+ sync = <0>;
-+ vmode = "FB_VMODE_NONINTERLACED";
-+
-+ tim2 = "TIM2_BCD", "TIM2_IPC";
-+ cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
-+ caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
-+ bpp = <16>;
-+ };
-+
-+ panel@1 {
-+ compatible = "panel";
-+ mode = "XVGA";
-+ refresh = <60>;
-+ xres = <1024>;
-+ yres = <768>;
-+ pixclock = <15748>;
-+ left_margin = <152>;
-+ right_margin = <48>;
-+ upper_margin = <23>;
-+ lower_margin = <3>;
-+ hsync_len = <104>;
-+ vsync_len = <4>;
-+ sync = <0>;
-+ vmode = "FB_VMODE_NONINTERLACED";
-+
-+ tim2 = "TIM2_BCD", "TIM2_IPC";
-+ cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
-+ caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
-+ bpp = <16>;
-+ };
-+ };
-+};
-diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/exynos5440.dtsi linux-3.10.30/arch/arm/boot/dts/exynos5440.dtsi
---- linux-3.10.30.orig/arch/arm/boot/dts/exynos5440.dtsi 2014-02-13 22:48:15.000000000 +0100
-+++ linux-3.10.30/arch/arm/boot/dts/exynos5440.dtsi 2014-05-19 19:07:23.429304311 +0200
-@@ -113,7 +113,7 @@
- clock-names = "spi", "spi_busclk0";
- };
-
-- pinctrl {
-+ pin_ctrl: pinctrl {
- compatible = "samsung,exynos5440-pinctrl";
- reg = <0xE0000 0x1000>;
- interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
-@@ -216,4 +216,44 @@
- clock-names = "rtc";
- status = "disabled";
- };
-+
-+ pcie@290000 {
-+ compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-+ reg = <0x290000 0x1000
-+ 0x270000 0x1000
-+ 0x271000 0x40>;
-+ interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
-+ clocks = <&clock 28>, <&clock 27>;
-+ clock-names = "pcie", "pcie_bus";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
-+ 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
-+ 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0x0 0 &gic 53>;
-+ num-lanes = <4>;
-+ };
-+
-+ pcie@2a0000 {
-+ compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-+ reg = <0x2a0000 0x1000
-+ 0x272000 0x1000
-+ 0x271040 0x40>;
-+ interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
-+ clocks = <&clock 29>, <&clock 27>;
-+ clock-names = "pcie", "pcie_bus";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ device_type = "pci";
-+ ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
-+ 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
-+ 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 0>;
-+ interrupt-map = <0x0 0 &gic 56>;
-+ num-lanes = <4>;
-+ };
- };
-diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/exynos5440-ssdk5440.dts linux-3.10.30/arch/arm/boot/dts/exynos5440-ssdk5440.dts
---- linux-3.10.30.orig/arch/arm/boot/dts/exynos5440-ssdk5440.dts 2014-02-13 22:48:15.000000000 +0100
-+++ linux-3.10.30/arch/arm/boot/dts/exynos5440-ssdk5440.dts 2014-05-19 19:07:23.429304311 +0200
-@@ -30,4 +30,12 @@
- clock-frequency = <50000000>;
- };
- };
-+
-+ pcie@290000 {
-+ reset-gpio = <&pin_ctrl 5 0>;
-+ };
-+
-+ pcie@2a0000 {
-+ reset-gpio = <&pin_ctrl 22 0>;
-+ };
- };
-diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx23.dtsi linux-3.10.30/arch/arm/boot/dts/imx23.dtsi
---- linux-3.10.30.orig/arch/arm/boot/dts/imx23.dtsi 2014-02-13 22:48:15.000000000 +0100
-+++ linux-3.10.30/arch/arm/boot/dts/imx23.dtsi 2014-05-19 19:07:23.429304311 +0200
-@@ -20,6 +20,7 @@
- gpio2 = &gpio2;
- serial0 = &auart0;
- serial1 = &auart1;
-+ usbphy0 = &usbphy0;
- };
-
- cpus {
-@@ -360,7 +361,8 @@
- compatible = "fsl,imx23-lcdif";
- reg = <0x80030000 2000>;
- interrupts = <46 45>;
-- clocks = <&clks 38>;
-+ clocks = <&clks 38>, <&clks 38>;
-+ clock-names = "pix", "axi";
- status = "disabled";
- };
-
-diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx28.dtsi linux-3.10.30/arch/arm/boot/dts/imx28.dtsi
---- linux-3.10.30.orig/arch/arm/boot/dts/imx28.dtsi 2014-02-13 22:48:15.000000000 +0100
-+++ linux-3.10.30/arch/arm/boot/dts/imx28.dtsi 2014-05-19 19:07:23.429304311 +0200
-@@ -29,6 +29,8 @@
- serial4 = &auart4;
- ethernet0 = &mac0;
- ethernet1 = &mac1;
-+ usbphy0 = &usbphy0;
-+ usbphy1 = &usbphy1;
- };
-
- cpus {
-@@ -727,7 +729,8 @@
- compatible = "fsl,imx28-lcdif";
- reg = <0x80030000 0x2000>;
- interrupts = <38 86>;
-- clocks = <&clks 55>;
-+ clocks = <&clks 55>, <&clks 55>;
-+ clock-names = "pix", "axi";
- dmas = <&dma_apbh 13>;
- dma-names = "rx";
- status = "disabled";
-diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx53.dtsi linux-3.10.30/arch/arm/boot/dts/imx53.dtsi
---- linux-3.10.30.orig/arch/arm/boot/dts/imx53.dtsi 2014-02-13 22:48:15.000000000 +0100
-+++ linux-3.10.30/arch/arm/boot/dts/imx53.dtsi 2014-05-19 19:07:23.429304311 +0200
-@@ -782,5 +782,10 @@
- status = "disabled";
- };
- };
-+
-+ ocram: sram@f8000000 {
-+ compatible = "mmio-sram";
-+ reg = <0xf8000000 0x20000>;
-+ };
- };
- };
-diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-cubox-i.dts linux-3.10.30/arch/arm/boot/dts/imx6dl-cubox-i.dts
---- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-cubox-i.dts 1970-01-01 01:00:00.000000000 +0100
-+++ linux-3.10.30/arch/arm/boot/dts/imx6dl-cubox-i.dts 2014-05-19 19:07:23.429304311 +0200
-@@ -0,0 +1,12 @@
-+/*
-+ * Copyright (C) 2014 Russell King
-+ */
-+/dts-v1/;
-+
-+#include "imx6dl.dtsi"
-+#include "imx6qdl-cubox-i.dtsi"
-+
-+/ {
-+ model = "SolidRun Cubox-i Solo/DualLite";
-+ compatible = "solidrun,cubox-i/dl", "fsl,imx6dl";
-+};
-diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl.dtsi linux-3.10.30/arch/arm/boot/dts/imx6dl.dtsi
---- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl.dtsi 2014-02-13 22:48:15.000000000 +0100
-+++ linux-3.10.30/arch/arm/boot/dts/imx6dl.dtsi 2014-05-19 19:07:23.429304311 +0200
-@@ -8,19 +8,39 @@
- *
- */
-
--#include "imx6qdl.dtsi"
- #include "imx6dl-pinfunc.h"
-+#include "imx6qdl.dtsi"
-
- / {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
-- cpu@0 {
-+ cpu0: cpu@0 {
- compatible = "arm,cortex-a9";
- device_type = "cpu";
- reg = <0>;
- next-level-cache = <&L2>;
-+ operating-points = <
-+ /* kHz uV */
-+ 996000 1275000
-+ 792000 1175000
-+ 396000 1075000
-+ >;
-+ fsl,soc-operating-points = <
-+ /* ARM kHz SOC-PU uV */
-+ 996000 1175000
-+ 792000 1175000
-+ 396000 1175000
-+ >;
-+ clock-latency = <61036>; /* two CLK32 periods */
-+ clocks = <&clks 104>, <&clks 6>, <&clks 16>,
-+ <&clks 17>, <&clks 170>;
-+ clock-names = "arm", "pll2_pfd2_396m", "step",
-+ "pll1_sw", "pll1_sys";
-+ arm-supply = <&reg_arm>;
-+ pu-supply = <&reg_pu>;
-+ soc-supply = <&reg_soc>;
- };
-
- cpu@1 {
-@@ -28,140 +48,125 @@
- device_type = "cpu";
- reg = <1>;
- next-level-cache = <&L2>;
-+ operating-points = <
-+ /* kHz uV */
-+ 996000 1250000
-+ 792000 1175000
-+ 396000 1075000
-+ >;
-+ fsl,soc-operating-points = <
-+ /* ARM kHz SOC-PU uV */
-+ 996000 1175000
-+ 792000 1175000
-+ 396000 1175000
-+ >;
-+ clock-latency = <61036>; /* two CLK32 periods */
-+ clocks = <&clks 104>, <&clks 6>, <&clks 16>,
-+ <&clks 17>, <&clks 170>;
-+ clock-names = "arm", "pll2_pfd2_396m", "step",
-+ "pll1_sw", "pll1_sys";
-+ arm-supply = <&reg_arm>;
-+ pu-supply = <&reg_pu>;
-+ soc-supply = <&reg_soc>;
- };
- };
-
- soc {
-- aips1: aips-bus@02000000 {
-- iomuxc: iomuxc@020e0000 {
-- compatible = "fsl,imx6dl-iomuxc";
-- reg = <0x020e0000 0x4000>;
-
-- enet {
-- pinctrl_enet_1: enetgrp-1 {
-- fsl,pins = <
-- MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
-- MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
-- MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
-- MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
-- MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
-- MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
-- MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
-- MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
-- MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
-- MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
-- MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
-- MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
-- MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
-- MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
-- MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
-- MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
-- >;
-- };
--
-- pinctrl_enet_2: enetgrp-2 {
-- fsl,pins = <
-- MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
-- MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
-- MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
-- MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
-- MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
-- MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
-- MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
-- MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
-- MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
-- MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
-- MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
-- MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
-- MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
-- MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
-- MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
-- >;
-- };
-- };
--
-- uart1 {
-- pinctrl_uart1_1: uart1grp-1 {
-- fsl,pins = <
-- MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
-- MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
-- >;
-- };
-- };
--
-- uart4 {
-- pinctrl_uart4_1: uart4grp-1 {
-- fsl,pins = <
-- MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
-- MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
-- >;
-- };
-- };
--
-- usbotg {
-- pinctrl_usbotg_2: usbotggrp-2 {
-- fsl,pins = <
-- MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
-- >;
-- };
-- };
--
-- usdhc2 {
-- pinctrl_usdhc2_1: usdhc2grp-1 {
-- fsl,pins = <
-- MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
-- MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
-- MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
-- MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
-- MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
-- MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
-- MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
-- MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
-- MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
-- MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
-- >;
-- };
-- };
--
-- usdhc3 {
-- pinctrl_usdhc3_1: usdhc3grp-1 {
-- fsl,pins = <
-- MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
-- MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
-- MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
-- MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
-- MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
-- MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
-- MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
-- MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
-- MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
-- MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
-- >;
-- };
--
-- pinctrl_usdhc3_2: usdhc3grp_2 {
-- fsl,pins = <
-- MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
-- MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
-- MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
-- MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
-- MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
-- MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
-- >;
-- };
-- };
-+ busfreq { /* BUSFREQ */
-+ compatible = "fsl,imx6_busfreq";
-+ clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
-+ <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 22> , <&clks 8>;
-+ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
-+ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_sel", "pll3_pfd1_540m";
-+ interrupts = <0 107 0x04>, <0 112 0x4>;
-+ interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
-+ fsl,max_ddr_freq = <400000000>;
-+ };
-+
-+ gpu: gpu@00130000 {
-+ compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
-+ reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
-+ <0x0 0x0>;
-+ reg-names = "iobase_3d", "iobase_2d",
-+ "phys_baseaddr";
-+ interrupts = <0 9 0x04>, <0 10 0x04>;
-+ interrupt-names = "irq_3d", "irq_2d";
-+ clocks = <&clks 143>, <&clks 27>,
-+ <&clks 121>, <&clks 122>,
-+ <&clks 0>;
-+ clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
-+ "gpu2d_clk", "gpu3d_clk",
-+ "gpu3d_shader_clk";
-+ resets = <&src 0>, <&src 3>;
-+ reset-names = "gpu3d", "gpu2d";
-+ pu-supply = <&reg_pu>;
-+ };
-+
-+ ocram: sram@00900000 {
-+ compatible = "mmio-sram";
-+ reg = <0x00900000 0x20000>;
-+ clocks = <&clks 142>;
-+ };
-
-+ hdmi_core: hdmi_core@00120000 {
-+ compatible = "fsl,imx6dl-hdmi-core";
-+ reg = <0x00120000 0x9000>;
-+ clocks = <&clks 124>, <&clks 123>;
-+ clock-names = "hdmi_isfr", "hdmi_iahb";
-+ status = "disabled";
-+ };
-+
-+ hdmi_video: hdmi_video@020e0000 {
-+ compatible = "fsl,imx6dl-hdmi-video";
-+ reg = <0x020e0000 0x1000>;
-+ reg-names = "hdmi_gpr";
-+ interrupts = <0 115 0x04>;
-+ clocks = <&clks 124>, <&clks 123>;
-+ clock-names = "hdmi_isfr", "hdmi_iahb";
-+ status = "disabled";
-+ };
-+
-+ hdmi_audio: hdmi_audio@00120000 {
-+ compatible = "fsl,imx6dl-hdmi-audio";
-+ clocks = <&clks 124>, <&clks 123>;
-+ clock-names = "hdmi_isfr", "hdmi_iahb";
-+ dmas = <&sdma 2 22 0>;
-+ dma-names = "tx";
-+ status = "disabled";
-+ };
-+
-+ hdmi_cec: hdmi_cec@00120000 {
-+ compatible = "fsl,imx6dl-hdmi-cec";
-+ interrupts = <0 115 0x04>;
-+ status = "disabled";
-+ };
-+
-+ aips1: aips-bus@02000000 {
-+ vpu@02040000 {
-+ iramsize = <0>;
-+ status = "okay";
-+ };
-
-+ iomuxc: iomuxc@020e0000 {
-+ compatible = "fsl,imx6dl-iomuxc";
- };
-
- pxp: pxp@020f0000 {
-+ compatible = "fsl,imx6dl-pxp-dma";
- reg = <0x020f0000 0x4000>;
- interrupts = <0 98 0x04>;
-+ clocks = <&clks 133>;
-+ clock-names = "pxp-axi";
-+ status = "disabled";
- };
-
- epdc: epdc@020f4000 {
-+ compatible = "fsl,imx6dl-epdc";
- reg = <0x020f4000 0x4000>;
- interrupts = <0 97 0x04>;
-+ clocks = <&clks 133>, <&clks 137>;
-+ clock-names = "epdc_axi", "epdc_pix";
- };
-
- lcdif: lcdif@020f8000 {
-@@ -171,6 +176,16 @@
- };
-
- aips2: aips-bus@02100000 {
-+ mipi_dsi: mipi@021e0000 {
-+ compatible = "fsl,imx6dl-mipi-dsi";
-+ reg = <0x021e0000 0x4000>;
-+ interrupts = <0 102 0x04>;
-+ gpr = <&gpr>;
-+ clocks = <&clks 138>, <&clks 204>;
-+ clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
-+ status = "disabled";
-+ };
-+
- i2c4: i2c@021f8000 {
- #address-cells = <1>;
- #size-cells = <0>;
-@@ -182,3 +197,54 @@
- };
- };
- };
-+
-+&ldb {
-+ clocks = <&clks 33>, <&clks 34>,
-+ <&clks 39>, <&clks 40>,
-+ <&clks 135>, <&clks 136>;
-+ clock-names = "di0_pll", "di1_pll",
-+ "di0_sel", "di1_sel",
-+ "di0", "di1";
-+
-+ lvds-channel@0 {
-+ crtcs = <&ipu1 0>, <&ipu1 1>;
-+ };
-+
-+ lvds-channel@1 {
-+ crtcs = <&ipu1 0>, <&ipu1 1>;
-+ };
-+};
-+
-+&iomuxc {
-+ epdc {
-+ pinctrl_epdc_0: epdcgrp-0 {
-+ fsl,pins = <
-+ MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x80000000
-+ MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x80000000
-+ MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x80000000
-+ MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x80000000
-+ MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x80000000
-+ MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x80000000
-+ MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x80000000
-+ MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x80000000
-+ MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x80000000
-+ MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x80000000
-+ MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x80000000
-+ MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x80000000
-+ MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000
-+ MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x80000000
-+ MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x80000000
-+ MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000
-+ MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x80000000
-+ MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000
-+ MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000
-+ MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000
-+ >;
-+ };
-+ };
-+};
-+
-+&hdmi {
-+ compatible = "fsl,imx6dl-hdmi";
-+ crtcs = <&ipu1 0>, <&ipu1 1>;
-+};
-diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-hummingboard.dts linux-3.10.30/arch/arm/boot/dts/imx6dl-hummingboard.dts
---- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-hummingboard.dts 1970-01-01 01:00:00.000000000 +0100
-+++ linux-3.10.30/arch/arm/boot/dts/imx6dl-hummingboard.dts 2014-05-19 19:07:23.429304311 +0200
-@@ -0,0 +1,258 @@
-+/*
-+ * Copyright (C) 2013 Russell King
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License version 2.
-+ */
-+/dts-v1/;
-+
-+#include "imx6dl.dtsi"
-+#include "imx6qdl-microsom.dtsi"
-+#include "imx6qdl-microsom-ar8035.dtsi"
-+
-+/ {
-+ model = "SolidRun HummingBoard DL/Solo";
-+ compatible = "solidrun,hummingboard", "fsl,imx6dl";
-+
-+ aliases {
-+ mxcfb0 = &mxcfb1;
-+ };
-+
-+ ir_recv: ir-receiver {
-+ compatible = "gpio-ir-receiver";
-+ gpios = <&gpio1 2 1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
-+ };
-+
-+ regulators {
-+ compatible = "simple-bus";
-+
-+ reg_3p3v: 3p3v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "3P3V";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-always-on;
-+ };
-+
-+ reg_usbh1_vbus: usb-h1-vbus {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio1 0 0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
-+ regulator-name = "usb_h1_vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ reg_usbotg_vbus: usb-otg-vbus {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio3 22 0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
-+ regulator-name = "usb_otg_vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+ };
-+
-+ codec: spdif-transmitter {
-+ compatible = "linux,spdif-dit";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hummingboard_spdif>;
-+ };
-+
-+ imx-drm {
-+ compatible = "fsl,imx-drm";
-+ crtcs = <&ipu1 0>, <&ipu1 1>;
-+ connectors = <&hdmi>;
-+ };
-+
-+ sound-spdif {
-+ compatible = "fsl,imx-audio-spdif";
-+ model = "imx-spdif";
-+ /* IMX6 doesn't implement this yet */
-+ spdif-controller = <&spdif>;
-+ spdif-out;
-+ };
-+
-+ sound-hdmi {
-+ compatible = "fsl,imx6q-audio-hdmi",
-+ "fsl,imx-audio-hdmi";
-+ model = "imx-audio-hdmi";
-+ hdmi-controller = <&hdmi_audio>;
-+ };
-+
-+ mxcfb1: mxc_sdc_fb@0 {
-+ compatible = "fsl,mxc_sdc_fb";
-+ disp_dev = "hdmi";
-+ interface_pix_fmt = "RGB24";
-+ mode_str ="1280x720@60";
-+ default_bpp = <32>;
-+ int_clk = <0>;
-+ late_init = <0>;
-+ status = "okay";
-+ };
-+
-+ v4l2_cap_0 {
-+ compatible = "fsl,imx6q-v4l2-capture";
-+ ipu_id = <0>;
-+ csi_id = <0>;
-+ mclk_source = <0>;
-+ status = "okay";
-+ };
-+
-+ v4l2_cap_1 {
-+ compatible = "fsl,imx6q-v4l2-capture";
-+ ipu_id = <0>;
-+ csi_id = <1>;
-+ mclk_source = <0>;
-+ status = "okay";
-+ };
-+
-+ v4l2_out {
-+ compatible = "fsl,mxc_v4l2_output";
-+ status = "okay";
-+ };
-+};
-+
-+&flexcan1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
-+ status = "okay";
-+};
-+
-+&hdmi {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
-+ ddc = <&i2c2>;
-+ status = "okay";
-+ crtcs = <&ipu1 0>;
-+};
-+
-+&hdmi_audio {
-+ status = "okay";
-+};
-+
-+&hdmi_cec {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
-+ status = "okay";
-+};
-+
-+&hdmi_core {
-+ ipu_id = <1>;
-+ disp_id = <0>;
-+ status = "okay";
-+};
-+
-+&hdmi_video {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hdmi_hdcp_1>;
-+ fsl,phy_reg_vlev = <0x0294>;
-+ fsl,phy_reg_cksymtx = <0x800d>;
-+ fsl,hdcp;
-+ status = "okay";
-+};
-+
-+&i2c1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c1_1>;
-+
-+ /*
-+ * Not fitted on Carrier-1 board... yet
-+ status = "okay";
-+
-+ rtc: pcf8523@68 {
-+ compatible = "nxp,pcf8523";
-+ reg = <0x68>;
-+ };
-+ */
-+};
-+
-+&i2c2 {
-+ clock-frequency = <100000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c2_2>;
-+ status = "okay";
-+};
-+
-+&iomuxc {
-+ hummingboard {
-+ pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
-+ MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
-+ >;
-+ };
-+
-+ pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
-+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
-+ >;
-+ };
-+
-+ pinctrl_hummingboard_hdmi: hummingboard-hdmi {
-+ fsl,pins = <
-+ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
-+ >;
-+ };
-+
-+ pinctrl_hummingboard_spdif: hummingboard-spdif {
-+ fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
-+ };
-+
-+ pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
-+ fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
-+ };
-+
-+ pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
-+ fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
-+ };
-+
-+ pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
-+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
-+ >;
-+ };
-+
-+ pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
-+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
-+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
-+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
-+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
-+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
-+ >;
-+ };
-+ };
-+};
-+
-+&spdif {
-+ status = "okay";
-+};
-+
-+&usbh1 {
-+ vbus-supply = <&reg_usbh1_vbus>;
-+ status = "okay";
-+};
-+
-+&usbotg {
-+ vbus-supply = <&reg_usbotg_vbus>;
-+ status = "okay";
-+};
-+
-+&usdhc2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <
-+ &pinctrl_hummingboard_usdhc2_aux
-+ &pinctrl_hummingboard_usdhc2
-+ >;
-+ vmmc-supply = <&reg_3p3v>;
-+ cd-gpios = <&gpio1 4 0>;
-+ status = "okay";
-+};
-diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-pinfunc.h linux-3.10.30/arch/arm/boot/dts/imx6dl-pinfunc.h
---- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-pinfunc.h 2014-02-13 22:48:15.000000000 +0100
-+++ linux-3.10.30/arch/arm/boot/dts/imx6dl-pinfunc.h 2014-05-19 19:07:23.433304326 +0200
-@@ -14,1072 +14,1076 @@
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
--#define MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
--#define MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
--#define MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
--#define MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1
--#define MX6DL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0
--#define MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0
--#define MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1
--#define MX6DL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0
--#define MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0
--#define MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1
--#define MX6DL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0
--#define MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0
--#define MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1
--#define MX6DL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0
--#define MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0
--#define MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1
--#define MX6DL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0
--#define MX6DL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0
--#define MX6DL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0
--#define MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0
--#define MX6DL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0
--#define MX6DL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0
--#define MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0
--#define MX6DL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0
--#define MX6DL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0
--#define MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0
--#define MX6DL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0
--#define MX6DL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0
--#define MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0
--#define MX6DL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0
--#define MX6DL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0
--#define MX6DL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0
--#define MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0
--#define MX6DL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0
--#define MX6DL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x3