diff options
| -rw-r--r-- | target/Config.in | 6 | ||||
| -rw-r--r-- | target/lemote/device.mk | 4 | ||||
| -rw-r--r-- | target/lemote/kernel.config | 2369 | ||||
| -rw-r--r-- | target/lemote/patches/yeelong.patch | 25204 | ||||
| -rw-r--r-- | toolchain/gcc/Makefile | 1 |
5 files changed, 27324 insertions, 260 deletions
diff --git a/target/Config.in b/target/Config.in index b005bae1f..227d3eb5a 100644 --- a/target/Config.in +++ b/target/Config.in @@ -122,9 +122,13 @@ config ADK_LINUX_CRIS_FOXBOARD Foxboard support config ADK_LINUX_MIPS64_LEMOTE - bool "Lemote Subnotebook" + bool "Lemote Subnotebook Yeeloong" select ADK_lemote select ADK_LINUX_MIPS64 + select ADK_KERNEL_NETDEVICES + select ADK_KERNEL_NET_PCI + select ADK_KERNEL_NET_ETHERNET + select ADK_KERNEL_MII help Lemote Subnotebook diff --git a/target/lemote/device.mk b/target/lemote/device.mk index 825a8b195..4b5de5ed2 100644 --- a/target/lemote/device.mk +++ b/target/lemote/device.mk @@ -1,7 +1,7 @@ ARCH:= mips CPU_ARCH:= mips64el -KERNEL_VERSION:= 2.6.29.1 +KERNEL_VERSION:= 2.6.30 KERNEL_RELEASE:= 1 -KERNEL_MD5SUM:= 4ada43caecb08fe2af71b416b6f586d8 +KERNEL_MD5SUM:= 7a80058a6382e5108cdb5554d1609615 TARGET_OPTIMIZATION:= -Os -pipe TARGET_CFLAGS_ARCH:= -march=loongson2f -mabi=64 diff --git a/target/lemote/kernel.config b/target/lemote/kernel.config index fb97eedee..f7dee9841 100644 --- a/target/lemote/kernel.config +++ b/target/lemote/kernel.config @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.29.1 -# Wed May 27 21:48:04 2009 +# Linux kernel version: 2.6.30 +# Thu Jun 11 17:37:11 2009 # CONFIG_MIPS=y @@ -9,14 +9,13 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set -# CONFIG_ATHEROS_AR71XX is not set # CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set -CONFIG_LEMOTE_FULONG=y +CONFIG_MACH_LOONGSON=y # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set # CONFIG_NEC_MARKEINS is not set @@ -47,6 +46,13 @@ CONFIG_LEMOTE_FULONG=y # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set # CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set CONFIG_ARCH_SPARSEMEM_ENABLE=y +# CONFIG_LEMOTE_FULOONG2E is not set +# CONFIG_LEMOTE_FULOONG2F is not set +CONFIG_LEMOTE_YEELOONG2F=y +CONFIG_CS5536=y +CONFIG_SYS_HAS_MACH_PROM_INIT_CMDLINE=y +CONFIG_CS5536_MFGPT=y +CONFIG_UCA_SIZE=0x400000 CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set @@ -59,17 +65,12 @@ CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_CEVT_R4K_LIB=y -CONFIG_CEVT_R4K=y -CONFIG_CSRC_R4K_LIB=y -CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y CONFIG_SYS_HAS_EARLY_PRINTK=y # CONFIG_HOTPLUG_CPU is not set CONFIG_I8259=y -# CONFIG_MIPS_MACHINE is not set # CONFIG_NO_IOPORT is not set CONFIG_GENERIC_ISA_DMA=y CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y @@ -79,12 +80,12 @@ CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_HAVE_STD_PC_SERIAL_PORT=y # # CPU selection # -CONFIG_CPU_LOONGSON2=y +# CONFIG_CPU_LOONGSON2E is not set +CONFIG_CPU_LOONGSON2F=y # CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -106,7 +107,8 @@ CONFIG_CPU_LOONGSON2=y # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set # CONFIG_CPU_CAVIUM_OCTEON is not set -CONFIG_SYS_HAS_CPU_LOONGSON2=y +CONFIG_CPU_LOONGSON2=y +CONFIG_SYS_HAS_CPU_LOONGSON2F=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y @@ -117,9 +119,10 @@ CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y # # CONFIG_32BIT is not set CONFIG_64BIT=y -CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_4KB is not set # CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set +CONFIG_PAGE_SIZE_16KB=y +# CONFIG_PAGE_SIZE_32KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_BOARD_SCACHE=y CONFIG_MIPS_MT_DISABLED=y @@ -134,34 +137,41 @@ CONFIG_SYS_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y +# CONFIG_FLATMEM_MANUAL is not set # CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_HAVE_MEMORY_PRESENT=y CONFIG_SPARSEMEM_STATIC=y + +# +# Memory hotplug is currently incompatible with Software Suspend +# CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -# CONFIG_UNEVICTABLE_LRU is not set -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set -CONFIG_HZ_100=y +# CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set +CONFIG_HZ_250=y # CONFIG_HZ_256 is not set # CONFIG_HZ_1000 is not set # CONFIG_HZ_1024 is not set CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=100 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set -# CONFIG_KEXEC is not set +CONFIG_KEXEC=y # CONFIG_SECCOMP is not set CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y @@ -175,13 +185,15 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_SWAP is not set +CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y # CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set +CONFIG_AUDIT=y # # RCU Subsystem @@ -191,15 +203,20 @@ CONFIG_CLASSIC_RCU=y # CONFIG_PREEMPT_RCU is not set # CONFIG_TREE_RCU_TRACE is not set # CONFIG_PREEMPT_RCU_TRACE is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=14 +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 # CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -207,6 +224,7 @@ CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y @@ -222,13 +240,17 @@ CONFIG_SHMEM=y CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y -# CONFIG_COMPAT_BRK is not set +CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -# CONFIG_PROFILING is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# CONFIG_MARKERS is not set +CONFIG_OPROFILE=m CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_SYSCALL_WRAPPERS=y +# CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -236,28 +258,28 @@ CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_BLOCK=y -# CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set +CONFIG_BLOCK_COMPAT=y # # IO Schedulers # CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y # CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -CONFIG_DEFAULT_NOOP=y -CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_PROBE_INITRD_HEADER is not set -# CONFIG_FREEZER is not set +CONFIG_FREEZER=y # # Bus options (PCI, PCMCIA, EISA, ISA, TC) @@ -266,12 +288,16 @@ CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCI_LEGACY is not set +CONFIG_PCI_LEGACY=y # CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set CONFIG_ISA=y CONFIG_MMU=y # CONFIG_PCCARD is not set -# CONFIG_HOTPLUG_PCI is not set +CONFIG_HOTPLUG_PCI=m +CONFIG_HOTPLUG_PCI_FAKE=m +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_SHPC=m # # Executable file formats @@ -279,91 +305,526 @@ CONFIG_MMU=y CONFIG_BINFMT_ELF=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_HAVE_AOUT is not set -# CONFIG_BINFMT_MISC is not set -# CONFIG_MIPS32_COMPAT is not set +CONFIG_BINFMT_MISC=m +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_MIPS32_O32=y +CONFIG_MIPS32_N32=y +CONFIG_BINFMT_ELF32=y # # Power management options # +CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_PM is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="" + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_LOONGSON2F_CPU_FREQ=y CONFIG_NET=y # # Networking options # -CONFIG_COMPAT_NET_DEV_OPS=y CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set +CONFIG_PACKET_MMAP=y CONFIG_UNIX=y CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set +CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y CONFIG_ASK_IP_FIB_HASH=y # CONFIG_IP_FIB_TRIE is not set CONFIG_IP_FIB_HASH=y -# CONFIG_IP_MULTIPLE_TABLES is not set -# CONFIG_IP_ROUTE_MULTIPATH is not set -# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y # CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y # CONFIG_ARPD is not set CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=y +CONFIG_TCP_CONG_CUBIC=m +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +CONFIG_DEFAULT_BIC=y +# CONFIG_DEFAULT_CUBIC is not set +# CONFIG_DEFAULT_HTCP is not set +# CONFIG_DEFAULT_VEGAS is not set +# CONFIG_DEFAULT_WESTWOOD is not set +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="bic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETLABEL is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_TPROXY is not set +CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +CONFIG_NETFILTER_XT_TARGET_HL=m +# CONFIG_NETFILTER_XT_TARGET_LED is not set +CONFIG_NETFILTER_XT_TARGET_MARK=m +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +CONFIG_NETFILTER_XT_MATCH_ESP=m +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_HL=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +CONFIG_NETFILTER_XT_MATCH_REALM=m +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +# CONFIG_IP_NF_SECURITY is not set +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +# CONFIG_IP6_NF_MATCH_MH is not set +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +# CONFIG_IP6_NF_SECURITY is not set + +# +# DECnet: Netfilter Configuration +# +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +# CONFIG_BRIDGE_EBT_IP6 is not set +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m +# CONFIG_BRIDGE_EBT_NFLOG is not set +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_CCID3_RTO=100 +CONFIG_IP_DCCP_TFRC_LIB=y +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +CONFIG_TIPC=m +CONFIG_TIPC_ADVANCED=y +CONFIG_TIPC_ZONES=3 +CONFIG_TIPC_CLUSTERS=1 +CONFIG_TIPC_NODES=255 +CONFIG_TIPC_SLAVE_NODES=0 +CONFIG_TIPC_PORTS=8191 +CONFIG_TIPC_LOG=0 +# CONFIG_TIPC_DEBUG is not set +CONFIG_ATM=y +CONFIG_ATM_CLIP=y +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_STP=m +CONFIG_BRIDGE=m # CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +CONFIG_DECNET=m +# CONFIG_DECNET_ROUTER is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_IPX=m +# CONFIG_IPX_INTERN is not set +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +# CONFIG_COPS is not set +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m +# CONFIG_PHONET is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +# CONFIG_NET_ACT_NAT is not set +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +# CONFIG_NET_ACT_SKBEDIT is not set +CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y # CONFIG_DCB is not set # # Network testing # -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set +CONFIG_NET_PKTGEN=m +# CONFIG_NET_DROP_MONITOR is not set +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +CONFIG_AX25=m +# CONFIG_AX25_DAMA_SLAVE is not set +CONFIG_NETROM=m +CONFIG_ROSE=m + +# +# AX.25 network device drivers +# +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m # CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_PHONET is not set -# CONFIG_WIRELESS is not set +CONFIG_IRDA=m + +# +# IrDA protocols +# +CONFIG_IRLAN=m +CONFIG_IRNET=m +CONFIG_IRCOMM=m +# CONFIG_IRDA_ULTRA is not set + +# +# IrDA options +# +CONFIG_IRDA_CACHE_LAST_LSAP=y +CONFIG_IRDA_FAST_RR=y +CONFIG_IRDA_DEBUG=y + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +CONFIG_IRTTY_SIR=m + +# +# Dongle support +# +CONFIG_DONGLE=y +CONFIG_ESI_DONGLE=m +CONFIG_ACTISYS_DONGLE=m +CONFIG_TEKRAM_DONGLE=m +CONFIG_TOIM3232_DONGLE=m +CONFIG_LITELINK_DONGLE=m +CONFIG_MA600_DONGLE=m +CONFIG_GIRBIL_DONGLE=m +CONFIG_MCP2120_DONGLE=m +CONFIG_OLD_BELKIN_DONGLE=m +CONFIG_ACT200L_DONGLE=m +# CONFIG_KINGSUN_DONGLE is not set +# CONFIG_KSDAZZLE_DONGLE is not set +# CONFIG_KS959_DONGLE is not set + +# +# FIR device drivers +# +CONFIG_USB_IRDA=m +CONFIG_SIGMATEL_FIR=m +CONFIG_VLSI_FIR=m +CONFIG_MCS_FIR=m +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +# CONFIG_BT_HCIUART_LL is not set +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_AF_RXRPC=m +# CONFIG_AF_RXRPC_DEBUG is not set +# CONFIG_RXKAD is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set +CONFIG_MAC80211=y + +# +# Rate control algorithm selection +# +CONFIG_MAC80211_RC_PID=y +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -376,41 +837,296 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_STANDALONE is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FW_LOADER is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=m +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set +CONFIG_CONNECTOR=m +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=m +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=m +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_RAM=m +CONFIG_MTD_ROM=m +CONFIG_MTD_ABSENT=m + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=m +CONFIG_MTD_PHYSMAP_COMPAT=y +CONFIG_MTD_PHYSMAP_START=0x8000000 +CONFIG_MTD_PHYSMAP_LEN=0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +CONFIG_MTD_PCI=m +# CONFIG_MTD_INTEL_VR_NOR is not set +CONFIG_MTD_PLATRAM=m + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_PMC551=m +# CONFIG_MTD_PMC551_BUGFIX is not set +# CONFIG_MTD_PMC551_DEBUG is not set +CONFIG_MTD_DATAFLASH=m +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +# CONFIG_MTD_DATAFLASH_OTP is not set +CONFIG_MTD_M25P80=m +CONFIG_M25PXX_USE_FAST_READ=y +CONFIG_MTD_SLRAM=m +CONFIG_MTD_PHRAM=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTDRAM_TOTAL_SIZE=4096 +CONFIG_MTDRAM_ERASE_SIZE=128 +CONFIG_MTD_BLOCK2MTD=m + +# +# Disk-On-Chip Device Drivers +# +CONFIG_MTD_DOC2000=m +CONFIG_MTD_DOC2001=m +CONFIG_MTD_DOC2001PLUS=m +CONFIG_MTD_DOCPROBE=m +CONFIG_MTD_DOCECC=m +# CONFIG_MTD_DOCPROBE_ADVANCED is not set +CONFIG_MTD_DOCPROBE_ADDRESS=0 +# CONFIG_MTD_NAND is not set +CONFIG_MTD_NAND_IDS=m +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set -# CONFIG_PNP is not set +CONFIG_PNP=y +CONFIG_PNP_DEBUG_MESSAGES=y + +# +# Protocols +# +CONFIG_ISAPNP=y +# CONFIG_PNPACPI is not set CONFIG_BLK_DEV=y # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_NBD=m # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +CONFIG_ATA_OVER_ETH=m # CONFIG_BLK_DEV_HD is not set -# CONFIG_MISC_DEVICES is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +CONFIG_EEPROM_93CX6=y CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set +CONFIG_IDE=y + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +CONFIG_IDE_XFER_MODE=y +CONFIG_IDE_TIMINGS=y +CONFIG_IDE_ATAPI=y +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +CONFIG_BLK_DEV_IDECD=m +CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y +# CONFIG_BLK_DEV_IDETAPE is not set +CONFIG_IDE_TASK_IOCTL=y +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set +# CONFIG_BLK_DEV_IDEPNP is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# +CONFIG_BLK_DEV_IDEPCI=y +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +# CONFIG_BLK_DEV_OFFBOARD is not set +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +CONFIG_BLK_DEV_AMD74XX=y +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT8172 is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set + +# +# Other IDE chipsets support +# + +# +# Note: most of these also require special kernel boot parameters +# +# CONFIG_BLK_DEV_4DRIVES is not set +# CONFIG_BLK_DEV_ALI14XX is not set +# CONFIG_BLK_DEV_DTC2278 is not set +# CONFIG_BLK_DEV_HT6560B is not set +# CONFIG_BLK_DEV_QD65XX is not set +# CONFIG_BLK_DEV_UMC8672 is not set +CONFIG_BLK_DEV_IDEDMA=y # # SCSI device support # -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set +CONFIG_RAID_ATTRS=m +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_SRP_ATTRS=m +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set # CONFIG_ATA is not set -# CONFIG_MD is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_RAID6_PQ=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set # CONFIG_FUSION is not set # @@ -423,27 +1139,282 @@ CONFIG_HAVE_IDE=y # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set -# CONFIG_NETDEVICES is not set +CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y +CONFIG_IFB=m +CONFIG_DUMMY=m +# CONFIG_BONDING is not set +CONFIG_MACVLAN=m +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +CONFIG_VETH=m +# CONFIG_NET_SB1000 is not set +# CONFIG_ARCNET is not set +CONFIG_PHYLIB=m +# CONFIG_SWCONFIG is not set + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m +CONFIG_VITESSE_PHY=m +CONFIG_SMSC_PHY=m +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +CONFIG_REALTEK_PHY=m +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_AT1700 is not set +# CONFIG_DEPCA is not set +# CONFIG_HP100 is not set +# CONFIG_NET_ISA is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_AC3200 is not set +# CONFIG_APRICOT is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_CS89x0 is not set +# CONFIG_TC35815 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +CONFIG_8139CP=m +CONFIG_8139TOO=y +# CONFIG_8139TOO_PIO is not set +CONFIG_8139TOO_TUNE_TWISTER=y +# CONFIG_8139TOO_8129 is not set +# CONFIG_8139_OLD_RX_RESET is not set +# CONFIG_R6040 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SMSC9420 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_ATMEL is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8180 is not set +CONFIG_RTL8187=y +# CONFIG_ADM8211 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_MWL8K is not set +# CONFIG_P54_COMMON is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH9K is not set +# CONFIG_AR9170_USB is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_IWLWIFI is not set +# CONFIG_HOSTAP is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_ZD1211RW is not set +# CONFIG_RT2X00 is not set +# CONFIG_HERMES is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDCETHER=m +# CONFIG_USB_NET_CDC_EEM is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SMSC95XX is not set +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +# CONFIG_USB_NET_MCS7830 is not set +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +# CONFIG_USB_KC2190 is not set +CONFIG_USB_NET_ZAURUS=m +# CONFIG_WAN is not set +# CONFIG_ATM_DRIVERS is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPPOATM=m +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_NET_FC is not set +CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +# CONFIG_NETPOLL_TRAP is not set +CONFIG_NET_POLL_CONTROLLER=y # CONFIG_ISDN is not set # CONFIG_PHONE is not set # # Input device support # -# CONFIG_INPUT is not set +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_LKKBD=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYBOARD_NEWTON=m +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=m +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +CONFIG_MOUSE_INPORT=m +# CONFIG_MOUSE_ATIXL is not set +CONFIG_MOUSE_LOGIBM=m +CONFIG_MOUSE_PC110PAD=m +CONFIG_MOUSE_VSXXXAA=m +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PCSPKR=m +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=m # # Hardware I/O ports # -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_PCIPS2=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m # # Character devices # -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -# CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_COMPUTONE is not set +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_DIGIEPCA is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_ISI is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_SYNCLINK_GT is not set +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_SX is not set +# CONFIG_RIO is not set +CONFIG_STALDRV=y +# CONFIG_STALLION is not set +# CONFIG_ISTALLION is not set # CONFIG_NOZOMI is not set # @@ -451,36 +1422,159 @@ CONFIG_HAVE_IDE=y # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=4 +# CONFIG_SERIAL_8250_PCI is not set +# CONFIG_SERIAL_8250_PNP is not set +CONFIG_SERIAL_8250_NR_UARTS=16 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_FOURPORT=y +# CONFIG_SERIAL_8250_ACCENT is not set +# CONFIG_SERIAL_8250_BOCA is not set +# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set +CONFIG_SERIAL_8250_HUB6=m +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_RSA=y # # Non-8250 serial port support # +# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_RAW_DRIVER is not set +CONFIG_RAW_DRIVER=m +CONFIG_MAX_RAW_DEVS=256 # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y -# CONFIG_I2C is not set -# CONFIG_SPI is not set +CONFIG_I2C=m +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +CONFIG_I2C_ALI1535=m +CONFIG_I2C_ALI1563=m +CONFIG_I2C_ALI15X3=m +CONFIG_I2C_AMD756=m +CONFIG_I2C_AMD8111=m +CONFIG_I2C_I801=m +# CONFIG_I2C_ISCH is not set +CONFIG_I2C_PIIX4=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_SIS5595=m +CONFIG_I2C_SIS630=m +CONFIG_I2C_SIS96X=m +CONFIG_I2C_VIA=m +CONFIG_I2C_VIAPRO=m + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_OCORES=m +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +CONFIG_I2C_PARPORT_LIGHT=m +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Graphics adapter I2C/DDC channel drivers +# +CONFIG_I2C_VOODOO3=m + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_ELEKTOR is not set +CONFIG_I2C_PCA_ISA=m +# CONFIG_I2C_PCA_PLATFORM is not set +CONFIG_I2C_STUB=m + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +CONFIG_SENSORS_PCF8574=m +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +CONFIG_SENSORS_MAX6875=m +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=m + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set -# CONFIG_WATCHDOG is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +CONFIG_SOFT_WATCHDOG=m +# CONFIG_ALIM7101_WDT is not set + +# +# ISA-based Watchdog Cards +# +# CONFIG_PCWATCHDOG is not set +# CONFIG_MIXCOMWD is not set +# CONFIG_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set CONFIG_SSB_POSSIBLE=y # @@ -495,6 +1589,9 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set # CONFIG_REGULATOR is not set # @@ -504,34 +1601,397 @@ CONFIG_SSB_POSSIBLE=y # # Multimedia core support # -# CONFIG_VIDEO_DEV is not set +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y # CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set +CONFIG_VIDEO_MEDIA=m # # Multimedia drivers # +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_TUNER=m +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L1=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA9875 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_BT848 is not set +# CONFIG_VIDEO_PMS is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_VIDEO_STRADIS is not set +# CONFIG_VIDEO_ZORAN is not set +# CONFIG_VIDEO_SAA7134 is not set +# CONFIG_VIDEO_MXB is not set +# CONFIG_VIDEO_HEXIUM_ORION is not set +# CONFIG_VIDEO_HEXIUM_GEMINI is not set +# CONFIG_VIDEO_CX88 is not set +# CONFIG_VIDEO_IVTV is not set +# CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +# CONFIG_USB_GSPCA is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_USB_VICAM is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_QUICKCAM_MESSENGER is not set +# CONFIG_USB_ET61X251 is not set +# CONFIG_VIDEO_OVCAMCHIP is not set +# CONFIG_USB_OV511 is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_STV680 is not set +# CONFIG_USB_ZC0301 is not set +# CONFIG_USB_PWC is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +CONFIG_RADIO_ADAPTERS=y +CONFIG_RADIO_CADET=m +CONFIG_RADIO_RTRACK=m +CONFIG_RADIO_RTRACK2=m +CONFIG_RADIO_AZTECH=m +CONFIG_RADIO_GEMTEK=m +CONFIG_RADIO_GEMTEK_PCI=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_MAESTRO=m +CONFIG_RADIO_SF16FMI=m +CONFIG_RADIO_SF16FMR2=m +CONFIG_RADIO_TERRATEC=m +CONFIG_RADIO_TRUST=m +CONFIG_RADIO_TYPHOON=m +CONFIG_RADIO_TYPHOON_PROC_FS=y +CONFIG_RADIO_ZOLTRIX=m +CONFIG_USB_DSBR=m +# CONFIG_USB_SI470X is not set +# CONFIG_USB_MR800 is not set +# CONFIG_RADIO_TEA5764 is not set # CONFIG_DAB is not set # # Graphics support # -# CONFIG_DRM is not set +CONFIG_DRM=m +CONFIG_DRM_TDFX=m +CONFIG_DRM_R128=m +CONFIG_DRM_RADEON=m +CONFIG_DRM_MGA=m +CONFIG_DRM_VIA=m +CONFIG_DRM_SAVAGE=m # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=m +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +CONFIG_FB_SM7XX=y +CONFIG_FB_SM7XX_ACCEL=y +# CONFIG_FB_SM7XX_DUALHEAD is not set +CONFIG_FB_VIRTUAL=m +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set -# CONFIG_SOUND is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_LOGO is not set +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_RAWMIDI=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +# CONFIG_SND_VIRMIDI is not set +CONFIG_SND_MTPAV=m +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_AC97_POWER_SAVE is not set +CONFIG_SND_PCI=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +CONFIG_SND_CS5535AUDIO=y +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HIFIER is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_USB is not set +# CONFIG_SND_SOC is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +CONFIG_HIDRAW=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_GREENASIA_FF is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=m +CONFIG_USB=y # CONFIG_USB_DEBUG is not set # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set @@ -540,7 +2000,8 @@ CONFIG_USB=m # CONFIG_USB_DEVICEFS=y CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_SUSPEND is not set # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set @@ -552,8 +2013,8 @@ CONFIG_USB_MON=m # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=m -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y # CONFIG_USB_EHCI_TT_NEWSCHED is not set # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set @@ -562,42 +2023,99 @@ CONFIG_USB_OHCI_HCD=m # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y -# CONFIG_USB_UHCI_HCD is not set +CONFIG_USB_UHCI_HCD=m # CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set +CONFIG_USB_R8A66597_HCD=y # CONFIG_USB_WHCI_HCD is not set # CONFIG_USB_HWA_HCD is not set # -# Enable Host or Gadget support to see Inventra options -# - -# # USB Device Class drivers # -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m # CONFIG_USB_WDM is not set # CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # -# see USB_STORAGE Help for more information -# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y # CONFIG_USB_LIBUSUAL is not set # # USB Imaging devices # -# CONFIG_USB_MDC800 is not set +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m # # USB port drivers # -# CONFIG_USB_SERIAL is not set +CONFIG_USB_SERIAL=m +CONFIG_USB_EZUSB=y +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_AIRCABLE is not set +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +# CONFIG_USB_SERIAL_CP210X is not set +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_FUNSOFT=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +# CONFIG_USB_SERIAL_IUU is not set +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +# CONFIG_USB_SERIAL_KEYSPAN is not set +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +CONFIG_USB_SERIAL_HP4X=m +CONFIG_USB_SERIAL_SAFE=m +# CONFIG_USB_SERIAL_SAFE_PADDED is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +# CONFIG_USB_SERIAL_SYMBOL is not set +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_DEBUG is not set # # USB Miscellaneous drivers @@ -606,168 +2124,492 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set +CONFIG_USB_RIO500=m # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_BERRY_CHARGE is not set # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGET is not set -# CONFIG_USB_IDMOUSE is not set +CONFIG_USB_IDMOUSE=m # CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SISUSBVGA_CON=y +CONFIG_USB_LD=m # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set +CONFIG_USB_TEST=m # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_VST is not set +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m # CONFIG_USB_GADGET is not set # # OTG and related infrastructure # +# CONFIG_NOP_USB_XCEIV is not set # CONFIG_UWB is not set -# CONFIG_MMC is not set +CONFIG_MMC=m +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +# CONFIG_MMC_BLOCK is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_SPI is not set # CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=m + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_BD2802 is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# # CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # CONFIG_STAGING is not set # # File systems # -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=m +CONFIG_EXT4DEV_COMPAT=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=m +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_FS_POSIX_ACL=y CONFIG_FILE_LOCKING=y -# CONFIG_XFS_FS is not set +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +# CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_STATS=y +CONFIG_OCFS2_DEBUG_MASKLOG=y +# CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_FS_POSIX_ACL is not set # CONFIG_BTRFS_FS is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS_FS=m +CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=m + +# +# Caches +# +# CONFIG_FSCACHE is not set # # CD-ROM/DVD Filesystems # -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y # # DOS/FAT/NT Filesystems # -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y # # Pseudo filesystems # CONFIG_PROC_FS=y -# CONFIG_PROC_KCORE is not set +CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y -# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set +CONFIG_CONFIGFS_FS=m CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set +CONFIG_ADFS_FS=m +# CONFIG_ADFS_FS_RW is not set +CONFIG_AFFS_FS=m +# CONFIG_ECRYPT_FS is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +# CONFIG_YAFFS_FS is not set +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set +CONFIG_VXFS_FS=m +CONFIG_MINIX_FS=m # CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y -# CONFIG_NFS_FS is not set -# CONFIG_NFSD is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_SPKM3=m +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_EXPERIMENTAL is not set +CONFIG_NCP_FS=m +CONFIG_NCPFS_PACKET_SIGNING=y +CONFIG_NCPFS_IOCTL_LOCKING=y +CONFIG_NCPFS_STRONG=y +CONFIG_NCPFS_NFS_NS=y +CONFIG_NCPFS_OS2_NS=y +# CONFIG_NCPFS_SMALLDOS is not set +CONFIG_NCPFS_NLS=y +CONFIG_NCPFS_EXTRAS=y +CONFIG_CODA_FS=m +CONFIG_AFS_FS=m +# CONFIG_AFS_DEBUG is not set # # Partition Types # -# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_ACORN_PARTITION=y +# CONFIG_ACORN_PARTITION_CUMANA is not set +# CONFIG_ACORN_PARTITION_EESOX is not set +CONFIG_ACORN_PARTITION_ICS=y +# CONFIG_ACORN_PARTITION_ADFS is not set +# CONFIG_ACORN_PARTITION_POWERTEC is not set +CONFIG_ACORN_PARTITION_RISCIX=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y CONFIG_MSDOS_PARTITION=y -# CONFIG_NLS is not set +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf-8" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m # CONFIG_DLM is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_PRINTK_TIME=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_STACKTRACE=y # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y # # Tracers # -# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_DYNAMIC_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y -CONFIG_CMDLINE="init=/init console=ttyS0,115200 " +CONFIG_CMDLINE="" # # Security options # -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +CONFIG_SECURITY=y # CONFIG_SECURITYFS is not set +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +# CONFIG_SECURITY_PATH is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_SECURITY_ROOTPLUG is not set +CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m CONFIG_CRYPTO=y # # Crypto core or helper # # CONFIG_CRYPTO_FIPS is not set -# CONFIG_CRYPTO_MANAGER is not set -# CONFIG_CRYPTO_MANAGER2 is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y # CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m # # Authenticated Encryption with Associated Data @@ -779,10 +2621,10 @@ CONFIG_CRYPTO=y # # Block modes # -# CONFIG_CRYPTO_CBC is not set +CONFIG_CRYPTO_CBC=m # CONFIG_CRYPTO_CTR is not set # CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set +CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_LRW is not set # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set @@ -790,74 +2632,87 @@ CONFIG_CRYPTO=y # # Hash modes # -# CONFIG_CRYPTO_HMAC is not set +CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_XCBC is not set # # Digest # -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m # CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set # CONFIG_CRYPTO_RMD256 is not set # CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m # # Ciphers # -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=m # CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m # CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set +CONFIG_CRYPTO_KHAZAD=m # CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m # # Compression # -# CONFIG_CRYPTO_DEFLATE is not set +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # # Random Number Generation # # CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set # # OCF Configuration # # CONFIG_OCF_OCF is not set +CONFIG_BINARY_PRINTF=y # # Library routines # +CONFIG_BITREVERSE=y CONFIG_GENERIC_FIND_LAST_BIT=y -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m # CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -# CONFIG_CRC32 is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y # CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_PLIST=y +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_DECOMPRESS_GZIP=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/target/lemote/patches/yeelong.patch b/target/lemote/patches/yeelong.patch new file mode 100644 index 000000000..66aa62573 --- /dev/null +++ b/target/lemote/patches/yeelong.patch @@ -0,0 +1,25204 @@ +diff -Nur linux-2.6.30/.gitignore rt4ls/.gitignore +--- linux-2.6.30/.gitignore 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/.gitignore 2009-06-12 16:27:01.954006636 +0200 +@@ -32,6 +32,7 @@ + tags + TAGS + vmlinux ++vmlinux.32 + System.map + Module.markers + Module.symvers +diff -Nur linux-2.6.30/Documentation/kernel-parameters.txt rt4ls/Documentation/kernel-parameters.txt +--- linux-2.6.30/Documentation/kernel-parameters.txt 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/Documentation/kernel-parameters.txt 2009-06-12 16:27:02.534042890 +0200 +@@ -1220,6 +1220,10 @@ + (machvec) in a generic kernel. + Example: machvec=hpzx1_swiotlb + ++ machtype= [Loongson] Share the same kernel image file between different ++ yeeloong laptop. ++ Example: machtype=lemote-yeeloong-2f-7inch ++ + max_addr=nn[KMG] [KNL,BOOT,ia64] All physical memory greater + than or equal to this physical address is ignored. + +diff -Nur linux-2.6.30/arch/mips/Kconfig rt4ls/arch/mips/Kconfig +--- linux-2.6.30/arch/mips/Kconfig 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/Kconfig 2009-06-12 16:27:08.186400556 +0200 +@@ -6,7 +6,7 @@ + select HAVE_ARCH_KGDB + # Horrible source of confusion. Die, die, die ... + select EMBEDDED +- select RTC_LIB ++ select RTC_LIB if !MACH_LOONGSON + + mainmenu "Linux/MIPS Kernel Configuration" + +@@ -154,30 +154,15 @@ + select SYS_SUPPORTS_64BIT_KERNEL if BROKEN + select SYS_SUPPORTS_LITTLE_ENDIAN + +-config LEMOTE_FULONG +- bool "Lemote Fulong mini-PC" +- select ARCH_SPARSEMEM_ENABLE +- select CEVT_R4K +- select CSRC_R4K +- select SYS_HAS_CPU_LOONGSON2 +- select DMA_NONCOHERENT +- select BOOT_ELF32 +- select BOARD_SCACHE +- select HAVE_STD_PC_SERIAL_PORT +- select HW_HAS_PCI +- select I8259 +- select ISA +- select IRQ_CPU +- select SYS_SUPPORTS_32BIT_KERNEL +- select SYS_SUPPORTS_64BIT_KERNEL +- select SYS_SUPPORTS_LITTLE_ENDIAN +- select SYS_SUPPORTS_HIGHMEM +- select SYS_HAS_EARLY_PRINTK +- select GENERIC_ISA_DMA_SUPPORT_BROKEN +- select CPU_HAS_WB ++config MACH_LOONGSON ++ bool "Loongson family of machines" + help +- Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and +- an FPGA northbridge ++ This enables the support of Loongson family of machines. ++ ++ Loongson is a family of general-purpose MIPS-compatible CPUs. ++ developed at Institute of Computing Technology (ICT), ++ Chinese Academy of Sciences (CAS) in the People's Republic ++ of China. The chief architect is Professor Weiwu Hu. + + config MIPS_MALTA + bool "MIPS Malta board" +@@ -643,6 +628,7 @@ + source "arch/mips/txx9/Kconfig" + source "arch/mips/vr41xx/Kconfig" + source "arch/mips/cavium-octeon/Kconfig" ++source "arch/mips/loongson/Kconfig" + + endmenu + +@@ -1005,16 +991,29 @@ + prompt "CPU type" + default CPU_R4X00 + +-config CPU_LOONGSON2 +- bool "Loongson 2" +- depends on SYS_HAS_CPU_LOONGSON2 +- select CPU_SUPPORTS_32BIT_KERNEL +- select CPU_SUPPORTS_64BIT_KERNEL +- select CPU_SUPPORTS_HIGHMEM ++config CPU_LOONGSON2E ++ bool "Loongson 2E" ++ depends on SYS_HAS_CPU_LOONGSON2E ++ select CPU_LOONGSON2 + help + The Loongson 2E processor implements the MIPS III instruction set + with many extensions. + ++ It has an internal FPGA northbridge, which is compatiable to ++ bonito64. ++ ++config CPU_LOONGSON2F ++ bool "Loongson 2F" ++ depends on SYS_HAS_CPU_LOONGSON2F ++ select CPU_LOONGSON2 ++ help ++ The Loongson 2F processor implements the MIPS III instruction set ++ with many extensions. ++ ++ Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller ++ have a similar programming interface with FPGA northbridge used in ++ Loongson2E. ++ + config CPU_MIPS32_R1 + bool "MIPS32 Release 1" + depends on SYS_HAS_CPU_MIPS32_R1 +@@ -1253,7 +1252,16 @@ + + endchoice + +-config SYS_HAS_CPU_LOONGSON2 ++config CPU_LOONGSON2 ++ bool ++ select CPU_SUPPORTS_32BIT_KERNEL ++ select CPU_SUPPORTS_64BIT_KERNEL ++ select CPU_SUPPORTS_HIGHMEM ++ ++config SYS_HAS_CPU_LOONGSON2E ++ bool ++ ++config SYS_HAS_CPU_LOONGSON2F + bool + + config SYS_HAS_CPU_MIPS32_R1 +@@ -2121,6 +2129,9 @@ + + menu "Power management options" + ++config ARCH_HIBERNATION_POSSIBLE ++ def_bool y ++ + config ARCH_SUSPEND_POSSIBLE + def_bool y + depends on !SMP +@@ -2129,6 +2140,23 @@ + + endmenu + ++menu "CPU Frequency scaling" ++ ++source "drivers/cpufreq/Kconfig" ++ ++config LOONGSON2F_CPU_FREQ ++ bool "Loongson-2F CPU Frequency driver" ++ depends on CPU_LOONGSON2F && CPU_FREQ && (CS5536_MFGPT || I8253) ++ select CPU_FREQ_TABLE ++ help ++ This adds the cpufreq driver for Loongson-2F. ++ ++ For details, take a look at <file:Documentation/cpu-freq>. ++ ++ If unsure, say N. ++ ++endmenu ++ + source "net/Kconfig" + + source "drivers/Kconfig" +diff -Nur linux-2.6.30/arch/mips/Makefile rt4ls/arch/mips/Makefile +--- linux-2.6.30/arch/mips/Makefile 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/Makefile 2009-06-12 16:27:08.186400556 +0200 +@@ -120,7 +120,14 @@ + cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap + cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap + cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap +-cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap ++ ++# only gcc >= 4.4 have the loongson-specific support ++cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap ++cflags-$(CONFIG_CPU_LOONGSON2E) += \ ++ $(call cc-option,-march=loongson2e,-march=r4600) $(call cc-option,-mtune=loongson2e) ++cflags-$(CONFIG_CPU_LOONGSON2F) += \ ++ $(call cc-option,-march=loongson2f,-march=r4600) $(call cc-optoin,-mtune=loongson2f) ++ + cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ + -Wa,-mips32 -Wa,--trap + cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ +@@ -307,9 +314,12 @@ + # + # lemote fulong mini-PC board + # +-core-$(CONFIG_LEMOTE_FULONG) +=arch/mips/lemote/lm2e/ +-load-$(CONFIG_LEMOTE_FULONG) +=0xffffffff80100000 +-cflags-$(CONFIG_LEMOTE_FULONG) += -I$(srctree)/arch/mips/include/asm/mach-lemote ++core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/ ++cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \ ++ -mno-branch-likely ++load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000 ++load-$(CONFIG_LEMOTE_FULOONG2F) +=0xffffffff80200000 ++load-$(CONFIG_LEMOTE_YEELOONG2F) +=0xffffffff80200000 + + # + # MIPS Malta board +@@ -675,6 +685,9 @@ + + drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ + ++# suspend and hibernation support ++drivers-$(CONFIG_PM) += arch/mips/power/ ++ + ifdef CONFIG_LASAT + rom.bin rom.sw: vmlinux + $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@ +diff -Nur linux-2.6.30/arch/mips/configs/fulong_defconfig rt4ls/arch/mips/configs/fulong_defconfig +--- linux-2.6.30/arch/mips/configs/fulong_defconfig 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/configs/fulong_defconfig 1970-01-01 01:00:00.000000000 +0100 +@@ -1,1912 +0,0 @@ +-# +-# Automatically generated make config: don't edit +-# Linux kernel version: 2.6.28-rc6 +-# Fri Nov 28 17:53:48 2008 +-# +-CONFIG_MIPS=y +- +-# +-# Machine selection +-# +-# CONFIG_MACH_ALCHEMY is not set +-# CONFIG_BASLER_EXCITE is not set +-# CONFIG_BCM47XX is not set +-# CONFIG_MIPS_COBALT is not set +-# CONFIG_MACH_DECSTATION is not set +-# CONFIG_MACH_JAZZ is not set +-# CONFIG_LASAT is not set +-CONFIG_LEMOTE_FULONG=y +-# CONFIG_MIPS_MALTA is not set +-# CONFIG_MIPS_SIM is not set +-# CONFIG_MACH_EMMA is not set +-# CONFIG_MACH_VR41XX is not set +-# CONFIG_NXP_STB220 is not set +-# CONFIG_NXP_STB225 is not set +-# CONFIG_PNX8550_JBS is not set +-# CONFIG_PNX8550_STB810 is not set +-# CONFIG_PMC_MSP is not set +-# CONFIG_PMC_YOSEMITE is not set +-# CONFIG_SGI_IP22 is not set +-# CONFIG_SGI_IP27 is not set +-# CONFIG_SGI_IP28 is not set +-# CONFIG_SGI_IP32 is not set +-# CONFIG_SIBYTE_CRHINE is not set +-# CONFIG_SIBYTE_CARMEL is not set +-# CONFIG_SIBYTE_CRHONE is not set +-# CONFIG_SIBYTE_RHONE is not set +-# CONFIG_SIBYTE_SWARM is not set +-# CONFIG_SIBYTE_LITTLESUR is not set +-# CONFIG_SIBYTE_SENTOSA is not set +-# CONFIG_SIBYTE_BIGSUR is not set +-# CONFIG_SNI_RM is not set +-# CONFIG_MACH_TX39XX is not set +-# CONFIG_MACH_TX49XX is not set +-# CONFIG_MIKROTIK_RB532 is not set +-# CONFIG_WR_PPMC is not set +-CONFIG_RWSEM_GENERIC_SPINLOCK=y +-# CONFIG_ARCH_HAS_ILOG2_U32 is not set +-# CONFIG_ARCH_HAS_ILOG2_U64 is not set +-CONFIG_ARCH_SUPPORTS_OPROFILE=y +-CONFIG_GENERIC_FIND_NEXT_BIT=y +-CONFIG_GENERIC_HWEIGHT=y +-CONFIG_GENERIC_CALIBRATE_DELAY=y +-CONFIG_GENERIC_CLOCKEVENTS=y +-CONFIG_GENERIC_TIME=y +-CONFIG_GENERIC_CMOS_UPDATE=y +-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +-CONFIG_CEVT_R4K=y +-CONFIG_CSRC_R4K=y +-CONFIG_DMA_NONCOHERENT=y +-CONFIG_DMA_NEED_PCI_MAP_STATE=y +-CONFIG_EARLY_PRINTK=y +-CONFIG_SYS_HAS_EARLY_PRINTK=y +-# CONFIG_HOTPLUG_CPU is not set +-CONFIG_I8259=y +-# CONFIG_NO_IOPORT is not set +-CONFIG_GENERIC_ISA_DMA=y +-CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y +-# CONFIG_CPU_BIG_ENDIAN is not set +-CONFIG_CPU_LITTLE_ENDIAN=y +-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +-CONFIG_IRQ_CPU=y +-CONFIG_BOOT_ELF32=y +-CONFIG_MIPS_L1_CACHE_SHIFT=5 +-CONFIG_HAVE_STD_PC_SERIAL_PORT=y +- +-# +-# CPU selection +-# +-CONFIG_CPU_LOONGSON2=y +-# CONFIG_CPU_MIPS32_R1 is not set +-# CONFIG_CPU_MIPS32_R2 is not set +-# CONFIG_CPU_MIPS64_R1 is not set +-# CONFIG_CPU_MIPS64_R2 is not set +-# CONFIG_CPU_R3000 is not set +-# CONFIG_CPU_TX39XX is not set +-# CONFIG_CPU_VR41XX is not set +-# CONFIG_CPU_R4300 is not set +-# CONFIG_CPU_R4X00 is not set +-# CONFIG_CPU_TX49XX is not set +-# CONFIG_CPU_R5000 is not set +-# CONFIG_CPU_R5432 is not set +-# CONFIG_CPU_R5500 is not set +-# CONFIG_CPU_R6000 is not set +-# CONFIG_CPU_NEVADA is not set +-# CONFIG_CPU_R8000 is not set +-# CONFIG_CPU_R10000 is not set +-# CONFIG_CPU_RM7000 is not set +-# CONFIG_CPU_RM9000 is not set +-# CONFIG_CPU_SB1 is not set +-CONFIG_SYS_HAS_CPU_LOONGSON2=y +-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y +- +-# +-# Kernel type +-# +-# CONFIG_32BIT is not set +-CONFIG_64BIT=y +-# CONFIG_PAGE_SIZE_4KB is not set +-# CONFIG_PAGE_SIZE_8KB is not set +-CONFIG_PAGE_SIZE_16KB=y +-# CONFIG_PAGE_SIZE_64KB is not set +-CONFIG_BOARD_SCACHE=y +-CONFIG_MIPS_MT_DISABLED=y +-# CONFIG_MIPS_MT_SMP is not set +-# CONFIG_MIPS_MT_SMTC is not set +-CONFIG_CPU_HAS_WB=y +-CONFIG_CPU_HAS_SYNC=y +-CONFIG_GENERIC_HARDIRQS=y +-CONFIG_GENERIC_IRQ_PROBE=y +-CONFIG_CPU_SUPPORTS_HIGHMEM=y +-CONFIG_SYS_SUPPORTS_HIGHMEM=y +-CONFIG_ARCH_FLATMEM_ENABLE=y +-CONFIG_ARCH_POPULATES_NODE_MAP=y +-CONFIG_ARCH_SPARSEMEM_ENABLE=y +-CONFIG_SELECT_MEMORY_MODEL=y +-CONFIG_FLATMEM_MANUAL=y +-# CONFIG_DISCONTIGMEM_MANUAL is not set +-# CONFIG_SPARSEMEM_MANUAL is not set +-CONFIG_FLATMEM=y +-CONFIG_FLAT_NODE_MEM_MAP=y +-CONFIG_SPARSEMEM_STATIC=y +-CONFIG_PAGEFLAGS_EXTENDED=y +-CONFIG_SPLIT_PTLOCK_CPUS=4 +-CONFIG_RESOURCES_64BIT=y +-CONFIG_PHYS_ADDR_T_64BIT=y +-CONFIG_ZONE_DMA_FLAG=0 +-CONFIG_VIRT_TO_BUS=y +-CONFIG_UNEVICTABLE_LRU=y +-CONFIG_TICK_ONESHOT=y +-CONFIG_NO_HZ=y +-CONFIG_HIGH_RES_TIMERS=y +-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +-# CONFIG_HZ_48 is not set +-# CONFIG_HZ_100 is not set +-# CONFIG_HZ_128 is not set +-CONFIG_HZ_250=y +-# CONFIG_HZ_256 is not set +-# CONFIG_HZ_1000 is not set +-# CONFIG_HZ_1024 is not set +-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +-CONFIG_HZ=250 +-# CONFIG_PREEMPT_NONE is not set +-CONFIG_PREEMPT_VOLUNTARY=y +-# CONFIG_PREEMPT is not set +-# CONFIG_KEXEC is not set +-CONFIG_SECCOMP=y +-CONFIG_LOCKDEP_SUPPORT=y +-CONFIG_STACKTRACE_SUPPORT=y +-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +- +-# +-# General setup +-# +-CONFIG_EXPERIMENTAL=y +-CONFIG_BROKEN_ON_SMP=y +-CONFIG_INIT_ENV_ARG_LIMIT=32 +-CONFIG_LOCALVERSION="lm32" +-# CONFIG_LOCALVERSION_AUTO is not set +-CONFIG_SWAP=y +-CONFIG_SYSVIPC=y +-CONFIG_SYSVIPC_SYSCTL=y +-CONFIG_POSIX_MQUEUE=y +-CONFIG_BSD_PROCESS_ACCT=y +-# CONFIG_BSD_PROCESS_ACCT_V3 is not set +-# CONFIG_TASKSTATS is not set +-# CONFIG_AUDIT is not set +-CONFIG_IKCONFIG=y +-CONFIG_IKCONFIG_PROC=y +-CONFIG_LOG_BUF_SHIFT=14 +-# CONFIG_CGROUPS is not set +-# CONFIG_GROUP_SCHED is not set +-CONFIG_SYSFS_DEPRECATED=y +-CONFIG_SYSFS_DEPRECATED_V2=y +-# CONFIG_RELAY is not set +-CONFIG_NAMESPACES=y +-# CONFIG_UTS_NS is not set +-# CONFIG_IPC_NS is not set +-CONFIG_USER_NS=y +-CONFIG_PID_NS=y +-# CONFIG_BLK_DEV_INITRD is not set +-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +-CONFIG_SYSCTL=y +-CONFIG_EMBEDDED=y +-CONFIG_SYSCTL_SYSCALL=y +-CONFIG_KALLSYMS=y +-# CONFIG_KALLSYMS_EXTRA_PASS is not set +-CONFIG_HOTPLUG=y +-CONFIG_PRINTK=y +-CONFIG_BUG=y +-CONFIG_ELF_CORE=y +-# CONFIG_PCSPKR_PLATFORM is not set +-# CONFIG_COMPAT_BRK is not set +-CONFIG_BASE_FULL=y +-CONFIG_FUTEX=y +-CONFIG_ANON_INODES=y +-CONFIG_EPOLL=y +-CONFIG_SIGNALFD=y +-CONFIG_TIMERFD=y +-CONFIG_EVENTFD=y +-CONFIG_SHMEM=y +-CONFIG_AIO=y +-CONFIG_VM_EVENT_COUNTERS=y +-CONFIG_PCI_QUIRKS=y +-CONFIG_SLAB=y +-# CONFIG_SLUB is not set +-# CONFIG_SLOB is not set +-CONFIG_PROFILING=y +-# CONFIG_MARKERS is not set +-CONFIG_OPROFILE=m +-CONFIG_HAVE_OPROFILE=y +-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +-CONFIG_SLABINFO=y +-CONFIG_RT_MUTEXES=y +-# CONFIG_TINY_SHMEM is not set +-CONFIG_BASE_SMALL=0 +-CONFIG_MODULES=y +-# CONFIG_MODULE_FORCE_LOAD is not set +-CONFIG_MODULE_UNLOAD=y +-CONFIG_MODULE_FORCE_UNLOAD=y +-# CONFIG_MODVERSIONS is not set +-# CONFIG_MODULE_SRCVERSION_ALL is not set +-CONFIG_KMOD=y +-CONFIG_BLOCK=y +-# CONFIG_BLK_DEV_IO_TRACE is not set +-CONFIG_BLK_DEV_BSG=y +-# CONFIG_BLK_DEV_INTEGRITY is not set +-CONFIG_BLOCK_COMPAT=y +- +-# +-# IO Schedulers +-# +-CONFIG_IOSCHED_NOOP=y +-CONFIG_IOSCHED_AS=y +-CONFIG_IOSCHED_DEADLINE=y +-CONFIG_IOSCHED_CFQ=y +-# CONFIG_DEFAULT_AS is not set +-# CONFIG_DEFAULT_DEADLINE is not set +-CONFIG_DEFAULT_CFQ=y +-# CONFIG_DEFAULT_NOOP is not set +-CONFIG_DEFAULT_IOSCHED="cfq" +-CONFIG_CLASSIC_RCU=y +-CONFIG_FREEZER=y +- +-# +-# Bus options (PCI, PCMCIA, EISA, ISA, TC) +-# +-CONFIG_HW_HAS_PCI=y +-CONFIG_PCI=y +-CONFIG_PCI_DOMAINS=y +-# CONFIG_ARCH_SUPPORTS_MSI is not set +-CONFIG_PCI_LEGACY=y +-CONFIG_ISA=y +-CONFIG_MMU=y +-# CONFIG_PCCARD is not set +-# CONFIG_HOTPLUG_PCI is not set +- +-# +-# Executable file formats +-# +-CONFIG_BINFMT_ELF=y +-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +-# CONFIG_HAVE_AOUT is not set +-CONFIG_BINFMT_MISC=y +-CONFIG_MIPS32_COMPAT=y +-CONFIG_COMPAT=y +-CONFIG_SYSVIPC_COMPAT=y +-CONFIG_MIPS32_O32=y +-CONFIG_MIPS32_N32=y +-CONFIG_BINFMT_ELF32=y +- +-# +-# Power management options +-# +-CONFIG_ARCH_SUSPEND_POSSIBLE=y +-CONFIG_PM=y +-# CONFIG_PM_DEBUG is not set +-CONFIG_PM_SLEEP=y +-CONFIG_SUSPEND=y +-CONFIG_SUSPEND_FREEZER=y +-CONFIG_NET=y +- +-# +-# Networking options +-# +-CONFIG_PACKET=y +-CONFIG_PACKET_MMAP=y +-CONFIG_UNIX=y +-CONFIG_XFRM=y +-# CONFIG_XFRM_USER is not set +-# CONFIG_XFRM_SUB_POLICY is not set +-# CONFIG_XFRM_MIGRATE is not set +-# CONFIG_XFRM_STATISTICS is not set +-# CONFIG_NET_KEY is not set +-CONFIG_INET=y +-CONFIG_IP_MULTICAST=y +-# CONFIG_IP_ADVANCED_ROUTER is not set +-CONFIG_IP_FIB_HASH=y +-CONFIG_IP_PNP=y +-# CONFIG_IP_PNP_DHCP is not set +-CONFIG_IP_PNP_BOOTP=y +-# CONFIG_IP_PNP_RARP is not set +-CONFIG_NET_IPIP=m +-CONFIG_NET_IPGRE=m +-CONFIG_NET_IPGRE_BROADCAST=y +-# CONFIG_IP_MROUTE is not set +-# CONFIG_ARPD is not set +-# CONFIG_SYN_COOKIES is not set +-# CONFIG_INET_AH is not set +-# CONFIG_INET_ESP is not set +-# CONFIG_INET_IPCOMP is not set +-# CONFIG_INET_XFRM_TUNNEL is not set +-CONFIG_INET_TUNNEL=m +-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +-# CONFIG_INET_XFRM_MODE_TUNNEL is not set +-CONFIG_INET_XFRM_MODE_BEET=y +-# CONFIG_INET_LRO is not set +-# CONFIG_INET_DIAG is not set +-# CONFIG_TCP_CONG_ADVANCED is not set +-CONFIG_TCP_CONG_CUBIC=y +-CONFIG_DEFAULT_TCP_CONG="cubic" +-# CONFIG_TCP_MD5SIG is not set +-# CONFIG_IPV6 is not set +-# CONFIG_NETWORK_SECMARK is not set +-CONFIG_NETFILTER=y +-# CONFIG_NETFILTER_DEBUG is not set +-CONFIG_NETFILTER_ADVANCED=y +- +-# +-# Core Netfilter Configuration +-# +-CONFIG_NETFILTER_NETLINK=m +-CONFIG_NETFILTER_NETLINK_QUEUE=m +-CONFIG_NETFILTER_NETLINK_LOG=m +-# CONFIG_NF_CONNTRACK is not set +-CONFIG_NETFILTER_XTABLES=m +-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +-# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +-CONFIG_NETFILTER_XT_TARGET_MARK=m +-# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +-CONFIG_NETFILTER_XT_TARGET_RATEEST=m +-CONFIG_NETFILTER_XT_TARGET_TRACE=m +-# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +-CONFIG_NETFILTER_XT_MATCH_COMMENT=m +-CONFIG_NETFILTER_XT_MATCH_DCCP=m +-# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +-CONFIG_NETFILTER_XT_MATCH_ESP=m +-# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +-CONFIG_NETFILTER_XT_MATCH_LENGTH=m +-CONFIG_NETFILTER_XT_MATCH_LIMIT=m +-CONFIG_NETFILTER_XT_MATCH_MAC=m +-CONFIG_NETFILTER_XT_MATCH_MARK=m +-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +-CONFIG_NETFILTER_XT_MATCH_OWNER=m +-# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +-CONFIG_NETFILTER_XT_MATCH_QUOTA=m +-CONFIG_NETFILTER_XT_MATCH_RATEEST=m +-CONFIG_NETFILTER_XT_MATCH_REALM=m +-CONFIG_NETFILTER_XT_MATCH_RECENT=m +-# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set +-CONFIG_NETFILTER_XT_MATCH_SCTP=m +-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +-CONFIG_NETFILTER_XT_MATCH_STRING=m +-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +-CONFIG_NETFILTER_XT_MATCH_TIME=m +-CONFIG_NETFILTER_XT_MATCH_U32=m +-# CONFIG_IP_VS is not set +- +-# +-# IP: Netfilter Configuration +-# +-# CONFIG_NF_DEFRAG_IPV4 is not set +-CONFIG_IP_NF_QUEUE=m +-CONFIG_IP_NF_IPTABLES=m +-CONFIG_IP_NF_MATCH_ADDRTYPE=m +-CONFIG_IP_NF_MATCH_AH=m +-CONFIG_IP_NF_MATCH_ECN=m +-CONFIG_IP_NF_MATCH_TTL=m +-CONFIG_IP_NF_FILTER=m +-CONFIG_IP_NF_TARGET_REJECT=m +-CONFIG_IP_NF_TARGET_LOG=m +-CONFIG_IP_NF_TARGET_ULOG=m +-CONFIG_IP_NF_MANGLE=m +-CONFIG_IP_NF_TARGET_ECN=m +-CONFIG_IP_NF_TARGET_TTL=m +-CONFIG_IP_NF_RAW=m +-CONFIG_IP_NF_ARPTABLES=m +-CONFIG_IP_NF_ARPFILTER=m +-CONFIG_IP_NF_ARP_MANGLE=m +-# CONFIG_IP_DCCP is not set +-# CONFIG_IP_SCTP is not set +-# CONFIG_TIPC is not set +-# CONFIG_ATM is not set +-# CONFIG_BRIDGE is not set +-# CONFIG_NET_DSA is not set +-# CONFIG_VLAN_8021Q is not set +-# CONFIG_DECNET is not set +-# CONFIG_LLC2 is not set +-# CONFIG_IPX is not set +-# CONFIG_ATALK is not set +-# CONFIG_X25 is not set +-# CONFIG_LAPB is not set +-# CONFIG_ECONET is not set +-# CONFIG_WAN_ROUTER is not set +-# CONFIG_NET_SCHED is not set +-CONFIG_NET_CLS_ROUTE=y +- +-# +-# Network testing +-# +-# CONFIG_NET_PKTGEN is not set +-# CONFIG_HAMRADIO is not set +-# CONFIG_CAN is not set +-# CONFIG_IRDA is not set +-# CONFIG_BT is not set +-# CONFIG_AF_RXRPC is not set +-CONFIG_PHONET=m +-CONFIG_WIRELESS=y +-# CONFIG_CFG80211 is not set +-CONFIG_WIRELESS_OLD_REGULATORY=y +-CONFIG_WIRELESS_EXT=y +-CONFIG_WIRELESS_EXT_SYSFS=y +-# CONFIG_MAC80211 is not set +-CONFIG_IEEE80211=m +-# CONFIG_IEEE80211_DEBUG is not set +-CONFIG_IEEE80211_CRYPT_WEP=m +-# CONFIG_IEEE80211_CRYPT_CCMP is not set +-# CONFIG_IEEE80211_CRYPT_TKIP is not set +-# CONFIG_RFKILL is not set +-CONFIG_NET_9P=m +-# CONFIG_NET_9P_DEBUG is not set +- +-# +-# Device Drivers +-# +- +-# +-# Generic Driver Options +-# +-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +-CONFIG_STANDALONE=y +-CONFIG_PREVENT_FIRMWARE_BUILD=y +-CONFIG_FW_LOADER=m +-CONFIG_FIRMWARE_IN_KERNEL=y +-CONFIG_EXTRA_FIRMWARE="" +-# CONFIG_SYS_HYPERVISOR is not set +-# CONFIG_CONNECTOR is not set +-CONFIG_MTD=m +-# CONFIG_MTD_DEBUG is not set +-# CONFIG_MTD_CONCAT is not set +-# CONFIG_MTD_PARTITIONS is not set +- +-# +-# User Modules And Translation Layers +-# +-CONFIG_MTD_CHAR=m +-CONFIG_MTD_BLKDEVS=m +-CONFIG_MTD_BLOCK=m +-# CONFIG_MTD_BLOCK_RO is not set +-# CONFIG_FTL is not set +-# CONFIG_NFTL is not set +-# CONFIG_INFTL is not set +-# CONFIG_RFD_FTL is not set +-# CONFIG_SSFDC is not set +-# CONFIG_MTD_OOPS is not set +- +-# +-# RAM/ROM/Flash chip drivers +-# +-CONFIG_MTD_CFI=m +-CONFIG_MTD_JEDECPROBE=m +-CONFIG_MTD_GEN_PROBE=m +-CONFIG_MTD_CFI_ADV_OPTIONS=y +-CONFIG_MTD_CFI_NOSWAP=y +-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +-# CONFIG_MTD_CFI_GEOMETRY is not set +-CONFIG_MTD_MAP_BANK_WIDTH_1=y +-CONFIG_MTD_MAP_BANK_WIDTH_2=y +-CONFIG_MTD_MAP_BANK_WIDTH_4=y +-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +-CONFIG_MTD_CFI_I1=y +-CONFIG_MTD_CFI_I2=y +-# CONFIG_MTD_CFI_I4 is not set +-# CONFIG_MTD_CFI_I8 is not set +-# CONFIG_MTD_OTP is not set +-# CONFIG_MTD_CFI_INTELEXT is not set +-CONFIG_MTD_CFI_AMDSTD=m +-CONFIG_MTD_CFI_STAA=m +-CONFIG_MTD_CFI_UTIL=m +-# CONFIG_MTD_RAM is not set +-# CONFIG_MTD_ROM is not set +-# CONFIG_MTD_ABSENT is not set +- +-# +-# Mapping drivers for chip access +-# +-# CONFIG_MTD_COMPLEX_MAPPINGS is not set +-CONFIG_MTD_PHYSMAP=m +-CONFIG_MTD_PHYSMAP_START=0x1fc00000 +-CONFIG_MTD_PHYSMAP_LEN=0x80000 +-CONFIG_MTD_PHYSMAP_BANKWIDTH=1 +-# CONFIG_MTD_INTEL_VR_NOR is not set +-# CONFIG_MTD_PLATRAM is not set +- +-# +-# Self-contained MTD device drivers +-# +-# CONFIG_MTD_PMC551 is not set +-# CONFIG_MTD_SLRAM is not set +-# CONFIG_MTD_PHRAM is not set +-# CONFIG_MTD_MTDRAM is not set +-# CONFIG_MTD_BLOCK2MTD is not set +- +-# +-# Disk-On-Chip Device Drivers +-# +-# CONFIG_MTD_DOC2000 is not set +-# CONFIG_MTD_DOC2001 is not set +-# CONFIG_MTD_DOC2001PLUS is not set +-# CONFIG_MTD_NAND is not set +-# CONFIG_MTD_ONENAND is not set +- +-# +-# UBI - Unsorted block images +-# +-# CONFIG_MTD_UBI is not set +-# CONFIG_PARPORT is not set +-# CONFIG_PNP is not set +-CONFIG_BLK_DEV=y +-# CONFIG_BLK_CPQ_DA is not set +-# CONFIG_BLK_CPQ_CISS_DA is not set +-# CONFIG_BLK_DEV_DAC960 is not set +-# CONFIG_BLK_DEV_UMEM is not set +-# CONFIG_BLK_DEV_COW_COMMON is not set +-CONFIG_BLK_DEV_LOOP=y +-CONFIG_BLK_DEV_CRYPTOLOOP=m +-# CONFIG_BLK_DEV_NBD is not set +-# CONFIG_BLK_DEV_SX8 is not set +-# CONFIG_BLK_DEV_UB is not set +-CONFIG_BLK_DEV_RAM=m +-CONFIG_BLK_DEV_RAM_COUNT=16 +-CONFIG_BLK_DEV_RAM_SIZE=4096 +-# CONFIG_BLK_DEV_XIP is not set +-CONFIG_CDROM_PKTCDVD=m +-CONFIG_CDROM_PKTCDVD_BUFFERS=8 +-# CONFIG_CDROM_PKTCDVD_WCACHE is not set +-CONFIG_ATA_OVER_ETH=m +-# CONFIG_BLK_DEV_HD is not set +-# CONFIG_MISC_DEVICES is not set +-CONFIG_HAVE_IDE=y +-CONFIG_IDE=y +- +-# +-# Please see Documentation/ide/ide.txt for help/info on IDE drives +-# +-CONFIG_IDE_TIMINGS=y +-CONFIG_IDE_ATAPI=y +-# CONFIG_BLK_DEV_IDE_SATA is not set +-CONFIG_IDE_GD=y +-CONFIG_IDE_GD_ATA=y +-# CONFIG_IDE_GD_ATAPI is not set +-CONFIG_BLK_DEV_IDECD=y +-CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y +-# CONFIG_BLK_DEV_IDETAPE is not set +-CONFIG_BLK_DEV_IDESCSI=y +-CONFIG_IDE_TASK_IOCTL=y +-CONFIG_IDE_PROC_FS=y +- +-# +-# IDE chipset support/bugfixes +-# +-CONFIG_IDE_GENERIC=y +-# CONFIG_BLK_DEV_PLATFORM is not set +-CONFIG_BLK_DEV_IDEDMA_SFF=y +- +-# +-# PCI IDE chipsets support +-# +-CONFIG_BLK_DEV_IDEPCI=y +-CONFIG_IDEPCI_PCIBUS_ORDER=y +-# CONFIG_BLK_DEV_OFFBOARD is not set +-CONFIG_BLK_DEV_GENERIC=y +-# CONFIG_BLK_DEV_OPTI621 is not set +-CONFIG_BLK_DEV_IDEDMA_PCI=y +-# CONFIG_BLK_DEV_AEC62XX is not set +-# CONFIG_BLK_DEV_ALI15X3 is not set +-# CONFIG_BLK_DEV_AMD74XX is not set +-# CONFIG_BLK_DEV_CMD64X is not set +-# CONFIG_BLK_DEV_TRIFLEX is not set +-# CONFIG_BLK_DEV_CS5520 is not set +-# CONFIG_BLK_DEV_CS5530 is not set +-# CONFIG_BLK_DEV_HPT366 is not set +-# CONFIG_BLK_DEV_JMICRON is not set +-# CONFIG_BLK_DEV_SC1200 is not set +-# CONFIG_BLK_DEV_PIIX is not set +-# CONFIG_BLK_DEV_IT8213 is not set +-# CONFIG_BLK_DEV_IT821X is not set +-# CONFIG_BLK_DEV_NS87415 is not set +-# CONFIG_BLK_DEV_PDC202XX_OLD is not set +-# CONFIG_BLK_DEV_PDC202XX_NEW is not set +-# CONFIG_BLK_DEV_SVWKS is not set +-# CONFIG_BLK_DEV_SIIMAGE is not set +-# CONFIG_BLK_DEV_SLC90E66 is not set +-# CONFIG_BLK_DEV_TRM290 is not set +-CONFIG_BLK_DEV_VIA82CXXX=y +-# CONFIG_BLK_DEV_TC86C001 is not set +- +-# +-# Other IDE chipsets support +-# +- +-# +-# Note: most of these also require special kernel boot parameters +-# +-# CONFIG_BLK_DEV_4DRIVES is not set +-# CONFIG_BLK_DEV_ALI14XX is not set +-# CONFIG_BLK_DEV_DTC2278 is not set +-# CONFIG_BLK_DEV_HT6560B is not set +-# CONFIG_BLK_DEV_QD65XX is not set +-# CONFIG_BLK_DEV_UMC8672 is not set +-CONFIG_BLK_DEV_IDEDMA=y +- +-# +-# SCSI device support +-# +-# CONFIG_RAID_ATTRS is not set +-CONFIG_SCSI=y +-CONFIG_SCSI_DMA=y +-# CONFIG_SCSI_TGT is not set +-# CONFIG_SCSI_NETLINK is not set +-CONFIG_SCSI_PROC_FS=y +- +-# +-# SCSI support type (disk, tape, CD-ROM) +-# +-CONFIG_BLK_DEV_SD=y +-# CONFIG_CHR_DEV_ST is not set +-# CONFIG_CHR_DEV_OSST is not set +-CONFIG_BLK_DEV_SR=y +-CONFIG_BLK_DEV_SR_VENDOR=y +-CONFIG_CHR_DEV_SG=y +-# CONFIG_CHR_DEV_SCH is not set +- +-# +-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +-# +-# CONFIG_SCSI_MULTI_LUN is not set +-CONFIG_SCSI_CONSTANTS=y +-# CONFIG_SCSI_LOGGING is not set +-# CONFIG_SCSI_SCAN_ASYNC is not set +-CONFIG_SCSI_WAIT_SCAN=m +- +-# +-# SCSI Transports +-# +-# CONFIG_SCSI_SPI_ATTRS is not set +-# CONFIG_SCSI_FC_ATTRS is not set +-# CONFIG_SCSI_ISCSI_ATTRS is not set +-# CONFIG_SCSI_SAS_ATTRS is not set +-# CONFIG_SCSI_SAS_LIBSAS is not set +-# CONFIG_SCSI_SRP_ATTRS is not set +-# CONFIG_SCSI_LOWLEVEL is not set +-# CONFIG_SCSI_DH is not set +-# CONFIG_ATA is not set +-# CONFIG_MD is not set +-# CONFIG_FUSION is not set +- +-# +-# IEEE 1394 (FireWire) support +-# +- +-# +-# Enable only one of the two stacks, unless you know what you are doing +-# +-# CONFIG_FIREWIRE is not set +-# CONFIG_IEEE1394 is not set +-# CONFIG_I2O is not set +-CONFIG_NETDEVICES=y +-# CONFIG_DUMMY is not set +-# CONFIG_BONDING is not set +-CONFIG_MACVLAN=m +-# CONFIG_EQUALIZER is not set +-# CONFIG_TUN is not set +-CONFIG_VETH=m +-# CONFIG_ARCNET is not set +-CONFIG_PHYLIB=m +- +-# +-# MII PHY device drivers +-# +-CONFIG_MARVELL_PHY=m +-CONFIG_DAVICOM_PHY=m +-CONFIG_QSEMI_PHY=m +-CONFIG_LXT_PHY=m +-CONFIG_CICADA_PHY=m +-# CONFIG_VITESSE_PHY is not set +-# CONFIG_SMSC_PHY is not set +-# CONFIG_BROADCOM_PHY is not set +-# CONFIG_ICPLUS_PHY is not set +-# CONFIG_REALTEK_PHY is not set +-# CONFIG_MDIO_BITBANG is not set +-CONFIG_NET_ETHERNET=y +-CONFIG_MII=y +-# CONFIG_AX88796 is not set +-# CONFIG_HAPPYMEAL is not set +-# CONFIG_SUNGEM is not set +-# CONFIG_CASSINI is not set +-# CONFIG_NET_VENDOR_3COM is not set +-# CONFIG_NET_VENDOR_SMC is not set +-# CONFIG_SMC91X is not set +-# CONFIG_DM9000 is not set +-# CONFIG_NET_VENDOR_RACAL is not set +-# CONFIG_NET_TULIP is not set +-# CONFIG_AT1700 is not set +-# CONFIG_DEPCA is not set +-# CONFIG_HP100 is not set +-# CONFIG_NET_ISA is not set +-# CONFIG_IBM_NEW_EMAC_ZMII is not set +-# CONFIG_IBM_NEW_EMAC_RGMII is not set +-# CONFIG_IBM_NEW_EMAC_TAH is not set +-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +-CONFIG_NET_PCI=y +-# CONFIG_PCNET32 is not set +-# CONFIG_AMD8111_ETH is not set +-# CONFIG_ADAPTEC_STARFIRE is not set +-# CONFIG_AC3200 is not set +-# CONFIG_APRICOT is not set +-# CONFIG_B44 is not set +-# CONFIG_FORCEDETH is not set +-# CONFIG_CS89x0 is not set +-# CONFIG_TC35815 is not set +-# CONFIG_EEPRO100 is not set +-# CONFIG_E100 is not set +-# CONFIG_FEALNX is not set +-# CONFIG_NATSEMI is not set +-# CONFIG_NE2K_PCI is not set +-# CONFIG_8139CP is not set +-CONFIG_8139TOO=y +-# CONFIG_8139TOO_PIO is not set +-# CONFIG_8139TOO_TUNE_TWISTER is not set +-# CONFIG_8139TOO_8129 is not set +-# CONFIG_8139_OLD_RX_RESET is not set +-# CONFIG_R6040 is not set +-# CONFIG_SIS900 is not set +-# CONFIG_EPIC100 is not set +-# CONFIG_SUNDANCE is not set +-# CONFIG_TLAN is not set +-# CONFIG_VIA_RHINE is not set +-# CONFIG_SC92031 is not set +-# CONFIG_ATL2 is not set +-CONFIG_NETDEV_1000=y +-# CONFIG_ACENIC is not set +-# CONFIG_DL2K is not set +-# CONFIG_E1000 is not set +-# CONFIG_E1000E is not set +-# CONFIG_IP1000 is not set +-# CONFIG_IGB is not set +-# CONFIG_NS83820 is not set +-# CONFIG_HAMACHI is not set +-# CONFIG_YELLOWFIN is not set +-# CONFIG_R8169 is not set +-# CONFIG_SIS190 is not set +-# CONFIG_SKGE is not set +-# CONFIG_SKY2 is not set +-# CONFIG_VIA_VELOCITY is not set +-# CONFIG_TIGON3 is not set +-# CONFIG_BNX2 is not set +-# CONFIG_QLA3XXX is not set +-# CONFIG_ATL1 is not set +-# CONFIG_ATL1E is not set +-# CONFIG_JME is not set +-CONFIG_NETDEV_10000=y +-# CONFIG_CHELSIO_T1 is not set +-# CONFIG_CHELSIO_T3 is not set +-# CONFIG_ENIC is not set +-# CONFIG_IXGBE is not set +-# CONFIG_IXGB is not set +-# CONFIG_S2IO is not set +-# CONFIG_MYRI10GE is not set +-# CONFIG_NETXEN_NIC is not set +-# CONFIG_NIU is not set +-# CONFIG_MLX4_EN is not set +-# CONFIG_MLX4_CORE is not set +-# CONFIG_TEHUTI is not set +-# CONFIG_BNX2X is not set +-# CONFIG_QLGE is not set +-# CONFIG_SFC is not set +-# CONFIG_TR is not set +- +-# +-# Wireless LAN +-# +-# CONFIG_WLAN_PRE80211 is not set +-# CONFIG_WLAN_80211 is not set +-# CONFIG_IWLWIFI_LEDS is not set +- +-# +-# USB Network Adapters +-# +-# CONFIG_USB_CATC is not set +-# CONFIG_USB_KAWETH is not set +-# CONFIG_USB_PEGASUS is not set +-# CONFIG_USB_RTL8150 is not set +-# CONFIG_USB_USBNET is not set +-# CONFIG_WAN is not set +-# CONFIG_FDDI is not set +-# CONFIG_HIPPI is not set +-CONFIG_PPP=m +-CONFIG_PPP_MULTILINK=y +-CONFIG_PPP_FILTER=y +-CONFIG_PPP_ASYNC=m +-CONFIG_PPP_SYNC_TTY=m +-CONFIG_PPP_DEFLATE=m +-CONFIG_PPP_BSDCOMP=m +-CONFIG_PPP_MPPE=m +-CONFIG_PPPOE=m +-CONFIG_PPPOL2TP=m +-CONFIG_SLIP=m +-CONFIG_SLIP_COMPRESSED=y +-CONFIG_SLHC=m +-CONFIG_SLIP_SMART=y +-CONFIG_SLIP_MODE_SLIP6=y +-CONFIG_NET_FC=y +-# CONFIG_NETCONSOLE is not set +-# CONFIG_NETPOLL is not set +-# CONFIG_NET_POLL_CONTROLLER is not set +-# CONFIG_ISDN is not set +-# CONFIG_PHONE is not set +- +-# +-# Input device support +-# +-CONFIG_INPUT=y +-CONFIG_INPUT_FF_MEMLESS=y +-# CONFIG_INPUT_POLLDEV is not set +- +-# +-# Userland interfaces +-# +-CONFIG_INPUT_MOUSEDEV=y +-CONFIG_INPUT_MOUSEDEV_PSAUX=y +-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +-# CONFIG_INPUT_JOYDEV is not set +-# CONFIG_INPUT_EVDEV is not set +-# CONFIG_INPUT_EVBUG is not set +- +-# +-# Input Device Drivers +-# +-CONFIG_INPUT_KEYBOARD=y +-CONFIG_KEYBOARD_ATKBD=m +-# CONFIG_KEYBOARD_SUNKBD is not set +-# CONFIG_KEYBOARD_LKKBD is not set +-# CONFIG_KEYBOARD_XTKBD is not set +-# CONFIG_KEYBOARD_NEWTON is not set +-# CONFIG_KEYBOARD_STOWAWAY is not set +-CONFIG_INPUT_MOUSE=y +-CONFIG_MOUSE_PS2=y +-CONFIG_MOUSE_PS2_ALPS=y +-CONFIG_MOUSE_PS2_LOGIPS2PP=y +-CONFIG_MOUSE_PS2_SYNAPTICS=y +-CONFIG_MOUSE_PS2_LIFEBOOK=y +-CONFIG_MOUSE_PS2_TRACKPOINT=y +-# CONFIG_MOUSE_PS2_ELANTECH is not set +-# CONFIG_MOUSE_PS2_TOUCHKIT is not set +-CONFIG_MOUSE_SERIAL=y +-# CONFIG_MOUSE_APPLETOUCH is not set +-# CONFIG_MOUSE_BCM5974 is not set +-# CONFIG_MOUSE_INPORT is not set +-# CONFIG_MOUSE_LOGIBM is not set +-# CONFIG_MOUSE_PC110PAD is not set +-# CONFIG_MOUSE_VSXXXAA is not set +-# CONFIG_INPUT_JOYSTICK is not set +-# CONFIG_INPUT_TABLET is not set +-# CONFIG_INPUT_TOUCHSCREEN is not set +-# CONFIG_INPUT_MISC is not set +- +-# +-# Hardware I/O ports +-# +-CONFIG_SERIO=y +-CONFIG_SERIO_I8042=y +-CONFIG_SERIO_SERPORT=y +-# CONFIG_SERIO_PCIPS2 is not set +-CONFIG_SERIO_LIBPS2=y +-# CONFIG_SERIO_RAW is not set +-# CONFIG_GAMEPORT is not set +- +-# +-# Character devices +-# +-CONFIG_VT=y +-CONFIG_CONSOLE_TRANSLATIONS=y +-CONFIG_VT_CONSOLE=y +-CONFIG_HW_CONSOLE=y +-# CONFIG_VT_HW_CONSOLE_BINDING is not set +-CONFIG_DEVKMEM=y +-# CONFIG_SERIAL_NONSTANDARD is not set +-# CONFIG_NOZOMI is not set +- +-# +-# Serial drivers +-# +-CONFIG_SERIAL_8250=y +-CONFIG_SERIAL_8250_CONSOLE=y +-CONFIG_SERIAL_8250_PCI=y +-CONFIG_SERIAL_8250_NR_UARTS=2 +-CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +-# CONFIG_SERIAL_8250_EXTENDED is not set +- +-# +-# Non-8250 serial port support +-# +-CONFIG_SERIAL_CORE=y +-CONFIG_SERIAL_CORE_CONSOLE=y +-# CONFIG_SERIAL_JSM is not set +-CONFIG_UNIX98_PTYS=y +-CONFIG_LEGACY_PTYS=y +-CONFIG_LEGACY_PTY_COUNT=256 +-# CONFIG_IPMI_HANDLER is not set +-CONFIG_HW_RANDOM=y +-# CONFIG_DTLK is not set +-# CONFIG_R3964 is not set +-# CONFIG_APPLICOM is not set +-# CONFIG_RAW_DRIVER is not set +-# CONFIG_TCG_TPM is not set +-CONFIG_DEVPORT=y +-CONFIG_I2C=m +-CONFIG_I2C_BOARDINFO=y +-CONFIG_I2C_CHARDEV=m +-CONFIG_I2C_HELPER_AUTO=y +- +-# +-# I2C Hardware Bus support +-# +- +-# +-# PC SMBus host controller drivers +-# +-# CONFIG_I2C_ALI1535 is not set +-# CONFIG_I2C_ALI1563 is not set +-# CONFIG_I2C_ALI15X3 is not set +-# CONFIG_I2C_AMD756 is not set +-# CONFIG_I2C_AMD8111 is not set +-# CONFIG_I2C_I801 is not set +-# CONFIG_I2C_ISCH is not set +-# CONFIG_I2C_PIIX4 is not set +-# CONFIG_I2C_NFORCE2 is not set +-# CONFIG_I2C_SIS5595 is not set +-# CONFIG_I2C_SIS630 is not set +-# CONFIG_I2C_SIS96X is not set +-# CONFIG_I2C_VIA is not set +-CONFIG_I2C_VIAPRO=m +- +-# +-# I2C system bus drivers (mostly embedded / system-on-chip) +-# +-# CONFIG_I2C_OCORES is not set +-# CONFIG_I2C_SIMTEC is not set +- +-# +-# External I2C/SMBus adapter drivers +-# +-# CONFIG_I2C_PARPORT_LIGHT is not set +-# CONFIG_I2C_TAOS_EVM is not set +-# CONFIG_I2C_TINY_USB is not set +- +-# +-# Graphics adapter I2C/DDC channel drivers +-# +-# CONFIG_I2C_VOODOO3 is not set +- +-# +-# Other I2C/SMBus bus drivers +-# +-# CONFIG_I2C_ELEKTOR is not set +-# CONFIG_I2C_PCA_ISA is not set +-# CONFIG_I2C_PCA_PLATFORM is not set +-# CONFIG_I2C_STUB is not set +- +-# +-# Miscellaneous I2C Chip support +-# +-# CONFIG_DS1682 is not set +-# CONFIG_EEPROM_AT24 is not set +-# CONFIG_EEPROM_LEGACY is not set +-# CONFIG_SENSORS_PCF8574 is not set +-# CONFIG_PCF8575 is not set +-# CONFIG_SENSORS_PCA9539 is not set +-# CONFIG_SENSORS_PCF8591 is not set +-# CONFIG_SENSORS_MAX6875 is not set +-# CONFIG_SENSORS_TSL2550 is not set +-# CONFIG_I2C_DEBUG_CORE is not set +-# CONFIG_I2C_DEBUG_ALGO is not set +-# CONFIG_I2C_DEBUG_BUS is not set +-# CONFIG_I2C_DEBUG_CHIP is not set +-# CONFIG_SPI is not set +-# CONFIG_W1 is not set +-# CONFIG_POWER_SUPPLY is not set +-# CONFIG_HWMON is not set +-# CONFIG_THERMAL is not set +-# CONFIG_THERMAL_HWMON is not set +-# CONFIG_WATCHDOG is not set +-CONFIG_SSB_POSSIBLE=y +- +-# +-# Sonics Silicon Backplane +-# +-# CONFIG_SSB is not set +- +-# +-# Multifunction device drivers +-# +-# CONFIG_MFD_CORE is not set +-# CONFIG_MFD_SM501 is not set +-# CONFIG_HTC_PASIC3 is not set +-# CONFIG_MFD_TMIO is not set +-# CONFIG_MFD_WM8400 is not set +-# CONFIG_MFD_WM8350_I2C is not set +-# CONFIG_REGULATOR is not set +- +-# +-# Multimedia devices +-# +- +-# +-# Multimedia core support +-# +-CONFIG_VIDEO_DEV=m +-CONFIG_VIDEO_V4L2_COMMON=m +-CONFIG_VIDEO_ALLOW_V4L1=y +-CONFIG_VIDEO_V4L1_COMPAT=y +-# CONFIG_DVB_CORE is not set +-CONFIG_VIDEO_MEDIA=m +- +-# +-# Multimedia drivers +-# +-CONFIG_MEDIA_ATTACH=y +-CONFIG_MEDIA_TUNER=m +-CONFIG_MEDIA_TUNER_CUSTOMIZE=y +-CONFIG_MEDIA_TUNER_SIMPLE=m +-CONFIG_MEDIA_TUNER_TDA8290=m +-CONFIG_MEDIA_TUNER_TDA827X=m +-CONFIG_MEDIA_TUNER_TDA18271=m +-CONFIG_MEDIA_TUNER_TDA9887=m +-CONFIG_MEDIA_TUNER_TEA5761=m +-CONFIG_MEDIA_TUNER_TEA5767=m +-CONFIG_MEDIA_TUNER_MT20XX=m +-CONFIG_MEDIA_TUNER_MT2060=m +-CONFIG_MEDIA_TUNER_MT2266=m +-CONFIG_MEDIA_TUNER_MT2131=m +-CONFIG_MEDIA_TUNER_QT1010=m +-CONFIG_MEDIA_TUNER_XC2028=m +-CONFIG_MEDIA_TUNER_XC5000=m +-CONFIG_MEDIA_TUNER_MXL5005S=m +-CONFIG_MEDIA_TUNER_MXL5007T=m +-CONFIG_VIDEO_V4L2=m +-CONFIG_VIDEO_V4L1=m +-CONFIG_VIDEOBUF_GEN=m +-CONFIG_VIDEOBUF_VMALLOC=m +-CONFIG_VIDEOBUF_DMA_CONTIG=m +-CONFIG_VIDEO_CAPTURE_DRIVERS=y +-# CONFIG_VIDEO_ADV_DEBUG is not set +-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +-# CONFIG_VIDEO_VIVI is not set +-# CONFIG_VIDEO_BT848 is not set +-# CONFIG_VIDEO_PMS is not set +-# CONFIG_VIDEO_CPIA is not set +-# CONFIG_VIDEO_CPIA2 is not set +-# CONFIG_VIDEO_SAA5246A is not set +-# CONFIG_VIDEO_SAA5249 is not set +-# CONFIG_VIDEO_STRADIS is not set +-# CONFIG_VIDEO_SAA7134 is not set +-# CONFIG_VIDEO_MXB is not set +-# CONFIG_VIDEO_HEXIUM_ORION is not set +-# CONFIG_VIDEO_HEXIUM_GEMINI is not set +-# CONFIG_VIDEO_CX88 is not set +-# CONFIG_VIDEO_IVTV is not set +-# CONFIG_VIDEO_CAFE_CCIC is not set +-CONFIG_SOC_CAMERA=m +-CONFIG_SOC_CAMERA_MT9M001=m +-CONFIG_SOC_CAMERA_MT9M111=m +-CONFIG_SOC_CAMERA_MT9V022=m +-CONFIG_SOC_CAMERA_PLATFORM=m +-CONFIG_VIDEO_SH_MOBILE_CEU=m +-CONFIG_V4L_USB_DRIVERS=y +-CONFIG_USB_VIDEO_CLASS=m +-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +-CONFIG_USB_GSPCA=m +-CONFIG_USB_M5602=m +-CONFIG_USB_GSPCA_CONEX=m +-CONFIG_USB_GSPCA_ETOMS=m +-CONFIG_USB_GSPCA_FINEPIX=m +-CONFIG_USB_GSPCA_MARS=m +-CONFIG_USB_GSPCA_OV519=m +-CONFIG_USB_GSPCA_PAC207=m +-CONFIG_USB_GSPCA_PAC7311=m +-CONFIG_USB_GSPCA_SONIXB=m +-CONFIG_USB_GSPCA_SONIXJ=m +-CONFIG_USB_GSPCA_SPCA500=m +-CONFIG_USB_GSPCA_SPCA501=m +-CONFIG_USB_GSPCA_SPCA505=m +-CONFIG_USB_GSPCA_SPCA506=m +-CONFIG_USB_GSPCA_SPCA508=m +-CONFIG_USB_GSPCA_SPCA561=m +-CONFIG_USB_GSPCA_STK014=m +-CONFIG_USB_GSPCA_SUNPLUS=m +-CONFIG_USB_GSPCA_T613=m +-CONFIG_USB_GSPCA_TV8532=m +-CONFIG_USB_GSPCA_VC032X=m +-CONFIG_USB_GSPCA_ZC3XX=m +-# CONFIG_VIDEO_PVRUSB2 is not set +-# CONFIG_VIDEO_EM28XX is not set +-# CONFIG_VIDEO_USBVISION is not set +-CONFIG_VIDEO_USBVIDEO=m +-CONFIG_USB_VICAM=m +-CONFIG_USB_IBMCAM=m +-CONFIG_USB_KONICAWC=m +-CONFIG_USB_QUICKCAM_MESSENGER=m +-CONFIG_USB_ET61X251=m +-# CONFIG_VIDEO_OVCAMCHIP is not set +-CONFIG_USB_OV511=m +-CONFIG_USB_SE401=m +-CONFIG_USB_SN9C102=m +-CONFIG_USB_STV680=m +-CONFIG_USB_ZC0301=m +-CONFIG_USB_PWC=m +-# CONFIG_USB_PWC_DEBUG is not set +-# CONFIG_USB_ZR364XX is not set +-CONFIG_USB_STKWEBCAM=m +-CONFIG_USB_S2255=m +-CONFIG_RADIO_ADAPTERS=y +-# CONFIG_RADIO_CADET is not set +-# CONFIG_RADIO_RTRACK is not set +-# CONFIG_RADIO_RTRACK2 is not set +-# CONFIG_RADIO_AZTECH is not set +-# CONFIG_RADIO_GEMTEK is not set +-# CONFIG_RADIO_GEMTEK_PCI is not set +-# CONFIG_RADIO_MAXIRADIO is not set +-# CONFIG_RADIO_MAESTRO is not set +-# CONFIG_RADIO_SF16FMI is not set +-# CONFIG_RADIO_SF16FMR2 is not set +-# CONFIG_RADIO_TERRATEC is not set +-# CONFIG_RADIO_TRUST is not set +-# CONFIG_RADIO_TYPHOON is not set +-# CONFIG_RADIO_ZOLTRIX is not set +-# CONFIG_USB_DSBR is not set +-CONFIG_USB_SI470X=m +-CONFIG_USB_MR800=m +-CONFIG_DAB=y +-# CONFIG_USB_DABUSB is not set +- +-# +-# Graphics support +-# +-# CONFIG_DRM is not set +-# CONFIG_VGASTATE is not set +-CONFIG_VIDEO_OUTPUT_CONTROL=m +-CONFIG_FB=y +-# CONFIG_FIRMWARE_EDID is not set +-# CONFIG_FB_DDC is not set +-# CONFIG_FB_BOOT_VESA_SUPPORT is not set +-CONFIG_FB_CFB_FILLRECT=y +-CONFIG_FB_CFB_COPYAREA=y +-CONFIG_FB_CFB_IMAGEBLIT=y +-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +-# CONFIG_FB_SYS_FILLRECT is not set +-# CONFIG_FB_SYS_COPYAREA is not set +-# CONFIG_FB_SYS_IMAGEBLIT is not set +-# CONFIG_FB_FOREIGN_ENDIAN is not set +-# CONFIG_FB_SYS_FOPS is not set +-# CONFIG_FB_SVGALIB is not set +-# CONFIG_FB_MACMODES is not set +-CONFIG_FB_BACKLIGHT=y +-CONFIG_FB_MODE_HELPERS=y +-# CONFIG_FB_TILEBLITTING is not set +- +-# +-# Frame buffer hardware drivers +-# +-# CONFIG_FB_CIRRUS is not set +-# CONFIG_FB_PM2 is not set +-# CONFIG_FB_CYBER2000 is not set +-# CONFIG_FB_ASILIANT is not set +-# CONFIG_FB_IMSTT is not set +-# CONFIG_FB_S1D13XXX is not set +-# CONFIG_FB_NVIDIA is not set +-# CONFIG_FB_RIVA is not set +-# CONFIG_FB_MATROX is not set +-CONFIG_FB_RADEON=y +-# CONFIG_FB_RADEON_I2C is not set +-CONFIG_FB_RADEON_BACKLIGHT=y +-# CONFIG_FB_RADEON_DEBUG is not set +-# CONFIG_FB_ATY128 is not set +-# CONFIG_FB_ATY is not set +-# CONFIG_FB_S3 is not set +-# CONFIG_FB_SAVAGE is not set +-# CONFIG_FB_SIS is not set +-# CONFIG_FB_VIA is not set +-# CONFIG_FB_NEOMAGIC is not set +-# CONFIG_FB_KYRO is not set +-# CONFIG_FB_3DFX is not set +-# CONFIG_FB_VOODOO1 is not set +-# CONFIG_FB_VT8623 is not set +-# CONFIG_FB_TRIDENT is not set +-# CONFIG_FB_ARK is not set +-# CONFIG_FB_PM3 is not set +-# CONFIG_FB_CARMINE is not set +-# CONFIG_FB_VIRTUAL is not set +-# CONFIG_FB_METRONOME is not set +-# CONFIG_FB_MB862XX is not set +-CONFIG_BACKLIGHT_LCD_SUPPORT=y +-CONFIG_LCD_CLASS_DEVICE=m +-# CONFIG_LCD_ILI9320 is not set +-# CONFIG_LCD_PLATFORM is not set +-CONFIG_BACKLIGHT_CLASS_DEVICE=y +-# CONFIG_BACKLIGHT_CORGI is not set +- +-# +-# Display device support +-# +-# CONFIG_DISPLAY_SUPPORT is not set +- +-# +-# Console display driver support +-# +-# CONFIG_VGA_CONSOLE is not set +-# CONFIG_MDA_CONSOLE is not set +-CONFIG_DUMMY_CONSOLE=y +-CONFIG_FRAMEBUFFER_CONSOLE=y +-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +-# CONFIG_FONTS is not set +-CONFIG_FONT_8x8=y +-CONFIG_FONT_8x16=y +-# CONFIG_LOGO is not set +-CONFIG_SOUND=y +-CONFIG_SOUND_OSS_CORE=y +-CONFIG_SND=m +-CONFIG_SND_TIMER=m +-CONFIG_SND_PCM=m +-CONFIG_SND_RAWMIDI=m +-CONFIG_SND_SEQUENCER=m +-CONFIG_SND_SEQ_DUMMY=m +-CONFIG_SND_OSSEMUL=y +-CONFIG_SND_MIXER_OSS=m +-CONFIG_SND_PCM_OSS=m +-CONFIG_SND_PCM_OSS_PLUGINS=y +-CONFIG_SND_SEQUENCER_OSS=y +-# CONFIG_SND_DYNAMIC_MINORS is not set +-CONFIG_SND_SUPPORT_OLD_API=y +-CONFIG_SND_VERBOSE_PROCFS=y +-# CONFIG_SND_VERBOSE_PRINTK is not set +-# CONFIG_SND_DEBUG is not set +-CONFIG_SND_VMASTER=y +-CONFIG_SND_MPU401_UART=m +-CONFIG_SND_AC97_CODEC=m +-CONFIG_SND_DRIVERS=y +-# CONFIG_SND_DUMMY is not set +-# CONFIG_SND_VIRMIDI is not set +-# CONFIG_SND_MTPAV is not set +-# CONFIG_SND_SERIAL_U16550 is not set +-# CONFIG_SND_MPU401 is not set +-# CONFIG_SND_AC97_POWER_SAVE is not set +-CONFIG_SND_PCI=y +-# CONFIG_SND_AD1889 is not set +-# CONFIG_SND_ALS300 is not set +-# CONFIG_SND_ALI5451 is not set +-# CONFIG_SND_ATIIXP is not set +-# CONFIG_SND_ATIIXP_MODEM is not set +-# CONFIG_SND_AU8810 is not set +-# CONFIG_SND_AU8820 is not set +-# CONFIG_SND_AU8830 is not set +-# CONFIG_SND_AW2 is not set +-# CONFIG_SND_AZT3328 is not set +-# CONFIG_SND_BT87X is not set +-# CONFIG_SND_CA0106 is not set +-# CONFIG_SND_CMIPCI is not set +-# CONFIG_SND_OXYGEN is not set +-# CONFIG_SND_CS4281 is not set +-# CONFIG_SND_CS46XX is not set +-# CONFIG_SND_DARLA20 is not set +-# CONFIG_SND_GINA20 is not set +-# CONFIG_SND_LAYLA20 is not set +-# CONFIG_SND_DARLA24 is not set +-# CONFIG_SND_GINA24 is not set +-# CONFIG_SND_LAYLA24 is not set +-# CONFIG_SND_MONA is not set +-# CONFIG_SND_MIA is not set +-# CONFIG_SND_ECHO3G is not set +-# CONFIG_SND_INDIGO is not set +-# CONFIG_SND_INDIGOIO is not set +-# CONFIG_SND_INDIGODJ is not set +-# CONFIG_SND_EMU10K1 is not set +-# CONFIG_SND_EMU10K1X is not set +-# CONFIG_SND_ENS1370 is not set +-# CONFIG_SND_ENS1371 is not set +-# CONFIG_SND_ES1938 is not set +-# CONFIG_SND_ES1968 is not set +-# CONFIG_SND_FM801 is not set +-# CONFIG_SND_HDA_INTEL is not set +-# CONFIG_SND_HDSP is not set +-# CONFIG_SND_HDSPM is not set +-# CONFIG_SND_HIFIER is not set +-# CONFIG_SND_ICE1712 is not set +-# CONFIG_SND_ICE1724 is not set +-# CONFIG_SND_INTEL8X0 is not set +-# CONFIG_SND_INTEL8X0M is not set +-# CONFIG_SND_KORG1212 is not set +-# CONFIG_SND_MAESTRO3 is not set +-# CONFIG_SND_MIXART is not set +-# CONFIG_SND_NM256 is not set +-# CONFIG_SND_PCXHR is not set +-# CONFIG_SND_RIPTIDE is not set +-# CONFIG_SND_RME32 is not set +-# CONFIG_SND_RME96 is not set +-# CONFIG_SND_RME9652 is not set +-# CONFIG_SND_SONICVIBES is not set +-# CONFIG_SND_TRIDENT is not set +-CONFIG_SND_VIA82XX=m +-# CONFIG_SND_VIA82XX_MODEM is not set +-# CONFIG_SND_VIRTUOSO is not set +-# CONFIG_SND_VX222 is not set +-# CONFIG_SND_YMFPCI is not set +-CONFIG_SND_MIPS=y +-CONFIG_SND_USB=y +-# CONFIG_SND_USB_AUDIO is not set +-# CONFIG_SND_USB_CAIAQ is not set +-# CONFIG_SND_SOC is not set +-# CONFIG_SOUND_PRIME is not set +-CONFIG_AC97_BUS=m +-CONFIG_HID_SUPPORT=y +-CONFIG_HID=y +-# CONFIG_HID_DEBUG is not set +-CONFIG_HIDRAW=y +- +-# +-# USB Input Devices +-# +-CONFIG_USB_HID=m +-CONFIG_HID_PID=y +-CONFIG_USB_HIDDEV=y +- +-# +-# USB HID Boot Protocol drivers +-# +-# CONFIG_USB_KBD is not set +-# CONFIG_USB_MOUSE is not set +- +-# +-# Special HID drivers +-# +-CONFIG_HID_COMPAT=y +-CONFIG_HID_A4TECH=m +-CONFIG_HID_APPLE=m +-CONFIG_HID_BELKIN=m +-CONFIG_HID_BRIGHT=m +-CONFIG_HID_CHERRY=m +-CONFIG_HID_CHICONY=m +-CONFIG_HID_CYPRESS=m +-CONFIG_HID_DELL=m +-CONFIG_HID_EZKEY=m +-CONFIG_HID_GYRATION=m +-CONFIG_HID_LOGITECH=m +-CONFIG_LOGITECH_FF=y +-CONFIG_LOGIRUMBLEPAD2_FF=y +-CONFIG_HID_MICROSOFT=m +-CONFIG_HID_MONTEREY=m +-CONFIG_HID_PANTHERLORD=m +-# CONFIG_PANTHERLORD_FF is not set +-CONFIG_HID_PETALYNX=m +-CONFIG_HID_SAMSUNG=m +-CONFIG_HID_SONY=m +-CONFIG_HID_SUNPLUS=m +-# CONFIG_THRUSTMASTER_FF is not set +-CONFIG_ZEROPLUS_FF=m +-CONFIG_USB_SUPPORT=y +-CONFIG_USB_ARCH_HAS_HCD=y +-CONFIG_USB_ARCH_HAS_OHCI=y +-CONFIG_USB_ARCH_HAS_EHCI=y +-CONFIG_USB=y +-# CONFIG_USB_DEBUG is not set +-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +- +-# +-# Miscellaneous USB options +-# +-CONFIG_USB_DEVICEFS=y +-# CONFIG_USB_DEVICE_CLASS is not set +-# CONFIG_USB_DYNAMIC_MINORS is not set +-# CONFIG_USB_SUSPEND is not set +-# CONFIG_USB_OTG is not set +-CONFIG_USB_OTG_WHITELIST=y +-# CONFIG_USB_OTG_BLACKLIST_HUB is not set +-# CONFIG_USB_MON is not set +-# CONFIG_USB_WUSB is not set +-CONFIG_USB_WUSB_CBAF=m +-# CONFIG_USB_WUSB_CBAF_DEBUG is not set +- +-# +-# USB Host Controller Drivers +-# +-CONFIG_USB_C67X00_HCD=m +-CONFIG_USB_EHCI_HCD=y +-CONFIG_USB_EHCI_ROOT_HUB_TT=y +-CONFIG_USB_EHCI_TT_NEWSCHED=y +-# CONFIG_USB_ISP116X_HCD is not set +-CONFIG_USB_ISP1760_HCD=m +-CONFIG_USB_OHCI_HCD=y +-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +-CONFIG_USB_OHCI_LITTLE_ENDIAN=y +-CONFIG_USB_UHCI_HCD=m +-# CONFIG_USB_SL811_HCD is not set +-CONFIG_USB_R8A66597_HCD=m +-# CONFIG_USB_WHCI_HCD is not set +-# CONFIG_USB_HWA_HCD is not set +- +-# +-# USB Device Class drivers +-# +-CONFIG_USB_ACM=y +-CONFIG_USB_PRINTER=y +-CONFIG_USB_WDM=m +-CONFIG_USB_TMC=m +- +-# +-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +-# +- +-# +-# see USB_STORAGE Help for more information +-# +-CONFIG_USB_STORAGE=y +-# CONFIG_USB_STORAGE_DEBUG is not set +-# CONFIG_USB_STORAGE_DATAFAB is not set +-# CONFIG_USB_STORAGE_FREECOM is not set +-# CONFIG_USB_STORAGE_ISD200 is not set +-# CONFIG_USB_STORAGE_DPCM is not set +-# CONFIG_USB_STORAGE_USBAT is not set +-# CONFIG_USB_STORAGE_SDDR09 is not set +-# CONFIG_USB_STORAGE_SDDR55 is not set +-# CONFIG_USB_STORAGE_JUMPSHOT is not set +-# CONFIG_USB_STORAGE_ALAUDA is not set +-CONFIG_USB_STORAGE_ONETOUCH=y +-# CONFIG_USB_STORAGE_KARMA is not set +-CONFIG_USB_STORAGE_CYPRESS_ATACB=y +-CONFIG_USB_LIBUSUAL=y +- +-# +-# USB Imaging devices +-# +-# CONFIG_USB_MDC800 is not set +-# CONFIG_USB_MICROTEK is not set +- +-# +-# USB port drivers +-# +-# CONFIG_USB_SERIAL is not set +- +-# +-# USB Miscellaneous drivers +-# +-# CONFIG_USB_EMI62 is not set +-# CONFIG_USB_EMI26 is not set +-# CONFIG_USB_ADUTUX is not set +-CONFIG_USB_SEVSEG=m +-# CONFIG_USB_RIO500 is not set +-# CONFIG_USB_LEGOTOWER is not set +-# CONFIG_USB_LCD is not set +-# CONFIG_USB_BERRY_CHARGE is not set +-# CONFIG_USB_LED is not set +-# CONFIG_USB_CYPRESS_CY7C63 is not set +-# CONFIG_USB_CYTHERM is not set +-# CONFIG_USB_PHIDGET is not set +-# CONFIG_USB_IDMOUSE is not set +-# CONFIG_USB_FTDI_ELAN is not set +-# CONFIG_USB_APPLEDISPLAY is not set +-# CONFIG_USB_SISUSBVGA is not set +-# CONFIG_USB_LD is not set +-# CONFIG_USB_TRANCEVIBRATOR is not set +-# CONFIG_USB_IOWARRIOR is not set +-# CONFIG_USB_TEST is not set +-CONFIG_USB_ISIGHTFW=m +-CONFIG_USB_VST=m +-# CONFIG_USB_GADGET is not set +-# CONFIG_UWB is not set +-# CONFIG_MMC is not set +-# CONFIG_MEMSTICK is not set +-# CONFIG_NEW_LEDS is not set +-# CONFIG_ACCESSIBILITY is not set +-# CONFIG_INFINIBAND is not set +-CONFIG_RTC_LIB=y +-CONFIG_RTC_CLASS=m +- +-# +-# RTC interfaces +-# +-CONFIG_RTC_INTF_SYSFS=y +-CONFIG_RTC_INTF_PROC=y +-CONFIG_RTC_INTF_DEV=y +-CONFIG_RTC_INTF_DEV_UIE_EMUL=y +-# CONFIG_RTC_DRV_TEST is not set +- +-# +-# I2C RTC drivers +-# +-# CONFIG_RTC_DRV_DS1307 is not set +-# CONFIG_RTC_DRV_DS1374 is not set +-# CONFIG_RTC_DRV_DS1672 is not set +-# CONFIG_RTC_DRV_MAX6900 is not set +-# CONFIG_RTC_DRV_RS5C372 is not set +-# CONFIG_RTC_DRV_ISL1208 is not set +-# CONFIG_RTC_DRV_X1205 is not set +-# CONFIG_RTC_DRV_PCF8563 is not set +-# CONFIG_RTC_DRV_PCF8583 is not set +-# CONFIG_RTC_DRV_M41T80 is not set +-# CONFIG_RTC_DRV_S35390A is not set +-# CONFIG_RTC_DRV_FM3130 is not set +-# CONFIG_RTC_DRV_RX8581 is not set +- +-# +-# SPI RTC drivers +-# +- +-# +-# Platform RTC drivers +-# +-CONFIG_RTC_DRV_CMOS=m +-# CONFIG_RTC_DRV_DS1286 is not set +-# CONFIG_RTC_DRV_DS1511 is not set +-# CONFIG_RTC_DRV_DS1553 is not set +-# CONFIG_RTC_DRV_DS1742 is not set +-# CONFIG_RTC_DRV_STK17TA8 is not set +-# CONFIG_RTC_DRV_M48T86 is not set +-# CONFIG_RTC_DRV_M48T35 is not set +-# CONFIG_RTC_DRV_M48T59 is not set +-# CONFIG_RTC_DRV_BQ4802 is not set +-# CONFIG_RTC_DRV_V3020 is not set +- +-# +-# on-CPU RTC drivers +-# +-# CONFIG_DMADEVICES is not set +-CONFIG_UIO=m +-CONFIG_UIO_CIF=m +-# CONFIG_UIO_PDRV is not set +-# CONFIG_UIO_PDRV_GENIRQ is not set +-# CONFIG_UIO_SMX is not set +-# CONFIG_UIO_SERCOS3 is not set +-# CONFIG_STAGING is not set +-CONFIG_STAGING_EXCLUDE_BUILD=y +- +-# +-# File systems +-# +-CONFIG_EXT2_FS=y +-# CONFIG_EXT2_FS_XATTR is not set +-CONFIG_EXT2_FS_XIP=y +-CONFIG_EXT3_FS=y +-# CONFIG_EXT3_FS_XATTR is not set +-CONFIG_EXT4_FS=m +-CONFIG_EXT4DEV_COMPAT=y +-CONFIG_EXT4_FS_XATTR=y +-CONFIG_EXT4_FS_POSIX_ACL=y +-CONFIG_EXT4_FS_SECURITY=y +-CONFIG_FS_XIP=y +-CONFIG_JBD=y +-CONFIG_JBD2=m +-CONFIG_FS_MBCACHE=m +-CONFIG_REISERFS_FS=m +-# CONFIG_REISERFS_CHECK is not set +-# CONFIG_REISERFS_PROC_INFO is not set +-# CONFIG_REISERFS_FS_XATTR is not set +-# CONFIG_JFS_FS is not set +-CONFIG_FS_POSIX_ACL=y +-CONFIG_FILE_LOCKING=y +-# CONFIG_XFS_FS is not set +-# CONFIG_GFS2_FS is not set +-# CONFIG_OCFS2_FS is not set +-CONFIG_DNOTIFY=y +-CONFIG_INOTIFY=y +-CONFIG_INOTIFY_USER=y +-# CONFIG_QUOTA is not set +-CONFIG_AUTOFS_FS=y +-CONFIG_AUTOFS4_FS=y +-CONFIG_FUSE_FS=y +- +-# +-# CD-ROM/DVD Filesystems +-# +-CONFIG_ISO9660_FS=m +-CONFIG_JOLIET=y +-CONFIG_ZISOFS=y +-CONFIG_UDF_FS=m +-CONFIG_UDF_NLS=y +- +-# +-# DOS/FAT/NT Filesystems +-# +-CONFIG_FAT_FS=m +-CONFIG_MSDOS_FS=m +-CONFIG_VFAT_FS=m +-CONFIG_FAT_DEFAULT_CODEPAGE=936 +-CONFIG_FAT_DEFAULT_IOCHARSET="utf8" +-CONFIG_NTFS_FS=m +-# CONFIG_NTFS_DEBUG is not set +-CONFIG_NTFS_RW=y +- +-# +-# Pseudo filesystems +-# +-CONFIG_PROC_FS=y +-CONFIG_PROC_KCORE=y +-CONFIG_PROC_SYSCTL=y +-CONFIG_PROC_PAGE_MONITOR=y +-CONFIG_SYSFS=y +-CONFIG_TMPFS=y +-# CONFIG_TMPFS_POSIX_ACL is not set +-# CONFIG_HUGETLB_PAGE is not set +-# CONFIG_CONFIGFS_FS is not set +- +-# +-# Miscellaneous filesystems +-# +-# CONFIG_ADFS_FS is not set +-# CONFIG_AFFS_FS is not set +-# CONFIG_HFS_FS is not set +-# CONFIG_HFSPLUS_FS is not set +-# CONFIG_BEFS_FS is not set +-# CONFIG_BFS_FS is not set +-# CONFIG_EFS_FS is not set +-# CONFIG_JFFS2_FS is not set +-# CONFIG_CRAMFS is not set +-# CONFIG_VXFS_FS is not set +-# CONFIG_MINIX_FS is not set +-CONFIG_OMFS_FS=m +-# CONFIG_HPFS_FS is not set +-# CONFIG_QNX4FS_FS is not set +-# CONFIG_ROMFS_FS is not set +-# CONFIG_SYSV_FS is not set +-# CONFIG_UFS_FS is not set +-CONFIG_NETWORK_FILESYSTEMS=y +-CONFIG_NFS_FS=m +-CONFIG_NFS_V3=y +-CONFIG_NFS_V3_ACL=y +-CONFIG_NFS_V4=y +-CONFIG_NFSD=m +-CONFIG_NFSD_V2_ACL=y +-CONFIG_NFSD_V3=y +-CONFIG_NFSD_V3_ACL=y +-CONFIG_NFSD_V4=y +-CONFIG_LOCKD=m +-CONFIG_LOCKD_V4=y +-CONFIG_EXPORTFS=m +-CONFIG_NFS_ACL_SUPPORT=m +-CONFIG_NFS_COMMON=y +-CONFIG_SUNRPC=m +-CONFIG_SUNRPC_GSS=m +-# CONFIG_SUNRPC_REGISTER_V4 is not set +-CONFIG_RPCSEC_GSS_KRB5=m +-# CONFIG_RPCSEC_GSS_SPKM3 is not set +-CONFIG_SMB_FS=m +-CONFIG_SMB_NLS_DEFAULT=y +-CONFIG_SMB_NLS_REMOTE="cp936" +-CONFIG_CIFS=m +-CONFIG_CIFS_STATS=y +-CONFIG_CIFS_STATS2=y +-CONFIG_CIFS_WEAK_PW_HASH=y +-CONFIG_CIFS_XATTR=y +-CONFIG_CIFS_POSIX=y +-CONFIG_CIFS_DEBUG2=y +-CONFIG_CIFS_EXPERIMENTAL=y +-# CONFIG_NCP_FS is not set +-# CONFIG_CODA_FS is not set +-# CONFIG_AFS_FS is not set +-# CONFIG_9P_FS is not set +- +-# +-# Partition Types +-# +-CONFIG_PARTITION_ADVANCED=y +-# CONFIG_ACORN_PARTITION is not set +-# CONFIG_OSF_PARTITION is not set +-# CONFIG_AMIGA_PARTITION is not set +-# CONFIG_ATARI_PARTITION is not set +-# CONFIG_MAC_PARTITION is not set +-CONFIG_MSDOS_PARTITION=y +-# CONFIG_BSD_DISKLABEL is not set +-# CONFIG_MINIX_SUBPARTITION is not set +-# CONFIG_SOLARIS_X86_PARTITION is not set +-# CONFIG_UNIXWARE_DISKLABEL is not set +-# CONFIG_LDM_PARTITION is not set +-# CONFIG_SGI_PARTITION is not set +-# CONFIG_ULTRIX_PARTITION is not set +-# CONFIG_SUN_PARTITION is not set +-# CONFIG_KARMA_PARTITION is not set +-# CONFIG_EFI_PARTITION is not set +-# CONFIG_SYSV68_PARTITION is not set +-CONFIG_NLS=y +-CONFIG_NLS_DEFAULT="utf8" +-# CONFIG_NLS_CODEPAGE_437 is not set +-# CONFIG_NLS_CODEPAGE_737 is not set +-# CONFIG_NLS_CODEPAGE_775 is not set +-# CONFIG_NLS_CODEPAGE_850 is not set +-# CONFIG_NLS_CODEPAGE_852 is not set +-# CONFIG_NLS_CODEPAGE_855 is not set +-# CONFIG_NLS_CODEPAGE_857 is not set +-# CONFIG_NLS_CODEPAGE_860 is not set +-# CONFIG_NLS_CODEPAGE_861 is not set +-# CONFIG_NLS_CODEPAGE_862 is not set +-# CONFIG_NLS_CODEPAGE_863 is not set +-# CONFIG_NLS_CODEPAGE_864 is not set +-# CONFIG_NLS_CODEPAGE_865 is not set +-# CONFIG_NLS_CODEPAGE_866 is not set +-# CONFIG_NLS_CODEPAGE_869 is not set +-CONFIG_NLS_CODEPAGE_936=y +-# CONFIG_NLS_CODEPAGE_950 is not set +-# CONFIG_NLS_CODEPAGE_932 is not set +-# CONFIG_NLS_CODEPAGE_949 is not set +-# CONFIG_NLS_CODEPAGE_874 is not set +-# CONFIG_NLS_ISO8859_8 is not set +-# CONFIG_NLS_CODEPAGE_1250 is not set +-# CONFIG_NLS_CODEPAGE_1251 is not set +-# CONFIG_NLS_ASCII is not set +-CONFIG_NLS_ISO8859_1=y +-# CONFIG_NLS_ISO8859_2 is not set +-# CONFIG_NLS_ISO8859_3 is not set +-# CONFIG_NLS_ISO8859_4 is not set +-# CONFIG_NLS_ISO8859_5 is not set +-# CONFIG_NLS_ISO8859_6 is not set +-# CONFIG_NLS_ISO8859_7 is not set +-# CONFIG_NLS_ISO8859_9 is not set +-# CONFIG_NLS_ISO8859_13 is not set +-# CONFIG_NLS_ISO8859_14 is not set +-# CONFIG_NLS_ISO8859_15 is not set +-# CONFIG_NLS_KOI8_R is not set +-# CONFIG_NLS_KOI8_U is not set +-CONFIG_NLS_UTF8=y +-# CONFIG_DLM is not set +- +-# +-# Kernel hacking +-# +-CONFIG_TRACE_IRQFLAGS_SUPPORT=y +-# CONFIG_PRINTK_TIME is not set +-CONFIG_ENABLE_WARN_DEPRECATED=y +-# CONFIG_ENABLE_MUST_CHECK is not set +-CONFIG_FRAME_WARN=2048 +-# CONFIG_MAGIC_SYSRQ is not set +-# CONFIG_UNUSED_SYMBOLS is not set +-# CONFIG_DEBUG_FS is not set +-# CONFIG_HEADERS_CHECK is not set +-# CONFIG_DEBUG_KERNEL is not set +-# CONFIG_DEBUG_MEMORY_INIT is not set +-# CONFIG_RCU_CPU_STALL_DETECTOR is not set +-CONFIG_SYSCTL_SYSCALL_CHECK=y +- +-# +-# Tracers +-# +-CONFIG_DYNAMIC_PRINTK_DEBUG=y +-# CONFIG_SAMPLES is not set +-CONFIG_HAVE_ARCH_KGDB=y +-CONFIG_CMDLINE="" +- +-# +-# Security options +-# +-# CONFIG_KEYS is not set +-# CONFIG_SECURITY is not set +-# CONFIG_SECURITYFS is not set +-CONFIG_SECURITY_FILE_CAPABILITIES=y +-CONFIG_CRYPTO=y +- +-# +-# Crypto core or helper +-# +-CONFIG_CRYPTO_FIPS=y +-CONFIG_CRYPTO_ALGAPI=y +-CONFIG_CRYPTO_AEAD=y +-CONFIG_CRYPTO_BLKCIPHER=y +-CONFIG_CRYPTO_HASH=y +-CONFIG_CRYPTO_RNG=y +-CONFIG_CRYPTO_MANAGER=y +-CONFIG_CRYPTO_GF128MUL=m +-# CONFIG_CRYPTO_NULL is not set +-# CONFIG_CRYPTO_CRYPTD is not set +-CONFIG_CRYPTO_AUTHENC=m +-# CONFIG_CRYPTO_TEST is not set +- +-# +-# Authenticated Encryption with Associated Data +-# +-CONFIG_CRYPTO_CCM=m +-CONFIG_CRYPTO_GCM=m +-CONFIG_CRYPTO_SEQIV=m +- +-# +-# Block modes +-# +-CONFIG_CRYPTO_CBC=m +-CONFIG_CRYPTO_CTR=m +-CONFIG_CRYPTO_CTS=m +-CONFIG_CRYPTO_ECB=m +-# CONFIG_CRYPTO_LRW is not set +-CONFIG_CRYPTO_PCBC=m +-CONFIG_CRYPTO_XTS=m +- +-# +-# Hash modes +-# +-CONFIG_CRYPTO_HMAC=y +-# CONFIG_CRYPTO_XCBC is not set +- +-# +-# Digest +-# +-# CONFIG_CRYPTO_CRC32C is not set +-# CONFIG_CRYPTO_MD4 is not set +-CONFIG_CRYPTO_MD5=m +-# CONFIG_CRYPTO_MICHAEL_MIC is not set +-CONFIG_CRYPTO_RMD128=m +-CONFIG_CRYPTO_RMD160=m +-CONFIG_CRYPTO_RMD256=m +-CONFIG_CRYPTO_RMD320=m +-CONFIG_CRYPTO_SHA1=m +-# CONFIG_CRYPTO_SHA256 is not set +-# CONFIG_CRYPTO_SHA512 is not set +-# CONFIG_CRYPTO_TGR192 is not set +-# CONFIG_CRYPTO_WP512 is not set +- +-# +-# Ciphers +-# +-CONFIG_CRYPTO_AES=m +-# CONFIG_CRYPTO_ANUBIS is not set +-CONFIG_CRYPTO_ARC4=m +-# CONFIG_CRYPTO_BLOWFISH is not set +-# CONFIG_CRYPTO_CAMELLIA is not set +-# CONFIG_CRYPTO_CAST5 is not set +-# CONFIG_CRYPTO_CAST6 is not set +-CONFIG_CRYPTO_DES=m +-# CONFIG_CRYPTO_FCRYPT is not set +-# CONFIG_CRYPTO_KHAZAD is not set +-CONFIG_CRYPTO_SALSA20=m +-CONFIG_CRYPTO_SEED=m +-# CONFIG_CRYPTO_SERPENT is not set +-# CONFIG_CRYPTO_TEA is not set +-# CONFIG_CRYPTO_TWOFISH is not set +- +-# +-# Compression +-# +-CONFIG_CRYPTO_DEFLATE=m +-CONFIG_CRYPTO_LZO=m +- +-# +-# Random Number Generation +-# +-CONFIG_CRYPTO_ANSI_CPRNG=m +-# CONFIG_CRYPTO_HW is not set +- +-# +-# Library routines +-# +-CONFIG_BITREVERSE=y +-CONFIG_CRC_CCITT=y +-CONFIG_CRC16=m +-# CONFIG_CRC_T10DIF is not set +-CONFIG_CRC_ITU_T=m +-CONFIG_CRC32=y +-CONFIG_CRC7=m +-# CONFIG_LIBCRC32C is not set +-CONFIG_ZLIB_INFLATE=m +-CONFIG_ZLIB_DEFLATE=m +-CONFIG_LZO_COMPRESS=m +-CONFIG_LZO_DECOMPRESS=m +-CONFIG_TEXTSEARCH=y +-CONFIG_TEXTSEARCH_KMP=m +-CONFIG_TEXTSEARCH_BM=m +-CONFIG_TEXTSEARCH_FSM=m +-CONFIG_PLIST=y +-CONFIG_HAS_IOMEM=y +-CONFIG_HAS_IOPORT=y +-CONFIG_HAS_DMA=y +diff -Nur linux-2.6.30/arch/mips/configs/fuloong2e_defconfig rt4ls/arch/mips/configs/fuloong2e_defconfig +--- linux-2.6.30/arch/mips/configs/fuloong2e_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/configs/fuloong2e_defconfig 2009-06-12 16:27:08.246405134 +0200 +@@ -0,0 +1,2018 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.30-rc8 ++# Thu Jun 11 01:50:35 2009 ++# ++CONFIG_MIPS=y ++ ++# ++# Machine selection ++# ++# CONFIG_MACH_ALCHEMY is not set ++# CONFIG_BASLER_EXCITE is not set ++# CONFIG_BCM47XX is not set ++# CONFIG_MIPS_COBALT is not set ++# CONFIG_MACH_DECSTATION is not set ++# CONFIG_MACH_JAZZ is not set ++# CONFIG_LASAT is not set ++CONFIG_MACH_LOONGSON=y ++# CONFIG_MIPS_MALTA is not set ++# CONFIG_MIPS_SIM is not set ++# CONFIG_NEC_MARKEINS is not set ++# CONFIG_MACH_VR41XX is not set ++# CONFIG_NXP_STB220 is not set ++# CONFIG_NXP_STB225 is not set ++# CONFIG_PNX8550_JBS is not set ++# CONFIG_PNX8550_STB810 is not set ++# CONFIG_PMC_MSP is not set ++# CONFIG_PMC_YOSEMITE is not set ++# CONFIG_SGI_IP22 is not set ++# CONFIG_SGI_IP27 is not set ++# CONFIG_SGI_IP28 is not set ++# CONFIG_SGI_IP32 is not set ++# CONFIG_SIBYTE_CRHINE is not set ++# CONFIG_SIBYTE_CARMEL is not set ++# CONFIG_SIBYTE_CRHONE is not set ++# CONFIG_SIBYTE_RHONE is not set ++# CONFIG_SIBYTE_SWARM is not set ++# CONFIG_SIBYTE_LITTLESUR is not set ++# CONFIG_SIBYTE_SENTOSA is not set ++# CONFIG_SIBYTE_BIGSUR is not set ++# CONFIG_SNI_RM is not set ++# CONFIG_MACH_TX39XX is not set ++# CONFIG_MACH_TX49XX is not set ++# CONFIG_MIKROTIK_RB532 is not set ++# CONFIG_WR_PPMC is not set ++# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set ++# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set ++CONFIG_ARCH_SPARSEMEM_ENABLE=y ++CONFIG_LEMOTE_FULOONG2E=y ++# CONFIG_LEMOTE_FULOONG2F is not set ++# CONFIG_LEMOTE_YEELOONG2F is not set ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_ARCH_SUPPORTS_OPROFILE=y ++CONFIG_GENERIC_FIND_NEXT_BIT=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CMOS_UPDATE=y ++CONFIG_SCHED_OMIT_FRAME_POINTER=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_CEVT_R4K_LIB=y ++CONFIG_CEVT_R4K=y ++CONFIG_CSRC_R4K_LIB=y ++CONFIG_CSRC_R4K=y ++CONFIG_DMA_NONCOHERENT=y ++CONFIG_DMA_NEED_PCI_MAP_STATE=y ++CONFIG_EARLY_PRINTK=y ++CONFIG_SYS_HAS_EARLY_PRINTK=y ++# CONFIG_HOTPLUG_CPU is not set ++CONFIG_I8259=y ++# CONFIG_NO_IOPORT is not set ++CONFIG_GENERIC_ISA_DMA=y ++CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y ++# CONFIG_CPU_BIG_ENDIAN is not set ++CONFIG_CPU_LITTLE_ENDIAN=y ++CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y ++CONFIG_IRQ_CPU=y ++CONFIG_BOOT_ELF32=y ++CONFIG_MIPS_L1_CACHE_SHIFT=5 ++ ++# ++# CPU selection ++# ++CONFIG_CPU_LOONGSON2E=y ++# CONFIG_CPU_LOONGSON2F is not set ++# CONFIG_CPU_MIPS32_R1 is not set ++# CONFIG_CPU_MIPS32_R2 is not set ++# CONFIG_CPU_MIPS64_R1 is not set ++# CONFIG_CPU_MIPS64_R2 is not set ++# CONFIG_CPU_R3000 is not set ++# CONFIG_CPU_TX39XX is not set ++# CONFIG_CPU_VR41XX is not set ++# CONFIG_CPU_R4300 is not set ++# CONFIG_CPU_R4X00 is not set ++# CONFIG_CPU_TX49XX is not set ++# CONFIG_CPU_R5000 is not set ++# CONFIG_CPU_R5432 is not set ++# CONFIG_CPU_R5500 is not set ++# CONFIG_CPU_R6000 is not set ++# CONFIG_CPU_NEVADA is not set ++# CONFIG_CPU_R8000 is not set ++# CONFIG_CPU_R10000 is not set ++# CONFIG_CPU_RM7000 is not set ++# CONFIG_CPU_RM9000 is not set ++# CONFIG_CPU_SB1 is not set ++# CONFIG_CPU_CAVIUM_OCTEON is not set ++CONFIG_CPU_LOONGSON2=y ++CONFIG_SYS_HAS_CPU_LOONGSON2E=y ++CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y ++CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y ++CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y ++CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y ++ ++# ++# Kernel type ++# ++# CONFIG_32BIT is not set ++CONFIG_64BIT=y ++# CONFIG_PAGE_SIZE_4KB is not set ++# CONFIG_PAGE_SIZE_8KB is not set ++CONFIG_PAGE_SIZE_16KB=y ++# CONFIG_PAGE_SIZE_32KB is not set ++# CONFIG_PAGE_SIZE_64KB is not set ++CONFIG_BOARD_SCACHE=y ++CONFIG_MIPS_MT_DISABLED=y ++# CONFIG_MIPS_MT_SMP is not set ++# CONFIG_MIPS_MT_SMTC is not set ++CONFIG_CPU_HAS_WB=y ++CONFIG_CPU_HAS_SYNC=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_CPU_SUPPORTS_HIGHMEM=y ++CONFIG_SYS_SUPPORTS_HIGHMEM=y ++CONFIG_ARCH_FLATMEM_ENABLE=y ++CONFIG_ARCH_POPULATES_NODE_MAP=y ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_SPARSEMEM_STATIC=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_PHYS_ADDR_T_64BIT=y ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++CONFIG_HAVE_MLOCK=y ++CONFIG_HAVE_MLOCKED_PAGE_BIT=y ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++# CONFIG_HZ_48 is not set ++# CONFIG_HZ_100 is not set ++# CONFIG_HZ_128 is not set ++CONFIG_HZ_250=y ++# CONFIG_HZ_256 is not set ++# CONFIG_HZ_1000 is not set ++# CONFIG_HZ_1024 is not set ++CONFIG_SYS_SUPPORTS_ARBIT_HZ=y ++CONFIG_HZ=250 ++# CONFIG_PREEMPT_NONE is not set ++CONFIG_PREEMPT_VOLUNTARY=y ++# CONFIG_PREEMPT is not set ++# CONFIG_KEXEC is not set ++CONFIG_SECCOMP=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="-loongson2e" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++CONFIG_BSD_PROCESS_ACCT=y ++# CONFIG_BSD_PROCESS_ACCT_V3 is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=14 ++# CONFIG_GROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++CONFIG_USER_NS=y ++CONFIG_PID_NS=y ++# CONFIG_NET_NS is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_EMBEDDED=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++# CONFIG_STRIP_ASM_SYMS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_PCSPKR_PLATFORM is not set ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_PCI_QUIRKS=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++CONFIG_PROFILING=y ++CONFIG_TRACEPOINTS=y ++# CONFIG_MARKERS is not set ++CONFIG_OPROFILE=m ++CONFIG_HAVE_OPROFILE=y ++CONFIG_HAVE_SYSCALL_WRAPPERS=y ++# CONFIG_SLOW_WORK is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_INTEGRITY is not set ++CONFIG_BLOCK_COMPAT=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_FREEZER=y ++ ++# ++# Bus options (PCI, PCMCIA, EISA, ISA, TC) ++# ++CONFIG_HW_HAS_PCI=y ++CONFIG_PCI=y ++CONFIG_PCI_DOMAINS=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++CONFIG_PCI_LEGACY=y ++# CONFIG_PCI_STUB is not set ++# CONFIG_PCI_IOV is not set ++CONFIG_ISA=y ++CONFIG_MMU=y ++# CONFIG_PCCARD is not set ++# CONFIG_HOTPLUG_PCI is not set ++ ++# ++# Executable file formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++# CONFIG_HAVE_AOUT is not set ++CONFIG_BINFMT_MISC=y ++CONFIG_MIPS32_COMPAT=y ++CONFIG_COMPAT=y ++CONFIG_SYSVIPC_COMPAT=y ++CONFIG_MIPS32_O32=y ++CONFIG_MIPS32_N32=y ++CONFIG_BINFMT_ELF32=y ++ ++# ++# Power management options ++# ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_SLEEP=y ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++CONFIG_HIBERNATION=y ++CONFIG_PM_STD_PARTITION="" ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++CONFIG_IP_PNP_BOOTP=y ++# CONFIG_IP_PNP_RARP is not set ++CONFIG_NET_IPIP=m ++CONFIG_NET_IPGRE=m ++CONFIG_NET_IPGRE_BROADCAST=y ++# CONFIG_IP_MROUTE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++CONFIG_INET_TUNNEL=m ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++CONFIG_INET_XFRM_MODE_BEET=y ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++CONFIG_NETFILTER=y ++# CONFIG_NETFILTER_DEBUG is not set ++CONFIG_NETFILTER_ADVANCED=y ++ ++# ++# Core Netfilter Configuration ++# ++CONFIG_NETFILTER_NETLINK=m ++CONFIG_NETFILTER_NETLINK_QUEUE=m ++CONFIG_NETFILTER_NETLINK_LOG=m ++# CONFIG_NF_CONNTRACK is not set ++# CONFIG_NETFILTER_TPROXY is not set ++CONFIG_NETFILTER_XTABLES=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++# CONFIG_NETFILTER_XT_TARGET_DSCP is not set ++CONFIG_NETFILTER_XT_TARGET_HL=m ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++CONFIG_NETFILTER_XT_TARGET_RATEEST=m ++CONFIG_NETFILTER_XT_TARGET_TRACE=m ++# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set ++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_DCCP=m ++# CONFIG_NETFILTER_XT_MATCH_DSCP is not set ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set ++CONFIG_NETFILTER_XT_MATCH_HL=m ++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++CONFIG_NETFILTER_XT_MATCH_OWNER=m ++# CONFIG_NETFILTER_XT_MATCH_POLICY is not set ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++CONFIG_NETFILTER_XT_MATCH_RATEEST=m ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++CONFIG_NETFILTER_XT_MATCH_RECENT=m ++# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set ++CONFIG_NETFILTER_XT_MATCH_SCTP=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++CONFIG_NETFILTER_XT_MATCH_TIME=m ++CONFIG_NETFILTER_XT_MATCH_U32=m ++# CONFIG_IP_VS is not set ++ ++# ++# IP: Netfilter Configuration ++# ++# CONFIG_NF_DEFRAG_IPV4 is not set ++CONFIG_IP_NF_QUEUE=m ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_ADDRTYPE=m ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_TARGET_LOG=m ++CONFIG_IP_NF_TARGET_ULOG=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++CONFIG_PHONET=m ++# CONFIG_NET_SCHED is not set ++CONFIG_NET_CLS_ROUTE=y ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_NET_DROP_MONITOR is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++CONFIG_WIRELESS_OLD_REGULATORY=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WIRELESS_EXT_SYSFS=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++CONFIG_NET_9P=m ++# CONFIG_NET_9P_DEBUG is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=m ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=m ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++# CONFIG_MTD_PARTITIONS is not set ++# CONFIG_MTD_TESTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=m ++CONFIG_MTD_BLKDEVS=m ++CONFIG_MTD_BLOCK=m ++# CONFIG_MTD_BLOCK_RO is not set ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=m ++CONFIG_MTD_JEDECPROBE=m ++CONFIG_MTD_GEN_PROBE=m ++CONFIG_MTD_CFI_ADV_OPTIONS=y ++CONFIG_MTD_CFI_NOSWAP=y ++# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set ++# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set ++# CONFIG_MTD_CFI_GEOMETRY is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_OTP is not set ++# CONFIG_MTD_CFI_INTELEXT is not set ++CONFIG_MTD_CFI_AMDSTD=m ++CONFIG_MTD_CFI_STAA=m ++CONFIG_MTD_CFI_UTIL=m ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP=m ++# CONFIG_MTD_PHYSMAP_COMPAT is not set ++# CONFIG_MTD_INTEL_VR_NOR is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_PMC551 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++# CONFIG_MTD_NAND is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++# CONFIG_PNP is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_CPQ_DA is not set ++# CONFIG_BLK_CPQ_CISS_DA is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_CRYPTOLOOP=m ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=m ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=4096 ++# CONFIG_BLK_DEV_XIP is not set ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_CDROM_PKTCDVD_BUFFERS=8 ++# CONFIG_CDROM_PKTCDVD_WCACHE is not set ++CONFIG_ATA_OVER_ETH=m ++# CONFIG_BLK_DEV_HD is not set ++# CONFIG_MISC_DEVICES is not set ++CONFIG_HAVE_IDE=y ++CONFIG_IDE=y ++ ++# ++# Please see Documentation/ide/ide.txt for help/info on IDE drives ++# ++CONFIG_IDE_XFER_MODE=y ++CONFIG_IDE_TIMINGS=y ++CONFIG_IDE_ATAPI=y ++# CONFIG_BLK_DEV_IDE_SATA is not set ++CONFIG_IDE_GD=y ++CONFIG_IDE_GD_ATA=y ++# CONFIG_IDE_GD_ATAPI is not set ++CONFIG_BLK_DEV_IDECD=y ++CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y ++# CONFIG_BLK_DEV_IDETAPE is not set ++CONFIG_IDE_TASK_IOCTL=y ++CONFIG_IDE_PROC_FS=y ++ ++# ++# IDE chipset support/bugfixes ++# ++CONFIG_IDE_GENERIC=y ++# CONFIG_BLK_DEV_PLATFORM is not set ++CONFIG_BLK_DEV_IDEDMA_SFF=y ++ ++# ++# PCI IDE chipsets support ++# ++CONFIG_BLK_DEV_IDEPCI=y ++CONFIG_IDEPCI_PCIBUS_ORDER=y ++# CONFIG_BLK_DEV_OFFBOARD is not set ++CONFIG_BLK_DEV_GENERIC=y ++# CONFIG_BLK_DEV_OPTI621 is not set ++CONFIG_BLK_DEV_IDEDMA_PCI=y ++# CONFIG_BLK_DEV_AEC62XX is not set ++# CONFIG_BLK_DEV_ALI15X3 is not set ++# CONFIG_BLK_DEV_AMD74XX is not set ++# CONFIG_BLK_DEV_CMD64X is not set ++# CONFIG_BLK_DEV_TRIFLEX is not set ++# CONFIG_BLK_DEV_CS5520 is not set ++# CONFIG_BLK_DEV_CS5530 is not set ++# CONFIG_BLK_DEV_HPT366 is not set ++# CONFIG_BLK_DEV_JMICRON is not set ++# CONFIG_BLK_DEV_SC1200 is not set ++# CONFIG_BLK_DEV_PIIX is not set ++# CONFIG_BLK_DEV_IT8172 is not set ++# CONFIG_BLK_DEV_IT8213 is not set ++# CONFIG_BLK_DEV_IT821X is not set ++# CONFIG_BLK_DEV_NS87415 is not set ++# CONFIG_BLK_DEV_PDC202XX_OLD is not set ++# CONFIG_BLK_DEV_PDC202XX_NEW is not set ++# CONFIG_BLK_DEV_SVWKS is not set ++# CONFIG_BLK_DEV_SIIMAGE is not set ++# CONFIG_BLK_DEV_SLC90E66 is not set ++# CONFIG_BLK_DEV_TRM290 is not set ++CONFIG_BLK_DEV_VIA82CXXX=y ++# CONFIG_BLK_DEV_TC86C001 is not set ++ ++# ++# Other IDE chipsets support ++# ++ ++# ++# Note: most of these also require special kernel boot parameters ++# ++# CONFIG_BLK_DEV_4DRIVES is not set ++# CONFIG_BLK_DEV_ALI14XX is not set ++# CONFIG_BLK_DEV_DTC2278 is not set ++# CONFIG_BLK_DEV_HT6560B is not set ++# CONFIG_BLK_DEV_QD65XX is not set ++# CONFIG_BLK_DEV_UMC8672 is not set ++CONFIG_BLK_DEV_IDEDMA=y ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++CONFIG_BLK_DEV_SR=y ++CONFIG_BLK_DEV_SR_VENDOR=y ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++CONFIG_SCSI_CONSTANTS=y ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++ ++# ++# Enable only one of the two stacks, unless you know what you are doing ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_IEEE1394 is not set ++# CONFIG_I2O is not set ++CONFIG_NETDEVICES=y ++CONFIG_COMPAT_NET_DEV_OPS=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++CONFIG_MACVLAN=m ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++CONFIG_VETH=m ++# CONFIG_ARCNET is not set ++CONFIG_PHYLIB=m ++ ++# ++# MII PHY device drivers ++# ++CONFIG_MARVELL_PHY=m ++CONFIG_DAVICOM_PHY=m ++CONFIG_QSEMI_PHY=m ++CONFIG_LXT_PHY=m ++CONFIG_CICADA_PHY=m ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_HAPPYMEAL is not set ++# CONFIG_SUNGEM is not set ++# CONFIG_CASSINI is not set ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_NET_VENDOR_SMC is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_ETHOC is not set ++# CONFIG_NET_VENDOR_RACAL is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_TULIP is not set ++# CONFIG_AT1700 is not set ++# CONFIG_DEPCA is not set ++# CONFIG_HP100 is not set ++# CONFIG_NET_ISA is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++CONFIG_NET_PCI=y ++# CONFIG_PCNET32 is not set ++# CONFIG_AMD8111_ETH is not set ++# CONFIG_ADAPTEC_STARFIRE is not set ++# CONFIG_AC3200 is not set ++# CONFIG_APRICOT is not set ++# CONFIG_B44 is not set ++# CONFIG_FORCEDETH is not set ++# CONFIG_CS89x0 is not set ++# CONFIG_TC35815 is not set ++# CONFIG_E100 is not set ++# CONFIG_FEALNX is not set ++# CONFIG_NATSEMI is not set ++# CONFIG_NE2K_PCI is not set ++# CONFIG_8139CP is not set ++CONFIG_8139TOO=y ++# CONFIG_8139TOO_PIO is not set ++# CONFIG_8139TOO_TUNE_TWISTER is not set ++# CONFIG_8139TOO_8129 is not set ++# CONFIG_8139_OLD_RX_RESET is not set ++# CONFIG_R6040 is not set ++# CONFIG_SIS900 is not set ++# CONFIG_EPIC100 is not set ++# CONFIG_SMSC9420 is not set ++# CONFIG_SUNDANCE is not set ++# CONFIG_TLAN is not set ++# CONFIG_VIA_RHINE is not set ++# CONFIG_SC92031 is not set ++# CONFIG_ATL2 is not set ++CONFIG_NETDEV_1000=y ++# CONFIG_ACENIC is not set ++# CONFIG_DL2K is not set ++# CONFIG_E1000 is not set ++# CONFIG_E1000E is not set ++# CONFIG_IP1000 is not set ++# CONFIG_IGB is not set ++# CONFIG_IGBVF is not set ++# CONFIG_NS83820 is not set ++# CONFIG_HAMACHI is not set ++# CONFIG_YELLOWFIN is not set ++# CONFIG_R8169 is not set ++# CONFIG_SIS190 is not set ++# CONFIG_SKGE is not set ++# CONFIG_SKY2 is not set ++# CONFIG_VIA_VELOCITY is not set ++# CONFIG_TIGON3 is not set ++# CONFIG_BNX2 is not set ++# CONFIG_QLA3XXX is not set ++# CONFIG_ATL1 is not set ++# CONFIG_ATL1E is not set ++# CONFIG_ATL1C is not set ++# CONFIG_JME is not set ++CONFIG_NETDEV_10000=y ++# CONFIG_CHELSIO_T1 is not set ++CONFIG_CHELSIO_T3_DEPENDS=y ++# CONFIG_CHELSIO_T3 is not set ++# CONFIG_ENIC is not set ++# CONFIG_IXGBE is not set ++# CONFIG_IXGB is not set ++# CONFIG_S2IO is not set ++# CONFIG_VXGE is not set ++# CONFIG_MYRI10GE is not set ++# CONFIG_NETXEN_NIC is not set ++# CONFIG_NIU is not set ++# CONFIG_MLX4_EN is not set ++# CONFIG_MLX4_CORE is not set ++# CONFIG_TEHUTI is not set ++# CONFIG_BNX2X is not set ++# CONFIG_QLGE is not set ++# CONFIG_SFC is not set ++# CONFIG_BE2NET is not set ++# CONFIG_TR is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++CONFIG_PPP=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_MPPE=m ++CONFIG_PPPOE=m ++CONFIG_PPPOL2TP=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_SLHC=m ++CONFIG_SLIP_SMART=y ++CONFIG_SLIP_MODE_SLIP6=y ++CONFIG_NET_FC=y ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++CONFIG_INPUT_FF_MEMLESS=y ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=m ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_SERIAL=y ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_INPORT is not set ++# CONFIG_MOUSE_LOGIBM is not set ++# CONFIG_MOUSE_PC110PAD is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_I8042=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_PCIPS2 is not set ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_NOZOMI is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++CONFIG_SERIAL_8250_CONSOLE=y ++CONFIG_SERIAL_8250_PCI=y ++CONFIG_SERIAL_8250_NR_UARTS=2 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=2 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set ++# CONFIG_DTLK is not set ++# CONFIG_R3964 is not set ++# CONFIG_APPLICOM is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_DEVPORT=y ++CONFIG_I2C=m ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=m ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++CONFIG_I2C_VIAPRO=m ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Graphics adapter I2C/DDC channel drivers ++# ++# CONFIG_I2C_VOODOO3 is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_ELEKTOR is not set ++# CONFIG_I2C_PCA_ISA is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++CONFIG_VIDEO_DEV=m ++CONFIG_VIDEO_V4L2_COMMON=m ++CONFIG_VIDEO_ALLOW_V4L1=y ++CONFIG_VIDEO_V4L1_COMPAT=y ++# CONFIG_DVB_CORE is not set ++CONFIG_VIDEO_MEDIA=m ++ ++# ++# Multimedia drivers ++# ++CONFIG_MEDIA_ATTACH=y ++CONFIG_MEDIA_TUNER=m ++# CONFIG_MEDIA_TUNER_CUSTOMISE is not set ++CONFIG_MEDIA_TUNER_SIMPLE=m ++CONFIG_MEDIA_TUNER_TDA8290=m ++CONFIG_MEDIA_TUNER_TDA9887=m ++CONFIG_MEDIA_TUNER_TEA5761=m ++CONFIG_MEDIA_TUNER_TEA5767=m ++CONFIG_MEDIA_TUNER_MT20XX=m ++CONFIG_MEDIA_TUNER_XC2028=m ++CONFIG_MEDIA_TUNER_XC5000=m ++CONFIG_MEDIA_TUNER_MC44S803=m ++CONFIG_VIDEO_V4L2=m ++CONFIG_VIDEO_V4L1=m ++CONFIG_VIDEOBUF_GEN=m ++CONFIG_VIDEOBUF_VMALLOC=m ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEO_HELPER_CHIPS_AUTO=y ++# CONFIG_VIDEO_VIVI is not set ++# CONFIG_VIDEO_BT848 is not set ++# CONFIG_VIDEO_PMS is not set ++# CONFIG_VIDEO_CPIA is not set ++# CONFIG_VIDEO_CPIA2 is not set ++# CONFIG_VIDEO_SAA5246A is not set ++# CONFIG_VIDEO_SAA5249 is not set ++# CONFIG_VIDEO_STRADIS is not set ++# CONFIG_VIDEO_SAA7134 is not set ++# CONFIG_VIDEO_MXB is not set ++# CONFIG_VIDEO_HEXIUM_ORION is not set ++# CONFIG_VIDEO_HEXIUM_GEMINI is not set ++# CONFIG_VIDEO_CX88 is not set ++# CONFIG_VIDEO_IVTV is not set ++# CONFIG_VIDEO_CAFE_CCIC is not set ++CONFIG_SOC_CAMERA=m ++CONFIG_SOC_CAMERA_MT9M001=m ++CONFIG_SOC_CAMERA_MT9M111=m ++# CONFIG_SOC_CAMERA_MT9T031 is not set ++CONFIG_SOC_CAMERA_MT9V022=m ++# CONFIG_SOC_CAMERA_TW9910 is not set ++CONFIG_SOC_CAMERA_PLATFORM=m ++# CONFIG_SOC_CAMERA_OV772X is not set ++CONFIG_V4L_USB_DRIVERS=y ++CONFIG_USB_VIDEO_CLASS=m ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++CONFIG_USB_GSPCA=m ++CONFIG_USB_M5602=m ++# CONFIG_USB_STV06XX is not set ++CONFIG_USB_GSPCA_CONEX=m ++CONFIG_USB_GSPCA_ETOMS=m ++CONFIG_USB_GSPCA_FINEPIX=m ++CONFIG_USB_GSPCA_MARS=m ++# CONFIG_USB_GSPCA_MR97310A is not set ++CONFIG_USB_GSPCA_OV519=m ++# CONFIG_USB_GSPCA_OV534 is not set ++CONFIG_USB_GSPCA_PAC207=m ++CONFIG_USB_GSPCA_PAC7311=m ++CONFIG_USB_GSPCA_SONIXB=m ++CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA500=m ++CONFIG_USB_GSPCA_SPCA501=m ++CONFIG_USB_GSPCA_SPCA505=m ++CONFIG_USB_GSPCA_SPCA506=m ++CONFIG_USB_GSPCA_SPCA508=m ++CONFIG_USB_GSPCA_SPCA561=m ++# CONFIG_USB_GSPCA_SQ905 is not set ++# CONFIG_USB_GSPCA_SQ905C is not set ++CONFIG_USB_GSPCA_STK014=m ++CONFIG_USB_GSPCA_SUNPLUS=m ++CONFIG_USB_GSPCA_T613=m ++CONFIG_USB_GSPCA_TV8532=m ++CONFIG_USB_GSPCA_VC032X=m ++CONFIG_USB_GSPCA_ZC3XX=m ++# CONFIG_VIDEO_PVRUSB2 is not set ++# CONFIG_VIDEO_HDPVR is not set ++# CONFIG_VIDEO_EM28XX is not set ++# CONFIG_VIDEO_CX231XX is not set ++# CONFIG_VIDEO_USBVISION is not set ++CONFIG_VIDEO_USBVIDEO=m ++CONFIG_USB_VICAM=m ++CONFIG_USB_IBMCAM=m ++CONFIG_USB_KONICAWC=m ++CONFIG_USB_QUICKCAM_MESSENGER=m ++CONFIG_USB_ET61X251=m ++# CONFIG_VIDEO_OVCAMCHIP is not set ++CONFIG_USB_OV511=m ++CONFIG_USB_SE401=m ++CONFIG_USB_SN9C102=m ++CONFIG_USB_STV680=m ++CONFIG_USB_ZC0301=m ++CONFIG_USB_PWC=m ++# CONFIG_USB_PWC_DEBUG is not set ++CONFIG_USB_PWC_INPUT_EVDEV=y ++# CONFIG_USB_ZR364XX is not set ++CONFIG_USB_STKWEBCAM=m ++CONFIG_USB_S2255=m ++CONFIG_RADIO_ADAPTERS=y ++# CONFIG_RADIO_CADET is not set ++# CONFIG_RADIO_RTRACK is not set ++# CONFIG_RADIO_RTRACK2 is not set ++# CONFIG_RADIO_AZTECH is not set ++# CONFIG_RADIO_GEMTEK is not set ++# CONFIG_RADIO_GEMTEK_PCI is not set ++# CONFIG_RADIO_MAXIRADIO is not set ++# CONFIG_RADIO_MAESTRO is not set ++# CONFIG_RADIO_SF16FMI is not set ++# CONFIG_RADIO_SF16FMR2 is not set ++# CONFIG_RADIO_TERRATEC is not set ++# CONFIG_RADIO_TRUST is not set ++# CONFIG_RADIO_TYPHOON is not set ++# CONFIG_RADIO_ZOLTRIX is not set ++# CONFIG_USB_DSBR is not set ++CONFIG_USB_SI470X=m ++CONFIG_USB_MR800=m ++# CONFIG_RADIO_TEA5764 is not set ++CONFIG_DAB=y ++# CONFIG_USB_DABUSB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++# CONFIG_VGASTATE is not set ++CONFIG_VIDEO_OUTPUT_CONTROL=m ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++CONFIG_FB_BACKLIGHT=y ++CONFIG_FB_MODE_HELPERS=y ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_CIRRUS is not set ++# CONFIG_FB_PM2 is not set ++# CONFIG_FB_CYBER2000 is not set ++# CONFIG_FB_ASILIANT is not set ++# CONFIG_FB_IMSTT is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_NVIDIA is not set ++# CONFIG_FB_RIVA is not set ++# CONFIG_FB_MATROX is not set ++CONFIG_FB_RADEON=y ++# CONFIG_FB_RADEON_I2C is not set ++CONFIG_FB_RADEON_BACKLIGHT=y ++# CONFIG_FB_RADEON_DEBUG is not set ++# CONFIG_FB_ATY128 is not set ++# CONFIG_FB_ATY is not set ++# CONFIG_FB_S3 is not set ++# CONFIG_FB_SAVAGE is not set ++# CONFIG_FB_SIS is not set ++# CONFIG_FB_VIA is not set ++# CONFIG_FB_NEOMAGIC is not set ++# CONFIG_FB_KYRO is not set ++# CONFIG_FB_3DFX is not set ++# CONFIG_FB_VOODOO1 is not set ++# CONFIG_FB_VT8623 is not set ++# CONFIG_FB_TRIDENT is not set ++# CONFIG_FB_ARK is not set ++# CONFIG_FB_PM3 is not set ++# CONFIG_FB_CARMINE is not set ++# CONFIG_FB_SM7XX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_FB_BROADSHEET is not set ++CONFIG_BACKLIGHT_LCD_SUPPORT=y ++CONFIG_LCD_CLASS_DEVICE=m ++# CONFIG_LCD_ILI9320 is not set ++# CONFIG_LCD_PLATFORM is not set ++CONFIG_BACKLIGHT_CLASS_DEVICE=y ++CONFIG_BACKLIGHT_GENERIC=y ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++# CONFIG_MDA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=m ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++CONFIG_SND_RAWMIDI=m ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_PCM_OSS_PLUGINS=y ++CONFIG_SND_SEQUENCER_OSS=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_VMASTER=y ++CONFIG_SND_MPU401_UART=m ++CONFIG_SND_AC97_CODEC=m ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_VIRMIDI is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++# CONFIG_SND_AC97_POWER_SAVE is not set ++CONFIG_SND_PCI=y ++# CONFIG_SND_AD1889 is not set ++# CONFIG_SND_ALS300 is not set ++# CONFIG_SND_ALI5451 is not set ++# CONFIG_SND_ATIIXP is not set ++# CONFIG_SND_ATIIXP_MODEM is not set ++# CONFIG_SND_AU8810 is not set ++# CONFIG_SND_AU8820 is not set ++# CONFIG_SND_AU8830 is not set ++# CONFIG_SND_AW2 is not set ++# CONFIG_SND_AZT3328 is not set ++# CONFIG_SND_BT87X is not set ++# CONFIG_SND_CA0106 is not set ++# CONFIG_SND_CMIPCI is not set ++# CONFIG_SND_OXYGEN is not set ++# CONFIG_SND_CS4281 is not set ++# CONFIG_SND_CS46XX is not set ++# CONFIG_SND_CS5535AUDIO is not set ++# CONFIG_SND_DARLA20 is not set ++# CONFIG_SND_GINA20 is not set ++# CONFIG_SND_LAYLA20 is not set ++# CONFIG_SND_DARLA24 is not set ++# CONFIG_SND_GINA24 is not set ++# CONFIG_SND_LAYLA24 is not set ++# CONFIG_SND_MONA is not set ++# CONFIG_SND_MIA is not set ++# CONFIG_SND_ECHO3G is not set ++# CONFIG_SND_INDIGO is not set ++# CONFIG_SND_INDIGOIO is not set ++# CONFIG_SND_INDIGODJ is not set ++# CONFIG_SND_INDIGOIOX is not set ++# CONFIG_SND_INDIGODJX is not set ++# CONFIG_SND_EMU10K1 is not set ++# CONFIG_SND_EMU10K1X is not set ++# CONFIG_SND_ENS1370 is not set ++# CONFIG_SND_ENS1371 is not set ++# CONFIG_SND_ES1938 is not set ++# CONFIG_SND_ES1968 is not set ++# CONFIG_SND_FM801 is not set ++# CONFIG_SND_HDA_INTEL is not set ++# CONFIG_SND_HDSP is not set ++# CONFIG_SND_HDSPM is not set ++# CONFIG_SND_HIFIER is not set ++# CONFIG_SND_ICE1712 is not set ++# CONFIG_SND_ICE1724 is not set ++# CONFIG_SND_INTEL8X0 is not set ++# CONFIG_SND_INTEL8X0M is not set ++# CONFIG_SND_KORG1212 is not set ++# CONFIG_SND_MAESTRO3 is not set ++# CONFIG_SND_MIXART is not set ++# CONFIG_SND_NM256 is not set ++# CONFIG_SND_PCXHR is not set ++# CONFIG_SND_RIPTIDE is not set ++# CONFIG_SND_RME32 is not set ++# CONFIG_SND_RME96 is not set ++# CONFIG_SND_RME9652 is not set ++# CONFIG_SND_SONICVIBES is not set ++# CONFIG_SND_TRIDENT is not set ++CONFIG_SND_VIA82XX=m ++# CONFIG_SND_VIA82XX_MODEM is not set ++# CONFIG_SND_VIRTUOSO is not set ++# CONFIG_SND_VX222 is not set ++# CONFIG_SND_YMFPCI is not set ++CONFIG_SND_MIPS=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_AC97_BUS=m ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++# CONFIG_HID_DEBUG is not set ++CONFIG_HIDRAW=y ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=m ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_A4TECH=m ++CONFIG_HID_APPLE=m ++CONFIG_HID_BELKIN=m ++CONFIG_HID_CHERRY=m ++CONFIG_HID_CHICONY=m ++CONFIG_HID_CYPRESS=m ++# CONFIG_DRAGONRISE_FF is not set ++CONFIG_HID_EZKEY=m ++# CONFIG_HID_KYE is not set ++CONFIG_HID_GYRATION=m ++# CONFIG_HID_KENSINGTON is not set ++CONFIG_HID_LOGITECH=m ++CONFIG_LOGITECH_FF=y ++CONFIG_LOGIRUMBLEPAD2_FF=y ++CONFIG_HID_MICROSOFT=m ++CONFIG_HID_MONTEREY=m ++# CONFIG_HID_NTRIG is not set ++CONFIG_HID_PANTHERLORD=m ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=m ++CONFIG_HID_SAMSUNG=m ++CONFIG_HID_SONY=m ++CONFIG_HID_SUNPLUS=m ++# CONFIG_GREENASIA_FF is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_THRUSTMASTER_FF is not set ++CONFIG_ZEROPLUS_FF=m ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++CONFIG_USB_ARCH_HAS_EHCI=y ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_SUSPEND is not set ++# CONFIG_USB_OTG is not set ++CONFIG_USB_OTG_WHITELIST=y ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++CONFIG_USB_WUSB_CBAF=m ++# CONFIG_USB_WUSB_CBAF_DEBUG is not set ++ ++# ++# USB Host Controller Drivers ++# ++CONFIG_USB_C67X00_HCD=m ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_ISP1760_HCD=m ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_UHCI_HCD=m ++# CONFIG_USB_SL811_HCD is not set ++CONFIG_USB_R8A66597_HCD=m ++# CONFIG_USB_WHCI_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++ ++# ++# USB Device Class drivers ++# ++CONFIG_USB_ACM=y ++CONFIG_USB_PRINTER=y ++CONFIG_USB_WDM=m ++CONFIG_USB_TMC=m ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++CONFIG_USB_STORAGE_ONETOUCH=y ++# CONFIG_USB_STORAGE_KARMA is not set ++CONFIG_USB_STORAGE_CYPRESS_ATACB=y ++CONFIG_USB_LIBUSUAL=y ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++CONFIG_USB_SEVSEG=m ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++CONFIG_USB_ISIGHTFW=m ++CONFIG_USB_VST=m ++# CONFIG_USB_GADGET is not set ++ ++# ++# OTG and related infrastructure ++# ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++CONFIG_RTC_DRV_CMOS=y ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=m ++CONFIG_UIO_CIF=m ++# CONFIG_UIO_PDRV is not set ++# CONFIG_UIO_PDRV_GENIRQ is not set ++# CONFIG_UIO_SMX is not set ++# CONFIG_UIO_AEC is not set ++# CONFIG_UIO_SERCOS3 is not set ++# CONFIG_STAGING is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++CONFIG_EXT2_FS_XIP=y ++CONFIG_EXT3_FS=y ++# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set ++# CONFIG_EXT3_FS_XATTR is not set ++CONFIG_EXT4_FS=m ++CONFIG_EXT4DEV_COMPAT=y ++CONFIG_EXT4_FS_XATTR=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++CONFIG_FS_XIP=y ++CONFIG_JBD=y ++# CONFIG_JBD_DEBUG is not set ++CONFIG_JBD2=m ++# CONFIG_JBD2_DEBUG is not set ++CONFIG_FS_MBCACHE=m ++CONFIG_REISERFS_FS=m ++# CONFIG_REISERFS_CHECK is not set ++# CONFIG_REISERFS_PROC_INFO is not set ++# CONFIG_REISERFS_FS_XATTR is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++CONFIG_AUTOFS_FS=y ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=y ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m ++CONFIG_UDF_NLS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=936 ++CONFIG_FAT_DEFAULT_IOCHARSET="utf8" ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_KCORE=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_JFFS2_FS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++CONFIG_OMFS_FS=m ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_NFSD=m ++CONFIG_NFSD_V2_ACL=y ++CONFIG_NFSD_V3=y ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y ++CONFIG_LOCKD=m ++CONFIG_LOCKD_V4=y ++CONFIG_EXPORTFS=m ++CONFIG_NFS_ACL_SUPPORT=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++CONFIG_SUNRPC_GSS=m ++CONFIG_RPCSEC_GSS_KRB5=m ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++CONFIG_SMB_FS=m ++CONFIG_SMB_NLS_DEFAULT=y ++CONFIG_SMB_NLS_REMOTE="cp936" ++CONFIG_CIFS=m ++CONFIG_CIFS_STATS=y ++CONFIG_CIFS_STATS2=y ++CONFIG_CIFS_WEAK_PW_HASH=y ++CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y ++CONFIG_CIFS_DEBUG2=y ++CONFIG_CIFS_EXPERIMENTAL=y ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++# CONFIG_9P_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="utf8" ++# CONFIG_NLS_CODEPAGE_437 is not set ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++CONFIG_NLS_CODEPAGE_936=y ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_FRAME_WARN=2048 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_NOP_TRACER=y ++CONFIG_RING_BUFFER=y ++CONFIG_TRACING=y ++CONFIG_TRACING_SUPPORT=y ++ ++# ++# Tracers ++# ++# CONFIG_IRQSOFF_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_EVENT_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_TRACE_BRANCH_PROFILING is not set ++# CONFIG_KMEMTRACE is not set ++# CONFIG_WORKQUEUE_TRACER is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_FTRACE_STARTUP_TEST is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++CONFIG_CMDLINE="" ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_SECURITY_FILE_CAPABILITIES=y ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_FIPS=y ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=m ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=m ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=m ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++CONFIG_CRYPTO_GF128MUL=m ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=m ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++CONFIG_CRYPTO_CCM=m ++CONFIG_CRYPTO_GCM=m ++CONFIG_CRYPTO_SEQIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=m ++CONFIG_CRYPTO_CTR=m ++CONFIG_CRYPTO_CTS=m ++CONFIG_CRYPTO_ECB=m ++# CONFIG_CRYPTO_LRW is not set ++CONFIG_CRYPTO_PCBC=m ++CONFIG_CRYPTO_XTS=m ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++CONFIG_CRYPTO_MD5=m ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++CONFIG_CRYPTO_RMD128=m ++CONFIG_CRYPTO_RMD160=m ++CONFIG_CRYPTO_RMD256=m ++CONFIG_CRYPTO_RMD320=m ++CONFIG_CRYPTO_SHA1=m ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=m ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=m ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=m ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++CONFIG_CRYPTO_SALSA20=m ++CONFIG_CRYPTO_SEED=m ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=m ++# CONFIG_CRYPTO_ZLIB is not set ++CONFIG_CRYPTO_LZO=m ++ ++# ++# Random Number Generation ++# ++CONFIG_CRYPTO_ANSI_CPRNG=m ++# CONFIG_CRYPTO_HW is not set ++CONFIG_BINARY_PRINTF=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=m ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=m ++CONFIG_CRC32=y ++CONFIG_CRC7=m ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=m ++CONFIG_ZLIB_DEFLATE=m ++CONFIG_LZO_COMPRESS=m ++CONFIG_LZO_DECOMPRESS=m ++CONFIG_TEXTSEARCH=y ++CONFIG_TEXTSEARCH_KMP=m ++CONFIG_TEXTSEARCH_BM=m ++CONFIG_TEXTSEARCH_FSM=m ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y ++CONFIG_NLATTR=y +diff -Nur linux-2.6.30/arch/mips/configs/fuloong2f_defconfig rt4ls/arch/mips/configs/fuloong2f_defconfig +--- linux-2.6.30/arch/mips/configs/fuloong2f_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/configs/fuloong2f_defconfig 2009-06-12 16:27:08.246405134 +0200 +@@ -0,0 +1,2637 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.30-rc8 ++# Wed Jun 10 22:20:53 2009 ++# ++CONFIG_MIPS=y ++ ++# ++# Machine selection ++# ++# CONFIG_MACH_ALCHEMY is not set ++# CONFIG_BASLER_EXCITE is not set ++# CONFIG_BCM47XX is not set ++# CONFIG_MIPS_COBALT is not set ++# CONFIG_MACH_DECSTATION is not set ++# CONFIG_MACH_JAZZ is not set ++# CONFIG_LASAT is not set ++CONFIG_MACH_LOONGSON=y ++# CONFIG_MIPS_MALTA is not set ++# CONFIG_MIPS_SIM is not set ++# CONFIG_NEC_MARKEINS is not set ++# CONFIG_MACH_VR41XX is not set ++# CONFIG_NXP_STB220 is not set ++# CONFIG_NXP_STB225 is not set ++# CONFIG_PNX8550_JBS is not set ++# CONFIG_PNX8550_STB810 is not set ++# CONFIG_PMC_MSP is not set ++# CONFIG_PMC_YOSEMITE is not set ++# CONFIG_SGI_IP22 is not set ++# CONFIG_SGI_IP27 is not set ++# CONFIG_SGI_IP28 is not set ++# CONFIG_SGI_IP32 is not set ++# CONFIG_SIBYTE_CRHINE is not set ++# CONFIG_SIBYTE_CARMEL is not set ++# CONFIG_SIBYTE_CRHONE is not set ++# CONFIG_SIBYTE_RHONE is not set ++# CONFIG_SIBYTE_SWARM is not set ++# CONFIG_SIBYTE_LITTLESUR is not set ++# CONFIG_SIBYTE_SENTOSA is not set ++# CONFIG_SIBYTE_BIGSUR is not set ++# CONFIG_SNI_RM is not set ++# CONFIG_MACH_TX39XX is not set ++# CONFIG_MACH_TX49XX is not set ++# CONFIG_MIKROTIK_RB532 is not set ++# CONFIG_WR_PPMC is not set ++# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set ++# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set ++CONFIG_ARCH_SPARSEMEM_ENABLE=y ++# CONFIG_LEMOTE_FULOONG2E is not set ++CONFIG_LEMOTE_FULOONG2F=y ++# CONFIG_LEMOTE_YEELOONG2F is not set ++CONFIG_CS5536=y ++CONFIG_CS5536_MFGPT=y ++CONFIG_UCA_SIZE=0x2000000 ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_ARCH_SUPPORTS_OPROFILE=y ++CONFIG_GENERIC_FIND_NEXT_BIT=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CMOS_UPDATE=y ++CONFIG_SCHED_OMIT_FRAME_POINTER=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_DMA_NONCOHERENT=y ++CONFIG_DMA_NEED_PCI_MAP_STATE=y ++CONFIG_EARLY_PRINTK=y ++CONFIG_SYS_HAS_EARLY_PRINTK=y ++# CONFIG_HOTPLUG_CPU is not set ++CONFIG_I8259=y ++# CONFIG_NO_IOPORT is not set ++CONFIG_GENERIC_ISA_DMA=y ++CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y ++# CONFIG_CPU_BIG_ENDIAN is not set ++CONFIG_CPU_LITTLE_ENDIAN=y ++CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y ++CONFIG_IRQ_CPU=y ++CONFIG_BOOT_ELF32=y ++CONFIG_MIPS_L1_CACHE_SHIFT=5 ++ ++# ++# CPU selection ++# ++# CONFIG_CPU_LOONGSON2E is not set ++CONFIG_CPU_LOONGSON2F=y ++# CONFIG_CPU_MIPS32_R1 is not set ++# CONFIG_CPU_MIPS32_R2 is not set ++# CONFIG_CPU_MIPS64_R1 is not set ++# CONFIG_CPU_MIPS64_R2 is not set ++# CONFIG_CPU_R3000 is not set ++# CONFIG_CPU_TX39XX is not set ++# CONFIG_CPU_VR41XX is not set ++# CONFIG_CPU_R4300 is not set ++# CONFIG_CPU_R4X00 is not set ++# CONFIG_CPU_TX49XX is not set ++# CONFIG_CPU_R5000 is not set ++# CONFIG_CPU_R5432 is not set ++# CONFIG_CPU_R5500 is not set ++# CONFIG_CPU_R6000 is not set ++# CONFIG_CPU_NEVADA is not set ++# CONFIG_CPU_R8000 is not set ++# CONFIG_CPU_R10000 is not set ++# CONFIG_CPU_RM7000 is not set ++# CONFIG_CPU_RM9000 is not set ++# CONFIG_CPU_SB1 is not set ++# CONFIG_CPU_CAVIUM_OCTEON is not set ++CONFIG_CPU_LOONGSON2=y ++CONFIG_SYS_HAS_CPU_LOONGSON2F=y ++CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y ++CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y ++CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y ++CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y ++ ++# ++# Kernel type ++# ++# CONFIG_32BIT is not set ++CONFIG_64BIT=y ++# CONFIG_PAGE_SIZE_4KB is not set ++# CONFIG_PAGE_SIZE_8KB is not set ++CONFIG_PAGE_SIZE_16KB=y ++# CONFIG_PAGE_SIZE_32KB is not set ++# CONFIG_PAGE_SIZE_64KB is not set ++CONFIG_BOARD_SCACHE=y ++CONFIG_MIPS_MT_DISABLED=y ++# CONFIG_MIPS_MT_SMP is not set ++# CONFIG_MIPS_MT_SMTC is not set ++CONFIG_CPU_HAS_WB=y ++CONFIG_CPU_HAS_SYNC=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_CPU_SUPPORTS_HIGHMEM=y ++CONFIG_SYS_SUPPORTS_HIGHMEM=y ++CONFIG_ARCH_FLATMEM_ENABLE=y ++CONFIG_ARCH_POPULATES_NODE_MAP=y ++CONFIG_SELECT_MEMORY_MODEL=y ++# CONFIG_FLATMEM_MANUAL is not set ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++CONFIG_SPARSEMEM_MANUAL=y ++CONFIG_SPARSEMEM=y ++CONFIG_HAVE_MEMORY_PRESENT=y ++CONFIG_SPARSEMEM_STATIC=y ++ ++# ++# Memory hotplug is currently incompatible with Software Suspend ++# ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_PHYS_ADDR_T_64BIT=y ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++CONFIG_HAVE_MLOCK=y ++CONFIG_HAVE_MLOCKED_PAGE_BIT=y ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++# CONFIG_HZ_48 is not set ++# CONFIG_HZ_100 is not set ++# CONFIG_HZ_128 is not set ++CONFIG_HZ_250=y ++# CONFIG_HZ_256 is not set ++# CONFIG_HZ_1000 is not set ++# CONFIG_HZ_1024 is not set ++CONFIG_SYS_SUPPORTS_ARBIT_HZ=y ++CONFIG_HZ=250 ++# CONFIG_PREEMPT_NONE is not set ++CONFIG_PREEMPT_VOLUNTARY=y ++# CONFIG_PREEMPT is not set ++CONFIG_KEXEC=y ++# CONFIG_SECCOMP is not set ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++# CONFIG_TASKSTATS is not set ++CONFIG_AUDIT=y ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=15 ++# CONFIG_GROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++# CONFIG_NAMESPACES is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_EMBEDDED=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++# CONFIG_STRIP_ASM_SYMS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_PCSPKR_PLATFORM=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_PCI_QUIRKS=y ++CONFIG_COMPAT_BRK=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++CONFIG_PROFILING=y ++# CONFIG_MARKERS is not set ++# CONFIG_OPROFILE is not set ++CONFIG_HAVE_OPROFILE=y ++CONFIG_HAVE_SYSCALL_WRAPPERS=y ++# CONFIG_SLOW_WORK is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++CONFIG_MODVERSIONS=y ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++CONFIG_BLOCK_COMPAT=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_PROBE_INITRD_HEADER is not set ++CONFIG_FREEZER=y ++ ++# ++# Bus options (PCI, PCMCIA, EISA, ISA, TC) ++# ++CONFIG_HW_HAS_PCI=y ++CONFIG_PCI=y ++CONFIG_PCI_DOMAINS=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++CONFIG_PCI_LEGACY=y ++# CONFIG_PCI_STUB is not set ++# CONFIG_PCI_IOV is not set ++CONFIG_ISA=y ++CONFIG_MMU=y ++CONFIG_PCCARD=m ++# CONFIG_PCMCIA_DEBUG is not set ++CONFIG_PCMCIA=m ++CONFIG_PCMCIA_LOAD_CIS=y ++CONFIG_PCMCIA_IOCTL=y ++CONFIG_CARDBUS=y ++ ++# ++# PC-card bridges ++# ++CONFIG_YENTA=m ++CONFIG_YENTA_O2=y ++CONFIG_YENTA_RICOH=y ++CONFIG_YENTA_TI=y ++CONFIG_YENTA_ENE_TUNE=y ++CONFIG_YENTA_TOSHIBA=y ++CONFIG_PD6729=m ++CONFIG_I82092=m ++CONFIG_I82365=m ++CONFIG_TCIC=m ++CONFIG_PCMCIA_PROBE=y ++CONFIG_PCCARD_NONSTATIC=m ++CONFIG_HOTPLUG_PCI=m ++CONFIG_HOTPLUG_PCI_FAKE=m ++CONFIG_HOTPLUG_PCI_CPCI=y ++CONFIG_HOTPLUG_PCI_SHPC=m ++ ++# ++# Executable file formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++# CONFIG_HAVE_AOUT is not set ++CONFIG_BINFMT_MISC=m ++CONFIG_MIPS32_COMPAT=y ++CONFIG_COMPAT=y ++CONFIG_SYSVIPC_COMPAT=y ++CONFIG_MIPS32_O32=y ++CONFIG_MIPS32_N32=y ++CONFIG_BINFMT_ELF32=y ++ ++# ++# Power management options ++# ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_SLEEP=y ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++CONFIG_HIBERNATION=y ++CONFIG_PM_STD_PARTITION="/dev/hda3" ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_TABLE=y ++# CONFIG_CPU_FREQ_DEBUG is not set ++CONFIG_CPU_FREQ_STAT=y ++# CONFIG_CPU_FREQ_STAT_DETAILS is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y ++CONFIG_LOONGSON2F_CPU_FREQ=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++CONFIG_XFRM_USER=m ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_XFRM_IPCOMP=m ++CONFIG_NET_KEY=m ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++CONFIG_NET_IPIP=m ++CONFIG_NET_IPGRE=m ++CONFIG_NET_IPGRE_BROADCAST=y ++CONFIG_IP_MROUTE=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++# CONFIG_ARPD is not set ++CONFIG_SYN_COOKIES=y ++CONFIG_INET_AH=m ++CONFIG_INET_ESP=m ++CONFIG_INET_IPCOMP=m ++CONFIG_INET_XFRM_TUNNEL=m ++CONFIG_INET_TUNNEL=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=m ++CONFIG_INET_XFRM_MODE_TUNNEL=m ++CONFIG_INET_XFRM_MODE_BEET=y ++CONFIG_INET_LRO=y ++CONFIG_INET_DIAG=m ++CONFIG_INET_TCP_DIAG=m ++CONFIG_TCP_CONG_ADVANCED=y ++CONFIG_TCP_CONG_BIC=y ++CONFIG_TCP_CONG_CUBIC=m ++CONFIG_TCP_CONG_WESTWOOD=m ++CONFIG_TCP_CONG_HTCP=m ++CONFIG_TCP_CONG_HSTCP=m ++CONFIG_TCP_CONG_HYBLA=m ++CONFIG_TCP_CONG_VEGAS=m ++CONFIG_TCP_CONG_SCALABLE=m ++CONFIG_TCP_CONG_LP=m ++CONFIG_TCP_CONG_VENO=m ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++CONFIG_DEFAULT_BIC=y ++# CONFIG_DEFAULT_CUBIC is not set ++# CONFIG_DEFAULT_HTCP is not set ++# CONFIG_DEFAULT_VEGAS is not set ++# CONFIG_DEFAULT_WESTWOOD is not set ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="bic" ++# CONFIG_TCP_MD5SIG is not set ++CONFIG_IPV6=m ++CONFIG_IPV6_PRIVACY=y ++# CONFIG_IPV6_ROUTER_PREF is not set ++# CONFIG_IPV6_OPTIMISTIC_DAD is not set ++CONFIG_INET6_AH=m ++CONFIG_INET6_ESP=m ++CONFIG_INET6_IPCOMP=m ++# CONFIG_IPV6_MIP6 is not set ++CONFIG_INET6_XFRM_TUNNEL=m ++CONFIG_INET6_TUNNEL=m ++CONFIG_INET6_XFRM_MODE_TRANSPORT=m ++CONFIG_INET6_XFRM_MODE_TUNNEL=m ++CONFIG_INET6_XFRM_MODE_BEET=m ++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set ++CONFIG_IPV6_SIT=m ++CONFIG_IPV6_NDISC_NODETYPE=y ++CONFIG_IPV6_TUNNEL=m ++# CONFIG_IPV6_MULTIPLE_TABLES is not set ++# CONFIG_IPV6_MROUTE is not set ++# CONFIG_NETLABEL is not set ++CONFIG_NETWORK_SECMARK=y ++CONFIG_NETFILTER=y ++# CONFIG_NETFILTER_DEBUG is not set ++CONFIG_NETFILTER_ADVANCED=y ++CONFIG_BRIDGE_NETFILTER=y ++ ++# ++# Core Netfilter Configuration ++# ++CONFIG_NETFILTER_NETLINK=m ++CONFIG_NETFILTER_NETLINK_QUEUE=m ++CONFIG_NETFILTER_NETLINK_LOG=m ++# CONFIG_NF_CONNTRACK is not set ++# CONFIG_NETFILTER_TPROXY is not set ++CONFIG_NETFILTER_XTABLES=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++# CONFIG_NETFILTER_XT_TARGET_DSCP is not set ++CONFIG_NETFILTER_XT_TARGET_HL=m ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set ++# CONFIG_NETFILTER_XT_TARGET_TRACE is not set ++CONFIG_NETFILTER_XT_TARGET_SECMARK=m ++# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set ++# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_DCCP=m ++# CONFIG_NETFILTER_XT_MATCH_DSCP is not set ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set ++CONFIG_NETFILTER_XT_MATCH_HL=m ++# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++# CONFIG_NETFILTER_XT_MATCH_OWNER is not set ++CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++# CONFIG_NETFILTER_XT_MATCH_RECENT is not set ++CONFIG_NETFILTER_XT_MATCH_SCTP=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++# CONFIG_NETFILTER_XT_MATCH_TIME is not set ++# CONFIG_NETFILTER_XT_MATCH_U32 is not set ++CONFIG_IP_VS=m ++# CONFIG_IP_VS_IPV6 is not set ++# CONFIG_IP_VS_DEBUG is not set ++CONFIG_IP_VS_TAB_BITS=12 ++ ++# ++# IPVS transport protocol load balancing support ++# ++CONFIG_IP_VS_PROTO_TCP=y ++CONFIG_IP_VS_PROTO_UDP=y ++CONFIG_IP_VS_PROTO_AH_ESP=y ++CONFIG_IP_VS_PROTO_ESP=y ++CONFIG_IP_VS_PROTO_AH=y ++ ++# ++# IPVS scheduler ++# ++CONFIG_IP_VS_RR=m ++CONFIG_IP_VS_WRR=m ++CONFIG_IP_VS_LC=m ++CONFIG_IP_VS_WLC=m ++CONFIG_IP_VS_LBLC=m ++CONFIG_IP_VS_LBLCR=m ++CONFIG_IP_VS_DH=m ++CONFIG_IP_VS_SH=m ++CONFIG_IP_VS_SED=m ++CONFIG_IP_VS_NQ=m ++ ++# ++# IPVS application helper ++# ++CONFIG_IP_VS_FTP=m ++ ++# ++# IP: Netfilter Configuration ++# ++# CONFIG_NF_DEFRAG_IPV4 is not set ++CONFIG_IP_NF_QUEUE=m ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_ADDRTYPE=m ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_TARGET_LOG=m ++CONFIG_IP_NF_TARGET_ULOG=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++# CONFIG_IP_NF_SECURITY is not set ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++ ++# ++# IPv6: Netfilter Configuration ++# ++CONFIG_IP6_NF_QUEUE=m ++CONFIG_IP6_NF_IPTABLES=m ++CONFIG_IP6_NF_MATCH_AH=m ++CONFIG_IP6_NF_MATCH_EUI64=m ++CONFIG_IP6_NF_MATCH_FRAG=m ++CONFIG_IP6_NF_MATCH_OPTS=m ++CONFIG_IP6_NF_MATCH_HL=m ++CONFIG_IP6_NF_MATCH_IPV6HEADER=m ++# CONFIG_IP6_NF_MATCH_MH is not set ++CONFIG_IP6_NF_MATCH_RT=m ++CONFIG_IP6_NF_TARGET_HL=m ++CONFIG_IP6_NF_TARGET_LOG=m ++CONFIG_IP6_NF_FILTER=m ++CONFIG_IP6_NF_TARGET_REJECT=m ++CONFIG_IP6_NF_MANGLE=m ++CONFIG_IP6_NF_RAW=m ++# CONFIG_IP6_NF_SECURITY is not set ++ ++# ++# DECnet: Netfilter Configuration ++# ++CONFIG_DECNET_NF_GRABULATOR=m ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++# CONFIG_BRIDGE_EBT_IP6 is not set ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_ULOG=m ++# CONFIG_BRIDGE_EBT_NFLOG is not set ++CONFIG_IP_DCCP=m ++CONFIG_INET_DCCP_DIAG=m ++ ++# ++# DCCP CCIDs Configuration (EXPERIMENTAL) ++# ++# CONFIG_IP_DCCP_CCID2_DEBUG is not set ++CONFIG_IP_DCCP_CCID3=y ++# CONFIG_IP_DCCP_CCID3_DEBUG is not set ++CONFIG_IP_DCCP_CCID3_RTO=100 ++CONFIG_IP_DCCP_TFRC_LIB=y ++CONFIG_IP_SCTP=m ++# CONFIG_SCTP_DBG_MSG is not set ++# CONFIG_SCTP_DBG_OBJCNT is not set ++# CONFIG_SCTP_HMAC_NONE is not set ++# CONFIG_SCTP_HMAC_SHA1 is not set ++CONFIG_SCTP_HMAC_MD5=y ++CONFIG_TIPC=m ++CONFIG_TIPC_ADVANCED=y ++CONFIG_TIPC_ZONES=3 ++CONFIG_TIPC_CLUSTERS=1 ++CONFIG_TIPC_NODES=255 ++CONFIG_TIPC_SLAVE_NODES=0 ++CONFIG_TIPC_PORTS=8191 ++CONFIG_TIPC_LOG=0 ++# CONFIG_TIPC_DEBUG is not set ++CONFIG_ATM=y ++CONFIG_ATM_CLIP=y ++# CONFIG_ATM_CLIP_NO_ICMP is not set ++CONFIG_ATM_LANE=m ++CONFIG_ATM_MPOA=m ++CONFIG_ATM_BR2684=m ++# CONFIG_ATM_BR2684_IPFILTER is not set ++CONFIG_STP=m ++CONFIG_BRIDGE=m ++# CONFIG_NET_DSA is not set ++CONFIG_VLAN_8021Q=m ++# CONFIG_VLAN_8021Q_GVRP is not set ++CONFIG_DECNET=m ++# CONFIG_DECNET_ROUTER is not set ++CONFIG_LLC=m ++CONFIG_LLC2=m ++CONFIG_IPX=m ++# CONFIG_IPX_INTERN is not set ++CONFIG_ATALK=m ++CONFIG_DEV_APPLETALK=m ++# CONFIG_COPS is not set ++CONFIG_IPDDP=m ++CONFIG_IPDDP_ENCAP=y ++CONFIG_IPDDP_DECAP=y ++CONFIG_X25=m ++CONFIG_LAPB=m ++CONFIG_ECONET=m ++CONFIG_ECONET_AUNUDP=y ++CONFIG_ECONET_NATIVE=y ++CONFIG_WAN_ROUTER=m ++# CONFIG_PHONET is not set ++CONFIG_NET_SCHED=y ++ ++# ++# Queueing/Scheduling ++# ++CONFIG_NET_SCH_CBQ=m ++CONFIG_NET_SCH_HTB=m ++CONFIG_NET_SCH_HFSC=m ++CONFIG_NET_SCH_ATM=m ++CONFIG_NET_SCH_PRIO=m ++# CONFIG_NET_SCH_MULTIQ is not set ++CONFIG_NET_SCH_RED=m ++CONFIG_NET_SCH_SFQ=m ++CONFIG_NET_SCH_TEQL=m ++CONFIG_NET_SCH_TBF=m ++CONFIG_NET_SCH_GRED=m ++CONFIG_NET_SCH_DSMARK=m ++CONFIG_NET_SCH_NETEM=m ++# CONFIG_NET_SCH_DRR is not set ++CONFIG_NET_SCH_INGRESS=m ++ ++# ++# Classification ++# ++CONFIG_NET_CLS=y ++CONFIG_NET_CLS_BASIC=m ++CONFIG_NET_CLS_TCINDEX=m ++CONFIG_NET_CLS_ROUTE4=m ++CONFIG_NET_CLS_ROUTE=y ++CONFIG_NET_CLS_FW=m ++CONFIG_NET_CLS_U32=m ++CONFIG_CLS_U32_PERF=y ++CONFIG_CLS_U32_MARK=y ++CONFIG_NET_CLS_RSVP=m ++CONFIG_NET_CLS_RSVP6=m ++# CONFIG_NET_CLS_FLOW is not set ++CONFIG_NET_EMATCH=y ++CONFIG_NET_EMATCH_STACK=32 ++CONFIG_NET_EMATCH_CMP=m ++CONFIG_NET_EMATCH_NBYTE=m ++CONFIG_NET_EMATCH_U32=m ++CONFIG_NET_EMATCH_META=m ++CONFIG_NET_EMATCH_TEXT=m ++CONFIG_NET_CLS_ACT=y ++CONFIG_NET_ACT_POLICE=m ++CONFIG_NET_ACT_GACT=m ++CONFIG_GACT_PROB=y ++CONFIG_NET_ACT_MIRRED=m ++CONFIG_NET_ACT_IPT=m ++# CONFIG_NET_ACT_NAT is not set ++CONFIG_NET_ACT_PEDIT=m ++CONFIG_NET_ACT_SIMP=m ++# CONFIG_NET_ACT_SKBEDIT is not set ++CONFIG_NET_CLS_IND=y ++CONFIG_NET_SCH_FIFO=y ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++CONFIG_NET_PKTGEN=m ++CONFIG_HAMRADIO=y ++ ++# ++# Packet Radio protocols ++# ++CONFIG_AX25=m ++# CONFIG_AX25_DAMA_SLAVE is not set ++CONFIG_NETROM=m ++CONFIG_ROSE=m ++ ++# ++# AX.25 network device drivers ++# ++CONFIG_MKISS=m ++CONFIG_6PACK=m ++CONFIG_BPQETHER=m ++CONFIG_BAYCOM_SER_FDX=m ++CONFIG_BAYCOM_SER_HDX=m ++CONFIG_YAM=m ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++CONFIG_AF_RXRPC=y ++# CONFIG_AF_RXRPC_DEBUG is not set ++# CONFIG_RXKAD is not set ++CONFIG_FIB_RULES=y ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=m ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++CONFIG_CONNECTOR=m ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_PNP=y ++CONFIG_PNP_DEBUG_MESSAGES=y ++ ++# ++# Protocols ++# ++CONFIG_ISAPNP=y ++# CONFIG_PNPACPI is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_CPQ_DA is not set ++# CONFIG_BLK_CPQ_CISS_DA is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_CRYPTOLOOP=y ++CONFIG_BLK_DEV_NBD=m ++# CONFIG_BLK_DEV_SX8 is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++# CONFIG_BLK_DEV_XIP is not set ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_CDROM_PKTCDVD_BUFFERS=8 ++# CONFIG_CDROM_PKTCDVD_WCACHE is not set ++CONFIG_ATA_OVER_ETH=m ++# CONFIG_BLK_DEV_HD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_PHANTOM is not set ++# CONFIG_SGI_IOC4 is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_93CX6 is not set ++CONFIG_HAVE_IDE=y ++CONFIG_IDE=y ++ ++# ++# Please see Documentation/ide/ide.txt for help/info on IDE drives ++# ++CONFIG_IDE_XFER_MODE=y ++CONFIG_IDE_TIMINGS=y ++CONFIG_IDE_ATAPI=y ++# CONFIG_BLK_DEV_IDE_SATA is not set ++CONFIG_IDE_GD=y ++CONFIG_IDE_GD_ATA=y ++# CONFIG_IDE_GD_ATAPI is not set ++# CONFIG_BLK_DEV_IDECS is not set ++# CONFIG_BLK_DEV_DELKIN is not set ++CONFIG_BLK_DEV_IDECD=m ++CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y ++# CONFIG_BLK_DEV_IDETAPE is not set ++CONFIG_IDE_TASK_IOCTL=y ++CONFIG_IDE_PROC_FS=y ++ ++# ++# IDE chipset support/bugfixes ++# ++# CONFIG_IDE_GENERIC is not set ++# CONFIG_BLK_DEV_PLATFORM is not set ++# CONFIG_BLK_DEV_IDEPNP is not set ++CONFIG_BLK_DEV_IDEDMA_SFF=y ++ ++# ++# PCI IDE chipsets support ++# ++CONFIG_BLK_DEV_IDEPCI=y ++# CONFIG_IDEPCI_PCIBUS_ORDER is not set ++# CONFIG_BLK_DEV_OFFBOARD is not set ++CONFIG_BLK_DEV_GENERIC=y ++# CONFIG_BLK_DEV_OPTI621 is not set ++CONFIG_BLK_DEV_IDEDMA_PCI=y ++# CONFIG_BLK_DEV_AEC62XX is not set ++# CONFIG_BLK_DEV_ALI15X3 is not set ++CONFIG_BLK_DEV_AMD74XX=y ++# CONFIG_BLK_DEV_CMD64X is not set ++# CONFIG_BLK_DEV_TRIFLEX is not set ++# CONFIG_BLK_DEV_CS5520 is not set ++# CONFIG_BLK_DEV_CS5530 is not set ++# CONFIG_BLK_DEV_HPT366 is not set ++# CONFIG_BLK_DEV_JMICRON is not set ++# CONFIG_BLK_DEV_SC1200 is not set ++# CONFIG_BLK_DEV_PIIX is not set ++# CONFIG_BLK_DEV_IT8172 is not set ++# CONFIG_BLK_DEV_IT8213 is not set ++# CONFIG_BLK_DEV_IT821X is not set ++# CONFIG_BLK_DEV_NS87415 is not set ++# CONFIG_BLK_DEV_PDC202XX_OLD is not set ++# CONFIG_BLK_DEV_PDC202XX_NEW is not set ++# CONFIG_BLK_DEV_SVWKS is not set ++# CONFIG_BLK_DEV_SIIMAGE is not set ++# CONFIG_BLK_DEV_SLC90E66 is not set ++# CONFIG_BLK_DEV_TRM290 is not set ++# CONFIG_BLK_DEV_VIA82CXXX is not set ++# CONFIG_BLK_DEV_TC86C001 is not set ++ ++# ++# Other IDE chipsets support ++# ++ ++# ++# Note: most of these also require special kernel boot parameters ++# ++# CONFIG_BLK_DEV_4DRIVES is not set ++# CONFIG_BLK_DEV_ALI14XX is not set ++# CONFIG_BLK_DEV_DTC2278 is not set ++# CONFIG_BLK_DEV_HT6560B is not set ++# CONFIG_BLK_DEV_QD65XX is not set ++# CONFIG_BLK_DEV_UMC8672 is not set ++CONFIG_BLK_DEV_IDEDMA=y ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++CONFIG_SCSI_NETLINK=y ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++CONFIG_BLK_DEV_SR=m ++CONFIG_BLK_DEV_SR_VENDOR=y ++CONFIG_CHR_DEV_SG=m ++CONFIG_CHR_DEV_SCH=m ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++CONFIG_SCSI_CONSTANTS=y ++CONFIG_SCSI_LOGGING=y ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++CONFIG_SCSI_SPI_ATTRS=m ++CONFIG_SCSI_FC_ATTRS=m ++CONFIG_SCSI_ISCSI_ATTRS=m ++CONFIG_SCSI_SAS_ATTRS=m ++# CONFIG_SCSI_SAS_LIBSAS is not set ++CONFIG_SCSI_SRP_ATTRS=m ++CONFIG_SCSI_LOWLEVEL=y ++CONFIG_ISCSI_TCP=m ++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set ++# CONFIG_SCSI_3W_9XXX is not set ++# CONFIG_SCSI_ACARD is not set ++# CONFIG_SCSI_AACRAID is not set ++# CONFIG_SCSI_AIC7XXX is not set ++# CONFIG_SCSI_AIC7XXX_OLD is not set ++# CONFIG_SCSI_AIC79XX is not set ++# CONFIG_SCSI_AIC94XX is not set ++# CONFIG_SCSI_DPT_I2O is not set ++# CONFIG_SCSI_ADVANSYS is not set ++# CONFIG_SCSI_IN2000 is not set ++# CONFIG_SCSI_ARCMSR is not set ++# CONFIG_MEGARAID_NEWGEN is not set ++# CONFIG_MEGARAID_LEGACY is not set ++# CONFIG_MEGARAID_SAS is not set ++# CONFIG_SCSI_MPT2SAS is not set ++# CONFIG_SCSI_HPTIOP is not set ++# CONFIG_LIBFC is not set ++# CONFIG_LIBFCOE is not set ++# CONFIG_FCOE is not set ++# CONFIG_SCSI_DMX3191D is not set ++# CONFIG_SCSI_DTC3280 is not set ++# CONFIG_SCSI_FUTURE_DOMAIN is not set ++# CONFIG_SCSI_GENERIC_NCR5380 is not set ++# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set ++# CONFIG_SCSI_IPS is not set ++# CONFIG_SCSI_INITIO is not set ++# CONFIG_SCSI_INIA100 is not set ++# CONFIG_SCSI_MVSAS is not set ++# CONFIG_SCSI_NCR53C406A is not set ++# CONFIG_SCSI_STEX is not set ++# CONFIG_SCSI_SYM53C8XX_2 is not set ++# CONFIG_SCSI_PAS16 is not set ++# CONFIG_SCSI_QLOGIC_FAS is not set ++# CONFIG_SCSI_QLOGIC_1280 is not set ++# CONFIG_SCSI_QLA_FC is not set ++# CONFIG_SCSI_QLA_ISCSI is not set ++# CONFIG_SCSI_LPFC is not set ++# CONFIG_SCSI_SYM53C416 is not set ++# CONFIG_SCSI_DC395x is not set ++# CONFIG_SCSI_DC390T is not set ++# CONFIG_SCSI_T128 is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_SRP is not set ++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++CONFIG_MD=y ++CONFIG_BLK_DEV_MD=m ++CONFIG_MD_LINEAR=m ++CONFIG_MD_RAID0=m ++CONFIG_MD_RAID1=m ++CONFIG_MD_RAID10=m ++CONFIG_MD_RAID456=m ++CONFIG_MD_RAID6_PQ=m ++CONFIG_MD_MULTIPATH=m ++CONFIG_MD_FAULTY=m ++CONFIG_BLK_DEV_DM=m ++# CONFIG_DM_DEBUG is not set ++CONFIG_DM_CRYPT=m ++CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_MIRROR=m ++CONFIG_DM_ZERO=m ++CONFIG_DM_MULTIPATH=m ++# CONFIG_DM_DELAY is not set ++# CONFIG_DM_UEVENT is not set ++CONFIG_FUSION=y ++CONFIG_FUSION_SPI=m ++CONFIG_FUSION_FC=m ++CONFIG_FUSION_SAS=m ++CONFIG_FUSION_MAX_SGE=40 ++CONFIG_FUSION_CTL=m ++# CONFIG_FUSION_LOGGING is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++ ++# ++# Enable only one of the two stacks, unless you know what you are doing ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_IEEE1394 is not set ++# CONFIG_I2O is not set ++CONFIG_NETDEVICES=y ++CONFIG_COMPAT_NET_DEV_OPS=y ++# CONFIG_IFB is not set ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++CONFIG_TUN=m ++CONFIG_VETH=m ++CONFIG_NET_SB1000=m ++# CONFIG_ARCNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++CONFIG_MARVELL_PHY=m ++CONFIG_DAVICOM_PHY=m ++CONFIG_QSEMI_PHY=m ++CONFIG_LXT_PHY=m ++CONFIG_CICADA_PHY=m ++CONFIG_VITESSE_PHY=m ++CONFIG_SMSC_PHY=m ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++CONFIG_REALTEK_PHY=m ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_HAPPYMEAL is not set ++# CONFIG_SUNGEM is not set ++# CONFIG_CASSINI is not set ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_NET_VENDOR_SMC is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_ETHOC is not set ++# CONFIG_NET_VENDOR_RACAL is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_TULIP is not set ++# CONFIG_AT1700 is not set ++# CONFIG_DEPCA is not set ++# CONFIG_HP100 is not set ++# CONFIG_NET_ISA is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_NET_PCI is not set ++# CONFIG_B44 is not set ++# CONFIG_CS89x0 is not set ++# CONFIG_ATL2 is not set ++CONFIG_NETDEV_1000=y ++# CONFIG_ACENIC is not set ++# CONFIG_DL2K is not set ++# CONFIG_E1000 is not set ++# CONFIG_E1000E is not set ++# CONFIG_IP1000 is not set ++# CONFIG_IGB is not set ++# CONFIG_IGBVF is not set ++# CONFIG_NS83820 is not set ++# CONFIG_HAMACHI is not set ++# CONFIG_YELLOWFIN is not set ++CONFIG_R8169=y ++CONFIG_R8169_VLAN=y ++# CONFIG_SIS190 is not set ++# CONFIG_SKGE is not set ++# CONFIG_SKY2 is not set ++# CONFIG_VIA_VELOCITY is not set ++# CONFIG_TIGON3 is not set ++# CONFIG_BNX2 is not set ++# CONFIG_QLA3XXX is not set ++# CONFIG_ATL1 is not set ++# CONFIG_ATL1E is not set ++# CONFIG_ATL1C is not set ++# CONFIG_JME is not set ++# CONFIG_NETDEV_10000 is not set ++# CONFIG_TR is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_NET_PCMCIA is not set ++# CONFIG_WAN is not set ++# CONFIG_ATM_DRIVERS is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++CONFIG_PPP=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_MPPE=m ++CONFIG_PPPOE=m ++CONFIG_PPPOATM=m ++# CONFIG_PPPOL2TP is not set ++# CONFIG_SLIP is not set ++CONFIG_SLHC=m ++# CONFIG_NET_FC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++CONFIG_INPUT_JOYDEV=m ++CONFIG_INPUT_EVDEV=m ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++CONFIG_KEYBOARD_SUNKBD=m ++CONFIG_KEYBOARD_LKKBD=m ++CONFIG_KEYBOARD_XTKBD=m ++CONFIG_KEYBOARD_NEWTON=m ++# CONFIG_KEYBOARD_STOWAWAY is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_SERIAL=m ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++CONFIG_MOUSE_INPORT=m ++# CONFIG_MOUSE_ATIXL is not set ++CONFIG_MOUSE_LOGIBM=m ++CONFIG_MOUSE_PC110PAD=m ++CONFIG_MOUSE_VSXXXAA=m ++CONFIG_INPUT_JOYSTICK=y ++CONFIG_JOYSTICK_ANALOG=m ++CONFIG_JOYSTICK_A3D=m ++CONFIG_JOYSTICK_ADI=m ++CONFIG_JOYSTICK_COBRA=m ++CONFIG_JOYSTICK_GF2K=m ++CONFIG_JOYSTICK_GRIP=m ++CONFIG_JOYSTICK_GRIP_MP=m ++CONFIG_JOYSTICK_GUILLEMOT=m ++CONFIG_JOYSTICK_INTERACT=m ++CONFIG_JOYSTICK_SIDEWINDER=m ++CONFIG_JOYSTICK_TMDC=m ++CONFIG_JOYSTICK_IFORCE=m ++CONFIG_JOYSTICK_IFORCE_USB=y ++CONFIG_JOYSTICK_IFORCE_232=y ++CONFIG_JOYSTICK_WARRIOR=m ++CONFIG_JOYSTICK_MAGELLAN=m ++CONFIG_JOYSTICK_SPACEORB=m ++CONFIG_JOYSTICK_SPACEBALL=m ++CONFIG_JOYSTICK_STINGER=m ++CONFIG_JOYSTICK_TWIDJOY=m ++# CONFIG_JOYSTICK_ZHENHUA is not set ++CONFIG_JOYSTICK_JOYDUMP=m ++# CONFIG_JOYSTICK_XPAD is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_AD7879_I2C is not set ++# CONFIG_TOUCHSCREEN_AD7879 is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++CONFIG_TOUCHSCREEN_GUNZE=m ++CONFIG_TOUCHSCREEN_ELO=m ++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set ++CONFIG_TOUCHSCREEN_MTOUCH=m ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++CONFIG_TOUCHSCREEN_MK712=m ++# CONFIG_TOUCHSCREEN_HTCPEN is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_WM97XX is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_TOUCHSCREEN_TSC2007 is not set ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_PCSPKR=m ++# CONFIG_INPUT_ATI_REMOTE is not set ++# CONFIG_INPUT_ATI_REMOTE2 is not set ++# CONFIG_INPUT_KEYSPAN_REMOTE is not set ++# CONFIG_INPUT_POWERMATE is not set ++# CONFIG_INPUT_YEALINK is not set ++# CONFIG_INPUT_CM109 is not set ++CONFIG_INPUT_UINPUT=m ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++# CONFIG_SERIO_I8042 is not set ++CONFIG_SERIO_SERPORT=m ++CONFIG_SERIO_PCIPS2=m ++CONFIG_SERIO_LIBPS2=y ++CONFIG_SERIO_RAW=m ++CONFIG_GAMEPORT=m ++CONFIG_GAMEPORT_NS558=m ++CONFIG_GAMEPORT_L4=m ++CONFIG_GAMEPORT_EMU10K1=m ++CONFIG_GAMEPORT_FM801=m ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++CONFIG_SERIAL_NONSTANDARD=y ++# CONFIG_COMPUTONE is not set ++# CONFIG_ROCKETPORT is not set ++# CONFIG_CYCLADES is not set ++# CONFIG_DIGIEPCA is not set ++# CONFIG_MOXA_INTELLIO is not set ++# CONFIG_MOXA_SMARTIO is not set ++# CONFIG_ISI is not set ++# CONFIG_SYNCLINKMP is not set ++# CONFIG_SYNCLINK_GT is not set ++# CONFIG_N_HDLC is not set ++# CONFIG_RISCOM8 is not set ++# CONFIG_SPECIALIX is not set ++# CONFIG_SX is not set ++# CONFIG_RIO is not set ++# CONFIG_STALDRV is not set ++# CONFIG_NOZOMI is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++CONFIG_SERIAL_8250_CONSOLE=y ++# CONFIG_SERIAL_8250_PCI is not set ++# CONFIG_SERIAL_8250_PNP is not set ++CONFIG_SERIAL_8250_CS=m ++CONFIG_SERIAL_8250_NR_UARTS=16 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++CONFIG_SERIAL_8250_EXTENDED=y ++CONFIG_SERIAL_8250_MANY_PORTS=y ++CONFIG_SERIAL_8250_FOURPORT=y ++# CONFIG_SERIAL_8250_ACCENT is not set ++# CONFIG_SERIAL_8250_BOCA is not set ++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set ++CONFIG_SERIAL_8250_HUB6=m ++CONFIG_SERIAL_8250_SHARE_IRQ=y ++# CONFIG_SERIAL_8250_DETECT_IRQ is not set ++CONFIG_SERIAL_8250_RSA=y ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++CONFIG_UNIX98_PTYS=y ++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=16 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set ++# CONFIG_DTLK is not set ++# CONFIG_R3964 is not set ++# CONFIG_APPLICOM is not set ++ ++# ++# PCMCIA character devices ++# ++# CONFIG_SYNCLINK_CS is not set ++# CONFIG_CARDMAN_4000 is not set ++# CONFIG_CARDMAN_4040 is not set ++# CONFIG_IPWIRELESS is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_DEVPORT=y ++CONFIG_I2C=m ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=m ++CONFIG_I2C_HELPER_AUTO=y ++CONFIG_I2C_ALGOBIT=m ++CONFIG_I2C_ALGOPCA=m ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++CONFIG_I2C_ALI1535=m ++CONFIG_I2C_ALI1563=m ++CONFIG_I2C_ALI15X3=m ++CONFIG_I2C_AMD756=m ++CONFIG_I2C_AMD8111=m ++CONFIG_I2C_I801=m ++# CONFIG_I2C_ISCH is not set ++CONFIG_I2C_PIIX4=m ++CONFIG_I2C_NFORCE2=m ++CONFIG_I2C_SIS5595=m ++CONFIG_I2C_SIS630=m ++CONFIG_I2C_SIS96X=m ++CONFIG_I2C_VIA=m ++CONFIG_I2C_VIAPRO=m ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_OCORES=m ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++CONFIG_I2C_PARPORT_LIGHT=m ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Graphics adapter I2C/DDC channel drivers ++# ++CONFIG_I2C_VOODOO3=m ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_ELEKTOR is not set ++CONFIG_I2C_PCA_ISA=m ++# CONFIG_I2C_PCA_PLATFORM is not set ++CONFIG_I2C_STUB=m ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++CONFIG_SENSORS_PCF8574=m ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++CONFIG_SENSORS_MAX6875=m ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++CONFIG_SOFT_WATCHDOG=m ++# CONFIG_ALIM7101_WDT is not set ++ ++# ++# ISA-based Watchdog Cards ++# ++CONFIG_PCWATCHDOG=m ++CONFIG_MIXCOMWD=m ++CONFIG_WDT=m ++ ++# ++# PCI-based Watchdog Cards ++# ++CONFIG_PCIPCWATCHDOG=m ++CONFIG_WDTPCI=m ++CONFIG_WDT_501_PCI=y ++ ++# ++# USB-based Watchdog Cards ++# ++CONFIG_USBPCWATCHDOG=m ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++CONFIG_SSB=m ++CONFIG_SSB_SPROM=y ++CONFIG_SSB_PCIHOST_POSSIBLE=y ++CONFIG_SSB_PCIHOST=y ++# CONFIG_SSB_B43_PCI_BRIDGE is not set ++CONFIG_SSB_PCMCIAHOST_POSSIBLE=y ++# CONFIG_SSB_PCMCIAHOST is not set ++# CONFIG_SSB_SILENT is not set ++# CONFIG_SSB_DEBUG is not set ++CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y ++CONFIG_SSB_DRIVER_PCICORE=y ++# CONFIG_SSB_DRIVER_MIPS is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++CONFIG_VIDEO_DEV=m ++CONFIG_VIDEO_V4L2_COMMON=m ++CONFIG_VIDEO_ALLOW_V4L1=y ++CONFIG_VIDEO_V4L1_COMPAT=y ++CONFIG_DVB_CORE=m ++CONFIG_VIDEO_MEDIA=m ++ ++# ++# Multimedia drivers ++# ++CONFIG_VIDEO_SAA7146=m ++CONFIG_VIDEO_SAA7146_VV=m ++# CONFIG_MEDIA_ATTACH is not set ++CONFIG_MEDIA_TUNER=m ++# CONFIG_MEDIA_TUNER_CUSTOMISE is not set ++CONFIG_MEDIA_TUNER_SIMPLE=m ++CONFIG_MEDIA_TUNER_TDA8290=m ++CONFIG_MEDIA_TUNER_TDA827X=m ++CONFIG_MEDIA_TUNER_TDA18271=m ++CONFIG_MEDIA_TUNER_TDA9887=m ++CONFIG_MEDIA_TUNER_TEA5761=m ++CONFIG_MEDIA_TUNER_TEA5767=m ++CONFIG_MEDIA_TUNER_MT20XX=m ++CONFIG_MEDIA_TUNER_MT2060=m ++CONFIG_MEDIA_TUNER_XC2028=m ++CONFIG_MEDIA_TUNER_XC5000=m ++CONFIG_MEDIA_TUNER_MXL5005S=m ++CONFIG_MEDIA_TUNER_MC44S803=m ++CONFIG_VIDEO_V4L2=m ++CONFIG_VIDEO_V4L1=m ++CONFIG_VIDEOBUF_GEN=m ++CONFIG_VIDEOBUF_DMA_SG=m ++CONFIG_VIDEOBUF_VMALLOC=m ++CONFIG_VIDEOBUF_DVB=m ++CONFIG_VIDEO_BTCX=m ++CONFIG_VIDEO_IR=m ++CONFIG_VIDEO_TVEEPROM=m ++CONFIG_VIDEO_TUNER=m ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++CONFIG_VIDEO_HELPER_CHIPS_AUTO=y ++CONFIG_VIDEO_IR_I2C=m ++CONFIG_VIDEO_TVAUDIO=m ++CONFIG_VIDEO_TDA7432=m ++CONFIG_VIDEO_TDA9840=m ++CONFIG_VIDEO_TEA6415C=m ++CONFIG_VIDEO_TEA6420=m ++CONFIG_VIDEO_MSP3400=m ++CONFIG_VIDEO_CS53L32A=m ++CONFIG_VIDEO_WM8775=m ++CONFIG_VIDEO_SAA6588=m ++CONFIG_VIDEO_BT819=m ++CONFIG_VIDEO_BT856=m ++CONFIG_VIDEO_BT866=m ++CONFIG_VIDEO_KS0127=m ++CONFIG_VIDEO_SAA7110=m ++CONFIG_VIDEO_SAA711X=m ++CONFIG_VIDEO_TVP5150=m ++CONFIG_VIDEO_VPX3220=m ++CONFIG_VIDEO_CX25840=m ++CONFIG_VIDEO_CX2341X=m ++CONFIG_VIDEO_SAA7185=m ++CONFIG_VIDEO_ADV7170=m ++CONFIG_VIDEO_ADV7175=m ++CONFIG_VIDEO_VIVI=m ++CONFIG_VIDEO_BT848=m ++CONFIG_VIDEO_BT848_DVB=y ++CONFIG_VIDEO_PMS=m ++CONFIG_VIDEO_CPIA=m ++CONFIG_VIDEO_CPIA_USB=m ++CONFIG_VIDEO_CPIA2=m ++CONFIG_VIDEO_SAA5246A=m ++CONFIG_VIDEO_SAA5249=m ++CONFIG_VIDEO_STRADIS=m ++CONFIG_VIDEO_ZORAN=m ++CONFIG_VIDEO_ZORAN_DC30=m ++CONFIG_VIDEO_ZORAN_ZR36060=m ++CONFIG_VIDEO_ZORAN_BUZ=m ++CONFIG_VIDEO_ZORAN_DC10=m ++CONFIG_VIDEO_ZORAN_LML33=m ++CONFIG_VIDEO_ZORAN_LML33R10=m ++CONFIG_VIDEO_ZORAN_AVS6EYES=m ++CONFIG_VIDEO_SAA7134=m ++CONFIG_VIDEO_SAA7134_ALSA=m ++CONFIG_VIDEO_SAA7134_DVB=m ++CONFIG_VIDEO_MXB=m ++CONFIG_VIDEO_HEXIUM_ORION=m ++CONFIG_VIDEO_HEXIUM_GEMINI=m ++CONFIG_VIDEO_CX88=m ++CONFIG_VIDEO_CX88_ALSA=m ++CONFIG_VIDEO_CX88_BLACKBIRD=m ++CONFIG_VIDEO_CX88_DVB=m ++CONFIG_VIDEO_CX88_MPEG=m ++CONFIG_VIDEO_CX88_VP3054=m ++# CONFIG_VIDEO_CX23885 is not set ++# CONFIG_VIDEO_AU0828 is not set ++# CONFIG_VIDEO_IVTV is not set ++# CONFIG_VIDEO_CX18 is not set ++# CONFIG_VIDEO_CAFE_CCIC is not set ++# CONFIG_SOC_CAMERA is not set ++CONFIG_V4L_USB_DRIVERS=y ++# CONFIG_USB_VIDEO_CLASS is not set ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++# CONFIG_USB_GSPCA is not set ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_PVRUSB2_SYSFS=y ++CONFIG_VIDEO_PVRUSB2_DVB=y ++# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set ++# CONFIG_VIDEO_HDPVR is not set ++CONFIG_VIDEO_EM28XX=m ++# CONFIG_VIDEO_EM28XX_ALSA is not set ++# CONFIG_VIDEO_EM28XX_DVB is not set ++# CONFIG_VIDEO_CX231XX is not set ++# CONFIG_VIDEO_USBVISION is not set ++CONFIG_VIDEO_USBVIDEO=m ++CONFIG_USB_VICAM=m ++CONFIG_USB_IBMCAM=m ++CONFIG_USB_KONICAWC=m ++CONFIG_USB_QUICKCAM_MESSENGER=m ++CONFIG_USB_ET61X251=m ++CONFIG_VIDEO_OVCAMCHIP=m ++# CONFIG_USB_W9968CF is not set ++CONFIG_USB_OV511=m ++CONFIG_USB_SE401=m ++CONFIG_USB_SN9C102=m ++CONFIG_USB_STV680=m ++CONFIG_USB_ZC0301=m ++CONFIG_USB_PWC=m ++# CONFIG_USB_PWC_DEBUG is not set ++CONFIG_USB_PWC_INPUT_EVDEV=y ++# CONFIG_USB_ZR364XX is not set ++# CONFIG_USB_STKWEBCAM is not set ++# CONFIG_USB_S2255 is not set ++CONFIG_RADIO_ADAPTERS=y ++CONFIG_RADIO_CADET=m ++CONFIG_RADIO_RTRACK=m ++CONFIG_RADIO_RTRACK2=m ++CONFIG_RADIO_AZTECH=m ++CONFIG_RADIO_GEMTEK=m ++CONFIG_RADIO_GEMTEK_PCI=m ++CONFIG_RADIO_MAXIRADIO=m ++CONFIG_RADIO_MAESTRO=m ++CONFIG_RADIO_SF16FMI=m ++CONFIG_RADIO_SF16FMR2=m ++CONFIG_RADIO_TERRATEC=m ++CONFIG_RADIO_TRUST=m ++CONFIG_RADIO_TYPHOON=m ++CONFIG_RADIO_TYPHOON_PROC_FS=y ++CONFIG_RADIO_ZOLTRIX=m ++CONFIG_USB_DSBR=m ++# CONFIG_USB_SI470X is not set ++# CONFIG_USB_MR800 is not set ++# CONFIG_RADIO_TEA5764 is not set ++# CONFIG_DVB_DYNAMIC_MINORS is not set ++CONFIG_DVB_CAPTURE_DRIVERS=y ++ ++# ++# Supported SAA7146 based PCI Adapters ++# ++CONFIG_TTPCI_EEPROM=m ++CONFIG_DVB_AV7110=m ++CONFIG_DVB_AV7110_OSD=y ++# CONFIG_DVB_BUDGET_CORE is not set ++ ++# ++# Supported USB Adapters ++# ++CONFIG_DVB_USB=m ++# CONFIG_DVB_USB_DEBUG is not set ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y ++CONFIG_DVB_USB_DIBUSB_MC=m ++# CONFIG_DVB_USB_DIB0700 is not set ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_CXUSB=m ++# CONFIG_DVB_USB_M920X is not set ++# CONFIG_DVB_USB_GL861 is not set ++# CONFIG_DVB_USB_AU6610 is not set ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_VP7045=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++# CONFIG_DVB_USB_TTUSB2 is not set ++CONFIG_DVB_USB_DTT200U=m ++# CONFIG_DVB_USB_OPERA1 is not set ++# CONFIG_DVB_USB_AF9005 is not set ++# CONFIG_DVB_USB_DW2102 is not set ++# CONFIG_DVB_USB_CINERGY_T2 is not set ++# CONFIG_DVB_USB_ANYSEE is not set ++# CONFIG_DVB_USB_DTV5100 is not set ++# CONFIG_DVB_USB_AF9015 is not set ++# CONFIG_DVB_USB_CE6230 is not set ++CONFIG_DVB_TTUSB_BUDGET=m ++CONFIG_DVB_TTUSB_DEC=m ++# CONFIG_DVB_SIANO_SMS1XXX is not set ++ ++# ++# Supported FlexCopII (B2C2) Adapters ++# ++CONFIG_DVB_B2C2_FLEXCOP=m ++CONFIG_DVB_B2C2_FLEXCOP_PCI=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m ++# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set ++ ++# ++# Supported BT878 Adapters ++# ++CONFIG_DVB_BT8XX=m ++ ++# ++# Supported Pluto2 Adapters ++# ++CONFIG_DVB_PLUTO2=m ++ ++# ++# Supported SDMC DM1105 Adapters ++# ++# CONFIG_DVB_DM1105 is not set ++ ++# ++# Supported DVB Frontends ++# ++# CONFIG_DVB_FE_CUSTOMISE is not set ++CONFIG_DVB_CX24110=m ++CONFIG_DVB_CX24123=m ++CONFIG_DVB_MT312=m ++CONFIG_DVB_ZL10036=m ++CONFIG_DVB_S5H1420=m ++CONFIG_DVB_STV0288=m ++CONFIG_DVB_STB6000=m ++CONFIG_DVB_STV0299=m ++CONFIG_DVB_TDA8083=m ++CONFIG_DVB_TDA10086=m ++CONFIG_DVB_VES1X93=m ++CONFIG_DVB_TUNER_ITD1000=m ++CONFIG_DVB_TUNER_CX24113=m ++CONFIG_DVB_TDA826X=m ++CONFIG_DVB_CX24116=m ++CONFIG_DVB_SP8870=m ++CONFIG_DVB_SP887X=m ++CONFIG_DVB_CX22700=m ++CONFIG_DVB_CX22702=m ++CONFIG_DVB_L64781=m ++CONFIG_DVB_TDA1004X=m ++CONFIG_DVB_NXT6000=m ++CONFIG_DVB_MT352=m ++CONFIG_DVB_ZL10353=m ++CONFIG_DVB_DIB3000MB=m ++CONFIG_DVB_DIB3000MC=m ++CONFIG_DVB_DIB7000P=m ++CONFIG_DVB_TDA10048=m ++CONFIG_DVB_VES1820=m ++CONFIG_DVB_STV0297=m ++CONFIG_DVB_NXT200X=m ++CONFIG_DVB_OR51211=m ++CONFIG_DVB_OR51132=m ++CONFIG_DVB_BCM3510=m ++CONFIG_DVB_LGDT330X=m ++CONFIG_DVB_LGDT3305=m ++CONFIG_DVB_S5H1409=m ++CONFIG_DVB_S5H1411=m ++CONFIG_DVB_PLL=m ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_LNBP21=m ++CONFIG_DVB_ISL6405=m ++CONFIG_DVB_ISL6421=m ++CONFIG_DVB_LGS8GL5=m ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++CONFIG_DRM=m ++CONFIG_DRM_TDFX=m ++CONFIG_DRM_R128=m ++CONFIG_DRM_RADEON=m ++CONFIG_DRM_MGA=m ++CONFIG_DRM_VIA=m ++CONFIG_DRM_SAVAGE=m ++CONFIG_VGASTATE=m ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++CONFIG_FIRMWARE_EDID=y ++CONFIG_FB_DDC=m ++CONFIG_FB_BOOT_VESA_SUPPORT=y ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++CONFIG_FB_SYS_FILLRECT=m ++CONFIG_FB_SYS_COPYAREA=m ++CONFIG_FB_SYS_IMAGEBLIT=m ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++CONFIG_FB_SYS_FOPS=m ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++CONFIG_FB_BACKLIGHT=y ++CONFIG_FB_MODE_HELPERS=y ++CONFIG_FB_TILEBLITTING=y ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_CIRRUS=m ++CONFIG_FB_PM2=m ++CONFIG_FB_PM2_FIFO_DISCONNECT=y ++CONFIG_FB_CYBER2000=m ++# CONFIG_FB_ASILIANT is not set ++# CONFIG_FB_IMSTT is not set ++# CONFIG_FB_UVESA is not set ++CONFIG_FB_S1D13XXX=m ++CONFIG_FB_NVIDIA=m ++CONFIG_FB_NVIDIA_I2C=y ++# CONFIG_FB_NVIDIA_DEBUG is not set ++CONFIG_FB_NVIDIA_BACKLIGHT=y ++# CONFIG_FB_RIVA is not set ++CONFIG_FB_MATROX=m ++CONFIG_FB_MATROX_MILLENIUM=y ++CONFIG_FB_MATROX_MYSTIQUE=y ++CONFIG_FB_MATROX_G=y ++CONFIG_FB_MATROX_I2C=m ++CONFIG_FB_MATROX_MAVEN=m ++CONFIG_FB_MATROX_MULTIHEAD=y ++CONFIG_FB_RADEON=m ++CONFIG_FB_RADEON_I2C=y ++CONFIG_FB_RADEON_BACKLIGHT=y ++# CONFIG_FB_RADEON_DEBUG is not set ++CONFIG_FB_ATY128=m ++CONFIG_FB_ATY128_BACKLIGHT=y ++CONFIG_FB_ATY=m ++CONFIG_FB_ATY_CT=y ++CONFIG_FB_ATY_GENERIC_LCD=y ++CONFIG_FB_ATY_GX=y ++CONFIG_FB_ATY_BACKLIGHT=y ++# CONFIG_FB_S3 is not set ++CONFIG_FB_SAVAGE=m ++CONFIG_FB_SAVAGE_I2C=y ++# CONFIG_FB_SAVAGE_ACCEL is not set ++CONFIG_FB_SIS=y ++CONFIG_FB_SIS_300=y ++CONFIG_FB_SIS_315=y ++# CONFIG_FB_VIA is not set ++CONFIG_FB_NEOMAGIC=m ++CONFIG_FB_KYRO=m ++CONFIG_FB_3DFX=m ++# CONFIG_FB_3DFX_ACCEL is not set ++CONFIG_FB_3DFX_I2C=y ++CONFIG_FB_VOODOO1=m ++# CONFIG_FB_VT8623 is not set ++CONFIG_FB_TRIDENT=m ++# CONFIG_FB_ARK is not set ++# CONFIG_FB_PM3 is not set ++# CONFIG_FB_CARMINE is not set ++# CONFIG_FB_SM7XX is not set ++CONFIG_FB_VIRTUAL=m ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_FB_BROADSHEET is not set ++CONFIG_BACKLIGHT_LCD_SUPPORT=y ++# CONFIG_LCD_CLASS_DEVICE is not set ++CONFIG_BACKLIGHT_CLASS_DEVICE=y ++CONFIG_BACKLIGHT_GENERIC=y ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++# CONFIG_MDA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++# CONFIG_LOGO is not set ++CONFIG_SOUND=m ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=m ++CONFIG_SND_TIMER=m ++CONFIG_SND_PCM=m ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_PCM_OSS_PLUGINS=y ++CONFIG_SND_SEQUENCER_OSS=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_VMASTER=y ++CONFIG_SND_AC97_CODEC=m ++# CONFIG_SND_DRIVERS is not set ++CONFIG_SND_PCI=y ++# CONFIG_SND_AD1889 is not set ++# CONFIG_SND_ALS300 is not set ++# CONFIG_SND_ALI5451 is not set ++# CONFIG_SND_ATIIXP is not set ++# CONFIG_SND_ATIIXP_MODEM is not set ++# CONFIG_SND_AU8810 is not set ++# CONFIG_SND_AU8820 is not set ++# CONFIG_SND_AU8830 is not set ++# CONFIG_SND_AW2 is not set ++# CONFIG_SND_AZT3328 is not set ++# CONFIG_SND_BT87X is not set ++# CONFIG_SND_CA0106 is not set ++# CONFIG_SND_CMIPCI is not set ++# CONFIG_SND_OXYGEN is not set ++# CONFIG_SND_CS4281 is not set ++# CONFIG_SND_CS46XX is not set ++CONFIG_SND_CS5535AUDIO=m ++# CONFIG_SND_DARLA20 is not set ++# CONFIG_SND_GINA20 is not set ++# CONFIG_SND_LAYLA20 is not set ++# CONFIG_SND_DARLA24 is not set ++# CONFIG_SND_GINA24 is not set ++# CONFIG_SND_LAYLA24 is not set ++# CONFIG_SND_MONA is not set ++# CONFIG_SND_MIA is not set ++# CONFIG_SND_ECHO3G is not set ++# CONFIG_SND_INDIGO is not set ++# CONFIG_SND_INDIGOIO is not set ++# CONFIG_SND_INDIGODJ is not set ++# CONFIG_SND_INDIGOIOX is not set ++# CONFIG_SND_INDIGODJX is not set ++# CONFIG_SND_EMU10K1 is not set ++# CONFIG_SND_EMU10K1X is not set ++# CONFIG_SND_ENS1370 is not set ++# CONFIG_SND_ENS1371 is not set ++# CONFIG_SND_ES1938 is not set ++# CONFIG_SND_ES1968 is not set ++# CONFIG_SND_FM801 is not set ++# CONFIG_SND_HDA_INTEL is not set ++# CONFIG_SND_HDSP is not set ++# CONFIG_SND_HDSPM is not set ++# CONFIG_SND_HIFIER is not set ++# CONFIG_SND_ICE1712 is not set ++# CONFIG_SND_ICE1724 is not set ++# CONFIG_SND_INTEL8X0 is not set ++# CONFIG_SND_INTEL8X0M is not set ++# CONFIG_SND_KORG1212 is not set ++# CONFIG_SND_MAESTRO3 is not set ++# CONFIG_SND_MIXART is not set ++# CONFIG_SND_NM256 is not set ++# CONFIG_SND_PCXHR is not set ++# CONFIG_SND_RIPTIDE is not set ++# CONFIG_SND_RME32 is not set ++# CONFIG_SND_RME96 is not set ++# CONFIG_SND_RME9652 is not set ++# CONFIG_SND_SONICVIBES is not set ++# CONFIG_SND_TRIDENT is not set ++# CONFIG_SND_VIA82XX is not set ++# CONFIG_SND_VIA82XX_MODEM is not set ++# CONFIG_SND_VIRTUOSO is not set ++# CONFIG_SND_VX222 is not set ++# CONFIG_SND_YMFPCI is not set ++# CONFIG_SND_MIPS is not set ++# CONFIG_SND_USB is not set ++# CONFIG_SND_PCMCIA is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_AC97_BUS=m ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++# CONFIG_HID_DEBUG is not set ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++CONFIG_USB_HIDDEV=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_DRAGONRISE_FF is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SONY is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_GREENASIA_FF is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++CONFIG_USB_ARCH_HAS_EHCI=y ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++# CONFIG_USB_DEVICE_CLASS is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_SUSPEND is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++CONFIG_USB_MON=y ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++# CONFIG_USB_EHCI_TT_NEWSCHED is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_UHCI_HCD=m ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_WHCI_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++ ++# ++# USB Device Class drivers ++# ++CONFIG_USB_ACM=m ++CONFIG_USB_PRINTER=m ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++CONFIG_USB_STORAGE_DATAFAB=y ++CONFIG_USB_STORAGE_FREECOM=y ++CONFIG_USB_STORAGE_ISD200=y ++CONFIG_USB_STORAGE_USBAT=y ++CONFIG_USB_STORAGE_SDDR09=y ++CONFIG_USB_STORAGE_SDDR55=y ++CONFIG_USB_STORAGE_JUMPSHOT=y ++CONFIG_USB_STORAGE_ALAUDA=y ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++CONFIG_USB_MDC800=m ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=m ++CONFIG_USB_EZUSB=y ++CONFIG_USB_SERIAL_GENERIC=y ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++CONFIG_USB_SERIAL_ARK3116=m ++CONFIG_USB_SERIAL_BELKIN=m ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m ++# CONFIG_USB_SERIAL_CP210X is not set ++CONFIG_USB_SERIAL_CYPRESS_M8=m ++CONFIG_USB_SERIAL_EMPEG=m ++CONFIG_USB_SERIAL_FTDI_SIO=m ++CONFIG_USB_SERIAL_FUNSOFT=m ++CONFIG_USB_SERIAL_VISOR=m ++CONFIG_USB_SERIAL_IPAQ=m ++CONFIG_USB_SERIAL_IR=m ++CONFIG_USB_SERIAL_EDGEPORT=m ++CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_GARMIN=m ++CONFIG_USB_SERIAL_IPW=m ++# CONFIG_USB_SERIAL_IUU is not set ++CONFIG_USB_SERIAL_KEYSPAN_PDA=m ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++CONFIG_USB_SERIAL_KLSI=m ++CONFIG_USB_SERIAL_KOBIL_SCT=m ++CONFIG_USB_SERIAL_MCT_U232=m ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++CONFIG_USB_SERIAL_NAVMAN=m ++CONFIG_USB_SERIAL_PL2303=m ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_QUALCOMM is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++CONFIG_USB_SERIAL_HP4X=m ++CONFIG_USB_SERIAL_SAFE=m ++# CONFIG_USB_SERIAL_SAFE_PADDED is not set ++# CONFIG_USB_SERIAL_SIEMENS_MPI is not set ++CONFIG_USB_SERIAL_SIERRAWIRELESS=m ++# CONFIG_USB_SERIAL_SYMBOL is not set ++CONFIG_USB_SERIAL_TI=m ++CONFIG_USB_SERIAL_CYBERJACK=m ++CONFIG_USB_SERIAL_XIRCOM=m ++CONFIG_USB_SERIAL_OPTION=m ++CONFIG_USB_SERIAL_OMNINET=m ++# CONFIG_USB_SERIAL_OPTICON is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++# CONFIG_USB_ATM is not set ++# CONFIG_USB_GADGET is not set ++ ++# ++# OTG and related infrastructure ++# ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++CONFIG_RTC_DRV_CMOS=y ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++CONFIG_EXT2_FS_XATTR=y ++CONFIG_EXT2_FS_POSIX_ACL=y ++CONFIG_EXT2_FS_SECURITY=y ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++# CONFIG_JBD_DEBUG is not set ++CONFIG_JBD2=m ++# CONFIG_JBD2_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++CONFIG_REISERFS_FS=m ++# CONFIG_REISERFS_CHECK is not set ++# CONFIG_REISERFS_PROC_INFO is not set ++CONFIG_REISERFS_FS_XATTR=y ++CONFIG_REISERFS_FS_POSIX_ACL=y ++CONFIG_REISERFS_FS_SECURITY=y ++CONFIG_JFS_FS=m ++CONFIG_JFS_POSIX_ACL=y ++CONFIG_JFS_SECURITY=y ++# CONFIG_JFS_DEBUG is not set ++# CONFIG_JFS_STATISTICS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++CONFIG_XFS_FS=m ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++# CONFIG_XFS_DEBUG is not set ++# CONFIG_GFS2_FS is not set ++CONFIG_OCFS2_FS=m ++CONFIG_OCFS2_FS_O2CB=m ++CONFIG_OCFS2_FS_STATS=y ++CONFIG_OCFS2_DEBUG_MASKLOG=y ++# CONFIG_OCFS2_DEBUG_FS is not set ++# CONFIG_OCFS2_FS_POSIX_ACL is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++CONFIG_QUOTA=y ++# CONFIG_QUOTA_NETLINK_INTERFACE is not set ++CONFIG_PRINT_QUOTA_WARNING=y ++CONFIG_QUOTA_TREE=m ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_QUOTACTL=y ++CONFIG_AUTOFS_FS=m ++CONFIG_AUTOFS4_FS=m ++CONFIG_FUSE_FS=m ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m ++CONFIG_UDF_NLS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_KCORE=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=m ++CONFIG_MISC_FILESYSTEMS=y ++CONFIG_ADFS_FS=m ++# CONFIG_ADFS_FS_RW is not set ++CONFIG_AFFS_FS=m ++# CONFIG_ECRYPT_FS is not set ++CONFIG_HFS_FS=m ++CONFIG_HFSPLUS_FS=m ++CONFIG_BEFS_FS=m ++# CONFIG_BEFS_DEBUG is not set ++CONFIG_BFS_FS=m ++CONFIG_EFS_FS=m ++CONFIG_CRAMFS=y ++# CONFIG_SQUASHFS is not set ++CONFIG_VXFS_FS=m ++CONFIG_MINIX_FS=m ++# CONFIG_OMFS_FS is not set ++CONFIG_HPFS_FS=m ++CONFIG_QNX4FS_FS=m ++CONFIG_ROMFS_FS=m ++CONFIG_ROMFS_BACKED_BY_BLOCK=y ++# CONFIG_ROMFS_BACKED_BY_MTD is not set ++# CONFIG_ROMFS_BACKED_BY_BOTH is not set ++CONFIG_ROMFS_ON_BLOCK=y ++CONFIG_SYSV_FS=m ++CONFIG_UFS_FS=m ++# CONFIG_UFS_FS_WRITE is not set ++# CONFIG_UFS_DEBUG is not set ++# CONFIG_NILFS2_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_NFSD=m ++CONFIG_NFSD_V2_ACL=y ++CONFIG_NFSD_V3=y ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y ++CONFIG_LOCKD=m ++CONFIG_LOCKD_V4=y ++CONFIG_EXPORTFS=m ++CONFIG_NFS_ACL_SUPPORT=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++CONFIG_SUNRPC_GSS=m ++CONFIG_RPCSEC_GSS_KRB5=m ++CONFIG_RPCSEC_GSS_SPKM3=m ++CONFIG_SMB_FS=m ++# CONFIG_SMB_NLS_DEFAULT is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++# CONFIG_CIFS_WEAK_PW_HASH is not set ++# CONFIG_CIFS_UPCALL is not set ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG2 is not set ++# CONFIG_CIFS_DFS_UPCALL is not set ++# CONFIG_CIFS_EXPERIMENTAL is not set ++CONFIG_NCP_FS=m ++CONFIG_NCPFS_PACKET_SIGNING=y ++CONFIG_NCPFS_IOCTL_LOCKING=y ++CONFIG_NCPFS_STRONG=y ++CONFIG_NCPFS_NFS_NS=y ++CONFIG_NCPFS_OS2_NS=y ++# CONFIG_NCPFS_SMALLDOS is not set ++CONFIG_NCPFS_NLS=y ++CONFIG_NCPFS_EXTRAS=y ++CONFIG_CODA_FS=m ++CONFIG_AFS_FS=m ++# CONFIG_AFS_DEBUG is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_ACORN_PARTITION=y ++# CONFIG_ACORN_PARTITION_CUMANA is not set ++# CONFIG_ACORN_PARTITION_EESOX is not set ++CONFIG_ACORN_PARTITION_ICS=y ++# CONFIG_ACORN_PARTITION_ADFS is not set ++# CONFIG_ACORN_PARTITION_POWERTEC is not set ++CONFIG_ACORN_PARTITION_RISCIX=y ++CONFIG_OSF_PARTITION=y ++CONFIG_AMIGA_PARTITION=y ++CONFIG_ATARI_PARTITION=y ++CONFIG_MAC_PARTITION=y ++CONFIG_MSDOS_PARTITION=y ++CONFIG_BSD_DISKLABEL=y ++CONFIG_MINIX_SUBPARTITION=y ++CONFIG_SOLARIS_X86_PARTITION=y ++CONFIG_UNIXWARE_DISKLABEL=y ++CONFIG_LDM_PARTITION=y ++# CONFIG_LDM_DEBUG is not set ++CONFIG_SGI_PARTITION=y ++CONFIG_ULTRIX_PARTITION=y ++CONFIG_SUN_PARTITION=y ++CONFIG_KARMA_PARTITION=y ++CONFIG_EFI_PARTITION=y ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=m ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=m ++CONFIG_NLS_ISO8859_1=m ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_UNUSED_SYMBOLS=y ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_TRACING_SUPPORT=y ++ ++# ++# Tracers ++# ++# CONFIG_IRQSOFF_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_EVENT_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_TRACE_BRANCH_PROFILING is not set ++# CONFIG_KMEMTRACE is not set ++# CONFIG_WORKQUEUE_TRACER is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++CONFIG_CMDLINE="" ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set ++CONFIG_SECURITY=y ++# CONFIG_SECURITYFS is not set ++CONFIG_SECURITY_NETWORK=y ++CONFIG_SECURITY_NETWORK_XFRM=y ++# CONFIG_SECURITY_PATH is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++# CONFIG_SECURITY_ROOTPLUG is not set ++CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 ++CONFIG_SECURITY_SELINUX=y ++CONFIG_SECURITY_SELINUX_BOOTPARAM=y ++CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 ++CONFIG_SECURITY_SELINUX_DISABLE=y ++CONFIG_SECURITY_SELINUX_DEVELOP=y ++CONFIG_SECURITY_SELINUX_AVC_STATS=y ++CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 ++# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set ++# CONFIG_SECURITY_TOMOYO is not set ++CONFIG_XOR_BLOCKS=m ++CONFIG_ASYNC_CORE=m ++CONFIG_ASYNC_MEMCPY=m ++CONFIG_ASYNC_XOR=m ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=m ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=m ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=m ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=m ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=m ++CONFIG_CRYPTO_MD4=m ++CONFIG_CRYPTO_MD5=y ++CONFIG_CRYPTO_MICHAEL_MIC=m ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=m ++CONFIG_CRYPTO_SHA256=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_WP512=m ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=m ++CONFIG_CRYPTO_ANUBIS=m ++CONFIG_CRYPTO_ARC4=m ++CONFIG_CRYPTO_BLOWFISH=m ++# CONFIG_CRYPTO_CAMELLIA is not set ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_CAST6=m ++CONFIG_CRYPTO_DES=m ++# CONFIG_CRYPTO_FCRYPT is not set ++CONFIG_CRYPTO_KHAZAD=m ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++CONFIG_CRYPTO_SERPENT=m ++CONFIG_CRYPTO_TEA=m ++CONFIG_CRYPTO_TWOFISH=m ++CONFIG_CRYPTO_TWOFISH_COMMON=m ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=m ++# CONFIG_CRYPTO_ZLIB is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_CRYPTO_DEV_HIFN_795X is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=m ++CONFIG_CRC16=m ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=m ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=m ++CONFIG_AUDIT_GENERIC=y ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=m ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_TEXTSEARCH=y ++CONFIG_TEXTSEARCH_KMP=m ++CONFIG_TEXTSEARCH_BM=m ++CONFIG_TEXTSEARCH_FSM=m ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y ++CONFIG_NLATTR=y +diff -Nur linux-2.6.30/arch/mips/configs/yeeloong2f_defconfig rt4ls/arch/mips/configs/yeeloong2f_defconfig +--- linux-2.6.30/arch/mips/configs/yeeloong2f_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/configs/yeeloong2f_defconfig 2009-06-12 16:27:08.290407950 +0200 +@@ -0,0 +1,2711 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.30-rc8 ++# Wed Jun 10 22:18:32 2009 ++# ++CONFIG_MIPS=y ++ ++# ++# Machine selection ++# ++# CONFIG_MACH_ALCHEMY is not set ++# CONFIG_BASLER_EXCITE is not set ++# CONFIG_BCM47XX is not set ++# CONFIG_MIPS_COBALT is not set ++# CONFIG_MACH_DECSTATION is not set ++# CONFIG_MACH_JAZZ is not set ++# CONFIG_LASAT is not set ++CONFIG_MACH_LOONGSON=y ++# CONFIG_MIPS_MALTA is not set ++# CONFIG_MIPS_SIM is not set ++# CONFIG_NEC_MARKEINS is not set ++# CONFIG_MACH_VR41XX is not set ++# CONFIG_NXP_STB220 is not set ++# CONFIG_NXP_STB225 is not set ++# CONFIG_PNX8550_JBS is not set ++# CONFIG_PNX8550_STB810 is not set ++# CONFIG_PMC_MSP is not set ++# CONFIG_PMC_YOSEMITE is not set ++# CONFIG_SGI_IP22 is not set ++# CONFIG_SGI_IP27 is not set ++# CONFIG_SGI_IP28 is not set ++# CONFIG_SGI_IP32 is not set ++# CONFIG_SIBYTE_CRHINE is not set ++# CONFIG_SIBYTE_CARMEL is not set ++# CONFIG_SIBYTE_CRHONE is not set ++# CONFIG_SIBYTE_RHONE is not set ++# CONFIG_SIBYTE_SWARM is not set ++# CONFIG_SIBYTE_LITTLESUR is not set ++# CONFIG_SIBYTE_SENTOSA is not set ++# CONFIG_SIBYTE_BIGSUR is not set ++# CONFIG_SNI_RM is not set ++# CONFIG_MACH_TX39XX is not set ++# CONFIG_MACH_TX49XX is not set ++# CONFIG_MIKROTIK_RB532 is not set ++# CONFIG_WR_PPMC is not set ++# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set ++# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set ++CONFIG_ARCH_SPARSEMEM_ENABLE=y ++# CONFIG_LEMOTE_FULOONG2E is not set ++# CONFIG_LEMOTE_FULOONG2F is not set ++CONFIG_LEMOTE_YEELOONG2F=y ++CONFIG_CS5536=y ++CONFIG_SYS_HAS_MACH_PROM_INIT_CMDLINE=y ++CONFIG_CS5536_MFGPT=y ++CONFIG_UCA_SIZE=0x400000 ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_ARCH_SUPPORTS_OPROFILE=y ++CONFIG_GENERIC_FIND_NEXT_BIT=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_TIME=y ++CONFIG_GENERIC_CMOS_UPDATE=y ++CONFIG_SCHED_OMIT_FRAME_POINTER=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_DMA_NONCOHERENT=y ++CONFIG_DMA_NEED_PCI_MAP_STATE=y ++CONFIG_EARLY_PRINTK=y ++CONFIG_SYS_HAS_EARLY_PRINTK=y ++# CONFIG_HOTPLUG_CPU is not set ++CONFIG_I8259=y ++# CONFIG_NO_IOPORT is not set ++CONFIG_GENERIC_ISA_DMA=y ++CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y ++# CONFIG_CPU_BIG_ENDIAN is not set ++CONFIG_CPU_LITTLE_ENDIAN=y ++CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y ++CONFIG_IRQ_CPU=y ++CONFIG_BOOT_ELF32=y ++CONFIG_MIPS_L1_CACHE_SHIFT=5 ++ ++# ++# CPU selection ++# ++# CONFIG_CPU_LOONGSON2E is not set ++CONFIG_CPU_LOONGSON2F=y ++# CONFIG_CPU_MIPS32_R1 is not set ++# CONFIG_CPU_MIPS32_R2 is not set ++# CONFIG_CPU_MIPS64_R1 is not set ++# CONFIG_CPU_MIPS64_R2 is not set ++# CONFIG_CPU_R3000 is not set ++# CONFIG_CPU_TX39XX is not set ++# CONFIG_CPU_VR41XX is not set ++# CONFIG_CPU_R4300 is not set ++# CONFIG_CPU_R4X00 is not set ++# CONFIG_CPU_TX49XX is not set ++# CONFIG_CPU_R5000 is not set ++# CONFIG_CPU_R5432 is not set ++# CONFIG_CPU_R5500 is not set ++# CONFIG_CPU_R6000 is not set ++# CONFIG_CPU_NEVADA is not set ++# CONFIG_CPU_R8000 is not set ++# CONFIG_CPU_R10000 is not set ++# CONFIG_CPU_RM7000 is not set ++# CONFIG_CPU_RM9000 is not set ++# CONFIG_CPU_SB1 is not set ++# CONFIG_CPU_CAVIUM_OCTEON is not set ++CONFIG_CPU_LOONGSON2=y ++CONFIG_SYS_HAS_CPU_LOONGSON2F=y ++CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y ++CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y ++CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y ++CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y ++ ++# ++# Kernel type ++# ++# CONFIG_32BIT is not set ++CONFIG_64BIT=y ++# CONFIG_PAGE_SIZE_4KB is not set ++# CONFIG_PAGE_SIZE_8KB is not set ++CONFIG_PAGE_SIZE_16KB=y ++# CONFIG_PAGE_SIZE_32KB is not set ++# CONFIG_PAGE_SIZE_64KB is not set ++CONFIG_BOARD_SCACHE=y ++CONFIG_MIPS_MT_DISABLED=y ++# CONFIG_MIPS_MT_SMP is not set ++# CONFIG_MIPS_MT_SMTC is not set ++CONFIG_CPU_HAS_WB=y ++CONFIG_CPU_HAS_SYNC=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_CPU_SUPPORTS_HIGHMEM=y ++CONFIG_SYS_SUPPORTS_HIGHMEM=y ++CONFIG_ARCH_FLATMEM_ENABLE=y ++CONFIG_ARCH_POPULATES_NODE_MAP=y ++CONFIG_SELECT_MEMORY_MODEL=y ++# CONFIG_FLATMEM_MANUAL is not set ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++CONFIG_SPARSEMEM_MANUAL=y ++CONFIG_SPARSEMEM=y ++CONFIG_HAVE_MEMORY_PRESENT=y ++CONFIG_SPARSEMEM_STATIC=y ++ ++# ++# Memory hotplug is currently incompatible with Software Suspend ++# ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_PHYS_ADDR_T_64BIT=y ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++CONFIG_HAVE_MLOCK=y ++CONFIG_HAVE_MLOCKED_PAGE_BIT=y ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++# CONFIG_HZ_48 is not set ++# CONFIG_HZ_100 is not set ++# CONFIG_HZ_128 is not set ++CONFIG_HZ_250=y ++# CONFIG_HZ_256 is not set ++# CONFIG_HZ_1000 is not set ++# CONFIG_HZ_1024 is not set ++CONFIG_SYS_SUPPORTS_ARBIT_HZ=y ++CONFIG_HZ=250 ++# CONFIG_PREEMPT_NONE is not set ++CONFIG_PREEMPT_VOLUNTARY=y ++# CONFIG_PREEMPT is not set ++CONFIG_KEXEC=y ++# CONFIG_SECCOMP is not set ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++# CONFIG_TASKSTATS is not set ++CONFIG_AUDIT=y ++ ++# ++# RCU Subsystem ++# ++CONFIG_CLASSIC_RCU=y ++# CONFIG_TREE_RCU is not set ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_PREEMPT_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=15 ++# CONFIG_GROUP_SCHED is not set ++# CONFIG_CGROUPS is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++# CONFIG_NAMESPACES is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_EMBEDDED=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++# CONFIG_STRIP_ASM_SYMS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_PCSPKR_PLATFORM=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_PCI_QUIRKS=y ++CONFIG_COMPAT_BRK=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++CONFIG_PROFILING=y ++CONFIG_TRACEPOINTS=y ++# CONFIG_MARKERS is not set ++CONFIG_OPROFILE=m ++CONFIG_HAVE_OPROFILE=y ++CONFIG_HAVE_SYSCALL_WRAPPERS=y ++# CONFIG_SLOW_WORK is not set ++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++CONFIG_MODVERSIONS=y ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_BLOCK=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++CONFIG_BLOCK_COMPAT=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_PROBE_INITRD_HEADER is not set ++CONFIG_FREEZER=y ++ ++# ++# Bus options (PCI, PCMCIA, EISA, ISA, TC) ++# ++CONFIG_HW_HAS_PCI=y ++CONFIG_PCI=y ++CONFIG_PCI_DOMAINS=y ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++CONFIG_PCI_LEGACY=y ++# CONFIG_PCI_STUB is not set ++# CONFIG_PCI_IOV is not set ++CONFIG_ISA=y ++CONFIG_MMU=y ++# CONFIG_PCCARD is not set ++CONFIG_HOTPLUG_PCI=m ++CONFIG_HOTPLUG_PCI_FAKE=m ++CONFIG_HOTPLUG_PCI_CPCI=y ++CONFIG_HOTPLUG_PCI_SHPC=m ++ ++# ++# Executable file formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++# CONFIG_HAVE_AOUT is not set ++CONFIG_BINFMT_MISC=m ++CONFIG_MIPS32_COMPAT=y ++CONFIG_COMPAT=y ++CONFIG_SYSVIPC_COMPAT=y ++CONFIG_MIPS32_O32=y ++CONFIG_MIPS32_N32=y ++CONFIG_BINFMT_ELF32=y ++ ++# ++# Power management options ++# ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_SLEEP=y ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++CONFIG_HIBERNATION=y ++CONFIG_PM_STD_PARTITION="" ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_TABLE=y ++# CONFIG_CPU_FREQ_DEBUG is not set ++CONFIG_CPU_FREQ_STAT=y ++# CONFIG_CPU_FREQ_STAT_DETAILS is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_GOV_USERSPACE is not set ++# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y ++CONFIG_LOONGSON2F_CPU_FREQ=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++CONFIG_XFRM_USER=m ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_XFRM_IPCOMP=m ++CONFIG_NET_KEY=m ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++CONFIG_NET_IPIP=m ++CONFIG_NET_IPGRE=m ++CONFIG_NET_IPGRE_BROADCAST=y ++CONFIG_IP_MROUTE=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++# CONFIG_ARPD is not set ++CONFIG_SYN_COOKIES=y ++CONFIG_INET_AH=m ++CONFIG_INET_ESP=m ++CONFIG_INET_IPCOMP=m ++CONFIG_INET_XFRM_TUNNEL=m ++CONFIG_INET_TUNNEL=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=m ++CONFIG_INET_XFRM_MODE_TUNNEL=m ++CONFIG_INET_XFRM_MODE_BEET=y ++CONFIG_INET_LRO=y ++CONFIG_INET_DIAG=m ++CONFIG_INET_TCP_DIAG=m ++CONFIG_TCP_CONG_ADVANCED=y ++CONFIG_TCP_CONG_BIC=y ++CONFIG_TCP_CONG_CUBIC=m ++CONFIG_TCP_CONG_WESTWOOD=m ++CONFIG_TCP_CONG_HTCP=m ++CONFIG_TCP_CONG_HSTCP=m ++CONFIG_TCP_CONG_HYBLA=m ++CONFIG_TCP_CONG_VEGAS=m ++CONFIG_TCP_CONG_SCALABLE=m ++CONFIG_TCP_CONG_LP=m ++CONFIG_TCP_CONG_VENO=m ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++CONFIG_DEFAULT_BIC=y ++# CONFIG_DEFAULT_CUBIC is not set ++# CONFIG_DEFAULT_HTCP is not set ++# CONFIG_DEFAULT_VEGAS is not set ++# CONFIG_DEFAULT_WESTWOOD is not set ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="bic" ++# CONFIG_TCP_MD5SIG is not set ++CONFIG_IPV6=m ++CONFIG_IPV6_PRIVACY=y ++# CONFIG_IPV6_ROUTER_PREF is not set ++# CONFIG_IPV6_OPTIMISTIC_DAD is not set ++CONFIG_INET6_AH=m ++CONFIG_INET6_ESP=m ++CONFIG_INET6_IPCOMP=m ++# CONFIG_IPV6_MIP6 is not set ++CONFIG_INET6_XFRM_TUNNEL=m ++CONFIG_INET6_TUNNEL=m ++CONFIG_INET6_XFRM_MODE_TRANSPORT=m ++CONFIG_INET6_XFRM_MODE_TUNNEL=m ++CONFIG_INET6_XFRM_MODE_BEET=m ++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set ++CONFIG_IPV6_SIT=m ++CONFIG_IPV6_NDISC_NODETYPE=y ++CONFIG_IPV6_TUNNEL=m ++# CONFIG_IPV6_MULTIPLE_TABLES is not set ++# CONFIG_IPV6_MROUTE is not set ++# CONFIG_NETLABEL is not set ++CONFIG_NETWORK_SECMARK=y ++CONFIG_NETFILTER=y ++# CONFIG_NETFILTER_DEBUG is not set ++CONFIG_NETFILTER_ADVANCED=y ++CONFIG_BRIDGE_NETFILTER=y ++ ++# ++# Core Netfilter Configuration ++# ++CONFIG_NETFILTER_NETLINK=m ++CONFIG_NETFILTER_NETLINK_QUEUE=m ++CONFIG_NETFILTER_NETLINK_LOG=m ++# CONFIG_NF_CONNTRACK is not set ++# CONFIG_NETFILTER_TPROXY is not set ++CONFIG_NETFILTER_XTABLES=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++# CONFIG_NETFILTER_XT_TARGET_DSCP is not set ++CONFIG_NETFILTER_XT_TARGET_HL=m ++# CONFIG_NETFILTER_XT_TARGET_LED is not set ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set ++# CONFIG_NETFILTER_XT_TARGET_TRACE is not set ++CONFIG_NETFILTER_XT_TARGET_SECMARK=m ++# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set ++# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_DCCP=m ++# CONFIG_NETFILTER_XT_MATCH_DSCP is not set ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set ++CONFIG_NETFILTER_XT_MATCH_HL=m ++# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++# CONFIG_NETFILTER_XT_MATCH_OWNER is not set ++CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++# CONFIG_NETFILTER_XT_MATCH_RECENT is not set ++CONFIG_NETFILTER_XT_MATCH_SCTP=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++# CONFIG_NETFILTER_XT_MATCH_TIME is not set ++# CONFIG_NETFILTER_XT_MATCH_U32 is not set ++CONFIG_IP_VS=m ++# CONFIG_IP_VS_IPV6 is not set ++# CONFIG_IP_VS_DEBUG is not set ++CONFIG_IP_VS_TAB_BITS=12 ++ ++# ++# IPVS transport protocol load balancing support ++# ++CONFIG_IP_VS_PROTO_TCP=y ++CONFIG_IP_VS_PROTO_UDP=y ++CONFIG_IP_VS_PROTO_AH_ESP=y ++CONFIG_IP_VS_PROTO_ESP=y ++CONFIG_IP_VS_PROTO_AH=y ++ ++# ++# IPVS scheduler ++# ++CONFIG_IP_VS_RR=m ++CONFIG_IP_VS_WRR=m ++CONFIG_IP_VS_LC=m ++CONFIG_IP_VS_WLC=m ++CONFIG_IP_VS_LBLC=m ++CONFIG_IP_VS_LBLCR=m ++CONFIG_IP_VS_DH=m ++CONFIG_IP_VS_SH=m ++CONFIG_IP_VS_SED=m ++CONFIG_IP_VS_NQ=m ++ ++# ++# IPVS application helper ++# ++CONFIG_IP_VS_FTP=m ++ ++# ++# IP: Netfilter Configuration ++# ++# CONFIG_NF_DEFRAG_IPV4 is not set ++CONFIG_IP_NF_QUEUE=m ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_ADDRTYPE=m ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_TARGET_LOG=m ++CONFIG_IP_NF_TARGET_ULOG=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++# CONFIG_IP_NF_SECURITY is not set ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++ ++# ++# IPv6: Netfilter Configuration ++# ++CONFIG_IP6_NF_QUEUE=m ++CONFIG_IP6_NF_IPTABLES=m ++CONFIG_IP6_NF_MATCH_AH=m ++CONFIG_IP6_NF_MATCH_EUI64=m ++CONFIG_IP6_NF_MATCH_FRAG=m ++CONFIG_IP6_NF_MATCH_OPTS=m ++CONFIG_IP6_NF_MATCH_HL=m ++CONFIG_IP6_NF_MATCH_IPV6HEADER=m ++# CONFIG_IP6_NF_MATCH_MH is not set ++CONFIG_IP6_NF_MATCH_RT=m ++CONFIG_IP6_NF_TARGET_HL=m ++CONFIG_IP6_NF_TARGET_LOG=m ++CONFIG_IP6_NF_FILTER=m ++CONFIG_IP6_NF_TARGET_REJECT=m ++CONFIG_IP6_NF_MANGLE=m ++CONFIG_IP6_NF_RAW=m ++# CONFIG_IP6_NF_SECURITY is not set ++ ++# ++# DECnet: Netfilter Configuration ++# ++CONFIG_DECNET_NF_GRABULATOR=m ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++# CONFIG_BRIDGE_EBT_IP6 is not set ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_ULOG=m ++# CONFIG_BRIDGE_EBT_NFLOG is not set ++CONFIG_IP_DCCP=m ++CONFIG_INET_DCCP_DIAG=m ++ ++# ++# DCCP CCIDs Configuration (EXPERIMENTAL) ++# ++# CONFIG_IP_DCCP_CCID2_DEBUG is not set ++CONFIG_IP_DCCP_CCID3=y ++# CONFIG_IP_DCCP_CCID3_DEBUG is not set ++CONFIG_IP_DCCP_CCID3_RTO=100 ++CONFIG_IP_DCCP_TFRC_LIB=y ++CONFIG_IP_SCTP=m ++# CONFIG_SCTP_DBG_MSG is not set ++# CONFIG_SCTP_DBG_OBJCNT is not set ++# CONFIG_SCTP_HMAC_NONE is not set ++# CONFIG_SCTP_HMAC_SHA1 is not set ++CONFIG_SCTP_HMAC_MD5=y ++CONFIG_TIPC=m ++CONFIG_TIPC_ADVANCED=y ++CONFIG_TIPC_ZONES=3 ++CONFIG_TIPC_CLUSTERS=1 ++CONFIG_TIPC_NODES=255 ++CONFIG_TIPC_SLAVE_NODES=0 ++CONFIG_TIPC_PORTS=8191 ++CONFIG_TIPC_LOG=0 ++# CONFIG_TIPC_DEBUG is not set ++CONFIG_ATM=y ++CONFIG_ATM_CLIP=y ++# CONFIG_ATM_CLIP_NO_ICMP is not set ++CONFIG_ATM_LANE=m ++CONFIG_ATM_MPOA=m ++CONFIG_ATM_BR2684=m ++# CONFIG_ATM_BR2684_IPFILTER is not set ++CONFIG_STP=m ++CONFIG_BRIDGE=m ++# CONFIG_NET_DSA is not set ++CONFIG_VLAN_8021Q=m ++# CONFIG_VLAN_8021Q_GVRP is not set ++CONFIG_DECNET=m ++# CONFIG_DECNET_ROUTER is not set ++CONFIG_LLC=m ++CONFIG_LLC2=m ++CONFIG_IPX=m ++# CONFIG_IPX_INTERN is not set ++CONFIG_ATALK=m ++CONFIG_DEV_APPLETALK=m ++# CONFIG_COPS is not set ++CONFIG_IPDDP=m ++CONFIG_IPDDP_ENCAP=y ++CONFIG_IPDDP_DECAP=y ++CONFIG_X25=m ++CONFIG_LAPB=m ++CONFIG_ECONET=m ++CONFIG_ECONET_AUNUDP=y ++CONFIG_ECONET_NATIVE=y ++CONFIG_WAN_ROUTER=m ++# CONFIG_PHONET is not set ++CONFIG_NET_SCHED=y ++ ++# ++# Queueing/Scheduling ++# ++CONFIG_NET_SCH_CBQ=m ++CONFIG_NET_SCH_HTB=m ++CONFIG_NET_SCH_HFSC=m ++CONFIG_NET_SCH_ATM=m ++CONFIG_NET_SCH_PRIO=m ++# CONFIG_NET_SCH_MULTIQ is not set ++CONFIG_NET_SCH_RED=m ++CONFIG_NET_SCH_SFQ=m ++CONFIG_NET_SCH_TEQL=m ++CONFIG_NET_SCH_TBF=m ++CONFIG_NET_SCH_GRED=m ++CONFIG_NET_SCH_DSMARK=m ++CONFIG_NET_SCH_NETEM=m ++# CONFIG_NET_SCH_DRR is not set ++CONFIG_NET_SCH_INGRESS=m ++ ++# ++# Classification ++# ++CONFIG_NET_CLS=y ++CONFIG_NET_CLS_BASIC=m ++CONFIG_NET_CLS_TCINDEX=m ++CONFIG_NET_CLS_ROUTE4=m ++CONFIG_NET_CLS_ROUTE=y ++CONFIG_NET_CLS_FW=m ++CONFIG_NET_CLS_U32=m ++CONFIG_CLS_U32_PERF=y ++CONFIG_CLS_U32_MARK=y ++CONFIG_NET_CLS_RSVP=m ++CONFIG_NET_CLS_RSVP6=m ++# CONFIG_NET_CLS_FLOW is not set ++CONFIG_NET_EMATCH=y ++CONFIG_NET_EMATCH_STACK=32 ++CONFIG_NET_EMATCH_CMP=m ++CONFIG_NET_EMATCH_NBYTE=m ++CONFIG_NET_EMATCH_U32=m ++CONFIG_NET_EMATCH_META=m ++CONFIG_NET_EMATCH_TEXT=m ++CONFIG_NET_CLS_ACT=y ++CONFIG_NET_ACT_POLICE=m ++CONFIG_NET_ACT_GACT=m ++CONFIG_GACT_PROB=y ++CONFIG_NET_ACT_MIRRED=m ++CONFIG_NET_ACT_IPT=m ++# CONFIG_NET_ACT_NAT is not set ++CONFIG_NET_ACT_PEDIT=m ++CONFIG_NET_ACT_SIMP=m ++# CONFIG_NET_ACT_SKBEDIT is not set ++CONFIG_NET_CLS_IND=y ++CONFIG_NET_SCH_FIFO=y ++# CONFIG_DCB is not set ++ ++# ++# Network testing ++# ++CONFIG_NET_PKTGEN=m ++# CONFIG_NET_DROP_MONITOR is not set ++CONFIG_HAMRADIO=y ++ ++# ++# Packet Radio protocols ++# ++CONFIG_AX25=m ++# CONFIG_AX25_DAMA_SLAVE is not set ++CONFIG_NETROM=m ++CONFIG_ROSE=m ++ ++# ++# AX.25 network device drivers ++# ++CONFIG_MKISS=m ++CONFIG_6PACK=m ++CONFIG_BPQETHER=m ++CONFIG_BAYCOM_SER_FDX=m ++CONFIG_BAYCOM_SER_HDX=m ++CONFIG_YAM=m ++# CONFIG_CAN is not set ++CONFIG_IRDA=m ++ ++# ++# IrDA protocols ++# ++CONFIG_IRLAN=m ++CONFIG_IRNET=m ++CONFIG_IRCOMM=m ++# CONFIG_IRDA_ULTRA is not set ++ ++# ++# IrDA options ++# ++CONFIG_IRDA_CACHE_LAST_LSAP=y ++CONFIG_IRDA_FAST_RR=y ++CONFIG_IRDA_DEBUG=y ++ ++# ++# Infrared-port device drivers ++# ++ ++# ++# SIR device drivers ++# ++CONFIG_IRTTY_SIR=m ++ ++# ++# Dongle support ++# ++CONFIG_DONGLE=y ++CONFIG_ESI_DONGLE=m ++CONFIG_ACTISYS_DONGLE=m ++CONFIG_TEKRAM_DONGLE=m ++CONFIG_TOIM3232_DONGLE=m ++CONFIG_LITELINK_DONGLE=m ++CONFIG_MA600_DONGLE=m ++CONFIG_GIRBIL_DONGLE=m ++CONFIG_MCP2120_DONGLE=m ++CONFIG_OLD_BELKIN_DONGLE=m ++CONFIG_ACT200L_DONGLE=m ++# CONFIG_KINGSUN_DONGLE is not set ++# CONFIG_KSDAZZLE_DONGLE is not set ++# CONFIG_KS959_DONGLE is not set ++ ++# ++# FIR device drivers ++# ++CONFIG_USB_IRDA=m ++CONFIG_SIGMATEL_FIR=m ++CONFIG_VLSI_FIR=m ++CONFIG_MCS_FIR=m ++CONFIG_BT=m ++CONFIG_BT_L2CAP=m ++CONFIG_BT_SCO=m ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++ ++# ++# Bluetooth device drivers ++# ++# CONFIG_BT_HCIBTUSB is not set ++# CONFIG_BT_HCIBTSDIO is not set ++CONFIG_BT_HCIUART=m ++CONFIG_BT_HCIUART_H4=y ++CONFIG_BT_HCIUART_BCSP=y ++# CONFIG_BT_HCIUART_LL is not set ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIVHCI=m ++CONFIG_AF_RXRPC=m ++# CONFIG_AF_RXRPC_DEBUG is not set ++# CONFIG_RXKAD is not set ++CONFIG_FIB_RULES=y ++CONFIG_WIRELESS=y ++CONFIG_CFG80211=y ++# CONFIG_CFG80211_REG_DEBUG is not set ++CONFIG_WIRELESS_OLD_REGULATORY=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WIRELESS_EXT_SYSFS=y ++# CONFIG_LIB80211 is not set ++CONFIG_MAC80211=y ++ ++# ++# Rate control algorithm selection ++# ++CONFIG_MAC80211_RC_PID=y ++CONFIG_MAC80211_RC_MINSTREL=y ++# CONFIG_MAC80211_RC_DEFAULT_PID is not set ++CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y ++CONFIG_MAC80211_RC_DEFAULT="minstrel" ++# CONFIG_MAC80211_MESH is not set ++# CONFIG_MAC80211_LEDS is not set ++# CONFIG_MAC80211_DEBUGFS is not set ++# CONFIG_MAC80211_DEBUG_MENU is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=m ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_SYS_HYPERVISOR is not set ++CONFIG_CONNECTOR=m ++CONFIG_MTD=m ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=m ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=m ++CONFIG_MTD_BLKDEVS=m ++CONFIG_MTD_BLOCK=m ++# CONFIG_MTD_BLOCK_RO is not set ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=m ++CONFIG_MTD_JEDECPROBE=m ++CONFIG_MTD_GEN_PROBE=m ++# CONFIG_MTD_CFI_ADV_OPTIONS is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_CFI_INTELEXT=m ++CONFIG_MTD_CFI_AMDSTD=m ++CONFIG_MTD_CFI_STAA=m ++CONFIG_MTD_CFI_UTIL=m ++CONFIG_MTD_RAM=m ++CONFIG_MTD_ROM=m ++CONFIG_MTD_ABSENT=m ++ ++# ++# Mapping drivers for chip access ++# ++CONFIG_MTD_COMPLEX_MAPPINGS=y ++CONFIG_MTD_PHYSMAP=m ++CONFIG_MTD_PHYSMAP_COMPAT=y ++CONFIG_MTD_PHYSMAP_START=0x8000000 ++CONFIG_MTD_PHYSMAP_LEN=0 ++CONFIG_MTD_PHYSMAP_BANKWIDTH=2 ++CONFIG_MTD_PCI=m ++# CONFIG_MTD_INTEL_VR_NOR is not set ++CONFIG_MTD_PLATRAM=m ++ ++# ++# Self-contained MTD device drivers ++# ++CONFIG_MTD_PMC551=m ++# CONFIG_MTD_PMC551_BUGFIX is not set ++# CONFIG_MTD_PMC551_DEBUG is not set ++CONFIG_MTD_DATAFLASH=m ++# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set ++# CONFIG_MTD_DATAFLASH_OTP is not set ++CONFIG_MTD_M25P80=m ++CONFIG_M25PXX_USE_FAST_READ=y ++CONFIG_MTD_SLRAM=m ++CONFIG_MTD_PHRAM=m ++CONFIG_MTD_MTDRAM=m ++CONFIG_MTDRAM_TOTAL_SIZE=4096 ++CONFIG_MTDRAM_ERASE_SIZE=128 ++CONFIG_MTD_BLOCK2MTD=m ++ ++# ++# Disk-On-Chip Device Drivers ++# ++CONFIG_MTD_DOC2000=m ++CONFIG_MTD_DOC2001=m ++CONFIG_MTD_DOC2001PLUS=m ++CONFIG_MTD_DOCPROBE=m ++CONFIG_MTD_DOCECC=m ++# CONFIG_MTD_DOCPROBE_ADVANCED is not set ++CONFIG_MTD_DOCPROBE_ADDRESS=0 ++# CONFIG_MTD_NAND is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR flash memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_PNP=y ++CONFIG_PNP_DEBUG_MESSAGES=y ++ ++# ++# Protocols ++# ++CONFIG_ISAPNP=y ++# CONFIG_PNPACPI is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_CPQ_DA is not set ++# CONFIG_BLK_CPQ_CISS_DA is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_CRYPTOLOOP=m ++CONFIG_BLK_DEV_NBD=m ++# CONFIG_BLK_DEV_SX8 is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++# CONFIG_BLK_DEV_XIP is not set ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_CDROM_PKTCDVD_BUFFERS=8 ++# CONFIG_CDROM_PKTCDVD_WCACHE is not set ++CONFIG_ATA_OVER_ETH=m ++# CONFIG_BLK_DEV_HD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_PHANTOM is not set ++# CONFIG_SGI_IOC4 is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_AT25 is not set ++# CONFIG_EEPROM_LEGACY is not set ++CONFIG_EEPROM_93CX6=y ++CONFIG_HAVE_IDE=y ++CONFIG_IDE=y ++ ++# ++# Please see Documentation/ide/ide.txt for help/info on IDE drives ++# ++CONFIG_IDE_XFER_MODE=y ++CONFIG_IDE_TIMINGS=y ++CONFIG_IDE_ATAPI=y ++# CONFIG_BLK_DEV_IDE_SATA is not set ++CONFIG_IDE_GD=y ++CONFIG_IDE_GD_ATA=y ++# CONFIG_IDE_GD_ATAPI is not set ++CONFIG_BLK_DEV_IDECD=m ++CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y ++# CONFIG_BLK_DEV_IDETAPE is not set ++CONFIG_IDE_TASK_IOCTL=y ++CONFIG_IDE_PROC_FS=y ++ ++# ++# IDE chipset support/bugfixes ++# ++# CONFIG_IDE_GENERIC is not set ++# CONFIG_BLK_DEV_PLATFORM is not set ++# CONFIG_BLK_DEV_IDEPNP is not set ++CONFIG_BLK_DEV_IDEDMA_SFF=y ++ ++# ++# PCI IDE chipsets support ++# ++CONFIG_BLK_DEV_IDEPCI=y ++# CONFIG_IDEPCI_PCIBUS_ORDER is not set ++# CONFIG_BLK_DEV_OFFBOARD is not set ++CONFIG_BLK_DEV_GENERIC=y ++# CONFIG_BLK_DEV_OPTI621 is not set ++CONFIG_BLK_DEV_IDEDMA_PCI=y ++# CONFIG_BLK_DEV_AEC62XX is not set ++# CONFIG_BLK_DEV_ALI15X3 is not set ++CONFIG_BLK_DEV_AMD74XX=y ++# CONFIG_BLK_DEV_CMD64X is not set ++# CONFIG_BLK_DEV_TRIFLEX is not set ++# CONFIG_BLK_DEV_CS5520 is not set ++# CONFIG_BLK_DEV_CS5530 is not set ++# CONFIG_BLK_DEV_HPT366 is not set ++# CONFIG_BLK_DEV_JMICRON is not set ++# CONFIG_BLK_DEV_SC1200 is not set ++# CONFIG_BLK_DEV_PIIX is not set ++# CONFIG_BLK_DEV_IT8172 is not set ++# CONFIG_BLK_DEV_IT8213 is not set ++# CONFIG_BLK_DEV_IT821X is not set ++# CONFIG_BLK_DEV_NS87415 is not set ++# CONFIG_BLK_DEV_PDC202XX_OLD is not set ++# CONFIG_BLK_DEV_PDC202XX_NEW is not set ++# CONFIG_BLK_DEV_SVWKS is not set ++# CONFIG_BLK_DEV_SIIMAGE is not set ++# CONFIG_BLK_DEV_SLC90E66 is not set ++# CONFIG_BLK_DEV_TRM290 is not set ++# CONFIG_BLK_DEV_VIA82CXXX is not set ++# CONFIG_BLK_DEV_TC86C001 is not set ++ ++# ++# Other IDE chipsets support ++# ++ ++# ++# Note: most of these also require special kernel boot parameters ++# ++# CONFIG_BLK_DEV_4DRIVES is not set ++# CONFIG_BLK_DEV_ALI14XX is not set ++# CONFIG_BLK_DEV_DTC2278 is not set ++# CONFIG_BLK_DEV_HT6560B is not set ++# CONFIG_BLK_DEV_QD65XX is not set ++# CONFIG_BLK_DEV_UMC8672 is not set ++CONFIG_BLK_DEV_IDEDMA=y ++ ++# ++# SCSI device support ++# ++CONFIG_RAID_ATTRS=m ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++CONFIG_SCSI_NETLINK=y ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++CONFIG_BLK_DEV_SR=m ++CONFIG_BLK_DEV_SR_VENDOR=y ++CONFIG_CHR_DEV_SG=m ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++CONFIG_SCSI_CONSTANTS=y ++CONFIG_SCSI_LOGGING=y ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++CONFIG_SCSI_SPI_ATTRS=m ++CONFIG_SCSI_FC_ATTRS=m ++CONFIG_SCSI_ISCSI_ATTRS=m ++# CONFIG_SCSI_SAS_LIBSAS is not set ++CONFIG_SCSI_SRP_ATTRS=m ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++CONFIG_MD=y ++CONFIG_BLK_DEV_MD=m ++CONFIG_MD_LINEAR=m ++CONFIG_MD_RAID0=m ++CONFIG_MD_RAID1=m ++CONFIG_MD_RAID10=m ++CONFIG_MD_RAID456=m ++CONFIG_MD_RAID6_PQ=m ++CONFIG_MD_MULTIPATH=m ++CONFIG_MD_FAULTY=m ++CONFIG_BLK_DEV_DM=m ++# CONFIG_DM_DEBUG is not set ++CONFIG_DM_CRYPT=m ++CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_MIRROR=m ++CONFIG_DM_ZERO=m ++CONFIG_DM_MULTIPATH=m ++# CONFIG_DM_DELAY is not set ++# CONFIG_DM_UEVENT is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++ ++# ++# Enable only one of the two stacks, unless you know what you are doing ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_IEEE1394 is not set ++# CONFIG_I2O is not set ++CONFIG_NETDEVICES=y ++CONFIG_COMPAT_NET_DEV_OPS=y ++CONFIG_IFB=m ++CONFIG_DUMMY=m ++# CONFIG_BONDING is not set ++CONFIG_MACVLAN=m ++# CONFIG_EQUALIZER is not set ++CONFIG_TUN=m ++CONFIG_VETH=m ++# CONFIG_NET_SB1000 is not set ++# CONFIG_ARCNET is not set ++CONFIG_PHYLIB=m ++ ++# ++# MII PHY device drivers ++# ++CONFIG_MARVELL_PHY=m ++CONFIG_DAVICOM_PHY=m ++CONFIG_QSEMI_PHY=m ++CONFIG_LXT_PHY=m ++CONFIG_CICADA_PHY=m ++CONFIG_VITESSE_PHY=m ++CONFIG_SMSC_PHY=m ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++CONFIG_REALTEK_PHY=m ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_HAPPYMEAL is not set ++# CONFIG_SUNGEM is not set ++# CONFIG_CASSINI is not set ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_NET_VENDOR_SMC is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_ENC28J60 is not set ++# CONFIG_ETHOC is not set ++# CONFIG_NET_VENDOR_RACAL is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_TULIP is not set ++# CONFIG_AT1700 is not set ++# CONFIG_DEPCA is not set ++# CONFIG_HP100 is not set ++# CONFIG_NET_ISA is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++CONFIG_NET_PCI=y ++# CONFIG_PCNET32 is not set ++# CONFIG_AMD8111_ETH is not set ++# CONFIG_ADAPTEC_STARFIRE is not set ++# CONFIG_AC3200 is not set ++# CONFIG_APRICOT is not set ++# CONFIG_B44 is not set ++# CONFIG_FORCEDETH is not set ++# CONFIG_CS89x0 is not set ++# CONFIG_TC35815 is not set ++# CONFIG_E100 is not set ++# CONFIG_FEALNX is not set ++# CONFIG_NATSEMI is not set ++# CONFIG_NE2K_PCI is not set ++CONFIG_8139CP=m ++CONFIG_8139TOO=y ++# CONFIG_8139TOO_PIO is not set ++CONFIG_8139TOO_TUNE_TWISTER=y ++# CONFIG_8139TOO_8129 is not set ++# CONFIG_8139_OLD_RX_RESET is not set ++# CONFIG_R6040 is not set ++# CONFIG_SIS900 is not set ++# CONFIG_EPIC100 is not set ++# CONFIG_SMSC9420 is not set ++# CONFIG_SUNDANCE is not set ++# CONFIG_TLAN is not set ++# CONFIG_VIA_RHINE is not set ++# CONFIG_SC92031 is not set ++# CONFIG_ATL2 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++# CONFIG_TR is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++CONFIG_WLAN_80211=y ++# CONFIG_LIBERTAS is not set ++# CONFIG_LIBERTAS_THINFIRM is not set ++# CONFIG_ATMEL is not set ++# CONFIG_AT76C50X_USB is not set ++# CONFIG_PRISM54 is not set ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_RTL8180 is not set ++CONFIG_RTL8187=y ++# CONFIG_ADM8211 is not set ++# CONFIG_MAC80211_HWSIM is not set ++# CONFIG_MWL8K is not set ++# CONFIG_P54_COMMON is not set ++# CONFIG_ATH5K is not set ++# CONFIG_ATH9K is not set ++# CONFIG_AR9170_USB is not set ++# CONFIG_IPW2100 is not set ++# CONFIG_IPW2200 is not set ++# CONFIG_IWLWIFI is not set ++# CONFIG_HOSTAP is not set ++# CONFIG_B43 is not set ++# CONFIG_B43LEGACY is not set ++# CONFIG_ZD1211RW is not set ++# CONFIG_RT2X00 is not set ++# CONFIG_HERMES is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET=m ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++# CONFIG_USB_NET_CDC_EEM is not set ++# CONFIG_USB_NET_DM9601 is not set ++# CONFIG_USB_NET_SMSC95XX is not set ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++# CONFIG_USB_NET_MCS7830 is not set ++CONFIG_USB_NET_RNDIS_HOST=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_BELKIN=y ++CONFIG_USB_ARMLINUX=y ++CONFIG_USB_EPSON2888=y ++# CONFIG_USB_KC2190 is not set ++CONFIG_USB_NET_ZAURUS=m ++# CONFIG_WAN is not set ++# CONFIG_ATM_DRIVERS is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++CONFIG_PPP=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_MPPE=m ++CONFIG_PPPOE=m ++CONFIG_PPPOATM=m ++# CONFIG_PPPOL2TP is not set ++# CONFIG_SLIP is not set ++CONFIG_SLHC=m ++# CONFIG_NET_FC is not set ++CONFIG_NETCONSOLE=y ++# CONFIG_NETCONSOLE_DYNAMIC is not set ++CONFIG_NETPOLL=y ++# CONFIG_NETPOLL_TRAP is not set ++CONFIG_NET_POLL_CONTROLLER=y ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++CONFIG_INPUT_JOYDEV=m ++CONFIG_INPUT_EVDEV=m ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++CONFIG_KEYBOARD_SUNKBD=m ++CONFIG_KEYBOARD_LKKBD=m ++CONFIG_KEYBOARD_XTKBD=m ++CONFIG_KEYBOARD_NEWTON=m ++# CONFIG_KEYBOARD_STOWAWAY is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_SERIAL=m ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++CONFIG_MOUSE_INPORT=m ++# CONFIG_MOUSE_ATIXL is not set ++CONFIG_MOUSE_LOGIBM=m ++CONFIG_MOUSE_PC110PAD=m ++CONFIG_MOUSE_VSXXXAA=m ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_PCSPKR=m ++# CONFIG_INPUT_ATI_REMOTE is not set ++# CONFIG_INPUT_ATI_REMOTE2 is not set ++# CONFIG_INPUT_KEYSPAN_REMOTE is not set ++# CONFIG_INPUT_POWERMATE is not set ++# CONFIG_INPUT_YEALINK is not set ++# CONFIG_INPUT_CM109 is not set ++CONFIG_INPUT_UINPUT=m ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_I8042=y ++CONFIG_SERIO_SERPORT=m ++CONFIG_SERIO_PCIPS2=m ++CONFIG_SERIO_LIBPS2=y ++CONFIG_SERIO_RAW=m ++CONFIG_GAMEPORT=m ++CONFIG_GAMEPORT_NS558=m ++CONFIG_GAMEPORT_L4=m ++CONFIG_GAMEPORT_EMU10K1=m ++CONFIG_GAMEPORT_FM801=m ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++CONFIG_SERIAL_NONSTANDARD=y ++# CONFIG_COMPUTONE is not set ++# CONFIG_ROCKETPORT is not set ++# CONFIG_CYCLADES is not set ++# CONFIG_DIGIEPCA is not set ++# CONFIG_MOXA_INTELLIO is not set ++# CONFIG_MOXA_SMARTIO is not set ++# CONFIG_ISI is not set ++# CONFIG_SYNCLINKMP is not set ++# CONFIG_SYNCLINK_GT is not set ++# CONFIG_N_HDLC is not set ++# CONFIG_RISCOM8 is not set ++# CONFIG_SPECIALIX is not set ++# CONFIG_SX is not set ++# CONFIG_RIO is not set ++CONFIG_STALDRV=y ++# CONFIG_STALLION is not set ++# CONFIG_ISTALLION is not set ++# CONFIG_NOZOMI is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++CONFIG_SERIAL_8250_CONSOLE=y ++# CONFIG_SERIAL_8250_PCI is not set ++# CONFIG_SERIAL_8250_PNP is not set ++CONFIG_SERIAL_8250_NR_UARTS=16 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++CONFIG_SERIAL_8250_EXTENDED=y ++CONFIG_SERIAL_8250_MANY_PORTS=y ++CONFIG_SERIAL_8250_FOURPORT=y ++# CONFIG_SERIAL_8250_ACCENT is not set ++# CONFIG_SERIAL_8250_BOCA is not set ++# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set ++CONFIG_SERIAL_8250_HUB6=m ++CONFIG_SERIAL_8250_SHARE_IRQ=y ++# CONFIG_SERIAL_8250_DETECT_IRQ is not set ++CONFIG_SERIAL_8250_RSA=y ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MAX3100 is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=16 ++CONFIG_IPMI_HANDLER=m ++# CONFIG_IPMI_PANIC_EVENT is not set ++CONFIG_IPMI_DEVICE_INTERFACE=m ++CONFIG_IPMI_SI=m ++CONFIG_IPMI_WATCHDOG=m ++CONFIG_IPMI_POWEROFF=m ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set ++# CONFIG_DTLK is not set ++# CONFIG_R3964 is not set ++# CONFIG_APPLICOM is not set ++CONFIG_RAW_DRIVER=m ++CONFIG_MAX_RAW_DEVS=256 ++# CONFIG_TCG_TPM is not set ++CONFIG_DEVPORT=y ++CONFIG_I2C=m ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=m ++CONFIG_I2C_HELPER_AUTO=y ++CONFIG_I2C_ALGOBIT=m ++CONFIG_I2C_ALGOPCA=m ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++CONFIG_I2C_ALI1535=m ++CONFIG_I2C_ALI1563=m ++CONFIG_I2C_ALI15X3=m ++CONFIG_I2C_AMD756=m ++CONFIG_I2C_AMD8111=m ++CONFIG_I2C_I801=m ++# CONFIG_I2C_ISCH is not set ++CONFIG_I2C_PIIX4=m ++CONFIG_I2C_NFORCE2=m ++CONFIG_I2C_SIS5595=m ++CONFIG_I2C_SIS630=m ++CONFIG_I2C_SIS96X=m ++CONFIG_I2C_VIA=m ++CONFIG_I2C_VIAPRO=m ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++CONFIG_I2C_OCORES=m ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++CONFIG_I2C_PARPORT_LIGHT=m ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Graphics adapter I2C/DDC channel drivers ++# ++CONFIG_I2C_VOODOO3=m ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_ELEKTOR is not set ++CONFIG_I2C_PCA_ISA=m ++# CONFIG_I2C_PCA_PLATFORM is not set ++CONFIG_I2C_STUB=m ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++CONFIG_SENSORS_PCF8574=m ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++CONFIG_SENSORS_MAX6875=m ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++CONFIG_SPI=y ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++CONFIG_SPI_BITBANG=m ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++CONFIG_SOFT_WATCHDOG=m ++# CONFIG_ALIM7101_WDT is not set ++ ++# ++# ISA-based Watchdog Cards ++# ++# CONFIG_PCWATCHDOG is not set ++# CONFIG_MIXCOMWD is not set ++# CONFIG_WDT is not set ++ ++# ++# PCI-based Watchdog Cards ++# ++# CONFIG_PCIPCWATCHDOG is not set ++# CONFIG_WDTPCI is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_REGULATOR is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++CONFIG_VIDEO_DEV=m ++CONFIG_VIDEO_V4L2_COMMON=m ++CONFIG_VIDEO_ALLOW_V4L1=y ++CONFIG_VIDEO_V4L1_COMPAT=y ++# CONFIG_DVB_CORE is not set ++CONFIG_VIDEO_MEDIA=m ++ ++# ++# Multimedia drivers ++# ++CONFIG_MEDIA_ATTACH=y ++CONFIG_MEDIA_TUNER=m ++# CONFIG_MEDIA_TUNER_CUSTOMISE is not set ++CONFIG_MEDIA_TUNER_SIMPLE=m ++CONFIG_MEDIA_TUNER_TDA8290=m ++CONFIG_MEDIA_TUNER_TDA9887=m ++CONFIG_MEDIA_TUNER_TEA5761=m ++CONFIG_MEDIA_TUNER_TEA5767=m ++CONFIG_MEDIA_TUNER_MT20XX=m ++CONFIG_MEDIA_TUNER_XC2028=m ++CONFIG_MEDIA_TUNER_XC5000=m ++CONFIG_MEDIA_TUNER_MC44S803=m ++CONFIG_VIDEO_V4L2=m ++CONFIG_VIDEO_V4L1=m ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set ++ ++# ++# Encoders/decoders and other helper chips ++# ++ ++# ++# Audio decoders ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TDA9875 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_M52790 is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_TCM825X is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_SAA7191 is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_CX25840 is not set ++ ++# ++# MPEG video encoders ++# ++# CONFIG_VIDEO_CX2341X is not set ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++# CONFIG_VIDEO_VIVI is not set ++# CONFIG_VIDEO_BT848 is not set ++# CONFIG_VIDEO_PMS is not set ++# CONFIG_VIDEO_CPIA is not set ++# CONFIG_VIDEO_CPIA2 is not set ++# CONFIG_VIDEO_SAA5246A is not set ++# CONFIG_VIDEO_SAA5249 is not set ++# CONFIG_VIDEO_STRADIS is not set ++# CONFIG_VIDEO_ZORAN is not set ++# CONFIG_VIDEO_SAA7134 is not set ++# CONFIG_VIDEO_MXB is not set ++# CONFIG_VIDEO_HEXIUM_ORION is not set ++# CONFIG_VIDEO_HEXIUM_GEMINI is not set ++# CONFIG_VIDEO_CX88 is not set ++# CONFIG_VIDEO_IVTV is not set ++# CONFIG_VIDEO_CAFE_CCIC is not set ++# CONFIG_SOC_CAMERA is not set ++CONFIG_V4L_USB_DRIVERS=y ++CONFIG_USB_VIDEO_CLASS=m ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++# CONFIG_USB_GSPCA is not set ++# CONFIG_VIDEO_PVRUSB2 is not set ++# CONFIG_VIDEO_HDPVR is not set ++# CONFIG_VIDEO_EM28XX is not set ++# CONFIG_VIDEO_CX231XX is not set ++# CONFIG_VIDEO_USBVISION is not set ++# CONFIG_USB_VICAM is not set ++# CONFIG_USB_IBMCAM is not set ++# CONFIG_USB_KONICAWC is not set ++# CONFIG_USB_QUICKCAM_MESSENGER is not set ++# CONFIG_USB_ET61X251 is not set ++# CONFIG_VIDEO_OVCAMCHIP is not set ++# CONFIG_USB_OV511 is not set ++# CONFIG_USB_SE401 is not set ++# CONFIG_USB_SN9C102 is not set ++# CONFIG_USB_STV680 is not set ++# CONFIG_USB_ZC0301 is not set ++# CONFIG_USB_PWC is not set ++CONFIG_USB_PWC_INPUT_EVDEV=y ++# CONFIG_USB_ZR364XX is not set ++# CONFIG_USB_STKWEBCAM is not set ++# CONFIG_USB_S2255 is not set ++CONFIG_RADIO_ADAPTERS=y ++CONFIG_RADIO_CADET=m ++CONFIG_RADIO_RTRACK=m ++CONFIG_RADIO_RTRACK2=m ++CONFIG_RADIO_AZTECH=m ++CONFIG_RADIO_GEMTEK=m ++CONFIG_RADIO_GEMTEK_PCI=m ++CONFIG_RADIO_MAXIRADIO=m ++CONFIG_RADIO_MAESTRO=m ++CONFIG_RADIO_SF16FMI=m ++CONFIG_RADIO_SF16FMR2=m ++CONFIG_RADIO_TERRATEC=m ++CONFIG_RADIO_TRUST=m ++CONFIG_RADIO_TYPHOON=m ++CONFIG_RADIO_TYPHOON_PROC_FS=y ++CONFIG_RADIO_ZOLTRIX=m ++CONFIG_USB_DSBR=m ++# CONFIG_USB_SI470X is not set ++# CONFIG_USB_MR800 is not set ++# CONFIG_RADIO_TEA5764 is not set ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++CONFIG_DRM=m ++CONFIG_DRM_TDFX=m ++CONFIG_DRM_R128=m ++CONFIG_DRM_RADEON=m ++CONFIG_DRM_MGA=m ++CONFIG_DRM_VIA=m ++CONFIG_DRM_SAVAGE=m ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++CONFIG_FIRMWARE_EDID=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++CONFIG_FB_SYS_FILLRECT=m ++CONFIG_FB_SYS_COPYAREA=m ++CONFIG_FB_SYS_IMAGEBLIT=m ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++CONFIG_FB_SYS_FOPS=m ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++CONFIG_FB_MODE_HELPERS=y ++CONFIG_FB_TILEBLITTING=y ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_CIRRUS is not set ++# CONFIG_FB_PM2 is not set ++# CONFIG_FB_CYBER2000 is not set ++# CONFIG_FB_ASILIANT is not set ++# CONFIG_FB_IMSTT is not set ++# CONFIG_FB_UVESA is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_NVIDIA is not set ++# CONFIG_FB_RIVA is not set ++# CONFIG_FB_MATROX is not set ++# CONFIG_FB_RADEON is not set ++# CONFIG_FB_ATY128 is not set ++# CONFIG_FB_ATY is not set ++# CONFIG_FB_S3 is not set ++# CONFIG_FB_SAVAGE is not set ++# CONFIG_FB_SIS is not set ++# CONFIG_FB_VIA is not set ++# CONFIG_FB_NEOMAGIC is not set ++# CONFIG_FB_KYRO is not set ++# CONFIG_FB_3DFX is not set ++# CONFIG_FB_VOODOO1 is not set ++# CONFIG_FB_VT8623 is not set ++# CONFIG_FB_TRIDENT is not set ++# CONFIG_FB_ARK is not set ++# CONFIG_FB_PM3 is not set ++# CONFIG_FB_CARMINE is not set ++CONFIG_FB_SM7XX=y ++CONFIG_FB_SM7XX_ACCEL=y ++# CONFIG_FB_SM7XX_DUALHEAD is not set ++CONFIG_FB_VIRTUAL=m ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_FB_BROADSHEET is not set ++CONFIG_BACKLIGHT_LCD_SUPPORT=y ++# CONFIG_LCD_CLASS_DEVICE is not set ++CONFIG_BACKLIGHT_CLASS_DEVICE=y ++CONFIG_BACKLIGHT_GENERIC=y ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++# CONFIG_MDA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_RAWMIDI=m ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_PCM_OSS_PLUGINS=y ++CONFIG_SND_SEQUENCER_OSS=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_VMASTER=y ++CONFIG_SND_AC97_CODEC=y ++CONFIG_SND_DRIVERS=y ++CONFIG_SND_DUMMY=m ++# CONFIG_SND_VIRMIDI is not set ++CONFIG_SND_MTPAV=m ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++# CONFIG_SND_AC97_POWER_SAVE is not set ++CONFIG_SND_PCI=y ++# CONFIG_SND_AD1889 is not set ++# CONFIG_SND_ALS300 is not set ++# CONFIG_SND_ALI5451 is not set ++# CONFIG_SND_ATIIXP is not set ++# CONFIG_SND_ATIIXP_MODEM is not set ++# CONFIG_SND_AU8810 is not set ++# CONFIG_SND_AU8820 is not set ++# CONFIG_SND_AU8830 is not set ++# CONFIG_SND_AW2 is not set ++# CONFIG_SND_AZT3328 is not set ++# CONFIG_SND_BT87X is not set ++# CONFIG_SND_CA0106 is not set ++# CONFIG_SND_CMIPCI is not set ++# CONFIG_SND_OXYGEN is not set ++# CONFIG_SND_CS4281 is not set ++# CONFIG_SND_CS46XX is not set ++CONFIG_SND_CS5535AUDIO=y ++# CONFIG_SND_DARLA20 is not set ++# CONFIG_SND_GINA20 is not set ++# CONFIG_SND_LAYLA20 is not set ++# CONFIG_SND_DARLA24 is not set ++# CONFIG_SND_GINA24 is not set ++# CONFIG_SND_LAYLA24 is not set ++# CONFIG_SND_MONA is not set ++# CONFIG_SND_MIA is not set ++# CONFIG_SND_ECHO3G is not set ++# CONFIG_SND_INDIGO is not set ++# CONFIG_SND_INDIGOIO is not set ++# CONFIG_SND_INDIGODJ is not set ++# CONFIG_SND_INDIGOIOX is not set ++# CONFIG_SND_INDIGODJX is not set ++# CONFIG_SND_EMU10K1 is not set ++# CONFIG_SND_EMU10K1X is not set ++# CONFIG_SND_ENS1370 is not set ++# CONFIG_SND_ENS1371 is not set ++# CONFIG_SND_ES1938 is not set ++# CONFIG_SND_ES1968 is not set ++# CONFIG_SND_FM801 is not set ++# CONFIG_SND_HDA_INTEL is not set ++# CONFIG_SND_HDSP is not set ++# CONFIG_SND_HDSPM is not set ++# CONFIG_SND_HIFIER is not set ++# CONFIG_SND_ICE1712 is not set ++# CONFIG_SND_ICE1724 is not set ++# CONFIG_SND_INTEL8X0 is not set ++# CONFIG_SND_INTEL8X0M is not set ++# CONFIG_SND_KORG1212 is not set ++# CONFIG_SND_MAESTRO3 is not set ++# CONFIG_SND_MIXART is not set ++# CONFIG_SND_NM256 is not set ++# CONFIG_SND_PCXHR is not set ++# CONFIG_SND_RIPTIDE is not set ++# CONFIG_SND_RME32 is not set ++# CONFIG_SND_RME96 is not set ++# CONFIG_SND_RME9652 is not set ++# CONFIG_SND_SONICVIBES is not set ++# CONFIG_SND_TRIDENT is not set ++# CONFIG_SND_VIA82XX is not set ++# CONFIG_SND_VIA82XX_MODEM is not set ++# CONFIG_SND_VIRTUOSO is not set ++# CONFIG_SND_VX222 is not set ++# CONFIG_SND_YMFPCI is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_MIPS is not set ++# CONFIG_SND_USB is not set ++# CONFIG_SND_SOC is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_AC97_BUS=y ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++# CONFIG_HID_DEBUG is not set ++CONFIG_HIDRAW=y ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++CONFIG_USB_HIDDEV=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_DRAGONRISE_FF is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SONY is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_GREENASIA_FF is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++CONFIG_USB_ARCH_HAS_EHCI=y ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++CONFIG_USB_DYNAMIC_MINORS=y ++# CONFIG_USB_SUSPEND is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++CONFIG_USB_MON=m ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++# CONFIG_USB_EHCI_TT_NEWSCHED is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++CONFIG_USB_OHCI_HCD=m ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_UHCI_HCD=m ++# CONFIG_USB_SL811_HCD is not set ++CONFIG_USB_R8A66597_HCD=y ++# CONFIG_USB_WHCI_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++ ++# ++# USB Device Class drivers ++# ++CONFIG_USB_ACM=m ++CONFIG_USB_PRINTER=m ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++CONFIG_USB_STORAGE_DATAFAB=y ++CONFIG_USB_STORAGE_FREECOM=y ++CONFIG_USB_STORAGE_ISD200=y ++CONFIG_USB_STORAGE_USBAT=y ++CONFIG_USB_STORAGE_SDDR09=y ++CONFIG_USB_STORAGE_SDDR55=y ++CONFIG_USB_STORAGE_JUMPSHOT=y ++CONFIG_USB_STORAGE_ALAUDA=y ++CONFIG_USB_STORAGE_ONETOUCH=y ++CONFIG_USB_STORAGE_KARMA=y ++CONFIG_USB_STORAGE_CYPRESS_ATACB=y ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++CONFIG_USB_MDC800=m ++CONFIG_USB_MICROTEK=m ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=m ++CONFIG_USB_EZUSB=y ++CONFIG_USB_SERIAL_GENERIC=y ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++CONFIG_USB_SERIAL_ARK3116=m ++CONFIG_USB_SERIAL_BELKIN=m ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m ++# CONFIG_USB_SERIAL_CP210X is not set ++CONFIG_USB_SERIAL_CYPRESS_M8=m ++CONFIG_USB_SERIAL_EMPEG=m ++CONFIG_USB_SERIAL_FTDI_SIO=m ++CONFIG_USB_SERIAL_FUNSOFT=m ++CONFIG_USB_SERIAL_VISOR=m ++CONFIG_USB_SERIAL_IPAQ=m ++CONFIG_USB_SERIAL_IR=m ++CONFIG_USB_SERIAL_EDGEPORT=m ++CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_GARMIN=m ++CONFIG_USB_SERIAL_IPW=m ++# CONFIG_USB_SERIAL_IUU is not set ++CONFIG_USB_SERIAL_KEYSPAN_PDA=m ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++CONFIG_USB_SERIAL_KLSI=m ++CONFIG_USB_SERIAL_KOBIL_SCT=m ++CONFIG_USB_SERIAL_MCT_U232=m ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++CONFIG_USB_SERIAL_NAVMAN=m ++CONFIG_USB_SERIAL_PL2303=m ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_QUALCOMM is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++CONFIG_USB_SERIAL_HP4X=m ++CONFIG_USB_SERIAL_SAFE=m ++# CONFIG_USB_SERIAL_SAFE_PADDED is not set ++# CONFIG_USB_SERIAL_SIEMENS_MPI is not set ++CONFIG_USB_SERIAL_SIERRAWIRELESS=m ++# CONFIG_USB_SERIAL_SYMBOL is not set ++CONFIG_USB_SERIAL_TI=m ++CONFIG_USB_SERIAL_CYBERJACK=m ++CONFIG_USB_SERIAL_XIRCOM=m ++CONFIG_USB_SERIAL_OPTION=m ++CONFIG_USB_SERIAL_OMNINET=m ++# CONFIG_USB_SERIAL_OPTICON is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++CONFIG_USB_RIO500=m ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++CONFIG_USB_IDMOUSE=m ++# CONFIG_USB_FTDI_ELAN is not set ++CONFIG_USB_APPLEDISPLAY=m ++CONFIG_USB_SISUSBVGA=m ++CONFIG_USB_SISUSBVGA_CON=y ++CONFIG_USB_LD=m ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++CONFIG_USB_TEST=m ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_ATM=m ++CONFIG_USB_SPEEDTOUCH=m ++CONFIG_USB_CXACRU=m ++CONFIG_USB_UEAGLEATM=m ++CONFIG_USB_XUSBATM=m ++# CONFIG_USB_GADGET is not set ++ ++# ++# OTG and related infrastructure ++# ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++# CONFIG_MMC_BLOCK is not set ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_TIFM_SD is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MEMSTICK is not set ++CONFIG_NEW_LEDS=y ++CONFIG_LEDS_CLASS=m ++ ++# ++# LED drivers ++# ++# CONFIG_LEDS_PCA9532 is not set ++# CONFIG_LEDS_LP5521 is not set ++# CONFIG_LEDS_PCA955X is not set ++# CONFIG_LEDS_DAC124S085 is not set ++# CONFIG_LEDS_BD2802 is not set ++ ++# ++# LED Triggers ++# ++CONFIG_LEDS_TRIGGERS=y ++CONFIG_LEDS_TRIGGER_TIMER=m ++# CONFIG_LEDS_TRIGGER_IDE_DISK is not set ++CONFIG_LEDS_TRIGGER_HEARTBEAT=m ++# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set ++# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set ++ ++# ++# iptables trigger is under Netfilter config (LED target) ++# ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++ ++# ++# Platform RTC drivers ++# ++CONFIG_RTC_DRV_CMOS=y ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_STAGING is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++CONFIG_EXT2_FS_XATTR=y ++CONFIG_EXT2_FS_POSIX_ACL=y ++CONFIG_EXT2_FS_SECURITY=y ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++CONFIG_EXT4_FS=m ++CONFIG_EXT4DEV_COMPAT=y ++CONFIG_EXT4_FS_XATTR=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++CONFIG_JBD=y ++# CONFIG_JBD_DEBUG is not set ++CONFIG_JBD2=m ++# CONFIG_JBD2_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++CONFIG_REISERFS_FS=m ++# CONFIG_REISERFS_CHECK is not set ++# CONFIG_REISERFS_PROC_INFO is not set ++CONFIG_REISERFS_FS_XATTR=y ++CONFIG_REISERFS_FS_POSIX_ACL=y ++CONFIG_REISERFS_FS_SECURITY=y ++CONFIG_JFS_FS=m ++CONFIG_JFS_POSIX_ACL=y ++CONFIG_JFS_SECURITY=y ++# CONFIG_JFS_DEBUG is not set ++# CONFIG_JFS_STATISTICS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++CONFIG_XFS_FS=m ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++# CONFIG_XFS_DEBUG is not set ++# CONFIG_GFS2_FS is not set ++CONFIG_OCFS2_FS=m ++CONFIG_OCFS2_FS_O2CB=m ++CONFIG_OCFS2_FS_STATS=y ++CONFIG_OCFS2_DEBUG_MASKLOG=y ++# CONFIG_OCFS2_DEBUG_FS is not set ++# CONFIG_OCFS2_FS_POSIX_ACL is not set ++# CONFIG_BTRFS_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++CONFIG_QUOTA=y ++# CONFIG_QUOTA_NETLINK_INTERFACE is not set ++CONFIG_PRINT_QUOTA_WARNING=y ++CONFIG_QUOTA_TREE=m ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_QUOTACTL=y ++CONFIG_AUTOFS_FS=m ++CONFIG_AUTOFS4_FS=m ++CONFIG_FUSE_FS=m ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m ++CONFIG_UDF_NLS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++CONFIG_NTFS_RW=y ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_KCORE=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=m ++CONFIG_MISC_FILESYSTEMS=y ++CONFIG_ADFS_FS=m ++# CONFIG_ADFS_FS_RW is not set ++CONFIG_AFFS_FS=m ++# CONFIG_ECRYPT_FS is not set ++CONFIG_HFS_FS=m ++CONFIG_HFSPLUS_FS=m ++CONFIG_BEFS_FS=m ++# CONFIG_BEFS_DEBUG is not set ++CONFIG_BFS_FS=m ++CONFIG_EFS_FS=m ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++CONFIG_JFFS2_FS_XATTR=y ++CONFIG_JFFS2_FS_POSIX_ACL=y ++CONFIG_JFFS2_FS_SECURITY=y ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_CRAMFS=y ++# CONFIG_SQUASHFS is not set ++CONFIG_VXFS_FS=m ++CONFIG_MINIX_FS=m ++# CONFIG_OMFS_FS is not set ++CONFIG_HPFS_FS=m ++CONFIG_QNX4FS_FS=m ++CONFIG_ROMFS_FS=m ++CONFIG_ROMFS_BACKED_BY_BLOCK=y ++# CONFIG_ROMFS_BACKED_BY_MTD is not set ++# CONFIG_ROMFS_BACKED_BY_BOTH is not set ++CONFIG_ROMFS_ON_BLOCK=y ++CONFIG_SYSV_FS=m ++CONFIG_UFS_FS=m ++# CONFIG_UFS_FS_WRITE is not set ++# CONFIG_UFS_DEBUG is not set ++# CONFIG_NILFS2_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_NFSD=m ++CONFIG_NFSD_V2_ACL=y ++CONFIG_NFSD_V3=y ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y ++CONFIG_LOCKD=m ++CONFIG_LOCKD_V4=y ++CONFIG_EXPORTFS=m ++CONFIG_NFS_ACL_SUPPORT=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++CONFIG_SUNRPC_GSS=m ++CONFIG_RPCSEC_GSS_KRB5=m ++CONFIG_RPCSEC_GSS_SPKM3=m ++CONFIG_SMB_FS=m ++# CONFIG_SMB_NLS_DEFAULT is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++# CONFIG_CIFS_WEAK_PW_HASH is not set ++# CONFIG_CIFS_UPCALL is not set ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG2 is not set ++# CONFIG_CIFS_DFS_UPCALL is not set ++# CONFIG_CIFS_EXPERIMENTAL is not set ++CONFIG_NCP_FS=m ++CONFIG_NCPFS_PACKET_SIGNING=y ++CONFIG_NCPFS_IOCTL_LOCKING=y ++CONFIG_NCPFS_STRONG=y ++CONFIG_NCPFS_NFS_NS=y ++CONFIG_NCPFS_OS2_NS=y ++# CONFIG_NCPFS_SMALLDOS is not set ++CONFIG_NCPFS_NLS=y ++CONFIG_NCPFS_EXTRAS=y ++CONFIG_CODA_FS=m ++CONFIG_AFS_FS=m ++# CONFIG_AFS_DEBUG is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_ACORN_PARTITION=y ++# CONFIG_ACORN_PARTITION_CUMANA is not set ++# CONFIG_ACORN_PARTITION_EESOX is not set ++CONFIG_ACORN_PARTITION_ICS=y ++# CONFIG_ACORN_PARTITION_ADFS is not set ++# CONFIG_ACORN_PARTITION_POWERTEC is not set ++CONFIG_ACORN_PARTITION_RISCIX=y ++CONFIG_OSF_PARTITION=y ++CONFIG_AMIGA_PARTITION=y ++CONFIG_ATARI_PARTITION=y ++CONFIG_MAC_PARTITION=y ++CONFIG_MSDOS_PARTITION=y ++CONFIG_BSD_DISKLABEL=y ++CONFIG_MINIX_SUBPARTITION=y ++CONFIG_SOLARIS_X86_PARTITION=y ++CONFIG_UNIXWARE_DISKLABEL=y ++CONFIG_LDM_PARTITION=y ++# CONFIG_LDM_DEBUG is not set ++CONFIG_SGI_PARTITION=y ++CONFIG_ULTRIX_PARTITION=y ++CONFIG_SUN_PARTITION=y ++CONFIG_KARMA_PARTITION=y ++CONFIG_EFI_PARTITION=y ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="utf-8" ++CONFIG_NLS_CODEPAGE_437=m ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++CONFIG_NLS_CODEPAGE_850=m ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=m ++# CONFIG_NLS_ISO8859_1 is not set ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_UNUSED_SYMBOLS=y ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_KERNEL is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_NOP_TRACER=y ++CONFIG_RING_BUFFER=y ++CONFIG_TRACING=y ++CONFIG_TRACING_SUPPORT=y ++ ++# ++# Tracers ++# ++# CONFIG_IRQSOFF_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_EVENT_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_TRACE_BRANCH_PROFILING is not set ++# CONFIG_KMEMTRACE is not set ++# CONFIG_WORKQUEUE_TRACER is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_FTRACE_STARTUP_TEST is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++CONFIG_CMDLINE="" ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set ++CONFIG_SECURITY=y ++# CONFIG_SECURITYFS is not set ++CONFIG_SECURITY_NETWORK=y ++CONFIG_SECURITY_NETWORK_XFRM=y ++# CONFIG_SECURITY_PATH is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++# CONFIG_SECURITY_ROOTPLUG is not set ++CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 ++CONFIG_SECURITY_SELINUX=y ++CONFIG_SECURITY_SELINUX_BOOTPARAM=y ++CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 ++CONFIG_SECURITY_SELINUX_DISABLE=y ++CONFIG_SECURITY_SELINUX_DEVELOP=y ++CONFIG_SECURITY_SELINUX_AVC_STATS=y ++CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 ++# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set ++# CONFIG_SECURITY_TOMOYO is not set ++CONFIG_XOR_BLOCKS=m ++CONFIG_ASYNC_CORE=m ++CONFIG_ASYNC_MEMCPY=m ++CONFIG_ASYNC_XOR=m ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=m ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=m ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=m ++CONFIG_CRYPTO_TEST=m ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=m ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=m ++CONFIG_CRYPTO_MD4=m ++CONFIG_CRYPTO_MD5=y ++CONFIG_CRYPTO_MICHAEL_MIC=m ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=m ++CONFIG_CRYPTO_SHA256=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_WP512=m ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++CONFIG_CRYPTO_ANUBIS=m ++CONFIG_CRYPTO_ARC4=y ++CONFIG_CRYPTO_BLOWFISH=m ++# CONFIG_CRYPTO_CAMELLIA is not set ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_CAST6=m ++CONFIG_CRYPTO_DES=m ++# CONFIG_CRYPTO_FCRYPT is not set ++CONFIG_CRYPTO_KHAZAD=m ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++CONFIG_CRYPTO_SERPENT=m ++CONFIG_CRYPTO_TEA=m ++CONFIG_CRYPTO_TWOFISH=m ++CONFIG_CRYPTO_TWOFISH_COMMON=m ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=m ++# CONFIG_CRYPTO_ZLIB is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_CRYPTO_DEV_HIFN_795X is not set ++CONFIG_BINARY_PRINTF=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_FIND_LAST_BIT=y ++CONFIG_CRC_CCITT=m ++CONFIG_CRC16=m ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=m ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=m ++CONFIG_AUDIT_GENERIC=y ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=m ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_TEXTSEARCH=y ++CONFIG_TEXTSEARCH_KMP=m ++CONFIG_TEXTSEARCH_BM=m ++CONFIG_TEXTSEARCH_FSM=m ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y ++CONFIG_NLATTR=y +diff -Nur linux-2.6.30/arch/mips/include/asm/bootinfo.h rt4ls/arch/mips/include/asm/bootinfo.h +--- linux-2.6.30/arch/mips/include/asm/bootinfo.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/bootinfo.h 2009-06-12 16:27:08.306407755 +0200 +@@ -7,6 +7,7 @@ + * Copyright (C) 1995, 1996 Andreas Busse + * Copyright (C) 1995, 1996 Stoned Elipot + * Copyright (C) 1995, 1996 Paul M. Antoine. ++ * Copyright (C) 2009 Zhang Le + */ + #ifndef _ASM_BOOTINFO_H + #define _ASM_BOOTINFO_H +@@ -57,6 +58,16 @@ + #define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */ + #define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */ + ++/* ++ * Valid machtype for group Loongson ++ */ ++#define MACH_LOONGSON_UNKNOWN 0 ++#define MACH_LEMOTE_FL2E 1 ++#define MACH_LEMOTE_FL2F 2 ++#define MACH_LEMOTE_YL2F89 3 ++#define MACH_LEMOTE_YL2F7 4 ++#define MACH_LOONGSON_END 5 ++ + #define CL_SIZE COMMAND_LINE_SIZE + + extern char *system_type; +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h rt4ls/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h +--- linux-2.6.30/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,59 +0,0 @@ +-/* +- * This file is subject to the terms and conditions of the GNU General Public +- * License. See the file "COPYING" in the main directory of this archive +- * for more details. +- * +- * Copyright (C) 2009 Wu Zhangjin <wuzj@lemote.com> +- * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca> +- * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org> +- * +- * reference: /proc/cpuinfo, +- * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy), +- * arch/mips/kernel/proc.c(show_cpuinfo), +- * loongson2f user manual. +- */ +- +-#ifndef __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H +-#define __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H +- +-#define cpu_dcache_line_size() 32 +-#define cpu_icache_line_size() 32 +-#define cpu_scache_line_size() 32 +- +- +-#define cpu_has_32fpr 1 +-#define cpu_has_3k_cache 0 +-#define cpu_has_4k_cache 1 +-#define cpu_has_4kex 1 +-#define cpu_has_64bits 1 +-#define cpu_has_cache_cdex_p 0 +-#define cpu_has_cache_cdex_s 0 +-#define cpu_has_counter 1 +-#define cpu_has_dc_aliases 1 +-#define cpu_has_divec 0 +-#define cpu_has_dsp 0 +-#define cpu_has_ejtag 0 +-#define cpu_has_fpu 1 +-#define cpu_has_ic_fills_f_dc 0 +-#define cpu_has_inclusive_pcaches 1 +-#define cpu_has_llsc 1 +-#define cpu_has_mcheck 0 +-#define cpu_has_mdmx 0 +-#define cpu_has_mips16 0 +-#define cpu_has_mips32r1 0 +-#define cpu_has_mips32r2 0 +-#define cpu_has_mips3d 0 +-#define cpu_has_mips64r1 0 +-#define cpu_has_mips64r2 0 +-#define cpu_has_mipsmt 0 +-#define cpu_has_prefetch 0 +-#define cpu_has_smartmips 0 +-#define cpu_has_tlb 1 +-#define cpu_has_tx39_cache 0 +-#define cpu_has_userlocal 0 +-#define cpu_has_vce 0 +-#define cpu_has_vtag_icache 0 +-#define cpu_has_watch 1 +-#define cpu_icache_snoops_remote_store 1 +- +-#endif /* __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-lemote/dma-coherence.h rt4ls/arch/mips/include/asm/mach-lemote/dma-coherence.h +--- linux-2.6.30/arch/mips/include/asm/mach-lemote/dma-coherence.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/mach-lemote/dma-coherence.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,66 +0,0 @@ +-/* +- * This file is subject to the terms and conditions of the GNU General Public +- * License. See the file "COPYING" in the main directory of this archive +- * for more details. +- * +- * Copyright (C) 2006, 07 Ralf Baechle <ralf@linux-mips.org> +- * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology +- * Author: Fuxin Zhang, zhangfx@lemote.com +- * +- */ +-#ifndef __ASM_MACH_LEMOTE_DMA_COHERENCE_H +-#define __ASM_MACH_LEMOTE_DMA_COHERENCE_H +- +-struct device; +- +-static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, +- size_t size) +-{ +- return virt_to_phys(addr) | 0x80000000; +-} +- +-static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, +- struct page *page) +-{ +- return page_to_phys(page) | 0x80000000; +-} +- +-static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) +-{ +- return dma_addr & 0x7fffffff; +-} +- +-static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) +-{ +-} +- +-static inline int plat_dma_supported(struct device *dev, u64 mask) +-{ +- /* +- * we fall back to GFP_DMA when the mask isn't all 1s, +- * so we can't guarantee allocations that must be +- * within a tighter range than GFP_DMA.. +- */ +- if (mask < DMA_BIT_MASK(24)) +- return 0; +- +- return 1; +-} +- +-static inline void plat_extra_sync_for_device(struct device *dev) +-{ +- return; +-} +- +-static inline int plat_dma_mapping_error(struct device *dev, +- dma_addr_t dma_addr) +-{ +- return 0; +-} +- +-static inline int plat_device_is_coherent(struct device *dev) +-{ +- return 0; +-} +- +-#endif /* __ASM_MACH_LEMOTE_DMA_COHERENCE_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-lemote/mc146818rtc.h rt4ls/arch/mips/include/asm/mach-lemote/mc146818rtc.h +--- linux-2.6.30/arch/mips/include/asm/mach-lemote/mc146818rtc.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/mach-lemote/mc146818rtc.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,36 +0,0 @@ +-/* +- * This file is subject to the terms and conditions of the GNU General Public +- * License. See the file "COPYING" in the main directory of this archive +- * for more details. +- * +- * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org) +- * +- * RTC routines for PC style attached Dallas chip. +- */ +-#ifndef __ASM_MACH_LEMOTE_MC146818RTC_H +-#define __ASM_MACH_LEMOTE_MC146818RTC_H +- +-#include <linux/io.h> +- +-#define RTC_PORT(x) (0x70 + (x)) +-#define RTC_IRQ 8 +- +-static inline unsigned char CMOS_READ(unsigned long addr) +-{ +- outb_p(addr, RTC_PORT(0)); +- return inb_p(RTC_PORT(1)); +-} +- +-static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +-{ +- outb_p(addr, RTC_PORT(0)); +- outb_p(data, RTC_PORT(1)); +-} +- +-#define RTC_ALWAYS_BCD 0 +- +-#ifndef mc146818_decode_year +-#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) +-#endif +- +-#endif /* __ASM_MACH_LEMOTE_MC146818RTC_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-lemote/pci.h rt4ls/arch/mips/include/asm/mach-lemote/pci.h +--- linux-2.6.30/arch/mips/include/asm/mach-lemote/pci.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/mach-lemote/pci.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,30 +0,0 @@ +-/* +- * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org> +- * +- * This program is free software; you can redistribute it +- * and/or modify it under the terms of the GNU General +- * Public License as published by the Free Software +- * Foundation; either version 2 of the License, or (at your +- * option) any later version. +- * +- * This program is distributed in the hope that it will be +- * useful, but WITHOUT ANY WARRANTY; without even the implied +- * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +- * PURPOSE. See the GNU General Public License for more +- * details. +- * +- * You should have received a copy of the GNU General Public +- * License along with this program; if not, write to the Free +- * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA +- * 02139, USA. +- */ +- +-#ifndef _LEMOTE_PCI_H_ +-#define _LEMOTE_PCI_H_ +- +-#define LOONGSON2E_PCI_MEM_START 0x14000000UL +-#define LOONGSON2E_PCI_MEM_END 0x1fffffffUL +-#define LOONGSON2E_PCI_IO_START 0x00004000UL +-#define LOONGSON2E_IO_PORT_BASE 0x1fd00000UL +- +-#endif /* !_LEMOTE_PCI_H_ */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-lemote/war.h rt4ls/arch/mips/include/asm/mach-lemote/war.h +--- linux-2.6.30/arch/mips/include/asm/mach-lemote/war.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/mach-lemote/war.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,25 +0,0 @@ +-/* +- * This file is subject to the terms and conditions of the GNU General Public +- * License. See the file "COPYING" in the main directory of this archive +- * for more details. +- * +- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> +- */ +-#ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H +-#define __ASM_MIPS_MACH_LEMOTE_WAR_H +- +-#define R4600_V1_INDEX_ICACHEOP_WAR 0 +-#define R4600_V1_HIT_CACHEOP_WAR 0 +-#define R4600_V2_HIT_CACHEOP_WAR 0 +-#define R5432_CP0_INTERRUPT_WAR 0 +-#define BCM1250_M3_WAR 0 +-#define SIBYTE_1956_WAR 0 +-#define MIPS4K_ICACHE_REFILL_WAR 0 +-#define MIPS_CACHE_SYNC_WAR 0 +-#define TX49XX_ICACHE_INDEX_INV_WAR 0 +-#define RM9000_CDEX_SMP_WAR 0 +-#define ICACHE_REFILLS_WORKAROUND_WAR 0 +-#define R10000_LLSC_WAR 0 +-#define MIPS34K_MISSED_ITLB_WAR 0 +- +-#endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/clock.h rt4ls/arch/mips/include/asm/mach-loongson/clock.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/clock.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/clock.h 2009-06-12 16:27:08.506427365 +0200 +@@ -0,0 +1,64 @@ ++#ifndef __ASM_MIPS_CLOCK_H ++#define __ASM_MIPS_CLOCK_H ++ ++#include <linux/kref.h> ++#include <linux/list.h> ++#include <linux/seq_file.h> ++#include <linux/clk.h> ++ ++extern void (*cpu_wait) (void); ++ ++struct clk; ++ ++struct clk_ops { ++ void (*init) (struct clk *clk); ++ void (*enable) (struct clk *clk); ++ void (*disable) (struct clk *clk); ++ void (*recalc) (struct clk *clk); ++ int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id); ++ long (*round_rate) (struct clk *clk, unsigned long rate); ++}; ++ ++struct clk { ++ struct list_head node; ++ const char *name; ++ int id; ++ struct module *owner; ++ ++ struct clk *parent; ++ struct clk_ops *ops; ++ ++ struct kref kref; ++ ++ unsigned long rate; ++ unsigned long flags; ++}; ++ ++#define CLK_ALWAYS_ENABLED (1 << 0) ++#define CLK_RATE_PROPAGATES (1 << 1) ++ ++/* Should be defined by processor-specific code */ ++void arch_init_clk_ops(struct clk_ops **, int type); ++ ++int clk_init(void); ++ ++int __clk_enable(struct clk *); ++void __clk_disable(struct clk *); ++ ++void clk_recalc_rate(struct clk *); ++ ++int clk_register(struct clk *); ++void clk_unregister(struct clk *); ++ ++/* the exported API, in addition to clk_set_rate */ ++/** ++ * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter ++ * @clk: clock source ++ * @rate: desired clock rate in Hz ++ * @algo_id: algorithm id to be passed down to ops->set_rate ++ * ++ * Returns success (0) or negative errno. ++ */ ++int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id); ++ ++#endif /* __ASM_MIPS_CLOCK_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/cmdline.h rt4ls/arch/mips/include/asm/mach-loongson/cmdline.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/cmdline.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/cmdline.h 2009-06-12 16:27:08.510427596 +0200 +@@ -0,0 +1,9 @@ ++/* machine-specific command line initialization */ ++#ifdef CONFIG_SYS_HAS_MACH_PROM_INIT_CMDLINE ++extern void __init mach_prom_init_cmdline(void); ++#else ++void __init mach_prom_init_cmdline(void) ++{ ++} ++#endif ++ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h rt4ls/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h 2009-06-12 16:27:08.510427596 +0200 +@@ -0,0 +1,59 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2009 Wu Zhangjin <wuzj@lemote.com> ++ * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca> ++ * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org> ++ * ++ * reference: /proc/cpuinfo, ++ * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy), ++ * arch/mips/kernel/proc.c(show_cpuinfo), ++ * loongson2f user manual. ++ */ ++ ++#ifndef __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H ++#define __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H ++ ++#define cpu_dcache_line_size() 32 ++#define cpu_icache_line_size() 32 ++#define cpu_scache_line_size() 32 ++ ++ ++#define cpu_has_32fpr 1 ++#define cpu_has_3k_cache 0 ++#define cpu_has_4k_cache 1 ++#define cpu_has_4kex 1 ++#define cpu_has_64bits 1 ++#define cpu_has_cache_cdex_p 0 ++#define cpu_has_cache_cdex_s 0 ++#define cpu_has_counter 1 ++#define cpu_has_dc_aliases 1 ++#define cpu_has_divec 0 ++#define cpu_has_dsp 0 ++#define cpu_has_ejtag 0 ++#define cpu_has_fpu 1 ++#define cpu_has_ic_fills_f_dc 0 ++#define cpu_has_inclusive_pcaches 1 ++#define cpu_has_llsc 1 ++#define cpu_has_mcheck 0 ++#define cpu_has_mdmx 0 ++#define cpu_has_mips16 0 ++#define cpu_has_mips32r1 0 ++#define cpu_has_mips32r2 0 ++#define cpu_has_mips3d 0 ++#define cpu_has_mips64r1 0 ++#define cpu_has_mips64r2 0 ++#define cpu_has_mipsmt 0 ++#define cpu_has_prefetch 0 ++#define cpu_has_smartmips 0 ++#define cpu_has_tlb 1 ++#define cpu_has_tx39_cache 0 ++#define cpu_has_userlocal 0 ++#define cpu_has_vce 0 ++#define cpu_has_vtag_icache 0 ++#define cpu_has_watch 1 ++#define cpu_icache_snoops_remote_store 1 ++ ++#endif /* __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h rt4ls/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h 2009-06-12 16:27:08.510427596 +0200 +@@ -0,0 +1,382 @@ ++/* ++ * The header file of cs5536 sourth bridge. ++ * ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author : jlliu <liujl@lemote.com> ++ */ ++ ++#ifndef _CS5536_H ++#define _CS5536_H ++ ++#include <linux/types.h> ++ ++extern void _rdmsr(u32 msr, u32 *hi, u32 *lo); ++extern void _wrmsr(u32 msr, u32 hi, u32 lo); ++ ++/* ++ * MSR module base ++ */ ++#define CS5536_SB_MSR_BASE (0x00000000) ++#define CS5536_GLIU_MSR_BASE (0x10000000) ++#define CS5536_ILLEGAL_MSR_BASE (0x20000000) ++#define CS5536_USB_MSR_BASE (0x40000000) ++#define CS5536_IDE_MSR_BASE (0x60000000) ++#define CS5536_DIVIL_MSR_BASE (0x80000000) ++#define CS5536_ACC_MSR_BASE (0xa0000000) ++#define CS5536_UNUSED_MSR_BASE (0xc0000000) ++#define CS5536_GLCP_MSR_BASE (0xe0000000) ++ ++#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset)) ++#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset)) ++#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset)) ++#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset)) ++#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset)) ++#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset)) ++#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset)) ++#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset)) ++#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset)) ++ ++/* ++ * BAR SPACE OF VIRTUAL PCI : ++ * range for pci probe use, length is the actual size. ++ */ ++/* IO space for all DIVIL modules */ ++#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */ ++#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */ ++#define CS5536_SMB_RANGE 0xfffffff8 ++#define CS5536_SMB_LENGTH 0x08 ++#define CS5536_GPIO_RANGE 0xffffff00 ++#define CS5536_GPIO_LENGTH 0x100 ++#define CS5536_MFGPT_RANGE 0xffffffc0 ++#define CS5536_MFGPT_LENGTH 0x40 ++#define CS5536_ACPI_RANGE 0xffffffe0 ++#define CS5536_ACPI_LENGTH 0x20 ++#define CS5536_PMS_RANGE 0xffffff80 ++#define CS5536_PMS_LENGTH 0x80 ++/* MEM space for 4KB nand flash; IO space for 16B nor flash. */ ++#ifdef CS5536_NOR_FLASH ++#define CS5536_FLSH_LENGTH 0x10 ++#define CS5536_FLSH_RANGE 0xfffffff0 ++#else ++#define CS5536_FLSH_RANGE 0xfffff000 ++#define CS5536_FLSH_LENGTH 0x1000 ++#endif ++/* IO space for IDE */ ++#define CS5536_IDE_RANGE 0xfffffff0 ++#define CS5536_IDE_LENGTH 0x10 ++/* IO space for ACC */ ++#define CS5536_ACC_RANGE 0xffffff80 ++#define CS5536_ACC_LENGTH 0x80 ++/* MEM space for ALL USB modules */ ++#define CS5536_OHCI_RANGE 0xfffff000 ++#define CS5536_OHCI_LENGTH 0x1000 ++#define CS5536_EHCI_RANGE 0xfffff000 ++#define CS5536_EHCI_LENGTH 0x1000 ++#define CS5536_UDC_RANGE 0xffffe000 ++#define CS5536_UDC_LENGTH 0x2000 ++#define CS5536_OTG_RANGE 0xfffff000 ++#define CS5536_OTG_LENGTH 0x1000 ++ ++/* ++ * PCI MSR ACCESS ++ */ ++#define PCI_MSR_CTRL 0xF0 ++#define PCI_MSR_ADDR 0xF4 ++#define PCI_MSR_DATA_LO 0xF8 ++#define PCI_MSR_DATA_HI 0xFC ++ ++/**************** MSR *****************************/ ++ ++/* ++ * GLIU STANDARD MSR ++ */ ++#define GLIU_CAP 0x00 ++#define GLIU_CONFIG 0x01 ++#define GLIU_SMI 0x02 ++#define GLIU_ERROR 0x03 ++#define GLIU_PM 0x04 ++#define GLIU_DIAG 0x05 ++ ++/* ++ * GLIU SPEC. MSR ++ */ ++#define GLIU_P2D_BM0 0x20 ++#define GLIU_P2D_BM1 0x21 ++#define GLIU_P2D_BM2 0x22 ++#define GLIU_P2D_BMK0 0x23 ++#define GLIU_P2D_BMK1 0x24 ++#define GLIU_P2D_BM3 0x25 ++#define GLIU_P2D_BM4 0x26 ++#define GLIU_COH 0x80 ++#define GLIU_PAE 0x81 ++#define GLIU_ARB 0x82 ++#define GLIU_ASMI 0x83 ++#define GLIU_AERR 0x84 ++#define GLIU_DEBUG 0x85 ++#define GLIU_PHY_CAP 0x86 ++#define GLIU_NOUT_RESP 0x87 ++#define GLIU_NOUT_WDATA 0x88 ++#define GLIU_WHOAMI 0x8B ++#define GLIU_SLV_DIS 0x8C ++#define GLIU_IOD_BM0 0xE0 ++#define GLIU_IOD_BM1 0xE1 ++#define GLIU_IOD_BM2 0xE2 ++#define GLIU_IOD_BM3 0xE3 ++#define GLIU_IOD_BM4 0xE4 ++#define GLIU_IOD_BM5 0xE5 ++#define GLIU_IOD_BM6 0xE6 ++#define GLIU_IOD_BM7 0xE7 ++#define GLIU_IOD_BM8 0xE8 ++#define GLIU_IOD_BM9 0xE9 ++#define GLIU_IOD_SC0 0xEA ++#define GLIU_IOD_SC1 0xEB ++#define GLIU_IOD_SC2 0xEC ++#define GLIU_IOD_SC3 0xED ++#define GLIU_IOD_SC4 0xEE ++#define GLIU_IOD_SC5 0xEF ++#define GLIU_IOD_SC6 0xF0 ++#define GLIU_IOD_SC7 0xF1 ++ ++/* ++ * SB STANDARD ++ */ ++#define SB_CAP 0x00 ++#define SB_CONFIG 0x01 ++#define SB_SMI 0x02 ++#define SB_ERROR 0x03 ++#define SB_MAR_ERR_EN 0x00000001 ++#define SB_TAR_ERR_EN 0x00000002 ++#define SB_RSVD_BIT1 0x00000004 ++#define SB_EXCEP_ERR_EN 0x00000008 ++#define SB_SYSE_ERR_EN 0x00000010 ++#define SB_PARE_ERR_EN 0x00000020 ++#define SB_TAS_ERR_EN 0x00000040 ++#define SB_MAR_ERR_FLAG 0x00010000 ++#define SB_TAR_ERR_FLAG 0x00020000 ++#define SB_RSVD_BIT2 0x00040000 ++#define SB_EXCEP_ERR_FLAG 0x00080000 ++#define SB_SYSE_ERR_FLAG 0x00100000 ++#define SB_PARE_ERR_FLAG 0x00200000 ++#define SB_TAS_ERR_FLAG 0x00400000 ++#define SB_PM 0x04 ++#define SB_DIAG 0x05 ++ ++/* ++ * SB SPEC. ++ */ ++#define SB_CTRL 0x10 ++#define SB_R0 0x20 ++#define SB_R1 0x21 ++#define SB_R2 0x22 ++#define SB_R3 0x23 ++#define SB_R4 0x24 ++#define SB_R5 0x25 ++#define SB_R6 0x26 ++#define SB_R7 0x27 ++#define SB_R8 0x28 ++#define SB_R9 0x29 ++#define SB_R10 0x2A ++#define SB_R11 0x2B ++#define SB_R12 0x2C ++#define SB_R13 0x2D ++#define SB_R14 0x2E ++#define SB_R15 0x2F ++ ++/* ++ * GLCP STANDARD ++ */ ++#define GLCP_CAP 0x00 ++#define GLCP_CONFIG 0x01 ++#define GLCP_SMI 0x02 ++#define GLCP_ERROR 0x03 ++#define GLCP_PM 0x04 ++#define GLCP_DIAG 0x05 ++ ++/* ++ * GLCP SPEC. ++ */ ++#define GLCP_CLK_DIS_DELAY 0x08 ++#define GLCP_PM_CLK_DISABLE 0x09 ++#define GLCP_GLB_PM 0x0B ++#define GLCP_DBG_OUT 0x0C ++#define GLCP_RSVD1 0x0D ++#define GLCP_SOFT_COM 0x0E ++#define SOFT_BAR_SMB_FLAG 0x00000001 ++#define SOFT_BAR_GPIO_FLAG 0x00000002 ++#define SOFT_BAR_MFGPT_FLAG 0x00000004 ++#define SOFT_BAR_IRQ_FLAG 0x00000008 ++#define SOFT_BAR_PMS_FLAG 0x00000010 ++#define SOFT_BAR_ACPI_FLAG 0x00000020 ++#define SOFT_BAR_FLSH0_FLAG 0x00000040 ++#define SOFT_BAR_FLSH1_FLAG 0x00000080 ++#define SOFT_BAR_FLSH2_FLAG 0x00000100 ++#define SOFT_BAR_FLSH3_FLAG 0x00000200 ++#define SOFT_BAR_IDE_FLAG 0x00000400 ++#define SOFT_BAR_ACC_FLAG 0x00000800 ++#define SOFT_BAR_OHCI_FLAG 0x00001000 ++#define SOFT_BAR_EHCI_FLAG 0x00002000 ++#define SOFT_BAR_UDC_FLAG 0x00004000 ++#define SOFT_BAR_OTG_FLAG 0x00008000 ++#define GLCP_RSVD2 0x0F ++#define GLCP_CLK_OFF 0x10 ++#define GLCP_CLK_ACTIVE 0x11 ++#define GLCP_CLK_DISABLE 0x12 ++#define GLCP_CLK4ACK 0x13 ++#define GLCP_SYS_RST 0x14 ++#define GLCP_RSVD3 0x15 ++#define GLCP_DBG_CLK_CTRL 0x16 ++#define GLCP_CHIP_REV_ID 0x17 ++ ++/* ++ * DIVIL STANDARD ++ */ ++#define DIVIL_CAP 0x00 ++#define DIVIL_CONFIG 0x01 ++#define DIVIL_SMI 0x02 ++#define DIVIL_ERROR 0x03 ++#define DIVIL_PM 0x04 ++#define DIVIL_DIAG 0x05 ++ ++/* ++ * DIVIL SPEC. ++ */ ++#define DIVIL_LBAR_IRQ 0x08 ++#define DIVIL_LBAR_KEL 0x09 ++#define DIVIL_LBAR_SMB 0x0B ++#define DIVIL_LBAR_GPIO 0x0C ++#define DIVIL_LBAR_MFGPT 0x0D ++#define DIVIL_LBAR_ACPI 0x0E ++#define DIVIL_LBAR_PMS 0x0F ++#define DIVIL_LBAR_FLSH0 0x10 ++#define DIVIL_LBAR_FLSH1 0x11 ++#define DIVIL_LBAR_FLSH2 0x12 ++#define DIVIL_LBAR_FLSH3 0x13 ++#define DIVIL_LEG_IO 0x14 ++#define DIVIL_BALL_OPTS 0x15 ++#define DIVIL_SOFT_IRQ 0x16 ++#define DIVIL_SOFT_RESET 0x17 ++/* NOR FLASH */ ++#define NORF_CTRL 0x18 ++#define NORF_T01 0x19 ++#define NORF_T23 0x1A ++/* NAND FLASH */ ++#define NANDF_DATA 0x1B ++#define NANDF_CTRL 0x1C ++#define NANDF_RSVD 0x1D ++/* KEL Keyboard Emulation Logic */ ++#define KEL_CTRL 0x1F ++/* PIC */ ++#define PIC_YSEL_LOW 0x20 ++#define PIC_YSEL_LOW_USB_SHIFT 8 ++#define PIC_YSEL_LOW_ACC_SHIFT 16 ++#define PIC_YSEL_LOW_FLASH_SHIFT 24 ++#define PIC_YSEL_HIGH 0x21 ++#define PIC_ZSEL_LOW 0x22 ++#define PIC_ZSEL_HIGH 0x23 ++#define PIC_IRQM_PRIM 0x24 ++#define PIC_IRQM_LPC 0x25 ++#define PIC_XIRR_STS_LOW 0x26 ++#define PIC_XIRR_STS_HIGH 0x27 ++#define PCI_SHDW 0x34 ++/* MFGPT */ ++#define MFGPT_IRQ 0x28 ++#define MFGPT_NR 0x29 ++#define MFGPT_RSVD 0x2A ++#define MFGPT_SETUP 0x2B ++/* FLOPPY */ ++#define FLPY_3F2_SHDW 0x30 ++#define FLPY_3F7_SHDW 0x31 ++#define FLPY_372_SHDW 0x32 ++#define FLPY_377_SHDW 0x33 ++/* PIT */ ++#define PIT_SHDW 0x36 ++#define PIT_CNTRL 0x37 ++/* UART */ ++#define UART1_MOD 0x38 ++#define UART1_DONG 0x39 ++#define UART1_CONF 0x3A ++#define UART1_RSVD 0x3B ++#define UART2_MOD 0x3C ++#define UART2_DONG 0x3D ++#define UART2_CONF 0x3E ++#define UART2_RSVD 0x3F ++/* DMA */ ++#define DIVIL_AC_DMA 0x1E ++#define DMA_MAP 0x40 ++#define DMA_SHDW_CH0 0x41 ++#define DMA_SHDW_CH1 0x42 ++#define DMA_SHDW_CH2 0x43 ++#define DMA_SHDW_CH3 0x44 ++#define DMA_SHDW_CH4 0x45 ++#define DMA_SHDW_CH5 0x46 ++#define DMA_SHDW_CH6 0x47 ++#define DMA_SHDW_CH7 0x48 ++#define DMA_MSK_SHDW 0x49 ++/* LPC */ ++#define LPC_EADDR 0x4C ++#define LPC_ESTAT 0x4D ++#define LPC_SIRQ 0x4E ++#define LPC_RSVD 0x4F ++/* PMC */ ++#define PMC_LTMR 0x50 ++#define PMC_RSVD 0x51 ++/* RTC */ ++#define RTC_RAM_LOCK 0x54 ++#define RTC_DOMA_OFFSET 0x55 ++#define RTC_MONA_OFFSET 0x56 ++#define RTC_CEN_OFFSET 0x57 ++ ++/* ++ * IDE STANDARD ++ */ ++#define IDE_CAP 0x00 ++#define IDE_CONFIG 0x01 ++#define IDE_SMI 0x02 ++#define IDE_ERROR 0x03 ++#define IDE_PM 0x04 ++#define IDE_DIAG 0x05 ++ ++/* ++ * IDE SPEC. ++ */ ++#define IDE_IO_BAR 0x08 ++#define IDE_CFG 0x10 ++#define IDE_DTC 0x12 ++#define IDE_CAST 0x13 ++#define IDE_ETC 0x14 ++#define IDE_INTERNAL_PM 0x15 ++ ++/* ++ * ACC STANDARD ++ */ ++#define ACC_CAP 0x00 ++#define ACC_CONFIG 0x01 ++#define ACC_SMI 0x02 ++#define ACC_ERROR 0x03 ++#define ACC_PM 0x04 ++#define ACC_DIAG 0x05 ++ ++/* ++ * USB STANDARD ++ */ ++#define USB_CAP 0x00 ++#define USB_CONFIG 0x01 ++#define USB_SMI 0x02 ++#define USB_ERROR 0x03 ++#define USB_PM 0x04 ++#define USB_DIAG 0x05 ++ ++/* ++ * USB SPEC. ++ */ ++#define USB_OHCI 0x08 ++#define USB_EHCI 0x09 ++#define USB_UDC 0x0A ++#define USB_OTG 0x0B ++ ++/****************** NATIVE ***************************/ ++/* GPIO : I/O SPACE; REG : 32BITS */ ++#define GPIOL_OUT_VAL 0x00 ++#define GPIOL_OUT_EN 0x04 ++ ++#endif /* _CS5536_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h rt4ls/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h 2009-06-12 16:27:08.510427596 +0200 +@@ -0,0 +1,26 @@ ++/* ++ * cs5536 mfgpt header file ++ */ ++ ++#ifndef _CS5536_MFGPT_H ++#define _CS5536_MFGPT_H ++ ++#include <cs5536/cs5536.h> ++ ++extern void setup_mfgpt_timer(void); ++ ++#if 1 ++#define MFGPT_TICK_RATE 14318000 ++#else ++#define MFGPT_TICK_RATE (14318180 / 8) ++#endif ++#define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ) ++ ++#define CS5536_MFGPT_INTR 5 ++ ++#define MFGPT_BASE mfgpt_base ++#define MFGPT0_CMP2 (MFGPT_BASE + 2) ++#define MFGPT0_CNT (MFGPT_BASE + 4) ++#define MFGPT0_SETUP (MFGPT_BASE + 6) ++ ++#endif /*!_CS5536_MFGPT_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h rt4ls/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h 2009-06-12 16:27:08.510427596 +0200 +@@ -0,0 +1,174 @@ ++/* ++ * the definition file of cs5536 Virtual Support Module(VSM). ++ * pci configuration space can be accessed through the VSM, so ++ * there is no need of the MSR read/write now, except the spec. ++ * MSR registers which are not implemented yet. ++ * ++ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology ++ * Author : jlliu, liujl@lemote.com ++ */ ++ ++#ifndef _CS5536_PCI_H ++#define _CS5536_PCI_H ++ ++#include <linux/types.h> ++#include <linux/pci_regs.h> ++ ++extern void cs5536_pci_conf_write4(int function, int reg, u32 value); ++extern u32 cs5536_pci_conf_read4(int function, int reg); ++ ++#define CS5536_FLASH_INTR 6 ++#define CS5536_ACC_INTR 9 ++#define CS5536_IDE_INTR 14 ++#define CS5536_USB_INTR 11 ++#define CS5536_UART1_INTR 4 ++#define CS5536_UART2_INTR 3 ++ ++/************** PCI BUS DEVICE FUNCTION ***************/ ++ ++/* ++ * PCI bus device function ++ */ ++#define PCI_BUS_CS5536 0 ++#define PCI_IDSEL_CS5536 14 ++ ++/********** STANDARD PCI-2.2 EXPANSION ****************/ ++ ++/* ++ * PCI configuration space ++ * we have to virtualize the PCI configure space head, so we should ++ * define the necessary IDs and some others. ++ */ ++ ++/* CONFIG of PCI VENDOR ID*/ ++#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \ ++ (((mod_dev_id) << 16) | (sys_vendor_id)) ++ ++/* VENDOR ID */ ++#define CS5536_VENDOR_ID 0x1022 ++ ++/* DEVICE ID */ ++#define CS5536_ISA_DEVICE_ID 0x2090 ++#define CS5536_FLASH_DEVICE_ID 0x2091 ++#define CS5536_IDE_DEVICE_ID 0x209a ++#define CS5536_ACC_DEVICE_ID 0x2093 ++#define CS5536_OHCI_DEVICE_ID 0x2094 ++#define CS5536_EHCI_DEVICE_ID 0x2095 ++#define CS5536_UDC_DEVICE_ID 0x2096 ++#define CS5536_OTG_DEVICE_ID 0x2097 ++ ++/* CLASS CODE : CLASS SUB-CLASS INTERFACE */ ++#define CS5536_ISA_CLASS_CODE 0x060100 ++#define CS5536_FLASH_CLASS_CODE 0x050100 ++#define CS5536_IDE_CLASS_CODE 0x010180 ++#define CS5536_ACC_CLASS_CODE 0x040100 ++#define CS5536_OHCI_CLASS_CODE 0x0C0310 ++#define CS5536_EHCI_CLASS_CODE 0x0C0320 ++#define CS5536_UDC_CLASS_CODE 0x0C03FE ++#define CS5536_OTG_CLASS_CODE 0x0C0380 ++ ++/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */ ++ ++#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \ ++ ((PCI_NONE_BIST << 24) | ((header_type) << 16) \ ++ | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE); ++ ++#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */ ++#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */ ++#define PCI_NORMAL_HEADER_TYPE 0x00 ++#define PCI_NORMAL_LATENCY_TIMER 0x00 ++#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */ ++ ++/* BAR */ ++#define PCI_BAR0_REG 0x10 ++#define PCI_BAR1_REG 0x14 ++#define PCI_BAR2_REG 0x18 ++#define PCI_BAR3_REG 0x1c ++#define PCI_BAR4_REG 0x20 ++#define PCI_BAR5_REG 0x24 ++#define PCI_BAR_COUNT 6 ++#define PCI_BAR_RANGE_MASK 0xFFFFFFFF ++ ++/* CARDBUS CIS POINTER */ ++#define PCI_CARDBUS_CIS_POINTER 0x00000000 ++ ++/* SUBSYSTEM VENDOR ID */ ++#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID ++ ++/* SUBSYSTEM ID */ ++#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID ++#define CS5536_FLASH_SUB_ID CS5536_FLASH_DEVICE_ID ++#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID ++#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID ++#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID ++#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID ++#define CS5536_UDC_SUB_ID CS5536_UDC_DEVICE_ID ++#define CS5536_OTG_SUB_ID CS5536_OTG_DEVICE_ID ++ ++/* EXPANSION ROM BAR */ ++#define PCI_EXPANSION_ROM_BAR 0x00000000 ++ ++/* CAPABILITIES POINTER */ ++#define PCI_CAPLIST_POINTER 0x00000000 ++#define PCI_CAPLIST_USB_POINTER 0x40 ++/* INTERRUPT */ ++ ++#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \ ++ ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \ ++ ((pin) << 8) | (mod_intr)) ++ ++#define PCI_MAX_LATENCY 0x40 ++#define PCI_MIN_GRANT 0x00 ++#define PCI_DEFAULT_PIN 0x01 ++ ++/*********** EXPANSION PCI REG ************************/ ++ ++/* ++ * ISA EXPANSION ++ */ ++#define PCI_UART1_INT_REG 0x50 ++#define PCI_UART2_INT_REG 0x54 ++#define PCI_ISA_FIXUP_REG 0x58 ++ ++/* ++ * FLASH EXPANSION ++ */ ++#define PCI_FLASH_INT_REG 0x50 ++#define PCI_NOR_FLASH_CTRL_REG 0x40 ++#define PCI_NOR_FLASH_T01_REG 0x44 ++#define PCI_NOR_FLASH_T23_REG 0x48 ++#define PCI_NAND_FLASH_TDATA_REG 0x60 ++#define PCI_NAND_FLASH_TCTRL_REG 0x64 ++#define PCI_NAND_FLASH_RSVD_REG 0x68 ++#define PCI_FLASH_SELECT_REG 0x70 ++ ++/* ++ * IDE EXPANSION ++ */ ++#define PCI_IDE_CFG_REG 0x40 ++#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF ++#define PCI_IDE_DTC_REG 0x48 ++#define PCI_IDE_CAST_REG 0x4C ++#define PCI_IDE_ETC_REG 0x50 ++#define PCI_IDE_PM_REG 0x54 ++#define PCI_IDE_INT_REG 0x60 ++ ++/* ++ * ACC EXPANSION ++ */ ++#define PCI_ACC_INT_REG 0x50 ++ ++/* ++ * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI ++ */ ++#define PCI_OHCI_PM_REG 0x40 ++#define PCI_OHCI_INT_REG 0x50 ++ ++/* ++ * EHCI EXPANSION ++ */ ++#define PCI_EHCI_LEGSMIEN_REG 0x50 ++#define PCI_EHCI_LEGSMISTS_REG 0x54 ++#define PCI_EHCI_FLADJ_REG 0x60 ++ ++#endif /* _CS5536_PCI_H_ */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h rt4ls/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h 2009-06-12 16:27:08.510427596 +0200 +@@ -0,0 +1,59 @@ ++/* ++ * the Virtual Support Module(VSM) read/write interfaces ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin <wuzj@lemote.com> ++ */ ++ ++#ifndef _CS5536_VSM_H ++#define _CS5536_VSM_H ++ ++#include <linux/types.h> ++ ++#define DECLARE_CS5536_MODULE(name) \ ++extern void pci_##name##_write_reg(int reg, u32 value); \ ++extern u32 pci_##name##_read_reg(int reg); ++ ++#define DEFINE_CS5536_MODULE(name) \ ++void pci_##name##_write_reg(int reg, u32 value)\ ++{ \ ++ return; \ ++} \ ++u32 pci_##name##_read_reg(int reg) \ ++{ \ ++ return 0xffffffff; \ ++} \ ++ ++/* core modules of cs5536 */ ++ ++/* ide module */ ++DECLARE_CS5536_MODULE(ide) ++/* acc module */ ++DECLARE_CS5536_MODULE(acc) ++/* ohci module */ ++DECLARE_CS5536_MODULE(ohci) ++/* isa module */ ++DECLARE_CS5536_MODULE(isa) ++/* ehci module */ ++DECLARE_CS5536_MODULE(ehci) ++ ++/* selective modules of cs5536 */ ++/* flash(nor or nand flash) module */ ++#ifdef CONFIG_CS5536_FLASH ++ DECLARE_CS5536_MODULE(flash) ++#else ++ DEFINE_CS5536_MODULE(flash) ++#endif ++/* otg module */ ++#ifdef CONFIG_CS5536_OTG ++ DECLARE_CS5536_MODULE(otg) ++#else ++ DEFINE_CS5536_MODULE(otg) ++#endif ++/* udc module */ ++#ifdef CONFIG_CS5536_UDC ++ DECLARE_CS5536_MODULE(udc) ++#else ++ DEFINE_CS5536_MODULE(udc) ++#endif ++#endif /* _CS5536_VSM_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/dma-coherence.h rt4ls/arch/mips/include/asm/mach-loongson/dma-coherence.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/dma-coherence.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/dma-coherence.h 2009-06-12 16:27:08.510427596 +0200 +@@ -0,0 +1,70 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2006, 07 Ralf Baechle <ralf@linux-mips.org> ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ */ ++#ifndef __ASM_MACH_LOONGSON_DMA_COHERENCE_H ++#define __ASM_MACH_LOONGSON_DMA_COHERENCE_H ++ ++struct device; ++ ++static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, ++ size_t size) ++{ ++ return virt_to_phys(addr) | 0x80000000; ++} ++ ++static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, ++ struct page *page) ++{ ++ return page_to_phys(page) | 0x80000000; ++} ++ ++static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) ++{ ++#if defined(CONFIG_CPU_LOONGSON2F) & defined(CONFIG_64BIT) ++ return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff); ++#else ++ return dma_addr & 0x7fffffff; ++#endif ++} ++ ++static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) ++{ ++} ++ ++static inline int plat_dma_supported(struct device *dev, u64 mask) ++{ ++ /* ++ * we fall back to GFP_DMA when the mask isn't all 1s, ++ * so we can't guarantee allocations that must be ++ * within a tighter range than GFP_DMA.. ++ */ ++ if (mask < DMA_BIT_MASK(24)) ++ return 0; ++ ++ return 1; ++} ++ ++static inline void plat_extra_sync_for_device(struct device *dev) ++{ ++ return; ++} ++ ++static inline int plat_dma_mapping_error(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return 0; ++} ++ ++static inline int plat_device_is_coherent(struct device *dev) ++{ ++ return 0; ++} ++ ++#endif /* __ASM_MACH_LOONGSON_DMA_COHERENCE_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/loongson.h rt4ls/arch/mips/include/asm/mach-loongson/loongson.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/loongson.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/loongson.h 2009-06-12 16:27:08.510427596 +0200 +@@ -0,0 +1,319 @@ ++/* ++ * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca> ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin <wuzj@lemote.com> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef __LOONGSON_H ++#define __LOONGSON_H ++ ++#include <linux/io.h> ++#include <linux/init.h> ++ ++/* loongson internal northbridge initialization */ ++extern void bonito_irq_init(void); ++ ++/* environment arguments from bootloader */ ++extern unsigned long bus_clock, cpu_clock_freq; ++extern unsigned long memsize, highmemsize; ++ ++/* loongson-based machines specific reboot setup */ ++extern void loongson_reboot_setup(void); ++ ++/* loongson-specific command line, env and memory initialization */ ++extern void __init prom_init_memory(void); ++extern void __init prom_init_cmdline(void); ++extern void __init prom_init_env(void); ++ ++/* irq operation functions */ ++extern void bonito_irqdispatch(void); ++extern void i8259_irqdispatch(void); ++extern void __init bonito_irq_init(void); ++extern void __init set_irq_trigger_mode(void); ++extern int mach_i8259_irq(void); ++extern void mach_irq_dispatch(unsigned int pending); ++ ++/* machine-specific reboot/halt operation */ ++extern void mach_prepare_reboot(void); ++extern void mach_prepare_shutdown(void); ++ ++/* We need this in some places... */ ++#define delay() ({ \ ++ int x; \ ++ for (x = 0; x < 100000; x++) \ ++ __asm__ __volatile__(""); \ ++}) ++ ++/* loongson-specific cpu frequency relative stuff */ ++#ifdef CONFIG_LOONGSON2F_CPU_FREQ ++#include <linux/cpufreq.h> ++extern void loongson2f_cpu_wait(void); ++extern struct cpufreq_frequency_table loongson2f_clockmod_table[]; ++#endif ++ ++#define LOONGSON_REG(x) \ ++ (*(u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) ++ ++#define LOONGSON_IRQ_BASE 32 ++#define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ ++ ++#define LOONGSON_FLASH_BASE 0x1c000000 ++#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */ ++#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1) ++ ++#define LOONGSON_LIO0_BASE 0x1e000000 ++#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */ ++#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1) ++ ++#define LOONGSON_BOOT_BASE 0x1fc00000 ++#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */ ++#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1) ++#define LOONGSON_REG_BASE 0x1fe00000 ++#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ ++#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1) ++ ++#define LOONGSON_LIO1_BASE 0x1ff00000 ++#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */ ++#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1) ++ ++#define LOONGSON_PCILO0_BASE 0x10000000 ++#define LOONGSON_PCILO1_BASE 0x14000000 ++#define LOONGSON_PCILO2_BASE 0x18000000 ++#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE ++#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */ ++#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1) ++ ++#define LOONGSON_PCICFG_BASE 0x1fe80000 ++#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */ ++#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1) ++#define LOONGSON_PCIIO_BASE 0x1fd00000 ++#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */ ++#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1) ++ ++/* Loongson Register Bases */ ++ ++#define LOONGSON_PCICONFIGBASE 0x00 ++#define LOONGSON_REGBASE 0x100 ++ ++/* PCI Configuration Registers */ ++ ++#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x)) ++#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00) ++#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04) ++#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08) ++#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c) ++#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10) ++#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14) ++#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18) ++#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c) ++#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20) ++#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30) ++#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c) ++ ++#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c) ++ ++#define LOONGSON_PCICMD_PERR_CLR 0x80000000 ++#define LOONGSON_PCICMD_SERR_CLR 0x40000000 ++#define LOONGSON_PCICMD_MABORT_CLR 0x20000000 ++#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000 ++#define LOONGSON_PCICMD_TABORT_CLR 0x08000000 ++#define LOONGSON_PCICMD_MPERR_CLR 0x01000000 ++#define LOONGSON_PCICMD_PERRRESPEN 0x00000040 ++#define LOONGSON_PCICMD_ASTEPEN 0x00000080 ++#define LOONGSON_PCICMD_SERREN 0x00000100 ++#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00 ++#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8 ++ ++/* Loongson h/w Configuration */ ++ ++#define LOONGSON_GENCFG_OFFSET 0x4 ++#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET) ++ ++#define LOONGSON_GENCFG_DEBUGMODE 0x00000001 ++#define LOONGSON_GENCFG_SNOOPEN 0x00000002 ++#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004 ++ ++#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008 ++#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010 ++#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020 ++#define LOONGSON_GENCFG_BYTESWAP 0x00000040 ++ ++#define LOONGSON_GENCFG_UNCACHED 0x00000080 ++#define LOONGSON_GENCFG_PREFETCHEN 0x00000100 ++#define LOONGSON_GENCFG_WBEHINDEN 0x00000200 ++#define LOONGSON_GENCFG_CACHEALG 0x00000c00 ++#define LOONGSON_GENCFG_CACHEALG_SHIFT 10 ++#define LOONGSON_GENCFG_PCIQUEUE 0x00001000 ++#define LOONGSON_GENCFG_CACHESTOP 0x00002000 ++#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000 ++#define LOONGSON_GENCFG_BUSERREN 0x00008000 ++#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000 ++#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000 ++ ++/* PCI address map control */ ++ ++#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10) ++#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14) ++#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18) ++ ++/* GPIO Regs - r/w */ ++ ++#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c) ++#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20) ++ ++/* ICU Configuration Regs - r/w */ ++ ++#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24) ++#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) ++#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c) ++ ++/* ICU Enable Regs - IntEn & IntISR are r/o. */ ++ ++#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) ++#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) ++#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38) ++#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c) ++ ++/* ICU */ ++#define LOONGSON_ICU_MBOXES 0x0000000f ++#define LOONGSON_ICU_MBOXES_SHIFT 0 ++#define LOONGSON_ICU_DMARDY 0x00000010 ++#define LOONGSON_ICU_DMAEMPTY 0x00000020 ++#define LOONGSON_ICU_COPYRDY 0x00000040 ++#define LOONGSON_ICU_COPYEMPTY 0x00000080 ++#define LOONGSON_ICU_COPYERR 0x00000100 ++#define LOONGSON_ICU_PCIIRQ 0x00000200 ++#define LOONGSON_ICU_MASTERERR 0x00000400 ++#define LOONGSON_ICU_SYSTEMERR 0x00000800 ++#define LOONGSON_ICU_DRAMPERR 0x00001000 ++#define LOONGSON_ICU_RETRYERR 0x00002000 ++#define LOONGSON_ICU_GPIOS 0x01ff0000 ++#define LOONGSON_ICU_GPIOS_SHIFT 16 ++#define LOONGSON_ICU_GPINS 0x7e000000 ++#define LOONGSON_ICU_GPINS_SHIFT 25 ++#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N))) ++#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N))) ++#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N))) ++ ++/* PCI prefetch window base & mask */ ++ ++#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40) ++#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44) ++#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48) ++#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c) ++ ++/* PCI_Hit*_Sel_* */ ++ ++#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50) ++#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54) ++#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58) ++#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c) ++#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60) ++#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64) ++ ++/* PXArb Config & Status */ ++ ++#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68) ++#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c) ++ ++/* Chip Config */ ++#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) ++ ++/* pcimap */ ++ ++#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f ++#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0 ++#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0 ++#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6 ++#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000 ++#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12 ++#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000 ++#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \ ++ ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) ++ ++/* ++ * address windows configuration module ++ * ++ * loongson2e do not have this module ++ */ ++#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) ++ ++/* address window config module base address */ ++#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul ++#define LOONGSON_ADDRWINCFG_SIZE 0x180 ++ ++extern unsigned long _loongson_addrwincfg_base; ++#define LOONGSON_ADDRWINCFG(offset) \ ++ (*(u64 *)(_loongson_addrwincfg_base + (offset))) ++ ++#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00) ++#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08) ++#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10) ++#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18) ++ ++#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20) ++#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28) ++#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30) ++#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38) ++ ++#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40) ++#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48) ++#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50) ++#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58) ++ ++#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60) ++#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68) ++#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70) ++#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78) ++ ++#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80) ++#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88) ++#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90) ++#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98) ++ ++#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0) ++#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8) ++#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0) ++#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8) ++ ++#define ADDRWIN_WIN0 0 ++#define ADDRWIN_WIN1 1 ++#define ADDRWIN_WIN2 2 ++#define ADDRWIN_WIN3 3 ++ ++#define ADDRWIN_MAP_DST_DDR 0 ++#define ADDRWIN_MAP_DST_PCI 1 ++#define ADDRWIN_MAP_DST_LIO 1 ++ ++/* ++ * s: CPU, PCIDMA ++ * d: DDR, PCI, LIO ++ * win: 0, 1, 2, 3 ++ * src: map source ++ * dst: map destination ++ * size: ~mask + 1 ++ */ ++#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\ ++ s##_WIN##w##_BASE = (src); \ ++ s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \ ++ s##_WIN##w##_MASK = ~(size-1); \ ++} while (0) ++ ++#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \ ++ LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size) ++#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \ ++ LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size) ++#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \ ++ LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size) ++ ++#endif /* ! CONFIG_CPU_LOONGSON2F && CONFIG_64BIT */ ++ ++#endif /* __LOONGSON_H */ ++ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/machine.h rt4ls/arch/mips/include/asm/mach-loongson/machine.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/machine.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/machine.h 2009-06-12 16:27:08.510427596 +0200 +@@ -0,0 +1,76 @@ ++/* ++ * board-specific header file ++ * ++ * Copyright (c) 2009 Wu Zhangjin <wuzj@lemote.com> ++ * ++ * Copyright (C) 2009 Zhang Le ++ * ++ * This program is free software; you can redistribute it ++ * and/or modify it under the terms of the GNU General ++ * Public License as published by the Free Software ++ * Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __MACHINE_H ++#define __MACHINE_H ++ ++#ifdef CONFIG_LEMOTE_FULOONG2E ++ ++#define MACHTYPE MACH_LEMOTE_FL2E ++ ++#define LOONGSON_UART_BASE (LOONGSON_PCIIO_BASE + 0x3f8) ++#define LOONGSON_UART_BAUD 1843200 ++#define LOONGSON_UART_IOTYPE UPIO_PORT ++ ++#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) ++#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 4) ++#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 5) ++#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) ++#define LOONGSON_DMATIMEOUT_IRQ (LOONGSON_IRQ_BASE + 10) ++ ++#elif defined(CONFIG_LEMOTE_FULOONG2F) ++ ++#define MACHTYPE MACH_LEMOTE_FL2F ++ ++#define LOONGSON_UART_BASE (LOONGSON_PCIIO_BASE + 0x2f8) ++#define LOONGSON_UART_BAUD 1843200 ++#define LOONGSON_UART_IOTYPE UPIO_PORT ++ ++#else /* CONFIG_CPU_YEELOONG2F */ ++ ++#define MACHTYPE MACH_LEMOTE_YL2F89 ++ ++/* yeeloong use the CPU serial port of Loongson2F */ ++#define LOONGSON_UART_BASE (LOONGSON_LIO1_BASE + 0x3f8) ++#define LOONGSON_UART_BAUD 3686400 ++#define LOONGSON_UART_IOTYPE UPIO_MEM ++ ++#endif /* !CONFIG_LEMOTE_FULOONG2E */ ++ ++/* fuloong2f and yeeloong2f have the same IRQ control interface */ ++#if defined(CONFIG_LEMOTE_FULOONG2F) || defined(CONFIG_LEMOTE_YEELOONG2F) ++ ++#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */ ++#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */ ++#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */ ++#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */ ++ ++#define LOONGSON_INT_BIT_GPIO1 (1 << 1) ++#define LOONGSON_INT_BIT_GPIO2 (1 << 2) ++#define LOONGSON_INT_BIT_GPIO3 (1 << 3) ++#define LOONGSON_INT_BIT_PCI_INTA (1 << 4) ++#define LOONGSON_INT_BIT_PCI_INTB (1 << 5) ++#define LOONGSON_INT_BIT_PCI_INTC (1 << 6) ++#define LOONGSON_INT_BIT_PCI_INTD (1 << 7) ++#define LOONGSON_INT_BIT_PCI_PERR (1 << 8) ++#define LOONGSON_INT_BIT_PCI_SERR (1 << 9) ++#define LOONGSON_INT_BIT_DDR (1 << 10) ++#define LOONGSON_INT_BIT_INT0 (1 << 11) ++#define LOONGSON_INT_BIT_INT1 (1 << 12) ++#define LOONGSON_INT_BIT_INT2 (1 << 13) ++#define LOONGSON_INT_BIT_INT3 (1 << 14) ++ ++#endif ++ ++#endif /* ! __MACHINE_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/mc146818rtc.h rt4ls/arch/mips/include/asm/mach-loongson/mc146818rtc.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/mc146818rtc.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/mc146818rtc.h 2009-06-12 16:27:08.510427596 +0200 +@@ -0,0 +1,36 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org) ++ * ++ * RTC routines for PC style attached Dallas chip. ++ */ ++#ifndef __ASM_MACH_LOONGSON_MC146818RTC_H ++#define __ASM_MACH_LOONGSON_MC146818RTC_H ++ ++#include <linux/io.h> ++ ++#define RTC_PORT(x) (0x70 + (x)) ++#define RTC_IRQ 8 ++ ++static inline unsigned char CMOS_READ(unsigned long addr) ++{ ++ outb_p(addr, RTC_PORT(0)); ++ return inb_p(RTC_PORT(1)); ++} ++ ++static inline void CMOS_WRITE(unsigned char data, unsigned long addr) ++{ ++ outb_p(addr, RTC_PORT(0)); ++ outb_p(data, RTC_PORT(1)); ++} ++ ++#define RTC_ALWAYS_BCD 0 ++ ++#ifndef mc146818_decode_year ++#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) ++#endif ++ ++#endif /* __ASM_MACH_LOONGSON_MC146818RTC_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/mem.h rt4ls/arch/mips/include/asm/mach-loongson/mem.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/mem.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/mem.h 2009-06-12 16:27:08.510427596 +0200 +@@ -0,0 +1,31 @@ ++#ifndef __MEM_H ++#define __MEM_H ++ ++/* ++ * high memory space ++ * ++ * in loongson2e, starts from 512M ++ * in loongson2f, starts from 2G + 256M ++ */ ++#ifdef CONFIG_CPU_LOONGSON2E ++#define LOONGSON_HIGHMEM_START 0x20000000 ++#else ++#define LOONGSON_HIGHMEM_START 0x90000000 ++#endif ++ ++/* ++ * the peripheral registers(MMIO): ++ * ++ * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000. ++ * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000. ++ */ ++ ++#define LOONGSON_MMIO_MEM_START 0x10000000 ++ ++#ifdef CONFIG_CPU_LOONGSON2E ++#define LOONGSON_MMIO_MEM_END 0x20000000 ++#else ++#define LOONGSON_MMIO_MEM_END 0x80000000 ++#endif ++ ++#endif /* !__MEM_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/pci.h rt4ls/arch/mips/include/asm/mach-loongson/pci.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/pci.h 2009-06-12 16:27:08.514429781 +0200 +@@ -0,0 +1,59 @@ ++/* ++ * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org> ++ * Copyright (c) 2009 Wu Zhangjin <wuzj@lemote.com> ++ * ++ * This program is free software; you can redistribute it ++ * and/or modify it under the terms of the GNU General ++ * Public License as published by the Free Software ++ * Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be ++ * useful, but WITHOUT ANY WARRANTY; without even the implied ++ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ++ * PURPOSE. See the GNU General Public License for more ++ * details. ++ * ++ * You should have received a copy of the GNU General Public ++ * License along with this program; if not, write to the Free ++ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA ++ * 02139, USA. ++ */ ++ ++#ifndef _LOONGSON_PCI_H_ ++#define _LOONGSON_PCI_H_ ++ ++extern struct pci_ops loongson_pci_ops; ++ ++/* this is an offset from mips_io_port_base */ ++#define LOONGSON_PCI_IO_START 0x00004000UL ++ ++#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) ++ ++/* ++ * we use address window2 to map cpu address space to pci space ++ * window2: cpu [1G, 2G] -> pci [1G, 2G] ++ * why not use window 0 & 1? because they are used by cpu when booting. ++ * window0: cpu [0, 256M] -> ddr [0, 256M] ++ * window1: cpu [256M, 512M] -> pci [256M, 512M] ++ */ ++ ++/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */ ++#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */ ++#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC ++ ++#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST ++#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */ ++ ++#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ ++ LOONGSON_PCI_MEM_START + 1) ++ ++#else /* loongson2f/32bit & loongson2e */ ++ ++#define LOONGSON_PCI_MEM_START 0x14000000UL ++#define LOONGSON_PCI_MEM_END 0x1fffffffUL ++ ++#endif /* !(defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT))*/ ++ ++ ++#endif /* !_LOONGSON_PCI_H_ */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mach-loongson/war.h rt4ls/arch/mips/include/asm/mach-loongson/war.h +--- linux-2.6.30/arch/mips/include/asm/mach-loongson/war.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/include/asm/mach-loongson/war.h 2009-06-12 16:27:08.514429781 +0200 +@@ -0,0 +1,25 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> ++ */ ++#ifndef __ASM_MIPS_MACH_LOONGSON_WAR_H ++#define __ASM_MIPS_MACH_LOONGSON_WAR_H ++ ++#define R4600_V1_INDEX_ICACHEOP_WAR 0 ++#define R4600_V1_HIT_CACHEOP_WAR 0 ++#define R4600_V2_HIT_CACHEOP_WAR 0 ++#define R5432_CP0_INTERRUPT_WAR 0 ++#define BCM1250_M3_WAR 0 ++#define SIBYTE_1956_WAR 0 ++#define MIPS4K_ICACHE_REFILL_WAR 0 ++#define MIPS_CACHE_SYNC_WAR 0 ++#define TX49XX_ICACHE_INDEX_INV_WAR 0 ++#define RM9000_CDEX_SMP_WAR 0 ++#define ICACHE_REFILLS_WORKAROUND_WAR 0 ++#define R10000_LLSC_WAR 0 ++#define MIPS34K_MISSED_ITLB_WAR 0 ++ ++#endif /* __ASM_MIPS_MACH_LOONGSON_WAR_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/mips-boards/bonito64.h rt4ls/arch/mips/include/asm/mips-boards/bonito64.h +--- linux-2.6.30/arch/mips/include/asm/mips-boards/bonito64.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/mips-boards/bonito64.h 2009-06-12 16:27:08.574431556 +0200 +@@ -26,11 +26,6 @@ + /* offsets from base register */ + #define BONITO(x) (x) + +-#elif defined(CONFIG_LEMOTE_FULONG) +- +-#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x))) +-#define BONITO_IRQ_BASE 32 +- + #else + + /* +diff -Nur linux-2.6.30/arch/mips/include/asm/page.h rt4ls/arch/mips/include/asm/page.h +--- linux-2.6.30/arch/mips/include/asm/page.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/page.h 2009-06-12 16:27:08.602426182 +0200 +@@ -179,8 +179,9 @@ + + #endif + +-#define virt_to_page(kaddr) pfn_to_page(PFN_DOWN(virt_to_phys(kaddr))) +-#define virt_addr_valid(kaddr) pfn_valid(PFN_DOWN(virt_to_phys(kaddr))) ++#define virt_to_page(kaddr) \ ++ pfn_to_page(PFN_DOWN(virt_to_phys((void *)kaddr))) ++#define virt_addr_valid(kaddr) pfn_valid(PFN_DOWN(virt_to_phys((void *)kaddr))) + + #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) +diff -Nur linux-2.6.30/arch/mips/include/asm/pci.h rt4ls/arch/mips/include/asm/pci.h +--- linux-2.6.30/arch/mips/include/asm/pci.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/pci.h 2009-06-12 16:27:08.606433396 +0200 +@@ -56,7 +56,7 @@ + /* + * board supplied pci irq fixup routine + */ +-extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); ++extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin); + + + /* Can be used to override the logic in pci_scan_bus for skipping +diff -Nur linux-2.6.30/arch/mips/include/asm/pgtable.h rt4ls/arch/mips/include/asm/pgtable.h +--- linux-2.6.30/arch/mips/include/asm/pgtable.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/pgtable.h 2009-06-12 16:27:08.610435582 +0200 +@@ -370,6 +370,19 @@ + #include <asm-generic/pgtable.h> + + /* ++ * uncache accelerate for video memory access ++ */ ++#ifdef CONFIG_LOONGSON2F ++#define __HAVE_PHYS_MEM_ACCESS_PROT ++ ++struct file; ++pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, ++ unsigned long size, pgprot_t vma_prot); ++int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, ++ unsigned long size, pgprot_t *vma_prot); ++#endif ++ ++/* + * We provide our own get_unmapped area to cope with the virtual aliasing + * constraints placed on us by the cache architecture. + */ +diff -Nur linux-2.6.30/arch/mips/include/asm/stackframe.h rt4ls/arch/mips/include/asm/stackframe.h +--- linux-2.6.30/arch/mips/include/asm/stackframe.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/stackframe.h 2009-06-12 16:27:08.674441225 +0200 +@@ -117,6 +117,20 @@ + .endm + #else + .macro get_saved_sp /* Uniprocessor variation */ ++#ifdef CONFIG_CPU_LOONGSON2 ++ move k0, ra ++ jal 2008f ++ nop ++2008 : jal 2008f ++ nop ++2008 : jal 2008f ++ nop ++2008 : jal 2008f ++ nop ++2008 : move ra, k0 ++ li k0, 3 ++ mtc0 k0, $22 ++#endif + #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(kernelsp) + #else +diff -Nur linux-2.6.30/arch/mips/include/asm/suspend.h rt4ls/arch/mips/include/asm/suspend.h +--- linux-2.6.30/arch/mips/include/asm/suspend.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/suspend.h 2009-06-12 16:27:08.678439779 +0200 +@@ -1,6 +1,9 @@ + #ifndef __ASM_SUSPEND_H + #define __ASM_SUSPEND_H + +-/* Somewhen... Maybe :-) */ ++static inline int arch_prepare_suspend(void) { return 0; } ++ ++/* References to section boundaries */ ++extern const void __nosave_begin, __nosave_end; + + #endif /* __ASM_SUSPEND_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/txx9/generic.h rt4ls/arch/mips/include/asm/txx9/generic.h +--- linux-2.6.30/arch/mips/include/asm/txx9/generic.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/txx9/generic.h 2009-06-12 16:27:08.686439682 +0200 +@@ -37,7 +37,7 @@ + void (*arch_init)(void); + void (*device_init)(void); + #ifdef CONFIG_PCI +- int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin); ++ int (*pci_map_irq)(struct pci_dev *dev, u8 slot, u8 pin); + #endif + }; + extern struct txx9_board_vec *txx9_board_vec; +diff -Nur linux-2.6.30/arch/mips/include/asm/txx9/jmr3927.h rt4ls/arch/mips/include/asm/txx9/jmr3927.h +--- linux-2.6.30/arch/mips/include/asm/txx9/jmr3927.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/txx9/jmr3927.h 2009-06-12 16:27:08.686439682 +0200 +@@ -175,6 +175,6 @@ + void jmr3927_prom_init(void); + void jmr3927_irq_setup(void); + struct pci_dev; +-int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); ++int jmr3927_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); + + #endif /* __ASM_TXX9_JMR3927_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/txx9/rbtx4927.h rt4ls/arch/mips/include/asm/txx9/rbtx4927.h +--- linux-2.6.30/arch/mips/include/asm/txx9/rbtx4927.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/txx9/rbtx4927.h 2009-06-12 16:27:08.690440751 +0200 +@@ -87,6 +87,6 @@ + void rbtx4927_prom_init(void); + void rbtx4927_irq_setup(void); + struct pci_dev; +-int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); ++int rbtx4927_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); + + #endif /* __ASM_TXX9_RBTX4927_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/txx9/rbtx4938.h rt4ls/arch/mips/include/asm/txx9/rbtx4938.h +--- linux-2.6.30/arch/mips/include/asm/txx9/rbtx4938.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/txx9/rbtx4938.h 2009-06-12 16:27:08.690440751 +0200 +@@ -140,6 +140,6 @@ + void rbtx4938_prom_init(void); + void rbtx4938_irq_setup(void); + struct pci_dev; +-int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); ++int rbtx4938_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); + + #endif /* __ASM_TXX9_RBTX4938_H */ +diff -Nur linux-2.6.30/arch/mips/include/asm/txx9/tx4938.h rt4ls/arch/mips/include/asm/txx9/tx4938.h +--- linux-2.6.30/arch/mips/include/asm/txx9/tx4938.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/txx9/tx4938.h 2009-06-12 16:27:08.690440751 +0200 +@@ -287,7 +287,7 @@ + void tx4938_report_pci1clk(void); + int tx4938_pciclk66_setup(void); + struct pci_dev; +-int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); ++int tx4938_pcic1_map_irq(struct pci_dev *dev, u8 slot); + void tx4938_setup_pcierr_irq(void); + void tx4938_irq_init(void); + void tx4938_mtd_init(int ch); +diff -Nur linux-2.6.30/arch/mips/include/asm/txx9/tx4939.h rt4ls/arch/mips/include/asm/txx9/tx4939.h +--- linux-2.6.30/arch/mips/include/asm/txx9/tx4939.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/include/asm/txx9/tx4939.h 2009-06-12 16:27:08.694430645 +0200 +@@ -534,8 +534,8 @@ + int tx4939_report_pciclk(void); + void tx4939_report_pci1clk(void); + struct pci_dev; +-int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot); +-int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); ++int tx4939_pcic1_map_irq(struct pci_dev *dev, u8 slot); ++int tx4939_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); + void tx4939_setup_pcierr_irq(void); + void tx4939_irq_init(void); + int tx4939_irq(void); +diff -Nur linux-2.6.30/arch/mips/kernel/Makefile rt4ls/arch/mips/kernel/Makefile +--- linux-2.6.30/arch/mips/kernel/Makefile 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/kernel/Makefile 2009-06-12 16:27:08.710440787 +0200 +@@ -73,6 +73,7 @@ + obj-$(CONFIG_MIPS32_COMPAT) += linux32.o ptrace32.o signal32.o + obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o + obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o ++obj-$(CONFIG_LOONGSON2F_CPU_FREQ) += loongson2f_freq.o + + obj-$(CONFIG_KGDB) += kgdb.o + obj-$(CONFIG_PROC_FS) += proc.o +diff -Nur linux-2.6.30/arch/mips/kernel/asm-offsets.c rt4ls/arch/mips/kernel/asm-offsets.c +--- linux-2.6.30/arch/mips/kernel/asm-offsets.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/kernel/asm-offsets.c 2009-06-12 16:27:08.710440787 +0200 +@@ -14,6 +14,7 @@ + #include <linux/mm.h> + #include <linux/interrupt.h> + #include <linux/kbuild.h> ++#include <linux/suspend.h> + #include <asm/ptrace.h> + #include <asm/processor.h> + +@@ -326,3 +327,15 @@ + BLANK(); + } + #endif ++ ++#ifdef CONFIG_HIBERNATION ++void output_pbe_defines(void) ++{ ++ COMMENT(" Linux struct pbe offsets. "); ++ OFFSET(PBE_ADDRESS, pbe, address); ++ OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address); ++ OFFSET(PBE_NEXT, pbe, next); ++ DEFINE(PBE_SIZE, sizeof(struct pbe)); ++ BLANK(); ++} ++#endif +diff -Nur linux-2.6.30/arch/mips/kernel/i8259.c rt4ls/arch/mips/kernel/i8259.c +--- linux-2.6.30/arch/mips/kernel/i8259.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/kernel/i8259.c 2009-06-12 16:27:08.722442317 +0200 +@@ -177,10 +177,12 @@ + outb(cached_slave_mask, PIC_SLAVE_IMR); + outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */ + outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */ ++ inb(PIC_MASTER_CMD); /* flush posted write */ + } else { + inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ + outb(cached_master_mask, PIC_MASTER_IMR); + outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ ++ inb(PIC_MASTER_CMD); /* flush posted write */ + } + smtc_im_ack_irq(irq); + spin_unlock_irqrestore(&i8259A_lock, flags); +diff -Nur linux-2.6.30/arch/mips/kernel/loongson2f_freq.c rt4ls/arch/mips/kernel/loongson2f_freq.c +--- linux-2.6.30/arch/mips/kernel/loongson2f_freq.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/kernel/loongson2f_freq.c 2009-06-12 16:27:08.726441989 +0200 +@@ -0,0 +1,216 @@ ++/* ++ * arch/mips/kernel/cpufreq.c ++ * ++ * cpufreq driver for the loongson-2f processors. ++ * ++ * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology ++ * Author: Yanhua, yanh@lemote.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ */ ++#include <linux/types.h> ++#include <linux/cpufreq.h> ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/err.h> ++#include <linux/cpumask.h> ++#include <linux/smp.h> ++#include <linux/sched.h> /* set_cpus_allowed() */ ++#include <linux/clk.h> ++#include <linux/delay.h> ++ ++#include <loongson.h> ++#include <clock.h> ++ ++static uint nowait; ++ ++static struct clk *cpuclk; ++ ++static void (*saved_cpu_wait) (void); ++ ++static int loongson2f_cpu_freq_notifier(struct notifier_block *nb, ++ unsigned long val, void *data); ++ ++static struct notifier_block loongson2f_cpufreq_notifier_block = { ++ .notifier_call = loongson2f_cpu_freq_notifier ++}; ++ ++static int loongson2f_cpu_freq_notifier(struct notifier_block *nb, ++ unsigned long val, void *data) ++{ ++ if (val == CPUFREQ_POSTCHANGE) ++ current_cpu_data.udelay_val = loops_per_jiffy; ++ ++ return 0; ++} ++ ++static unsigned int loongson2f_cpufreq_get(unsigned int cpu) ++{ ++ return clk_get_rate(cpuclk); ++} ++ ++/* ++ * Here we notify other drivers of the proposed change and the final change. ++ */ ++static int loongson2f_cpufreq_target(struct cpufreq_policy *policy, ++ unsigned int target_freq, ++ unsigned int relation) ++{ ++ unsigned int cpu = policy->cpu; ++ unsigned int newstate = 0; ++ cpumask_t cpus_allowed; ++ struct cpufreq_freqs freqs; ++ long freq; ++ ++ if (!cpu_online(cpu)) ++ return -ENODEV; ++ ++ cpus_allowed = current->cpus_allowed; ++ set_cpus_allowed(current, cpumask_of_cpu(cpu)); ++ ++#ifdef CONFIG_SMP ++ BUG_ON(smp_processor_id() != cpu); ++#endif ++ ++ if (cpufreq_frequency_table_target ++ (policy, &loongson2f_clockmod_table[0], target_freq, relation, ++ &newstate)) ++ return -EINVAL; ++ ++ freq = ++ cpu_clock_freq / 1000 * loongson2f_clockmod_table[newstate].index / ++ 8; ++ if (freq < policy->min || freq > policy->max) ++ return -EINVAL; ++ ++ pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000); ++ ++ freqs.cpu = cpu; ++ freqs.old = loongson2f_cpufreq_get(cpu); ++ freqs.new = freq; ++ freqs.flags = 0; ++ ++ if (freqs.new == freqs.old) ++ return 0; ++ ++ /* notifiers */ ++ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); ++ ++ set_cpus_allowed(current, cpus_allowed); ++ ++ /* setting the cpu frequency */ ++ clk_set_rate(cpuclk, freq); ++ ++ /* notifiers */ ++ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); ++ ++ pr_debug("cpufreq: set frequency %lu kHz\n", freq); ++ ++ return 0; ++} ++ ++static int loongson2f_cpufreq_cpu_init(struct cpufreq_policy *policy) ++{ ++ int i; ++ int result; ++ ++ if (!cpu_online(policy->cpu)) ++ return -ENODEV; ++ ++ cpuclk = clk_get(NULL, "cpu_clk"); ++ if (IS_ERR(cpuclk)) { ++ printk(KERN_ERR "cpufreq: couldn't get CPU clk\n"); ++ return PTR_ERR(cpuclk); ++ } ++ ++ cpuclk->rate = cpu_clock_freq / 1000; ++ if (!cpuclk->rate) ++ return -EINVAL; ++ ++ /* clock table init */ ++ for (i = 2; ++ (loongson2f_clockmod_table[i].frequency != CPUFREQ_TABLE_END); ++ i++) { ++ loongson2f_clockmod_table[i].frequency = (cpuclk->rate * i) / 8; ++ } ++ ++ policy->cur = loongson2f_cpufreq_get(policy->cpu); ++ ++ cpufreq_frequency_table_get_attr(&loongson2f_clockmod_table[0], ++ policy->cpu); ++ ++ result = ++ cpufreq_frequency_table_cpuinfo(policy, ++ &loongson2f_clockmod_table[0]); ++ if (result) ++ return result; ++ ++ return 0; ++} ++ ++static int loongson2f_cpufreq_verify(struct cpufreq_policy *policy) ++{ ++ return cpufreq_frequency_table_verify(policy, ++ &loongson2f_clockmod_table[0]); ++} ++ ++static int loongson2f_cpufreq_exit(struct cpufreq_policy *policy) ++{ ++ clk_put(cpuclk); ++ return 0; ++} ++ ++static struct freq_attr *loongson2f_table_attr[] = { ++ &cpufreq_freq_attr_scaling_available_freqs, ++ NULL, ++}; ++ ++static struct cpufreq_driver loongson2f_cpufreq_driver = { ++ .owner = THIS_MODULE, ++ .name = "loongson2f", ++ .init = loongson2f_cpufreq_cpu_init, ++ .verify = loongson2f_cpufreq_verify, ++ .target = loongson2f_cpufreq_target, ++ .get = loongson2f_cpufreq_get, ++ .exit = loongson2f_cpufreq_exit, ++ .attr = loongson2f_table_attr, ++}; ++ ++static int __init loongson2f_cpufreq_module_init(void) ++{ ++ int result; ++ ++ printk(KERN_INFO "cpufreq: Loongson-2F CPU frequency driver.\n"); ++ result = cpufreq_register_driver(&loongson2f_cpufreq_driver); ++ ++ if (!result && !nowait) { ++ saved_cpu_wait = cpu_wait; ++ cpu_wait = loongson2f_cpu_wait; ++ } ++ ++ cpufreq_register_notifier(&loongson2f_cpufreq_notifier_block, ++ CPUFREQ_TRANSITION_NOTIFIER); ++ return result; ++} ++ ++static void __exit loongson2f_cpufreq_module_exit(void) ++{ ++ if (!nowait && saved_cpu_wait) ++ cpu_wait = saved_cpu_wait; ++ cpufreq_unregister_driver(&loongson2f_cpufreq_driver); ++ cpufreq_unregister_notifier(&loongson2f_cpufreq_notifier_block, ++ CPUFREQ_TRANSITION_NOTIFIER); ++} ++ ++module_init(loongson2f_cpufreq_module_init); ++module_exit(loongson2f_cpufreq_module_exit); ++ ++module_param(nowait, uint, 0644); ++MODULE_PARM_DESC(nowait, "Disable Loongson-2F specific wait"); ++ ++MODULE_AUTHOR("Yanhua <yanh@lemote.com>"); ++MODULE_DESCRIPTION("cpufreq driver for Loongson2F"); ++MODULE_LICENSE("GPL"); +diff -Nur linux-2.6.30/arch/mips/kernel/smtc.c rt4ls/arch/mips/kernel/smtc.c +--- linux-2.6.30/arch/mips/kernel/smtc.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/kernel/smtc.c 2009-06-12 16:27:08.746436158 +0200 +@@ -924,6 +924,7 @@ + int irq = MIPS_CPU_IRQ_BASE + 1; + + smtc_ipi_nq(&freeIPIq, pipi); ++ + switch (type_copy) { + case SMTC_CLOCK_TICK: + irq_enter(); +diff -Nur linux-2.6.30/arch/mips/lemote/lm2e/Makefile rt4ls/arch/mips/lemote/lm2e/Makefile +--- linux-2.6.30/arch/mips/lemote/lm2e/Makefile 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/lemote/lm2e/Makefile 1970-01-01 01:00:00.000000000 +0100 +@@ -1,7 +0,0 @@ +-# +-# Makefile for Lemote Fulong mini-PC board. +-# +- +-obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o +- +-EXTRA_CFLAGS += -Werror +diff -Nur linux-2.6.30/arch/mips/lemote/lm2e/bonito-irq.c rt4ls/arch/mips/lemote/lm2e/bonito-irq.c +--- linux-2.6.30/arch/mips/lemote/lm2e/bonito-irq.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/lemote/lm2e/bonito-irq.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,74 +0,0 @@ +-/* +- * Copyright 2001 MontaVista Software Inc. +- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net +- * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) +- * +- * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology +- * Author: Fuxin Zhang, zhangfx@lemote.com +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License as published by the +- * Free Software Foundation; either version 2 of the License, or (at your +- * option) any later version. +- * +- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED +- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF +- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- * +- * You should have received a copy of the GNU General Public License along +- * with this program; if not, write to the Free Software Foundation, Inc., +- * 675 Mass Ave, Cambridge, MA 02139, USA. +- * +- */ +-#include <linux/errno.h> +-#include <linux/init.h> +-#include <linux/io.h> +-#include <linux/types.h> +-#include <linux/interrupt.h> +-#include <linux/irq.h> +- +-#include <asm/mips-boards/bonito64.h> +- +- +-static inline void bonito_irq_enable(unsigned int irq) +-{ +- BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); +- mmiowb(); +-} +- +-static inline void bonito_irq_disable(unsigned int irq) +-{ +- BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); +- mmiowb(); +-} +- +-static struct irq_chip bonito_irq_type = { +- .name = "bonito_irq", +- .ack = bonito_irq_disable, +- .mask = bonito_irq_disable, +- .mask_ack = bonito_irq_disable, +- .unmask = bonito_irq_enable, +-}; +- +-static struct irqaction dma_timeout_irqaction = { +- .handler = no_action, +- .name = "dma_timeout", +-}; +- +-void bonito_irq_init(void) +-{ +- u32 i; +- +- for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) { +- set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); +- } +- +- setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); +-} +diff -Nur linux-2.6.30/arch/mips/lemote/lm2e/dbg_io.c rt4ls/arch/mips/lemote/lm2e/dbg_io.c +--- linux-2.6.30/arch/mips/lemote/lm2e/dbg_io.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/lemote/lm2e/dbg_io.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,146 +0,0 @@ +-/* +- * Copyright 2001 MontaVista Software Inc. +- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net +- * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) +- * +- * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology +- * Author: Fuxin Zhang, zhangfx@lemote.com +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License as published by the +- * Free Software Foundation; either version 2 of the License, or (at your +- * option) any later version. +- * +- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED +- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF +- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- * +- * You should have received a copy of the GNU General Public License along +- * with this program; if not, write to the Free Software Foundation, Inc., +- * 675 Mass Ave, Cambridge, MA 02139, USA. +- * +- */ +- +-#include <linux/io.h> +-#include <linux/init.h> +-#include <linux/types.h> +- +-#include <asm/serial.h> +- +-#define UART16550_BAUD_2400 2400 +-#define UART16550_BAUD_4800 4800 +-#define UART16550_BAUD_9600 9600 +-#define UART16550_BAUD_19200 19200 +-#define UART16550_BAUD_38400 38400 +-#define UART16550_BAUD_57600 57600 +-#define UART16550_BAUD_115200 115200 +- +-#define UART16550_PARITY_NONE 0 +-#define UART16550_PARITY_ODD 0x08 +-#define UART16550_PARITY_EVEN 0x18 +-#define UART16550_PARITY_MARK 0x28 +-#define UART16550_PARITY_SPACE 0x38 +- +-#define UART16550_DATA_5BIT 0x0 +-#define UART16550_DATA_6BIT 0x1 +-#define UART16550_DATA_7BIT 0x2 +-#define UART16550_DATA_8BIT 0x3 +- +-#define UART16550_STOP_1BIT 0x0 +-#define UART16550_STOP_2BIT 0x4 +- +-/* ----------------------------------------------------- */ +- +-/* === CONFIG === */ +-#ifdef CONFIG_64BIT +-#define BASE (0xffffffffbfd003f8) +-#else +-#define BASE (0xbfd003f8) +-#endif +- +-#define MAX_BAUD BASE_BAUD +-/* === END OF CONFIG === */ +- +-#define REG_OFFSET 1 +- +-/* register offset */ +-#define OFS_RCV_BUFFER 0 +-#define OFS_TRANS_HOLD 0 +-#define OFS_SEND_BUFFER 0 +-#define OFS_INTR_ENABLE (1*REG_OFFSET) +-#define OFS_INTR_ID (2*REG_OFFSET) +-#define OFS_DATA_FORMAT (3*REG_OFFSET) +-#define OFS_LINE_CONTROL (3*REG_OFFSET) +-#define OFS_MODEM_CONTROL (4*REG_OFFSET) +-#define OFS_RS232_OUTPUT (4*REG_OFFSET) +-#define OFS_LINE_STATUS (5*REG_OFFSET) +-#define OFS_MODEM_STATUS (6*REG_OFFSET) +-#define OFS_RS232_INPUT (6*REG_OFFSET) +-#define OFS_SCRATCH_PAD (7*REG_OFFSET) +- +-#define OFS_DIVISOR_LSB (0*REG_OFFSET) +-#define OFS_DIVISOR_MSB (1*REG_OFFSET) +- +-/* memory-mapped read/write of the port */ +-#define UART16550_READ(y) readb((char *)BASE + (y)) +-#define UART16550_WRITE(y, z) writeb(z, (char *)BASE + (y)) +- +-void debugInit(u32 baud, u8 data, u8 parity, u8 stop) +-{ +- u32 divisor; +- +- /* disable interrupts */ +- UART16550_WRITE(OFS_INTR_ENABLE, 0); +- +- /* set up buad rate */ +- /* set DIAB bit */ +- UART16550_WRITE(OFS_LINE_CONTROL, 0x80); +- +- /* set divisor */ +- divisor = MAX_BAUD / baud; +- UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); +- UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); +- +- /* clear DIAB bit */ +- UART16550_WRITE(OFS_LINE_CONTROL, 0x0); +- +- /* set data format */ +- UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); +-} +- +-static int remoteDebugInitialized; +- +-u8 getDebugChar(void) +-{ +- if (!remoteDebugInitialized) { +- remoteDebugInitialized = 1; +- debugInit(UART16550_BAUD_115200, +- UART16550_DATA_8BIT, +- UART16550_PARITY_NONE, UART16550_STOP_1BIT); +- } +- +- while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0) ; +- return UART16550_READ(OFS_RCV_BUFFER); +-} +- +-int putDebugChar(u8 byte) +-{ +- if (!remoteDebugInitialized) { +- remoteDebugInitialized = 1; +- /* +- debugInit(UART16550_BAUD_115200, +- UART16550_DATA_8BIT, +- UART16550_PARITY_NONE, UART16550_STOP_1BIT); */ +- } +- +- while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0) ; +- UART16550_WRITE(OFS_SEND_BUFFER, byte); +- return 1; +-} +diff -Nur linux-2.6.30/arch/mips/lemote/lm2e/irq.c rt4ls/arch/mips/lemote/lm2e/irq.c +--- linux-2.6.30/arch/mips/lemote/lm2e/irq.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/lemote/lm2e/irq.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,143 +0,0 @@ +-/* +- * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology +- * Author: Fuxin Zhang, zhangfx@lemote.com +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License as published by the +- * Free Software Foundation; either version 2 of the License, or (at your +- * option) any later version. +- * +- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED +- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF +- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- * +- * You should have received a copy of the GNU General Public License along +- * with this program; if not, write to the Free Software Foundation, Inc., +- * 675 Mass Ave, Cambridge, MA 02139, USA. +- * +- */ +-#include <linux/delay.h> +-#include <linux/io.h> +-#include <linux/init.h> +-#include <linux/interrupt.h> +-#include <linux/irq.h> +- +-#include <asm/irq_cpu.h> +-#include <asm/i8259.h> +-#include <asm/mipsregs.h> +-#include <asm/mips-boards/bonito64.h> +- +- +-/* +- * the first level int-handler will jump here if it is a bonito irq +- */ +-static void bonito_irqdispatch(void) +-{ +- u32 int_status; +- int i; +- +- /* workaround the IO dma problem: let cpu looping to allow DMA finish */ +- int_status = BONITO_INTISR; +- if (int_status & (1 << 10)) { +- while (int_status & (1 << 10)) { +- udelay(1); +- int_status = BONITO_INTISR; +- } +- } +- +- /* Get pending sources, masked by current enables */ +- int_status = BONITO_INTISR & BONITO_INTEN; +- +- if (int_status != 0) { +- i = __ffs(int_status); +- int_status &= ~(1 << i); +- do_IRQ(BONITO_IRQ_BASE + i); +- } +-} +- +-static void i8259_irqdispatch(void) +-{ +- int irq; +- +- irq = i8259_irq(); +- if (irq >= 0) { +- do_IRQ(irq); +- } else { +- spurious_interrupt(); +- } +- +-} +- +-asmlinkage void plat_irq_dispatch(void) +-{ +- unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; +- +- if (pending & CAUSEF_IP7) { +- do_IRQ(MIPS_CPU_IRQ_BASE + 7); +- } else if (pending & CAUSEF_IP5) { +- i8259_irqdispatch(); +- } else if (pending & CAUSEF_IP2) { +- bonito_irqdispatch(); +- } else { +- spurious_interrupt(); +- } +-} +- +-static struct irqaction cascade_irqaction = { +- .handler = no_action, +- .name = "cascade", +-}; +- +-void __init arch_init_irq(void) +-{ +- extern void bonito_irq_init(void); +- +- /* +- * Clear all of the interrupts while we change the able around a bit. +- * int-handler is not on bootstrap +- */ +- clear_c0_status(ST0_IM | ST0_BEV); +- local_irq_disable(); +- +- /* most bonito irq should be level triggered */ +- BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR | +- BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; +- BONITO_INTSTEER = 0; +- +- /* +- * Mask out all interrupt by writing "1" to all bit position in +- * the interrupt reset reg. +- */ +- BONITO_INTENCLR = ~0; +- +- /* init all controller +- * 0-15 ------> i8259 interrupt +- * 16-23 ------> mips cpu interrupt +- * 32-63 ------> bonito irq +- */ +- +- /* Sets the first-level interrupt dispatcher. */ +- mips_cpu_irq_init(); +- init_i8259_irqs(); +- bonito_irq_init(); +- +- /* +- printk("GPIODATA=%x, GPIOIE=%x\n", BONITO_GPIODATA, BONITO_GPIOIE); +- printk("INTEN=%x, INTSET=%x, INTCLR=%x, INTISR=%x\n", +- BONITO_INTEN, BONITO_INTENSET, +- BONITO_INTENCLR, BONITO_INTISR); +- */ +- +- /* bonito irq at IP2 */ +- setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); +- /* 8259 irq at IP5 */ +- setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); +- +-} +diff -Nur linux-2.6.30/arch/mips/lemote/lm2e/mem.c rt4ls/arch/mips/lemote/lm2e/mem.c +--- linux-2.6.30/arch/mips/lemote/lm2e/mem.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/lemote/lm2e/mem.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,23 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License as published by the +- * Free Software Foundation; either version 2 of the License, or (at your +- * option) any later version. +- */ +-#include <linux/fs.h> +-#include <linux/fcntl.h> +-#include <linux/mm.h> +- +-/* override of arch/mips/mm/cache.c: __uncached_access */ +-int __uncached_access(struct file *file, unsigned long addr) +-{ +- if (file->f_flags & O_SYNC) +- return 1; +- +- /* +- * On the Lemote Loongson 2e system, the peripheral registers +- * reside between 0x1000:0000 and 0x2000:0000. +- */ +- return addr >= __pa(high_memory) || +- ((addr >= 0x10000000) && (addr < 0x20000000)); +-} +diff -Nur linux-2.6.30/arch/mips/lemote/lm2e/pci.c rt4ls/arch/mips/lemote/lm2e/pci.c +--- linux-2.6.30/arch/mips/lemote/lm2e/pci.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/lemote/lm2e/pci.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,97 +0,0 @@ +-/* +- * pci.c +- * +- * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology +- * Author: Fuxin Zhang, zhangfx@lemote.com +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License as published by the +- * Free Software Foundation; either version 2 of the License, or (at your +- * option) any later version. +- * +- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED +- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF +- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- * +- * You should have received a copy of the GNU General Public License along +- * with this program; if not, write to the Free Software Foundation, Inc., +- * 675 Mass Ave, Cambridge, MA 02139, USA. +- * +- */ +-#include <linux/types.h> +-#include <linux/pci.h> +-#include <linux/kernel.h> +-#include <linux/init.h> +-#include <asm/mips-boards/bonito64.h> +-#include <asm/mach-lemote/pci.h> +- +-extern struct pci_ops bonito64_pci_ops; +- +-static struct resource loongson2e_pci_mem_resource = { +- .name = "LOONGSON2E PCI MEM", +- .start = LOONGSON2E_PCI_MEM_START, +- .end = LOONGSON2E_PCI_MEM_END, +- .flags = IORESOURCE_MEM, +-}; +- +-static struct resource loongson2e_pci_io_resource = { +- .name = "LOONGSON2E PCI IO MEM", +- .start = LOONGSON2E_PCI_IO_START, +- .end = IO_SPACE_LIMIT, +- .flags = IORESOURCE_IO, +-}; +- +-static struct pci_controller loongson2e_pci_controller = { +- .pci_ops = &bonito64_pci_ops, +- .io_resource = &loongson2e_pci_io_resource, +- .mem_resource = &loongson2e_pci_mem_resource, +- .mem_offset = 0x00000000UL, +- .io_offset = 0x00000000UL, +-}; +- +-static void __init ict_pcimap(void) +-{ +- /* +- * local to PCI mapping: [256M,512M] -> [256M,512M]; differ from PMON +- * +- * CPU address space [256M,448M] is window for accessing pci space +- * we set pcimap_lo[0,1,2] to map it to pci space [256M,448M] +- * pcimap: bit18,pcimap_2; bit[17-12],lo2;bit[11-6],lo1;bit[5-0],lo0 +- */ +- /* 1,00 0110 ,0001 01,00 0000 */ +- BONITO_PCIMAP = 0x46140; +- +- /* 1, 00 0010, 0000,01, 00 0000 */ +- /* BONITO_PCIMAP = 0x42040; */ +- +- /* +- * PCI to local mapping: [2G,2G+256M] -> [0,256M] +- */ +- BONITO_PCIBASE0 = 0x80000000; +- BONITO_PCIBASE1 = 0x00800000; +- BONITO_PCIBASE2 = 0x90000000; +- +-} +- +-static int __init pcibios_init(void) +-{ +- ict_pcimap(); +- +- loongson2e_pci_controller.io_map_base = +- (unsigned long) ioremap(LOONGSON2E_IO_PORT_BASE, +- loongson2e_pci_io_resource.end - +- loongson2e_pci_io_resource.start + 1); +- +- register_pci_controller(&loongson2e_pci_controller); +- +- return 0; +-} +- +-arch_initcall(pcibios_init); +diff -Nur linux-2.6.30/arch/mips/lemote/lm2e/prom.c rt4ls/arch/mips/lemote/lm2e/prom.c +--- linux-2.6.30/arch/mips/lemote/lm2e/prom.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/lemote/lm2e/prom.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,97 +0,0 @@ +-/* +- * Based on Ocelot Linux port, which is +- * Copyright 2001 MontaVista Software Inc. +- * Author: jsun@mvista.com or jsun@junsun.net +- * +- * Copyright 2003 ICT CAS +- * Author: Michael Guo <guoyi@ict.ac.cn> +- * +- * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology +- * Author: Fuxin Zhang, zhangfx@lemote.com +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License as published by the +- * Free Software Foundation; either version 2 of the License, or (at your +- * option) any later version. +- */ +-#include <linux/init.h> +-#include <linux/bootmem.h> +-#include <asm/bootinfo.h> +- +-extern unsigned long bus_clock; +-extern unsigned long cpu_clock_freq; +-extern unsigned int memsize, highmemsize; +-extern int putDebugChar(unsigned char byte); +- +-static int argc; +-/* pmon passes arguments in 32bit pointers */ +-static int *arg; +-static int *env; +- +-const char *get_system_type(void) +-{ +- return "lemote-fulong"; +-} +- +-void __init prom_init_cmdline(void) +-{ +- int i; +- long l; +- +- /* arg[0] is "g", the rest is boot parameters */ +- arcs_cmdline[0] = '\0'; +- for (i = 1; i < argc; i++) { +- l = (long)arg[i]; +- if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) +- >= sizeof(arcs_cmdline)) +- break; +- strcat(arcs_cmdline, ((char *)l)); +- strcat(arcs_cmdline, " "); +- } +-} +- +-void __init prom_init(void) +-{ +- long l; +- argc = fw_arg0; +- arg = (int *)fw_arg1; +- env = (int *)fw_arg2; +- +- prom_init_cmdline(); +- +- if ((strstr(arcs_cmdline, "console=")) == NULL) +- strcat(arcs_cmdline, " console=ttyS0,115200"); +- if ((strstr(arcs_cmdline, "root=")) == NULL) +- strcat(arcs_cmdline, " root=/dev/hda1"); +- +-#define parse_even_earlier(res, option, p) \ +-do { \ +- if (strncmp(option, (char *)p, strlen(option)) == 0) \ +- res = simple_strtol((char *)p + strlen(option"="), \ +- NULL, 10); \ +-} while (0) +- +- l = (long)*env; +- while (l != 0) { +- parse_even_earlier(bus_clock, "busclock", l); +- parse_even_earlier(cpu_clock_freq, "cpuclock", l); +- parse_even_earlier(memsize, "memsize", l); +- parse_even_earlier(highmemsize, "highmemsize", l); +- env++; +- l = (long)*env; +- } +- if (memsize == 0) +- memsize = 256; +- +- pr_info("busclock=%ld, cpuclock=%ld,memsize=%d,highmemsize=%d\n", +- bus_clock, cpu_clock_freq, memsize, highmemsize); +-} +- +-void __init prom_free_prom_memory(void) +-{ +-} +- +-void prom_putchar(char c) +-{ +- putDebugChar(c); +-} +diff -Nur linux-2.6.30/arch/mips/lemote/lm2e/reset.c rt4ls/arch/mips/lemote/lm2e/reset.c +--- linux-2.6.30/arch/mips/lemote/lm2e/reset.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/lemote/lm2e/reset.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,41 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License as published by the +- * Free Software Foundation; either version 2 of the License, or (at your +- * option) any later version. +- * +- * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology +- * Author: Fuxin Zhang, zhangfx@lemote.com +- */ +-#include <linux/pm.h> +- +-#include <asm/reboot.h> +- +-static void loongson2e_restart(char *command) +-{ +-#ifdef CONFIG_32BIT +- *(unsigned long *)0xbfe00104 &= ~(1 << 2); +- *(unsigned long *)0xbfe00104 |= (1 << 2); +-#else +- *(unsigned long *)0xffffffffbfe00104 &= ~(1 << 2); +- *(unsigned long *)0xffffffffbfe00104 |= (1 << 2); +-#endif +- __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); +-} +- +-static void loongson2e_halt(void) +-{ +- while (1) ; +-} +- +-static void loongson2e_power_off(void) +-{ +- loongson2e_halt(); +-} +- +-void mips_reboot_setup(void) +-{ +- _machine_restart = loongson2e_restart; +- _machine_halt = loongson2e_halt; +- pm_power_off = loongson2e_power_off; +-} +diff -Nur linux-2.6.30/arch/mips/lemote/lm2e/setup.c rt4ls/arch/mips/lemote/lm2e/setup.c +--- linux-2.6.30/arch/mips/lemote/lm2e/setup.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/lemote/lm2e/setup.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,111 +0,0 @@ +-/* +- * BRIEF MODULE DESCRIPTION +- * setup.c - board dependent boot routines +- * +- * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology +- * Author: Fuxin Zhang, zhangfx@lemote.com +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License as published by the +- * Free Software Foundation; either version 2 of the License, or (at your +- * option) any later version. +- * +- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED +- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF +- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- * +- * You should have received a copy of the GNU General Public License along +- * with this program; if not, write to the Free Software Foundation, Inc., +- * 675 Mass Ave, Cambridge, MA 02139, USA. +- * +- */ +-#include <linux/bootmem.h> +-#include <linux/init.h> +-#include <linux/irq.h> +- +-#include <asm/bootinfo.h> +-#include <asm/mc146818-time.h> +-#include <asm/time.h> +-#include <asm/wbflush.h> +-#include <asm/mach-lemote/pci.h> +- +-#ifdef CONFIG_VT +-#include <linux/console.h> +-#include <linux/screen_info.h> +-#endif +- +-extern void mips_reboot_setup(void); +- +-unsigned long cpu_clock_freq; +-unsigned long bus_clock; +-unsigned int memsize; +-unsigned int highmemsize = 0; +- +-void __init plat_time_init(void) +-{ +- /* setup mips r4k timer */ +- mips_hpt_frequency = cpu_clock_freq / 2; +-} +- +-unsigned long read_persistent_clock(void) +-{ +- return mc146818_get_cmos_time(); +-} +- +-void (*__wbflush)(void); +-EXPORT_SYMBOL(__wbflush); +- +-static void wbflush_loongson2e(void) +-{ +- asm(".set\tpush\n\t" +- ".set\tnoreorder\n\t" +- ".set mips3\n\t" +- "sync\n\t" +- "nop\n\t" +- ".set\tpop\n\t" +- ".set mips0\n\t"); +-} +- +-void __init plat_mem_setup(void) +-{ +- set_io_port_base((unsigned long)ioremap(LOONGSON2E_IO_PORT_BASE, +- IO_SPACE_LIMIT - LOONGSON2E_PCI_IO_START + 1)); +- mips_reboot_setup(); +- +- __wbflush = wbflush_loongson2e; +- +- add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); +-#ifdef CONFIG_64BIT +- if (highmemsize > 0) { +- add_memory_region(0x20000000, highmemsize << 20, BOOT_MEM_RAM); +- } +-#endif +- +-#ifdef CONFIG_VT +-#if defined(CONFIG_VGA_CONSOLE) +- conswitchp = &vga_con; +- +- screen_info = (struct screen_info) { +- 0, 25, /* orig-x, orig-y */ +- 0, /* unused */ +- 0, /* orig-video-page */ +- 0, /* orig-video-mode */ +- 80, /* orig-video-cols */ +- 0, 0, 0, /* ega_ax, ega_bx, ega_cx */ +- 25, /* orig-video-lines */ +- VIDEO_TYPE_VGAC, /* orig-video-isVGA */ +- 16 /* orig-video-points */ +- }; +-#elif defined(CONFIG_DUMMY_CONSOLE) +- conswitchp = &dummy_con; +-#endif +-#endif +- +-} +diff -Nur linux-2.6.30/arch/mips/lib/delay.c rt4ls/arch/mips/lib/delay.c +--- linux-2.6.30/arch/mips/lib/delay.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/lib/delay.c 2009-06-12 16:27:08.762444064 +0200 +@@ -43,7 +43,7 @@ + { + unsigned int lpj = current_cpu_data.udelay_val; + +- __delay((us * 0x000010c7 * HZ * lpj) >> 32); ++ __delay((us * 0x000010c7ull * HZ * lpj) >> 32); + } + EXPORT_SYMBOL(__udelay); + +@@ -51,6 +51,6 @@ + { + unsigned int lpj = current_cpu_data.udelay_val; + +- __delay((us * 0x00000005 * HZ * lpj) >> 32); ++ __delay((ns * 0x00000005ull * HZ * lpj) >> 32); + } + EXPORT_SYMBOL(__ndelay); +diff -Nur linux-2.6.30/arch/mips/loongson/Kconfig rt4ls/arch/mips/loongson/Kconfig +--- linux-2.6.30/arch/mips/loongson/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/Kconfig 2009-06-12 16:27:08.770446201 +0200 +@@ -0,0 +1,135 @@ ++choice ++ prompt "Machine Type" ++ depends on MACH_LOONGSON ++ ++config LEMOTE_FULOONG2E ++ bool "Lemote Fuloong(2e) mini-PC" ++ select ARCH_SPARSEMEM_ENABLE ++ select CEVT_R4K ++ select CSRC_R4K ++ select SYS_HAS_CPU_LOONGSON2E ++ select DMA_NONCOHERENT ++ select BOOT_ELF32 ++ select BOARD_SCACHE ++ select HW_HAS_PCI ++ select I8259 ++ select ISA ++ select IRQ_CPU ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_64BIT_KERNEL ++ select SYS_SUPPORTS_LITTLE_ENDIAN ++ select SYS_SUPPORTS_HIGHMEM ++ select SYS_HAS_EARLY_PRINTK ++ select GENERIC_HARDIRQS_NO__DO_IRQ ++ select GENERIC_ISA_DMA_SUPPORT_BROKEN ++ select CPU_HAS_WB ++ help ++ Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and ++ an FPGA northbridge ++ ++ Lemote Fuloong(2e) mini PC have a VIA686B south bridge. ++ ++config LEMOTE_FULOONG2F ++ bool "Lemote Fuloong(2f) mini-PC" ++ select ARCH_SPARSEMEM_ENABLE ++ select CEVT_R4K if !CS5536_MFGPT ++ select CSRC_R4K if !CS5536_MFGPT ++ select SYS_HAS_CPU_LOONGSON2F ++ select DMA_NONCOHERENT ++ select BOOT_ELF32 ++ select BOARD_SCACHE ++ select HW_HAS_PCI ++ select I8259 ++ select ISA ++ select IRQ_CPU ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_64BIT_KERNEL ++ select SYS_SUPPORTS_LITTLE_ENDIAN ++ select SYS_SUPPORTS_HIGHMEM ++ select SYS_HAS_EARLY_PRINTK ++ select GENERIC_HARDIRQS_NO__DO_IRQ ++ select GENERIC_ISA_DMA_SUPPORT_BROKEN ++ select CPU_HAS_WB ++ select CS5536 ++ help ++ Lemote Fuloong(2f) mini-PC board based on the Chinese Loongson-2F ++ CPU, which has an internal DDR and PCIX controller. the PCIX ++ controller have the similiar programming interface of the FPGA north ++ bridge of LOONGSON2E. ++ ++ Lemote Fuloong(2f) mini PC have an AMD CS5536 south bridge. ++ ++config LEMOTE_YEELOONG2F ++ bool "Lemote Yeeloong(2f) mini Notebook" ++ select ARCH_SPARSEMEM_ENABLE ++ select CEVT_R4K if !CS5536_MFGPT ++ select CSRC_R4K if !CS5536_MFGPT ++ select SYS_HAS_CPU_LOONGSON2F ++ select DMA_NONCOHERENT ++ select BOOT_ELF32 ++ select BOARD_SCACHE ++ select HW_HAS_PCI ++ select I8259 ++ select ISA ++ select IRQ_CPU ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_64BIT_KERNEL ++ select SYS_SUPPORTS_LITTLE_ENDIAN ++ select SYS_SUPPORTS_HIGHMEM ++ select SYS_HAS_EARLY_PRINTK ++ select SYS_HAS_MACH_PROM_INIT_CMDLINE ++ select GENERIC_HARDIRQS_NO__DO_IRQ ++ select GENERIC_ISA_DMA_SUPPORT_BROKEN ++ select CPU_HAS_WB ++ select CS5536 ++ help ++ Lemote Laptop based on the Chinese Loongson-2F CPU, which has an ++ internal DDR and PCIX controller. the PCIX controller have the ++ similiar programming interface of the FPGA north bridge of ++ LOONGSON2E. ++ ++ Lemote Yeeloong(2f) laptop have an AMD CS5536 south bridge and an EC ++ controller. ++ ++endchoice ++ ++config CS5536 ++ bool ++ ++config CS5536_FLASH ++ bool ++ depends on CS5536 ++ ++config CS5536_NOR_FLASH ++ bool ++ depends on CS5536_FLASH ++ ++config CS5536_OTG ++ bool ++ depends on CS5536 ++ ++config CS5536_UDC ++ bool ++ depends on CS5536 ++ ++config SYS_HAS_MACH_PROM_INIT_CMDLINE ++ bool ++ ++config CS5536_MFGPT ++ bool "Using cs5536's MFGPT as system clock" ++ depends on CS5536 ++ help ++ This is needed if cpufreq and oprofile is enabled in Loongson2(F) ++ machines ++ ++config UCA_SIZE ++ hex "Uncache Accelerated Region size" ++ depends on CPU_LOONGSON2F ++ default 0x400000 if LEMOTE_YEELOONG2F ++ default 0x2000000 if LEMOTE_FULOONG2F ++ help ++ Uncached Acceleration(UCA) can greatly improve video performance. ++ Normally the Video memory can be accessed in Uncached Accelerated mode, ++ other peripheral spaces not. ++ ++ Specify a zeroed size to disable this feature. +diff -Nur linux-2.6.30/arch/mips/loongson/Makefile rt4ls/arch/mips/loongson/Makefile +--- linux-2.6.30/arch/mips/loongson/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/Makefile 2009-06-12 16:27:08.770446201 +0200 +@@ -0,0 +1,23 @@ ++# ++# Common code for all Loongson based systems ++# ++ ++obj-$(CONFIG_MACH_LOONGSON) += common/ ++ ++# ++# Lemote Fuloong mini-PC (Loongson 2E-based) ++# ++ ++obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/ ++ ++# ++# Lemote Fuloong mini-PC (Loongson 2F-based) ++# ++ ++obj-$(CONFIG_LEMOTE_FULOONG2F) += fuloong-2f/ ++ ++# ++# Lemote Yeeloong mini-PC (Loongson 2F-based) ++# ++ ++obj-$(CONFIG_LEMOTE_YEELOONG2F) += yeeloong-2f/ +diff -Nur linux-2.6.30/arch/mips/loongson/common/Makefile rt4ls/arch/mips/loongson/common/Makefile +--- linux-2.6.30/arch/mips/loongson/common/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/Makefile 2009-06-12 16:27:08.774444476 +0200 +@@ -0,0 +1,37 @@ ++# ++# Makefile for loongson based machines. ++# ++ ++obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ ++ pci.o bonito-irq.o mem.o machtype.o ++ ++# ++# Early printk support ++# ++obj-$(CONFIG_EARLY_PRINTK) += early_printk.o ++ ++# ++# Enable RTC Class support ++# ++# please enable CONFIG_RTC_DRV_CMOS ++# ++obj-$(CONFIG_RTC_DRV_CMOS) += rtc.o ++ ++# ++# Enable CS5536 Virtual Support Module(VSM) for virtulize the PCI configure ++# space ++# ++obj-$(CONFIG_CS5536) += cs5536/ ++ ++# ++# Enable fuloong(2f) and yeeloong(2f) cpu frequency scaling support ++# This is based on CS5536 mfgpt timer ++# ++obj-$(CONFIG_LOONGSON2F_CPU_FREQ) += clock.o ++ ++# ++# Enable serial port ++# ++obj-$(CONFIG_SERIAL_8250) += serial.o ++ ++EXTRA_CFLAGS += -Werror +diff -Nur linux-2.6.30/arch/mips/loongson/common/bonito-irq.c rt4ls/arch/mips/loongson/common/bonito-irq.c +--- linux-2.6.30/arch/mips/loongson/common/bonito-irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/bonito-irq.c 2009-06-12 16:27:08.774444476 +0200 +@@ -0,0 +1,78 @@ ++/* ++ * Copyright 2001 MontaVista Software Inc. ++ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net ++ * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) ++ * ++ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ */ ++ ++#include <linux/interrupt.h> ++ ++#include <loongson.h> ++#include <machine.h> ++ ++static inline void bonito_irq_enable(unsigned int irq) ++{ ++ LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE)); ++ /* flush posted write */ ++ (void)LOONGSON_INTENSET; ++ mmiowb(); ++} ++ ++static inline void bonito_irq_disable(unsigned int irq) ++{ ++ LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE)); ++ /* flush posted write */ ++ (void)LOONGSON_INTENCLR; ++ mmiowb(); ++} ++ ++static struct irq_chip bonito_irq_type = { ++ .name = "bonito_irq", ++ .ack = bonito_irq_disable, ++ .mask = bonito_irq_disable, ++ .mask_ack = bonito_irq_disable, ++ .unmask = bonito_irq_enable, ++}; ++ ++/* there is no need to handle dma timeout in loongson-2f based machines */ ++#ifdef CONFIG_CPU_LOONGSON2E ++static struct irqaction dma_timeout_irqaction = { ++ .handler = no_action, ++ .name = "dma_timeout", ++}; ++#endif ++ ++void bonito_irq_init(void) ++{ ++ u32 i; ++ ++ for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) ++ set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); ++ ++#ifdef CONFIG_CPU_LOONGSON2E ++ setup_irq(LOONGSON_DMATIMEOUT_IRQ, &dma_timeout_irqaction); ++#endif ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/clock.c rt4ls/arch/mips/loongson/common/clock.c +--- linux-2.6.30/arch/mips/loongson/common/clock.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/clock.c 2009-06-12 16:27:08.774444476 +0200 +@@ -0,0 +1,166 @@ ++/* ++ * arch/mips/loongson/common/clock.c ++ * ++ * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology ++ * Author: Yanhua, yanh@lemote.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ */ ++ ++#include <linux/cpufreq.h> ++#include <linux/platform_device.h> ++ ++#include <loongson.h> ++#include <clock.h> ++ ++static LIST_HEAD(clock_list); ++static DEFINE_SPINLOCK(clock_lock); ++static DEFINE_MUTEX(clock_list_sem); ++ ++/* Minimum CLK support */ ++enum { ++ DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT, ++ DC_87PT, DC_DISABLE, DC_RESV ++}; ++ ++struct cpufreq_frequency_table loongson2f_clockmod_table[] = { ++ {DC_RESV, CPUFREQ_ENTRY_INVALID}, ++ {DC_ZERO, CPUFREQ_ENTRY_INVALID}, ++ {DC_25PT, 0}, ++ {DC_37PT, 0}, ++ {DC_50PT, 0}, ++ {DC_62PT, 0}, ++ {DC_75PT, 0}, ++ {DC_87PT, 0}, ++ {DC_DISABLE, 0}, ++ {DC_RESV, CPUFREQ_TABLE_END}, ++}; ++EXPORT_SYMBOL_GPL(loongson2f_clockmod_table); ++ ++static struct clk cpu_clk = { ++ .name = "cpu_clk", ++ .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES, ++ .rate = 800000000, ++}; ++ ++struct clk *clk_get(struct device *dev, const char *id) ++{ ++ return &cpu_clk; ++} ++EXPORT_SYMBOL(clk_get); ++ ++static void propagate_rate(struct clk *clk) ++{ ++ struct clk *clkp; ++ ++ list_for_each_entry(clkp, &clock_list, node) { ++ if (likely(clkp->parent != clk)) ++ continue; ++ if (likely(clkp->ops && clkp->ops->recalc)) ++ clkp->ops->recalc(clkp); ++ if (unlikely(clkp->flags & CLK_RATE_PROPAGATES)) ++ propagate_rate(clkp); ++ } ++} ++ ++int clk_enable(struct clk *clk) ++{ ++ return 0; ++} ++EXPORT_SYMBOL(clk_enable); ++ ++void clk_disable(struct clk *clk) ++{ ++} ++EXPORT_SYMBOL(clk_disable); ++ ++unsigned long clk_get_rate(struct clk *clk) ++{ ++ return (unsigned long)clk->rate; ++} ++EXPORT_SYMBOL(clk_get_rate); ++ ++void clk_put(struct clk *clk) ++{ ++} ++EXPORT_SYMBOL(clk_put); ++ ++int clk_set_rate(struct clk *clk, unsigned long rate) ++{ ++ return clk_set_rate_ex(clk, rate, 0); ++} ++EXPORT_SYMBOL_GPL(clk_set_rate); ++ ++int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id) ++{ ++ int ret = 0; ++ int regval; ++ int i; ++ ++ if (likely(clk->ops && clk->ops->set_rate)) { ++ unsigned long flags; ++ ++ spin_lock_irqsave(&clock_lock, flags); ++ ret = clk->ops->set_rate(clk, rate, algo_id); ++ spin_unlock_irqrestore(&clock_lock, flags); ++ } ++ ++ if (unlikely(clk->flags & CLK_RATE_PROPAGATES)) ++ propagate_rate(clk); ++ ++ for (i = 0; loongson2f_clockmod_table[i].frequency != CPUFREQ_TABLE_END; ++ i++) { ++ if (loongson2f_clockmod_table[i].frequency == ++ CPUFREQ_ENTRY_INVALID) ++ continue; ++ if (rate == loongson2f_clockmod_table[i].frequency) ++ break; ++ } ++ if (rate != loongson2f_clockmod_table[i].frequency) ++ return -ENOTSUPP; ++ ++ clk->rate = rate; ++ ++ regval = LOONGSON_CHIPCFG0; ++ regval = (regval & ~0x7) | (loongson2f_clockmod_table[i].index - 1); ++ LOONGSON_CHIPCFG0 = regval; ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(clk_set_rate_ex); ++ ++long clk_round_rate(struct clk *clk, unsigned long rate) ++{ ++ if (likely(clk->ops && clk->ops->round_rate)) { ++ unsigned long flags, rounded; ++ ++ spin_lock_irqsave(&clock_lock, flags); ++ rounded = clk->ops->round_rate(clk, rate); ++ spin_unlock_irqrestore(&clock_lock, flags); ++ ++ return rounded; ++ } ++ ++ return rate; ++} ++EXPORT_SYMBOL_GPL(clk_round_rate); ++ ++/* ++ * This is the simple version of Loongson-2F wait ++ * Maybe we need do this in interrupt disabled content ++ */ ++DEFINE_SPINLOCK(loongson2f_wait_lock); ++void loongson2f_cpu_wait(void) ++{ ++ u32 cpu_freq; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&loongson2f_wait_lock, flags); ++ cpu_freq = LOONGSON_CHIPCFG0; ++ LOONGSON_CHIPCFG0 &= ~0x7; /* Put CPU into wait mode */ ++ LOONGSON_CHIPCFG0 = cpu_freq; /* Restore CPU state */ ++ spin_unlock_irqrestore(&loongson2f_wait_lock, flags); ++} ++EXPORT_SYMBOL_GPL(loongson2f_cpu_wait); +diff -Nur linux-2.6.30/arch/mips/loongson/common/cmdline.c rt4ls/arch/mips/loongson/common/cmdline.c +--- linux-2.6.30/arch/mips/loongson/common/cmdline.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/cmdline.c 2009-06-12 16:27:08.774444476 +0200 +@@ -0,0 +1,57 @@ ++/* ++ * Based on Ocelot Linux port, which is ++ * Copyright 2001 MontaVista Software Inc. ++ * Author: jsun@mvista.com or jsun@junsun.net ++ * ++ * Copyright 2003 ICT CAS ++ * Author: Michael Guo <guoyi@ict.ac.cn> ++ * ++ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <asm/bootinfo.h> ++ ++#include <loongson.h> ++#include <cmdline.h> ++ ++int prom_argc; ++/* pmon passes arguments in 32bit pointers */ ++int *_prom_argv; ++ ++void __init prom_init_cmdline(void) ++{ ++ int i; ++ long l; ++ ++ /* firmware arguments are initialized in head.S */ ++ prom_argc = fw_arg0; ++ _prom_argv = (int *)fw_arg1; ++ ++ /* arg[0] is "g", the rest is boot parameters */ ++ arcs_cmdline[0] = '\0'; ++ for (i = 1; i < prom_argc; i++) { ++ l = (long)_prom_argv[i]; ++ if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) ++ >= sizeof(arcs_cmdline)) ++ break; ++ strcat(arcs_cmdline, ((char *)l)); ++ strcat(arcs_cmdline, " "); ++ } ++ ++ /* machine specific prom_init_cmdline */ ++ mach_prom_init_cmdline(); ++ ++ if ((strstr(arcs_cmdline, "console=")) == NULL) ++ strcat(arcs_cmdline, " console=ttyS0,115200"); ++ if ((strstr(arcs_cmdline, "root=")) == NULL) ++ strcat(arcs_cmdline, " root=/dev/hda1"); ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/cs5536/Makefile rt4ls/arch/mips/loongson/common/cs5536/Makefile +--- linux-2.6.30/arch/mips/loongson/common/cs5536/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/cs5536/Makefile 2009-06-12 16:27:08.774444476 +0200 +@@ -0,0 +1,25 @@ ++# ++# Makefile for CS5536 support. ++# ++ ++# ++# core modules ++# ++obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \ ++ cs5536_isa.o cs5536_ehci.o ++# ++# selective modules ++# ++# add a CS5536_[MODULE] to your board in arch/mips/loongson/Kconfig ++# ++obj-$(CONFIG_CS5536_FLASH) += cs5536_flash.o ++obj-$(CONFIG_CS5536_NOR_FLASH) += cs5536_flash.o ++obj-$(CONFIG_CS5536_OTG) += cs5536_otg.o ++obj-$(CONFIG_CS5536_UDC) += cs5536_udc.o ++ ++# ++# Enable cs5536 mfgpt Timer ++# ++obj-$(CONFIG_CS5536_MFGPT) += cs5536_mfgpt.o ++ ++EXTRA_CFLAGS += -Werror +diff -Nur linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_acc.c rt4ls/arch/mips/loongson/common/cs5536/cs5536_acc.c +--- linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_acc.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/cs5536/cs5536_acc.c 2009-06-12 16:27:08.774444476 +0200 +@@ -0,0 +1,156 @@ ++/* ++ * the ACC Virtual Support Module of AMD CS5536 ++ * ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author : jlliu, liujl@lemote.com ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <cs5536/cs5536.h> ++#include <cs5536/cs5536_pci.h> ++ ++/* ++ * acc_write: acc write transfering ++ */ ++ ++void pci_acc_write_reg(int reg, u32 value) ++{ ++ u32 hi = 0, lo = value; ++ ++ switch (reg) { ++ case PCI_COMMAND: ++ _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); ++ if (value & PCI_COMMAND_MASTER) ++ lo |= (0x03 << 8); ++ else ++ lo &= ~(0x03 << 8); ++ _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo); ++ break; ++ case PCI_STATUS: ++ if (value & PCI_STATUS_PARITY) { ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) { ++ lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; ++ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); ++ } ++ } ++ break; ++ case PCI_BAR0_REG: ++ if (value == PCI_BAR_RANGE_MASK) { ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ lo |= SOFT_BAR_ACC_FLAG; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else if (value & 0x01) { ++ value &= 0xfffffffc; ++ hi = 0xA0000000 | ((value & 0x000ff000) >> 12); ++ lo = 0x000fff80 | ((value & 0x00000fff) << 20); ++ _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo); ++ } ++ break; ++ case PCI_ACC_INT_REG: ++ _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); ++ /* disable all the usb interrupt in PIC */ ++ lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT); ++ if (value) /* enable all the acc interrupt in PIC */ ++ lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT); ++ _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); ++ break; ++ default: ++ break; ++ } ++ ++ return; ++} ++ ++/* ++ * acc_read: acc read transfering ++ */ ++ ++u32 pci_acc_read_reg(int reg) ++{ ++ u32 hi, lo; ++ u32 conf_data = 0; ++ ++ switch (reg) { ++ case PCI_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID); ++ break; ++ case PCI_COMMAND: ++ _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); ++ if (((lo & 0xfff00000) || (hi & 0x000000ff)) ++ && ((hi & 0xf0000000) == 0xa0000000)) ++ conf_data |= PCI_COMMAND_IO; ++ _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); ++ if ((lo & 0x300) == 0x300) ++ conf_data |= PCI_COMMAND_MASTER; ++ break; ++ case PCI_STATUS: ++ conf_data |= PCI_STATUS_66MHZ; ++ conf_data |= PCI_STATUS_FAST_BACK; ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) ++ conf_data |= PCI_STATUS_PARITY; ++ conf_data |= PCI_STATUS_DEVSEL_MEDIUM; ++ break; ++ case PCI_CLASS_REVISION: ++ _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo); ++ conf_data = lo & 0x000000ff; ++ conf_data |= (CS5536_ACC_CLASS_CODE << 8); ++ break; ++ case PCI_CACHE_LINE_SIZE: ++ conf_data = ++ CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, ++ PCI_NORMAL_LATENCY_TIMER); ++ break; ++ case PCI_BAR0_REG: ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ if (lo & SOFT_BAR_ACC_FLAG) { ++ conf_data = CS5536_ACC_RANGE | ++ PCI_BASE_ADDRESS_SPACE_IO; ++ lo &= ~SOFT_BAR_ACC_FLAG; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else { ++ _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); ++ conf_data = (hi & 0x000000ff) << 12; ++ conf_data |= (lo & 0xfff00000) >> 20; ++ conf_data |= 0x01; ++ conf_data &= ~0x02; ++ } ++ break; ++ case PCI_BAR1_REG: ++ case PCI_BAR2_REG: ++ case PCI_BAR3_REG: ++ case PCI_BAR4_REG: ++ case PCI_BAR5_REG: ++ break; ++ case PCI_CARDBUS_CIS: ++ conf_data = PCI_CARDBUS_CIS_POINTER; ++ break; ++ case PCI_SUBSYSTEM_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID); ++ break; ++ case PCI_ROM_ADDRESS: ++ conf_data = PCI_EXPANSION_ROM_BAR; ++ break; ++ case PCI_CAPABILITY_LIST: ++ conf_data = PCI_CAPLIST_USB_POINTER; ++ break; ++ case PCI_INTERRUPT_LINE: ++ conf_data = ++ CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR); ++ break; ++ default: ++ break; ++ } ++ ++ return conf_data; ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_ehci.c rt4ls/arch/mips/loongson/common/cs5536/cs5536_ehci.c +--- linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_ehci.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/cs5536/cs5536_ehci.c 2009-06-12 16:27:08.774444476 +0200 +@@ -0,0 +1,166 @@ ++/* ++ * the EHCI Virtual Support Module of AMD CS5536 ++ * ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author : jlliu, liujl@lemote.com ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <cs5536/cs5536.h> ++#include <cs5536/cs5536_pci.h> ++ ++void pci_ehci_write_reg(int reg, u32 value) ++{ ++ u32 hi = 0, lo = value; ++ ++ switch (reg) { ++ case PCI_COMMAND: ++ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); ++ if (value & PCI_COMMAND_MASTER) ++ hi |= PCI_COMMAND_MASTER; ++ else ++ hi &= ~PCI_COMMAND_MASTER; ++ ++ if (value & PCI_COMMAND_MEMORY) ++ hi |= PCI_COMMAND_MEMORY; ++ else ++ hi &= ~PCI_COMMAND_MEMORY; ++ _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); ++ break; ++ case PCI_STATUS: ++ if (value & PCI_STATUS_PARITY) { ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) { ++ lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; ++ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); ++ } ++ } ++ break; ++ case PCI_BAR0_REG: ++ if (value == PCI_BAR_RANGE_MASK) { ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ lo |= SOFT_BAR_EHCI_FLAG; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else if ((value & 0x01) == 0x00) { ++ _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); ++ ++ value &= 0xfffffff0; ++ hi = 0x40000000 | ((value & 0xff000000) >> 24); ++ lo = 0x000fffff | ((value & 0x00fff000) << 8); ++ _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo); ++ } ++ break; ++ case PCI_EHCI_LEGSMIEN_REG: ++ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); ++ hi &= 0x003f0000; ++ hi |= (value & 0x3f) << 16; ++ _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); ++ break; ++ case PCI_EHCI_FLADJ_REG: ++ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); ++ hi &= ~0x00003f00; ++ hi |= value & 0x00003f00; ++ _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); ++ break; ++ default: ++ break; ++ } ++ ++ return; ++} ++ ++u32 pci_ehci_read_reg(int reg) ++{ ++ u32 conf_data = 0; ++ u32 hi, lo; ++ ++ switch (reg) { ++ case PCI_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID); ++ break; ++ case PCI_COMMAND: ++ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); ++ if (hi & PCI_COMMAND_MASTER) ++ conf_data |= PCI_COMMAND_MASTER; ++ if (hi & PCI_COMMAND_MEMORY) ++ conf_data |= PCI_COMMAND_MEMORY; ++ break; ++ case PCI_STATUS: ++ conf_data |= PCI_STATUS_66MHZ; ++ conf_data |= PCI_STATUS_FAST_BACK; ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) ++ conf_data |= PCI_STATUS_PARITY; ++ conf_data |= PCI_STATUS_DEVSEL_MEDIUM; ++ break; ++ case PCI_CLASS_REVISION: ++ _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); ++ conf_data = lo & 0x000000ff; ++ conf_data |= (CS5536_EHCI_CLASS_CODE << 8); ++ break; ++ case PCI_CACHE_LINE_SIZE: ++ conf_data = ++ CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, ++ PCI_NORMAL_LATENCY_TIMER); ++ break; ++ case PCI_BAR0_REG: ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ if (lo & SOFT_BAR_EHCI_FLAG) { ++ conf_data = CS5536_EHCI_RANGE | ++ PCI_BASE_ADDRESS_SPACE_MEMORY; ++ lo &= ~SOFT_BAR_EHCI_FLAG; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else { ++ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); ++ conf_data = lo & 0xfffff000; ++ } ++ break; ++ case PCI_BAR1_REG: ++ case PCI_BAR2_REG: ++ case PCI_BAR3_REG: ++ case PCI_BAR4_REG: ++ case PCI_BAR5_REG: ++ break; ++ case PCI_CARDBUS_CIS: ++ conf_data = PCI_CARDBUS_CIS_POINTER; ++ break; ++ case PCI_SUBSYSTEM_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID); ++ break; ++ case PCI_ROM_ADDRESS: ++ conf_data = PCI_EXPANSION_ROM_BAR; ++ break; ++ case PCI_CAPABILITY_LIST: ++ conf_data = PCI_CAPLIST_USB_POINTER; ++ break; ++ case PCI_INTERRUPT_LINE: ++ conf_data = ++ CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); ++ break; ++ case PCI_EHCI_LEGSMIEN_REG: ++ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); ++ conf_data = (hi & 0x003f0000) >> 16; ++ break; ++ case PCI_EHCI_LEGSMISTS_REG: ++ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); ++ conf_data = (hi & 0x3f000000) >> 24; ++ break; ++ case PCI_EHCI_FLADJ_REG: ++ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); ++ conf_data = hi & 0x00003f00; ++ break; ++ default: ++ break; ++ } ++ ++ return conf_data; ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_flash.c rt4ls/arch/mips/loongson/common/cs5536/cs5536_flash.c +--- linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_flash.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/cs5536/cs5536_flash.c 2009-06-12 16:27:08.774444476 +0200 +@@ -0,0 +1,452 @@ ++/* ++ * the FLASH Virtual Support Module of AMD CS5536 ++ * ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author : jlliu, liujl@lemote.com ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <cs5536/cs5536.h> ++#include <cs5536/cs5536_pci.h> ++ ++/* ++ * enable the region of flashs(NOR or NAND) ++ * ++ * the same as the DIVIL other modules above, two groups of regs should be ++ * modified here to control the region. DIVIL flash LBAR and the ++ * RCONFx(6~9 reserved). ++ */ ++static void flash_lbar_enable(void) ++{ ++ u32 hi, lo; ++ int offset; ++ ++ for (offset = DIVIL_LBAR_FLSH0; offset <= DIVIL_LBAR_FLSH3; offset++) { ++ _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); ++ hi |= 0x1; ++ _wrmsr(DIVIL_MSR_REG(offset), hi, lo); ++ } ++ ++ for (offset = SB_R6; offset <= SB_R9; offset++) { ++ _rdmsr(SB_MSR_REG(offset), &hi, &lo); ++ lo |= 0x1; ++ _wrmsr(SB_MSR_REG(offset), hi, lo); ++ } ++ ++ return; ++} ++ ++/* ++ * disable the region of flashs(NOR or NAND) ++ */ ++static void flash_lbar_disable(void) ++{ ++ u32 hi, lo; ++ int offset; ++ ++ for (offset = DIVIL_LBAR_FLSH0; offset <= DIVIL_LBAR_FLSH3; offset++) { ++ _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); ++ hi &= ~0x01; ++ _wrmsr(DIVIL_MSR_REG(offset), hi, lo); ++ } ++ for (offset = SB_R6; offset <= SB_R9; offset++) { ++ _rdmsr(SB_MSR_REG(offset), &hi, &lo); ++ lo &= ~0x01; ++ _wrmsr(SB_MSR_REG(offset), hi, lo); ++ } ++ ++ return; ++} ++ ++#ifndef CONFIG_CS5536_NOR_FLASH /* for nand flash */ ++ ++void pci_flash_write_bar(int n, u32 value) ++{ ++ u32 hi = 0, lo = value; ++ ++ if (value == PCI_BAR_RANGE_MASK) { ++ /* make the flag for reading the bar length. */ ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ lo |= (SOFT_BAR_FLSH0_FLAG << n); ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else if ((value & 0x01) == 0x00) { ++ /* mem space nand flash native reg base addr */ ++ hi = 0xfffff007; ++ lo &= CS5536_FLSH_RANGE; ++ _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0 + n), hi, lo); ++ ++ /* RCONFx is 4KB in units for mem space. */ ++ hi = ((value & 0xfffff000) << 12) | ++ ((CS5536_FLSH_LENGTH & 0xfffff000) - (1 << 12)) | 0x00; ++ lo = ((value & 0xfffff000) << 12) | 0x01; ++ _wrmsr(SB_MSR_REG(SB_R6 + n), hi, lo); ++ } ++ return; ++} ++ ++void pci_flash_write_reg(int reg, u32 value) ++{ ++ u32 hi = 0, lo = value; ++ ++ switch (reg) { ++ case PCI_COMMAND: ++ if (value & PCI_COMMAND_MEMORY) ++ flash_lbar_enable(); ++ else ++ flash_lbar_disable(); ++ break; ++ case PCI_STATUS: ++ if (value & PCI_STATUS_PARITY) { ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) { ++ lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; ++ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); ++ } ++ } ++ break; ++ case PCI_BAR0_REG: ++ pci_flash_write_bar(0, value); ++ break; ++ case PCI_BAR1_REG: ++ pci_flash_write_bar(1, value); ++ break; ++ case PCI_BAR2_REG: ++ pci_flash_write_bar(2, value); ++ break; ++ case PCI_BAR3_REG: ++ pci_flash_write_bar(3, value); ++ break; ++ case PCI_FLASH_INT_REG: ++ _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); ++ /* disable all the flash interrupt in PIC */ ++ lo &= ~(0xf << PIC_YSEL_LOW_FLASH_SHIFT); ++ if (value) /* enable all the flash interrupt in PIC */ ++ lo |= (CS5536_FLASH_INTR << PIC_YSEL_LOW_FLASH_SHIFT); ++ _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); ++ break; ++ case PCI_NAND_FLASH_TDATA_REG: ++ _wrmsr(DIVIL_MSR_REG(NANDF_DATA), hi, lo); ++ break; ++ case PCI_NAND_FLASH_TCTRL_REG: ++ lo &= 0x00000fff; ++ _wrmsr(DIVIL_MSR_REG(NANDF_CTRL), hi, lo); ++ break; ++ case PCI_NAND_FLASH_RSVD_REG: ++ _wrmsr(DIVIL_MSR_REG(NANDF_RSVD), hi, lo); ++ break; ++ case PCI_FLASH_SELECT_REG: ++ if (value == CS5536_IDE_FLASH_SIGNATURE) { ++ _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo); ++ lo &= ~0x01; ++ _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo); ++ } ++ break; ++ default: ++ break; ++ } ++ ++ return; ++} ++ ++u32 pci_flash_read_bar(int n) ++{ ++ u32 hi, lo; ++ u32 conf_data = 0; ++ ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ if (lo & (SOFT_BAR_FLSH0_FLAG << n)) { ++ conf_data = CS5536_FLSH_RANGE | PCI_BASE_ADDRESS_SPACE_MEMORY; ++ lo &= ~(SOFT_BAR_FLSH0_FLAG << n); ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else { ++ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0 + n), &hi, &lo); ++ conf_data = lo; ++ conf_data &= ~0x0f; ++ } ++ ++ return conf_data; ++} ++ ++u32 pci_flash_read_reg(int reg) ++{ ++ u32 conf_data = 0; ++ u32 hi, lo; ++ ++ switch (reg) { ++ case PCI_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_FLASH_DEVICE_ID, CS5536_VENDOR_ID); ++ break; ++ case PCI_COMMAND: ++ /* we just read one lbar for returning. */ ++ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0), &hi, &lo); ++ if (hi & 0x1) ++ conf_data |= PCI_COMMAND_MEMORY; ++ break; ++ case PCI_STATUS: ++ conf_data |= PCI_STATUS_66MHZ; ++ conf_data |= PCI_STATUS_FAST_BACK; ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) ++ conf_data |= PCI_STATUS_PARITY; ++ conf_data |= PCI_STATUS_DEVSEL_MEDIUM; ++ break; ++ case PCI_CLASS_REVISION: ++ _rdmsr(DIVIL_MSR_REG(DIVIL_CAP), &hi, &lo); ++ conf_data = lo & 0x000000ff; ++ conf_data |= (CS5536_FLASH_CLASS_CODE << 8); ++ break; ++ case PCI_CACHE_LINE_SIZE: ++ conf_data = ++ CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, ++ PCI_NORMAL_LATENCY_TIMER); ++ break; ++ case PCI_BAR0_REG: ++ return pci_flash_read_bar(0); ++ break; ++ case PCI_BAR1_REG: ++ return pci_flash_read_bar(1); ++ break; ++ case PCI_BAR2_REG: ++ return pci_flash_read_bar(2); ++ break; ++ case PCI_BAR3_REG: ++ return pci_flash_read_bar(3); ++ break; ++ case PCI_CARDBUS_CIS: ++ conf_data = PCI_CARDBUS_CIS_POINTER; ++ break; ++ case PCI_SUBSYSTEM_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_FLASH_SUB_ID, ++ CS5536_SUB_VENDOR_ID); ++ break; ++ case PCI_ROM_ADDRESS: ++ conf_data = PCI_EXPANSION_ROM_BAR; ++ break; ++ case PCI_CAPABILITY_LIST: ++ conf_data = PCI_CAPLIST_POINTER; ++ break; ++ case PCI_INTERRUPT_LINE: ++ conf_data = ++ CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_FLASH_INTR); ++ break; ++ case PCI_NAND_FLASH_TDATA_REG: ++ _rdmsr(DIVIL_MSR_REG(NANDF_DATA), &hi, &lo); ++ conf_data = lo; ++ break; ++ case PCI_NAND_FLASH_TCTRL_REG: ++ _rdmsr(DIVIL_MSR_REG(NANDF_CTRL), &hi, &lo); ++ conf_data = lo & 0x00000fff; ++ break; ++ case PCI_NAND_FLASH_RSVD_REG: ++ _rdmsr(DIVIL_MSR_REG(NANDF_RSVD), &hi, &lo); ++ conf_data = lo; ++ break; ++ case PCI_FLASH_SELECT_REG: ++ _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo); ++ conf_data = lo & 0x01; ++ break; ++ default: ++ break; ++ } ++ return 0; ++} ++ ++#else /* CONFIG_CS5536_NOR_FLASH */ ++ ++void pci_flash_write_bar(int n, u32 value) ++{ ++ u32 hi = 0, lo = value; ++ ++ if (value == PCI_BAR_RANGE_MASK) { ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ lo |= (SOFT_BAR_FLSH0_FLAG << n); ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else if (value & 0x01) { ++ /* IO space of 16bytes nor flash */ ++ hi = 0x0000fff1; ++ lo &= CS5536_FLSH_RANGE; ++ _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0 + n), hi, lo); ++ ++ /* RCONFx used for 16bytes reserved. */ ++ hi = ((value & 0x000ffffc) << 12) | ((CS5536_FLSH_LENGTH - 4) ++ << 12) | 0x01; ++ lo = ((value & 0x000ffffc) << 12) | 0x01; ++ _wrmsr(SB_MSR_REG(SB_R6 + n), hi, lo); ++ } ++ return; ++} ++ ++void pci_flash_write_reg(int reg, u32 value) ++{ ++ u32 hi = 0, lo = value; ++ ++ switch (reg) { ++ case PCI_COMMAND: ++ if (value & PCI_COMMAND_IO) ++ flash_lbar_enable(); ++ else ++ flash_lbar_disable(); ++ break; ++ case PCI_STATUS: ++ if (value & PCI_STATUS_PARITY) { ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) { ++ lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; ++ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); ++ } ++ } ++ break; ++ case PCI_BAR0_REG: ++ pci_flash_write_bar(0, value); ++ break; ++ case PCI_BAR1_REG: ++ pci_flash_write_bar(1, value); ++ break; ++ case PCI_BAR2_REG: ++ pci_flash_write_bar(2, value); ++ break; ++ case PCI_BAR3_REG: ++ pci_flash_write_bar(3, value); ++ break; ++ case PCI_FLASH_INT_REG: ++ _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); ++ /* disable all the flash interrupt in PIC */ ++ lo &= ~(0xf << PIC_YSEL_LOW_FLASH_SHIFT); ++ if (value) /* enable all the flash interrupt in PIC */ ++ lo |= (CS5536_FLASH_INTR << PIC_YSEL_LOW_FLASH_SHIFT); ++ _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); ++ break; ++ case PCI_NOR_FLASH_CTRL_REG: ++ lo &= 0x000000ff; ++ _wrmsr(DIVIL_MSR_REG(NORF_CTRL), hi, lo); ++ break; ++ case PCI_NOR_FLASH_T01_REG: ++ _wrmsr(DIVIL_MSR_REG(NORF_T01), hi, lo); ++ break; ++ case PCI_NOR_FLASH_T23_REG: ++ _wrmsr(DIVIL_MSR_REG(NORF_T23), hi, lo); ++ break; ++ case PCI_FLASH_SELECT_REG: ++ if (value == CS5536_IDE_FLASH_SIGNATURE) { ++ _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo); ++ lo &= ~0x01; ++ _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo); ++ } ++ break; ++ default: ++ break; ++ } ++ return; ++} ++ ++u32 pci_flash_read_bar(int n) ++{ ++ u32 hi, lo; ++ u32 conf_data = 0; ++ ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ if (lo & (SOFT_BAR_FLSH0_FLAG << n)) { ++ conf_data = CS5536_FLSH_RANGE | PCI_BASE_ADDRESS_SPACE_IO; ++ lo &= ~(SOFT_BAR_FLSH0_FLAG << n); ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else { ++ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0 + n), &hi, &lo); ++ conf_data = lo & 0x0000ffff; ++ conf_data |= 0x01; ++ conf_data &= ~0x02; ++ } ++ ++ return conf_data; ++} ++ ++u32 pci_flash_read_reg(int reg) ++{ ++ u32 conf_data = 0; ++ u32 hi, lo; ++ ++ switch (reg) { ++ case PCI_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_FLASH_DEVICE_ID, CS5536_VENDOR_ID); ++ break; ++ case PCI_COMMAND: ++ /* we just check one flash bar for returning. */ ++ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_FLSH0), &hi, &lo); ++ if (hi & PCI_COMMAND_IO) ++ conf_data |= PCI_COMMAND_IO; ++ break; ++ case PCI_STATUS: ++ conf_data |= PCI_STATUS_66MHZ; ++ conf_data |= PCI_STATUS_FAST_BACK; ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) ++ conf_data |= PCI_STATUS_PARITY; ++ conf_data |= PCI_STATUS_DEVSEL_MEDIUM; ++ break; ++ case PCI_CLASS_REVISION: ++ _rdmsr(DIVIL_MSR_REG(DIVIL_CAP), &hi, &lo); ++ conf_data = lo & 0x000000ff; ++ conf_data |= (CS5536_FLASH_CLASS_CODE << 8); ++ break; ++ case PCI_CACHE_LINE_SIZE: ++ conf_data = ++ CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, ++ PCI_NORMAL_LATENCY_TIMER); ++ break; ++ case PCI_BAR0_REG: ++ return pci_flash_read_bar(0); ++ break; ++ case PCI_BAR1_REG: ++ return pci_flash_read_bar(1); ++ break; ++ case PCI_BAR2_REG: ++ return pci_flash_read_bar(2); ++ break; ++ case PCI_BAR3_REG: ++ return pci_flash_read_bar(3); ++ break; ++ case PCI_CARDBUS_CIS: ++ conf_data = PCI_CARDBUS_CIS_POINTER; ++ break; ++ case PCI_SUBSYSTEM_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_FLASH_SUB_ID, ++ CS5536_SUB_VENDOR_ID); ++ break; ++ case PCI_ROM_ADDRESS: ++ conf_data = PCI_EXPANSION_ROM_BAR; ++ break; ++ case PCI_CAPABILITY_LIST: ++ conf_data = PCI_CAPLIST_POINTER; ++ break; ++ case PCI_INTERRUPT_LINE: ++ conf_data = ++ CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_FLASH_INTR); ++ break; ++ case PCI_NOR_FLASH_CTRL_REG: ++ _rdmsr(DIVIL_MSR_REG(NORF_CTRL), &hi, &lo); ++ conf_data = lo & 0x000000ff; ++ break; ++ case PCI_NOR_FLASH_T01_REG: ++ _rdmsr(DIVIL_MSR_REG(NORF_T01), &hi, &lo); ++ conf_data = lo; ++ break; ++ case PCI_NOR_FLASH_T23_REG: ++ _rdmsr(DIVIL_MSR_REG(NORF_T23), &hi, &lo); ++ conf_data = lo; ++ break; ++ default: ++ break; ++ } ++ return conf_data; ++} ++#endif /* CONFIG_CS5536_NOR_FLASH */ +diff -Nur linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_ide.c rt4ls/arch/mips/loongson/common/cs5536/cs5536_ide.c +--- linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_ide.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/cs5536/cs5536_ide.c 2009-06-12 16:27:08.774444476 +0200 +@@ -0,0 +1,194 @@ ++/* ++ * the IDE Virtual Support Module of AMD CS5536 ++ * ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author : jlliu, liujl@lemote.com ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <cs5536/cs5536.h> ++#include <cs5536/cs5536_pci.h> ++ ++/* ++ * ide_write : ide write transfering ++ */ ++void pci_ide_write_reg(int reg, u32 value) ++{ ++ u32 hi = 0, lo = value; ++ ++ switch (reg) { ++ case PCI_COMMAND: ++ _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); ++ if (value & PCI_COMMAND_MASTER) ++ lo |= (0x03 << 4); ++ else ++ lo &= ~(0x03 << 4); ++ _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo); ++ break; ++ case PCI_STATUS: ++ if (value & PCI_STATUS_PARITY) { ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) { ++ lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; ++ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); ++ } ++ } ++ break; ++ case PCI_CACHE_LINE_SIZE: ++ value &= 0x0000ff00; ++ _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); ++ hi &= 0xffffff00; ++ hi |= (value >> 8); ++ _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo); ++ break; ++ case PCI_BAR4_REG: ++ if (value == PCI_BAR_RANGE_MASK) { ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ lo |= SOFT_BAR_IDE_FLAG; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else if (value & 0x01) { ++ lo = (value & 0xfffffff0) | 0x1; ++ _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo); ++ ++ value &= 0xfffffffc; ++ hi = 0x60000000 | ((value & 0x000ff000) >> 12); ++ lo = 0x000ffff0 | ((value & 0x00000fff) << 20); ++ _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo); ++ } ++ break; ++ case PCI_IDE_CFG_REG: ++ if (value == CS5536_IDE_FLASH_SIGNATURE) { ++ _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo); ++ lo |= 0x01; ++ _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo); ++ } else ++ _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo); ++ break; ++ case PCI_IDE_DTC_REG: ++ _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo); ++ break; ++ case PCI_IDE_CAST_REG: ++ _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo); ++ break; ++ case PCI_IDE_ETC_REG: ++ _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo); ++ break; ++ case PCI_IDE_PM_REG: ++ _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo); ++ break; ++ default: ++ break; ++ } ++ ++ return; ++} ++ ++/* ++ * ide_read : ide read tranfering. ++ */ ++u32 pci_ide_read_reg(int reg) ++{ ++ u32 conf_data = 0; ++ u32 hi, lo; ++ ++ switch (reg) { ++ case PCI_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID); ++ break; ++ case PCI_COMMAND: ++ _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); ++ if (lo & 0xfffffff0) ++ conf_data |= PCI_COMMAND_IO; ++ _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); ++ if ((lo & 0x30) == 0x30) ++ conf_data |= PCI_COMMAND_MASTER; ++ break; ++ case PCI_STATUS: ++ conf_data |= PCI_STATUS_66MHZ; ++ conf_data |= PCI_STATUS_FAST_BACK; ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) ++ conf_data |= PCI_STATUS_PARITY; ++ conf_data |= PCI_STATUS_DEVSEL_MEDIUM; ++ break; ++ case PCI_CLASS_REVISION: ++ _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo); ++ conf_data = lo & 0x000000ff; ++ conf_data |= (CS5536_IDE_CLASS_CODE << 8); ++ break; ++ case PCI_CACHE_LINE_SIZE: ++ _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); ++ hi &= 0x000000f8; ++ conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi); ++ break; ++ case PCI_BAR0_REG: ++ case PCI_BAR1_REG: ++ case PCI_BAR2_REG: ++ case PCI_BAR3_REG: ++ break; ++ case PCI_BAR4_REG: ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ if (lo & SOFT_BAR_IDE_FLAG) { ++ conf_data = CS5536_IDE_RANGE | ++ PCI_BASE_ADDRESS_SPACE_IO; ++ lo &= ~SOFT_BAR_IDE_FLAG; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else { ++ _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); ++ conf_data = lo & 0xfffffff0; ++ conf_data |= 0x01; ++ conf_data &= ~0x02; ++ } ++ break; ++ case PCI_BAR5_REG: ++ break; ++ case PCI_CARDBUS_CIS: ++ conf_data = PCI_CARDBUS_CIS_POINTER; ++ break; ++ case PCI_SUBSYSTEM_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID); ++ break; ++ case PCI_ROM_ADDRESS: ++ conf_data = PCI_EXPANSION_ROM_BAR; ++ break; ++ case PCI_CAPABILITY_LIST: ++ conf_data = PCI_CAPLIST_POINTER; ++ break; ++ case PCI_INTERRUPT_LINE: ++ conf_data = ++ CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR); ++ break; ++ case PCI_IDE_CFG_REG: ++ _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo); ++ conf_data = lo; ++ break; ++ case PCI_IDE_DTC_REG: ++ _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo); ++ conf_data = lo; ++ break; ++ case PCI_IDE_CAST_REG: ++ _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo); ++ conf_data = lo; ++ break; ++ case PCI_IDE_ETC_REG: ++ _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo); ++ conf_data = lo; ++ case PCI_IDE_PM_REG: ++ _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo); ++ conf_data = lo; ++ break; ++ default: ++ break; ++ } ++ ++ return conf_data; ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_isa.c rt4ls/arch/mips/loongson/common/cs5536/cs5536_isa.c +--- linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_isa.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/cs5536/cs5536_isa.c 2009-06-12 16:27:08.774444476 +0200 +@@ -0,0 +1,376 @@ ++/* ++ * the ISA Virtual Support Module of AMD CS5536 ++ * ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author : jlliu, liujl@lemote.com ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <cs5536/cs5536.h> ++#include <cs5536/cs5536_pci.h> ++ ++/* common variables for PCI_ISA_READ/WRITE_BAR */ ++static const u32 divil_msr_reg[6] = { ++ DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO), ++ DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ), ++ DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI), ++}; ++ ++static const u32 soft_bar_flag[6] = { ++ SOFT_BAR_SMB_FLAG, SOFT_BAR_GPIO_FLAG, SOFT_BAR_MFGPT_FLAG, ++ SOFT_BAR_IRQ_FLAG, SOFT_BAR_PMS_FLAG, SOFT_BAR_ACPI_FLAG, ++}; ++ ++static const u32 sb_msr_reg[6] = { ++ SB_MSR_REG(SB_R0), SB_MSR_REG(SB_R1), SB_MSR_REG(SB_R2), ++ SB_MSR_REG(SB_R3), SB_MSR_REG(SB_R4), SB_MSR_REG(SB_R5), ++}; ++ ++static const u32 bar_space_range[6] = { ++ CS5536_SMB_RANGE, CS5536_GPIO_RANGE, CS5536_MFGPT_RANGE, ++ CS5536_IRQ_RANGE, CS5536_PMS_RANGE, CS5536_ACPI_RANGE, ++}; ++ ++static const int bar_space_len[6] = { ++ CS5536_SMB_LENGTH, CS5536_GPIO_LENGTH, CS5536_MFGPT_LENGTH, ++ CS5536_IRQ_LENGTH, CS5536_PMS_LENGTH, CS5536_ACPI_LENGTH, ++}; ++ ++/* ++ * enable the divil module bar space. ++ * ++ * For all the DIVIL module LBAR, you should control the DIVIL LBAR reg ++ * and the RCONFx(0~5) reg to use the modules. ++ */ ++static void divil_lbar_enable(void) ++{ ++ u32 hi, lo; ++ int offset; ++ ++ /* ++ * The DIVIL IRQ is not used yet. and make the RCONF0 reserved. ++ */ ++ ++ for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) { ++ _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); ++ hi |= 0x01; ++ _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo); ++ } ++ return; ++} ++ ++/* ++ * disable the divil module bar space. ++ */ ++static void divil_lbar_disable(void) ++{ ++ u32 hi, lo; ++ int offset; ++ ++ for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) { ++ _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); ++ hi &= ~0x01; ++ _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo); ++ } ++ return; ++} ++ ++/* ++ * BAR write: write value to the n BAR ++ */ ++ ++void pci_isa_write_bar(int n, u32 value) ++{ ++ u32 hi = 0, lo = value; ++ ++ if (value == PCI_BAR_RANGE_MASK) { ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ lo |= soft_bar_flag[n]; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else if (value & 0x01) { ++ /* NATIVE reg */ ++ hi = 0x0000f001; ++ lo &= bar_space_range[n]; ++ _wrmsr(divil_msr_reg[n], hi, lo); ++ ++ /* RCONFx is 4bytes in units for I/O space */ ++ hi = ((value & 0x000ffffc) << 12) | ++ ((bar_space_len[n] - 4) << 12) | 0x01; ++ lo = ((value & 0x000ffffc) << 12) | 0x01; ++ _wrmsr(sb_msr_reg[n], hi, lo); ++ } ++ ++ return; ++} ++ ++/* ++ * BAR read: read the n BAR ++ */ ++ ++u32 pci_isa_read_bar(int n) ++{ ++ u32 conf_data = 0; ++ u32 hi, lo; ++ ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ if (lo & soft_bar_flag[n]) { ++ conf_data = bar_space_range[n] | PCI_BASE_ADDRESS_SPACE_IO; ++ lo &= ~soft_bar_flag[n]; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else { ++ _rdmsr(divil_msr_reg[n], &hi, &lo); ++ conf_data = lo & bar_space_range[n]; ++ conf_data |= 0x01; ++ conf_data &= ~0x02; ++ } ++ return conf_data; ++} ++ ++/* ++ * isa_write : isa write transfering. ++ * WE assume that the ISA is not the BUS MASTER.!!! ++ */ ++/* FAST BACK TO BACK '1' for BUS MASTER '0' for BUS SALVE */ ++/* COMMAND : ++ * bit0 : IO SPACE ENABLE ++ * bit1 : MEMORY SPACE ENABLE(ignore) ++ * bit2 : BUS MASTER ENABLE(ignore) ++ * bit3 : SPECIAL CYCLE(ignore)? default is ignored. ++ * bit4 : MEMORY WRITE and INVALIDATE(ignore) ++ * bit5 : VGA PALETTE(ignore) ++ * bit6 : PARITY ERROR(ignore)? : default is ignored. ++ * bit7 : WAIT CYCLE CONTROL(ignore) ++ * bit8 : SYSTEM ERROR(ignore) ++ * bit9 : FAST BACK TO BACK(ignore) ++ * bit10-bit15 : RESERVED ++ * STATUS : ++ * bit0-bit3 : RESERVED ++ * bit4 : CAPABILITY LIST(ignore) ++ * bit5 : 66MHZ CAPABLE ++ * bit6 : RESERVED ++ * bit7 : FAST BACK TO BACK(ignore) ++ * bit8 : DATA PARITY ERROR DETECED(ignore) ++ * bit9-bit10 : DEVSEL TIMING(ALL MEDIUM) ++ * bit11: SIGNALED TARGET ABORT ++ * bit12: RECEIVED TARGET ABORT ++ * bit13: RECEIVED MASTER ABORT ++ * bit14: SIGNALED SYSTEM ERROR ++ * bit15: DETECTED PARITY ERROR ++ */ ++ ++void pci_isa_write_reg(int reg, u32 value) ++{ ++ u32 hi = 0, lo = value; ++ u32 temp; ++ ++ switch (reg) { ++ case PCI_COMMAND: ++ if (value & PCI_COMMAND_IO) ++ divil_lbar_enable(); ++ else ++ divil_lbar_disable(); ++ break; ++ case PCI_STATUS: ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ temp = lo & 0x0000ffff; ++ if ((value & PCI_STATUS_SIG_TARGET_ABORT) && ++ (lo & SB_TAS_ERR_EN)) ++ temp |= SB_TAS_ERR_FLAG; ++ ++ if ((value & PCI_STATUS_REC_TARGET_ABORT) && ++ (lo & SB_TAR_ERR_EN)) ++ temp |= SB_TAR_ERR_FLAG; ++ ++ if ((value & PCI_STATUS_REC_MASTER_ABORT) ++ && (lo & SB_MAR_ERR_EN)) ++ temp |= SB_MAR_ERR_FLAG; ++ ++ if ((value & PCI_STATUS_DETECTED_PARITY) ++ && (lo & SB_PARE_ERR_EN)) ++ temp |= SB_PARE_ERR_FLAG; ++ ++ lo = temp; ++ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); ++ break; ++ case PCI_CACHE_LINE_SIZE: ++ value &= 0x0000ff00; ++ _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); ++ hi &= 0xffffff00; ++ hi |= (value >> 8); ++ _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo); ++ break; ++ case PCI_BAR0_REG: ++ pci_isa_write_bar(0, value); ++ break; ++ case PCI_BAR1_REG: ++ pci_isa_write_bar(1, value); ++ break; ++ case PCI_BAR2_REG: ++ pci_isa_write_bar(2, value); ++ break; ++ case PCI_BAR3_REG: ++ pci_isa_write_bar(3, value); ++ break; ++ case PCI_BAR4_REG: ++ pci_isa_write_bar(4, value); ++ break; ++ case PCI_BAR5_REG: ++ pci_isa_write_bar(5, value); ++ break; ++ case PCI_UART1_INT_REG: ++ _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); ++ /* disable uart1 interrupt in PIC */ ++ lo &= ~(0xf << 24); ++ if (value) /* enable uart1 interrupt in PIC */ ++ lo |= (CS5536_UART1_INTR << 24); ++ _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo); ++ break; ++ case PCI_UART2_INT_REG: ++ _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); ++ /* disable uart2 interrupt in PIC */ ++ lo &= ~(0xf << 28); ++ if (value) /* enable uart2 interrupt in PIC */ ++ lo |= (CS5536_UART2_INTR << 28); ++ _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo); ++ break; ++ case PCI_ISA_FIXUP_REG: ++ if (value) { ++ /* enable the TARGET ABORT/MASTER ABORT etc. */ ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ lo |= 0x00000063; ++ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); ++ } ++ ++ default: ++ /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */ ++ break; ++ } ++ ++ return; ++} ++ ++/* ++ * isa_read : isa read transfering. ++ * we assume that the ISA is not the BUS MASTER. ++ */ ++ ++ /* COMMAND : ++ * bit0 : IO SPACE ENABLE ++ * bit1 : MEMORY SPACE ENABLE(ignore) ++ * bit2 : BUS MASTER ENABLE(ignore) ++ * bit3 : SPECIAL CYCLE(ignore)? default is ignored. ++ * bit4 : MEMORY WRITE and INVALIDATE(ignore) ++ * bit5 : VGA PALETTE(ignore) ++ * bit6 : PARITY ERROR(ignore)? : default is ignored. ++ * bit7 : WAIT CYCLE CONTROL(ignore) ++ * bit8 : SYSTEM ERROR(ignore) ++ * bit9 : FAST BACK TO BACK(ignore) ++ * bit10-bit15 : RESERVED ++ * STATUS : ++ * bit0-bit3 : RESERVED ++ * bit4 : CAPABILITY LIST(ignore) ++ * bit5 : 66MHZ CAPABLE ++ * bit6 : RESERVED ++ * bit7 : FAST BACK TO BACK(ignore) ++ * bit8 : DATA PARITY ERROR DETECED(ignore)? ++ * bit9-bit10 : DEVSEL TIMING(ALL MEDIUM) ++ * bit11: SIGNALED TARGET ABORT ++ * bit12: RECEIVED TARGET ABORT ++ * bit13: RECEIVED MASTER ABORT ++ * bit14: SIGNALED SYSTEM ERROR ++ * bit15: DETECTED PARITY ERROR(?) ++ */ ++ ++u32 pci_isa_read_reg(int reg) ++{ ++ u32 conf_data = 0; ++ u32 hi, lo; ++ ++ switch (reg) { ++ case PCI_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_ISA_DEVICE_ID, CS5536_VENDOR_ID); ++ break; ++ case PCI_COMMAND: ++ /* we just check the first LBAR for the IO enable bit, */ ++ /* maybe we should changed later. */ ++ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo); ++ if (hi & 0x01) ++ conf_data |= PCI_COMMAND_IO; ++ break; ++ case PCI_STATUS: ++ conf_data |= PCI_STATUS_66MHZ; ++ conf_data |= PCI_STATUS_DEVSEL_MEDIUM; ++ conf_data |= PCI_STATUS_FAST_BACK; ++ ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_TAS_ERR_FLAG) ++ conf_data |= PCI_STATUS_SIG_TARGET_ABORT; ++ if (lo & SB_TAR_ERR_FLAG) ++ conf_data |= PCI_STATUS_REC_TARGET_ABORT; ++ if (lo & SB_MAR_ERR_FLAG) ++ conf_data |= PCI_STATUS_REC_MASTER_ABORT; ++ if (lo & SB_PARE_ERR_FLAG) ++ conf_data |= PCI_STATUS_DETECTED_PARITY; ++ break; ++ case PCI_CLASS_REVISION: ++ _rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo); ++ conf_data = lo & 0x000000ff; ++ conf_data |= (CS5536_ISA_CLASS_CODE << 8); ++ break; ++ case PCI_CACHE_LINE_SIZE: ++ _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); ++ hi &= 0x000000f8; ++ conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi); ++ break; ++ /* ++ * we only use the LBAR of DIVIL, no RCONF used. ++ * all of them are IO space. ++ */ ++ case PCI_BAR0_REG: ++ return pci_isa_read_bar(0); ++ break; ++ case PCI_BAR1_REG: ++ return pci_isa_read_bar(1); ++ break; ++ case PCI_BAR2_REG: ++ return pci_isa_read_bar(2); ++ break; ++ case PCI_BAR3_REG: ++ break; ++ case PCI_BAR4_REG: ++ return pci_isa_read_bar(4); ++ break; ++ case PCI_BAR5_REG: ++ return pci_isa_read_bar(5); ++ break; ++ case PCI_CARDBUS_CIS: ++ conf_data = PCI_CARDBUS_CIS_POINTER; ++ break; ++ case PCI_SUBSYSTEM_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_ISA_SUB_ID, CS5536_SUB_VENDOR_ID); ++ break; ++ case PCI_ROM_ADDRESS: ++ conf_data = PCI_EXPANSION_ROM_BAR; ++ break; ++ case PCI_CAPABILITY_LIST: ++ conf_data = PCI_CAPLIST_POINTER; ++ break; ++ case PCI_INTERRUPT_LINE: ++ /* no interrupt used here */ ++ conf_data = CFG_PCI_INTERRUPT_LINE(0x00, 0x00); ++ break; ++ default: ++ break; ++ } ++ ++ return conf_data; ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c rt4ls/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c +--- linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c 2009-06-12 16:27:08.774444476 +0200 +@@ -0,0 +1,257 @@ ++/* ++ * CS5536 General timer functions ++ * ++ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology ++ * Author: Yanhua, yanh@lemote.com ++ * ++ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology ++ * Author: Wu zhangjin, wuzj@lemote.com ++ * ++ * Reference: 'AMD Geode(TM) CS5536 Companion Device Data Book' ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/io.h> ++#include <linux/init.h> ++#include <linux/module.h> ++#include <linux/jiffies.h> ++#include <linux/spinlock.h> ++#include <linux/interrupt.h> ++#include <linux/clockchips.h> ++ ++#include <asm/time.h> ++ ++#include <cs5536/cs5536_mfgpt.h> ++ ++DEFINE_SPINLOCK(mfgpt_lock); ++EXPORT_SYMBOL(mfgpt_lock); ++ ++static u32 mfgpt_base; ++ ++/* ++ * Initialize the MFGPT timer. ++ * ++ * This is also called after resume to bring the MFGPT into operation again. ++ */ ++/* setup register bit fields: ++ * 15: counter enable ++ * 14: compare2 output status, write 1 to clear when in event mode ++ * 13: compare1 output status ++ * 12: setup(ro) ++ * 11: stop enable, stop on sleep ++ * 10: external enable ++ * 9:8 compare2 mode; 00: disable, 01: compare on equal; 10: compare on GE, ++ * 11 event: GE + irq ++ * 7:6 compare1 mode ++ * 5: reverse enable, bit reverse of the counter ++ * 4: clock select. 0: 32KHz, 1: 14.318MHz ++ * 3:0 counter prescaler scale factor. ++ * select the input clock divide-by value. 2^n ++ * bit 11:0 is write once ++ */ ++ ++static void init_mfgpt_timer(enum clock_event_mode mode, ++ struct clock_event_device *evt) ++{ ++ spin_lock(&mfgpt_lock); ++ ++ switch (mode) { ++ case CLOCK_EVT_MODE_PERIODIC: ++ outw(COMPARE, MFGPT0_CMP2); /* set comparator2 */ ++ outw(0, MFGPT0_CNT); /* set counter to 0 */ ++ /* enable counter, comparator2 to event mode, 14.318MHz clock */ ++ outw(0xe310, MFGPT0_SETUP); ++ break; ++ ++ case CLOCK_EVT_MODE_SHUTDOWN: ++ case CLOCK_EVT_MODE_UNUSED: ++ if (evt->mode == CLOCK_EVT_MODE_PERIODIC || ++ evt->mode == CLOCK_EVT_MODE_ONESHOT) { ++ /* disable counter */ ++ outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP); ++ } ++ break; ++ ++ case CLOCK_EVT_MODE_ONESHOT: ++ /* One shot setup */ ++ outw(0xe300, MFGPT0_SETUP); ++ break; ++ ++ case CLOCK_EVT_MODE_RESUME: ++ /* Nothing to do here */ ++ break; ++ } ++ spin_unlock(&mfgpt_lock); ++} ++ ++/* ++ * Program the next event in oneshot mode ++ * ++ * Delta is given in MFGPT ticks ++ */ ++static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt) ++{ ++ spin_lock(&mfgpt_lock); ++ outw(delta & 0xffff, MFGPT0_CMP2); /* set comparator2 */ ++ outw(0, MFGPT0_CNT); /* set counter to 0 */ ++ spin_unlock(&mfgpt_lock); ++ ++ return 0; ++} ++ ++static struct clock_event_device mfgpt_clockevent = { ++ .name = "mfgpt", ++ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_MODE_ONESHOT, ++ .set_mode = init_mfgpt_timer, ++ .set_next_event = mfgpt_next_event, ++ .irq = CS5536_MFGPT_INTR, ++}; ++ ++static irqreturn_t timer_interrupt(int irq, void *dev_id) ++{ ++ u32 basehi; ++ ++ /* ++ * get MFGPT base address ++ * ++ * NOTE: do not remove me, it's need for the value of mfgpt_base is ++ * variable ++ */ ++ _rdmsr(CS5536_DIVIL_MSR_BASE + DIVIL_LBAR_MFGPT, &basehi, &mfgpt_base); ++ ++ /* ack */ ++ outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP); ++ ++ mfgpt_clockevent.event_handler(&mfgpt_clockevent); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction irq5 = { ++ .handler = timer_interrupt, ++ .flags = IRQF_DISABLED | IRQF_NOBALANCING, ++ .name = "timer" ++}; ++ ++/* ++ * Initialize the conversion factor and the min/max deltas of the clock event ++ * structure and register the clock event source with the framework. ++ */ ++void __init setup_mfgpt_timer(void) ++{ ++ u32 basehi; ++ struct clock_event_device *cd = &mfgpt_clockevent; ++ unsigned int cpu = smp_processor_id(); ++ ++ cd->cpumask = cpumask_of(cpu); ++ clockevent_set_clock(cd, MFGPT_TICK_RATE); ++ cd->max_delta_ns = clockevent_delta2ns(0xffff, cd); ++ cd->min_delta_ns = clockevent_delta2ns(0xf, cd); ++ ++ /* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */ ++ _wrmsr(CS5536_DIVIL_MSR_BASE + MFGPT_IRQ, 0, 0x100); ++ ++ /* Enable Interrupt Gate 5 */ ++ _wrmsr(CS5536_DIVIL_MSR_BASE + PIC_ZSEL_LOW, 0, 0x50000); ++ ++ /* get MFGPT base address */ ++ _rdmsr(CS5536_DIVIL_MSR_BASE + DIVIL_LBAR_MFGPT, &basehi, &mfgpt_base); ++ ++ irq5.mask = cpumask_of_cpu(cpu); ++ ++ clockevents_register_device(cd); ++ ++ setup_irq(CS5536_MFGPT_INTR, &irq5); ++} ++ ++/* ++ * Since the MFGPT overflows every tick, its not very useful ++ * to just read by itself. So use jiffies to emulate a free ++ * running counter: ++ */ ++static cycle_t mfgpt_read(struct clocksource *cs) ++{ ++ unsigned long flags; ++ int count; ++ u32 jifs; ++ static int old_count; ++ static u32 old_jifs; ++ ++ spin_lock_irqsave(&mfgpt_lock, flags); ++ /* ++ * Although our caller may have the read side of xtime_lock, ++ * this is now a seqlock, and we are cheating in this routine ++ * by having side effects on state that we cannot undo if ++ * there is a collision on the seqlock and our caller has to ++ * retry. (Namely, old_jifs and old_count.) So we must treat ++ * jiffies as volatile despite the lock. We read jiffies ++ * before latching the timer count to guarantee that although ++ * the jiffies value might be older than the count (that is, ++ * the counter may underflow between the last point where ++ * jiffies was incremented and the point where we latch the ++ * count), it cannot be newer. ++ */ ++ jifs = jiffies; ++ /* latch the counter */ ++ outw(inw(MFGPT0_SETUP) | 0x0200, MFGPT0_SETUP); ++ /* read the latched count */ ++ count = inw(MFGPT0_CNT); ++ /* restart the counter */ ++ outw(inw(MFGPT0_SETUP) & 0xfdff, MFGPT0_SETUP); ++ ++ /* reset the latch if count > max + 1 */ ++ if (count > COMPARE) { ++ /* set comparator2 */ ++ outw(COMPARE, MFGPT0_CMP2); ++ /* set counter to 0 */ ++ outw(0, MFGPT0_CNT); ++ /* enable counter, comparator2 to event mode, 14.318MHz clock */ ++ outw(0xe310, MFGPT0_SETUP); ++ ++ count = COMPARE - 1; ++ } ++ ++ /* ++ * It's possible for count to appear to go the wrong way for this ++ * reason: ++ * ++ * The timer counter underflows, but we haven't handled the resulting ++ * interrupt and incremented jiffies yet. ++ * ++ * Previous attempts to handle these cases intelligently were buggy, so ++ * we just do the simple thing now. ++ */ ++ if (count > old_count && jifs == old_jifs) ++ count = old_count; ++ ++ old_count = count; ++ old_jifs = jifs; ++ ++ spin_unlock_irqrestore(&mfgpt_lock, flags); ++ ++ return (cycle_t) (jifs * COMPARE) + count; ++} ++ ++static struct clocksource clocksource_mfgpt = { ++ .name = "mfgpt", ++ .rating = 120, /* Functional for real use, but not desired */ ++ .read = mfgpt_read, ++ .mask = CLOCKSOURCE_MASK(32), ++ .mult = 0, ++ .shift = 22, ++}; ++ ++int __init init_mfgpt_clocksource(void) ++{ ++ if (num_possible_cpus() > 1) /* MFGPT does not scale! */ ++ return 0; ++ ++ clocksource_mfgpt.mult = clocksource_hz2mult(MFGPT_TICK_RATE, 22); ++ return clocksource_register(&clocksource_mfgpt); ++} ++ ++arch_initcall(init_mfgpt_clocksource); +diff -Nur linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_ohci.c rt4ls/arch/mips/loongson/common/cs5536/cs5536_ohci.c +--- linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_ohci.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/cs5536/cs5536_ohci.c 2009-06-12 16:27:08.778446663 +0200 +@@ -0,0 +1,168 @@ ++/* ++ * the OHCI Virtual Support Module of AMD CS5536 ++ * ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author : jlliu, liujl@lemote.com ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <cs5536/cs5536.h> ++#include <cs5536/cs5536_pci.h> ++ ++/* ++ * ohci_write : ohci write transfering. ++ */ ++void pci_ohci_write_reg(int reg, u32 value) ++{ ++ u32 hi = 0, lo = value; ++ ++ switch (reg) { ++ case PCI_COMMAND: ++ _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); ++ if (value & PCI_COMMAND_MASTER) ++ hi |= PCI_COMMAND_MASTER; ++ else ++ hi &= ~PCI_COMMAND_MASTER; ++ ++ if (value & PCI_COMMAND_MEMORY) ++ hi |= PCI_COMMAND_MEMORY; ++ else ++ hi &= ~PCI_COMMAND_MEMORY; ++ _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo); ++ break; ++ case PCI_STATUS: ++ if (value & PCI_STATUS_PARITY) { ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) { ++ lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; ++ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); ++ } ++ } ++ break; ++ case PCI_BAR0_REG: ++ if (value == PCI_BAR_RANGE_MASK) { ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ lo |= SOFT_BAR_OHCI_FLAG; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else if ((value & 0x01) == 0x00) { ++ _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo); ++ ++ value &= 0xfffffff0; ++ hi = 0x40000000 | ((value & 0xff000000) >> 24); ++ lo = 0x000fffff | ((value & 0x00fff000) << 8); ++ _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo); ++ } ++ break; ++ case PCI_INTERRUPT_LINE: ++ value &= 0x000000ff; ++ break; ++ case PCI_OHCI_PM_REG: ++ break; ++ case PCI_OHCI_INT_REG: ++ _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); ++ lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT); ++ if (value) /* enable all the usb interrupt in PIC */ ++ lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT); ++ _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); ++ break; ++ default: ++ break; ++ } ++ ++ return; ++} ++ ++/* ++ * ohci_read : ohci read transfering. ++ */ ++u32 pci_ohci_read_reg(int reg) ++{ ++ u32 conf_data = 0; ++ u32 hi, lo; ++ ++ switch (reg) { ++ case PCI_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID); ++ break; ++ case PCI_COMMAND: ++ _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); ++ if (hi & PCI_COMMAND_MASTER) ++ conf_data |= PCI_COMMAND_MASTER; ++ if (hi & PCI_COMMAND_MEMORY) ++ conf_data |= PCI_COMMAND_MEMORY; ++ break; ++ case PCI_STATUS: ++ conf_data |= PCI_STATUS_66MHZ; ++ conf_data |= PCI_STATUS_FAST_BACK; ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) ++ conf_data |= PCI_STATUS_PARITY; ++ conf_data |= PCI_STATUS_DEVSEL_MEDIUM; ++ break; ++ case PCI_CLASS_REVISION: ++ _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); ++ conf_data = lo & 0x000000ff; ++ conf_data |= (CS5536_OHCI_CLASS_CODE << 8); ++ break; ++ case PCI_CACHE_LINE_SIZE: ++ conf_data = ++ CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, ++ PCI_NORMAL_LATENCY_TIMER); ++ break; ++ case PCI_BAR0_REG: ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ if (lo & SOFT_BAR_OHCI_FLAG) { ++ conf_data = CS5536_OHCI_RANGE | ++ PCI_BASE_ADDRESS_SPACE_MEMORY; ++ lo &= ~SOFT_BAR_OHCI_FLAG; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else { ++ _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); ++ conf_data = lo & 0xffffff00; ++ conf_data &= ~0x0000000f; /* 32bit mem */ ++ } ++ break; ++ case PCI_BAR1_REG: ++ case PCI_BAR2_REG: ++ case PCI_BAR3_REG: ++ case PCI_BAR4_REG: ++ case PCI_BAR5_REG: ++ break; ++ case PCI_CARDBUS_CIS: ++ conf_data = PCI_CARDBUS_CIS_POINTER; ++ break; ++ case PCI_SUBSYSTEM_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID); ++ break; ++ case PCI_ROM_ADDRESS: ++ conf_data = PCI_EXPANSION_ROM_BAR; ++ break; ++ case PCI_CAPABILITY_LIST: ++ conf_data = PCI_CAPLIST_USB_POINTER; ++ break; ++ case PCI_INTERRUPT_LINE: ++ conf_data = ++ CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); ++ break; ++ case PCI_OHCI_PM_REG: ++ break; ++ case PCI_OHCI_INT_REG: ++ _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); ++ if ((lo & 0x00000f00) == CS5536_USB_INTR) ++ conf_data = 1; ++ break; ++ default: ++ break; ++ } ++ ++ return conf_data; ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_otg.c rt4ls/arch/mips/loongson/common/cs5536/cs5536_otg.c +--- linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_otg.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/cs5536/cs5536_otg.c 2009-06-12 16:27:08.778446663 +0200 +@@ -0,0 +1,138 @@ ++/* ++ * the OTG Virtual Support Module of AMD CS5536 ++ * ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author : jlliu, liujl@lemote.com ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <cs5536/cs5536.h> ++#include <cs5536/cs5536_pci.h> ++ ++void pci_otg_write_reg(int reg, u32 value) ++{ ++ u32 hi = 0, lo = value; ++ ++ switch (reg) { ++ case PCI_COMMAND: ++ _rdmsr(USB_MSR_REG(USB_OTG), &hi, &lo); ++ if (value & PCI_COMMAND_MEMORY) ++ hi |= PCI_COMMAND_MEMORY; ++ else ++ hi &= ~PCI_COMMAND_MEMORY; ++ _wrmsr(USB_MSR_REG(USB_OTG), hi, lo); ++ break; ++ case PCI_STATUS: ++ if (value & PCI_STATUS_PARITY) { ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) { ++ lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; ++ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); ++ } ++ } ++ break; ++ case PCI_BAR0_REG: ++ if (value == PCI_BAR_RANGE_MASK) { ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ lo |= SOFT_BAR_OTG_FLAG; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else if ((value & 0x01) == 0x00) { ++ _rdmsr(USB_MSR_REG(USB_OTG), &hi, &lo); ++ lo &= 0xffffff00; ++ _wrmsr(USB_MSR_REG(USB_OTG), hi, lo); ++ ++ value &= 0xfffffff0; ++ hi = 0x40000000 | ((value & 0xff000000) >> 24); ++ lo = 0x000fffff | ((value & 0x00fff000) << 8); ++ _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM1), hi, lo); ++ } ++ break; ++ default: ++ break; ++ } ++ ++ return; ++} ++ ++u32 pci_otg_read_reg(int reg) ++{ ++ u32 conf_data = 0; ++ u32 hi, lo; ++ ++ switch (reg) { ++ case PCI_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_OTG_DEVICE_ID, CS5536_VENDOR_ID); ++ break; ++ case PCI_COMMAND: ++ _rdmsr(USB_MSR_REG(USB_OTG), &hi, &lo); ++ if (hi & PCI_COMMAND_MEMORY) ++ conf_data |= PCI_COMMAND_MEMORY; ++ break; ++ case PCI_STATUS: ++ conf_data |= PCI_STATUS_66MHZ; ++ conf_data |= PCI_STATUS_FAST_BACK; ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) ++ conf_data |= PCI_STATUS_PARITY; ++ conf_data |= PCI_STATUS_DEVSEL_MEDIUM; ++ break; ++ case PCI_CLASS_REVISION: ++ _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); ++ conf_data = lo & 0x000000ff; ++ conf_data |= (CS5536_OTG_CLASS_CODE << 8); ++ break; ++ case PCI_CACHE_LINE_SIZE: ++ conf_data = ++ CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, ++ PCI_NORMAL_LATENCY_TIMER); ++ break; ++ case PCI_BAR0_REG: ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ if (lo & SOFT_BAR_OTG_FLAG) { ++ conf_data = CS5536_OTG_RANGE | ++ PCI_BASE_ADDRESS_SPACE_MEMORY; ++ lo &= ~SOFT_BAR_OTG_FLAG; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else { ++ _rdmsr(USB_MSR_REG(USB_OTG), &hi, &lo); ++ conf_data = lo & 0xffffff00; ++ conf_data &= ~0x0000000f; ++ } ++ break; ++ case PCI_BAR1_REG: ++ case PCI_BAR2_REG: ++ case PCI_BAR3_REG: ++ case PCI_BAR4_REG: ++ case PCI_BAR5_REG: ++ break; ++ case PCI_CARDBUS_CIS: ++ conf_data = PCI_CARDBUS_CIS_POINTER; ++ break; ++ case PCI_SUBSYSTEM_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_OTG_SUB_ID, CS5536_SUB_VENDOR_ID); ++ break; ++ case PCI_ROM_ADDRESS: ++ conf_data = PCI_EXPANSION_ROM_BAR; ++ break; ++ case PCI_CAPABILITY_LIST: ++ conf_data = PCI_CAPLIST_USB_POINTER; ++ break; ++ case PCI_INTERRUPT_LINE: ++ conf_data = ++ CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); ++ break; ++ default: ++ break; ++ } ++ ++ return conf_data; ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_pci.c rt4ls/arch/mips/loongson/common/cs5536/cs5536_pci.c +--- linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/cs5536/cs5536_pci.c 2009-06-12 16:27:08.778446663 +0200 +@@ -0,0 +1,126 @@ ++/* ++ * read/write operation to the PCI config space of CS5536 ++ * ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author : jlliu, liujl@lemote.com ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * the Virtual Support Module(VSM) for virtulizing the PCI ++ * configure space are defined in cs5536_modulename.c respectively, ++ * so you can select modules which have been used in his/her board. ++ * to archive this, you just need to add a "select CS5536_[MODULE]" ++ * option in your board in arch/mips/loongson/Kconfig ++ * ++ * after this virtulizing, user can access the PCI configure space ++ * directly as a normal multi-function PCI device which following ++ * the PCI-2.2 spec. ++ */ ++ ++#include <linux/types.h> ++#include <cs5536/cs5536_vsm.h> ++ ++enum { ++ CS5536_FUNC_START = -1, ++ CS5536_ISA_FUNC, ++ CS5536_FLASH_FUNC, ++ CS5536_IDE_FUNC, ++ CS5536_ACC_FUNC, ++ CS5536_OHCI_FUNC, ++ CS5536_EHCI_FUNC, ++ CS5536_UDC_FUNC, ++ CS5536_OTG_FUNC, ++ CS5536_FUNC_END, ++}; ++ ++/* ++ * write to PCI config space and transfer it to MSR write. ++ */ ++void cs5536_pci_conf_write4(int function, int reg, u32 value) ++{ ++ if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END)) ++ return; ++ if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0)) ++ return; ++ ++ switch (function) { ++ case CS5536_ISA_FUNC: ++ pci_isa_write_reg(reg, value); ++ break; ++ case CS5536_FLASH_FUNC: ++ pci_flash_write_reg(reg, value); ++ break; ++ case CS5536_IDE_FUNC: ++ pci_ide_write_reg(reg, value); ++ break; ++ case CS5536_ACC_FUNC: ++ pci_acc_write_reg(reg, value); ++ break; ++ case CS5536_OHCI_FUNC: ++ pci_ohci_write_reg(reg, value); ++ break; ++ case CS5536_EHCI_FUNC: ++ pci_ehci_write_reg(reg, value); ++ break; ++ case CS5536_UDC_FUNC: ++ pci_udc_write_reg(reg, value); ++ break; ++ case CS5536_OTG_FUNC: ++ pci_otg_write_reg(reg, value); ++ break; ++ default: ++ break; ++ } ++ return; ++} ++ ++/* ++ * read PCI config space and transfer it to MSR access. ++ */ ++u32 cs5536_pci_conf_read4(int function, int reg) ++{ ++ u32 data = 0; ++ ++ if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END)) ++ return 0; ++ if ((reg < 0) || ((reg & 0x03) != 0)) ++ return 0; ++ if (reg > 0x100) ++ return 0xffffffff; ++ ++ switch (function) { ++ case CS5536_ISA_FUNC: ++ data = pci_isa_read_reg(reg); ++ break; ++ case CS5536_FLASH_FUNC: ++ data = pci_flash_read_reg(reg); ++ break; ++ case CS5536_IDE_FUNC: ++ data = pci_ide_read_reg(reg); ++ break; ++ case CS5536_ACC_FUNC: ++ data = pci_acc_read_reg(reg); ++ break; ++ case CS5536_OHCI_FUNC: ++ data = pci_ohci_read_reg(reg); ++ break; ++ case CS5536_EHCI_FUNC: ++ data = pci_ehci_read_reg(reg); ++ break; ++ case CS5536_UDC_FUNC: ++ data = pci_udc_read_reg(reg); ++ break; ++ case CS5536_OTG_FUNC: ++ data = pci_otg_read_reg(reg); ++ break; ++ default: ++ break; ++ } ++ return data; ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_udc.c rt4ls/arch/mips/loongson/common/cs5536/cs5536_udc.c +--- linux-2.6.30/arch/mips/loongson/common/cs5536/cs5536_udc.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/cs5536/cs5536_udc.c 2009-06-12 16:27:08.778446663 +0200 +@@ -0,0 +1,143 @@ ++/* ++ * the UDC Virtual Support Module of AMD CS5536 ++ * ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author : jlliu, liujl@lemote.com ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <cs5536/cs5536.h> ++#include <cs5536/cs5536_pci.h> ++ ++void pci_udc_write_reg(int reg, u32 value) ++{ ++ u32 hi = 0, lo = value; ++ ++ switch (reg) { ++ case PCI_COMMAND: ++ _rdmsr(USB_MSR_REG(USB_UDC), &hi, &lo); ++ if (value & PCI_COMMAND_MASTER) ++ hi |= PCI_COMMAND_MASTER; ++ else ++ hi &= ~PCI_COMMAND_MASTER; ++ ++ if (value & PCI_COMMAND_MEMORY) ++ hi |= PCI_COMMAND_MEMORY; ++ else ++ hi &= ~PCI_COMMAND_MEMORY; ++ _wrmsr(USB_MSR_REG(USB_UDC), hi, lo); ++ break; ++ case PCI_STATUS: ++ if (value & PCI_STATUS_PARITY) { ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) { ++ lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; ++ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); ++ } ++ } ++ break; ++ case PCI_BAR0_REG: ++ if (value == PCI_BAR_RANGE_MASK) { ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ lo |= SOFT_BAR_UDC_FLAG; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else if ((value & 0x01) == 0x00) { ++ _wrmsr(USB_MSR_REG(USB_UDC), hi, lo); ++ ++ value &= 0xfffffff0; ++ hi = 0x40000000 | ((value & 0xff000000) >> 24); ++ lo = 0x000fffff | ((value & 0x00fff000) << 8); ++ _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM0), hi, lo); ++ } ++ break; ++ default: ++ break; ++ } ++ ++ return; ++} ++ ++u32 pci_udc_read_reg(int reg) ++{ ++ u32 conf_data = 0; ++ u32 hi, lo; ++ ++ switch (reg) { ++ case PCI_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_UDC_DEVICE_ID, CS5536_VENDOR_ID); ++ break; ++ case PCI_COMMAND: ++ _rdmsr(USB_MSR_REG(USB_UDC), &hi, &lo); ++ if (hi & PCI_COMMAND_MASTER) ++ conf_data |= PCI_COMMAND_MASTER; ++ if (hi & PCI_COMMAND_MEMORY) ++ conf_data |= PCI_COMMAND_MEMORY; ++ break; ++ case PCI_STATUS: ++ conf_data |= PCI_STATUS_66MHZ; ++ conf_data |= PCI_STATUS_FAST_BACK; ++ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); ++ if (lo & SB_PARE_ERR_FLAG) ++ conf_data |= PCI_STATUS_PARITY; ++ conf_data |= PCI_STATUS_DEVSEL_MEDIUM; ++ break; ++ case PCI_CLASS_REVISION: ++ _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); ++ conf_data = lo & 0x000000ff; ++ conf_data |= (CS5536_UDC_CLASS_CODE << 8); ++ break; ++ case PCI_CACHE_LINE_SIZE: ++ conf_data = ++ CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, ++ PCI_NORMAL_LATENCY_TIMER); ++ break; ++ case PCI_BAR0_REG: ++ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); ++ if (lo & SOFT_BAR_UDC_FLAG) { ++ conf_data = CS5536_UDC_RANGE | ++ PCI_BASE_ADDRESS_SPACE_MEMORY; ++ lo &= ~SOFT_BAR_UDC_FLAG; ++ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); ++ } else { ++ _rdmsr(USB_MSR_REG(USB_UDC), &hi, &lo); ++ conf_data = lo & 0xfffff000; ++ conf_data &= ~0x0000000f; /* 32bit mem */ ++ } ++ break; ++ case PCI_BAR1_REG: ++ case PCI_BAR2_REG: ++ case PCI_BAR3_REG: ++ case PCI_BAR4_REG: ++ case PCI_BAR5_REG: ++ break; ++ case PCI_CARDBUS_CIS: ++ conf_data = PCI_CARDBUS_CIS_POINTER; ++ break; ++ case PCI_SUBSYSTEM_VENDOR_ID: ++ conf_data = ++ CFG_PCI_VENDOR_ID(CS5536_UDC_SUB_ID, CS5536_SUB_VENDOR_ID); ++ break; ++ case PCI_ROM_ADDRESS: ++ conf_data = PCI_EXPANSION_ROM_BAR; ++ break; ++ case PCI_CAPABILITY_LIST: ++ conf_data = PCI_CAPLIST_USB_POINTER; ++ break; ++ case PCI_INTERRUPT_LINE: ++ conf_data = ++ CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); ++ break; ++ default: ++ break; ++ } ++ ++ return conf_data; ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/early_printk.c rt4ls/arch/mips/loongson/common/early_printk.c +--- linux-2.6.30/arch/mips/loongson/common/early_printk.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/early_printk.c 2009-06-12 16:27:08.778446663 +0200 +@@ -0,0 +1,28 @@ ++/* early printk support ++ * ++ * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/types.h> ++#include <linux/serial_reg.h> ++ ++#include <loongson.h> ++#include <machine.h> ++ ++void prom_putchar(char c) ++{ ++ int timeout; ++ phys_addr_t uart_base = ++ (phys_addr_t) ioremap_nocache(LOONGSON_UART_BASE, 8); ++ char reg = readb((u8 *) (uart_base + UART_LSR)) & UART_LSR_THRE; ++ ++ for (timeout = 1024; reg == 0 && timeout > 0; timeout--) ++ reg = readb((u8 *) (uart_base + UART_LSR)) & UART_LSR_THRE; ++ ++ writeb(c, (u8 *) (uart_base + UART_TX)); ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/env.c rt4ls/arch/mips/loongson/common/env.c +--- linux-2.6.30/arch/mips/loongson/common/env.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/env.c 2009-06-12 16:27:08.778446663 +0200 +@@ -0,0 +1,59 @@ ++/* ++ * Based on Ocelot Linux port, which is ++ * Copyright 2001 MontaVista Software Inc. ++ * Author: jsun@mvista.com or jsun@junsun.net ++ * ++ * Copyright 2003 ICT CAS ++ * Author: Michael Guo <guoyi@ict.ac.cn> ++ * ++ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <asm/bootinfo.h> ++ ++#include <loongson.h> ++ ++unsigned long bus_clock, cpu_clock_freq; ++unsigned long memsize, highmemsize; ++ ++/* pmon passes arguments in 32bit pointers */ ++int *_prom_envp; ++ ++#define parse_even_earlier(res, option, p) \ ++do { \ ++ if (strncmp(option, (char *)p, strlen(option)) == 0) \ ++ strict_strtol((char *)p + strlen(option"="), \ ++ 10, &res); \ ++} while (0) ++ ++void __init prom_init_env(void) ++{ ++ long l; ++ ++ /* firmware arguments are initialized in head.S */ ++ _prom_envp = (int *)fw_arg2; ++ ++ l = (long)*_prom_envp; ++ while (l != 0) { ++ parse_even_earlier(bus_clock, "busclock", l); ++ parse_even_earlier(cpu_clock_freq, "cpuclock", l); ++ parse_even_earlier(memsize, "memsize", l); ++ parse_even_earlier(highmemsize, "highmemsize", l); ++ _prom_envp++; ++ l = (long)*_prom_envp; ++ } ++ if (memsize == 0) ++ memsize = 256; ++ ++ pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", ++ bus_clock, cpu_clock_freq, memsize, highmemsize); ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/init.c rt4ls/arch/mips/loongson/common/init.c +--- linux-2.6.30/arch/mips/loongson/common/init.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/init.c 2009-06-12 16:27:08.778446663 +0200 +@@ -0,0 +1,54 @@ ++/* ++ * Based on Ocelot Linux port, which is ++ * Copyright 2001 MontaVista Software Inc. ++ * Author: jsun@mvista.com or jsun@junsun.net ++ * ++ * Copyright 2003 ICT CAS ++ * Author: Michael Guo <guoyi@ict.ac.cn> ++ * ++ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/bootmem.h> ++ ++#include <asm/bootinfo.h> ++ ++#include <loongson.h> ++ ++#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) ++unsigned long _loongson_addrwincfg_base; ++ ++/* Loongson CPU address windows config space base address */ ++static inline void set_loongson_addrwincfg_base(unsigned long base) ++{ ++ *(unsigned long *)&_loongson_addrwincfg_base = base; ++ barrier(); ++} ++#endif ++ ++void __init prom_init(void) ++{ ++ /* init several base address */ ++ set_io_port_base((unsigned long) ++ ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); ++ ++#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) ++ set_loongson_addrwincfg_base((unsigned long) ++ ioremap(LOONGSON_ADDRWINCFG_BASE, ++ LOONGSON_ADDRWINCFG_SIZE)); ++#endif ++ ++ prom_init_cmdline(); ++ prom_init_env(); ++ prom_init_memory(); ++} ++ ++void __init prom_free_prom_memory(void) ++{ ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/irq.c rt4ls/arch/mips/loongson/common/irq.c +--- linux-2.6.30/arch/mips/loongson/common/irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/irq.c 2009-06-12 16:27:08.778446663 +0200 +@@ -0,0 +1,132 @@ ++/* ++ * Copyright 2001 MontaVista Software Inc. ++ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net ++ * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) ++ * ++ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/delay.h> ++#include <linux/interrupt.h> ++ ++#include <asm/irq_cpu.h> ++#include <asm/i8259.h> ++ ++#include <loongson.h> ++#include <machine.h> ++ ++/* ++ * the first level int-handler will jump here if it is a loongson irq ++ */ ++void bonito_irqdispatch(void) ++{ ++ u32 int_status; ++ int i; ++ ++ /* workaround the IO dma problem: let cpu looping to allow DMA finish */ ++ int_status = LOONGSON_INTISR; ++ while (int_status & (1 << 10)) { ++ udelay(1); ++ int_status = LOONGSON_INTISR; ++ } ++ ++ /* Get pending sources, masked by current enables */ ++ int_status = LOONGSON_INTISR & LOONGSON_INTEN; ++ ++ if (int_status != 0) { ++ i = __ffs(int_status); ++ int_status &= ~(1 << i); ++ do_IRQ(LOONGSON_IRQ_BASE + i); ++ } ++} ++ ++void i8259_irqdispatch(void) ++{ ++ int irq; ++ ++ irq = mach_i8259_irq(); ++ if (irq < 0) ++ spurious_interrupt(); ++ else ++ do_IRQ(irq); ++} ++ ++asmlinkage void plat_irq_dispatch(void) ++{ ++ unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; ++ ++ mach_irq_dispatch(pending); ++} ++ ++ ++static struct irqaction cascade_irqaction = { ++ .handler = no_action, ++ .name = "cascade", ++}; ++ ++/* ++ * fuloong2f and yeeloong2f share the cpu perf counter interrupt and the north ++ * bridge interrupt in IP6, so, the ip6_irqaction should be sharable. ++ * otherwise, we will can not request the perf counter irq(setup the perf ++ * counter irq handler) in op_model_loongson2.c. ++ */ ++ ++#if defined(CONFIG_OPROFILE) && \ ++ (defined(CONFIG_LEMOTE_FULOONG2F) || defined(CONFIG_LEMOTE_YEELOONG2F)) ++irqreturn_t ip6_action(int cpl, void *dev_id) ++{ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction ip6_irqaction = { ++ .handler = ip6_action, ++ .name = "cascade", ++ .flags = IRQF_SHARED, ++}; ++#else ++#define ip6_irqaction cascade_irqaction ++#endif ++ ++void __init arch_init_irq(void) ++{ ++ /* ++ * Clear all of the interrupts while we change the able around a bit. ++ * int-handler is not on bootstrap ++ */ ++ clear_c0_status(ST0_IM | ST0_BEV); ++ local_irq_disable(); ++ ++ /* setting irq trigger mode */ ++ set_irq_trigger_mode(); ++ ++ /* no steer */ ++ LOONGSON_INTSTEER = 0; ++ ++ /* ++ * Mask out all interrupt by writing "1" to all bit position in ++ * the interrupt reset reg. ++ */ ++ LOONGSON_INTENCLR = ~0; ++ ++ /* init all controller ++ * 0-15 ------> i8259 interrupt ++ * 16-23 ------> mips cpu interrupt ++ * 32-63 ------> bonito irq ++ */ ++ ++ /* Sets the first-level interrupt dispatcher. */ ++ mips_cpu_irq_init(); ++ init_i8259_irqs(); ++ bonito_irq_init(); ++ ++ /* setup north bridge irq (bonito) */ ++ setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction); ++ /* setup source bridge irq (i8259) */ ++ setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction); ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/machtype.c rt4ls/arch/mips/loongson/common/machtype.c +--- linux-2.6.30/arch/mips/loongson/common/machtype.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/machtype.c 2009-06-12 16:27:08.782445496 +0200 +@@ -0,0 +1,50 @@ ++/* ++ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * Copyright (c) 2009 Zhang Le <r0bertz@gentoo.org> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/errno.h> ++#include <asm/bootinfo.h> ++ ++#include <loongson.h> ++#include <machine.h> ++ ++static const char *system_types[] = { ++ [MACH_LOONGSON_UNKNOWN] "unknown loongson machine", ++ [MACH_LEMOTE_FL2E] "lemote-fuloong-2e-box", ++ [MACH_LEMOTE_FL2F] "lemote-fuloong-2f-box", ++ [MACH_LEMOTE_YL2F89] "lemote-yeeloong-2f-8.9inches", ++ [MACH_LEMOTE_YL2F7] "lemote-yeeloong-2f-7inches", ++ [MACH_LOONGSON_END] NULL, ++}; ++ ++const char *get_system_type(void) ++{ ++ if (mips_machtype == MACH_UNKNOWN) ++ mips_machtype = MACHTYPE; ++ ++ return system_types[mips_machtype]; ++} ++ ++static __init int machtype_setup(char *str) ++{ ++ int machtype = MACH_LEMOTE_FL2E; ++ ++ if (!str) ++ return -EINVAL; ++ ++ for (; system_types[machtype]; machtype++) ++ if (strstr(system_types[machtype], str)) { ++ mips_machtype = machtype; ++ break; ++ } ++ return 0; ++} ++__setup("machtype=", machtype_setup); +diff -Nur linux-2.6.30/arch/mips/loongson/common/mem.c rt4ls/arch/mips/loongson/common/mem.c +--- linux-2.6.30/arch/mips/loongson/common/mem.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/mem.c 2009-06-12 16:27:08.782445496 +0200 +@@ -0,0 +1,116 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/fs.h> ++#include <linux/mm.h> ++ ++#include <asm/bootinfo.h> ++ ++#include <loongson.h> ++#include <mem.h> ++ ++void __init prom_init_memory(void) ++{ ++ add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); ++#ifdef CONFIG_64BIT ++#ifdef CONFIG_CPU_LOONGSON2F ++ { ++ int bit; ++ ++ bit = fls(memsize + highmemsize); ++ if (bit != ffs(memsize + highmemsize)) ++ bit += 20; ++ else ++ bit = bit + 20 - 1; ++ ++ /* set cpu window3 to map CPU to DDR: 2G -> 2G */ ++ LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul, ++ 0x80000000ul, (1 << bit)); ++ mmiowb(); ++ } ++#endif /* CONFIG_CPU_LOONGSON2F */ ++ ++ if (highmemsize > 0) { ++ add_memory_region(LOONGSON_HIGHMEM_START, ++ highmemsize << 20, BOOT_MEM_RAM); ++ } ++#endif /* CONFIG_64BIT */ ++} ++ ++/* override of arch/mips/mm/cache.c: __uncached_access */ ++int __uncached_access(struct file *file, unsigned long addr) ++{ ++ if (file->f_flags & O_SYNC) ++ return 1; ++ ++ return addr >= __pa(high_memory) || ++ ((addr >= LOONGSON_MMIO_MEM_START) && \ ++ (addr < LOONGSON_MMIO_MEM_END)); ++} ++ ++#if defined(CONFIG_CPU_LOONGSON2F) ++ ++#include <linux/pci.h> ++#include <linux/sched.h> ++#include <asm/current.h> ++ ++static unsigned long uca_start; ++static unsigned long uca_size = CONFIG_UCA_SIZE; ++ ++pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, ++ unsigned long size, pgprot_t vma_prot) ++{ ++ unsigned long offset = pfn << PAGE_SHIFT; ++ unsigned long end = offset + size; ++ ++ if (__uncached_access(file, offset)) { ++ if (((uca_start && offset) >= uca_start) && \ ++ (end <= (uca_start + uca_size))) ++ return __pgprot((pgprot_val(vma_prot) & \ ++ ~_CACHE_MASK) | \ ++ _CACHE_UNCACHED_ACCELERATED); ++ else ++ return pgprot_noncached(vma_prot); ++ } ++ return vma_prot; ++} ++ ++static int __init find_vga_mem_init(void) ++{ ++ struct pci_dev *dev = 0; ++ struct resource *r; ++ int idx; ++ ++ if (uca_start) ++ return 0; ++ ++ for_each_pci_dev(dev) { ++ if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) { ++ for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) { ++ r = &dev->resource[idx]; ++ if (!r->start && r->end) ++ continue; ++ if (r->flags & IORESOURCE_IO) ++ continue; ++ if (r->flags & IORESOURCE_MEM) { ++ uca_start = r->start; ++ ++ printk(KERN_INFO ++ "find the frame buffer:start=%lx\n", ++ uca_start); ++ ++ return 0; ++ } ++ } ++ ++ } ++ } ++ return 0; ++} ++ ++late_initcall(find_vga_mem_init); ++#endif /* !CONFIG_CPU_LOONGSON2F */ +diff -Nur linux-2.6.30/arch/mips/loongson/common/pci.c rt4ls/arch/mips/loongson/common/pci.c +--- linux-2.6.30/arch/mips/loongson/common/pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/pci.c 2009-06-12 16:27:08.782445496 +0200 +@@ -0,0 +1,109 @@ ++/* ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ */ ++ ++#include <linux/pci.h> ++ ++#include <loongson.h> ++#include <pci.h> ++ ++static struct resource loongson_pci_mem_resource = { ++ .name = "pci memory space", ++ .start = LOONGSON_PCI_MEM_START, ++ .end = LOONGSON_PCI_MEM_END, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct resource loongson_pci_io_resource = { ++ .name = "pci io space", ++ .start = LOONGSON_PCI_IO_START, /* reserve regacy I/O space */ ++ .end = IO_SPACE_LIMIT, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct pci_controller loongson_pci_controller = { ++ .pci_ops = &loongson_pci_ops, ++ .io_resource = &loongson_pci_io_resource, ++ .mem_resource = &loongson_pci_mem_resource, ++ .mem_offset = 0x00000000UL, ++ .io_offset = 0x00000000UL, ++}; ++ ++static void __init ict_pcimap(void) ++{ ++ /* ++ * local to PCI mapping for CPU accessing PCI space ++ * ++ * CPU address space [256M,448M] is window for accessing pci space ++ * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M] ++ * ++ * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 ++ * [<2G] [384M,448M] [320M,384M] [0M,64M] ++ */ ++ LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 | ++ LOONGSON_PCIMAP_WIN(2, 0x18000000) | ++ LOONGSON_PCIMAP_WIN(1, 0x14000000) | ++ LOONGSON_PCIMAP_WIN(0, 0); ++ ++ /* ++ * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] ++ */ ++ LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ ++ /* size: 256M, burst transmission, pre-fetch enable, 64bit */ ++ LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; ++ LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; ++ LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */ ++ LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul; ++ LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */ ++ LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul; ++ ++ /* avoid deadlock of PCI reading/writing lock operation */ ++ LOONGSON_PCI_ISR4C = 0xd2000001ul; ++ ++ /* can not change gnt to break pci transfer when device's gnt not ++ deassert for some broken device */ ++ LOONGSON_PXARB_CFG = 0x00fe0105ul; ++ ++#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) ++ /* ++ * set cpu addr window2 to map CPU address space to PCI address space ++ */ ++ LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC, ++ LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE); ++#endif ++} ++ ++static int __init pcibios_init(void) ++{ ++ ict_pcimap(); ++ ++ loongson_pci_controller.io_map_base = mips_io_port_base; ++ ++ register_pci_controller(&loongson_pci_controller); ++ ++ return 0; ++} ++ ++arch_initcall(pcibios_init); +diff -Nur linux-2.6.30/arch/mips/loongson/common/reset.c rt4ls/arch/mips/loongson/common/reset.c +--- linux-2.6.30/arch/mips/loongson/common/reset.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/reset.c 2009-06-12 16:27:08.782445496 +0200 +@@ -0,0 +1,38 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ */ ++ ++#include <linux/pm.h> ++ ++#include <asm/reboot.h> ++ ++#include <loongson.h> ++ ++static void loongson_restart(char *command) ++{ ++ /* perform board-specific pre-reboot operations */ ++ mach_prepare_reboot(); ++ ++ /* reboot via jumping to 0xbfc00000 */ ++ ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) (); ++} ++ ++static void loongson_halt(void) ++{ ++ mach_prepare_shutdown(); ++ while (1) ++ ; ++} ++ ++void __init loongson_reboot_setup(void) ++{ ++ _machine_restart = loongson_restart; ++ _machine_halt = loongson_halt; ++ pm_power_off = loongson_halt; ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/rtc.c rt4ls/arch/mips/loongson/common/rtc.c +--- linux-2.6.30/arch/mips/loongson/common/rtc.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/rtc.c 2009-06-12 16:27:08.782445496 +0200 +@@ -0,0 +1,54 @@ ++/* ++ * Registration of Cobalt RTC platform device. ++ * ++ * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> ++ * Copyright (C) 2009 Wu Zhangjin <wuzj@lemote.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, ++ * MA 02110-1301 USA ++ */ ++ ++#include <linux/ioport.h> ++#include <linux/mc146818rtc.h> ++#include <linux/platform_device.h> ++ ++static struct resource rtc_cmos_resource[] = { ++ { ++ .start = RTC_PORT(0), ++ .end = RTC_PORT(1), ++ .flags = IORESOURCE_IO, ++ }, ++ { ++ .start = RTC_IRQ, ++ .end = RTC_IRQ, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device rtc_cmos_device = { ++ .name = "rtc_cmos", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(rtc_cmos_resource), ++ .resource = rtc_cmos_resource ++}; ++ ++static __init int rtc_cmos_init(void) ++{ ++ platform_device_register(&rtc_cmos_device); ++ ++ return 0; ++} ++ ++device_initcall(rtc_cmos_init); +diff -Nur linux-2.6.30/arch/mips/loongson/common/serial.c rt4ls/arch/mips/loongson/common/serial.c +--- linux-2.6.30/arch/mips/loongson/common/serial.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/serial.c 2009-06-12 16:27:08.782445496 +0200 +@@ -0,0 +1,66 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: yanhua (yanhua@lemote.com) ++ * Author: Wu Zhangjin (wuzj@lemote.com) ++ */ ++ ++#include <linux/io.h> ++#include <linux/init.h> ++#include <linux/serial_8250.h> ++ ++#include <loongson.h> ++#include <machine.h> ++ ++#define PORT(int, base_baud, io_type) \ ++{ \ ++ .irq = int, \ ++ .uartclk = base_baud, \ ++ .iotype = io_type, \ ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ ++ .regshift = 0, \ ++} ++ ++static struct plat_serial8250_port uart8250_data[] = { ++ PORT(LOONGSON_UART_IRQ, LOONGSON_UART_BAUD, LOONGSON_UART_IOTYPE), ++ {}, ++}; ++ ++static struct platform_device uart8250_device = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = uart8250_data, ++ }, ++}; ++ ++static inline void uart8250_init(void) ++{ ++#if (LOONGSON_UART_IOTYPE == UPIO_MEM) ++ uart8250_data[0].membase = ++ ioremap_nocache(LOONGSON_UART_BASE, 8); ++#elif (LOONGSON_UART_IOTYPE == UPIO_PORT) ++ uart8250_data[0].iobase = ++ LOONGSON_UART_BASE - LOONGSON_PCIIO_BASE; ++ uart8250_data[0].irq -= MIPS_CPU_IRQ_BASE; ++#else ++#warning currently, no such iotype of uart used in loongson-based machines ++ ++#endif ++} ++ ++static int __init serial_init(void) ++{ ++ uart8250_init(); ++ ++ platform_device_register(&uart8250_device); ++ ++ return 0; ++} ++ ++device_initcall(serial_init); +diff -Nur linux-2.6.30/arch/mips/loongson/common/setup.c rt4ls/arch/mips/loongson/common/setup.c +--- linux-2.6.30/arch/mips/loongson/common/setup.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/setup.c 2009-06-12 16:27:08.782445496 +0200 +@@ -0,0 +1,74 @@ ++/* ++ * board dependent setup routines ++ * ++ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/module.h> ++ ++#include <asm/wbflush.h> ++ ++#include <loongson.h> ++ ++void (*__wbflush) (void); ++EXPORT_SYMBOL(__wbflush); ++ ++static void loongson_wbflush(void) ++{ ++ asm(".set\tpush\n\t" ++ ".set\tnoreorder\n\t" ++ ".set mips3\n\t" ++ "sync\n\t" ++ "nop\n\t" ++ ".set\tpop\n\t" ++ ".set mips0\n\t"); ++} ++ ++void __init loongson_wbflush_setup(void) ++{ ++ __wbflush = loongson_wbflush; ++} ++ ++#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) ++#include <linux/screen_info.h> ++ ++void __init loongson_screeninfo_setup(void) ++{ ++ screen_info = (struct screen_info) { ++ 0, /* orig-x */ ++ 25, /* orig-y */ ++ 0, /* unused */ ++ 0, /* orig-video-page */ ++ 0, /* orig-video-mode */ ++ 80, /* orig-video-cols */ ++ 0, /* ega_ax */ ++ 0, /* ega_bx */ ++ 0, /* ega_cx */ ++ 25, /* orig-video-lines */ ++ VIDEO_TYPE_VGAC, /* orig-video-isVGA */ ++ 16 /* orig-video-points */ ++ }; ++} ++#else ++void __init loongson_screeninfo_setup(void) ++{ ++} ++#endif ++ ++void __init plat_mem_setup(void) ++{ ++ loongson_reboot_setup(); ++ ++ loongson_wbflush_setup(); ++ ++ loongson_screeninfo_setup(); ++} +diff -Nur linux-2.6.30/arch/mips/loongson/common/time.c rt4ls/arch/mips/loongson/common/time.c +--- linux-2.6.30/arch/mips/loongson/common/time.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/common/time.c 2009-06-12 16:27:08.782445496 +0200 +@@ -0,0 +1,34 @@ ++/* ++ * board dependent boot routines ++ * ++ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <asm/mc146818-time.h> ++#include <asm/time.h> ++ ++#include <loongson.h> ++#ifdef CONFIG_CS5536_MFGPT ++#include <cs5536/cs5536_mfgpt.h> ++#endif ++ ++unsigned long read_persistent_clock(void) ++{ ++ return mc146818_get_cmos_time(); ++} ++ ++void __init plat_time_init(void) ++{ ++ /* setup mips r4k timer */ ++ mips_hpt_frequency = cpu_clock_freq / 2; ++ ++#ifdef CONFIG_CS5536_MFGPT ++ setup_mfgpt_timer(); ++#endif ++} +diff -Nur linux-2.6.30/arch/mips/loongson/fuloong-2e/Makefile rt4ls/arch/mips/loongson/fuloong-2e/Makefile +--- linux-2.6.30/arch/mips/loongson/fuloong-2e/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/fuloong-2e/Makefile 2009-06-12 16:27:08.782445496 +0200 +@@ -0,0 +1,7 @@ ++# ++# Makefile for fuloong-2e ++# ++ ++obj-y += irq.o reset.o ++ ++EXTRA_CFLAGS += -Werror +diff -Nur linux-2.6.30/arch/mips/loongson/fuloong-2e/irq.c rt4ls/arch/mips/loongson/fuloong-2e/irq.c +--- linux-2.6.30/arch/mips/loongson/fuloong-2e/irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/fuloong-2e/irq.c 2009-06-12 16:27:08.782445496 +0200 +@@ -0,0 +1,58 @@ ++/* ++ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ */ ++ ++#include <linux/interrupt.h> ++ ++#include <asm/i8259.h> ++ ++#include <loongson.h> ++#include <machine.h> ++ ++int mach_i8259_irq(void) ++{ ++ return i8259_irq(); ++} ++ ++void mach_irq_dispatch(unsigned int pending) ++{ ++ if (pending & CAUSEF_IP7) ++ do_IRQ(LOONGSON_TIMER_IRQ); ++ else if (pending & CAUSEF_IP6) /* perf counter loverflow */ ++ do_IRQ(LOONGSON_PERFCNT_IRQ); ++ else if (pending & CAUSEF_IP5) ++ i8259_irqdispatch(); ++ else if (pending & CAUSEF_IP2) ++ bonito_irqdispatch(); ++ else ++ spurious_interrupt(); ++} ++ ++void __init set_irq_trigger_mode(void) ++{ ++ /* most bonito irq should be level triggered */ ++ LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR | ++ LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES; ++} +diff -Nur linux-2.6.30/arch/mips/loongson/fuloong-2e/reset.c rt4ls/arch/mips/loongson/fuloong-2e/reset.c +--- linux-2.6.30/arch/mips/loongson/fuloong-2e/reset.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/fuloong-2e/reset.c 2009-06-12 16:27:08.786446844 +0200 +@@ -0,0 +1,26 @@ ++/* Board-specific reboot/shutdown routines ++ * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca> ++ * ++ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/delay.h> ++#include <linux/types.h> ++ ++#include <loongson.h> ++ ++void mach_prepare_reboot(void) ++{ ++ LOONGSON_GENCFG &= ~LOONGSON_GENCFG_CPUSELFRESET; ++ LOONGSON_GENCFG |= LOONGSON_GENCFG_CPUSELFRESET; ++} ++ ++void mach_prepare_shutdown(void) ++{ ++} +diff -Nur linux-2.6.30/arch/mips/loongson/fuloong-2f/Makefile rt4ls/arch/mips/loongson/fuloong-2f/Makefile +--- linux-2.6.30/arch/mips/loongson/fuloong-2f/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/fuloong-2f/Makefile 2009-06-12 16:27:08.786446844 +0200 +@@ -0,0 +1,5 @@ ++# ++# Makefile for fuloong-2f ++# ++ ++obj-y += irq.o reset.o +diff -Nur linux-2.6.30/arch/mips/loongson/fuloong-2f/irq.c rt4ls/arch/mips/loongson/fuloong-2f/irq.c +--- linux-2.6.30/arch/mips/loongson/fuloong-2f/irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/fuloong-2f/irq.c 2009-06-12 16:27:08.786446844 +0200 +@@ -0,0 +1,53 @@ ++/* ++ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/interrupt.h> ++ ++#include <loongson.h> ++#include <machine.h> ++ ++int mach_i8259_irq(void) ++{ ++ int irq, isr, imr; ++ ++ irq = -1; ++ ++ if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { ++ imr = inb(0x21) | (inb(0xa1) << 8); ++ isr = inb(0x20) | (inb(0xa0) << 8); ++ isr &= ~0x4; /* irq2 for cascade */ ++ isr &= ~imr; ++ irq = ffs(isr) - 1; ++ } ++ ++ return irq; ++} ++ ++void mach_irq_dispatch(unsigned int pending) ++{ ++ if (pending & CAUSEF_IP7) ++ do_IRQ(LOONGSON_TIMER_IRQ); ++ else if (pending & CAUSEF_IP6) { ++ do_IRQ(LOONGSON_PERFCNT_IRQ); /* Perf counter overflow */ ++ bonito_irqdispatch(); /* North Bridge */ ++ } else if (pending & CAUSEF_IP3) /* CPU UART */ ++ do_IRQ(LOONGSON_UART_IRQ); ++ else if (pending & CAUSEF_IP2) /* South Bridge */ ++ i8259_irqdispatch(); ++ else ++ spurious_interrupt(); ++} ++ ++void __init set_irq_trigger_mode(void) ++{ ++ /* setup cs5536 as high level trigger */ ++ LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1; ++ LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1); ++} +diff -Nur linux-2.6.30/arch/mips/loongson/fuloong-2f/reset.c rt4ls/arch/mips/loongson/fuloong-2f/reset.c +--- linux-2.6.30/arch/mips/loongson/fuloong-2f/reset.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/fuloong-2f/reset.c 2009-06-12 16:27:08.786446844 +0200 +@@ -0,0 +1,65 @@ ++/* Board-specific reboot/shutdown routines ++ * ++ * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca> ++ * ++ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/io.h> ++#include <linux/delay.h> ++#include <linux/types.h> ++ ++#include <loongson.h> ++ ++/* cs5536 is the south bridge used by fuloong2f mini PC */ ++#include <cs5536/cs5536.h> ++ ++void mach_prepare_reboot(void) ++{ ++ /* ++ * reset cpu to full speed, this is needed when enabling cpu frequency ++ * scalling ++ */ ++ LOONGSON_CHIPCFG0 |= 0x7; ++ ++ /* send a reset signal to south bridge. ++ * ++ * NOTE: if enable "Power Management" in kernel, rtl8169 will not reset ++ * normally with this reset operation and it will not work in PMON, but ++ * you can type halt command and then reboot, seems the hardware reset ++ * logic not work normally. ++ */ ++ { ++ u32 hi, lo; ++ _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo); ++ lo |= 0x00000001; ++ _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo); ++ } ++} ++ ++void mach_prepare_shutdown(void) ++{ ++ u32 hi, lo, val; ++ phys_addr_t gpio_base; ++ ++ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo); ++ ++ gpio_base = mips_io_port_base | (lo & 0xff00); ++ ++ /* make cs5536 gpio13 output enable */ ++ val = (readl((u32 *) (gpio_base + GPIOL_OUT_EN)) & ~(1 << (16 + 13))) ++ | (1 << 13); ++ writel(val, (u32 *) (gpio_base + GPIOL_OUT_EN)); ++ mmiowb(); ++ /* make cs5536 gpio13 output low level voltage. */ ++ val = (readl((u32 *) (gpio_base + GPIOL_OUT_VAL)) & ~(1 << (13))) ++ | (1 << (16 + 13)); ++ writel(val, (u32 *) (gpio_base + GPIOL_OUT_VAL)); ++ mmiowb(); ++} +diff -Nur linux-2.6.30/arch/mips/loongson/yeeloong-2f/Makefile rt4ls/arch/mips/loongson/yeeloong-2f/Makefile +--- linux-2.6.30/arch/mips/loongson/yeeloong-2f/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/yeeloong-2f/Makefile 2009-06-12 16:27:08.786446844 +0200 +@@ -0,0 +1,5 @@ ++# ++# Makefile for fuloong-2f ++# ++ ++obj-y += init.o irq.o reset.o +diff -Nur linux-2.6.30/arch/mips/loongson/yeeloong-2f/init.c rt4ls/arch/mips/loongson/yeeloong-2f/init.c +--- linux-2.6.30/arch/mips/loongson/yeeloong-2f/init.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/yeeloong-2f/init.c 2009-06-12 16:27:08.786446844 +0200 +@@ -0,0 +1,81 @@ ++/* ++ * board specific init routines ++ * ++ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/bootmem.h> ++ ++#include <asm/bootinfo.h> ++ ++#include <cs5536/cs5536.h> ++ ++void __init mach_prom_init_cmdline(void) ++{ ++ /* set lpc irq to quiet mode */ ++ _wrmsr(DIVIL_MSR_REG(DIVIL_LEG_IO), 0x00, 0x16000003); ++ ++ /*Emulate post for usb */ ++ _wrmsr(USB_MSR_REG(USB_CONFIG), 0x4, 0xBF000); ++ ++ if (strstr(arcs_cmdline, "no_auto_cmd") == NULL) { ++ unsigned char default_root[50] = "/dev/hda1"; ++ char *pmon_ver, *ec_ver, *p, version[60], ec_version[64]; ++ ++ p = arcs_cmdline; ++ ++ pmon_ver = strstr(arcs_cmdline, "PMON_VER"); ++ if (pmon_ver) { ++ p = strstr(pmon_ver, " "); ++ if (p) ++ *p++ = '\0'; ++ strncpy(version, pmon_ver, 60); ++ } else ++ strncpy(version, "PMON_VER=Unknown", 60); ++ ++ ec_ver = strstr(p, "EC_VER"); ++ if (ec_ver) { ++ p = strstr(ec_ver, " "); ++ if (p) ++ *p = '\0'; ++ strncpy(ec_version, ec_ver, 64); ++ } else ++ strncpy(ec_version, "EC_VER=Unknown", 64); ++ ++ p = strstr(arcs_cmdline, "root="); ++ if (p) { ++ strncpy(default_root, p, sizeof(default_root)); ++ p = strstr(default_root, " "); ++ if (p) ++ *p = '\0'; ++ } ++ ++ memset(arcs_cmdline, 0, sizeof(arcs_cmdline)); ++ strcat(arcs_cmdline, version); ++ strcat(arcs_cmdline, " "); ++ strcat(arcs_cmdline, ec_version); ++ strcat(arcs_cmdline, " "); ++ strcat(arcs_cmdline, default_root); ++ strcat(arcs_cmdline, " console=tty2"); ++ strcat(arcs_cmdline, " quiet"); ++ } ++ ++ /* ++ * automatically pass the vga argument via machtype argument if ++ * vga is not passed: yeeloong-7inch's vga mode is 800x480x24 ++ */ ++ ++ if ((strstr(arcs_cmdline, "vga") == NULL) ++ && (strstr(arcs_cmdline, "machtype") != NULL) ++ && (strstr(arcs_cmdline, "7inch") != NULL)) ++ strcat(arcs_cmdline, " vga=800x480x16"); ++} +diff -Nur linux-2.6.30/arch/mips/loongson/yeeloong-2f/irq.c rt4ls/arch/mips/loongson/yeeloong-2f/irq.c +--- linux-2.6.30/arch/mips/loongson/yeeloong-2f/irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/yeeloong-2f/irq.c 2009-06-12 16:27:08.786446844 +0200 +@@ -0,0 +1,53 @@ ++/* ++ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/interrupt.h> ++ ++#include <loongson.h> ++#include <machine.h> ++ ++int mach_i8259_irq(void) ++{ ++ int irq, isr, imr; ++ ++ irq = -1; ++ ++ if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { ++ imr = inb(0x21) | (inb(0xa1) << 8); ++ isr = inb(0x20) | (inb(0xa0) << 8); ++ isr &= ~0x4; /* irq2 for cascade */ ++ isr &= ~imr; ++ irq = ffs(isr) - 1; ++ } ++ ++ return irq; ++} ++ ++void mach_irq_dispatch(unsigned int pending) ++{ ++ if (pending & CAUSEF_IP7) ++ do_IRQ(LOONGSON_TIMER_IRQ); ++ else if (pending & CAUSEF_IP6) { ++ do_IRQ(LOONGSON_PERFCNT_IRQ); /* Perf counter overflow */ ++ bonito_irqdispatch(); /* North Bridge */ ++ } else if (pending & CAUSEF_IP3) /* CPU UART */ ++ do_IRQ(LOONGSON_UART_IRQ); ++ else if (pending & CAUSEF_IP2) /* South Bridge */ ++ i8259_irqdispatch(); ++ else ++ spurious_interrupt(); ++} ++ ++void __init set_irq_trigger_mode(void) ++{ ++ /* setup cs5536 as high level trigger */ ++ LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1; ++ LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1); ++} +diff -Nur linux-2.6.30/arch/mips/loongson/yeeloong-2f/reset.c rt4ls/arch/mips/loongson/yeeloong-2f/reset.c +--- linux-2.6.30/arch/mips/loongson/yeeloong-2f/reset.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/loongson/yeeloong-2f/reset.c 2009-06-12 16:27:08.786446844 +0200 +@@ -0,0 +1,91 @@ ++/* Board-specific reboot/shutdown routines ++ * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca> ++ * ++ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include <linux/types.h> ++#include <asm/bootinfo.h> ++ ++#include <loongson.h> ++#include <machine.h> ++ ++/* ++ * The following registers are determined by the EC index configuration. ++ * 1, fill the PORT_HIGH as EC register high part. ++ * 2, fill the PORT_LOW as EC register low part. ++ * 3, fill the PORT_DATA as EC register write data or get the data from it. ++ */ ++#define EC_RESET_IO_PORT_HIGH 0x0381 ++#define EC_RESET_IO_PORT_LOW 0x0382 ++#define EC_RESET_IO_PORT_DATA 0x0383 ++#define REG_RESET_HIGH 0xF4 /* reset the machine auto-clear : rd/wr */ ++#define REG_RESET_LOW 0xEC ++#define BIT_RESET_ON (1 << 0) ++ ++/* 7inch yeeloong have the different shutdown hardware logic from 8.9inch */ ++#define EC_SHUTDOWN_IO_PORT_HIGH 0xff2d ++#define EC_SHUTDOWN_IO_PORT_LOW 0xff2e ++#define EC_SHUTDOWN_IO_PORT_DATA 0xff2f ++#define REG_SHUTDOWN_HIGH 0xFC ++#define REG_SHUTDOWN_LOW 0x29 ++#define BIT_SHUTDOWN_ON (1 << 1) ++ ++void mach_prepare_reboot(void) ++{ ++ /* ++ * reset cpu to full speed, this is needed when enabling cpu frequency ++ * scalling ++ */ ++ LOONGSON_CHIPCFG0 |= 0x7; ++ ++ /* sending an reset signal to EC(embedded controller) */ ++ writeb(REG_RESET_HIGH, ++ (u8 *) (mips_io_port_base + EC_RESET_IO_PORT_HIGH)); ++ writeb(REG_RESET_LOW, ++ (u8 *) (mips_io_port_base + EC_RESET_IO_PORT_LOW)); ++ mmiowb(); ++ writeb(BIT_RESET_ON, ++ (u8 *) (mips_io_port_base + EC_RESET_IO_PORT_DATA)); ++ mmiowb(); ++} ++ ++void mach_prepare_shutdown(void) ++{ ++ const char *system_type = get_system_type(); ++ ++ if (strstr(system_type, "8.9inch") != NULL) { ++ /* cpu-gpio0 output low */ ++ LOONGSON_GPIODATA &= ~0x00000001; ++ /* cpu-gpio0 as output */ ++ LOONGSON_GPIOIE &= ~0x00000001; ++ } else if (strstr(system_type, "7inch") != NULL) { ++ u8 val; ++ u64 i; ++ ++ writeb(REG_SHUTDOWN_HIGH, ++ (u8 *) (mips_io_port_base + EC_SHUTDOWN_IO_PORT_HIGH)); ++ writeb(REG_SHUTDOWN_LOW, ++ (u8 *) (mips_io_port_base + EC_SHUTDOWN_IO_PORT_LOW)); ++ mmiowb(); ++ val = ++ readb((u8 *) (mips_io_port_base + ++ EC_SHUTDOWN_IO_PORT_DATA)); ++ writeb(val & (~BIT_SHUTDOWN_ON), ++ (u8 *) (mips_io_port_base + EC_SHUTDOWN_IO_PORT_DATA)); ++ mmiowb(); ++ /* need enough wait here... how many microseconds needs? */ ++ for (i = 0; i < 0x10000; i++) ++ delay(); ++ writeb(val | BIT_SHUTDOWN_ON, ++ (u8 *) (mips_io_port_base + EC_SHUTDOWN_IO_PORT_DATA)); ++ mmiowb(); ++ } else ++ printk(KERN_INFO "you can shutdown the power safely now!\n"); ++} +diff -Nur linux-2.6.30/arch/mips/oprofile/Makefile rt4ls/arch/mips/oprofile/Makefile +--- linux-2.6.30/arch/mips/oprofile/Makefile 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/oprofile/Makefile 2009-06-12 16:27:08.846439406 +0200 +@@ -15,3 +15,4 @@ + oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o + oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o + oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o ++oprofile-$(CONFIG_CPU_LOONGSON2) += op_model_loongson2.o +diff -Nur linux-2.6.30/arch/mips/oprofile/common.c rt4ls/arch/mips/oprofile/common.c +--- linux-2.6.30/arch/mips/oprofile/common.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/oprofile/common.c 2009-06-12 16:27:08.846439406 +0200 +@@ -16,6 +16,7 @@ + + extern struct op_mips_model op_model_mipsxx_ops __attribute__((weak)); + extern struct op_mips_model op_model_rm9000_ops __attribute__((weak)); ++extern struct op_mips_model op_model_loongson2_ops __attribute__((weak)); + + static struct op_mips_model *model; + +@@ -93,6 +94,10 @@ + case CPU_RM9000: + lmodel = &op_model_rm9000_ops; + break; ++ ++ case CPU_LOONGSON2: ++ lmodel = &op_model_loongson2_ops; ++ break; + }; + + if (!lmodel) +diff -Nur linux-2.6.30/arch/mips/oprofile/op_model_loongson2.c rt4ls/arch/mips/oprofile/op_model_loongson2.c +--- linux-2.6.30/arch/mips/oprofile/op_model_loongson2.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/oprofile/op_model_loongson2.c 2009-06-12 16:27:08.846439406 +0200 +@@ -0,0 +1,186 @@ ++/* ++ * Loongson2 performance counter driver for oprofile ++ * ++ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology ++ * Author: Yanhua <yanh@lemote.com> ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ */ ++#include <linux/init.h> ++#include <linux/oprofile.h> ++#include <linux/interrupt.h> ++#include <linux/smp.h> ++#include <linux/spinlock.h> ++#include <linux/proc_fs.h> ++#include <linux/uaccess.h> ++ ++#include <irq.h> ++#include <loongson.h> /* LOONGSON_PERFCNT_IRQ */ ++#include "op_impl.h" ++ ++/* ++ * a patch should be sent to oprofile with the loongson-specific support. ++ * otherwise, the oprofile tool will not recognize this and complain about ++ * "cpu_type 'unset' is not valid". ++ */ ++#define LOONGSON_CPU_TYPE "mips/loongson2" ++ ++#define LOONGSON_COUNTER1_EVENT(event) ((event & 0x0f) << 5) ++#define LOONGSON_COUNTER2_EVENT(event) ((event & 0x0f) << 9) ++ ++#define LOONGSON_PERFCNT_EXL (1UL << 0) ++#define LOONGSON_PERFCNT_KERNEL (1UL << 1) ++#define LOONGSON_PERFCNT_SUPERVISOR (1UL << 2) ++#define LOONGSON_PERFCNT_USER (1UL << 3) ++#define LOONGSON_PERFCNT_INT_EN (1UL << 4) ++#define LOONGSON_PERFCNT_OVERFLOW (1ULL << 31) ++ ++/* Loongson2 performance counter register */ ++#define read_c0_perflo() __read_64bit_c0_register($24, 0) ++#define write_c0_perflo(val) __write_64bit_c0_register($24, 0, val) ++#define read_c0_perfhi() __read_64bit_c0_register($25, 0) ++#define write_c0_perfhi(val) __write_64bit_c0_register($25, 0, val) ++ ++static struct loongson2_register_config { ++ unsigned int ctrl; ++ unsigned long long reset_counter1; ++ unsigned long long reset_counter2; ++ int cnt1_enable, cnt2_enable; ++} reg; ++ ++DEFINE_SPINLOCK(sample_lock); ++ ++static char *oprofid = "LoongsonPerf"; ++static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id); ++/* Compute all of the registers in preparation for enabling profiling. */ ++ ++static void loongson2_reg_setup(struct op_counter_config *cfg) ++{ ++ unsigned int ctrl = 0; ++ ++ reg.reset_counter1 = 0; ++ reg.reset_counter2 = 0; ++ /* Compute the performance counter ctrl word. */ ++ /* For now count kernel and user mode */ ++ if (cfg[0].enabled) { ++ ctrl |= LOONGSON_COUNTER1_EVENT(cfg[0].event) | ++ LOONGSON_PERFCNT_INT_EN; ++ if (cfg[0].kernel) ++ ctrl |= LOONGSON_PERFCNT_KERNEL; ++ if (cfg[0].user) ++ ctrl |= LOONGSON_PERFCNT_USER; ++ reg.reset_counter1 = 0x80000000ULL - cfg[0].count; ++ } ++ ++ if (cfg[1].enabled) { ++ ctrl |= LOONGSON_COUNTER2_EVENT(cfg[1].event) | ++ LOONGSON_PERFCNT_INT_EN; ++ if (cfg[1].kernel) ++ ctrl |= LOONGSON_PERFCNT_KERNEL; ++ if (cfg[1].user) ++ ctrl |= LOONGSON_PERFCNT_USER; ++ reg.reset_counter2 = (0x80000000ULL - cfg[1].count); ++ } ++ ++ if (cfg[0].enabled || cfg[1].enabled) ++ ctrl |= LOONGSON_PERFCNT_EXL; ++ ++ reg.ctrl = ctrl; ++ ++ reg.cnt1_enable = cfg[0].enabled; ++ reg.cnt2_enable = cfg[1].enabled; ++ ++} ++ ++/* Program all of the registers in preparation for enabling profiling. */ ++ ++static void loongson2_cpu_setup(void *args) ++{ ++ uint64_t perfcount; ++ ++ perfcount = (reg.reset_counter2 << 32) | reg.reset_counter1; ++ write_c0_perfhi(perfcount); ++} ++ ++static void loongson2_cpu_start(void *args) ++{ ++ /* Start all counters on current CPU */ ++ if (reg.cnt1_enable || reg.cnt2_enable) ++ write_c0_perflo(reg.ctrl); ++} ++ ++static void loongson2_cpu_stop(void *args) ++{ ++ /* Stop all counters on current CPU */ ++ write_c0_perflo(0); ++ memset(®, 0, sizeof(reg)); ++} ++ ++static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id) ++{ ++ uint64_t counter, counter1, counter2; ++ struct pt_regs *regs = get_irq_regs(); ++ int enabled; ++ unsigned long flags; ++ ++ /* ++ * LOONGSON2 defines two 32-bit performance counters. ++ * To avoid a race updating the registers we need to stop the counters ++ * while we're messing with ++ * them ... ++ */ ++ ++ /* Check whether the irq belongs to me */ ++ enabled = reg.cnt1_enable | reg.cnt2_enable; ++ if (!enabled) ++ return IRQ_NONE; ++ ++ counter = read_c0_perfhi(); ++ counter1 = counter & 0xffffffff; ++ counter2 = counter >> 32; ++ ++ spin_lock_irqsave(&sample_lock, flags); ++ ++ if (counter1 & LOONGSON_PERFCNT_OVERFLOW) { ++ if (reg.cnt1_enable) ++ oprofile_add_sample(regs, 0); ++ counter1 = reg.reset_counter1; ++ } ++ if (counter2 & LOONGSON_PERFCNT_OVERFLOW) { ++ if (reg.cnt2_enable) ++ oprofile_add_sample(regs, 1); ++ counter2 = reg.reset_counter2; ++ } ++ ++ spin_unlock_irqrestore(&sample_lock, flags); ++ ++ write_c0_perfhi((counter2 << 32) | counter1); ++ ++ return IRQ_HANDLED; ++} ++ ++static int __init loongson2_init(void) ++{ ++ return request_irq(LOONGSON_PERFCNT_IRQ, loongson2_perfcount_handler, ++ IRQF_SHARED, "Perfcounter", oprofid); ++} ++ ++static void loongson2_exit(void) ++{ ++ write_c0_perflo(0); ++ free_irq(LOONGSON_PERFCNT_IRQ, oprofid); ++} ++ ++struct op_mips_model op_model_loongson2_ops = { ++ .reg_setup = loongson2_reg_setup, ++ .cpu_setup = loongson2_cpu_setup, ++ .init = loongson2_init, ++ .exit = loongson2_exit, ++ .cpu_start = loongson2_cpu_start, ++ .cpu_stop = loongson2_cpu_stop, ++ .cpu_type = LOONGSON_CPU_TYPE, ++ .num_counters = 2 ++}; +diff -Nur linux-2.6.30/arch/mips/pci/Makefile rt4ls/arch/mips/pci/Makefile +--- linux-2.6.30/arch/mips/pci/Makefile 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/Makefile 2009-06-12 16:27:08.846439406 +0200 +@@ -26,7 +26,9 @@ + obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o + obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o + obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o +-obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o ++obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o ++obj-$(CONFIG_LEMOTE_FULOONG2F) += fixup-lemote2f.o ops-loongson2.o ++obj-$(CONFIG_LEMOTE_YEELOONG2F) += fixup-lemote2f.o ops-loongson2.o + obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o + obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o + obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o +diff -Nur linux-2.6.30/arch/mips/pci/fixup-au1000.c rt4ls/arch/mips/pci/fixup-au1000.c +--- linux-2.6.30/arch/mips/pci/fixup-au1000.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-au1000.c 2009-06-12 16:27:08.846439406 +0200 +@@ -31,7 +31,7 @@ + + extern char irq_tab_alchemy[][5]; + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + return irq_tab_alchemy[slot][pin]; + } +diff -Nur linux-2.6.30/arch/mips/pci/fixup-capcella.c rt4ls/arch/mips/pci/fixup-capcella.c +--- linux-2.6.30/arch/mips/pci/fixup-capcella.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-capcella.c 2009-06-12 16:27:08.846439406 +0200 +@@ -38,7 +38,7 @@ + [14] = { -1, INTA, INTB, INTC, INTD } + }; + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + return irq_tab_capcella[slot][pin]; + } +diff -Nur linux-2.6.30/arch/mips/pci/fixup-cobalt.c rt4ls/arch/mips/pci/fixup-cobalt.c +--- linux-2.6.30/arch/mips/pci/fixup-cobalt.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-cobalt.c 2009-06-12 16:27:08.846439406 +0200 +@@ -175,7 +175,7 @@ + [COBALT_PCICONF_ETH1] = ETH1_IRQ + }; + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + if (cobalt_board_id <= COBALT_BRD_ID_QUBE1) + return irq_tab_qube1[slot]; +diff -Nur linux-2.6.30/arch/mips/pci/fixup-emma2rh.c rt4ls/arch/mips/pci/fixup-emma2rh.c +--- linux-2.6.30/arch/mips/pci/fixup-emma2rh.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-emma2rh.c 2009-06-12 16:27:08.846439406 +0200 +@@ -88,7 +88,7 @@ + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH, + emma2rh_pci_host_fixup); + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + return irq_map[slot][pin]; + } +diff -Nur linux-2.6.30/arch/mips/pci/fixup-excite.c rt4ls/arch/mips/pci/fixup-excite.c +--- linux-2.6.30/arch/mips/pci/fixup-excite.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-excite.c 2009-06-12 16:27:08.846439406 +0200 +@@ -21,7 +21,7 @@ + #include <linux/pci.h> + #include <excite.h> + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + if (pin == 0) + return -1; +diff -Nur linux-2.6.30/arch/mips/pci/fixup-fuloong2e.c rt4ls/arch/mips/pci/fixup-fuloong2e.c +--- linux-2.6.30/arch/mips/pci/fixup-fuloong2e.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/pci/fixup-fuloong2e.c 2009-06-12 16:27:08.846439406 +0200 +@@ -0,0 +1,243 @@ ++/* ++ * fixup-fuloong2e.c ++ * ++ * Copyright (C) 2004 ICT CAS ++ * Author: Li xiaoyu, ICT CAS ++ * lixy@ict.ac.cn ++ * ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ */ ++#include <linux/init.h> ++#include <linux/pci.h> ++ ++#include <loongson.h> ++ ++/* South bridge slot number is set by the pci probe process */ ++static u8 sb_slot = 5; ++ ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ int irq = 0; ++ ++ if (slot == sb_slot) { ++ switch (PCI_FUNC(dev->devfn)) { ++ case 2: ++ irq = 10; ++ break; ++ case 3: ++ irq = 11; ++ break; ++ case 5: ++ irq = 9; ++ break; ++ } ++ } else { ++ irq = LOONGSON_IRQ_BASE + 25 + pin; ++ } ++ return irq; ++ ++} ++ ++/* Do platform specific device initialization at pci_enable_device() time */ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++ return 0; ++} ++ ++static void __init fuloong2e_nec_fixup(struct pci_dev *pdev) ++{ ++ unsigned int val; ++ ++ /* Configues port 1, 2, 3, 4 to be validate*/ ++ pci_read_config_dword(pdev, 0xe0, &val); ++ pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x4); ++ ++ /* System clock is 48-MHz Oscillator. */ ++ pci_write_config_dword(pdev, 0xe4, 1 << 5); ++} ++ ++static void __init fuloong2e_686b_func0_fixup(struct pci_dev *pdev) ++{ ++ unsigned char c; ++ ++ sb_slot = PCI_SLOT(pdev->devfn); ++ ++ printk(KERN_INFO "via686b fix: ISA bridge\n"); ++ ++ /* Enable I/O Recovery time */ ++ pci_write_config_byte(pdev, 0x40, 0x08); ++ ++ /* Enable ISA refresh */ ++ pci_write_config_byte(pdev, 0x41, 0x01); ++ ++ /* disable ISA line buffer */ ++ pci_write_config_byte(pdev, 0x45, 0x00); ++ ++ /* Gate INTR, and flush line buffer */ ++ pci_write_config_byte(pdev, 0x46, 0xe0); ++ ++ /* Disable PCI Delay Transaction, Enable EISA ports 4D0/4D1. */ ++ /* pci_write_config_byte(pdev, 0x47, 0x20); */ ++ ++ /* ++ * enable PCI Delay Transaction, Enable EISA ports 4D0/4D1. ++ * enable time-out timer ++ */ ++ pci_write_config_byte(pdev, 0x47, 0xe6); ++ ++ /* ++ * enable level trigger on pci irqs: 9,10,11,13 ++ * important! without this PCI interrupts won't work ++ */ ++ outb(0x2e, 0x4d1); ++ ++ /* 512 K PCI Decode */ ++ pci_write_config_byte(pdev, 0x48, 0x01); ++ ++ /* Wait for PGNT before grant to ISA Master/DMA */ ++ pci_write_config_byte(pdev, 0x4a, 0x84); ++ ++ /* ++ * Plug'n'Play ++ * ++ * Parallel DRQ 3, Floppy DRQ 2 (default) ++ */ ++ pci_write_config_byte(pdev, 0x50, 0x0e); ++ ++ /* ++ * IRQ Routing for Floppy and Parallel port ++ * ++ * IRQ 6 for floppy, IRQ 7 for parallel port ++ */ ++ pci_write_config_byte(pdev, 0x51, 0x76); ++ ++ /* IRQ Routing for serial ports (take IRQ 3 and 4) */ ++ pci_write_config_byte(pdev, 0x52, 0x34); ++ ++ /* All IRQ's level triggered. */ ++ pci_write_config_byte(pdev, 0x54, 0x00); ++ ++ /* route PIRQA-D irq */ ++ pci_write_config_byte(pdev, 0x55, 0x90); /* bit 7-4, PIRQA */ ++ pci_write_config_byte(pdev, 0x56, 0xba); /* bit 7-4, PIRQC; */ ++ /* 3-0, PIRQB */ ++ pci_write_config_byte(pdev, 0x57, 0xd0); /* bit 7-4, PIRQD */ ++ ++ /* enable function 5/6, audio/modem */ ++ pci_read_config_byte(pdev, 0x85, &c); ++ c &= ~(0x3 << 2); ++ pci_write_config_byte(pdev, 0x85, c); ++ ++ printk(KERN_INFO"via686b fix: ISA bridge done\n"); ++} ++ ++static void __init fuloong2e_686b_func1_fixup(struct pci_dev *pdev) ++{ ++ printk(KERN_INFO"via686b fix: IDE\n"); ++ ++ /* Modify IDE controller setup */ ++ pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 48); ++ pci_write_config_byte(pdev, PCI_COMMAND, ++ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER); ++ pci_write_config_byte(pdev, 0x40, 0x0b); ++ /* legacy mode */ ++ pci_write_config_byte(pdev, 0x42, 0x09); ++ ++#if 1/* play safe, otherwise we may see notebook's usb keyboard lockup */ ++ /* disable read prefetch/write post buffers */ ++ pci_write_config_byte(pdev, 0x41, 0x02); ++ ++ /* use 3/4 as fifo thresh hold */ ++ pci_write_config_byte(pdev, 0x43, 0x0a); ++ pci_write_config_byte(pdev, 0x44, 0x00); ++ ++ pci_write_config_byte(pdev, 0x45, 0x00); ++#else ++ pci_write_config_byte(pdev, 0x41, 0xc2); ++ pci_write_config_byte(pdev, 0x43, 0x35); ++ pci_write_config_byte(pdev, 0x44, 0x1c); ++ ++ pci_write_config_byte(pdev, 0x45, 0x10); ++#endif ++ ++ printk(KERN_INFO"via686b fix: IDE done\n"); ++} ++ ++static void __init fuloong2e_686b_func2_fixup(struct pci_dev *pdev) ++{ ++ /* irq routing */ ++ pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10); ++} ++ ++static void __init fuloong2e_686b_func3_fixup(struct pci_dev *pdev) ++{ ++ /* irq routing */ ++ pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11); ++} ++ ++static void __init fuloong2e_686b_func5_fixup(struct pci_dev *pdev) ++{ ++ unsigned int val; ++ unsigned char c; ++ ++ /* enable IO */ ++ pci_write_config_byte(pdev, PCI_COMMAND, ++ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER); ++ pci_read_config_dword(pdev, 0x4, &val); ++ pci_write_config_dword(pdev, 0x4, val | 1); ++ ++ /* route ac97 IRQ */ ++ pci_write_config_byte(pdev, 0x3c, 9); ++ ++ pci_read_config_byte(pdev, 0x8, &c); ++ ++ /* link control: enable link & SGD PCM output */ ++ pci_write_config_byte(pdev, 0x41, 0xcc); ++ ++ /* disable game port, FM, midi, sb, enable write to reg2c-2f */ ++ pci_write_config_byte(pdev, 0x42, 0x20); ++ ++ /* we are using Avance logic codec */ ++ pci_write_config_word(pdev, 0x2c, 0x1005); ++ pci_write_config_word(pdev, 0x2e, 0x4710); ++ pci_read_config_dword(pdev, 0x2c, &val); ++ ++ pci_write_config_byte(pdev, 0x42, 0x0); ++} ++ ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, ++ fuloong2e_686b_func0_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, ++ fuloong2e_686b_func1_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, ++ fuloong2e_686b_func2_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, ++ fuloong2e_686b_func3_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, ++ fuloong2e_686b_func5_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB, ++ fuloong2e_nec_fixup); +diff -Nur linux-2.6.30/arch/mips/pci/fixup-ip32.c rt4ls/arch/mips/pci/fixup-ip32.c +--- linux-2.6.30/arch/mips/pci/fixup-ip32.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-ip32.c 2009-06-12 16:27:08.850451649 +0200 +@@ -39,7 +39,7 @@ + * irqs. I suppose a device without a pin A will thank us for doing it + * right if there exists such a broken piece of crap. + */ +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + return irq_tab_mace[slot][pin]; + } +diff -Nur linux-2.6.30/arch/mips/pci/fixup-jmr3927.c rt4ls/arch/mips/pci/fixup-jmr3927.c +--- linux-2.6.30/arch/mips/pci/fixup-jmr3927.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-jmr3927.c 2009-06-12 16:27:08.850451649 +0200 +@@ -31,7 +31,7 @@ + #include <asm/txx9/pci.h> + #include <asm/txx9/jmr3927.h> + +-int __init jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init jmr3927_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + unsigned char irq = pin; + +diff -Nur linux-2.6.30/arch/mips/pci/fixup-lemote2f.c rt4ls/arch/mips/pci/fixup-lemote2f.c +--- linux-2.6.30/arch/mips/pci/fixup-lemote2f.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/pci/fixup-lemote2f.c 2009-06-12 16:27:08.850451649 +0200 +@@ -0,0 +1,171 @@ ++/* ++ * Copyright (C) 2008 Lemote Technology ++ * Copyright (C) 2004 ICT CAS ++ * Author: Li xiaoyu, lixy@ict.ac.cn ++ * ++ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology ++ * Author: Fuxin Zhang, zhangfx@lemote.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++#include <linux/init.h> ++#include <linux/pci.h> ++ ++#include <loongson.h> ++#include <cs5536/cs5536.h> ++#include <cs5536/cs5536_pci.h> ++ ++/* PCI interrupt pins ++ * ++ * These should not be changed, or you should consider loongson2f interrupt ++ * register and your pci card dispatch ++ */ ++ ++#define PCIA 4 ++#define PCIB 5 ++#define PCIC 6 ++#define PCID 7 ++ ++/* all the pci device has the PCIA pin, check the datasheet. */ ++static char irq_tab[][5] __initdata = { ++ /* INTA INTB INTC INTD */ ++ {0, 0, 0, 0, 0}, /* 11: Unused */ ++ {0, 0, 0, 0, 0}, /* 12: Unused */ ++ {0, 0, 0, 0, 0}, /* 13: Unused */ ++ {0, 0, 0, 0, 0}, /* 14: Unused */ ++ {0, 0, 0, 0, 0}, /* 15: Unused */ ++ {0, 0, 0, 0, 0}, /* 16: Unused */ ++ {0, PCIA, 0, 0, 0}, /* 17: RTL8110-0 */ ++ {0, PCIB, 0, 0, 0}, /* 18: RTL8110-1 */ ++ {0, PCIC, 0, 0, 0}, /* 19: SiI3114 */ ++ {0, PCID, 0, 0, 0}, /* 20: 3-ports nec usb */ ++ {0, PCIA, PCIB, PCIC, PCID}, /* 21: PCI-SLOT */ ++ {0, 0, 0, 0, 0}, /* 22: Unused */ ++ {0, 0, 0, 0, 0}, /* 23: Unused */ ++ {0, 0, 0, 0, 0}, /* 24: Unused */ ++ {0, 0, 0, 0, 0}, /* 25: Unused */ ++ {0, 0, 0, 0, 0}, /* 26: Unused */ ++ {0, 0, 0, 0, 0}, /* 27: Unused */ ++}; ++ ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ int virq; ++ ++ if ((PCI_SLOT(dev->devfn) != PCI_IDSEL_CS5536) ++ && (PCI_SLOT(dev->devfn) < 32)) { ++ virq = irq_tab[slot][pin]; ++ printk(KERN_INFO "slot: %d, pin: %d, irq: %d\n", slot, pin, ++ virq + LOONGSON_IRQ_BASE); ++ if (virq != 0) ++ return LOONGSON_IRQ_BASE + virq; ++ else ++ return 0; ++ } else if (PCI_SLOT(dev->devfn) == PCI_IDSEL_CS5536) { /* cs5536 */ ++ switch (PCI_FUNC(dev->devfn)) { ++ case 2: ++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, ++ CS5536_IDE_INTR); ++ return 14; /* for IDE */ ++ case 3: ++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, ++ CS5536_ACC_INTR); ++ return 9; /* for AUDIO */ ++ case 4: /* for OHCI */ ++ case 5: /* for EHCI */ ++ case 6: /* for UDC */ ++ case 7: /* for OTG */ ++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, ++ CS5536_USB_INTR); ++ return 11; ++ } ++ return dev->irq; ++ } else { ++ printk(KERN_INFO " strange pci slot number.\n"); ++ return 0; ++ } ++} ++ ++/* Do platform specific device initialization at pci_enable_device() time */ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++ return 0; ++} ++ ++/* CS5536 SPEC. fixup */ ++static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev) ++{ ++ /* the uart1 and uart2 interrupt in PIC is enabled as default */ ++ pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1); ++ pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1); ++ return; ++} ++ ++static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev) ++{ ++ /* setting the mutex pin as IDE function */ ++ pci_write_config_dword(pdev, PCI_IDE_CFG_REG, ++ CS5536_IDE_FLASH_SIGNATURE); ++ return; ++} ++ ++static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev) ++{ ++ u8 val; ++ ++ /* enable the AUDIO interrupt in PIC */ ++ pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1); ++ ++#if 1 ++ pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val); ++ printk(KERN_INFO "cs5536 acc latency 0x%x\n", val); ++ pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0); ++#endif ++ return; ++} ++ ++static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev) ++{ ++ /* enable the OHCI interrupt in PIC */ ++ /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */ ++ pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1); ++ return; ++} ++ ++static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev) ++{ ++ u32 hi, lo; ++ ++ /* Serial short detect enable */ ++ _rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo); ++ _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 2) | (1 << 3), lo); ++ ++ /* setting the USB2.0 micro frame length */ ++ pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000); ++ return; ++} ++ ++static void __init loongson_nec_fixup(struct pci_dev *pdev) ++{ ++ unsigned int val; ++ ++ pci_read_config_dword(pdev, 0xe0, &val); ++ /* Only 2 port be used */ ++ pci_write_config_dword(pdev, 0xe0, (val & ~3) | 0x2); ++} ++ ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, ++ loongson_cs5536_isa_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OHC, ++ loongson_cs5536_ohci_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHC, ++ loongson_cs5536_ehci_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_AUDIO, ++ loongson_cs5536_acc_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE, ++ loongson_cs5536_ide_fixup); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB, ++ loongson_nec_fixup); +diff -Nur linux-2.6.30/arch/mips/pci/fixup-lm2e.c rt4ls/arch/mips/pci/fixup-lm2e.c +--- linux-2.6.30/arch/mips/pci/fixup-lm2e.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-lm2e.c 1970-01-01 01:00:00.000000000 +0100 +@@ -1,242 +0,0 @@ +-/* +- * fixup-lm2e.c +- * +- * Copyright (C) 2004 ICT CAS +- * Author: Li xiaoyu, ICT CAS +- * lixy@ict.ac.cn +- * +- * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology +- * Author: Fuxin Zhang, zhangfx@lemote.com +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License as published by the +- * Free Software Foundation; either version 2 of the License, or (at your +- * option) any later version. +- * +- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED +- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF +- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- * +- * You should have received a copy of the GNU General Public License along +- * with this program; if not, write to the Free Software Foundation, Inc., +- * 675 Mass Ave, Cambridge, MA 02139, USA. +- * +- */ +-#include <linux/init.h> +-#include <linux/pci.h> +-#include <asm/mips-boards/bonito64.h> +- +-/* South bridge slot number is set by the pci probe process */ +-static u8 sb_slot = 5; +- +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +-{ +- int irq = 0; +- +- if (slot == sb_slot) { +- switch (PCI_FUNC(dev->devfn)) { +- case 2: +- irq = 10; +- break; +- case 3: +- irq = 11; +- break; +- case 5: +- irq = 9; +- break; +- } +- } else { +- irq = BONITO_IRQ_BASE + 25 + pin; +- } +- return irq; +- +-} +- +-/* Do platform specific device initialization at pci_enable_device() time */ +-int pcibios_plat_dev_init(struct pci_dev *dev) +-{ +- return 0; +-} +- +-static void __init loongson2e_nec_fixup(struct pci_dev *pdev) +-{ +- unsigned int val; +- +- /* Configues port 1, 2, 3, 4 to be validate*/ +- pci_read_config_dword(pdev, 0xe0, &val); +- pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x4); +- +- /* System clock is 48-MHz Oscillator. */ +- pci_write_config_dword(pdev, 0xe4, 1 << 5); +-} +- +-static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev) +-{ +- unsigned char c; +- +- sb_slot = PCI_SLOT(pdev->devfn); +- +- printk(KERN_INFO "via686b fix: ISA bridge\n"); +- +- /* Enable I/O Recovery time */ +- pci_write_config_byte(pdev, 0x40, 0x08); +- +- /* Enable ISA refresh */ +- pci_write_config_byte(pdev, 0x41, 0x01); +- +- /* disable ISA line buffer */ +- pci_write_config_byte(pdev, 0x45, 0x00); +- +- /* Gate INTR, and flush line buffer */ +- pci_write_config_byte(pdev, 0x46, 0xe0); +- +- /* Disable PCI Delay Transaction, Enable EISA ports 4D0/4D1. */ +- /* pci_write_config_byte(pdev, 0x47, 0x20); */ +- +- /* +- * enable PCI Delay Transaction, Enable EISA ports 4D0/4D1. +- * enable time-out timer +- */ +- pci_write_config_byte(pdev, 0x47, 0xe6); +- +- /* +- * enable level trigger on pci irqs: 9,10,11,13 +- * important! without this PCI interrupts won't work +- */ +- outb(0x2e, 0x4d1); +- +- /* 512 K PCI Decode */ +- pci_write_config_byte(pdev, 0x48, 0x01); +- +- /* Wait for PGNT before grant to ISA Master/DMA */ +- pci_write_config_byte(pdev, 0x4a, 0x84); +- +- /* +- * Plug'n'Play +- * +- * Parallel DRQ 3, Floppy DRQ 2 (default) +- */ +- pci_write_config_byte(pdev, 0x50, 0x0e); +- +- /* +- * IRQ Routing for Floppy and Parallel port +- * +- * IRQ 6 for floppy, IRQ 7 for parallel port +- */ +- pci_write_config_byte(pdev, 0x51, 0x76); +- +- /* IRQ Routing for serial ports (take IRQ 3 and 4) */ +- pci_write_config_byte(pdev, 0x52, 0x34); +- +- /* All IRQ's level triggered. */ +- pci_write_config_byte(pdev, 0x54, 0x00); +- +- /* route PIRQA-D irq */ +- pci_write_config_byte(pdev, 0x55, 0x90); /* bit 7-4, PIRQA */ +- pci_write_config_byte(pdev, 0x56, 0xba); /* bit 7-4, PIRQC; */ +- /* 3-0, PIRQB */ +- pci_write_config_byte(pdev, 0x57, 0xd0); /* bit 7-4, PIRQD */ +- +- /* enable function 5/6, audio/modem */ +- pci_read_config_byte(pdev, 0x85, &c); +- c &= ~(0x3 << 2); +- pci_write_config_byte(pdev, 0x85, c); +- +- printk(KERN_INFO"via686b fix: ISA bridge done\n"); +-} +- +-static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev) +-{ +- printk(KERN_INFO"via686b fix: IDE\n"); +- +- /* Modify IDE controller setup */ +- pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 48); +- pci_write_config_byte(pdev, PCI_COMMAND, +- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | +- PCI_COMMAND_MASTER); +- pci_write_config_byte(pdev, 0x40, 0x0b); +- /* legacy mode */ +- pci_write_config_byte(pdev, 0x42, 0x09); +- +-#if 1/* play safe, otherwise we may see notebook's usb keyboard lockup */ +- /* disable read prefetch/write post buffers */ +- pci_write_config_byte(pdev, 0x41, 0x02); +- +- /* use 3/4 as fifo thresh hold */ +- pci_write_config_byte(pdev, 0x43, 0x0a); +- pci_write_config_byte(pdev, 0x44, 0x00); +- +- pci_write_config_byte(pdev, 0x45, 0x00); +-#else +- pci_write_config_byte(pdev, 0x41, 0xc2); +- pci_write_config_byte(pdev, 0x43, 0x35); +- pci_write_config_byte(pdev, 0x44, 0x1c); +- +- pci_write_config_byte(pdev, 0x45, 0x10); +-#endif +- +- printk(KERN_INFO"via686b fix: IDE done\n"); +-} +- +-static void __init loongson2e_686b_func2_fixup(struct pci_dev *pdev) +-{ +- /* irq routing */ +- pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10); +-} +- +-static void __init loongson2e_686b_func3_fixup(struct pci_dev *pdev) +-{ +- /* irq routing */ +- pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11); +-} +- +-static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev) +-{ +- unsigned int val; +- unsigned char c; +- +- /* enable IO */ +- pci_write_config_byte(pdev, PCI_COMMAND, +- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | +- PCI_COMMAND_MASTER); +- pci_read_config_dword(pdev, 0x4, &val); +- pci_write_config_dword(pdev, 0x4, val | 1); +- +- /* route ac97 IRQ */ +- pci_write_config_byte(pdev, 0x3c, 9); +- +- pci_read_config_byte(pdev, 0x8, &c); +- +- /* link control: enable link & SGD PCM output */ +- pci_write_config_byte(pdev, 0x41, 0xcc); +- +- /* disable game port, FM, midi, sb, enable write to reg2c-2f */ +- pci_write_config_byte(pdev, 0x42, 0x20); +- +- /* we are using Avance logic codec */ +- pci_write_config_word(pdev, 0x2c, 0x1005); +- pci_write_config_word(pdev, 0x2e, 0x4710); +- pci_read_config_dword(pdev, 0x2c, &val); +- +- pci_write_config_byte(pdev, 0x42, 0x0); +-} +- +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, +- loongson2e_686b_func0_fixup); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, +- loongson2e_686b_func1_fixup); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, +- loongson2e_686b_func2_fixup); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, +- loongson2e_686b_func3_fixup); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, +- loongson2e_686b_func5_fixup); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB, +- loongson2e_nec_fixup); +diff -Nur linux-2.6.30/arch/mips/pci/fixup-malta.c rt4ls/arch/mips/pci/fixup-malta.c +--- linux-2.6.30/arch/mips/pci/fixup-malta.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-malta.c 2009-06-12 16:27:08.850451649 +0200 +@@ -36,7 +36,7 @@ + {0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */ + }; + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + int virq; + virq = irq_tab[slot][pin]; +diff -Nur linux-2.6.30/arch/mips/pci/fixup-mpc30x.c rt4ls/arch/mips/pci/fixup-mpc30x.c +--- linux-2.6.30/arch/mips/pci/fixup-mpc30x.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-mpc30x.c 2009-06-12 16:27:08.850451649 +0200 +@@ -34,7 +34,7 @@ + [29] = MQ200_IRQ, + }; + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + if (slot == 30) + return internal_func_irqs[PCI_FUNC(dev->devfn)]; +diff -Nur linux-2.6.30/arch/mips/pci/fixup-pmcmsp.c rt4ls/arch/mips/pci/fixup-pmcmsp.c +--- linux-2.6.30/arch/mips/pci/fixup-pmcmsp.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-pmcmsp.c 2009-06-12 16:27:08.850451649 +0200 +@@ -202,7 +202,7 @@ + * RETURNS: IRQ number + * + ****************************************************************************/ +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + #if !defined(CONFIG_PMC_MSP7120_GW) && !defined(CONFIG_PMC_MSP7120_EVAL) + printk(KERN_WARNING "PCI: unknown board, no PCI IRQs assigned.\n"); +diff -Nur linux-2.6.30/arch/mips/pci/fixup-pnx8550.c rt4ls/arch/mips/pci/fixup-pnx8550.c +--- linux-2.6.30/arch/mips/pci/fixup-pnx8550.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-pnx8550.c 2009-06-12 16:27:08.850451649 +0200 +@@ -45,7 +45,7 @@ + /* nothing to do here */ + } + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + return pnx8550_irq_tab[slot][pin]; + } +diff -Nur linux-2.6.30/arch/mips/pci/fixup-rbtx4927.c rt4ls/arch/mips/pci/fixup-rbtx4927.c +--- linux-2.6.30/arch/mips/pci/fixup-rbtx4927.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-rbtx4927.c 2009-06-12 16:27:08.850451649 +0200 +@@ -36,7 +36,7 @@ + #include <asm/txx9/pci.h> + #include <asm/txx9/rbtx4927.h> + +-int __init rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init rbtx4927_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + unsigned char irq = pin; + +diff -Nur linux-2.6.30/arch/mips/pci/fixup-rbtx4938.c rt4ls/arch/mips/pci/fixup-rbtx4938.c +--- linux-2.6.30/arch/mips/pci/fixup-rbtx4938.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-rbtx4938.c 2009-06-12 16:27:08.854451321 +0200 +@@ -13,7 +13,7 @@ + #include <asm/txx9/pci.h> + #include <asm/txx9/rbtx4938.h> + +-int __init rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init rbtx4938_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + int irq = tx4938_pcic1_map_irq(dev, slot); + +diff -Nur linux-2.6.30/arch/mips/pci/fixup-rc32434.c rt4ls/arch/mips/pci/fixup-rc32434.c +--- linux-2.6.30/arch/mips/pci/fixup-rc32434.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-rc32434.c 2009-06-12 16:27:08.854451321 +0200 +@@ -37,7 +37,7 @@ + {0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3} + }; + +-int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + int irq = 0; + +diff -Nur linux-2.6.30/arch/mips/pci/fixup-sni.c rt4ls/arch/mips/pci/fixup-sni.c +--- linux-2.6.30/arch/mips/pci/fixup-sni.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-sni.c 2009-06-12 16:27:08.854451321 +0200 +@@ -130,7 +130,7 @@ + return (csmsr & 0xa0) == 0x20; + } + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + switch (sni_brd_type) { + case SNI_BRD_PCI_TOWER_CPLUS: +diff -Nur linux-2.6.30/arch/mips/pci/fixup-tb0219.c rt4ls/arch/mips/pci/fixup-tb0219.c +--- linux-2.6.30/arch/mips/pci/fixup-tb0219.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-tb0219.c 2009-06-12 16:27:08.854451321 +0200 +@@ -23,7 +23,7 @@ + + #include <asm/vr41xx/tb0219.h> + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + int irq = -1; + +diff -Nur linux-2.6.30/arch/mips/pci/fixup-tb0226.c rt4ls/arch/mips/pci/fixup-tb0226.c +--- linux-2.6.30/arch/mips/pci/fixup-tb0226.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-tb0226.c 2009-06-12 16:27:08.854451321 +0200 +@@ -23,7 +23,7 @@ + #include <asm/vr41xx/giu.h> + #include <asm/vr41xx/tb0226.h> + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + int irq = -1; + +diff -Nur linux-2.6.30/arch/mips/pci/fixup-tb0287.c rt4ls/arch/mips/pci/fixup-tb0287.c +--- linux-2.6.30/arch/mips/pci/fixup-tb0287.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-tb0287.c 2009-06-12 16:27:08.854451321 +0200 +@@ -22,7 +22,7 @@ + + #include <asm/vr41xx/tb0287.h> + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + unsigned char bus; + int irq = -1; +diff -Nur linux-2.6.30/arch/mips/pci/fixup-wrppmc.c rt4ls/arch/mips/pci/fixup-wrppmc.c +--- linux-2.6.30/arch/mips/pci/fixup-wrppmc.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-wrppmc.c 2009-06-12 16:27:08.854451321 +0200 +@@ -25,7 +25,7 @@ + [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0}, + }; + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + return pci_irq_tab[slot][pin]; + } +diff -Nur linux-2.6.30/arch/mips/pci/fixup-yosemite.c rt4ls/arch/mips/pci/fixup-yosemite.c +--- linux-2.6.30/arch/mips/pci/fixup-yosemite.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/fixup-yosemite.c 2009-06-12 16:27:08.886440592 +0200 +@@ -26,7 +26,7 @@ + #include <linux/init.h> + #include <linux/pci.h> + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + if (pin == 0) + return -1; +diff -Nur linux-2.6.30/arch/mips/pci/ops-bonito64.c rt4ls/arch/mips/pci/ops-bonito64.c +--- linux-2.6.30/arch/mips/pci/ops-bonito64.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/ops-bonito64.c 2009-06-12 16:27:08.890441660 +0200 +@@ -29,20 +29,16 @@ + #define PCI_ACCESS_READ 0 + #define PCI_ACCESS_WRITE 1 + +-#ifdef CONFIG_LEMOTE_FULONG +-#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset)) +-#define ID_SEL_BEGIN 11 +-#else +-#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset)) ++#define CFG_SPACE_REG(offset) \ ++ (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset)) + #define ID_SEL_BEGIN 10 +-#endif + #define MAX_DEV_NUM (31 - ID_SEL_BEGIN) + + + static int bonito64_pcibios_config_access(unsigned char access_type, + struct pci_bus *bus, + unsigned int devfn, int where, +- u32 * data) ++ u32 *data) + { + u32 busnum = bus->number; + u32 addr, type; +@@ -77,10 +73,9 @@ + addrp = CFG_SPACE_REG(addr & 0xffff); + if (access_type == PCI_ACCESS_WRITE) { + writel(cpu_to_le32(*data), addrp); +-#ifndef CONFIG_LEMOTE_FULONG + /* Wait till done */ +- while (BONITO_PCIMSTAT & 0xF); +-#endif ++ while (BONITO_PCIMSTAT & 0xF) ++ ; + } else { + *data = le32_to_cpu(readl(addrp)); + } +@@ -107,7 +102,7 @@ + * read/write a 32bit word and mask/modify the data we actually want. + */ + static int bonito64_pcibios_read(struct pci_bus *bus, unsigned int devfn, +- int where, int size, u32 * val) ++ int where, int size, u32 *val) + { + u32 data = 0; + +@@ -144,7 +139,7 @@ + data = val; + else { + if (bonito64_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, +- where, &data)) ++ where, &data)) + return -1; + + if (size == 1) +diff -Nur linux-2.6.30/arch/mips/pci/ops-loongson2.c rt4ls/arch/mips/pci/ops-loongson2.c +--- linux-2.6.30/arch/mips/pci/ops-loongson2.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/pci/ops-loongson2.c 2009-06-12 16:27:08.890441660 +0200 +@@ -0,0 +1,213 @@ ++/* ++ * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. ++ * All rights reserved. ++ * Authors: Carsten Langgaard <carstenl@mips.com> ++ * Maciej W. Rozycki <macro@mips.com> ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * MIPS boards specific PCI support. ++ */ ++#include <linux/types.h> ++#include <linux/pci.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++ ++#include <loongson.h> ++ ++#ifdef CONFIG_CS5536 ++#include <cs5536/cs5536_pci.h> ++#include <cs5536/cs5536.h> ++#endif ++ ++#define PCI_ACCESS_READ 0 ++#define PCI_ACCESS_WRITE 1 ++ ++#define CFG_SPACE_REG(offset) \ ++ (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset)) ++#define ID_SEL_BEGIN 11 ++#define MAX_DEV_NUM (31 - ID_SEL_BEGIN) ++ ++ ++static int loongson_pcibios_config_access(unsigned char access_type, ++ struct pci_bus *bus, ++ unsigned int devfn, int where, ++ u32 *data) ++{ ++ u32 busnum = bus->number; ++ u32 addr, type; ++ u32 dummy; ++ void *addrp; ++ int device = PCI_SLOT(devfn); ++ int function = PCI_FUNC(devfn); ++ int reg = where & ~3; ++ ++ if (busnum == 0) { ++ /* board-specific part,currently,only fuloong2f,yeeloong2f ++ * use CS5536, fuloong2e use via686b, gdium has no ++ * south bridge ++ */ ++#ifdef CONFIG_CS5536 ++ /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() ++ * to access the regsters 0xf4,0xf8,0xfc, which is bigger than ++ * 0xf0, so, it will not go this branch, but the others. so, ++ * no calling dead loop here. ++ */ ++ if ((PCI_IDSEL_CS5536 == device) && (reg < 0xF0)) { ++ switch (access_type) { ++ case PCI_ACCESS_READ: ++ *data = cs5536_pci_conf_read4(function, reg); ++ break; ++ case PCI_ACCESS_WRITE: ++ cs5536_pci_conf_write4(function, reg, *data); ++ break; ++ } ++ return 0; ++ } ++#endif ++ /* Type 0 configuration for onboard PCI bus */ ++ if (device > MAX_DEV_NUM) ++ return -1; ++ ++ addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg; ++ type = 0; ++ } else { ++ /* Type 1 configuration for offboard PCI bus */ ++ addr = (busnum << 16) | (device << 11) | (function << 8) | reg; ++ type = 0x10000; ++ } ++ ++ /* Clear aborts */ ++ LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \ ++ LOONGSON_PCICMD_MTABORT_CLR; ++ ++ LOONGSON_PCIMAP_CFG = (addr >> 16) | type; ++ ++ /* Flush Bonito register block */ ++ dummy = LOONGSON_PCIMAP_CFG; ++ mmiowb(); ++ ++ addrp = CFG_SPACE_REG(addr & 0xffff); ++ if (access_type == PCI_ACCESS_WRITE) ++ writel(cpu_to_le32(*data), addrp); ++ else ++ *data = le32_to_cpu(readl(addrp)); ++ ++ /* Detect Master/Target abort */ ++ if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR | ++ LOONGSON_PCICMD_MTABORT_CLR)) { ++ /* Error occurred */ ++ ++ /* Clear bits */ ++ LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR | ++ LOONGSON_PCICMD_MTABORT_CLR); ++ ++ return -1; ++ } ++ ++ return 0; ++ ++} ++ ++ ++/* ++ * We can't address 8 and 16 bit words directly. Instead we have to ++ * read/write a 32bit word and mask/modify the data we actually want. ++ */ ++static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 *val) ++{ ++ u32 data = 0; ++ ++ if ((size == 2) && (where & 1)) ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ else if ((size == 4) && (where & 3)) ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ ++ if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, ++ &data)) ++ return -1; ++ ++ if (size == 1) ++ *val = (data >> ((where & 3) << 3)) & 0xff; ++ else if (size == 2) ++ *val = (data >> ((where & 3) << 3)) & 0xffff; ++ else ++ *val = data; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 val) ++{ ++ u32 data = 0; ++ ++ if ((size == 2) && (where & 1)) ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ else if ((size == 4) && (where & 3)) ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ ++ if (size == 4) ++ data = val; ++ else { ++ if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, ++ where, &data)) ++ return -1; ++ ++ if (size == 1) ++ data = (data & ~(0xff << ((where & 3) << 3))) | ++ (val << ((where & 3) << 3)); ++ else if (size == 2) ++ data = (data & ~(0xffff << ((where & 3) << 3))) | ++ (val << ((where & 3) << 3)); ++ } ++ ++ if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, ++ &data)) ++ return -1; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++struct pci_ops loongson_pci_ops = { ++ .read = loongson_pcibios_read, ++ .write = loongson_pcibios_write ++}; ++ ++#ifdef CONFIG_CS5536 ++void _rdmsr(u32 msr, u32 *hi, u32 *lo) ++{ ++ struct pci_bus bus = { ++ .number = PCI_BUS_CS5536 ++ }; ++ u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0); ++ loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); ++ loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo); ++ loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi); ++} ++EXPORT_SYMBOL(_rdmsr); ++ ++void _wrmsr(u32 msr, u32 hi, u32 lo) ++{ ++ struct pci_bus bus = { ++ .number = PCI_BUS_CS5536 ++ }; ++ u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0); ++ loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); ++ loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo); ++ loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi); ++} ++EXPORT_SYMBOL(_wrmsr); ++#endif +diff -Nur linux-2.6.30/arch/mips/pci/pci-bcm1480.c rt4ls/arch/mips/pci/pci-bcm1480.c +--- linux-2.6.30/arch/mips/pci/pci-bcm1480.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/pci-bcm1480.c 2009-06-12 16:27:09.146457490 +0200 +@@ -74,7 +74,7 @@ + *(u32 *)(cfg_space + (addr & ~3)) = data; + } + +-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + if (pin == 0) + return -1; +diff -Nur linux-2.6.30/arch/mips/pci/pci-bcm47xx.c rt4ls/arch/mips/pci/pci-bcm47xx.c +--- linux-2.6.30/arch/mips/pci/pci-bcm47xx.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/pci-bcm47xx.c 2009-06-12 16:27:09.146457490 +0200 +@@ -26,7 +26,7 @@ + #include <linux/pci.h> + #include <linux/ssb/ssb.h> + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + return 0; + } +diff -Nur linux-2.6.30/arch/mips/pci/pci-ip27.c rt4ls/arch/mips/pci/pci-ip27.c +--- linux-2.6.30/arch/mips/pci/pci-ip27.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/pci-ip27.c 2009-06-12 16:27:09.150468058 +0200 +@@ -141,7 +141,7 @@ + * A given PCI device, in general, should be able to intr any of the cpus + * on any one of the hubs connected to its xbow. + */ +-int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + return 0; + } +diff -Nur linux-2.6.30/arch/mips/pci/pci-lasat.c rt4ls/arch/mips/pci/pci-lasat.c +--- linux-2.6.30/arch/mips/pci/pci-lasat.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/pci-lasat.c 2009-06-12 16:27:09.150468058 +0200 +@@ -61,7 +61,7 @@ + #define LASAT_IRQ_PCIC (LASAT_IRQ_BASE + 7) + #define LASAT_IRQ_PCID (LASAT_IRQ_BASE + 8) + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + switch (slot) { + case 1: +diff -Nur linux-2.6.30/arch/mips/pci/pci-sb1250.c rt4ls/arch/mips/pci/pci-sb1250.c +--- linux-2.6.30/arch/mips/pci/pci-sb1250.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/pci-sb1250.c 2009-06-12 16:27:09.150468058 +0200 +@@ -84,7 +84,7 @@ + *(u32 *) (cfg_space + (addr & ~3)) = data; + } + +-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + return dev->irq; + } +diff -Nur linux-2.6.30/arch/mips/pci/pci-tx4938.c rt4ls/arch/mips/pci/pci-tx4938.c +--- linux-2.6.30/arch/mips/pci/pci-tx4938.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/pci-tx4938.c 2009-06-12 16:27:09.154469127 +0200 +@@ -114,7 +114,7 @@ + return pciclk; + } + +-int __init tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot) ++int __init tx4938_pcic1_map_irq(struct pci_dev *dev, u8 slot) + { + if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) { + switch (slot) { +diff -Nur linux-2.6.30/arch/mips/pci/pci-tx4939.c rt4ls/arch/mips/pci/pci-tx4939.c +--- linux-2.6.30/arch/mips/pci/pci-tx4939.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/pci/pci-tx4939.c 2009-06-12 16:27:09.154469127 +0200 +@@ -50,7 +50,7 @@ + ((pciclk + 50000) / 100000) % 10); + } + +-int __init tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot) ++int __init tx4939_pcic1_map_irq(struct pci_dev *dev, u8 slot) + { + if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4939_pcic1ptr) { + switch (slot) { +@@ -70,7 +70,7 @@ + return -1; + } + +-int __init tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init tx4939_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + int irq = tx4939_pcic1_map_irq(dev, slot); + +diff -Nur linux-2.6.30/arch/mips/power/Makefile rt4ls/arch/mips/power/Makefile +--- linux-2.6.30/arch/mips/power/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/power/Makefile 2009-06-12 16:27:09.166460321 +0200 +@@ -0,0 +1 @@ ++obj-$(CONFIG_HIBERNATION) += cpu.o hibernate.o +diff -Nur linux-2.6.30/arch/mips/power/cpu.c rt4ls/arch/mips/power/cpu.c +--- linux-2.6.30/arch/mips/power/cpu.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/power/cpu.c 2009-06-12 16:27:09.170469770 +0200 +@@ -0,0 +1,43 @@ ++/* ++ * Suspend support for mips. ++ * ++ * Distributed under GPLv2 ++ * ++ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology ++ * Author: Hu Hongbing <huhb@lemote.com> ++ * Wu Zhangjin <wuzj@lemote.com> ++ */ ++#include <asm/suspend.h> ++#include <asm/fpu.h> ++#include <asm/dsp.h> ++ ++static u32 saved_status; ++struct pt_regs saved_regs; ++ ++void save_processor_state(void) ++{ ++ saved_status = read_c0_status(); ++ ++ if (is_fpu_owner()) ++ save_fp(current); ++ if (cpu_has_dsp) ++ save_dsp(current); ++} ++ ++void restore_processor_state(void) ++{ ++ write_c0_status(saved_status); ++ ++ if (is_fpu_owner()) ++ restore_fp(current); ++ if (cpu_has_dsp) ++ restore_dsp(current); ++} ++ ++int pfn_is_nosave(unsigned long pfn) ++{ ++ unsigned long nosave_begin_pfn = PFN_DOWN(__pa(&__nosave_begin)); ++ unsigned long nosave_end_pfn = PFN_UP(__pa(&__nosave_end)); ++ ++ return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn); ++} +diff -Nur linux-2.6.30/arch/mips/power/hibernate.S rt4ls/arch/mips/power/hibernate.S +--- linux-2.6.30/arch/mips/power/hibernate.S 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/arch/mips/power/hibernate.S 2009-06-12 16:27:09.170469770 +0200 +@@ -0,0 +1,70 @@ ++/* ++ * Hibernation support for mips - temporary page tables ++ * ++ * Distributed under GPLv2 ++ * ++ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology ++ * Author: Hu Hongbing <huhb@lemote.com> ++ * Wu Zhangjin <wuzj@lemote.com> ++ */ ++#include <asm/asm-offsets.h> ++#include <asm/regdef.h> ++#include <asm/asm.h> ++ ++.text ++LEAF(swsusp_arch_suspend) ++ PTR_LA t0, saved_regs ++ PTR_S ra, PT_R31(t0) ++ PTR_S sp, PT_R29(t0) ++ PTR_S fp, PT_R30(t0) ++ PTR_S gp, PT_R28(t0) ++ PTR_S s0, PT_R16(t0) ++ PTR_S s1, PT_R17(t0) ++ PTR_S s2, PT_R18(t0) ++ PTR_S s3, PT_R19(t0) ++ PTR_S s4, PT_R20(t0) ++ PTR_S s5, PT_R21(t0) ++ PTR_S s6, PT_R22(t0) ++ PTR_S s7, PT_R23(t0) ++ j swsusp_save ++END(swsusp_arch_suspend) ++ ++LEAF(swsusp_arch_resume) ++ PTR_L t0, restore_pblist ++0: ++ PTR_L t1, PBE_ADDRESS(t0) /* source */ ++ PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */ ++ PTR_ADDIU t3, t1, _PAGE_SIZE ++1: ++ REG_L t8, (t1) ++ REG_S t8, (t2) ++ PTR_ADDIU t1, t1, SZREG ++ PTR_ADDIU t2, t2, SZREG ++ bne t1, t3, 1b ++ PTR_L t0, PBE_NEXT(t0) ++ bnez t0, 0b ++ /* flush caches to make sure context is in memory */ ++ PTR_L t0, __flush_cache_all ++ jalr t0 ++ /* flush tlb entries */ ++#ifdef CONFIG_SMP ++ jal flush_tlb_all ++#else ++ jal local_flush_tlb_all ++#endif ++ PTR_LA t0, saved_regs ++ PTR_L ra, PT_R31(t0) ++ PTR_L sp, PT_R29(t0) ++ PTR_L fp, PT_R30(t0) ++ PTR_L gp, PT_R28(t0) ++ PTR_L s0, PT_R16(t0) ++ PTR_L s1, PT_R17(t0) ++ PTR_L s2, PT_R18(t0) ++ PTR_L s3, PT_R19(t0) ++ PTR_L s4, PT_R20(t0) ++ PTR_L s5, PT_R21(t0) ++ PTR_L s6, PT_R22(t0) ++ PTR_L s7, PT_R23(t0) ++ PTR_LI v0, 0x0 ++ jr ra ++END(swsusp_arch_resume) +diff -Nur linux-2.6.30/arch/mips/sibyte/bcm1480/irq.c rt4ls/arch/mips/sibyte/bcm1480/irq.c +--- linux-2.6.30/arch/mips/sibyte/bcm1480/irq.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/sibyte/bcm1480/irq.c 2009-06-12 16:27:09.190461705 +0200 +@@ -116,10 +116,6 @@ + unsigned long flags; + unsigned int irq_dirty; + +- if (cpumask_weight(mask) != 1) { +- printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); +- return; +- } + i = cpumask_first(mask); + + /* Convert logical CPU to physical CPU */ +diff -Nur linux-2.6.30/arch/mips/sibyte/sb1250/irq.c rt4ls/arch/mips/sibyte/sb1250/irq.c +--- linux-2.6.30/arch/mips/sibyte/sb1250/irq.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/sibyte/sb1250/irq.c 2009-06-12 16:27:09.194461656 +0200 +@@ -111,11 +111,6 @@ + + i = cpumask_first(mask); + +- if (cpumask_weight(mask) > 1) { +- printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); +- return; +- } +- + /* Convert logical CPU to physical CPU */ + cpu = cpu_logical_map(i); + +diff -Nur linux-2.6.30/arch/mips/txx9/generic/pci.c rt4ls/arch/mips/txx9/generic/pci.c +--- linux-2.6.30/arch/mips/txx9/generic/pci.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/mips/txx9/generic/pci.c 2009-06-12 16:27:09.214461413 +0200 +@@ -382,7 +382,7 @@ + return 0; + } + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) + { + return txx9_board_vec->pci_map_irq(dev, slot, pin); + } +diff -Nur linux-2.6.30/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c rt4ls/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c +--- linux-2.6.30/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c 2009-06-12 16:27:12.750683917 +0200 +@@ -550,7 +550,7 @@ + return -ENOMEM; + } + for_each_possible_cpu(i) { +- if (!zalloc_cpumask_var_node( ++ if (!alloc_cpumask_var_node( + &per_cpu_ptr(acpi_perf_data, i)->shared_cpu_map, + GFP_KERNEL, cpu_to_node(i))) { + +diff -Nur linux-2.6.30/arch/x86/kernel/cpu/cpufreq/powernow-k7.c rt4ls/arch/x86/kernel/cpu/cpufreq/powernow-k7.c +--- linux-2.6.30/arch/x86/kernel/cpu/cpufreq/powernow-k7.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/x86/kernel/cpu/cpufreq/powernow-k7.c 2009-06-12 16:27:12.758683819 +0200 +@@ -322,7 +322,7 @@ + goto err0; + } + +- if (!zalloc_cpumask_var(&acpi_processor_perf->shared_cpu_map, ++ if (!alloc_cpumask_var(&acpi_processor_perf->shared_cpu_map, + GFP_KERNEL)) { + retval = -ENOMEM; + goto err05; +diff -Nur linux-2.6.30/arch/x86/kernel/cpu/cpufreq/powernow-k8.c rt4ls/arch/x86/kernel/cpu/cpufreq/powernow-k8.c +--- linux-2.6.30/arch/x86/kernel/cpu/cpufreq/powernow-k8.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/x86/kernel/cpu/cpufreq/powernow-k8.c 2009-06-12 16:27:12.758683819 +0200 +@@ -887,7 +887,7 @@ + /* notify BIOS that we exist */ + acpi_processor_notify_smm(THIS_MODULE); + +- if (!zalloc_cpumask_var(&data->acpi_data.shared_cpu_map, GFP_KERNEL)) { ++ if (!alloc_cpumask_var(&data->acpi_data.shared_cpu_map, GFP_KERNEL)) { + printk(KERN_ERR PFX + "unable to alloc powernow_k8_data cpumask\n"); + ret_val = -ENOMEM; +diff -Nur linux-2.6.30/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c rt4ls/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c +--- linux-2.6.30/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c 2009-06-12 16:27:12.758683819 +0200 +@@ -471,7 +471,7 @@ + + if (unlikely(!alloc_cpumask_var(&saved_mask, GFP_KERNEL))) + return -ENOMEM; +- if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL))) { ++ if (unlikely(!alloc_cpumask_var(&covered_cpus, GFP_KERNEL))) { + free_cpumask_var(saved_mask); + return -ENOMEM; + } +diff -Nur linux-2.6.30/arch/x86/kernel/cpu/mcheck/mce_64.c rt4ls/arch/x86/kernel/cpu/mcheck/mce_64.c +--- linux-2.6.30/arch/x86/kernel/cpu/mcheck/mce_64.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/x86/kernel/cpu/mcheck/mce_64.c 2009-06-12 16:27:12.766685398 +0200 +@@ -1163,7 +1163,7 @@ + if (!mce_available(&boot_cpu_data)) + return -EIO; + +- zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL); ++ alloc_cpumask_var(&mce_device_initialized, GFP_KERNEL); + + err = mce_init_banks(); + if (err) +diff -Nur linux-2.6.30/arch/x86/kernel/tlb_uv.c rt4ls/arch/x86/kernel/tlb_uv.c +--- linux-2.6.30/arch/x86/kernel/tlb_uv.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/arch/x86/kernel/tlb_uv.c 2009-06-12 16:27:13.002711263 +0200 +@@ -832,7 +832,7 @@ + return 0; + + for_each_possible_cpu(cur_cpu) +- zalloc_cpumask_var_node(&per_cpu(uv_flush_tlb_mask, cur_cpu), ++ alloc_cpumask_var_node(&per_cpu(uv_flush_tlb_mask, cur_cpu), + GFP_KERNEL, cpu_to_node(cur_cpu)); + + uv_bau_retry_limit = 1; +diff -Nur linux-2.6.30/block/bsg.c rt4ls/block/bsg.c +--- linux-2.6.30/block/bsg.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/block/bsg.c 2009-06-12 16:27:13.226714938 +0200 +@@ -315,7 +315,6 @@ + blk_put_request(rq); + if (next_rq) { + blk_rq_unmap_user(next_rq->bio); +- next_rq->bio = NULL; + blk_put_request(next_rq); + } + return ERR_PTR(ret); +@@ -449,7 +448,6 @@ + hdr->dout_resid = rq->data_len; + hdr->din_resid = rq->next_rq->data_len; + blk_rq_unmap_user(bidi_bio); +- rq->next_rq->bio = NULL; + blk_put_request(rq->next_rq); + } else if (rq_data_dir(rq) == READ) + hdr->din_resid = rq->data_len; +@@ -468,7 +466,6 @@ + blk_rq_unmap_user(bio); + if (rq->cmd != rq->__cmd) + kfree(rq->cmd); +- rq->bio = NULL; + blk_put_request(rq); + + return ret; +diff -Nur linux-2.6.30/drivers/acpi/processor_core.c rt4ls/drivers/acpi/processor_core.c +--- linux-2.6.30/drivers/acpi/processor_core.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/drivers/acpi/processor_core.c 2009-06-12 16:27:13.558736838 +0200 +@@ -844,7 +844,7 @@ + if (!pr) + return -ENOMEM; + +- if (!zalloc_cpumask_var(&pr->throttling.shared_cpu_map, GFP_KERNEL)) { ++ if (!alloc_cpumask_var(&pr->throttling.shared_cpu_map, GFP_KERNEL)) { + kfree(pr); + return -ENOMEM; + } +diff -Nur linux-2.6.30/drivers/char/mxser.c rt4ls/drivers/char/mxser.c +--- linux-2.6.30/drivers/char/mxser.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/drivers/char/mxser.c 2009-06-12 16:27:13.878756104 +0200 +@@ -2711,7 +2711,7 @@ + continue; + + brd = &mxser_boards[m]; +- retval = mxser_get_ISA_conf(ioaddr[b], brd); ++ retval = mxser_get_ISA_conf(!ioaddr[b], brd); + if (retval <= 0) { + brd->info = NULL; + continue; +diff -Nur linux-2.6.30/drivers/cpufreq/cpufreq.c rt4ls/drivers/cpufreq/cpufreq.c +--- linux-2.6.30/drivers/cpufreq/cpufreq.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/drivers/cpufreq/cpufreq.c 2009-06-12 16:27:23.183344589 +0200 +@@ -808,7 +808,7 @@ + ret = -ENOMEM; + goto nomem_out; + } +- if (!zalloc_cpumask_var(&policy->related_cpus, GFP_KERNEL)) { ++ if (!alloc_cpumask_var(&policy->related_cpus, GFP_KERNEL)) { + free_cpumask_var(policy->cpus); + kfree(policy); + ret = -ENOMEM; +diff -Nur linux-2.6.30/drivers/ide/amd74xx.c rt4ls/drivers/ide/amd74xx.c +--- linux-2.6.30/drivers/ide/amd74xx.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/drivers/ide/amd74xx.c 2009-06-12 16:27:31.515864613 +0200 +@@ -23,6 +23,11 @@ + + #define DRV_NAME "amd74xx" + ++static const char *am74xx_quirk_drives[] = { ++ "FUJITSU MHZ2160BH G2", ++ NULL ++}; ++ + enum { + AMD_IDE_CONFIG = 0x41, + AMD_CABLE_DETECT = 0x42, +@@ -112,6 +117,19 @@ + amd_set_drive(drive, XFER_PIO_0 + pio); + } + ++static void amd_quirkproc(ide_drive_t *drive) ++{ ++ const char **list, *m = (char *)&drive->id[ATA_ID_PROD]; ++ ++ for (list = am74xx_quirk_drives; *list != NULL; list++) ++ if (strstr(m, *list) != NULL) { ++ drive->quirk_list = 2; ++ return; ++ } ++ ++ drive->quirk_list = 0; ++} ++ + static void amd7409_cable_detect(struct pci_dev *dev) + { + /* no host side cable detection */ +@@ -186,6 +204,7 @@ + static const struct ide_port_ops amd_port_ops = { + .set_pio_mode = amd_set_pio_mode, + .set_dma_mode = amd_set_drive, ++ .quirkproc = amd_quirkproc, + .cable_detect = amd_cable_detect, + }; + +diff -Nur linux-2.6.30/drivers/md/raid5.c rt4ls/drivers/md/raid5.c +--- linux-2.6.30/drivers/md/raid5.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/drivers/md/raid5.c 2009-06-12 16:27:48.380919207 +0200 +@@ -362,7 +362,7 @@ + + static struct stripe_head * + get_active_stripe(raid5_conf_t *conf, sector_t sector, +- int previous, int noblock, int noquiesce) ++ int previous, int noblock) + { + struct stripe_head *sh; + +@@ -372,7 +372,7 @@ + + do { + wait_event_lock_irq(conf->wait_for_stripe, +- conf->quiesce == 0 || noquiesce, ++ conf->quiesce == 0, + conf->device_lock, /* nothing */); + sh = __find_stripe(conf, sector, conf->generation - previous); + if (!sh) { +@@ -2671,7 +2671,7 @@ + sector_t bn = compute_blocknr(sh, i, 1); + sector_t s = raid5_compute_sector(conf, bn, 0, + &dd_idx, NULL); +- sh2 = get_active_stripe(conf, s, 0, 1, 1); ++ sh2 = get_active_stripe(conf, s, 0, 1); + if (sh2 == NULL) + /* so far only the early blocks of this stripe + * have been requested. When later blocks +@@ -2944,7 +2944,7 @@ + /* Finish reconstruct operations initiated by the expansion process */ + if (sh->reconstruct_state == reconstruct_state_result) { + struct stripe_head *sh2 +- = get_active_stripe(conf, sh->sector, 1, 1, 1); ++ = get_active_stripe(conf, sh->sector, 1, 1); + if (sh2 && test_bit(STRIPE_EXPAND_SOURCE, &sh2->state)) { + /* sh cannot be written until sh2 has been read. + * so arrange for sh to be delayed a little +@@ -3189,7 +3189,7 @@ + + if (s.expanded && test_bit(STRIPE_EXPANDING, &sh->state)) { + struct stripe_head *sh2 +- = get_active_stripe(conf, sh->sector, 1, 1, 1); ++ = get_active_stripe(conf, sh->sector, 1, 1); + if (sh2 && test_bit(STRIPE_EXPAND_SOURCE, &sh2->state)) { + /* sh cannot be written until sh2 has been read. + * so arrange for sh to be delayed a little +@@ -3288,7 +3288,7 @@ + int i; + + rcu_read_lock(); +- for (i = 0; i < conf->raid_disks; i++) { ++ for (i=0; i<mddev->raid_disks; i++) { + mdk_rdev_t *rdev = rcu_dereference(conf->disks[i].rdev); + if (rdev && !test_bit(Faulty, &rdev->flags) && atomic_read(&rdev->nr_pending)) { + struct request_queue *r_queue = bdev_get_queue(rdev->bdev); +@@ -3675,7 +3675,7 @@ + (unsigned long long)logical_sector); + + sh = get_active_stripe(conf, new_sector, previous, +- (bi->bi_rw&RWA_MASK), 0); ++ (bi->bi_rw&RWA_MASK)); + if (sh) { + if (unlikely(previous)) { + /* expansion might have moved on while waiting for a +@@ -3873,7 +3873,7 @@ + for (i = 0; i < reshape_sectors; i += STRIPE_SECTORS) { + int j; + int skipped = 0; +- sh = get_active_stripe(conf, stripe_addr+i, 0, 0, 1); ++ sh = get_active_stripe(conf, stripe_addr+i, 0, 0); + set_bit(STRIPE_EXPANDING, &sh->state); + atomic_inc(&conf->reshape_stripes); + /* If any of this stripe is beyond the end of the old +@@ -3916,13 +3916,13 @@ + raid5_compute_sector(conf, stripe_addr*(new_data_disks), + 1, &dd_idx, NULL); + last_sector = +- raid5_compute_sector(conf, ((stripe_addr+reshape_sectors) ++ raid5_compute_sector(conf, ((stripe_addr+conf->chunk_size/512) + *(new_data_disks) - 1), + 1, &dd_idx, NULL); + if (last_sector >= mddev->dev_sectors) + last_sector = mddev->dev_sectors - 1; + while (first_sector <= last_sector) { +- sh = get_active_stripe(conf, first_sector, 1, 0, 1); ++ sh = get_active_stripe(conf, first_sector, 1, 0); + set_bit(STRIPE_EXPAND_SOURCE, &sh->state); + set_bit(STRIPE_HANDLE, &sh->state); + release_stripe(sh); +@@ -4022,9 +4022,9 @@ + + bitmap_cond_end_sync(mddev->bitmap, sector_nr); + +- sh = get_active_stripe(conf, sector_nr, 0, 1, 0); ++ sh = get_active_stripe(conf, sector_nr, 0, 1); + if (sh == NULL) { +- sh = get_active_stripe(conf, sector_nr, 0, 0, 0); ++ sh = get_active_stripe(conf, sector_nr, 0, 0); + /* make sure we don't swamp the stripe cache if someone else + * is trying to get access + */ +@@ -4034,7 +4034,7 @@ + * We don't need to check the 'failed' flag as when that gets set, + * recovery aborts. + */ +- for (i = 0; i < conf->raid_disks; i++) ++ for (i=0; i<mddev->raid_disks; i++) + if (conf->disks[i].rdev == NULL) + still_degraded = 1; + +@@ -4086,7 +4086,7 @@ + /* already done this stripe */ + continue; + +- sh = get_active_stripe(conf, sector, 0, 1, 0); ++ sh = get_active_stripe(conf, sector, 0, 1); + + if (!sh) { + /* failed to get a stripe - must wait */ +diff -Nur linux-2.6.30/drivers/net/Kconfig rt4ls/drivers/net/Kconfig +--- linux-2.6.30/drivers/net/Kconfig 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/drivers/net/Kconfig 2009-06-12 16:28:08.898195438 +0200 +@@ -2362,6 +2362,13 @@ + Some boards that use the Discovery chipset are the Momenco + Ocelot C and Jaguar ATX and Pegasos II. + ++config TITAN_GE ++ bool "PMC-Sierra TITAN Gigabit Ethernet Support" ++ depends on PMC_YOSEMITE ++ help ++ This enables support for the the integrated ethernet of ++ PMC-Sierra's Titan SoC. ++ + config QLA3XXX + tristate "QLogic QLA3XXX Network Driver Support" + depends on PCI +diff -Nur linux-2.6.30/drivers/net/Makefile rt4ls/drivers/net/Makefile +--- linux-2.6.30/drivers/net/Makefile 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/drivers/net/Makefile 2009-06-12 16:28:08.910193335 +0200 +@@ -137,6 +137,8 @@ + obj-$(CONFIG_QLA3XXX) += qla3xxx.o + obj-$(CONFIG_QLGE) += qlge/ + ++obj-$(CONFIG_TITAN_GE) += titan_mdio.o titan_ge.o ++ + obj-$(CONFIG_PPP) += ppp_generic.o + obj-$(CONFIG_PPP_ASYNC) += ppp_async.o + obj-$(CONFIG_PPP_SYNC_TTY) += ppp_synctty.o +diff -Nur linux-2.6.30/drivers/net/r8169.c rt4ls/drivers/net/r8169.c +--- linux-2.6.30/drivers/net/r8169.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/drivers/net/r8169.c 2009-06-12 16:28:14.650663877 +0200 +@@ -66,6 +66,7 @@ + #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ + #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ + #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ ++#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ + #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ + #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ + +@@ -2356,10 +2357,10 @@ + return cmd; + } + +-static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) ++static void rtl_set_rx_max_size(void __iomem *ioaddr) + { + /* Low hurts. Let's disable the filtering. */ +- RTL_W16(RxMaxSize, rx_buf_sz); ++ RTL_W16(RxMaxSize, 16383); + } + + static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) +@@ -2406,7 +2407,7 @@ + + RTL_W8(EarlyTxThres, EarlyTxThld); + +- rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); ++ rtl_set_rx_max_size(ioaddr); + + if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || + (tp->mac_version == RTL_GIGA_MAC_VER_02) || +@@ -2667,7 +2668,7 @@ + + RTL_W8(EarlyTxThres, EarlyTxThld); + +- rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); ++ rtl_set_rx_max_size(ioaddr); + + tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; + +@@ -2845,7 +2846,7 @@ + + RTL_W8(EarlyTxThres, EarlyTxThld); + +- rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); ++ rtl_set_rx_max_size(ioaddr); + + tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; + +diff -Nur linux-2.6.30/drivers/net/titan_ge.c rt4ls/drivers/net/titan_ge.c +--- linux-2.6.30/drivers/net/titan_ge.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/drivers/net/titan_ge.c 2009-06-12 16:28:16.835950077 +0200 +@@ -0,0 +1,2069 @@ ++/* ++ * drivers/net/titan_ge.c - Driver for Titan ethernet ports ++ * ++ * Copyright (C) 2003 PMC-Sierra Inc. ++ * Author : Manish Lachwani (lachwani@pmc-sierra.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++ ++/* ++ * The MAC unit of the Titan consists of the following: ++ * ++ * -> XDMA Engine to move data to from the memory to the MAC packet FIFO ++ * -> FIFO is where the incoming and outgoing data is placed ++ * -> TRTG is the unit that pulls the data from the FIFO for Tx and pushes ++ * the data into the FIFO for Rx ++ * -> TMAC is the outgoing MAC interface and RMAC is the incoming. ++ * -> AFX is the address filtering block ++ * -> GMII block to communicate with the PHY ++ * ++ * Rx will look like the following: ++ * GMII --> RMAC --> AFX --> TRTG --> Rx FIFO --> XDMA --> CPU memory ++ * ++ * Tx will look like the following: ++ * CPU memory --> XDMA --> Tx FIFO --> TRTG --> TMAC --> GMII ++ * ++ * The Titan driver has support for the following performance features: ++ * -> Rx side checksumming ++ * -> Jumbo Frames ++ * -> Interrupt Coalscing ++ * -> Rx NAPI ++ * -> SKB Recycling ++ * -> Transmit/Receive descriptors in SRAM ++ * -> Fast routing for IP forwarding ++ */ ++ ++#include <linux/dma-mapping.h> ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/sched.h> ++#include <linux/ioport.h> ++#include <linux/interrupt.h> ++#include <linux/slab.h> ++#include <linux/string.h> ++#include <linux/errno.h> ++#include <linux/ip.h> ++#include <linux/init.h> ++#include <linux/in.h> ++#include <linux/platform_device.h> ++#include <linux/netdevice.h> ++#include <linux/etherdevice.h> ++#include <linux/skbuff.h> ++#include <linux/mii.h> ++#include <linux/delay.h> ++#include <linux/skbuff.h> ++#include <linux/prefetch.h> ++ ++/* For MII specifc registers, titan_mdio.h should be included */ ++#include <net/ip.h> ++ ++#include <asm/bitops.h> ++#include <asm/io.h> ++#include <asm/types.h> ++#include <asm/pgtable.h> ++#include <asm/system.h> ++#include <asm/titan_dep.h> ++ ++#include "titan_ge.h" ++#include "titan_mdio.h" ++ ++/* Static Function Declarations */ ++static int titan_ge_eth_open(struct net_device *); ++static void titan_ge_eth_stop(struct net_device *); ++static struct net_device_stats *titan_ge_get_stats(struct net_device *); ++static int titan_ge_init_rx_desc_ring(titan_ge_port_info *, int, int, ++ unsigned long, unsigned long, ++ unsigned long); ++static int titan_ge_init_tx_desc_ring(titan_ge_port_info *, int, ++ unsigned long, unsigned long); ++ ++static int titan_ge_open(struct net_device *); ++static int titan_ge_start_xmit(struct sk_buff *, struct net_device *); ++static int titan_ge_stop(struct net_device *); ++ ++static unsigned long titan_ge_tx_coal(unsigned long, int); ++ ++static void titan_ge_port_reset(unsigned int); ++static int titan_ge_free_tx_queue(titan_ge_port_info *); ++static int titan_ge_rx_task(struct net_device *, titan_ge_port_info *); ++static int titan_ge_port_start(struct net_device *, titan_ge_port_info *); ++ ++static int titan_ge_return_tx_desc(titan_ge_port_info *, int); ++ ++/* ++ * Some configuration for the FIFO and the XDMA channel needs ++ * to be done only once for all the ports. This flag controls ++ * that ++ */ ++static unsigned long config_done; ++ ++/* ++ * One time out of memory flag ++ */ ++static unsigned int oom_flag; ++ ++static int titan_ge_poll(struct net_device *netdev, int *budget); ++ ++static int titan_ge_receive_queue(struct net_device *, unsigned int); ++ ++static struct platform_device *titan_ge_device[3]; ++ ++/* MAC Address */ ++extern unsigned char titan_ge_mac_addr_base[6]; ++ ++unsigned long titan_ge_base; ++static unsigned long titan_ge_sram; ++ ++static char titan_string[] = "titan"; ++ ++/* ++ * The Titan GE has two alignment requirements: ++ * -> skb->data to be cacheline aligned (32 byte) ++ * -> IP header alignment to 16 bytes ++ * ++ * The latter is not implemented. So, that results in an extra copy on ++ * the Rx. This is a big performance hog. For the former case, the ++ * dev_alloc_skb() has been replaced with titan_ge_alloc_skb(). The size ++ * requested is calculated: ++ * ++ * Ethernet Frame Size : 1518 ++ * Ethernet Header : 14 ++ * Future Titan change for IP header alignment : 2 ++ * ++ * Hence, we allocate (1518 + 14 + 2+ 64) = 1580 bytes. For IP header ++ * alignment, we use skb_reserve(). ++ */ ++ ++#define ALIGNED_RX_SKB_ADDR(addr) \ ++ ((((unsigned long)(addr) + (64UL - 1UL)) \ ++ & ~(64UL - 1UL)) - (unsigned long)(addr)) ++ ++#define titan_ge_alloc_skb(__length, __gfp_flags) \ ++({ struct sk_buff *__skb; \ ++ __skb = alloc_skb((__length) + 64, (__gfp_flags)); \ ++ if(__skb) { \ ++ int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \ ++ if(__offset) \ ++ skb_reserve(__skb, __offset); \ ++ } \ ++ __skb; \ ++}) ++ ++/* ++ * Configure the GMII block of the Titan based on what the PHY tells us ++ */ ++static void titan_ge_gmii_config(int port_num) ++{ ++ unsigned int reg_data = 0, phy_reg; ++ int err; ++ ++ err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg); ++ ++ if (err == TITAN_GE_MDIO_ERROR) { ++ printk(KERN_ERR ++ "Could not read PHY control register 0x11 \n"); ++ printk(KERN_ERR ++ "Setting speed to 1000 Mbps and Duplex to Full \n"); ++ ++ return; ++ } ++ ++ err = titan_ge_mdio_write(port_num, TITAN_GE_MDIO_PHY_IE, 0); ++ ++ if (phy_reg & 0x8000) { ++ if (phy_reg & 0x2000) { ++ /* Full Duplex and 1000 Mbps */ ++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE + ++ (port_num << 12)), 0x201); ++ } else { ++ /* Half Duplex and 1000 Mbps */ ++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE + ++ (port_num << 12)), 0x2201); ++ } ++ } ++ if (phy_reg & 0x4000) { ++ if (phy_reg & 0x2000) { ++ /* Full Duplex and 100 Mbps */ ++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE + ++ (port_num << 12)), 0x100); ++ } else { ++ /* Half Duplex and 100 Mbps */ ++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE + ++ (port_num << 12)), 0x2100); ++ } ++ } ++ reg_data = TITAN_GE_READ(TITAN_GE_GMII_CONFIG_GENERAL + ++ (port_num << 12)); ++ reg_data |= 0x3; ++ TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_GENERAL + ++ (port_num << 12)), reg_data); ++} ++ ++/* ++ * Enable the TMAC if it is not ++ */ ++static void titan_ge_enable_tx(unsigned int port_num) ++{ ++ unsigned long reg_data; ++ ++ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)); ++ if (!(reg_data & 0x8000)) { ++ printk("TMAC disabled for port %d!! \n", port_num); ++ ++ reg_data |= 0x0001; /* Enable TMAC */ ++ reg_data |= 0x4000; /* CRC Check Enable */ ++ reg_data |= 0x2000; /* Padding enable */ ++ reg_data |= 0x0800; /* CRC Add enable */ ++ reg_data |= 0x0080; /* PAUSE frame */ ++ ++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + ++ (port_num << 12)), reg_data); ++ } ++} ++ ++/* ++ * Tx Timeout function ++ */ ++static void titan_ge_tx_timeout(struct net_device *netdev) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ ++ printk(KERN_INFO "%s: TX timeout ", netdev->name); ++ printk(KERN_INFO "Resetting card \n"); ++ ++ /* Do the reset outside of interrupt context */ ++ schedule_work(&titan_ge_eth->tx_timeout_task); ++} ++ ++/* ++ * Update the AFX tables for UC and MC for slice 0 only ++ */ ++static void titan_ge_update_afx(titan_ge_port_info * titan_ge_eth) ++{ ++ int port = titan_ge_eth->port_num; ++ unsigned int i; ++ volatile unsigned long reg_data = 0; ++ u8 p_addr[6]; ++ ++ memcpy(p_addr, titan_ge_eth->port_mac_addr, 6); ++ ++ /* Set the MAC address here for TMAC and RMAC */ ++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port << 12)), ++ ((p_addr[5] << 8) | p_addr[4])); ++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port << 12)), ++ ((p_addr[3] << 8) | p_addr[2])); ++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port << 12)), ++ ((p_addr[1] << 8) | p_addr[0])); ++ ++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port << 12)), ++ ((p_addr[5] << 8) | p_addr[4])); ++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port << 12)), ++ ((p_addr[3] << 8) | p_addr[2])); ++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port << 12)), ++ ((p_addr[1] << 8) | p_addr[0])); ++ ++ TITAN_GE_WRITE((0x112c | (port << 12)), 0x1); ++ /* Configure the eight address filters */ ++ for (i = 0; i < 8; i++) { ++ /* Select each of the eight filters */ ++ TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 + ++ (port << 12)), i); ++ ++ /* Configure the match */ ++ reg_data = 0x9; /* Forward Enable Bit */ ++ TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 + ++ (port << 12)), reg_data); ++ ++ /* Finally, AFX Exact Match Address Registers */ ++ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_LOW + (port << 12)), ++ ((p_addr[1] << 8) | p_addr[0])); ++ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_MID + (port << 12)), ++ ((p_addr[3] << 8) | p_addr[2])); ++ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_HIGH + (port << 12)), ++ ((p_addr[5] << 8) | p_addr[4])); ++ ++ /* VLAN id set to 0 */ ++ TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_VID + ++ (port << 12)), 0); ++ } ++} ++ ++/* ++ * Actual Routine to reset the adapter when the timeout occurred ++ */ ++static void titan_ge_tx_timeout_task(struct net_device *netdev) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ int port = titan_ge_eth->port_num; ++ ++ printk("Titan GE: Transmit timed out. Resetting ... \n"); ++ ++ /* Dump debug info */ ++ printk(KERN_ERR "TRTG cause : %x \n", ++ TITAN_GE_READ(0x100c + (port << 12))); ++ ++ /* Fix this for the other ports */ ++ printk(KERN_ERR "FIFO cause : %x \n", TITAN_GE_READ(0x482c)); ++ printk(KERN_ERR "IE cause : %x \n", TITAN_GE_READ(0x0040)); ++ printk(KERN_ERR "XDMA GDI ERROR : %x \n", ++ TITAN_GE_READ(0x5008 + (port << 8))); ++ printk(KERN_ERR "CHANNEL ERROR: %x \n", ++ TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT ++ + (port << 8))); ++ ++ netif_device_detach(netdev); ++ titan_ge_port_reset(titan_ge_eth->port_num); ++ titan_ge_port_start(netdev, titan_ge_eth); ++ netif_device_attach(netdev); ++} ++ ++/* ++ * Change the MTU of the Ethernet Device ++ */ ++static int titan_ge_change_mtu(struct net_device *netdev, int new_mtu) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ unsigned long flags; ++ ++ if ((new_mtu > 9500) || (new_mtu < 64)) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&titan_ge_eth->lock, flags); ++ ++ netdev->mtu = new_mtu; ++ ++ /* Now we have to reopen the interface so that SKBs with the new ++ * size will be allocated */ ++ ++ if (netif_running(netdev)) { ++ titan_ge_eth_stop(netdev); ++ ++ if (titan_ge_eth_open(netdev) != TITAN_OK) { ++ printk(KERN_ERR ++ "%s: Fatal error on opening device\n", ++ netdev->name); ++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags); ++ return -1; ++ } ++ } ++ ++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags); ++ return 0; ++} ++ ++/* ++ * Titan Gbe Interrupt Handler. All the three ports send interrupt to one line ++ * only. Once an interrupt is triggered, figure out the port and then check ++ * the channel. ++ */ ++static irqreturn_t titan_ge_int_handler(int irq, void *dev_id) ++{ ++ struct net_device *netdev = (struct net_device *) dev_id; ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ unsigned int port_num = titan_ge_eth->port_num; ++ unsigned int reg_data; ++ unsigned int eth_int_cause_error = 0, is; ++ unsigned long eth_int_cause1; ++ int err = 0; ++#ifdef CONFIG_SMP ++ unsigned long eth_int_cause2; ++#endif ++ ++ /* Ack the CPU interrupt */ ++ switch (port_num) { ++ case 0: ++ is = OCD_READ(RM9000x2_OCD_INTP0STATUS1); ++ OCD_WRITE(RM9000x2_OCD_INTP0CLEAR1, is); ++ ++#ifdef CONFIG_SMP ++ is = OCD_READ(RM9000x2_OCD_INTP1STATUS1); ++ OCD_WRITE(RM9000x2_OCD_INTP1CLEAR1, is); ++#endif ++ break; ++ ++ case 1: ++ is = OCD_READ(RM9000x2_OCD_INTP0STATUS0); ++ OCD_WRITE(RM9000x2_OCD_INTP0CLEAR0, is); ++ ++#ifdef CONFIG_SMP ++ is = OCD_READ(RM9000x2_OCD_INTP1STATUS0); ++ OCD_WRITE(RM9000x2_OCD_INTP1CLEAR0, is); ++#endif ++ break; ++ ++ case 2: ++ is = OCD_READ(RM9000x2_OCD_INTP0STATUS4); ++ OCD_WRITE(RM9000x2_OCD_INTP0CLEAR4, is); ++ ++#ifdef CONFIG_SMP ++ is = OCD_READ(RM9000x2_OCD_INTP1STATUS4); ++ OCD_WRITE(RM9000x2_OCD_INTP1CLEAR4, is); ++#endif ++ } ++ ++ eth_int_cause1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A); ++#ifdef CONFIG_SMP ++ eth_int_cause2 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_B); ++#endif ++ ++ /* Spurious interrupt */ ++#ifdef CONFIG_SMP ++ if ( (eth_int_cause1 == 0) && (eth_int_cause2 == 0)) { ++#else ++ if (eth_int_cause1 == 0) { ++#endif ++ eth_int_cause_error = TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT + ++ (port_num << 8)); ++ ++ if (eth_int_cause_error == 0) ++ return IRQ_NONE; ++ } ++ ++ /* Handle Tx first. No need to ack interrupts */ ++#ifdef CONFIG_SMP ++ if ( (eth_int_cause1 & 0x20202) || ++ (eth_int_cause2 & 0x20202) ) ++#else ++ if (eth_int_cause1 & 0x20202) ++#endif ++ titan_ge_free_tx_queue(titan_ge_eth); ++ ++ /* Handle the Rx next */ ++#ifdef CONFIG_SMP ++ if ( (eth_int_cause1 & 0x10101) || ++ (eth_int_cause2 & 0x10101)) { ++#else ++ if (eth_int_cause1 & 0x10101) { ++#endif ++ if (netif_rx_schedule_prep(netdev)) { ++ unsigned int ack; ++ ++ ack = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE); ++ /* Disable Tx and Rx both */ ++ if (port_num == 0) ++ ack &= ~(0x3); ++ if (port_num == 1) ++ ack &= ~(0x300); ++ ++ if (port_num == 2) ++ ack &= ~(0x30000); ++ ++ /* Interrupts have been disabled */ ++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, ack); ++ ++ __netif_rx_schedule(netdev); ++ } ++ } ++ ++ /* Handle error interrupts */ ++ if (eth_int_cause_error && (eth_int_cause_error != 0x2)) { ++ printk(KERN_ERR ++ "XDMA Channel Error : %x on port %d\n", ++ eth_int_cause_error, port_num); ++ ++ printk(KERN_ERR ++ "XDMA GDI Hardware error : %x on port %d\n", ++ TITAN_GE_READ(0x5008 + (port_num << 8)), port_num); ++ ++ printk(KERN_ERR ++ "XDMA currently has %d Rx descriptors \n", ++ TITAN_GE_READ(0x5048 + (port_num << 8))); ++ ++ printk(KERN_ERR ++ "XDMA currently has prefetcted %d Rx descriptors \n", ++ TITAN_GE_READ(0x505c + (port_num << 8))); ++ ++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT + ++ (port_num << 8)), eth_int_cause_error); ++ } ++ ++ /* ++ * PHY interrupt to inform abt the changes. Reading the ++ * PHY Status register will clear the interrupt ++ */ ++ if ((!(eth_int_cause1 & 0x30303)) && ++ (eth_int_cause_error == 0)) { ++ err = ++ titan_ge_mdio_read(port_num, ++ TITAN_GE_MDIO_PHY_IS, ®_data); ++ ++ if (reg_data & 0x0400) { ++ /* Link status change */ ++ titan_ge_mdio_read(port_num, ++ TITAN_GE_MDIO_PHY_STATUS, ®_data); ++ if (!(reg_data & 0x0400)) { ++ /* Link is down */ ++ netif_carrier_off(netdev); ++ netif_stop_queue(netdev); ++ } else { ++ /* Link is up */ ++ netif_carrier_on(netdev); ++ netif_wake_queue(netdev); ++ ++ /* Enable the queue */ ++ titan_ge_enable_tx(port_num); ++ } ++ } ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Multicast and Promiscuous mode set. The ++ * set_multi entry point is called whenever the ++ * multicast address list or the network interface ++ * flags are updated. ++ */ ++static void titan_ge_set_multi(struct net_device *netdev) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ unsigned int port_num = titan_ge_eth->port_num; ++ unsigned long reg_data; ++ ++ reg_data = TITAN_GE_READ(TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 + ++ (port_num << 12)); ++ ++ if (netdev->flags & IFF_PROMISC) { ++ reg_data |= 0x2; ++ } ++ else if (netdev->flags & IFF_ALLMULTI) { ++ reg_data |= 0x01; ++ reg_data |= 0x400; /* Use the 64-bit Multicast Hash bin */ ++ } ++ else { ++ reg_data = 0x2; ++ } ++ ++ TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 + ++ (port_num << 12)), reg_data); ++ if (reg_data & 0x01) { ++ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_LOW + ++ (port_num << 12)), 0xffff); ++ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDLOW + ++ (port_num << 12)), 0xffff); ++ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDHI + ++ (port_num << 12)), 0xffff); ++ TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_HI + ++ (port_num << 12)), 0xffff); ++ } ++} ++ ++/* ++ * Open the network device ++ */ ++static int titan_ge_open(struct net_device *netdev) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ unsigned int port_num = titan_ge_eth->port_num; ++ unsigned int irq = TITAN_ETH_PORT_IRQ - port_num; ++ int retval; ++ ++ retval = request_irq(irq, titan_ge_int_handler, ++ SA_INTERRUPT | SA_SAMPLE_RANDOM , netdev->name, netdev); ++ ++ if (retval != 0) { ++ printk(KERN_ERR "Cannot assign IRQ number to TITAN GE \n"); ++ return -1; ++ } ++ ++ netdev->irq = irq; ++ printk(KERN_INFO "Assigned IRQ %d to port %d\n", irq, port_num); ++ ++ spin_lock_irq(&(titan_ge_eth->lock)); ++ ++ if (titan_ge_eth_open(netdev) != TITAN_OK) { ++ spin_unlock_irq(&(titan_ge_eth->lock)); ++ printk("%s: Error opening interface \n", netdev->name); ++ free_irq(netdev->irq, netdev); ++ return -EBUSY; ++ } ++ ++ spin_unlock_irq(&(titan_ge_eth->lock)); ++ ++ return 0; ++} ++ ++/* ++ * Allocate the SKBs for the Rx ring. Also used ++ * for refilling the queue ++ */ ++static int titan_ge_rx_task(struct net_device *netdev, ++ titan_ge_port_info *titan_ge_port) ++{ ++ struct device *device = &titan_ge_device[titan_ge_port->port_num]->dev; ++ volatile titan_ge_rx_desc *rx_desc; ++ struct sk_buff *skb; ++ int rx_used_desc; ++ int count = 0; ++ ++ while (titan_ge_port->rx_ring_skbs < titan_ge_port->rx_ring_size) { ++ ++ /* First try to get the skb from the recycler */ ++#ifdef TITAN_GE_JUMBO_FRAMES ++ skb = titan_ge_alloc_skb(TITAN_GE_JUMBO_BUFSIZE, GFP_ATOMIC); ++#else ++ skb = titan_ge_alloc_skb(TITAN_GE_STD_BUFSIZE, GFP_ATOMIC); ++#endif ++ if (unlikely(!skb)) { ++ /* OOM, set the flag */ ++ printk("OOM \n"); ++ oom_flag = 1; ++ break; ++ } ++ count++; ++ skb->dev = netdev; ++ ++ titan_ge_port->rx_ring_skbs++; ++ ++ rx_used_desc = titan_ge_port->rx_used_desc_q; ++ rx_desc = &(titan_ge_port->rx_desc_area[rx_used_desc]); ++ ++#ifdef TITAN_GE_JUMBO_FRAMES ++ rx_desc->buffer_addr = dma_map_single(device, skb->data, ++ TITAN_GE_JUMBO_BUFSIZE - 2, DMA_FROM_DEVICE); ++#else ++ rx_desc->buffer_addr = dma_map_single(device, skb->data, ++ TITAN_GE_STD_BUFSIZE - 2, DMA_FROM_DEVICE); ++#endif ++ ++ titan_ge_port->rx_skb[rx_used_desc] = skb; ++ rx_desc->cmd_sts = TITAN_GE_RX_BUFFER_OWNED; ++ ++ titan_ge_port->rx_used_desc_q = ++ (rx_used_desc + 1) % TITAN_GE_RX_QUEUE; ++ } ++ ++ return count; ++} ++ ++/* ++ * Actual init of the Tital GE port. There is one register for ++ * the channel configuration ++ */ ++static void titan_port_init(struct net_device *netdev, ++ titan_ge_port_info * titan_ge_eth) ++{ ++ unsigned long reg_data; ++ ++ titan_ge_port_reset(titan_ge_eth->port_num); ++ ++ /* First reset the TMAC */ ++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG); ++ reg_data |= 0x80000000; ++ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data); ++ ++ udelay(30); ++ ++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG); ++ reg_data &= ~(0xc0000000); ++ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data); ++ ++ /* Now reset the RMAC */ ++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG); ++ reg_data |= 0x00080000; ++ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data); ++ ++ udelay(30); ++ ++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG); ++ reg_data &= ~(0x000c0000); ++ TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data); ++} ++ ++/* ++ * Start the port. All the hardware specific configuration ++ * for the XDMA, Tx FIFO, Rx FIFO, TMAC, RMAC, TRTG and AFX ++ * go here ++ */ ++static int titan_ge_port_start(struct net_device *netdev, ++ titan_ge_port_info * titan_port) ++{ ++ volatile unsigned long reg_data, reg_data1; ++ int port_num = titan_port->port_num; ++ int count = 0; ++ unsigned long reg_data_1; ++ ++ if (config_done == 0) { ++ reg_data = TITAN_GE_READ(0x0004); ++ reg_data |= 0x100; ++ TITAN_GE_WRITE(0x0004, reg_data); ++ ++ reg_data &= ~(0x100); ++ TITAN_GE_WRITE(0x0004, reg_data); ++ ++ /* Turn on GMII/MII mode and turn off TBI mode */ ++ reg_data = TITAN_GE_READ(TITAN_GE_TSB_CTRL_1); ++ reg_data |= 0x00000700; ++ reg_data &= ~(0x00800000); /* Fencing */ ++ ++ TITAN_GE_WRITE(0x000c, 0x00001100); ++ ++ TITAN_GE_WRITE(TITAN_GE_TSB_CTRL_1, reg_data); ++ ++ /* Set the CPU Resource Limit register */ ++ TITAN_GE_WRITE(0x00f8, 0x8); ++ ++ /* Be conservative when using the BIU buffers */ ++ TITAN_GE_WRITE(0x0068, 0x4); ++ } ++ ++ titan_port->tx_threshold = 0; ++ titan_port->rx_threshold = 0; ++ ++ /* We need to write the descriptors for Tx and Rx */ ++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_TX_DESC + (port_num << 8)), ++ (unsigned long) titan_port->tx_dma); ++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_RX_DESC + (port_num << 8)), ++ (unsigned long) titan_port->rx_dma); ++ ++ if (config_done == 0) { ++ /* Step 1: XDMA config */ ++ reg_data = TITAN_GE_READ(TITAN_GE_XDMA_CONFIG); ++ reg_data &= ~(0x80000000); /* clear reset */ ++ reg_data |= 0x1 << 29; /* sparse tx descriptor spacing */ ++ reg_data |= 0x1 << 28; /* sparse rx descriptor spacing */ ++ reg_data |= (0x1 << 23) | (0x1 << 24); /* Descriptor Coherency */ ++ reg_data |= (0x1 << 21) | (0x1 << 22); /* Data Coherency */ ++ TITAN_GE_WRITE(TITAN_GE_XDMA_CONFIG, reg_data); ++ } ++ ++ /* IR register for the XDMA */ ++ reg_data = TITAN_GE_READ(TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8)); ++ reg_data |= 0x80068000; /* No Rx_OOD */ ++ TITAN_GE_WRITE((TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8)), reg_data); ++ ++ /* Start the Tx and Rx XDMA controller */ ++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + (port_num << 8)); ++ reg_data &= 0x4fffffff; /* Clear tx reset */ ++ reg_data &= 0xfff4ffff; /* Clear rx reset */ ++ ++#ifdef TITAN_GE_JUMBO_FRAMES ++ reg_data |= 0xa0 | 0x30030000; ++#else ++ reg_data |= 0x40 | 0x20030000; ++#endif ++ ++#ifndef CONFIG_SMP ++ reg_data &= ~(0x10); ++ reg_data |= 0x0f; /* All of the packet */ ++#endif ++ ++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + (port_num << 8)), reg_data); ++ ++ /* Rx desc count */ ++ count = titan_ge_rx_task(netdev, titan_port); ++ TITAN_GE_WRITE((0x5048 + (port_num << 8)), count); ++ count = TITAN_GE_READ(0x5048 + (port_num << 8)); ++ ++ udelay(30); ++ ++ /* ++ * Step 2: Configure the SDQPF, i.e. FIFO ++ */ ++ if (config_done == 0) { ++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL); ++ reg_data = 0x1; ++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data); ++ reg_data &= ~(0x1); ++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data); ++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL); ++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data); ++ ++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL); ++ reg_data = 0x1; ++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data); ++ reg_data &= ~(0x1); ++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data); ++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL); ++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data); ++ } ++ /* ++ * Enable RX FIFO 0, 4 and 8 ++ */ ++ if (port_num == 0) { ++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_0); ++ ++ reg_data |= 0x100000; ++ reg_data |= (0xff << 10); ++ ++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data); ++ /* ++ * BAV2,BAV and DAV settings for the Rx FIFO ++ */ ++ reg_data1 = TITAN_GE_READ(0x4844); ++ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1); ++ TITAN_GE_WRITE(0x4844, reg_data1); ++ ++ reg_data &= ~(0x00100000); ++ reg_data |= 0x200000; ++ ++ TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data); ++ ++ reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_0); ++ reg_data |= 0x100000; ++ ++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data); ++ ++ reg_data |= (0xff << 10); ++ ++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data); ++ ++ /* ++ * BAV2, BAV and DAV settings for the Tx FIFO ++ */ ++ reg_data1 = TITAN_GE_READ(0x4944); ++ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10); ++ ++ TITAN_GE_WRITE(0x4944, reg_data1); ++ ++ reg_data &= ~(0x00100000); ++ reg_data |= 0x200000; ++ ++ TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data); ++ ++ } ++ ++ if (port_num == 1) { ++ reg_data = TITAN_GE_READ(0x4870); ++ ++ reg_data |= 0x100000; ++ reg_data |= (0xff << 10) | (0xff + 1); ++ ++ TITAN_GE_WRITE(0x4870, reg_data); ++ /* ++ * BAV2,BAV and DAV settings for the Rx FIFO ++ */ ++ reg_data1 = TITAN_GE_READ(0x4874); ++ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1); ++ TITAN_GE_WRITE(0x4874, reg_data1); ++ ++ reg_data &= ~(0x00100000); ++ reg_data |= 0x200000; ++ ++ TITAN_GE_WRITE(0x4870, reg_data); ++ ++ reg_data = TITAN_GE_READ(0x494c); ++ reg_data |= 0x100000; ++ ++ TITAN_GE_WRITE(0x494c, reg_data); ++ reg_data |= (0xff << 10) | (0xff + 1); ++ TITAN_GE_WRITE(0x494c, reg_data); ++ ++ /* ++ * BAV2, BAV and DAV settings for the Tx FIFO ++ */ ++ reg_data1 = TITAN_GE_READ(0x4950); ++ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10); ++ ++ TITAN_GE_WRITE(0x4950, reg_data1); ++ ++ reg_data &= ~(0x00100000); ++ reg_data |= 0x200000; ++ ++ TITAN_GE_WRITE(0x494c, reg_data); ++ } ++ ++ /* ++ * Titan 1.2 revision does support port #2 ++ */ ++ if (port_num == 2) { ++ /* ++ * Put the descriptors in the SRAM ++ */ ++ reg_data = TITAN_GE_READ(0x48a0); ++ ++ reg_data |= 0x100000; ++ reg_data |= (0xff << 10) | (2*(0xff + 1)); ++ ++ TITAN_GE_WRITE(0x48a0, reg_data); ++ /* ++ * BAV2,BAV and DAV settings for the Rx FIFO ++ */ ++ reg_data1 = TITAN_GE_READ(0x48a4); ++ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1); ++ TITAN_GE_WRITE(0x48a4, reg_data1); ++ ++ reg_data &= ~(0x00100000); ++ reg_data |= 0x200000; ++ ++ TITAN_GE_WRITE(0x48a0, reg_data); ++ ++ reg_data = TITAN_GE_READ(0x4958); ++ reg_data |= 0x100000; ++ ++ TITAN_GE_WRITE(0x4958, reg_data); ++ reg_data |= (0xff << 10) | (2*(0xff + 1)); ++ TITAN_GE_WRITE(0x4958, reg_data); ++ ++ /* ++ * BAV2, BAV and DAV settings for the Tx FIFO ++ */ ++ reg_data1 = TITAN_GE_READ(0x495c); ++ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10); ++ ++ TITAN_GE_WRITE(0x495c, reg_data1); ++ ++ reg_data &= ~(0x00100000); ++ reg_data |= 0x200000; ++ ++ TITAN_GE_WRITE(0x4958, reg_data); ++ } ++ ++ if (port_num == 2) { ++ reg_data = TITAN_GE_READ(0x48a0); ++ ++ reg_data |= 0x100000; ++ reg_data |= (0xff << 10) | (2*(0xff + 1)); ++ ++ TITAN_GE_WRITE(0x48a0, reg_data); ++ /* ++ * BAV2,BAV and DAV settings for the Rx FIFO ++ */ ++ reg_data1 = TITAN_GE_READ(0x48a4); ++ reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1); ++ TITAN_GE_WRITE(0x48a4, reg_data1); ++ ++ reg_data &= ~(0x00100000); ++ reg_data |= 0x200000; ++ ++ TITAN_GE_WRITE(0x48a0, reg_data); ++ ++ reg_data = TITAN_GE_READ(0x4958); ++ reg_data |= 0x100000; ++ ++ TITAN_GE_WRITE(0x4958, reg_data); ++ reg_data |= (0xff << 10) | (2*(0xff + 1)); ++ TITAN_GE_WRITE(0x4958, reg_data); ++ ++ /* ++ * BAV2, BAV and DAV settings for the Tx FIFO ++ */ ++ reg_data1 = TITAN_GE_READ(0x495c); ++ reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10); ++ ++ TITAN_GE_WRITE(0x495c, reg_data1); ++ ++ reg_data &= ~(0x00100000); ++ reg_data |= 0x200000; ++ ++ TITAN_GE_WRITE(0x4958, reg_data); ++ } ++ ++ /* ++ * Step 3: TRTG block enable ++ */ ++ reg_data = TITAN_GE_READ(TITAN_GE_TRTG_CONFIG + (port_num << 12)); ++ ++ /* ++ * This is the 1.2 revision of the chip. It has fix for the ++ * IP header alignment. Now, the IP header begins at an ++ * aligned address and this wont need an extra copy in the ++ * driver. This performance drawback existed in the previous ++ * versions of the silicon ++ */ ++ reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12)); ++ reg_data_1 |= 0x40000000; ++ TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); ++ ++ reg_data_1 |= 0x04000000; ++ TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); ++ ++ mdelay(5); ++ ++ reg_data_1 &= ~(0x04000000); ++ TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1); ++ ++ mdelay(5); ++ ++ reg_data |= 0x0001; ++ TITAN_GE_WRITE((TITAN_GE_TRTG_CONFIG + (port_num << 12)), reg_data); ++ ++ /* ++ * Step 4: Start the Tx activity ++ */ ++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_2 + (port_num << 12)), 0xe197); ++#ifdef TITAN_GE_JUMBO_FRAMES ++ TITAN_GE_WRITE((0x1258 + (port_num << 12)), 0x4000); ++#endif ++ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)); ++ reg_data |= 0x0001; /* Enable TMAC */ ++ reg_data |= 0x6c70; /* PAUSE also set */ ++ ++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)), reg_data); ++ ++ udelay(30); ++ ++ /* Destination Address drop bit */ ++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_2 + (port_num << 12)); ++ reg_data |= 0x218; /* DA_DROP bit and pause */ ++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_2 + (port_num << 12)), reg_data); ++ ++ TITAN_GE_WRITE((0x1218 + (port_num << 12)), 0x3); ++ ++#ifdef TITAN_GE_JUMBO_FRAMES ++ TITAN_GE_WRITE((0x1208 + (port_num << 12)), 0x4000); ++#endif ++ /* Start the Rx activity */ ++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)); ++ reg_data |= 0x0001; /* RMAC Enable */ ++ reg_data |= 0x0010; /* CRC Check enable */ ++ reg_data |= 0x0040; /* Min Frame check enable */ ++ reg_data |= 0x4400; /* Max Frame check enable */ ++ ++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data); ++ ++ udelay(30); ++ ++ /* ++ * Enable the Interrupts for Tx and Rx ++ */ ++ reg_data1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE); ++ ++ if (port_num == 0) { ++ reg_data1 |= 0x3; ++#ifdef CONFIG_SMP ++ TITAN_GE_WRITE(0x0038, 0x003); ++#else ++ TITAN_GE_WRITE(0x0038, 0x303); ++#endif ++ } ++ ++ if (port_num == 1) { ++ reg_data1 |= 0x300; ++ } ++ ++ if (port_num == 2) ++ reg_data1 |= 0x30000; ++ ++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1); ++ TITAN_GE_WRITE(0x003c, 0x300); ++ ++ if (config_done == 0) { ++ TITAN_GE_WRITE(0x0024, 0x04000024); /* IRQ vector */ ++ TITAN_GE_WRITE(0x0020, 0x000fb000); /* INTMSG base */ ++ } ++ ++ /* Priority */ ++ reg_data = TITAN_GE_READ(0x1038 + (port_num << 12)); ++ reg_data &= ~(0x00f00000); ++ TITAN_GE_WRITE((0x1038 + (port_num << 12)), reg_data); ++ ++ /* Step 5: GMII config */ ++ titan_ge_gmii_config(port_num); ++ ++ if (config_done == 0) { ++ TITAN_GE_WRITE(0x1a80, 0); ++ config_done = 1; ++ } ++ ++ return TITAN_OK; ++} ++ ++/* ++ * Function to queue the packet for the Ethernet device ++ */ ++static void titan_ge_tx_queue(titan_ge_port_info * titan_ge_eth, ++ struct sk_buff * skb) ++{ ++ struct device *device = &titan_ge_device[titan_ge_eth->port_num]->dev; ++ unsigned int curr_desc = titan_ge_eth->tx_curr_desc_q; ++ volatile titan_ge_tx_desc *tx_curr; ++ int port_num = titan_ge_eth->port_num; ++ ++ tx_curr = &(titan_ge_eth->tx_desc_area[curr_desc]); ++ tx_curr->buffer_addr = ++ dma_map_single(device, skb->data, skb_headlen(skb), ++ DMA_TO_DEVICE); ++ ++ titan_ge_eth->tx_skb[curr_desc] = (struct sk_buff *) skb; ++ tx_curr->buffer_len = skb_headlen(skb); ++ ++ /* Last descriptor enables interrupt and changes ownership */ ++ tx_curr->cmd_sts = 0x1 | (1 << 15) | (1 << 5); ++ ++ /* Kick the XDMA to start the transfer from memory to the FIFO */ ++ TITAN_GE_WRITE((0x5044 + (port_num << 8)), 0x1); ++ ++ /* Current descriptor updated */ ++ titan_ge_eth->tx_curr_desc_q = (curr_desc + 1) % TITAN_GE_TX_QUEUE; ++ ++ /* Prefetch the next descriptor */ ++ prefetch((const void *) ++ &titan_ge_eth->tx_desc_area[titan_ge_eth->tx_curr_desc_q]); ++} ++ ++/* ++ * Actually does the open of the Ethernet device ++ */ ++static int titan_ge_eth_open(struct net_device *netdev) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ unsigned int port_num = titan_ge_eth->port_num; ++ struct device *device = &titan_ge_device[port_num]->dev; ++ unsigned long reg_data; ++ unsigned int phy_reg; ++ int err = 0; ++ ++ /* Stop the Rx activity */ ++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)); ++ reg_data &= ~(0x00000001); ++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data); ++ ++ /* Clear the port interrupts */ ++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT + (port_num << 8)), 0x0); ++ ++ if (config_done == 0) { ++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0); ++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_B, 0); ++ } ++ ++ /* Set the MAC Address */ ++ memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6); ++ ++ if (config_done == 0) ++ titan_port_init(netdev, titan_ge_eth); ++ ++ titan_ge_update_afx(titan_ge_eth); ++ ++ /* Allocate the Tx ring now */ ++ titan_ge_eth->tx_ring_skbs = 0; ++ titan_ge_eth->tx_ring_size = TITAN_GE_TX_QUEUE; ++ ++ /* Allocate space in the SRAM for the descriptors */ ++ titan_ge_eth->tx_desc_area = (titan_ge_tx_desc *) ++ (titan_ge_sram + TITAN_TX_RING_BYTES * port_num); ++ titan_ge_eth->tx_dma = TITAN_SRAM_BASE + TITAN_TX_RING_BYTES * port_num; ++ ++ if (!titan_ge_eth->tx_desc_area) { ++ printk(KERN_ERR ++ "%s: Cannot allocate Tx Ring (size %d bytes) for port %d\n", ++ netdev->name, TITAN_TX_RING_BYTES, port_num); ++ return -ENOMEM; ++ } ++ ++ memset(titan_ge_eth->tx_desc_area, 0, titan_ge_eth->tx_desc_area_size); ++ ++ /* Now initialize the Tx descriptor ring */ ++ titan_ge_init_tx_desc_ring(titan_ge_eth, ++ titan_ge_eth->tx_ring_size, ++ (unsigned long) titan_ge_eth->tx_desc_area, ++ (unsigned long) titan_ge_eth->tx_dma); ++ ++ /* Allocate the Rx ring now */ ++ titan_ge_eth->rx_ring_size = TITAN_GE_RX_QUEUE; ++ titan_ge_eth->rx_ring_skbs = 0; ++ ++ titan_ge_eth->rx_desc_area = ++ (titan_ge_rx_desc *)(titan_ge_sram + 0x1000 + TITAN_RX_RING_BYTES * port_num); ++ ++ titan_ge_eth->rx_dma = TITAN_SRAM_BASE + 0x1000 + TITAN_RX_RING_BYTES * port_num; ++ ++ if (!titan_ge_eth->rx_desc_area) { ++ printk(KERN_ERR "%s: Cannot allocate Rx Ring (size %d bytes)\n", ++ netdev->name, TITAN_RX_RING_BYTES); ++ ++ printk(KERN_ERR "%s: Freeing previously allocated TX queues...", ++ netdev->name); ++ ++ dma_free_coherent(device, titan_ge_eth->tx_desc_area_size, ++ (void *) titan_ge_eth->tx_desc_area, ++ titan_ge_eth->tx_dma); ++ ++ return -ENOMEM; ++ } ++ ++ memset(titan_ge_eth->rx_desc_area, 0, titan_ge_eth->rx_desc_area_size); ++ ++ /* Now initialize the Rx ring */ ++#ifdef TITAN_GE_JUMBO_FRAMES ++ if ((titan_ge_init_rx_desc_ring ++ (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_JUMBO_BUFSIZE, ++ (unsigned long) titan_ge_eth->rx_desc_area, 0, ++ (unsigned long) titan_ge_eth->rx_dma)) == 0) ++#else ++ if ((titan_ge_init_rx_desc_ring ++ (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_STD_BUFSIZE, ++ (unsigned long) titan_ge_eth->rx_desc_area, 0, ++ (unsigned long) titan_ge_eth->rx_dma)) == 0) ++#endif ++ panic("%s: Error initializing RX Ring\n", netdev->name); ++ ++ /* Fill the Rx ring with the SKBs */ ++ titan_ge_port_start(netdev, titan_ge_eth); ++ ++ /* ++ * Check if Interrupt Coalscing needs to be turned on. The ++ * values specified in the register is multiplied by ++ * (8 x 64 nanoseconds) to determine when an interrupt should ++ * be sent to the CPU. ++ */ ++ ++ if (TITAN_GE_TX_COAL) { ++ titan_ge_eth->tx_int_coal = ++ titan_ge_tx_coal(TITAN_GE_TX_COAL, port_num); ++ } ++ ++ err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg); ++ if (err == TITAN_GE_MDIO_ERROR) { ++ printk(KERN_ERR ++ "Could not read PHY control register 0x11 \n"); ++ return TITAN_ERROR; ++ } ++ if (!(phy_reg & 0x0400)) { ++ netif_carrier_off(netdev); ++ netif_stop_queue(netdev); ++ return TITAN_ERROR; ++ } else { ++ netif_carrier_on(netdev); ++ netif_start_queue(netdev); ++ } ++ ++ return TITAN_OK; ++} ++ ++/* ++ * Queue the packet for Tx. Currently no support for zero copy, ++ * checksum offload and Scatter Gather. The chip does support ++ * Scatter Gather only. But, that wont help here since zero copy ++ * requires support for Tx checksumming also. ++ */ ++int titan_ge_start_xmit(struct sk_buff *skb, struct net_device *netdev) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ unsigned long flags; ++ struct net_device_stats *stats; ++//printk("titan_ge_start_xmit\n"); ++ ++ stats = &titan_ge_eth->stats; ++ spin_lock_irqsave(&titan_ge_eth->lock, flags); ++ ++ if ((TITAN_GE_TX_QUEUE - titan_ge_eth->tx_ring_skbs) <= ++ (skb_shinfo(skb)->nr_frags + 1)) { ++ netif_stop_queue(netdev); ++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags); ++ printk(KERN_ERR "Tx OOD \n"); ++ return 1; ++ } ++ ++ titan_ge_tx_queue(titan_ge_eth, skb); ++ titan_ge_eth->tx_ring_skbs++; ++ ++ if (TITAN_GE_TX_QUEUE <= (titan_ge_eth->tx_ring_skbs + 4)) { ++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags); ++ titan_ge_free_tx_queue(titan_ge_eth); ++ spin_lock_irqsave(&titan_ge_eth->lock, flags); ++ } ++ ++ stats->tx_bytes += skb->len; ++ stats->tx_packets++; ++ ++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags); ++ ++ netdev->trans_start = jiffies; ++ ++ return 0; ++} ++ ++/* ++ * Actually does the Rx. Rx side checksumming supported. ++ */ ++static int titan_ge_rx(struct net_device *netdev, int port_num, ++ titan_ge_port_info * titan_ge_port, ++ titan_ge_packet * packet) ++{ ++ int rx_curr_desc, rx_used_desc; ++ volatile titan_ge_rx_desc *rx_desc; ++ ++ rx_curr_desc = titan_ge_port->rx_curr_desc_q; ++ rx_used_desc = titan_ge_port->rx_used_desc_q; ++ ++ if (((rx_curr_desc + 1) % TITAN_GE_RX_QUEUE) == rx_used_desc) ++ return TITAN_ERROR; ++ ++ rx_desc = &(titan_ge_port->rx_desc_area[rx_curr_desc]); ++ ++ if (rx_desc->cmd_sts & TITAN_GE_RX_BUFFER_OWNED) ++ return TITAN_ERROR; ++ ++ packet->skb = titan_ge_port->rx_skb[rx_curr_desc]; ++ packet->len = (rx_desc->cmd_sts & 0x7fff); ++ ++ /* ++ * At this point, we dont know if the checksumming ++ * actually helps relieve CPU. So, keep it for ++ * port 0 only ++ */ ++ packet->checksum = ntohs((rx_desc->buffer & 0xffff0000) >> 16); ++ packet->cmd_sts = rx_desc->cmd_sts; ++ ++ titan_ge_port->rx_curr_desc_q = (rx_curr_desc + 1) % TITAN_GE_RX_QUEUE; ++ ++ /* Prefetch the next descriptor */ ++ prefetch((const void *) ++ &titan_ge_port->rx_desc_area[titan_ge_port->rx_curr_desc_q + 1]); ++ ++ return TITAN_OK; ++} ++ ++/* ++ * Free the Tx queue of the used SKBs ++ */ ++static int titan_ge_free_tx_queue(titan_ge_port_info *titan_ge_eth) ++{ ++ unsigned long flags; ++ ++ /* Take the lock */ ++ spin_lock_irqsave(&(titan_ge_eth->lock), flags); ++ ++ while (titan_ge_return_tx_desc(titan_ge_eth, titan_ge_eth->port_num) == 0) ++ if (titan_ge_eth->tx_ring_skbs != 1) ++ titan_ge_eth->tx_ring_skbs--; ++ ++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags); ++ ++ return TITAN_OK; ++} ++ ++/* ++ * Threshold beyond which we do the cleaning of ++ * Tx queue and new allocation for the Rx ++ * queue ++ */ ++#define TX_THRESHOLD 4 ++#define RX_THRESHOLD 10 ++ ++/* ++ * Receive the packets and send it to the kernel. ++ */ ++static int titan_ge_receive_queue(struct net_device *netdev, unsigned int max) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ unsigned int port_num = titan_ge_eth->port_num; ++ titan_ge_packet packet; ++ struct net_device_stats *stats; ++ struct sk_buff *skb; ++ unsigned long received_packets = 0; ++ unsigned int ack; ++ ++ stats = &titan_ge_eth->stats; ++ ++ while ((--max) ++ && (titan_ge_rx(netdev, port_num, titan_ge_eth, &packet) == TITAN_OK)) { ++ skb = (struct sk_buff *) packet.skb; ++ ++ titan_ge_eth->rx_ring_skbs--; ++ ++ if (--titan_ge_eth->rx_work_limit < 0) ++ break; ++ received_packets++; ++ ++ stats->rx_packets++; ++ stats->rx_bytes += packet.len; ++ ++ if ((packet.cmd_sts & TITAN_GE_RX_PERR) || ++ (packet.cmd_sts & TITAN_GE_RX_OVERFLOW_ERROR) || ++ (packet.cmd_sts & TITAN_GE_RX_TRUNC) || ++ (packet.cmd_sts & TITAN_GE_RX_CRC_ERROR)) { ++ stats->rx_dropped++; ++ dev_kfree_skb_any(skb); ++ ++ continue; ++ } ++ /* ++ * Either support fast path or slow path. Decision ++ * making can really slow down the performance. The ++ * idea is to cut down the number of checks and improve ++ * the fastpath. ++ */ ++ ++ skb_put(skb, packet.len - 2); ++ ++ /* ++ * Increment data pointer by two since thats where ++ * the MAC starts ++ */ ++ skb_reserve(skb, 2); ++ skb->protocol = eth_type_trans(skb, netdev); ++ netif_receive_skb(skb); ++ ++ if (titan_ge_eth->rx_threshold > RX_THRESHOLD) { ++ ack = titan_ge_rx_task(netdev, titan_ge_eth); ++ TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack); ++ titan_ge_eth->rx_threshold = 0; ++ } else ++ titan_ge_eth->rx_threshold++; ++ ++ if (titan_ge_eth->tx_threshold > TX_THRESHOLD) { ++ titan_ge_eth->tx_threshold = 0; ++ titan_ge_free_tx_queue(titan_ge_eth); ++ } ++ else ++ titan_ge_eth->tx_threshold++; ++ ++ } ++ return received_packets; ++} ++ ++ ++/* ++ * Enable the Rx side interrupts ++ */ ++static void titan_ge_enable_int(unsigned int port_num, ++ titan_ge_port_info *titan_ge_eth, ++ struct net_device *netdev) ++{ ++ unsigned long reg_data = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE); ++ ++ if (port_num == 0) ++ reg_data |= 0x3; ++ if (port_num == 1) ++ reg_data |= 0x300; ++ if (port_num == 2) ++ reg_data |= 0x30000; ++ ++ /* Re-enable interrupts */ ++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data); ++} ++ ++/* ++ * Main function to handle the polling for Rx side NAPI. ++ * Receive interrupts have been disabled at this point. ++ * The poll schedules the transmit followed by receive. ++ */ ++static int titan_ge_poll(struct net_device *netdev, int *budget) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ int port_num = titan_ge_eth->port_num; ++ int work_done = 0; ++ unsigned long flags, status; ++ ++ titan_ge_eth->rx_work_limit = *budget; ++ if (titan_ge_eth->rx_work_limit > netdev->quota) ++ titan_ge_eth->rx_work_limit = netdev->quota; ++ ++ do { ++ /* Do the transmit cleaning work here */ ++ titan_ge_free_tx_queue(titan_ge_eth); ++ ++ /* Ack the Rx interrupts */ ++ if (port_num == 0) ++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x3); ++ if (port_num == 1) ++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x300); ++ if (port_num == 2) ++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x30000); ++ ++ work_done += titan_ge_receive_queue(netdev, 0); ++ ++ /* Out of quota and there is work to be done */ ++ if (titan_ge_eth->rx_work_limit < 0) ++ goto not_done; ++ ++ /* Receive alloc_skb could lead to OOM */ ++ if (oom_flag == 1) { ++ oom_flag = 0; ++ goto oom; ++ } ++ ++ status = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A); ++ } while (status & 0x30300); ++ ++ /* If we are here, then no more interrupts to process */ ++ goto done; ++ ++not_done: ++ *budget -= work_done; ++ netdev->quota -= work_done; ++ return 1; ++ ++oom: ++ printk(KERN_ERR "OOM \n"); ++ netif_rx_complete(netdev); ++ return 0; ++ ++done: ++ /* ++ * No more packets on the poll list. Turn the interrupts ++ * back on and we should be able to catch the new ++ * packets in the interrupt handler ++ */ ++ if (!work_done) ++ work_done = 1; ++ ++ *budget -= work_done; ++ netdev->quota -= work_done; ++ ++ spin_lock_irqsave(&titan_ge_eth->lock, flags); ++ ++ /* Remove us from the poll list */ ++ netif_rx_complete(netdev); ++ ++ /* Re-enable interrupts */ ++ titan_ge_enable_int(port_num, titan_ge_eth, netdev); ++ ++ spin_unlock_irqrestore(&titan_ge_eth->lock, flags); ++ ++ return 0; ++} ++ ++/* ++ * Close the network device ++ */ ++int titan_ge_stop(struct net_device *netdev) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ ++ spin_lock_irq(&(titan_ge_eth->lock)); ++ titan_ge_eth_stop(netdev); ++ free_irq(netdev->irq, netdev); ++ spin_unlock_irq(&titan_ge_eth->lock); ++ ++ return TITAN_OK; ++} ++ ++/* ++ * Free the Tx ring ++ */ ++static void titan_ge_free_tx_rings(struct net_device *netdev) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ unsigned int port_num = titan_ge_eth->port_num; ++ unsigned int curr; ++ unsigned long reg_data; ++ ++ /* Stop the Tx DMA */ ++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + ++ (port_num << 8)); ++ reg_data |= 0xc0000000; ++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + ++ (port_num << 8)), reg_data); ++ ++ /* Disable the TMAC */ ++ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + ++ (port_num << 12)); ++ reg_data &= ~(0x00000001); ++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + ++ (port_num << 12)), reg_data); ++ ++ for (curr = 0; ++ (titan_ge_eth->tx_ring_skbs) && (curr < TITAN_GE_TX_QUEUE); ++ curr++) { ++ if (titan_ge_eth->tx_skb[curr]) { ++ dev_kfree_skb(titan_ge_eth->tx_skb[curr]); ++ titan_ge_eth->tx_ring_skbs--; ++ } ++ } ++ ++ if (titan_ge_eth->tx_ring_skbs != 0) ++ printk ++ ("%s: Error on Tx descriptor free - could not free %d" ++ " descriptors\n", netdev->name, ++ titan_ge_eth->tx_ring_skbs); ++ ++#ifndef TITAN_RX_RING_IN_SRAM ++ dma_free_coherent(&titan_ge_device[port_num]->dev, ++ titan_ge_eth->tx_desc_area_size, ++ (void *) titan_ge_eth->tx_desc_area, ++ titan_ge_eth->tx_dma); ++#endif ++} ++ ++/* ++ * Free the Rx ring ++ */ ++static void titan_ge_free_rx_rings(struct net_device *netdev) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ unsigned int port_num = titan_ge_eth->port_num; ++ unsigned int curr; ++ unsigned long reg_data; ++ ++ /* Stop the Rx DMA */ ++ reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + ++ (port_num << 8)); ++ reg_data |= 0x000c0000; ++ TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + ++ (port_num << 8)), reg_data); ++ ++ /* Disable the RMAC */ ++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + ++ (port_num << 12)); ++ reg_data &= ~(0x00000001); ++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + ++ (port_num << 12)), reg_data); ++ ++ for (curr = 0; ++ titan_ge_eth->rx_ring_skbs && (curr < TITAN_GE_RX_QUEUE); ++ curr++) { ++ if (titan_ge_eth->rx_skb[curr]) { ++ dev_kfree_skb(titan_ge_eth->rx_skb[curr]); ++ titan_ge_eth->rx_ring_skbs--; ++ } ++ } ++ ++ if (titan_ge_eth->rx_ring_skbs != 0) ++ printk(KERN_ERR ++ "%s: Error in freeing Rx Ring. %d skb's still" ++ " stuck in RX Ring - ignoring them\n", netdev->name, ++ titan_ge_eth->rx_ring_skbs); ++ ++#ifndef TITAN_RX_RING_IN_SRAM ++ dma_free_coherent(&titan_ge_device[port_num]->dev, ++ titan_ge_eth->rx_desc_area_size, ++ (void *) titan_ge_eth->rx_desc_area, ++ titan_ge_eth->rx_dma); ++#endif ++} ++ ++/* ++ * Actually does the stop of the Ethernet device ++ */ ++static void titan_ge_eth_stop(struct net_device *netdev) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ ++ netif_stop_queue(netdev); ++ ++ titan_ge_port_reset(titan_ge_eth->port_num); ++ ++ titan_ge_free_tx_rings(netdev); ++ titan_ge_free_rx_rings(netdev); ++ ++ /* Disable the Tx and Rx Interrupts for all channels */ ++ TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, 0x0); ++} ++ ++/* ++ * Update the MAC address. Note that we have to write the ++ * address in three station registers, 16 bits each. And this ++ * has to be done for TMAC and RMAC ++ */ ++static void titan_ge_update_mac_address(struct net_device *netdev) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ unsigned int port_num = titan_ge_eth->port_num; ++ u8 p_addr[6]; ++ ++ memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6); ++ memcpy(p_addr, netdev->dev_addr, 6); ++ ++ /* Update the Address Filtering Match tables */ ++ titan_ge_update_afx(titan_ge_eth); ++ ++ printk("Station MAC : %d %d %d %d %d %d \n", ++ p_addr[5], p_addr[4], p_addr[3], ++ p_addr[2], p_addr[1], p_addr[0]); ++ ++ /* Set the MAC address here for TMAC and RMAC */ ++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port_num << 12)), ++ ((p_addr[5] << 8) | p_addr[4])); ++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port_num << 12)), ++ ((p_addr[3] << 8) | p_addr[2])); ++ TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port_num << 12)), ++ ((p_addr[1] << 8) | p_addr[0])); ++ ++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port_num << 12)), ++ ((p_addr[5] << 8) | p_addr[4])); ++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port_num << 12)), ++ ((p_addr[3] << 8) | p_addr[2])); ++ TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port_num << 12)), ++ ((p_addr[1] << 8) | p_addr[0])); ++} ++ ++/* ++ * Set the MAC address of the Ethernet device ++ */ ++static int titan_ge_set_mac_address(struct net_device *dev, void *addr) ++{ ++ titan_ge_port_info *tp = netdev_priv(dev); ++ struct sockaddr *sa = addr; ++ ++ memcpy(dev->dev_addr, sa->sa_data, dev->addr_len); ++ ++ spin_lock_irq(&tp->lock); ++ titan_ge_update_mac_address(dev); ++ spin_unlock_irq(&tp->lock); ++ ++ return 0; ++} ++ ++/* ++ * Get the Ethernet device stats ++ */ ++static struct net_device_stats *titan_ge_get_stats(struct net_device *netdev) ++{ ++ titan_ge_port_info *titan_ge_eth = netdev_priv(netdev); ++ ++ return &titan_ge_eth->stats; ++} ++ ++/* ++ * Initialize the Rx descriptor ring for the Titan Ge ++ */ ++static int titan_ge_init_rx_desc_ring(titan_ge_port_info * titan_eth_port, ++ int rx_desc_num, ++ int rx_buff_size, ++ unsigned long rx_desc_base_addr, ++ unsigned long rx_buff_base_addr, ++ unsigned long rx_dma) ++{ ++ volatile titan_ge_rx_desc *rx_desc; ++ unsigned long buffer_addr; ++ int index; ++ unsigned long titan_ge_rx_desc_bus = rx_dma; ++ ++ buffer_addr = rx_buff_base_addr; ++ rx_desc = (titan_ge_rx_desc *) rx_desc_base_addr; ++ ++ /* Check alignment */ ++ if (rx_buff_base_addr & 0xF) ++ return 0; ++ ++ /* Check Rx buffer size */ ++ if ((rx_buff_size < 8) || (rx_buff_size > TITAN_GE_MAX_RX_BUFFER)) ++ return 0; ++ ++ /* 64-bit alignment ++ if ((rx_buff_base_addr + rx_buff_size) & 0x7) ++ return 0; */ ++ ++ /* Initialize the Rx desc ring */ ++ for (index = 0; index < rx_desc_num; index++) { ++ titan_ge_rx_desc_bus += sizeof(titan_ge_rx_desc); ++ rx_desc[index].cmd_sts = 0; ++ rx_desc[index].buffer_addr = buffer_addr; ++ titan_eth_port->rx_skb[index] = NULL; ++ buffer_addr += rx_buff_size; ++ } ++ ++ titan_eth_port->rx_curr_desc_q = 0; ++ titan_eth_port->rx_used_desc_q = 0; ++ ++ titan_eth_port->rx_desc_area = (titan_ge_rx_desc *) rx_desc_base_addr; ++ titan_eth_port->rx_desc_area_size = ++ rx_desc_num * sizeof(titan_ge_rx_desc); ++ ++ titan_eth_port->rx_dma = rx_dma; ++ ++ return TITAN_OK; ++} ++ ++/* ++ * Initialize the Tx descriptor ring. Descriptors in the SRAM ++ */ ++static int titan_ge_init_tx_desc_ring(titan_ge_port_info * titan_ge_port, ++ int tx_desc_num, ++ unsigned long tx_desc_base_addr, ++ unsigned long tx_dma) ++{ ++ titan_ge_tx_desc *tx_desc; ++ int index; ++ unsigned long titan_ge_tx_desc_bus = tx_dma; ++ ++ if (tx_desc_base_addr & 0xF) ++ return 0; ++ ++ tx_desc = (titan_ge_tx_desc *) tx_desc_base_addr; ++ ++ for (index = 0; index < tx_desc_num; index++) { ++ titan_ge_port->tx_dma_array[index] = ++ (dma_addr_t) titan_ge_tx_desc_bus; ++ titan_ge_tx_desc_bus += sizeof(titan_ge_tx_desc); ++ tx_desc[index].cmd_sts = 0x0000; ++ tx_desc[index].buffer_len = 0; ++ tx_desc[index].buffer_addr = 0x00000000; ++ titan_ge_port->tx_skb[index] = NULL; ++ } ++ ++ titan_ge_port->tx_curr_desc_q = 0; ++ titan_ge_port->tx_used_desc_q = 0; ++ ++ titan_ge_port->tx_desc_area = (titan_ge_tx_desc *) tx_desc_base_addr; ++ titan_ge_port->tx_desc_area_size = ++ tx_desc_num * sizeof(titan_ge_tx_desc); ++ ++ titan_ge_port->tx_dma = tx_dma; ++ return TITAN_OK; ++} ++ ++/* ++ * Initialize the device as an Ethernet device ++ */ ++static int __init titan_ge_probe(struct device *device) ++{ ++ titan_ge_port_info *titan_ge_eth; ++ struct net_device *netdev; ++ int port = to_platform_device(device)->id; ++ int err; ++ ++ netdev = alloc_etherdev(sizeof(titan_ge_port_info)); ++ if (!netdev) { ++ err = -ENODEV; ++ goto out; ++ } ++ ++ netdev->open = titan_ge_open; ++ netdev->stop = titan_ge_stop; ++ netdev->hard_start_xmit = titan_ge_start_xmit; ++ netdev->get_stats = titan_ge_get_stats; ++ netdev->set_multicast_list = titan_ge_set_multi; ++ netdev->set_mac_address = titan_ge_set_mac_address; ++ ++ /* Tx timeout */ ++ netdev->tx_timeout = titan_ge_tx_timeout; ++ netdev->watchdog_timeo = 2 * HZ; ++ ++ /* Set these to very high values */ ++ netdev->poll = titan_ge_poll; ++ netdev->weight = 64; ++ ++ netdev->tx_queue_len = TITAN_GE_TX_QUEUE; ++ netif_carrier_off(netdev); ++ netdev->base_addr = 0; ++ ++ netdev->change_mtu = titan_ge_change_mtu; ++ ++ titan_ge_eth = netdev_priv(netdev); ++ /* Allocation of memory for the driver structures */ ++ ++ titan_ge_eth->port_num = port; ++ ++ /* Configure the Tx timeout handler */ ++ INIT_WORK(&titan_ge_eth->tx_timeout_task, ++ (void (*)(void *)) titan_ge_tx_timeout_task, netdev); ++ ++ spin_lock_init(&titan_ge_eth->lock); ++ ++ /* set MAC addresses */ ++ memcpy(netdev->dev_addr, titan_ge_mac_addr_base, 6); ++ netdev->dev_addr[5] += port; ++ ++ err = register_netdev(netdev); ++ ++ if (err) ++ goto out_free_netdev; ++ ++ printk(KERN_NOTICE ++ "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", ++ netdev->name, port, netdev->dev_addr[0], ++ netdev->dev_addr[1], netdev->dev_addr[2], ++ netdev->dev_addr[3], netdev->dev_addr[4], ++ netdev->dev_addr[5]); ++ ++ printk(KERN_NOTICE "Rx NAPI supported, Tx Coalescing ON \n"); ++ ++ return 0; ++ ++out_free_netdev: ++ kfree(netdev); ++ ++out: ++ return err; ++} ++ ++static void __devexit titan_device_remove(struct device *device) ++{ ++} ++ ++/* ++ * Reset the Ethernet port ++ */ ++static void titan_ge_port_reset(unsigned int port_num) ++{ ++ unsigned int reg_data; ++ ++ /* Stop the Tx port activity */ ++ reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + ++ (port_num << 12)); ++ reg_data &= ~(0x0001); ++ TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + ++ (port_num << 12)), reg_data); ++ ++ /* Stop the Rx port activity */ ++ reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + ++ (port_num << 12)); ++ reg_data &= ~(0x0001); ++ TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + ++ (port_num << 12)), reg_data); ++ ++ return; ++} ++ ++/* ++ * Return the Tx desc after use by the XDMA ++ */ ++static int titan_ge_return_tx_desc(titan_ge_port_info * titan_ge_eth, int port) ++{ ++ int tx_desc_used; ++ struct sk_buff *skb; ++ ++ tx_desc_used = titan_ge_eth->tx_used_desc_q; ++ ++ /* return right away */ ++ if (tx_desc_used == titan_ge_eth->tx_curr_desc_q) ++ return TITAN_ERROR; ++ ++ /* Now the critical stuff */ ++ skb = titan_ge_eth->tx_skb[tx_desc_used]; ++ ++ dev_kfree_skb_any(skb); ++ ++ titan_ge_eth->tx_skb[tx_desc_used] = NULL; ++ titan_ge_eth->tx_used_desc_q = ++ (tx_desc_used + 1) % TITAN_GE_TX_QUEUE; ++ ++ return 0; ++} ++ ++/* ++ * Coalescing for the Tx path ++ */ ++static unsigned long titan_ge_tx_coal(unsigned long delay, int port) ++{ ++ unsigned long rx_delay; ++ ++ rx_delay = TITAN_GE_READ(TITAN_GE_INT_COALESCING); ++ delay = (delay << 16) | rx_delay; ++ ++ TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay); ++ TITAN_GE_WRITE(0x5038, delay); ++ ++ return delay; ++} ++ ++static struct device_driver titan_soc_driver = { ++ .name = titan_string, ++ .bus = &platform_bus_type, ++ .probe = titan_ge_probe, ++ .remove = __devexit_p(titan_device_remove), ++}; ++ ++static void titan_platform_release (struct device *device) ++{ ++ struct platform_device *pldev; ++ ++ /* free device */ ++ pldev = to_platform_device (device); ++ kfree (pldev); ++} ++ ++/* ++ * Register the Titan GE with the kernel ++ */ ++static int __init titan_ge_init_module(void) ++{ ++ struct platform_device *pldev; ++ unsigned int version, device; ++ int i; ++ ++ printk(KERN_NOTICE ++ "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n"); ++ ++ titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE); ++ if (!titan_ge_base) { ++ printk("Mapping Titan GE failed\n"); ++ goto out; ++ } ++ ++ device = TITAN_GE_READ(TITAN_GE_DEVICE_ID); ++ version = (device & 0x000f0000) >> 16; ++ device &= 0x0000ffff; ++ ++ printk(KERN_NOTICE "Device Id : %x, Version : %x \n", device, version); ++ ++#ifdef TITAN_RX_RING_IN_SRAM ++ titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE, ++ TITAN_SRAM_SIZE); ++ if (!titan_ge_sram) { ++ printk("Mapping Titan SRAM failed\n"); ++ goto out_unmap_ge; ++ } ++#endif ++ ++ if (driver_register(&titan_soc_driver)) { ++ printk(KERN_ERR "Driver registration failed\n"); ++ goto out_unmap_sram; ++ } ++ ++ for (i = 0; i < 3; i++) { ++ titan_ge_device[i] = NULL; ++ ++ if (!(pldev = kmalloc (sizeof (*pldev), GFP_KERNEL))) ++ continue; ++ ++ memset (pldev, 0, sizeof (*pldev)); ++ pldev->name = titan_string; ++ pldev->id = i; ++ pldev->dev.release = titan_platform_release; ++ titan_ge_device[i] = pldev; ++ ++ if (platform_device_register (pldev)) { ++ kfree (pldev); ++ titan_ge_device[i] = NULL; ++ continue; ++ } ++ ++ if (!pldev->dev.driver) { ++ /* ++ * The driver was not bound to this device, there was ++ * no hardware at this address. Unregister it, as the ++ * release fuction will take care of freeing the ++ * allocated structure ++ */ ++ titan_ge_device[i] = NULL; ++ platform_device_unregister (pldev); ++ } ++ } ++ ++ return 0; ++ ++out_unmap_sram: ++ iounmap((void *)titan_ge_sram); ++ ++out_unmap_ge: ++ iounmap((void *)titan_ge_base); ++ ++out: ++ return -ENOMEM; ++} ++ ++/* ++ * Unregister the Titan GE from the kernel ++ */ ++static void __exit titan_ge_cleanup_module(void) ++{ ++ int i; ++ ++ driver_unregister(&titan_soc_driver); ++ ++ for (i = 0; i < 3; i++) { ++ if (titan_ge_device[i]) { ++ platform_device_unregister (titan_ge_device[i]); ++ titan_ge_device[i] = NULL; ++ } ++ } ++ ++ iounmap((void *)titan_ge_sram); ++ iounmap((void *)titan_ge_base); ++} ++ ++MODULE_AUTHOR("Manish Lachwani <lachwani@pmc-sierra.com>"); ++MODULE_DESCRIPTION("Titan GE Ethernet driver"); ++MODULE_LICENSE("GPL"); ++ ++module_init(titan_ge_init_module); ++module_exit(titan_ge_cleanup_module); +diff -Nur linux-2.6.30/drivers/net/titan_ge.h rt4ls/drivers/net/titan_ge.h +--- linux-2.6.30/drivers/net/titan_ge.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/drivers/net/titan_ge.h 2009-06-12 16:28:16.835950077 +0200 +@@ -0,0 +1,415 @@ ++#ifndef _TITAN_GE_H_ ++#define _TITAN_GE_H_ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/spinlock.h> ++#include <asm/byteorder.h> ++ ++/* ++ * These functions should be later moved to a more generic location since there ++ * will be others accessing it also ++ */ ++ ++/* ++ * This is the way it works: LKB5 Base is at 0x0128. TITAN_BASE is defined in ++ * include/asm/titan_dep.h. TITAN_GE_BASE is the value in the TITAN_GE_LKB5 ++ * register. ++ */ ++ ++#define TITAN_GE_BASE 0xfe000000UL ++#define TITAN_GE_SIZE 0x10000UL ++ ++extern unsigned long titan_ge_base; ++ ++#define TITAN_GE_WRITE(offset, data) \ ++ *(volatile u32 *)(titan_ge_base + (offset)) = (data) ++ ++#define TITAN_GE_READ(offset) *(volatile u32 *)(titan_ge_base + (offset)) ++ ++#ifndef msec_delay ++#define msec_delay(x) do { if(in_interrupt()) { \ ++ /* Don't mdelay in interrupt context! */ \ ++ BUG(); \ ++ } else { \ ++ set_current_state(TASK_UNINTERRUPTIBLE); \ ++ schedule_timeout((x * HZ)/1000); \ ++ } } while(0) ++#endif ++ ++#define TITAN_GE_PORT_0 ++ ++#define TITAN_SRAM_BASE ((OCD_READ(RM9000x2_OCD_LKB13) & ~1) << 4) ++#define TITAN_SRAM_SIZE 0x2000UL ++ ++/* ++ * We may need these constants ++ */ ++#define TITAN_BIT0 0x00000001 ++#define TITAN_BIT1 0x00000002 ++#define TITAN_BIT2 0x00000004 ++#define TITAN_BIT3 0x00000008 ++#define TITAN_BIT4 0x00000010 ++#define TITAN_BIT5 0x00000020 ++#define TITAN_BIT6 0x00000040 ++#define TITAN_BIT7 0x00000080 ++#define TITAN_BIT8 0x00000100 ++#define TITAN_BIT9 0x00000200 ++#define TITAN_BIT10 0x00000400 ++#define TITAN_BIT11 0x00000800 ++#define TITAN_BIT12 0x00001000 ++#define TITAN_BIT13 0x00002000 ++#define TITAN_BIT14 0x00004000 ++#define TITAN_BIT15 0x00008000 ++#define TITAN_BIT16 0x00010000 ++#define TITAN_BIT17 0x00020000 ++#define TITAN_BIT18 0x00040000 ++#define TITAN_BIT19 0x00080000 ++#define TITAN_BIT20 0x00100000 ++#define TITAN_BIT21 0x00200000 ++#define TITAN_BIT22 0x00400000 ++#define TITAN_BIT23 0x00800000 ++#define TITAN_BIT24 0x01000000 ++#define TITAN_BIT25 0x02000000 ++#define TITAN_BIT26 0x04000000 ++#define TITAN_BIT27 0x08000000 ++#define TITAN_BIT28 0x10000000 ++#define TITAN_BIT29 0x20000000 ++#define TITAN_BIT30 0x40000000 ++#define TITAN_BIT31 0x80000000 ++ ++/* Flow Control */ ++#define TITAN_GE_FC_NONE 0x0 ++#define TITAN_GE_FC_FULL 0x1 ++#define TITAN_GE_FC_TX_PAUSE 0x2 ++#define TITAN_GE_FC_RX_PAUSE 0x3 ++ ++/* Duplex Settings */ ++#define TITAN_GE_FULL_DUPLEX 0x1 ++#define TITAN_GE_HALF_DUPLEX 0x2 ++ ++/* Speed settings */ ++#define TITAN_GE_SPEED_1000 0x1 ++#define TITAN_GE_SPEED_100 0x2 ++#define TITAN_GE_SPEED_10 0x3 ++ ++/* Debugging info only */ ++#undef TITAN_DEBUG ++ ++/* Keep the rings in the Titan's SSRAM */ ++#define TITAN_RX_RING_IN_SRAM ++ ++#ifdef CONFIG_64BIT ++#define TITAN_GE_IE_MASK 0xfffffffffb001b64 ++#define TITAN_GE_IE_STATUS 0xfffffffffb001b60 ++#else ++#define TITAN_GE_IE_MASK 0xfb001b64 ++#define TITAN_GE_IE_STATUS 0xfb001b60 ++#endif ++ ++/* Support for Jumbo Frames */ ++#undef TITAN_GE_JUMBO_FRAMES ++ ++/* Rx buffer size */ ++#ifdef TITAN_GE_JUMBO_FRAMES ++#define TITAN_GE_JUMBO_BUFSIZE 9080 ++#else ++#define TITAN_GE_STD_BUFSIZE 1580 ++#endif ++ ++/* ++ * Tx and Rx Interrupt Coalescing parameter. These values are ++ * for 1 Ghz processor. Rx coalescing can be taken care of ++ * by NAPI. NAPI is adaptive and hence useful. Tx coalescing ++ * is not adaptive. Hence, these values need to be adjusted ++ * based on load, CPU speed etc. ++ */ ++#define TITAN_GE_RX_COAL 150 ++#define TITAN_GE_TX_COAL 300 ++ ++#if defined(__BIG_ENDIAN) ++ ++/* Define the Rx descriptor */ ++typedef struct eth_rx_desc { ++ u32 reserved; /* Unused */ ++ u32 buffer_addr; /* CPU buffer address */ ++ u32 cmd_sts; /* Command and Status */ ++ u32 buffer; /* XDMA buffer address */ ++} titan_ge_rx_desc; ++ ++/* Define the Tx descriptor */ ++typedef struct eth_tx_desc { ++ u16 cmd_sts; /* Command, Status and Buffer count */ ++ u16 buffer_len; /* Length of the buffer */ ++ u32 buffer_addr; /* Physical address of the buffer */ ++} titan_ge_tx_desc; ++ ++#elif defined(__LITTLE_ENDIAN) ++ ++/* Define the Rx descriptor */ ++typedef struct eth_rx_desc { ++ u32 buffer_addr; /* CPU buffer address */ ++ u32 reserved; /* Unused */ ++ u32 buffer; /* XDMA buffer address */ ++ u32 cmd_sts; /* Command and Status */ ++} titan_ge_rx_desc; ++ ++/* Define the Tx descriptor */ ++typedef struct eth_tx_desc { ++ u32 buffer_addr; /* Physical address of the buffer */ ++ u16 buffer_len; /* Length of the buffer */ ++ u16 cmd_sts; /* Command, Status and Buffer count */ ++} titan_ge_tx_desc; ++#endif ++ ++/* Default Tx Queue Size */ ++#define TITAN_GE_TX_QUEUE 128 ++#define TITAN_TX_RING_BYTES (TITAN_GE_TX_QUEUE * sizeof(struct eth_tx_desc)) ++ ++/* Default Rx Queue Size */ ++#define TITAN_GE_RX_QUEUE 64 ++#define TITAN_RX_RING_BYTES (TITAN_GE_RX_QUEUE * sizeof(struct eth_rx_desc)) ++ ++/* Packet Structure */ ++typedef struct _pkt_info { ++ unsigned int len; ++ unsigned int cmd_sts; ++ unsigned int buffer; ++ struct sk_buff *skb; ++ unsigned int checksum; ++} titan_ge_packet; ++ ++ ++#define PHYS_CNT 3 ++ ++/* Titan Port specific data structure */ ++typedef struct _eth_port_ctrl { ++ unsigned int port_num; ++ u8 port_mac_addr[6]; ++ ++ /* Rx descriptor pointers */ ++ int rx_curr_desc_q, rx_used_desc_q; ++ ++ /* Tx descriptor pointers */ ++ int tx_curr_desc_q, tx_used_desc_q; ++ ++ /* Rx descriptor area */ ++ volatile titan_ge_rx_desc *rx_desc_area; ++ unsigned int rx_desc_area_size; ++ struct sk_buff* rx_skb[TITAN_GE_RX_QUEUE]; ++ ++ /* Tx Descriptor area */ ++ volatile titan_ge_tx_desc *tx_desc_area; ++ unsigned int tx_desc_area_size; ++ struct sk_buff* tx_skb[TITAN_GE_TX_QUEUE]; ++ ++ /* Timeout task */ ++ struct work_struct tx_timeout_task; ++ ++ /* DMA structures and handles */ ++ dma_addr_t tx_dma; ++ dma_addr_t rx_dma; ++ dma_addr_t tx_dma_array[TITAN_GE_TX_QUEUE]; ++ ++ /* Device lock */ ++ spinlock_t lock; ++ ++ unsigned int tx_ring_skbs; ++ unsigned int rx_ring_size; ++ unsigned int tx_ring_size; ++ unsigned int rx_ring_skbs; ++ ++ struct net_device_stats stats; ++ ++ /* Tx and Rx coalescing */ ++ unsigned long rx_int_coal; ++ unsigned long tx_int_coal; ++ ++ /* Threshold for replenishing the Rx and Tx rings */ ++ unsigned int tx_threshold; ++ unsigned int rx_threshold; ++ ++ /* NAPI work limit */ ++ unsigned int rx_work_limit; ++} titan_ge_port_info; ++ ++/* Titan specific constants */ ++#define TITAN_ETH_PORT_IRQ 3 ++ ++/* Max Rx buffer */ ++#define TITAN_GE_MAX_RX_BUFFER 65536 ++ ++/* Tx and Rx Error */ ++#define TITAN_GE_ERROR ++ ++/* Rx Descriptor Command and Status */ ++ ++#define TITAN_GE_RX_CRC_ERROR TITAN_BIT27 /* crc error */ ++#define TITAN_GE_RX_OVERFLOW_ERROR TITAN_BIT15 /* overflow */ ++#define TITAN_GE_RX_BUFFER_OWNED TITAN_BIT21 /* buffer ownership */ ++#define TITAN_GE_RX_STP TITAN_BIT31 /* start of packet */ ++#define TITAN_GE_RX_BAM TITAN_BIT30 /* broadcast address match */ ++#define TITAN_GE_RX_PAM TITAN_BIT28 /* physical address match */ ++#define TITAN_GE_RX_LAFM TITAN_BIT29 /* logical address filter match */ ++#define TITAN_GE_RX_VLAN TITAN_BIT26 /* virtual lans */ ++#define TITAN_GE_RX_PERR TITAN_BIT19 /* packet error */ ++#define TITAN_GE_RX_TRUNC TITAN_BIT20 /* packet size greater than 32 buffers */ ++ ++/* Tx Descriptor Command */ ++#define TITAN_GE_TX_BUFFER_OWNED TITAN_BIT5 /* buffer ownership */ ++#define TITAN_GE_TX_ENABLE_INTERRUPT TITAN_BIT15 /* Interrupt Enable */ ++ ++/* Return Status */ ++#define TITAN_OK 0x1 /* Good Status */ ++#define TITAN_ERROR 0x2 /* Error Status */ ++ ++/* MIB specific register offset */ ++#define TITAN_GE_MSTATX_STATS_BASE_LOW 0x0800 /* MSTATX COUNTL[15:0] */ ++#define TITAN_GE_MSTATX_STATS_BASE_MID 0x0804 /* MSTATX COUNTM[15:0] */ ++#define TITAN_GE_MSTATX_STATS_BASE_HI 0x0808 /* MSTATX COUNTH[7:0] */ ++#define TITAN_GE_MSTATX_CONTROL 0x0828 /* MSTATX Control */ ++#define TITAN_GE_MSTATX_VARIABLE_SELECT 0x082C /* MSTATX Variable Select */ ++ ++/* MIB counter offsets, add to the TITAN_GE_MSTATX_STATS_BASE_XXX */ ++#define TITAN_GE_MSTATX_RXFRAMESOK 0x0040 ++#define TITAN_GE_MSTATX_RXOCTETSOK 0x0050 ++#define TITAN_GE_MSTATX_RXFRAMES 0x0060 ++#define TITAN_GE_MSTATX_RXOCTETS 0x0070 ++#define TITAN_GE_MSTATX_RXUNICASTFRAMESOK 0x0080 ++#define TITAN_GE_MSTATX_RXBROADCASTFRAMESOK 0x0090 ++#define TITAN_GE_MSTATX_RXMULTICASTFRAMESOK 0x00A0 ++#define TITAN_GE_MSTATX_RXTAGGEDFRAMESOK 0x00B0 ++#define TITAN_GE_MSTATX_RXMACPAUSECONTROLFRAMESOK 0x00C0 ++#define TITAN_GE_MSTATX_RXMACCONTROLFRAMESOK 0x00D0 ++#define TITAN_GE_MSTATX_RXFCSERROR 0x00E0 ++#define TITAN_GE_MSTATX_RXALIGNMENTERROR 0x00F0 ++#define TITAN_GE_MSTATX_RXSYMBOLERROR 0x0100 ++#define TITAN_GE_MSTATX_RXLAYER1ERROR 0x0110 ++#define TITAN_GE_MSTATX_RXINRANGELENGTHERROR 0x0120 ++#define TITAN_GE_MSTATX_RXLONGLENGTHERROR 0x0130 ++#define TITAN_GE_MSTATX_RXLONGLENGTHCRCERROR 0x0140 ++#define TITAN_GE_MSTATX_RXSHORTLENGTHERROR 0x0150 ++#define TITAN_GE_MSTATX_RXSHORTLLENGTHCRCERROR 0x0160 ++#define TITAN_GE_MSTATX_RXFRAMES64OCTETS 0x0170 ++#define TITAN_GE_MSTATX_RXFRAMES65TO127OCTETS 0x0180 ++#define TITAN_GE_MSTATX_RXFRAMES128TO255OCTETS 0x0190 ++#define TITAN_GE_MSTATX_RXFRAMES256TO511OCTETS 0x01A0 ++#define TITAN_GE_MSTATX_RXFRAMES512TO1023OCTETS 0x01B0 ++#define TITAN_GE_MSTATX_RXFRAMES1024TO1518OCTETS 0x01C0 ++#define TITAN_GE_MSTATX_RXFRAMES1519TOMAXSIZE 0x01D0 ++#define TITAN_GE_MSTATX_RXSTATIONADDRESSFILTERED 0x01E0 ++#define TITAN_GE_MSTATX_RXVARIABLE 0x01F0 ++#define TITAN_GE_MSTATX_GENERICADDRESSFILTERED 0x0200 ++#define TITAN_GE_MSTATX_UNICASTFILTERED 0x0210 ++#define TITAN_GE_MSTATX_MULTICASTFILTERED 0x0220 ++#define TITAN_GE_MSTATX_BROADCASTFILTERED 0x0230 ++#define TITAN_GE_MSTATX_HASHFILTERED 0x0240 ++#define TITAN_GE_MSTATX_TXFRAMESOK 0x0250 ++#define TITAN_GE_MSTATX_TXOCTETSOK 0x0260 ++#define TITAN_GE_MSTATX_TXOCTETS 0x0270 ++#define TITAN_GE_MSTATX_TXTAGGEDFRAMESOK 0x0280 ++#define TITAN_GE_MSTATX_TXMACPAUSECONTROLFRAMESOK 0x0290 ++#define TITAN_GE_MSTATX_TXFCSERROR 0x02A0 ++#define TITAN_GE_MSTATX_TXSHORTLENGTHERROR 0x02B0 ++#define TITAN_GE_MSTATX_TXLONGLENGTHERROR 0x02C0 ++#define TITAN_GE_MSTATX_TXSYSTEMERROR 0x02D0 ++#define TITAN_GE_MSTATX_TXMACERROR 0x02E0 ++#define TITAN_GE_MSTATX_TXCARRIERSENSEERROR 0x02F0 ++#define TITAN_GE_MSTATX_TXSQETESTERROR 0x0300 ++#define TITAN_GE_MSTATX_TXUNICASTFRAMESOK 0x0310 ++#define TITAN_GE_MSTATX_TXBROADCASTFRAMESOK 0x0320 ++#define TITAN_GE_MSTATX_TXMULTICASTFRAMESOK 0x0330 ++#define TITAN_GE_MSTATX_TXUNICASTFRAMESATTEMPTED 0x0340 ++#define TITAN_GE_MSTATX_TXBROADCASTFRAMESATTEMPTED 0x0350 ++#define TITAN_GE_MSTATX_TXMULTICASTFRAMESATTEMPTED 0x0360 ++#define TITAN_GE_MSTATX_TXFRAMES64OCTETS 0x0370 ++#define TITAN_GE_MSTATX_TXFRAMES65TO127OCTETS 0x0380 ++#define TITAN_GE_MSTATX_TXFRAMES128TO255OCTETS 0x0390 ++#define TITAN_GE_MSTATX_TXFRAMES256TO511OCTETS 0x03A0 ++#define TITAN_GE_MSTATX_TXFRAMES512TO1023OCTETS 0x03B0 ++#define TITAN_GE_MSTATX_TXFRAMES1024TO1518OCTETS 0x03C0 ++#define TITAN_GE_MSTATX_TXFRAMES1519TOMAXSIZE 0x03D0 ++#define TITAN_GE_MSTATX_TXVARIABLE 0x03E0 ++#define TITAN_GE_MSTATX_RXSYSTEMERROR 0x03F0 ++#define TITAN_GE_MSTATX_SINGLECOLLISION 0x0400 ++#define TITAN_GE_MSTATX_MULTIPLECOLLISION 0x0410 ++#define TITAN_GE_MSTATX_DEFERREDXMISSIONS 0x0420 ++#define TITAN_GE_MSTATX_LATECOLLISIONS 0x0430 ++#define TITAN_GE_MSTATX_ABORTEDDUETOXSCOLLS 0x0440 ++ ++/* Interrupt specific defines */ ++#define TITAN_GE_DEVICE_ID 0x0000 /* Device ID */ ++#define TITAN_GE_RESET 0x0004 /* Reset reg */ ++#define TITAN_GE_TSB_CTRL_0 0x000C /* TSB Control reg 0 */ ++#define TITAN_GE_TSB_CTRL_1 0x0010 /* TSB Control reg 1 */ ++#define TITAN_GE_INTR_GRP0_STATUS 0x0040 /* General Interrupt Group 0 Status */ ++#define TITAN_GE_INTR_XDMA_CORE_A 0x0048 /* XDMA Channel Interrupt Status, Core A*/ ++#define TITAN_GE_INTR_XDMA_CORE_B 0x004C /* XDMA Channel Interrupt Status, Core B*/ ++#define TITAN_GE_INTR_XDMA_IE 0x0058 /* XDMA Channel Interrupt Enable */ ++#define TITAN_GE_SDQPF_ECC_INTR 0x480C /* SDQPF ECC Interrupt Status */ ++#define TITAN_GE_SDQPF_RXFIFO_CTL 0x4828 /* SDQPF RxFifo Control and Interrupt Enb*/ ++#define TITAN_GE_SDQPF_RXFIFO_INTR 0x482C /* SDQPF RxFifo Interrupt Status */ ++#define TITAN_GE_SDQPF_TXFIFO_CTL 0x4928 /* SDQPF TxFifo Control and Interrupt Enb*/ ++#define TITAN_GE_SDQPF_TXFIFO_INTR 0x492C /* SDQPF TxFifo Interrupt Status */ ++#define TITAN_GE_SDQPF_RXFIFO_0 0x4840 /* SDQPF RxFIFO Enable */ ++#define TITAN_GE_SDQPF_TXFIFO_0 0x4940 /* SDQPF TxFIFO Enable */ ++#define TITAN_GE_XDMA_CONFIG 0x5000 /* XDMA Global Configuration */ ++#define TITAN_GE_XDMA_INTR_SUMMARY 0x5010 /* XDMA Interrupt Summary */ ++#define TITAN_GE_XDMA_BUFADDRPRE 0x5018 /* XDMA Buffer Address Prefix */ ++#define TITAN_GE_XDMA_DESCADDRPRE 0x501C /* XDMA Descriptor Address Prefix */ ++#define TITAN_GE_XDMA_PORTWEIGHT 0x502C /* XDMA Port Weight Configuration */ ++ ++/* Rx MAC defines */ ++#define TITAN_GE_RMAC_CONFIG_1 0x1200 /* RMAC Configuration 1 */ ++#define TITAN_GE_RMAC_CONFIG_2 0x1204 /* RMAC Configuration 2 */ ++#define TITAN_GE_RMAC_MAX_FRAME_LEN 0x1208 /* RMAC Max Frame Length */ ++#define TITAN_GE_RMAC_STATION_HI 0x120C /* Rx Station Address High */ ++#define TITAN_GE_RMAC_STATION_MID 0x1210 /* Rx Station Address Middle */ ++#define TITAN_GE_RMAC_STATION_LOW 0x1214 /* Rx Station Address Low */ ++#define TITAN_GE_RMAC_LINK_CONFIG 0x1218 /* RMAC Link Configuration */ ++ ++/* Tx MAC defines */ ++#define TITAN_GE_TMAC_CONFIG_1 0x1240 /* TMAC Configuration 1 */ ++#define TITAN_GE_TMAC_CONFIG_2 0x1244 /* TMAC Configuration 2 */ ++#define TITAN_GE_TMAC_IPG 0x1248 /* TMAC Inter-Packet Gap */ ++#define TITAN_GE_TMAC_STATION_HI 0x124C /* Tx Station Address High */ ++#define TITAN_GE_TMAC_STATION_MID 0x1250 /* Tx Station Address Middle */ ++#define TITAN_GE_TMAC_STATION_LOW 0x1254 /* Tx Station Address Low */ ++#define TITAN_GE_TMAC_MAX_FRAME_LEN 0x1258 /* TMAC Max Frame Length */ ++#define TITAN_GE_TMAC_MIN_FRAME_LEN 0x125C /* TMAC Min Frame Length */ ++#define TITAN_GE_TMAC_PAUSE_FRAME_TIME 0x1260 /* TMAC Pause Frame Time */ ++#define TITAN_GE_TMAC_PAUSE_FRAME_INTERVAL 0x1264 /* TMAC Pause Frame Interval */ ++ ++/* GMII register */ ++#define TITAN_GE_GMII_INTERRUPT_STATUS 0x1348 /* GMII Interrupt Status */ ++#define TITAN_GE_GMII_CONFIG_GENERAL 0x134C /* GMII Configuration General */ ++#define TITAN_GE_GMII_CONFIG_MODE 0x1350 /* GMII Configuration Mode */ ++ ++/* Tx and Rx XDMA defines */ ++#define TITAN_GE_INT_COALESCING 0x5030 /* Interrupt Coalescing */ ++#define TITAN_GE_CHANNEL0_CONFIG 0x5040 /* Channel 0 XDMA config */ ++#define TITAN_GE_CHANNEL0_INTERRUPT 0x504c /* Channel 0 Interrupt Status */ ++#define TITAN_GE_GDI_INTERRUPT_ENABLE 0x5050 /* IE for the GDI Errors */ ++#define TITAN_GE_CHANNEL0_PACKET 0x5060 /* Channel 0 Packet count */ ++#define TITAN_GE_CHANNEL0_BYTE 0x5064 /* Channel 0 Byte count */ ++#define TITAN_GE_CHANNEL0_TX_DESC 0x5054 /* Channel 0 Tx first desc */ ++#define TITAN_GE_CHANNEL0_RX_DESC 0x5058 /* Channel 0 Rx first desc */ ++ ++/* AFX (Address Filter Exact) register offsets for Slice 0 */ ++#define TITAN_GE_AFX_EXACT_MATCH_LOW 0x1100 /* AFX Exact Match Address Low*/ ++#define TITAN_GE_AFX_EXACT_MATCH_MID 0x1104 /* AFX Exact Match Address Mid*/ ++#define TITAN_GE_AFX_EXACT_MATCH_HIGH 0x1108 /* AFX Exact Match Address Hi */ ++#define TITAN_GE_AFX_EXACT_MATCH_VID 0x110C /* AFX Exact Match VID */ ++#define TITAN_GE_AFX_MULTICAST_HASH_LOW 0x1110 /* AFX Multicast HASH Low */ ++#define TITAN_GE_AFX_MULTICAST_HASH_MIDLOW 0x1114 /* AFX Multicast HASH MidLow */ ++#define TITAN_GE_AFX_MULTICAST_HASH_MIDHI 0x1118 /* AFX Multicast HASH MidHi */ ++#define TITAN_GE_AFX_MULTICAST_HASH_HI 0x111C /* AFX Multicast HASH Hi */ ++#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 0x1120 /* AFX Address Filter Ctrl 0 */ ++#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 0x1124 /* AFX Address Filter Ctrl 1 */ ++#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 0x1128 /* AFX Address Filter Ctrl 2 */ ++ ++/* Traffic Groomer block */ ++#define TITAN_GE_TRTG_CONFIG 0x1000 /* TRTG Config */ ++ ++#endif /* _TITAN_GE_H_ */ ++ +diff -Nur linux-2.6.30/drivers/net/titan_mdio.c rt4ls/drivers/net/titan_mdio.c +--- linux-2.6.30/drivers/net/titan_mdio.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/drivers/net/titan_mdio.c 2009-06-12 16:28:16.835950077 +0200 +@@ -0,0 +1,217 @@ ++/* ++ * drivers/net/titan_mdio.c - Driver for Titan ethernet ports ++ * ++ * Copyright (C) 2003 PMC-Sierra Inc. ++ * Author : Manish Lachwani (lachwani@pmc-sierra.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Management Data IO (MDIO) driver for the Titan GMII. Interacts with the Marvel PHY ++ * on the Titan. No support for the TBI as yet. ++ * ++ */ ++ ++#include "titan_mdio.h" ++ ++#define MDIO_DEBUG ++ ++/* ++ * Local constants ++ */ ++#define MAX_CLKA 1023 ++#define MAX_PHY_DEV 31 ++#define MAX_PHY_REG 31 ++#define WRITEADDRS_OPCODE 0x0 ++#define READ_OPCODE 0x2 ++#define WRITE_OPCODE 0x1 ++#define MAX_MDIO_POLL 100 ++ ++/* ++ * Titan MDIO and SCMB registers ++ */ ++#define TITAN_GE_SCMB_CONTROL 0x01c0 /* SCMB Control */ ++#define TITAN_GE_SCMB_CLKA 0x01c4 /* SCMB Clock A */ ++#define TITAN_GE_MDIO_COMMAND 0x01d0 /* MDIO Command */ ++#define TITAN_GE_MDIO_DEVICE_PORT_ADDRESS 0x01d4 /* MDIO Device and Port addrs */ ++#define TITAN_GE_MDIO_DATA 0x01d8 /* MDIO Data */ ++#define TITAN_GE_MDIO_INTERRUPTS 0x01dC /* MDIO Interrupts */ ++ ++/* ++ * Function to poll the MDIO ++ */ ++static int titan_ge_mdio_poll(void) ++{ ++ int i, val; ++ ++ for (i = 0; i < MAX_MDIO_POLL; i++) { ++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND); ++ ++ if (!(val & 0x8000)) ++ return TITAN_GE_MDIO_GOOD; ++ } ++ ++ return TITAN_GE_MDIO_ERROR; ++} ++ ++ ++/* ++ * Initialize and configure the MDIO ++ */ ++int titan_ge_mdio_setup(titan_ge_mdio_config *titan_mdio) ++{ ++ unsigned long val; ++ ++ /* Reset the SCMB and program into MDIO mode*/ ++ TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x9000); ++ TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x1000); ++ ++ /* CLK A */ ++ val = TITAN_GE_MDIO_READ(TITAN_GE_SCMB_CLKA); ++ val = ( (val & ~(0x03ff)) | (titan_mdio->clka & 0x03ff)); ++ TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CLKA, val); ++ ++ /* Preamble Suppresion */ ++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND); ++ val = ( (val & ~(0x0001)) | (titan_mdio->mdio_spre & 0x0001)); ++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val); ++ ++ /* MDIO mode */ ++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS); ++ val = ( (val & ~(0x4000)) | (titan_mdio->mdio_mode & 0x4000)); ++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val); ++ ++ return TITAN_GE_MDIO_GOOD; ++} ++ ++/* ++ * Set the PHY address in indirect mode ++ */ ++int titan_ge_mdio_inaddrs(int dev_addr, int reg_addr) ++{ ++ volatile unsigned long val; ++ ++ /* Setup the PHY device */ ++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS); ++ val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00)); ++ val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f)); ++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val); ++ ++ /* Write the new address */ ++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND); ++ val = ( (val & ~(0x0300)) | ( (WRITEADDRS_OPCODE << 8) & 0x0300)); ++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val); ++ ++ return TITAN_GE_MDIO_GOOD; ++} ++ ++/* ++ * Read the MDIO register. This is what the individual parametes mean: ++ * ++ * dev_addr : PHY ID ++ * reg_addr : register offset ++ * ++ * See the spec for the Titan MAC. We operate in the Direct Mode. ++ */ ++ ++#define MAX_RETRIES 2 ++ ++int titan_ge_mdio_read(int dev_addr, int reg_addr, unsigned int *pdata) ++{ ++ volatile unsigned long val; ++ int retries = 0; ++ ++ /* Setup the PHY device */ ++ ++again: ++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS); ++ val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00)); ++ val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f)); ++ val |= 0x4000; ++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val); ++ ++ udelay(30); ++ ++ /* Issue the read command */ ++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND); ++ val = ( (val & ~(0x0300)) | ( (READ_OPCODE << 8) & 0x0300)); ++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val); ++ ++ udelay(30); ++ ++ if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD) ++ return TITAN_GE_MDIO_ERROR; ++ ++ *pdata = (unsigned int)TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DATA); ++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS); ++ ++ udelay(30); ++ ++ if (val & 0x2) { ++ if (retries == MAX_RETRIES) ++ return TITAN_GE_MDIO_ERROR; ++ else { ++ retries++; ++ goto again; ++ } ++ } ++ ++ return TITAN_GE_MDIO_GOOD; ++} ++ ++/* ++ * Write to the MDIO register ++ * ++ * dev_addr : PHY ID ++ * reg_addr : register that needs to be written to ++ * ++ */ ++int titan_ge_mdio_write(int dev_addr, int reg_addr, unsigned int data) ++{ ++ volatile unsigned long val; ++ ++ if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD) ++ return TITAN_GE_MDIO_ERROR; ++ ++ /* Setup the PHY device */ ++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS); ++ val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00)); ++ val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f)); ++ val |= 0x4000; ++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val); ++ ++ udelay(30); ++ ++ /* Setup the data to write */ ++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DATA, data); ++ ++ udelay(30); ++ ++ /* Issue the write command */ ++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND); ++ val = ( (val & ~(0x0300)) | ( (WRITE_OPCODE << 8) & 0x0300)); ++ TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val); ++ ++ udelay(30); ++ ++ if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD) ++ return TITAN_GE_MDIO_ERROR; ++ ++ val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS); ++ if (val & 0x2) ++ return TITAN_GE_MDIO_ERROR; ++ ++ return TITAN_GE_MDIO_GOOD; ++} ++ +diff -Nur linux-2.6.30/drivers/net/titan_mdio.h rt4ls/drivers/net/titan_mdio.h +--- linux-2.6.30/drivers/net/titan_mdio.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/drivers/net/titan_mdio.h 2009-06-12 16:28:16.835950077 +0200 +@@ -0,0 +1,56 @@ ++/* ++ * MDIO used to interact with the PHY when using GMII/MII ++ */ ++#ifndef _TITAN_MDIO_H ++#define _TITAN_MDIO_H ++ ++#include <linux/netdevice.h> ++#include <linux/workqueue.h> ++#include <linux/delay.h> ++#include "titan_ge.h" ++ ++ ++#define TITAN_GE_MDIO_ERROR (-9000) ++#define TITAN_GE_MDIO_GOOD 0 ++ ++#define TITAN_GE_MDIO_BASE titan_ge_base ++ ++#define TITAN_GE_MDIO_READ(offset) \ ++ *(volatile u32 *)(titan_ge_base + (offset)) ++ ++#define TITAN_GE_MDIO_WRITE(offset, data) \ ++ *(volatile u32 *)(titan_ge_base + (offset)) = (data) ++ ++ ++/* GMII specific registers */ ++#define TITAN_GE_MARVEL_PHY_ID 0x00 ++#define TITAN_PHY_AUTONEG_ADV 0x04 ++#define TITAN_PHY_LP_ABILITY 0x05 ++#define TITAN_GE_MDIO_MII_CTRL 0x09 ++#define TITAN_GE_MDIO_MII_EXTENDED 0x0f ++#define TITAN_GE_MDIO_PHY_CTRL 0x10 ++#define TITAN_GE_MDIO_PHY_STATUS 0x11 ++#define TITAN_GE_MDIO_PHY_IE 0x12 ++#define TITAN_GE_MDIO_PHY_IS 0x13 ++#define TITAN_GE_MDIO_PHY_LED 0x18 ++#define TITAN_GE_MDIO_PHY_LED_OVER 0x19 ++#define PHY_ANEG_TIME_WAIT 45 /* 45 seconds wait time */ ++ ++/* ++ * MDIO Config Structure ++ */ ++typedef struct { ++ unsigned int clka; ++ int mdio_spre; ++ int mdio_mode; ++} titan_ge_mdio_config; ++ ++/* ++ * Function Prototypes ++ */ ++int titan_ge_mdio_setup(titan_ge_mdio_config *); ++int titan_ge_mdio_inaddrs(int, int); ++int titan_ge_mdio_read(int, int, unsigned int *); ++int titan_ge_mdio_write(int, int, unsigned int); ++ ++#endif /* _TITAN_MDIO_H */ +diff -Nur linux-2.6.30/drivers/rtc/rtc-cmos.c rt4ls/drivers/rtc/rtc-cmos.c +--- linux-2.6.30/drivers/rtc/rtc-cmos.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/drivers/rtc/rtc-cmos.c 2009-06-12 16:28:34.779818333 +0200 +@@ -691,7 +691,8 @@ + */ + #if defined(CONFIG_ATARI) + address_space = 64; +-#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) || defined(__sparc__) ++#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \ ++ || defined(__sparc__) || defined(__mips__) + address_space = 128; + #else + #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. +@@ -756,9 +757,8 @@ + /* FIXME teach the alarm code how to handle binary mode; + * <asm-generic/rtc.h> doesn't know 12-hour mode either. + */ +- if (is_valid_irq(rtc_irq) && +- (!(rtc_control & RTC_24H) || (rtc_control & (RTC_DM_BINARY)))) { +- dev_dbg(dev, "only 24-hr BCD mode supported\n"); ++ if (is_valid_irq(rtc_irq) && !(rtc_control & RTC_24H)) { ++ dev_dbg(dev, "only 24-hr supported\n"); + retval = -ENXIO; + goto cleanup1; + } +diff -Nur linux-2.6.30/drivers/video/Kconfig rt4ls/drivers/video/Kconfig +--- linux-2.6.30/drivers/video/Kconfig 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/drivers/video/Kconfig 2009-06-12 16:28:47.484606170 +0200 +@@ -1930,6 +1930,28 @@ + Turn on debugging messages. Note that you can set/unset at run time + through sysfs + ++config FB_SM7XX ++ tristate "Silicon Motion SM7XX Frame Buffer Support" ++ depends on FB ++ select FB_CFB_FILLRECT ++ select FB_CFB_COPYAREA ++ select FB_CFB_IMAGEBLIT ++ help ++ Frame Buffer driver for the Silicon Motion SM7XX serial graphic card. ++ ++config FB_SM7XX_ACCEL ++ bool "Siliconmotion Acceleration functions (EXPERIMENTAL)" ++ depends on FB_SM7XX && EXPERIMENTAL ++ help ++ This will compile the Trident frame buffer device with ++ acceleration functions. ++ ++config FB_SM7XX_DUALHEAD ++ bool "Siliconmotion dualhead support (EXPERIMENTAL)" ++ depends on FB_SM7XX && EXPERIMENTAL ++ help ++ This will enable the dualhead support of SM7XX ++ + config FB_SM501 + tristate "Silicon Motion SM501 framebuffer support" + depends on FB && MFD_SM501 +diff -Nur linux-2.6.30/drivers/video/Makefile rt4ls/drivers/video/Makefile +--- linux-2.6.30/drivers/video/Makefile 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/drivers/video/Makefile 2009-06-12 16:28:47.484606170 +0200 +@@ -70,6 +70,7 @@ + obj-$(CONFIG_FB_TCX) += tcx.o sbuslib.o + obj-$(CONFIG_FB_LEO) += leo.o sbuslib.o + obj-$(CONFIG_FB_SGIVW) += sgivwfb.o ++obj-$(CONFIG_FB_SM7XX) += sm7xx/ + obj-$(CONFIG_FB_ACORN) += acornfb.o + obj-$(CONFIG_FB_ATARI) += atafb.o c2p_iplan2.o atafb_mfb.o \ + atafb_iplan2p2.o atafb_iplan2p4.o atafb_iplan2p8.o +diff -Nur linux-2.6.30/drivers/video/sm7xx/Makefile rt4ls/drivers/video/sm7xx/Makefile +--- linux-2.6.30/drivers/video/sm7xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/drivers/video/sm7xx/Makefile 2009-06-12 16:28:47.728622169 +0200 +@@ -0,0 +1,3 @@ ++obj-$(CONFIG_FB_SM7XX) += sm7xx.o ++ ++sm7xx-y := smtcfb.o +diff -Nur linux-2.6.30/drivers/video/sm7xx/smtc2d.c rt4ls/drivers/video/sm7xx/smtc2d.c +--- linux-2.6.30/drivers/video/sm7xx/smtc2d.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/drivers/video/sm7xx/smtc2d.c 2009-06-12 16:28:47.728622169 +0200 +@@ -0,0 +1,979 @@ ++/* ++ * smtc2d.c -- Silicon Motion SM7xx 2D drawing engine functions. ++ * ++ * Copyright (C) 2006 Silicon Motion Technology Corp. ++ * Author: Boyod boyod.yang@siliconmotion.com.cn ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ * ++ * Version 0.10.26192.21.01 ++ * - Add PowerPC support ++ * - Add 2D support for Lynx - ++ * Verified on 2.6.19.2 ++ * Boyod.yang <boyod.yang@siliconmotion.com.cn> ++ */ ++ ++unsigned char smtc_de_busy; ++ ++void SMTC_write2Dreg(unsigned long nOffset, unsigned long nData) ++{ ++ writel(nData, smtc_2DBaseAddress + nOffset); ++} ++ ++unsigned long SMTC_read2Dreg(unsigned long nOffset) ++{ ++ return readl(smtc_2DBaseAddress + nOffset); ++} ++ ++void SMTC_write2Ddataport(unsigned long nOffset, unsigned long nData) ++{ ++ writel(nData, smtc_2Ddataport + nOffset); ++} ++ ++/********************************************************************** ++ * ++ * deInit ++ * ++ * Purpose ++ * Drawing engine initialization. ++ * ++ **********************************************************************/ ++ ++void deInit(unsigned int nModeWidth, unsigned int nModeHeight, ++ unsigned int bpp) ++{ ++ /* Get current power configuration. */ ++ unsigned char clock; ++ clock = smtc_seqr(0x21); ++ ++ /* initialize global 'mutex lock' variable */ ++ smtc_de_busy = 0; ++ ++ /* Enable 2D Drawing Engine */ ++ smtc_seqw(0x21, clock & 0xF8); ++ ++ SMTC_write2Dreg(DE_CLIP_TL, ++ FIELD_VALUE(0, DE_CLIP_TL, TOP, 0) | ++ FIELD_SET(0, DE_CLIP_TL, STATUS, DISABLE) | ++ FIELD_SET(0, DE_CLIP_TL, INHIBIT, OUTSIDE) | ++ FIELD_VALUE(0, DE_CLIP_TL, LEFT, 0)); ++ ++ if (bpp >= 24) { ++ SMTC_write2Dreg(DE_PITCH, ++ FIELD_VALUE(0, DE_PITCH, DESTINATION, ++ nModeWidth * 3) | FIELD_VALUE(0, ++ DE_PITCH, ++ SOURCE, ++ nModeWidth ++ * 3)); ++ } else { ++ SMTC_write2Dreg(DE_PITCH, ++ FIELD_VALUE(0, DE_PITCH, DESTINATION, ++ nModeWidth) | FIELD_VALUE(0, ++ DE_PITCH, ++ SOURCE, ++ nModeWidth)); ++ } ++ ++ SMTC_write2Dreg(DE_WINDOW_WIDTH, ++ FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, ++ nModeWidth) | FIELD_VALUE(0, ++ DE_WINDOW_WIDTH, ++ SOURCE, ++ nModeWidth)); ++ ++ switch (bpp) { ++ case 8: ++ SMTC_write2Dreg(DE_STRETCH_FORMAT, ++ FIELD_SET(0, DE_STRETCH_FORMAT, PATTERN_XY, ++ NORMAL) | FIELD_VALUE(0, ++ DE_STRETCH_FORMAT, ++ PATTERN_Y, ++ 0) | ++ FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_X, ++ 0) | FIELD_SET(0, DE_STRETCH_FORMAT, ++ PIXEL_FORMAT, ++ 8) | FIELD_SET(0, ++ DE_STRETCH_FORMAT, ++ ADDRESSING, ++ XY) | ++ FIELD_VALUE(0, DE_STRETCH_FORMAT, ++ SOURCE_HEIGHT, 3)); ++ break; ++ case 24: ++ SMTC_write2Dreg(DE_STRETCH_FORMAT, ++ FIELD_SET(0, DE_STRETCH_FORMAT, PATTERN_XY, ++ NORMAL) | FIELD_VALUE(0, ++ DE_STRETCH_FORMAT, ++ PATTERN_Y, ++ 0) | ++ FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_X, ++ 0) | FIELD_SET(0, DE_STRETCH_FORMAT, ++ PIXEL_FORMAT, ++ 24) | FIELD_SET(0, ++ DE_STRETCH_FORMAT, ++ ADDRESSING, ++ XY) | ++ FIELD_VALUE(0, DE_STRETCH_FORMAT, ++ SOURCE_HEIGHT, 3)); ++ break; ++ case 16: ++ default: ++ SMTC_write2Dreg(DE_STRETCH_FORMAT, ++ FIELD_SET(0, DE_STRETCH_FORMAT, PATTERN_XY, ++ NORMAL) | FIELD_VALUE(0, ++ DE_STRETCH_FORMAT, ++ PATTERN_Y, ++ 0) | ++ FIELD_VALUE(0, DE_STRETCH_FORMAT, PATTERN_X, ++ 0) | FIELD_SET(0, DE_STRETCH_FORMAT, ++ PIXEL_FORMAT, ++ 16) | FIELD_SET(0, ++ DE_STRETCH_FORMAT, ++ ADDRESSING, ++ XY) | ++ FIELD_VALUE(0, DE_STRETCH_FORMAT, ++ SOURCE_HEIGHT, 3)); ++ break; ++ } ++ ++ SMTC_write2Dreg(DE_MASKS, ++ FIELD_VALUE(0, DE_MASKS, BYTE_MASK, 0xFFFF) | ++ FIELD_VALUE(0, DE_MASKS, BIT_MASK, 0xFFFF)); ++ SMTC_write2Dreg(DE_COLOR_COMPARE_MASK, ++ FIELD_VALUE(0, DE_COLOR_COMPARE_MASK, MASKS, \ ++ 0xFFFFFF)); ++ SMTC_write2Dreg(DE_COLOR_COMPARE, ++ FIELD_VALUE(0, DE_COLOR_COMPARE, COLOR, 0xFFFFFF)); ++} ++ ++void deVerticalLine(unsigned long dst_base, ++ unsigned long dst_pitch, ++ unsigned long nX, ++ unsigned long nY, ++ unsigned long dst_height, unsigned long nColor) ++{ ++ deWaitForNotBusy(); ++ ++ SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, ++ FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, ++ dst_base)); ++ ++ SMTC_write2Dreg(DE_PITCH, ++ FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) | ++ FIELD_VALUE(0, DE_PITCH, SOURCE, dst_pitch)); ++ ++ SMTC_write2Dreg(DE_WINDOW_WIDTH, ++ FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, ++ dst_pitch) | FIELD_VALUE(0, DE_WINDOW_WIDTH, ++ SOURCE, ++ dst_pitch)); ++ ++ SMTC_write2Dreg(DE_FOREGROUND, ++ FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor)); ++ ++ SMTC_write2Dreg(DE_DESTINATION, ++ FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | ++ FIELD_VALUE(0, DE_DESTINATION, X, nX) | ++ FIELD_VALUE(0, DE_DESTINATION, Y, nY)); ++ ++ SMTC_write2Dreg(DE_DIMENSION, ++ FIELD_VALUE(0, DE_DIMENSION, X, 1) | ++ FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height)); ++ ++ SMTC_write2Dreg(DE_CONTROL, ++ FIELD_SET(0, DE_CONTROL, STATUS, START) | ++ FIELD_SET(0, DE_CONTROL, DIRECTION, LEFT_TO_RIGHT) | ++ FIELD_SET(0, DE_CONTROL, MAJOR, Y) | ++ FIELD_SET(0, DE_CONTROL, STEP_X, NEGATIVE) | ++ FIELD_SET(0, DE_CONTROL, STEP_Y, POSITIVE) | ++ FIELD_SET(0, DE_CONTROL, LAST_PIXEL, OFF) | ++ FIELD_SET(0, DE_CONTROL, COMMAND, SHORT_STROKE) | ++ FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) | ++ FIELD_VALUE(0, DE_CONTROL, ROP, 0x0C)); ++ ++ smtc_de_busy = 1; ++} ++ ++void deHorizontalLine(unsigned long dst_base, ++ unsigned long dst_pitch, ++ unsigned long nX, ++ unsigned long nY, ++ unsigned long dst_width, unsigned long nColor) ++{ ++ deWaitForNotBusy(); ++ ++ SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, ++ FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, ++ dst_base)); ++ ++ SMTC_write2Dreg(DE_PITCH, ++ FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) | ++ FIELD_VALUE(0, DE_PITCH, SOURCE, dst_pitch)); ++ ++ SMTC_write2Dreg(DE_WINDOW_WIDTH, ++ FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, ++ dst_pitch) | FIELD_VALUE(0, DE_WINDOW_WIDTH, ++ SOURCE, ++ dst_pitch)); ++ SMTC_write2Dreg(DE_FOREGROUND, ++ FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor)); ++ SMTC_write2Dreg(DE_DESTINATION, ++ FIELD_SET(0, DE_DESTINATION, WRAP, ++ DISABLE) | FIELD_VALUE(0, DE_DESTINATION, X, ++ nX) | FIELD_VALUE(0, ++ DE_DESTINATION, ++ Y, ++ nY)); ++ SMTC_write2Dreg(DE_DIMENSION, ++ FIELD_VALUE(0, DE_DIMENSION, X, ++ dst_width) | FIELD_VALUE(0, DE_DIMENSION, ++ Y_ET, 1)); ++ SMTC_write2Dreg(DE_CONTROL, ++ FIELD_SET(0, DE_CONTROL, STATUS, START) | FIELD_SET(0, ++ DE_CONTROL, ++ DIRECTION, ++ RIGHT_TO_LEFT) ++ | FIELD_SET(0, DE_CONTROL, MAJOR, X) | FIELD_SET(0, ++ DE_CONTROL, ++ STEP_X, ++ POSITIVE) ++ | FIELD_SET(0, DE_CONTROL, STEP_Y, ++ NEGATIVE) | FIELD_SET(0, DE_CONTROL, ++ LAST_PIXEL, ++ OFF) | FIELD_SET(0, ++ DE_CONTROL, ++ COMMAND, ++ SHORT_STROKE) ++ | FIELD_SET(0, DE_CONTROL, ROP_SELECT, ++ ROP2) | FIELD_VALUE(0, DE_CONTROL, ROP, ++ 0x0C)); ++ ++ smtc_de_busy = 1; ++} ++ ++void deLine(unsigned long dst_base, ++ unsigned long dst_pitch, ++ unsigned long nX1, ++ unsigned long nY1, ++ unsigned long nX2, unsigned long nY2, unsigned long nColor) ++{ ++ unsigned long nCommand = ++ FIELD_SET(0, DE_CONTROL, STATUS, START) | ++ FIELD_SET(0, DE_CONTROL, DIRECTION, LEFT_TO_RIGHT) | ++ FIELD_SET(0, DE_CONTROL, MAJOR, X) | ++ FIELD_SET(0, DE_CONTROL, STEP_X, POSITIVE) | ++ FIELD_SET(0, DE_CONTROL, STEP_Y, POSITIVE) | ++ FIELD_SET(0, DE_CONTROL, LAST_PIXEL, OFF) | ++ FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) | ++ FIELD_VALUE(0, DE_CONTROL, ROP, 0x0C); ++ unsigned long DeltaX; ++ unsigned long DeltaY; ++ ++ /* Calculate delta X */ ++ if (nX1 <= nX2) ++ DeltaX = nX2 - nX1; ++ else { ++ DeltaX = nX1 - nX2; ++ nCommand = FIELD_SET(nCommand, DE_CONTROL, STEP_X, NEGATIVE); ++ } ++ ++ /* Calculate delta Y */ ++ if (nY1 <= nY2) ++ DeltaY = nY2 - nY1; ++ else { ++ DeltaY = nY1 - nY2; ++ nCommand = FIELD_SET(nCommand, DE_CONTROL, STEP_Y, NEGATIVE); ++ } ++ ++ /* Determine the major axis */ ++ if (DeltaX < DeltaY) ++ nCommand = FIELD_SET(nCommand, DE_CONTROL, MAJOR, Y); ++ ++ /* Vertical line? */ ++ if (nX1 == nX2) ++ deVerticalLine(dst_base, dst_pitch, nX1, nY1, DeltaY, nColor); ++ ++ /* Horizontal line? */ ++ else if (nY1 == nY2) ++ deHorizontalLine(dst_base, dst_pitch, nX1, nY1, \ ++ DeltaX, nColor); ++ ++ /* Diagonal line? */ ++ else if (DeltaX == DeltaY) { ++ deWaitForNotBusy(); ++ ++ SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, ++ FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ++ ADDRESS, dst_base)); ++ ++ SMTC_write2Dreg(DE_PITCH, ++ FIELD_VALUE(0, DE_PITCH, DESTINATION, ++ dst_pitch) | FIELD_VALUE(0, ++ DE_PITCH, ++ SOURCE, ++ dst_pitch)); ++ ++ SMTC_write2Dreg(DE_WINDOW_WIDTH, ++ FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, ++ dst_pitch) | FIELD_VALUE(0, ++ DE_WINDOW_WIDTH, ++ SOURCE, ++ dst_pitch)); ++ ++ SMTC_write2Dreg(DE_FOREGROUND, ++ FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor)); ++ ++ SMTC_write2Dreg(DE_DESTINATION, ++ FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | ++ FIELD_VALUE(0, DE_DESTINATION, X, 1) | ++ FIELD_VALUE(0, DE_DESTINATION, Y, nY1)); ++ ++ SMTC_write2Dreg(DE_DIMENSION, ++ FIELD_VALUE(0, DE_DIMENSION, X, 1) | ++ FIELD_VALUE(0, DE_DIMENSION, Y_ET, DeltaX)); ++ ++ SMTC_write2Dreg(DE_CONTROL, ++ FIELD_SET(nCommand, DE_CONTROL, COMMAND, ++ SHORT_STROKE)); ++ } ++ ++ /* Generic line */ ++ else { ++ unsigned int k1, k2, et, w; ++ if (DeltaX < DeltaY) { ++ k1 = 2 * DeltaX; ++ et = k1 - DeltaY; ++ k2 = et - DeltaY; ++ w = DeltaY + 1; ++ } else { ++ k1 = 2 * DeltaY; ++ et = k1 - DeltaX; ++ k2 = et - DeltaX; ++ w = DeltaX + 1; ++ } ++ ++ deWaitForNotBusy(); ++ ++ SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, ++ FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ++ ADDRESS, dst_base)); ++ ++ SMTC_write2Dreg(DE_PITCH, ++ FIELD_VALUE(0, DE_PITCH, DESTINATION, ++ dst_pitch) | FIELD_VALUE(0, ++ DE_PITCH, ++ SOURCE, ++ dst_pitch)); ++ ++ SMTC_write2Dreg(DE_WINDOW_WIDTH, ++ FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, ++ dst_pitch) | FIELD_VALUE(0, ++ DE_WINDOW_WIDTH, ++ SOURCE, ++ dst_pitch)); ++ ++ SMTC_write2Dreg(DE_FOREGROUND, ++ FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor)); ++ ++ SMTC_write2Dreg(DE_SOURCE, ++ FIELD_SET(0, DE_SOURCE, WRAP, DISABLE) | ++ FIELD_VALUE(0, DE_SOURCE, X_K1, k1) | ++ FIELD_VALUE(0, DE_SOURCE, Y_K2, k2)); ++ ++ SMTC_write2Dreg(DE_DESTINATION, ++ FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | ++ FIELD_VALUE(0, DE_DESTINATION, X, nX1) | ++ FIELD_VALUE(0, DE_DESTINATION, Y, nY1)); ++ ++ SMTC_write2Dreg(DE_DIMENSION, ++ FIELD_VALUE(0, DE_DIMENSION, X, w) | ++ FIELD_VALUE(0, DE_DIMENSION, Y_ET, et)); ++ ++ SMTC_write2Dreg(DE_CONTROL, ++ FIELD_SET(nCommand, DE_CONTROL, COMMAND, ++ LINE_DRAW)); ++ } ++ ++ smtc_de_busy = 1; ++} ++ ++void deFillRect(unsigned long dst_base, ++ unsigned long dst_pitch, ++ unsigned long dst_X, ++ unsigned long dst_Y, ++ unsigned long dst_width, ++ unsigned long dst_height, unsigned long nColor) ++{ ++ deWaitForNotBusy(); ++ ++ SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, ++ FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, ++ dst_base)); ++ ++ if (dst_pitch) { ++ SMTC_write2Dreg(DE_PITCH, ++ FIELD_VALUE(0, DE_PITCH, DESTINATION, ++ dst_pitch) | FIELD_VALUE(0, ++ DE_PITCH, ++ SOURCE, ++ dst_pitch)); ++ ++ SMTC_write2Dreg(DE_WINDOW_WIDTH, ++ FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, ++ dst_pitch) | FIELD_VALUE(0, ++ DE_WINDOW_WIDTH, ++ SOURCE, ++ dst_pitch)); ++ } ++ ++ SMTC_write2Dreg(DE_FOREGROUND, ++ FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor)); ++ ++ SMTC_write2Dreg(DE_DESTINATION, ++ FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | ++ FIELD_VALUE(0, DE_DESTINATION, X, dst_X) | ++ FIELD_VALUE(0, DE_DESTINATION, Y, dst_Y)); ++ ++ SMTC_write2Dreg(DE_DIMENSION, ++ FIELD_VALUE(0, DE_DIMENSION, X, dst_width) | ++ FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height)); ++ ++ SMTC_write2Dreg(DE_CONTROL, ++ FIELD_SET(0, DE_CONTROL, STATUS, START) | ++ FIELD_SET(0, DE_CONTROL, DIRECTION, LEFT_TO_RIGHT) | ++ FIELD_SET(0, DE_CONTROL, LAST_PIXEL, OFF) | ++ FIELD_SET(0, DE_CONTROL, COMMAND, RECTANGLE_FILL) | ++ FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) | ++ FIELD_VALUE(0, DE_CONTROL, ROP, 0x0C)); ++ ++ smtc_de_busy = 1; ++} ++ ++/********************************************************************** ++ * ++ * deRotatePattern ++ * ++ * Purpose ++ * Rotate the given pattern if necessary ++ * ++ * Parameters ++ * [in] ++ * pPattern - Pointer to DE_SURFACE structure containing ++ * pattern attributes ++ * patternX - X position (0-7) of pattern origin ++ * patternY - Y position (0-7) of pattern origin ++ * ++ * [out] ++ * pattern_dstaddr - Pointer to pre-allocated buffer containing ++ * rotated pattern ++ * ++ **********************************************************************/ ++void deRotatePattern(unsigned char *pattern_dstaddr, ++ unsigned long pattern_src_addr, ++ unsigned long pattern_BPP, ++ unsigned long pattern_stride, int patternX, int patternY) ++{ ++ unsigned int i; ++ unsigned long pattern[PATTERN_WIDTH * PATTERN_HEIGHT]; ++ unsigned int x, y; ++ unsigned char *pjPatByte; ++ ++ if (pattern_dstaddr != NULL) { ++ deWaitForNotBusy(); ++ ++ if (patternX || patternY) { ++ /* Rotate pattern */ ++ pjPatByte = (unsigned char *)pattern; ++ ++ switch (pattern_BPP) { ++ case 8: ++ { ++ for (y = 0; y < 8; y++) { ++ unsigned char *pjBuffer = ++ pattern_dstaddr + ++ ((patternY + y) & 7) * 8; ++ for (x = 0; x < 8; x++) { ++ pjBuffer[(patternX + ++ x) & 7] = ++ pjPatByte[x]; ++ } ++ pjPatByte += pattern_stride; ++ } ++ break; ++ } ++ ++ case 16: ++ { ++ for (y = 0; y < 8; y++) { ++ unsigned short *pjBuffer = ++ (unsigned short *) ++ pattern_dstaddr + ++ ((patternY + y) & 7) * 8; ++ for (x = 0; x < 8; x++) { ++ pjBuffer[(patternX + ++ x) & 7] = ++ ((unsigned short *) ++ pjPatByte)[x]; ++ } ++ pjPatByte += pattern_stride; ++ } ++ break; ++ } ++ ++ case 32: ++ { ++ for (y = 0; y < 8; y++) { ++ unsigned long *pjBuffer = ++ (unsigned long *) ++ pattern_dstaddr + ++ ((patternY + y) & 7) * 8; ++ for (x = 0; x < 8; x++) { ++ pjBuffer[(patternX + ++ x) & 7] = ++ ((unsigned long *) ++ pjPatByte)[x]; ++ } ++ pjPatByte += pattern_stride; ++ } ++ break; ++ } ++ } ++ } else { ++ /*Don't rotate,just copy pattern into pattern_dstaddr*/ ++ for (i = 0; i < (pattern_BPP * 2); i++) { ++ ((unsigned long *)pattern_dstaddr)[i] = ++ pattern[i]; ++ } ++ } ++ ++ } ++} ++ ++/********************************************************************** ++ * ++ * deCopy ++ * ++ * Purpose ++ * Copy a rectangular area of the source surface to a destination surface ++ * ++ * Remarks ++ * Source bitmap must have the same color depth (BPP) as the destination ++ * bitmap. ++ * ++**********************************************************************/ ++void deCopy(unsigned long dst_base, ++ unsigned long dst_pitch, ++ unsigned long dst_BPP, ++ unsigned long dst_X, ++ unsigned long dst_Y, ++ unsigned long dst_width, ++ unsigned long dst_height, ++ unsigned long src_base, ++ unsigned long src_pitch, ++ unsigned long src_X, ++ unsigned long src_Y, pTransparent pTransp, unsigned char nROP2) ++{ ++ unsigned long nDirection = 0; ++ unsigned long nTransparent = 0; ++ /* Direction of ROP2 operation: ++ * 1 = Left to Right, ++ * (-1) = Right to Left ++ */ ++ unsigned long opSign = 1; ++ /* xWidth is in pixels */ ++ unsigned long xWidth = 192 / (dst_BPP / 8); ++ unsigned long de_ctrl = 0; ++ ++ deWaitForNotBusy(); ++ ++ SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, ++ FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS, ++ dst_base)); ++ ++ SMTC_write2Dreg(DE_WINDOW_SOURCE_BASE, ++ FIELD_VALUE(0, DE_WINDOW_SOURCE_BASE, ADDRESS, ++ src_base)); ++ ++ if (dst_pitch && src_pitch) { ++ SMTC_write2Dreg(DE_PITCH, ++ FIELD_VALUE(0, DE_PITCH, DESTINATION, ++ dst_pitch) | FIELD_VALUE(0, ++ DE_PITCH, ++ SOURCE, ++ src_pitch)); ++ ++ SMTC_write2Dreg(DE_WINDOW_WIDTH, ++ FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, ++ dst_pitch) | FIELD_VALUE(0, ++ DE_WINDOW_WIDTH, ++ SOURCE, ++ src_pitch)); ++ } ++ ++ /* Set transparent bits if necessary */ ++ if (pTransp != NULL) { ++ nTransparent = ++ pTransp->match | pTransp->select | pTransp->control; ++ ++ /* Set color compare register */ ++ SMTC_write2Dreg(DE_COLOR_COMPARE, ++ FIELD_VALUE(0, DE_COLOR_COMPARE, COLOR, ++ pTransp->color)); ++ } ++ ++ /* Determine direction of operation */ ++ if (src_Y < dst_Y) { ++ /* +----------+ ++ |S | ++ | +----------+ ++ | | | | ++ | | | | ++ +---|------+ | ++ | D | ++ +----------+ */ ++ ++ nDirection = BOTTOM_TO_TOP; ++ } else if (src_Y > dst_Y) { ++ /* +----------+ ++ |D | ++ | +----------+ ++ | | | | ++ | | | | ++ +---|------+ | ++ | S | ++ +----------+ */ ++ ++ nDirection = TOP_TO_BOTTOM; ++ } else { ++ /* src_Y == dst_Y */ ++ ++ if (src_X <= dst_X) { ++ /* +------+---+------+ ++ |S | | D| ++ | | | | ++ | | | | ++ | | | | ++ +------+---+------+ */ ++ ++ nDirection = RIGHT_TO_LEFT; ++ } else { ++ /* src_X > dst_X */ ++ ++ /* +------+---+------+ ++ |D | | S| ++ | | | | ++ | | | | ++ | | | | ++ +------+---+------+ */ ++ ++ nDirection = LEFT_TO_RIGHT; ++ } ++ } ++ ++ if ((nDirection == BOTTOM_TO_TOP) || (nDirection == RIGHT_TO_LEFT)) { ++ src_X += dst_width - 1; ++ src_Y += dst_height - 1; ++ dst_X += dst_width - 1; ++ dst_Y += dst_height - 1; ++ opSign = (-1); ++ } ++ ++ if (dst_BPP >= 24) { ++ src_X *= 3; ++ src_Y *= 3; ++ dst_X *= 3; ++ dst_Y *= 3; ++ dst_width *= 3; ++ if ((nDirection == BOTTOM_TO_TOP) ++ || (nDirection == RIGHT_TO_LEFT)) { ++ src_X += 2; ++ dst_X += 2; ++ } ++ } ++ ++ /* Workaround for 192 byte hw bug */ ++ if ((nROP2 != 0x0C) && ((dst_width * (dst_BPP / 8)) >= 192)) { ++ /* ++ * Perform the ROP2 operation in chunks of (xWidth * ++ * dst_height) ++ */ ++ while (1) { ++ deWaitForNotBusy(); ++ ++ SMTC_write2Dreg(DE_SOURCE, ++ FIELD_SET(0, DE_SOURCE, WRAP, DISABLE) | ++ FIELD_VALUE(0, DE_SOURCE, X_K1, src_X) | ++ FIELD_VALUE(0, DE_SOURCE, Y_K2, src_Y)); ++ ++ SMTC_write2Dreg(DE_DESTINATION, ++ FIELD_SET(0, DE_DESTINATION, WRAP, ++ DISABLE) | FIELD_VALUE(0, ++ DE_DESTINATION, ++ X, ++ dst_X) ++ | FIELD_VALUE(0, DE_DESTINATION, Y, ++ dst_Y)); ++ ++ SMTC_write2Dreg(DE_DIMENSION, ++ FIELD_VALUE(0, DE_DIMENSION, X, ++ xWidth) | FIELD_VALUE(0, ++ DE_DIMENSION, ++ Y_ET, ++ dst_height)); ++ ++ de_ctrl = ++ FIELD_VALUE(0, DE_CONTROL, ROP, ++ nROP2) | nTransparent | FIELD_SET(0, ++ DE_CONTROL, ++ ROP_SELECT, ++ ROP2) ++ | FIELD_SET(0, DE_CONTROL, COMMAND, ++ BITBLT) | ((nDirection == ++ 1) ? FIELD_SET(0, ++ DE_CONTROL, ++ DIRECTION, ++ RIGHT_TO_LEFT) ++ : FIELD_SET(0, DE_CONTROL, ++ DIRECTION, ++ LEFT_TO_RIGHT)) | ++ FIELD_SET(0, DE_CONTROL, STATUS, START); ++ ++ SMTC_write2Dreg(DE_CONTROL, de_ctrl); ++ ++ src_X += (opSign * xWidth); ++ dst_X += (opSign * xWidth); ++ dst_width -= xWidth; ++ ++ if (dst_width <= 0) { ++ /* ROP2 operation is complete */ ++ break; ++ } ++ ++ if (xWidth > dst_width) ++ xWidth = dst_width; ++ } ++ } else { ++ deWaitForNotBusy(); ++ SMTC_write2Dreg(DE_SOURCE, ++ FIELD_SET(0, DE_SOURCE, WRAP, DISABLE) | ++ FIELD_VALUE(0, DE_SOURCE, X_K1, src_X) | ++ FIELD_VALUE(0, DE_SOURCE, Y_K2, src_Y)); ++ ++ SMTC_write2Dreg(DE_DESTINATION, ++ FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | ++ FIELD_VALUE(0, DE_DESTINATION, X, dst_X) | ++ FIELD_VALUE(0, DE_DESTINATION, Y, dst_Y)); ++ ++ SMTC_write2Dreg(DE_DIMENSION, ++ FIELD_VALUE(0, DE_DIMENSION, X, dst_width) | ++ FIELD_VALUE(0, DE_DIMENSION, Y_ET, dst_height)); ++ ++ de_ctrl = FIELD_VALUE(0, DE_CONTROL, ROP, nROP2) | ++ nTransparent | ++ FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) | ++ FIELD_SET(0, DE_CONTROL, COMMAND, BITBLT) | ++ ((nDirection == 1) ? FIELD_SET(0, DE_CONTROL, DIRECTION, ++ RIGHT_TO_LEFT) ++ : FIELD_SET(0, DE_CONTROL, DIRECTION, ++ LEFT_TO_RIGHT)) | FIELD_SET(0, DE_CONTROL, ++ STATUS, START); ++ SMTC_write2Dreg(DE_CONTROL, de_ctrl); ++ } ++ ++ smtc_de_busy = 1; ++} ++ ++/* ++ * This function sets the pixel format that will apply to the 2D Engine. ++ */ ++void deSetPixelFormat(unsigned long bpp) ++{ ++ unsigned long de_format; ++ ++ de_format = SMTC_read2Dreg(DE_STRETCH_FORMAT); ++ ++ switch (bpp) { ++ case 8: ++ de_format = ++ FIELD_SET(de_format, DE_STRETCH_FORMAT, PIXEL_FORMAT, 8); ++ break; ++ default: ++ case 16: ++ de_format = ++ FIELD_SET(de_format, DE_STRETCH_FORMAT, PIXEL_FORMAT, 16); ++ break; ++ case 32: ++ de_format = ++ FIELD_SET(de_format, DE_STRETCH_FORMAT, PIXEL_FORMAT, 32); ++ break; ++ } ++ ++ SMTC_write2Dreg(DE_STRETCH_FORMAT, de_format); ++} ++ ++/* ++ * System memory to Video memory monochrome expansion. ++ * ++ * Source is monochrome image in system memory. This function expands the ++ * monochrome data to color image in video memory. ++ */ ++ ++long deSystemMem2VideoMemMonoBlt(const char *pSrcbuf, ++ long srcDelta, ++ unsigned long startBit, ++ unsigned long dBase, ++ unsigned long dPitch, ++ unsigned long bpp, ++ unsigned long dx, unsigned long dy, ++ unsigned long width, unsigned long height, ++ unsigned long fColor, ++ unsigned long bColor, ++ unsigned long rop2) { ++ unsigned long bytePerPixel; ++ unsigned long ulBytesPerScan; ++ unsigned long ul4BytesPerScan; ++ unsigned long ulBytesRemain; ++ unsigned long de_ctrl = 0; ++ unsigned char ajRemain[4]; ++ long i, j; ++ ++ bytePerPixel = bpp / 8; ++ ++ /* Just make sure the start bit is within legal range */ ++ startBit &= 7; ++ ++ ulBytesPerScan = (width + startBit + 7) / 8; ++ ul4BytesPerScan = ulBytesPerScan & ~3; ++ ulBytesRemain = ulBytesPerScan & 3; ++ ++ if (smtc_de_busy) ++ deWaitForNotBusy(); ++ ++ /* ++ * 2D Source Base. Use 0 for HOST Blt. ++ */ ++ ++ SMTC_write2Dreg(DE_WINDOW_SOURCE_BASE, 0); ++ ++ /* ++ * 2D Destination Base. ++ * ++ * It is an address offset (128 bit aligned) from the beginning of ++ * frame buffer. ++ */ ++ ++ SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE, dBase); ++ ++ if (dPitch) { ++ ++ /* ++ * Program pitch (distance between the 1st points of two ++ * adjacent lines). ++ * ++ * Note that input pitch is BYTE value, but the 2D Pitch ++ * register uses pixel values. Need Byte to pixel convertion. ++ */ ++ ++ SMTC_write2Dreg(DE_PITCH, ++ FIELD_VALUE(0, DE_PITCH, DESTINATION, ++ dPitch / ++ bytePerPixel) | FIELD_VALUE(0, ++ DE_PITCH, ++ SOURCE, ++ dPitch / ++ bytePerPixel)); ++ ++ /* Screen Window width in Pixels. ++ * ++ * 2D engine uses this value to calculate the linear address in ++ * frame buffer for a given point. ++ */ ++ ++ SMTC_write2Dreg(DE_WINDOW_WIDTH, ++ FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION, ++ (dPitch / ++ bytePerPixel)) | FIELD_VALUE(0, ++ DE_WINDOW_WIDTH, ++ SOURCE, ++ (dPitch ++ / ++ bytePerPixel))); ++ } ++ /* Note: For 2D Source in Host Write, only X_K1 field is needed, and ++ * Y_K2 field is not used. For mono bitmap, use startBit for X_K1. ++ */ ++ ++ SMTC_write2Dreg(DE_SOURCE, ++ FIELD_SET(0, DE_SOURCE, WRAP, DISABLE) | ++ FIELD_VALUE(0, DE_SOURCE, X_K1, startBit) | ++ FIELD_VALUE(0, DE_SOURCE, Y_K2, 0)); ++ ++ SMTC_write2Dreg(DE_DESTINATION, ++ FIELD_SET(0, DE_DESTINATION, WRAP, DISABLE) | ++ FIELD_VALUE(0, DE_DESTINATION, X, dx) | ++ FIELD_VALUE(0, DE_DESTINATION, Y, dy)); ++ ++ SMTC_write2Dreg(DE_DIMENSION, ++ FIELD_VALUE(0, DE_DIMENSION, X, width) | ++ FIELD_VALUE(0, DE_DIMENSION, Y_ET, height)); ++ ++ SMTC_write2Dreg(DE_FOREGROUND, fColor); ++ SMTC_write2Dreg(DE_BACKGROUND, bColor); ++ ++ if (bpp) ++ deSetPixelFormat(bpp); ++ /* Set the pixel format of the destination */ ++ ++ de_ctrl = FIELD_VALUE(0, DE_CONTROL, ROP, rop2) | ++ FIELD_SET(0, DE_CONTROL, ROP_SELECT, ROP2) | ++ FIELD_SET(0, DE_CONTROL, COMMAND, HOST_WRITE) | ++ FIELD_SET(0, DE_CONTROL, HOST, MONO) | ++ FIELD_SET(0, DE_CONTROL, STATUS, START); ++ ++ SMTC_write2Dreg(DE_CONTROL, de_ctrl | deGetTransparency()); ++ ++ /* Write MONO data (line by line) to 2D Engine data port */ ++ for (i = 0; i < height; i++) { ++ /* For each line, send the data in chunks of 4 bytes */ ++ for (j = 0; j < (ul4BytesPerScan / 4); j++) ++ SMTC_write2Ddataport(0, ++ *(unsigned long *)(pSrcbuf + ++ (j * 4))); ++ ++ if (ulBytesRemain) { ++ memcpy(ajRemain, pSrcbuf + ul4BytesPerScan, ++ ulBytesRemain); ++ SMTC_write2Ddataport(0, *(unsigned long *)ajRemain); ++ } ++ ++ pSrcbuf += srcDelta; ++ } ++ smtc_de_busy = 1; ++ ++ return 0; ++} ++ ++/* ++ * This function gets the transparency status from DE_CONTROL register. ++ * It returns a double word with the transparent fields properly set, ++ * while other fields are 0. ++ */ ++unsigned long deGetTransparency(void) ++{ ++ unsigned long de_ctrl; ++ ++ de_ctrl = SMTC_read2Dreg(DE_CONTROL); ++ ++ de_ctrl &= ++ FIELD_MASK(DE_CONTROL_TRANSPARENCY_MATCH) | ++ FIELD_MASK(DE_CONTROL_TRANSPARENCY_SELECT) | ++ FIELD_MASK(DE_CONTROL_TRANSPARENCY); ++ ++ return de_ctrl; ++} +diff -Nur linux-2.6.30/drivers/video/sm7xx/smtc2d.h rt4ls/drivers/video/sm7xx/smtc2d.h +--- linux-2.6.30/drivers/video/sm7xx/smtc2d.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/drivers/video/sm7xx/smtc2d.h 2009-06-12 16:28:47.728622169 +0200 +@@ -0,0 +1,530 @@ ++/* ++ * smtc2d.h -- Silicon Motion SM7xx 2D drawing engine functions. ++ * ++ * Copyright (C) 2006 Silicon Motion Technology Corp. ++ * Author: Ge Wang, gewang@siliconmotion.com ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ */ ++ ++#ifndef NULL ++#define NULL 0 ++#endif ++ ++/* Internal macros */ ++ ++#define _F_START(f) (0 ? f) ++#define _F_END(f) (1 ? f) ++#define _F_SIZE(f) (1 + _F_END(f) - _F_START(f)) ++#define _F_MASK(f) (((1ULL << _F_SIZE(f)) - 1) << _F_START(f)) ++#define _F_NORMALIZE(v, f) (((v) & _F_MASK(f)) >> _F_START(f)) ++#define _F_DENORMALIZE(v, f) (((v) << _F_START(f)) & _F_MASK(f)) ++ ++/* Global macros */ ++ ++#define FIELD_GET(x, reg, field) \ ++( \ ++ _F_NORMALIZE((x), reg ## _ ## field) \ ++) ++ ++#define FIELD_SET(x, reg, field, value) \ ++( \ ++ (x & ~_F_MASK(reg ## _ ## field)) \ ++ | _F_DENORMALIZE(reg ## _ ## field ## _ ## value, reg ## _ ## field) \ ++) ++ ++#define FIELD_VALUE(x, reg, field, value) \ ++( \ ++ (x & ~_F_MASK(reg ## _ ## field)) \ ++ | _F_DENORMALIZE(value, reg ## _ ## field) \ ++) ++ ++#define FIELD_CLEAR(reg, field) \ ++( \ ++ ~_F_MASK(reg ## _ ## field) \ ++) ++ ++/* Field Macros */ ++ ++#define FIELD_START(field) (0 ? field) ++#define FIELD_END(field) (1 ? field) ++#define FIELD_SIZE(field) \ ++ (1 + FIELD_END(field) - FIELD_START(field)) ++ ++#define FIELD_MASK(field) \ ++ (((1 << (FIELD_SIZE(field)-1)) \ ++ | ((1 << (FIELD_SIZE(field)-1)) - 1)) \ ++ << FIELD_START(field)) ++ ++#define FIELD_NORMALIZE(reg, field) \ ++ (((reg) & FIELD_MASK(field)) >> FIELD_START(field)) ++ ++#define FIELD_DENORMALIZE(field, value) \ ++ (((value) << FIELD_START(field)) & FIELD_MASK(field)) ++ ++#define FIELD_INIT(reg, field, value) \ ++ FIELD_DENORMALIZE(reg ## _ ## field, \ ++ reg ## _ ## field ## _ ## value) ++ ++#define FIELD_INIT_VAL(reg, field, value) \ ++ (FIELD_DENORMALIZE(reg ## _ ## field, value)) ++ ++#define FIELD_VAL_SET(x, r, f, v) ({ \ ++ x = (x & ~FIELD_MASK(r ## _ ## f)) \ ++ | FIELD_DENORMALIZE(r ## _ ## f, r ## _ ## f ## _ ## v) \ ++}) ++ ++#define RGB(r, g, b) ((unsigned long)(((r) << 16) | ((g) << 8) | (b))) ++ ++/* Transparent info definition */ ++typedef struct { ++ unsigned long match; /* Matching pixel is OPAQUE/TRANSPARENT */ ++ unsigned long select; /* Transparency controlled by SRC/DST */ ++ unsigned long control; /* ENABLE/DISABLE transparency */ ++ unsigned long color; /* Transparent color */ ++} Transparent, *pTransparent; ++ ++#define PIXEL_DEPTH_1_BP 0 /* 1 bit per pixel */ ++#define PIXEL_DEPTH_8_BPP 1 /* 8 bits per pixel */ ++#define PIXEL_DEPTH_16_BPP 2 /* 16 bits per pixel */ ++#define PIXEL_DEPTH_32_BPP 3 /* 32 bits per pixel */ ++#define PIXEL_DEPTH_YUV422 8 /* 16 bits per pixel YUV422 */ ++#define PIXEL_DEPTH_YUV420 9 /* 16 bits per pixel YUV420 */ ++ ++#define PATTERN_WIDTH 8 ++#define PATTERN_HEIGHT 8 ++ ++#define TOP_TO_BOTTOM 0 ++#define BOTTOM_TO_TOP 1 ++#define RIGHT_TO_LEFT BOTTOM_TO_TOP ++#define LEFT_TO_RIGHT TOP_TO_BOTTOM ++ ++/* Constants used in Transparent structure */ ++#define MATCH_OPAQUE 0x00000000 ++#define MATCH_TRANSPARENT 0x00000400 ++#define SOURCE 0x00000000 ++#define DESTINATION 0x00000200 ++ ++/* 2D registers. */ ++ ++#define DE_SOURCE 0x000000 ++#define DE_SOURCE_WRAP 31 : 31 ++#define DE_SOURCE_WRAP_DISABLE 0 ++#define DE_SOURCE_WRAP_ENABLE 1 ++#define DE_SOURCE_X_K1 29 : 16 ++#define DE_SOURCE_Y_K2 15 : 0 ++ ++#define DE_DESTINATION 0x000004 ++#define DE_DESTINATION_WRAP 31 : 31 ++#define DE_DESTINATION_WRAP_DISABLE 0 ++#define DE_DESTINATION_WRAP_ENABLE 1 ++#define DE_DESTINATION_X 28 : 16 ++#define DE_DESTINATION_Y 15 : 0 ++ ++#define DE_DIMENSION 0x000008 ++#define DE_DIMENSION_X 28 : 16 ++#define DE_DIMENSION_Y_ET 15 : 0 ++ ++#define DE_CONTROL 0x00000C ++#define DE_CONTROL_STATUS 31 : 31 ++#define DE_CONTROL_STATUS_STOP 0 ++#define DE_CONTROL_STATUS_START 1 ++#define DE_CONTROL_PATTERN 30 : 30 ++#define DE_CONTROL_PATTERN_MONO 0 ++#define DE_CONTROL_PATTERN_COLOR 1 ++#define DE_CONTROL_UPDATE_DESTINATION_X 29 : 29 ++#define DE_CONTROL_UPDATE_DESTINATION_X_DISABLE 0 ++#define DE_CONTROL_UPDATE_DESTINATION_X_ENABLE 1 ++#define DE_CONTROL_QUICK_START 28 : 28 ++#define DE_CONTROL_QUICK_START_DISABLE 0 ++#define DE_CONTROL_QUICK_START_ENABLE 1 ++#define DE_CONTROL_DIRECTION 27 : 27 ++#define DE_CONTROL_DIRECTION_LEFT_TO_RIGHT 0 ++#define DE_CONTROL_DIRECTION_RIGHT_TO_LEFT 1 ++#define DE_CONTROL_MAJOR 26 : 26 ++#define DE_CONTROL_MAJOR_X 0 ++#define DE_CONTROL_MAJOR_Y 1 ++#define DE_CONTROL_STEP_X 25 : 25 ++#define DE_CONTROL_STEP_X_POSITIVE 1 ++#define DE_CONTROL_STEP_X_NEGATIVE 0 ++#define DE_CONTROL_STEP_Y 24 : 24 ++#define DE_CONTROL_STEP_Y_POSITIVE 1 ++#define DE_CONTROL_STEP_Y_NEGATIVE 0 ++#define DE_CONTROL_STRETCH 23 : 23 ++#define DE_CONTROL_STRETCH_DISABLE 0 ++#define DE_CONTROL_STRETCH_ENABLE 1 ++#define DE_CONTROL_HOST 22 : 22 ++#define DE_CONTROL_HOST_COLOR 0 ++#define DE_CONTROL_HOST_MONO 1 ++#define DE_CONTROL_LAST_PIXEL 21 : 21 ++#define DE_CONTROL_LAST_PIXEL_OFF 0 ++#define DE_CONTROL_LAST_PIXEL_ON 1 ++#define DE_CONTROL_COMMAND 20 : 16 ++#define DE_CONTROL_COMMAND_BITBLT 0 ++#define DE_CONTROL_COMMAND_RECTANGLE_FILL 1 ++#define DE_CONTROL_COMMAND_DE_TILE 2 ++#define DE_CONTROL_COMMAND_TRAPEZOID_FILL 3 ++#define DE_CONTROL_COMMAND_ALPHA_BLEND 4 ++#define DE_CONTROL_COMMAND_RLE_STRIP 5 ++#define DE_CONTROL_COMMAND_SHORT_STROKE 6 ++#define DE_CONTROL_COMMAND_LINE_DRAW 7 ++#define DE_CONTROL_COMMAND_HOST_WRITE 8 ++#define DE_CONTROL_COMMAND_HOST_READ 9 ++#define DE_CONTROL_COMMAND_HOST_WRITE_BOTTOM_UP 10 ++#define DE_CONTROL_COMMAND_ROTATE 11 ++#define DE_CONTROL_COMMAND_FONT 12 ++#define DE_CONTROL_COMMAND_TEXTURE_LOAD 15 ++#define DE_CONTROL_ROP_SELECT 15 : 15 ++#define DE_CONTROL_ROP_SELECT_ROP3 0 ++#define DE_CONTROL_ROP_SELECT_ROP2 1 ++#define DE_CONTROL_ROP2_SOURCE 14 : 14 ++#define DE_CONTROL_ROP2_SOURCE_BITMAP 0 ++#define DE_CONTROL_ROP2_SOURCE_PATTERN 1 ++#define DE_CONTROL_MONO_DATA 13 : 12 ++#define DE_CONTROL_MONO_DATA_NOT_PACKED 0 ++#define DE_CONTROL_MONO_DATA_8_PACKED 1 ++#define DE_CONTROL_MONO_DATA_16_PACKED 2 ++#define DE_CONTROL_MONO_DATA_32_PACKED 3 ++#define DE_CONTROL_REPEAT_ROTATE 11 : 11 ++#define DE_CONTROL_REPEAT_ROTATE_DISABLE 0 ++#define DE_CONTROL_REPEAT_ROTATE_ENABLE 1 ++#define DE_CONTROL_TRANSPARENCY_MATCH 10 : 10 ++#define DE_CONTROL_TRANSPARENCY_MATCH_OPAQUE 0 ++#define DE_CONTROL_TRANSPARENCY_MATCH_TRANSPARENT 1 ++#define DE_CONTROL_TRANSPARENCY_SELECT 9 : 9 ++#define DE_CONTROL_TRANSPARENCY_SELECT_SOURCE 0 ++#define DE_CONTROL_TRANSPARENCY_SELECT_DESTINATION 1 ++#define DE_CONTROL_TRANSPARENCY 8 : 8 ++#define DE_CONTROL_TRANSPARENCY_DISABLE 0 ++#define DE_CONTROL_TRANSPARENCY_ENABLE 1 ++#define DE_CONTROL_ROP 7 : 0 ++ ++/* Pseudo fields. */ ++ ++#define DE_CONTROL_SHORT_STROKE_DIR 27 : 24 ++#define DE_CONTROL_SHORT_STROKE_DIR_225 0 ++#define DE_CONTROL_SHORT_STROKE_DIR_135 1 ++#define DE_CONTROL_SHORT_STROKE_DIR_315 2 ++#define DE_CONTROL_SHORT_STROKE_DIR_45 3 ++#define DE_CONTROL_SHORT_STROKE_DIR_270 4 ++#define DE_CONTROL_SHORT_STROKE_DIR_90 5 ++#define DE_CONTROL_SHORT_STROKE_DIR_180 8 ++#define DE_CONTROL_SHORT_STROKE_DIR_0 10 ++#define DE_CONTROL_ROTATION 25 : 24 ++#define DE_CONTROL_ROTATION_0 0 ++#define DE_CONTROL_ROTATION_270 1 ++#define DE_CONTROL_ROTATION_90 2 ++#define DE_CONTROL_ROTATION_180 3 ++ ++#define DE_PITCH 0x000010 ++#define DE_PITCH_DESTINATION 28 : 16 ++#define DE_PITCH_SOURCE 12 : 0 ++ ++#define DE_FOREGROUND 0x000014 ++#define DE_FOREGROUND_COLOR 31 : 0 ++ ++#define DE_BACKGROUND 0x000018 ++#define DE_BACKGROUND_COLOR 31 : 0 ++ ++#define DE_STRETCH_FORMAT 0x00001C ++#define DE_STRETCH_FORMAT_PATTERN_XY 30 : 30 ++#define DE_STRETCH_FORMAT_PATTERN_XY_NORMAL 0 ++#define DE_STRETCH_FORMAT_PATTERN_XY_OVERWRITE 1 ++#define DE_STRETCH_FORMAT_PATTERN_Y 29 : 27 ++#define DE_STRETCH_FORMAT_PATTERN_X 25 : 23 ++#define DE_STRETCH_FORMAT_PIXEL_FORMAT 21 : 20 ++#define DE_STRETCH_FORMAT_PIXEL_FORMAT_8 0 ++#define DE_STRETCH_FORMAT_PIXEL_FORMAT_16 1 ++#define DE_STRETCH_FORMAT_PIXEL_FORMAT_24 3 ++#define DE_STRETCH_FORMAT_PIXEL_FORMAT_32 2 ++#define DE_STRETCH_FORMAT_ADDRESSING 19 : 16 ++#define DE_STRETCH_FORMAT_ADDRESSING_XY 0 ++#define DE_STRETCH_FORMAT_ADDRESSING_LINEAR 15 ++#define DE_STRETCH_FORMAT_SOURCE_HEIGHT 11 : 0 ++ ++#define DE_COLOR_COMPARE 0x000020 ++#define DE_COLOR_COMPARE_COLOR 23 : 0 ++ ++#define DE_COLOR_COMPARE_MASK 0x000024 ++#define DE_COLOR_COMPARE_MASK_MASKS 23 : 0 ++ ++#define DE_MASKS 0x000028 ++#define DE_MASKS_BYTE_MASK 31 : 16 ++#define DE_MASKS_BIT_MASK 15 : 0 ++ ++#define DE_CLIP_TL 0x00002C ++#define DE_CLIP_TL_TOP 31 : 16 ++#define DE_CLIP_TL_STATUS 13 : 13 ++#define DE_CLIP_TL_STATUS_DISABLE 0 ++#define DE_CLIP_TL_STATUS_ENABLE 1 ++#define DE_CLIP_TL_INHIBIT 12 : 12 ++#define DE_CLIP_TL_INHIBIT_OUTSIDE 0 ++#define DE_CLIP_TL_INHIBIT_INSIDE 1 ++#define DE_CLIP_TL_LEFT 11 : 0 ++ ++#define DE_CLIP_BR 0x000030 ++#define DE_CLIP_BR_BOTTOM 31 : 16 ++#define DE_CLIP_BR_RIGHT 12 : 0 ++ ++#define DE_MONO_PATTERN_LOW 0x000034 ++#define DE_MONO_PATTERN_LOW_PATTERN 31 : 0 ++ ++#define DE_MONO_PATTERN_HIGH 0x000038 ++#define DE_MONO_PATTERN_HIGH_PATTERN 31 : 0 ++ ++#define DE_WINDOW_WIDTH 0x00003C ++#define DE_WINDOW_WIDTH_DESTINATION 28 : 16 ++#define DE_WINDOW_WIDTH_SOURCE 12 : 0 ++ ++#define DE_WINDOW_SOURCE_BASE 0x000040 ++#define DE_WINDOW_SOURCE_BASE_EXT 27 : 27 ++#define DE_WINDOW_SOURCE_BASE_EXT_LOCAL 0 ++#define DE_WINDOW_SOURCE_BASE_EXT_EXTERNAL 1 ++#define DE_WINDOW_SOURCE_BASE_CS 26 : 26 ++#define DE_WINDOW_SOURCE_BASE_CS_0 0 ++#define DE_WINDOW_SOURCE_BASE_CS_1 1 ++#define DE_WINDOW_SOURCE_BASE_ADDRESS 25 : 0 ++ ++#define DE_WINDOW_DESTINATION_BASE 0x000044 ++#define DE_WINDOW_DESTINATION_BASE_EXT 27 : 27 ++#define DE_WINDOW_DESTINATION_BASE_EXT_LOCAL 0 ++#define DE_WINDOW_DESTINATION_BASE_EXT_EXTERNAL 1 ++#define DE_WINDOW_DESTINATION_BASE_CS 26 : 26 ++#define DE_WINDOW_DESTINATION_BASE_CS_0 0 ++#define DE_WINDOW_DESTINATION_BASE_CS_1 1 ++#define DE_WINDOW_DESTINATION_BASE_ADDRESS 25 : 0 ++ ++#define DE_ALPHA 0x000048 ++#define DE_ALPHA_VALUE 7 : 0 ++ ++#define DE_WRAP 0x00004C ++#define DE_WRAP_X 31 : 16 ++#define DE_WRAP_Y 15 : 0 ++ ++#define DE_STATUS 0x000050 ++#define DE_STATUS_CSC 1 : 1 ++#define DE_STATUS_CSC_CLEAR 0 ++#define DE_STATUS_CSC_NOT_ACTIVE 0 ++#define DE_STATUS_CSC_ACTIVE 1 ++#define DE_STATUS_2D 0 : 0 ++#define DE_STATUS_2D_CLEAR 0 ++#define DE_STATUS_2D_NOT_ACTIVE 0 ++#define DE_STATUS_2D_ACTIVE 1 ++ ++/* Color Space Conversion registers. */ ++ ++#define CSC_Y_SOURCE_BASE 0x0000C8 ++#define CSC_Y_SOURCE_BASE_EXT 27 : 27 ++#define CSC_Y_SOURCE_BASE_EXT_LOCAL 0 ++#define CSC_Y_SOURCE_BASE_EXT_EXTERNAL 1 ++#define CSC_Y_SOURCE_BASE_CS 26 : 26 ++#define CSC_Y_SOURCE_BASE_CS_0 0 ++#define CSC_Y_SOURCE_BASE_CS_1 1 ++#define CSC_Y_SOURCE_BASE_ADDRESS 25 : 0 ++ ++#define CSC_CONSTANTS 0x0000CC ++#define CSC_CONSTANTS_Y 31 : 24 ++#define CSC_CONSTANTS_R 23 : 16 ++#define CSC_CONSTANTS_G 15 : 8 ++#define CSC_CONSTANTS_B 7 : 0 ++ ++#define CSC_Y_SOURCE_X 0x0000D0 ++#define CSC_Y_SOURCE_X_INTEGER 26 : 16 ++#define CSC_Y_SOURCE_X_FRACTION 15 : 3 ++ ++#define CSC_Y_SOURCE_Y 0x0000D4 ++#define CSC_Y_SOURCE_Y_INTEGER 27 : 16 ++#define CSC_Y_SOURCE_Y_FRACTION 15 : 3 ++ ++#define CSC_U_SOURCE_BASE 0x0000D8 ++#define CSC_U_SOURCE_BASE_EXT 27 : 27 ++#define CSC_U_SOURCE_BASE_EXT_LOCAL 0 ++#define CSC_U_SOURCE_BASE_EXT_EXTERNAL 1 ++#define CSC_U_SOURCE_BASE_CS 26 : 26 ++#define CSC_U_SOURCE_BASE_CS_0 0 ++#define CSC_U_SOURCE_BASE_CS_1 1 ++#define CSC_U_SOURCE_BASE_ADDRESS 25 : 0 ++ ++#define CSC_V_SOURCE_BASE 0x0000DC ++#define CSC_V_SOURCE_BASE_EXT 27 : 27 ++#define CSC_V_SOURCE_BASE_EXT_LOCAL 0 ++#define CSC_V_SOURCE_BASE_EXT_EXTERNAL 1 ++#define CSC_V_SOURCE_BASE_CS 26 : 26 ++#define CSC_V_SOURCE_BASE_CS_0 0 ++#define CSC_V_SOURCE_BASE_CS_1 1 ++#define CSC_V_SOURCE_BASE_ADDRESS 25 : 0 ++ ++#define CSC_SOURCE_DIMENSION 0x0000E0 ++#define CSC_SOURCE_DIMENSION_X 31 : 16 ++#define CSC_SOURCE_DIMENSION_Y 15 : 0 ++ ++#define CSC_SOURCE_PITCH 0x0000E4 ++#define CSC_SOURCE_PITCH_Y 31 : 16 ++#define CSC_SOURCE_PITCH_UV 15 : 0 ++ ++#define CSC_DESTINATION 0x0000E8 ++#define CSC_DESTINATION_WRAP 31 : 31 ++#define CSC_DESTINATION_WRAP_DISABLE 0 ++#define CSC_DESTINATION_WRAP_ENABLE 1 ++#define CSC_DESTINATION_X 27 : 16 ++#define CSC_DESTINATION_Y 11 : 0 ++ ++#define CSC_DESTINATION_DIMENSION 0x0000EC ++#define CSC_DESTINATION_DIMENSION_X 31 : 16 ++#define CSC_DESTINATION_DIMENSION_Y 15 : 0 ++ ++#define CSC_DESTINATION_PITCH 0x0000F0 ++#define CSC_DESTINATION_PITCH_X 31 : 16 ++#define CSC_DESTINATION_PITCH_Y 15 : 0 ++ ++#define CSC_SCALE_FACTOR 0x0000F4 ++#define CSC_SCALE_FACTOR_HORIZONTAL 31 : 16 ++#define CSC_SCALE_FACTOR_VERTICAL 15 : 0 ++ ++#define CSC_DESTINATION_BASE 0x0000F8 ++#define CSC_DESTINATION_BASE_EXT 27 : 27 ++#define CSC_DESTINATION_BASE_EXT_LOCAL 0 ++#define CSC_DESTINATION_BASE_EXT_EXTERNAL 1 ++#define CSC_DESTINATION_BASE_CS 26 : 26 ++#define CSC_DESTINATION_BASE_CS_0 0 ++#define CSC_DESTINATION_BASE_CS_1 1 ++#define CSC_DESTINATION_BASE_ADDRESS 25 : 0 ++ ++#define CSC_CONTROL 0x0000FC ++#define CSC_CONTROL_STATUS 31 : 31 ++#define CSC_CONTROL_STATUS_STOP 0 ++#define CSC_CONTROL_STATUS_START 1 ++#define CSC_CONTROL_SOURCE_FORMAT 30 : 28 ++#define CSC_CONTROL_SOURCE_FORMAT_YUV422 0 ++#define CSC_CONTROL_SOURCE_FORMAT_YUV420I 1 ++#define CSC_CONTROL_SOURCE_FORMAT_YUV420 2 ++#define CSC_CONTROL_SOURCE_FORMAT_YVU9 3 ++#define CSC_CONTROL_SOURCE_FORMAT_IYU1 4 ++#define CSC_CONTROL_SOURCE_FORMAT_IYU2 5 ++#define CSC_CONTROL_SOURCE_FORMAT_RGB565 6 ++#define CSC_CONTROL_SOURCE_FORMAT_RGB8888 7 ++#define CSC_CONTROL_DESTINATION_FORMAT 27 : 26 ++#define CSC_CONTROL_DESTINATION_FORMAT_RGB565 0 ++#define CSC_CONTROL_DESTINATION_FORMAT_RGB8888 1 ++#define CSC_CONTROL_HORIZONTAL_FILTER 25 : 25 ++#define CSC_CONTROL_HORIZONTAL_FILTER_DISABLE 0 ++#define CSC_CONTROL_HORIZONTAL_FILTER_ENABLE 1 ++#define CSC_CONTROL_VERTICAL_FILTER 24 : 24 ++#define CSC_CONTROL_VERTICAL_FILTER_DISABLE 0 ++#define CSC_CONTROL_VERTICAL_FILTER_ENABLE 1 ++#define CSC_CONTROL_BYTE_ORDER 23 : 23 ++#define CSC_CONTROL_BYTE_ORDER_YUYV 0 ++#define CSC_CONTROL_BYTE_ORDER_UYVY 1 ++ ++#define DE_DATA_PORT_501 0x110000 ++#define DE_DATA_PORT_712 0x400000 ++#define DE_DATA_PORT_722 0x6000 ++ ++/* point to virtual Memory Map IO starting address */ ++extern char *smtc_RegBaseAddress; ++/* point to virtual video memory starting address */ ++extern char *smtc_VRAMBaseAddress; ++extern unsigned char smtc_de_busy; ++ ++extern unsigned long memRead32(unsigned long nOffset); ++extern void memWrite32(unsigned long nOffset, unsigned long nData); ++extern unsigned long SMTC_read2Dreg(unsigned long nOffset); ++ ++/* 2D functions */ ++extern void deInit(unsigned int nModeWidth, unsigned int nModeHeight, ++ unsigned int bpp); ++ ++extern void deWaitForNotBusy(void); ++ ++extern void deVerticalLine(unsigned long dst_base, ++ unsigned long dst_pitch, ++ unsigned long nX, ++ unsigned long nY, ++ unsigned long dst_height, ++ unsigned long nColor); ++ ++extern void deHorizontalLine(unsigned long dst_base, ++ unsigned long dst_pitch, ++ unsigned long nX, ++ unsigned long nY, ++ unsigned long dst_width, ++ unsigned long nColor); ++ ++extern void deLine(unsigned long dst_base, ++ unsigned long dst_pitch, ++ unsigned long nX1, ++ unsigned long nY1, ++ unsigned long nX2, ++ unsigned long nY2, ++ unsigned long nColor); ++ ++extern void deFillRect(unsigned long dst_base, ++ unsigned long dst_pitch, ++ unsigned long dst_X, ++ unsigned long dst_Y, ++ unsigned long dst_width, ++ unsigned long dst_height, ++ unsigned long nColor); ++ ++extern void deRotatePattern(unsigned char *pattern_dstaddr, ++ unsigned long pattern_src_addr, ++ unsigned long pattern_BPP, ++ unsigned long pattern_stride, ++ int patternX, ++ int patternY); ++ ++extern void deCopy(unsigned long dst_base, ++ unsigned long dst_pitch, ++ unsigned long dst_BPP, ++ unsigned long dst_X, ++ unsigned long dst_Y, ++ unsigned long dst_width, ++ unsigned long dst_height, ++ unsigned long src_base, ++ unsigned long src_pitch, ++ unsigned long src_X, ++ unsigned long src_Y, ++ pTransparent pTransp, ++ unsigned char nROP2); ++ ++/* ++ * System memory to Video memory monochrome expansion. ++ * ++ * Source is monochrome image in system memory. This function expands the ++ * monochrome data to color image in video memory. ++ * ++ * @pSrcbuf: pointer to start of source buffer in system memory ++ * @srcDelta: Pitch value (in bytes) of the source buffer, +ive means top ++ * down and -ive mean button up ++ * @startBit: Mono data can start at any bit in a byte, this value should ++ * be 0 to 7 ++ * @dBase: Address of destination : offset in frame buffer ++ * @dPitch: Pitch value of destination surface in BYTE ++ * @bpp: Color depth of destination surface ++ * @dx, dy: Starting coordinate of destination surface ++ * @width, height: width and height of rectange in pixel value ++ * @fColor,bColor: Foreground, Background color (corresponding to a 1, 0 in ++ * the monochrome data) ++ * @rop2: ROP value ++ */ ++ ++extern long deSystemMem2VideoMemMonoBlt( ++ const char *pSrcbuf, ++ long srcDelta, ++ unsigned long startBit, ++ unsigned long dBase, ++ unsigned long dPitch, ++ unsigned long bpp, ++ unsigned long dx, unsigned long dy, ++ unsigned long width, unsigned long height, ++ unsigned long fColor, ++ unsigned long bColor, ++ unsigned long rop2); ++ ++extern unsigned long deGetTransparency(void); ++extern void deSetPixelFormat(unsigned long bpp); +diff -Nur linux-2.6.30/drivers/video/sm7xx/smtcfb.c rt4ls/drivers/video/sm7xx/smtcfb.c +--- linux-2.6.30/drivers/video/sm7xx/smtcfb.c 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/drivers/video/sm7xx/smtcfb.c 2009-06-12 16:28:47.728622169 +0200 +@@ -0,0 +1,1135 @@ ++/* ++ * smtcfb.c -- Silicon Motion SM7xx frame buffer device ++ * ++ * Copyright (C) 2006 Silicon Motion Technology Corp. ++ * Authors: Ge Wang, gewang@siliconmotion.com ++ * Boyod boyod.yang@siliconmotion.com.cn ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ * ++ * Version 0.10.26192.21.01 ++ * - Add PowerPC/Big endian support ++ * - Add 2D support for Lynx ++ * - Verified on2.6.19.2 Boyod.yang <boyod.yang@siliconmotion.com.cn> ++ * ++ * Version 0.09.2621.00.01 ++ * - Only support Linux Kernel's version 2.6.21. ++ * Boyod.yang <boyod.yang@siliconmotion.com.cn> ++ * ++ * Version 0.09 ++ * - Only support Linux Kernel's version 2.6.12. ++ * Boyod.yang <boyod.yang@siliconmotion.com.cn> ++ */ ++ ++#ifndef __KERNEL__ ++#define __KERNEL__ ++#endif ++ ++#include <linux/io.h> ++#include <linux/fb.h> ++#include <linux/pci.h> ++#include <linux/init.h> ++#include <linux/uaccess.h> ++#include <linux/screen_info.h> ++ ++#ifdef CONFIG_PM ++#include <linux/pm.h> ++#endif ++ ++struct screen_info smtc_screen_info; ++ ++#include "smtcfb.h" ++#include "smtc2d.h" ++ ++#ifdef DEBUG ++#define smdbg(format, arg...) printk(KERN_DEBUG format , ## arg) ++#else ++#define smdbg(format, arg...) ++#endif ++ ++/* ++* Private structure ++*/ ++struct smtcfb_info { ++ /* ++ * The following is a pointer to be passed into the ++ * functions below. The modules outside the main ++ * voyager.c driver have no knowledge as to what ++ * is within this structure. ++ */ ++ struct fb_info fb; ++ struct display_switch *dispsw; ++ struct pci_dev *dev; ++ signed int currcon; ++ ++ struct { ++ u8 red, green, blue; ++ } palette[NR_RGB]; ++ ++ u_int palette_size; ++}; ++ ++struct par_info { ++ /* ++ * Hardware ++ */ ++ u16 chipID; ++ unsigned char __iomem *m_pMMIO; ++ char __iomem *m_pLFB; ++ char *m_pDPR; ++ char *m_pVPR; ++ char *m_pCPR; ++ ++ u_int width; ++ u_int height; ++ u_int hz; ++ u_long BaseAddressInVRAM; ++ u8 chipRevID; ++}; ++ ++struct vesa_mode_table { ++ char mode_index[15]; ++ u16 lfb_width; ++ u16 lfb_height; ++ u16 lfb_depth; ++}; ++ ++static struct vesa_mode_table vesa_mode[] = { ++ {"640x480x8", 640, 480, 8}, ++ {"800x480x8", 800, 480, 8}, ++ {"800x600x8", 800, 600, 8}, ++ {"1024x768x8", 1024, 768, 8}, ++ {"1280x1024x8", 1280, 1024, 8}, ++ ++ {"640x480x16", 640, 480, 16}, ++ {"800x480x16", 800, 480, 16}, ++ {"800x600x16", 800, 600, 16}, ++ {"1024x768x16", 1024, 768, 16}, ++ {"1280x1024x16", 1280, 1024, 16}, ++ ++ {"640x480x24", 640, 480, 24}, ++ {"800x480x24", 800, 480, 24}, ++ {"800x600x24", 800, 600, 24}, ++ {"1024x768x24", 1024, 768, 24}, ++ {"1280x1024x24", 1280, 1024, 24}, ++}; ++ ++char __iomem *smtc_RegBaseAddress; /* Memory Map IO starting address */ ++char __iomem *smtc_VRAMBaseAddress; /* video memory starting address */ ++ ++char *smtc_2DBaseAddress; /* 2D engine starting address */ ++char *smtc_2Ddataport; /* 2D data port offset */ ++short smtc_2Dacceleration; ++ ++static u32 colreg[17]; ++static struct par_info hw; /* hardware information */ ++ ++#if defined(CONFIG_FB_SM7XX_DUALHEAD) ++ ++static u32 colreg2[17]; ++/* hardware information for second display (CRT) */ ++static struct par_info hw2; ++/* fb_info for second display (CRT) */ ++struct smtcfb_info smtcfb_info2; ++ ++#endif /* CONFIG_FB_SM501_DUALHEAD */ ++ ++u16 smtc_ChipIDs[] = { ++ 0x710, ++ 0x712, ++ 0x720 ++}; ++ ++int sm712be_flag; ++ ++#define numSMTCchipIDs (sizeof(smtc_ChipIDs) / sizeof(u16)) ++ ++void deWaitForNotBusy(void) ++{ ++ unsigned long i = 0x1000000; ++ while (i--) { ++ if ((smtc_seqr(0x16) & 0x18) == 0x10) ++ break; ++ } ++ smtc_de_busy = 0; ++} ++ ++static void sm712_set_timing(struct smtcfb_info *sfb, ++ struct par_info *ppar_info) ++{ ++ int i = 0, j = 0; ++ u32 m_nScreenStride; ++ ++ smdbg("\nppar_info->width = %d ppar_info->height = %d" ++ "sfb->fb.var.bits_per_pixel = %d ppar_info->hz = %d\n", ++ ppar_info->width, ppar_info->height, ++ sfb->fb.var.bits_per_pixel, ppar_info->hz); ++ ++ for (j = 0; j < numVGAModes; j++) { ++ if (VGAMode[j].mmSizeX == ppar_info->width && ++ VGAMode[j].mmSizeY == ppar_info->height && ++ VGAMode[j].bpp == sfb->fb.var.bits_per_pixel && ++ VGAMode[j].hz == ppar_info->hz) { ++ ++ smdbg("\nVGAMode[j].mmSizeX = %d VGAMode[j].mmSizeY =" ++ "%d VGAMode[j].bpp = %d" ++ "VGAMode[j].hz=%d\n", ++ VGAMode[j].mmSizeX, VGAMode[j].mmSizeY, ++ VGAMode[j].bpp, VGAMode[j].hz); ++ ++ smdbg("VGAMode index=%d\n", j); ++ ++ smtc_mmiowb(0x0, 0x3c6); ++ ++ smtc_seqw(0, 0x1); ++ ++ smtc_mmiowb(VGAMode[j].Init_MISC, 0x3c2); ++ ++ /* init SEQ register SR00 - SR04 */ ++ for (i = 0; i < SIZE_SR00_SR04; i++) ++ smtc_seqw(i, VGAMode[j].Init_SR00_SR04[i]); ++ ++ /* init SEQ register SR10 - SR24 */ ++ for (i = 0; i < SIZE_SR10_SR24; i++) ++ smtc_seqw(i + 0x10, ++ VGAMode[j].Init_SR10_SR24[i]); ++ ++ /* init SEQ register SR30 - SR75 */ ++ for (i = 0; i < SIZE_SR30_SR75; i++) ++ if (((i + 0x30) != 0x62) \ ++ && ((i + 0x30) != 0x6a) \ ++ && ((i + 0x30) != 0x6b)) ++ smtc_seqw(i + 0x30, ++ VGAMode[j].Init_SR30_SR75[i]); ++ ++ /* init SEQ register SR80 - SR93 */ ++ for (i = 0; i < SIZE_SR80_SR93; i++) ++ smtc_seqw(i + 0x80, ++ VGAMode[j].Init_SR80_SR93[i]); ++ ++ /* init SEQ register SRA0 - SRAF */ ++ for (i = 0; i < SIZE_SRA0_SRAF; i++) ++ smtc_seqw(i + 0xa0, ++ VGAMode[j].Init_SRA0_SRAF[i]); ++ ++ /* init Graphic register GR00 - GR08 */ ++ for (i = 0; i < SIZE_GR00_GR08; i++) ++ smtc_grphw(i, VGAMode[j].Init_GR00_GR08[i]); ++ ++ /* init Attribute register AR00 - AR14 */ ++ for (i = 0; i < SIZE_AR00_AR14; i++) ++ smtc_attrw(i, VGAMode[j].Init_AR00_AR14[i]); ++ ++ /* init CRTC register CR00 - CR18 */ ++ for (i = 0; i < SIZE_CR00_CR18; i++) ++ smtc_crtcw(i, VGAMode[j].Init_CR00_CR18[i]); ++ ++ /* init CRTC register CR30 - CR4D */ ++ for (i = 0; i < SIZE_CR30_CR4D; i++) ++ smtc_crtcw(i + 0x30, ++ VGAMode[j].Init_CR30_CR4D[i]); ++ ++ /* init CRTC register CR90 - CRA7 */ ++ for (i = 0; i < SIZE_CR90_CRA7; i++) ++ smtc_crtcw(i + 0x90, ++ VGAMode[j].Init_CR90_CRA7[i]); ++ } ++ } ++ smtc_mmiowb(0x67, 0x3c2); ++ ++ /* set VPR registers */ ++ writel(0x0, ppar_info->m_pVPR + 0x0C); ++ writel(0x0, ppar_info->m_pVPR + 0x40); ++ ++ /* set data width */ ++ m_nScreenStride = ++ (ppar_info->width * sfb->fb.var.bits_per_pixel) / 64; ++ switch (sfb->fb.var.bits_per_pixel) { ++ case 8: ++ writel(0x0, ppar_info->m_pVPR + 0x0); ++ break; ++ case 16: ++ writel(0x00020000, ppar_info->m_pVPR + 0x0); ++ break; ++ case 24: ++ writel(0x00040000, ppar_info->m_pVPR + 0x0); ++ break; ++ case 32: ++ writel(0x00030000, ppar_info->m_pVPR + 0x0); ++ break; ++ } ++ writel((u32) (((m_nScreenStride + 2) << 16) | m_nScreenStride), ++ ppar_info->m_pVPR + 0x10); ++ ++} ++ ++static void sm712_setpalette(int regno, unsigned red, unsigned green, ++ unsigned blue, struct fb_info *info) ++{ ++ struct par_info *cur_par = (struct par_info *)info->par; ++ ++ if (cur_par->BaseAddressInVRAM) ++ /* ++ * second display palette for dual head. Enable CRT RAM, 6-bit ++ * RAM ++ */ ++ smtc_seqw(0x66, (smtc_seqr(0x66) & 0xC3) | 0x20); ++ else ++ /* primary display palette. Enable LCD RAM only, 6-bit RAM */ ++ smtc_seqw(0x66, (smtc_seqr(0x66) & 0xC3) | 0x10); ++ smtc_mmiowb(regno, dac_reg); ++ smtc_mmiowb(red >> 10, dac_val); ++ smtc_mmiowb(green >> 10, dac_val); ++ smtc_mmiowb(blue >> 10, dac_val); ++} ++ ++static void smtc_set_timing(struct smtcfb_info *sfb, struct par_info ++ *ppar_info) ++{ ++ switch (ppar_info->chipID) { ++ case 0x710: ++ case 0x712: ++ case 0x720: ++ sm712_set_timing(sfb, ppar_info); ++ break; ++ } ++} ++ ++static struct fb_var_screeninfo smtcfb_var = { ++ .xres = 1024, ++ .yres = 600, ++ .xres_virtual = 1024, ++ .yres_virtual = 600, ++ .bits_per_pixel = 16, ++ .red = {16, 8, 0}, ++ .green = {8, 8, 0}, ++ .blue = {0, 8, 0}, ++ .activate = FB_ACTIVATE_NOW, ++ .height = -1, ++ .width = -1, ++ .vmode = FB_VMODE_NONINTERLACED, ++}; ++ ++static struct fb_fix_screeninfo smtcfb_fix = { ++ .id = "sm712fb", ++ .type = FB_TYPE_PACKED_PIXELS, ++ .visual = FB_VISUAL_TRUECOLOR, ++ .line_length = 800 * 3, ++ .accel = FB_ACCEL_SMI_LYNX, ++}; ++ ++/* chan_to_field ++ * ++ * convert a colour value into a field position ++ * ++ * from pxafb.c ++ */ ++ ++static inline unsigned int chan_to_field(unsigned int chan, ++ struct fb_bitfield *bf) ++{ ++ chan &= 0xffff; ++ chan >>= 16 - bf->length; ++ return chan << bf->offset; ++} ++ ++static int smtc_setcolreg(unsigned regno, unsigned red, unsigned green, ++ unsigned blue, unsigned trans, struct fb_info *info) ++{ ++ struct smtcfb_info *sfb = (struct smtcfb_info *)info; ++ u32 val; ++ ++ if (regno > 255) ++ return 1; ++ ++ switch (sfb->fb.fix.visual) { ++ case FB_VISUAL_DIRECTCOLOR: ++ case FB_VISUAL_TRUECOLOR: ++ /* ++ * 16/32 bit true-colour, use pseuo-palette for 16 base color ++ */ ++ if (regno < 16) { ++ if (sfb->fb.var.bits_per_pixel == 16) { ++ u32 *pal = sfb->fb.pseudo_palette; ++ val = chan_to_field(red, &sfb->fb.var.red); ++ val |= chan_to_field(green, \ ++ &sfb->fb.var.green); ++ val |= chan_to_field(blue, &sfb->fb.var.blue); ++#ifdef __BIG_ENDIAN ++ pal[regno] = ++ ((red & 0xf800) >> 8) | ++ ((green & 0xe000) >> 13) | ++ ((green & 0x1c00) << 3) | ++ ((blue & 0xf800) >> 3); ++#else ++ pal[regno] = val; ++#endif ++ } else { ++ u32 *pal = sfb->fb.pseudo_palette; ++ val = chan_to_field(red, &sfb->fb.var.red); ++ val |= chan_to_field(green, \ ++ &sfb->fb.var.green); ++ val |= chan_to_field(blue, &sfb->fb.var.blue); ++#ifdef __BIG_ENDIAN ++ val = ++ (val & 0xff00ff00 >> 8) | ++ (val & 0x00ff00ff << 8); ++#endif ++ pal[regno] = val; ++ } ++ } ++ break; ++ ++ case FB_VISUAL_PSEUDOCOLOR: ++ /* color depth 8 bit */ ++ sm712_setpalette(regno, red, green, blue, info); ++ break; ++ ++ default: ++ return 1; /* unknown type */ ++ } ++ ++ return 0; ++ ++} ++ ++#ifdef __BIG_ENDIAN ++static ssize_t smtcfb_read(struct fb_info *info, char __user * buf, size_t ++ count, loff_t *ppos) ++{ ++ unsigned long p = *ppos; ++ ++ u32 *buffer, *dst; ++ u32 __iomem *src; ++ int c, i, cnt = 0, err = 0; ++ unsigned long total_size; ++ ++ if (!info || !info->screen_base) ++ return -ENODEV; ++ ++ if (info->state != FBINFO_STATE_RUNNING) ++ return -EPERM; ++ ++ total_size = info->screen_size; ++ ++ if (total_size == 0) ++ total_size = info->fix.smem_len; ++ ++ if (p >= total_size) ++ return 0; ++ ++ if (count >= total_size) ++ count = total_size; ++ ++ if (count + p > total_size) ++ count = total_size - p; ++ ++ buffer = kmalloc((count > PAGE_SIZE) ? PAGE_SIZE : count, GFP_KERNEL); ++ if (!buffer) ++ return -ENOMEM; ++ ++ src = (u32 __iomem *) (info->screen_base + p); ++ ++ if (info->fbops->fb_sync) ++ info->fbops->fb_sync(info); ++ ++ while (count) { ++ c = (count > PAGE_SIZE) ? PAGE_SIZE : count; ++ dst = buffer; ++ for (i = c >> 2; i--;) { ++ *dst = fb_readl(src++); ++ *dst = ++ (*dst & 0xff00ff00 >> 8) | ++ (*dst & 0x00ff00ff << 8); ++ dst++; ++ } ++ if (c & 3) { ++ u8 *dst8 = (u8 *) dst; ++ u8 __iomem *src8 = (u8 __iomem *) src; ++ ++ for (i = c & 3; i--;) { ++ if (i & 1) { ++ *dst8++ = fb_readb(++src8); ++ } else { ++ *dst8++ = fb_readb(--src8); ++ src8 += 2; ++ } ++ } ++ src = (u32 __iomem *) src8; ++ } ++ ++ if (copy_to_user(buf, buffer, c)) { ++ err = -EFAULT; ++ break; ++ } ++ *ppos += c; ++ buf += c; ++ cnt += c; ++ count -= c; ++ } ++ ++ kfree(buffer); ++ ++ return (err) ? err : cnt; ++} ++ ++static ssize_t ++smtcfb_write(struct fb_info *info, const char __user *buf, size_t count, ++ loff_t *ppos) ++{ ++ unsigned long p = *ppos; ++ ++ u32 *buffer, *src; ++ u32 __iomem *dst; ++ int c, i, cnt = 0, err = 0; ++ unsigned long total_size; ++ ++ if (!info || !info->screen_base) ++ return -ENODEV; ++ ++ if (info->state != FBINFO_STATE_RUNNING) ++ return -EPERM; ++ ++ total_size = info->screen_size; ++ ++ if (total_size == 0) ++ total_size = info->fix.smem_len; ++ ++ if (p > total_size) ++ return -EFBIG; ++ ++ if (count > total_size) { ++ err = -EFBIG; ++ count = total_size; ++ } ++ ++ if (count + p > total_size) { ++ if (!err) ++ err = -ENOSPC; ++ ++ count = total_size - p; ++ } ++ ++ buffer = kmalloc((count > PAGE_SIZE) ? PAGE_SIZE : count, GFP_KERNEL); ++ if (!buffer) ++ return -ENOMEM; ++ ++ dst = (u32 __iomem *) (info->screen_base + p); ++ ++ if (info->fbops->fb_sync) ++ info->fbops->fb_sync(info); ++ ++ while (count) { ++ c = (count > PAGE_SIZE) ? PAGE_SIZE : count; ++ src = buffer; ++ ++ if (copy_from_user(src, buf, c)) { ++ err = -EFAULT; ++ break; ++ } ++ ++ for (i = c >> 2; i--;) { ++ fb_writel((*src & 0xff00ff00 >> 8) | ++ (*src & 0x00ff00ff << 8), dst++); ++ src++; ++ } ++ if (c & 3) { ++ u8 *src8 = (u8 *) src; ++ u8 __iomem *dst8 = (u8 __iomem *) dst; ++ ++ for (i = c & 3; i--;) { ++ if (i & 1) { ++ fb_writeb(*src8++, ++dst8); ++ } else { ++ fb_writeb(*src8++, --dst8); ++ dst8 += 2; ++ } ++ } ++ dst = (u32 __iomem *) dst8; ++ } ++ ++ *ppos += c; ++ buf += c; ++ cnt += c; ++ count -= c; ++ } ++ ++ kfree(buffer); ++ ++ return (cnt) ? cnt : err; ++} ++#endif /* ! __BIG_ENDIAN */ ++ ++#include "smtc2d.c" ++ ++void smtcfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) ++{ ++ struct par_info *p = (struct par_info *)info->par; ++ ++ if (smtc_2Dacceleration) { ++ if (!area->width || !area->height) ++ return; ++ ++ deCopy(p->BaseAddressInVRAM, 0, info->var.bits_per_pixel, ++ area->dx, area->dy, area->width, area->height, ++ p->BaseAddressInVRAM, 0, area->sx, area->sy, 0, 0xC); ++ ++ } else ++ cfb_copyarea(info, area); ++} ++ ++void smtcfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) ++{ ++ struct par_info *p = (struct par_info *)info->par; ++ ++ if (smtc_2Dacceleration) { ++ if (!rect->width || !rect->height) ++ return; ++ if (info->var.bits_per_pixel >= 24) ++ deFillRect(p->BaseAddressInVRAM, 0, rect->dx * 3, ++ rect->dy * 3, rect->width * 3, rect->height, ++ rect->color); ++ else ++ deFillRect(p->BaseAddressInVRAM, 0, rect->dx, rect->dy, ++ rect->width, rect->height, rect->color); ++ } else ++ cfb_fillrect(info, rect); ++} ++ ++void smtcfb_imageblit(struct fb_info *info, const struct fb_image *image) ++{ ++ struct par_info *p = (struct par_info *)info->par; ++ u32 bg_col = 0, fg_col = 0; ++ ++ if ((smtc_2Dacceleration) && (image->depth == 1)) { ++ if (smtc_de_busy) ++ deWaitForNotBusy(); ++ ++ switch (info->var.bits_per_pixel) { ++ case 8: ++ bg_col = image->bg_color; ++ fg_col = image->fg_color; ++ break; ++ case 16: ++ bg_col = ++ ((u32 *) (info->pseudo_palette))[image->bg_color]; ++ fg_col = ++ ((u32 *) (info->pseudo_palette))[image->fg_color]; ++ break; ++ case 32: ++ bg_col = ++ ((u32 *) (info->pseudo_palette))[image->bg_color]; ++ fg_col = ++ ((u32 *) (info->pseudo_palette))[image->fg_color]; ++ break; ++ } ++ ++ deSystemMem2VideoMemMonoBlt( ++ image->data, ++ image->width / 8, ++ 0, ++ p->BaseAddressInVRAM, ++ 0, ++ 0, ++ image->dx, image->dy, ++ image->width, image->height, ++ fg_col, bg_col, ++ 0x0C); ++ ++ } else ++ cfb_imageblit(info, image); ++} ++ ++static struct fb_ops smtcfb_ops = { ++ .owner = THIS_MODULE, ++ .fb_setcolreg = smtc_setcolreg, ++ .fb_fillrect = smtcfb_fillrect, ++ .fb_imageblit = smtcfb_imageblit, ++ .fb_copyarea = smtcfb_copyarea, ++#ifdef __BIG_ENDIAN ++ .fb_read = smtcfb_read, ++ .fb_write = smtcfb_write, ++#endif ++ ++}; ++ ++void smtcfb_setmode(struct smtcfb_info *sfb) ++{ ++ switch (sfb->fb.var.bits_per_pixel) { ++ case 32: ++ sfb->fb.fix.visual = FB_VISUAL_TRUECOLOR; ++ sfb->fb.fix.line_length = sfb->fb.var.xres * 4; ++ sfb->fb.var.red.length = 8; ++ sfb->fb.var.green.length = 8; ++ sfb->fb.var.blue.length = 8; ++ sfb->fb.var.red.offset = 16; ++ sfb->fb.var.green.offset = 8; ++ sfb->fb.var.blue.offset = 0; ++ ++ break; ++ case 8: ++ sfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; ++ sfb->fb.fix.line_length = sfb->fb.var.xres; ++ sfb->fb.var.red.offset = 5; ++ sfb->fb.var.red.length = 3; ++ sfb->fb.var.green.offset = 2; ++ sfb->fb.var.green.length = 3; ++ sfb->fb.var.blue.offset = 0; ++ sfb->fb.var.blue.length = 2; ++ break; ++ case 24: ++ sfb->fb.fix.visual = FB_VISUAL_TRUECOLOR; ++ sfb->fb.fix.line_length = sfb->fb.var.xres * 3; ++ sfb->fb.var.red.length = 8; ++ sfb->fb.var.green.length = 8; ++ sfb->fb.var.blue.length = 8; ++ ++ sfb->fb.var.red.offset = 16; ++ sfb->fb.var.green.offset = 8; ++ sfb->fb.var.blue.offset = 0; ++ ++ break; ++ case 16: ++ default: ++ sfb->fb.fix.visual = FB_VISUAL_TRUECOLOR; ++ sfb->fb.fix.line_length = sfb->fb.var.xres * 2; ++ ++ sfb->fb.var.red.length = 5; ++ sfb->fb.var.green.length = 6; ++ sfb->fb.var.blue.length = 5; ++ ++ sfb->fb.var.red.offset = 11; ++ sfb->fb.var.green.offset = 5; ++ sfb->fb.var.blue.offset = 0; ++ ++ break; ++ } ++ ++ hw.width = sfb->fb.var.xres; ++ hw.height = sfb->fb.var.yres; ++ hw.hz = 60; ++ smtc_set_timing(sfb, &hw); ++ if (smtc_2Dacceleration) { ++ printk("2D acceleration enabled!\n"); ++ /* Init smtc drawing engine */ ++ deInit(sfb->fb.var.xres, sfb->fb.var.yres, ++ sfb->fb.var.bits_per_pixel); ++ } ++} ++ ++#if defined(CONFIG_FB_SM7XX_DUALHEAD) ++void smtc_head2_init(struct smtcfb_info *sfb) ++{ ++ smtcfb_info2 = *sfb; ++ smtcfb_info2.fb.pseudo_palette = &colreg2; ++ smtcfb_info2.fb.par = &hw2; ++ sprintf(smtcfb_info2.fb.fix.id, "sm%Xfb2", hw.chipID); ++ hw2.chipID = hw.chipID; ++ hw2.chipRevID = hw.chipRevID; ++ hw2.width = smtcfb_info2.fb.var.xres; ++ hw2.height = smtcfb_info2.fb.var.yres; ++ hw2.hz = 60; ++ hw2.m_pMMIO = smtc_RegBaseAddress; ++ ++ /*hard code 2nd head starting from half VRAM size postion */ ++ hw2.BaseAddressInVRAM = smtcfb_info2.fb.fix.smem_len / 2; ++ ++ hw2.m_pLFB = smtc_VRAMBaseAddress + hw2.BaseAddressInVRAM; ++ smtcfb_info2.fb.screen_base = hw2.m_pLFB; ++ ++ writel(hw2.BaseAddressInVRAM >> 3, hw2.m_pVPR + 0x10); ++} ++#endif ++ ++/* ++ * Alloc struct smtcfb_info and assign the default value ++ */ ++static struct smtcfb_info *__devinit smtc_alloc_fb_info(struct pci_dev *dev, ++ char *name) ++{ ++ struct smtcfb_info *sfb; ++ ++ sfb = kmalloc(sizeof(struct smtcfb_info), GFP_KERNEL); ++ ++ if (!sfb) ++ return NULL; ++ ++ memset(sfb, 0, sizeof(struct smtcfb_info)); ++ ++ sfb->currcon = -1; ++ sfb->dev = dev; ++ ++ /*** Init sfb->fb with default value ***/ ++ sfb->fb.flags = FBINFO_FLAG_DEFAULT; ++ sfb->fb.fbops = &smtcfb_ops; ++ sfb->fb.var = smtcfb_var; ++ sfb->fb.fix = smtcfb_fix; ++ ++ strcpy(sfb->fb.fix.id, name); ++ ++ sfb->fb.fix.type = FB_TYPE_PACKED_PIXELS; ++ sfb->fb.fix.type_aux = 0; ++ sfb->fb.fix.xpanstep = 0; ++ sfb->fb.fix.ypanstep = 0; ++ sfb->fb.fix.ywrapstep = 0; ++ sfb->fb.fix.accel = FB_ACCEL_SMI_LYNX; ++ ++ sfb->fb.var.nonstd = 0; ++ sfb->fb.var.activate = FB_ACTIVATE_NOW; ++ sfb->fb.var.height = -1; ++ sfb->fb.var.width = -1; ++ /* text mode acceleration */ ++ sfb->fb.var.accel_flags = FB_ACCELF_TEXT; ++ sfb->fb.var.vmode = FB_VMODE_NONINTERLACED; ++ sfb->fb.par = &hw; ++ sfb->fb.pseudo_palette = colreg; ++ ++ return sfb; ++} ++ ++/* ++ * Unmap in the memory mapped IO registers ++ */ ++ ++static void __devinit smtc_unmap_mmio(struct smtcfb_info *sfb) ++{ ++ if (sfb && smtc_RegBaseAddress) ++ smtc_RegBaseAddress = NULL; ++} ++ ++/* ++ * Map in the screen memory ++ */ ++ ++static int __devinit smtc_map_smem(struct smtcfb_info *sfb, ++ struct pci_dev *dev, u_long smem_len) ++{ ++ if (sfb->fb.var.bits_per_pixel == 32) { ++#ifdef __BIG_ENDIAN ++ sfb->fb.fix.smem_start = pci_resource_start(dev, 0) ++ + 0x800000; ++#else ++ sfb->fb.fix.smem_start = pci_resource_start(dev, 0); ++#endif ++ } else { ++ sfb->fb.fix.smem_start = pci_resource_start(dev, 0); ++ } ++ ++ sfb->fb.fix.smem_len = smem_len; ++ ++ sfb->fb.screen_base = smtc_VRAMBaseAddress; ++ ++ if (!sfb->fb.screen_base) { ++ printk(KERN_INFO "%s: unable to map screen memory\n", ++ sfb->fb.fix.id); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++/* ++ * Unmap in the screen memory ++ * ++ */ ++static void __devinit smtc_unmap_smem(struct smtcfb_info *sfb) ++{ ++ if (sfb && sfb->fb.screen_base) { ++ iounmap(sfb->fb.screen_base); ++ sfb->fb.screen_base = NULL; ++ } ++} ++ ++/* ++ * We need to wake up the LynxEM+, and make sure its in linear memory mode. ++ */ ++static inline void __devinit sm7xx_init_hw(void) ++{ ++ outb_p(0x18, 0x3c4); ++ outb_p(0x11, 0x3c5); ++} ++ ++static void __devinit smtc_free_fb_info(struct smtcfb_info *sfb) ++{ ++ if (sfb) { ++ fb_alloc_cmap(&sfb->fb.cmap, 0, 0); ++ kfree(sfb); ++ } ++} ++ ++static int __init smtcfb_init(void) ++{ ++ struct smtcfb_info *sfb; ++ u_long smem_size = 0x00800000; /* default 8MB */ ++ char name[16]; ++ int err, i = 0; ++ unsigned long pFramebufferPhysical; ++ struct pci_dev *pdev = NULL; ++ ++ printk(KERN_INFO ++ "Silicon Motion display driver " SMTC_LINUX_FB_VERSION "\n"); ++ ++ /* init the global variable */ ++ smtc_2Dacceleration = 0; /* default no 2D acceleration */ ++ ++ do { ++ pdev = pci_get_device(0x126f, smtc_ChipIDs[i], pdev); ++ if (pdev == NULL) { ++ i++; ++ } else { ++ hw.chipID = smtc_ChipIDs[i]; ++ break; ++ } ++ } while (i < numSMTCchipIDs); ++ ++ err = pci_enable_device(pdev); /* enable SMTC chip */ ++ ++ if (err) ++ return err; ++ ++ err = -ENOMEM; ++ ++ sprintf(name, "sm%Xfb", hw.chipID); ++ ++ sfb = smtc_alloc_fb_info(pdev, name); ++ ++ if (!sfb) ++ goto failed; ++ ++ sm7xx_init_hw(); ++ ++ /*get mode parameter from smtc_screen_info */ ++ if (smtc_screen_info.lfb_width != 0) { ++ sfb->fb.var.xres = smtc_screen_info.lfb_width; ++ sfb->fb.var.yres = smtc_screen_info.lfb_height; ++ sfb->fb.var.bits_per_pixel = smtc_screen_info.lfb_depth; ++ } else { ++ /* default resolution 1024x600 16bit mode */ ++ sfb->fb.var.xres = SCREEN_X_RES; ++ sfb->fb.var.yres = SCREEN_Y_RES; ++ sfb->fb.var.bits_per_pixel = SCREEN_BPP; ++ } ++ ++ smdbg("\nsfb->fb.var.bits_per_pixel = %d sm712be_flag = %d\n", ++ sfb->fb.var.bits_per_pixel, sm712be_flag); ++#ifdef __BIG_ENDIAN ++ if (sm712be_flag == 1 && sfb->fb.var.bits_per_pixel == 24) ++ sfb->fb.var.bits_per_pixel = (smtc_screen_info.lfb_depth = 32); ++#endif ++ /* Map address and memory detection */ ++ pFramebufferPhysical = pci_resource_start(pdev, 0); ++ pci_read_config_byte(pdev, PCI_REVISION_ID, &hw.chipRevID); ++ ++ switch (hw.chipID) { ++ case 0x710: ++ case 0x712: ++ sfb->fb.fix.mmio_start = pFramebufferPhysical + 0x00400000; ++ sfb->fb.fix.mmio_len = 0x00400000; ++ smem_size = SM712_VIDEOMEMORYSIZE; ++#ifdef __BIG_ENDIAN ++ hw.m_pLFB = (smtc_VRAMBaseAddress = ++ ioremap(pFramebufferPhysical, 0x00c00000)); ++#else ++ hw.m_pLFB = (smtc_VRAMBaseAddress = ++ ioremap(pFramebufferPhysical, 0x00800000)); ++#endif ++ hw.m_pMMIO = (smtc_RegBaseAddress = ++ smtc_VRAMBaseAddress + 0x00700000); ++ smtc_2DBaseAddress = (hw.m_pDPR = ++ smtc_VRAMBaseAddress + 0x00408000); ++ smtc_2Ddataport = smtc_VRAMBaseAddress + DE_DATA_PORT_712; ++ hw.m_pVPR = hw.m_pLFB + 0x0040c000; ++ if (sfb->fb.var.bits_per_pixel == 32) { ++#ifdef __BIG_ENDIAN ++ smtc_VRAMBaseAddress += 0x800000; ++ hw.m_pLFB += 0x800000; ++ printk(KERN_INFO ++ "\nsmtc_VRAMBaseAddress=%p hw.m_pLFB=%p\n", ++ smtc_VRAMBaseAddress, hw.m_pLFB); ++#endif ++ } ++ if (!smtc_RegBaseAddress) { ++ ++ printk(KERN_INFO ++ "%s: unable to map memory mapped IO\n", ++ sfb->fb.fix.id); ++ ++ return -ENOMEM; ++ } ++ ++ /* set MCLK = 14.31818 * (0x16 / 0x2) */ ++ smtc_seqw(0x6a, 0x16); ++ smtc_seqw(0x6b, 0x02); ++ smtc_seqw(0x62, 0x3e); ++ /* enable PCI burst */ ++ smtc_seqw(0x17, 0x20); ++ /* enabel word swap */ ++ if (sfb->fb.var.bits_per_pixel == 32) { ++#ifdef __BIG_ENDIAN ++ smtc_seqw(0x17, 0x30); ++#endif ++ } ++#ifdef CONFIG_FB_SM7XX_ACCEL ++ smtc_2Dacceleration = 1; ++#endif ++ ++ break; ++ ++ case 0x720: ++ sfb->fb.fix.mmio_start = pFramebufferPhysical; ++ sfb->fb.fix.mmio_len = 0x00200000; ++ smem_size = SM722_VIDEOMEMORYSIZE; ++ smtc_2DBaseAddress = (hw.m_pDPR = ++ ioremap(pFramebufferPhysical, 0x00a00000)); ++ hw.m_pLFB = (smtc_VRAMBaseAddress = ++ smtc_2DBaseAddress + 0x00200000); ++ hw.m_pMMIO = (smtc_RegBaseAddress = ++ smtc_2DBaseAddress + 0x000c0000); ++ smtc_2Ddataport = smtc_2DBaseAddress + DE_DATA_PORT_722; ++ hw.m_pVPR = smtc_2DBaseAddress + 0x800; ++ ++ smtc_seqw(0x62, 0xff); ++ smtc_seqw(0x6a, 0x0d); ++ smtc_seqw(0x6b, 0x02); ++ smtc_2Dacceleration = 0; ++ break; ++ default: ++ printk(KERN_INFO ++ "No valid Silicon Motion display chip was detected!\n"); ++ ++ smtc_free_fb_info(sfb); ++ return err; ++ } ++ ++ /* can support 32 bpp */ ++ if (15 == sfb->fb.var.bits_per_pixel) ++ sfb->fb.var.bits_per_pixel = 16; ++ ++ sfb->fb.var.xres_virtual = sfb->fb.var.xres; ++ ++ sfb->fb.var.yres_virtual = sfb->fb.var.yres; ++ err = smtc_map_smem(sfb, pdev, smem_size); ++ if (err) ++ goto failed; ++ ++ smtcfb_setmode(sfb); ++ /* Primary display starting from 0 postion */ ++ hw.BaseAddressInVRAM = 0; ++ sfb->fb.par = &hw; ++ ++ err = register_framebuffer(&sfb->fb); ++ if (err < 0) ++ goto failed; ++ ++ printk(KERN_INFO "Silicon Motion SM%X Rev%X primary display mode" ++ "%dx%d-%d Init Complete.\n", hw.chipID, hw.chipRevID, ++ sfb->fb.var.xres, sfb->fb.var.yres, ++ sfb->fb.var.bits_per_pixel); ++ ++#if defined(CONFIG_FB_SM7XX_DUALHEAD) ++ smtc_head2_init(sfb); ++ err = register_framebuffer(&smtcfb_info2.fb); ++ ++ /* if second head display fails, also fails the primary display */ ++ if (err < 0) { ++ printk(KERN_INFO ++ "Silicon Motion, Inc. second head init fail\n"); ++ goto failed; ++ } ++ ++ printk(KERN_INFO "Silicon Motion SM%X Rev%X secondary display mode" ++ "%dx%d-%d Init Complete.\n", hw.chipID, hw.chipRevID, ++ hw2.width, hw2.height, ++ smtcfb_info2.fb.var.bits_per_pixel); ++#endif ++ ++ return 0; ++ ++ failed: ++ printk(KERN_INFO "Silicon Motion, Inc. primary display init fail\n"); ++ ++ smtc_unmap_smem(sfb); ++ smtc_unmap_mmio(sfb); ++ smtc_free_fb_info(sfb); ++ ++ return err; ++} ++ ++static void __exit smtcfb_exit(void) ++{ ++} ++ ++module_init(smtcfb_init); ++module_exit(smtcfb_exit); ++ ++/* ++ * sm712be_setup - process command line options ++ * @options: string of options ++ * Returns zero. ++ * ++ */ ++static int __init sm712be_setup(char *options) ++{ ++ sm712be_flag = 0; ++ if (!options || !*options) { ++ smdbg("\n No sm712be parameter\n"); ++ return -EINVAL; ++ } ++ if (strstr(options, "enable") != NULL) ++ sm712be_flag = 1; ++ ++ smdbg("\nsm712be_setup = %s sm712be_flag = %d\n", options, ++ sm712be_flag); ++ ++ return 0; ++} ++ ++__setup("sm712be=", sm712be_setup); ++ ++/* ++ * sm712vga_setup - process command line options, get vga parameter ++ * @options: string of options ++ * Returns zero. ++ * ++ */ ++static int __init sm712vga_setup(char *options) ++{ ++ int index; ++ sm712be_flag = 0; ++ ++ if (!options || !*options) { ++ smdbg("\n No vga parameter\n"); ++ return -EINVAL; ++ } ++ ++ smtc_screen_info.lfb_width = 0; ++ smtc_screen_info.lfb_height = 0; ++ smtc_screen_info.lfb_depth = 0; ++ ++ smdbg("\nsm712vga_setup = %s\n", options); ++ ++ for (index = 0; ++ index < (sizeof(vesa_mode) / sizeof(struct vesa_mode_table)); ++ index++) { ++ if (strstr(options, vesa_mode[index].mode_index)) { ++ smtc_screen_info.lfb_width = vesa_mode[index].lfb_width; ++ smtc_screen_info.lfb_height = ++ vesa_mode[index].lfb_height; ++ smtc_screen_info.lfb_depth = vesa_mode[index].lfb_depth; ++ return 0; ++ } ++ } ++ ++ return -1; ++} ++ ++__setup("vga=", sm712vga_setup); ++ ++MODULE_AUTHOR("Siliconmotion "); ++MODULE_DESCRIPTION("Framebuffer driver for SMI Graphic Cards"); ++MODULE_LICENSE("GPL"); +diff -Nur linux-2.6.30/drivers/video/sm7xx/smtcfb.h rt4ls/drivers/video/sm7xx/smtcfb.h +--- linux-2.6.30/drivers/video/sm7xx/smtcfb.h 1970-01-01 01:00:00.000000000 +0100 ++++ rt4ls/drivers/video/sm7xx/smtcfb.h 2009-06-12 16:28:47.728622169 +0200 +@@ -0,0 +1,793 @@ ++/* ++ * smtcfb.h -- Silicon Motion SM7xx frame buffer device ++ * ++ * Copyright (C) 2006 Silicon Motion Technology Corp. ++ * Authors: Ge Wang, gewang@siliconmotion.com ++ * Boyod boyod.yang@siliconmotion.com.cn ++ * ++ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology ++ * Author: Wu Zhangjin, wuzj@lemote.com ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ */ ++ ++#define SMTC_LINUX_FB_VERSION "version 0.11.2619.21.01 July 27, 2008" ++ ++#define NR_PALETTE 256 ++#define NR_RGB 2 ++ ++#define FB_ACCEL_SMI_LYNX 88 ++ ++#ifdef __BIG_ENDIAN ++#define PC_VGA 0 ++#else ++#define PC_VGA 1 ++#endif ++ ++#define SCREEN_X_RES 1024 ++#define SCREEN_Y_RES 600 ++#define SCREEN_BPP 16 ++ ++#ifndef FIELD_OFFSET ++#define FIELD_OFSFET(type, field) \ ++ ((unsigned long) (PUCHAR) & (((type *)0)->field)) ++#endif ++ ++/*Assume SM712 graphics chip has 4MB VRAM */ ++#define SM712_VIDEOMEMORYSIZE 0x00400000 ++/*Assume SM722 graphics chip has 8MB VRAM */ ++#define SM722_VIDEOMEMORYSIZE 0x00800000 ++ ++#define dac_reg (0x3c8) ++#define dac_val (0x3c9) ++ ++extern char *smtc_RegBaseAddress; ++#define smtc_mmiowb(dat, reg) writeb(dat, smtc_RegBaseAddress + reg) ++#define smtc_mmioww(dat, reg) writew(dat, smtc_RegBaseAddress + reg) ++#define smtc_mmiowl(dat, reg) writel(dat, smtc_RegBaseAddress + reg) ++ ++#define smtc_mmiorb(reg) readb(smtc_RegBaseAddress + reg) ++#define smtc_mmiorw(reg) readw(smtc_RegBaseAddress + reg) ++#define smtc_mmiorl(reg) readl(smtc_RegBaseAddress + reg) ++ ++#define SIZE_SR00_SR04 (0x04 - 0x00 + 1) ++#define SIZE_SR10_SR24 (0x24 - 0x10 + 1) ++#define SIZE_SR30_SR75 (0x75 - 0x30 + 1) ++#define SIZE_SR80_SR93 (0x93 - 0x80 + 1) ++#define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1) ++#define SIZE_GR00_GR08 (0x08 - 0x00 + 1) ++#define SIZE_AR00_AR14 (0x14 - 0x00 + 1) ++#define SIZE_CR00_CR18 (0x18 - 0x00 + 1) ++#define SIZE_CR30_CR4D (0x4D - 0x30 + 1) ++#define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1) ++#define SIZE_VPR (0x6C + 1) ++#define SIZE_DPR (0x44 + 1) ++ ++static inline void smtc_crtcw(int reg, int val) ++{ ++ smtc_mmiowb(reg, 0x3d4); ++ smtc_mmiowb(val, 0x3d5); ++} ++ ++static inline unsigned int smtc_crtcr(int reg) ++{ ++ smtc_mmiowb(reg, 0x3d4); ++ return smtc_mmiorb(0x3d5); ++} ++ ++static inline void smtc_grphw(int reg, int val) ++{ ++ smtc_mmiowb(reg, 0x3ce); ++ smtc_mmiowb(val, 0x3cf); ++} ++ ++static inline unsigned int smtc_grphr(int reg) ++{ ++ smtc_mmiowb(reg, 0x3ce); ++ return smtc_mmiorb(0x3cf); ++} ++ ++static inline void smtc_attrw(int reg, int val) ++{ ++ smtc_mmiorb(0x3da); ++ smtc_mmiowb(reg, 0x3c0); ++ smtc_mmiorb(0x3c1); ++ smtc_mmiowb(val, 0x3c0); ++} ++ ++static inline void smtc_seqw(int reg, int val) ++{ ++ smtc_mmiowb(reg, 0x3c4); ++ smtc_mmiowb(val, 0x3c5); ++} ++ ++static inline unsigned int smtc_seqr(int reg) ++{ ++ smtc_mmiowb(reg, 0x3c4); ++ return smtc_mmiorb(0x3c5); ++} ++ ++/* The next structure holds all information relevant for a specific video mode. ++ */ ++ ++struct ModeInit { ++ int mmSizeX; ++ int mmSizeY; ++ int bpp; ++ int hz; ++ unsigned char Init_MISC; ++ unsigned char Init_SR00_SR04[SIZE_SR00_SR04]; ++ unsigned char Init_SR10_SR24[SIZE_SR10_SR24]; ++ unsigned char Init_SR30_SR75[SIZE_SR30_SR75]; ++ unsigned char Init_SR80_SR93[SIZE_SR80_SR93]; ++ unsigned char Init_SRA0_SRAF[SIZE_SRA0_SRAF]; ++ unsigned char Init_GR00_GR08[SIZE_GR00_GR08]; ++ unsigned char Init_AR00_AR14[SIZE_AR00_AR14]; ++ unsigned char Init_CR00_CR18[SIZE_CR00_CR18]; ++ unsigned char Init_CR30_CR4D[SIZE_CR30_CR4D]; ++ unsigned char Init_CR90_CRA7[SIZE_CR90_CRA7]; ++}; ++ ++/********************************************************************** ++ SM712 Mode table. ++ **********************************************************************/ ++struct ModeInit VGAMode[] = { ++ { ++ /* mode#0: 640 x 480 16Bpp 60Hz */ ++ 640, 480, 16, 60, ++ /* Init_MISC */ ++ 0xE3, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x00, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32, ++ 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32, ++ 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA, ++ 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32, ++ 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04, ++ 0x00, 0x45, 0x30, 0x30, 0x40, 0x30, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32, ++ 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, ++ 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E, ++ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD, ++ 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00, ++ 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55, ++ 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00, ++ 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, ++ }, ++ }, ++ { ++ /* mode#1: 640 x 480 24Bpp 60Hz */ ++ 640, 480, 24, 60, ++ /* Init_MISC */ ++ 0xE3, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x00, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32, ++ 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32, ++ 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA, ++ 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32, ++ 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04, ++ 0x00, 0x45, 0x30, 0x30, 0x40, 0x30, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32, ++ 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, ++ 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E, ++ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD, ++ 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00, ++ 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55, ++ 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00, ++ 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, ++ }, ++ }, ++ { ++ /* mode#0: 640 x 480 32Bpp 60Hz */ ++ 640, 480, 32, 60, ++ /* Init_MISC */ ++ 0xE3, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x00, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32, ++ 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32, ++ 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA, ++ 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32, ++ 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04, ++ 0x00, 0x45, 0x30, 0x30, 0x40, 0x30, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32, ++ 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, ++ 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E, ++ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD, ++ 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00, ++ 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55, ++ 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00, ++ 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, ++ }, ++ }, ++ ++ { /* mode#2: 800 x 600 16Bpp 60Hz */ ++ 800, 600, 16, 60, ++ /* Init_MISC */ ++ 0x2B, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x03, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x34, 0x03, 0x20, 0x09, 0xC0, 0x24, 0x24, 0x24, ++ 0x24, 0x24, 0x24, 0x24, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x24, 0x24, 0x24, ++ 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58, ++ 0x04, 0x55, 0x59, 0x24, 0x24, 0x00, 0x00, 0x24, ++ 0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13, ++ 0x02, 0x45, 0x30, 0x35, 0x40, 0x20, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0x00, 0x00, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x24, ++ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x24, 0x24, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, ++ 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0, ++ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD, ++ 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00, ++ 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA, ++ 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00, ++ 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00, ++ }, ++ }, ++ { /* mode#3: 800 x 600 24Bpp 60Hz */ ++ 800, 600, 24, 60, ++ 0x2B, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x03, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x36, 0x03, 0x20, 0x09, 0xC0, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x36, 0x36, 0x36, ++ 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58, ++ 0x04, 0x55, 0x59, 0x36, 0x36, 0x00, 0x00, 0x36, ++ 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13, ++ 0x02, 0x45, 0x30, 0x30, 0x40, 0x20, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x36, ++ 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x36, 0x36, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, ++ 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0, ++ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD, ++ 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00, ++ 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA, ++ 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00, ++ 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00, ++ }, ++ }, ++ { /* mode#7: 800 x 600 32Bpp 60Hz */ ++ 800, 600, 32, 60, ++ /* Init_MISC */ ++ 0x2B, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x03, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x34, 0x03, 0x20, 0x09, 0xC0, 0x24, 0x24, 0x24, ++ 0x24, 0x24, 0x24, 0x24, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x24, 0x24, 0x24, ++ 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58, ++ 0x04, 0x55, 0x59, 0x24, 0x24, 0x00, 0x00, 0x24, ++ 0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13, ++ 0x02, 0x45, 0x30, 0x35, 0x40, 0x20, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0x00, 0x00, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x24, ++ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x24, 0x24, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED, ++ 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0, ++ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD, ++ 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00, ++ 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA, ++ 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00, ++ 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00, ++ }, ++ }, ++ /* We use 1024x768 table to light 1024x600 panel for lemote */ ++ { /* mode#4: 1024 x 600 16Bpp 60Hz */ ++ 1024, 600, 16, 60, ++ /* Init_MISC */ ++ 0xEB, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x00, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xC8, 0x40, 0x14, 0x60, 0x00, 0x0A, 0x17, 0x20, ++ 0x51, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x00, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x22, 0x03, 0x24, 0x09, 0xC0, 0x22, 0x22, 0x22, ++ 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x22, 0x22, 0x22, ++ 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03, ++ 0x00, 0x60, 0x59, 0x22, 0x22, 0x00, 0x00, 0x22, ++ 0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x16, 0x02, 0x0D, 0x82, 0x09, 0x02, ++ 0x04, 0x45, 0x3F, 0x30, 0x40, 0x20, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A, ++ 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED, ++ 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5, ++ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF, ++ 0xA3, 0x7F, 0x00, 0x82, 0x0b, 0x6f, 0x57, 0x00, ++ 0x5c, 0x0f, 0xE0, 0xe0, 0x7F, 0x57, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26, ++ 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00, ++ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03, ++ }, ++ }, ++ { /* mode#5: 1024 x 768 24Bpp 60Hz */ ++ 1024, 768, 24, 60, ++ /* Init_MISC */ ++ 0xEB, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x03, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x30, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A, ++ 0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A, ++ 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03, ++ 0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A, ++ 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x3B, 0x0D, 0x09, 0x02, ++ 0x04, 0x45, 0x30, 0x30, 0x40, 0x20, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A, ++ 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED, ++ 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5, ++ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF, ++ 0xA3, 0x7F, 0x00, 0x86, 0x15, 0x24, 0xFF, 0x00, ++ 0x01, 0x07, 0xE5, 0x20, 0x7F, 0xFF, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26, ++ 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00, ++ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03, ++ }, ++ }, ++ { /* mode#4: 1024 x 768 32Bpp 60Hz */ ++ 1024, 768, 32, 60, ++ /* Init_MISC */ ++ 0xEB, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x03, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x32, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A, ++ 0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A, ++ 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03, ++ 0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A, ++ 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x3B, 0x0D, 0x09, 0x02, ++ 0x04, 0x45, 0x30, 0x30, 0x40, 0x20, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A, ++ 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED, ++ 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5, ++ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20, ++ 0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF, ++ 0xA3, 0x7F, 0x00, 0x86, 0x15, 0x24, 0xFF, 0x00, ++ 0x01, 0x07, 0xE5, 0x20, 0x7F, 0xFF, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26, ++ 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00, ++ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03, ++ }, ++ }, ++ { /* mode#6: 320 x 240 16Bpp 60Hz */ ++ 320, 240, 16, 60, ++ /* Init_MISC */ ++ 0xEB, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x03, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x32, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A, ++ 0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A, ++ 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03, ++ 0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A, ++ 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x08, 0x43, 0x08, 0x43, ++ 0x04, 0x45, 0x30, 0x30, 0x40, 0x20, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A, ++ 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED, ++ 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5, ++ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20, ++ 0x00, 0x00, 0x30, 0x40, 0x00, 0xFF, 0xBF, 0xFF, ++ 0x2E, 0x27, 0x00, 0x2b, 0x0c, 0x0F, 0xEF, 0x00, ++ 0xFe, 0x0f, 0x01, 0xC0, 0x27, 0xEF, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26, ++ 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00, ++ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03, ++ }, ++ }, ++ ++ { /* mode#8: 320 x 240 32Bpp 60Hz */ ++ 320, 240, 32, 60, ++ /* Init_MISC */ ++ 0xEB, ++ { /* Init_SR0_SR4 */ ++ 0x03, 0x01, 0x0F, 0x03, 0x0E, ++ }, ++ { /* Init_SR10_SR24 */ ++ 0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C, ++ 0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC4, 0x32, 0x02, 0x01, 0x01, ++ }, ++ { /* Init_SR30_SR75 */ ++ 0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A, ++ 0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF, ++ 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC, ++ 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A, ++ 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03, ++ 0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A, ++ 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00, ++ 0x50, 0x03, 0x74, 0x14, 0x08, 0x43, 0x08, 0x43, ++ 0x04, 0x45, 0x30, 0x30, 0x40, 0x20, ++ }, ++ { /* Init_SR80_SR93 */ ++ 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A, ++ 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A, ++ 0x00, 0x00, 0x00, 0x00, ++ }, ++ { /* Init_SRA0_SRAF */ ++ 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED, ++ 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF, ++ }, ++ { /* Init_GR00_GR08 */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, ++ 0xFF, ++ }, ++ { /* Init_AR00_AR14 */ ++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x41, 0x00, 0x0F, 0x00, 0x00, ++ }, ++ { /* Init_CR00_CR18 */ ++ 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5, ++ 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3, ++ 0xFF, ++ }, ++ { /* Init_CR30_CR4D */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20, ++ 0x00, 0x00, 0x30, 0x40, 0x00, 0xFF, 0xBF, 0xFF, ++ 0x2E, 0x27, 0x00, 0x2b, 0x0c, 0x0F, 0xEF, 0x00, ++ 0xFe, 0x0f, 0x01, 0xC0, 0x27, 0xEF, ++ }, ++ { /* Init_CR90_CRA7 */ ++ 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26, ++ 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00, ++ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03, ++ }, ++ }, ++}; ++ ++#define numVGAModes (sizeof(VGAMode) / sizeof(struct ModeInit)) +diff -Nur linux-2.6.30/fs/autofs4/waitq.c rt4ls/fs/autofs4/waitq.c +--- linux-2.6.30/fs/autofs4/waitq.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/fs/autofs4/waitq.c 2009-06-12 16:28:48.180649291 +0200 +@@ -297,14 +297,20 @@ + */ + if (notify == NFY_MOUNT) { + /* +- * If the dentry was successfully mounted while we slept +- * on the wait queue mutex we can return success. If it +- * isn't mounted (doesn't have submounts for the case of +- * a multi-mount with no mount at it's base) we can +- * continue on and create a new request. +- */ +- if (have_submounts(dentry)) +- return 0; ++ * If the dentry isn't hashed just go ahead and try the ++ * mount again with a new wait (not much else we can do). ++ */ ++ if (!d_unhashed(dentry)) { ++ /* ++ * But if the dentry is hashed, that means that we ++ * got here through the revalidate path. Thus, we ++ * need to check if the dentry has been mounted ++ * while we waited on the wq_mutex. If it has, ++ * simply return success. ++ */ ++ if (d_mountpoint(dentry)) ++ return 0; ++ } + } + + return 1; +diff -Nur linux-2.6.30/fs/jbd/commit.c rt4ls/fs/jbd/commit.c +--- linux-2.6.30/fs/jbd/commit.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/fs/jbd/commit.c 2009-06-12 16:28:48.464665929 +0200 +@@ -241,7 +241,7 @@ + spin_lock(&journal->j_list_lock); + } + /* Someone already cleaned up the buffer? */ +- if (!buffer_jbd(bh) || bh2jh(bh) != jh ++ if (!buffer_jbd(bh) + || jh->b_transaction != commit_transaction + || jh->b_jlist != BJ_SyncData) { + jbd_unlock_bh_state(bh); +@@ -478,9 +478,7 @@ + spin_lock(&journal->j_list_lock); + continue; + } +- if (buffer_jbd(bh) && bh2jh(bh) == jh && +- jh->b_transaction == commit_transaction && +- jh->b_jlist == BJ_Locked) { ++ if (buffer_jbd(bh) && jh->b_jlist == BJ_Locked) { + __journal_unfile_buffer(jh); + jbd_unlock_bh_state(bh); + journal_remove_journal_head(bh); +diff -Nur linux-2.6.30/include/linux/cpumask.h rt4ls/include/linux/cpumask.h +--- linux-2.6.30/include/linux/cpumask.h 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/include/linux/cpumask.h 2009-06-12 16:29:16.018395927 +0200 +@@ -1022,8 +1022,6 @@ + + bool alloc_cpumask_var_node(cpumask_var_t *mask, gfp_t flags, int node); + bool alloc_cpumask_var(cpumask_var_t *mask, gfp_t flags); +-bool zalloc_cpumask_var_node(cpumask_var_t *mask, gfp_t flags, int node); +-bool zalloc_cpumask_var(cpumask_var_t *mask, gfp_t flags); + void alloc_bootmem_cpumask_var(cpumask_var_t *mask); + void free_cpumask_var(cpumask_var_t mask); + void free_bootmem_cpumask_var(cpumask_var_t mask); +@@ -1042,19 +1040,6 @@ + return true; + } + +-static inline bool zalloc_cpumask_var(cpumask_var_t *mask, gfp_t flags) +-{ +- cpumask_clear(*mask); +- return true; +-} +- +-static inline bool zalloc_cpumask_var_node(cpumask_var_t *mask, gfp_t flags, +- int node) +-{ +- cpumask_clear(*mask); +- return true; +-} +- + static inline void alloc_bootmem_cpumask_var(cpumask_var_t *mask) + { + } +diff -Nur linux-2.6.30/ipc/shm.c rt4ls/ipc/shm.c +--- linux-2.6.30/ipc/shm.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/ipc/shm.c 2009-06-12 16:29:47.289072291 +0200 +@@ -969,13 +969,10 @@ + SYSCALL_DEFINE1(shmdt, char __user *, shmaddr) + { + struct mm_struct *mm = current->mm; +- struct vm_area_struct *vma; ++ struct vm_area_struct *vma, *next; + unsigned long addr = (unsigned long)shmaddr; +- int retval = -EINVAL; +-#ifdef CONFIG_MMU + loff_t size = 0; +- struct vm_area_struct *next; +-#endif ++ int retval = -EINVAL; + + if (addr & ~PAGE_MASK) + return retval; +diff -Nur linux-2.6.30/kernel/sched_cpupri.c rt4ls/kernel/sched_cpupri.c +--- linux-2.6.30/kernel/sched_cpupri.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/kernel/sched_cpupri.c 2009-06-12 16:29:48.957102637 +0200 +@@ -165,7 +165,7 @@ + vec->count = 0; + if (bootmem) + alloc_bootmem_cpumask_var(&vec->mask); +- else if (!zalloc_cpumask_var(&vec->mask, GFP_KERNEL)) ++ else if (!alloc_cpumask_var(&vec->mask, GFP_KERNEL)) + goto cleanup; + } + +diff -Nur linux-2.6.30/kernel/sched_rt.c rt4ls/kernel/sched_rt.c +--- linux-2.6.30/kernel/sched_rt.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/kernel/sched_rt.c 2009-06-12 16:29:48.969124560 +0200 +@@ -1591,7 +1591,7 @@ + unsigned int i; + + for_each_possible_cpu(i) +- zalloc_cpumask_var_node(&per_cpu(local_cpu_mask, i), ++ alloc_cpumask_var_node(&per_cpu(local_cpu_mask, i), + GFP_KERNEL, cpu_to_node(i)); + } + #endif /* CONFIG_SMP */ +diff -Nur linux-2.6.30/kernel/smp.c rt4ls/kernel/smp.c +--- linux-2.6.30/kernel/smp.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/kernel/smp.c 2009-06-12 16:29:48.969124560 +0200 +@@ -52,7 +52,7 @@ + switch (action) { + case CPU_UP_PREPARE: + case CPU_UP_PREPARE_FROZEN: +- if (!zalloc_cpumask_var_node(&cfd->cpumask, GFP_KERNEL, ++ if (!alloc_cpumask_var_node(&cfd->cpumask, GFP_KERNEL, + cpu_to_node(cpu))) + return NOTIFY_BAD; + break; +diff -Nur linux-2.6.30/lib/cpumask.c rt4ls/lib/cpumask.c +--- linux-2.6.30/lib/cpumask.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/lib/cpumask.c 2009-06-12 16:29:49.032452180 +0200 +@@ -119,12 +119,6 @@ + } + EXPORT_SYMBOL(alloc_cpumask_var_node); + +-bool zalloc_cpumask_var_node(cpumask_var_t *mask, gfp_t flags, int node) +-{ +- return alloc_cpumask_var_node(mask, flags | __GFP_ZERO, node); +-} +-EXPORT_SYMBOL(zalloc_cpumask_var_node); +- + /** + * alloc_cpumask_var - allocate a struct cpumask + * @mask: pointer to cpumask_var_t where the cpumask is returned +@@ -141,12 +135,6 @@ + } + EXPORT_SYMBOL(alloc_cpumask_var); + +-bool zalloc_cpumask_var(cpumask_var_t *mask, gfp_t flags) +-{ +- return alloc_cpumask_var(mask, flags | __GFP_ZERO); +-} +-EXPORT_SYMBOL(zalloc_cpumask_var); +- + /** + * alloc_bootmem_cpumask_var - allocate a struct cpumask from the bootmem arena. + * @mask: pointer to cpumask_var_t where the cpumask is returned +diff -Nur linux-2.6.30/net/sched/cls_cgroup.c rt4ls/net/sched/cls_cgroup.c +--- linux-2.6.30/net/sched/cls_cgroup.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/net/sched/cls_cgroup.c 2009-06-12 16:29:50.516543166 +0200 +@@ -167,9 +167,6 @@ + struct tcf_exts e; + int err; + +- if (!tca[TCA_OPTIONS]) +- return -EINVAL; +- + if (head == NULL) { + if (!handle) + return -EINVAL; +diff -Nur linux-2.6.30/sound/core/pcm_native.c rt4ls/sound/core/pcm_native.c +--- linux-2.6.30/sound/core/pcm_native.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/sound/core/pcm_native.c 2009-06-12 16:29:54.880818910 +0200 +@@ -3091,7 +3091,11 @@ + return VM_FAULT_SIGBUS; + } else { + vaddr = runtime->dma_area + offset; ++#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) ++ page = virt_to_page(CAC_ADDR(vaddr)); ++#else + page = virt_to_page(vaddr); ++#endif + } + get_page(page); + vmf->page = page; +@@ -3206,6 +3210,11 @@ + if (PCM_RUNTIME_CHECK(substream)) + return -ENXIO; + ++#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) ++ /* all mmap using uncached mode */ ++ area->vm_page_prot = pgprot_noncached(area->vm_page_prot); ++ area->vm_flags |= (VM_RESERVED | VM_IO); ++#endif + offset = area->vm_pgoff << PAGE_SHIFT; + switch (offset) { + case SNDRV_PCM_MMAP_OFFSET_STATUS: +diff -Nur linux-2.6.30/sound/core/sgbuf.c rt4ls/sound/core/sgbuf.c +--- linux-2.6.30/sound/core/sgbuf.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/sound/core/sgbuf.c 2009-06-12 16:29:54.904819175 +0200 +@@ -114,7 +114,11 @@ + if (!i) + table->addr |= chunk; /* mark head */ + table++; ++#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) ++ *pgtable++ = virt_to_page(CAC_ADDR(tmpb.area)); ++#else + *pgtable++ = virt_to_page(tmpb.area); ++#endif + tmpb.area += PAGE_SIZE; + tmpb.addr += PAGE_SIZE; + } +@@ -125,7 +129,12 @@ + } + + sgbuf->size = size; ++#if defined(__mips__) && defined(CONFIG_DMA_NONCOHERENT) ++ dmab->area = vmap(sgbuf->page_table, sgbuf->pages, \ ++ VM_MAP | VM_IO, pgprot_noncached(PAGE_KERNEL)); ++#else + dmab->area = vmap(sgbuf->page_table, sgbuf->pages, VM_MAP, PAGE_KERNEL); ++#endif + if (! dmab->area) + goto _failed; + if (res_size) +diff -Nur linux-2.6.30/sound/pci/Kconfig rt4ls/sound/pci/Kconfig +--- linux-2.6.30/sound/pci/Kconfig 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/sound/pci/Kconfig 2009-06-12 16:29:55.036828170 +0200 +@@ -259,7 +259,6 @@ + + config SND_CS5535AUDIO + tristate "CS5535/CS5536 Audio" +- depends on X86 && !X86_64 + select SND_PCM + select SND_AC97_CODEC + help +diff -Nur linux-2.6.30/virt/kvm/kvm_main.c rt4ls/virt/kvm/kvm_main.c +--- linux-2.6.30/virt/kvm/kvm_main.c 2009-06-10 05:05:27.000000000 +0200 ++++ rt4ls/virt/kvm/kvm_main.c 2009-06-12 16:29:55.860876705 +0200 +@@ -2301,7 +2301,7 @@ + + bad_pfn = page_to_pfn(bad_page); + +- if (!zalloc_cpumask_var(&cpus_hardware_enabled, GFP_KERNEL)) { ++ if (!alloc_cpumask_var(&cpus_hardware_enabled, GFP_KERNEL)) { + r = -ENOMEM; + goto out_free_0; + } diff --git a/toolchain/gcc/Makefile b/toolchain/gcc/Makefile index e573d922e..4d9a75e4e 100644 --- a/toolchain/gcc/Makefile +++ b/toolchain/gcc/Makefile @@ -23,6 +23,7 @@ GCC_CONFOPTS= --prefix=$(STAGING_TOOLS) \ --with-gnu-ld \ --without-headers \ --disable-libmudflap \ + --enable-sjlj-exceptions \ --disable-libgomp \ --disable-biarch \ --disable-multilib \ |