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authorWaldemar Brodkorb <wbx@openadk.org>2023-01-09 16:55:58 +0100
committerWaldemar Brodkorb <wbx@openadk.org>2023-01-19 03:47:13 +0100
commitcee21cdad9a4686842ccb54ef3b4485dcb4ab1f7 (patch)
tree0eebfd9ff4a95e9dd0d968f1c396206ba07a176a /toolchain/elf2flt/patches
parenta27d69db62e3f87affc00e5df02fd9cb678ae5a5 (diff)
riscv32: add basic nommu support
Diffstat (limited to 'toolchain/elf2flt/patches')
-rw-r--r--toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch46
-rw-r--r--toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch66
2 files changed, 112 insertions, 0 deletions
diff --git a/toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch b/toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch
new file mode 100644
index 000000000..be5b0c33e
--- /dev/null
+++ b/toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch
@@ -0,0 +1,46 @@
+diff -Nur elf2flt-v2021.08.orig/elf2flt.c elf2flt-v2021.08/elf2flt.c
+--- elf2flt-v2021.08.orig/elf2flt.c 2023-01-09 11:08:28.637676113 +0100
++++ elf2flt-v2021.08/elf2flt.c 2023-01-09 11:09:04.502804007 +0100
+@@ -835,7 +835,20 @@
+ continue;
+ case R_XTENSA_32:
+ case R_XTENSA_PLT:
+- goto good_32bit_resolved_reloc;
++ if (bfd_big_endian (abs_bfd))
++ sym_addr =
++ (r_mem[0] << 24)
++ + (r_mem[1] << 16)
++ + (r_mem[2] << 8)
++ + r_mem[3];
++ else
++ sym_addr =
++ r_mem[0]
++ + (r_mem[1] << 8)
++ + (r_mem[2] << 16)
++ + (r_mem[3] << 24);
++ relocation_needed = 1;
++ break;
+ default:
+ goto bad_resolved_reloc;
+ #elif defined(TARGET_riscv64)
+diff -Nur elf2flt-v2021.08.orig/elf2flt.c.orig elf2flt-v2021.08/elf2flt.c.orig
+--- elf2flt-v2021.08.orig/elf2flt.c.orig 2023-01-09 11:08:22.417478947 +0100
++++ elf2flt-v2021.08/elf2flt.c.orig 2023-01-09 11:08:28.637676113 +0100
+@@ -349,8 +349,15 @@
+ static bool
+ ro_reloc_data_section_should_be_in_text(asection *s)
+ {
+- return (s->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) ==
+- (SEC_DATA | SEC_READONLY | SEC_RELOC);
++ if ((s->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) ==
++ (SEC_DATA | SEC_READONLY | SEC_RELOC)) {
++#if defined(TARGET_m68k) || defined(TARGET_riscv64) || defined(TARGET_xtensa)
++ if (!strcmp(".eh_frame", s->name))
++ return false;
++#endif
++ return true;
++ }
++ return false;
+ }
+
+ static uint32_t *
diff --git a/toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch b/toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch
new file mode 100644
index 000000000..dad501482
--- /dev/null
+++ b/toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch
@@ -0,0 +1,66 @@
+diff -Nur elf2flt-v2021.08.orig/elf2flt.c elf2flt-v2021.08/elf2flt.c
+--- elf2flt-v2021.08.orig/elf2flt.c 2023-01-09 11:08:28.637676113 +0100
++++ elf2flt-v2021.08/elf2flt.c 2023-01-09 11:16:05.447182514 +0100
+@@ -81,7 +81,7 @@
+ #include <elf/v850.h>
+ #elif defined(TARGET_xtensa)
+ #include <elf/xtensa.h>
+-#elif defined(TARGET_riscv64)
++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
+ #include <elf/riscv.h>
+ #endif
+
+@@ -127,6 +127,8 @@
+ #define ARCH "xtensa"
+ #elif defined(TARGET_riscv64)
+ #define ARCH "riscv64"
++#elif defined(TARGET_riscv32)
++#define ARCH "riscv32"
+ #else
+ #error "Don't know how to support your CPU architecture??"
+ #endif
+@@ -351,7 +353,8 @@
+ {
+ if ((s->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) ==
+ (SEC_DATA | SEC_READONLY | SEC_RELOC)) {
+-#if defined(TARGET_m68k) || defined(TARGET_riscv64) || defined(TARGET_xtensa)
++#if defined(TARGET_m68k) || defined(TARGET_riscv64) || \
++ defined(TARGET_xtensa) || defined(TARGET_riscv32)
+ if (!strcmp(".eh_frame", s->name))
+ return false;
+ #endif
+@@ -838,12 +841,21 @@
+ goto good_32bit_resolved_reloc;
+ default:
+ goto bad_resolved_reloc;
+-#elif defined(TARGET_riscv64)
++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
+ case R_RISCV_32_PCREL:
++ case R_RISCV_ADD8:
++ case R_RISCV_ADD16:
+ case R_RISCV_ADD32:
+ case R_RISCV_ADD64:
++ case R_RISCV_SUB6:
++ case R_RISCV_SUB8:
++ case R_RISCV_SUB16:
+ case R_RISCV_SUB32:
+ case R_RISCV_SUB64:
++ case R_RISCV_SET6:
++ case R_RISCV_SET8:
++ case R_RISCV_SET16:
++ case R_RISCV_SET32:
+ continue;
+ case R_RISCV_32:
+ case R_RISCV_64:
+diff -Nur elf2flt-v2021.08.orig/ld-elf2flt.c elf2flt-v2021.08/ld-elf2flt.c
+--- elf2flt-v2021.08.orig/ld-elf2flt.c 2023-01-09 11:08:16.441289072 +0100
++++ elf2flt-v2021.08/ld-elf2flt.c 2023-01-09 11:16:43.236237537 +0100
+@@ -327,7 +327,7 @@
+ /* riscv adds a global pointer symbol to the linker file with the
+ "RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and
+ the entire line for other architectures. */
+- if (streq(TARGET_CPU, "riscv64"))
++ if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32"))
+ append_sed(&sed, "^RISCV_GP:", "");
+ else
+ append_sed(&sed, "^RISCV_GP:", NULL);