cris: hack around broken driver patch

1 files changed, 4050 insertions, 0 deletions

diff --git a/target/cris/qemu-cris/patches/4.4.6/crisv32_ethernet_driver.patch b/target/cris/qemu-cris/patches/4.4.6/crisv32_ethernet_driver.patch
new file mode 100644
index 000000000..80f03383c
--- /dev/null
+++ b/target/cris/qemu-cris/patches/4.4.6/crisv32_ethernet_driver.patch
@@ -0,0 +1,4050 @@
+diff -Nur linux-4.4.6.orig/arch/cris/arch-v32/drivers/Kconfig linux-4.4.6/arch/cris/arch-v32/drivers/Kconfig
+--- linux-4.4.6.orig/arch/cris/arch-v32/drivers/Kconfig	2016-03-16 16:43:17.000000000 +0100
++++ linux-4.4.6/arch/cris/arch-v32/drivers/Kconfig	2016-03-20 11:35:09.089964990 +0100
+@@ -8,9 +8,18 @@
+ 	  This option enables the ETRAX FS built-in 10/100Mbit Ethernet
+ 	  controller.
+ 
++config ETRAX_HAVE_PHY
++        bool "PHY present"
++	default y
++        help
++          Search and use the first PHY available on the MDIO bus. Fail
++          if none is found. Say Y here if you are not in a switched
++          environment (single port device).
++
+ config ETRAX_NO_PHY
+ 	bool "PHY not present"
+ 	depends on ETRAX_ETHERNET
++	default n
+ 	help
+ 	  This option disables all MDIO communication with an ethernet
+ 	  transceiver connected to the MII interface. This option shall
+@@ -18,6 +27,70 @@
+ 	  switch. This option should normally be disabled. If enabled,
+ 	  speed and duplex will be locked to 100 Mbit and full duplex.
+ 
++config ETRAX_PHY_FALLBACK
++        bool "Fixed PHY fallback"
++        depends on ETRAX_ETHERNET
++	default n
++        help
++          If no PHY is found on the MDIO bus, fall back on a fixed
++          100/Full fixed PHY. Say Y here if you need dynamic PHY
++          presence detection (switch connection where some but not
++          all ports have integrated PHYs), otherwise say N.
++
++config ETRAX_ETHERNET_IFACE0
++        depends on ETRAX_ETHERNET
++        bool "Enable network interface 0"
++
++config ETRAX_ETHERNET_IFACE1
++        depends on (ETRAX_ETHERNET && ETRAXFS)
++        bool "Enable network interface 1 (uses DMA6 and DMA7)"
++
++choice
++        prompt "Eth0 led group"
++        depends on ETRAX_ETHERNET_IFACE0
++        default ETRAX_ETH0_USE_LEDGRP0
++
++config ETRAX_ETH0_USE_LEDGRP0
++        bool "Use LED grp 0"
++        depends on ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO
++        help
++          Use LED grp 0 for eth0
++
++config ETRAX_ETH0_USE_LEDGRP1
++        bool "Use LED grp 1"
++        depends on ETRAX_NBR_LED_GRP_TWO
++        help
++          Use LED grp 1 for eth0
++
++config ETRAX_ETH0_USE_LEDGRPNULL
++        bool "Use no LEDs for eth0"
++        help
++          Use no LEDs for eth0
++endchoice
++
++choice
++        prompt "Eth1 led group"
++        depends on ETRAX_ETHERNET_IFACE1
++        default ETRAX_ETH1_USE_LEDGRP1
++
++config ETRAX_ETH1_USE_LEDGRP0
++        bool "Use LED grp 0"
++        depends on ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO
++        help
++          Use LED grp 0 for eth1
++
++config ETRAX_ETH1_USE_LEDGRP1
++        bool "Use LED grp 1"
++        depends on ETRAX_NBR_LED_GRP_TWO
++        help
++          Use LED grp 1 for eth1
++
++config ETRAX_ETH1_USE_LEDGRPNULL
++        bool "Use no LEDs for eth1"
++        help
++          Use no LEDs for eth1
++endchoice
++
+ config ETRAXFS_SERIAL
+ 	bool "Serial-port support"
+ 	depends on ETRAX_ARCH_V32
+diff -Nur linux-4.4.6.orig/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h linux-4.4.6/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h
+--- linux-4.4.6.orig/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h	2016-03-16 16:43:17.000000000 +0100
++++ linux-4.4.6/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h	2016-03-20 11:35:09.089964990 +0100
+@@ -2,69 +2,64 @@
+ #define __eth_defs_h
+ 
+ /*
+- * This file is autogenerated from
+- *   file:           eth.r
+- *     id:           eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp
+- *     last modfied: Mon Jan  9 06:06:41 2006
+- *
+- *   by /n/asic/design/tools/rdesc/rdes2c eth.r
+- *      id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $
+- * Any changes here will be lost.
+- *
+- * -*- buffer-read-only: t -*-
++ * Note: Previously this was autogenerated code from the hardware
++ * implementation. However, to enable the same file to be used
++ * for both ARTPEC-3 and ETRAX FS this file is now hand-edited.
++ * Be careful.
+  */
++
+ /* Main access macros */
+ #ifndef REG_RD
+ #define REG_RD( scope, inst, reg ) \
+-  REG_READ( reg_##scope##_##reg, \
+-            (inst) + REG_RD_ADDR_##scope##_##reg )
++	REG_READ( reg_##scope##_##reg, \
++			(inst) + REG_RD_ADDR_##scope##_##reg )
+ #endif
+ 
+ #ifndef REG_WR
+ #define REG_WR( scope, inst, reg, val ) \
+-  REG_WRITE( reg_##scope##_##reg, \
+-             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
++	REG_WRITE( reg_##scope##_##reg, \
++			(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+ #endif
+ 
+ #ifndef REG_RD_VECT
+ #define REG_RD_VECT( scope, inst, reg, index ) \
+-  REG_READ( reg_##scope##_##reg, \
+-            (inst) + REG_RD_ADDR_##scope##_##reg + \
+-	    (index) * STRIDE_##scope##_##reg )
++	REG_READ( reg_##scope##_##reg, \
++			(inst) + REG_RD_ADDR_##scope##_##reg + \
++			(index) * STRIDE_##scope##_##reg )
+ #endif
+ 
+ #ifndef REG_WR_VECT
+ #define REG_WR_VECT( scope, inst, reg, index, val ) \
+-  REG_WRITE( reg_##scope##_##reg, \
+-             (inst) + REG_WR_ADDR_##scope##_##reg + \
+-	     (index) * STRIDE_##scope##_##reg, (val) )
++	REG_WRITE( reg_##scope##_##reg, \
++			(inst) + REG_WR_ADDR_##scope##_##reg + \
++			(index) * STRIDE_##scope##_##reg, (val) )
+ #endif
+ 
+ #ifndef REG_RD_INT
+ #define REG_RD_INT( scope, inst, reg ) \
+-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
++	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+ #endif
+ 
+ #ifndef REG_WR_INT
+ #define REG_WR_INT( scope, inst, reg, val ) \
+-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
++	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+ #endif
+ 
+ #ifndef REG_RD_INT_VECT
+ #define REG_RD_INT_VECT( scope, inst, reg, index ) \
+-  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+-	    (index) * STRIDE_##scope##_##reg )
++	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
++			(index) * STRIDE_##scope##_##reg )
+ #endif
+ 
+ #ifndef REG_WR_INT_VECT
+ #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+-  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+-	     (index) * STRIDE_##scope##_##reg, (val) )
++	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
++			(index) * STRIDE_##scope##_##reg, (val) )
+ #endif
+ 
+ #ifndef REG_TYPE_CONV
+ #define REG_TYPE_CONV( type, orgtype, val ) \
+-  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
++	( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+ #endif
+ 
+ #ifndef reg_page_size
+@@ -73,306 +68,332 @@
+ 
+ #ifndef REG_ADDR
+ #define REG_ADDR( scope, inst, reg ) \
+-  ( (inst) + REG_RD_ADDR_##scope##_##reg )
++	( (inst) + REG_RD_ADDR_##scope##_##reg )
+ #endif
+ 
+ #ifndef REG_ADDR_VECT
+ #define REG_ADDR_VECT( scope, inst, reg, index ) \
+-  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+-    (index) * STRIDE_##scope##_##reg )
++	( (inst) + REG_RD_ADDR_##scope##_##reg + \
++	  (index) * STRIDE_##scope##_##reg )
+ #endif
+ 
+ /* C-code for register scope eth */
+ 
+ /* Register rw_ma0_lo, scope eth, type rw */
+ typedef struct {
+-  unsigned int addr : 32;
++	unsigned int addr : 32;
+ } reg_eth_rw_ma0_lo;
+ #define REG_RD_ADDR_eth_rw_ma0_lo 0
+ #define REG_WR_ADDR_eth_rw_ma0_lo 0
+ 
+ /* Register rw_ma0_hi, scope eth, type rw */
+ typedef struct {
+-  unsigned int addr : 16;
+-  unsigned int dummy1 : 16;
++	unsigned int addr : 16;
++	unsigned int dummy1 : 16;
+ } reg_eth_rw_ma0_hi;
+ #define REG_RD_ADDR_eth_rw_ma0_hi 4
+ #define REG_WR_ADDR_eth_rw_ma0_hi 4
+ 
+ /* Register rw_ma1_lo, scope eth, type rw */
+ typedef struct {
+-  unsigned int addr : 32;
++	unsigned int addr : 32;
+ } reg_eth_rw_ma1_lo;
+ #define REG_RD_ADDR_eth_rw_ma1_lo 8
+ #define REG_WR_ADDR_eth_rw_ma1_lo 8
+ 
+ /* Register rw_ma1_hi, scope eth, type rw */
+ typedef struct {
+-  unsigned int addr : 16;
+-  unsigned int dummy1 : 16;
++	unsigned int addr : 16;
++	unsigned int dummy1 : 16;
+ } reg_eth_rw_ma1_hi;
+ #define REG_RD_ADDR_eth_rw_ma1_hi 12
+ #define REG_WR_ADDR_eth_rw_ma1_hi 12
+ 
+ /* Register rw_ga_lo, scope eth, type rw */
+ typedef struct {
+-  unsigned int tbl : 32;
++	unsigned int table : 32;
+ } reg_eth_rw_ga_lo;
+ #define REG_RD_ADDR_eth_rw_ga_lo 16
+ #define REG_WR_ADDR_eth_rw_ga_lo 16
+ 
+ /* Register rw_ga_hi, scope eth, type rw */
+ typedef struct {
+-  unsigned int tbl : 32;
++	unsigned int table : 32;
+ } reg_eth_rw_ga_hi;
+ #define REG_RD_ADDR_eth_rw_ga_hi 20
+ #define REG_WR_ADDR_eth_rw_ga_hi 20
+ 
+ /* Register rw_gen_ctrl, scope eth, type rw */
+ typedef struct {
+-  unsigned int en         : 1;
+-  unsigned int phy        : 2;
+-  unsigned int protocol   : 1;
+-  unsigned int loopback   : 1;
+-  unsigned int flow_ctrl  : 1;
+-  unsigned int gtxclk_out : 1;
+-  unsigned int phyrst_n   : 1;
+-  unsigned int dummy1     : 24;
++	unsigned int en         : 1;
++	unsigned int phy        : 2;
++	unsigned int protocol   : 1;
++	unsigned int loopback   : 1;
++	unsigned int flow_ctrl  : 1;
++	unsigned int gtxclk_out : 1;
++	unsigned int phyrst_n   : 1;
++	unsigned int dummy1     : 24;
+ } reg_eth_rw_gen_ctrl;
+ #define REG_RD_ADDR_eth_rw_gen_ctrl 24
+ #define REG_WR_ADDR_eth_rw_gen_ctrl 24
+ 
+ /* Register rw_rec_ctrl, scope eth, type rw */
+ typedef struct {
+-  unsigned int ma0        : 1;
+-  unsigned int ma1        : 1;
+-  unsigned int individual : 1;
+-  unsigned int broadcast  : 1;
+-  unsigned int undersize  : 1;
+-  unsigned int oversize   : 1;
+-  unsigned int bad_crc    : 1;
+-  unsigned int duplex     : 1;
+-  unsigned int max_size   : 16;
+-  unsigned int dummy1     : 8;
++	unsigned int ma0        : 1;
++	unsigned int ma1        : 1;
++	unsigned int individual : 1;
++	unsigned int broadcast  : 1;
++	unsigned int undersize  : 1;
++	unsigned int oversize   : 1;
++	unsigned int bad_crc    : 1;
++	unsigned int duplex     : 1;
++#ifdef CONFIG_CRIS_MACH_ARTPEC3
++	unsigned int max_size   : 16;
++	unsigned int dummy1     : 8;
++#else
++	unsigned int max_size   : 1;
++	unsigned int dummy1     : 23;
++#endif
+ } reg_eth_rw_rec_ctrl;
+ #define REG_RD_ADDR_eth_rw_rec_ctrl 28
+ #define REG_WR_ADDR_eth_rw_rec_ctrl 28
+ 
+ /* Register rw_tr_ctrl, scope eth, type rw */
+ typedef struct {
+-  unsigned int crc         : 1;
+-  unsigned int pad         : 1;
+-  unsigned int retry       : 1;
+-  unsigned int ignore_col  : 1;
+-  unsigned int cancel      : 1;
+-  unsigned int hsh_delay   : 1;
+-  unsigned int ignore_crs  : 1;
+-  unsigned int carrier_ext : 1;
+-  unsigned int dummy1      : 24;
++	unsigned int crc         : 1;
++	unsigned int pad         : 1;
++	unsigned int retry       : 1;
++	unsigned int ignore_col  : 1;
++	unsigned int cancel      : 1;
++	unsigned int hsh_delay   : 1;
++	unsigned int ignore_crs  : 1;
++	unsigned int carrier_ext : 1;
++	unsigned int dummy1      : 24;
+ } reg_eth_rw_tr_ctrl;
+ #define REG_RD_ADDR_eth_rw_tr_ctrl 32
+ #define REG_WR_ADDR_eth_rw_tr_ctrl 32
+ 
+ /* Register rw_clr_err, scope eth, type rw */
+ typedef struct {
+-  unsigned int clr : 1;
+-  unsigned int dummy1 : 31;
++	unsigned int clr : 1;
++	unsigned int dummy1 : 31;
+ } reg_eth_rw_clr_err;
+ #define REG_RD_ADDR_eth_rw_clr_err 36
+ #define REG_WR_ADDR_eth_rw_clr_err 36
+ 
+ /* Register rw_mgm_ctrl, scope eth, type rw */
+ typedef struct {
+-  unsigned int mdio : 1;
+-  unsigned int mdoe : 1;
+-  unsigned int mdc  : 1;
+-  unsigned int dummy1 : 29;
++	unsigned int mdio : 1;
++	unsigned int mdoe : 1;
++	unsigned int mdc  : 1;
++	unsigned int phyclk : 1;
++	unsigned int txdata : 4;
++	unsigned int txen   : 1;
++	unsigned int dummy1 : 23;
+ } reg_eth_rw_mgm_ctrl;
+ #define REG_RD_ADDR_eth_rw_mgm_ctrl 40
+ #define REG_WR_ADDR_eth_rw_mgm_ctrl 40
+ 
+ /* Register r_stat, scope eth, type r */
+ typedef struct {
+-  unsigned int mdio    : 1;
+-  unsigned int exc_col : 1;
+-  unsigned int urun    : 1;
+-  unsigned int clk_125 : 1;
+-  unsigned int dummy1  : 28;
++	unsigned int mdio    : 1;
++	unsigned int exc_col : 1;
++	unsigned int urun    : 1;
++#ifdef CONFIG_CRIS_MACH_ARTPEC3
++	unsigned int clk_125 : 1;
++#else
++	unsigned int phyclk  : 1;
++#endif
++	unsigned int txdata  : 4;
++	unsigned int txen    : 1;
++	unsigned int col     : 1;
++	unsigned int crs     : 1;
++	unsigned int txclk   : 1;
++	unsigned int rxdata  : 4;
++	unsigned int rxer    : 1;
++	unsigned int rxdv    : 1;
++	unsigned int rxclk   : 1;
++	unsigned int dummy1  : 13;
+ } reg_eth_r_stat;
+ #define REG_RD_ADDR_eth_r_stat 44
+ 
+ /* Register rs_rec_cnt, scope eth, type rs */
+ typedef struct {
+-  unsigned int crc_err    : 8;
+-  unsigned int align_err  : 8;
+-  unsigned int oversize   : 8;
+-  unsigned int congestion : 8;
++	unsigned int crc_err    : 8;
++	unsigned int align_err  : 8;
++	unsigned int oversize   : 8;
++	unsigned int congestion : 8;
+ } reg_eth_rs_rec_cnt;
+ #define REG_RD_ADDR_eth_rs_rec_cnt 48
+ 
+ /* Register r_rec_cnt, scope eth, type r */
+ typedef struct {
+-  unsigned int crc_err    : 8;
+-  unsigned int align_err  : 8;
+-  unsigned int oversize   : 8;
+-  unsigned int congestion : 8;
++	unsigned int crc_err    : 8;
++	unsigned int align_err  : 8;
++	unsigned int oversize   : 8;
++	unsigned int congestion : 8;
+ } reg_eth_r_rec_cnt;
+ #define REG_RD_ADDR_eth_r_rec_cnt 52
+ 
+ /* Register rs_tr_cnt, scope eth, type rs */
+ typedef struct {
+-  unsigned int single_col : 8;
+-  unsigned int mult_col   : 8;
+-  unsigned int late_col   : 8;
+-  unsigned int deferred   : 8;
++	unsigned int single_col : 8;
++	unsigned int mult_col   : 8;
++	unsigned int late_col   : 8;
++	unsigned int deferred   : 8;
+ } reg_eth_rs_tr_cnt;
+ #define REG_RD_ADDR_eth_rs_tr_cnt 56
+ 
+ /* Register r_tr_cnt, scope eth, type r */
+ typedef struct {
+-  unsigned int single_col : 8;
+-  unsigned int mult_col   : 8;
+-  unsigned int late_col   : 8;
+-  unsigned int deferred   : 8;
++	unsigned int single_col : 8;
++	unsigned int mult_col   : 8;
++	unsigned int late_col   : 8;
++	unsigned int deferred   : 8;
+ } reg_eth_r_tr_cnt;
+ #define REG_RD_ADDR_eth_r_tr_cnt 60
+ 
+ /* Register rs_phy_cnt, scope eth, type rs */
+ typedef struct {
+-  unsigned int carrier_loss : 8;
+-  unsigned int sqe_err      : 8;
+-  unsigned int dummy1       : 16;
++	unsigned int carrier_loss : 8;
++	unsigned int sqe_err      : 8;
++	unsigned int dummy1       : 16;
+ } reg_eth_rs_phy_cnt;
+ #define REG_RD_ADDR_eth_rs_phy_cnt 64
+ 
+ /* Register r_phy_cnt, scope eth, type r */
+ typedef struct {
+-  unsigned int carrier_loss : 8;
+-  unsigned int sqe_err      : 8;
+-  unsigned int dummy1       : 16;
++	unsigned int carrier_loss : 8;
++	unsigned int sqe_err      : 8;
++	unsigned int dummy1       : 16;
+ } reg_eth_r_phy_cnt;
+ #define REG_RD_ADDR_eth_r_phy_cnt 68
+ 
+ /* Register rw_test_ctrl, scope eth, type rw */
+ typedef struct {
+-  unsigned int snmp_inc : 1;
+-  unsigned int snmp     : 1;
+-  unsigned int backoff  : 1;
+-  unsigned int dummy1   : 29;
++	unsigned int snmp_inc : 1;
++	unsigned int snmp     : 1;
++	unsigned int backoff  : 1;
++	unsigned int dummy1   : 29;
+ } reg_eth_rw_test_ctrl;
+ #define REG_RD_ADDR_eth_rw_test_ctrl 72
+ #define REG_WR_ADDR_eth_rw_test_ctrl 72
+ 
+ /* Register rw_intr_mask, scope eth, type rw */
+ typedef struct {
+-  unsigned int crc          : 1;
+-  unsigned int align        : 1;
+-  unsigned int oversize     : 1;
+-  unsigned int congestion   : 1;
+-  unsigned int single_col   : 1;
+-  unsigned int mult_col     : 1;
+-  unsigned int late_col     : 1;
+-  unsigned int deferred     : 1;
+-  unsigned int carrier_loss : 1;
+-  unsigned int sqe_test_err : 1;
+-  unsigned int orun         : 1;
+-  unsigned int urun         : 1;
+-  unsigned int exc_col      : 1;
+-  unsigned int mdio         : 1;
+-  unsigned int dummy1       : 18;
++	unsigned int crc          : 1;
++	unsigned int align        : 1;
++	unsigned int oversize     : 1;
++	unsigned int congestion   : 1;
++	unsigned int single_col   : 1;
++	unsigned int mult_col     : 1;
++	unsigned int late_col     : 1;
++	unsigned int deferred     : 1;
++	unsigned int carrier_loss : 1;
++	unsigned int sqe_test_err : 1;
++	unsigned int orun         : 1;
++	unsigned int urun         : 1;
++	unsigned int exc_col      : 1;
++	unsigned int mdio         : 1;
++	unsigned int dummy1       : 18;
+ } reg_eth_rw_intr_mask;
+ #define REG_RD_ADDR_eth_rw_intr_mask 76
+ #define REG_WR_ADDR_eth_rw_intr_mask 76
+ 
+ /* Register rw_ack_intr, scope eth, type rw */
+ typedef struct {
+-  unsigned int crc          : 1;
+-  unsigned int align        : 1;
+-  unsigned int oversize     : 1;
+-  unsigned int congestion   : 1;
+-  unsigned int single_col   : 1;
+-  unsigned int mult_col     : 1;
+-  unsigned int late_col     : 1;
+-  unsigned int deferred     : 1;
+-  unsigned int carrier_loss : 1;
+-  unsigned int sqe_test_err : 1;
+-  unsigned int orun         : 1;
+-  unsigned int urun         : 1;
+-  unsigned int exc_col      : 1;
+-  unsigned int mdio         : 1;
+-  unsigned int dummy1       : 18;
++	unsigned int crc          : 1;
++	unsigned int align        : 1;
++	unsigned int oversize     : 1;
++	unsigned int congestion   : 1;
++	unsigned int single_col   : 1;
++	unsigned int mult_col     : 1;
++	unsigned int late_col     : 1;
++	unsigned int deferred     : 1;
++	unsigned int carrier_loss : 1;
++	unsigned int sqe_test_err : 1;
++	unsigned int orun         : 1;
++	unsigned int urun         : 1;
++	unsigned int exc_col      : 1;
++	unsigned int mdio         : 1;
++	unsigned int dummy1       : 18;
+ } reg_eth_rw_ack_intr;
+ #define REG_RD_ADDR_eth_rw_ack_intr 80
+ #define REG_WR_ADDR_eth_rw_ack_intr 80
+ 
+ /* Register r_intr, scope eth, type r */
+ typedef struct {
+-  unsigned int crc          : 1;
+-  unsigned int align        : 1;
+-  unsigned int oversize     : 1;
+-  unsigned int congestion   : 1;
+-  unsigned int single_col   : 1;
+-  unsigned int mult_col     : 1;
+-  unsigned int late_col     : 1;
+-  unsigned int deferred     : 1;
+-  unsigned int carrier_loss : 1;
+-  unsigned int sqe_test_err : 1;
+-  unsigned int orun         : 1;
+-  unsigned int urun         : 1;
+-  unsigned int exc_col      : 1;
+-  unsigned int mdio         : 1;
+-  unsigned int dummy1       : 18;
++	unsigned int crc          : 1;
++	unsigned int align        : 1;
++	unsigned int oversize     : 1;
++	unsigned int congestion   : 1;
++	unsigned int single_col   : 1;
++	unsigned int mult_col     : 1;
++	unsigned int late_col     : 1;
++	unsigned int deferred     : 1;
++	unsigned int carrier_loss : 1;
++	unsigned int sqe_test_err : 1;
++	unsigned int orun         : 1;
++	unsigned int urun         : 1;
++	unsigned int exc_col      : 1;
++	unsigned int mdio         : 1;
++	unsigned int dummy1       : 18;
+ } reg_eth_r_intr;
+ #define REG_RD_ADDR_eth_r_intr 84
+ 
+ /* Register r_masked_intr, scope eth, type r */
+ typedef struct {
+-  unsigned int crc          : 1;
+-  unsigned int align        : 1;
+-  unsigned int oversize     : 1;
+-  unsigned int congestion   : 1;
+-  unsigned int single_col   : 1;
+-  unsigned int mult_col     : 1;
+-  unsigned int late_col     : 1;
+-  unsigned int deferred     : 1;
+-  unsigned int carrier_loss : 1;
+-  unsigned int sqe_test_err : 1;
+-  unsigned int orun         : 1;
+-  unsigned int urun         : 1;
+-  unsigned int exc_col      : 1;
+-  unsigned int mdio         : 1;
+-  unsigned int dummy1       : 18;
++	unsigned int crc          : 1;
++	unsigned int align        : 1;
++	unsigned int oversize     : 1;
++	unsigned int congestion   : 1;
++	unsigned int single_col   : 1;
++	unsigned int mult_col     : 1;
++	unsigned int late_col     : 1;
++	unsigned int deferred     : 1;
++	unsigned int carrier_loss : 1;
++	unsigned int sqe_test_err : 1;
++	unsigned int orun         : 1;
++	unsigned int urun         : 1;
++	unsigned int exc_col      : 1;
++	unsigned int mdio         : 1;
++	unsigned int dummy1       : 18;
+ } reg_eth_r_masked_intr;
+ #define REG_RD_ADDR_eth_r_masked_intr 88
+ 
+-
+ /* Constants */
+ enum {
+-  regk_eth_discard                         = 0x00000000,
+-  regk_eth_ether                           = 0x00000000,
+-  regk_eth_full                            = 0x00000001,
+-  regk_eth_gmii                            = 0x00000003,
+-  regk_eth_gtxclk                          = 0x00000001,
+-  regk_eth_half                            = 0x00000000,
+-  regk_eth_hsh                             = 0x00000001,
+-  regk_eth_mii                             = 0x00000001,
+-  regk_eth_mii_arec                        = 0x00000002,
+-  regk_eth_mii_clk                         = 0x00000000,
+-  regk_eth_no                              = 0x00000000,
+-  regk_eth_phyrst                          = 0x00000000,
+-  regk_eth_rec                             = 0x00000001,
+-  regk_eth_rw_ga_hi_default                = 0x00000000,
+-  regk_eth_rw_ga_lo_default                = 0x00000000,
+-  regk_eth_rw_gen_ctrl_default             = 0x00000000,
+-  regk_eth_rw_intr_mask_default            = 0x00000000,
+-  regk_eth_rw_ma0_hi_default               = 0x00000000,
+-  regk_eth_rw_ma0_lo_default               = 0x00000000,
+-  regk_eth_rw_ma1_hi_default               = 0x00000000,
+-  regk_eth_rw_ma1_lo_default               = 0x00000000,
+-  regk_eth_rw_mgm_ctrl_default             = 0x00000000,
+-  regk_eth_rw_test_ctrl_default            = 0x00000000,
+-  regk_eth_size1518                        = 0x000005ee,
+-  regk_eth_size1522                        = 0x000005f2,
+-  regk_eth_yes                             = 0x00000001
++	regk_eth_discard                         = 0x00000000,
++	regk_eth_ether                           = 0x00000000,
++	regk_eth_full                            = 0x00000001,
++	regk_eth_gmii                            = 0x00000003,
++	regk_eth_gtxclk                          = 0x00000001,
++	regk_eth_half                            = 0x00000000,
++	regk_eth_hsh                             = 0x00000001,
++	regk_eth_mii                             = 0x00000001,
++	regk_eth_mii_arec                        = 0x00000002,
++	regk_eth_mii_clk                         = 0x00000000,
++	regk_eth_no                              = 0x00000000,
++	regk_eth_phyrst                          = 0x00000000,
++	regk_eth_rec                             = 0x00000001,
++	regk_eth_rw_ga_hi_default                = 0x00000000,
++	regk_eth_rw_ga_lo_default                = 0x00000000,
++	regk_eth_rw_gen_ctrl_default             = 0x00000000,
++	regk_eth_rw_intr_mask_default            = 0x00000000,
++	regk_eth_rw_ma0_hi_default               = 0x00000000,
++	regk_eth_rw_ma0_lo_default               = 0x00000000,
++	regk_eth_rw_ma1_hi_default               = 0x00000000,
++	regk_eth_rw_ma1_lo_default               = 0x00000000,
++	regk_eth_rw_mgm_ctrl_default             = 0x00000000,
++	regk_eth_rw_test_ctrl_default            = 0x00000000,
++#ifdef CONFIG_CRIS_MACH_ARTPEC3
++	regk_eth_size1518                        = 0x000005ee,
++	regk_eth_size1522                        = 0x000005f2,
++#else
++	regk_eth_size1518                        = 0x00000000,
++	regk_eth_size1522                        = 0x00000001,
++#endif
++	regk_eth_yes                             = 0x00000001
+ };
++
+ #endif /* __eth_defs_h */
+diff -Nur linux-4.4.6.orig/drivers/net/cris/eth_v32.c linux-4.4.6/drivers/net/cris/eth_v32.c
+--- linux-4.4.6.orig/drivers/net/cris/eth_v32.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-4.4.6/drivers/net/cris/eth_v32.c	2016-03-20 15:09:58.183871830 +0100
+@@ -0,0 +1,3062 @@
++/*
++ * Driver for the ETRAX FS/Artpec-3 network controller.
++ *
++ * Copyright (c) 2003-2008 Axis Communications AB.
++ *
++ * TODO:
++ *   *    Decrease the amount of code running with interrupts disabled.
++ *   *    Rework the error handling so that we do not need to touch the tx
++ *        ring from the error interrupts. When done, we should be able to
++ *        do tx completition from the NAPI loop without disabling interrupts.
++ *   *    Remove the gigabit code. It's probably never going to be used.
++ */
++
++#include <linux/module.h>
++
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/delay.h>
++#include <linux/types.h>
++#include <linux/fcntl.h>
++#include <linux/interrupt.h>
++#include <linux/spinlock.h>
++#include <linux/errno.h>
++#include <linux/init.h>
++
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++#include <linux/ethtool.h>
++#include <linux/mii.h>
++
++#include <asm/io.h>		/* CRIS_LED_* I/O functions */
++#include <asm/irq.h>
++#include <hwregs/reg_map.h>
++#include <hwregs/reg_rdwr.h>
++#include <hwregs/dma.h>
++#include <hwregs/eth_defs.h>
++#ifdef CONFIG_ETRAXFS
++#include <hwregs/config_defs.h>
++#else
++#include <hwregs/clkgen_defs.h>
++#endif
++#include <hwregs/intr_vect_defs.h>
++#include <hwregs/strmux_defs.h>
++#include <asm/bitops.h>
++#include <asm/ethernet.h>
++#include <mach/dma.h>
++#include <pinmux.h>
++
++#include "eth_v32.h"
++
++#ifndef CONFIG_ETRAXFS
++#define ETH0_INTR_VECT ETH_INTR_VECT
++#define ETH1_INTR_VECT ETH_INTR_VECT
++#define regi_eth0 regi_eth
++#define regi_eth1 regi_
++#endif
++
++#define DEBUG(x)
++#define GET_BIT(bit,val)   (((val) >> (bit)) & 0x01)
++
++#if defined(CONFIG_ETRAX_HAVE_PHY) || defined(CONFIG_ETRAX_PHY_FALLBACK)
++#define RESET_PHY 1
++#else
++#define RESET_PHY 0
++#endif
++
++enum {
++	HAVE_PHY,
++	NO_PHY,
++	FALLBACK_PHY,
++};
++#if defined(CONFIG_ETRAX_PHY_FALLBACK)
++#define PHY_MODE (FALLBACK_PHY)
++#elif defined(CONFIG_ETRAX_NO_PHY)
++#define PHY_MODE (NO_PHY)
++#elif defined(CONFIG_ETRAX_HAVE_PHY)
++#define PHY_MODE (HAVE_PHY)
++#else
++#error Unknown PHY behaviour
++#endif
++
++static struct {
++	const char str[ETH_GSTRING_LEN];
++} const ethtool_stats_keys[] = {
++	{ "tx_dma_restarts" },
++	{ "tx_mac_resets" },
++	{ "rx_dma_restarts" },
++	{ "rx_dma_timeouts" },
++	{ "  dropped_rx" }
++};
++
++static void crisv32_eth_check_speed(unsigned long idev);
++static void crisv32_eth_check_duplex(unsigned long idev);
++static void update_rx_stats(struct crisv32_ethernet_local *np);
++static void update_tx_stats(struct crisv32_ethernet_local *np);
++static int crisv32_eth_poll(struct napi_struct *napi, int budget);
++static void crisv32_eth_setup_controller(struct net_device *dev);
++static int crisv32_eth_request_irqdma(struct net_device *dev);
++#ifdef CONFIG_CRIS_MACH_ARTPEC3
++static void
++crisv32_eth_restart_rx_dma(struct net_device* dev,
++			   struct crisv32_ethernet_local *np);
++#endif
++#if 0
++static void crisv32_ethernet_bug(struct net_device *dev);
++#endif
++
++/*
++ * The name of the card. Is used for messages and in the requests for
++ * io regions, irqs and dma channels.
++ */
++#ifdef CONFIG_ETRAXFS
++static const char cardname[] = "ETRAX FS built-in ethernet controller";
++#else
++static const char cardname[] = "ARTPEC-3 built-in ethernet controller";
++#endif
++
++/* Some chipset needs special care. */
++#ifndef CONFIG_ETRAX_NO_PHY
++struct transceiver_ops transceivers[] = {
++	{0x1018, broadcom_check_speed, broadcom_check_duplex},
++	{0x50EF, broadcom_check_speed, broadcom_check_duplex},
++	/* TDK 2120 and TDK 2120C */
++	{0xC039, tdk_check_speed, tdk_check_duplex},
++	{0x039C, tdk_check_speed, tdk_check_duplex},
++	/* Intel LXT972A*/
++	{0x04de, intel_check_speed, intel_check_duplex},
++	/* National Semiconductor DP83865 */
++	{0x0017, national_check_speed, national_check_duplex},
++	/* Vitesse VCS8641 */
++	{0x01c1, vitesse_check_speed, vitesse_check_duplex},
++	/* Davicom DM9161 */
++	{0x606E, davicom_check_speed, davicom_check_duplex},
++	/* Generic, must be last. */
++	{0x0000, generic_check_speed, generic_check_duplex}
++};
++#endif
++
++static struct net_device *crisv32_dev[2];
++static struct crisv32_eth_leds *crisv32_leds[3];
++
++/* Default MAC address for interface 0.
++ * The real one will be set later. */
++static struct sockaddr default_mac_iface0 =
++  {0, {0x00, 0x40, 0x8C, 0xCD, 0x00, 0x00}};
++
++#ifdef CONFIG_CPU_FREQ
++static int
++crisv32_ethernet_freq_notifier(struct notifier_block *nb, unsigned long val,
++			       void *data);
++
++static struct notifier_block crisv32_ethernet_freq_notifier_block = {
++	.notifier_call	= crisv32_ethernet_freq_notifier
++};
++#endif
++
++static void receive_timeout(unsigned long arg);
++static void receive_timeout_work(struct work_struct* work);
++static void transmit_timeout(unsigned long arg);
++
++/*
++ * mask in and out tx/rx interrupts.
++ */
++static inline void crisv32_disable_tx_ints(struct crisv32_ethernet_local *np)
++{
++	reg_dma_rw_intr_mask intr_mask_tx = { .data = regk_dma_no };
++	REG_WR(dma, np->dma_out_inst, rw_intr_mask, intr_mask_tx);
++}
++
++static inline void crisv32_enable_tx_ints(struct crisv32_ethernet_local *np)
++{
++	reg_dma_rw_intr_mask intr_mask_tx = { .data = regk_dma_yes };
++	REG_WR(dma, np->dma_out_inst, rw_intr_mask, intr_mask_tx);
++}
++
++static inline void crisv32_disable_rx_ints(struct crisv32_ethernet_local *np)
++{
++	reg_dma_rw_intr_mask intr_mask_rx = { .in_eop = regk_dma_no };
++	REG_WR(dma, np->dma_in_inst, rw_intr_mask, intr_mask_rx);
++}
++
++static inline void crisv32_enable_rx_ints(struct crisv32_ethernet_local *np)
++{
++	reg_dma_rw_intr_mask intr_mask_rx = { .in_eop = regk_dma_yes };
++	REG_WR(dma, np->dma_in_inst, rw_intr_mask, intr_mask_rx);
++}
++
++static inline void crisv32_disable_eth_ints(struct crisv32_ethernet_local *np)
++{
++	int intr_mask_nw = 0x0;
++	REG_WR_INT(eth, np->eth_inst, rw_intr_mask, intr_mask_nw);
++}
++
++static inline void crisv32_enable_eth_ints(struct crisv32_ethernet_local *np)
++{
++#ifdef CONFIG_CRIS_MACH_ARTPEC3
++	/* For Artpec-3 we use overrun to workaround voodoo TR 87 */
++	int intr_mask_nw = 0x1c00;
++#else
++	int intr_mask_nw = 0x1800;
++#endif
++	REG_WR_INT(eth, np->eth_inst, rw_intr_mask, intr_mask_nw);
++}
++
++static inline int crisv32_eth_gigabit(struct crisv32_ethernet_local *np)
++{
++#ifdef CONFIG_CRIS_MACH_ARTPEC3
++	return np->gigabit_mode;
++#else
++	return 0;
++#endif
++}
++
++static inline void crisv32_eth_set_gigabit(struct crisv32_ethernet_local *np,
++					   int g)
++{
++#ifdef CONFIG_CRIS_MACH_ARTPEC3
++	np->gigabit_mode = g;
++#endif
++}
++
++/* start/stop receiver */
++static inline void crisv32_start_receiver(struct crisv32_ethernet_local *np)
++{
++	reg_eth_rw_rec_ctrl rec_ctrl;
++
++	rec_ctrl = REG_RD(eth, np->eth_inst, rw_rec_ctrl);
++	rec_ctrl.ma0 = regk_eth_yes;
++	rec_ctrl.broadcast = regk_eth_rec;
++	REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
++}
++
++static inline void crisv32_stop_receiver(struct crisv32_ethernet_local *np)
++{
++	reg_eth_rw_rec_ctrl rec_ctrl;
++
++	rec_ctrl = REG_RD(eth, np->eth_inst, rw_rec_ctrl);
++	rec_ctrl.ma0 = regk_eth_no;
++	rec_ctrl.broadcast = regk_eth_discard;
++	REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl);
++}
++
++static inline void crisv32_eth_reset(struct crisv32_ethernet_local *np)
++{
++	reg_eth_rw_gen_ctrl gen_ctrl = { 0 };
++
++	gen_ctrl = REG_RD(eth, np->eth_inst, rw_gen_ctrl);
++	gen_ctrl.en = regk_eth_no;
++	REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl);
++	gen_ctrl.en = regk_eth_yes;
++	REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl);
++}
++
++static void crisv32_eth_tx_cancel_frame(struct crisv32_ethernet_local *np)
++{
++	reg_eth_rw_tr_ctrl tr_ctrl;
++
++	/* Cancel any pending transmits.  This should bring us to the
++	   excessive collisions state but it doesn't always do it.  */
++	tr_ctrl = REG_RD(eth, np->eth_inst, rw_tr_ctrl);
++	tr_ctrl.cancel = 1;
++	REG_WR(eth, np->eth_inst, rw_tr_ctrl, tr_ctrl);
++	tr_ctrl.cancel = 0;
++	REG_WR(eth, np->eth_inst, rw_tr_ctrl, tr_ctrl);
++}
++
++/*
++ * Hack to disconnect/reconnect the dma from the ethernet block while we reset
++ * things. TODO: verify that we don't need to disconnect out channels and
++ * remove that code.
++ *
++ * ARTPEC-3 has only a single ethernet block so np->eth_inst is always eth0.
++ * The strmux values are named slightly different, redefine to avoid #ifdefs
++ * in the code blocks. For artpec3 only regk_strmux_eth0 and channel 0/1
++ * should be used.
++ */
++#ifdef CONFIG_CRIS_MACH_ARTPEC3
++#define regk_strmux_eth0 regk_strmux_eth
++#define regk_strmux_eth1 regk_strmux_eth
++#endif
++static inline void
++crisv32_disconnect_eth_tx_dma(struct crisv32_ethernet_local *np)
++{
++	reg_strmux_rw_cfg strmux_cfg;
++
++	strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
++	if (np->eth_inst == regi_eth0)
++		strmux_cfg.dma0 = regk_strmux_off;
++	else
++		strmux_cfg.dma6 = regk_strmux_off;
++	REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
++}
++
++static inline void crisv32_connect_eth_tx_dma(struct crisv32_ethernet_local *np)
++{
++	reg_strmux_rw_cfg strmux_cfg;
++
++	strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
++	if (np->eth_inst == regi_eth0)
++		strmux_cfg.dma0 = regk_strmux_eth0;
++	else
++		strmux_cfg.dma6 = regk_strmux_eth1;
++	REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
++}
++
++static inline void
++crisv32_disconnect_eth_rx_dma(struct crisv32_ethernet_local *np)
++{
++	reg_strmux_rw_cfg strmux_cfg;
++
++	strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
++	if (np->eth_inst == regi_eth0)
++		strmux_cfg.dma1 = regk_strmux_off;
++	else
++		strmux_cfg.dma7 = regk_strmux_off;
++	REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
++}
++
++static inline void crisv32_connect_eth_rx_dma(struct crisv32_ethernet_local *np)
++{
++	reg_strmux_rw_cfg strmux_cfg;
++
++	strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
++	if (np->eth_inst == regi_eth0)
++		strmux_cfg.dma1 = regk_strmux_eth0;
++	else
++		strmux_cfg.dma7 = regk_strmux_eth1;
++	REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
++}
++
++static int dma_wait_busy(int inst, int timeout)
++{
++	reg_dma_rw_stream_cmd dma_sc;
++
++	do {
++		dma_sc = REG_RD(dma, inst, rw_stream_cmd);
++	} while (timeout-- > 0 && dma_sc.busy);
++	return dma_sc.busy;
++}
++
++static int __init crisv32_eth_request_irqdma(struct net_device *dev)
++{
++	struct crisv32_ethernet_local *np = netdev_priv(dev);
++
++	/* Allocate IRQs and DMAs. */
++	if (np->eth_inst == regi_eth0) {
++		if (request_irq(DMA0_INTR_VECT, crisv32tx_eth_interrupt,
++				0, "Ethernet TX", dev)) {
++			return -EAGAIN;
++		}
++
++		if (request_irq(DMA1_INTR_VECT, crisv32rx_eth_interrupt,
++				0, "Ethernet RX", dev))
++			goto err0_1;
++
++		if (crisv32_request_dma(0, cardname, DMA_VERBOSE_ON_ERROR,
++					12500000, dma_eth0))
++			goto err0_2;
++
++		if (crisv32_request_dma(1, cardname, DMA_VERBOSE_ON_ERROR,
++					12500000, dma_eth0))
++			goto err0_3;
++
++		if (request_irq(ETH0_INTR_VECT, crisv32nw_eth_interrupt, 0,
++					cardname, dev)) {
++			crisv32_free_dma(1);
++err0_3:
++			crisv32_free_dma(0);
++err0_2:
++			free_irq(DMA1_INTR_VECT, dev);
++err0_1:
++			free_irq(DMA0_INTR_VECT, dev);
++			return -EAGAIN;
++		}
++	} else {
++		if (request_irq(DMA6_INTR_VECT, crisv32tx_eth_interrupt,
++				0, cardname, dev))
++			return -EAGAIN;
++
++		if (request_irq(DMA7_INTR_VECT, crisv32rx_eth_interrupt,
++				0, cardname, dev))