update to 4.1.3, which will be the base for stable branch

1 files changed, 171697 insertions, 0 deletions

diff --git a/target/arm/solidrun-imx6/patches/4.1.3/0001-xbian.patch b/target/arm/solidrun-imx6/patches/4.1.3/0001-xbian.patch
new file mode 100644
index 000000000..6286c0868
--- /dev/null
+++ b/target/arm/solidrun-imx6/patches/4.1.3/0001-xbian.patch
@@ -0,0 +1,171697 @@
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6dl.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6dl.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/imx6dl.dtsi	2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/boot/dts/imx6dl.dtsi	2015-07-27 23:13:00.299912248 +0200
+@@ -60,17 +60,103 @@
+ 	};
+ 
+ 	soc {
+-		ocram: sram@00900000 {
++		busfreq { /* BUSFREQ */
++			compatible = "fsl,imx6_busfreq";
++			clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
++				 <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 22> , <&clks 8>;
++			clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
++				      "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_sel", "pll3_pfd1_540m";
++			interrupts = <0 107 0x04>, <0 112 0x4>;
++			interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
++			fsl,max_ddr_freq = <400000000>;
++		};
++
++		gpu@00130000 {
++			compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
++			reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
++			      <0x0 0x0>;
++			reg-names = "iobase_3d", "iobase_2d",
++			            "phys_baseaddr";
++			interrupts = <0 9 0x04>, <0 10 0x04>;
++			interrupt-names = "irq_3d", "irq_2d";
++			clocks = <&clks 26>, <&clks 27>,
++			         <&clks 121>, <&clks 122>,
++			         <&clks 74>;
++			clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
++		                      "gpu2d_clk", "gpu3d_clk",
++		                      "gpu3d_shader_clk";
++			resets = <&src 0>, <&src 3>;
++			reset-names = "gpu3d", "gpu2d";
++			power-domains = <&gpc 1>;
++		};
++
++		hdmi_core: hdmi_core@00120000 {
++			compatible = "fsl,imx6q-hdmi-core";
++			reg = <0x00120000 0x9000>;
++			clocks = <&clks 124>, <&clks 123>;
++			clock-names = "hdmi_isfr", "hdmi_iahb";
++			status = "disabled";
++		};
++
++		hdmi_video: hdmi_video@020e0000 {
++			compatible = "fsl,imx6q-hdmi-video";
++			reg = <0x020e0000 0x1000>;
++			reg-names = "hdmi_gpr";
++			interrupts = <0 115 0x04>;
++			clocks = <&clks 124>, <&clks 123>;
++			clock-names = "hdmi_isfr", "hdmi_iahb";
++			status = "disabled";
++		};
++
++		hdmi_audio: hdmi_audio@00120000 {
++			compatible = "fsl,imx6q-hdmi-audio";
++			clocks = <&clks 124>, <&clks 123>;
++			clock-names = "hdmi_isfr", "hdmi_iahb";
++			dmas = <&sdma 2 23 0>;
++			dma-names = "tx";
++			status = "disabled";
++		};
++
++		hdmi_cec: hdmi_cec@00120000 {
++			compatible = "fsl,imx6q-hdmi-cec";
++			interrupts = <0 115 0x04>;
++			status = "disabled";
++		};
++
++		ocrams: sram@00900000 {
++			compatible = "fsl,lpm-sram";
++			reg = <0x00900000 0x4000>;
++			clocks = <&clks IMX6QDL_CLK_OCRAM>;
++		};
++
++		ocrams_ddr: sram@00904000 {
++			compatible = "fsl,ddr-lpm-sram";
++			reg = <0x00904000 0x1000>;
++			clocks = <&clks IMX6QDL_CLK_OCRAM>;
++		};
++
++		ocram: sram@00905000 {
+ 			compatible = "mmio-sram";
+-			reg = <0x00900000 0x20000>;
++			reg = <0x00905000 0x1B000>;
+ 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
+ 		};
+ 
+ 		aips1: aips-bus@02000000 {
++			vpu@02040000 {
++				iramsize = <0>;
++				status = "okay";
++			};
++
+ 			iomuxc: iomuxc@020e0000 {
+ 				compatible = "fsl,imx6dl-iomuxc";
+ 			};
+ 
++			dcic2: dcic@020e8000 {
++				clocks = <&clks IMX6QDL_CLK_DCIC1 >,
++					 <&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/
++				clock-names = "dcic", "disp-axi";
++			};
++
+ 			pxp: pxp@020f0000 {
+ 				reg = <0x020f0000 0x4000>;
+ 				interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+@@ -99,26 +185,13 @@
+ 			};
+ 		};
+ 	};
+-
+-	display-subsystem {
+-		compatible = "fsl,imx-display-subsystem";
+-		ports = <&ipu1_di0>, <&ipu1_di1>;
+-	};
+-};
+-
+-&hdmi {
+-	compatible = "fsl,imx6dl-hdmi";
+ };
+ 
+ &ldb {
+-	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+-		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+-		 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
++	clocks = <&clks 33>, <&clks 34>,
++		 <&clks 39>, <&clks 40>,
++		 <&clks 135>, <&clks 136>;
+ 	clock-names = "di0_pll", "di1_pll",
+ 		      "di0_sel", "di1_sel",
+ 		      "di0", "di1";
+ };
+-
+-&vpu {
+-	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
+-};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi	2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi	2015-07-27 23:13:00.303898027 +0200
+@@ -45,11 +45,22 @@
+ #include <dt-bindings/gpio/gpio.h>
+ 
+ / {
++	chosen {
++		bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw";
++	};
++
++	aliases {
++		mmc0 = &usdhc2;
++		mmc1 = &usdhc1;
++		mxcfb0 = &mxcfb1;
++	};
++
+ 	ir_recv: ir-receiver {
+ 		compatible = "gpio-ir-receiver";
+ 		gpios = <&gpio3 9 1>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pinctrl_cubox_i_ir>;
++		linux,rc-map-name = "rc-rc6-mce";
+ 	};
+ 
+ 	pwmleds {
+@@ -78,6 +89,8 @@
+ 
+ 		reg_usbh1_vbus: usb-h1-vbus {
+ 			compatible = "regulator-fixed";
++			regulator-boot-on;
++			regulator-always-on;
+ 			enable-active-high;
+ 			gpio = <&gpio1 0 0>;
+ 			pinctrl-names = "default";
+@@ -89,6 +102,8 @@
+ 
+ 		reg_usbotg_vbus: usb-otg-vbus {
+ 			compatible = "regulator-fixed";
++			regulator-boot-on;
++			regulator-always-on;
+ 			enable-active-high;
+ 			gpio = <&gpio3 22 0>;
+ 			pinctrl-names = "default";
+@@ -101,8 +116,7 @@
+ 
+ 	sound-spdif {
+ 		compatible = "fsl,imx-audio-spdif";
+-		model = "Integrated SPDIF";
+-		/* IMX6 doesn't implement this yet */
++		model = "imx-spdif";
+ 		spdif-controller = <&spdif>;
+ 		spdif-out;
+ 	};
+@@ -118,12 +132,45 @@
+ 			linux,code = <BTN_0>;
+ 		};
+ 	};
++
++	sound-hdmi {
++		compatible = "fsl,imx6q-audio-hdmi",
++			     "fsl,imx-audio-hdmi";
++		model = "imx-audio-hdmi";
++		hdmi-controller = <&hdmi_audio>;
++	};
++
++	mxcfb1: fb@0 {
++		compatible = "fsl,mxc_sdc_fb";
++		disp_dev = "hdmi";
++		interface_pix_fmt = "RGB24";
++		mode_str ="1920x1080M@60";
++		default_bpp = <32>;
++		int_clk = <0>;
++		late_init = <0>;
++		status = "okay";
++	};
++};
++
++&hdmi_core {
++	ipu_id = <0>;
++	disp_id = <0>;
++	status = "okay";
++};
++
++&hdmi_video {
++	fsl,phy_reg_vlev = <0x0294>;
++	fsl,phy_reg_cksymtx = <0x800d>;
++	status = "okay";
++};
++
++&hdmi_audio {
++	status = "okay";
+ };
+ 
+-&hdmi {
++&hdmi_cec {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_cubox_i_hdmi>;
+-	ddc-i2c-bus = <&i2c2>;
+ 	status = "okay";
+ };
+ 
+@@ -131,7 +178,13 @@
+ 	clock-frequency = <100000>;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_cubox_i_i2c2>;
++
+ 	status = "okay";
++
++	ddc: imx6_hdmi_i2c@50 {
++		compatible = "fsl,imx6-hdmi-i2c";
++		reg = <0x50>;
++	};
+ };
+ 
+ &i2c3 {
+@@ -228,6 +281,28 @@
+ 				MX6QDL_PAD_EIM_DA8__GPIO3_IO08	0x17059
+ 			>;
+ 		};
++
++		pinctrl_cubox_i_usdhc2_100mhz: cubox-i-usdhc2-100mhz {
++			fsl,pins = <
++				MX6QDL_PAD_SD2_CMD__SD2_CMD    0x170b9
++				MX6QDL_PAD_SD2_CLK__SD2_CLK    0x100b9
++				MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
++				MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
++				MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
++				MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9
++			>;
++		};
++
++		pinctrl_cubox_i_usdhc2_200mhz: cubox-i-usdhc2-200mhz {
++			fsl,pins = <
++				MX6QDL_PAD_SD2_CMD__SD2_CMD    0x170f9
++				MX6QDL_PAD_SD2_CLK__SD2_CLK    0x100f9
++				MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
++				MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
++				MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
++				MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9
++			>;
++		};
+ 	};
+ };
+ 
+@@ -256,9 +331,24 @@
+ };
+ 
+ &usdhc2 {
+-	pinctrl-names = "default";
++	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ 	pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>;
++	pinctrl-1 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_100mhz>;
++	pinctrl-2 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_200mhz>;
+ 	vmmc-supply = <&reg_3p3v>;
+ 	cd-gpios = <&gpio1 4 0>;
+ 	status = "okay";
++	no-1-8-v;
++};
++
++&dcic1 {
++	dcic_id = <0>;
++	dcic_mux = "dcic-hdmi";
++	status = "okay";
++};
++
++&dcic2 {
++	dcic_id = <1>;
++	dcic_mux = "dcic-lvds1";
++	status = "okay";
+ };
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6qdl.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6qdl.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/imx6qdl.dtsi	2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/boot/dts/imx6qdl.dtsi	2015-07-27 23:13:00.303898027 +0200
+@@ -14,6 +14,7 @@
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ 
+ #include "skeleton.dtsi"
++#include <dt-bindings/gpio/gpio.h>
+ 
+ / {
+ 	aliases {
+@@ -30,6 +31,7 @@
+ 		i2c0 = &i2c1;
+ 		i2c1 = &i2c2;
+ 		i2c2 = &i2c3;
++		ipu0 = &ipu1;
+ 		mmc0 = &usdhc1;
+ 		mmc1 = &usdhc2;
+ 		mmc2 = &usdhc3;
+@@ -79,6 +81,10 @@
+ 		};
+ 	};
+ 
++	pu_dummy: pudummy_reg {
++		compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */
++	};
++
+ 	soc {
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+@@ -86,6 +92,11 @@
+ 		interrupt-parent = <&gpc>;
+ 		ranges;
+ 
++		caam_sm: caam-sm@00100000 {
++			compatible = "fsl,imx6q-caam-sm";
++			reg = <0x00100000 0x3fff>;
++		};
++
+ 		dma_apbh: dma-apbh@00110000 {
+ 			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+ 			reg = <0x00110000 0x2000>;
+@@ -99,6 +110,12 @@
+ 			clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
+ 		};
+ 
++		irq_sec_vio: caam_secvio {
++			compatible = "fsl,imx6q-caam-secvio";
++			interrupts = <0 20 0x04>;
++			secvio_src = <0x8000001d>;
++		};
++
+ 		gpmi: gpmi-nand@00112000 {
+ 			compatible = "fsl,imx6q-gpmi-nand";
+ 			#address-cells = <1>;
+@@ -190,16 +207,16 @@
+ 					dmas = <&sdma 14 18 0>,
+ 					       <&sdma 15 18 0>;
+ 					dma-names = "rx", "tx";
+-					clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
+-						 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
+-						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
+-						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
+-						 <&clks IMX6QDL_CLK_DUMMY>;
++					clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
++						 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
++						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
++						 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
++						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
+ 					clock-names = "core",  "rxtx0",
+ 						      "rxtx1", "rxtx2",
+ 						      "rxtx3", "rxtx4",
+ 						      "rxtx5", "rxtx6",
+-						      "rxtx7";
++						      "rxtx7", "dma";
+ 					status = "disabled";
+ 				};
+ 
+@@ -274,7 +291,12 @@
+ 				esai: esai@02024000 {
+ 					reg = <0x02024000 0x4000>;
+ 					interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
+-				};
++					compatible = "fsl,imx6q-esai";
++					clocks = <&clks 118>;
++					fsl,esai-dma-events = <24 23>;
++					fsl,flags = <1>;
++					status = "disabled";
++                                };
+ 
+ 				ssi1: ssi@02028000 {
+ 					#sound-dai-cells = <0>;
+@@ -325,8 +347,30 @@
+ 				};
+ 
+ 				asrc: asrc@02034000 {
++					compatible = "fsl,imx53-asrc";
+ 					reg = <0x02034000 0x4000>;
+ 					interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
++					clocks = <&clks IMX6QDL_CLK_ASRC_MEM>,
++						 <&clks IMX6QDL_CLK_ASRC_IPG>,
++						 <&clks IMX6QDL_CLK_SPDIF>,
++						 <&clks IMX6QDL_CLK_SPBA>;
++					clock-names = "mem", "ipg", "asrck_0", "dma";
++					dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, <&sdma 19 20 1>,
++					       <&sdma 20 20 1>, <&sdma 21 20 1>, <&sdma 22 20 1>;
++					dma-names = "rxa", "rxb", "rxc",
++						    "txa", "txb", "txc";
++					fsl,asrc-rate = <48000>;
++					fsl,asrc-width = <16>;
++					status = "okay";
++				};
++
++				asrc_p2p: asrc_p2p {
++					compatible = "fsl,imx6q-asrc-p2p";
++					fsl,output-rate  = <48000>;
++					fsl,output-width = <16>;
++					fsl,asrc-dma-rx-events = <17 18 19>;
++					fsl,asrc-dma-tx-events = <20 21 22>;
++					status = "okay";
+ 				};
+ 
+ 				spba@0203c000 {
+@@ -335,16 +379,20 @@
+ 			};
+ 
+ 			vpu: vpu@02040000 {
+-				compatible = "cnm,coda960";
++				compatible = "cnm,coda960", "fsl,imx6-vpu";
+ 				reg = <0x02040000 0x3c000>;
++				reg-names = "vpu_regs";
+ 				interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
+ 					     <0 3 IRQ_TYPE_LEVEL_HIGH>;
+ 				interrupt-names = "bit", "jpeg";
+ 				clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
+-					 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
+-				clock-names = "per", "ahb";
+-				resets = <&src 1>;
++					 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
++					 <&clks IMX6QDL_CLK_OCRAM>;
++				clock-names = "per", "ahb", "ocram";
++				iramsize = <0x21000>;
+ 				iram = <&ocram>;
++				resets = <&src 1>;
++				power-domains = <&gpc 1>;
+ 			};
+ 
+ 			aipstz@0207c000 { /* AIPSTZ1 */
+@@ -552,20 +600,21 @@
+ 					anatop-min-bit-val = <4>;
+ 					anatop-min-voltage = <800000>;
+ 					anatop-max-voltage = <1375000>;
++					anatop-enable-bit = <0>;
+ 				};
+ 
+-				regulator-3p0@120 {
++				reg_3p0: regulator-3p0@120 {
+ 					compatible = "fsl,anatop-regulator";
+ 					regulator-name = "vdd3p0";
+-					regulator-min-microvolt = <2800000>;
+-					regulator-max-microvolt = <3150000>;
+-					regulator-always-on;
++					regulator-min-microvolt = <2625000>;
++					regulator-max-microvolt = <3400000>;
+ 					anatop-reg-offset = <0x120>;
+ 					anatop-vol-bit-shift = <8>;
+ 					anatop-vol-bit-width = <5>;
+ 					anatop-min-bit-val = <0>;
+ 					anatop-min-voltage = <2625000>;
+ 					anatop-max-voltage = <3400000>;
++					anatop-enable-bit = <0>;
+ 				};
+ 
+ 				regulator-2p5@130 {
+@@ -580,6 +629,7 @@
+ 					anatop-min-bit-val = <0>;
+ 					anatop-min-voltage = <2000000>;
+ 					anatop-max-voltage = <2750000>;
++					anatop-enable-bit = <0>;
+ 				};
+ 
+ 				reg_arm: regulator-vddcore@140 {
+@@ -647,6 +697,7 @@
+ 				reg = <0x020c9000 0x1000>;
+ 				interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+ 				clocks = <&clks IMX6QDL_CLK_USBPHY1>;
++				phy-3p0-supply = <&reg_3p0>;
+ 				fsl,anatop = <&anatop>;
+ 			};
+ 
+@@ -655,9 +706,15 @@
+ 				reg = <0x020ca000 0x1000>;
+ 				interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
+ 				clocks = <&clks IMX6QDL_CLK_USBPHY2>;
++				phy-3p0-supply = <&reg_3p0>;
+ 				fsl,anatop = <&anatop>;
+ 			};
+ 
++			caam_snvs: caam-snvs@020cc000 {
++				compatible = "fsl,imx6q-caam-snvs";
++				reg = <0x020cc000 0x4000>;
++			};
++
+ 			snvs@020cc000 {
+ 				compatible = "fsl,sec-v4.0-mon", "simple-bus";
+ 				#address-cells = <1>;
+@@ -704,14 +761,12 @@
+ 				interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
+ 					     <0 90 IRQ_TYPE_LEVEL_HIGH>;
+ 				interrupt-parent = <&intc>;
+-				pu-supply = <&reg_pu>;
+-				clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+-					 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+-					 <&clks IMX6QDL_CLK_GPU2D_CORE>,
+-					 <&clks IMX6QDL_CLK_GPU2D_AXI>,
+-					 <&clks IMX6QDL_CLK_OPENVG_AXI>,
+-					 <&clks IMX6QDL_CLK_VPU_AXI>;
+ 				#power-domain-cells = <1>;
++				clocks = <&clks 122>, <&clks 74>, <&clks 121>,
++					 <&clks 26>, <&clks 143>, <&clks 168>;
++				clock-names = "gpu3d_core", "gpu3d_shader", "gpu2d_core",
++					      "gpu2d_axi", "openvg_axi", "vpu_axi";
++				pu-supply = <&reg_pu>;
+ 			};
+ 
+ 			gpr: iomuxc-gpr@020e0000 {
+@@ -736,22 +791,6 @@
+ 					#size-cells = <0>;
+ 					reg = <0>;
+ 					status = "disabled";
+-
+-					port@0 {
+-						reg = <0>;
+-
+-						lvds0_mux_0: endpoint {
+-							remote-endpoint = <&ipu1_di0_lvds0>;
+-						};
+-					};
+-
+-					port@1 {
+-						reg = <1>;
+-
+-						lvds0_mux_1: endpoint {
+-							remote-endpoint = <&ipu1_di1_lvds0>;
+-						};
+-					};
+ 				};
+ 
+ 				lvds-channel@1 {
+@@ -759,22 +798,6 @@
+ 					#size-cells = <0>;
+ 					reg = <1>;
+ 					status = "disabled";
+-
+-					port@0 {
+-						reg = <0>;
+-
+-						lvds1_mux_0: endpoint {
+-							remote-endpoint = <&ipu1_di0_lvds1>;
+-						};
+-					};
+-
+-					port@1 {
+-						reg = <1>;
+-
+-						lvds1_mux_1: endpoint {
+-							remote-endpoint = <&ipu1_di1_lvds1>;
+-						};
+-					};
+ 				};
+ 			};
+ 
+@@ -788,32 +811,26 @@
+ 					 <&clks IMX6QDL_CLK_HDMI_ISFR>;
+ 				clock-names = "iahb", "isfr";
+ 				status = "disabled";
+-
+-				port@0 {
+-					reg = <0>;
+-
+-					hdmi_mux_0: endpoint {
+-						remote-endpoint = <&ipu1_di0_hdmi>;
+-					};
+-				};
+-
+-				port@1 {
+-					reg = <1>;
+-
+-					hdmi_mux_1: endpoint {
+-						remote-endpoint = <&ipu1_di1_hdmi>;
+-					};
+-				};
+ 			};
+ 
+ 			dcic1: dcic@020e4000 {
++				compatible = "fsl,imx6q-dcic";
+ 				reg = <0x020e4000 0x4000>;
+ 				interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
++				clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>;
++				clock-names = "dcic", "disp-axi";
++				gpr = <&gpr>;
++				status = "disabled";
+ 			};
+ 
+ 			dcic2: dcic@020e8000 {
++				compatible = "fsl,imx6q-dcic";
+ 				reg = <0x020e8000 0x4000>;
+ 				interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
++				clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>;
++				clock-names = "dcic", "disp-axi";
++				gpr = <&gpr>;
++				status = "disabled";
+ 			};
+ 
+ 			sdma: sdma@020ec000 {
+@@ -824,6 +841,7 @@
+ 					 <&clks IMX6QDL_CLK_SDMA>;
+ 				clock-names = "ipg", "ahb";
+ 				#dma-cells = <3>;
++				iram = <&ocram>;
+ 				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+ 			};
+ 		};
+@@ -835,10 +853,30 @@
+ 			reg = <0x02100000 0x100000>;
+ 			ranges;
+ 
+-			caam@02100000 {
+-				reg = <0x02100000 0x40000>;
+-				interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
+-					     <0 106 IRQ_TYPE_LEVEL_HIGH>;
++			crypto: caam@2100000 {
++				compatible = "fsl,sec-v4.0";
++				#address-cells = <1>;
++				#size-cells = <1>;
++				reg = <0x2100000 0x40000>;
++				ranges = <0 0x2100000 0x40000>;
++				interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */
++				interrupts = <0 92 0x4>;
++				clocks = <&clks 213>, <&clks 214>, <&clks 215> ,<&clks 196>;
++				clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow";
++
++				sec_jr0: jr0@1000 {
++					compatible = "fsl,sec-v4.0-job-ring";
++					reg = <0x1000 0x1000>;
++					interrupt-parent = <&intc>;
++					interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
++				};
++
++				sec_jr1: jr1@2000 {
++					compatible = "fsl,sec-v4.0-job-ring";
++					reg = <0x2000 0x1000>;
++					interrupt-parent = <&intc>;
++					interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
++				};
+ 			};
+ 
+ 			aipstz@0217c000 { /* AIPSTZ2 */
+@@ -852,6 +890,7 @@
+ 				clocks = <&clks IMX6QDL_CLK_USBOH3>;
+ 				fsl,usbphy = <&usbphy1>;
+ 				fsl,usbmisc = <&usbmisc 0>;
++				fsl,anatop = <&anatop>;
+ 				status = "disabled";
+ 			};
+ 
+@@ -903,14 +942,21 @@
+ 					 <&clks IMX6QDL_CLK_ENET>,
+ 					 <&clks IMX6QDL_CLK_ENET_REF>;
+ 				clock-names = "ipg", "ahb", "ptp";
+-				status = "disabled";
++				phy-mode = "rgmii";
++				fsl,magic-packet;
++				status = "okay";
+ 			};
+ 
+-			mlb@0218c000 {
++			mlb: mlb@0218c000 {
+ 				reg = <0x0218c000 0x4000>;
+ 				interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
+ 					     <0 117 IRQ_TYPE_LEVEL_HIGH>,
+ 					     <0 126 IRQ_TYPE_LEVEL_HIGH>;
++				compatible = "fsl,imx6q-mlb150";
++				clocks = <&clks 139>, <&clks 175>;
++				clock-names = "mlb", "pll8_mlb";
++				iram = <&ocram>;
++				status = "disabled";
+ 			};
+ 
+ 			usdhc1: usdhc@02190000 {
+@@ -995,6 +1041,11 @@
+ 				reg = <0x021ac000 0x4000>;
+ 			};
+ 
++			mmdc0-1@021b0000 {
++				compatible = "fsl,imx6q-mmdc-combine";
++				reg = <0x021b0000 0x8000>;
++			};
++
+ 			mmdc0: mmdc@021b0000 { /* MMDC0 */
+ 				compatible = "fsl,imx6q-mmdc";
+ 				reg = <0x021b0000 0x4000>;
+@@ -1011,11 +1062,17 @@
+ 				clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
+ 			};
+ 
+-			ocotp: ocotp@021bc000 {
+-				compatible = "fsl,imx6q-ocotp", "syscon";
++			ocotp: ocotp-ctrl@021bc000 {
++				compatible = "syscon";
+ 				reg = <0x021bc000 0x4000>;
+ 			};
+ 
++			ocotp-fuse@021bc000 {
++				compatible = "fsl,imx6q-ocotp";
++				reg = <0x021bc000 0x4000>;
++				clocks = <&clks 128>;
++			};
++
+ 			tzasc@021d0000 { /* TZASC1 */
+ 				reg = <0x021d0000 0x4000>;
+ 				interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+@@ -1034,39 +1091,38 @@
+ 
+ 			mipi_csi: mipi@021dc000 {
+ 				reg = <0x021dc000 0x4000>;
++				compatible = "fsl,imx6q-mipi-csi2";
++				interrupts = <0 100 0x04>, <0 101 0x04>;
++				clocks = <&clks IMX6QDL_CLK_HSI_TX>,
++					 <&clks IMX6QDL_CLK_EIM_SEL>,
++					 <&clks IMX6QDL_CLK_LVDS2_IN>;
++				/* Note: clks 138 is hsi_tx, however, the dphy_c
++                                 * hsi_tx and pll_refclk use the same clk gate.
++                                 * In current clk driver, open/close clk gate do
++                                 * use hsi_tx for a temporary debug purpose.
++                                 */
++				clock-names = "dphy_clk", "pixel_clk", "cfg_clk";
++				status = "disabled";
+ 			};
+ 
+ 			mipi_dsi: mipi@021e0000 {
++				compatible = "fsl,imx6q-mipi-dsi";
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+ 				reg = <0x021e0000 0x4000>;
+ 				status = "disabled";
+-
+-				ports {
+-					#address-cells = <1>;
+-					#size-cells = <0>;
+-
+-					port@0 {
+-						reg = <0>;
+-
+-						mipi_mux_0: endpoint {
+-							remote-endpoint = <&ipu1_di0_mipi>;
+-						};
+-					};
+-
+-					port@1 {
+-						reg = <1>;
+-
+-						mipi_mux_1: endpoint {
+-							remote-endpoint = <&ipu1_di1_mipi>;
+-						};
+-					};
+-				};
++				interrupts = <0 102 0x04>;
++				gpr = <&gpr>;
++				clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>;
++				clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
+ 			};
+ 
+ 			vdoa@021e4000 {
++				compatible = "fsl,imx6q-vdoa";
+ 				reg = <0x021e4000 0x4000>;
+ 				interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
++				clocks = <&clks 202>;
++				iram = <&ocram>;
+ 			};
+ 
+ 			uart2: serial@021e8000 {
+@@ -1127,67 +1183,14 @@
+ 				     <0 5 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&clks IMX6QDL_CLK_IPU1>,
+ 				 <&clks IMX6QDL_CLK_IPU1_DI0>,
+-				 <&clks IMX6QDL_CLK_IPU1_DI1>;
+-			clock-names = "bus", "di0", "di1";
++				 <&clks IMX6QDL_CLK_IPU1_DI1>,
++                                 <&clks 39>, <&clks 40>,
++                                 <&clks 135>, <&clks 136>;
++			clock-names = "bus", "di0", "di1",
++                                      "di0_sel", "di1_sel",
++                                      "ldb_di0", "ldb_di1";
+ 			resets = <&src 2>;
+-
+-			ipu1_csi0: port@0 {
+-				reg = <0>;
+-			};
+-
+-			ipu1_csi1: port@1 {
+-				reg = <1>;
+-			};
+-
+-			ipu1_di0: port@2 {
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-				reg = <2>;
+-
+-				ipu1_di0_disp0: endpoint@0 {
+-				};
+-
+-				ipu1_di0_hdmi: endpoint@1 {
+-					remote-endpoint = <&hdmi_mux_0>;
+-				};
+-
+-				ipu1_di0_mipi: endpoint@2 {
+-					remote-endpoint = <&mipi_mux_0>;
+-				};
+-
+-				ipu1_di0_lvds0: endpoint@3 {
+-					remote-endpoint = <&lvds0_mux_0>;
+-				};
+-
+-				ipu1_di0_lvds1: endpoint@4 {
+-					remote-endpoint = <&lvds1_mux_0>;
+-				};
+-			};
+-
+-			ipu1_di1: port@3 {
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-				reg = <3>;
+-
+-				ipu1_di0_disp1: endpoint@0 {
+-				};
+-
+-				ipu1_di1_hdmi: endpoint@1 {
+-					remote-endpoint = <&hdmi_mux_1>;
+-				};
+-
+-				ipu1_di1_mipi: endpoint@2 {
+-					remote-endpoint = <&mipi_mux_1>;
+-				};
+-
+-				ipu1_di1_lvds0: endpoint@3 {
+-					remote-endpoint = <&lvds0_mux_1>;
+-				};
+-
+-				ipu1_di1_lvds1: endpoint@4 {
+-					remote-endpoint = <&lvds1_mux_1>;
+-				};
+-			};
++			bypass_reset = <0>;
+ 		};
+ 	};
+ };
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
+--- linux-4.1.3/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi	2015-07-21 19:10:33.000000000 +0200
++++ linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi	2015-07-27 23:13:00.303898027 +0200
+@@ -43,8 +43,10 @@
+ #include "imx6qdl-microsom-ar8035.dtsi"
+ 
+ / {
+-	chosen {
+-		stdout-path = &uart1;
++	aliases {
++		mmc0 = &usdhc2;
++		mmc1 = &usdhc1;
++		mxcfb0 = &mxcfb1;
+ 	};
+ 
+ 	ir_recv: ir-receiver {
+@@ -52,6 +54,7 @@
+ 		gpios = <&gpio3 5 1>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>;
++		linux,rc-map-name = "rc-rc6-mce";
+ 	};
+ 
+ 	regulators {
+@@ -98,32 +101,70 @@
+ 		model = "On-board Codec";
+ 		mux-ext-port = <5>;
+ 		mux-int-port = <1>;
++		cpu-dai = <&ssi1>;
+ 		ssi-controller = <&ssi1>;
+ 	};
+ 
+ 	sound-spdif {
+ 		compatible = "fsl,imx-audio-spdif";
+-		model = "On-board SPDIF";
++		model = "imx-spdif";
+ 		/* IMX6 doesn't implement this yet */
+ 		spdif-controller = <&spdif>;
+ 		spdif-out;
+ 	};
++
++	sound-hdmi {
++		compatible = "fsl,imx6q-audio-hdmi",
++			     "fsl,imx-audio-hdmi";
++		model = "imx-audio-hdmi";
++		hdmi-controller = <&hdmi_audio>;
++	};
++
++	mxcfb1: fb@0 {
++		compatible = "fsl,mxc_sdc_fb";
++		disp_dev = "hdmi";
++		interface_pix_fmt = "RGB24";
++		mode_str ="1920x1080M@60";
++		default_bpp = <32>;
++		int_clk = <0>;
++		late_init = <0>;
++		status = "okay";
++	};
+ };
+ 
+ &audmux {
+ 	status = "okay";
+ };
+ 
+-&can1 {
++/*&can1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
+ 	status = "okay";
+ };
++*/
++&hdmi_core {
++	ipu_id = <0>;
++	disp_id = <0>;
++	status = "okay";
++};
++
++&hdmi_video {
++	fsl,phy_reg_vlev = <0x0294>;
++	fsl,phy_reg_cksymtx = <0x800d>;
++	status = "okay";
++};
++
++&hdmi_audio {
++	status = "okay";
++};
++
++&ocram {
++	status = "okay";
++};
+ 
+-&hdmi {
++&hdmi_cec {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
+-	ddc-i2c-bus = <&i2c2>;
+ 	status = "okay";
+ };
+ 
+@@ -136,6 +177,7 @@
+ 	rtc: pcf8523@68 {
+ 		compatible = "nxp,pcf8523";
+ 		reg = <0x68>;
++		nxp,12p5_pf;
+ 	};
+ 
+ 	/* Pro baseboard model */
+@@ -155,20 +197,57 @@
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
+ 	status = "okay";
++
++	ddc: imx6_hdmi_i2c@50 {
++		compatible = "fsl,imx6-hdmi-i2c";
++		reg = <0x50>;
++	};
+ };
+ 
+ &iomuxc {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_hog>;
+ 	hummingboard {
+-		pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
++		pinctrl_hog: hoggrp {
++			fsl,pins = <
++				/*
++                                 * 26 pin header GPIO description. The pins.
++                                 * numbering as following -
++                                 * GPIO number | GPIO (bank,num) |  PIN number
++                                 * ------------+-----------------+------------
++                                 * gpio1       | (1,1)           | IO7
++                                 * gpio73      | (3,9)           | IO11
++                                 * gpio72      | (3,8)           | IO12
++                                 * gpio71      | (3,7)           | IO13
++                                 * gpio70      | (3,6)           | IO15
++                                 * gpio194     | (7,2)           | IO16
++                                 * gpio195     | (7,3)           | IO18
++                                 * gpio67      | (3,3)           | IO22
++                                 *
++                                 * Notice the gpioX and GPIO (Y,Z) mapping forumla :
++                                 * X = (Y-1) * 32 + Z
++                                 */
++				MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x400130b1
++				MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1
++				MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1
++				MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1
++				MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1
++				MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x400130b1
++				MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x400130b1
++				MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1
++			>;
++		};
++
++/*		pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
+ 				MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
+ 			>;
+ 		};
+-
++*/
+ 		pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 {
+ 			fsl,pins = <
+-				MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1
++				MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x80000000
+ 			>;
+ 		};
+ 
+@@ -198,10 +277,10 @@
+ 
+ 		pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 {
+ 			fsl,pins = <
+-				MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
+-				MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
+-				MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0
+-				MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
++				MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 /*brk*/
++				MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /*ok*/
++				MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /*brk*/
++				MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /*ok*/
+ 				MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
+ 			>;
+ 		};
+@@ -219,7 +298,7 @@
+ 			 * Similar to pinctrl_usbotg_2, but we want it
+ 			 * pulled down for a fixed host connection.
+ 			 */
+-			fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
++			fsl,pins = <MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059>;
+ 		};
+ 
+ 		pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
+@@ -242,6 +321,13 @@
+ 				MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
+ 			>;
+ 		};
++
++		pinctrl_hummingboard_pcie_reset: hummingboard-pcie-reset {
++			fsl,pins = <
++				MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x80000000
++			>;
++		};
++
+ 	};
+ };
+ 
+@@ -256,6 +342,14 @@
+ 	 status = "okay";
+ };
+ 
++&pwm3 {
++	status = "disabled";
++};
++
++&pwm4 {
++	status = "disabled";
++};
++
+ &spdif {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_hummingboard_spdif>;
+@@ -291,3 +385,48 @@
+ 	cd-gpios = <&gpio1 4 0>;
+ 	status = "okay";
+ };
++
++&gpc {
++	fsl,cpu_pupscr_sw2iso = <0xf>;
++	fsl,cpu_pupscr_sw = <0xf>;
++	fsl,cpu_pdnscr_iso2sw = <0x1>;
++	fsl,cpu_pdnscr_iso = <0x1>;
++	status = "okay";
++};
++
++&pcie {
++	pinctrl-names = "default";
++	pinctrl-0 = <
++		&pinctrl_hummingboard_pcie_reset
++	>;
++	reset-gpio = <&gpio3 4 0>;
++	status = "okay";
++	no-msi;
++};
++
++&ecspi1 {
++	status = "okay";
++	fsl,spi-num-chipselects = <1>;
++};
++
++&ecspi2 {
++	status = "okay";
++	fsl,spi-num-chipselects = <2>;
++};
++
++&ecspi3 {
++	status = "okay";
++	fsl,spi-num-chipselects = <3>;
++};
++
++&dcic1 {
++	dcic_id = <0>;
++	dcic_mux = "dcic-hdmi";
++	status = "okay";
++};
++
++&dcic2 {
++	dcic_id = <1>;
++	dcic_mux = "dcic-lvds1";
++	status = "okay";
++};
+diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6qdl-microsom.dtsi linux-xbian-im