From 6a0aa4add30eecf76b9d14ad3f204e4017f9f22c Mon Sep 17 00:00:00 2001 From: Bernhard Reutner-Fischer Date: Wed, 9 Feb 2011 20:08:20 +0100 Subject: arm: mv nptl specific atomic impl to common place Thanks to Nitin Garg for notincing! Signed-off-by: Bernhard Reutner-Fischer --- libc/sysdeps/linux/arm/bits/atomic.h | 122 +++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 libc/sysdeps/linux/arm/bits/atomic.h (limited to 'libc/sysdeps/linux/arm') diff --git a/libc/sysdeps/linux/arm/bits/atomic.h b/libc/sysdeps/linux/arm/bits/atomic.h new file mode 100644 index 000000000..8f63e2510 --- /dev/null +++ b/libc/sysdeps/linux/arm/bits/atomic.h @@ -0,0 +1,122 @@ +/* Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307 USA. */ + +#include +#include + + +typedef int8_t atomic8_t; +typedef uint8_t uatomic8_t; +typedef int_fast8_t atomic_fast8_t; +typedef uint_fast8_t uatomic_fast8_t; + +typedef int32_t atomic32_t; +typedef uint32_t uatomic32_t; +typedef int_fast32_t atomic_fast32_t; +typedef uint_fast32_t uatomic_fast32_t; + +typedef intptr_t atomicptr_t; +typedef uintptr_t uatomicptr_t; +typedef intmax_t atomic_max_t; +typedef uintmax_t uatomic_max_t; + +void __arm_link_error (void); + +#ifdef __thumb2__ +#define atomic_full_barrier() \ + __asm__ __volatile__ \ + ("movw\tip, #0x0fa0\n\t" \ + "movt\tip, #0xffff\n\t" \ + "blx\tip" \ + : : : "ip", "lr", "cc", "memory"); +#else +#define atomic_full_barrier() \ + __asm__ __volatile__ \ + ("mov\tip, #0xffff0fff\n\t" \ + "mov\tlr, pc\n\t" \ + "add\tpc, ip, #(0xffff0fa0 - 0xffff0fff)" \ + : : : "ip", "lr", "cc", "memory"); +#endif + +/* Atomic compare and exchange. This sequence relies on the kernel to + provide a compare and exchange operation which is atomic on the + current architecture, either via cleverness on pre-ARMv6 or via + ldrex / strex on ARMv6. */ + +#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \ + ({ __arm_link_error (); oldval; }) + +#define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \ + ({ __arm_link_error (); oldval; }) + +/* It doesn't matter what register is used for a_oldval2, but we must + specify one to work around GCC PR rtl-optimization/21223. Otherwise + it may cause a_oldval or a_tmp to be moved to a different register. */ + +#ifdef __thumb2__ +/* Thumb-2 has ldrex/strex. However it does not have barrier instructions, + so we still need to use the kernel helper. */ +#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ + ({ register __typeof (oldval) a_oldval __asm__ ("r0"); \ + register __typeof (oldval) a_newval __asm__ ("r1") = (newval); \ + register __typeof (mem) a_ptr __asm__ ("r2") = (mem); \ + register __typeof (oldval) a_tmp __asm__ ("r3"); \ + register __typeof (oldval) a_oldval2 __asm__ ("r4") = (oldval); \ + __asm__ __volatile__ \ + ("0:\tldr\t%[tmp],[%[ptr]]\n\t" \ + "cmp\t%[tmp], %[old2]\n\t" \ + "bne\t1f\n\t" \ + "mov\t%[old], %[old2]\n\t" \ + "movw\t%[tmp], #0x0fc0\n\t" \ + "movt\t%[tmp], #0xffff\n\t" \ + "blx\t%[tmp]\n\t" \ + "bcc\t0b\n\t" \ + "mov\t%[tmp], %[old2]\n\t" \ + "1:" \ + : [old] "=&r" (a_oldval), [tmp] "=&r" (a_tmp) \ + : [new] "r" (a_newval), [ptr] "r" (a_ptr), \ + [old2] "r" (a_oldval2) \ + : "ip", "lr", "cc", "memory"); \ + a_tmp; }) +#else +#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ + ({ register __typeof (oldval) a_oldval __asm__ ("r0"); \ + register __typeof (oldval) a_newval __asm__ ("r1") = (newval); \ + register __typeof (mem) a_ptr __asm__ ("r2") = (mem); \ + register __typeof (oldval) a_tmp __asm__ ("r3"); \ + register __typeof (oldval) a_oldval2 __asm__ ("r4") = (oldval); \ + __asm__ __volatile__ \ + ("0:\tldr\t%[tmp],[%[ptr]]\n\t" \ + "cmp\t%[tmp], %[old2]\n\t" \ + "bne\t1f\n\t" \ + "mov\t%[old], %[old2]\n\t" \ + "mov\t%[tmp], #0xffff0fff\n\t" \ + "mov\tlr, pc\n\t" \ + "add\tpc, %[tmp], #(0xffff0fc0 - 0xffff0fff)\n\t" \ + "bcc\t0b\n\t" \ + "mov\t%[tmp], %[old2]\n\t" \ + "1:" \ + : [old] "=&r" (a_oldval), [tmp] "=&r" (a_tmp) \ + : [new] "r" (a_newval), [ptr] "r" (a_ptr), \ + [old2] "r" (a_oldval2) \ + : "ip", "lr", "cc", "memory"); \ + a_tmp; }) +#endif + +#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \ + ({ __arm_link_error (); oldval; }) -- cgit v1.2.3 From da2d70ed69b57d63243a7b1e05ac7d43e91778ab Mon Sep 17 00:00:00 2001 From: Bernhard Reutner-Fischer Date: Fri, 11 Feb 2011 17:26:19 +0100 Subject: arm: use CAS gcc builtin if SI-mode pattern is available Signed-off-by: Bernhard Reutner-Fischer --- libc/sysdeps/linux/arm/bits/atomic.h | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) (limited to 'libc/sysdeps/linux/arm') diff --git a/libc/sysdeps/linux/arm/bits/atomic.h b/libc/sysdeps/linux/arm/bits/atomic.h index 8f63e2510..07101fbe8 100644 --- a/libc/sysdeps/linux/arm/bits/atomic.h +++ b/libc/sysdeps/linux/arm/bits/atomic.h @@ -37,7 +37,12 @@ typedef uintmax_t uatomic_max_t; void __arm_link_error (void); -#ifdef __thumb2__ +/* Use the atomic builtins provided by GCC in case the backend provides + a pattern to do this efficiently. */ + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 +#define atomic_full_barrier() __sync_synchronize () +#elif defined __thumb2__ #define atomic_full_barrier() \ __asm__ __volatile__ \ ("movw\tip, #0x0fa0\n\t" \ @@ -64,17 +69,21 @@ void __arm_link_error (void); #define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \ ({ __arm_link_error (); oldval; }) +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 +#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ + __sync_val_compare_and_swap ((mem), (oldval), (newval)) + /* It doesn't matter what register is used for a_oldval2, but we must specify one to work around GCC PR rtl-optimization/21223. Otherwise it may cause a_oldval or a_tmp to be moved to a different register. */ -#ifdef __thumb2__ +#elif defined __thumb2__ /* Thumb-2 has ldrex/strex. However it does not have barrier instructions, so we still need to use the kernel helper. */ #define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ - ({ register __typeof (oldval) a_oldval __asm__ ("r0"); \ - register __typeof (oldval) a_newval __asm__ ("r1") = (newval); \ - register __typeof (mem) a_ptr __asm__ ("r2") = (mem); \ + ({ register __typeof (oldval) a_oldval __asm__ ("r0"); \ + register __typeof (oldval) a_newval __asm__ ("r1") = (newval); \ + register __typeof (mem) a_ptr __asm__ ("r2") = (mem); \ register __typeof (oldval) a_tmp __asm__ ("r3"); \ register __typeof (oldval) a_oldval2 __asm__ ("r4") = (oldval); \ __asm__ __volatile__ \ @@ -95,9 +104,9 @@ void __arm_link_error (void); a_tmp; }) #else #define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ - ({ register __typeof (oldval) a_oldval __asm__ ("r0"); \ - register __typeof (oldval) a_newval __asm__ ("r1") = (newval); \ - register __typeof (mem) a_ptr __asm__ ("r2") = (mem); \ + ({ register __typeof (oldval) a_oldval __asm__ ("r0"); \ + register __typeof (oldval) a_newval __asm__ ("r1") = (newval); \ + register __typeof (mem) a_ptr __asm__ ("r2") = (mem); \ register __typeof (oldval) a_tmp __asm__ ("r3"); \ register __typeof (oldval) a_oldval2 __asm__ ("r4") = (oldval); \ __asm__ __volatile__ \ -- cgit v1.2.3 From 73d59554144f429b1cf0d4d7fa7de42bdf59ad92 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 23 Jul 2009 01:11:38 -0400 Subject: unify stub logic Signed-off-by: Mike Frysinger --- libc/sysdeps/linux/arm/posix_fadvise.c | 2 +- libc/sysdeps/linux/arm/posix_fadvise64.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'libc/sysdeps/linux/arm') diff --git a/libc/sysdeps/linux/arm/posix_fadvise.c b/libc/sysdeps/linux/arm/posix_fadvise.c index 278bff981..80d3c5044 100644 --- a/libc/sysdeps/linux/arm/posix_fadvise.c +++ b/libc/sysdeps/linux/arm/posix_fadvise.c @@ -39,7 +39,7 @@ int posix_fadvise(int fd, off_t offset, off_t len, int advise) /* weak_alias(__libc_posix_fadvise, posix_fadvise); */ -#else +#elif defined __UCLIBC_HAS_STUBS__ int posix_fadvise(int fd attribute_unused, off_t offset attribute_unused, off_t len attribute_unused, int advice attribute_unused) { diff --git a/libc/sysdeps/linux/arm/posix_fadvise64.c b/libc/sysdeps/linux/arm/posix_fadvise64.c index 4b27381d1..678c42f90 100644 --- a/libc/sysdeps/linux/arm/posix_fadvise64.c +++ b/libc/sysdeps/linux/arm/posix_fadvise64.c @@ -47,7 +47,7 @@ int posix_fadvise64(int fd, __off64_t offset, __off64_t len, int advise) /* weak_alias(__libc_posix_fadvise64, posix_fadvise64); */ -#else +#elif defined __UCLIBC_HAS_STUBS__ int posix_fadvise64(int fd, __off64_t offset, __off64_t len, int advise) { -- cgit v1.2.3 From 41647059ec1945a258a9ee26638a1c0e4d181eaa Mon Sep 17 00:00:00 2001 From: "Peter S. Mazinger" Date: Wed, 9 Mar 2011 12:31:15 +0100 Subject: bits/kernel_stat.h: no need for _LIBC guard, the file is not installed on target Signed-off-by: Peter S. Mazinger --- libc/sysdeps/linux/arm/bits/kernel_stat.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'libc/sysdeps/linux/arm') diff --git a/libc/sysdeps/linux/arm/bits/kernel_stat.h b/libc/sysdeps/linux/arm/bits/kernel_stat.h index 2ca63a223..7bd89f9ab 100644 --- a/libc/sysdeps/linux/arm/bits/kernel_stat.h +++ b/libc/sysdeps/linux/arm/bits/kernel_stat.h @@ -1,10 +1,6 @@ #ifndef _BITS_STAT_STRUCT_H #define _BITS_STAT_STRUCT_H -#ifndef _LIBC -#error bits/kernel_stat.h is for internal uClibc use only! -#endif - /* This file provides whatever this particular arch's kernel thinks * struct kernel_stat should look like... It turns out each arch has a * different opinion on the subject... */ -- cgit v1.2.3 From 3fa004b7d2d9a3648aa95b093000259a123fa2d8 Mon Sep 17 00:00:00 2001 From: "Peter S. Mazinger" Date: Wed, 9 Mar 2011 15:14:48 +0100 Subject: regcomp.c, aeabi_mb_cur_max.c: use unconditionally MB_CUR_MAX from stdlib.h Signed-off-by: Peter S. Mazinger --- libc/sysdeps/linux/arm/aeabi_mb_cur_max.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'libc/sysdeps/linux/arm') diff --git a/libc/sysdeps/linux/arm/aeabi_mb_cur_max.c b/libc/sysdeps/linux/arm/aeabi_mb_cur_max.c index f12309eaf..77e979a65 100644 --- a/libc/sysdeps/linux/arm/aeabi_mb_cur_max.c +++ b/libc/sysdeps/linux/arm/aeabi_mb_cur_max.c @@ -23,9 +23,5 @@ int __aeabi_MB_CUR_MAX (void) { -#ifdef __UCLIBC_HAS_WCHAR__ return MB_CUR_MAX; -#else - return 1; -#endif } -- cgit v1.2.3 From e25a95a7a3c9f5bb3a38106422b12f83bf58d119 Mon Sep 17 00:00:00 2001 From: Khem Raj Date: Mon, 14 Mar 2011 22:45:33 -0700 Subject: arm/bits/atomic.h: Include common/bit/atomic.h for thumb1 This restores the behavior for thumb1 builds and yet uses the new atomic.h for arm and thumb2 modes. Signed-off-by: Khem Raj --- libc/sysdeps/linux/arm/bits/atomic.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'libc/sysdeps/linux/arm') diff --git a/libc/sysdeps/linux/arm/bits/atomic.h b/libc/sysdeps/linux/arm/bits/atomic.h index 07101fbe8..0b90330dd 100644 --- a/libc/sysdeps/linux/arm/bits/atomic.h +++ b/libc/sysdeps/linux/arm/bits/atomic.h @@ -16,6 +16,9 @@ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. */ +#if defined __thumb__ && !defined __thumb2__ +#include_next +#else #include #include @@ -129,3 +132,5 @@ void __arm_link_error (void); #define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \ ({ __arm_link_error (); oldval; }) + +#endif -- cgit v1.2.3