From afab56958f1cbb47b831ee3ebff231dfbae74af2 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Thu, 19 Feb 2015 19:13:59 +0530 Subject: ARCv2 ISA support This is next gen Instruction Set Architecture from Synopsys and basis for the ARC HS family of processors. http://www.synopsys.com/dw/ipdir.php?ds=arc-hs38-processor&elq_mid=5732&elq_cid=458802 http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/arc-hs/Pages/default.aspx Signed-off-by: Vineet Gupta Signed-off-by: Bernhard Reutner-Fischer --- libc/sysdeps/linux/arc/bits/uClibc_arch_features.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'libc/sysdeps/linux/arc/bits/uClibc_arch_features.h') diff --git a/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h b/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h index 8af6eca4c..451575586 100755 --- a/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h +++ b/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h @@ -47,4 +47,11 @@ /* The default ';' is a comment on ARC. */ #define __UCLIBC_ASM_LINE_SEP__ ` +/* does your target align 64bit values in register pairs ? (32bit arches only) */ +#if defined(__A7__) +#undef __UCLIBC_SYSCALL_ALIGN_64BIT__ +#else +#define __UCLIBC_SYSCALL_ALIGN_64BIT__ +#endif + #endif /* _BITS_UCLIBC_ARCH_FEATURES_H */ -- cgit v1.2.3