From afab56958f1cbb47b831ee3ebff231dfbae74af2 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Thu, 19 Feb 2015 19:13:59 +0530 Subject: ARCv2 ISA support This is next gen Instruction Set Architecture from Synopsys and basis for the ARC HS family of processors. http://www.synopsys.com/dw/ipdir.php?ds=arc-hs38-processor&elq_mid=5732&elq_cid=458802 http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/arc-hs/Pages/default.aspx Signed-off-by: Vineet Gupta Signed-off-by: Bernhard Reutner-Fischer --- ldso/ldso/arc/elfinterp.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'ldso/ldso/arc/elfinterp.c') diff --git a/ldso/ldso/arc/elfinterp.c b/ldso/ldso/arc/elfinterp.c index d26c94705..7c31d3ac7 100644 --- a/ldso/ldso/arc/elfinterp.c +++ b/ldso/ldso/arc/elfinterp.c @@ -11,7 +11,11 @@ */ #include "ldso.h" +#ifdef __A7__ #define ARC_PLT_SIZE 12 +#else +#define ARC_PLT_SIZE 16 +#endif unsigned long _dl_linux_resolver(struct elf_resolve *tpnt, unsigned int plt_pc) -- cgit v1.2.3