From 4d8e5484afb4978f672a8568ddd12e628fb02724 Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Thu, 8 Oct 2015 20:28:39 +0200 Subject: add new architecture support for or1k Information about Openrisc: http://opencores.org/or1k/Main_Page Integrated from: https://github.com/openrisc/uClibc-or1k --- include/elf.h | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/elf.h b/include/elf.h index 18d286b03..ed952664f 100644 --- a/include/elf.h +++ b/include/elf.h @@ -257,7 +257,7 @@ typedef struct #define EM_MN10300 89 /* Matsushita MN10300 */ #define EM_MN10200 90 /* Matsushita MN10200 */ #define EM_PJ 91 /* picoJava */ -#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ +#define EM_OR1K 92 /* OpenRISC 32-bit embedded processor */ #define EM_ARCOMPACT 93 /* ARCompact ISA based Cores: ARC 700 */ #define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ #define EM_IP2K 101 /* Ubicom IP2022 micro controller */ @@ -3188,6 +3188,30 @@ typedef Elf32_Addr Elf32_Conflict; #define R_METAG_TLS_DTPMOD 57 #define R_METAG_TLS_DTPOFF 58 +/* OpenRISC 1000 specific relocs */ +#define R_OR1K_NONE 0 +#define R_OR1K_32 1 +#define R_OR1K_16 2 +#define R_OR1K_8 3 +#define R_OR1K_LO_16_IN_INSN 4 +#define R_OR1K_HI_16_IN_INSN 5 +#define R_OR1K_INSN_REL_26 6 +#define R_OR1K_GNU_VTENTRY 7 +#define R_OR1K_GNU_VTINHERIT 8 +#define R_OR1K_32_PCREL 9 +#define R_OR1K_16_PCREL 10 +#define R_OR1K_8_PCREL 11 +#define R_OR1K_GOTPC_HI16 12 +#define R_OR1K_GOTPC_LO16 13 +#define R_OR1K_GOT16 14 +#define R_OR1K_PLT26 15 +#define R_OR1K_GOTOFF_HI16 16 +#define R_OR1K_GOTOFF_LO16 17 +#define R_OR1K_COPY 18 +#define R_OR1K_GLOB_DAT 19 +#define R_OR1K_JMP_SLOT 20 +#define R_OR1K_RELATIVE 21 + /* ARCompact specific relocs */ #define R_ARC_NONE 0x0 #define R_ARC_8 0x1 -- cgit v1.2.3