diff -Nur gcc-4.2.4.orig/ccs_version.h gcc-4.2.4/ccs_version.h
--- gcc-4.2.4.orig/ccs_version.h 1969-12-31 18:00:00.000000000 -0600
+++ gcc-4.2.4/ccs_version.h 2015-07-03 18:46:05.717283542 -0500
@@ -0,0 +1,8 @@
+/* This file has been generated by CCS - do not edit. */
+
+#define CCS_FULL_VSTR "1.4.0.3"
+
+#define CCS_MAJOR_VN 1
+#define CCS_MINOR_VN 4
+#define CCS_RELEASE_VN 0
+#define CCS_BUILD_VN 3
diff -Nur gcc-4.2.4.orig/config.guess gcc-4.2.4/config.guess
--- gcc-4.2.4.orig/config.guess 2006-10-15 22:27:17.000000000 -0500
+++ gcc-4.2.4/config.guess 2015-07-03 19:15:14.097267674 -0500
@@ -1,14 +1,12 @@
#! /bin/sh
# Attempt to guess a canonical system name.
-# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-# 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
-# Inc.
+# Copyright 1992-2014 Free Software Foundation, Inc.
-timestamp='2006-07-02'
+timestamp='2014-03-23'
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
+# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful, but
@@ -17,26 +15,22 @@
# General Public License for more details.
#
# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
-# 02110-1301, USA.
+# along with this program; if not, see .
#
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
# configuration script generated by Autoconf, you may include it under
-# the same distribution terms that you use for the rest of that program.
-
-
-# Originally written by Per Bothner .
-# Please send patches to . Submit a context
-# diff and a properly formatted ChangeLog entry.
+# the same distribution terms that you use for the rest of that
+# program. This Exception is an additional permission under section 7
+# of the GNU General Public License, version 3 ("GPLv3").
#
-# This script attempts to guess a canonical system name similar to
-# config.sub. If it succeeds, it prints the system name on stdout, and
-# exits with 0. Otherwise, it exits with 1.
+# Originally written by Per Bothner.
#
-# The plan is that this can be called by configure scripts if you
-# don't specify an explicit build system type.
+# You can get the latest version of this script from:
+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD
+#
+# Please send patches with a ChangeLog entry to config-patches@gnu.org.
+
me=`echo "$0" | sed -e 's,.*/,,'`
@@ -56,8 +50,7 @@
GNU config.guess ($timestamp)
Originally written by Per Bothner.
-Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
-Free Software Foundation, Inc.
+Copyright 1992-2014 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
@@ -139,12 +132,33 @@
UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown
UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown
+case "${UNAME_SYSTEM}" in
+Linux|GNU|GNU/*)
+ # If the system lacks a compiler, then just pick glibc.
+ # We could probably try harder.
+ LIBC=gnu
+
+ eval $set_cc_for_build
+ cat <<-EOF > $dummy.c
+ #include
+ #if defined(__UCLIBC__)
+ LIBC=uclibc
+ #elif defined(__dietlibc__)
+ LIBC=dietlibc
+ #else
+ LIBC=gnu
+ #endif
+ EOF
+ eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC' | sed 's, ,,g'`
+ ;;
+esac
+
# Note: order is significant - the case branches are not exclusive.
case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
*:NetBSD:*:*)
# NetBSD (nbsd) targets should (where applicable) match one or
- # more of the tupples: *-*-netbsdelf*, *-*-netbsdaout*,
+ # more of the tuples: *-*-netbsdelf*, *-*-netbsdaout*,
# *-*-netbsdecoff* and *-*-netbsd*. For targets that recently
# switched to ELF, *-*-netbsd* would select the old
# object file format. This provides both forward
@@ -161,6 +175,7 @@
arm*) machine=arm-unknown ;;
sh3el) machine=shl-unknown ;;
sh3eb) machine=sh-unknown ;;
+ sh5el) machine=sh5le-unknown ;;
*) machine=${UNAME_MACHINE_ARCH}-unknown ;;
esac
# The Operating System including object format, if it has switched
@@ -169,7 +184,7 @@
arm*|i386|m68k|ns32k|sh3*|sparc|vax)
eval $set_cc_for_build
if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \
- | grep __ELF__ >/dev/null
+ | grep -q __ELF__
then
# Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout).
# Return netbsd for either. FIX?
@@ -179,7 +194,7 @@
fi
;;
*)
- os=netbsd
+ os=netbsd
;;
esac
# The OS release
@@ -200,6 +215,10 @@
# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used.
echo "${machine}-${os}${release}"
exit ;;
+ *:Bitrig:*:*)
+ UNAME_MACHINE_ARCH=`arch | sed 's/Bitrig.//'`
+ echo ${UNAME_MACHINE_ARCH}-unknown-bitrig${UNAME_RELEASE}
+ exit ;;
*:OpenBSD:*:*)
UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'`
echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE}
@@ -222,7 +241,7 @@
UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'`
;;
*5.*)
- UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'`
+ UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'`
;;
esac
# According to Compaq, /usr/sbin/psrinfo has been available on
@@ -268,7 +287,10 @@
# A Xn.n version is an unreleased experimental baselevel.
# 1.2 uses "1.2" for uname -r.
echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'`
- exit ;;
+ # Reset EXIT trap before exiting to avoid spurious non-zero exit code.
+ exitcode=$?
+ trap '' 0
+ exit $exitcode ;;
Alpha\ *:Windows_NT*:*)
# How do we know it's Interix rather than the generic POSIX subsystem?
# Should we change UNAME_MACHINE based on the output of uname instead
@@ -294,12 +316,12 @@
echo s390-ibm-zvmoe
exit ;;
*:OS400:*:*)
- echo powerpc-ibm-os400
+ echo powerpc-ibm-os400
exit ;;
arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*)
echo arm-acorn-riscix${UNAME_RELEASE}
exit ;;
- arm:riscos:*:*|arm:RISCOS:*:*)
+ arm*:riscos:*:*|arm*:RISCOS:*:*)
echo arm-unknown-riscos
exit ;;
SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*)
@@ -323,14 +345,33 @@
case `/usr/bin/uname -p` in
sparc) echo sparc-icl-nx7; exit ;;
esac ;;
+ s390x:SunOS:*:*)
+ echo ${UNAME_MACHINE}-ibm-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+ exit ;;
sun4H:SunOS:5.*:*)
echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
exit ;;
sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*)
echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
exit ;;
- i86pc:SunOS:5.*:*)
- echo i386-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+ i86pc:AuroraUX:5.*:* | i86xen:AuroraUX:5.*:*)
+ echo i386-pc-auroraux${UNAME_RELEASE}
+ exit ;;
+ i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*)
+ eval $set_cc_for_build
+ SUN_ARCH="i386"
+ # If there is a compiler, see if it is configured for 64-bit objects.
+ # Note that the Sun cc does not turn __LP64__ into 1 like gcc does.
+ # This test works for both compilers.
+ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then
+ if (echo '#ifdef __amd64'; echo IS_64BIT_ARCH; echo '#endif') | \
+ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \
+ grep IS_64BIT_ARCH >/dev/null
+ then
+ SUN_ARCH="x86_64"
+ fi
+ fi
+ echo ${SUN_ARCH}-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
exit ;;
sun4*:SunOS:6*:*)
# According to config.sub, this is the proper way to canonicalize
@@ -374,23 +415,23 @@
# MiNT. But MiNT is downward compatible to TOS, so this should
# be no problem.
atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*)
- echo m68k-atari-mint${UNAME_RELEASE}
+ echo m68k-atari-mint${UNAME_RELEASE}
exit ;;
atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*)
echo m68k-atari-mint${UNAME_RELEASE}
- exit ;;
+ exit ;;
*falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*)
- echo m68k-atari-mint${UNAME_RELEASE}
+ echo m68k-atari-mint${UNAME_RELEASE}
exit ;;
milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*)
- echo m68k-milan-mint${UNAME_RELEASE}
- exit ;;
+ echo m68k-milan-mint${UNAME_RELEASE}
+ exit ;;
hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*)
- echo m68k-hades-mint${UNAME_RELEASE}
- exit ;;
+ echo m68k-hades-mint${UNAME_RELEASE}
+ exit ;;
*:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*)
- echo m68k-unknown-mint${UNAME_RELEASE}
- exit ;;
+ echo m68k-unknown-mint${UNAME_RELEASE}
+ exit ;;
m68k:machten:*:*)
echo m68k-apple-machten${UNAME_RELEASE}
exit ;;
@@ -460,8 +501,8 @@
echo m88k-motorola-sysv3
exit ;;
AViiON:dgux:*:*)
- # DG/UX returns AViiON for all architectures
- UNAME_PROCESSOR=`/usr/bin/uname -p`
+ # DG/UX returns AViiON for all architectures
+ UNAME_PROCESSOR=`/usr/bin/uname -p`
if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ]
then
if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \
@@ -474,7 +515,7 @@
else
echo i586-dg-dgux${UNAME_RELEASE}
fi
- exit ;;
+ exit ;;
M88*:DolphinOS:*:*) # DolphinOS (SVR3)
echo m88k-dolphin-sysv3
exit ;;
@@ -531,7 +572,7 @@
echo rs6000-ibm-aix3.2
fi
exit ;;
- *:AIX:*:[45])
+ *:AIX:*:[4567])
IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'`
if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then
IBM_ARCH=rs6000
@@ -574,52 +615,52 @@
9000/[678][0-9][0-9])
if [ -x /usr/bin/getconf ]; then
sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null`
- sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null`
- case "${sc_cpu_version}" in
- 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0
- 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1
- 532) # CPU_PA_RISC2_0
- case "${sc_kernel_bits}" in
- 32) HP_ARCH="hppa2.0n" ;;
- 64) HP_ARCH="hppa2.0w" ;;
+ sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null`
+ case "${sc_cpu_version}" in
+ 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0
+ 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1
+ 532) # CPU_PA_RISC2_0
+ case "${sc_kernel_bits}" in
+ 32) HP_ARCH="hppa2.0n" ;;
+ 64) HP_ARCH="hppa2.0w" ;;
'') HP_ARCH="hppa2.0" ;; # HP-UX 10.20
- esac ;;
- esac
+ esac ;;
+ esac
fi
if [ "${HP_ARCH}" = "" ]; then
eval $set_cc_for_build
- sed 's/^ //' << EOF >$dummy.c
+ sed 's/^ //' << EOF >$dummy.c
+
+ #define _HPUX_SOURCE
+ #include
+ #include
+
+ int main ()
+ {
+ #if defined(_SC_KERNEL_BITS)
+ long bits = sysconf(_SC_KERNEL_BITS);
+ #endif
+ long cpu = sysconf (_SC_CPU_VERSION);
- #define _HPUX_SOURCE
- #include
- #include
-
- int main ()
- {
- #if defined(_SC_KERNEL_BITS)
- long bits = sysconf(_SC_KERNEL_BITS);
- #endif
- long cpu = sysconf (_SC_CPU_VERSION);
-
- switch (cpu)
- {
- case CPU_PA_RISC1_0: puts ("hppa1.0"); break;
- case CPU_PA_RISC1_1: puts ("hppa1.1"); break;
- case CPU_PA_RISC2_0:
- #if defined(_SC_KERNEL_BITS)
- switch (bits)
- {
- case 64: puts ("hppa2.0w"); break;
- case 32: puts ("hppa2.0n"); break;
- default: puts ("hppa2.0"); break;
- } break;
- #else /* !defined(_SC_KERNEL_BITS) */
- puts ("hppa2.0"); break;
- #endif
- default: puts ("hppa1.0"); break;
- }
- exit (0);
- }
+ switch (cpu)
+ {
+ case CPU_PA_RISC1_0: puts ("hppa1.0"); break;
+ case CPU_PA_RISC1_1: puts ("hppa1.1"); break;
+ case CPU_PA_RISC2_0:
+ #if defined(_SC_KERNEL_BITS)
+ switch (bits)
+ {
+ case 64: puts ("hppa2.0w"); break;
+ case 32: puts ("hppa2.0n"); break;
+ default: puts ("hppa2.0"); break;
+ } break;
+ #else /* !defined(_SC_KERNEL_BITS) */
+ puts ("hppa2.0"); break;
+ #endif
+ default: puts ("hppa1.0"); break;
+ }
+ exit (0);
+ }
EOF
(CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy`
test -z "$HP_ARCH" && HP_ARCH=hppa
@@ -639,7 +680,7 @@
# => hppa64-hp-hpux11.23
if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) |
- grep __LP64__ >/dev/null
+ grep -q __LP64__
then
HP_ARCH="hppa2.0w"
else
@@ -710,22 +751,22 @@
exit ;;
C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*)
echo c1-convex-bsd
- exit ;;
+ exit ;;
C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*)
if getsysinfo -f scalar_acc
then echo c32-convex-bsd
else echo c2-convex-bsd
fi
- exit ;;
+ exit ;;
C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*)
echo c34-convex-bsd
- exit ;;
+ exit ;;
C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*)
echo c38-convex-bsd
- exit ;;
+ exit ;;
C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*)
echo c4-convex-bsd
- exit ;;
+ exit ;;
CRAY*Y-MP:*:*:*)
echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
exit ;;
@@ -749,14 +790,14 @@
exit ;;
F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*)
FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'`
- FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'`
- FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'`
- echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
- exit ;;
+ FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'`
+ FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'`
+ echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
+ exit ;;
5000:UNIX_System_V:4.*:*)
- FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'`
- FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'`
- echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
+ FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'`
+ FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'`
+ echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
exit ;;
i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*)
echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE}
@@ -768,37 +809,51 @@
echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE}
exit ;;
*:FreeBSD:*:*)
- case ${UNAME_MACHINE} in
- pc98)
- echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
+ UNAME_PROCESSOR=`/usr/bin/uname -p`
+ case ${UNAME_PROCESSOR} in
amd64)
echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
*)
- echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
+ echo ${UNAME_PROCESSOR}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;;
esac
exit ;;
i*:CYGWIN*:*)
echo ${UNAME_MACHINE}-pc-cygwin
exit ;;
- i*:MINGW*:*)
+ *:MINGW64*:*)
+ echo ${UNAME_MACHINE}-pc-mingw64
+ exit ;;
+ *:MINGW*:*)
echo ${UNAME_MACHINE}-pc-mingw32
exit ;;
+ *:MSYS*:*)
+ echo ${UNAME_MACHINE}-pc-msys
+ exit ;;
i*:windows32*:*)
- # uname -m includes "-pc" on this system.
- echo ${UNAME_MACHINE}-mingw32
+ # uname -m includes "-pc" on this system.
+ echo ${UNAME_MACHINE}-mingw32
exit ;;
i*:PW*:*)
echo ${UNAME_MACHINE}-pc-pw32
exit ;;
- x86:Interix*:[3456]*)
- echo i586-pc-interix${UNAME_RELEASE}
- exit ;;
- EM64T:Interix*:[3456]*)
- echo x86_64-unknown-interix${UNAME_RELEASE}
- exit ;;
+ *:Interix*:*)
+ case ${UNAME_MACHINE} in
+ x86)
+ echo i586-pc-interix${UNAME_RELEASE}
+ exit ;;
+ authenticamd | genuineintel | EM64T)
+ echo x86_64-unknown-interix${UNAME_RELEASE}
+ exit ;;
+ IA64)
+ echo ia64-unknown-interix${UNAME_RELEASE}
+ exit ;;
+ esac ;;
[345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*)
echo i${UNAME_MACHINE}-pc-mks
exit ;;
+ 8664:Windows_NT:*)
+ echo x86_64-pc-mks
+ exit ;;
i*:Windows_NT*:* | Pentium*:Windows_NT*:*)
# How do we know it's Interix rather than the generic POSIX subsystem?
# It also conflicts with pre-2.0 versions of AT&T UWIN. Should we
@@ -819,200 +874,157 @@
exit ;;
*:GNU:*:*)
# the GNU system
- echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'`
+ echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'`
exit ;;
*:GNU/*:*:*)
# other systems with GNU libc and userland
- echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu
+ echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC}
exit ;;
i*86:Minix:*:*)
echo ${UNAME_MACHINE}-pc-minix
exit ;;
+ aarch64:Linux:*:*)
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+ exit ;;
+ aarch64_be:Linux:*:*)
+ UNAME_MACHINE=aarch64_be
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+ exit ;;
+ alpha:Linux:*:*)
+ case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in
+ EV5) UNAME_MACHINE=alphaev5 ;;
+ EV56) UNAME_MACHINE=alphaev56 ;;
+ PCA56) UNAME_MACHINE=alphapca56 ;;
+ PCA57) UNAME_MACHINE=alphapca56 ;;
+ EV6) UNAME_MACHINE=alphaev6 ;;
+ EV67) UNAME_MACHINE=alphaev67 ;;
+ EV68*) UNAME_MACHINE=alphaev68 ;;
+ esac
+ objdump --private-headers /bin/sh | grep -q ld.so.1
+ if test "$?" = 0 ; then LIBC="gnulibc1" ; fi
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+ exit ;;
+ arc:Linux:*:* | arceb:Linux:*:*)
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+ exit ;;
arm*:Linux:*:*)
- echo ${UNAME_MACHINE}-unknown-linux-gnu
+ eval $set_cc_for_build
+ if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \
+ | grep -q __ARM_EABI__
+ then
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+ else
+ if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \
+ | grep -q __ARM_PCS_VFP
+ then
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi
+ else
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf
+ fi
+ fi
exit ;;
avr32*:Linux:*:*)
- echo ${UNAME_MACHINE}-unknown-linux-gnu
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
exit ;;
cris:Linux:*:*)
- echo cris-axis-linux-gnu
+ echo ${UNAME_MACHINE}-axis-linux-${LIBC}
exit ;;
crisv32:Linux:*:*)
- echo crisv32-axis-linux-gnu
+ echo ${UNAME_MACHINE}-axis-linux-${LIBC}
exit ;;
frv:Linux:*:*)
- echo frv-unknown-linux-gnu
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+ exit ;;
+ hexagon:Linux:*:*)
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+ exit ;;
+ i*86:Linux:*:*)
+ echo ${UNAME_MACHINE}-pc-linux-${LIBC}
exit ;;
ia64:Linux:*:*)
- echo ${UNAME_MACHINE}-unknown-linux-gnu
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
exit ;;
m32r*:Linux:*:*)
- echo ${UNAME_MACHINE}-unknown-linux-gnu
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
exit ;;
m68*:Linux:*:*)
- echo ${UNAME_MACHINE}-unknown-linux-gnu
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
exit ;;
- mips:Linux:*:*)
+ mips:Linux:*:* | mips64:Linux:*:*)
eval $set_cc_for_build
sed 's/^ //' << EOF >$dummy.c
#undef CPU
- #undef mips
- #undef mipsel
+ #undef ${UNAME_MACHINE}
+ #undef ${UNAME_MACHINE}el
#if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL)
- CPU=mipsel
+ CPU=${UNAME_MACHINE}el
#else
#if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB)
- CPU=mips
+ CPU=${UNAME_MACHINE}
#else
CPU=
#endif
#endif
EOF
- eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n '
- /^CPU/{
- s: ::g
- p
- }'`"
- test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; }
+ eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'`
+ test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; }
;;
- mips64:Linux:*:*)
- eval $set_cc_for_build
- sed 's/^ //' << EOF >$dummy.c
- #undef CPU
- #undef mips64
- #undef mips64el
- #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL)
- CPU=mips64el
- #else
- #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB)
- CPU=mips64
- #else
- CPU=
- #endif
- #endif
-EOF
- eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n '
- /^CPU/{
- s: ::g
- p
- }'`"
- test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; }
- ;;
- or32:Linux:*:*)
- echo or32-unknown-linux-gnu
+ openrisc*:Linux:*:*)
+ echo or1k-unknown-linux-${LIBC}
exit ;;
- ppc:Linux:*:*)
- echo powerpc-unknown-linux-gnu
+ or32:Linux:*:* | or1k*:Linux:*:*)
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
exit ;;
- ppc64:Linux:*:*)
- echo powerpc64-unknown-linux-gnu
+ padre:Linux:*:*)
+ echo sparc-unknown-linux-${LIBC}
exit ;;
- alpha:Linux:*:*)
- case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in
- EV5) UNAME_MACHINE=alphaev5 ;;
- EV56) UNAME_MACHINE=alphaev56 ;;
- PCA56) UNAME_MACHINE=alphapca56 ;;
- PCA57) UNAME_MACHINE=alphapca56 ;;
- EV6) UNAME_MACHINE=alphaev6 ;;
- EV67) UNAME_MACHINE=alphaev67 ;;
- EV68*) UNAME_MACHINE=alphaev68 ;;
- esac
- objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null
- if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi
- echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC}
+ parisc64:Linux:*:* | hppa64:Linux:*:*)
+ echo hppa64-unknown-linux-${LIBC}
exit ;;
parisc:Linux:*:* | hppa:Linux:*:*)
# Look for CPU level
case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in
- PA7*) echo hppa1.1-unknown-linux-gnu ;;
- PA8*) echo hppa2.0-unknown-linux-gnu ;;
- *) echo hppa-unknown-linux-gnu ;;
+ PA7*) echo hppa1.1-unknown-linux-${LIBC} ;;
+ PA8*) echo hppa2.0-unknown-linux-${LIBC} ;;
+ *) echo hppa-unknown-linux-${LIBC} ;;
esac
exit ;;
- parisc64:Linux:*:* | hppa64:Linux:*:*)
- echo hppa64-unknown-linux-gnu
+ ppc64:Linux:*:*)
+ echo powerpc64-unknown-linux-${LIBC}
+ exit ;;
+ ppc:Linux:*:*)
+ echo powerpc-unknown-linux-${LIBC}
+ exit ;;
+ ppc64le:Linux:*:*)
+ echo powerpc64le-unknown-linux-${LIBC}
+ exit ;;
+ ppcle:Linux:*:*)
+ echo powerpcle-unknown-linux-${LIBC}
exit ;;
s390:Linux:*:* | s390x:Linux:*:*)
- echo ${UNAME_MACHINE}-ibm-linux
+ echo ${UNAME_MACHINE}-ibm-linux-${LIBC}
exit ;;
sh64*:Linux:*:*)
- echo ${UNAME_MACHINE}-unknown-linux-gnu
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
exit ;;
sh*:Linux:*:*)
- echo ${UNAME_MACHINE}-unknown-linux-gnu
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
exit ;;
sparc:Linux:*:* | sparc64:Linux:*:*)
- echo ${UNAME_MACHINE}-unknown-linux-gnu
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+ exit ;;
+ tile*:Linux:*:*)
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
exit ;;
vax:Linux:*:*)
- echo ${UNAME_MACHINE}-dec-linux-gnu
+ echo ${UNAME_MACHINE}-dec-linux-${LIBC}
exit ;;
x86_64:Linux:*:*)
- echo x86_64-unknown-linux-gnu
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+ exit ;;
+ xtensa*:Linux:*:*)
+ echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
exit ;;
- i*86:Linux:*:*)
- # The BFD linker knows what the default object file format is, so
- # first see if it will tell us. cd to the root directory to prevent
- # problems with other programs or directories called `ld' in the path.
- # Set LC_ALL=C to ensure ld outputs messages in English.
- ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \
- | sed -ne '/supported targets:/!d
- s/[ ][ ]*/ /g
- s/.*supported targets: *//
- s/ .*//
- p'`
- case "$ld_supported_targets" in
- elf32-i386)
- TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu"
- ;;
- a.out-i386-linux)
- echo "${UNAME_MACHINE}-pc-linux-gnuaout"
- exit ;;
- coff-i386)
- echo "${UNAME_MACHINE}-pc-linux-gnucoff"
- exit ;;
- "")
- # Either a pre-BFD a.out linker (linux-gnuoldld) or
- # one that does not give us useful --help.
- echo "${UNAME_MACHINE}-pc-linux-gnuoldld"
- exit ;;
- esac
- # Determine whether the default compiler is a.out or elf
- eval $set_cc_for_build
- sed 's/^ //' << EOF >$dummy.c
- #include
- #ifdef __ELF__
- # ifdef __GLIBC__
- # if __GLIBC__ >= 2
- LIBC=gnu
- # else
- LIBC=gnulibc1
- # endif
- # else
- LIBC=gnulibc1
- # endif
- #else
- #if defined(__INTEL_COMPILER) || defined(__PGI) || defined(__SUNPRO_C) || defined(__SUNPRO_CC)
- LIBC=gnu
- #else
- LIBC=gnuaout
- #endif
- #endif
- #ifdef __dietlibc__
- LIBC=dietlibc
- #endif
-EOF
- eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n '
- /^LIBC/{
- s: ::g
- p
- }'`"
- test x"${LIBC}" != x && {
- echo "${UNAME_MACHINE}-pc-linux-${LIBC}"
- exit
- }
- test x"${TENTATIVE}" != x && { echo "${TENTATIVE}"; exit; }
- ;;
i*86:DYNIX/ptx:4*:*)
# ptx 4.0 does uname -s correctly, with DYNIX/ptx in there.
# earlier versions are messed up and put the nodename in both
@@ -1020,11 +1032,11 @@
echo i386-sequent-sysv4
exit ;;
i*86:UNIX_SV:4.2MP:2.*)
- # Unixware is an offshoot of SVR4, but it has its own version
- # number series starting with 2...
- # I am not positive that other SVR4 systems won't match this,
+ # Unixware is an offshoot of SVR4, but it has its own version
+ # number series starting with 2...
+ # I am not positive that other SVR4 systems won't match this,
# I just have to hope. -- rms.
- # Use sysv4.2uw... so that sysv4* matches it.
+ # Use sysv4.2uw... so that sysv4* matches it.
echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION}
exit ;;
i*86:OS/2:*:*)
@@ -1041,7 +1053,7 @@
i*86:syllable:*:*)
echo ${UNAME_MACHINE}-pc-syllable
exit ;;
- i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*)
+ i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.[02]*:*)
echo i386-unknown-lynxos${UNAME_RELEASE}
exit ;;
i*86:*DOS:*:*)
@@ -1056,7 +1068,7 @@
fi
exit ;;
i*86:*:5:[678]*)
- # UnixWare 7.x, OpenUNIX and OpenServer 6.
+ # UnixWare 7.x, OpenUNIX and OpenServer 6.
case `/bin/uname -X | grep "^Machine"` in
*486*) UNAME_MACHINE=i486 ;;
*Pentium) UNAME_MACHINE=i586 ;;
@@ -1084,10 +1096,13 @@
exit ;;
pc:*:*:*)
# Left here for compatibility:
- # uname -m prints for DJGPP always 'pc', but it prints nothing about
- # the processor, so we play safe by assuming i386.
- echo i386-pc-msdosdjgpp
- exit ;;
+ # uname -m prints for DJGPP always 'pc', but it prints nothing about
+ # the processor, so we play safe by assuming i586.
+ # Note: whatever this is, it MUST be the same as what config.sub
+ # prints for the "djgpp" host, or else GDB configury will decide that
+ # this is a cross-build.
+ echo i586-pc-msdosdjgpp
+ exit ;;
Intel:Mach:3*:*)
echo i386-pc-mach3
exit ;;
@@ -1122,8 +1137,18 @@
/bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \
&& { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;;
3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*)
- /bin/uname -p 2>/dev/null | grep 86 >/dev/null \
- && { echo i486-ncr-sysv4; exit; } ;;
+ /bin/uname -p 2>/dev/null | grep 86 >/dev/null \
+ && { echo i486-ncr-sysv4; exit; } ;;
+ NCR*:*:4.2:* | MPRAS*:*:4.2:*)
+ OS_REL='.3'
+ test -r /etc/.relid \
+ && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid`
+ /bin/uname -p 2>/dev/null | grep 86 >/dev/null \
+ && { echo i486-ncr-sysv4.3${OS_REL}; exit; }
+ /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \
+ && { echo i586-ncr-sysv4.3${OS_REL}; exit; }
+ /bin/uname -p 2>/dev/null | /bin/grep pteron >/dev/null \
+ && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;;
m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*)
echo m68k-unknown-lynxos${UNAME_RELEASE}
exit ;;
@@ -1136,7 +1161,7 @@
rs6000:LynxOS:2.*:*)
echo rs6000-unknown-lynxos${UNAME_RELEASE}
exit ;;
- PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*)
+ PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.[02]*:*)
echo powerpc-unknown-lynxos${UNAME_RELEASE}
exit ;;
SM[BE]S:UNIX_SV:*:*)
@@ -1156,10 +1181,10 @@
echo ns32k-sni-sysv
fi
exit ;;
- PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort
- # says
- echo i586-unisys-sysv4
- exit ;;
+ PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort
+ # says
+ echo i586-unisys-sysv4
+ exit ;;
*:UNIX_System_V:4*:FTX*)
# From Gerald Hewes .
# How about differentiating between stratus architectures? -djm
@@ -1185,11 +1210,11 @@
exit ;;
R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*)
if [ -d /usr/nec ]; then
- echo mips-nec-sysv${UNAME_RELEASE}
+ echo mips-nec-sysv${UNAME_RELEASE}
else
- echo mips-unknown-sysv${UNAME_RELEASE}
+ echo mips-unknown-sysv${UNAME_RELEASE}
fi
- exit ;;
+ exit ;;
BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only.
echo powerpc-be-beos
exit ;;
@@ -1199,6 +1224,12 @@
BePC:BeOS:*:*) # BeOS running on Intel PC compatible.
echo i586-pc-beos
exit ;;
+ BePC:Haiku:*:*) # Haiku running on Intel PC compatible.
+ echo i586-pc-haiku
+ exit ;;
+ x86_64:Haiku:*:*)
+ echo x86_64-unknown-haiku
+ exit ;;
SX-4:SUPER-UX:*:*)
echo sx4-nec-superux${UNAME_RELEASE}
exit ;;
@@ -1208,6 +1239,15 @@
SX-6:SUPER-UX:*:*)
echo sx6-nec-superux${UNAME_RELEASE}
exit ;;
+ SX-7:SUPER-UX:*:*)
+ echo sx7-nec-superux${UNAME_RELEASE}
+ exit ;;
+ SX-8:SUPER-UX:*:*)
+ echo sx8-nec-superux${UNAME_RELEASE}
+ exit ;;
+ SX-8R:SUPER-UX:*:*)
+ echo sx8r-nec-superux${UNAME_RELEASE}
+ exit ;;
Power*:Rhapsody:*:*)
echo powerpc-apple-rhapsody${UNAME_RELEASE}
exit ;;
@@ -1216,9 +1256,31 @@
exit ;;
*:Darwin:*:*)
UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown
- case $UNAME_PROCESSOR in
- unknown) UNAME_PROCESSOR=powerpc ;;
- esac
+ eval $set_cc_for_build
+ if test "$UNAME_PROCESSOR" = unknown ; then
+ UNAME_PROCESSOR=powerpc
+ fi
+ if test `echo "$UNAME_RELEASE" | sed -e 's/\..*//'` -le 10 ; then
+ if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then
+ if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \
+ (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \
+ grep IS_64BIT_ARCH >/dev/null
+ then
+ case $UNAME_PROCESSOR in
+ i386) UNAME_PROCESSOR=x86_64 ;;
+ powerpc) UNAME_PROCESSOR=powerpc64 ;;
+ esac
+ fi
+ fi
+ elif test "$UNAME_PROCESSOR" = i386 ; then
+ # Avoid executing cc on OS X 10.9, as it ships with a stub
+ # that puts up a graphical alert prompting to install
+ # developer tools. Any system running Mac OS X 10.7 or
+ # later (Darwin 11 and later) is required to have a 64-bit
+ # processor. This is not true of the ARM version of Darwin
+ # that Apple uses in portable devices.
+ UNAME_PROCESSOR=x86_64
+ fi
echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE}
exit ;;
*:procnto*:*:* | *:QNX:[0123456789]*:*)
@@ -1232,7 +1294,10 @@
*:QNX:*:4*)
echo i386-pc-qnx
exit ;;
- NSE-?:NONSTOP_KERNEL:*:*)
+ NEO-?:NONSTOP_KERNEL:*:*)
+ echo neo-tandem-nsk${UNAME_RELEASE}
+ exit ;;
+ NSE-*:NONSTOP_KERNEL:*:*)
echo nse-tandem-nsk${UNAME_RELEASE}
exit ;;
NSR-?:NONSTOP_KERNEL:*:*)
@@ -1277,13 +1342,13 @@
echo pdp10-unknown-its
exit ;;
SEI:*:*:SEIUX)
- echo mips-sei-seiux${UNAME_RELEASE}
+ echo mips-sei-seiux${UNAME_RELEASE}
exit ;;
*:DragonFly:*:*)
echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`
exit ;;
*:*VMS:*:*)
- UNAME_MACHINE=`(uname -p) 2>/dev/null`
+ UNAME_MACHINE=`(uname -p) 2>/dev/null`
case "${UNAME_MACHINE}" in
A*) echo alpha-dec-vms ; exit ;;
I*) echo ia64-dec-vms ; exit ;;
@@ -1298,158 +1363,13 @@
i*86:rdos:*:*)
echo ${UNAME_MACHINE}-pc-rdos
exit ;;
-esac
-
-#echo '(No uname command or uname output not recognized.)' 1>&2
-#echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2
-
-eval $set_cc_for_build
-cat >$dummy.c <
-# include
-#endif
-main ()
-{
-#if defined (sony)
-#if defined (MIPSEB)
- /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed,
- I don't know.... */
- printf ("mips-sony-bsd\n"); exit (0);
-#else
-#include
- printf ("m68k-sony-newsos%s\n",
-#ifdef NEWSOS4
- "4"
-#else
- ""
-#endif
- ); exit (0);
-#endif
-#endif
-
-#if defined (__arm) && defined (__acorn) && defined (__unix)
- printf ("arm-acorn-riscix\n"); exit (0);
-#endif
-
-#if defined (hp300) && !defined (hpux)
- printf ("m68k-hp-bsd\n"); exit (0);
-#endif
-
-#if defined (NeXT)
-#if !defined (__ARCHITECTURE__)
-#define __ARCHITECTURE__ "m68k"
-#endif
- int version;
- version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`;
- if (version < 4)
- printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version);
- else
- printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version);
- exit (0);
-#endif
-
-#if defined (MULTIMAX) || defined (n16)
-#if defined (UMAXV)
- printf ("ns32k-encore-sysv\n"); exit (0);
-#else
-#if defined (CMU)
- printf ("ns32k-encore-mach\n"); exit (0);
-#else
- printf ("ns32k-encore-bsd\n"); exit (0);
-#endif
-#endif
-#endif
-
-#if defined (__386BSD__)
- printf ("i386-pc-bsd\n"); exit (0);
-#endif
-
-#if defined (sequent)
-#if defined (i386)
- printf ("i386-sequent-dynix\n"); exit (0);
-#endif
-#if defined (ns32000)
- printf ("ns32k-sequent-dynix\n"); exit (0);
-#endif
-#endif
-
-#if defined (_SEQUENT_)
- struct utsname un;
-
- uname(&un);
-
- if (strncmp(un.version, "V2", 2) == 0) {
- printf ("i386-sequent-ptx2\n"); exit (0);
- }
- if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */
- printf ("i386-sequent-ptx1\n"); exit (0);
- }
- printf ("i386-sequent-ptx\n"); exit (0);
-
-#endif
-
-#if defined (vax)
-# if !defined (ultrix)
-# include
-# if defined (BSD)
-# if BSD == 43
- printf ("vax-dec-bsd4.3\n"); exit (0);
-# else
-# if BSD == 199006
- printf ("vax-dec-bsd4.3reno\n"); exit (0);
-# else
- printf ("vax-dec-bsd\n"); exit (0);
-# endif
-# endif
-# else
- printf ("vax-dec-bsd\n"); exit (0);
-# endif
-# else
- printf ("vax-dec-ultrix\n"); exit (0);
-# endif
-#endif
-
-#if defined (alliant) && defined (i860)
- printf ("i860-alliant-bsd\n"); exit (0);
-#endif
-
- exit (1);
-}
-EOF
-
-$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` &&
- { echo "$SYSTEM_NAME"; exit; }
-
-# Apollos put the system type in the environment.
-
-test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; }
-
-# Convex versions that predate uname can use getsysinfo(1)
-
-if [ -x /usr/convex/getsysinfo ]
-then
- case `getsysinfo -f cpu_type` in
- c1*)
- echo c1-convex-bsd
+ i*86:AROS:*:*)
+ echo ${UNAME_MACHINE}-pc-aros
exit ;;
- c2*)
- if getsysinfo -f scalar_acc
- then echo c32-convex-bsd
- else echo c2-convex-bsd
- fi
- exit ;;
- c34*)
- echo c34-convex-bsd
+ x86_64:VMkernel:*:*)
+ echo ${UNAME_MACHINE}-unknown-esx
exit ;;
- c38*)
- echo c38-convex-bsd
- exit ;;
- c4*)
- echo c4-convex-bsd
- exit ;;
- esac
-fi
+esac
cat >&2 </dev/null`; do \
dir=`echo $$i | sed -e 's/;.*$$//'`; \
@@ -581,8 +586,13 @@
true; \
else \
lib=`${PWD_COMMAND} | sed -e 's,^.*/\([^/][^/]*\)$$,\1,'`; \
- for dir in Makefile $(MULTIDIRS); do \
- if [ -f ../$${dir}/$${lib}/Makefile ]; then \
+ for dir in : $(MULTIDIRS); do \
+ test $$dir != : || continue; \
+EOF
+cat >>Multi.tem <>Multi.tem <<\EOF
if (cd ../$${dir}/$${lib}; $(MAKE) $(FLAGS_TO_PASS) $(DO)); \
then true; \
else exit 1; \
@@ -600,7 +610,7 @@
fi # ${ml_toplevel_p} = yes
if [ "${ml_verbose}" = --verbose ]; then
- echo "Adding multilib support to Makefile in ${ml_realsrcdir}"
+ echo "Adding multilib support to ${Makefile} in ${ml_realsrcdir}"
if [ "${ml_toplevel_p}" = yes ]; then
echo "multidirs=${multidirs}"
fi
@@ -691,7 +701,7 @@
fi
ml_origdir=`${PWDCMD-pwd}`
- ml_libdir=`echo $ml_origdir | sed -e 's,^.*/,,'`
+ ml_libdir=`echo "$ml_origdir" | sed -e 's,^.*/,,'`
# cd to top-level-build-dir/${with_target_subdir}
cd ..
@@ -727,7 +737,7 @@
case ${srcdir} in
".")
- echo Building symlink tree in `${PWDCMD-pwd}`/${ml_dir}/${ml_libdir}
+ echo "Building symlink tree in `${PWDCMD-pwd}`/${ml_dir}/${ml_libdir}"
if [ "${with_target_subdir}" != "." ]; then
ml_unsubdir="../"
else
@@ -735,7 +745,7 @@
fi
(cd ${ml_dir}/${ml_libdir};
../${dotdot}${ml_unsubdir}symlink-tree ../${dotdot}${ml_unsubdir}${ml_libdir} "")
- if [ -f ${ml_dir}/${ml_libdir}/Makefile ]; then
+ if [ -f ${ml_dir}/${ml_libdir}/${Makefile} ]; then
if [ x"${MAKE}" = x ]; then
(cd ${ml_dir}/${ml_libdir}; make distclean)
else
@@ -792,7 +802,7 @@
else
# Create a regular expression that matches any string as long
# as ML_POPDIR.
- popdir_rx=`echo ${ML_POPDIR} | sed 's,.,.,g'`
+ popdir_rx=`echo "${ML_POPDIR}" | sed 's,.,.,g'`
CC_=
for arg in ${CC}; do
case $arg in
@@ -890,17 +900,17 @@
if eval ${ml_config_env} ${ml_config_shell} ${ml_recprog} \
--with-multisubdir=${ml_dir} --with-multisrctop=${multisrctop} \
- ${ac_configure_args} ${ml_srcdiroption} ; then
+ ${ac_configure_args} ${ml_config_env} ${ml_srcdiroption} ; then
true
else
exit 1
fi
- cd ${ML_POPDIR}
+ cd "${ML_POPDIR}"
done
- cd ${ml_origdir}
+ cd "${ml_origdir}"
fi
fi # ${ml_toplevel_p} = yes
diff -Nur gcc-4.2.4.orig/config.sub gcc-4.2.4/config.sub
--- gcc-4.2.4.orig/config.sub 2006-10-15 22:27:17.000000000 -0500
+++ gcc-4.2.4/config.sub 2015-07-03 19:15:14.097267674 -0500
@@ -1,44 +1,40 @@
#! /bin/sh
# Configuration validation subroutine script.
-# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-# 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
-# Inc.
-
-timestamp='2006-09-20'
-
-# This file is (in principle) common to ALL GNU software.
-# The presence of a machine in this file suggests that SOME GNU software
-# can handle that machine. It does not imply ALL GNU software can.
-#
-# This file is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
+# Copyright 1992-2014 Free Software Foundation, Inc.
+
+timestamp='2014-09-26'
+
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
#
# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
-# 02110-1301, USA.
+# along with this program; if not, see .
#
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
# configuration script generated by Autoconf, you may include it under
-# the same distribution terms that you use for the rest of that program.
+# the same distribution terms that you use for the rest of that
+# program. This Exception is an additional permission under section 7
+# of the GNU General Public License, version 3 ("GPLv3").
-# Please send patches to . Submit a context
-# diff and a properly formatted ChangeLog entry.
+# Please send patches with a ChangeLog entry to config-patches@gnu.org.
#
# Configuration subroutine to validate and canonicalize a configuration type.
# Supply the specified configuration type as an argument.
# If it is invalid, we print an error message on stderr and exit with code 1.
# Otherwise, we print the canonical config type on stdout and succeed.
+# You can get the latest version of this script from:
+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD
+
# This file is supposed to be the same for all GNU packages
# and recognize all the CPU types, system types and aliases
# that are meaningful with *any* GNU software.
@@ -72,8 +68,7 @@
version="\
GNU config.sub ($timestamp)
-Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
-Free Software Foundation, Inc.
+Copyright 1992-2014 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
@@ -120,12 +115,18 @@
# Here we must recognize all the valid KERNEL-OS combinations.
maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'`
case $maybe_os in
- nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \
- uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \
+ nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \
+ linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \
+ knetbsd*-gnu* | netbsd*-gnu* | \
+ kopensolaris*-gnu* | \
storm-chaos* | os2-emx* | rtmk-nova*)
os=-$maybe_os
basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`
;;
+ android-linux)
+ os=-linux-android
+ basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`-unknown
+ ;;
*)
basic_machine=`echo $1 | sed 's/-[^-]*$//'`
if [ $basic_machine != $1 ]
@@ -148,10 +149,13 @@
-convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\
-c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \
-harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \
- -apple | -axis | -knuth | -cray)
+ -apple | -axis | -knuth | -cray | -microblaze*)
os=
basic_machine=$1
;;
+ -bluegene*)
+ os=-cnk
+ ;;
-sim | -cisco | -oki | -wec | -winbond)
os=
basic_machine=$1
@@ -166,10 +170,10 @@
os=-chorusos
basic_machine=$1
;;
- -chorusrdb)
- os=-chorusrdb
+ -chorusrdb)
+ os=-chorusrdb
basic_machine=$1
- ;;
+ ;;
-hiux*)
os=-hiuxwe2
;;
@@ -214,6 +218,12 @@
-isc*)
basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
;;
+ -lynx*178)
+ os=-lynxos178
+ ;;
+ -lynx*5)
+ os=-lynxos5
+ ;;
-lynx*)
os=-lynxos
;;
@@ -238,59 +248,89 @@
# Some are omitted here because they have special meanings below.
1750a | 580 \
| a29k \
+ | aarch64 | aarch64_be \
| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \
| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \
| am33_2.0 \
- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \
+ | arc | arceb \
+ | arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \
+ | avr | avr32 \
+ | be32 | be64 \
| bfin \
- | c4x | clipper \
+ | c4x | c8051 | clipper \
| d10v | d30v | dlx | dsp16xx \
- | fr30 | frv \
+ | epiphany \
+ | fido | fr30 | frv \
| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
+ | hexagon \
| i370 | i860 | i960 | ia64 \
| ip2k | iq2000 \
+ | k1om \
+ | le32 | le64 \
+ | lm32 \
| m32c | m32r | m32rle | m68000 | m68k | m88k \
- | maxq | mb | microblaze | mcore \
+ | maxq | mb | microblaze | microblazeel | mcore | mep | metag \
| mips | mipsbe | mipseb | mipsel | mipsle \
| mips16 \
| mips64 | mips64el \
- | mips64vr | mips64vrel \
+ | mips64octeon | mips64octeonel \
| mips64orion | mips64orionel \
+ | mips64r5900 | mips64r5900el \
+ | mips64vr | mips64vrel \
| mips64vr4100 | mips64vr4100el \
| mips64vr4300 | mips64vr4300el \
| mips64vr5000 | mips64vr5000el \
| mips64vr5900 | mips64vr5900el \
| mipsisa32 | mipsisa32el \
| mipsisa32r2 | mipsisa32r2el \
+ | mipsisa32r6 | mipsisa32r6el \
| mipsisa64 | mipsisa64el \
| mipsisa64r2 | mipsisa64r2el \
+ | mipsisa64r6 | mipsisa64r6el \
| mipsisa64sb1 | mipsisa64sb1el \
| mipsisa64sr71k | mipsisa64sr71kel \
+ | mipsr5900 | mipsr5900el \
| mipstx39 | mipstx39el \
| mn10200 | mn10300 \
+ | moxie \
| mt \
| msp430 \
- | nios | nios2 \
+ | nds32 | nds32le | nds32be \
+ | nios | nios2 | nios2eb | nios2el \
| ns16k | ns32k \
- | or32 \
+ | open8 | or1k | or1knd | or32 \
| pdp10 | pdp11 | pj | pjl \
- | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \
+ | powerpc | powerpc64 | powerpc64le | powerpcle \
| pyramid \
+ | riscv32 | riscv64 \
+ | rl78 | rx \
| score \
- | sh | sh[1234] | sh[24]a | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
+ | sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
| sh64 | sh64le \
| sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \
| sparcv8 | sparcv9 | sparcv9b | sparcv9v \
- | spu | strongarm \
- | tahoe | thumb | tic4x | tic80 | tron \
- | v850 | v850e \
+ | spu \
+ | tahoe | tic4x | tic54x | tic55x | tic6x | tic80 | tron \
+ | ubicom32 \
+ | v850 | v850e | v850e1 | v850e2 | v850es | v850e2v3 \
| we32k \
- | x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \
- | z8k)
+ | x86 | xc16x | xstormy16 | xtensa \
+ | z8k | z80)
basic_machine=$basic_machine-unknown
;;
- m6811 | m68hc11 | m6812 | m68hc12)
- # Motorola 68HC11/12.
+ c54x)
+ basic_machine=tic54x-unknown
+ ;;
+ c55x)
+ basic_machine=tic55x-unknown
+ ;;
+ c6x)
+ basic_machine=tic6x-unknown
+ ;;
+ leon|leon[3-9])
+ basic_machine=sparc-$basic_machine
+ ;;
+ m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip)
basic_machine=$basic_machine-unknown
os=-none
;;
@@ -300,6 +340,21 @@
basic_machine=mt-unknown
;;
+ strongarm | thumb | xscale)
+ basic_machine=arm-unknown
+ ;;
+ xgate)
+ basic_machine=$basic_machine-unknown
+ os=-none
+ ;;
+ xscaleeb)
+ basic_machine=armeb-unknown
+ ;;
+
+ xscaleel)
+ basic_machine=armel-unknown
+ ;;
+
# We use `pc' rather than `unknown'
# because (1) that's what they normally are, and
# (2) the word "unknown" tends to confuse beginning users.
@@ -314,64 +369,86 @@
# Recognize the basic CPU types with company name.
580-* \
| a29k-* \
+ | aarch64-* | aarch64_be-* \
| alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \
| alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \
- | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \
+ | alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \
| arm-* | armbe-* | armle-* | armeb-* | armv*-* \
| avr-* | avr32-* \
+ | be32-* | be64-* \
| bfin-* | bs2000-* \
- | c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \
- | clipper-* | craynv-* | cydra-* \
+ | c[123]* | c30-* | [cjt]90-* | c4x-* \
+ | c8051-* | clipper-* | craynv-* | cydra-* \
| d10v-* | d30v-* | dlx-* \
| elxsi-* \
- | f30[01]-* | f700-* | fr30-* | frv-* | fx80-* \
+ | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \
| h8300-* | h8500-* \
| hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \
+ | hexagon-* \
| i*86-* | i860-* | i960-* | ia64-* \
| ip2k-* | iq2000-* \
+ | k1om-* \
+ | le32-* | le64-* \
+ | lm32-* \
| m32c-* | m32r-* | m32rle-* \
| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
- | m88110-* | m88k-* | maxq-* | mcore-* \
+ | m88110-* | m88k-* | maxq-* | mcore-* | metag-* \
+ | microblaze-* | microblazeel-* \
| mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
| mips16-* \
| mips64-* | mips64el-* \
- | mips64vr-* | mips64vrel-* \
+ | mips64octeon-* | mips64octeonel-* \
| mips64orion-* | mips64orionel-* \
+ | mips64r5900-* | mips64r5900el-* \
+ | mips64vr-* | mips64vrel-* \
| mips64vr4100-* | mips64vr4100el-* \
| mips64vr4300-* | mips64vr4300el-* \
| mips64vr5000-* | mips64vr5000el-* \
| mips64vr5900-* | mips64vr5900el-* \
| mipsisa32-* | mipsisa32el-* \
| mipsisa32r2-* | mipsisa32r2el-* \
+ | mipsisa32r6-* | mipsisa32r6el-* \
| mipsisa64-* | mipsisa64el-* \
| mipsisa64r2-* | mipsisa64r2el-* \
+ | mipsisa64r6-* | mipsisa64r6el-* \
| mipsisa64sb1-* | mipsisa64sb1el-* \
| mipsisa64sr71k-* | mipsisa64sr71kel-* \
+ | mipsr5900-* | mipsr5900el-* \
| mipstx39-* | mipstx39el-* \
| mmix-* \
| mt-* \
| msp430-* \
- | nios-* | nios2-* \
+ | nds32-* | nds32le-* | nds32be-* \
+ | nios-* | nios2-* | nios2eb-* | nios2el-* \
| none-* | np1-* | ns16k-* | ns32k-* \
+ | open8-* \
+ | or1k*-* \
| orion-* \
| pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \
- | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \
+ | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \
| pyramid-* \
- | romp-* | rs6000-* \
- | sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
+ | rl78-* | romp-* | rs6000-* | rx-* \
+ | sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
| shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
| sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \
| sparclite-* \
- | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \
- | tahoe-* | thumb-* \
+ | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx?-* \
+ | tahoe-* \
| tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \
+ | tile*-* \
| tron-* \
- | v850-* | v850e-* | vax-* \
+ | ubicom32-* \
+ | v850-* | v850e-* | v850e1-* | v850es-* | v850e2-* | v850e2v3-* \
+ | vax-* \
| we32k-* \
- | x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \
- | xstormy16-* | xtensa-* \
+ | x86-* | x86_64-* | xc16x-* | xps100-* \
+ | xstormy16-* | xtensa*-* \
| ymp-* \
- | z8k-*)
+ | z8k-* | z80-*)
+ ;;
+ # Recognize the basic CPU types without company name, with glob match.
+ xtensa*)
+ basic_machine=$basic_machine-unknown
;;
# Recognize the various machine names and aliases which stand
# for a CPU type and a company and sometimes even an OS.
@@ -389,7 +466,7 @@
basic_machine=a29k-amd
os=-udi
;;
- abacus)
+ abacus)
basic_machine=abacus-unknown
;;
adobe68k)
@@ -435,6 +512,10 @@
basic_machine=m68k-apollo
os=-bsd
;;
+ aros)
+ basic_machine=i386-pc
+ os=-aros
+ ;;
aux)
basic_machine=m68k-apple
os=-aux
@@ -443,10 +524,35 @@
basic_machine=ns32k-sequent
os=-dynix
;;
+ blackfin)
+ basic_machine=bfin-unknown
+ os=-linux
+ ;;
+ blackfin-*)
+ basic_machine=bfin-`echo $basic_machine | sed 's/^[^-]*-//'`
+ os=-linux
+ ;;
+ bluegene*)
+ basic_machine=powerpc-ibm
+ os=-cnk
+ ;;
+ c54x-*)
+ basic_machine=tic54x-`echo $basic_machine | sed 's/^[^-]*-//'`
+ ;;
+ c55x-*)
+ basic_machine=tic55x-`echo $basic_machine | sed 's/^[^-]*-//'`
+ ;;
+ c6x-*)
+ basic_machine=tic6x-`echo $basic_machine | sed 's/^[^-]*-//'`
+ ;;
c90)
basic_machine=c90-cray
os=-unicos
;;
+ cegcc)
+ basic_machine=arm-unknown
+ os=-cegcc
+ ;;
convex-c1)
basic_machine=c1-convex
os=-bsd
@@ -475,8 +581,8 @@
basic_machine=craynv-cray
os=-unicosmp
;;
- cr16c)
- basic_machine=cr16c-unknown
+ cr16 | cr16-*)
+ basic_machine=cr16-unknown
os=-elf
;;
crds | unos)
@@ -514,6 +620,10 @@
basic_machine=m88k-motorola
os=-sysv3
;;
+ dicos)
+ basic_machine=i686-pc
+ os=-dicos
+ ;;
djgpp)
basic_machine=i586-pc
os=-msdosdjgpp
@@ -629,7 +739,6 @@
i370-ibm* | ibm*)
basic_machine=i370-ibm
;;
-# I'm not sure what "Sysv32" means. Should this be sysv3.2?
i*86v32)
basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
os=-sysv32
@@ -668,6 +777,17 @@
basic_machine=m68k-isi
os=-sysv
;;
+ leon-*|leon[3-9]-*)
+ basic_machine=sparc-`echo $basic_machine | sed 's/-.*//'`
+ ;;
+ m68knommu)
+ basic_machine=m68k-unknown
+ os=-linux
+ ;;
+ m68knommu-*)
+ basic_machine=m68k-`echo $basic_machine | sed 's/^[^-]*-//'`
+ os=-linux
+ ;;
m88k-omron*)
basic_machine=m88k-omron
;;
@@ -679,10 +799,21 @@
basic_machine=ns32k-utek
os=-sysv
;;
+ microblaze*)
+ basic_machine=microblaze-xilinx
+ ;;
+ mingw64)
+ basic_machine=x86_64-pc
+ os=-mingw64
+ ;;
mingw32)
- basic_machine=i386-pc
+ basic_machine=i686-pc
os=-mingw32
;;
+ mingw32ce)
+ basic_machine=arm-unknown
+ os=-mingw32ce
+ ;;
miniframe)
basic_machine=m68000-convergent
;;
@@ -704,6 +835,10 @@
basic_machine=powerpc-unknown
os=-morphos
;;
+ moxiebox)
+ basic_machine=moxie-unknown
+ os=-moxiebox
+ ;;
msdos)
basic_machine=i386-pc
os=-msdos
@@ -711,10 +846,18 @@
ms1-*)
basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'`
;;
+ msys)
+ basic_machine=i686-pc
+ os=-msys
+ ;;
mvs)
basic_machine=i370-ibm
os=-mvs
;;
+ nacl)
+ basic_machine=le32-unknown
+ os=-nacl
+ ;;
ncr3000)
basic_machine=i486-ncr
os=-sysv4
@@ -779,6 +922,12 @@
np1)
basic_machine=np1-gould
;;
+ neo-tandem)
+ basic_machine=neo-tandem
+ ;;
+ nse-tandem)
+ basic_machine=nse-tandem
+ ;;
nsr-tandem)
basic_machine=nsr-tandem
;;
@@ -809,6 +958,14 @@
basic_machine=i860-intel
os=-osf
;;
+ parisc)
+ basic_machine=hppa-unknown
+ os=-linux
+ ;;
+ parisc-*)
+ basic_machine=hppa-`echo $basic_machine | sed 's/^[^-]*-//'`
+ os=-linux
+ ;;
pbd)
basic_machine=sparc-tti
;;
@@ -853,9 +1010,10 @@
;;
power) basic_machine=power-ibm
;;
- ppc) basic_machine=powerpc-unknown
+ ppc | ppcbe) basic_machine=powerpc-unknown
;;
- ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'`
+ ppc-* | ppcbe-*)
+ basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'`
;;
ppcle | powerpclittle | ppc-le | powerpc-little)
basic_machine=powerpcle-unknown
@@ -880,7 +1038,11 @@
basic_machine=i586-unknown
os=-pw32
;;
- rdos)
+ rdos | rdos64)
+ basic_machine=x86_64-pc
+ os=-rdos
+ ;;
+ rdos32)
basic_machine=i386-pc
os=-rdos
;;
@@ -925,6 +1087,9 @@
basic_machine=sh-hitachi
os=-hms
;;
+ sh5el)
+ basic_machine=sh5le-unknown
+ ;;
sh64)
basic_machine=sh64-unknown
;;
@@ -946,6 +1111,9 @@
basic_machine=i860-stratus
os=-sysv4
;;
+ strongarm-* | thumb-*)
+ basic_machine=arm-`echo $basic_machine | sed 's/^[^-]*-//'`
+ ;;
sun2)
basic_machine=m68000-sun
;;
@@ -1002,17 +1170,9 @@
basic_machine=t90-cray
os=-unicos
;;
- tic54x | c54x*)
- basic_machine=tic54x-unknown
- os=-coff
- ;;
- tic55x | c55x*)
- basic_machine=tic55x-unknown
- os=-coff
- ;;
- tic6x | c6x*)
- basic_machine=tic6x-unknown
- os=-coff
+ tile*)
+ basic_machine=$basic_machine-unknown
+ os=-linux-gnu
;;
tx39)
basic_machine=mipstx39-unknown
@@ -1081,6 +1241,9 @@
xps | xps100)
basic_machine=xps100-honeywell
;;
+ xscale-* | xscalee[bl]-*)
+ basic_machine=`echo $basic_machine | sed 's/^xscale/arm/'`
+ ;;
ymp)
basic_machine=ymp-cray
os=-unicos
@@ -1089,6 +1252,10 @@
basic_machine=z8k-unknown
os=-sim
;;
+ z80-*-coff)
+ basic_machine=z80-unknown
+ os=-sim
+ ;;
none)
basic_machine=none-none
os=-none
@@ -1127,7 +1294,7 @@
we32k)
basic_machine=we32k-att
;;
- sh[1234] | sh[24]a | sh[34]eb | sh[1234]le | sh[23]ele)
+ sh[1234] | sh[24]a | sh[24]aeb | sh[34]eb | sh[1234]le | sh[23]ele)
basic_machine=sh-unknown
;;
sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v)
@@ -1174,9 +1341,12 @@
if [ x"$os" != x"" ]
then
case $os in
- # First match some system type aliases
- # that might get confused with valid system types.
+ # First match some system type aliases
+ # that might get confused with valid system types.
# -solaris* is a basic system type, with this one exception.
+ -auroraux)
+ os=-auroraux
+ ;;
-solaris1 | -solaris1.*)
os=`echo $os | sed -e 's|solaris1|sunos4|'`
;;
@@ -1197,29 +1367,31 @@
# Each alternative MUST END IN A *, to match a version number.
# -sysv* is not here because it comes later, after sysvr4.
-gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \
- | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\
- | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \
+ | -*vms* | -sco* | -esix* | -isc* | -aix* | -cnk* | -sunos | -sunos[34]*\
+ | -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* \
+ | -sym* | -kopensolaris* | -plan9* \
| -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \
- | -aos* \
+ | -aos* | -aros* \
| -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \
| -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \
| -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \
- | -openbsd* | -solidbsd* \
+ | -bitrig* | -openbsd* | -solidbsd* \
| -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \
| -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \
| -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \
| -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \
- | -chorusos* | -chorusrdb* \
- | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
- | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \
- | -uxpv* | -beos* | -mpeix* | -udk* \
+ | -chorusos* | -chorusrdb* | -cegcc* \
+ | -cygwin* | -msys* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
+ | -mingw32* | -mingw64* | -linux-gnu* | -linux-android* \
+ | -linux-newlib* | -linux-musl* | -linux-uclibc* \
+ | -uxpv* | -beos* | -mpeix* | -udk* | -moxiebox* \
| -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \
| -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \
| -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \
| -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \
| -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \
| -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \
- | -skyos* | -haiku* | -rdos* | -toppers*)
+ | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* | -tirtos*)
# Remember, each alternative MUST END IN *, to match a version number.
;;
-qnx*)
@@ -1258,7 +1430,7 @@
-opened*)
os=-openedition
;;
- -os400*)
+ -os400*)
os=-os400
;;
-wince*)
@@ -1307,7 +1479,7 @@
-sinix*)
os=-sysv4
;;
- -tpf*)
+ -tpf*)
os=-tpf
;;
-triton*)
@@ -1343,12 +1515,14 @@
-aros*)
os=-aros
;;
- -kaos*)
- os=-kaos
- ;;
-zvmoe)
os=-zvmoe
;;
+ -dicos*)
+ os=-dicos
+ ;;
+ -nacl*)
+ ;;
-none)
;;
*)
@@ -1371,10 +1545,10 @@
# system, and we'll never get to this point.
case $basic_machine in
- score-*)
+ score-*)
os=-elf
;;
- spu-*)
+ spu-*)
os=-elf
;;
*-acorn)
@@ -1386,8 +1560,23 @@
arm*-semi)
os=-aout
;;
- c4x-* | tic4x-*)
- os=-coff
+ c4x-* | tic4x-*)
+ os=-coff
+ ;;
+ c8051-*)
+ os=-elf
+ ;;
+ hexagon-*)
+ os=-elf
+ ;;
+ tic54x-*)
+ os=-coff
+ ;;
+ tic55x-*)
+ os=-coff
+ ;;
+ tic6x-*)
+ os=-coff
;;
# This must come before the *-dec entry.
pdp10-*)
@@ -1407,13 +1596,13 @@
;;
m68000-sun)
os=-sunos3
- # This also exists in the configure program, but was not the
- # default.
- # os=-sunos4
;;
m68*-cisco)
os=-aout
;;
+ mep-*)
+ os=-elf
+ ;;
mips*-cisco)
os=-elf
;;
@@ -1438,7 +1627,7 @@
*-ibm)
os=-aix
;;
- *-knuth)
+ *-knuth)
os=-mmixware
;;
*-wec)
@@ -1543,7 +1732,7 @@
-sunos*)
vendor=sun
;;
- -aix*)
+ -cnk*|-aix*)
vendor=ibm
;;
-beos*)
diff -Nur gcc-4.2.4.orig/contrib/test_installed gcc-4.2.4/contrib/test_installed
--- gcc-4.2.4.orig/contrib/test_installed 2003-07-11 01:05:01.000000000 -0500
+++ gcc-4.2.4/contrib/test_installed 2015-07-03 18:46:05.717283542 -0500
@@ -107,6 +107,8 @@
set srcdir "${testsuite-${srcdir}/gcc/testsuite}"
set CFLAGS ""
set CXXFLAGS ""
+set HOSTCC "cc"
+set HOSTCFLAGS ""
set GCC_UNDER_TEST "${GCC_UNDER_TEST-${prefix}${prefix+/bin/}gcc}"
set GXX_UNDER_TEST "${GXX_UNDER_TEST-${prefix}${prefix+/bin/}g++}"
set G77_UNDER_TEST "${G77_UNDER_TEST-${prefix}${prefix+/bin/}g77}"
diff -Nur gcc-4.2.4.orig/fixincludes/mkfixinc.sh gcc-4.2.4/fixincludes/mkfixinc.sh
--- gcc-4.2.4.orig/fixincludes/mkfixinc.sh 2004-11-23 16:45:53.000000000 -0600
+++ gcc-4.2.4/fixincludes/mkfixinc.sh 2015-07-03 18:46:05.717283542 -0500
@@ -23,6 +23,7 @@
i?86-*-mingw32* | \
i?86-*-uwin* | \
i?86-*-interix* | \
+ metag*-linux-uclibc* | \
powerpc-*-eabiaix* | \
powerpc-*-eabisim* | \
powerpc-*-eabi* | \
diff -Nur gcc-4.2.4.orig/gcc/caller-save.c gcc-4.2.4/gcc/caller-save.c
--- gcc-4.2.4.orig/gcc/caller-save.c 2007-09-01 10:28:30.000000000 -0500
+++ gcc-4.2.4/gcc/caller-save.c 2015-07-03 18:46:05.717283542 -0500
@@ -36,6 +36,10 @@
#include "tm_p.h"
#include "addresses.h"
+#ifndef CALLER_SAVE_INSN_CODE
+#define CALLER_SAVE_INSN_CODE(CODE) (CODE)
+#endif
+
#ifndef MAX_MOVE_MAX
#define MAX_MOVE_MAX MOVE_MAX
#endif
@@ -776,7 +780,8 @@
/* Emit a new caller-save insn and set the code. */
static struct insn_chain *
-insert_one_insn (struct insn_chain *chain, int before_p, int code, rtx pat)
+insert_one_insn (struct insn_chain *chain, int before_p,
+ int code ATTRIBUTE_UNUSED, rtx pat)
{
rtx insn = chain->insn;
struct insn_chain *new;
@@ -857,6 +862,6 @@
new->block = chain->block;
new->is_caller_save_insn = 1;
- INSN_CODE (new->insn) = code;
+ INSN_CODE (new->insn) = CALLER_SAVE_INSN_CODE (code);
return new;
}
diff -Nur gcc-4.2.4.orig/gcc/calls.c gcc-4.2.4/gcc/calls.c
--- gcc-4.2.4.orig/gcc/calls.c 2007-09-01 10:28:30.000000000 -0500
+++ gcc-4.2.4/gcc/calls.c 2015-07-03 18:46:05.717283542 -0500
@@ -829,6 +829,7 @@
{
int bytes = int_size_in_bytes (TREE_TYPE (args[i].tree_value));
int endian_correction = 0;
+ rtx value;
if (args[i].partial)
{
@@ -858,10 +859,22 @@
)
endian_correction = BITS_PER_WORD - bytes * BITS_PER_UNIT;
+
+ value = args[i].value;
+
+#if METAG_PARTIAL_ARGS
+ if (args[i].partial)
+ {
+ HOST_WIDE_INT excess = (bytes + (UNITS_PER_WORD - 1)) & ~(UNITS_PER_WORD - 1);
+
+ value = adjust_address (value, GET_MODE (value), excess - args[i].partial);
+ }
+#endif
+
for (j = 0; j < args[i].n_aligned_regs; j++)
{
rtx reg = gen_reg_rtx (word_mode);
- rtx word = operand_subword_force (args[i].value, j, BLKmode);
+ rtx word = operand_subword_force (value, j, BLKmode);
int bitsize = MIN (bytes * BITS_PER_UNIT, BITS_PER_WORD);
args[i].aligned_regs[j] = reg;
diff -Nur gcc-4.2.4.orig/gcc/config/metag/builtins.md gcc-4.2.4/gcc/config/metag/builtins.md
--- gcc-4.2.4.orig/gcc/config/metag/builtins.md 1969-12-31 18:00:00.000000000 -0600
+++ gcc-4.2.4/gcc/config/metag/builtins.md 2015-07-03 18:46:05.741283542 -0500
@@ -0,0 +1,106 @@
+;; Machine description for GNU compiler,
+;; Imagination Technologies Meta version.
+;; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+;; Imagination Technologies Ltd
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it under
+;; the terms of the GNU General Public License as published by the Free
+;; Software Foundation; either version 3, or (at your option) any later
+;; version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+;; for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; .
+
+;;- meta builtins functions
+
+;; "__builtin_dcache_preload" data cache preload
+(define_insn "dcache_preload"
+ [(set (reg:SI RAPF_REG)
+ (unspec_volatile:SI [(match_operand:SI 0 "metag_register_op" "r")] VUNSPEC_DCACHE_PRELOAD))]
+ "TARGET_BUILTINS_METAC_1_1 || TARGET_BUILTINS_METAC_1_2 || TARGET_BUILTINS_METAC_2_1"
+ "MOV\\tRAPF,%0\\t\\t%@ (*prefetch OK)"
+ [(set_attr "type" "fast")])
+
+;; "__builtin_dcache_flush" data cache flush
+(define_insn "dcache_flush"
+ [(unspec_volatile [(match_operand:SI 0 "metag_register_op" "r")
+ (match_operand:SI 1 "metag_register_op" "r")] VUNSPEC_DCACHE)]
+ "TARGET_BUILTINS_METAC_1_2 || TARGET_BUILTINS_METAC_2_1"
+ "DCACHE\\t[%0],%1\\t\\t%@ (*flush OK)"
+ [(set_attr "type" "fast")])
+
+;; "__builtin_dcache_refresh" data cache refresh
+(define_insn "dcache_refresh"
+ [(set (reg:SI RAPF_REG)
+ (unspec_volatile:SI [(match_operand:SI 0 "metag_register_op" "d")
+ (match_operand:SI 1 "metag_register_op" "a")] VUNSPEC_DCACHE_REFRESH))]
+ "TARGET_BUILTINS_METAC_1_1 || TARGET_BUILTINS_METAC_1_2 || TARGET_BUILTINS_METAC_2_1"
+ "*
+{
+ if (TARGET_BUILTINS_METAC_1_1)
+ output_asm_insn (\"SETB\\t[%0],%1\\t\\t%@ (*refresh ...\\n\\tLSL\\tRAPF,%0,#6\\t\\t%@ ... OK)\",
+ operands);
+ else
+ output_asm_insn (\"DCACHE\\t[%0],%1\\t\\t%@ (*refresh ...\\n\\tADD\\tRAPF,%0,#0\\t\\t%@ ... OK)\",
+ operands);
+ return \"\";
+}"
+ [(set_attr "type" "two")])
+
+;; "__builtin_meta2_cacherd"
+(define_insn "meta2_cacherd"
+ [(set (match_operand:SI 0 "metag_register_op" "=r")
+ (unspec_volatile:SI [(match_operand:SI 1 "metag_register_op" "r")] VUNSPEC_META2_CACHERD))]
+ "TARGET_BUILTINS_METAC_2_1"
+ "CACHERD\\t%0,[%1]\\t\\t%@ (*cacherd OK)"
+ [(set_attr "type" "fast")])
+
+;; "__builtin_meta2_cacherl"
+(define_insn "meta2_cacherl"
+ [(set (match_operand:DI 0 "metag_register_op" "=r")
+ (unspec_volatile:DI [(match_operand:SI 1 "metag_register_op" "r")] VUNSPEC_META2_CACHERL))]
+ "TARGET_BUILTINS_METAC_2_1"
+ "CACHERL\\t%0,%t0,[%1]\\t\\t%@ (*cacherl OK)"
+ [(set_attr "type" "fast")])
+
+;; "__builtin_meta2_cachewd"
+(define_insn "meta2_cachewd"
+ [(unspec_volatile [(match_operand:SI 0 "metag_register_op" "r")
+ (match_operand:SI 1 "metag_register_op" "r")] VUNSPEC_META2_CACHEWD)]
+ "TARGET_BUILTINS_METAC_2_1"
+ "CACHEWD\\t[%0],%1\\t\\t%@ (*cachewd OK)"
+ [(set_attr "type" "fast")])
+
+;; "__builtin_meta2_cachewl"
+(define_insn "meta2_cachewl"
+ [(unspec_volatile [(match_operand:SI 0 "metag_register_op" "r")
+ (match_operand:DI 1 "metag_register_op" "r")] VUNSPEC_META2_CACHEWL)]
+ "TARGET_BUILTINS_METAC_2_1"
+ "CACHEWL\\t[%0],%1,%t1\\t\\t%@ (*cachewl OK)"
+ [(set_attr "type" "fast")])
+
+; "__builtin_metag_bswap"
+(define_insn "metag_bswap"
+ [(set (match_operand:SI 0 "metag_register_op" "=e,f")
+ (unspec:SI [(match_operand:SI 1 "metag_register_op" "e,f")] UNSPEC_METAG_BSWAP))]
+ "TARGET_BUILTINS_METAC_2_1 && metag_meta2_bex_enabled"
+ "BEXD\\t%0,%1\\t\\t%@ (*bswap OK)"
+ [(set_attr "type" "fast")])
+
+; "__builtin_metag_bswapll"
+(define_insn "metag_bswapll"
+ [(set (match_operand:DI 0 "metag_register_op" "=d")
+ (unspec:DI [(match_operand:DI 1 "metag_register_op" "d")] UNSPEC_METAG_BSWAPLL))]
+ "TARGET_BUILTINS_METAC_2_1 && metag_meta2_bex_enabled"
+ "BEXL\\t%t0,%1\\t\\t%@ (*bswapll OK)"
+ [(set_attr "type" "fast")])
+
+;; end of file
diff -Nur gcc-4.2.4.orig/gcc/config/metag/combines.md gcc-4.2.4/gcc/config/metag/combines.md
--- gcc-4.2.4.orig/gcc/config/metag/combines.md 1969-12-31 18:00:00.000000000 -0600
+++ gcc-4.2.4/gcc/config/metag/combines.md 2015-07-03 18:46:05.745283542 -0500
@@ -0,0 +1,1052 @@
+;; Machine description for GNU compiler,
+;; Imagination Technologies Meta version.
+;; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010
+;; Imagination Technologies Ltd
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it under
+;; the terms of the GNU General Public License as published by the Free
+;; Software Foundation; either version 3, or (at your option) any later
+;; version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+;; for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; .
+
+;; -----------------------------------------------------------------------------
+;; | Recognising SI/HI/QI store pre-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*sto__pre_inc_dec_modify_disp_split"
+ [(set (mem:MEMOP (plus:SI (match_operand:SI 0 "metag_regnofrm_op" "+efhl")
+ (match_operand:SI 1 "metag_offset6_" "")))
+ (match_operand: 2 "metag_register_op" "r"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_dup 1)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx pre, mem, insn;
+
+ if (INTVAL (operands[1]) == GET_MODE_SIZE (mode))
+ pre = gen_rtx_PRE_INC (SImode, operands[0]);
+ else if (INTVAL (operands[1]) == -GET_MODE_SIZE (mode))
+ pre = gen_rtx_PRE_DEC (SImode, operands[0]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[1]);
+
+ pre = gen_rtx_PRE_MODIFY (SImode, operands[0], plus);
+ }
+
+ mem = gen_rtx_MEM (mode, pre);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[2]));
+
+ if (auto_inc_p (pre))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+(define_insn_and_split "*sto__pre_modify_reg_split"
+ [(set (mem:MEMOP (plus:SI (match_operand:SI 0 "metag_regnofrm_op" "+%e,f,h,l")
+ (match_operand:SI 1 "metag_register_op" "e,f,h,l")))
+ (match_operand: 2 "metag_register_op" "t,u,y,z"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_dup 1)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[1]);
+ rtx pre_modify = gen_rtx_PRE_MODIFY (SImode, operands[0], plus);
+ rtx mem = gen_rtx_MEM (mode, pre_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[2]));
+
+ if (auto_inc_p (pre_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+;; -----------------------------------------------------------------------------
+
+;; -----------------------------------------------------------------------------
+;; | Recognising SI/HI/QI store post-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*sto__post_inc_dec_modify_disp_split"
+ [(set (mem:MEMOP (match_operand:SI 0 "metag_regnofrm_op" "+efhl"))
+ (match_operand: 1 "metag_register_op" "r"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 2 "metag_offset6_" "")))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx post, mem, insn;
+
+ if (INTVAL (operands[2]) == GET_MODE_SIZE (mode))
+ post = gen_rtx_POST_INC (SImode, operands[0]);
+ else if (INTVAL (operands[2]) == -GET_MODE_SIZE (mode))
+ post = gen_rtx_POST_DEC (SImode, operands[0]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[2]);
+
+ post = gen_rtx_POST_MODIFY (SImode, operands[0], plus);
+ }
+
+ mem = gen_rtx_MEM (mode, post);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1]));
+
+ if (auto_inc_p (post))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (post, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+(define_insn_and_split "*sto__post_modify_reg_split"
+ [(set (mem:MEMOP (match_operand:SI 0 "metag_regnofrm_op" "+e,f,h,l"))
+ (match_operand: 1 "metag_register_op" "t,u,y,z"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 2 "metag_register_op" "e,f,h,l")))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[2]);
+ rtx post_modify = gen_rtx_POST_MODIFY (SImode, operands[0], plus);
+ rtx mem = gen_rtx_MEM (mode, post_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1]));
+
+ if (auto_inc_p (post_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (post_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+;; -----------------------------------------------------------------------------
+
+;; -----------------------------------------------------------------------------
+;; | Recognising QI/HI/SI load pre-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*lod__pre_inc_dec_modify_disp_split"
+ [(set (match_operand: 0 "metag_register_op" "=r")
+ (mem:MEMOP (plus:SI (match_operand:SI 1 "metag_regnofrm_op" "+efhl")
+ (match_operand:SI 2 "metag_offset6_" ""))))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx pre, mem, insn;
+
+ if (INTVAL (operands[2]) == GET_MODE_SIZE (mode))
+ pre = gen_rtx_PRE_INC (SImode, operands[1]);
+ else if (INTVAL (operands[2]) == -GET_MODE_SIZE (mode))
+ pre = gen_rtx_PRE_DEC (SImode, operands[1]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[1], operands[2]);
+
+ pre = gen_rtx_PRE_MODIFY (SImode, operands[1], plus);
+ }
+
+ mem = gen_rtx_MEM (mode, pre);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem));
+
+ if (auto_inc_p (pre))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+(define_insn_and_split "*lod__pre_modify_reg_split"
+ [(set (match_operand: 0 "metag_register_op" "=r,r,r,r")
+ (mem:MEMOP (plus:SI (match_operand:SI 1 "metag_regnofrm_op" "+e,f,h,l")
+ (match_operand:SI 2 "metag_register_op" "e,f,h,l"))))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[1], operands[2]);
+ rtx pre_modify = gen_rtx_PRE_MODIFY (SImode, operands[1], plus);
+ rtx mem = gen_rtx_MEM (mode, pre_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem));
+
+ if (auto_inc_p (pre_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+;; -----------------------------------------------------------------------------
+
+;; -----------------------------------------------------------------------------
+;; | Recognising DI store pre-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*sto_di_pre_inc_dec_modify_disp_split"
+ [(set (mem:DI (plus:SI (match_operand:SI 0 "metag_regnofrm_op" "+efhl")
+ (match_operand:SI 1 "metag_offset6_di" "O8")))
+ (match_operand:DI 2 "metag_register_op" "r"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_dup 1)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx pre, mem, insn;
+
+ if (INTVAL (operands[1]) == GET_MODE_SIZE (DImode))
+ pre = gen_rtx_PRE_INC (SImode, operands[0]);
+ else if (INTVAL (operands[1]) == -GET_MODE_SIZE (DImode))
+ pre = gen_rtx_PRE_DEC (SImode, operands[0]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[1]);
+
+ pre = gen_rtx_PRE_MODIFY (SImode, operands[0], plus);
+ }
+
+ mem = gen_rtx_MEM (DImode, pre);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[2]));
+
+ if (auto_inc_p (pre))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+(define_insn_and_split "*sto_di_pre_modify_reg_split"
+ [(set (mem:DI (plus:SI (match_operand:SI 0 "metag_regnofrm_op" "+e,f,h,l")
+ (match_operand:SI 1 "metag_register_op" "e,f,h,l")))
+ (match_operand:DI 2 "metag_register_op" "a,a,d,d"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_dup 1)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[1]);
+ rtx pre_modify = gen_rtx_PRE_MODIFY (SImode, operands[0], plus);
+ rtx mem = gen_rtx_MEM (DImode, pre_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[2]));
+
+ if (auto_inc_p (pre_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+;; -----------------------------------------------------------------------------
+;; | Recognising DI store post-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*sto_di_post_inc_dec_modify_disp_split"
+ [(set (mem:DI (match_operand:SI 0 "metag_regnofrm_op" "+efhl"))
+ (match_operand:DI 1 "metag_register_op" "r"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 2 "metag_offset6_di" "O8")))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx post, mem, insn;
+
+ if (INTVAL (operands[2]) == GET_MODE_SIZE (DImode))
+ post = gen_rtx_POST_INC (SImode, operands[0]);
+ else if (INTVAL (operands[2]) == -GET_MODE_SIZE (DImode))
+ post = gen_rtx_POST_DEC (SImode, operands[0]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[2]);
+
+ post = gen_rtx_POST_MODIFY (SImode, operands[0], plus);
+ }
+
+ mem = gen_rtx_MEM (DImode, post);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1]));
+
+ if (auto_inc_p (post))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (post, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+(define_insn_and_split "*sto_di_post_modify_reg_split"
+ [(set (mem:DI (match_operand:SI 0 "metag_regnofrm_op" "+e,f,h,l"))
+ (match_operand:DI 1 "metag_register_op" "a,a,d,d"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 2 "metag_register_op" "e,f,h,l")))]
+
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[2]);
+ rtx post_modify = gen_rtx_POST_MODIFY (SImode, operands[0], plus);
+ rtx mem = gen_rtx_MEM (DImode, post_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1]));
+
+ if (auto_inc_p (post_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (post_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+;; -----------------------------------------------------------------------------
+
+;; -----------------------------------------------------------------------------
+;; | Recognising DI load pre-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*lod_di_pre_inc_dec_modify_disp_split"
+ [(set (match_operand:DI 0 "metag_register_op" "=r")
+ (mem:DI (plus:SI (match_operand:SI 1 "metag_regnofrm_op" "+efhl")
+ (match_operand:SI 2 "metag_offset6_di" "O8"))))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx pre, mem, insn;
+
+ if (INTVAL (operands[2]) == GET_MODE_SIZE (DImode))
+ pre = gen_rtx_PRE_INC (SImode, operands[1]);
+ else if (INTVAL (operands[2]) == -GET_MODE_SIZE (DImode))
+ pre = gen_rtx_PRE_DEC (SImode, operands[1]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[1], operands[2]);
+
+ pre = gen_rtx_PRE_MODIFY (SImode, operands[1], plus);
+ }
+
+ mem = gen_rtx_MEM (DImode, pre);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem));
+
+ if (auto_inc_p (pre))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "load")])
+
+(define_insn_and_split "*lod_di_pre_modify_reg_split"
+ [(set (match_operand:DI 0 "metag_register_op" "=r,r,r,r")
+ (mem:DI (plus:SI (match_operand:SI 1 "metag_regnofrm_op" "+e,f,h,l")
+ (match_operand:SI 2 "metag_register_op" "e,f,h,l"))))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[1], operands[2]);
+ rtx pre_modify = gen_rtx_PRE_MODIFY (SImode, operands[1], plus);
+ rtx mem = gen_rtx_MEM (DImode, pre_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem));
+
+ if (auto_inc_p (pre_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "load")])
+
+;; -----------------------------------------------------------------------------
+
+;; -----------------------------------------------------------------------------
+;; | Recognising DI load post-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*lod_di_post_inc_dec_modify_disp_split"
+ [(set (match_operand:SI 0 "metag_regnofrm_op" "+efhl")
+ (plus:SI (match_dup 0)
+ (match_operand:SI 1 "metag_offset6_di" "O8")))
+ (set (match_operand:DI 2 "metag_register_op" "=r")
+ (mem:DI (match_dup 0)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx post, mem, insn;
+
+ if (INTVAL (operands[1]) == GET_MODE_SIZE (DImode))
+ post = gen_rtx_PRE_INC (SImode, operands[0]);
+ else if (INTVAL (operands[1]) == -GET_MODE_SIZE (DImode))
+ post = gen_rtx_PRE_DEC (SImode, operands[0]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[1]);
+
+ post = gen_rtx_POST_MODIFY (SImode, operands[0], plus);
+ }
+
+ mem = gen_rtx_MEM (DImode, post);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, operands[2], mem));
+
+ if (auto_inc_p (post))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (post, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "load")])
+
+(define_insn_and_split "*lod_di_post_modify_reg_split"
+ [(set (match_operand:SI 0 "metag_regnofrm_op" "+e,f,h,l")
+ (plus:SI (match_dup 0)
+ (match_operand:SI 1 "metag_register_op" "e,f,h,l")))
+ (set (match_operand:DI 2 "metag_register_op" "=r,r,r,r")
+ (mem:DI (match_dup 0)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[1]);
+ rtx post_modify = gen_rtx_POST_MODIFY (SImode, operands[0], plus);
+ rtx mem = gen_rtx_MEM (DImode, post_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, operands[2], mem));
+
+ if (auto_inc_p (post_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (post_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "load")])
+
+;; -----------------------------------------------------------------------------
+
+;; -----------------------------------------------------------------------------
+;; | Recognising zero extend EXTHI load pre-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*lodz_hi_pre_inc_dec_modify_disp_split"
+ [(set (match_operand:HI 0 "metag_register_op" "=r")
+ (zero_extend:HI
+ (mem:EXTHI (plus:SI (match_operand:SI 1 "metag_regnofrm_op" "+efhl")
+ (match_operand:SI 2 "metag_offset6_" "")))))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx pre, mem, zextend, insn;
+
+ if (INTVAL (operands[2]) == GET_MODE_SIZE (mode))
+ pre = gen_rtx_PRE_INC (SImode, operands[1]);
+ else if (INTVAL (operands[2]) == -GET_MODE_SIZE (mode))
+ pre = gen_rtx_PRE_DEC (SImode, operands[1]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[1], operands[2]);
+
+ pre = gen_rtx_PRE_MODIFY (SImode, operands[1], plus);
+ }
+
+ mem = gen_rtx_MEM (mode, pre);
+ zextend = gen_rtx_ZERO_EXTEND (HImode, mem);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, operands[0], zextend));
+
+ if (auto_inc_p (pre))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+(define_insn_and_split "*lodz_hi_pre_modify_reg_split"
+ [(set (match_operand:HI 0 "metag_register_op" "=r,r,r,r")
+ (zero_extend:HI
+ (mem:EXTHI (plus:SI (match_operand:SI 1 "metag_regnofrm_op" "+e,f,h,l")
+ (match_operand:SI 2 "metag_register_op" "e,f,h,l")))))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[1], operands[2]);
+ rtx pre_modify = gen_rtx_PRE_MODIFY (SImode, operands[1], plus);
+ rtx mem = gen_rtx_MEM (mode, pre_modify);
+ rtx zextend = gen_rtx_ZERO_EXTEND (HImode, mem);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, operands[0], zextend));
+
+ if (auto_inc_p (pre_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+;; -----------------------------------------------------------------------------
+
+;; -----------------------------------------------------------------------------
+;; | Recognising zero extend EXTSI load pre-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*lodz_si_pre_inc_dec_modify_disp_split"
+ [(set (match_operand:SI 0 "metag_register_op" "=r")
+ (zero_extend:SI
+ (mem:EXTSI (plus:SI (match_operand:SI 1 "metag_regnofrm_op" "+efhl")
+ (match_operand:SI 2 "metag_offset6_" "")))))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx pre, mem, zextend, insn;
+
+ if (INTVAL (operands[2]) == GET_MODE_SIZE (mode))
+ pre = gen_rtx_PRE_INC (SImode, operands[1]);
+ else if (INTVAL (operands[2]) == -GET_MODE_SIZE (mode))
+ pre = gen_rtx_PRE_DEC (SImode, operands[1]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[1], operands[2]);
+
+ pre = gen_rtx_PRE_MODIFY (SImode, operands[1], plus);
+ }
+
+ mem = gen_rtx_MEM (mode, pre);
+ zextend = gen_rtx_ZERO_EXTEND (SImode, mem);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, operands[0], zextend));
+
+ if (auto_inc_p (pre))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+(define_insn_and_split "*lodz_si_pre_modify_reg_split"
+ [(set (match_operand:SI 0 "metag_register_op" "=r,r,r,r")
+ (zero_extend:SI
+ (mem:EXTSI (plus:SI (match_operand:SI 1 "metag_regnofrm_op" "+e,f,h,l")
+ (match_operand:SI 2 "metag_register_op" "e,f,h,l")))))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[1], operands[2]);
+ rtx pre_modify = gen_rtx_PRE_MODIFY (SImode, operands[1], plus);
+ rtx mem = gen_rtx_MEM (mode, pre_modify);
+ rtx zextend = gen_rtx_ZERO_EXTEND (SImode, mem);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, operands[0], zextend));
+
+ if (auto_inc_p (pre_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+;; -----------------------------------------------------------------------------
+
+;; -----------------------------------------------------------------------------
+;; | Recognising SF store pre-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*sto_sf_pre_inc_dec_modify_disp_split"
+ [(set (mem:SF
+ (plus:SI (match_operand:SI 0 "metag_regnofrm_op" "+efhl")
+ (match_operand:SI 1 "metag_offset6_sf" "O4")))
+ (match_operand:SF 2 "metag_register_op" "r"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_dup 1)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx pre, mem, insn;
+
+ if (INTVAL (operands[1]) == GET_MODE_SIZE (SFmode))
+ pre = gen_rtx_PRE_INC (SImode, operands[0]);
+ else if (INTVAL (operands[1]) == -GET_MODE_SIZE (SFmode))
+ pre = gen_rtx_PRE_DEC (SImode, operands[0]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[1]);
+
+ pre = gen_rtx_PRE_MODIFY (SImode, operands[0], plus);
+ }
+
+ mem = gen_rtx_MEM (SFmode, pre);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[2]));
+
+ if (auto_inc_p (pre))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+(define_insn_and_split "*sto_sf_pre_modify_reg_split"
+ [(set (mem:SF
+ (plus:SI (match_operand:SI 0 "metag_regnofrm_op" "+%e,f,h,l")
+ (match_operand:SI 1 "metag_register_op" "e,f,h,l")))
+ (match_operand:SF 2 "metag_register_op" "t,u,y,z"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_dup 1)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[1]);
+ rtx pre_modify = gen_rtx_PRE_MODIFY (SImode, operands[0], plus);
+ rtx mem = gen_rtx_MEM (SFmode, pre_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[2]));
+
+ if (auto_inc_p (pre_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+;; -----------------------------------------------------------------------------
+
+;; -----------------------------------------------------------------------------
+;; | Recognising SF store post-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*sto_sf_post_inc_dec_modify_disp_split"
+ [(set (mem:SF (match_operand:SI 0 "metag_regnofrm_op" "+efhl"))
+ (match_operand:SF 1 "metag_register_op" "r"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 2 "metag_offset6_sf" "O4")))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx post, mem, insn;
+
+ if (INTVAL (operands[2]) == GET_MODE_SIZE (SFmode))
+ post = gen_rtx_POST_INC (SImode, operands[0]);
+ else if (INTVAL (operands[2]) == -GET_MODE_SIZE (SFmode))
+ post = gen_rtx_POST_DEC (SImode, operands[0]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[2]);
+
+ post = gen_rtx_POST_MODIFY (SImode, operands[0], plus);
+ }
+
+ mem = gen_rtx_MEM (SFmode, post);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1]));
+
+ if (auto_inc_p (post))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (post, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+(define_insn_and_split "*sto_sf_post_modify_reg_split"
+ [(set (mem:SF (match_operand:SI 0 "metag_regnofrm_op" "+e,f,h,l"))
+ (match_operand:SF 1 "metag_register_op" "t,u,y,z"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 2 "metag_register_op" "e,f,h,l")))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[2]);
+ rtx post_modify = gen_rtx_POST_MODIFY (SImode, operands[0], plus);
+ rtx mem = gen_rtx_MEM (SFmode, post_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1]));
+
+ if (auto_inc_p (post_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (post_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+;; -----------------------------------------------------------------------------
+
+;; -----------------------------------------------------------------------------
+;; | Recognising SF load pre-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*lod_sf_pre_inc_dec_modify_disp_split"
+ [(set (match_operand:SF 0 "metag_register_op" "=r")
+ (mem:SF (plus:SI (match_operand:SI 1 "metag_regnofrm_op" "+efhl")
+ (match_operand:SI 2 "metag_offset6_sf" "O4"))))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx pre, mem, insn;
+
+ if (INTVAL (operands[2]) == GET_MODE_SIZE (SFmode))
+ pre = gen_rtx_PRE_INC (SImode, operands[1]);
+ else if (INTVAL (operands[2]) == -GET_MODE_SIZE (SFmode))
+ pre = gen_rtx_PRE_DEC (SImode, operands[1]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[1], operands[2]);
+
+ pre = gen_rtx_PRE_MODIFY (SImode, operands[1], plus);
+ }
+
+ mem = gen_rtx_MEM (SFmode, pre);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem));
+
+ if (auto_inc_p (pre))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+(define_insn_and_split "*lod_sf_pre_modify_reg_split"
+ [(set (match_operand:SF 0 "metag_register_op" "=r,r,r,r")
+ (mem:SF (plus:SI (match_operand:SI 1 "metag_regnofrm_op" "+e,f,h,l")
+ (match_operand:SI 2 "metag_register_op" "e,f,h,l"))))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[1], operands[2]);
+ rtx pre_modify = gen_rtx_PRE_MODIFY (SImode, operands[1], plus);
+ rtx mem = gen_rtx_MEM (SFmode, pre_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem));
+
+ if (auto_inc_p (pre_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+;; -----------------------------------------------------------------------------
+;; | Recognising DF load pre-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*lod_df_pre_inc_dec_modify_disp_split"
+ [(set (match_operand:DF 0 "metag_register_op" "=r")
+ (mem:DF (plus:SI (match_operand:SI 1 "metag_regnofrm_op" "+efhl")
+ (match_operand:SI 2 "metag_offset6_df" "O8"))))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx pre, mem, insn;
+
+ if (INTVAL (operands[2]) == GET_MODE_SIZE (DFmode))
+ pre = gen_rtx_PRE_INC (SImode, operands[1]);
+ else if (INTVAL (operands[2]) == -GET_MODE_SIZE (DFmode))
+ pre = gen_rtx_PRE_DEC (SImode, operands[1]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[1], operands[2]);
+
+ pre = gen_rtx_PRE_MODIFY (SImode, operands[1], plus);
+ }
+
+ mem = gen_rtx_MEM (DFmode, pre);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem));
+
+ if (auto_inc_p (pre))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "load")])
+
+(define_insn_and_split "*lod_df_pre_modify_reg_split"
+ [(set (match_operand:DF 0 "metag_register_op" "=r,r,r,r")
+ (mem:DF (plus:SI (match_operand:SI 1 "metag_regnofrm_op" "+e,f,h,l")
+ (match_operand:SI 2 "metag_register_op" "e,f,h,l"))))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[1], operands[2]);
+ rtx pre_modify = gen_rtx_PRE_MODIFY (SImode, operands[1], plus);
+ rtx mem = gen_rtx_MEM (DFmode, pre_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem));
+
+ if (auto_inc_p (pre_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "load")])
+
+;; -----------------------------------------------------------------------------
+
+;; -----------------------------------------------------------------------------
+;; | Recognising DF load post-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*lod_df_post_inc_dec_modify_disp_split"
+ [(set (match_operand:SI 0 "metag_regnofrm_op" "+efhl")
+ (plus:SI (match_dup 0)
+ (match_operand:SI 1 "metag_offset6_df" "O8")))
+ (set (match_operand:DF 2 "metag_register_op" "=r")
+ (mem:DF (match_dup 0)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx post, mem, insn;
+
+ if (INTVAL (operands[1]) == GET_MODE_SIZE (DFmode))
+ post = gen_rtx_PRE_INC (SImode, operands[0]);
+ else if (INTVAL (operands[1]) == -GET_MODE_SIZE (DFmode))
+ post = gen_rtx_PRE_DEC (SImode, operands[0]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[1]);
+
+ post = gen_rtx_POST_MODIFY (SImode, operands[0], plus);
+ }
+
+ mem = gen_rtx_MEM (DFmode, post);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, operands[2], mem));
+
+ if (auto_inc_p (post))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (post, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "load")])
+
+(define_insn_and_split "*lod_df_post_modify_reg_split"
+ [(set (match_operand:SI 0 "metag_regnofrm_op" "+e,f,h,l")
+ (plus:SI (match_dup 0)
+ (match_operand:SI 1 "metag_register_op" "e,f,h,l")))
+ (set (match_operand:DF 2 "metag_register_op" "=r,r,r,r")
+ (mem:DF (match_dup 0)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[1]);
+ rtx post_modify = gen_rtx_POST_MODIFY (SImode, operands[0], plus);
+ rtx mem = gen_rtx_MEM (DFmode, post_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, operands[2], mem));
+
+ if (auto_inc_p (post_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (post_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "load")])
+
+;; -----------------------------------------------------------------------------
+
+;; -----------------------------------------------------------------------------
+;; | Recognising DF store pre-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*sto_df_pre_inc_dec_modify_disp_split"
+ [(set (mem:DF (plus:SI (match_operand:SI 0 "metag_regnofrm_op" "+efhl")
+ (match_operand:SI 1 "metag_offset6_df" "O8")))
+ (match_operand:DF 2 "metag_register_op" "r"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_dup 1)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx pre, mem, insn;
+
+ if (INTVAL (operands[1]) == GET_MODE_SIZE (DFmode))
+ pre = gen_rtx_PRE_INC (SImode, operands[0]);
+ else if (INTVAL (operands[1]) == -GET_MODE_SIZE (DFmode))
+ pre = gen_rtx_PRE_DEC (SImode, operands[0]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[1]);
+
+ pre = gen_rtx_PRE_MODIFY (SImode, operands[0], plus);
+ }
+
+ mem = gen_rtx_MEM (DFmode, pre);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[2]));
+
+ if (auto_inc_p (pre))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+(define_insn_and_split "*sto_df_pre_modify_reg_split"
+ [(set (mem:DF (plus:SI (match_operand:SI 0 "metag_regnofrm_op" "+e,f,h,l")
+ (match_operand:SI 1 "metag_register_op" "e,f,h,l")))
+ (match_operand:DF 2 "metag_register_op" "a,a,d,d"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_dup 1)))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[1]);
+ rtx pre_modify = gen_rtx_PRE_MODIFY (SImode, operands[0], plus);
+ rtx mem = gen_rtx_MEM (DFmode, pre_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[2]));
+
+ if (auto_inc_p (pre_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (pre_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+;; -----------------------------------------------------------------------------
+;; | Recognising DF store post-inc/dec/modify |
+;; -----------------------------------------------------------------------------
+
+(define_insn_and_split "*sto_df_post_inc_dec_modify_disp_split"
+ [(set (mem:DF (match_operand:SI 0 "metag_regnofrm_op" "+efhl"))
+ (match_operand:DF 1 "metag_register_op" "r"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 2 "metag_offset6_df" "O8")))]
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx post, mem, insn;
+
+ if (INTVAL (operands[2]) == GET_MODE_SIZE (DFmode))
+ post = gen_rtx_POST_INC (SImode, operands[0]);
+ else if (INTVAL (operands[2]) == -GET_MODE_SIZE (DFmode))
+ post = gen_rtx_POST_DEC (SImode, operands[0]);
+ else
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[2]);
+
+ post = gen_rtx_POST_MODIFY (SImode, operands[0], plus);
+ }
+
+ mem = gen_rtx_MEM (DFmode, post);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1]));
+
+ if (auto_inc_p (post))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (post, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
+
+(define_insn_and_split "*sto_df_post_modify_reg_split"
+ [(set (mem:DF (match_operand:SI 0 "metag_regnofrm_op" "+e,f,h,l"))
+ (match_operand:DF 1 "metag_register_op" "a,a,d,d"))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 2 "metag_register_op" "e,f,h,l")))]
+
+ "TARGET_METAC_1_1
+ && !reload_in_progress && !reload_completed"
+ "#"
+ "&& TRUE"
+ [(const_int 0)]
+ {
+ rtx plus = gen_rtx_PLUS (SImode, operands[0], operands[2]);
+ rtx post_modify = gen_rtx_POST_MODIFY (SImode, operands[0], plus);
+ rtx mem = gen_rtx_MEM (DFmode, post_modify);
+ rtx insn = emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1]));
+
+ if (auto_inc_p (post_modify))
+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, XEXP (post_modify, 0), REG_NOTES (insn));
+ DONE;
+ }
+ [(set_attr "type" "fast")])
diff -Nur gcc-4.2.4.orig/gcc/config/metag/constants.md gcc-4.2.4/gcc/config/metag/constants.md
--- gcc-4.2.4.orig/gcc/config/metag/constants.md 1969-12-31 18:00:00.000000000 -0600
+++ gcc-4.2.4/gcc/config/metag/constants.md 2015-07-03 18:46:05.745283542 -0500
@@ -0,0 +1,179 @@
+;; Constants definitions for META
+;; Copyright (C) 2007 Imagination Technologies Ltd
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it under
+;; the terms of the GNU General Public License as published by the Free
+;; Software Foundation; either version 3, or (at your option) any later
+;; version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+;; for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; .
+
+;; UNSPEC
+(define_constants
+ [(UNSPEC_GOTOFF 1)
+ (UNSPEC_GOT 2)
+ (UNSPEC_PLT 3)
+ (UNSPEC_PIC 4)
+ (UNSPEC_PIC_BASE 5)
+
+ (UNSPEC_PROLOGUE_USE 6)
+ (UNSPEC_CONCAT 7)
+ (UNSPEC_SIBCALL 8)
+ (UNSPEC_SIBCALL_VALUE 9)
+
+ (UNSPEC_RET_COND 10)
+ (UNSPEC_RET_COND_INVERTED 11)
+
+ (UNSPEC_METAG_BSWAP 12)
+ (UNSPEC_METAG_BSWAPLL 13)
+
+ (UNSPEC_MINIM_JUMP_TABLE 14)
+
+ (UNSPEC_FIRST_TLS 15)
+ (UNSPEC_TLS 15)
+ (UNSPEC_TLSGD 16)
+ (UNSPEC_TLSLDM 17)
+ (UNSPEC_TLSLDO 18)
+ (UNSPEC_TLSIE 19)
+ (UNSPEC_TLSLE 20)
+ (UNSPEC_LAST_TLS 20)])
+
+
+;; UNSPEC VOLATILE
+(define_constants
+ [(VUNSPEC_DCACHE_PRELOAD 1)
+ (VUNSPEC_DCACHE 2)
+ (VUNSPEC_DCACHE_REFRESH 3)
+ (VUNSPEC_BLOCKAGE 4)
+ (VUNSPEC_EPILOGUE 5)
+ (VUNSPEC_EH_RETURN 6)
+ (VUNSPEC_META2_CACHERD 7)
+ (VUNSPEC_META2_CACHERL 8)
+ (VUNSPEC_META2_CACHEWD 9)
+ (VUNSPEC_META2_CACHEWL 10)
+ (VUNSPEC_TTMOV 11)
+ (VUNSPEC_TTREC 12)])
+
+
+;; Register
+(define_constants
+ [(D0Ar6_REG 2)
+ (D1Ar5_REG 3)
+ (D0Ar4_REG 4)
+ (D1Ar3_REG 5)
+ (D0Ar2_REG 6)
+ (D1Ar1_REG 7)
+
+ (D0Re0_REG 0)
+ (D1Re0_REG 1)
+ (D0FrT_REG 8)
+ (D1RtP_REG 9)
+
+ (FIRST_DATA_REG 0)
+ (D0_0_REG 0)
+ (D1_0_REG 1)
+ (D0_1_REG 2)
+ (D1_1_REG 3)
+ (D0_2_REG 4)
+ (D1_2_REG 5)
+ (D0_3_REG 6)
+ (D1_3_REG 7)
+ (D0_4_REG 8)
+ (D1_4_REG 9)
+ (D0_5_REG 10)
+ (D1_5_REG 11)
+ (D0_6_REG 12)
+ (D1_6_REG 13)
+ (D0_7_REG 14)
+ (D1_7_REG 15)
+ (FIRST_ECH_DATA_REG 16)
+ (D0_8_REG 16)
+ (D1_8_REG 17)
+ (D0_9_REG 18)
+ (D1_9_REG 19)
+ (D0_10_REG 20)
+ (D1_10_REG 21)
+ (D0_11_REG 22)
+ (D1_11_REG 23)
+ (D0_12_REG 24)
+ (D1_12_REG 25)
+ (D0_13_REG 26)
+ (D1_13_REG 27)
+ (D0_14_REG 28)
+ (D1_14_REG 29)
+ (D0_15_REG 30)
+ (D1_15_REG 31)
+ (LAST_DATA_REG 31)
+
+ (A0StP_REG 32)
+ (A1GbP_REG 33)
+ (A0FrP_REG 34)
+ (A1LbP_REG 35)
+
+ (PIC_REG 35)
+
+ (FIRST_ADDR_REG 32)
+ (A0_0_REG 32)
+ (A1_0_REG 33)
+ (A0_1_REG 34)
+ (A1_1_REG 35)
+ (A0_2_REG 36)
+ (A1_2_REG 37)
+ (A0_3_REG 38)
+ (A1_3_REG 39)
+ (FIRST_ECH_ADDR_REG 40)
+ (A0_4_REG 40)
+ (A1_4_REG 41)
+ (A0_5_REG 42)
+ (A1_5_REG 43)
+ (A0_6_REG 44)
+ (A1_6_REG 45)
+ (A0_7_REG 46)
+ (A1_7_REG 47)
+ (LAST_ADDR_REG 47)
+
+ (FRAME_REG 48)
+ (CC_REG 49)
+ (ARGP_REG 50)
+ (RAPF_REG 51)
+ (CPC0_REG 52)
+ (CPC1_REG 53)
+ (PC_REG 54)
+ (TXRPT_REG 55)
+
+ (FIRST_FP_REG 56)
+ (FX_0_REG 56)
+ (FX_1_REG 57)
+ (FX_2_REG 58)
+ (FX_3_REG 59)
+ (FX_4_REG 60)
+ (FX_5_REG 61)
+ (FX_6_REG 62)
+ (FX_7_REG 63)
+ (FX_8_REG 64)
+ (FX_9_REG 65)
+ (FX_10_REG 66)
+ (FX_11_REG 67)
+ (FX_12_REG 68)
+ (FX_13_REG 69)
+ (FX_14_REG 70)
+ (FX_15_REG 71)
+ (LAST_FP_REG 71)
+ (TTREC_REG 72)
+ (TTRECL_REG 73)
+ (LAST_REG 73)])
+
+;; Exception handling - dwarf2 call frame unwinder
+(define_constants
+ [(EH_RETURN_FIRST_DATA_REG 2)
+ (EH_RETURN_LAST_DATA_REG 3)
+ (EH_RETURN_STACKADJ_REG 4)])
diff -Nur gcc-4.2.4.orig/gcc/config/metag/constraints.md gcc-4.2.4/gcc/config/metag/constraints.md
--- gcc-4.2.4.orig/gcc/config/metag/constraints.md 1969-12-31 18:00:00.000000000 -0600
+++ gcc-4.2.4/gcc/config/metag/constraints.md 2015-07-03 18:46:05.745283542 -0500
@@ -0,0 +1,319 @@
+;; Constraint definitions for META.
+;; Copyright (C) 2007, 2010 Imagination Technologies Ltd
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it under
+;; the terms of the GNU General Public License as published by the Free
+;; Software Foundation; either version 3, or (at your option) any later
+;; version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+;; for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; .
+
+;; Register constraints
+
+(define_register_constraint "d" "D_REGS"
+ "data unit register")
+
+(define_register_constraint "e" "D0_REGS"
+ "data unit 0 register")
+
+(define_register_constraint "f" "D1_REGS"
+ "data unit 1 register")
+
+(define_register_constraint "a" "A_REGS"
+ "address unit register")
+
+(define_register_constraint "h" "A0_REGS"
+ "address unit 0 register")
+
+(define_register_constraint "l" "A1_REGS"
+ "address unit 1 register")
+
+(define_register_constraint "be" "Be_REGS"
+ "O2R register data unit 0")
+
+(define_register_constraint "bf" "Bf_REGS"
+ "O2R register data unit 1")
+
+(define_register_constraint "bd" "Bd_REGS"
+ "O2R register data unit")
+
+(define_register_constraint "bh" "Bh_REGS"
+ "O2R register address unit 0")
+
+(define_register_constraint "bl" "Bl_REGS"
+ "O2R register address unit 1")
+
+(define_register_constraint "ba" "Ba_REGS"
+ "O2R register address unit")
+
+(define_register_constraint "br" "Br_REGS"
+ "O2R register any unit")
+
+(define_register_constraint "t" "nD0_REGS"
+ "data unit 1, addr unit 0, addr unit 1 register")
+
+(define_register_constraint "u" "nD1_REGS"
+ "data unit 0, addr unit 0, addr unit 1 register")
+
+(define_register_constraint "y" "nA0_REGS"
+ "data unit 0, data unit 1, addr unit 1 register")
+
+(define_register_constraint "z" "nA1_REGS"
+ "data unit 0, addr unit 1, addr unit 0 register")
+
+(define_register_constraint "q" "nBU_REGS"
+ "not base unit register")
+
+(define_register_constraint "Wx" "Wx_REGS"
+ "control register i.e. TXRPT")
+
+(define_register_constraint "WQh" "WQh_REGS"
+ "A0 QuickRoT control registers A0.2 A0.3")
+
+(define_register_constraint "WQl" "WQl_REGS"
+ "A1 QuickRoT control registers A1.2 A1.3")
+
+(define_register_constraint "Ye" "Ye_REGS"
+ "data unit 0 register 12-bit offsetable")
+
+(define_register_constraint "Yf" "Yf_REGS"
+ "data unit 1 register 12-bit offsetable")
+
+(define_register_constraint "Yd" "Yd_REGS"
+ "data unit register 12-bit offsetable")
+
+(define_register_constraint "Yh" "Yh_REGS"
+ "addr unit 0 register 12-bit offsetable")
+
+(define_register_constraint "Yl" "Yl_REGS"
+ "addr unit 1 register 12-bit offsetable")
+
+(define_register_constraint "Ya" "Ya_REGS"
+ "addr unit register 12-bit offsetable")
+
+(define_register_constraint "Yr" "Yr_REGS"
+ "data/addr register 12-bit offsetable")
+
+(define_register_constraint "Yne" "nYe_REGS"
+ "...")
+
+(define_register_constraint "Ynf" "nYf_REGS"
+ "...")
+
+(define_register_constraint "Ynd" "nYd_REGS"
+ "...")
+
+(define_register_constraint "Ynh" "nYh_REGS"
+ "...")
+
+(define_register_constraint "Ynl" "nYl_REGS"
+ "...")
+
+(define_register_constraint "Yna" "nYa_REGS"
+ "...")
+
+(define_register_constraint "Ynr" "nYr_REGS"
+ "...")
+
+(define_register_constraint "ce" "metag_fpu_resources ? cD0_REGS : D0_REGS"
+ "data 0 or float unit register")
+
+(define_register_constraint "cf" "metag_fpu_resources ? cD1_REGS : D1_REGS"
+ "data 1, or float unit register")
+
+(define_register_constraint "cd" "metag_fpu_resources ? cD_REGS : D_REGS"
+ "data, or float unit register")
+
+(define_register_constraint "ch" "metag_fpu_resources ? cA0_REGS : A0_REGS"
+ "addr 0 or float unit register")
+
+(define_register_constraint "cl" "metag_fpu_resources ? cA1_REGS : A1_REGS"
+ "addr 1 or float unit register")
+
+(define_register_constraint "ca" "metag_fpu_resources ? cA_REGS : A_REGS"
+ "addr or float unit register")
+
+(define_register_constraint "cr" "metag_fpu_resources ? cDA_REGS : DA_REGS"
+ "data, addr or float unit register")
+
+(define_register_constraint "ct" "metag_fpu_resources ? cnD0_REGS : nD0_REGS"
+ "data unit 1, addr unit 0, addr unit 1 or float unit register")
+
+(define_register_constraint "cu" "metag_fpu_resources ? cnD1_REGS : nD1_REGS"
+ "data unit 0, addr unit 0, addr unit 1 or float unit register")
+
+(define_register_constraint "cy" "metag_fpu_resources ? cnA0_REGS : nA0_REGS"
+ "data unit 0, data unit 0, addr unit 1 or float unit register")
+
+(define_register_constraint "cz" "metag_fpu_resources ? cnA1_REGS : nA1_REGS"
+ "data unit 0, data unit 1, addr unit 0 or float unit register")
+
+(define_register_constraint "cx" "metag_fpu_resources ? FPC_REGS : NO_REGS"
+ "floating point register")
+
+(define_register_constraint "cp" "metag_fpu_resources ? FPP_REGS : NO_REGS"
+ "floating point register pair")
+
+;; Integer constraints
+
+(define_constraint "I"
+ "...."
+ (and (match_code "const_int")
+ (match_test "(ival >= -32768 && ival <= -256) || (ival >= 256 && ival <= 65535)")))
+
+(define_constraint "J"
+ "...."
+ (and (match_code "const_int")
+ (match_test "(ival & 0x0000FFFF) == 0")))
+
+(define_constraint "O0"
+ "...."
+ (and (match_code "const_int")
+ (match_test "(ival & 0xFFFF) == 0")))
+
+(define_constraint "O3"
+ "...."
+ (and (match_code "const_int")
+ (match_test "((ival >> 16) & 0x0000FFFF) == 0")))
+
+(define_constraint "K"
+ "..."
+ (and (match_code "const_int")
+ (match_test "0 <= ival && ival <= 255")))
+
+(define_constraint "L"
+ "..."
+ (and (match_code "const_int")
+ (match_test "0 <= ival && ival <= 31")))
+
+(define_constraint "M"
+ "..."
+ (and (match_code "const_int")
+ (match_test "((ival >> 16) & 0xFFFF) == 0x0000FFFF")))
+
+(define_constraint "N"
+ "..."
+ (and (match_code "const_int")
+ (match_test "((ival & 0x0000FFFF) == 0x0000FFFF)")))
+
+(define_constraint "O1"
+ "..."
+ (and (match_code "const_int")
+ (match_test "-32 <= ival && ival < 32")))
+
+(define_constraint "O2"
+ "..."
+ (and (match_code "const_int")
+ (match_test "(-64 <= ival && ival < 64) && (ival & 1) == 0")))
+
+(define_constraint "O4"
+ "..."
+ (and (match_code "const_int")
+ (match_test "(-128 <= ival && ival < 128) && (ival & 3) == 0")))
+
+(define_constraint "O8"
+ "..."
+ (and (match_code "const_int")
+ (match_test "(-256 <= ival && ival < 256) && (ival & 7) == 0")))
+
+(define_constraint "P"
+ "..."
+ (and (match_code "const_int")
+ (match_test "-255 <= ival && ival < 0")))
+
+(define_constraint "vci"
+ "..."
+ (and (match_code "const_vector")
+ (match_test "GET_MODE_INNER (mode) == SImode")))
+
+(define_constraint "vcf"
+ "..."
+ (and (match_code "const_vector")
+ (match_test "GET_MODE_INNER (mode) == SFmode")))
+
+(define_constraint "vc5"
+ "..."
+ (and (match_code "const_vector")
+ (match_test "metag_vector_5bit_op (op, mode)")))
+
+(define_constraint "v16"
+ "..."
+ (and (match_code "const_vector")
+ (match_test "metag_vector_16bit_op (op, mode)")))
+
+;; Floating-point constraints
+
+(define_constraint "G"
+ "Floating-point zero."
+ (and (match_code "const_double")
+ (match_test "GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode)")))
+
+(define_constraint "H"
+ "Floating-point one."
+ (and (match_code "const_double")
+ (match_test "GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST1_RTX (mode)")))
+
+(define_constraint "ci"
+ "Floating-point immediates in half precision"
+ (and (match_code "const_double")
+ (match_test "GET_MODE_CLASS (mode) == MODE_FLOAT && metag_fphalf_imm_op (op, mode)")))
+
+;; General constraints
+
+(define_constraint "Th"
+ "@internal"
+ (and (match_test "metag_mem_base_p (op, A0_REGS)")
+ (match_test "metag_legitimate_address_p (XEXP (op, 0), GET_MODE (op), true)")))
+
+(define_constraint "Tl"
+ "@internal"
+ (and (match_test "metag_mem_base_p (op, A1_REGS)")
+ (match_test "metag_legitimate_address_p (XEXP (op, 0), GET_MODE (op), true)")))
+
+(define_constraint "Te"
+ "@internal"
+ (and (match_test "metag_mem_base_p (op, D0_REGS)")
+ (match_test "metag_legitimate_address_p (XEXP (op, 0), GET_MODE (op), true)")))
+
+(define_constraint "Tf"
+ "@internal"
+ (and (match_test "metag_mem_base_p (op, D1_REGS)")
+ (match_test "metag_legitimate_address_p (XEXP (op, 0), GET_MODE (op), true)")))
+
+(define_constraint "Tr"
+ "@internal"
+ (and (match_test "metag_legitimate_address_p (XEXP (op, 0), GET_MODE (op), true)")
+ (not (match_test "GET_CODE (XEXP (op, 0)) == PLUS
+ && metag_regs_ok_for_base_offset_p (XEXP (XEXP (op, 0), 0),
+ XEXP (XEXP (op, 0), 1),
+ true)"))))
+
+(define_constraint "Z1"
+ "..."
+ (and (match_code "const_int")
+ (match_test "-2048 <= ival && ival < 2048")))
+
+(define_constraint "Z2"
+ "..."
+ (and (match_code "const_int")
+ (match_test "-4096 <= ival && ival < 4096 && (ival & 1) == 0")))
+
+(define_constraint "Z4"
+ "..."
+ (and (match_code "const_int")
+ (match_test "-8192 <= ival && ival < 8192 && (ival & 3) == 0")))
+
+(define_constraint "Z8"
+ "..."
+ (and (match_code "const_int")
+ (match_test "-16384 <= ival && ival < 16384 && (ival & 7) == 0")))
+
diff -Nur gcc-4.2.4.orig/gcc/config/metag/driver-metag.c gcc-4.2.4/gcc/config/metag/driver-metag.c
--- gcc-4.2.4.orig/gcc/config/metag/driver-metag.c 1969-12-31 18:00:00.000000000 -0600
+++ gcc-4.2.4/gcc/config/metag/driver-metag.c 2015-07-03 18:46:05.745283542 -0500
@@ -0,0 +1,276 @@
+/* Subroutines for the gcc driver.
+ Copyright (C) 2008 Imagination Technologies Ltd
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+. */
+
+#include
+#include
+#include "libiberty.h"
+#include "filenames.h"
+
+const char *metag_reduce_options (int argc, const char **argv);
+const char *metag_emb_asm_preprocessor (int argc, const char **argv);
+const char *metag_emb_onlylast (int argc, const char **argv);
+const char *metag_emb_change_suffix (int argc, const char **argv);
+
+/* This function will reduce all -mmetac options to remove all but
+ the last one with the %.
+
+;; See comment at the top of dsppeephole.md for information about
+;; dual unit DSP support in the metag backend.
+
+;; The metag_dsp_peephole2_xxxxxx_convert functions used in these
+;; rules promote operands to V2SI mode. They are all structured such
+;; that they can be used for both flag setting and non-flag setting
+;; rules.
+
+;; DSP Math peephole2s
+
+(define_peephole2
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" "")))
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" "")))]
+ "TARGET_DSP
+ && metag_dsp_rrr_operands (operands, )"
+ [(set (match_dup 3)
+ (3OPREG:V2SI (match_dup 4)
+ (match_dup 5)))]
+ {
+ metag_dsp_peephole2_rrr_convert (operands);
+ })
+
+(define_peephole2
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPIMM16:SI (match_dup 0)
+ (match_operand:SI 1 "metag_16bit_op" "")))
+ (set (match_operand:SI 2 "metag_datareg_op" "")
+ (3OPIMM16:SI (match_dup 2)
+ (match_dup 1)))]
+ "TARGET_DSP
+ && metag_dsp_ri16_operands (operands)
+ "
+ [(set (match_dup 2)
+ (3OPIMM16:V2SI (match_dup 2)
+ (match_dup 3)))]
+ {
+ metag_dsp_peephole2_ri16_convert (operands);
+ })
+
+(define_peephole2
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_5bit_op" "")))
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_dup 2)))]
+ "TARGET_DSP
+ && metag_dsp_rri5_operands (operands)
+ "
+ [(set (match_dup 3)
+ (3OPIMM5:V2SI (match_dup 4)
+ (match_dup 5)))]
+ {
+ metag_dsp_peephole2_rri5_convert (operands);
+ })
+
+;; DSP MUL peephole
+
+;; MUL is not supported due to default DSP arithmetic mode being 16x16
+
+;; DSP MIN/MAX
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (MINMAX:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])
+ (parallel
+ [(set (match_operand:SI 3 "metag_datareg_op" "")
+ (MINMAX:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rrr_operands (operands, true)"
+ [(parallel
+ [(set (match_dup 3)
+ (MINMAX:V2SI (match_dup 4)
+ (match_dup 5)))
+ (clobber (reg:CC CC_REG))])]
+ {
+ metag_dsp_peephole2_rrr_convert (operands);
+ })
+
+;; DSP ABS peephole
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (abs:SI (match_operand:SI 1 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])
+ (parallel
+ [(set (match_operand:SI 2 "metag_datareg_op" "")
+ (abs:SI (match_operand:SI 3 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rr_operands (operands)"
+ [(parallel
+ [(set (match_dup 2)
+ (abs:V2SI (match_dup 3)))
+ (clobber (reg:CC CC_REG))])]
+ {
+ metag_dsp_peephole2_rr_convert (operands);
+ })
+
+;; DSP MOV peephole
+
+(define_peephole2
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (match_operand:SI 1 "metag_datareg_op" ""))
+ (set (match_operand:SI 2 "metag_datareg_op" "")
+ (match_operand:SI 3 "metag_datareg_op" ""))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rr_operands (operands)"
+ [(set (match_dup 2)
+ (match_dup 3))]
+ {
+ metag_dsp_peephole2_rr_convert (operands);
+ })
+
+;; DSP Math with flags peepholes
+
+(define_peephole2
+ [(parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPREG:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPREG:SI (match_dup 1)
+ (match_dup 2)))])
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" "")))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rrr_operands (operands, )"
+ [(parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPREG:SI (match_dup 1)
+ (match_dup 2))
+ (const_int 0)))
+ (set (match_dup 3)
+ (3OPREG:V2SI (match_dup 4)
+ (match_dup 5)))])]
+ {
+ metag_dsp_peephole2_rrr_convert (operands);
+ })
+
+(define_peephole2
+ [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPREG:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPREG:SI (match_dup 1)
+ (match_dup 2)))
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" "")))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rrr_operands (operands, )"
+ [(parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPREG:SI (match_dup 1)
+ (match_dup 2))
+ (const_int 0)))
+ (set (match_dup 3)
+ (3OPREG:V2SI (match_dup 4)
+ (match_dup 5)))])]
+ {
+ metag_dsp_peephole2_rrr_convert (operands);
+ })
+
+(define_peephole2
+ [(parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM16:SI (match_operand:SI 0 "metag_datareg_op" "")
+ (match_operand:SI 1 "metag_16bit_op" ""))
+ (const_int 0)))
+ (set (match_dup 0)
+ (3OPIMM16:SI (match_dup 0)
+ (match_dup 1)))])
+ (set (match_operand:SI 2 "metag_datareg_op" "")
+ (3OPIMM16:SI (match_dup 2)
+ (match_dup 1)))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_ri16_operands (operands)
+ "
+ [(parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM16:SI (match_dup 0)
+ (match_dup 1))
+ (const_int 0)))
+ (set (match_dup 2)
+ (3OPIMM16:V2SI (match_dup 2)
+ (match_dup 3)))])]
+ {
+ metag_dsp_peephole2_ri16_convert (operands);
+ })
+
+(define_peephole2
+ [(parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM5:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_5bit_op" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_dup 1)
+ (match_dup 2)))])
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_dup 2)))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rri5_operands (operands)
+ "
+ [(parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM5:SI (match_dup 1)
+ (match_dup 2))
+ (const_int 0)))
+ (set (match_dup 3)
+ (3OPIMM5:V2SI (match_dup 4)
+ (match_dup 5)))])]
+ {
+ metag_dsp_peephole2_rri5_convert (operands);
+ })
+
+(define_peephole2
+ [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM16:SI (match_operand:SI 0 "metag_datareg_op" "")
+ (match_operand:SI 1 "metag_16bit_op" ""))
+ (const_int 0)))
+ (set (match_dup 0)
+ (3OPIMM16:SI (match_dup 0)
+ (match_dup 1)))
+ (set (match_operand:SI 2 "metag_datareg_op" "")
+ (3OPIMM16:SI (match_dup 2)
+ (match_dup 1)))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_ri16_operands (operands)
+ "
+ [(parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM16:SI (match_dup 0)
+ (match_dup 1))
+ (const_int 0)))
+ (set (match_dup 2)
+ (3OPIMM16:V2SI (match_dup 2)
+ (match_dup 3)))])]
+ {
+ metag_dsp_peephole2_ri16_convert (operands);
+ })
+
+(define_peephole2
+ [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM5:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_5bit_op" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_dup 1)
+ (match_dup 2)))
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_dup 2)))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rri5_operands (operands)
+ "
+ [(parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM5:SI (match_dup 1)
+ (match_dup 2))
+ (const_int 0)))
+ (set (match_dup 3)
+ (3OPIMM5:V2SI (match_dup 4)
+ (match_dup 5)))])]
+ {
+ metag_dsp_peephole2_rri5_convert (operands);
+ })
+
+;; DSP OP + MOV
+
+(define_peephole2
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" "")))
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" "")))
+ (set (match_operand:SI 6 "metag_datareg_op" "")
+ (match_dup 0))
+ (set (match_operand:SI 7 "metag_datareg_op" "")
+ (match_dup 3))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rrr_mov_operands (operands, )
+ && peep2_reg_dead_p (3, operands[0])
+ && peep2_reg_dead_p (4, operands[3])"
+ [(set (match_dup 6)
+ (3OPREG:V2SI (match_dup 1)
+ (match_dup 2)))]
+ {
+ metag_dsp_peephole2_rrr_mov_convert (operands);
+ })
+
+;; DSP MUL + MOV
+
+;; MUL is not supported due to default dsp arithmetic mode being 16x16
+
+;; DSP ABS + MOV
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:SI 0 "metag_reg_nofloat_op" "")
+ (abs:SI (match_operand:SI 1 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])
+ (set (match_operand:SI 4 "metag_datareg_op" "")
+ (match_dup 0))
+ (parallel
+ [(set (match_operand:SI 2 "metag_reg_nofloat_op" "")
+ (abs:SI (match_operand:SI 3 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])
+ (set (match_operand:SI 5 "metag_datareg_op" "")
+ (match_dup 2))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rr_rr_mov_operands (operands)
+ && peep2_reg_dead_p (2, operands[0])
+ && peep2_reg_dead_p (4, operands[2])"
+ [(parallel
+ [(set (match_dup 4)
+ (abs:SI (match_dup 1)))
+ (clobber (reg:CC CC_REG))])]
+ {
+ metag_dsp_peephole2_rr_mov_convert (operands);
+ })
+
+;; DSP MIN/MAX + MOV
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (MINMAX:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])
+ (set (match_operand:SI 6 "metag_datareg_op" "")
+ (match_dup 0))
+ (parallel
+ [(set (match_operand:SI 3 "metag_datareg_op" "")
+ (MINMAX:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])
+ (set (match_operand:SI 7 "metag_datareg_op" "")
+ (match_dup 3))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rrr_mov_operands (operands, )
+ && peep2_reg_dead_p (2, operands[0])
+ && peep2_reg_dead_p (4, operands[3])"
+ [(parallel
+ [(set (match_dup 6)
+ (MINMAX:SI (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC CC_REG))])]
+ {
+ metag_dsp_peephole2_rrr_mov_convert (operands);
+ })
+
+;; END DSP Peephole2s
+
diff -Nur gcc-4.2.4.orig/gcc/config/metag/dsppeephole.md gcc-4.2.4/gcc/config/metag/dsppeephole.md
--- gcc-4.2.4.orig/gcc/config/metag/dsppeephole.md 1969-12-31 18:00:00.000000000 -0600
+++ gcc-4.2.4/gcc/config/metag/dsppeephole.md 2015-07-03 18:46:05.745283542 -0500
@@ -0,0 +1,434 @@
+;; Machine description for GNU compiler,
+;; Imagination Technologies Meta version.
+;; Copyright (C) 2008
+;; Imagination Technologies Ltd
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it under
+;; the terms of the GNU General Public License as published by the Free
+;; Software Foundation; either version 3, or (at your option) any later
+;; version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+;; for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; .
+
+;; READ THIS...
+
+;; DSP peephole transformations are mostly templated. There are 3 templates:
+;; 1) 3OPREG - This is the set of operations that have 3 register operands
+;; 2 input and 1 output.
+;; 2) 3OPIMM16 - This is the set of operations that have 3 operands
+;; 1 register input, 1 16 bit immediate input, 1 register output
+;; 2) 3OPIMM5 - This is the set of operations that have 3 operands
+;; 1 register input, 1 5 bit immediate input, 1 register output
+
+;; Special code attributes:
+
+;;
+;; Indicates if an insn code has commutative input operands.
+;;
+;; Special immediate conditions for dual unit operations.
+;;
+;; The name of the insn suitable for use in rtl generation.
+;;
+;; The assembler nmemonic for the given insn code.
+
+;; Dual unit conditions:
+
+;; The conditions for all DSP transformations are checked in the functions
+;; called metag_dsp_xxxxxxx_operands. These functions check that the operands
+;; in one instruction are an exact mirror of the operands of another
+;; instruction.
+;; For example metag_dsp_rrr_operands returns true for the following 2
+;; instructions regardless of which order they appear (D1 or D0 first):
+;;
+;; (set (reg D0Re0 [D0.0])
+;; (operation (reg D0Ar6 [D0.1])
+;; (reg D0Ar4 (D0.2])))
+;; (set (reg D1Re0 [D1.0])
+;; (operation (reg D1Ar5 [D1.1])
+;; (reg D1Ar3 (D1.2])))
+
+(define_peephole
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" "")))
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" "")))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rrr_operands (operands, )"
+ "DL\\t\\t%0, %1, %2\\t%@ (*\\t%3, %4, %5)"
+ [(set_attr "type" "fast")])
+
+(define_peephole
+ [(set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" "")))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" "")))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rrr_operands (operands, )"
+ "DL\\t\\t%3, %4, %5\\t%@ (*\\t%0, %1, %2)"
+ [(set_attr "type" "fast")])
+
+(define_peephole
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPIMM16:SI (match_dup 0)
+ (match_operand:SI 1 "metag_16bit_op" "")))
+ (set (match_operand:SI 2 "metag_datareg_op" "")
+ (3OPIMM16:SI (match_dup 2)
+ (match_dup 1)))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_ri16_operands (operands)
+ "
+ "DL\\t\\t%0, %0, %1\\t%@ (*\\t%2, %2, %1)"
+ [(set_attr "type" "fast")])
+
+(define_peephole
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_5bit_op" "")))
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_dup 2)))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rri5_operands (operands)
+ "
+ "DL\\t\\t%0, %1, %2\\t%@ (*\\t%3, %4, %2)"
+ [(set_attr "type" "fast")])
+
+;; DSP MIN/MAX
+
+(define_peephole
+ [(parallel
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (MINMAX:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])
+ (parallel
+ [(set (match_operand:SI 3 "metag_datareg_op" "")
+ (MINMAX:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rrr_operands (operands, true)"
+ "DL\\t\\t%0, %1, %2\\t%@ (*\\t%3, %4, %5)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "ccx")])
+
+;; DSP ABS peephole
+
+(define_peephole
+ [(parallel
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (abs:SI (match_operand:SI 1 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])
+ (parallel
+ [(set (match_operand:SI 2 "metag_datareg_op" "")
+ (abs:SI (match_operand:SI 3 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rr_operands (operands)"
+ "DL\\tABS\\t%0, %1\\t%@ *ABS\\t%2, %3)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "ccx")])
+
+;; DSP MOV peephole
+
+(define_peephole
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (match_operand:SI 1 "metag_datareg_op" ""))
+ (set (match_operand:SI 2 "metag_datareg_op" "")
+ (match_operand:SI 3 "metag_datareg_op" ""))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rr_operands (operands)"
+ "DL\\tMOV\\t%0, %1\\t%@ (*MOV\\t%2, %3)"
+ [(set_attr "type" "fast")])
+
+;; DSP Math with flags peepholes
+
+(define_peephole
+ [(parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPREG:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPREG:SI (match_dup 1)
+ (match_dup 2)))])
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" "")))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rrr_operands (operands, )"
+ "DL\\tS\\t%0, %1, %2\\t%@ (*S\\t%3, %4, %5)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "set")])
+
+(define_peephole
+ [(set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" "")))
+ (parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPREG:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPREG:SI (match_dup 1)
+ (match_dup 2)))])]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rrr_operands (operands, )"
+ "DL\\tS\\t%0, %1, %2\\t%@ (*S\\t%3, %4, %5)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "set")])
+
+(define_peephole
+ [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPREG:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" "")))
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPREG:SI (match_dup 4)
+ (match_dup 5)))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rrr_operands (operands, )"
+ "DL\\tS\\t%3, %4, %5\\t%@ (*S\\t%0, %1, %2)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "set")])
+
+(define_peephole
+ [(parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM16:SI (match_operand:SI 0 "metag_datareg_op" "")
+ (match_operand:SI 1 "metag_16bit_op" ""))
+ (const_int 0)))
+ (set (match_dup 0)
+ (3OPIMM16:SI (match_dup 0)
+ (match_dup 1)))])
+ (set (match_operand:SI 2 "metag_datareg_op" "")
+ (3OPIMM16:SI (match_dup 2)
+ (match_dup 1)))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_ri16_operands (operands)
+ "
+ "DL\\tS\\t%0, %0, %1\\t%@ (*S\\t%2, %2, %1)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "set")])
+
+(define_peephole
+ [(parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM5:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_5bit_op" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_dup 1)
+ (match_dup 2)))])
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_dup 2)))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rri5_operands (operands)
+ "
+ "DL\\tS\\t%0, %1, %2\\t%@ (*S\\t%3, %4, %2)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "set")])
+
+(define_peephole
+ [(set (match_operand:SI 2 "metag_datareg_op" "")
+ (3OPIMM16:SI (match_dup 2)
+ (match_operand:SI 1 "metag_16bit_op" "")))
+ (parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM16:SI (match_operand:SI 0 "metag_datareg_op" "")
+ (match_dup 1))
+ (const_int 0)))
+ (set (match_dup 0)
+ (3OPIMM16:SI (match_dup 0)
+ (match_dup 1)))])]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_ri16_operands (operands)
+ "
+ "DL\\tS\\t%0, %0, %1\\t%@ (*S\\t%2, %2, %1)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "set")])
+
+(define_peephole
+ [(set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_5bit_op" "")))
+ (parallel [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM5:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_dup 2))
+ (const_int 0)))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_dup 1)
+ (match_dup 2)))])]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rri5_operands (operands)
+ "
+ "DL\\tS\\t%0, %1, %2\\t%@ (*S\\t%3, %4, %2)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "set")])
+
+(define_peephole
+ [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM16:SI (match_operand:SI 2 "metag_datareg_op" "")
+ (match_operand:SI 1 "metag_16bit_op" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPIMM16:SI (match_dup 0)
+ (match_dup 1)))
+ (set (match_dup 2)
+ (3OPIMM16:SI (match_dup 2)
+ (match_dup 1)))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_ri16_operands (operands)
+ "
+ "DL\\tS\\t%2, %2, %1\\t%@ (*S\\t%0, %0, %1)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "set")])
+
+(define_peephole
+ [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM5:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_5bit_op" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_dup 2)))
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_dup 4)
+ (match_dup 2)))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rri5_operands (operands)
+ "
+ "DL\\tS\\t%3, %4, %2\\t%@ (*S\\t%0, %1, %2)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "set")])
+
+(define_peephole
+ [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM16:SI (match_operand:SI 2 "metag_datareg_op" "")
+ (match_operand:SI 1 "metag_16bit_op" ""))
+ (const_int 0)))
+ (set (match_dup 2)
+ (3OPIMM16:SI (match_dup 2)
+ (match_dup 1)))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPIMM16:SI (match_dup 0)
+ (match_dup 1)))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_ri16_operands (operands)
+ "
+ "DL\\tS\\t%2, %2, %1\\t%@ (*S\\t%0, %0, %1)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "set")])
+
+(define_peephole
+ [(set (reg:CC_NOOV CC_REG)
+ (compare:CC_NOOV
+ (3OPIMM5:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_5bit_op" ""))
+ (const_int 0)))
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_dup 4)
+ (match_dup 2)))
+ (set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPIMM5:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_dup 2)))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rri5_operands (operands)
+ "
+ "DL\\tS\\t%3, %4, %2\\t%@ (*S\\t%0, %1, %2)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "set")])
+
+;; DSP OP + MOV
+
+(define_peephole
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" "")))
+ (set (match_operand:SI 3 "metag_datareg_op" "")
+ (3OPREG:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" "")))
+ (set (match_operand:SI 6 "metag_datareg_op" "")
+ (match_dup 0))
+ (set (match_operand:SI 7 "metag_datareg_op" "")
+ (match_dup 3))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rrr_mov_operands (operands, )
+ && dead_or_set_p (PREV_INSN (insn), operands[0])
+ && dead_or_set_p (insn, operands[3])"
+ "DL\\t\\t%6, %1, %2\\t%@ (*\\t%7, %4, %5)"
+ [(set_attr "type" "fast")])
+
+;; DSP ABS + MOV
+
+(define_peephole
+ [(parallel
+ [(set (match_operand:SI 0 "metag_reg_nofloat_op" "")
+ (abs:SI (match_operand:SI 1 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])
+ (set (match_operand:SI 4 "metag_datareg_op" "")
+ (match_dup 0))
+ (parallel
+ [(set (match_operand:SI 2 "metag_reg_nofloat_op" "")
+ (abs:SI (match_operand:SI 3 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])
+ (set (match_operand:SI 5 "metag_datareg_op" "")
+ (match_dup 2))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rr_rr_mov_operands (operands)
+ && dead_or_set_p (PREV_INSN (PREV_INSN (insn)), operands[0])
+ && dead_or_set_p (insn, operands[2])"
+ "DL\\tABS\\t%4, %1\\t%@ (*ABS\\t%5, %2)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "ccx")])
+
+;; DSP MIN/MAX + MOV
+
+(define_peephole
+ [(parallel
+ [(set (match_operand:SI 0 "metag_datareg_op" "")
+ (MINMAX:SI (match_operand:SI 1 "metag_datareg_op" "")
+ (match_operand:SI 2 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])
+ (set (match_operand:SI 6 "metag_datareg_op" "")
+ (match_dup 0))
+ (parallel
+ [(set (match_operand:SI 3 "metag_datareg_op" "")
+ (MINMAX:SI (match_operand:SI 4 "metag_datareg_op" "")
+ (match_operand:SI 5 "metag_datareg_op" "")))
+ (clobber (reg:CC CC_REG))])
+ (set (match_operand:SI 7 "metag_datareg_op" "")
+ (match_dup 3))]
+ "TARGET_DSP && !metag_cond_exec_p ()
+ && metag_dsp_rrr_mov_operands (operands, )
+ && dead_or_set_p (PREV_INSN (PREV_INSN (insn)), operands[0])
+ && dead_or_set_p (insn, operands[3])"
+ "DL\\t\\t%6, %1, %2\\t%@ (*\\r%7, %4, %5)"
+ [(set_attr "type" "fast")
+ (set_attr "ccstate" "ccx")])
+
+;; END DSP Peepholes
+
diff -Nur gcc-4.2.4.orig/gcc/config/metag/elf.h gcc-4.2.4/gcc/config/metag/elf.h
--- gcc-4.2.4.orig/gcc/config/metag/elf.h 1969-12-31 18:00:00.000000000 -0600
+++ gcc-4.2.4/gcc/config/metag/elf.h 2015-07-03 18:46:05.745283542 -0500
@@ -0,0 +1,84 @@
+/* Definitions of target machine for GNU compiler,
+ for Meta Linux-based GNU systems.
+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
+ Free Software Foundation, Inc.
+ Contributed by Imagination Technologies Ltd (toolkit@metagence.com)
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+. */
+
+#ifndef OBJECT_FORMAT_ELF
+#error elf.h included before elfos.h
+#endif
+
+#undef BSS_SECTION_ASM_OP
+
+/* Dots in labels are not allowed. */
+
+#define NO_DOT_IN_LABEL 1
+
+#define ASM_PN_FORMAT "%s___%lu"
+
+#undef DBX_DEBUGGING_INFO
+
+#undef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+
+#undef ASM_FINAL_SPEC
+
+#ifdef MINIM_DEFAULT
+#define DEFAULT_MINIM_LINK_SPEC "%{!mno-minim:%{mmetac=2.1:--minim}} "
+#else
+#define DEFAULT_MINIM_LINK_SPEC
+#endif
+
+#ifdef METAG_LINK_GLOBAL
+#define LINK_MACHINE_TYPE "-m elf32metag_global "
+#else
+#define LINK_MACHINE_TYPE "-m elf32metag "
+#endif
+
+#undef LINK_SPEC
+#define LINK_SPEC \
+ LINK_MACHINE_TYPE \
+ "%{shared:-shared} " \
+ "-init=__init -fini=__fini " \
+ "%{mminim:%{mmetac=2.1:--minim}%{!mmetac=2.1:%eMiniM mode is only available on a META 2.1}} "\
+ DEFAULT_MINIM_LINK_SPEC \
+ "%{!shared: " \
+ "%{!static: " \
+ "%{rdynamic:-export-dynamic} " \
+ "%{!dynamic-linker:-dynamic-linker %(elf_dynamic_linker)}} " \
+ "%{static:-static}} "
+
+#ifndef ASM_COMMENT_START
+#define ASM_COMMENT_START "!"
+#endif
+
+#define ASM_IDENTIFY_LANGUAGE(FILE) \
+ fprintf (FILE, "%s \"GCC (%s) %s\"\n", IDENT_ASM_OP, \
+ lang_identify (), version_string)
+
+
+#undef ASM_OUTPUT_CASE_LABEL
+
+/* For PIC code we need to explicitly specify (PLT) and (GOT) relocs. */
+#define NEED_PLT_RELOC flag_pic
+#define NEED_GOT_RELOC flag_pic
+
+#ifndef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "-D__ELF__"
+#endif
diff -Nur gcc-4.2.4.orig/gcc/config/metag/fp-hard-bit.c gcc-4.2.4/gcc/config/metag/fp-hard-bit.c
--- gcc-4.2.4.orig/gcc/config/metag/fp-hard-bit.c 1969-12-31 18:00:00.000000000 -0600
+++ gcc-4.2.4/gcc/config/metag/fp-hard-bit.c 2015-07-03 18:46:05.745283542 -0500
@@ -0,0 +1,1756 @@
+/* This is a software floating point library which can be used
+ for targets without hardware floating point.
+ Copyright (C) 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003,
+ 2004, 2005, 2009 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+. */
+
+/* This implements IEEE 754 format arithmetic, but does not provide a
+ mechanism for setting the rounding mode, or for generating or handling
+ exceptions.
+
+ The original code by Steve Chamberlain, hacked by Mark Eichin and Jim
+ Wilson, all of Cygnus Support. */
+
+/* The intended way to use this file is to make two copies, add `#define FLOAT'
+ to one copy, then compile both copies and add them to libgcc.a. */
+
+#include "tconfig.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "config/fp-bit.h"
+
+/* The following macros can be defined to change the behavior of this file:
+ FLOAT: Implement a `float', aka SFmode, fp library. If this is not
+ defined, then this file implements a `double', aka DFmode, fp library.
+ FLOAT_ONLY: Used with FLOAT, to implement a `float' only library, i.e.
+ don't include float->double conversion which requires the double library.
+ This is useful only for machines which can't support doubles, e.g. some
+ 8-bit processors.
+ CMPtype: Specify the type that floating point compares should return.
+ This defaults to SItype, aka int.
+ US_SOFTWARE_GOFAST: This makes all entry points use the same names as the
+ US Software goFast library.
+ _DEBUG_BITFLOAT: This makes debugging the code a little easier, by adding
+ two integers to the FLO_union_type.
+ NO_DENORMALS: Disable handling of denormals.
+ NO_NANS: Disable nan and infinity handling
+ SMALL_MACHINE: Useful when operations on QIs and HIs are faster
+ than on an SI */
+
+/* We don't currently support extended floats (long doubles) on machines
+ without hardware to deal with them.
+
+ These stubs are just to keep the linker from complaining about unresolved
+ references which can be pulled in from libio & libstdc++, even if the
+ user isn't using long doubles. However, they may generate an unresolved
+ external to abort if abort is not used by the function, and the stubs
+ are referenced from within libc, since libgcc goes before and after the
+ system library. */
+
+#ifdef DECLARE_LIBRARY_RENAMES
+ DECLARE_LIBRARY_RENAMES
+#endif
+
+#ifdef EXTENDED_FLOAT_STUBS
+extern void abort (void);
+void __extendsfxf2 (void) { abort(); }
+void __extenddfxf2 (void) { abort(); }
+void __truncxfdf2 (void) { abort(); }
+void __truncxfsf2 (void) { abort(); }
+void __fixxfsi (void) { abort(); }
+void __floatsixf (void) { abort(); }
+void __addxf3 (void) { abort(); }
+void __subxf3 (void) { abort(); }
+void __mulxf3 (void) { abort(); }
+void __divxf3 (void) { abort(); }
+void __negxf2 (void) { abort(); }
+void __eqxf2 (void) { abort(); }
+void __nexf2 (void) { abort(); }
+void __gtxf2 (void) { abort(); }
+void __gexf2 (void) { abort(); }
+void __lexf2 (void) { abort(); }
+void __ltxf2 (void) { abort(); }
+
+void __extendsftf2 (void) { abort(); }
+void __extenddftf2 (void) { abort(); }
+void __trunctfdf2 (void) { abort(); }
+void __trunctfsf2 (void) { abort(); }
+void __fixtfsi (void) { abort(); }
+void __floatsitf (void) { abort(); }
+void __addtf3 (void) { abort(); }
+void __subtf3 (void) { abort(); }
+void __multf3 (void) { abort(); }
+void __divtf3 (void) { abort(); }
+void __negtf2 (void) { abort(); }
+void __eqtf2 (void) { abort(); }
+void __netf2 (void) { abort(); }
+void __gttf2 (void) { abort(); }
+void __getf2 (void) { abort(); }
+void __letf2 (void) { abort(); }
+void __lttf2 (void) { abort(); }
+#else /* !EXTENDED_FLOAT_STUBS, rest of file */
+
+/* IEEE "special" number predicates */
+
+#ifdef NO_NANS
+
+#define nan() 0
+#define isnan(x) 0
+#define isinf(x) 0
+#else
+
+#if defined L_thenan_sf
+const fp_number_type __thenan_sf = { CLASS_SNAN, 0, 0, {(fractype) 0} };
+#elif defined L_thenan_df
+const fp_number_type __thenan_df = { CLASS_SNAN, 0, 0, {(fractype) 0} };
+#elif defined L_thenan_tf
+const fp_number_type __thenan_tf = { CLASS_SNAN, 0, 0, {(fractype) 0} };
+#elif defined TFLOAT
+extern const fp_number_type __thenan_tf;
+#elif defined FLOAT
+extern const fp_number_type __thenan_sf;
+#else
+extern const fp_number_type __thenan_df;
+#endif
+
+INLINE
+static fp_number_type *
+nan (void)
+{
+ /* Discard the const qualifier... */
+#ifdef TFLOAT
+ return (fp_number_type *) (& __thenan_tf);
+#elif defined FLOAT
+ return (fp_number_type *) (& __thenan_sf);
+#else
+ return (fp_number_type *) (& __thenan_df);
+#endif
+}
+
+INLINE
+static int
+isnan ( fp_number_type * x)
+{
+ return __builtin_expect (x->class == CLASS_SNAN || x->class == CLASS_QNAN,
+ 0);
+}
+
+INLINE
+static int
+isinf ( fp_number_type * x)
+{
+ return __builtin_expect (x->class == CLASS_INFINITY, 0);
+}
+
+#endif /* NO_NANS */
+
+INLINE
+static int
+iszero ( fp_number_type * x)
+{
+ return x->class == CLASS_ZERO;
+}
+
+INLINE
+static void
+flip_sign ( fp_number_type * x)
+{
+ x->sign = !x->sign;
+}
+
+/* Count leading zeroes in N. */
+INLINE
+static int
+clzusi (USItype n)
+{
+ extern int __clzsi2 (USItype);
+ if (sizeof (USItype) == sizeof (unsigned int))
+ return __builtin_clz (n);
+ else if (sizeof (USItype) == sizeof (unsigned long))
+ return __builtin_clzl (n);
+ else if (sizeof (USItype) == sizeof (unsigned long long))
+ return __builtin_clzll (n);
+ else
+ return __clzsi2 (n);
+}
+
+extern FLO_type pack_d ( fp_number_type * );
+
+#if defined(L_pack_df) || defined(L_pack_sf) || defined(L_pack_tf)
+FLO_type
+pack_d ( fp_number_type * src)
+{
+ FLO_union_type dst;
+ fractype fraction = src->fraction.ll; /* wasn't unsigned before? */
+ int sign = src->sign;
+ int exp = 0;
+
+ if (LARGEST_EXPONENT_IS_NORMAL (FRAC_NBITS) && (isnan (src) || isinf (src)))
+ {
+ /* We can't represent these values accurately. By using the
+ largest possible magnitude, we guarantee that the conversion
+ of infinity is at least as big as any finite number. */
+ exp = EXPMAX;
+ fraction = ((fractype) 1 << FRACBITS) - 1;
+ }
+ else if (isnan (src))
+ {
+ exp = EXPMAX;
+ if (src->class == CLASS_QNAN || 1)
+ {
+#ifdef QUIET_NAN_NEGATED
+ fraction |= QUIET_NAN - 1;
+#else
+ fraction |= QUIET_NAN;
+#endif
+ }
+ }
+ else if (isinf (src))
+ {
+ exp = EXPMAX;
+ fraction = 0;
+ }
+ else if (iszero (src))
+ {
+ exp = 0;
+ fraction = 0;
+ }
+ else if (fraction == 0)
+ {
+ exp = 0;
+ }
+ else
+ {
+ if (__builtin_expect (src->normal_exp < NORMAL_EXPMIN, 0))
+ {
+#ifdef NO_DENORMALS
+ /* Go straight to a zero representation if denormals are not
+ supported. The denormal handling would be harmless but
+ isn't unnecessary. */
+ exp = 0;
+ fraction = 0;
+#else /* NO_DENORMALS */
+ /* This number's exponent is too low to fit into the bits
+ available in the number, so we'll store 0 in the exponent and
+ shift the fraction to the right to make up for it. */
+
+ int shift = NORMAL_EXPMIN - src->normal_exp;
+
+ exp = 0;
+
+ if (shift > FRAC_NBITS - NGARDS)
+ {
+ /* No point shifting, since it's more that 64 out. */
+ fraction = 0;
+ }
+ else
+ {
+ int lowbit = (fraction & (((fractype)1 << shift) - 1)) ? 1 : 0;
+ fraction = (fraction >> shift) | lowbit;
+ }
+ if ((fraction & GARDMASK) == GARDMSB)
+ {
+ if ((fraction & (1 << NGARDS)))
+ fraction += GARDROUND + 1;
+ }
+ else
+ {
+ /* Add to the guards to round up. */
+ fraction += GARDROUND;
+ }
+ /* Perhaps the rounding means we now need to change the
+ exponent, because the fraction is no longer denormal. */
+ if (fraction >= IMPLICIT_1)
+ {
+ exp += 1;
+ }
+ fraction >>= NGARDS;
+#endif /* NO_DENORMALS */
+ }
+ else if (!LARGEST_EXPONENT_IS_NORMAL (FRAC_NBITS)
+ && __builtin_expect (src->normal_exp > EXPBIAS, 0))
+ {
+ exp = EXPMAX;
+ fraction = 0;
+ }
+ else
+ {
+ exp = src->normal_exp + EXPBIAS;
+ if (!ROUND_TOWARDS_ZERO)
+ {
+ /* IF the gard bits are the all zero, but the first, then we're
+ half way between two numbers, choose the one which makes the
+ lsb of the answer 0. */
+ if ((fraction & GARDMASK) == GARDMSB)
+ {
+ if (fraction & (1 << NGARDS))
+ fraction += GARDROUND + 1;
+ }
+ else
+ {
+ /* Add a one to the guards to round up */
+ fraction += GARDROUND;
+ }
+ if (fraction >= IMPLICIT_2)
+ {
+ fraction >>= 1;
+ exp += 1;
+ }
+ }
+ fraction >>= NGARDS;
+
+ if (LARGEST_EXPONENT_IS_NORMAL (FRAC_NBITS) && exp > EXPMAX)
+ {
+ /* Saturate on overflow. */
+ exp = EXPMAX;
+ fraction = ((fractype) 1 << FRACBITS) - 1;
+ }
+ }
+ }
+
+ /* We previously used bitfields to store the number, but this doesn't
+ handle little/big endian systems conveniently, so use shifts and
+ masks */
+#ifdef FLOAT_BIT_ORDER_MISMATCH
+ dst.bits.fraction = fraction;
+ dst.bits.exp = exp;
+ dst.bits.sign = sign;
+#else
+# if defined TFLOAT && defined HALFFRACBITS
+ {
+ halffractype high, low, unity;
+ int lowsign, lowexp;
+
+ unity = (halffractype) 1 << HALFFRACBITS;
+
+ /* Set HIGH to the high double's significand, masking out the implicit 1.
+ Set LOW to the low double's full significand. */
+ high = (fraction >> (FRACBITS - HALFFRACBITS)) & (unity - 1);
+ low = fraction & (unity * 2 - 1);
+
+ /* Get the initial sign and exponent of the low double. */
+ lowexp = exp - HALFFRACBITS - 1;
+ lowsign = sign;
+
+ /* HIGH should be rounded like a normal double, making |LOW| <=
+ 0.5 ULP of HIGH. Assume round-to-nearest. */
+ if (exp < EXPMAX)
+ if (low > unity || (low == unity && (high & 1) == 1))
+ {
+ /* Round HIGH up and adjust LOW to match. */
+ high++;
+ if (high == unity)
+ {
+ /* May make it infinite, but that's OK. */
+ high = 0;
+ exp++;
+ }
+ low = unity * 2 - low;
+ lowsign ^= 1;
+ }
+
+ high |= (halffractype) exp << HALFFRACBITS;
+ high |= (halffractype) sign << (HALFFRACBITS + EXPBITS);
+
+ if (exp == EXPMAX || exp == 0 || low == 0)
+ low = 0;
+ else
+ {
+ while (lowexp > 0 && low < unity)
+ {
+ low <<= 1;
+ lowexp--;
+ }
+
+ if (lowexp <= 0)
+ {
+ halffractype roundmsb, round;
+ int shift;
+
+ shift = 1 - lowexp;
+ roundmsb = (1 << (shift - 1));
+ round = low & ((roundmsb << 1) - 1);
+
+ low >>= shift;
+ lowexp = 0;
+
+ if (round > roundmsb || (round == roundmsb && (low & 1) == 1))
+ {
+ low++;
+ if (low == unity)
+ /* LOW rounds up to the smallest normal number. */
+ lowexp++;
+ }
+ }
+
+ low &= unity - 1;
+ low |= (halffractype) lowexp << HALFFRACBITS;
+ low |= (halffractype) lowsign << (HALFFRACBITS + EXPBITS);
+ }
+ dst.value_raw = ((fractype) high << HALFSHIFT) | low;
+ }
+# else
+ dst.value_raw = fraction & ((((fractype)1) << FRACBITS) - (fractype)1);
+ dst.value_raw |= ((fractype) (exp & ((1 << EXPBITS) - 1))) << FRACBITS;
+ dst.value_raw |= ((fractype) (sign & 1)) << (FRACBITS | EXPBITS);
+# endif
+#endif
+
+#if defined(FLOAT_WORD_ORDER_MISMATCH) && !defined(FLOAT)
+#ifdef TFLOAT
+ {
+ qrtrfractype tmp1 = dst.words[0];
+ qrtrfractype tmp2 = dst.words[1];
+ dst.words[0] = dst.words[3];
+ dst.words[1] = dst.words[2];
+ dst.words[2] = tmp2;
+ dst.words[3] = tmp1;
+ }
+#else
+ {
+ halffractype tmp = dst.words[0];
+ dst.words[0] = dst.words[1];
+ dst.words[1] = tmp;
+ }
+#endif
+#endif
+
+ return dst.value;
+}
+#endif
+
+#if defined(L_unpack_df) || defined(L_unpack_sf) || defined(L_unpack_tf)
+void
+unpack_d (FLO_union_type * src, fp_number_type * dst)
+{
+ /* We previously used bitfields to store the number, but this doesn't
+ handle little/big endian systems conveniently, so use shifts and
+ masks */
+ fractype fraction;
+ int exp;
+ int sign;
+
+#if defined(FLOAT_WORD_ORDER_MISMATCH) && !defined(FLOAT)
+ FLO_union_type swapped;
+
+#ifdef TFLOAT
+ swapped.words[0] = src->words[3];
+ swapped.words[1] = src->words[2];
+ swapped.words[2] = src->words[1];
+ swapped.words[3] = src->words[0];
+#else
+ swapped.words[0] = src->words[1];
+ swapped.words[1] = src->words[0];
+#endif
+ src = &swapped;
+#endif
+
+#ifdef FLOAT_BIT_ORDER_MISMATCH
+ fraction = src->bits.fraction;
+ exp = src->bits.exp;
+ sign = src->bits.sign;
+#else
+# if defined TFLOAT && defined HALFFRACBITS
+ {
+ halffractype high, low;
+
+ high = src->value_raw >> HALFSHIFT;
+ low = src->value_raw & (((fractype)1 << HALFSHIFT) - 1);
+
+ fraction = high & ((((fractype)1) << HALFFRACBITS) - 1);
+ fraction <<= FRACBITS - HALFFRACBITS;
+ exp = ((int)(high >> HALFFRACBITS)) & ((1 << EXPBITS) - 1);
+ sign = ((int)(high >> (((HALFFRACBITS + EXPBITS))))) & 1;
+
+ if (exp != EXPMAX && exp != 0 && low != 0)
+ {
+ int lowexp = ((int)(low >> HALFFRACBITS)) & ((1 << EXPBITS) - 1);
+ int lowsign = ((int)(low >> (((HALFFRACBITS + EXPBITS))))) & 1;
+ int shift;
+ fractype xlow;
+
+ xlow = low & ((((fractype)1) << HALFFRACBITS) - 1);
+ if (lowexp)
+ xlow |= (((halffractype)1) << HALFFRACBITS);
+ else
+ lowexp = 1;
+ shift = (FRACBITS - HALFFRACBITS) - (exp - lowexp);
+ if (shift > 0)
+ xlow <<= shift;
+ else if (shift < 0)
+ xlow >>= -shift;
+ if (sign == lowsign)
+ fraction += xlow;
+ else if (fraction >= xlow)
+ fraction -= xlow;
+ else
+ {
+ /* The high part is a power of two but the full number is lower.
+ This code will leave the implicit 1 in FRACTION, but we'd
+ have added that below anyway. */
+ fraction = (((fractype) 1 << FRACBITS) - xlow) << 1;
+ exp--;
+ }
+ }
+ }
+# else
+ fraction = src->value_raw & ((((fractype)1) << FRACBITS) - 1);
+ exp = ((int)(src->value_raw >> FRACBITS)) & ((1 << EXPBITS) - 1);
+ sign = ((int)(src->value_raw >> (FRACBITS + EXPBITS))) & 1;
+# endif
+#endif
+
+ dst->sign = sign;
+ if (exp == 0)
+ {
+ /* Hmm. Looks like 0 */
+ if (fraction == 0
+#ifdef NO_DENORMALS
+ || 1
+#endif
+ )
+ {
+ /* tastes like zero */
+ dst->class = CLASS_ZERO;
+ }
+ else
+ {
+ /* Zero exponent with nonzero fraction - it's denormalized,
+ so there isn't a leading implicit one - we'll shift it so
+ it gets one. */
+ dst->normal_exp = exp - EXPBIAS + 1;
+ fraction <<= NGARDS;
+
+ dst->class = CLASS_NUMBER;
+#if 1
+ while (fraction < IMPLICIT_1)
+ {
+ fraction <<= 1;
+ dst->normal_exp--;
+ }
+#endif
+ dst->fraction.ll = fraction;
+ }
+ }
+ else if (!LARGEST_EXPONENT_IS_NORMAL (FRAC_NBITS)
+ && __builtin_expect (exp == EXPMAX, 0))
+ {
+ /* Huge exponent*/
+ if (fraction == 0)
+ {
+ /* Attached to a zero fraction - means infinity */
+ dst->class = CLASS_INFINITY;
+ }
+ else
+ {
+ /* Nonzero fraction, means nan */
+#ifdef QUIET_NAN_NEGATED
+ if ((fraction & QUIET_NAN) == 0)
+#else
+ if (fraction & QUIET_NAN)
+#endif
+ {
+ dst->class = CLASS_QNAN;
+ }
+ else
+ {
+ dst->class = CLASS_SNAN;
+ }
+ /* Keep the fraction part as the nan number */
+ dst->fraction.ll = fraction;
+ }
+ }
+ else
+ {
+ /* Nothing strange about this number */
+ dst->normal_exp = exp - EXPBIAS;
+ dst->class = CLASS_NUMBER;
+ dst->fraction.ll = (fraction << NGARDS) | IMPLICIT_1;
+ }
+}
+#endif /* L_unpack_df || L_unpack_sf */
+
+#if defined(L_addsub_sf) || defined(L_addsub_df) || defined(L_addsub_tf)
+static fp_number_type *
+_fpadd_parts (fp_number_type * a,
+ fp_number_type * b,
+ fp_number_type * tmp)
+{
+ intfrac tfraction;
+
+ /* Put commonly used fields in local variables. */
+ int a_normal_exp;
+ int b_normal_exp;
+ fractype a_fraction;
+ fractype b_fraction;
+
+ if (isnan (a))
+ {
+ return a;
+ }
+ if (isnan (b))
+ {
+ return b;
+ }
+ if (isinf (a))
+ {
+ /* Adding infinities with opposite signs yields a NaN. */
+ if (isinf (b) && a->sign != b->sign)
+ return nan ();
+ return a;
+ }
+ if (isinf (b))
+ {
+ return b;
+ }
+ if (iszero (b))
+ {
+ if (iszero (a))
+ {
+ *tmp = *a;
+ tmp->sign = a->sign & b->sign;
+ return tmp;
+ }
+ return a;
+ }
+ if (iszero (a))
+ {
+ return b;
+ }
+
+ /* Got two numbers. shift the smaller and increment the exponent till
+ they're the same */
+ {
+ int diff;
+ int sdiff;
+
+ a_normal_exp = a->normal_exp;
+ b_normal_exp = b->normal_exp;
+ a_fraction = a->fraction.ll;
+ b_fraction = b->fraction.ll;
+
+ diff = a_normal_exp - b_normal_exp;
+ sdiff = diff;
+
+ if (diff < 0)
+ diff = -diff;
+ if (diff < FRAC_NBITS)
+ {
+ if (sdiff > 0)
+ {
+ b_normal_exp += diff;
+ LSHIFT (b_fraction, diff);
+ }
+ else if (sdiff < 0)
+ {
+ a_normal_exp += diff;
+ LSHIFT (a_fraction, diff);
+ }
+ }
+ else
+ {
+ /* Somethings's up.. choose the biggest */
+ if (a_normal_exp > b_normal_exp)
+ {
+ b_normal_exp = a_normal_exp;
+ b_fraction = 0;
+ }
+ else
+ {
+ a_normal_exp = b_normal_exp;
+ a_fraction = 0;
+ }
+ }
+ }
+
+ if (a->sign != b->sign)
+ {
+ if (a->sign)
+ {
+ tfraction = -a_fraction + b_fraction;
+ }
+ else
+ {
+ tfraction = a_fraction - b_fraction;
+ }
+ if (tfraction >= 0)
+ {
+ tmp->sign = 0;
+ tmp->normal_exp = a_normal_exp;
+ tmp->fraction.ll = tfraction;
+ }
+ else
+ {
+ tmp->sign = 1;
+ tmp->normal_exp = a_normal_exp;
+ tmp->fraction.ll = -tfraction;
+ }
+ /* and renormalize it */
+
+ while (tmp->fraction.ll < IMPLICIT_1 && tmp->fraction.ll)
+ {
+ tmp->fraction.ll <<= 1;
+ tmp->normal_exp--;
+ }
+ }
+ else
+ {
+ tmp->sign = a->sign;
+ tmp->normal_exp = a_normal_exp;
+ tmp->fraction.ll = a_fraction + b_fraction;
+ }
+ tmp->class = CLASS_NUMBER;
+ /* Now the fraction is added, we have to shift down to renormalize the
+ number */
+
+ if (tmp->fraction.ll >= IMPLICIT_2)
+ {
+ LSHIFT (tmp->fraction.ll, 1);
+ tmp->normal_exp++;
+ }
+ return tmp;
+
+}
+
+FLO_type
+add (FLO_type arg_a, FLO_type arg_b)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ fp_number_type b;
+ fp_number_type tmp;
+ fp_number_type *res;
+ FLO_union_type au, bu;
+
+ au.value = arg_a;
+ bu.value = arg_b;
+
+ unpack_d (&au, &a);
+ unpack_d (&bu, &b);
+
+ res = _fpadd_parts (&a, &b, &tmp);
+
+ return pack_d (res);
+#else
+ return arg_a + arg_b;
+#endif
+}
+
+FLO_type
+sub (FLO_type arg_a, FLO_type arg_b)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ fp_number_type b;
+ fp_number_type tmp;
+ fp_number_type *res;
+ FLO_union_type au, bu;
+
+ au.value = arg_a;
+ bu.value = arg_b;
+
+ unpack_d (&au, &a);
+ unpack_d (&bu, &b);
+
+ b.sign ^= 1;
+
+ res = _fpadd_parts (&a, &b, &tmp);
+
+ return pack_d (res);
+#else
+ return arg_a - arg_b;
+#endif
+}
+#endif /* L_addsub_sf || L_addsub_df */
+
+#if defined(L_mul_sf) || defined(L_mul_df) || defined(L_mul_tf)
+static inline __attribute__ ((__always_inline__)) fp_number_type *
+_fpmul_parts ( fp_number_type * a,
+ fp_number_type * b,
+ fp_number_type * tmp)
+{
+ fractype low = 0;
+ fractype high = 0;
+
+ if (isnan (a))
+ {
+ a->sign = a->sign != b->sign;
+ return a;
+ }
+ if (isnan (b))
+ {
+ b->sign = a->sign != b->sign;
+ return b;
+ }
+ if (isinf (a))
+ {
+ if (iszero (b))
+ return nan ();
+ a->sign = a->sign != b->sign;
+ return a;
+ }
+ if (isinf (b))
+ {
+ if (iszero (a))
+ {
+ return nan ();
+ }
+ b->sign = a->sign != b->sign;
+ return b;
+ }
+ if (iszero (a))
+ {
+ a->sign = a->sign != b->sign;
+ return a;
+ }
+ if (iszero (b))
+ {
+ b->sign = a->sign != b->sign;
+ return b;
+ }
+
+ /* Calculate the mantissa by multiplying both numbers to get a
+ twice-as-wide number. */
+ {
+#if defined(NO_DI_MODE) || defined(TFLOAT)
+ {
+ fractype x = a->fraction.ll;
+ fractype ylow = b->fraction.ll;
+ fractype yhigh = 0;
+ int bit;
+
+ /* ??? This does multiplies one bit at a time. Optimize. */
+ for (bit = 0; bit < FRAC_NBITS; bit++)
+ {
+ int carry;
+
+ if (x & 1)
+ {
+ carry = (low += ylow) < ylow;
+ high += yhigh + carry;
+ }
+ yhigh <<= 1;
+ if (ylow & FRACHIGH)
+ {
+ yhigh |= 1;
+ }
+ ylow <<= 1;
+ x >>= 1;
+ }
+ }
+#elif defined(FLOAT)
+ /* Multiplying two USIs to get a UDI, we're safe. */
+ {
+ UDItype answer = (UDItype)a->fraction.ll * (UDItype)b->fraction.ll;
+
+ high = answer >> BITS_PER_SI;
+ low = answer;
+ }
+#else
+ /* fractype is DImode, but we need the result to be twice as wide.
+ Assuming a widening multiply from DImode to TImode is not
+ available, build one by hand. */
+ {
+ USItype nl = a->fraction.ll;
+ USItype nh = a->fraction.ll >> BITS_PER_SI;
+ USItype ml = b->fraction.ll;
+ USItype mh = b->fraction.ll >> BITS_PER_SI;
+ UDItype pp_ll = (UDItype) ml * nl;
+ UDItype pp_hl = (UDItype) mh * nl;
+ UDItype pp_lh = (UDItype) ml * nh;
+ UDItype pp_hh = (UDItype) mh * nh;
+ UDItype res2 = 0;
+ UDItype res0 = 0;
+ UDItype ps_hh__ = pp_hl + pp_lh;
+ if (ps_hh__ < pp_hl)
+ res2 += (UDItype)1 << BITS_PER_SI;
+ pp_hl = (UDItype)(USItype)ps_hh__ << BITS_PER_SI;
+ res0 = pp_ll + pp_hl;
+ if (res0 < pp_ll)
+ res2++;
+ res2 += (ps_hh__ >> BITS_PER_SI) + pp_hh;
+ high = res2;
+ low = res0;
+ }
+#endif
+ }
+
+ tmp->normal_exp = a->normal_exp + b->normal_exp
+ + FRAC_NBITS - (FRACBITS + NGARDS);
+ tmp->sign = a->sign != b->sign;
+ while (high >= IMPLICIT_2)
+ {
+ tmp->normal_exp++;
+ if (high & 1)
+ {
+ low >>= 1;
+ low |= FRACHIGH;
+ }
+ high >>= 1;
+ }
+ while (high < IMPLICIT_1)
+ {
+ tmp->normal_exp--;
+
+ high <<= 1;
+ if (low & FRACHIGH)
+ high |= 1;
+ low <<= 1;
+ }
+
+ if (!ROUND_TOWARDS_ZERO && (high & GARDMASK) == GARDMSB)
+ {
+ if (high & (1 << NGARDS))
+ {
+ /* Because we're half way, we would round to even by adding
+ GARDROUND + 1, except that's also done in the packing
+ function, and rounding twice will lose precision and cause
+ the result to be too far off. Example: 32-bit floats with
+ bit patterns 0xfff * 0x3f800400 ~= 0xfff (less than 0.5ulp
+ off), not 0x1000 (more than 0.5ulp off). */
+ }
+ else if (low)
+ {
+ /* We're a further than half way by a small amount corresponding
+ to the bits set in "low". Knowing that, we round here and
+ not in pack_d, because there we don't have "low" available
+ anymore. */
+ high += GARDROUND + 1;
+
+ /* Avoid further rounding in pack_d. */
+ high &= ~(fractype) GARDMASK;
+ }
+ }
+ tmp->fraction.ll = high;
+ tmp->class = CLASS_NUMBER;
+ return tmp;
+}
+
+FLO_type
+multiply (FLO_type arg_a, FLO_type arg_b)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ fp_number_type b;
+ fp_number_type tmp;
+ fp_number_type *res;
+ FLO_union_type au, bu;
+
+ au.value = arg_a;
+ bu.value = arg_b;
+
+ unpack_d (&au, &a);
+ unpack_d (&bu, &b);
+
+ res = _fpmul_parts (&a, &b, &tmp);
+
+ return pack_d (res);
+#else
+ return arg_a * arg_b;
+#endif
+}
+#endif /* L_mul_sf || L_mul_df || L_mul_tf */
+
+#if defined(L_div_sf) || defined(L_div_df) || defined(L_div_tf)
+static inline __attribute__ ((__always_inline__)) fp_number_type *
+_fpdiv_parts (fp_number_type * a,
+ fp_number_type * b)
+{
+ fractype bit;
+ fractype numerator;
+ fractype denominator;
+ fractype quotient;
+
+ if (isnan (a))
+ {
+ return a;
+ }
+ if (isnan (b))
+ {
+ return b;
+ }
+
+ a->sign = a->sign ^ b->sign;
+
+ if (isinf (a) || iszero (a))
+ {
+ if (a->class == b->class)
+ return nan ();
+ return a;
+ }
+
+ if (isinf (b))
+ {
+ a->fraction.ll = 0;
+ a->normal_exp = 0;
+ return a;
+ }
+ if (iszero (b))
+ {
+ a->class = CLASS_INFINITY;
+ return a;
+ }
+
+ /* Calculate the mantissa by multiplying both 64bit numbers to get a
+ 128 bit number */
+ {
+ /* quotient =
+ ( numerator / denominator) * 2^(numerator exponent - denominator exponent)
+ */
+
+ a->normal_exp = a->normal_exp - b->normal_exp;
+ numerator = a->fraction.ll;
+ denominator = b->fraction.ll;
+
+ if (numerator < denominator)
+ {
+ /* Fraction will be less than 1.0 */
+ numerator *= 2;
+ a->normal_exp--;
+ }
+ bit = IMPLICIT_1;
+ quotient = 0;
+ /* ??? Does divide one bit at a time. Optimize. */
+ while (bit)
+ {
+ if (numerator >= denominator)
+ {
+ quotient |= bit;
+ numerator -= denominator;
+ }
+ bit >>= 1;
+ numerator *= 2;
+ }
+
+ if (!ROUND_TOWARDS_ZERO && (quotient & GARDMASK) == GARDMSB)
+ {
+ if (quotient & (1 << NGARDS))
+ {
+ /* Because we're half way, we would round to even by adding
+ GARDROUND + 1, except that's also done in the packing
+ function, and rounding twice will lose precision and cause
+ the result to be too far off. */
+ }
+ else if (numerator)
+ {
+ /* We're a further than half way by the small amount
+ corresponding to the bits set in "numerator". Knowing
+ that, we round here and not in pack_d, because there we
+ don't have "numerator" available anymore. */
+ quotient += GARDROUND + 1;
+
+ /* Avoid further rounding in pack_d. */
+ quotient &= ~(fractype) GARDMASK;
+ }
+ }
+
+ a->fraction.ll = quotient;
+ return (a);
+ }
+}
+
+FLO_type
+divide (FLO_type arg_a, FLO_type arg_b)
+{
+ fp_number_type a;
+ fp_number_type b;
+ fp_number_type *res;
+ FLO_union_type au, bu;
+
+ au.value = arg_a;
+ bu.value = arg_b;
+
+ unpack_d (&au, &a);
+ unpack_d (&bu, &b);
+
+ res = _fpdiv_parts (&a, &b);
+
+ return pack_d (res);
+}
+#endif /* L_div_sf || L_div_df */
+
+#if defined(L_fpcmp_parts_sf) || defined(L_fpcmp_parts_df) \
+ || defined(L_fpcmp_parts_tf)
+/* according to the demo, fpcmp returns a comparison with 0... thus
+ a -1
+ a==b -> 0
+ a>b -> +1
+ */
+
+int
+__fpcmp_parts (fp_number_type * a, fp_number_type * b)
+{
+#if 0
+ /* either nan -> unordered. Must be checked outside of this routine. */
+ if (isnan (a) && isnan (b))
+ {
+ return 1; /* still unordered! */
+ }
+#endif
+
+ if (isnan (a) || isnan (b))
+ {
+ return 1; /* how to indicate unordered compare? */
+ }
+ if (isinf (a) && isinf (b))
+ {
+ /* +inf > -inf, but +inf != +inf */
+ /* b \a| +inf(0)| -inf(1)
+ ______\+--------+--------
+ +inf(0)| a==b(0)| ab(1) | a==b(0)
+ -------+--------+--------
+ So since unordered must be nonzero, just line up the columns...
+ */
+ return b->sign - a->sign;
+ }
+ /* but not both... */
+ if (isinf (a))
+ {
+ return a->sign ? -1 : 1;
+ }
+ if (isinf (b))
+ {
+ return b->sign ? 1 : -1;
+ }
+ if (iszero (a) && iszero (b))
+ {
+ return 0;
+ }
+ if (iszero (a))
+ {
+ return b->sign ? 1 : -1;
+ }
+ if (iszero (b))
+ {
+ return a->sign ? -1 : 1;
+ }
+ /* now both are "normal". */
+ if (a->sign != b->sign)
+ {
+ /* opposite signs */
+ return a->sign ? -1 : 1;
+ }
+ /* same sign; exponents? */
+ if (a->normal_exp > b->normal_exp)
+ {
+ return a->sign ? -1 : 1;
+ }
+ if (a->normal_exp < b->normal_exp)
+ {
+ return a->sign ? 1 : -1;
+ }
+ /* same exponents; check size. */
+ if (a->fraction.ll > b->fraction.ll)
+ {
+ return a->sign ? -1 : 1;
+ }
+ if (a->fraction.ll < b->fraction.ll)
+ {
+ return a->sign ? 1 : -1;
+ }
+ /* after all that, they're equal. */
+ return 0;
+}
+#endif
+
+#if defined(L_compare_sf) || defined(L_compare_df) || defined(L_compoare_tf)
+CMPtype
+compare (FLO_type arg_a, FLO_type arg_b)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ fp_number_type b;
+ FLO_union_type au, bu;
+
+ au.value = arg_a;
+ bu.value = arg_b;
+
+ unpack_d (&au, &a);
+ unpack_d (&bu, &b);
+
+ return __fpcmp_parts (&a, &b);
+#else
+ if (arg_a < arg_b)
+ return -1;
+ else if (arg_a == arg_b)
+ return 0;
+ else
+ return 1;
+#endif
+}
+#endif /* L_compare_sf || L_compare_df */
+
+#ifndef US_SOFTWARE_GOFAST
+
+/* These should be optimized for their specific tasks someday. */
+
+#if defined(L_eq_sf) || defined(L_eq_df) || defined(L_eq_tf)
+CMPtype
+_eq_f2 (FLO_type arg_a, FLO_type arg_b)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ fp_number_type b;
+ FLO_union_type au, bu;
+
+ au.value = arg_a;
+ bu.value = arg_b;
+
+ unpack_d (&au, &a);
+ unpack_d (&bu, &b);
+
+ if (isnan (&a) || isnan (&b))
+ return 1; /* false, truth == 0 */
+
+ return __fpcmp_parts (&a, &b) ;
+#else
+ return compare (arg_a, arg_b);
+#endif
+}
+#endif /* L_eq_sf || L_eq_df */
+
+#if defined(L_ne_sf) || defined(L_ne_df) || defined(L_ne_tf)
+CMPtype
+_ne_f2 (FLO_type arg_a, FLO_type arg_b)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ fp_number_type b;
+ FLO_union_type au, bu;
+
+ au.value = arg_a;
+ bu.value = arg_b;
+
+ unpack_d (&au, &a);
+ unpack_d (&bu, &b);
+
+ if (isnan (&a) || isnan (&b))
+ return 1; /* true, truth != 0 */
+
+ return __fpcmp_parts (&a, &b) ;
+#else
+ return compare (arg_a, arg_b);
+#endif
+}
+#endif /* L_ne_sf || L_ne_df */
+
+#if defined(L_gt_sf) || defined(L_gt_df) || defined(L_gt_tf)
+CMPtype
+_gt_f2 (FLO_type arg_a, FLO_type arg_b)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ fp_number_type b;
+ FLO_union_type au, bu;
+
+ au.value = arg_a;
+ bu.value = arg_b;
+
+ unpack_d (&au, &a);
+ unpack_d (&bu, &b);
+
+ if (isnan (&a) || isnan (&b))
+ return -1; /* false, truth > 0 */
+
+ return __fpcmp_parts (&a, &b);
+#else
+ if (__builtin_isnan (arg_a) || __builtin_isnan (arg_b))
+ return -1;
+
+ return compare (arg_a, arg_b);
+#endif
+}
+#endif /* L_gt_sf || L_gt_df */
+
+#if defined(L_ge_sf) || defined(L_ge_df) || defined(L_ge_tf)
+CMPtype
+_ge_f2 (FLO_type arg_a, FLO_type arg_b)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ fp_number_type b;
+ FLO_union_type au, bu;
+
+ au.value = arg_a;
+ bu.value = arg_b;
+
+ unpack_d (&au, &a);
+ unpack_d (&bu, &b);
+
+ if (isnan (&a) || isnan (&b))
+ return -1; /* false, truth >= 0 */
+ return __fpcmp_parts (&a, &b) ;
+#else
+ if (__builtin_isnan (arg_a) || __builtin_isnan (arg_b))
+ return -1;
+
+ return compare (arg_a, arg_b);
+#endif
+}
+#endif /* L_ge_sf || L_ge_df */
+
+#if defined(L_lt_sf) || defined(L_lt_df) || defined(L_lt_tf)
+CMPtype
+_lt_f2 (FLO_type arg_a, FLO_type arg_b)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ fp_number_type b;
+ FLO_union_type au, bu;
+
+ au.value = arg_a;
+ bu.value = arg_b;
+
+ unpack_d (&au, &a);
+ unpack_d (&bu, &b);
+
+ if (isnan (&a) || isnan (&b))
+ return 1; /* false, truth < 0 */
+
+ return __fpcmp_parts (&a, &b);
+#else
+ return compare (arg_a, arg_b);
+#endif
+}
+#endif /* L_lt_sf || L_lt_df */
+
+#if defined(L_le_sf) || defined(L_le_df) || defined(L_le_tf)
+CMPtype
+_le_f2 (FLO_type arg_a, FLO_type arg_b)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ fp_number_type b;
+ FLO_union_type au, bu;
+
+ au.value = arg_a;
+ bu.value = arg_b;
+
+ unpack_d (&au, &a);
+ unpack_d (&bu, &b);
+
+ if (isnan (&a) || isnan (&b))
+ return 1; /* false, truth <= 0 */
+
+ return __fpcmp_parts (&a, &b) ;
+#else
+ return compare (arg_a, arg_b);
+#endif
+}
+#endif /* L_le_sf || L_le_df */
+
+#endif /* ! US_SOFTWARE_GOFAST */
+
+#if defined(L_unord_sf) || defined(L_unord_df) || defined(L_unord_tf)
+CMPtype
+_unord_f2 (FLO_type arg_a, FLO_type arg_b)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ fp_number_type b;
+ FLO_union_type au, bu;
+
+ au.value = arg_a;
+ bu.value = arg_b;
+
+ unpack_d (&au, &a);
+ unpack_d (&bu, &b);
+
+ return (isnan (&a) || isnan (&b));
+#else
+ return __builtin_isunordered (arg_a, arg_b);
+#endif
+}
+#endif /* L_unord_sf || L_unord_df */
+
+#if defined(L_si_to_sf) || defined(L_si_to_df) || defined(L_si_to_tf)
+FLO_type
+si_to_float (SItype arg_a)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type in;
+
+ in.class = CLASS_NUMBER;
+ in.sign = arg_a < 0;
+ if (!arg_a)
+ {
+ in.class = CLASS_ZERO;
+ }
+ else
+ {
+ USItype uarg;
+ int shift;
+ in.normal_exp = FRACBITS + NGARDS;
+ if (in.sign)
+ {
+ /* Special case for minint, since there is no +ve integer
+ representation for it */
+ if (arg_a == (- MAX_SI_INT - 1))
+ {
+ return (FLO_type)(- MAX_SI_INT - 1);
+ }
+ uarg = (-arg_a);
+ }
+ else
+ uarg = arg_a;
+
+ in.fraction.ll = uarg;
+ shift = clzusi (uarg) - (BITS_PER_SI - 1 - FRACBITS - NGARDS);
+ if (shift > 0)
+ {
+ in.fraction.ll <<= shift;
+ in.normal_exp -= shift;
+ }
+ }
+ return pack_d (&in);
+#else
+ return (FLO_type)arg_a;
+#endif
+}
+#endif /* L_si_to_sf || L_si_to_df */
+
+#if defined(L_usi_to_sf) || defined(L_usi_to_df) || defined(L_usi_to_tf)
+FLO_type
+usi_to_float (USItype arg_a)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type in;
+
+ in.sign = 0;
+ if (!arg_a)
+ {
+ in.class = CLASS_ZERO;
+ }
+ else
+ {
+ int shift;
+ in.class = CLASS_NUMBER;
+ in.normal_exp = FRACBITS + NGARDS;
+ in.fraction.ll = arg_a;
+
+ shift = clzusi (arg_a) - (BITS_PER_SI - 1 - FRACBITS - NGARDS);
+ if (shift < 0)
+ {
+ fractype guard = in.fraction.ll & (((fractype)1 << -shift) - 1);
+ in.fraction.ll >>= -shift;
+ in.fraction.ll |= (guard != 0);
+ in.normal_exp -= shift;
+ }
+ else if (shift > 0)
+ {
+ in.fraction.ll <<= shift;
+ in.normal_exp -= shift;
+ }
+ }
+ return pack_d (&in);
+#else
+ return (FLO_type)arg_a;
+#endif
+}
+#endif
+
+#if defined(L_sf_to_si) || defined(L_df_to_si) || defined(L_tf_to_si)
+SItype
+float_to_si (FLO_type arg_a)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ SItype tmp;
+ FLO_union_type au;
+
+ au.value = arg_a;
+ unpack_d (&au, &a);
+
+ if (iszero (&a))
+ return 0;
+ if (isnan (&a))
+ return 0;
+ /* get reasonable MAX_SI_INT... */
+ if (isinf (&a))
+ return a.sign ? (-MAX_SI_INT)-1 : MAX_SI_INT;
+ /* it is a number, but a small one */
+ if (a.normal_exp < 0)
+ return 0;
+ if (a.normal_exp > BITS_PER_SI - 2)
+ return a.sign ? (-MAX_SI_INT)-1 : MAX_SI_INT;
+ tmp = a.fraction.ll >> ((FRACBITS + NGARDS) - a.normal_exp);
+ return a.sign ? (-tmp) : (tmp);
+#else
+ return (SItype)arg_a;
+#endif
+}
+#endif /* L_sf_to_si || L_df_to_si */
+
+#if defined(L_sf_to_usi) || defined(L_df_to_usi) || defined(L_tf_to_usi)
+#if defined US_SOFTWARE_GOFAST || defined(L_tf_to_usi)
+/* While libgcc2.c defines its own __fixunssfsi and __fixunsdfsi routines,
+ we also define them for GOFAST because the ones in libgcc2.c have the
+ wrong names and I'd rather define these here and keep GOFAST CYG-LOC's
+ out of libgcc2.c. We can't define these here if not GOFAST because then
+ there'd be duplicate copies. */
+
+USItype
+float_to_usi (FLO_type arg_a)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ FLO_union_type au;
+
+ au.value = arg_a;
+ unpack_d (&au, &a);
+
+ if (iszero (&a))
+ return 0;
+ if (isnan (&a))
+ return 0;
+ /* it is a negative number */
+ if (a.sign)
+ return 0;
+ /* get reasonable MAX_USI_INT... */
+ if (isinf (&a))
+ return MAX_USI_INT;
+ /* it is a number, but a small one */
+ if (a.normal_exp < 0)
+ return 0;
+ if (a.normal_exp > BITS_PER_SI - 1)
+ return MAX_USI_INT;
+ else if (a.normal_exp > (FRACBITS + NGARDS))
+ return a.fraction.ll << (a.normal_exp - (FRACBITS + NGARDS));
+ else
+ return a.fraction.ll >> ((FRACBITS + NGARDS) - a.normal_exp);
+#else
+ return (USItype)arg_a;
+#endif
+}
+#endif /* US_SOFTWARE_GOFAST */
+#endif /* L_sf_to_usi || L_df_to_usi */
+
+#if defined(L_negate_sf) || defined(L_negate_df) || defined(L_negate_tf)
+FLO_type
+negate (FLO_type arg_a)
+{
+#if defined(TFLOAT) || (!defined(FLOAT) && !defined(METAC_FPU_DOUBLE)) || !defined(METAC_FPU_FLOAT)
+ fp_number_type a;
+ FLO_union_type au;
+
+ au.value = arg_a;
+ unpack_d (&au, &a);
+
+ flip_sign (&a);
+ return pack_d (&a);
+#else
+ return -arg_a;
+#endif
+}
+#endif /* L_negate_sf || L_negate_df */
+
+#ifdef FLOAT
+
+#if defined(L_make_sf)
+SFtype
+__make_fp(fp_class_type class,
+ unsigned int sign,
+ int exp,
+ USItype frac)
+{
+ fp_number_type in;
+
+ in.class = class;
+ in.sign = sign;
+ in.normal_exp = exp;
+ in.fraction.ll = frac;
+ return pack_d (&in);
+}
+#endif /* L_make_sf */
+
+#ifndef FLOAT_ONLY
+
+/* This enables one to build an fp library that supports float but not double.
+ Otherwise, we would get an undefined reference to __make_dp.
+ This is needed for some 8-bit ports that can't handle well values that
+ are 8-bytes in size, so we just don't support double for them at all. */
+
+#if defined(L_sf_to_df)
+DFtype
+sf_to_df (SFtype arg_a)
+{
+#if defined(TFLOAT) || !defined(METAC_FPU_DOUBLE)
+ fp_number_type in;
+ FLO_union_type au;
+
+ au.value = arg_a;
+ unpack_d (&au, &in);
+
+ return __make_dp (in.class, in.sign, in.normal_exp,
+ ((UDItype) in.fraction.ll) << F_D_BITOFF);
+#else
+ return (DFtype)arg_a;
+#endif
+}
+#endif /* L_sf_to_df */
+
+#if defined(L_sf_to_tf) && defined(TMODES)
+TFtype
+sf_to_tf (SFtype arg_a)
+{
+ fp_number_type in;
+ FLO_union_type au;
+
+ au.value = arg_a;
+ unpack_d (&au, &in);
+
+ return __make_tp (in.class, in.sign, in.normal_exp,
+ ((UTItype) in.fraction.ll) << F_T_BITOFF);
+}
+#endif /* L_sf_to_df */
+
+#endif /* ! FLOAT_ONLY */
+#endif /* FLOAT */
+
+#ifndef FLOAT
+
+extern SFtype __make_fp (fp_class_type, unsigned int, int, USItype);
+
+#if defined(L_make_df)
+DFtype
+__make_dp (fp_class_type class, unsigned int sign, int exp, UDItype frac)
+{
+ fp_number_type in;
+
+ in.class = class;
+ in.sign = sign;
+ in.normal_exp = exp;
+ in.fraction.ll = frac;
+ return pack_d (&in);
+}
+#endif /* L_make_df */
+
+#if defined(L_df_to_sf)
+SFtype
+df_to_sf (DFtype arg_a)
+{
+#if defined(TFLOAT) || !defined(METAC_FPU_DOUBLE)
+ fp_number_type in;
+ USItype sffrac;
+ FLO_union_type au;
+
+ au.value = arg_a;
+ unpack_d (&au, &in);
+
+ sffrac = in.fraction.ll >> F_D_BITOFF;
+
+ /* We set the lowest guard bit in SFFRAC if we discarded any non
+ zero bits. */
+ if ((in.fraction.ll & (((USItype) 1 << F_D_BITOFF) - 1)) != 0)
+ sffrac |= 1;
+
+ return __make_fp (in.class, in.sign, in.normal_exp, sffrac);
+#else
+ return (SFtype)arg_a;
+#endif
+}
+#endif /* L_df_to_sf */
+
+#if defined(L_df_to_tf) && defined(TMODES) \
+ && !defined(FLOAT) && !defined(TFLOAT)
+TFtype
+df_to_tf (DFtype arg_a)
+{
+ fp_number_type in;
+ FLO_union_type au;
+
+ au.value = arg_a;
+ unpack_d (&au, &in);
+
+ return __make_tp (in.class, in.sign, in.normal_exp,
+ ((UTItype) in.fraction.ll) << D_T_BITOFF);
+}
+#endif /* L_sf_to_df */
+
+#ifdef TFLOAT
+#if defined(L_make_tf)
+TFtype
+__make_tp(fp_class_type class,
+ unsigned int sign,
+ int exp,
+ UTItype frac)
+{
+ fp_number_type in;
+
+ in.class = class;
+ in.sign = sign;
+ in.normal_exp = exp;
+ in.fraction.ll = frac;
+ return pack_d (&in);
+}
+#endif /* L_make_tf */
+
+#if defined(L_tf_to_df)
+DFtype
+tf_to_df (TFtype arg_a)
+{
+ fp_number_type in;
+ UDItype sffrac;
+ FLO_union_type au;
+
+ au.value = arg_a;
+ unpack_d (&au, &in);
+
+ sffrac = in.fraction.ll >> D_T_BITOFF;
+
+ /* We set the lowest guard bit in SFFRAC if we discarded any non
+ zero bits. */
+ if ((in.fraction.ll & (((UTItype) 1 << D_T_BITOFF) - 1)) != 0)
+ sffrac |= 1;
+
+ return __make_dp (in.class, in.sign, in.normal_exp, sffrac);
+}
+#endif /* L_tf_to_df */
+
+#if defined(L_tf_to_sf)
+SFtype
+tf_to_sf (TFtype arg_a)
+{
+ fp_number_type in;
+ USItype sffrac;
+ FLO_union_type au;
+
+ au.value = arg_a;
+ unpack_d (&au, &in);
+
+ sffrac = in.fraction.ll >> F_T_BITOFF;
+
+ /* We set the lowest guard bit in SFFRAC if we discarded any non
+ zero bits. */
+ if ((in.fraction.ll & (((UTItype) 1 << F_T_BITOFF) - 1)) != 0)
+ sffrac |= 1;
+
+ return __make_fp (in.class, in.sign, in.normal_exp, sffrac);
+}
+#endif /* L_tf_to_sf */
+#endif /* TFLOAT */
+
+#endif /* ! FLOAT */
+#endif /* !EXTENDED_FLOAT_STUBS */
diff -Nur gcc-4.2.4.orig/gcc/config/metag/fp.md gcc-4.2.4/gcc/config/metag/fp.md
--- gcc-4.2.4.orig/gcc/config/metag/fp.md 1969-12-31 18:00:00.000000000 -0600
+++ gcc-4.2.4/gcc/config/metag/fp.md 2015-07-03 18:46:05.745283542 -0500
@@ -0,0 +1,1037 @@
+;; Machine description for GNU compiler,
+;; Imagination Technologies Meta version.
+;; Copyright (C) 2008
+;; Imagination Technologies Ltd
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it under
+;; the terms of the GNU General Public License as published by the Free
+;; Software Foundation; either version 3, or (at your option) any later
+;; version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+;; for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; .
+
+;;- instruction definitions
+
+;;- @@The original PO technology requires these to be ordered by speed,
+;;- @@ so that assigner will pick the fastest.
+
+;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+;;- When naming insn's (operand 0 of define_insn) be careful about using
+;;- names from other targets machine descriptions.
+
+
+
+(define_insn_and_split "*movv2sfrr"
+ [(set (match_operand:V2SF 0 "metag_fpreg_or_dreg_op" "=cx,cx,d, d")
+ (match_operand:V2SF 1 "metag_fpreg_or_dreg_op" "cx,d, cx,d"))]
+ "TARGET_FPU_SIMD"
+ "@
+ FL\\tMOV\\t%0,%1\\t%@ (*mov v2sf rr)
+ #
+ #
+ #"
+ "&& reload_completed"
+ [(set (match_dup 2)
+ (match_dup 3))
+ (set (match_dup 4)
+ (match_dup 5))]
+ {
+ operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));
+ operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]));
+ operands[4] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
+ operands[5] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
+ }
+ [(set_attr "type" "FPfast")])
+
+(define_insn_and_split "*movv2sfri"
+ [(set (match_operand:V2SF 0 "metag_fpreg_op" "=cx")
+ (match_operand:V2SF 1 "metag_vector_float_op" "vcf"))]
+ "TARGET_FPU_SIMD"
+ {
+ if (rtx_equal_p (CONST_VECTOR_ELT (operands[1], 0),
+ CONST_VECTOR_ELT (operands[1], 1)))
+ return "FL\\tMOV\\t%0,#%h1";
+ else
+ return "#";
+ }
+ "&& reload_completed
+ && !rtx_equal_p (CONST_VECTOR_ELT (operands[1], 0),
+ CONST_VECTOR_ELT (operands[1], 1))"
+ [(set (match_dup 2)
+ (match_dup 4))
+ (set (match_dup 3)
+ (match_dup 5))]
+ {
+ operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
+ operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]) + 1);
+ operands[4] = CONST_VECTOR_ELT (operands[1], 0);
+ operands[5] = CONST_VECTOR_ELT (operands[1], 1);
+ }
+ [(set_attr "type" "FPfast")])
+
+(define_expand "movv2sf"
+ [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
+ (match_operand:V2SF 1 "general_operand" ""))]
+ "TARGET_FPU_SIMD"
+ {
+ if (MEM_P (operands[0]) && !REG_P (operands[1]))
+ {
+ /* All except mem = const, mem = mem, or mem = addr can be done quickly */
+ if (!no_new_pseudos)
+ operands[1] = force_reg (V2SFmode, operands[1]);
+ }
+ else if (GET_CODE(operands[1]) == CONST_VECTOR)
+ if ( (!metag_fphalf_imm_op (CONST_VECTOR_ELT (operands[1], 0), SFmode)
+ || !metag_fphalf_imm_op (CONST_VECTOR_ELT (operands[1], 1), SFmode)))
+ {
+ emit_move_insn (gen_rtx_SUBREG (SFmode, operands[0], 0),
+ CONST_VECTOR_ELT (operands[1], 0));
+ emit_move_insn (gen_rtx_SUBREG (SFmode, operands[0], UNITS_PER_WORD),
+ CONST_VECTOR_ELT (operands[1], 1));
+ DONE;
+ }
+ }
+)
+
+;; -----------------------------------------------------------------------------
+;; | Matching V2SF load [post/pre]_[inc/dec/modify]
+;; -----------------------------------------------------------------------------
+
+(define_insn "*lod_v2sf_post_inc"
+ [(set (match_operand:V2SF 0 "metag_fpreg_op" "=cx")
+ (mem:V2SF (post_inc:SI (match_operand:SI 1 "metag_reg_nofloat_op" "+da"))))]
+ "TARGET_FPU_SIMD"
+ "F\\tGETL\\t%0, %t0, [%1++]\\t%@ (*load V2SF post_inc OK)"
+ [(set_attr "type" "load")])
+
+(define_insn "*lod_v2sf_post_dec"
+ [(set (match_operand:V2SF 0 "metag_fpreg_op" "=cx")
+ (mem:V2SF (post_dec:SI (match_operand:SI 1 "metag_reg_nofloat_op" "+da"))))]
+ "TARGET_FPU_SIMD"
+ "F\\tGETL\\t%0, %t0, [%1--]\\t%@ (*load V2SF post_dec OK)"
+ [(set_attr "type" "load")])
+
+(define_insn "*lod_v2sf_pre_inc"
+ [(set (match_operand:V2SF 0 "metag_fpreg_op" "=cx")
+ (mem:V2SF (pre_inc:SI (match_operand:SI 1 "metag_reg_nofloat_op" "+da"))))]
+ "TARGET_FPU_SIMD"
+ "F\\tGETL\\t%0, %t0, [++%1]\\t%@ (*load V2SF pre_inc OK)"
+ [(set_attr "type" "load")])
+
+(define_insn "*lod_v2sf_pre_dec"
+ [(set (match_operand:V2SF 0 "metag_fpreg_op" "=cx")
+ (mem:V2SF (pre_dec:SI (match_operand:SI 1 "metag_reg_nofloat_op" "+da"))))]
+ "TARGET_FPU_SIMD"
+ "F\\tGETL\\t%0, %t0, [--%1]\\t%@ (*load V2SF pre_dec OK)"
+ [(set_attr "type" "load")])
+
+(define_insn "*lod_v2sf_post_modify_disp"
+ [(set (match_operand:V2SF 0 "metag_fpreg_op" "=cx")
+ (mem:V2SF (post_modify:SI
+ (match_operand:SI 1 "metag_reg_nofloat_op" "+da")
+ (plus:SI (match_dup 1)
+ (match_operand:SI 2 "metag_offset6_v2sf" "O8")))))]
+ "TARGET_FPU_SIMD"
+ "F\\tGETL\\t%0, %t0, [%1+%2++]\\t%@ (*load V2SF post_modify_disp OK)"
+ [(set_attr "type" "load")])
+
+(define_insn "*lod_v2sf_post_modify_reg"
+ [(set (match_operand:V2SF 0 "metag_fpreg_op" "=cx,cx,cx,cx")
+ (mem:V2SF (post_modify:SI
+ (match_operand:SI 1 "metag_reg_nofloat_op" "+e, f, h, l")
+ (plus:SI (match_dup 1)
+ (match_operand:SI 2 "metag_reg_nofloat_op" "e, f, h, l")))))]
+ "TARGET_FPU_SIMD"
+ "F\\tGETL\\t%0, %t0, [%1+%2++]\\t%@ (*load V2SF post_modify_reg OK)"
+ [(set_attr "type" "load")])
+
+(define_insn "*lod_v2sf_pre_modify_disp"
+ [(set (match_operand:V2SF 0 "metag_fpreg_op" "=cx")
+ (mem:V2SF (pre_modify:SI
+ (match_operand:SI 1 "metag_reg_nofloat_op" "+da")
+ (plus:SI (match_dup 1)
+ (match_operand:SI 2 "metag_offset6_v2sf" "O8")))))]
+ "TARGET_FPU_SIMD"
+ "F\\tGETL\\t%0, %t0, [%1++%2]\\t%@ (*load V2SF pre_modify_disp OK)"
+ [(set_attr "type" "load")])
+
+(define_insn "*lod_v2sf_pre_modify_reg"
+ [(set (match_operand:V2SF 0 "metag_fpreg_op" "=cx,cx,cx,cx")
+ (mem:V2SF (pre_modify:SI
+ (match_operand:SI 1 "metag_reg_nofloat_op" "+e, f, h, l")
+ (plus:SI (match_dup 1)
+ (match_operand:SI 2 "metag_reg_nofloat_op" "e, f, h, l")))))]
+ "TARGET_FPU_SIMD"
+ "F\\tGETL\\t%0, %t0, [%1++%2]\\t%@ (*load V2SF pre_modify_reg OK)"
+ [(set_attr "type" "load")])
+
+;; -----------------------------------------------------------------------------
+
+(define_insn "*lod_v2sf_off6"
+ [(set (match_operand:V2SF 0 "metag_fpreg_op" "=cx")
+ (mem:V2SF (plus:SI (match_operand:SI 1 "metag_reg_nofloat_op" "da")
+ (match_operand:SI 2 "metag_offset6_v2sf" "O8"))))]
+ "TARGET_FPU_SIMD"
+ "F\\tGETL\\t%0, %t0, [%1+%2]"
+ [(set_attr "type" "load")])
+
+(define_insn "*lod_v2sf_mem"
+ [(set (match_operand:V2SF 0 "metag_datareg_op" "=d")
+ (match_operand:V2SF 1 "memory_operand" "m"))]
+ "TARGET_FPU_SIMD"
+ "GETL\\t%0, %t0, %1\\t%@ (*lod v2sf rm OK)"
+ [(set_attr "memaccess" "load")])
+
+;; -----------------------------------------------------------------------------
+;; | Matching V2SF store [post/pre]_[inc/dec/modify]
+;; -----------------------------------------------------------------------------
+
+(define_insn "*sto_v2sf_post_inc"
+ [(set (mem:V2SF (post_inc:SI (match_operand:SI 0 "metag_reg_nofloat_op" "+da")))
+ (match_operand:V2SF 1 "metag_fpreg_op" "cx"))]
+ "TARGET_FPU_SIMD"
+ "F\\tSETL\\t[%0++], %1, %t1\\t%@ (*store V2SF post_inc OK)"
+ [(set_attr "type" "fast")])
+
+(define_insn "*sto_v2sf_post_dec"
+ [(set (mem:V2SF (post_dec:SI (match_operand:SI 0 "metag_reg_nofloat_op" "+da")))
+ (match_operand:V2SF 1 "metag_fpreg_op" "cx"))]
+ "TARGET_FPU_SIMD"
+ "F\\tSETL\\t[%0--], %1, %t1\\t%@ (*store V2SF post_dec OK)"
+ [(set_attr "type" "fast")])
+
+(define_insn "*sto_v2sf_pre_inc"
+ [(set (mem:V2SF (pre_inc:SI (match_operand:SI 0 "metag_reg_nofloat_op" "+da")))
+ (match_operand:V2SF 1 "metag_fpreg_op" "cx"))]
+ "TARGET_FPU_SIMD"
+ "F\\tSETL\\t[++%0], %1, %t1\\t%@ (*store V2SF pre_inc OK)"
+ [(set_attr "type" "fast")])
+
+(define_insn "*sto_v2sf_pre_dec"
+ [(set (mem:V2SF (pre_dec:SI (match_operand:SI 0 "metag_reg_nofloat_op" "+da")))
+ (match_operand:V2SF 1 "metag_fpreg_op" "cx"))]
+ "TARGET_FPU_SIMD"
+ "F\\tSETL\\t[--%0], %1, %t1\\t%@ (*store V2SF pre_dec OK)"
+ [(set_attr "type" "fast")])
+
+(define_insn "*sto_v2sf_post_modify_disp"
+ [(set (mem:V2SF (post_modify:SI
+ (match_operand:SI 0 "metag_reg_nofloat_op" "+da")
+ (plus:SI (match_dup 0)
+ (match_operand:SI 1 "metag_offset6_v2sf" "O8"))))
+ (match_operand:V2SF 2 "metag_fpreg_op" "cx"))]
+ "TARGET_FPU_SIMD"
+ "F\\tSETL\\t[%0+%1++], %2, %t2\\t%@ (*store V2SF post_modify_disp OK)"
+ [(set_attr "type" "fast")])
+
+(define_insn "*sto_v2sf_post_modify_reg"
+ [(set (mem:V2SF (post_modify:SI
+ (match_operand:SI 0 "metag_reg_nofloat_op" "+e, f, h, l")
+ (plus:SI (match_dup 0)
+ (match_operand:SI 1 "metag_reg_nofloat_op" "e, f, h, l"))))
+ (match_operand:V2SF 2 "metag_fpreg_op" "cx,cx,cx,cx"))]
+ "TARGET_FPU_SIMD"
+ "F\\tSETL\\t[%0+%1++], %2, %t2\\t%@ (*store V2SF post_modify_reg OK)"
+ [(set_attr "type" "fast")])
+
+(define_insn "*sto_v2sf_pre_modify_disp"
+ [(set (mem:V2SF (pre_modify:SI
+ (match_operand:SI 0 "metag_reg_nofloat_op" "+da")
+ (plus:SI (match_dup 0)
+ (match_operand:SI 1 "metag_offset6_v2sf" "O8"))))
+ (match_operand:V2SF 2 "metag_fpreg_op" "cx"))]
+ "TARGET_FPU_SIMD"
+ "F\\tSETL\\t[%0++%1], %2, %t2\\t%@ (*store V2SF pre_modify_disp OK)"
+ [(set_attr "type" "fast")])
+
+(define_insn "*sto_v2sf_pre_modify_reg"
+ [(set (mem:V2SF (pre_modify:SI
+ (match_operand:SI 0 "metag_reg_nofloat_op" "+e, f, h, l")
+ (plus:SI (match_dup 0)
+ (match_operand:SI 1 "metag_reg_nofloat_op" "e, f, h, l"))))
+ (match_operand:V2SF 2 "metag_fpreg_op" "cx,cx,cx,cx"))]
+ "TARGET_FPU_SIMD"
+ "F\\tSETL\\t[%0++%1], %2, %t2\\t%@ (*store V2SF pre_modify_reg OK)"
+ [(set_attr "type" "fast")])
+
+;; -----------------------------------------------------------------------------
+
+(define_insn "*sto_v2sf_off6"
+ [(set (mem:V2SF (plus:SI (match_operand:SI 0 "metag_reg_nofloat_op" "da")
+ (match_operand:SI 1 "metag_offset6_v2sf" "O8")))
+ (match_operand:V2SF 2 "metag_fpreg_op" "cx"))]
+ "TARGET_FPU_SIMD"
+ "F\\tSETL\\t[%0+%1], %2, %t2"
+ [(set_attr "type" "fast")])
+
+(define_insn "*sto_v2sf_mem"
+ [(set (match_operand:V2SF 0 "memory_operand" "=m")
+ (match_operand:V2SF 1 "metag_datareg_op" "d"))]
+ "TARGET_FPU_SIMD"
+ "SETL\\t%0, %1, %t1\\t%@ (*sto v2sf rm OK)"
+ [(set_attr "type" "FPfast")])
+
+; Movement instructions
+
+(define_insn "abs2"
+ [(set (match_operand:FLMODES 0 "metag_fpreg_op" "=cx")
+ (abs: (match_operand: 1 "metag_fpreg_op" "cx")))]
+ ""
+ "F\\tABS%?\\t%0,%1"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+;;(define_insn "*mmovsf_d_to_f"
+;; [(match_parallel 0 "metag_mmov_valid"
+;; [(set (match_operand:SF 1 "metag_fpreg_op" "=cx")
+;; (match_operand:SF 2 "metag_datareg_op" "d" ))
+;; (set (match_operand:SF 3 "metag_fpreg_op" "=cx")
+;; (match_operand:SF 4 "metag_datareg_op" "d" ))])]
+;; "TARGET_FPU"
+;; {
+;; switch (XVECLEN(operands[0], 0))
+;; {
+;; case 2:
+;; return "F\\tMMOV\\t%1,%3,%2,%4";
+;; case 3:
+;; return "F\\tMMOV\\t%1,%3,%5,%2,%4,%6";
+;; case 4:
+;; return "F\\tMMOV\\t%1,%3,%5,%7,%2,%4,%6,%8";
+;; case 5:
+;; return "F\\tMMOV\\t%1,%3,%5,%7,%9,%2,%4,%6,%8,%10";
+;; case 6:
+;; return "F\\tMMOV\\t%1,%3,%5,%7,%9,%11,%2,%4,%6,%8,%10,%12";
+;; case 7:
+;; return "F\\tMMOV\\t%1,%3,%5,%7,%9,%11,%13,%2,%4,%6,%8,%10,%12,%14";
+;; case 8:
+;; return "F\\tMMOV\\t%1,%3,%5,%7,%9,%11,%13,%15,%2,%4,%6,%8,%10,%12,%14,%16";
+;; default:
+;; gcc_unreachable ();
+;; }
+;; })
+
+(define_insn "*mov__imm"
+ [(set (match_operand:FMODES 0 "metag_fpreg_op" "=cx")
+ (match_operand: 1 "metag_fphalf_imm_op" "ci"))]
+ ""
+ "F\\tMOV\\t%0,#%h1"
+ [(set_attr "type" "FPfast")])
+
+(define_insn "neg2"
+ [(set (match_operand:FLMODES 0 "metag_fpreg_op" "=cx")
+ (neg: (match_operand: 1 "metag_fpreg_op" "cx")))]
+ ""
+ "F\\tNEG%?\\t%0,%1"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+; TODO: PACK
+; TODO: SWAP
+
+; Comparison Operations
+
+(define_expand "cmp"
+ [(match_operand:FMODES 0 "metag_fpreg_op" "")
+ (match_operand: 1 "metag_fpreg_or_imm_op" "")]
+ ""
+ {
+ enum machine_mode mode;
+
+ /* These are processed via the conditional branch define_expand's later */
+ metag_compare_op0 = operands[0];
+ metag_compare_op1 = operands[1];
+
+ mode = GET_MODE (operands[1]);
+
+ /* Have to do register to register comparison for big constants */
+ if (CONST_DOUBLE_P (operands[1]) && operands[1] != CONST0_RTX (mode))
+ metag_compare_op1 = force_reg (mode, operands[1]);
+
+ DONE;
+ })
+
+(define_insn "*cmpsf"
+ [(set (reg:CCFP CC_REG)
+ (compare:CCFP
+ (match_operand:SF 0 "metag_fpreg_op" "cx,cx")
+ (match_operand:SF 1 "metag_fpreg_or_fpzero_imm_op" "cx,G")))]
+ "TARGET_FPU"
+ "@
+ F\\tCMP%?\\t%0,%1
+ F\\tCMP%?\\t%0,#%h1"
+ [(set_attr "type" "FPfast")])
+
+(define_insn "*cmpdf"
+ [(set (reg:CCFP CC_REG)
+ (compare:CCFP
+ (match_operand:DF 0 "metag_fpreg_op" "cx,cx")
+ (match_operand:DF 1 "metag_fpreg_or_fpzero_imm_op" "cx,G")))]
+ "TARGET_FPU && !metag_fpu_single"
+ "@
+ FD\\tCMP%?\\t%0,%1
+ FD\\tCMP%?\\t%0,#%h1"
+ [(set_attr "type" "FPfast")])
+
+(define_insn "*abscmpsf2"
+ [(set (reg:CCFP CC_REG)
+ (compare:CCFP
+ (abs:SF (match_operand:SF 0 "metag_fpreg_op" "cx,cx"))
+ (abs:SF (match_operand:SF 1 "metag_fpreg_or_fpzero_imm_op" "cx,G"))))]
+ "TARGET_FPU"
+ "@
+ FA\\tCMP%?\\t%0,%1
+ FA\\tCMP%?\\t%0,#%h1"
+ [(set_attr "type" "FPmas")])
+
+(define_insn "*abscmpdf2"
+ [(set (reg:CCFP CC_REG)
+ (compare:CCFP
+ (abs:DF (match_operand:DF 0 "metag_fpreg_op" "cx,cx"))
+ (abs:DF (match_operand:DF 1 "metag_fpreg_or_fpzero_imm_op" "cx,G"))))]
+ "TARGET_FPU && !metag_fpu_single"
+ "@
+ FDA\\tCMP%?\\t%0,%1
+ FDA\\tCMP%?\\t%0,#%h1"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+(define_insn "smax3"
+ [(set (match_operand:FLMODES 0 "metag_fpreg_op" "=cx")
+ (smax: (match_operand: 1 "metag_fpreg_op" "cx")
+ (match_operand: 2 "metag_fpreg_op" "cx")))
+ (clobber (reg:CC CC_REG))]
+ ""
+ "F\\tMAX%?\\t%0,%1,%2"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")
+ (set_attr "ccstate" "ccx")])
+
+(define_insn "smin3"
+ [(set (match_operand:FLMODES 0 "metag_fpreg_op" "=cx")
+ (smin: (match_operand: 1 "metag_fpreg_op" "cx")
+ (match_operand: 2 "metag_fpreg_op" "cx")))
+ (clobber (reg:CC CC_REG))]
+ ""
+ "F\\tMIN%?\\t%0,%1,%2"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")
+ (set_attr "ccstate" "ccx")])
+
+; Data Conversion
+(define_insn "extendsfdf2"
+ [(set (match_operand:DF 0 "metag_fpreg_op" "=cx")
+ (float_extend:DF (match_operand:SF 1 "metag_fpreg_op" "cx")))]
+ "TARGET_FPU && !metag_fpu_single"
+ "F\\tFTOD%?\\t%0,%1"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+(define_insn "truncdfsf2"
+ [(set (match_operand:SF 0 "metag_fpreg_op" "=cx")
+ (float_truncate:SF (match_operand:DF 1 "metag_fpreg_op" "cx")))]
+ "TARGET_FPU && !metag_fpu_single"
+ "F\\tDTOF%?\\t%0,%1"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+;; HFmode isnt supported at the moment but the rules would be something like:
+;;
+;;(define_insn "truncsfhf2"
+;; [(set (match_operand:HF 0 "metag_fpreg_op" "=cx")
+;; (float:HF (match_operand:SF 1 "metag_fpreg_op" "cx")))]
+;; "TARGET_FPU"
+;; "F\\tFTOH%?\\t%0,%1"
+;; )
+;;
+;;(define_insn "truncdfhf2"
+;; [(set (match_operand:HF 0 "metag_fpreg_op" "=cx")
+;; (float:HF (match_operand:DF 1 "metag_fpreg_op" "cx")))]
+;; "TARGET_FPU"
+;; "F\\tDTOH%?\\t%0,%1"
+;; )
+
+(define_insn "fix_truncsi2"
+ [(set (match_operand:SI 0 "metag_fpreg_op" "=cx")
+ (fix:SI (match_operand:FSMODES 1 "metag_fpreg_op" "cx")))]
+ ""
+ "FZ\\tTOI%?\\t%0,%1"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+(define_expand "fix_truncsfdi2"
+ [(set (match_dup 2)
+ (float_extend:DF (match_operand:SF 1 "metag_fpreg_op" "")))
+ (set (match_operand:DI 0 "metag_fpreg_op" "")
+ (fix:DI (match_dup 2)))]
+ "TARGET_FPU && !metag_fpu_single"
+ {
+ operands[2] = gen_reg_rtx (DFmode);
+ })
+
+(define_insn "fix_truncdfdi2"
+ [(set (match_operand:DI 0 "metag_fpreg_op" "=cx")
+ (fix:DI (match_operand:DF 1 "metag_fpreg_op" "cx")))]
+ "TARGET_FPU && !metag_fpu_single"
+ "FZ\\tDTOL%?\\t%0,%1"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+(define_expand "fixuns_truncsfdi2"
+ [(set (match_operand:DI 0 "metag_fpreg_op" "")
+ (unsigned_fix:DI (match_operand:SF 1 "metag_fpreg_op" "")))]
+ "TARGET_FPU && !metag_fpu_single"
+ {
+ rtx dscr = gen_reg_rtx (SImode);
+ rtx fscr = gen_reg_rtx (SFmode);
+ rtx fscr_as_si = gen_rtx_SUBREG (SImode, fscr, 0);
+ rtx fscr2 = gen_reg_rtx (SFmode);
+ rtx fdscr = gen_reg_rtx (DFmode);
+ rtx rdhi = gen_rtx_SUBREG (SImode, operands[0], 4);
+ rtx temp_operands[1];
+
+ /* single precision 2^63 is 0x5F000000 */
+ emit_move_insn (fscr_as_si,
+ gen_int_mode (0x5F000000, SImode));
+
+ /* Is input in 'difficult' range */
+ emit_insn (gen_cmpsf (operands[1], fscr));
+ gen_metag_compare (GE, temp_operands, 0);
+
+ /* Copy input to scratch */
+ emit_move_insn (fscr2, operands[1]);
+
+ /* If it is then wrap around once (note, we dont have to
+ * deal with the case where it's still difficult, C doesnt define
+ * overflow behaviour */
+ emit_insn (gen_rtx_SET (VOIDmode, fscr2,
+ gen_rtx_IF_THEN_ELSE (SFmode,
+ gen_rtx_GE (VOIDmode, temp_operands[0],
+ const0_rtx),
+ gen_rtx_MINUS (SFmode, operands[1],
+ fscr),
+ fscr2)));
+
+ /* Extend to double before DI conversion */
+ emit_insn (gen_rtx_SET (DFmode, fdscr,
+ gen_rtx_FLOAT_EXTEND (DFmode, fscr2)));
+
+ /* Convert to DI */
+ emit_insn (gen_rtx_SET (DImode, operands[0],
+ gen_rtx_FIX (DImode, fdscr)));
+
+ /* Restore truncated value from earlier */
+ emit_insn (gen_rtx_SET (SImode, dscr,
+ gen_int_mode (0x80000000, SImode)));
+ emit_insn (gen_rtx_SET (VOIDmode, rdhi,
+ gen_rtx_IF_THEN_ELSE (SImode,
+ gen_rtx_GE (VOIDmode, temp_operands[0],
+ const0_rtx),
+ gen_rtx_PLUS (SImode, rdhi,
+ dscr),
+ rdhi)));
+ DONE;
+
+ })
+
+(define_expand "fixuns_truncdfdi2"
+ [(set (match_operand:DI 0 "metag_fpreg_op" "")
+ (unsigned_fix:DI (match_operand:DF 1 "metag_fpreg_op" "")))]
+ "TARGET_FPU && !metag_fpu_single"
+ {
+ rtx dscr = gen_reg_rtx (SImode);
+ rtx fscr = gen_reg_rtx (DFmode);
+ rtx fscrlo_as_si = gen_rtx_SUBREG (SImode, fscr, 0);
+ rtx fscrhi_as_si = gen_rtx_SUBREG (SImode, fscr, 4);
+ rtx fdscr = gen_reg_rtx (DFmode);
+ rtx rdhi = gen_rtx_SUBREG (SImode, operands[0], 4);
+ rtx temp_operands[1];
+
+ /* double precision 2^63 is 0x43e00000 00000000*/
+ emit_move_insn (fscrhi_as_si,
+ gen_int_mode (0x43e00000, SImode));
+ emit_move_insn (fscrlo_as_si, const0_rtx);
+
+ /* Is input in 'difficult' range */
+ emit_insn (gen_cmpdf (operands[1], fscr));
+ gen_metag_compare (GE, temp_operands, 0);
+
+ /* Copy input to scratch */
+ emit_move_insn (fdscr, operands[1]);
+
+ /* If it is then wrap around once (note, we dont have to
+ * deal with the case where it's still difficult, C doesnt define
+ * overflow behaviour */
+ emit_insn (gen_rtx_SET (VOIDmode, fdscr,
+ gen_rtx_IF_THEN_ELSE (DFmode,
+ gen_rtx_GE (VOIDmode, temp_operands[0],
+ const0_rtx),
+ gen_rtx_MINUS (DFmode, operands[1],
+ fscr),
+ fdscr)));
+
+ /* Convert to DI */
+ emit_insn (gen_rtx_SET (DImode, operands[0],
+ gen_rtx_FIX (DImode, fdscr)));
+
+ /* Restore truncated value from earlier */
+ emit_insn (gen_rtx_SET (SImode, dscr,
+ gen_int_mode (0x80000000, SImode)));
+ emit_insn (gen_rtx_SET (VOIDmode, rdhi,
+ gen_rtx_IF_THEN_ELSE (SImode,
+ gen_rtx_GE (VOIDmode, temp_operands[0],
+ const0_rtx),
+ gen_rtx_PLUS (SImode, rdhi,
+ dscr),
+ rdhi)));
+
+ DONE;
+
+ })
+
+(define_expand "fixuns_truncsfsi2"
+ [(set (match_operand:SI 0 "metag_fpreg_op" "")
+ (unsigned_fix:SI (match_operand:SF 1 "metag_fpreg_op" "")))]
+ "TARGET_FPU && metag_fpu_single"
+ {
+ if (metag_fpu_single)
+ {
+ rtx dscr = gen_reg_rtx (SImode);
+ rtx fscr = gen_reg_rtx (SFmode);
+ rtx fscr_as_si = gen_rtx_SUBREG (SImode, fscr, 0);
+ rtx fscr2 = gen_reg_rtx (SFmode);
+ rtx temp_operands[1];
+
+ /* single precision 2^31 is 0x4F000000 */
+ emit_move_insn (fscr_as_si,
+ gen_int_mode (0x4f000000, SImode));
+
+ /* Is input in 'difficult' range */
+ emit_insn (gen_cmpsf (operands[1], fscr));
+ gen_metag_compare (GE, temp_operands, 0);
+
+ /* Copy input to scratch */
+ emit_move_insn (fscr2, operands[1]);
+
+ /* If it is then wrap around once (note, we dont have to
+ * deal with the case where it's still difficult, C doesnt define
+ * overflow behaviour */
+ emit_insn (gen_rtx_SET (VOIDmode, fscr2,
+ gen_rtx_IF_THEN_ELSE (SFmode,
+ gen_rtx_GE (VOIDmode, temp_operands[0],
+ const0_rtx),
+ gen_rtx_MINUS (SFmode, operands[1],
+ fscr),
+ fscr2)));
+
+ /* Convert to SI */
+ emit_insn (gen_rtx_SET (SImode, operands[0],
+ gen_rtx_FIX (SImode, fscr2)));
+
+ /* Restore truncated value from earlier */
+ emit_insn (gen_rtx_SET (SImode, dscr,
+ gen_int_mode (0x80000000, SImode)));
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+ gen_rtx_IF_THEN_ELSE (SImode,
+ gen_rtx_GE (VOIDmode, temp_operands[0],
+ const0_rtx),
+ gen_rtx_PLUS (SImode, operands[0],
+ dscr),
+ operands[0])));
+
+ DONE;
+ }
+ else
+ {
+ rtx op2 = gen_reg_rtx (DFmode);
+ rtx op3 = gen_reg_rtx (DImode);
+
+ emit_insn (gen_extendsfdf2 (op2, operands[1]));
+ emit_insn (gen_fix_truncdfdi2 (op3, op2));
+ emit_move_insn (operands[0], gen_rtx_SUBREG (SImode, op3, 0));
+ DONE;
+ }
+
+ })
+
+
+; DTOX, FTOX, DTOXL not supported
+(define_insn "floatsi2"
+ [(set (match_operand:FSMODES 0 "metag_fpreg_op" "=cx")
+ (float: (match_operand:SI 1 "metag_fpreg_op" "cx")))]
+ ""
+ "F\\tITO%?\\t%0,%1"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+(define_expand "floatdisf2"
+ [(set (match_dup 2)
+ (float:DF (match_operand:DI 1 "metag_fpreg_op" "")))
+ (set (match_operand:SF 0 "metag_fpreg_op" "")
+ (float_truncate:SF (match_dup 2)))]
+ "TARGET_FPU && !metag_fpu_single"
+ {
+ operands[2] = gen_reg_rtx (DFmode);
+ })
+
+(define_insn "floatdidf2"
+ [(set (match_operand:DF 0 "metag_fpreg_op" "=cx")
+ (float:DF (match_operand:DI 1 "metag_fpreg_op" "cx")))]
+ "TARGET_FPU && !metag_fpu_single"
+ "F\\tLTOD%?\\t%0,%1"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+(define_expand "floatunshi2"
+ [(set (match_dup:SI 2)
+ (zero_extend:SI (match_operand:HI 1 "metag_reg_nofloat_op" "")))
+ (set (match_operand:FMODES 0 "metag_fpreg_op" "")
+ (float: (match_dup 2)))]
+ ""
+ {
+ operands[2] = gen_reg_rtx (SImode);
+ })
+
+(define_expand "floatunssidf2"
+ [(set (match_dup 2)
+ (zero_extend:DI (match_operand:SI 1 "metag_register_op" "")))
+ (set (match_operand:DF 0 "metag_fpreg_op" "")
+ (float:DF (match_dup 2)))]
+ "TARGET_FPU && !metag_fpu_single"
+ {
+ operands[2] = gen_reg_rtx (DImode);
+ })
+
+(define_expand "floatunsdidf2"
+ [(set (match_operand:DF 0 "metag_fpreg_op" "")
+ (unsigned_float:DF (match_operand:DI 1 "metag_register_op" "")))]
+ "TARGET_FPU && !metag_fpu_single"
+ {
+ metag_expand_didf2 (operands[0], operands[1]);
+ DONE;
+ })
+
+(define_expand "floatunsdisf2"
+ [(set (match_dup 2)
+ (unsigned_float:DF (match_operand:DI 1 "metag_register_op" "")))
+ (set (match_operand:SF 0 "metag_fpreg_op" "")
+ (float_truncate:SF (match_dup 2)))]
+ "TARGET_FPU && !metag_fpu_single"
+ {
+ operands[2] = gen_reg_rtx (DFmode);
+
+ metag_expand_didf2 (operands[2], operands[1]);
+
+ emit_insn (gen_truncdfsf2 (operands[0], operands[2]));
+ DONE;
+ })
+
+(define_expand "floatunssisf2"
+ [(set (match_operand:SF 0 "metag_fpreg_op" "")
+ (unsigned_float:SF (match_operand:SI 1 "metag_register_op" "")))]
+ "TARGET_FPU && metag_fpu_single"
+ {
+ if (metag_fpu_single)
+ {
+ rtx dscr = gen_reg_rtx (SImode);
+ rtx fscr2 = gen_reg_rtx (SFmode);
+ rtx fscr2_as_si = gen_rtx_SUBREG (SImode, fscr2, 0);
+ rtx temp_operands[1];
+
+ /* Test to see if rs is in the difficult range (> 2^31) */
+ emit_move_insn (dscr, operands[1]);
+ metag_compare_op0 = gen_rtx_AND (SImode, dscr,
+ gen_int_mode (0x80000000, SImode));
+ metag_compare_op1 = const0_rtx;
+ gen_metag_compare (NE, temp_operands, 0);
+
+ /* Drop the 2^31 component */
+ emit_insn (gen_andsi3 (dscr, dscr,
+ gen_int_mode (0x7fffffff, SImode)));
+
+ /* Convert to single */
+ emit_insn (gen_floatsisf2 (operands[0], dscr));
+
+ /* Prepare 2^31 in single precision */
+ emit_move_insn (fscr2_as_si,
+ gen_int_mode (0x4f000000, SImode));
+
+ /* Add on the missing 2^31 if requried */
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+ gen_rtx_IF_THEN_ELSE (SFmode,
+ gen_rtx_NE (VOIDmode, temp_operands[0],
+ const0_rtx),
+ gen_rtx_PLUS (SFmode, operands[0], fscr2),
+ operands[0])));
+
+ DONE;
+ }
+ else
+ {
+ rtx op2 = gen_reg_rtx (DImode);
+ rtx op3 = gen_reg_rtx (DFmode);
+
+ emit_insn (gen_zero_extendsidi2 (op2, operands[1]));
+ emit_insn (gen_floatdidf2 (op3, op2));
+ emit_insn (gen_truncdfsf2 (operands[0], op3));
+ DONE;
+ }
+ })
+
+; Basic Arithmetic
+; SFmode
+(define_insn "add3"
+ [(set (match_operand:FLMODES 0 "metag_fpreg_op" "=cx")
+ (plus: (match_operand: 1 "metag_fpreg_op" "cx")
+ (match_operand: 2 "metag_fpreg_op" "cx")))]
+ ""
+ "F\\tADD%?\\t%0,%1,%2"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+(define_insn "*add_if__cxcxcxcx"
+ [(set (match_operand:FMODES 0 "metag_fpreg_op" "=cx")
+ (if_then_else:FMODES (match_operator 1 "comparison_operator"
+ [(match_operand:CCALL 2 "metag__reg" "")
+ (const_int 0)])
+ (plus:FMODES (match_operand:FMODES 3 "metag_fpreg_op" "cx")
+ (match_operand:FMODES 4 "metag_fpreg_op" "cx"))
+ (match_operand:FMODES 5 "metag_fpreg_op" "0")))]
+ ""
+ "F\\tADD%z1\\t%0,%3,%4"
+ [(set_attr "type" "FPmas")
+ (set_attr "ccstate" "xcc")])
+
+(define_insn "*nadd3"
+ [(set (match_operand:FLMODES 0 "metag_fpreg_op" "=cx")
+ (neg:
+ (plus: (match_operand: 1 "metag_fpreg_op" "cx")
+ (match_operand: 2 "metag_fpreg_op" "cx"))))]
+ ""
+ "FI\\tADD%?\\t%0,%1,%2"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+(define_insn "mul3"
+ [(set (match_operand:FLMODES 0 "metag_fpreg_op" "=cx")
+ (mult: (match_operand: 1 "metag_fpreg_op" "cx")
+ (match_operand: 2 "metag_fpreg_op" "cx")))]
+ ""
+ "F\\tMUL%?\\t%0,%1,%2"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+(define_insn "*nmul3"
+ [(set (match_operand:FLMODES 0 "metag_fpreg_op" "=cx")
+ (neg:
+ (mult: (match_operand: 1 "metag_fpreg_op" "cx")
+ (match_operand: 2 "metag_fpreg_op" "cx"))))]
+ ""
+ "FI\\tMUL%?\\t%0,%1,%2"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+(define_insn "sub3"
+ [(set (match_operand:FLMODES 0 "metag_fpreg_op" "=cx")
+ (minus: (match_operand: 1 "metag_fpreg_op" "cx")
+ (match_operand: 2 "metag_fpreg_op" "cx")))]
+ ""
+ "F\\tSUB%?\\t%0,%1,%2"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+(define_insn "*sub_if__cxcxcxcx"
+ [(set (match_operand:FMODES 0 "metag_fpreg_op" "=cx")
+ (if_then_else:FMODES (match_operator 1 "comparison_operator"
+ [(match_operand:CCALL 2 "metag__reg" "")
+ (const_int 0)])
+ (minus:FMODES (match_operand:FMODES 3 "metag_fpreg_op" "cx")
+ (match_operand:FMODES 4 "metag_fpreg_op" "cx"))
+ (match_operand:FMODES 5 "metag_fpreg_op" "0")))]
+ ""
+ "F\\tSUB%z1\\t%0,%3,%4"
+ [(set_attr "type" "FPmas")
+ (set_attr "ccstate" "xcc")])
+
+(define_insn "*nsub3"
+ [(set (match_operand:FLMODES 0 "metag_fpreg_op" "=cx")
+ (neg:
+ (minus: (match_operand: 1 "metag_fpreg_op" "cx")
+ (match_operand: 2 "metag_fpreg_op" "cx"))))]
+ ""
+ "FI\\tSUB%?\\t%0,%1,%2"
+ [(set_attr "type" "FPmas")
+ (set_attr "predicable" "yes")])
+
+
+; Extended Floating Point Insn's
+; SFmode
+
+; TODO MUZ
+(define_insn "*muladd3_fused"
+ [(set (match_operand:FLMODES 0 "metag_fpreg_op" "=cx")
+ (plus:
+ (mult: (match_operand: 1 "metag_fpreg_op" "cx")
+ (match_operand: 2 "metag_fpreg_op" "cx"))
+ (match_operand: 3 "metag_fpreg_op" "0")))]
+ ""
+ "F\\tMUZ\\t%0,%1,%2"
+ [(set_attr "type" "FPmas")])
+
+(define_insn "*muladd13_fused"
+ [(set (match_operand:FLMODES 0 "metag_fpreg_op" "=cx")
+ (plus:
+ (mult: (match_operand: 1 "metag_fpreg_op" "cx")
+ (match_operand: 2 "metag_fpreg_op" "cx"))
+ (match_operand: 3 "metag_fpone_imm_op" "H")))]
+ ""
+ "F\\tMUZ1\\t%0,%1,%2"
+ [(set_attr "type" "FPmas")])
+
+(define_insn "*mulsub3_fused"
+ [(set (match_operand:FLMODES 0 "metag_fpreg_op" "=cx")
+ (minus:
+ (mult: