diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms linux-2.6.39-rc7/arch/mips/Kbuild.platforms --- linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms 2011-05-10 04:33:54.000000000 +0200 +++ linux-2.6.39-rc7/arch/mips/Kbuild.platforms 2011-05-15 21:34:57.000000000 +0200 @@ -6,6 +6,7 @@ platforms += bcm47xx platforms += bcm63xx platforms += cavium-octeon +platforms += ar231x platforms += cobalt platforms += dec platforms += emma diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kconfig linux-2.6.39-rc7/arch/mips/Kconfig --- linux-2.6.39-rc7.orig/arch/mips/Kconfig 2011-05-10 04:33:54.000000000 +0200 +++ linux-2.6.39-rc7/arch/mips/Kconfig 2011-05-16 12:11:11.000000000 +0200 @@ -121,6 +121,21 @@ help Support for BCM63XX based boards +config ATHEROS_AR231X + bool "Atheros 231x/531x SoC support" + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT + select IRQ_CPU + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_32BIT_KERNEL + select GENERIC_GPIO + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_ZBOOT + help + Support for AR231x and AR531x based boards + config MIPS_COBALT bool "Cobalt Server" select CEVT_R4K @@ -738,6 +753,7 @@ endchoice +source "arch/mips/ar231x/Kconfig" source "arch/mips/alchemy/Kconfig" source "arch/mips/ath79/Kconfig" source "arch/mips/bcm63xx/Kconfig" diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig linux-2.6.39-rc7/arch/mips/ar231x/Kconfig --- linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/Kconfig 2011-05-15 21:34:57.000000000 +0200 @@ -0,0 +1,27 @@ +config ATHEROS_AR5312 + bool "Atheros 5312/2312+ support" + depends on ATHEROS_AR231X + default y + +config ATHEROS_AR2315 + bool "Atheros 2315+ support" + depends on ATHEROS_AR231X + select DMA_NONCOHERENT + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select GENERIC_GPIO + default y + +config ATHEROS_AR2315_PCI + bool "PCI support" + depends on ATHEROS_AR2315 + select HW_HAS_PCI + select PCI + select USB_ARCH_HAS_HCD + select USB_ARCH_HAS_OHCI + select USB_ARCH_HAS_EHCI + default n diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile linux-2.6.39-rc7/arch/mips/ar231x/Makefile --- linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/Makefile 2011-05-15 21:34:57.000000000 +0200 @@ -0,0 +1,17 @@ +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright (C) 2006 FON Technology, SL. +# Copyright (C) 2006 Imre Kaloz +# Copyright (C) 2006-2009 Felix Fietkau +# + +obj-y += board.o prom.o devices.o + +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o +obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform linux-2.6.39-rc7/arch/mips/ar231x/Platform --- linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/Platform 2011-05-15 21:34:57.000000000 +0200 @@ -0,0 +1,6 @@ +# +# Atheros AR5312/AR2312 WiSoC +# +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/ +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000 diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c --- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c 2011-05-15 21:47:07.000000000 +0200 @@ -0,0 +1,654 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. + * Copyright (C) 2006 FON Technology, SL. + * Copyright (C) 2006 Imre Kaloz + * Copyright (C) 2006 Felix Fietkau + */ + +/* + * Platform devices for Atheros SoCs + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "devices.h" +#include "ar2315.h" + +static u32 gpiointmask = 0, gpiointval = 0; + +static inline void ar2315_gpio_irq(void) +{ + u32 pend; + int bit = -1; + + /* only do one gpio interrupt at a time */ + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask; + + if (pend) { + bit = fls(pend) - 1; + pend &= ~(1 << bit); + gpiointval ^= (1 << bit); + } + + if (!pend) + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO); + + /* Enable interrupt with edge detection */ + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit)) + return; + + if (bit >= 0) + do_IRQ(AR531X_GPIO_IRQ_BASE + bit); +} + +#ifdef CONFIG_ATHEROS_AR2315_PCI +static inline void pci_abort_irq(void) +{ + ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT); +} + +static inline void pci_ack_irq(void) +{ + ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT); +} + +void ar2315_pci_irq(int irq) +{ + if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT) + pci_abort_irq(); + else { + do_IRQ(irq); + pci_ack_irq(); + } +} +#endif /* CONFIG_ATHEROS_AR2315_PCI */ + +/* + * Called when an interrupt is received, this function + * determines exactly which interrupt it was, and it + * invokes the appropriate handler. + * + * Implicitly, we also define interrupt priority by + * choosing which to dispatch first. + */ +static asmlinkage void +ar2315_irq_dispatch(void) +{ + int pending = read_c0_status() & read_c0_cause(); + + if (pending & CAUSEF_IP3) + do_IRQ(AR2315_IRQ_WLAN0_INTRS); + else if (pending & CAUSEF_IP4) + do_IRQ(AR2315_IRQ_ENET0_INTRS); +#ifdef CONFIG_ATHEROS_AR2315_PCI + else if (pending & CAUSEF_IP5) + ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI); +#endif + else if (pending & CAUSEF_IP2) { + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR); + + if (misc_intr & AR2315_ISR_SPI) + do_IRQ(AR531X_MISC_IRQ_SPI); + else if (misc_intr & AR2315_ISR_TIMER) + do_IRQ(AR531X_MISC_IRQ_TIMER); + else if (misc_intr & AR2315_ISR_AHB) + do_IRQ(AR531X_MISC_IRQ_AHB_PROC); + else if (misc_intr & AR2315_ISR_GPIO) + ar2315_gpio_irq(); + else if (misc_intr & AR2315_ISR_UART0) + do_IRQ(AR531X_MISC_IRQ_UART0); + else if (misc_intr & AR2315_ISR_WD) + do_IRQ(AR531X_MISC_IRQ_WATCHDOG); + else + do_IRQ(AR531X_MISC_IRQ_NONE); + } else if (pending & CAUSEF_IP7) + do_IRQ(AR531X_IRQ_CPU_CLOCK); +} + +static void ar2315_set_gpiointmask(int gpio, int level) +{ + u32 reg; + + reg = ar231x_read_reg(AR2315_GPIO_INT); + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M); + reg |= gpio | AR2315_GPIO_INT_LVL(level); + ar231x_write_reg(AR2315_GPIO_INT, reg); +} + +static void ar2315_gpio_intr_enable(struct irq_data *d) +{ + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; + + /* Enable interrupt with edge detection */ + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio)) + return; + + gpiointmask |= (1 << gpio); + ar2315_set_gpiointmask(gpio, 3); +} + +static void ar2315_gpio_intr_disable(struct irq_data *d) +{ + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; + + /* Disable interrupt */ + gpiointmask &= ~(1 << gpio); + ar2315_set_gpiointmask(gpio, 0); +} + +static struct irq_chip ar2315_gpio_intr_controller = { + .name = "AR2315-GPIO", + .irq_ack = ar2315_gpio_intr_disable, + .irq_mask_ack = ar2315_gpio_intr_disable, + .irq_mask = ar2315_gpio_intr_disable, + .irq_unmask = ar2315_gpio_intr_enable, +}; + +static void +ar2315_misc_intr_enable(struct irq_data *d) +{ + unsigned int imr; + + imr = ar231x_read_reg(AR2315_IMR); + switch(d->irq) { + case AR531X_MISC_IRQ_SPI: + imr |= AR2315_ISR_SPI; + break; + case AR531X_MISC_IRQ_TIMER: + imr |= AR2315_ISR_TIMER; + break; + case AR531X_MISC_IRQ_AHB_PROC: + imr |= AR2315_ISR_AHB; + break; + case AR531X_MISC_IRQ_GPIO: + imr |= AR2315_ISR_GPIO; + break; + case AR531X_MISC_IRQ_UART0: + imr |= AR2315_ISR_UART0; + break; + case AR531X_MISC_IRQ_WATCHDOG: + imr |= AR2315_ISR_WD; + break; + default: + break; + } + ar231x_write_reg(AR2315_IMR, imr); +} + +static void +ar2315_misc_intr_disable(struct irq_data *d) +{ + unsigned int imr; + + imr = ar231x_read_reg(AR2315_IMR); + switch(d->irq) { + case AR531X_MISC_IRQ_SPI: + imr &= ~AR2315_ISR_SPI; + break; + case AR531X_MISC_IRQ_TIMER: + imr &= ~AR2315_ISR_TIMER; + break; + case AR531X_MISC_IRQ_AHB_PROC: + imr &= ~AR2315_ISR_AHB; + break; + case AR531X_MISC_IRQ_GPIO: + imr &= ~AR2315_ISR_GPIO; + break; + case AR531X_MISC_IRQ_UART0: + imr &= ~AR2315_ISR_UART0; + break; + case AR531X_MISC_IRQ_WATCHDOG: + imr &= ~AR2315_ISR_WD; + break; + default: + break; + } + ar231x_write_reg(AR2315_IMR, imr); +} + + +static struct irq_chip ar2315_misc_intr_controller = { + .name = "AR2315-MISC", + .irq_mask = ar2315_misc_intr_disable, + .irq_unmask = ar2315_misc_intr_enable, +}; + +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id) +{ + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET); + ar231x_read_reg(AR2315_AHB_ERR1); + + printk(KERN_ERR "AHB fatal error\n"); + machine_restart("AHB error"); /* Catastrophic failure */ + + return IRQ_HANDLED; +} + +static struct irqaction ar2315_ahb_proc_interrupt = { + .handler = ar2315_ahb_proc_handler, + .flags = IRQF_DISABLED, + .name = "ar2315_ahb_proc_interrupt", +}; + +static struct irqaction cascade = { + .handler = no_action, + .flags = IRQF_DISABLED, + .name = "cascade", +}; + +void +ar2315_irq_init(void) +{ + int i; + + if (!is_2315()) + return; + + ar231x_irq_dispatch = ar2315_irq_dispatch; + gpiointval = ar231x_read_reg(AR2315_GPIO_DI); + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { + int irq = AR531X_MISC_IRQ_BASE + i; + irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller, + handle_level_irq); + } + for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) { + int irq = AR531X_GPIO_IRQ_BASE + i; + irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller, + handle_level_irq); + } + setup_irq(AR531X_MISC_IRQ_GPIO, &cascade); + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt); + setup_irq(AR2315_IRQ_MISC_INTRS, &cascade); +} + +const struct ar231x_gpiodev ar2315_gpiodev; + +static u32 +ar2315_gpio_get_output(void) +{ + u32 reg; + reg = ar231x_read_reg(AR2315_GPIO_CR); + reg &= ar2315_gpiodev.valid_mask; + return reg; +} + +static u32 +ar2315_gpio_set_output(u32 mask, u32 val) +{ + u32 reg; + + reg = ar231x_read_reg(AR2315_GPIO_CR); + reg &= ~mask; + reg |= val; + ar231x_write_reg(AR2315_GPIO_CR, reg); + return reg; +} + +static u32 +ar2315_gpio_get(void) +{ + u32 reg; + reg = ar231x_read_reg(AR2315_GPIO_DI); + reg &= ar2315_gpiodev.valid_mask; + return reg; +} + +static u32 +ar2315_gpio_set(u32 mask, u32 value) +{ + u32 reg; + reg = ar231x_read_reg(AR2315_GPIO_DO); + reg &= ~mask; + reg |= value; + ar231x_write_reg(AR2315_GPIO_DO, reg); + return reg; +} + +const struct ar231x_gpiodev ar2315_gpiodev = { + .valid_mask = (1 << 22) - 1, + .get_output = ar2315_gpio_get_output, + .set_output = ar2315_gpio_set_output, + .get = ar2315_gpio_get, + .set = ar2315_gpio_set, +}; + +static struct ar231x_eth ar2315_eth_data = { + .reset_base = AR2315_RESET, + .reset_mac = AR2315_RESET_ENET0, + .reset_phy = AR2315_RESET_EPHY0, + .phy_base = KSEG1ADDR(AR2315_ENET0), + .config = &ar231x_board, +}; + +static struct resource ar2315_spiflash_res[] = { + { + .name = "flash_base", + .flags = IORESOURCE_MEM, + .start = KSEG1ADDR(AR2315_SPI_READ), + .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1, + }, + { + .name = "flash_regs", + .flags = IORESOURCE_MEM, + .start = 0x11300000, + .end = 0x11300012, + }, +}; + +static struct platform_device ar2315_spiflash = { + .id = 0, + .name = "spiflash", + .resource = ar2315_spiflash_res, + .num_resources = ARRAY_SIZE(ar2315_spiflash_res) +}; + +static struct platform_device ar2315_wdt = { + .id = 0, + .name = "ar2315_wdt", +}; + +#define SPI_FLASH_CTL 0x00 +#define SPI_FLASH_OPCODE 0x04 +#define SPI_FLASH_DATA 0x08 + +static inline u32 +spiflash_read_reg(int reg) +{ + return ar231x_read_reg(AR2315_SPI + reg); +} + +static inline void +spiflash_write_reg(int reg, u32 data) +{ + ar231x_write_reg(AR2315_SPI + reg, data); +} + +static u32 +spiflash_wait_status(void) +{ + u32 reg; + + do { + reg = spiflash_read_reg(SPI_FLASH_CTL); + } while (reg & SPI_CTL_BUSY); + + return reg; +} + +static u8 +spiflash_probe(void) +{ + u32 reg; + + reg = spiflash_wait_status(); + reg &= ~SPI_CTL_TX_RX_CNT_MASK; + reg |= (1 << 4) | 4 | SPI_CTL_START; + + spiflash_write_reg(SPI_FLASH_OPCODE, 0xab); + spiflash_write_reg(SPI_FLASH_CTL, reg); + + reg = spiflash_wait_status(); + reg = spiflash_read_reg(SPI_FLASH_DATA); + reg &= 0xff; + + return (u8) reg; +} + + +#define STM_8MBIT_SIGNATURE 0x13 +#define STM_16MBIT_SIGNATURE 0x14 +#define STM_32MBIT_SIGNATURE 0x15 +#define STM_64MBIT_SIGNATURE 0x16 +#define STM_128MBIT_SIGNATURE 0x17 + +static u8 __init * +ar2315_flash_limit(void) +{ + u32 flash_size = 0; + + /* probe the flash chip size */ + switch(spiflash_probe()) { + case STM_8MBIT_SIGNATURE: + flash_size = 0x00100000; + break; + case STM_16MBIT_SIGNATURE: + flash_size = 0x00200000; + break; + case STM_32MBIT_SIGNATURE: + flash_size = 0x00400000; + break; + case STM_64MBIT_SIGNATURE: + flash_size = 0x00800000; + break; + case STM_128MBIT_SIGNATURE: + flash_size = 0x01000000; + break; + } + + ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start + + flash_size - 1; + return (u8 *) ar2315_spiflash_res[0].end + 1; +} + +#ifdef CONFIG_LEDS_GPIO +static struct gpio_led ar2315_leds[6]; +static struct gpio_led_platform_data ar2315_led_data = { + .leds = (void *) ar2315_leds, +}; + +static struct platform_device ar2315_gpio_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = (void *) &ar2315_led_data, + } +}; + +static void __init +ar2315_init_gpio(void) +{ + static char led_names[6][6]; + int i, led = 0; + + ar2315_led_data.num_leds = 0; + for(i = 1; i < 8; i++) + { + if((i == AR2315_RESET_GPIO) || + (i == ar231x_board.config->resetConfigGpio)) + continue; + + if(i == ar231x_board.config->sysLedGpio) + strcpy(led_names[led], "wlan"); + else + sprintf(led_names[led], "gpio%d", i); + + ar2315_leds[led].name = led_names[led]; + ar2315_leds[led].gpio = i; + ar2315_leds[led].active_low = 0; + led++; + } + ar2315_led_data.num_leds = led; + platform_device_register(&ar2315_gpio_leds); +} +#else +static inline void ar2315_init_gpio(void) +{ +} +#endif + +int __init +ar2315_init_devices(void) +{ + if (!is_2315()) + return 0; + + /* Find board configuration */ + ar231x_find_config(ar2315_flash_limit()); + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac; + + ar2315_init_gpio(); + platform_device_register(&ar2315_wdt); + platform_device_register(&ar2315_spiflash); + ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS, + &ar2315_eth_data); + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS); + + return 0; +} + +static void +ar2315_restart(char *command) +{ + void (*mips_reset_vec)(void) = (void *) 0xbfc00000; + + local_irq_disable(); + + /* try reset the system via reset control */ + ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM); + + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround. + * give it some time to attempt a gpio based hardware reset + * (atheros reference design workaround) */ + gpio_direction_output(AR2315_RESET_GPIO, 0); + mdelay(100); + + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic + * workaround. Attempt to jump to the mips reset location - + * the boot loader itself might be able to recover the system */ + mips_reset_vec(); +} + + +/* + * This table is indexed by bits 5..4 of the CLOCKCTL1 register + * to determine the predevisor value. + */ +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; +static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 }; + +static unsigned int __init +ar2315_sys_clk(unsigned int clockCtl) +{ + unsigned int pllcCtrl,cpuDiv; + unsigned int pllcOut,refdiv,fdiv,divby2; + unsigned int clkDiv; + + pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL); + refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S; + refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv]; + fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S; + divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S; + divby2 += 1; + pllcOut = (40000000/refdiv)*(2*divby2)*fdiv; + + + /* clkm input selected */ + switch(clockCtl & CPUCLK_CLK_SEL_M) { + case 0: + case 1: + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S]; + break; + case 2: + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S]; + break; + default: + pllcOut = 40000000; + clkDiv = 1; + break; + } + cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S; + cpuDiv = cpuDiv * 2 ?: 1; + return (pllcOut/(clkDiv * cpuDiv)); +} + +static inline unsigned int +ar2315_cpu_frequency(void) +{ + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK)); +} + +static inline unsigned int +ar2315_apb_frequency(void) +{ + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK)); +} + +void __init +ar2315_time_init(void) +{ + if (!is_2315()) + return; + + mips_hpt_frequency = ar2315_cpu_frequency() / 2; +} + +void __init +ar2315_prom_init(void) +{ + u32 memsize, memcfg, devid; + + if (!is_2315()) + return; + + memcfg = ar231x_read_reg(AR2315_MEM_CFG); + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S); + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S); + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S); + memsize <<= 3; + add_memory_region(0, memsize, BOOT_MEM_RAM); + + /* Detect the hardware based on the device ID */ + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP; + switch(devid) { + case 0x90: + case 0x91: + ar231x_devtype = DEV_TYPE_AR2317; + break; + default: + ar231x_devtype = DEV_TYPE_AR2315; + break; + } + ar231x_gpiodev = &ar2315_gpiodev; + ar231x_board.devid = devid; +} + +void __init +ar2315_plat_setup(void) +{ + u32 config; + + if (!is_2315()) + return; + + /* Clear any lingering AHB errors */ + config = read_c0_config(); + write_c0_config(config & ~0x3); + ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET); + ar231x_read_reg(AR2315_AHB_ERR1); + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION); + + _machine_restart = ar2315_restart; + ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency()); +} diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h --- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h 2011-05-15 21:34:57.000000000 +0200 @@ -0,0 +1,37 @@ +#ifndef __AR2315_H +#define __AR2315_H + +#ifdef CONFIG_ATHEROS_AR2315 + +extern void ar2315_irq_init(void); +extern int ar2315_init_devices(void); +extern void ar2315_prom_init(void); +extern void ar2315_plat_setup(void); +extern void ar2315_time_init(void); + +#else + +static inline void ar2315_irq_init(void) +{ +} + +static inline int ar2315_init_devices(void) +{ + return 0; +} + +static inline void ar2315_prom_init(void) +{ +} + +static inline void ar2315_plat_setup(void) +{ +} + +static inline void ar2315_time_init(void) +{ +} + +#endif + +#endif diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c --- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c 2011-05-15 21:34:57.000000000 +0200 @@ -0,0 +1,538 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. + * Copyright (C) 2006 FON Technology, SL. + * Copyright (C) 2006 Imre Kaloz + * Copyright (C) 2006-2009 Felix Fietkau + */ + +/* + * Platform devices for Atheros SoCs + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "devices.h" +#include "ar5312.h" + +static void +ar5312_misc_irq_dispatch(void) +{ + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR); + + if (ar231x_misc_intrs & AR531X_ISR_TIMER) { + do_IRQ(AR531X_MISC_IRQ_TIMER); + (void)ar231x_read_reg(AR531X_TIMER); + } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC) + do_IRQ(AR531X_MISC_IRQ_AHB_PROC); + else if ((ar231x_misc_intrs & AR531X_ISR_UART0)) + do_IRQ(AR531X_MISC_IRQ_UART0); + else if (ar231x_misc_intrs & AR531X_ISR_WD) + do_IRQ(AR531X_MISC_IRQ_WATCHDOG); + else + do_IRQ(AR531X_MISC_IRQ_NONE); +} + +static asmlinkage void +ar5312_irq_dispatch(void) +{ + int pending = read_c0_status() & read_c0_cause(); + + if (pending & CAUSEF_IP2) + do_IRQ(AR5312_IRQ_WLAN0_INTRS); + else if (pending & CAUSEF_IP3) + do_IRQ(AR5312_IRQ_ENET0_INTRS); + else if (pending & CAUSEF_IP4) + do_IRQ(AR5312_IRQ_ENET1_INTRS); + else if (pending & CAUSEF_IP5) + do_IRQ(AR5312_IRQ_WLAN1_INTRS); + else if (pending & CAUSEF_IP6) + ar5312_misc_irq_dispatch(); + else if (pending & CAUSEF_IP7) + do_IRQ(AR531X_IRQ_CPU_CLOCK); +} + + +/* Enable the specified AR531X_MISC_IRQ interrupt */ +static void +ar5312_misc_intr_enable(struct irq_data *d) +{ + unsigned int imr; + + imr = ar231x_read_reg(AR531X_IMR); + imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); + ar231x_write_reg(AR531X_IMR, imr); +} + +/* Disable the specified AR531X_MISC_IRQ interrupt */ +static void +ar5312_misc_intr_disable(struct irq_data *d) +{ + unsigned int imr; + + imr = ar231x_read_reg(AR531X_IMR); + imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); + ar231x_write_reg(AR531X_IMR, imr); + ar231x_read_reg(AR531X_IMR); /* flush write buffer */ +} + +static struct irq_chip ar5312_misc_intr_controller = { + .name = "AR5312-MISC", + .irq_mask = ar5312_misc_intr_disable, + .irq_unmask = ar5312_misc_intr_enable, +}; + + +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id) +{ + u32 proc1 = ar231x_read_reg(AR531X_PROC1); + u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */ + u32 dma1 = ar231x_read_reg(AR531X_DMA1); + u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */ + + printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", + procAddr, proc1, dmaAddr, dma1); + + machine_restart("AHB error"); /* Catastrophic failure */ + return IRQ_HANDLED; +} + + +static struct irqaction ar5312_ahb_proc_interrupt = { + .handler = ar5312_ahb_proc_handler, + .flags = IRQF_DISABLED, + .name = "ar5312_ahb_proc_interrupt", +}; + + +static struct irqaction cascade = { + .handler = no_action, + .flags = IRQF_DISABLED, + .name = "cascade", +}; + +void __init ar5312_irq_init(void) +{ + int i; + + if (!is_5312()) + return; + + ar231x_irq_dispatch = ar5312_irq_dispatch; + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { + int irq = AR531X_MISC_IRQ_BASE + i; + irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller, + handle_level_irq); + } + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt); + setup_irq(AR5312_IRQ_MISC_INTRS, &cascade); +} + +const struct ar231x_gpiodev ar5312_gpiodev; + +static u32 +ar5312_gpio_get_output(void) +{ + u32 reg; + reg = ~(ar231x_read_reg(AR531X_GPIO_CR)); + reg &= ar5312_gpiodev.valid_mask; + return reg; +} + +static u32 +ar5312_gpio_set_output(u32 mask, u32 val) +{ + u32 reg; + + reg = ar231x_read_reg(AR531X_GPIO_CR); + reg |= mask; + reg &= ~val; + ar231x_write_reg(AR531X_GPIO_CR, reg); + return reg; +} + +static u32 +ar5312_gpio_get(void) +{ + u32 reg; + reg = ar231x_read_reg(AR531X_GPIO_DI); + reg &= ar5312_gpiodev.valid_mask; + return reg; +} + +static u32 +ar5312_gpio_set(u32 mask, u32 value) +{ + u32 reg; + reg = ar231x_read_reg(AR531X_GPIO_DO); + reg &= ~mask; + reg |= value; + ar231x_write_reg(AR531X_GPIO_DO, reg); + return reg; +} + +const struct ar231x_gpiodev ar5312_gpiodev = { + .valid_mask = (1 << 8) - 1, + .get_output = ar5312_gpio_get_output, + .set_output = ar5312_gpio_set_output, + .get = ar5312_gpio_get, + .set = ar5312_gpio_set, +}; + +static struct physmap_flash_data ar5312_flash_data = { + .width = 2, +}; + +static struct resource ar5312_flash_resource = { + .start = AR531X_FLASH, + .end = AR531X_FLASH + 0x800000 - 1, + .flags = IORESOURCE_MEM, +}; + +static struct ar231x_eth ar5312_eth0_data = { + .reset_base = AR531X_RESET, + .reset_mac = AR531X_RESET_ENET0, + .reset_phy = AR531X_RESET_EPHY0, + .phy_base = KSEG1ADDR(AR531X_ENET0), + .config = &ar231x_board, +}; + +static struct ar231x_eth ar5312_eth1_data = { + .reset_base = AR531X_RESET, + .reset_mac = AR531X_RESET_ENET1, + .reset_phy = AR531X_RESET_EPHY1, + .phy_base = KSEG1ADDR(AR531X_ENET1), + .config = &ar231x_board, +}; + +static struct platform_device ar5312_physmap_flash = { + .name = "physmap-flash", + .id = 0, + .dev.platform_data = &ar5312_flash_data, + .resource = &ar5312_flash_resource, + .num_resources = 1, +}; + +#ifdef CONFIG_LEDS_GPIO +static struct gpio_led ar5312_leds[] = { + { .name = "wlan", .gpio = 0, .active_low = 1, }, +}; + +static const struct gpio_led_platform_data ar5312_led_data = { + .num_leds = ARRAY_SIZE(ar5312_leds), + .leds = (void *) ar5312_leds, +}; + +static struct platform_device ar5312_gpio_leds = { + .name = "leds-gpio", + .id = -1, + .dev.platform_data = (void *) &ar5312_led_data, +}; +#endif + +/* + * NB: This mapping size is larger than the actual flash size, + * but this shouldn't be a problem here, because the flash + * will simply be mapped multiple times. + */ +static char __init *ar5312_flash_limit(void) +{ + u32 ctl; + /* + * Configure flash bank 0. + * Assume 8M window size. Flash will be aliased if it's smaller + */ + ctl = FLASHCTL_E | + FLASHCTL_AC_8M | + FLASHCTL_RBLE | + (0x01 << FLASHCTL_IDCY_S) | + (0x07 << FLASHCTL_WST1_S) | + (0x07 << FLASHCTL_WST2_S) | + (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW); + + ar231x_write_reg(AR531X_FLASHCTL0, ctl); + + /* Disable other flash banks */ + ar231x_write_reg(AR531X_FLASHCTL1, + ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC)); + + ar231x_write_reg(AR531X_FLASHCTL2, + ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC)); + + return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000); +} + +int __init ar5312_init_devices(void) +{ + struct ar231x_boarddata *config; + u32 fctl = 0; + const u8 *radio; + u8 *c; + + if (!is_5312()) + return 0; + + /* Locate board/radio config data */ + ar231x_find_config(ar5312_flash_limit()); + config = ar231x_board.config; + + + /* + * Chip IDs and hardware detection for some Atheros + * models are really broken! + * + * Atheros uses a disabled WMAC0 and Silicon ID of AR5312 + * as indication for AR2312, which is otherwise + * indistinguishable from the real AR5312. + */ + if (ar231x_board.radio) { + radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF; + if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0) + config->flags |= BD_ISCASPER; + } else + radio = NULL; + + /* AR2313 has CPU minor rev. 10 */ + if ((current_cpu_data.processor_id & 0xff) == 0x0a) + ar231x_devtype = DEV_TYPE_AR2313; + + /* AR2312 shares the same Silicon ID as AR5312 */ + else if (config->flags & BD_ISCASPER) + ar231x_devtype = DEV_TYPE_AR2312; + + /* Everything else is probably AR5312 or compatible */ + else + ar231x_devtype = DEV_TYPE_AR5312; + + /* fixup flash width */ + fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW; + switch (fctl) { + case FLASHCTL_MWx16: + ar5312_flash_data.width = 2; + break; + case FLASHCTL_MWx8: + default: + ar5312_flash_data.width = 1; + break; + } + + platform_device_register(&ar5312_physmap_flash); + +#ifdef CONFIG_LEDS_GPIO + ar5312_leds[0].gpio = config->sysLedGpio; + platform_device_register(&ar5312_gpio_leds); +#endif + + /* Fix up MAC addresses if necessary */ + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6)) + memcpy(config->enet0_mac, config->enet1_mac, 6); + + /* If ENET0 and ENET1 have the same mac address, + * increment the one from ENET1 */ + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) { + c = config->enet1_mac + 5; + while ((c >= config->enet1_mac) && !(++(*c))) + c--; + } + + switch(ar231x_devtype) { + case DEV_TYPE_AR5312: + ar5312_eth0_data.macaddr = config->enet0_mac; + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0), + AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data); + + ar5312_eth1_data.macaddr = config->enet1_mac; + ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1), + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); + + if (!ar231x_board.radio) + return 0; + + if ((*((u32 *) radio) & AR531X_RADIO0_MASK) && + (config->flags & BD_WLAN0)) + ar231x_add_wmac(0, AR531X_WLAN0, + AR5312_IRQ_WLAN0_INTRS); + + break; + /* + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC + * of ENET1. Atheros calls it 'twisted' for a reason :) + */ + case DEV_TYPE_AR2312: + case DEV_TYPE_AR2313: + ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base; + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy; + ar5312_eth1_data.macaddr = config->enet0_mac; + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1), + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); + + if (!ar231x_board.radio) + return 0; + break; + default: + break; + } + + if ((*((u32 *) radio) & AR531X_RADIO1_MASK) && + (config->flags & BD_WLAN1)) + ar231x_add_wmac(1, AR531X_WLAN1, + AR5312_IRQ_WLAN1_INTRS); + + return 0; +} + + +static void ar5312_restart(char *command) +{ + /* reset the system */ + local_irq_disable(); + while(1) { + ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM); + } +} + + +/* + * This table is indexed by bits 5..4 of the CLOCKCTL1 register + * to determine the predevisor value. + */ +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; + + +static int __init +ar5312_cpu_frequency(void) +{ + unsigned int result; + unsigned int predivide_mask, predivide_shift; + unsigned int multiplier_mask, multiplier_shift; + unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier; + unsigned int doubler_mask; + u16 devid; + + /* Trust the bootrom's idea of cpu frequency. */ + if ((result = ar231x_read_reg(AR5312_SCRATCH))) + return result; + + devid = ar231x_read_reg(AR531X_REV); + devid &= AR531X_REV_MAJ; + devid >>= AR531X_REV_MAJ_S; + if (devid == AR531X_REV_MAJ_AR2313) { + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK; + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT; + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK; + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT; + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK; + } else { /* AR5312 and AR2312 */ + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK; + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT; + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK; + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT; + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK; + } + + /* + * Clocking is derived from a fixed 40MHz input clock. + * + * cpuFreq = InputClock * MULT (where MULT is PLL multiplier) + * sysFreq = cpuFreq / 4 (used for APB clock, serial, + * flash, Timer, Watchdog Timer) + * + * cntFreq = cpuFreq / 2 (use for CPU count/compare) + * + * So, for example, with a PLL multiplier of 5, we have + * + * cpuFreq = 200MHz + * sysFreq = 50MHz + * cntFreq = 100MHz + * + * We compute the CPU frequency, based on PLL settings. + */ + + clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1); + preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift; + preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect]; + multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift; + + if (clockCtl1 & doubler_mask) { + multiplier = multiplier << 1; + } + return (40000000 / preDivisor) * multiplier; +} + +static inline int +ar5312_sys_frequency(void) +{ + return ar5312_cpu_frequency() / 4; +} + +void __init +ar5312_time_init(void) +{ + if (!is_5312()) + return; + + mips_hpt_frequency = ar5312_cpu_frequency() / 2; +} + + +void __init +ar5312_prom_init(void) +{ + u32 memsize, memcfg, bank0AC, bank1AC; + u32 devid; + + if (!is_5312()) + return; + + /* Detect memory size */ + memcfg = ar231x_read_reg(AR531X_MEM_CFG1); + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S; + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S; + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) + + (bank1AC ? (1 << (bank1AC+1)) : 0); + memsize <<= 20; + add_memory_region(0, memsize, BOOT_MEM_RAM); + + devid = ar231x_read_reg(AR531X_REV); + devid >>= AR531X_REV_WMAC_MIN_S; + devid &= AR531X_REV_CHIP; + ar231x_board.devid = (u16) devid; + ar231x_gpiodev = &ar5312_gpiodev; +} + +void __init +ar5312_plat_setup(void) +{ + if (!is_5312()) + return; + + /* Clear any lingering AHB errors */ + ar231x_read_reg(AR531X_PROCADDR); + ar231x_read_reg(AR531X_DMAADDR); + ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION); + + _machine_restart = ar5312_restart; + ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency()); +} + diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h --- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h 2011-05-15 21:34:57.000000000 +0200 @@ -0,0 +1,38 @@ +#ifndef __AR5312_H +#define __AR5312_H + +#ifdef CONFIG_ATHEROS_AR5312 + +extern void ar5312_irq_init(void); +extern int ar5312_init_devices(void); +extern void ar5312_prom_init(void); +extern void ar5312_plat_setup(void); +extern void ar5312_time_init(void); +extern void ar5312_time_init(void); + +#else + +static inline void ar5312_irq_init(void) +{ +} + +static inline int ar5312_init_devices(void) +{ + return 0; +} + +static inline void ar5312_prom_init(void) +{ +} + +static inline void ar5312_plat_setup(void) +{ +} + +static inline void ar5312_time_init(void) +{ +} + +#endif + +#endif diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c linux-2.6.39-rc7/arch/mips/ar231x/board.c --- linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/board.c 2011-05-15 22:16:11.000000000 +0200 @@ -0,0 +1,261 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. + * Copyright (C) 2006 FON Technology, SL. + * Copyright (C) 2006 Imre Kaloz + * Copyright (C) 2006-2009 Felix Fietkau + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "devices.h" +#include "ar5312.h" +#include "ar2315.h" + +void (*ar231x_irq_dispatch)(void); + +static inline bool +check_radio_magic(u8 *addr) +{ + addr += 0x7a; /* offset for flash magic */ + if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) { + return 1; + } + return 0; +} + +static inline bool +check_board_data(u8 *flash_limit, u8 *addr, bool broken) +{ + /* config magic found */ + if (*((u32 *)addr) == AR531X_BD_MAGIC) + return 1; + + if (!broken) + return 0; + + if (check_radio_magic(addr + 0xf8)) + ar231x_board.radio = addr + 0xf8; + if ((addr < flash_limit + 0x10000) && + check_radio_magic(addr + 0x10000)) + ar231x_board.radio = addr + 0x10000; + + if (ar231x_board.radio) { + /* broken board data detected, use radio data to find the offset, + * user will fix this */ + return 1; + } + return 0; +} + +static u8 * +find_board_config(u8 *flash_limit, bool broken) +{ + u8 *addr; + int found = 0; + + for (addr = flash_limit - 0x1000; + addr >= flash_limit - 0x30000; + addr -= 0x1000) { + + if (check_board_data(flash_limit, addr, broken)) { + found = 1; + break; + } + } + + if (!found) + addr = NULL; + + return addr; +} + +static u8 * +find_radio_config(u8 *flash_limit, u8 *board_config) +{ + int found; + u8 *radio_config; + + /* + * Now find the start of Radio Configuration data, using heuristics: + * Search forward from Board Configuration data by 0x1000 bytes + * at a time until we find non-0xffffffff. + */ + found = 0; + for (radio_config = board_config + 0x1000; + (radio_config < flash_limit); + radio_config += 0x1000) { + if ((*(u32 *)radio_config != 0xffffffff) && + check_radio_magic(radio_config)) { + found = 1; + break; + } + } + + /* AR2316 relocates radio config to new location */ + if (!found) { + for (radio_config = board_config + 0xf8; + (radio_config < flash_limit - 0x1000 + 0xf8); + radio_config += 0x1000) { + if ((*(u32 *)radio_config != 0xffffffff) && + check_radio_magic(radio_config)) { + found = 1; + break; + } + } + } + + if (!found) { + printk("Could not find Radio Configuration data\n"); + radio_config = 0; + } + + return (u8 *) radio_config; +} + +int __init +ar231x_find_config(u8 *flash_limit) +{ + struct ar231x_boarddata *config; + unsigned int rcfg_size; + int broken_boarddata = 0, i, tmp; + u8 *bcfg, *rcfg; + u8 *board_data; + u8 *radio_data; + u32 offset; + + ar231x_board.config = NULL; + ar231x_board.radio = NULL; + /* Copy the board and radio data to RAM, because accessing the mapped + * memory of the flash directly after booting is not safe */ + + /* Try to find valid board and radio data */ + bcfg = find_board_config(flash_limit, false); + + /* If that fails, try to at least find valid radio data */ + if (!bcfg) { + bcfg = find_board_config(flash_limit, true); + broken_boarddata = 1; + } + + if (!bcfg) { + printk(KERN_WARNING "WARNING: No board configuration data found!\n"); + return -ENODEV; + } + + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL); + ar231x_board.config = (struct ar231x_boarddata *) board_data; + memcpy(board_data, bcfg, 0x100); + if (broken_boarddata) { + printk(KERN_WARNING "WARNING: broken board data detected\n"); + config = ar231x_board.config; + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) { + printk(KERN_INFO "Fixing up empty mac addresses\n"); + config->resetConfigGpio = 0xffff; + config->sysLedGpio = 0xffff; + random_ether_addr(config->wlan0_mac); + config->wlan0_mac[0] &= ~0x06; + random_ether_addr(config->enet0_mac); + random_ether_addr(config->enet1_mac); + } + } + + + /* Radio config starts 0x100 bytes after board config, regardless + * of what the physical layout on the flash chip looks like */ + + if (ar231x_board.radio) + rcfg = (u8 *) ar231x_board.radio; + else + rcfg = find_radio_config(flash_limit, bcfg); + + if (!rcfg) + return -ENODEV; + + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff); + ar231x_board.radio = radio_data; + offset = radio_data - board_data; + printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset); + rcfg_size = BOARD_CONFIG_BUFSZ - offset; + memcpy(radio_data, rcfg, rcfg_size); + + for (tmp = 0xff, i = 0; i < ETH_ALEN; i++) + tmp &= radio_data[i + 0x1d * 2]; + if (tmp == 0xff) { + u16 *eep = (u16 *)radio_data, *bcfgs = (u16 *)bcfg; + printk(KERN_INFO "Radio MAC is blank; using board-data\n"); + eep[0x1f] = bcfgs[0x30]; + eep[0x1e] = bcfgs[0x34]; + eep[0x1d] = bcfgs[0x32]; + } + + return 0; +} + +static void +ar231x_halt(void) +{ + local_irq_disable(); + while (1); +} + +void __init +plat_mem_setup(void) +{ + _machine_halt = ar231x_halt; + pm_power_off = ar231x_halt; + + ar5312_plat_setup(); + ar2315_plat_setup(); + + /* Disable data watchpoints */ + write_c0_watchlo0(0); +} + + +asmlinkage void +plat_irq_dispatch(void) +{ + ar231x_irq_dispatch(); +} + +void __init +plat_time_init(void) +{ + ar5312_time_init(); + ar2315_time_init(); +} + +unsigned int __cpuinit +get_c0_compare_int(void) +{ + return CP0_LEGACY_COMPARE_IRQ; +} + +void __init +arch_init_irq(void) +{ + clear_c0_status(ST0_IM); + mips_cpu_irq_init(); + + /* Initialize interrupt controllers */ + ar5312_irq_init(); + ar2315_irq_init(); +} + + diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c linux-2.6.39-rc7/arch/mips/ar231x/devices.c --- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/devices.c 2011-05-15 21:34:57.000000000 +0200 @@ -0,0 +1,175 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "devices.h" +#include "ar5312.h" +#include "ar2315.h" + +struct ar231x_board_config ar231x_board; +int ar231x_devtype = DEV_TYPE_UNKNOWN; +const struct ar231x_gpiodev *ar231x_gpiodev; +EXPORT_SYMBOL(ar231x_gpiodev); + +static struct resource ar231x_eth0_res[] = { + { + .name = "eth0_membase", + .flags = IORESOURCE_MEM, + }, + { + .name = "eth0_irq", + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource ar231x_eth1_res[] = { + { + .name = "eth1_membase", + .flags = IORESOURCE_MEM, + }, + { + .name = "eth1_irq", + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device ar231x_eth[] = { + { + .id = 0, + .name = "ar231x-eth", + .resource = ar231x_eth0_res, + .num_resources = ARRAY_SIZE(ar231x_eth0_res) + }, + { + .id = 1, + .name = "ar231x-eth", + .resource = ar231x_eth1_res, + .num_resources = ARRAY_SIZE(ar231x_eth1_res) + } +}; + +static struct resource ar231x_wmac0_res[] = { + { + .name = "wmac0_membase", + .flags = IORESOURCE_MEM, + }, + { + .name = "wmac0_irq", + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource ar231x_wmac1_res[] = { + { + .name = "wmac1_membase", + .flags = IORESOURCE_MEM, + }, + { + .name = "wmac1_irq", + .flags = IORESOURCE_IRQ, + } +}; + + +static struct platform_device ar231x_wmac[] = { + { + .id = 0, + .name = "ar231x-wmac", + .resource = ar231x_wmac0_res, + .num_resources = ARRAY_SIZE(ar231x_wmac0_res), + .dev.platform_data = &ar231x_board, + }, + { + .id = 1, + .name = "ar231x-wmac", + .resource = ar231x_wmac1_res, + .num_resources = ARRAY_SIZE(ar231x_wmac1_res), + .dev.platform_data = &ar231x_board, + }, +}; + +static const char *devtype_strings[] = { + [DEV_TYPE_AR5312] = "Atheros AR5312", + [DEV_TYPE_AR2312] = "Atheros AR2312", + [DEV_TYPE_AR2313] = "Atheros AR2313", + [DEV_TYPE_AR2315] = "Atheros AR2315", + [DEV_TYPE_AR2316] = "Atheros AR2316", + [DEV_TYPE_AR2317] = "Atheros AR2317", + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)", +}; + +const char *get_system_type(void) +{ + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) || + !devtype_strings[ar231x_devtype]) + return devtype_strings[DEV_TYPE_UNKNOWN]; + return devtype_strings[ar231x_devtype]; +} + + +int __init +ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata) +{ + struct resource *res; + + ar231x_eth[nr].dev.platform_data = pdata; + res = &ar231x_eth[nr].resource[0]; + res->start = base; + res->end = base + 0x2000 - 1; + res++; + res->start = irq; + res->end = irq; + return platform_device_register(&ar231x_eth[nr]); +} + +void __init +ar231x_serial_setup(u32 mapbase, unsigned int uartclk) +{ + struct uart_port s; + + memset(&s, 0, sizeof(s)); + + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; + s.iotype = UPIO_MEM; + s.irq = AR531X_MISC_IRQ_UART0; + s.regshift = 2; + s.mapbase = mapbase; + s.uartclk = uartclk; + s.membase = (void __iomem *)s.mapbase; + + early_serial_setup(&s); +} + +int __init +ar231x_add_wmac(int nr, u32 base, int irq) +{ + struct resource *res; + + ar231x_wmac[nr].dev.platform_data = &ar231x_board; + res = &ar231x_wmac[nr].resource[0]; + res->start = base; + res->end = base + 0x10000 - 1; + res++; + res->start = irq; + res->end = irq; + return platform_device_register(&ar231x_wmac[nr]); +} + +static int __init ar231x_register_devices(void) +{ + static struct resource res = { + .start = 0xFFFFFFFF, + }; + + platform_device_register_simple("GPIODEV", 0, &res, 1); + ar5312_init_devices(); + ar2315_init_devices(); + + return 0; +} + +device_initcall(ar231x_register_devices); diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h linux-2.6.39-rc7/arch/mips/ar231x/devices.h --- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/devices.h 2011-05-15 21:34:57.000000000 +0200 @@ -0,0 +1,37 @@ +#ifndef __AR231X_DEVICES_H +#define __AR231X_DEVICES_H + +enum { + /* handled by ar5312.c */ + DEV_TYPE_AR2312, + DEV_TYPE_AR2313, + DEV_TYPE_AR5312, + + /* handled by ar2315.c */ + DEV_TYPE_AR2315, + DEV_TYPE_AR2316, + DEV_TYPE_AR2317, + + DEV_TYPE_UNKNOWN +}; + +extern int ar231x_devtype; +extern struct ar231x_board_config ar231x_board; +extern asmlinkage void (*ar231x_irq_dispatch)(void); + +extern int ar231x_find_config(u8 *flash_limit); +extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk); +extern int ar231x_add_wmac(int nr, u32 base, int irq); +extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata); + +static inline bool is_2315(void) +{ + return (current_cpu_data.cputype == CPU_4KEC); +} + +static inline bool is_5312(void) +{ + return !is_2315(); +} + +#endif diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c --- linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c 2011-05-15 21:34:57.000000000 +0200 @@ -0,0 +1,44 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2010 Gabor Juhos + */ + +#include +#include +#include +#include + +#include +#include +#include "devices.h" + +static inline void prom_uart_wr(void __iomem *base, unsigned reg, + unsigned char ch) +{ + __raw_writeb(ch, base + 4 * reg); +} + +static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) +{ + return __raw_readb(base + 4 * reg); +} + +void prom_putchar(unsigned char ch) +{ + static void __iomem *base; + + if (unlikely(base == NULL)) { + if (is_2315()) + base = (void __iomem *)(KSEG1ADDR(AR2315_UART0)); + else + base = (void __iomem *)(KSEG1ADDR(AR531X_UART0)); + } + + while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); + prom_uart_wr(base, UART_TX, ch); + while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); +} + diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c linux-2.6.39-rc7/arch/mips/ar231x/pci.c --- linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/pci.c 2011-05-15 21:34:57.000000000 +0200 @@ -0,0 +1,230 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "devices.h" + +#define AR531X_MEM_BASE 0x80800000UL +#define AR531X_MEM_SIZE 0x00ffffffUL +#define AR531X_IO_SIZE 0x00007fffUL + +static unsigned long configspace; + +static int config_access(int devfn, int where, int size, u32 *ptr, bool write) +{ + unsigned long flags; + int func = PCI_FUNC(devfn); + int dev = PCI_SLOT(devfn); + u32 value = 0; + int err = 0; + u32 addr; + + if (((dev != 0) && (dev != 3)) || (func > 2)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* Select Configuration access */ + local_irq_save(flags); + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL); + mb(); + + addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where; + if (size == 1) + addr ^= 0x3; + else if (size == 2) + addr ^= 0x2; + + if (write) { + value = *ptr; + if (size == 1) + err = put_dbe(value, (u8 *) addr); + else if (size == 2) + err = put_dbe(value, (u16 *) addr); + else if (size == 4) + err = put_dbe(value, (u32 *) addr); + } else { + if (size == 1) + err = get_dbe(value, (u8 *) addr); + else if (size == 2) + err = get_dbe(value, (u16 *) addr); + else if (size == 4) + err = get_dbe(value, (u32 *) addr); + if (err) + *ptr = 0xffffffff; + else + *ptr = value; + } + + /* Select Memory access */ + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0); + local_irq_restore(flags); + + return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL); +} + +static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value) +{ + return config_access(devfn, where, size, value, 0); +} + +static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) +{ + return config_access(devfn, where, size, &value, 1); +} + +struct pci_ops ar231x_pci_ops = { + .read = ar231x_pci_read, + .write = ar231x_pci_write, +}; + +static struct resource ar231x_mem_resource = { + .name = "AR531x PCI MEM", + .start = AR531X_MEM_BASE, + .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000, + .flags = IORESOURCE_MEM, +}; + +static struct resource ar231x_io_resource = { + .name = "AR531x PCI I/O", + .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE, + .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1, + .flags = IORESOURCE_IO, +}; + +struct pci_controller ar231x_pci_controller = { + .pci_ops = &ar231x_pci_ops, + .mem_resource = &ar231x_mem_resource, + .io_resource = &ar231x_io_resource, + .mem_offset = 0x00000000UL, + .io_offset = 0x00000000UL, +}; + +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return AR2315_IRQ_LCBUS_PCI; +} + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5); + pci_write_config_word(dev, 0x40, 0); + + /* Clear any pending Abort or external Interrupts + * and enable interrupt processing */ + ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0); + ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); + ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); + ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE); + + return 0; +} + +static void +ar2315_pci_fixup(struct pci_dev *dev) +{ + unsigned int devfn = dev->devfn; + + if (dev->bus->number != 0) + return; + + /* Only fix up the PCI host settings */ + if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0)) + return; + + /* Fix up MBARs */ + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2); + pci_write_config_dword(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | + PCI_COMMAND_FAST_BACK); +} +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup); + +static int __init +ar2315_pci_init(void) +{ + u32 reg; + + if (ar231x_devtype != DEV_TYPE_AR2315) + return -ENODEV; + + configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */ + ar231x_pci_controller.io_map_base = + (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE); + set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */ + + reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA); + msleep(10); + + reg &= ~AR2315_RESET_PCIDMA; + ar231x_write_reg(AR2315_RESET, reg); + msleep(10); + + ar231x_mask_reg(AR2315_ENDIAN_CTL, 0, + AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE); + + ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | + (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S)); + ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); + ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK, + AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | + (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT)); + + /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */ + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, + AR2315_PCIRST_LOW); + msleep(100); + + /* Bring the PCI out of reset */ + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, + AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8); + + ar231x_write_reg(AR2315_PCI_UNCACHE_CFG, + 0x1E | /* 1GB uncached */ + (1 << 5) | /* Enable uncached */ + (0x2 << 30) /* Base: 0x80000000 */ + ); + ar231x_read_reg(AR2315_PCI_UNCACHE_CFG); + + msleep(500); + + /* dirty hack - anyone with a datasheet that knows the memory map ? */ + ioport_resource.start = 0x10000000; + ioport_resource.end = 0xffffffff; + iomem_resource.start = 0x10000000; + iomem_resource.end = 0xffffffff; + + register_pci_controller(&ar231x_pci_controller); + + return 0; +} + +arch_initcall(ar2315_pci_init); diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c linux-2.6.39-rc7/arch/mips/ar231x/prom.c --- linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/prom.c 2011-05-15 21:34:57.000000000 +0200 @@ -0,0 +1,37 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright MontaVista Software Inc + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. + * Copyright (C) 2006 FON Technology, SL. + * Copyright (C) 2006 Imre Kaloz + * Copyright (C) 2006 Felix Fietkau + */ + +/* + * Prom setup file for ar531x + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include "ar5312.h" +#include "ar2315.h" + +void __init prom_init(void) +{ + ar5312_prom_init(); + ar2315_prom_init(); +} + +void __init prom_free_prom_memory(void) +{ +} diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c linux-2.6.39-rc7/arch/mips/ar231x/reset.c --- linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/ar231x/reset.c 2011-05-15 21:34:57.000000000 +0200 @@ -0,0 +1,161 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "devices.h" + +#define AR531X_RESET_GPIO_IRQ (AR531X_GPIO_IRQ(ar231x_board.config->resetConfigGpio)) + +struct event_t { + struct work_struct wq; + int set; + unsigned long jiffies; +}; + +static struct timer_list rst_button_timer; +static unsigned long seen; + +struct sock *uevent_sock = NULL; +EXPORT_SYMBOL_GPL(uevent_sock); +extern u64 uevent_next_seqnum(void); + +static int no_release_workaround = 1; +module_param(no_release_workaround, int, 0); + +static inline void +add_msg(struct sk_buff *skb, char *msg) +{ + char *scratch; + scratch = skb_put(skb, strlen(msg) + 1); + sprintf(scratch, msg); +} + +static void +hotplug_button(struct work_struct *wq) +{ + struct sk_buff *skb; + struct event_t *event; + size_t len; + char *scratch, *s; + char buf[128]; + + event = container_of(wq, struct event_t, wq); + if (!uevent_sock) + goto done; + + /* allocate message with the maximum possible size */ + s = event->set ? "pressed" : "released"; + len = strlen(s) + 2; + skb = alloc_skb(NLMSG_GOODSIZE, GFP_KERNEL); + if (!skb) + goto done; + + /* add header */ + scratch = skb_put(skb, len); + sprintf(scratch, "%s@",s); + + /* copy keys to our continuous event payload buffer */ + add_msg(skb, "HOME=/"); + add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin"); + add_msg(skb, "SUBSYSTEM=button"); + add_msg(skb, "BUTTON=reset"); + add_msg(skb, (event->set ? "ACTION=pressed" : "ACTION=released")); + sprintf(buf, "SEEN=%ld", (event->jiffies - seen)/HZ); + add_msg(skb, buf); + snprintf(buf, 128, "SEQNUM=%llu", uevent_next_seqnum()); + add_msg(skb, buf); + + NETLINK_CB(skb).dst_group = 1; + netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL); + +done: + kfree(event); +} + +static void +reset_button_poll(unsigned long unused) +{ + struct event_t *event; + int gpio = ~0; + + if(!no_release_workaround) + return; + + gpio = ar231x_gpiodev->get(); + gpio &= (1 << (AR531X_RESET_GPIO_IRQ - AR531X_GPIO_IRQ_BASE)); + if(gpio) { + rst_button_timer.expires = jiffies + (HZ / 4); + add_timer(&rst_button_timer); + return; + } + + event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); + if (!event) + return; + + event->set = 0; + event->jiffies = jiffies; + INIT_WORK(&event->wq, hotplug_button); + schedule_work(&event->wq); +} + +static irqreturn_t +button_handler(int irq, void *dev_id) +{ + static int pressed = 0; + struct event_t *event; + u32 gpio = ~0; + + event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); + if (!event) + return IRQ_NONE; + + pressed = !pressed; + + gpio = ar231x_gpiodev->get() & (1 << (irq - AR531X_GPIO_IRQ_BASE)); + + event->set = gpio; + if(!event->set) + no_release_workaround = 0; + + event->jiffies = jiffies; + + INIT_WORK(&event->wq, hotplug_button); + schedule_work(&event->wq); + + seen = jiffies; + if(event->set && no_release_workaround) + mod_timer(&rst_button_timer, jiffies + (HZ / 4)); + + return IRQ_HANDLED; +} + + +static int __init +ar231x_init_reset(void) +{ + seen = jiffies; + + if (ar231x_board.config->resetConfigGpio == 0xffff) + return -ENODEV; + + init_timer(&rst_button_timer); + rst_button_timer.function = reset_button_poll; + rst_button_timer.expires = jiffies + HZ / 50; + add_timer(&rst_button_timer); + + request_irq(AR531X_RESET_GPIO_IRQ, &button_handler, IRQF_SAMPLE_RANDOM, "ar231x_reset", NULL); + + return 0; +} + +module_init(ar231x_init_reset); diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h --- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 2011-05-15 21:44:12.000000000 +0200 @@ -0,0 +1,580 @@ +/* + * Register definitions for AR2315+ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. + * Copyright (C) 2006 FON Technology, SL. + * Copyright (C) 2006 Imre Kaloz + * Copyright (C) 2006-2008 Felix Fietkau + */ + +#ifndef __AR2315_REG_H +#define __AR2315_REG_H + +/* + * IRQs + */ +#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ +#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ +#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ +#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ +#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ + +/* + * Address map + */ +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */ +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */ +#define AR2315_PCI 0x10100000 /* PCI MMR */ +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */ +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */ +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */ +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */ +#define AR2315_UART0 0x11100003 /* UART MMR */ +#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */ +#define AR2315_PCIEXT 0x80000000 /* pci external */ + +/* + * Reset Register + */ +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000) + +#define AR2315_RESET_COLD_AHB 0x00000001 +#define AR2315_RESET_COLD_APB 0x00000002 +#define AR2315_RESET_COLD_CPU 0x00000004 +#define AR2315_RESET_COLD_CPUWARM 0x00000008 +#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */ +#define AR2317_RESET_SYSTEM 0x00000010 + + +#define AR2315_RESET (AR2315_DSLBASE + 0x0004) + +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */ +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */ +#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */ +#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */ +#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */ +#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */ +#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */ +#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */ +#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */ +#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */ +#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */ +#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */ + +/* + * AHB master arbitration control + */ +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008) + +#define AR2315_ARB_CPU 0x00000001 /* CPU, default */ +#define AR2315_ARB_WLAN 0x00000002 /* WLAN */ +#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ +#define AR2315_ARB_LOCAL