diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/clcd-panels.dtsi linux-3.14.35/arch/arm/boot/dts/clcd-panels.dtsi --- linux-3.14.35.orig/arch/arm/boot/dts/clcd-panels.dtsi 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/clcd-panels.dtsi 2015-03-08 14:27:37.381684503 -0500 @@ -0,0 +1,52 @@ +/* + * ARM Ltd. Versatile Express + * + */ + +/ { + panels { + panel@0 { + compatible = "panel"; + mode = "VGA"; + refresh = <60>; + xres = <640>; + yres = <480>; + pixclock = <39721>; + left_margin = <40>; + right_margin = <24>; + upper_margin = <32>; + lower_margin = <11>; + hsync_len = <96>; + vsync_len = <2>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + + panel@1 { + compatible = "panel"; + mode = "XVGA"; + refresh = <60>; + xres = <1024>; + yres = <768>; + pixclock = <15748>; + left_margin = <152>; + right_margin = <48>; + upper_margin = <23>; + lower_margin = <3>; + hsync_len = <104>; + vsync_len = <4>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + }; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/efm32gg-dk3750.dts linux-3.14.35/arch/arm/boot/dts/efm32gg-dk3750.dts --- linux-3.14.35.orig/arch/arm/boot/dts/efm32gg-dk3750.dts 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/efm32gg-dk3750.dts 2015-03-08 14:27:37.381684503 -0500 @@ -26,7 +26,7 @@ }; i2c@4000a000 { - location = <3>; + efm32,location = <3>; status = "ok"; temp@48 { diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx23.dtsi linux-3.14.35/arch/arm/boot/dts/imx23.dtsi --- linux-3.14.35.orig/arch/arm/boot/dts/imx23.dtsi 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx23.dtsi 2015-03-08 14:27:37.381684503 -0500 @@ -363,7 +363,8 @@ compatible = "fsl,imx23-lcdif"; reg = <0x80030000 2000>; interrupts = <46 45>; - clocks = <&clks 38>; + clocks = <&clks 38>, <&clks 38>; + clock-names = "pix", "axi"; status = "disabled"; }; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx25.dtsi linux-3.14.35/arch/arm/boot/dts/imx25.dtsi --- linux-3.14.35.orig/arch/arm/boot/dts/imx25.dtsi 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx25.dtsi 2015-03-08 14:27:37.381684503 -0500 @@ -13,6 +13,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -56,6 +57,7 @@ osc { compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <24000000>; }; }; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx25-karo-tx25.dts linux-3.14.35/arch/arm/boot/dts/imx25-karo-tx25.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx25-karo-tx25.dts 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx25-karo-tx25.dts 2015-03-08 14:27:37.385684503 -0500 @@ -16,6 +16,10 @@ model = "Ka-Ro TX25"; compatible = "karo,imx25-tx25", "fsl,imx25"; + chosen { + stdout-path = &uart1; + }; + memory { reg = <0x80000000 0x02000000 0x90000000 0x02000000>; }; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx27-apf27.dts linux-3.14.35/arch/arm/boot/dts/imx27-apf27.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx27-apf27.dts 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx27-apf27.dts 2015-03-08 14:27:37.385684503 -0500 @@ -29,6 +29,7 @@ osc26m { compatible = "fsl,imx-osc26m", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <0>; }; }; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx27.dtsi linux-3.14.35/arch/arm/boot/dts/imx27.dtsi --- linux-3.14.35.orig/arch/arm/boot/dts/imx27.dtsi 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx27.dtsi 2015-03-08 14:27:37.385684503 -0500 @@ -13,6 +13,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -46,6 +47,7 @@ osc26m { compatible = "fsl,imx-osc26m", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <26000000>; }; }; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts linux-3.14.35/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts 2015-03-08 14:27:37.385684503 -0500 @@ -15,6 +15,10 @@ model = "Phytec pca100 rapid development kit"; compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; + chosen { + stdout-path = &uart1; + }; + display: display { model = "Primeview-PD050VL1"; native-mode = <&timing0>; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx28.dtsi linux-3.14.35/arch/arm/boot/dts/imx28.dtsi --- linux-3.14.35.orig/arch/arm/boot/dts/imx28.dtsi 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx28.dtsi 2015-03-08 14:27:37.385684503 -0500 @@ -840,7 +840,8 @@ compatible = "fsl,imx28-lcdif"; reg = <0x80030000 0x2000>; interrupts = <38>; - clocks = <&clks 55>; + clocks = <&clks 55>, <&clks 55>; + clock-names = "pix", "axi"; dmas = <&dma_apbh 13>; dma-names = "rx"; status = "disabled"; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx51-babbage.dts linux-3.14.35/arch/arm/boot/dts/imx51-babbage.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx51-babbage.dts 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx51-babbage.dts 2015-03-08 14:27:37.385684503 -0500 @@ -17,6 +17,10 @@ model = "Freescale i.MX51 Babbage Board"; compatible = "fsl,imx51-babbage", "fsl,imx51"; + chosen { + stdout-path = &uart1; + }; + memory { reg = <0x90000000 0x20000000>; }; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx51.dtsi linux-3.14.35/arch/arm/boot/dts/imx51.dtsi --- linux-3.14.35.orig/arch/arm/boot/dts/imx51.dtsi 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx51.dtsi 2015-03-08 14:27:37.385684503 -0500 @@ -15,6 +15,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -43,21 +44,25 @@ ckil { compatible = "fsl,imx-ckil", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <32768>; }; ckih1 { compatible = "fsl,imx-ckih1", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <0>; }; ckih2 { compatible = "fsl,imx-ckih2", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <0>; }; osc { compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <24000000>; }; }; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx53.dtsi linux-3.14.35/arch/arm/boot/dts/imx53.dtsi --- linux-3.14.35.orig/arch/arm/boot/dts/imx53.dtsi 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx53.dtsi 2015-03-08 14:27:37.389684503 -0500 @@ -15,6 +15,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -59,21 +60,25 @@ ckil { compatible = "fsl,imx-ckil", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <32768>; }; ckih1 { compatible = "fsl,imx-ckih1", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <22579200>; }; ckih2 { compatible = "fsl,imx-ckih2", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <0>; }; osc { compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <24000000>; }; }; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx53-mba53.dts linux-3.14.35/arch/arm/boot/dts/imx53-mba53.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx53-mba53.dts 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx53-mba53.dts 2015-03-08 14:27:37.389684503 -0500 @@ -25,6 +25,10 @@ enable-active-low; }; + chosen { + stdout-path = &uart2; + }; + backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 50000>; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts linux-3.14.35/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts 2015-03-08 14:27:37.389684503 -0500 @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Sascha Hauer + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DTS_V1__ +#define __DTS_V1__ +/dts-v1/; +#endif + +#include "imx6dl.dtsi" +#include "imx6qdl-dfi-fs700-m60.dtsi" + +/ { + model = "DFI FS700-M60-6DL i.MX6dl Q7 Board"; + compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl.dtsi linux-3.14.35/arch/arm/boot/dts/imx6dl.dtsi --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl.dtsi 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl.dtsi 2015-03-08 14:27:37.389684503 -0500 @@ -8,6 +8,7 @@ * */ +#include #include "imx6dl-pinfunc.h" #include "imx6qdl.dtsi" @@ -21,6 +22,26 @@ device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1075000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks 104>, <&clks 6>, <&clks 16>, + <&clks 17>, <&clks 170>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; cpu@1 { @@ -32,40 +53,124 @@ }; soc { + + busfreq { /* BUSFREQ */ + compatible = "fsl,imx6_busfreq"; + clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, + <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 22> , <&clks 8>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_sel", "pll3_pfd1_540m"; + interrupts = <0 107 0x04>, <0 112 0x4>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; + fsl,max_ddr_freq = <400000000>; + }; + + gpu@00130000 { + compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu"; + reg = <0x00130000 0x4000>, <0x00134000 0x4000>, + <0x0 0x0>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr"; + interrupts = <0 9 0x04>, <0 10 0x04>; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clks 143>, <&clks 27>, + <&clks 121>, <&clks 122>, + <&clks 0>; + clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk", + "gpu2d_clk", "gpu3d_clk", + "gpu3d_shader_clk"; + resets = <&src 0>, <&src 3>; + reset-names = "gpu3d", "gpu2d"; + pu-supply = <®_pu>; + }; + ocram: sram@00900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; clocks = <&clks 142>; }; + hdmi_core: hdmi_core@00120000 { + compatible = "fsl,imx6dl-hdmi-core"; + reg = <0x00120000 0x9000>; + clocks = <&clks 124>, <&clks 123>; + clock-names = "hdmi_isfr", "hdmi_iahb"; + status = "disabled"; + }; + + hdmi_video: hdmi_video@020e0000 { + compatible = "fsl,imx6dl-hdmi-video"; + reg = <0x020e0000 0x1000>; + reg-names = "hdmi_gpr"; + interrupts = <0 115 0x04>; + clocks = <&clks 124>, <&clks 123>; + clock-names = "hdmi_isfr", "hdmi_iahb"; + status = "disabled"; + }; + + hdmi_audio: hdmi_audio@00120000 { + compatible = "fsl,imx6dl-hdmi-audio"; + clocks = <&clks 124>, <&clks 123>; + clock-names = "hdmi_isfr", "hdmi_iahb"; + dmas = <&sdma 2 23 0>; + dma-names = "tx"; + status = "disabled"; + }; + + hdmi_cec: hdmi_cec@00120000 { + compatible = "fsl,imx6dl-hdmi-cec"; + interrupts = <0 115 0x04>; + status = "disabled"; + }; + aips1: aips-bus@02000000 { + vpu@02040000 { + iramsize = <0>; + status = "okay"; + }; + iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6dl-iomuxc"; }; pxp: pxp@020f0000 { + compatible = "fsl,imx6dl-pxp-dma"; reg = <0x020f0000 0x4000>; - interrupts = <0 98 0x04>; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 133>; + clock-names = "pxp-axi"; + status = "disabled"; }; epdc: epdc@020f4000 { reg = <0x020f4000 0x4000>; - interrupts = <0 97 0x04>; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; }; lcdif: lcdif@020f8000 { reg = <0x020f8000 0x4000>; - interrupts = <0 39 0x04>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; }; }; aips2: aips-bus@02100000 { + mipi_dsi: mipi@021e0000 { + compatible = "fsl,imx6dl-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 0x04>; + gpr = <&gpr>; + clocks = <&clks 138>, <&clks 209>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + status = "disabled"; + }; + i2c4: i2c@021f8000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx1-i2c"; + compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; reg = <0x021f8000 0x4000>; - interrupts = <0 35 0x04>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 116>; status = "disabled"; }; }; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-gw51xx.dts linux-3.14.35/arch/arm/boot/dts/imx6dl-gw51xx.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-gw51xx.dts 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-gw51xx.dts 2015-03-08 14:27:37.389684503 -0500 @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw51xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite GW51XX"; + compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-gw52xx.dts linux-3.14.35/arch/arm/boot/dts/imx6dl-gw52xx.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-gw52xx.dts 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-gw52xx.dts 2015-03-08 14:27:37.389684503 -0500 @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw52xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite GW52XX"; + compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-gw53xx.dts linux-3.14.35/arch/arm/boot/dts/imx6dl-gw53xx.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-gw53xx.dts 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-gw53xx.dts 2015-03-08 14:27:37.389684503 -0500 @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw53xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite GW53XX"; + compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-gw54xx.dts linux-3.14.35/arch/arm/boot/dts/imx6dl-gw54xx.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-gw54xx.dts 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-gw54xx.dts 2015-03-08 14:27:37.389684503 -0500 @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw54xx.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite GW54XX"; + compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-hummingboard.dts linux-3.14.35/arch/arm/boot/dts/imx6dl-hummingboard.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-hummingboard.dts 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-hummingboard.dts 2015-03-08 14:27:37.393684503 -0500 @@ -1,163 +1,13 @@ /* - * Copyright (C) 2013,2014 Russell King + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on work by Russell King */ /dts-v1/; #include "imx6dl.dtsi" -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" +#include "imx6qdl-hummingboard.dtsi" / { - model = "SolidRun HummingBoard DL/Solo"; - compatible = "solidrun,hummingboard", "fsl,imx6dl"; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 2 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>; - }; - - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - /* IMX6 doesn't implement this yet */ - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c1>; - - /* - * Not fitted on Carrier-1 board... yet - status = "okay"; - - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - */ -}; - -&iomuxc { - hummingboard { - pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000 - >; - }; - - pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 - >; - }; - - pinctrl_hummingboard_i2c1: hummingboard-i2c1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard_spdif: hummingboard-spdif { - fsl,pins = ; - }; - - pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { - fsl,pins = ; - }; - - pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - >; - }; - - pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; - }; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_spdif>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usbotg_vbus>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_hummingboard_usdhc2_aux - &pinctrl_hummingboard_usdhc2 - >; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio1 4 0>; - status = "okay"; + model = "SolidRun HummingBoard Solo/DualLite"; + compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; }; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-nitrogen6x.dts linux-3.14.35/arch/arm/boot/dts/imx6dl-nitrogen6x.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-nitrogen6x.dts 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-nitrogen6x.dts 2015-03-08 14:27:37.393684503 -0500 @@ -0,0 +1,21 @@ +/* + * Copyright 2013 Boundary Devices, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-nitrogen6x.dtsi" + +/ { + model = "Freescale i.MX6 DualLite Nitrogen6x Board"; + compatible = "fsl,imx6dl-nitrogen6x", "fsl,imx6dl"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts linux-3.14.35/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts 2015-03-08 14:27:37.393684503 -0500 @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl-phytec-pfla02.dtsi" +#include "imx6qdl-phytec-pbab01.dtsi" + +/ { + model = "Phytec phyFLEX-i.MX6 DualLite/Solo Carrier-Board"; + compatible = "phytec,imx6dl-pbab01", "phytec,imx6dl-pfla02", "fsl,imx6dl"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi linux-3.14.35/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi 2015-03-08 14:27:37.393684503 -0500 @@ -0,0 +1,22 @@ +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-phytec-pfla02.dtsi" + +/ { + model = "Phytec phyFLEX-i.MX6 DualLite/Solo"; + compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x20000000>; + }; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-pinfunc.h linux-3.14.35/arch/arm/boot/dts/imx6dl-pinfunc.h --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-pinfunc.h 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-pinfunc.h 2015-03-08 14:27:37.393684503 -0500 @@ -755,6 +755,7 @@ #define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 #define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 +#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609 #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 #define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 @@ -950,6 +951,7 @@ #define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 #define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 #define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 +#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0 #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 #define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-sabreauto.dts linux-3.14.35/arch/arm/boot/dts/imx6dl-sabreauto.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-sabreauto.dts 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-sabreauto.dts 2015-03-08 14:27:37.393684503 -0500 @@ -15,3 +15,16 @@ model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; }; + +&ldb { + ipu_id = <0>; + sec_ipu_id = <0>; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-sabrelite.dts linux-3.14.35/arch/arm/boot/dts/imx6dl-sabrelite.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-sabrelite.dts 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-sabrelite.dts 2015-03-08 14:27:37.393684503 -0500 @@ -0,0 +1,20 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-sabrelite.dtsi" + +/ { + model = "Freescale i.MX6 DualLite SABRE Lite Board"; + compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-sabresd.dts linux-3.14.35/arch/arm/boot/dts/imx6dl-sabresd.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-sabresd.dts 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-sabresd.dts 2015-03-08 14:27:37.393684503 -0500 @@ -15,3 +15,20 @@ model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; }; + +&ldb { + ipu_id = <0>; + sec_ipu_id = <0>; +}; + +&pxp { + status = "okay"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts linux-3.14.35/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts 2015-03-08 14:27:37.393684503 -0500 @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabresd.dts" + +&hdmi_video { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_hdcp>; + fsl,hdcp; +}; + +&i2c2 { + status = "disable"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6q-arm2.dts linux-3.14.35/arch/arm/boot/dts/imx6q-arm2.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6q-arm2.dts 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6q-arm2.dts 2015-03-08 14:27:37.393684503 -0500 @@ -23,14 +23,27 @@ regulators { compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_3p3v: 3p3v { + reg_3p3v: regulator@0 { compatible = "regulator-fixed"; + reg = <0>; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; }; leds { @@ -46,7 +59,7 @@ &gpmi { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand_1>; + pinctrl-0 = <&pinctrl_gpmi_nand>; status = "disabled"; /* gpmi nand conflicts with SD */ }; @@ -54,28 +67,131 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - hog { + imx6q-arm2 { pinctrl_hog: hoggrp { fsl,pins = < MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 >; }; - }; - arm2 { - pinctrl_usdhc3_arm2: usdhc3grp-arm2 { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { fsl,pins = < MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 >; }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; }; }; &fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_2>; + pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; status = "okay"; }; @@ -84,8 +200,8 @@ wp-gpios = <&gpio6 14 0>; vmmc-supply = <®_3p3v>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3_1 - &pinctrl_usdhc3_arm2>; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; status = "okay"; }; @@ -93,13 +209,13 @@ non-removable; vmmc-supply = <®_3p3v>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4_1>; + pinctrl-0 = <&pinctrl_usdhc4>; status = "okay"; }; &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_2>; + pinctrl-0 = <&pinctrl_uart2>; fsl,dte-mode; fsl,uart-has-rtscts; status = "okay"; @@ -107,6 +223,6 @@ &uart4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4_1>; + pinctrl-0 = <&pinctrl_uart4>; status = "okay"; }; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6q-arm2-hsic.dts linux-3.14.35/arch/arm/boot/dts/imx6q-arm2-hsic.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6q-arm2-hsic.dts 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6q-arm2-hsic.dts 2015-03-08 14:27:37.393684503 -0500 @@ -0,0 +1,32 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6q-arm2.dts" + +&fec { + status = "disabled"; +}; + +&usbh2 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_1>; + pinctrl-1 = <&pinctrl_usbh2_2>; + osc-clkgate-delay = <0x3>; + status = "okay"; +}; + +&usbh3 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh3_1>; + pinctrl-1 = <&pinctrl_usbh3_2>; + osc-clkgate-delay = <0x3>; + status = "okay"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6q-cm-fx6.dts linux-3.14.35/arch/arm/boot/dts/imx6q-cm-fx6.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6q-cm-fx6.dts 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6q-cm-fx6.dts 2015-03-08 14:27:37.393684503 -0500 @@ -0,0 +1,107 @@ +/* + * Copyright 2013 CompuLab Ltd. + * + * Author: Valentin Raevsky + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q.dtsi" + +/ { + model = "CompuLab CM-FX6"; + compatible = "compulab,cm-fx6", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat-led { + label = "Heartbeat"; + gpios = <&gpio2 31 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&iomuxc { + imx6q-cm-fx6 { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6q-cubox-i.dts linux-3.14.35/arch/arm/boot/dts/imx6q-cubox-i.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6q-cubox-i.dts 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6q-cubox-i.dts 2015-03-08 14:27:37.393684503 -0500 @@ -13,4 +13,8 @@ &sata { status = "okay"; + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <0>; + fsl,transmit-atten-16ths = <9>; + fsl,no-spread-spectrum; }; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts linux-3.14.35/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts --- linux-3.14.35.orig/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts 2015-03-08 14:27:37.393684503 -0500 @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Sascha Hauer + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DTS_V1__ +#define __DTS_V1__ +/dts-v1/; +#endif + +#include "imx6q.dtsi" +#include "imx6qdl-dfi-fs700-m60.dtsi" + +/ { + model = "DFI FS700-M60-6QD i.MX6qd Q7 Board"; + compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi linux-3.14.35/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi --- linux-3.14.35.orig/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2015-03-08 14:27:37.393684503 -0500 @@ -5,11 +5,33 @@ #include "imx6qdl-microsom-ar8035.dtsi" / { + chosen { + bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw"; + }; + + aliases { + mxcfb0 = &mxcfb1; + }; + ir_recv: ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio3 9 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_ir>; + linux,rc-map-name = "rc-rc6-mce"; + }; + + pwmleds { + compatible = "pwm-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_pwm1>; + + front { + active-low; + label = "imx6:red:front"; + max-brightness = <248>; + pwms = <&pwm1 0 50000>; + }; }; regulators { @@ -49,10 +71,62 @@ sound-spdif { compatible = "fsl,imx-audio-spdif"; model = "imx-spdif"; - /* IMX6 doesn't implement this yet */ spdif-controller = <&spdif>; spdif-out; }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <32>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_hdmi>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_i2c2>; + + status = "okay"; + + ddc: imx6_hdmi_i2c@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &i2c3 { @@ -69,6 +143,19 @@ &iomuxc { cubox_i { + pinctrl_cubox_i_hdmi: cubox-i-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_cubox_i_i2c2: cubox-i-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + pinctrl_cubox_i_i2c3: cubox-i-i2c3 { fsl,pins = < MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 @@ -82,16 +169,35 @@ >; }; + pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led { + fsl,pins = ; + }; + pinctrl_cubox_i_spdif: cubox-i-spdif { fsl,pins = ; }; + pinctrl_cubox_i_usbh1: cubox-i-usbh1 { + fsl,pins = ; + }; + pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus { - fsl,pins = ; + fsl,pins = ; + }; + + pinctrl_cubox_i_usbotg: cubox-i-usbotg { + /* + * The Cubox-i pulls ID low, but as it's pointless + * leaving it as a pull-up, even if it is just 10uA. + */ + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; }; pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus { - fsl,pins = ; + fsl,pins = ; }; pinctrl_cubox_i_usdhc2_aux: cubox-i-usdhc2-aux { @@ -111,29 +217,76 @@ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 >; }; + + pinctrl_cubox_i_usdhc2_100mhz: cubox-i-usdhc2-100mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 + >; + }; + + pinctrl_cubox_i_usdhc2_200mhz: cubox-i-usdhc2-200mhz { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 + >; + }; }; }; &spdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_spdif>; + clocks = <&clks 197>, <&clks 0>, + <&clks 197>, <&clks 0>, + <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, + <&clks 0>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7"; status = "okay"; }; &usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_usbh1>; vbus-supply = <®_usbh1_vbus>; status = "okay"; }; &usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_usbotg>; vbus-supply = <®_usbotg_vbus>; status = "okay"; }; &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>; + pinctrl-1 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_200mhz>; vmmc-supply = <®_3p3v>; cd-gpios = <&gpio1 4 0>; + no-1-8-v; status = "okay"; }; + + +&gpc { + fsl,cpu_pupscr_sw2iso = <0xf>; + fsl,cpu_pupscr_sw = <0xf>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi linux-3.14.35/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi --- linux-3.14.35.orig/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi 1969-12-31 18:00:00.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi 2015-03-08 14:27:37.393684503 -0500 @@ -0,0 +1,199 @@ +/ { + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + dummy_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "dummy-supply"; + }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + chosen { + stdout-path = &uart1; + }; +}; + +&ecspi3 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 24 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf040b", "m25p80"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + phy-mode = "rgmii"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-dfi-fs700-m60 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */ + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */ + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ + >; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { /* module slot */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio2 2 0>; + status = "okay"; +}; + +&usdhc3 { /* baseboard slot */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; +}; + +&usdhc4 { /* eMMC */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff -Nur linux-3.14.35.orig/arch/arm/boot/dts/imx6qdl.dtsi linux-3.14.35/arch/arm/boot/dts/imx6qdl.dtsi --- linux-3.14.35.orig/arch/arm/boot/dts/imx6qdl.dtsi 2015-03-06 16:44:34.000000000 -0600 +++ linux-3.14.35/arch/arm/boot/dts/imx6qdl.dtsi 2015-03-08 14:27:37.393684503 -0500 @@ -10,10 +10,16 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include + #include "skeleton.dtsi" +#include / { aliases { + ethernet0 = &fec; + can0 = &can1; + can1 = &can2; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -24,6 +30,11 @@ i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; + ipu0 = &ipu1; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + mmc3 = &usdhc4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -33,13 +44,13 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; }; intc: interrupt-controller@00a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; interrupt-controller; reg = <0x00a01000 0x1000>, <0x00a00100 0x100>; @@ -51,20 +62,27 @@ ckil { compatible = "fsl,imx-ckil", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <32768>; }; ckih1 { compatible = "fsl,imx-ckih1", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <0>; }; osc { compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; clock-frequency = <24000000>; }; }; + pu_dummy: pudummy_reg { + compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */ + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -75,7 +93,10 @@ dma_apbh: dma-apbh@00110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; - interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; @@ -88,7 +109,7 @@ #size-cells = <1>; reg = <0x00112000 0x2000>, <0x00114000 0x2000>; reg-names = "gpmi-nand", "bch"; - interrupts = <0 15 0x04>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "bch"; clocks = <&clks 152>, <&clks 153>, <&clks 151>, <&clks 150>, <&clks 149>; @@ -109,11 +130,13 @@ L2: l2-cache@00a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; - interrupts = <0 92 0x04>; + interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; arm,tag-latency = <4 2 3>; arm,data-latency = <4 2 3>; + arm,dynamic-clk-gating; + arm,standby-mode; }; pcie: pcie@0x01000000 { @@ -126,15 +149,22 @@ 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; - interrupts = <0 123 0x04>; - clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; - clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; + interrupts = ; + interrupt-names = "pme"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 144>, <&clks 221>, <&clks 189>, <&clks 187>; + clock-names = "pcie_axi", "lvds_gate", "pcie_ref_125m", "sata_ref_100m"; status = "disabled"; }; pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 94 0x04>; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; }; aips-bus@02000000 { /* AIPS1 */ @@ -154,7 +184,7 @@ spdif: spdif@02004000 { compatible = "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; - interrupts = <0 52 0x04>; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; dma-names = "rx", "tx"; @@ -176,9 +206,11 @@ #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02008000 0x4000>; - interrupts = <0 31 0x04>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 112>, <&clks 112>; clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -187,9 +219,11 @@ #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x0200c000 0x4000>; - interrupts = <0 32 0x04>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 113>, <&clks 113>; clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -198,9 +232,11 @@ #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02010000 0x4000>; - interrupts = <0 33 0x04>; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 114>, <&clks 114>; clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -209,16 +245,18 @@ #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02014000 0x4000>; - interrupts = <0 34 0x04>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 115>, <&clks 115>; clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; uart1: serial@02020000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; - interrupts = <0 26 0x04>; + interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 160>, <&clks 161>; clock-names = "ipg", "per"; dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; @@ -227,15 +265,23 @@ }; esai: esai@02024000 { + compatible = "fsl,imx6q-esai"; reg = <0x02024000 0x4000>; - interrupts = <0 51 0x04>; + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 118>; + fsl,esai-dma-events = <24 23>; + fsl,flags = <1>; + status = "disabled"; }; ssi1: ssi@02028000 { - compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; + compatible = "fsl,imx6q-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; reg = <0x02028000 0x4000>; - interrupts = <0 46 0x04>; - clocks = <&clks 178>; + interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 178>, <&clks 157>; + clock-names = "ipg", "baud"; dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; dma-names = "rx", "tx"; @@ -245,10 +291,13 @@ }; ssi2: ssi@0202c000 { - compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; + compatible = "fsl,imx6q-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; reg = <0x0202c000 0x4000>; - interrupts = <0 47 0x04>; - clocks = <&clks 179>; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 179>, <&clks 158>; + clock-names = "ipg", "baud"; dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; dma-names = "rx", "tx"; @@ -258,10 +307,13 @@ }; ssi3: ssi@02030000 { - compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; + compatible = "fsl,imx6q-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; reg = <0x02030000 0x4000>; - interrupts = <0 48 0x04>; - clocks = <&clks 180>; + interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 180>, <&clks 159>; + clock-names = "ipg", "baud"; dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; dma-names = "rx", "tx"; @@ -271,8 +323,25 @@ }; asrc: asrc@02034000 { + compatible = "fsl,imx53-asrc"; reg = <0x02034000 0x4000>; - interrupts = <0 50 0x04>; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 107>, <&clks 156>; + clock-names = "core", "dma"; + dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, <&sdma 19 20 1>, + <&sdma 20 20 1>, <&sdma 21 20 1>, <&sdma 22 20 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + status = "okay"; + }; + + asrc_p2p: asrc_p2p { + compatible = "fsl,imx6q-asrc-p2p"; + fsl,output-rate = <48000>; + fsl,output-width = <16>; + fsl,asrc-dma-rx-events = <17 18 19>; + fsl,asrc-dma-tx-events = <20 21 22>; + status = "okay"; }; spba@0203c000 { @@ -281,8 +350,19 @@ }; vpu: vpu@02040000 { + compatible = "fsl,imx6-vpu"; reg = <0x02040000 0x3c000>; - interrupts = <0 3 0x04 0 12 0x04>; + reg-names = "vpu_regs"; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq"; + clocks = <&clks 168>, <&clks 140>, <&clks 142>; + clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram"; + iramsize = <0x21000>; + iram = <&ocram>; + resets = <&src 1>; + pu-supply = <®_pu>; + status = "disabled"; }; aipstz@0207c000 { /* AIPSTZ1 */ @@ -293,7 +373,7 @@ #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; - interrupts = <0 83 0x04>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 62>, <&clks 145>; clock-names = "ipg", "per"; }; @@ -302,7 +382,7 @@ #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; - interrupts = <0 84 0x04>; + interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 62>, <&clks 146>; clock-names = "ipg", "per"; }; @@ -311,7 +391,7 @@ #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; - interrupts = <0 85 0x04>; + interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 62>, <&clks 147>; clock-names = "ipg", "per"; }; @@ -320,7 +400,7 @@ #pwm-cells = <2>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; - interrupts = <0 86 0x04>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 62>, <&clks 148>; clock-names = "ipg", "per"; }; @@ -328,23 +408,25 @@ can1: flexcan@02090000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; - interrupts = <0 110 0x04>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 108>, <&clks 109>; clock-names = "ipg", "per"; + status = "disabled"; }; can2: flexcan@02094000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; - interrupts = <0 111 0x04>; + interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 110>, <&clks 111>; clock-names = "ipg", "per"; + status = "disabled"; }; gpt: gpt@02098000 { compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; reg = <0x02098000 0x4000>; - interrupts = <0 55 0x04>; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks 119>, <&clks 120>; clock-names = "ipg", "per"; }; @@ -352,7 +434,8 @@ gpio1: gpio@0209c000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; - interrupts = <0 66 0x04 0 67 0x04>; + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, + <0 67 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -362,7 +445,8 @@ gpio2: gpio@020a0000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; - interrupts = <0 68 0x04 0 69 0x04>; + interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, + <0 69 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -372,7 +456,8 @@ gpio3: gpio@020a4000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; - interrupts = <0 70 0x04 0 71 0x04>; + interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, + <0 71 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -382,7 +467,8 @@ gpio4: gpio@020a8000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; - interrupts = <0 72 0x04 0 73 0x04>; + interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, + <0 73 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -392,7 +478,8 @@ gpio5: gpio@020ac000 { compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; - interrupts = <0 74 0x04 0 75 0x04>; + interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, + <0 75 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -402,7 +489,8 @@ gpio6: gpio@020b0000 { compatibl