From 896b6bb853f900eaebd56447df16958bf15916db Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Thu, 20 May 2010 18:55:17 +0200 Subject: activate and refresh support for rb411/rb433 after n0-1 helped to find a way to fix my broken rb433 by using the primary bootloader via shortening a jumper I got the motivation to get this target working again. Summarize both targets to newly created rb4xx target. --- target/rb4xx/patches/ar71xx.patch | 18749 ++++++++++++++++++++++++++++++++++++ 1 file changed, 18749 insertions(+) create mode 100644 target/rb4xx/patches/ar71xx.patch (limited to 'target/rb4xx/patches') diff --git a/target/rb4xx/patches/ar71xx.patch b/target/rb4xx/patches/ar71xx.patch new file mode 100644 index 000000000..b0a342dfa --- /dev/null +++ b/target/rb4xx/patches/ar71xx.patch @@ -0,0 +1,18749 @@ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/ar71xx.c linux-2.6.33.3/arch/mips/ar71xx/ar71xx.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/ar71xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/ar71xx.c 2010-04-02 11:07:51.850954806 +0200 +@@ -0,0 +1,177 @@ ++/* ++ * AR71xx SoC routines ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++static DEFINE_MUTEX(ar71xx_flash_mutex); ++ ++void __iomem *ar71xx_ddr_base; ++EXPORT_SYMBOL_GPL(ar71xx_ddr_base); ++ ++void __iomem *ar71xx_pll_base; ++EXPORT_SYMBOL_GPL(ar71xx_pll_base); ++ ++void __iomem *ar71xx_reset_base; ++EXPORT_SYMBOL_GPL(ar71xx_reset_base); ++ ++void __iomem *ar71xx_gpio_base; ++EXPORT_SYMBOL_GPL(ar71xx_gpio_base); ++ ++void __iomem *ar71xx_usb_ctrl_base; ++EXPORT_SYMBOL_GPL(ar71xx_usb_ctrl_base); ++ ++void ar71xx_device_stop(u32 mask) ++{ ++ unsigned long flags; ++ u32 mask_inv; ++ u32 t; ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t | mask); ++ local_irq_restore(flags); ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); ++ t |= mask; ++ t &= ~mask_inv; ++ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); ++ local_irq_restore(flags); ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t | mask); ++ local_irq_restore(flags); ++ break; ++ ++ default: ++ BUG(); ++ } ++} ++EXPORT_SYMBOL_GPL(ar71xx_device_stop); ++ ++void ar71xx_device_start(u32 mask) ++{ ++ unsigned long flags; ++ u32 mask_inv; ++ u32 t; ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t & ~mask); ++ local_irq_restore(flags); ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); ++ t &= ~mask; ++ t |= mask_inv; ++ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); ++ local_irq_restore(flags); ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t & ~mask); ++ local_irq_restore(flags); ++ break; ++ ++ default: ++ BUG(); ++ } ++} ++EXPORT_SYMBOL_GPL(ar71xx_device_start); ++ ++int ar71xx_device_stopped(u32 mask) ++{ ++ unsigned long flags; ++ u32 t; ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); ++ local_irq_restore(flags); ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); ++ local_irq_restore(flags); ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); ++ local_irq_restore(flags); ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ return ((t & mask) == mask); ++} ++EXPORT_SYMBOL_GPL(ar71xx_device_stopped); ++ ++void ar71xx_ddr_flush(u32 reg) ++{ ++ ar71xx_ddr_wr(reg, 1); ++ while ((ar71xx_ddr_rr(reg) & 0x1)); ++ ++ ar71xx_ddr_wr(reg, 1); ++ while ((ar71xx_ddr_rr(reg) & 0x1)); ++} ++EXPORT_SYMBOL_GPL(ar71xx_ddr_flush); ++ ++void ar71xx_flash_acquire(void) ++{ ++ mutex_lock(&ar71xx_flash_mutex); ++} ++EXPORT_SYMBOL_GPL(ar71xx_flash_acquire); ++ ++void ar71xx_flash_release(void) ++{ ++ mutex_unlock(&ar71xx_flash_mutex); ++} ++EXPORT_SYMBOL_GPL(ar71xx_flash_release); +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ap91-eth.c linux-2.6.33.3/arch/mips/ar71xx/dev-ap91-eth.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ap91-eth.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-ap91-eth.c 2010-03-23 20:31:04.580708993 +0100 +@@ -0,0 +1,70 @@ ++/* ++ * Atheros AP91 reference board ethernet initialization ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include "devices.h" ++#include "dev-dsa.h" ++#include "dev-ap91-eth.h" ++ ++static struct dsa_chip_data ap91_dsa_chip = { ++ .port_names[0] = "cpu", ++ .port_names[1] = "lan1", ++ .port_names[2] = "lan2", ++ .port_names[3] = "lan3", ++ .port_names[4] = "lan4", ++}; ++ ++static struct dsa_platform_data ap91_dsa_data = { ++ .nr_chips = 1, ++ .chip = &ap91_dsa_chip, ++}; ++ ++static void ap91_eth_set_port_name(unsigned port, const char *name) ++{ ++ if (port < 1 || port > 5) ++ return; ++ ++ if (name) ++ ap91_dsa_chip.port_names[port] = (char *) name; ++} ++ ++void __init ap91_eth_init(u8 *mac_addr, const char *port_names[]) ++{ ++ if (mac_addr) ++ ar71xx_set_mac_base(mac_addr); ++ ++ if (port_names) { ++ int i; ++ ++ for (i = 0; i < AP91_ETH_NUM_PORT_NAMES; i++) ++ ap91_eth_set_port_name(i + 1, port_names[i]); ++ } ++ ++ /* WAN port */ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.fifo_cfg1 = 0x0fff0000; ++ ar71xx_eth0_data.fifo_cfg2 = 0x00001fff; ++ ar71xx_eth0_data.fifo_cfg3 = 0x008001ff; ++ ++ /* LAN ports */ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ar71xx_eth1_data.fifo_cfg1 = 0x0fff0000; ++ ar71xx_eth1_data.fifo_cfg2 = 0x00001fff; ++ ar71xx_eth1_data.fifo_cfg3 = 0x008001ff; ++ ++ ar71xx_add_device_mdio(0x0); ++ ar71xx_add_device_eth(1); ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_add_device_dsa(1, &ap91_dsa_data); ++} +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ap91-eth.h linux-2.6.33.3/arch/mips/ar71xx/dev-ap91-eth.h +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ap91-eth.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-ap91-eth.h 2010-03-12 19:31:46.886045750 +0100 +@@ -0,0 +1,23 @@ ++/* ++ * Atheros AP91 reference board ethernet initialization ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_AP91_ETH_H ++#define _AR71XX_DEV_AP91_ETH_H ++ ++#define AP91_ETH_NUM_PORT_NAMES 4 ++ ++#if defined(CONFIG_AR71XX_DEV_AP91_ETH) ++void ap91_eth_init(u8 *mac_addr, const char *port_names[]) __init; ++#else ++static inline void ap91_eth_init(u8 *mac_addr) { } ++#endif ++ ++#endif /* _AR71XX_DEV_AP91_ETH_H */ ++ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ap91-pci.c linux-2.6.33.3/arch/mips/ar71xx/dev-ap91-pci.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ap91-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-ap91-pci.c 2009-12-25 12:10:59.596028998 +0100 +@@ -0,0 +1,114 @@ ++/* ++ * Atheros AP91 reference board PCI initialization ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "dev-ap91-pci.h" ++ ++static struct ath9k_platform_data ap91_wmac_data; ++static char ap91_wmac_mac[6]; ++static int ap91_pci_fixup_enabled; ++ ++static struct ar71xx_pci_irq ap91_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ } ++}; ++ ++static int ap91_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ switch(PCI_SLOT(dev->devfn)) { ++ case 0: ++ dev->dev.platform_data = &ap91_wmac_data; ++ break; ++ } ++ ++ return 0; ++} ++ ++static void ap91_pci_fixup(struct pci_dev *dev) ++{ ++ void __iomem *mem; ++ u16 *cal_data; ++ u16 cmd; ++ u32 val; ++ ++ if (!ap91_pci_fixup_enabled) ++ return; ++ ++ printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev)); ++ ++ cal_data = ap91_wmac_data.eeprom_data; ++ if (*cal_data != 0xa55a) { ++ printk(KERN_ERR "PCI: no calibration data found for %s\n", ++ pci_name(dev)); ++ return; ++ } ++ ++ mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); ++ if (!mem) { ++ printk(KERN_ERR "PCI: ioremap error for device %s\n", ++ pci_name(dev)); ++ return; ++ } ++ ++ /* Setup the PCI device to allow access to the internal registers */ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff); ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ /* set pointer to first reg address */ ++ cal_data += 3; ++ while (*cal_data != 0xffff) { ++ u32 reg; ++ reg = *cal_data++; ++ val = *cal_data++; ++ val |= (*cal_data++) << 16; ++ ++ __raw_writel(val, mem + reg); ++ udelay(100); ++ } ++ ++ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); ++ dev->vendor = val & 0xffff; ++ dev->device = (val >> 16) & 0xffff; ++ ++ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); ++ dev->revision = val & 0xff; ++ dev->class = val >> 8; /* upper 3 bytes */ ++ ++ iounmap(mem); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ap91_pci_fixup); ++ ++void __init ap91_pci_init(u8 *cal_data, u8 *mac_addr) ++{ ++ if (cal_data) ++ memcpy(ap91_wmac_data.eeprom_data, cal_data, ++ sizeof(ap91_wmac_data.eeprom_data)); ++ ++ if (mac_addr) { ++ memcpy(ap91_wmac_mac, mac_addr, sizeof(ap91_wmac_mac)); ++ ap91_wmac_data.macaddr = ap91_wmac_mac; ++ } ++ ++ ar71xx_pci_plat_dev_init = ap91_pci_plat_dev_init; ++ ar71xx_pci_init(ARRAY_SIZE(ap91_pci_irqs), ap91_pci_irqs); ++ ++ ap91_pci_fixup_enabled = 1; ++} +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ap91-pci.h linux-2.6.33.3/arch/mips/ar71xx/dev-ap91-pci.h +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ap91-pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-ap91-pci.h 2010-01-05 20:38:52.249392561 +0100 +@@ -0,0 +1,21 @@ ++/* ++ * Atheros AP91 reference board PCI initialization ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_AP91_PCI_H ++#define _AR71XX_DEV_AP91_PCI_H ++ ++#if defined(CONFIG_AR71XX_DEV_AP91_PCI) ++void ap91_pci_init(u8 *cal_data, u8 *mac_addr) __init; ++#else ++static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) { } ++#endif ++ ++#endif /* _AR71XX_DEV_AP91_PCI_H */ ++ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ap94-pci.c linux-2.6.33.3/arch/mips/ar71xx/dev-ap94-pci.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ap94-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-ap94-pci.c 2010-02-13 16:30:07.244691791 +0100 +@@ -0,0 +1,159 @@ ++/* ++ * Atheros AP94 reference board PCI initialization ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "dev-ap94-pci.h" ++ ++static struct ath9k_platform_data ap94_wmac0_data; ++static struct ath9k_platform_data ap94_wmac1_data; ++static char ap94_wmac0_mac[6]; ++static char ap94_wmac1_mac[6]; ++static int ap94_pci_fixup_enabled; ++ ++static struct ar71xx_pci_irq ap94_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ }, { ++ .slot = 1, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV1, ++ } ++}; ++ ++static int ap94_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ switch(PCI_SLOT(dev->devfn)) { ++ case 17: ++ dev->dev.platform_data = &ap94_wmac0_data; ++ break; ++ ++ case 18: ++ dev->dev.platform_data = &ap94_wmac1_data; ++ break; ++ } ++ ++ return 0; ++} ++ ++static void ap94_pci_fixup(struct pci_dev *dev) ++{ ++ void __iomem *mem; ++ u16 *cal_data; ++ u16 cmd; ++ u32 bar0; ++ u32 val; ++ ++ if (!ap94_pci_fixup_enabled) ++ return; ++ ++ switch (PCI_SLOT(dev->devfn)) { ++ case 17: ++ cal_data = ap94_wmac0_data.eeprom_data; ++ break; ++ case 18: ++ cal_data = ap94_wmac1_data.eeprom_data; ++ break; ++ default: ++ return; ++ } ++ ++ if (*cal_data != 0xa55a) { ++ printk(KERN_ERR "PCI: no calibration data found for %s\n", ++ pci_name(dev)); ++ return; ++ } ++ ++ mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); ++ if (!mem) { ++ printk(KERN_ERR "PCI: ioremap error for device %s\n", ++ pci_name(dev)); ++ return; ++ } ++ ++ printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev)); ++ ++ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); ++ ++ /* Setup the PCI device to allow access to the internal registers */ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, AR71XX_PCI_MEM_BASE); ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ /* set pointer to first reg address */ ++ cal_data += 3; ++ while (*cal_data != 0xffff) { ++ u32 reg; ++ reg = *cal_data++; ++ val = *cal_data++; ++ val |= (*cal_data++) << 16; ++ ++ __raw_writel(val, mem + reg); ++ udelay(100); ++ } ++ ++ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); ++ dev->vendor = val & 0xffff; ++ dev->device = (val >> 16) & 0xffff; ++ ++ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); ++ dev->revision = val & 0xff; ++ dev->class = val >> 8; /* upper 3 bytes */ ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); ++ ++ iounmap(mem); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ap94_pci_fixup); ++ ++void __init ap94_pci_enable_quirk_wndr3700(void) ++{ ++ ap94_wmac0_data.quirk_wndr3700 = 1; ++ ap94_wmac1_data.quirk_wndr3700 = 1; ++} ++ ++void __init ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, ++ u8 *cal_data1, u8 *mac_addr1) ++{ ++ if (cal_data0) ++ memcpy(ap94_wmac0_data.eeprom_data, cal_data0, ++ sizeof(ap94_wmac0_data.eeprom_data)); ++ ++ if (cal_data1) ++ memcpy(ap94_wmac1_data.eeprom_data, cal_data1, ++ sizeof(ap94_wmac1_data.eeprom_data)); ++ ++ if (mac_addr0) { ++ memcpy(ap94_wmac0_mac, mac_addr0, sizeof(ap94_wmac0_mac)); ++ ap94_wmac0_data.macaddr = ap94_wmac0_mac; ++ } ++ ++ if (mac_addr1) { ++ memcpy(ap94_wmac1_mac, mac_addr1, sizeof(ap94_wmac1_mac)); ++ ap94_wmac1_data.macaddr = ap94_wmac1_mac; ++ } ++ ++ ar71xx_pci_plat_dev_init = ap94_pci_plat_dev_init; ++ ar71xx_pci_init(ARRAY_SIZE(ap94_pci_irqs), ap94_pci_irqs); ++ ++ ap94_pci_fixup_enabled = 1; ++} +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ap94-pci.h linux-2.6.33.3/arch/mips/ar71xx/dev-ap94-pci.h +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ap94-pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-ap94-pci.h 2010-02-13 16:30:07.244691791 +0100 +@@ -0,0 +1,28 @@ ++/* ++ * Atheros AP94 reference board PCI initialization ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_AP94_PCI_H ++#define _AR71XX_DEV_AP94_PCI_H ++ ++#if defined(CONFIG_AR71XX_DEV_AP94_PCI) ++void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, ++ u8 *cal_data1, u8 *mac_addr1) __init; ++ ++void ap94_pci_enable_quirk_wndr3700(void) __init; ++ ++#else ++static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, ++ u8 *cal_data1, u8 *mac_addr1) {} ++ ++static inline void ap94_pci_enable_quirk_wndr3700(void) {} ++#endif ++ ++#endif /* _AR71XX_DEV_AP94_PCI_H */ ++ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ar913x-wmac.c linux-2.6.33.3/arch/mips/ar71xx/dev-ar913x-wmac.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ar913x-wmac.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-ar913x-wmac.c 2010-03-23 20:31:04.941023040 +0100 +@@ -0,0 +1,68 @@ ++/* ++ * Atheros AR913x SoC built-in WMAC device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "dev-ar913x-wmac.h" ++ ++static struct ath9k_platform_data ar913x_wmac_data; ++static char ar913x_wmac_mac[6]; ++ ++static struct resource ar913x_wmac_resources[] = { ++ { ++ .start = AR91XX_WMAC_BASE, ++ .end = AR91XX_WMAC_BASE + AR91XX_WMAC_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = AR71XX_CPU_IRQ_IP2, ++ .end = AR71XX_CPU_IRQ_IP2, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device ar913x_wmac_device = { ++ .name = "ath9k", ++ .id = -1, ++ .resource = ar913x_wmac_resources, ++ .num_resources = ARRAY_SIZE(ar913x_wmac_resources), ++ .dev = { ++ .platform_data = &ar913x_wmac_data, ++ }, ++}; ++ ++void __init ar913x_add_device_wmac(u8 *cal_data, u8 *mac_addr) ++{ ++ if (cal_data) ++ memcpy(ar913x_wmac_data.eeprom_data, cal_data, ++ sizeof(ar913x_wmac_data.eeprom_data)); ++ ++ if (mac_addr) { ++ memcpy(ar913x_wmac_mac, mac_addr, sizeof(ar913x_wmac_mac)); ++ ar913x_wmac_data.macaddr = ar913x_wmac_mac; ++ } ++ ++ ar71xx_device_stop(RESET_MODULE_AMBA2WMAC); ++ mdelay(10); ++ ++ ar71xx_device_start(RESET_MODULE_AMBA2WMAC); ++ mdelay(10); ++ ++ platform_device_register(&ar913x_wmac_device); ++} +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ar913x-wmac.h linux-2.6.33.3/arch/mips/ar71xx/dev-ar913x-wmac.h +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-ar913x-wmac.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-ar913x-wmac.h 2010-01-05 20:38:52.185278525 +0100 +@@ -0,0 +1,19 @@ ++/* ++ * Atheros AR913x SoC built-in WMAC device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_AR913X_WMAC_H ++#define _AR71XX_DEV_AR913X_WMAC_H ++ ++void ar913x_add_device_wmac(u8 *cal_data, u8 *mac_addr) __init; ++ ++#endif /* _AR71XX_DEV_AR913X_WMAC_H */ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-dsa.c linux-2.6.33.3/arch/mips/ar71xx/dev-dsa.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-dsa.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-dsa.c 2010-01-05 20:38:52.058900684 +0100 +@@ -0,0 +1,50 @@ ++/* ++ * Atheros AR71xx DSA switch device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "devices.h" ++#include "dev-dsa.h" ++ ++static struct platform_device ar71xx_dsa_switch_device = { ++ .name = "dsa", ++ .id = 0, ++}; ++ ++void __init ar71xx_add_device_dsa(unsigned int id, ++ struct dsa_platform_data *d) ++{ ++ int i; ++ ++ switch (id) { ++ case 0: ++ d->netdev = &ar71xx_eth0_device.dev; ++ break; ++ case 1: ++ d->netdev = &ar71xx_eth1_device.dev; ++ break; ++ default: ++ printk(KERN_ERR ++ "ar71xx: invalid ethernet id %d for DSA switch\n", ++ id); ++ return; ++ } ++ ++ for (i = 0; i < d->nr_chips; i++) ++ d->chip[i].mii_bus = &ar71xx_mdio_device.dev; ++ ++ ar71xx_dsa_switch_device.dev.platform_data = d; ++ ++ platform_device_register(&ar71xx_dsa_switch_device); ++} +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-dsa.h linux-2.6.33.3/arch/mips/ar71xx/dev-dsa.h +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-dsa.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-dsa.h 2010-01-05 20:38:52.137278273 +0100 +@@ -0,0 +1,20 @@ ++/* ++ * Atheros AR71xx DSA switch device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_DSA_H ++#define _AR71XX_DEV_DSA_H ++ ++#include ++ ++void ar71xx_add_device_dsa(unsigned int id, ++ struct dsa_platform_data *d) __init; ++ ++#endif /* _AR71XX_DEV_DSA_H */ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-gpio-buttons.c linux-2.6.33.3/arch/mips/ar71xx/dev-gpio-buttons.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-gpio-buttons.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-gpio-buttons.c 2010-01-05 20:38:52.310262885 +0100 +@@ -0,0 +1,58 @@ ++/* ++ * Atheros AR71xx GPIO button support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include "linux/init.h" ++#include ++ ++#include "dev-gpio-buttons.h" ++ ++void __init ar71xx_add_device_gpio_buttons(int id, ++ unsigned poll_interval, ++ unsigned nbuttons, ++ struct gpio_button *buttons) ++{ ++ struct platform_device *pdev; ++ struct gpio_buttons_platform_data pdata; ++ struct gpio_button *p; ++ int err; ++ ++ p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); ++ if (!p) ++ return; ++ ++ memcpy(p, buttons, nbuttons * sizeof(*p)); ++ ++ pdev = platform_device_alloc("gpio-buttons", id); ++ if (!pdev) ++ goto err_free_buttons; ++ ++ memset(&pdata, 0, sizeof(pdata)); ++ pdata.poll_interval = poll_interval; ++ pdata.nbuttons = nbuttons; ++ pdata.buttons = p; ++ ++ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); ++ if (err) ++ goto err_put_pdev; ++ ++ ++ err = platform_device_add(pdev); ++ if (err) ++ goto err_put_pdev; ++ ++ return; ++ ++err_put_pdev: ++ platform_device_put(pdev); ++ ++err_free_buttons: ++ kfree(p); ++} +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-gpio-buttons.h linux-2.6.33.3/arch/mips/ar71xx/dev-gpio-buttons.h +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-gpio-buttons.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-gpio-buttons.h 2010-01-05 20:38:52.385278021 +0100 +@@ -0,0 +1,25 @@ ++/* ++ * Atheros AR71xx GPIO button support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_GPIO_BUTTONS_H ++#define _AR71XX_DEV_GPIO_BUTTONS_H ++ ++#include ++#include ++ ++#include ++ ++void ar71xx_add_device_gpio_buttons(int id, ++ unsigned poll_interval, ++ unsigned nbuttons, ++ struct gpio_button *buttons) __init; ++ ++#endif /* _AR71XX_DEV_GPIO_BUTTONS_H */ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/devices.c linux-2.6.33.3/arch/mips/ar71xx/devices.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/devices.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/devices.c 2010-04-02 11:07:51.658955496 +0200 +@@ -0,0 +1,575 @@ ++/* ++ * Atheros AR71xx SoC platform devices ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "devices.h" ++ ++static u8 ar71xx_mac_base[ETH_ALEN] __initdata; ++ ++static struct resource ar71xx_uart_resources[] = { ++ { ++ .start = AR71XX_UART_BASE, ++ .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) ++static struct plat_serial8250_port ar71xx_uart_data[] = { ++ { ++ .mapbase = AR71XX_UART_BASE, ++ .irq = AR71XX_MISC_IRQ_UART, ++ .flags = AR71XX_UART_FLAGS, ++ .iotype = UPIO_MEM32, ++ .regshift = 2, ++ }, { ++ /* terminating entry */ ++ } ++}; ++ ++static struct platform_device ar71xx_uart_device = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .resource = ar71xx_uart_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_uart_resources), ++ .dev = { ++ .platform_data = ar71xx_uart_data ++ }, ++}; ++ ++void __init ar71xx_add_device_uart(void) ++{ ++ ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq; ++ platform_device_register(&ar71xx_uart_device); ++} ++ ++static struct resource ar71xx_mdio_resources[] = { ++ { ++ .name = "mdio_base", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_GE0_BASE, ++ .end = AR71XX_GE0_BASE + 0x200 - 1, ++ } ++}; ++ ++static struct ag71xx_mdio_platform_data ar71xx_mdio_data; ++ ++struct platform_device ar71xx_mdio_device = { ++ .name = "ag71xx-mdio", ++ .id = -1, ++ .resource = ar71xx_mdio_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_mdio_resources), ++ .dev = { ++ .platform_data = &ar71xx_mdio_data, ++ }, ++}; ++ ++void __init ar71xx_add_device_mdio(u32 phy_mask) ++{ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ar71xx_mdio_data.is_ar7240 = 1; ++ break; ++ default: ++ break; ++ } ++ ++ ar71xx_mdio_data.phy_mask = phy_mask; ++ ++ platform_device_register(&ar71xx_mdio_device); ++} ++ ++static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift) ++{ ++ void __iomem *base; ++ u32 t; ++ ++ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); ++ ++ t = __raw_readl(base + cfg_reg); ++ t &= ~(3 << shift); ++ t |= (2 << shift); ++ __raw_writel(t, base + cfg_reg); ++ udelay(100); ++ ++ __raw_writel(pll_val, base + pll_reg); ++ ++ t |= (3 << shift); ++ __raw_writel(t, base + cfg_reg); ++ udelay(100); ++ ++ t &= ~(3 << shift); ++ __raw_writel(t, base + cfg_reg); ++ udelay(100); ++ ++ printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n", ++ (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg)); ++ ++ iounmap(base); ++} ++ ++struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; ++struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; ++ ++static u32 ar71xx_get_eth_pll(unsigned int mac, int speed) ++{ ++ struct ar71xx_eth_pll_data *pll_data; ++ u32 pll_val; ++ ++ switch (mac) { ++ case 0: ++ pll_data = &ar71xx_eth0_pll_data; ++ break; ++ case 1: ++ pll_data = &ar71xx_eth1_pll_data; ++ break; ++ default: ++ BUG(); ++ } ++ ++ switch (speed) { ++ case SPEED_10: ++ pll_val = pll_data->pll_10; ++ break; ++ case SPEED_100: ++ pll_val = pll_data->pll_100; ++ break; ++ case SPEED_1000: ++ pll_val = pll_data->pll_1000; ++ break; ++ default: ++ BUG(); ++ } ++ ++ return pll_val; ++} ++ ++static void ar71xx_set_pll_ge0(int speed) ++{ ++ u32 val = ar71xx_get_eth_pll(0, speed); ++ ++ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK, ++ val, AR71XX_ETH0_PLL_SHIFT); ++} ++ ++static void ar71xx_set_pll_ge1(int speed) ++{ ++ u32 val = ar71xx_get_eth_pll(1, speed); ++ ++ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK, ++ val, AR71XX_ETH1_PLL_SHIFT); ++} ++ ++static void ar724x_set_pll_ge0(int speed) ++{ ++ /* TODO */ ++} ++ ++static void ar724x_set_pll_ge1(int speed) ++{ ++ /* TODO */ ++} ++ ++static void ar91xx_set_pll_ge0(int speed) ++{ ++ u32 val = ar71xx_get_eth_pll(0, speed); ++ ++ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK, ++ val, AR91XX_ETH0_PLL_SHIFT); ++} ++ ++static void ar91xx_set_pll_ge1(int speed) ++{ ++ u32 val = ar71xx_get_eth_pll(1, speed); ++ ++ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK, ++ val, AR91XX_ETH1_PLL_SHIFT); ++} ++ ++static void ar71xx_ddr_flush_ge0(void) ++{ ++ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0); ++} ++ ++static void ar71xx_ddr_flush_ge1(void) ++{ ++ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1); ++} ++ ++static void ar724x_ddr_flush_ge0(void) ++{ ++ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0); ++} ++ ++static void ar724x_ddr_flush_ge1(void) ++{ ++ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1); ++} ++ ++static void ar91xx_ddr_flush_ge0(void) ++{ ++ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0); ++} ++ ++static void ar91xx_ddr_flush_ge1(void) ++{ ++ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1); ++} ++ ++static struct resource ar71xx_eth0_resources[] = { ++ { ++ .name = "mac_base", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_GE0_BASE, ++ .end = AR71XX_GE0_BASE + 0x200 - 1, ++ }, { ++ .name = "mii_ctrl", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL, ++ .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3, ++ }, { ++ .name = "mac_irq", ++ .flags = IORESOURCE_IRQ, ++ .start = AR71XX_CPU_IRQ_GE0, ++ .end = AR71XX_CPU_IRQ_GE0, ++ }, ++}; ++ ++struct ag71xx_platform_data ar71xx_eth0_data = { ++ .reset_bit = RESET_MODULE_GE0_MAC, ++}; ++ ++struct platform_device ar71xx_eth0_device = { ++ .name = "ag71xx", ++ .id = 0, ++ .resource = ar71xx_eth0_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_eth0_resources), ++ .dev = { ++ .platform_data = &ar71xx_eth0_data, ++ }, ++}; ++ ++static struct resource ar71xx_eth1_resources[] = { ++ { ++ .name = "mac_base", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_GE1_BASE, ++ .end = AR71XX_GE1_BASE + 0x200 - 1, ++ }, { ++ .name = "mii_ctrl", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL, ++ .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3, ++ }, { ++ .name = "mac_irq", ++ .flags = IORESOURCE_IRQ, ++ .start = AR71XX_CPU_IRQ_GE1, ++ .end = AR71XX_CPU_IRQ_GE1, ++ }, ++}; ++ ++struct ag71xx_platform_data ar71xx_eth1_data = { ++ .reset_bit = RESET_MODULE_GE1_MAC, ++}; ++ ++struct platform_device ar71xx_eth1_device = { ++ .name = "ag71xx", ++ .id = 1, ++ .resource = ar71xx_eth1_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_eth1_resources), ++ .dev = { ++ .platform_data = &ar71xx_eth1_data, ++ }, ++}; ++ ++#define AR71XX_PLL_VAL_1000 0x00110000 ++#define AR71XX_PLL_VAL_100 0x00001099 ++#define AR71XX_PLL_VAL_10 0x00991099 ++ ++#define AR724X_PLL_VAL_1000 0x00110000 ++#define AR724X_PLL_VAL_100 0x00001099 ++#define AR724X_PLL_VAL_10 0x00991099 ++ ++#define AR91XX_PLL_VAL_1000 0x1a000000 ++#define AR91XX_PLL_VAL_100 0x13000a44 ++#define AR91XX_PLL_VAL_10 0x00441099 ++ ++static void __init ar71xx_init_eth_pll_data(unsigned int id) ++{ ++ struct ar71xx_eth_pll_data *pll_data; ++ u32 pll_10, pll_100, pll_1000; ++ ++ switch (id) { ++ case 0: ++ pll_data = &ar71xx_eth0_pll_data; ++ break; ++ case 1: ++ pll_data = &ar71xx_eth1_pll_data; ++ break; ++ default: ++ BUG(); ++ } ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ pll_10 = AR71XX_PLL_VAL_10; ++ pll_100 = AR71XX_PLL_VAL_100; ++ pll_1000 = AR71XX_PLL_VAL_1000; ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ pll_10 = AR724X_PLL_VAL_10; ++ pll_100 = AR724X_PLL_VAL_100; ++ pll_1000 = AR724X_PLL_VAL_1000; ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ pll_10 = AR91XX_PLL_VAL_10; ++ pll_100 = AR91XX_PLL_VAL_100; ++ pll_1000 = AR91XX_PLL_VAL_1000; ++ break; ++ default: ++ BUG(); ++ } ++ ++ if (!pll_data->pll_10) ++ pll_data->pll_10 = pll_10; ++ ++ if (!pll_data->pll_100) ++ pll_data->pll_100 = pll_100; ++ ++ if (!pll_data->pll_1000) ++ pll_data->pll_1000 = pll_1000; ++} ++ ++static int ar71xx_eth_instance __initdata; ++void __init ar71xx_add_device_eth(unsigned int id) ++{ ++ struct platform_device *pdev; ++ struct ag71xx_platform_data *pdata; ++ ++ ar71xx_init_eth_pll_data(id); ++ ++ switch (id) { ++ case 0: ++ switch (ar71xx_eth0_data.phy_if_mode) { ++ case PHY_INTERFACE_MODE_MII: ++ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII; ++ break; ++ case PHY_INTERFACE_MODE_GMII: ++ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII; ++ break; ++ case PHY_INTERFACE_MODE_RMII: ++ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII; ++ break; ++ default: ++ printk(KERN_ERR "ar71xx: invalid PHY interface mode " ++ "for eth0\n"); ++ return; ++ } ++ pdev = &ar71xx_eth0_device; ++ break; ++ case 1: ++ switch (ar71xx_eth1_data.phy_if_mode) { ++ case PHY_INTERFACE_MODE_RMII: ++ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII; ++ break; ++ default: ++ printk(KERN_ERR "ar71xx: invalid PHY interface mode " ++ "for eth1\n"); ++ return; ++ } ++ pdev = &ar71xx_eth1_device; ++ break; ++ default: ++ printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id); ++ return; ++ } ++ ++ pdata = pdev->dev.platform_data; ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 ++ : ar71xx_ddr_flush_ge0; ++ pdata->set_pll = id ? ar71xx_set_pll_ge1 ++ : ar71xx_set_pll_ge0; ++ break; ++ ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 ++ : ar71xx_ddr_flush_ge0; ++ pdata->set_pll = id ? ar71xx_set_pll_ge1 ++ : ar71xx_set_pll_ge0; ++ pdata->has_gbit = 1; ++ break; ++ ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO; ++ ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO; ++ /* fall through */ ++ case AR71XX_SOC_AR7240: ++ pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 ++ : ar724x_ddr_flush_ge0; ++ pdata->set_pll = id ? ar724x_set_pll_ge1 ++ : ar724x_set_pll_ge0; ++ pdata->is_ar724x = 1; ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 ++ : ar91xx_ddr_flush_ge0; ++ pdata->set_pll = id ? ar91xx_set_pll_ge1 ++ : ar91xx_set_pll_ge0; ++ pdata->is_ar91xx = 1; ++ break; ++ ++ case AR71XX_SOC_AR9132: ++ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 ++ : ar91xx_ddr_flush_ge0; ++ pdata->set_pll = id ? ar91xx_set_pll_ge1 ++ : ar91xx_set_pll_ge0; ++ pdata->is_ar91xx = 1; ++ pdata->has_gbit = 1; ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ switch (pdata->phy_if_mode) { ++ case PHY_INTERFACE_MODE_GMII: ++ case PHY_INTERFACE_MODE_RGMII: ++ if (!pdata->has_gbit) { ++ printk(KERN_ERR "ar71xx: no gbit available on eth%d\n", ++ id); ++ return; ++ } ++ /* fallthrough */ ++ default: ++ break; ++ } ++ ++ if (is_valid_ether_addr(ar71xx_mac_base)) { ++ memcpy(pdata->mac_addr, ar71xx_mac_base, ETH_ALEN); ++ pdata->mac_addr[5] += ar71xx_eth_instance; ++ } else { ++ random_ether_addr(pdata->mac_addr); ++ printk(KERN_DEBUG ++ "ar71xx: using random MAC address for eth%d\n", ++ ar71xx_eth_instance); ++ } ++ ++ if (pdata->mii_bus_dev == NULL) ++ pdata->mii_bus_dev = &ar71xx_mdio_device.dev; ++ ++ /* Reset the device */ ++ ar71xx_device_stop(pdata->reset_bit); ++ mdelay(100); ++ ++ ar71xx_device_start(pdata->reset_bit); ++ mdelay(100); ++ ++ platform_device_register(pdev); ++ ar71xx_eth_instance++; ++} ++ ++static struct resource ar71xx_spi_resources[] = { ++ [0] = { ++ .start = AR71XX_SPI_BASE, ++ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static struct platform_device ar71xx_spi_device = { ++ .name = "ar71xx-spi", ++ .id = -1, ++ .resource = ar71xx_spi_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_spi_resources), ++}; ++ ++void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, ++ struct spi_board_info const *info, ++ unsigned n) ++{ ++ spi_register_board_info(info, n); ++ ar71xx_spi_device.dev.platform_data = pdata; ++ platform_device_register(&ar71xx_spi_device); ++} ++ ++void __init ar71xx_add_device_wdt(void) ++{ ++ platform_device_register_simple("ar71xx-wdt", -1, NULL, 0); ++} ++ ++void __init ar71xx_set_mac_base(unsigned char *mac) ++{ ++ memcpy(ar71xx_mac_base, mac, ETH_ALEN); ++} ++ ++void __init ar71xx_parse_mac_addr(char *mac_str) ++{ ++ u8 tmp[ETH_ALEN]; ++ int t; ++ ++ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", ++ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); ++ ++ if (t != ETH_ALEN) ++ t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx", ++ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); ++ ++ if (t == ETH_ALEN) ++ ar71xx_set_mac_base(tmp); ++ else ++ printk(KERN_DEBUG "ar71xx: failed to parse mac address " ++ "\"%s\"\n", mac_str); ++} ++ ++static int __init ar71xx_ethaddr_setup(char *str) ++{ ++ ar71xx_parse_mac_addr(str); ++ return 1; ++} ++__setup("ethaddr=", ar71xx_ethaddr_setup); ++ ++static int __init ar71xx_kmac_setup(char *str) ++{ ++ ar71xx_parse_mac_addr(str); ++ return 1; ++} ++__setup("kmac=", ar71xx_kmac_setup); +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/devices.h linux-2.6.33.3/arch/mips/ar71xx/devices.h +--- linux-2.6.33.3.orig/arch/mips/ar71xx/devices.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/devices.h 2010-01-05 20:38:52.093279648 +0100 +@@ -0,0 +1,48 @@ ++/* ++ * Atheros AR71xx SoC device definitions ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __AR71XX_DEVICES_H ++#define __AR71XX_DEVICES_H ++ ++#include ++ ++struct platform_device; ++ ++void ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, ++ struct spi_board_info const *info, ++ unsigned n) __init; ++ ++void ar71xx_set_mac_base(unsigned char *mac) __init; ++void ar71xx_parse_mac_addr(char *mac_str) __init; ++ ++struct ar71xx_eth_pll_data { ++ u32 pll_10; ++ u32 pll_100; ++ u32 pll_1000; ++}; ++ ++extern struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; ++extern struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; ++ ++extern struct ag71xx_platform_data ar71xx_eth0_data; ++extern struct ag71xx_platform_data ar71xx_eth1_data; ++extern struct platform_device ar71xx_eth0_device; ++extern struct platform_device ar71xx_eth1_device; ++void ar71xx_add_device_eth(unsigned int id) __init; ++ ++extern struct platform_device ar71xx_mdio_device; ++void ar71xx_add_device_mdio(u32 phy_mask) __init; ++ ++void ar71xx_add_device_uart(void) __init; ++ ++void ar71xx_add_device_wdt(void) __init; ++ ++#endif /* __AR71XX_DEVICES_H */ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-leds-gpio.c linux-2.6.33.3/arch/mips/ar71xx/dev-leds-gpio.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-leds-gpio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-leds-gpio.c 2010-01-05 20:38:51.933280770 +0100 +@@ -0,0 +1,56 @@ ++/* ++ * Atheros AR71xx GPIO LED device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include "dev-leds-gpio.h" ++ ++void __init ar71xx_add_device_leds_gpio(int id, unsigned num_leds, ++ struct gpio_led *leds) ++{ ++ struct platform_device *pdev; ++ struct gpio_led_platform_data pdata; ++ struct gpio_led *p; ++ int err; ++ ++ p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); ++ if (!p) ++ return; ++ ++ memcpy(p, leds, num_leds * sizeof(*p)); ++ ++ pdev = platform_device_alloc("leds-gpio", id); ++ if (!pdev) ++ goto err_free_leds; ++ ++ memset(&pdata, 0, sizeof(pdata)); ++ pdata.num_leds = num_leds; ++ pdata.leds = p; ++ ++ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); ++ if (err) ++ goto err_put_pdev; ++ ++ err = platform_device_add(pdev); ++ if (err) ++ goto err_put_pdev; ++ ++ return; ++ ++err_put_pdev: ++ platform_device_put(pdev); ++ ++err_free_leds: ++ kfree(p); ++} +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-leds-gpio.h linux-2.6.33.3/arch/mips/ar71xx/dev-leds-gpio.h +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-leds-gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-leds-gpio.h 2010-01-05 20:38:51.937279883 +0100 +@@ -0,0 +1,21 @@ ++/* ++ * Atheros AR71xx GPIO LED device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_LEDS_GPIO_H ++#define _AR71XX_DEV_LEDS_GPIO_H ++ ++#include ++ ++void ar71xx_add_device_leds_gpio(int id, ++ unsigned num_leds, ++ struct gpio_led *leds) __init; ++ ++#endif /* _AR71XX_DEV_LEDS_GPIO_H */ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-m25p80.c linux-2.6.33.3/arch/mips/ar71xx/dev-m25p80.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-m25p80.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-m25p80.c 2009-12-25 12:10:59.660426865 +0100 +@@ -0,0 +1,30 @@ ++/* ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include "devices.h" ++#include "dev-m25p80.h" ++ ++static struct spi_board_info ar71xx_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "m25p80", ++ } ++}; ++ ++void __init ar71xx_add_device_m25p80(struct flash_platform_data *pdata) ++{ ++ ar71xx_spi_info[0].platform_data = pdata; ++ ar71xx_add_device_spi(NULL, ar71xx_spi_info, ++ ARRAY_SIZE(ar71xx_spi_info)); ++} +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-m25p80.h linux-2.6.33.3/arch/mips/ar71xx/dev-m25p80.h +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-m25p80.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-m25p80.h 2009-12-25 12:10:59.660426865 +0100 +@@ -0,0 +1,16 @@ ++/* ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_M25P80_H ++#define _AR71XX_DEV_M25P80_H ++ ++#include ++ ++void ar71xx_add_device_m25p80(struct flash_platform_data *pdata) __init; ++ ++#endif /* _AR71XX_DEV_M25P80_H */ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-pb42-pci.c linux-2.6.33.3/arch/mips/ar71xx/dev-pb42-pci.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-pb42-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-pb42-pci.c 2010-01-05 20:38:52.185278525 +0100 +@@ -0,0 +1,40 @@ ++/* ++ * Atheros PB42 reference board PCI initialization ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++ ++#include ++#include ++ ++#include "dev-pb42-pci.h" ++ ++static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ }, { ++ .slot = 1, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV1, ++ }, { ++ .slot = 2, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV2, ++ } ++}; ++ ++void __init pb42_pci_init(void) ++{ ++ ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs); ++} +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-pb42-pci.h linux-2.6.33.3/arch/mips/ar71xx/dev-pb42-pci.h +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-pb42-pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-pb42-pci.h 2010-01-05 20:38:52.217277854 +0100 +@@ -0,0 +1,21 @@ ++/* ++ * Atheros PB42 reference board PCI initialization ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_PB42_PCI_H ++#define _AR71XX_DEV_PB42_PCI_H ++ ++#if defined(CONFIG_AR71XX_DEV_PB42_PCI) ++void pb42_pci_init(void) __init; ++#else ++static inline void pb42_pci_init(void) { } ++#endif ++ ++#endif /* _AR71XX_DEV_PB42_PCI_H */ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-pb9x-pci.c linux-2.6.33.3/arch/mips/ar71xx/dev-pb9x-pci.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-pb9x-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-pb9x-pci.c 2010-04-02 11:07:51.650955594 +0200 +@@ -0,0 +1,33 @@ ++/* ++ * Atheros PB9x reference board PCI initialization ++ * ++ * Copyright (C) 2010 Felix Fietkau ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++ ++#include ++#include ++ ++#include "dev-pb9x-pci.h" ++ ++static struct ar71xx_pci_irq pb9x_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ } ++}; ++ ++void __init pb9x_pci_init(void) ++{ ++ ar71xx_pci_init(ARRAY_SIZE(pb9x_pci_irqs), pb9x_pci_irqs); ++} +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-pb9x-pci.h linux-2.6.33.3/arch/mips/ar71xx/dev-pb9x-pci.h +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-pb9x-pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-pb9x-pci.h 2010-04-02 11:07:51.654953031 +0200 +@@ -0,0 +1,22 @@ ++/* ++ * Atheros PB9x reference board PCI initialization ++ * ++ * Copyright (C) 2010 Felix Fietkau ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_PB9X_PCI_H ++#define _AR71XX_DEV_PB9X_PCI_H ++ ++#if defined(CONFIG_AR71XX_DEV_PB9X_PCI) ++void pb9x_pci_init(void) __init; ++#else ++static inline void pb9x_pci_init(void) { } ++#endif ++ ++#endif /* _AR71XX_DEV_PB9X_PCI_H */ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-usb.c linux-2.6.33.3/arch/mips/ar71xx/dev-usb.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-usb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-usb.c 2010-04-02 11:07:51.694953375 +0200 +@@ -0,0 +1,181 @@ ++/* ++ * Atheros AR71xx USB host device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "dev-usb.h" ++ ++/* ++ * OHCI (USB full speed host controller) ++ */ ++static struct resource ar71xx_ohci_resources[] = { ++ [0] = { ++ .start = AR71XX_OHCI_BASE, ++ .end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = AR71XX_MISC_IRQ_OHCI, ++ .end = AR71XX_MISC_IRQ_OHCI, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource ar7240_ohci_resources[] = { ++ [0] = { ++ .start = AR7240_OHCI_BASE, ++ .end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = AR71XX_CPU_IRQ_USB, ++ .end = AR71XX_CPU_IRQ_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 ar71xx_ohci_dmamask = DMA_BIT_MASK(32); ++static struct platform_device ar71xx_ohci_device = { ++ .name = "ar71xx-ohci", ++ .id = -1, ++ .resource = ar71xx_ohci_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_ohci_resources), ++ .dev = { ++ .dma_mask = &ar71xx_ohci_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++}; ++ ++/* ++ * EHCI (USB full speed host controller) ++ */ ++static struct resource ar71xx_ehci_resources[] = { ++ [0] = { ++ .start = AR71XX_EHCI_BASE, ++ .end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = AR71XX_CPU_IRQ_USB, ++ .end = AR71XX_CPU_IRQ_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 ar71xx_ehci_dmamask = DMA_BIT_MASK(32); ++static struct ar71xx_ehci_platform_data ar71xx_ehci_data; ++ ++static struct platform_device ar71xx_ehci_device = { ++ .name = "ar71xx-ehci", ++ .id = -1, ++ .resource = ar71xx_ehci_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_ehci_resources), ++ .dev = { ++ .dma_mask = &ar71xx_ehci_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ .platform_data = &ar71xx_ehci_data, ++ }, ++}; ++ ++#define AR71XX_USB_RESET_MASK \ ++ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_PHY \ ++ | RESET_MODULE_USB_OHCI_DLL) ++ ++#define AR7240_USB_RESET_MASK \ ++ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_OHCI_DLL_7240) ++ ++static void __init ar71xx_usb_setup(void) ++{ ++ ar71xx_device_stop(AR71XX_USB_RESET_MASK); ++ mdelay(1000); ++ ar71xx_device_start(AR71XX_USB_RESET_MASK); ++ ++ /* Turning on the Buff and Desc swap bits */ ++ ar71xx_usb_ctrl_wr(USB_CTRL_REG_CONFIG, 0xf0000); ++ ++ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ ++ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x20c00); ++ ++ mdelay(900); ++ ++ platform_device_register(&ar71xx_ohci_device); ++ platform_device_register(&ar71xx_ehci_device); ++} ++ ++static void __init ar7240_usb_setup(void) ++{ ++ ar71xx_device_stop(AR7240_USB_RESET_MASK); ++ mdelay(1000); ++ ar71xx_device_start(AR7240_USB_RESET_MASK); ++ ++ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ ++ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x3); ++ ++ if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) { ++ ar71xx_ehci_data.is_ar91xx = 1; ++ ar71xx_ehci_device.resource = ar7240_ohci_resources; ++ ar71xx_ehci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); ++ platform_device_register(&ar71xx_ehci_device); ++ } else { ++ ar71xx_ohci_device.resource = ar7240_ohci_resources; ++ ar71xx_ohci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); ++ platform_device_register(&ar71xx_ohci_device); ++ } ++} ++ ++static void __init ar91xx_usb_setup(void) ++{ ++ ar71xx_device_stop(RESET_MODULE_USBSUS_OVERRIDE); ++ mdelay(10); ++ ++ ar71xx_device_start(RESET_MODULE_USB_HOST); ++ mdelay(10); ++ ++ ar71xx_device_start(RESET_MODULE_USB_PHY); ++ mdelay(10); ++ ++ ar71xx_ehci_data.is_ar91xx = 1; ++ platform_device_register(&ar71xx_ehci_device); ++} ++ ++void __init ar71xx_add_device_usb(void) ++{ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ar7240_usb_setup(); ++ break; ++ ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ ar71xx_usb_setup(); ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ ar91xx_usb_setup(); ++ break; ++ ++ default: ++ BUG(); ++ } ++} +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/dev-usb.h linux-2.6.33.3/arch/mips/ar71xx/dev-usb.h +--- linux-2.6.33.3.orig/arch/mips/ar71xx/dev-usb.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/dev-usb.h 2010-01-05 20:38:52.326200390 +0100 +@@ -0,0 +1,17 @@ ++/* ++ * Atheros AR71xx USB host device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_USB_H ++#define _AR71XX_DEV_USB_H ++ ++void ar71xx_add_device_usb(void) __init; ++ ++#endif /* _AR71XX_DEV_USB_H */ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/early_printk.c linux-2.6.33.3/arch/mips/ar71xx/early_printk.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/early_printk.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/early_printk.c 2009-12-13 20:45:21.280039916 +0100 +@@ -0,0 +1,30 @@ ++/* ++ * Atheros AR71xx SoC early printk support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++ ++#define UART_READ(r) \ ++ __raw_readl((void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE) + 4 * (r))) ++ ++#define UART_WRITE(r, v) \ ++ __raw_writel((v), (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE) + 4*(r))) ++ ++void prom_putchar(unsigned char ch) ++{ ++ while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); ++ UART_WRITE(UART_TX, ch); ++ while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); ++} ++ +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/gpio.c linux-2.6.33.3/arch/mips/ar71xx/gpio.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/gpio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/gpio.c 2010-04-02 11:07:51.646954247 +0200 +@@ -0,0 +1,182 @@ ++/* ++ * Atheros AR71xx SoC GPIO API support ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++static DEFINE_SPINLOCK(ar71xx_gpio_lock); ++ ++unsigned long ar71xx_gpio_count; ++EXPORT_SYMBOL(ar71xx_gpio_count); ++ ++void __ar71xx_gpio_set_value(unsigned gpio, int value) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ ++ if (value) ++ __raw_writel(1 << gpio, base + GPIO_REG_SET); ++ else ++ __raw_writel(1 << gpio, base + GPIO_REG_CLEAR); ++} ++EXPORT_SYMBOL(__ar71xx_gpio_set_value); ++ ++int __ar71xx_gpio_get_value(unsigned gpio) ++{ ++ return (__raw_readl(ar71xx_gpio_base + GPIO_REG_IN) >> gpio) & 1; ++} ++EXPORT_SYMBOL(__ar71xx_gpio_get_value); ++ ++static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset) ++{ ++ return __ar71xx_gpio_get_value(offset); ++} ++ ++static void ar71xx_gpio_set_value(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ __ar71xx_gpio_set_value(offset, value); ++} ++ ++static int ar71xx_gpio_direction_input(struct gpio_chip *chip, ++ unsigned offset) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); ++ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(1 << offset), ++ base + GPIO_REG_OE); ++ ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); ++ ++ return 0; ++} ++ ++static int ar71xx_gpio_direction_output(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); ++ ++ if (value) ++ __raw_writel(1 << offset, base + GPIO_REG_SET); ++ else ++ __raw_writel(1 << offset, base + GPIO_REG_CLEAR); ++ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) | (1 << offset), ++ base + GPIO_REG_OE); ++ ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); ++ ++ return 0; ++} ++ ++static struct gpio_chip ar71xx_gpio_chip = { ++ .label = "ar71xx", ++ .get = ar71xx_gpio_get_value, ++ .set = ar71xx_gpio_set_value, ++ .direction_input = ar71xx_gpio_direction_input, ++ .direction_output = ar71xx_gpio_direction_output, ++ .base = 0, ++ .ngpio = AR71XX_GPIO_COUNT, ++}; ++ ++void ar71xx_gpio_function_enable(u32 mask) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); ++ ++ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) | mask, ++ base + GPIO_REG_FUNC); ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_FUNC); ++ ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); ++} ++ ++void ar71xx_gpio_function_disable(u32 mask) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); ++ ++ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) & ~mask, ++ base + GPIO_REG_FUNC); ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_FUNC); ++ ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); ++} ++ ++void ar71xx_gpio_function_setup(u32 set, u32 clear) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); ++ ++ __raw_writel((__raw_readl(base + GPIO_REG_FUNC) & ~clear) | set, ++ base + GPIO_REG_FUNC); ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_FUNC); ++ ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); ++} ++EXPORT_SYMBOL(ar71xx_gpio_function_setup); ++ ++void __init ar71xx_gpio_init(void) ++{ ++ int err; ++ ++ if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, ++ "AR71xx GPIO controller")) ++ panic("cannot allocate AR71xx GPIO registers page"); ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT; ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT; ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT; ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ err = gpiochip_add(&ar71xx_gpio_chip); ++ if (err) ++ panic("cannot add AR71xx GPIO chip, error=%d", err); ++} +diff -Nur linux-2.6.33.3.orig/arch/mips/ar71xx/irq.c linux-2.6.33.3/arch/mips/ar71xx/irq.c +--- linux-2.6.33.3.orig/arch/mips/ar71xx/irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.33.3/arch/mips/ar71xx/irq.c 2010-05-16 13:17:31.871599360 +0200 +@@ -0,0 +1,295 @@ ++/* ++ * Atheros AR71xx SoC specific interrupt handling ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++static int ip2_flush_reg; ++ ++static void ar71xx_gpio_irq_dispatch(void) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ u32 pending; ++ ++ pending = __raw_readl(base + GPIO_REG_INT_PENDING) & ++ __raw_readl(base + GPIO_REG_INT_ENABLE); ++ ++ if (pending) ++ do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);