From 6d99c6b253a1816d3efc12578deb05222ff3f9f8 Mon Sep 17 00:00:00 2001
From: Waldemar Brodkorb <wbx@openadk.org>
Date: Wed, 7 Oct 2015 15:24:49 +0200
Subject: bump linux kernels
---
.../4.1.10/0001-mtd-add-rb4xx-nand-driver.patch | 351 ++
...htool-ioctl-support-used-by-ag71xx-driver.patch | 80 +
.../4.1.10/0003-net-add-ag71xx-mac-driver.patch | 4185 ++++++++++++++++++
...ious-flags-to-spi_transfer-and-spi_messag.patch | 34 +
.../4.1.10/0006-spi-add-rb4xx-SPI-driver.patch | 538 +++
.../4.1.10/0007-spi-add-rb4xx-cpld-driver.patch | 525 +++
.../4.1.10/0008-gpio-add-GPIO-latch-driver.patch | 290 ++
...0009-spi-export-spi_bitbang_bufs-function.patch | 45 +
...spi-add-type-field-to-spi_transfer-struct.patch | 37 +
...mips-ath79-swizzle-PCI-address-for-ar71xx.patch | 130 +
.../4.1.10/0013-net-add-swconfig-support.patch | 1837 ++++++++
.../4.1.10/0015-phy-add-ar8216-PHY-support.patch | 4513 ++++++++++++++++++++
.../0016-phy-mdio-bitbang-ignore-TA-value.patch | 44 +
.../0017-MIPS-ath79-fix-maximum-timeout.patch | 37 +
...PHY-drivers-to-insert-packet-mangle-hooks.patch | 167 +
...9-MIPS-ath79-process-board-cmdline-option.patch | 26 +
...020-spi-ath79-add-fast-flash-read-support.patch | 202 +
.../4.1.10/0021-phy-add-mdio-boardinfo.patch | 199 +
...0022-mips-ath79-add-ath79-ethernet-driver.patch | 1429 +++++++
...S-ath79-add-Mikrotik-rb4xx-device-support.patch | 536 +++
.../4.1.10/0024-various-fixups-for-Werror.patch | 66 +
.../0025-rb4xx_nand-add-partition-for-cfgfs.patch | 28 +
.../4.1.10/0027-ar71xx-add-zboot-support.patch | 64 +
...028-ag71xx-workaround-some-link-state-bug.patch | 39 +
.../4.1.10/0029-gpio-add-gpio-latch-driver.patch | 1261 ++++++
.../4.1.6/0001-mtd-add-rb4xx-nand-driver.patch | 351 --
...htool-ioctl-support-used-by-ag71xx-driver.patch | 80 -
.../4.1.6/0003-net-add-ag71xx-mac-driver.patch | 4185 ------------------
...ious-flags-to-spi_transfer-and-spi_messag.patch | 34 -
.../4.1.6/0006-spi-add-rb4xx-SPI-driver.patch | 538 ---
.../4.1.6/0007-spi-add-rb4xx-cpld-driver.patch | 525 ---
.../4.1.6/0008-gpio-add-GPIO-latch-driver.patch | 290 --
...0009-spi-export-spi_bitbang_bufs-function.patch | 45 -
...spi-add-type-field-to-spi_transfer-struct.patch | 37 -
...mips-ath79-swizzle-PCI-address-for-ar71xx.patch | 130 -
.../4.1.6/0013-net-add-swconfig-support.patch | 1837 --------
.../4.1.6/0015-phy-add-ar8216-PHY-support.patch | 4513 --------------------
.../0016-phy-mdio-bitbang-ignore-TA-value.patch | 44 -
.../0017-MIPS-ath79-fix-maximum-timeout.patch | 37 -
...PHY-drivers-to-insert-packet-mangle-hooks.patch | 167 -
...9-MIPS-ath79-process-board-cmdline-option.patch | 26 -
...020-spi-ath79-add-fast-flash-read-support.patch | 202 -
.../4.1.6/0021-phy-add-mdio-boardinfo.patch | 199 -
...0022-mips-ath79-add-ath79-ethernet-driver.patch | 1429 -------
...S-ath79-add-Mikrotik-rb4xx-device-support.patch | 536 ---
.../4.1.6/0024-various-fixups-for-Werror.patch | 66 -
.../0025-rb4xx_nand-add-partition-for-cfgfs.patch | 28 -
.../4.1.6/0027-ar71xx-add-zboot-support.patch | 64 -
...028-ag71xx-workaround-some-link-state-bug.patch | 39 -
.../4.1.6/0029-gpio-add-gpio-latch-driver.patch | 1261 ------
50 files changed, 16663 insertions(+), 16663 deletions(-)
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0001-mtd-add-rb4xx-nand-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0002-phy-add-ethtool-ioctl-support-used-by-ag71xx-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0003-net-add-ag71xx-mac-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0005-spi-add-various-flags-to-spi_transfer-and-spi_messag.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0006-spi-add-rb4xx-SPI-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0007-spi-add-rb4xx-cpld-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0008-gpio-add-GPIO-latch-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0009-spi-export-spi_bitbang_bufs-function.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0010-spi-add-type-field-to-spi_transfer-struct.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0012-mips-ath79-swizzle-PCI-address-for-ar71xx.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0013-net-add-swconfig-support.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0015-phy-add-ar8216-PHY-support.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0016-phy-mdio-bitbang-ignore-TA-value.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0017-MIPS-ath79-fix-maximum-timeout.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0018-net-allow-PHY-drivers-to-insert-packet-mangle-hooks.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0019-MIPS-ath79-process-board-cmdline-option.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0020-spi-ath79-add-fast-flash-read-support.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0021-phy-add-mdio-boardinfo.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0022-mips-ath79-add-ath79-ethernet-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0023-MIPS-ath79-add-Mikrotik-rb4xx-device-support.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0024-various-fixups-for-Werror.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0025-rb4xx_nand-add-partition-for-cfgfs.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0027-ar71xx-add-zboot-support.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0028-ag71xx-workaround-some-link-state-bug.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.10/0029-gpio-add-gpio-latch-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0001-mtd-add-rb4xx-nand-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0002-phy-add-ethtool-ioctl-support-used-by-ag71xx-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0003-net-add-ag71xx-mac-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0005-spi-add-various-flags-to-spi_transfer-and-spi_messag.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0006-spi-add-rb4xx-SPI-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0007-spi-add-rb4xx-cpld-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0008-gpio-add-GPIO-latch-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0009-spi-export-spi_bitbang_bufs-function.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0010-spi-add-type-field-to-spi_transfer-struct.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0012-mips-ath79-swizzle-PCI-address-for-ar71xx.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0013-net-add-swconfig-support.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0015-phy-add-ar8216-PHY-support.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0016-phy-mdio-bitbang-ignore-TA-value.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0017-MIPS-ath79-fix-maximum-timeout.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0018-net-allow-PHY-drivers-to-insert-packet-mangle-hooks.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0019-MIPS-ath79-process-board-cmdline-option.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0020-spi-ath79-add-fast-flash-read-support.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0021-phy-add-mdio-boardinfo.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0022-mips-ath79-add-ath79-ethernet-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0023-MIPS-ath79-add-Mikrotik-rb4xx-device-support.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0024-various-fixups-for-Werror.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0025-rb4xx_nand-add-partition-for-cfgfs.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0027-ar71xx-add-zboot-support.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0028-ag71xx-workaround-some-link-state-bug.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/4.1.6/0029-gpio-add-gpio-latch-driver.patch
(limited to 'target/mips/mikrotik-rb4xx')
diff --git a/target/mips/mikrotik-rb4xx/patches/4.1.10/0001-mtd-add-rb4xx-nand-driver.patch b/target/mips/mikrotik-rb4xx/patches/4.1.10/0001-mtd-add-rb4xx-nand-driver.patch
new file mode 100644
index 000000000..8199de991
--- /dev/null
+++ b/target/mips/mikrotik-rb4xx/patches/4.1.10/0001-mtd-add-rb4xx-nand-driver.patch
@@ -0,0 +1,351 @@
+From 1e692cc0c53202b932eedabd0315107910c5b093 Mon Sep 17 00:00:00 2001
+From: Phil Sutter <phil@nwl.cc>
+Date: Tue, 13 May 2014 00:08:54 +0200
+Subject: [PATCH] mtd: add rb4xx nand driver
+
+---
+ drivers/mtd/nand/Kconfig | 4 +
+ drivers/mtd/nand/Makefile | 1 +
+ drivers/mtd/nand/rb4xx_nand.c | 305 ++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 310 insertions(+)
+ create mode 100644 drivers/mtd/nand/rb4xx_nand.c
+
+diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
+index 90ff447..bb01309 100644
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -510,4 +510,8 @@ config MTD_NAND_XWAY
+ Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
+ to the External Bus Unit (EBU).
+
++config MTD_NAND_RB4XX
++ tristate "NAND flash driver for RouterBoard 4xx series"
++ depends on MTD_NAND && ATH79_MACH_RB4XX
++
+ endif # MTD_NAND
+diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
+index 542b568..e2b5e1c 100644
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -31,6 +31,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
+ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
+ obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
+ obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
++obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
+ obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
+ obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
+diff --git a/drivers/mtd/nand/rb4xx_nand.c b/drivers/mtd/nand/rb4xx_nand.c
+new file mode 100644
+index 0000000..5b9841b
+--- /dev/null
++++ b/drivers/mtd/nand/rb4xx_nand.c
+@@ -0,0 +1,305 @@
++/*
++ * NAND flash driver for the MikroTik RouterBoard 4xx series
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This file was based on the driver for Linux 2.6.22 published by
++ * MikroTik for their RouterBoard 4xx series devices.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/gpio.h>
++#include <linux/slab.h>
++
++#include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/rb4xx_cpld.h>
++
++#define DRV_NAME "rb4xx-nand"
++#define DRV_VERSION "0.2.0"
++#define DRV_DESC "NAND flash driver for RouterBoard 4xx series"
++
++#define RB4XX_NAND_GPIO_READY 5
++#define RB4XX_NAND_GPIO_ALE 37
++#define RB4XX_NAND_GPIO_CLE 38
++#define RB4XX_NAND_GPIO_NCE 39
++
++struct rb4xx_nand_info {
++ struct nand_chip chip;
++ struct mtd_info mtd;
++};
++
++/*
++ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
++ * will not be able to find the kernel that we load.
++ */
++static struct nand_ecclayout rb4xx_nand_ecclayout = {
++ .eccbytes = 6,
++ .eccpos = { 8, 9, 10, 13, 14, 15 },
++ .oobavail = 9,
++ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
++};
++
++static struct mtd_partition rb4xx_nand_partitions[] = {
++ {
++ .name = "booter",
++ .offset = 0,
++ .size = (256 * 1024),
++ .mask_flags = MTD_WRITEABLE,
++ },
++ {
++ .name = "kernel",
++ .offset = (256 * 1024),
++ .size = (4 * 1024 * 1024) - (256 * 1024),
++ },
++ {
++ .name = "rootfs",
++ .offset = MTDPART_OFS_NXTBLK,
++ .size = MTDPART_SIZ_FULL,
++ },
++};
++
++static int rb4xx_nand_dev_ready(struct mtd_info *mtd)
++{
++ return gpio_get_value_cansleep(RB4XX_NAND_GPIO_READY);
++}
++
++static void rb4xx_nand_write_cmd(unsigned char cmd)
++{
++ unsigned char data = cmd;
++ int err;
++
++ err = rb4xx_cpld_write(&data, 1);
++ if (err)
++ pr_err("rb4xx_nand: write cmd failed, err=%d\n", err);
++}
++
++static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
++ unsigned int ctrl)
++{
++ if (ctrl & NAND_CTRL_CHANGE) {
++ gpio_set_value_cansleep(RB4XX_NAND_GPIO_CLE,
++ (ctrl & NAND_CLE) ? 1 : 0);
++ gpio_set_value_cansleep(RB4XX_NAND_GPIO_ALE,
++ (ctrl & NAND_ALE) ? 1 : 0);
++ gpio_set_value_cansleep(RB4XX_NAND_GPIO_NCE,
++ (ctrl & NAND_NCE) ? 0 : 1);
++ }
++
++ if (cmd != NAND_CMD_NONE)
++ rb4xx_nand_write_cmd(cmd);
++}
++
++static unsigned char rb4xx_nand_read_byte(struct mtd_info *mtd)
++{
++ unsigned char data = 0;
++ int err;
++
++ err = rb4xx_cpld_read(&data, NULL, 1);
++ if (err) {
++ pr_err("rb4xx_nand: read data failed, err=%d\n", err);
++ data = 0xff;
++ }
++
++ return data;
++}
++
++static void rb4xx_nand_write_buf(struct mtd_info *mtd, const unsigned char *buf,
++ int len)
++{
++ int err;
++
++ err = rb4xx_cpld_write(buf, len);
++ if (err)
++ pr_err("rb4xx_nand: write buf failed, err=%d\n", err);
++}
++
++static void rb4xx_nand_read_buf(struct mtd_info *mtd, unsigned char *buf,
++ int len)
++{
++ int err;
++
++ err = rb4xx_cpld_read(buf, NULL, len);
++ if (err)
++ pr_err("rb4xx_nand: read buf failed, err=%d\n", err);
++}
++
++static int rb4xx_nand_probe(struct platform_device *pdev)
++{
++ struct rb4xx_nand_info *info;
++ int ret;
++
++ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n");
++
++ ret = gpio_request(RB4XX_NAND_GPIO_READY, "NAND RDY");
++ if (ret) {
++ dev_err(&pdev->dev, "unable to request gpio %d\n",
++ RB4XX_NAND_GPIO_READY);
++ goto err;
++ }
++
++ ret = gpio_direction_input(RB4XX_NAND_GPIO_READY);
++ if (ret) {
++ dev_err(&pdev->dev, "unable to set input mode on gpio %d\n",
++ RB4XX_NAND_GPIO_READY);
++ goto err_free_gpio_ready;
++ }
++
++ ret = gpio_request(RB4XX_NAND_GPIO_ALE, "NAND ALE");
++ if (ret) {
++ dev_err(&pdev->dev, "unable to request gpio %d\n",
++ RB4XX_NAND_GPIO_ALE);
++ goto err_free_gpio_ready;
++ }
++
++ ret = gpio_direction_output(RB4XX_NAND_GPIO_ALE, 0);
++ if (ret) {
++ dev_err(&pdev->dev, "unable to set output mode on gpio %d\n",
++ RB4XX_NAND_GPIO_ALE);
++ goto err_free_gpio_ale;
++ }
++
++ ret = gpio_request(RB4XX_NAND_GPIO_CLE, "NAND CLE");
++ if (ret) {
++ dev_err(&pdev->dev, "unable to request gpio %d\n",
++ RB4XX_NAND_GPIO_CLE);
++ goto err_free_gpio_ale;
++ }
++
++ ret = gpio_direction_output(RB4XX_NAND_GPIO_CLE, 0);
++ if (ret) {
++ dev_err(&pdev->dev, "unable to set output mode on gpio %d\n",
++ RB4XX_NAND_GPIO_CLE);
++ goto err_free_gpio_cle;
++ }
++
++ ret = gpio_request(RB4XX_NAND_GPIO_NCE, "NAND NCE");
++ if (ret) {
++ dev_err(&pdev->dev, "unable to request gpio %d\n",
++ RB4XX_NAND_GPIO_NCE);
++ goto err_free_gpio_cle;
++ }
++
++ ret = gpio_direction_output(RB4XX_NAND_GPIO_NCE, 1);
++ if (ret) {
++ dev_err(&pdev->dev, "unable to set output mode on gpio %d\n",
++ RB4XX_NAND_GPIO_ALE);
++ goto err_free_gpio_nce;
++ }
++
++ info = kzalloc(sizeof(*info), GFP_KERNEL);
++ if (!info) {
++ dev_err(&pdev->dev, "rb4xx-nand: no memory for private data\n");
++ ret = -ENOMEM;
++ goto err_free_gpio_nce;
++ }
++
++ info->chip.priv = &info;
++ info->mtd.priv = &info->chip;
++ info->mtd.owner = THIS_MODULE;
++
++ info->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl;
++ info->chip.dev_ready = rb4xx_nand_dev_ready;
++ info->chip.read_byte = rb4xx_nand_read_byte;
++ info->chip.write_buf = rb4xx_nand_write_buf;
++ info->chip.read_buf = rb4xx_nand_read_buf;
++
++ info->chip.chip_delay = 25;
++ info->chip.ecc.mode = NAND_ECC_SOFT;
++
++ platform_set_drvdata(pdev, info);
++
++ ret = nand_scan_ident(&info->mtd, 1, NULL);
++ if (ret) {
++ ret = -ENXIO;
++ goto err_free_info;
++ }
++
++ if (info->mtd.writesize == 512)
++ info->chip.ecc.layout = &rb4xx_nand_ecclayout;
++
++ ret = nand_scan_tail(&info->mtd);
++ if (ret) {
++ return -ENXIO;
++ goto err_set_drvdata;
++ }
++
++ mtd_device_register(&info->mtd, rb4xx_nand_partitions,
++ ARRAY_SIZE(rb4xx_nand_partitions));
++ if (ret)
++ goto err_release_nand;
++
++ return 0;
++
++err_release_nand:
++ nand_release(&info->mtd);
++err_set_drvdata:
++ platform_set_drvdata(pdev, NULL);
++err_free_info:
++ kfree(info);
++err_free_gpio_nce:
++ gpio_free(RB4XX_NAND_GPIO_NCE);
++err_free_gpio_cle:
++ gpio_free(RB4XX_NAND_GPIO_CLE);
++err_free_gpio_ale:
++ gpio_free(RB4XX_NAND_GPIO_ALE);
++err_free_gpio_ready:
++ gpio_free(RB4XX_NAND_GPIO_READY);
++err:
++ return ret;
++}
++
++static int rb4xx_nand_remove(struct platform_device *pdev)
++{
++ struct rb4xx_nand_info *info = platform_get_drvdata(pdev);
++
++ nand_release(&info->mtd);
++ platform_set_drvdata(pdev, NULL);
++ kfree(info);
++ gpio_free(RB4XX_NAND_GPIO_NCE);
++ gpio_free(RB4XX_NAND_GPIO_CLE);
++ gpio_free(RB4XX_NAND_GPIO_ALE);
++ gpio_free(RB4XX_NAND_GPIO_READY);
++
++ return 0;
++}
++
++static struct platform_driver rb4xx_nand_driver = {
++ .probe = rb4xx_nand_probe,
++ .remove = rb4xx_nand_remove,
++ .driver = {
++ .name = DRV_NAME,
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init rb4xx_nand_init(void)
++{
++ return platform_driver_register(&rb4xx_nand_driver);
++}
++
++static void __exit rb4xx_nand_exit(void)
++{
++ platform_driver_unregister(&rb4xx_nand_driver);
++}
++
++module_init(rb4xx_nand_init);
++module_exit(rb4xx_nand_exit);
++
++MODULE_DESCRIPTION(DRV_DESC);
++MODULE_VERSION(DRV_VERSION);
++MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
++MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
++MODULE_LICENSE("GPL v2");
+--
+1.8.5.3
+
diff --git a/target/mips/mikrotik-rb4xx/patches/4.1.10/0002-phy-add-ethtool-ioctl-support-used-by-ag71xx-driver.patch b/target/mips/mikrotik-rb4xx/patches/4.1.10/0002-phy-add-ethtool-ioctl-support-used-by-ag71xx-driver.patch
new file mode 100644
index 000000000..ba7fbfad8
--- /dev/null
+++ b/target/mips/mikrotik-rb4xx/patches/4.1.10/0002-phy-add-ethtool-ioctl-support-used-by-ag71xx-driver.patch
@@ -0,0 +1,80 @@
+From 7b864612a6e3b139a5a607abd0048a19078fe42f Mon Sep 17 00:00:00 2001
+From: Phil Sutter <phil@nwl.cc>
+Date: Wed, 14 May 2014 02:55:06 +0200
+Subject: [PATCH] phy: add ethtool ioctl support, used by ag71xx driver
+
+---
+ drivers/net/phy/phy.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
+ include/linux/phy.h | 1 +
+ 2 files changed, 45 insertions(+)
+
+diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
+index 76d96b9..9439ef3 100644
+--- a/drivers/net/phy/phy.c
++++ b/drivers/net/phy/phy.c
+@@ -293,6 +293,50 @@ int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd)
+ }
+ EXPORT_SYMBOL(phy_ethtool_gset);
+
++int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr)
++{
++ u32 cmd;
++ int tmp;
++ struct ethtool_cmd ecmd = { ETHTOOL_GSET };
++ struct ethtool_value edata = { ETHTOOL_GLINK };
++
++ if (get_user(cmd, (u32 *) useraddr))
++ return -EFAULT;
++
++ switch (cmd) {
++ case ETHTOOL_GSET:
++ phy_ethtool_gset(phydev, &ecmd);
++ if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
++ return -EFAULT;
++ return 0;
++
++ case ETHTOOL_SSET:
++ if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
++ return -EFAULT;
++ return phy_ethtool_sset(phydev, &ecmd);
++
++ case ETHTOOL_NWAY_RST:
++ /* if autoneg is off, it's an error */
++ tmp = phy_read(phydev, MII_BMCR);
++ if (tmp & BMCR_ANENABLE) {
++ tmp |= (BMCR_ANRESTART);
++ phy_write(phydev, MII_BMCR, tmp);
++ return 0;
++ }
++ return -EINVAL;
++
++ case ETHTOOL_GLINK:
++ edata.data = (phy_read(phydev,
++ MII_BMSR) & BMSR_LSTATUS) ? 1 : 0;
++ if (copy_to_user(useraddr, &edata, sizeof(edata)))
++ return -EFAULT;
++ return 0;
++ }
++
++ return -EOPNOTSUPP;
++}
++EXPORT_SYMBOL(phy_ethtool_ioctl);
++
+ /**
+ * phy_mii_ioctl - generic PHY MII ioctl interface
+ * @phydev: the phy_device struct
+diff --git a/include/linux/phy.h b/include/linux/phy.h
+index 565188c..9ab0d79 100644
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -628,6 +628,7 @@ void phy_stop_machine(struct phy_device *phydev);
+ int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd);
+ int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd);
+ int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd);
++int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr);
+ int phy_start_interrupts(struct phy_device *phydev);
+ void phy_print_status(struct phy_device *phydev);
+ void phy_device_free(struct phy_device *phydev);
+--
+1.8.5.3
+
diff --git a/target/mips/mikrotik-rb4xx/patches/4.1.10/0003-net-add-ag71xx-mac-driver.patch b/target/mips/mikrotik-rb4xx/patches/4.1.10/0003-net-add-ag71xx-mac-driver.patch
new file mode 100644
index 000000000..f8db1f2a4
--- /dev/null
+++ b/target/mips/mikrotik-rb4xx/patches/4.1.10/0003-net-add-ag71xx-mac-driver.patch
@@ -0,0 +1,4185 @@
+diff -Nur linux-4.1.6.orig/arch/mips/include/asm/mach-ath79/ag71xx_platform.h linux-4.1.6/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
+--- linux-4.1.6.orig/arch/mips/include/asm/mach-ath79/ag71xx_platform.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-4.1.6/arch/mips/include/asm/mach-ath79/ag71xx_platform.h 2015-09-13 19:45:36.374555224 +0200
+@@ -0,0 +1,65 @@
++/*
++ * Atheros AR71xx SoC specific platform data definitions
++ *
++ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_ATH79_PLATFORM_H
++#define __ASM_MACH_ATH79_PLATFORM_H
++
++#include <linux/if_ether.h>
++#include <linux/skbuff.h>
++#include <linux/phy.h>
++#include <linux/spi/spi.h>
++
++struct ag71xx_switch_platform_data {
++ u8 phy4_mii_en:1;
++ u8 phy_poll_mask;
++};
++
++struct ag71xx_platform_data {
++ phy_interface_t phy_if_mode;
++ u32 phy_mask;
++ int speed;
++ int duplex;
++ u32 reset_bit;
++ u8 mac_addr[ETH_ALEN];
++ struct device *mii_bus_dev;
++
++ u8 has_gbit:1;
++ u8 is_ar91xx:1;
++ u8 is_ar7240:1;
++ u8 is_ar724x:1;
++ u8 has_ar8216:1;
++
++ struct ag71xx_switch_platform_data *switch_data;
++
++ void (*ddr_flush)(void);
++ void (*set_speed)(int speed);
++
++ u32 fifo_cfg1;
++ u32 fifo_cfg2;
++ u32 fifo_cfg3;
++
++ unsigned int max_frame_len;
++ unsigned int desc_pktlen_mask;
++};
++
++struct ag71xx_mdio_platform_data {
++ u32 phy_mask;
++ u8 builtin_switch:1;
++ u8 is_ar7240:1;
++ u8 is_ar9330:1;
++ u8 is_ar934x:1;
++ unsigned long mdio_clock;
++ unsigned long ref_clock;
++
++ void (*reset)(struct mii_bus *bus);
++};
++
++#endif /* __ASM_MACH_ATH79_PLATFORM_H */
+diff -Nur linux-4.1.6.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c linux-4.1.6/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c
+--- linux-4.1.6.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-4.1.6/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c 2015-09-13 19:45:36.374555224 +0200
+@@ -0,0 +1,1202 @@
++/*
++ * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
++ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ */
++
++#include <linux/etherdevice.h>
++#include <linux/list.h>
++#include <linux/netdevice.h>
++#include <linux/phy.h>
++#include <linux/mii.h>
++#include <linux/bitops.h>
++#include <linux/switch.h>
++#include "ag71xx.h"
++
++#define BITM(_count) (BIT(_count) - 1)
++#define BITS(_shift, _count) (BITM(_count) << _shift)
++
++#define AR7240_REG_MASK_CTRL 0x00
++#define AR7240_MASK_CTRL_REVISION_M BITM(8)
++#define AR7240_MASK_CTRL_VERSION_M BITM(8)
++#define AR7240_MASK_CTRL_VERSION_S 8
++#define AR7240_MASK_CTRL_VERSION_AR7240 0x01
++#define AR7240_MASK_CTRL_VERSION_AR934X 0x02
++#define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
++
++#define AR7240_REG_MAC_ADDR0 0x20
++#define AR7240_REG_MAC_ADDR1 0x24
++
++#define AR7240_REG_FLOOD_MASK 0x2c
++#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
++
++#define AR7240_REG_GLOBAL_CTRL 0x30
++#define AR7240_GLOBAL_CTRL_MTU_M BITM(11)
++#define AR9340_GLOBAL_CTRL_MTU_M BITM(14)
++
++#define AR7240_REG_VTU 0x0040
++#define AR7240_VTU_OP BITM(3)
++#define AR7240_VTU_OP_NOOP 0x0
++#define AR7240_VTU_OP_FLUSH 0x1
++#define AR7240_VTU_OP_LOAD 0x2
++#define AR7240_VTU_OP_PURGE 0x3
++#define AR7240_VTU_OP_REMOVE_PORT 0x4
++#define AR7240_VTU_ACTIVE BIT(3)
++#define AR7240_VTU_FULL BIT(4)
++#define AR7240_VTU_PORT BITS(8, 4)
++#define AR7240_VTU_PORT_S 8
++#define AR7240_VTU_VID BITS(16, 12)
++#define AR7240_VTU_VID_S 16
++#define AR7240_VTU_PRIO BITS(28, 3)
++#define AR7240_VTU_PRIO_S 28
++#define AR7240_VTU_PRIO_EN BIT(31)
++
++#define AR7240_REG_VTU_DATA 0x0044
++#define AR7240_VTUDATA_MEMBER BITS(0, 10)
++#define AR7240_VTUDATA_VALID BIT(11)
++
++#define AR7240_REG_ATU 0x50
++#define AR7240_ATU_FLUSH_ALL 0x1
++
++#define AR7240_REG_AT_CTRL 0x5c
++#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
++#define AR7240_AT_CTRL_AGE_EN BIT(17)
++#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
++#define AR7240_AT_CTRL_RESERVED BIT(19)
++#define AR7240_AT_CTRL_ARP_EN BIT(20)
++
++#define AR7240_REG_TAG_PRIORITY 0x70
++
++#define AR7240_REG_SERVICE_TAG 0x74
++#define AR7240_SERVICE_TAG_M BITM(16)
++
++#define AR7240_REG_CPU_PORT 0x78
++#define AR7240_MIRROR_PORT_S 4
++#define AR7240_CPU_PORT_EN BIT(8)
++
++#define AR7240_REG_MIB_FUNCTION0 0x80
++#define AR7240_MIB_TIMER_M BITM(16)
++#define AR7240_MIB_AT_HALF_EN BIT(16)
++#define AR7240_MIB_BUSY BIT(17)
++#define AR7240_MIB_FUNC_S 24
++#define AR7240_MIB_FUNC_M BITM(3)
++#define AR7240_MIB_FUNC_NO_OP 0x0
++#define AR7240_MIB_FUNC_FLUSH 0x1
++#define AR7240_MIB_FUNC_CAPTURE 0x3
++
++#define AR7240_REG_MDIO_CTRL 0x98
++#define AR7240_MDIO_CTRL_DATA_M BITM(16)
++#define AR7240_MDIO_CTRL_REG_ADDR_S 16
++#define AR7240_MDIO_CTRL_PHY_ADDR_S 21
++#define AR7240_MDIO_CTRL_CMD_WRITE 0
++#define AR7240_MDIO_CTRL_CMD_READ BIT(27)
++#define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
++#define AR7240_MDIO_CTRL_BUSY BIT(31)
++
++#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
++
++#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
++#define AR7240_PORT_STATUS_SPEED_S 0
++#define AR7240_PORT_STATUS_SPEED_M BITM(2)
++#define AR7240_PORT_STATUS_SPEED_10 0
++#define AR7240_PORT_STATUS_SPEED_100 1
++#define AR7240_PORT_STATUS_SPEED_1000 2
++#define AR7240_PORT_STATUS_TXMAC BIT(2)
++#define AR7240_PORT_STATUS_RXMAC BIT(3)
++#define AR7240_PORT_STATUS_TXFLOW BIT(4)
++#define AR7240_PORT_STATUS_RXFLOW BIT(5)
++#define AR7240_PORT_STATUS_DUPLEX BIT(6)
++#define AR7240_PORT_STATUS_LINK_UP BIT(8)
++#define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
++#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
++
++#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
++#define AR7240_PORT_CTRL_STATE_M BITM(3)
++#define AR7240_PORT_CTRL_STATE_DISABLED 0
++#define AR7240_PORT_CTRL_STATE_BLOCK 1
++#define AR7240_PORT_CTRL_STATE_LISTEN 2
++#define AR7240_PORT_CTRL_STATE_LEARN 3
++#define AR7240_PORT_CTRL_STATE_FORWARD 4
++#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
++#define AR7240_PORT_CTRL_VLAN_MODE_S 8
++#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
++#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
++#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
++#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
++#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
++#define AR7240_PORT_CTRL_HEADER BIT(11)
++#define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
++#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
++#define AR7240_PORT_CTRL_LEARN BIT(14)
++#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
++#define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
++#define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
++
++#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
++
++#define AR7240_PORT_VLAN_DEFAULT_ID_S 0
++#define AR7240_PORT_VLAN_DEST_PORTS_S 16
++#define AR7240_PORT_VLAN_MODE_S 30
++#define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
++#define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
++#define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
++#define AR7240_PORT_VLAN_MODE_SECURE 3
++
++
++#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
++
++#define AR7240_STATS_RXBROAD 0x00
++#define AR7240_STATS_RXPAUSE 0x04
++#define AR7240_STATS_RXMULTI 0x08
++#define AR7240_STATS_RXFCSERR 0x0c
++#define AR7240_STATS_RXALIGNERR 0x10
++#define AR7240_STATS_RXRUNT 0x14
++#define AR7240_STATS_RXFRAGMENT 0x18
++#define AR7240_STATS_RX64BYTE 0x1c
++#define AR7240_STATS_RX128BYTE 0x20
++#define AR7240_STATS_RX256BYTE 0x24
++#define AR7240_STATS_RX512BYTE 0x28
++#define AR7240_STATS_RX1024BYTE 0x2c
++#define AR7240_STATS_RX1518BYTE 0x30
++#define AR7240_STATS_RXMAXBYTE 0x34
++#define AR7240_STATS_RXTOOLONG 0x38
++#define AR7240_STATS_RXGOODBYTE 0x3c
++#define AR7240_STATS_RXBADBYTE 0x44
++#define AR7240_STATS_RXOVERFLOW 0x4c
++#define AR7240_STATS_FILTERED 0x50
++#define AR7240_STATS_TXBROAD 0x54
++#define AR7240_STATS_TXPAUSE 0x58
++#define AR7240_STATS_TXMULTI 0x5c
++#define AR7240_STATS_TXUNDERRUN 0x60
++#define AR7240_STATS_TX64BYTE 0x64
++#define AR7240_STATS_TX128BYTE 0x68
++#define AR7240_STATS_TX256BYTE 0x6c
++#define AR7240_STATS_TX512BYTE 0x70
++#define AR7240_STATS_TX1024BYTE 0x74
++#define AR7240_STATS_TX1518BYTE 0x78
++#define AR7240_STATS_TXMAXBYTE 0x7c
++#define AR7240_STATS_TXOVERSIZE 0x80
++#define AR7240_STATS_TXBYTE 0x84
++#define AR7240_STATS_TXCOLLISION 0x8c
++#define AR7240_STATS_TXABORTCOL 0x90
++#define AR7240_STATS_TXMULTICOL 0x94
++#define AR7240_STATS_TXSINGLECOL 0x98
++#define AR7240_STATS_TXEXCDEFER 0x9c
++#define AR7240_STATS_TXDEFER 0xa0
++#define AR7240_STATS_TXLATECOL 0xa4
++
++#define AR7240_PORT_CPU 0
++#define AR7240_NUM_PORTS 6
++#define AR7240_NUM_PHYS 5
++
++#define AR7240_PHY_ID1 0x004d
++#define AR7240_PHY_ID2 0xd041
++
++#define AR934X_PHY_ID1 0x004d
++#define AR934X_PHY_ID2 0xd042
++
++#define AR7240_MAX_VLANS 16
++
++#define AR934X_REG_OPER_MODE0 0x04
++#define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
++#define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
++
++#define AR934X_REG_OPER_MODE1 0x08
++#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
++
++#define AR934X_REG_FLOOD_MASK 0x2c
++#define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
++#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
++
++#define AR934X_REG_QM_CTRL 0x3c
++#define AR934X_QM_CTRL_ARP_EN BIT(15)
++
++#define AR934X_REG_AT_CTRL 0x5c
++#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
++#define AR934X_AT_CTRL_AGE_EN BIT(17)
++#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
++
++#define AR934X_MIB_ENABLE BIT(30)
++
++#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
++
++#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
++#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
++#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
++#define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
++#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
++#define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
++#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
++#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
++#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
++
++#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
++#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
++#define AR934X_PORT_VLAN2_8021Q_MODE_S 30
++#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
++#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
++#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
++#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
++
++#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
++
++struct ar7240sw_port_stat {
++ unsigned long rx_broadcast;
++ unsigned long rx_pause;
++ unsigned long rx_multicast;
++ unsigned long rx_fcs_error;
++ unsigned long rx_align_error;
++ unsigned long rx_runt;
++ unsigned long rx_fragments;
++ unsigned long rx_64byte;
++ unsigned long rx_128byte;
++ unsigned long rx_256byte;
++ unsigned long rx_512byte;
++ unsigned long rx_1024byte;
++ unsigned long rx_1518byte;
++ unsigned long rx_maxbyte;
++ unsigned long rx_toolong;
++ unsigned long rx_good_byte;
++ unsigned long rx_bad_byte;
++ unsigned long rx_overflow;
++ unsigned long filtered;
++
++ unsigned long tx_broadcast;
++ unsigned long tx_pause;
++ unsigned long tx_multicast;
++ unsigned long tx_underrun;
++ unsigned long tx_64byte;
++ unsigned long tx_128byte;
++ unsigned long tx_256byte;
++ unsigned long tx_512byte;
++ unsigned long tx_1024byte;
++ unsigned long tx_1518byte;
++ unsigned long tx_maxbyte;
++ unsigned long tx_oversize;
++ unsigned long tx_byte;
++ unsigned long tx_collision;
++ unsigned long tx_abortcol;
++ unsigned long tx_multicol;
++ unsigned long tx_singlecol;
++ unsigned long tx_excdefer;
++ unsigned long tx_defer;
++ unsigned long tx_xlatecol;
++};
++
++struct ar7240sw {
++ struct mii_bus *mii_bus;
++ struct ag71xx_switch_platform_data *swdata;
++ struct switch_dev swdev;
++ int num_ports;
++ u8 ver;
++ bool vlan;
++ u16 vlan_id[AR7240_MAX_VLANS];
++ u8 vlan_table[AR7240_MAX_VLANS];
++ u8 vlan_tagged;
++ u16 pvid[AR7240_NUM_PORTS];
++ char buf[80];
++
++ rwlock_t stats_lock;
++ struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
++};
++
++struct ar7240sw_hw_stat {
++ char string[ETH_GSTRING_LEN];
++ int sizeof_stat;
++ int reg;
++};
++
++static DEFINE_MUTEX(reg_mutex);
++
++static inline int sw_is_ar7240(struct ar7240sw *as)
++{
++ return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
++}
++
++static inline int sw_is_ar934x(struct ar7240sw *as)
++{
++ return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
++}
++
++static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
++{
++ return BIT(port);
++}
++
++static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
++{
++ return BIT(as->swdev.ports) - 1;
++}
++
++static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
++{
++ return ar7240sw_port_mask_all(as) & ~BIT(port);
++}
++
++static inline u16 mk_phy_addr(u32 reg)
++{
++ return 0x17 & ((reg >> 4) | 0x10);
++}
++
++static inline u16 mk_phy_reg(u32 reg)
++{
++ return (reg << 1) & 0x1e;
++}
++
++static inline u16 mk_high_addr(u32 reg)
++{
++ return (reg >> 7) & 0x1ff;
++}
++
++static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
++{
++ unsigned long flags;
++ u16 phy_addr;
++ u16 phy_reg;
++ u32 hi, lo;
++
++ reg = (reg & 0xfffffffc) >> 2;
++ phy_addr = mk_phy_addr(reg);
++ phy_reg = mk_phy_reg(reg);
++
++ local_irq_save(flags);
++ ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
++ lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
++ hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
++ local_irq_restore(flags);
++
++ return (hi << 16) | lo;
++}
++
++static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
++{
++ unsigned long flags;
++ u16 phy_addr;
++ u16 phy_reg;
++
++ reg = (reg & 0xfffffffc) >> 2;
++ phy_addr = mk_phy_addr(reg);
++ phy_reg = mk_phy_reg(reg);
++
++ local_irq_save(flags);
++ ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
++ ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
++ ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
++ local_irq_restore(flags);
++}
++
++static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
++{
++ u32 ret;
++
++ mutex_lock(®_mutex);
++ ret = __ar7240sw_reg_read(mii, reg_addr);
++ mutex_unlock(®_mutex);
++
++ return ret;
++}
++
++static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
++{
++ mutex_lock(®_mutex);
++ __ar7240sw_reg_write(mii, reg_addr, reg_val);
++ mutex_unlock(®_mutex);
++}
++
++static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
++{
++ u32 t;
++
++ mutex_lock(®_mutex);
++ t = __ar7240sw_reg_read(mii, reg);
++ t &= ~mask;
++ t |= val;
++ __ar7240sw_reg_write(mii, reg, t);
++ mutex_unlock(®_mutex);
++
++ return t;
++}
++
++static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
++{
++ u32 t;
++
++ mutex_lock(®_mutex);
++ t = __ar7240sw_reg_read(mii, reg);
++ t |= val;
++ __ar7240sw_reg_write(mii, reg, t);
++ mutex_unlock(®_mutex);
++}
++
++static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
++ unsigned timeout)
++{
++ int i;
++
++ for (i = 0; i < timeout; i++) {
++ u32 t;
++
++ t = __ar7240sw_reg_read(mii, reg);
++ if ((t & mask) == val)
++ return 0;
++
++ msleep(1);
++ }
++
++ return -ETIMEDOUT;
++}
++
++static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
++ unsigned timeout)
++{
++ int ret;
++
++ mutex_lock(®_mutex);
++ ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
++ mutex_unlock(®_mutex);
++ return ret;
++}
++
++u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
++ unsigned reg_addr)
++{
++ u32 t, val = 0xffff;
++ int err;
++
++ if (phy_addr >= AR7240_NUM_PHYS)
++ return 0xffff;
++
++ mutex_lock(®_mutex);
++ t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
++ (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
++ AR7240_MDIO_CTRL_MASTER_EN |
++ AR7240_MDIO_CTRL_BUSY |
++ AR7240_MDIO_CTRL_CMD_READ;
++
++ __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
++ err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
++ AR7240_MDIO_CTRL_BUSY, 0, 5);
++ if (!err)
++ val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
++ mutex_unlock(®_mutex);
++
++ return val & AR7240_MDIO_CTRL_DATA_M;
++}
++
++int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
++ unsigned reg_addr, u16 reg_val)
++{
++ u32 t;
++ int ret;
++
++ if (phy_addr >= AR7240_NUM_PHYS)
++ return -EINVAL;
++
++ mutex_lock(®_mutex);
++ t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
++ (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
++ AR7240_MDIO_CTRL_MASTER_EN |
++ AR7240_MDIO_CTRL_BUSY |
++ AR7240_MDIO_CTRL_CMD_WRITE |
++ reg_val;
++
++ __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
++ ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
++ AR7240_MDIO_CTRL_BUSY, 0, 5);
++ mutex_unlock(®_mutex);
++
++ return ret;
++}
++
++static int ar7240sw_capture_stats(struct ar7240sw *as)
++{
++ struct mii_bus *mii = as->mii_bus;
++ int port;
++ int ret;
++
++ write_lock(&as->stats_lock);
++
++ /* Capture the hardware statistics for all ports */
++ ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0,
++ (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S),
++ (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
++
++ /* Wait for the capturing to complete. */
++ ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
++ AR7240_MIB_BUSY, 0, 10);
++
++ if (ret)
++ goto unlock;
++
++ for (port = 0; port < AR7240_NUM_PORTS; port++) {
++ unsigned int base;
++ struct ar7240sw_port_stat *stats;
++
++ base = AR7240_REG_STATS_BASE(port);
++ stats = &as->port_stats[port];
++
++#define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
++
++ stats->rx_good_byte += READ_STAT(RXGOODBYTE);
++ stats->tx_byte += READ_STAT(TXBYTE);
++
++#undef READ_STAT
++ }
++
++ ret = 0;
++
++unlock:
++ write_unlock(&as->stats_lock);
++ return ret;
++}
++
++static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
++{
++ ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
++ AR7240_PORT_CTRL_STATE_DISABLED);
++}
++
++static void ar7240sw_setup(struct ar7240sw *as)
++{
++ struct mii_bus *mii = as->mii_bus;
++
++ /* Enable CPU port, and disable mirror port */
++ ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
++ AR7240_CPU_PORT_EN |
++ (15 << AR7240_MIRROR_PORT_S));
++
++ /* Setup TAG priority mapping */
++ ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
++
++ if (sw_is_ar934x(as)) {
++ /* Enable aging, MAC replacing */
++ ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
++ 0x2b /* 5 min age time */ |
++ AR934X_AT_CTRL_AGE_EN |
++ AR934X_AT_CTRL_LEARN_CHANGE);
++ /* Enable ARP frame acknowledge */
++ ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
++ AR934X_QM_CTRL_ARP_EN);
++ /* Enable Broadcast/Multicast frames transmitted to the CPU */
++ ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
++ AR934X_FLOOD_MASK_BC_DP(0) |
++ AR934X_FLOOD_MASK_MC_DP(0));
++
++ /* setup MTU */
++ ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
++ AR9340_GLOBAL_CTRL_MTU_M,
++ AR9340_GLOBAL_CTRL_MTU_M);
++
++ /* Enable MIB counters */
++ ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
++ AR934X_MIB_ENABLE);
++
++ } else {
++ /* Enable ARP frame acknowledge, aging, MAC replacing */
++ ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
++ AR7240_AT_CTRL_RESERVED |
++ 0x2b /* 5 min age time */ |
++ AR7240_AT_CTRL_AGE_EN |
++ AR7240_AT_CTRL_ARP_EN |
++ AR7240_AT_CTRL_LEARN_CHANGE);
++ /* Enable Broadcast frames transmitted to the CPU */
++ ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
++ AR7240_FLOOD_MASK_BROAD_TO_CPU);
++
++ /* setup MTU */
++ ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
++ AR7240_GLOBAL_CTRL_MTU_M,
++ AR7240_GLOBAL_CTRL_MTU_M);
++ }
++
++ /* setup Service TAG */
++ ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
++}
++
++static int ar7240sw_reset(struct ar7240sw *as)
++{
++ struct mii_bus *mii = as->mii_bus;
++ int ret;
++ int i;
++
++ /* Set all ports to disabled state. */
++ for (i = 0; i < AR7240_NUM_PORTS; i++)
++ ar7240sw_disable_port(as, i);
++
++ /* Wait for transmit queues to drain. */
++ msleep(2);
++
++ /* Reset the switch. */
++ ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
++ AR7240_MASK_CTRL_SOFT_RESET);
++
++ ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
++ AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
++
++ /* setup PHYs */
++ for (i = 0; i < AR7240_NUM_PHYS; i++) {
++ ar7240sw_phy_write(mii, i, MII_ADVERTISE,
++ ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
++ ADVERTISE_PAUSE_ASYM);
++ ar7240sw_phy_write(mii, i, MII_BMCR,
++ BMCR_RESET | BMCR_ANENABLE);
++ }
++ msleep(1000);
++
++ ar7240sw_setup(as);
++ return ret;
++}
++
++static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
++{
++ struct mii_bus *mii = as->mii_bus;
++ u32 ctrl;
++ u32 vid, mode;
++
++ ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
++ AR7240_PORT_CTRL_SINGLE_VLAN;
++
++ if (port == AR7240_PORT_CPU) {
++ ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
++ AR7240_PORT_STATUS_SPEED_1000 |
++ AR7240_PORT_STATUS_TXFLOW |
++ AR7240_PORT_STATUS_RXFLOW |
++ AR7240_PORT_STATUS_TXMAC |
++ AR7240_PORT_STATUS_RXMAC |
++ AR7240_PORT_STATUS_DUPLEX);
++ } else {
++ ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
++ AR7240_PORT_STATUS_LINK_AUTO);
++ }
++
++ /* Set the default VID for this port */
++ if (as->vlan) {
++ vid = as->vlan_id[as->pvid[port]];
++ mode = AR7240_PORT_VLAN_MODE_SECURE;
++ } else {
++ vid = port;
++ mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
++ }
++
++ if (as->vlan) {
++ if (as->vlan_tagged & BIT(port))
++ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
++ AR7240_PORT_CTRL_VLAN_MODE_S;
++ else
++ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
++ AR7240_PORT_CTRL_VLAN_MODE_S;
++ } else {
++ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP <<
++ AR7240_PORT_CTRL_VLAN_MODE_S;
++ }
++
++ if (!portmask) {
++ if (port == AR7240_PORT_CPU)
++ portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
++ else
++ portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
++ }
++
++ /* allow the port to talk to all other ports, but exclude its
++ * own ID to prevent frames from being reflected back to the
++ * port that they came from */
++ portmask &= ar7240sw_port_mask_but(as, port);
++
++ ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
++ if (sw_is_ar934x(as)) {
++ u32 vlan1, vlan2;
++
++ vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
++ vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
++ (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
++ ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
++ ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
++ } else {
++ u32 vlan;
++
++ vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
++ (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
++
++ ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
++ }
++}
++
++static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
++{
++ struct mii_bus *mii = as->mii_bus;
++ u32 t;
++
++ t = (addr[4] << 8) | addr[5];
++ ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
++
++ t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
++ ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
++
++ return 0;
++}
++
++static int
++ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
++ struct switch_val *val)
++{
++ struct ar7240sw *as = sw_to_ar7240(dev);
++ as->vlan_id[val->port_vlan] = val->value.i;
++ return 0;
++}
++
++static int
++ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
++ struct switch_val *val)
++{
++ struct ar7240sw *as = sw_to_ar7240(dev);
++ val->value.i = as->vlan_id[val->port_vlan];
++ return 0;
++}
++
++static int
++ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
++{
++ struct ar7240sw *as = sw_to_ar7240(dev);
++
++ /* make sure no invalid PVIDs get set */
++
++ if (vlan >= dev->vlans)
++ return -EINVAL;
++
++ as->pvid[port] = vlan;
++ return 0;
++}
++
++static int
++ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
++{
++ struct ar7240sw *as = sw_to_ar7240(dev);
++ *vlan = as->pvid[port];
++ return 0;
++}
++
++static int
++ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
++{
++ struct ar7240sw *as = sw_to_ar7240(dev);
++ u8 ports = as->vlan_table[val->port_vlan];
++ int i;
++
++ val->len = 0;
++ for (i = 0; i < as->swdev.ports; i++) {
++ struct switch_port *p;
++
++ if (!(ports & (1 << i)))
++ continue;
++
++ p = &val->value.ports[val->len++];
++ p->id = i;
++ if (as->vlan_tagged & (1 << i))
++ p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
++ else
++ p->flags = 0;
++ }
++ return 0;
++}
++
++static int
++ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
++{
++ struct ar7240sw *as = sw_to_ar7240(dev);
++ u8 *vt = &as->vlan_table[val->port_vlan];
++ int i, j;
++
++ *vt = 0;
++ for (i = 0; i < val->len; i++) {
++ struct switch_port *p = &val->value.ports[i];
++
++ if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
++ as->vlan_tagged |= (1 << p->id);
++ else {
++ as->vlan_tagged &= ~(1 << p->id);
++ as->pvid[p->id] = val->port_vlan;
++
++ /* make sure that an untagged port does not
++ * appear in other vlans */
++ for (j = 0; j < AR7240_MAX_VLANS; j++) {
++ if (j == val->port_vlan)
++ continue;
++ as->vlan_table[j] &= ~(1 << p->id);
++ }
++ }
++
++ *vt |= 1 << p->id;
++ }
++ return 0;
++}
++
++static int
++ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
++ struct switch_val *val)
++{
++ struct ar7240sw *as = sw_to_ar7240(dev);
++ as->vlan = !!val->value.i;
++ return 0;
++}
++
++static int
++ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
++ struct switch_val *val)
++{
++ struct ar7240sw *as = sw_to_ar7240(dev);
++ val->value.i = as->vlan;
++ return 0;
++}
++
++static void
++ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
++{
++ struct mii_bus *mii = as->mii_bus;
++
++ if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
++ return;
++
++ if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
++ val &= AR7240_VTUDATA_MEMBER;
++ val |= AR7240_VTUDATA_VALID;
++ ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
++ }
++ op |= AR7240_VTU_ACTIVE;
++ ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
++}
++
++static int
++ar7240_hw_apply(struct switch_dev *dev)
++{
++ struct ar7240sw *as = sw_to_ar7240(dev);
++ u8 portmask[AR7240_NUM_PORTS];
++ int i, j;
++
++ /* flush all vlan translation unit entries */
++ ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
++
++ memset(portmask, 0, sizeof(portmask));
++ if (as->vlan) {
++ /* calculate the port destination masks and load vlans
++ * into the vlan translation unit */
++ for (j = 0; j < AR7240_MAX_VLANS; j++) {
++ u8 vp = as->vlan_table[j];
++
++ if (!vp)
++ continue;
++
++ for (i = 0; i < as->swdev.ports; i++) {
++ u8 mask = (1 << i);
++ if (vp & mask)
++ portmask[i] |= vp & ~mask;
++ }
++
++ ar7240_vtu_op(as,
++ AR7240_VTU_OP_LOAD |
++ (as->vlan_id[j] << AR7240_VTU_VID_S),
++ as->vlan_table[j]);
++ }
++ } else {
++ /* vlan disabled:
++ * isolate all ports, but connect them to the cpu port */
++ for (i = 0; i < as->swdev.ports; i++) {
++ if (i == AR7240_PORT_CPU)
++ continue;
++
++ portmask[i] = 1 << AR7240_PORT_CPU;
++ portmask[AR7240_PORT_CPU] |= (1 << i);
++ }
++ }
++
++ /* update the port destination mask registers and tag settings */
++ for (i = 0; i < as->swdev.ports; i++)
++ ar7240sw_setup_port(as, i, portmask[i]);
++
++ return 0;
++}
++
++static int
++ar7240_reset_switch(struct switch_dev *dev)
++{
++ struct ar7240sw *as = sw_to_ar7240(dev);
++ ar7240sw_reset(as);
++ return 0;
++}
++
++static int
++ar7240_get_port_link(struct switch_dev *dev, int port,
++ struct switch_port_link *link)
++{
++ struct ar7240sw *as = sw_to_ar7240(dev);
++ struct mii_bus *mii = as->mii_bus;
++ u32 status;
++
++ if (port > AR7240_NUM_PORTS)
++ return -EINVAL;
++
++ status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
++ link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO);
++ if (link->aneg) {
++ link->link = !!(status & AR7240_PORT_STATUS_LINK_UP);
++ if (!link->link)
++ return 0;
++ } else {
++ link->link = true;
++ }
++
++ link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX);
++ link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW);
++ link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW);
++ switch (status & AR7240_PORT_STATUS_SPEED_M) {
++ case AR7240_PORT_STATUS_SPEED_10:
++ link->speed = SWITCH_PORT_SPEED_10;
++ break;
++ case AR7240_PORT_STATUS_SPEED_100:
++ link->speed = SWITCH_PORT_SPEED_100;
++ break;
++ case AR7240_PORT_STATUS_SPEED_1000:
++ link->speed = SWITCH_PORT_SPEED_1000;
++ break;
++ }
++
++ return 0;
++}
++
++static int
++ar7240_get_port_stats(struct switch_dev *dev, int port,
++ struct switch_port_stats *stats)
++{
++ struct ar7240sw *as = sw_to_ar7240(dev);
++
++ if (port > AR7240_NUM_PORTS)
++ return -EINVAL;
++
++ ar7240sw_capture_stats(as);
++
++ read_lock(&as->stats_lock);
++ stats->rx_bytes = as->port_stats[port].rx_good_byte;
++ stats->tx_bytes = as->port_stats[port].tx_byte;
++ read_unlock(&as->stats_lock);
++
++ return 0;
++}
++
++static struct switch_attr ar7240_globals[] = {
++ {
++ .type = SWITCH_TYPE_INT,
++ .name = "enable_vlan",
++ .description = "Enable VLAN mode",
++ .set = ar7240_set_vlan,
++ .get = ar7240_get_vlan,
++ .max = 1
++ },
++};
++
++static struct switch_attr ar7240_port[] = {
++};
++
++static struct switch_attr ar7240_vlan[] = {
++ {
++ .type = SWITCH_TYPE_INT,
++ .name = "vid",
++ .description = "VLAN ID",
++ .set = ar7240_set_vid,
++ .get = ar7240_get_vid,
++ .max = 4094,
++ },
++};
++
++static const struct switch_dev_ops ar7240_ops = {
++ .attr_global = {
++ .attr = ar7240_globals,
++ .n_attr = ARRAY_SIZE(ar7240_globals),
++ },
++ .attr_port = {
++ .attr = ar7240_port,
++ .n_attr = ARRAY_SIZE(ar7240_port),
++ },
++ .attr_vlan = {
++ .attr = ar7240_vlan,
++ .n_attr = ARRAY_SIZE(ar7240_vlan),
++ },
++ .get_port_pvid = ar7240_get_pvid,
++ .set_port_pvid = ar7240_set_pvid,
++ .get_vlan_ports = ar7240_get_ports,
++ .set_vlan_ports = ar7240_set_ports,
++ .apply_config = ar7240_hw_apply,
++ .reset_switch = ar7240_reset_switch,
++ .get_port_link = ar7240_get_port_link,
++ .get_port_stats = ar7240_get_port_stats,
++};
++
++static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
++{
++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
++ struct mii_bus *mii = ag->mii_bus;
++ struct ar7240sw *as;
++ struct switch_dev *swdev;
++ u32 ctrl;
++ u16 phy_id1;
++ u16 phy_id2;
++ int i;
++
++ phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
++ phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
++ if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
++ (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
++ pr_err("%s: unknown phy id '%04x:%04x'\n",
++ dev_name(&mii->dev), phy_id1, phy_id2);
++ return NULL;
++ }
++
++ as = kzalloc(sizeof(*as), GFP_KERNEL);
++ if (!as)
++ return NULL;
++
++ as->mii_bus = mii;
++ as->swdata = pdata->switch_data;
++
++ swdev = &as->swdev;
++
++ ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
++ as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
++ AR7240_MASK_CTRL_VERSION_M;
++
++ if (sw_is_ar7240(as)) {
++ swdev->name = "AR7240/AR9330 built-in switch";
++ swdev->ports = AR7240_NUM_PORTS - 1;
++ } else if (sw_is_ar934x(as)) {
++ swdev->name = "AR934X built-in switch";
++
++ if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
++ ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
++ AR934X_OPER_MODE0_MAC_GMII_EN);
++ } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
++ ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
++ AR934X_OPER_MODE0_PHY_MII_EN);
++ } else {
++ pr_err("%s: invalid PHY interface mode\n",
++ dev_name(&mii->dev));
++ goto err_free;
++ }
++
++ if (as->swdata->phy4_mii_en) {
++ ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
++ AR934X_REG_OPER_MODE1_PHY4_MII_EN);
++ swdev->ports = AR7240_NUM_PORTS - 1;
++ } else {
++ swdev->ports = AR7240_NUM_PORTS;
++ }
++ } else {
++ pr_err("%s: unsupported chip, ctrl=%08x\n",
++ dev_name(&mii->dev), ctrl);
++ goto err_free;
++ }
++
++ swdev->cpu_port = AR7240_PORT_CPU;
++ swdev->vlans = AR7240_MAX_VLANS;
++ swdev->ops = &ar7240_ops;
++
++ if (register_switch(&as->swdev, ag->dev) < 0)
++ goto err_free;
++
++ pr_info("%s: Found an %s\n", dev_name(&mii->dev), swdev->name);
++
++ /* initialize defaults */
++ for (i = 0; i < AR7240_MAX_VLANS; i++)
++ as->vlan_id[i] = i;
++
++ as->vlan_table[0] = ar7240sw_port_mask_all(as);
++
++ return as;
++
++err_free:
++ kfree(as);
++ return NULL;
++}
++
++static void link_function(struct work_struct *work) {
++ struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
++ struct ar7240sw *as = ag->phy_priv;
++ unsigned long flags;
++ u8 mask;
++ int i;
++ int status = 0;
++
++ mask = ~as->swdata->phy_poll_mask;
++ for (i = 0; i < AR7240_NUM_PHYS; i++) {
++ int link;
++
++ if (!(mask & BIT(i)))
++ continue;
++
++ link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
++ if (link & BMSR_LSTATUS) {
++ status = 1;
++ break;
++ }
++ }
++
++ spin_lock_irqsave(&ag->lock, flags);
++ if (status != ag->link) {
++ ag->link = status;
++ ag71xx_link_adjust(ag);
++ }
++ spin_unlock_irqrestore(&ag->lock, flags);
++
++ schedule_delayed_work(&ag->link_work, HZ / 2);
++}
++
++void ag71xx_ar7240_start(struct ag71xx *ag)
++{
++ struct ar7240sw *as = ag->phy_priv;
++
++ ar7240sw_reset(as);
++
++ ag->speed = SPEED_1000;
++ ag->duplex = 1;
++
++ ar7240_set_addr(as, ag->dev->dev_addr);
++ ar7240_hw_apply(&as->swdev);
++
++ schedule_delayed_work(&ag->link_work, HZ / 10);
++}
++
++void ag71xx_ar7240_stop(struct ag71xx *ag)
++{
++ cancel_delayed_work_sync(&ag->link_work);
++}
++
++int ag71xx_ar7240_init(struct ag71xx *ag)
++{
++ struct ar7240sw *as;
++
++ as = ar7240_probe(ag);
++ if (!as)
++ return -ENODEV;
++
++ ag->phy_priv = as;
++ ar7240sw_reset(as);
++
++ rwlock_init(&as->stats_lock);
++ INIT_DELAYED_WORK(&ag->link_work, link_function);
++
++ return 0;
++}
++
++void ag71xx_ar7240_cleanup(struct ag71xx *ag)
++{
++ struct ar7240sw *as = ag->phy_priv;
++
++ if (!as)
++ return;
++
++ unregister_switch(&as->swdev);
++ kfree(as);
++ ag->phy_priv = NULL;
++}
+diff -Nur linux-4.1.6.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c linux-4.1.6/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c
+--- linux-4.1.6.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-4.1.6/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c 2015-09-13 19:45:36.374555224 +0200
+@@ -0,0 +1,44 @@
++/*
++ * Atheros AR71xx built-in ethernet mac driver
++ * Special support for the Atheros ar8216 switch chip
++ *
++ * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * Based on Atheros' AG7100 driver
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include "ag71xx.h"
++
++#define AR8216_PACKET_TYPE_MASK 0xf
++#define AR8216_PACKET_TYPE_NORMAL 0
++
++#define AR8216_HEADER_LEN 2
++
++void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb)
++{
++ skb_push(skb, AR8216_HEADER_LEN);
++ skb->data[0] = 0x10;
++ skb->data[1] = 0x80;
++}
++
++int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
++ int pktlen)
++{
++ u8 type;
++
++ type = skb->data[1] & AR8216_PACKET_TYPE_MASK;
++ switch (type) {
++ case AR8216_PACKET_TYPE_NORMAL:
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ skb_pull(skb, AR8216_HEADER_LEN);
++ return 0;
++}
+diff -Nur linux-4.1.6.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c linux-4.1.6/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c
+--- linux-4.1.6.orig/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-4.1.6/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c 2015-09-13 19:45:36.374555224 +0200
+@@ -0,0 +1,284 @@
++/*
++ * Atheros AR71xx built-in ethernet mac driver
++ *
++ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * Based on Atheros' AG7100 driver
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/debugfs.h>
++
++#include "ag71xx.h"
++
++static struct dentry *ag71xx_debugfs_root;
++
++static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file)
++{
++ file->private_data = inode->i_private;
++ return 0;
++}
++
++void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status)
++{
++ if (status)
++ ag->debug.int_stats.total++;
++ if (status & AG71XX_INT_TX_PS)
++ ag->debug.int_stats.tx_ps++;
++ if (status & AG71XX_INT_TX_UR)
++ ag->debug.int_stats.tx_ur++;
++ if (status & AG71XX_INT_TX_BE)
++ ag->debug.int_stats.tx_be++;
++ if (status & AG71XX_INT_RX_PR)
++ ag->debug.int_stats.rx_pr++;
++ if (status & AG71XX_INT_RX_OF)
++ ag->debug.int_stats.rx_of++;
++ if (status & AG71XX_INT_RX_BE)
++ ag->debug.int_stats.rx_be++;
++}
++
++static ssize_t read_file_int_stats(struct file *file, char __user *user_buf,
++ size_t count, loff_t *ppos)
++{
++#define PR_INT_STAT(_label, _field) \
++ len += snprintf(buf + len, sizeof(buf) - len, \
++ "%20s: %10lu\n", _label, ag->debug.int_stats._field);
++
++ struct ag71xx *ag = file->private_data;
++ char buf[256];
++ unsigned int len = 0;
++
++ PR_INT_STAT("TX Packet Sent", tx_ps);
++ PR_INT_STAT("TX Underrun", tx_ur);
++ PR_INT_STAT("TX Bus Error", tx_be);
++ PR_INT_STAT("RX Packet Received", rx_pr);
++ PR_INT_STAT("RX Overflow", rx_of);
++ PR_INT_STAT("RX Bus Error", rx_be);
++ len += snprintf(buf + len, sizeof(buf) - len, "\n");
++ PR_INT_STAT("Total", total);
++
++ return simple_read_from_buffer(user_buf, count, ppos, buf, len);
++#undef PR_INT_STAT
++}
++
++static const struct file_operations ag71xx_fops_int_stats = {
++ .open = ag71xx_debugfs_generic_open,
++ .read = read_file_int_stats,
++ .owner = THIS_MODULE
++};
++
++void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx)
++{
++ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats;
++
++ if (rx) {
++ stats->rx_count++;
++ stats->rx_packets += rx;
++ if (rx <= AG71XX_NAPI_WEIGHT)
++ stats->rx[rx]++;
++ if (rx > stats->rx_packets_max)
++ stats->rx_packets_max = rx;
++ }
++
++ if (tx) {
++ stats->tx_count++;
++ stats->tx_packets += tx;
++ if (tx <= AG71XX_NAPI_WEIGHT)
++ stats->tx[tx]++;
++ if (tx > stats->tx_packets_max)
++ stats->tx_packets_max = tx;
++ }
++}
++
++static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf,
++ size_t count, loff_t *ppos)
++{
++ struct ag71xx *ag = file->private_data;
++ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats;
++ char *buf;
++ unsigned int buflen;
++ unsigned int len = 0;
++ unsigned long rx_avg = 0;
++ unsigned long tx_avg = 0;
++ int ret;
++ int i;
++
++ buflen = 2048;
++ buf = kmalloc(buflen, GFP_KERNEL);
++ if (!buf)
++ return -ENOMEM;
++
++ if (stats->rx_count)
++ rx_avg = stats->rx_packets / stats->rx_count;
++
++ if (stats->tx_count)
++ tx_avg = stats->tx_packets / stats->tx_count;
++
++ len += snprintf(buf + len, buflen - len, "%3s %10s %10s\n",
++ "len", "rx", "tx");
++
++ for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++)
++ len += snprintf(buf + len, buflen - len,
++ "%3d: %10lu %10lu\n",
++ i, stats->rx[i], stats->tx[i]);
++
++ len += snprintf(buf + len, buflen - len, "\n");
++
++ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
++ "sum", stats->rx_count, stats->tx_count);
++ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
++ "avg", rx_avg, tx_avg);
++ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
++ "max", stats->rx_packets_max, stats->tx_packets_max);
++ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
++ "pkt", stats->rx_packets, stats->tx_packets);
++
++ ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
++ kfree(buf);
++
++ return ret;
++}
++
++static const struct file_operations ag71xx_fops_napi_stats = {
++ .open = ag71xx_debugfs_generic_open,
++ .read = read_file_napi_stats,
++ .owner = THIS_MODULE
++};
++
++#define DESC_PRINT_LEN 64
++
++static ssize_t read_file_ring(struct file *file, char __user *user_buf,
++ size_t count, loff_t *ppos,
++ struct ag71xx *ag,
++ struct ag71xx_ring *ring,
++ unsigned desc_reg)
++{
++ char *buf;
++ unsigned int buflen;
++ unsigned int len = 0;
++ unsigned long flags;
++ ssize_t ret;
++ int curr;
++ int dirty;
++ u32 desc_hw;
++ int i;
++
++ buflen = (ring->size * DESC_PRINT_LEN);
++ buf = kmalloc(buflen, GFP_KERNEL);
++ if (!buf)
++ return -ENOMEM;
++
++ len += snprintf(buf + len, buflen - len,
++ "Idx ... %-8s %-8s %-8s %-8s . %-10s\n",
++ "desc", "next", "data", "ctrl", "timestamp");
++
++ spin_lock_irqsave(&ag->lock, flags);
++
++ curr = (ring->curr % ring->size);
++ dirty = (ring->dirty % ring->size);
++ desc_hw = ag71xx_rr(ag, desc_reg);
++ for (i = 0; i < ring->size; i++) {
++ struct ag71xx_buf *ab = &ring->buf[i];
++ u32 desc_dma = ((u32) ring->descs_dma) + i * ring->desc_size;
++
++ len += snprintf(buf + len, buflen - len,
++ "%3d %c%c%c %08x %08x %08x %08x %c %10lu\n",
++ i,
++ (i == curr) ? 'C' : ' ',
++ (i == dirty) ? 'D' : ' ',
++ (desc_hw == desc_dma) ? 'H' : ' ',
++ desc_dma,
++ ab->desc->next,
++ ab->desc->data,
++ ab->desc->ctrl,
++ (ab->desc->ctrl & DESC_EMPTY) ? 'E' : '*',
++ ab->timestamp);
++ }
++
++ spin_unlock_irqrestore(&ag->lock, flags);
++
++ ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
++ kfree(buf);
++
++ return ret;
++}
++
++static ssize_t read_file_tx_ring(struct file *file, char __user *user_buf,
++ size_t count, loff_t *ppos)
++{
++ struct ag71xx *ag = file->private_data;
++
++ return read_file_ring(file, user_buf, count, ppos, ag, &ag->tx_ring,
++