From 1e60e4f0aa8e9dc5f03d58c8651d98742fdc36b7 Mon Sep 17 00:00:00 2001
From: Waldemar Brodkorb <wbx@openadk.org>
Date: Mon, 8 Dec 2014 13:00:14 -0600
Subject: bump kernel to 3.14.26
---
.../3.14.22/0001-mtd-add-rb4xx-nand-driver.patch | 351 --
...htool-ioctl-support-used-by-ag71xx-driver.patch | 80 -
.../3.14.22/0003-net-add-ag71xx-mac-driver.patch | 4245 --------------------
...ivers-link-SPI-drivers-before-MTD-drivers.patch | 27 -
...ious-flags-to-spi_transfer-and-spi_messag.patch | 34 -
.../3.14.22/0006-spi-add-rb4xx-SPI-driver.patch | 557 ---
.../3.14.22/0007-spi-add-rb4xx-cpld-driver.patch | 548 ---
.../3.14.22/0008-gpio-add-GPIO-latch-driver.patch | 290 --
...0009-spi-export-spi_bitbang_bufs-function.patch | 45 -
...spi-add-type-field-to-spi_transfer-struct.patch | 37 -
.../0011-mtd-m25p80-set-SPI-transfer-type.patch | 29 -
...mips-ath79-swizzle-PCI-address-for-ar71xx.patch | 130 -
.../3.14.22/0013-net-add-swconfig-support.patch | 1859 ---------
...-add-detach-callback-to-struct-phy_driver.patch | 46 -
.../3.14.22/0015-phy-add-ar8216-PHY-support.patch | 3671 -----------------
.../0016-phy-mdio-bitbang-ignore-TA-value.patch | 44 -
.../0017-MIPS-ath79-fix-maximum-timeout.patch | 37 -
...PHY-drivers-to-insert-packet-mangle-hooks.patch | 211 -
...9-MIPS-ath79-process-board-cmdline-option.patch | 26 -
...020-spi-ath79-add-fast-flash-read-support.patch | 202 -
.../3.14.22/0021-phy-add-mdio-boardinfo.patch | 227 --
...0022-mips-ath79-add-ath79-ethernet-driver.patch | 1429 -------
...S-ath79-add-Mikrotik-rb4xx-device-support.patch | 536 ---
.../3.14.22/0024-various-fixups-for-Werror.patch | 105 -
.../0025-rb4xx_nand-add-partition-for-cfgfs.patch | 28 -
...us-fixups-for-ath5k-fixing-system-freezes.patch | 108 -
.../3.14.26/0001-mtd-add-rb4xx-nand-driver.patch | 351 ++
...htool-ioctl-support-used-by-ag71xx-driver.patch | 80 +
.../3.14.26/0003-net-add-ag71xx-mac-driver.patch | 4245 ++++++++++++++++++++
...ivers-link-SPI-drivers-before-MTD-drivers.patch | 27 +
...ious-flags-to-spi_transfer-and-spi_messag.patch | 34 +
.../3.14.26/0006-spi-add-rb4xx-SPI-driver.patch | 557 +++
.../3.14.26/0007-spi-add-rb4xx-cpld-driver.patch | 548 +++
.../3.14.26/0008-gpio-add-GPIO-latch-driver.patch | 290 ++
...0009-spi-export-spi_bitbang_bufs-function.patch | 45 +
...spi-add-type-field-to-spi_transfer-struct.patch | 37 +
.../0011-mtd-m25p80-set-SPI-transfer-type.patch | 29 +
...mips-ath79-swizzle-PCI-address-for-ar71xx.patch | 130 +
.../3.14.26/0013-net-add-swconfig-support.patch | 1859 +++++++++
...-add-detach-callback-to-struct-phy_driver.patch | 46 +
.../3.14.26/0015-phy-add-ar8216-PHY-support.patch | 3671 +++++++++++++++++
.../0016-phy-mdio-bitbang-ignore-TA-value.patch | 44 +
.../0017-MIPS-ath79-fix-maximum-timeout.patch | 37 +
...PHY-drivers-to-insert-packet-mangle-hooks.patch | 211 +
...9-MIPS-ath79-process-board-cmdline-option.patch | 26 +
...020-spi-ath79-add-fast-flash-read-support.patch | 202 +
.../3.14.26/0021-phy-add-mdio-boardinfo.patch | 227 ++
...0022-mips-ath79-add-ath79-ethernet-driver.patch | 1429 +++++++
...S-ath79-add-Mikrotik-rb4xx-device-support.patch | 536 +++
.../3.14.26/0024-various-fixups-for-Werror.patch | 105 +
.../0025-rb4xx_nand-add-partition-for-cfgfs.patch | 28 +
...us-fixups-for-ath5k-fixing-system-freezes.patch | 108 +
52 files changed, 14902 insertions(+), 14902 deletions(-)
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0001-mtd-add-rb4xx-nand-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0002-phy-add-ethtool-ioctl-support-used-by-ag71xx-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0003-net-add-ag71xx-mac-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0004-drivers-link-SPI-drivers-before-MTD-drivers.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0005-spi-add-various-flags-to-spi_transfer-and-spi_messag.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0006-spi-add-rb4xx-SPI-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0007-spi-add-rb4xx-cpld-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0008-gpio-add-GPIO-latch-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0009-spi-export-spi_bitbang_bufs-function.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0010-spi-add-type-field-to-spi_transfer-struct.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0011-mtd-m25p80-set-SPI-transfer-type.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0012-mips-ath79-swizzle-PCI-address-for-ar71xx.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0013-net-add-swconfig-support.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0014-phy-add-detach-callback-to-struct-phy_driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0015-phy-add-ar8216-PHY-support.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0016-phy-mdio-bitbang-ignore-TA-value.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0017-MIPS-ath79-fix-maximum-timeout.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0018-net-allow-PHY-drivers-to-insert-packet-mangle-hooks.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0019-MIPS-ath79-process-board-cmdline-option.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0020-spi-ath79-add-fast-flash-read-support.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0021-phy-add-mdio-boardinfo.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0022-mips-ath79-add-ath79-ethernet-driver.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0023-MIPS-ath79-add-Mikrotik-rb4xx-device-support.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0024-various-fixups-for-Werror.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0025-rb4xx_nand-add-partition-for-cfgfs.patch
delete mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.22/0026-various-fixups-for-ath5k-fixing-system-freezes.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0001-mtd-add-rb4xx-nand-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0002-phy-add-ethtool-ioctl-support-used-by-ag71xx-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0003-net-add-ag71xx-mac-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0004-drivers-link-SPI-drivers-before-MTD-drivers.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0005-spi-add-various-flags-to-spi_transfer-and-spi_messag.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0006-spi-add-rb4xx-SPI-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0007-spi-add-rb4xx-cpld-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0008-gpio-add-GPIO-latch-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0009-spi-export-spi_bitbang_bufs-function.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0010-spi-add-type-field-to-spi_transfer-struct.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0011-mtd-m25p80-set-SPI-transfer-type.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0012-mips-ath79-swizzle-PCI-address-for-ar71xx.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0013-net-add-swconfig-support.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0014-phy-add-detach-callback-to-struct-phy_driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0015-phy-add-ar8216-PHY-support.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0016-phy-mdio-bitbang-ignore-TA-value.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0017-MIPS-ath79-fix-maximum-timeout.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0018-net-allow-PHY-drivers-to-insert-packet-mangle-hooks.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0019-MIPS-ath79-process-board-cmdline-option.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0020-spi-ath79-add-fast-flash-read-support.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0021-phy-add-mdio-boardinfo.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0022-mips-ath79-add-ath79-ethernet-driver.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0023-MIPS-ath79-add-Mikrotik-rb4xx-device-support.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0024-various-fixups-for-Werror.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0025-rb4xx_nand-add-partition-for-cfgfs.patch
create mode 100644 target/mips/mikrotik-rb4xx/patches/3.14.26/0026-various-fixups-for-ath5k-fixing-system-freezes.patch
(limited to 'target/mips/mikrotik-rb4xx')
diff --git a/target/mips/mikrotik-rb4xx/patches/3.14.22/0001-mtd-add-rb4xx-nand-driver.patch b/target/mips/mikrotik-rb4xx/patches/3.14.22/0001-mtd-add-rb4xx-nand-driver.patch
deleted file mode 100644
index 8199de991..000000000
--- a/target/mips/mikrotik-rb4xx/patches/3.14.22/0001-mtd-add-rb4xx-nand-driver.patch
+++ /dev/null
@@ -1,351 +0,0 @@
-From 1e692cc0c53202b932eedabd0315107910c5b093 Mon Sep 17 00:00:00 2001
-From: Phil Sutter <phil@nwl.cc>
-Date: Tue, 13 May 2014 00:08:54 +0200
-Subject: [PATCH] mtd: add rb4xx nand driver
-
----
- drivers/mtd/nand/Kconfig | 4 +
- drivers/mtd/nand/Makefile | 1 +
- drivers/mtd/nand/rb4xx_nand.c | 305 ++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 310 insertions(+)
- create mode 100644 drivers/mtd/nand/rb4xx_nand.c
-
-diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
-index 90ff447..bb01309 100644
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -510,4 +510,8 @@ config MTD_NAND_XWAY
- Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
- to the External Bus Unit (EBU).
-
-+config MTD_NAND_RB4XX
-+ tristate "NAND flash driver for RouterBoard 4xx series"
-+ depends on MTD_NAND && ATH79_MACH_RB4XX
-+
- endif # MTD_NAND
-diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
-index 542b568..e2b5e1c 100644
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -31,6 +31,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
- obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
- obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
- obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
-+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
- obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
- obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
- obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
-diff --git a/drivers/mtd/nand/rb4xx_nand.c b/drivers/mtd/nand/rb4xx_nand.c
-new file mode 100644
-index 0000000..5b9841b
---- /dev/null
-+++ b/drivers/mtd/nand/rb4xx_nand.c
-@@ -0,0 +1,305 @@
-+/*
-+ * NAND flash driver for the MikroTik RouterBoard 4xx series
-+ *
-+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This file was based on the driver for Linux 2.6.22 published by
-+ * MikroTik for their RouterBoard 4xx series devices.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/mtd/nand.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/platform_device.h>
-+#include <linux/delay.h>
-+#include <linux/io.h>
-+#include <linux/gpio.h>
-+#include <linux/slab.h>
-+
-+#include <asm/mach-ath79/ath79.h>
-+#include <asm/mach-ath79/rb4xx_cpld.h>
-+
-+#define DRV_NAME "rb4xx-nand"
-+#define DRV_VERSION "0.2.0"
-+#define DRV_DESC "NAND flash driver for RouterBoard 4xx series"
-+
-+#define RB4XX_NAND_GPIO_READY 5
-+#define RB4XX_NAND_GPIO_ALE 37
-+#define RB4XX_NAND_GPIO_CLE 38
-+#define RB4XX_NAND_GPIO_NCE 39
-+
-+struct rb4xx_nand_info {
-+ struct nand_chip chip;
-+ struct mtd_info mtd;
-+};
-+
-+/*
-+ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
-+ * will not be able to find the kernel that we load.
-+ */
-+static struct nand_ecclayout rb4xx_nand_ecclayout = {
-+ .eccbytes = 6,
-+ .eccpos = { 8, 9, 10, 13, 14, 15 },
-+ .oobavail = 9,
-+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
-+};
-+
-+static struct mtd_partition rb4xx_nand_partitions[] = {
-+ {
-+ .name = "booter",
-+ .offset = 0,
-+ .size = (256 * 1024),
-+ .mask_flags = MTD_WRITEABLE,
-+ },
-+ {
-+ .name = "kernel",
-+ .offset = (256 * 1024),
-+ .size = (4 * 1024 * 1024) - (256 * 1024),
-+ },
-+ {
-+ .name = "rootfs",
-+ .offset = MTDPART_OFS_NXTBLK,
-+ .size = MTDPART_SIZ_FULL,
-+ },
-+};
-+
-+static int rb4xx_nand_dev_ready(struct mtd_info *mtd)
-+{
-+ return gpio_get_value_cansleep(RB4XX_NAND_GPIO_READY);
-+}
-+
-+static void rb4xx_nand_write_cmd(unsigned char cmd)
-+{
-+ unsigned char data = cmd;
-+ int err;
-+
-+ err = rb4xx_cpld_write(&data, 1);
-+ if (err)
-+ pr_err("rb4xx_nand: write cmd failed, err=%d\n", err);
-+}
-+
-+static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
-+ unsigned int ctrl)
-+{
-+ if (ctrl & NAND_CTRL_CHANGE) {
-+ gpio_set_value_cansleep(RB4XX_NAND_GPIO_CLE,
-+ (ctrl & NAND_CLE) ? 1 : 0);
-+ gpio_set_value_cansleep(RB4XX_NAND_GPIO_ALE,
-+ (ctrl & NAND_ALE) ? 1 : 0);
-+ gpio_set_value_cansleep(RB4XX_NAND_GPIO_NCE,
-+ (ctrl & NAND_NCE) ? 0 : 1);
-+ }
-+
-+ if (cmd != NAND_CMD_NONE)
-+ rb4xx_nand_write_cmd(cmd);
-+}
-+
-+static unsigned char rb4xx_nand_read_byte(struct mtd_info *mtd)
-+{
-+ unsigned char data = 0;
-+ int err;
-+
-+ err = rb4xx_cpld_read(&data, NULL, 1);
-+ if (err) {
-+ pr_err("rb4xx_nand: read data failed, err=%d\n", err);
-+ data = 0xff;
-+ }
-+
-+ return data;
-+}
-+
-+static void rb4xx_nand_write_buf(struct mtd_info *mtd, const unsigned char *buf,
-+ int len)
-+{
-+ int err;
-+
-+ err = rb4xx_cpld_write(buf, len);
-+ if (err)
-+ pr_err("rb4xx_nand: write buf failed, err=%d\n", err);
-+}
-+
-+static void rb4xx_nand_read_buf(struct mtd_info *mtd, unsigned char *buf,
-+ int len)
-+{
-+ int err;
-+
-+ err = rb4xx_cpld_read(buf, NULL, len);
-+ if (err)
-+ pr_err("rb4xx_nand: read buf failed, err=%d\n", err);
-+}
-+
-+static int rb4xx_nand_probe(struct platform_device *pdev)
-+{
-+ struct rb4xx_nand_info *info;
-+ int ret;
-+
-+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n");
-+
-+ ret = gpio_request(RB4XX_NAND_GPIO_READY, "NAND RDY");
-+ if (ret) {
-+ dev_err(&pdev->dev, "unable to request gpio %d\n",
-+ RB4XX_NAND_GPIO_READY);
-+ goto err;
-+ }
-+
-+ ret = gpio_direction_input(RB4XX_NAND_GPIO_READY);
-+ if (ret) {
-+ dev_err(&pdev->dev, "unable to set input mode on gpio %d\n",
-+ RB4XX_NAND_GPIO_READY);
-+ goto err_free_gpio_ready;
-+ }
-+
-+ ret = gpio_request(RB4XX_NAND_GPIO_ALE, "NAND ALE");
-+ if (ret) {
-+ dev_err(&pdev->dev, "unable to request gpio %d\n",
-+ RB4XX_NAND_GPIO_ALE);
-+ goto err_free_gpio_ready;
-+ }
-+
-+ ret = gpio_direction_output(RB4XX_NAND_GPIO_ALE, 0);
-+ if (ret) {
-+ dev_err(&pdev->dev, "unable to set output mode on gpio %d\n",
-+ RB4XX_NAND_GPIO_ALE);
-+ goto err_free_gpio_ale;
-+ }
-+
-+ ret = gpio_request(RB4XX_NAND_GPIO_CLE, "NAND CLE");
-+ if (ret) {
-+ dev_err(&pdev->dev, "unable to request gpio %d\n",
-+ RB4XX_NAND_GPIO_CLE);
-+ goto err_free_gpio_ale;
-+ }
-+
-+ ret = gpio_direction_output(RB4XX_NAND_GPIO_CLE, 0);
-+ if (ret) {
-+ dev_err(&pdev->dev, "unable to set output mode on gpio %d\n",
-+ RB4XX_NAND_GPIO_CLE);
-+ goto err_free_gpio_cle;
-+ }
-+
-+ ret = gpio_request(RB4XX_NAND_GPIO_NCE, "NAND NCE");
-+ if (ret) {
-+ dev_err(&pdev->dev, "unable to request gpio %d\n",
-+ RB4XX_NAND_GPIO_NCE);
-+ goto err_free_gpio_cle;
-+ }
-+
-+ ret = gpio_direction_output(RB4XX_NAND_GPIO_NCE, 1);
-+ if (ret) {
-+ dev_err(&pdev->dev, "unable to set output mode on gpio %d\n",
-+ RB4XX_NAND_GPIO_ALE);
-+ goto err_free_gpio_nce;
-+ }
-+
-+ info = kzalloc(sizeof(*info), GFP_KERNEL);
-+ if (!info) {
-+ dev_err(&pdev->dev, "rb4xx-nand: no memory for private data\n");
-+ ret = -ENOMEM;
-+ goto err_free_gpio_nce;
-+ }
-+
-+ info->chip.priv = &info;
-+ info->mtd.priv = &info->chip;
-+ info->mtd.owner = THIS_MODULE;
-+
-+ info->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl;
-+ info->chip.dev_ready = rb4xx_nand_dev_ready;
-+ info->chip.read_byte = rb4xx_nand_read_byte;
-+ info->chip.write_buf = rb4xx_nand_write_buf;
-+ info->chip.read_buf = rb4xx_nand_read_buf;
-+
-+ info->chip.chip_delay = 25;
-+ info->chip.ecc.mode = NAND_ECC_SOFT;
-+
-+ platform_set_drvdata(pdev, info);
-+
-+ ret = nand_scan_ident(&info->mtd, 1, NULL);
-+ if (ret) {
-+ ret = -ENXIO;
-+ goto err_free_info;
-+ }
-+
-+ if (info->mtd.writesize == 512)
-+ info->chip.ecc.layout = &rb4xx_nand_ecclayout;
-+
-+ ret = nand_scan_tail(&info->mtd);
-+ if (ret) {
-+ return -ENXIO;
-+ goto err_set_drvdata;
-+ }
-+
-+ mtd_device_register(&info->mtd, rb4xx_nand_partitions,
-+ ARRAY_SIZE(rb4xx_nand_partitions));
-+ if (ret)
-+ goto err_release_nand;
-+
-+ return 0;
-+
-+err_release_nand:
-+ nand_release(&info->mtd);
-+err_set_drvdata:
-+ platform_set_drvdata(pdev, NULL);
-+err_free_info:
-+ kfree(info);
-+err_free_gpio_nce:
-+ gpio_free(RB4XX_NAND_GPIO_NCE);
-+err_free_gpio_cle:
-+ gpio_free(RB4XX_NAND_GPIO_CLE);
-+err_free_gpio_ale:
-+ gpio_free(RB4XX_NAND_GPIO_ALE);
-+err_free_gpio_ready:
-+ gpio_free(RB4XX_NAND_GPIO_READY);
-+err:
-+ return ret;
-+}
-+
-+static int rb4xx_nand_remove(struct platform_device *pdev)
-+{
-+ struct rb4xx_nand_info *info = platform_get_drvdata(pdev);
-+
-+ nand_release(&info->mtd);
-+ platform_set_drvdata(pdev, NULL);
-+ kfree(info);
-+ gpio_free(RB4XX_NAND_GPIO_NCE);
-+ gpio_free(RB4XX_NAND_GPIO_CLE);
-+ gpio_free(RB4XX_NAND_GPIO_ALE);
-+ gpio_free(RB4XX_NAND_GPIO_READY);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver rb4xx_nand_driver = {
-+ .probe = rb4xx_nand_probe,
-+ .remove = rb4xx_nand_remove,
-+ .driver = {
-+ .name = DRV_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init rb4xx_nand_init(void)
-+{
-+ return platform_driver_register(&rb4xx_nand_driver);
-+}
-+
-+static void __exit rb4xx_nand_exit(void)
-+{
-+ platform_driver_unregister(&rb4xx_nand_driver);
-+}
-+
-+module_init(rb4xx_nand_init);
-+module_exit(rb4xx_nand_exit);
-+
-+MODULE_DESCRIPTION(DRV_DESC);
-+MODULE_VERSION(DRV_VERSION);
-+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-+MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
-+MODULE_LICENSE("GPL v2");
---
-1.8.5.3
-
diff --git a/target/mips/mikrotik-rb4xx/patches/3.14.22/0002-phy-add-ethtool-ioctl-support-used-by-ag71xx-driver.patch b/target/mips/mikrotik-rb4xx/patches/3.14.22/0002-phy-add-ethtool-ioctl-support-used-by-ag71xx-driver.patch
deleted file mode 100644
index ba7fbfad8..000000000
--- a/target/mips/mikrotik-rb4xx/patches/3.14.22/0002-phy-add-ethtool-ioctl-support-used-by-ag71xx-driver.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 7b864612a6e3b139a5a607abd0048a19078fe42f Mon Sep 17 00:00:00 2001
-From: Phil Sutter <phil@nwl.cc>
-Date: Wed, 14 May 2014 02:55:06 +0200
-Subject: [PATCH] phy: add ethtool ioctl support, used by ag71xx driver
-
----
- drivers/net/phy/phy.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
- include/linux/phy.h | 1 +
- 2 files changed, 45 insertions(+)
-
-diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
-index 76d96b9..9439ef3 100644
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -293,6 +293,50 @@ int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd)
- }
- EXPORT_SYMBOL(phy_ethtool_gset);
-
-+int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr)
-+{
-+ u32 cmd;
-+ int tmp;
-+ struct ethtool_cmd ecmd = { ETHTOOL_GSET };
-+ struct ethtool_value edata = { ETHTOOL_GLINK };
-+
-+ if (get_user(cmd, (u32 *) useraddr))
-+ return -EFAULT;
-+
-+ switch (cmd) {
-+ case ETHTOOL_GSET:
-+ phy_ethtool_gset(phydev, &ecmd);
-+ if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
-+ return -EFAULT;
-+ return 0;
-+
-+ case ETHTOOL_SSET:
-+ if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
-+ return -EFAULT;
-+ return phy_ethtool_sset(phydev, &ecmd);
-+
-+ case ETHTOOL_NWAY_RST:
-+ /* if autoneg is off, it's an error */
-+ tmp = phy_read(phydev, MII_BMCR);
-+ if (tmp & BMCR_ANENABLE) {
-+ tmp |= (BMCR_ANRESTART);
-+ phy_write(phydev, MII_BMCR, tmp);
-+ return 0;
-+ }
-+ return -EINVAL;
-+
-+ case ETHTOOL_GLINK:
-+ edata.data = (phy_read(phydev,
-+ MII_BMSR) & BMSR_LSTATUS) ? 1 : 0;
-+ if (copy_to_user(useraddr, &edata, sizeof(edata)))
-+ return -EFAULT;
-+ return 0;
-+ }
-+
-+ return -EOPNOTSUPP;
-+}
-+EXPORT_SYMBOL(phy_ethtool_ioctl);
-+
- /**
- * phy_mii_ioctl - generic PHY MII ioctl interface
- * @phydev: the phy_device struct
-diff --git a/include/linux/phy.h b/include/linux/phy.h
-index 565188c..9ab0d79 100644
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -628,6 +628,7 @@ void phy_stop_machine(struct phy_device *phydev);
- int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd);
- int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd);
- int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd);
-+int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr);
- int phy_start_interrupts(struct phy_device *phydev);
- void phy_print_status(struct phy_device *phydev);
- void phy_device_free(struct phy_device *phydev);
---
-1.8.5.3
-
diff --git a/target/mips/mikrotik-rb4xx/patches/3.14.22/0003-net-add-ag71xx-mac-driver.patch b/target/mips/mikrotik-rb4xx/patches/3.14.22/0003-net-add-ag71xx-mac-driver.patch
deleted file mode 100644
index 1915c184c..000000000
--- a/target/mips/mikrotik-rb4xx/patches/3.14.22/0003-net-add-ag71xx-mac-driver.patch
+++ /dev/null
@@ -1,4245 +0,0 @@
-From c5eb03f91f9185f4813431692f36db3862716a35 Mon Sep 17 00:00:00 2001
-From: Phil Sutter <phil@nwl.cc>
-Date: Tue, 13 May 2014 00:12:37 +0200
-Subject: [PATCH] net: add ag71xx mac driver
-
----
- arch/mips/include/asm/mach-ath79/ag71xx_platform.h | 65 +
- drivers/net/ethernet/atheros/Kconfig | 2 +
- drivers/net/ethernet/atheros/Makefile | 1 +
- drivers/net/ethernet/atheros/ag71xx/Kconfig | 33 +
- drivers/net/ethernet/atheros/ag71xx/Makefile | 15 +
- drivers/net/ethernet/atheros/ag71xx/ag71xx.h | 476 +++++++
- .../net/ethernet/atheros/ag71xx/ag71xx_ar7240.c | 1202 ++++++++++++++++++
- .../net/ethernet/atheros/ag71xx/ag71xx_ar8216.c | 44 +
- .../net/ethernet/atheros/ag71xx/ag71xx_debugfs.c | 284 +++++
- .../net/ethernet/atheros/ag71xx/ag71xx_ethtool.c | 124 ++
- drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c | 1325 ++++++++++++++++++++
- drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c | 318 +++++
- drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c | 235 ++++
- 13 files changed, 4124 insertions(+)
- create mode 100644 arch/mips/include/asm/mach-ath79/ag71xx_platform.h
- create mode 100644 drivers/net/ethernet/atheros/ag71xx/Kconfig
- create mode 100644 drivers/net/ethernet/atheros/ag71xx/Makefile
- create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx.h
- create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c
- create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c
- create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c
- create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c
- create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
- create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c
- create mode 100644 drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c
-
-diff --git a/arch/mips/include/asm/mach-ath79/ag71xx_platform.h b/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
-new file mode 100644
-index 0000000..d46dc4e
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
-@@ -0,0 +1,65 @@
-+/*
-+ * Atheros AR71xx SoC specific platform data definitions
-+ *
-+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#ifndef __ASM_MACH_ATH79_PLATFORM_H
-+#define __ASM_MACH_ATH79_PLATFORM_H
-+
-+#include <linux/if_ether.h>
-+#include <linux/skbuff.h>
-+#include <linux/phy.h>
-+#include <linux/spi/spi.h>
-+
-+struct ag71xx_switch_platform_data {
-+ u8 phy4_mii_en:1;
-+ u8 phy_poll_mask;
-+};
-+
-+struct ag71xx_platform_data {
-+ phy_interface_t phy_if_mode;
-+ u32 phy_mask;
-+ int speed;
-+ int duplex;
-+ u32 reset_bit;
-+ u8 mac_addr[ETH_ALEN];
-+ struct device *mii_bus_dev;
-+
-+ u8 has_gbit:1;
-+ u8 is_ar91xx:1;
-+ u8 is_ar7240:1;
-+ u8 is_ar724x:1;
-+ u8 has_ar8216:1;
-+
-+ struct ag71xx_switch_platform_data *switch_data;
-+
-+ void (*ddr_flush)(void);
-+ void (*set_speed)(int speed);
-+
-+ u32 fifo_cfg1;
-+ u32 fifo_cfg2;
-+ u32 fifo_cfg3;
-+
-+ unsigned int max_frame_len;
-+ unsigned int desc_pktlen_mask;
-+};
-+
-+struct ag71xx_mdio_platform_data {
-+ u32 phy_mask;
-+ u8 builtin_switch:1;
-+ u8 is_ar7240:1;
-+ u8 is_ar9330:1;
-+ u8 is_ar934x:1;
-+ unsigned long mdio_clock;
-+ unsigned long ref_clock;
-+
-+ void (*reset)(struct mii_bus *bus);
-+};
-+
-+#endif /* __ASM_MACH_ATH79_PLATFORM_H */
-diff --git a/drivers/net/ethernet/atheros/Kconfig b/drivers/net/ethernet/atheros/Kconfig
-index 58ad37c..1fae572 100644
---- a/drivers/net/ethernet/atheros/Kconfig
-+++ b/drivers/net/ethernet/atheros/Kconfig
-@@ -80,4 +80,6 @@ config ALX
- To compile this driver as a module, choose M here. The module
- will be called alx.
-
-+source drivers/net/ethernet/atheros/ag71xx/Kconfig
-+
- endif # NET_VENDOR_ATHEROS
-diff --git a/drivers/net/ethernet/atheros/Makefile b/drivers/net/ethernet/atheros/Makefile
-index 5cf1c65..d1c5a49 100644
---- a/drivers/net/ethernet/atheros/Makefile
-+++ b/drivers/net/ethernet/atheros/Makefile
-@@ -2,6 +2,7 @@
- # Makefile for the Atheros network device drivers.
- #
-
-+obj-$(CONFIG_AG71XX) += ag71xx/
- obj-$(CONFIG_ATL1) += atlx/
- obj-$(CONFIG_ATL2) += atlx/
- obj-$(CONFIG_ATL1E) += atl1e/
-diff --git a/drivers/net/ethernet/atheros/ag71xx/Kconfig b/drivers/net/ethernet/atheros/ag71xx/Kconfig
-new file mode 100644
-index 0000000..42d544f
---- /dev/null
-+++ b/drivers/net/ethernet/atheros/ag71xx/Kconfig
-@@ -0,0 +1,33 @@
-+config AG71XX
-+ tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support"
-+ depends on ATH79
-+ select PHYLIB
-+ help
-+ If you wish to compile a kernel for AR7XXX/91XXX and enable
-+ ethernet support, then you should always answer Y to this.
-+
-+if AG71XX
-+
-+config AG71XX_DEBUG
-+ bool "Atheros AR71xx built-in ethernet driver debugging"
-+ default n
-+ help
-+ Atheros AR71xx built-in ethernet driver debugging messages.
-+
-+config AG71XX_DEBUG_FS
-+ bool "Atheros AR71xx built-in ethernet driver debugfs support"
-+ depends on DEBUG_FS
-+ default n
-+ help
-+ Say Y, if you need access to various statistics provided by
-+ the ag71xx driver.
-+
-+config AG71XX_AR8216_SUPPORT
-+ bool "special support for the Atheros AR8216 switch"
-+ default n
-+ default y if ATH79_MACH_WNR2000 || ATH79_MACH_MZK_W04NU
-+ help
-+ Say 'y' here if you want to enable special support for the
-+ Atheros AR8216 switch found on some boards.
-+
-+endif
-diff --git a/drivers/net/ethernet/atheros/ag71xx/Makefile b/drivers/net/ethernet/atheros/ag71xx/Makefile
-new file mode 100644
-index 0000000..b3ec408
---- /dev/null
-+++ b/drivers/net/ethernet/atheros/ag71xx/Makefile
-@@ -0,0 +1,15 @@
-+#
-+# Makefile for the Atheros AR71xx built-in ethernet macs
-+#
-+
-+ag71xx-y += ag71xx_main.o
-+ag71xx-y += ag71xx_ethtool.o
-+ag71xx-y += ag71xx_phy.o
-+ag71xx-y += ag71xx_mdio.o
-+ag71xx-y += ag71xx_ar7240.o
-+
-+ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o
-+ag71xx-$(CONFIG_AG71XX_AR8216_SUPPORT) += ag71xx_ar8216.o
-+
-+obj-$(CONFIG_AG71XX) += ag71xx.o
-+
-diff --git a/drivers/net/ethernet/atheros/ag71xx/ag71xx.h b/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
-new file mode 100644
-index 0000000..f6d85b9
---- /dev/null
-+++ b/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
-@@ -0,0 +1,476 @@
-+/*
-+ * Atheros AR71xx built-in ethernet mac driver
-+ *
-+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * Based on Atheros' AG7100 driver
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+
-+#ifndef __AG71XX_H
-+#define __AG71XX_H
-+
-+#include <linux/kernel.h>
-+#include <linux/version.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/types.h>
-+#include <linux/random.h>
-+#include <linux/spinlock.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/ethtool.h>
-+#include <linux/etherdevice.h>
-+#include <linux/if_vlan.h>
-+#include <linux/phy.h>
-+#include <linux/skbuff.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/workqueue.h>
-+
-+#include <linux/bitops.h>
-+
-+#include <asm/mach-ath79/ar71xx_regs.h>
-+#include <asm/mach-ath79/ath79.h>
-+#include <asm/mach-ath79/ag71xx_platform.h>
-+
-+#define AG71XX_DRV_NAME "ag71xx"
-+#define AG71XX_DRV_VERSION "0.5.35"
-+
-+#define AG71XX_NAPI_WEIGHT 64
-+#define AG71XX_OOM_REFILL (1 + HZ/10)
-+
-+#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
-+#define AG71XX_INT_TX (AG71XX_INT_TX_PS)
-+#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
-+
-+#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
-+#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
-+
-+#define AG71XX_TX_MTU_LEN 1540
-+
-+#define AG71XX_TX_RING_SIZE_DEFAULT 32
-+#define AG71XX_RX_RING_SIZE_DEFAULT 128
-+
-+#define AG71XX_TX_RING_SIZE_MAX 32
-+#define AG71XX_RX_RING_SIZE_MAX 128
-+
-+#ifdef CONFIG_AG71XX_DEBUG
-+#define DBG(fmt, args...) pr_debug(fmt, ## args)
-+#else
-+#define DBG(fmt, args...) do {} while (0)
-+#endif
-+
-+#define ag71xx_assert(_cond) \
-+do { \
-+ if (_cond) \
-+ break; \
-+ printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
-+ BUG(); \
-+} while (0)
-+
-+struct ag71xx_desc {
-+ u32 data;
-+ u32 ctrl;
-+#define DESC_EMPTY BIT(31)
-+#define DESC_MORE BIT(24)
-+#define DESC_PKTLEN_M 0xfff
-+ u32 next;
-+ u32 pad;
-+} __attribute__((aligned(4)));
-+
-+struct ag71xx_buf {
-+ union {
-+ struct sk_buff *skb;
-+ void *rx_buf;
-+ };
-+ struct ag71xx_desc *desc;
-+ union {
-+ dma_addr_t dma_addr;
-+ unsigned long timestamp;
-+ };
-+ unsigned int len;
-+};
-+
-+struct ag71xx_ring {
-+ struct ag71xx_buf *buf;
-+ u8 *descs_cpu;
-+ dma_addr_t descs_dma;
-+ unsigned int desc_size;
-+ unsigned int curr;
-+ unsigned int dirty;
-+ unsigned int size;
-+};
-+
-+struct ag71xx_mdio {
-+ struct mii_bus *mii_bus;
-+ int mii_irq[PHY_MAX_ADDR];
-+ void __iomem *mdio_base;
-+ struct ag71xx_mdio_platform_data *pdata;
-+};
-+
-+struct ag71xx_int_stats {
-+ unsigned long rx_pr;
-+ unsigned long rx_be;
-+ unsigned long rx_of;
-+ unsigned long tx_ps;
-+ unsigned long tx_be;
-+ unsigned long tx_ur;
-+ unsigned long total;
-+};
-+
-+struct ag71xx_napi_stats {
-+ unsigned long napi_calls;
-+ unsigned long rx_count;
-+ unsigned long rx_packets;
-+ unsigned long rx_packets_max;
-+ unsigned long tx_count;
-+ unsigned long tx_packets;
-+ unsigned long tx_packets_max;
-+
-+ unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
-+ unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
-+};
-+
-+struct ag71xx_debug {
-+ struct dentry *debugfs_dir;
-+
-+ struct ag71xx_int_stats int_stats;
-+ struct ag71xx_napi_stats napi_stats;
-+};
-+
-+struct ag71xx {
-+ void __iomem *mac_base;
-+
-+ spinlock_t lock;
-+ struct platform_device *pdev;
-+ struct net_device *dev;
-+ struct napi_struct napi;
-+ u32 msg_enable;
-+
-+ struct ag71xx_desc *stop_desc;
-+ dma_addr_t stop_desc_dma;
-+
-+ struct ag71xx_ring rx_ring;
-+ struct ag71xx_ring tx_ring;
-+
-+ struct mii_bus *mii_bus;
-+ struct phy_device *phy_dev;
-+ void *phy_priv;
-+
-+ unsigned int link;
-+ unsigned int speed;
-+ int duplex;
-+
-+ unsigned int max_frame_len;
-+ unsigned int desc_pktlen_mask;
-+ unsigned int rx_buf_size;
-+
-+ struct work_struct restart_work;
-+ struct delayed_work link_work;
-+ struct timer_list oom_timer;
-+
-+#ifdef CONFIG_AG71XX_DEBUG_FS
-+ struct ag71xx_debug debug;
-+#endif
-+};
-+
-+extern struct ethtool_ops ag71xx_ethtool_ops;
-+void ag71xx_link_adjust(struct ag71xx *ag);
-+
-+int ag71xx_mdio_driver_init(void) __init;
-+void ag71xx_mdio_driver_exit(void);
-+
-+int ag71xx_phy_connect(struct ag71xx *ag);
-+void ag71xx_phy_disconnect(struct ag71xx *ag);
-+void ag71xx_phy_start(struct ag71xx *ag);
-+void ag71xx_phy_stop(struct ag71xx *ag);
-+
-+static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
-+{
-+ return ag->pdev->dev.platform_data;
-+}
-+
-+static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
-+{
-+ return (desc->ctrl & DESC_EMPTY) != 0;
-+}
-+
-+/* Register offsets */
-+#define AG71XX_REG_MAC_CFG1 0x0000
-+#define AG71XX_REG_MAC_CFG2 0x0004
-+#define AG71XX_REG_MAC_IPG 0x0008
-+#define AG71XX_REG_MAC_HDX 0x000c
-+#define AG71XX_REG_MAC_MFL 0x0010
-+#define AG71XX_REG_MII_CFG 0x0020
-+#define AG71XX_REG_MII_CMD 0x0024
-+#define AG71XX_REG_MII_ADDR 0x0028
-+#define AG71XX_REG_MII_CTRL 0x002c
-+#define AG71XX_REG_MII_STATUS 0x0030
-+#define AG71XX_REG_MII_IND 0x0034
-+#define AG71XX_REG_MAC_IFCTL 0x0038
-+#define AG71XX_REG_MAC_ADDR1 0x0040
-+#define AG71XX_REG_MAC_ADDR2 0x0044
-+#define AG71XX_REG_FIFO_CFG0 0x0048
-+#define AG71XX_REG_FIFO_CFG1 0x004c
-+#define AG71XX_REG_FIFO_CFG2 0x0050
-+#define AG71XX_REG_FIFO_CFG3 0x0054
-+#define AG71XX_REG_FIFO_CFG4 0x0058
-+#define AG71XX_REG_FIFO_CFG5 0x005c
-+#define AG71XX_REG_FIFO_RAM0 0x0060
-+#define AG71XX_REG_FIFO_RAM1 0x0064
-+#define AG71XX_REG_FIFO_RAM2 0x0068
-+#define AG71XX_REG_FIFO_RAM3 0x006c
-+#define AG71XX_REG_FIFO_RAM4 0x0070
-+#define AG71XX_REG_FIFO_RAM5 0x0074
-+#define AG71XX_REG_FIFO_RAM6 0x0078
-+#define AG71XX_REG_FIFO_RAM7 0x007c
-+
-+#define AG71XX_REG_TX_CTRL 0x0180
-+#define AG71XX_REG_TX_DESC 0x0184
-+#define AG71XX_REG_TX_STATUS 0x0188
-+#define AG71XX_REG_RX_CTRL 0x018c
-+#define AG71XX_REG_RX_DESC 0x0190
-+#define AG71XX_REG_RX_STATUS 0x0194
-+#define AG71XX_REG_INT_ENABLE 0x0198
-+#define AG71XX_REG_INT_STATUS 0x019c
-+
-+#define AG71XX_REG_FIFO_DEPTH 0x01a8
-+#define AG71XX_REG_RX_SM 0x01b0
-+#define AG71XX_REG_TX_SM 0x01b4
-+
-+#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
-+#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
-+#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
-+#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
-+#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
-+#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
-+#define MAC_CFG1_LB BIT(8) /* Loopback mode */
-+#define MAC_CFG1_SR BIT(31) /* Soft Reset */
-+
-+#define MAC_CFG2_FDX BIT(0)
-+#define MAC_CFG2_CRC_EN BIT(1)
-+#define MAC_CFG2_PAD_CRC_EN BIT(2)
-+#define MAC_CFG2_LEN_CHECK BIT(4)
-+#define MAC_CFG2_HUGE_FRAME_EN BIT(5)
-+#define MAC_CFG2_IF_1000 BIT(9)
-+#define MAC_CFG2_IF_10_100 BIT(8)
-+
-+#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
-+#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
-+#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
-+#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
-+#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
-+#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
-+ | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
-+
-+#define FIFO_CFG0_ENABLE_SHIFT 8
-+
-+#define FIFO_CFG4_DE BIT(0) /* Drop Event */
-+#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
-+#define FIFO_CFG4_FC BIT(2) /* False Carrier */
-+#define FIFO_CFG4_CE BIT(3) /* Code Error */
-+#define FIFO_CFG4_CR BIT(4) /* CRC error */
-+#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
-+#define FIFO_CFG4_LO BIT(6) /* Length out of range */
-+#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
-+#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
-+#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
-+#define FIFO_CFG4_DR BIT(10) /* Dribble */
-+#define FIFO_CFG4_LE BIT(11) /* Long Event */
-+#define FIFO_CFG4_CF BIT(12) /* Control Frame */
-+#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
-+#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
-+#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
-+#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
-+#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
-+
-+#define FIFO_CFG5_DE BIT(0) /* Drop Event */
-+#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
-+#define FIFO_CFG5_FC BIT(2) /* False Carrier */
-+#define FIFO_CFG5_CE BIT(3) /* Code Error */
-+#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
-+#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
-+#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
-+#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
-+#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
-+#define FIFO_CFG5_DR BIT(9) /* Dribble */
-+#define FIFO_CFG5_CF BIT(10) /* Control Frame */
-+#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
-+#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
-+#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
-+#define FIFO_CFG5_LE BIT(14) /* Long Event */
-+#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
-+#define FIFO_CFG5_16 BIT(16) /* unknown */
-+#define FIFO_CFG5_17 BIT(17) /* unknown */
-+#define FIFO_CFG5_SF BIT(18) /* Short Frame */
-+#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
-+
-+#define AG71XX_INT_TX_PS BIT(0)
-+#define AG71XX_INT_TX_UR BIT(1)
-+#define AG71XX_INT_TX_BE BIT(3)
-+#define AG71XX_INT_RX_PR BIT(4)
-+#define AG71XX_INT_RX_OF BIT(6)
-+#define AG71XX_INT_RX_BE BIT(7)
-+
-+#define MAC_IFCTL_SPEED BIT(16)
-+
-+#define MII_CFG_CLK_DIV_4 0
-+#define MII_CFG_CLK_DIV_6 2
-+#define MII_CFG_CLK_DIV_8 3
-+#define MII_CFG_CLK_DIV_10 4
-+#define MII_CFG_CLK_DIV_14 5
-+#define MII_CFG_CLK_DIV_20 6
-+#define MII_CFG_CLK_DIV_28 7
-+#define MII_CFG_CLK_DIV_34 8
-+#define MII_CFG_CLK_DIV_42 9
-+#define MII_CFG_CLK_DIV_50 10
-+#define MII_CFG_CLK_DIV_58 11
-+#define MII_CFG_CLK_DIV_66 12
-+#define MII_CFG_CLK_DIV_74 13
-+#define MII_CFG_CLK_DIV_82 14
-+#define MII_CFG_CLK_DIV_98 15
-+#define MII_CFG_RESET BIT(31)
-+
-+#define MII_CMD_WRITE 0x0
-+#define MII_CMD_READ 0x1
-+#define MII_ADDR_SHIFT 8
-+#define MII_IND_BUSY BIT(0)
-+#define MII_IND_INVALID BIT(2)
-+
-+#define TX_CTRL_TXE BIT(0) /* Tx Enable */
-+
-+#define TX_STATUS_PS BIT(0) /* Packet Sent */
-+#define TX_STATUS_UR BIT(1) /* Tx Underrun */
-+#define TX_STATUS_BE BIT(3) /* Bus Error */
-+
-+#define RX_CTRL_RXE BIT(0) /* Rx Enable */
-+
-+#define RX_STATUS_PR BIT(0) /* Packet Received */
-+#define RX_STATUS_OF BIT(2) /* Rx Overflow */
-+#define RX_STATUS_BE BIT(3) /* Bus Error */
-+
-+static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
-+{
-+ switch (reg) {
-+ case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
-+ case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
-+ case AG71XX_REG_MII_CFG:
-+ break;
-+
-+ default:
-+ BUG();
-+ }
-+}
-+
-+static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
-+{
-+ ag71xx_check_reg_offset(ag, reg);
-+
-+ __raw_writel(value, ag->mac_base + reg);
-+ /* flush write */
-+ (void) __raw_readl(ag->mac_base + reg);
-+}
-+
-+static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
-+{
-+ ag71xx_check_reg_offset(ag, reg);
-+
-+ return __raw_readl(ag->mac_base + reg);
-+}
-+
-+static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
-+{
-+ void __iomem *r;
-+
-+ ag71xx_check_reg_offset(ag, reg);
-+
-+ r = ag->mac_base + reg;
-+ __raw_writel(__raw_readl(r) | mask, r);
-+ /* flush write */
-+ (void)__raw_readl(r);
-+}
-+
-+static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
-+{
-+ void __iomem *r;
-+
-+ ag71xx_check_reg_offset(ag, reg);
-+
-+ r = ag->mac_base + reg;
-+ __raw_writel(__raw_readl(r) & ~mask, r);
-+ /* flush write */
-+ (void) __raw_readl(r);
-+}
-+
-+static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
-+{
-+ ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
-+}
-+
-+static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
-+{
-+ ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
-+}
-+
-+#ifdef CONFIG_AG71XX_AR8216_SUPPORT
-+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
-+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
-+ int pktlen);
-+static inline int ag71xx_has_ar8216(struct ag71xx *ag)
-+{
-+ return ag71xx_get_pdata(ag)->has_ar8216;
-+}
-+#else
-+static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
-+ struct sk_buff *skb)
-+{
-+}
-+
-+static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
-+ struct sk_buff *skb,
-+ int pktlen)
-+{
-+ return 0;
-+}
-+static inline int ag71xx_has_ar8216(struct ag71xx *ag)
-+{
-+ return 0;
-+}
-+#endif
-+
-+#ifdef CONFIG_AG71XX_DEBUG_FS
-+int ag71xx_debugfs_root_init(void);
-+void ag71xx_debugfs_root_exit(void);
-+int ag71xx_debugfs_init(struct ag71xx *ag);
-+void ag71xx_debugfs_exit(struct ag71xx *ag);
-+void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
-+void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
-+#else
-+static inline int ag71xx_debugfs_root_init(void) { return 0; }
-+static inline void ag71xx_debugfs_root_exit(void) {}
-+static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
-+static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
-+static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
-+ u32 status) {}
-+static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
-+ int rx, int tx) {}
-+#endif /* CONFIG_AG71XX_DEBUG_FS */
-+
-+void ag71xx_ar7240_start(struct ag71xx *ag);
-+void ag71xx_ar7240_stop(struct ag71xx *ag);
-+int ag71xx_ar7240_init(struct ag71xx *ag);
-+void ag71xx_ar7240_cleanup(struct ag71xx *ag);
-+
-+int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
-+void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
-+
-+u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
-+ unsigned reg_addr);
-+int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
-+ unsigned reg_addr, u16 reg_val);
-+
-+#endif /* _AG71XX_H */
-diff --git a/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c b/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c
-new file mode 100644
-index 0000000..d4ccc02
---- /dev/null
-+++ b/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c
-@@ -0,0 +1,1202 @@
-+/*
-+ * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
-+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/etherdevice.h>
-+#include <linux/list.h>
-+#include <linux/netdevice.h>
-+#include <linux/phy.h>
-+#include <linux/mii.h>
-+#include <linux/bitops.h>
-+#include <linux/switch.h>
-+#include "ag71xx.h"
-+
-+#define BITM(_count) (BIT(_count) - 1)
-+#define BITS(_shift, _count) (BITM(_count) << _shift)
-+
-+#define AR7240_REG_MASK_CTRL 0x00
-+#define AR7240_MASK_CTRL_REVISION_M BITM(8)
-+#define AR7240_MASK_CTRL_VERSION_M BITM(8)
-+#define AR7240_MASK_CTRL_VERSION_S 8
-+#define AR7240_MASK_CTRL_VERSION_AR7240 0x01
-+#define AR7240_MASK_CTRL_VERSION_AR934X 0x02
-+#define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
-+
-+#define AR7240_REG_MAC_ADDR0 0x20
-+#define AR7240_REG_MAC_ADDR1 0x24
-+
-+#define AR7240_REG_FLOOD_MASK 0x2c
-+#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
-+
-+#define AR7240_REG_GLOBAL_CTRL 0x30
-+#define AR7240_GLOBAL_CTRL_MTU_M BITM(11)
-+#define AR9340_GLOBAL_CTRL_MTU_M BITM(14)
-+
-+#define AR7240_REG_VTU 0x0040
-+#define AR7240_VTU_OP BITM(3)
-+#define AR7240_VTU_OP_NOOP 0x0
-+#define AR7240_VTU_OP_FLUSH 0x1
-+#define AR7240_VTU_OP_LOAD 0x2
-+#define AR7240_VTU_OP_PURGE 0x3
-+#define AR7240_VTU_OP_REMOVE_PORT 0x4
-+#define AR7240_VTU_ACTIVE BIT(3)
-+#define AR7240_VTU_FULL BIT(4)
-+#define AR7240_VTU_PORT BITS(8, 4)
-+#define AR7240_VTU_PORT_S 8
-+#define AR7240_VTU_VID BITS(16, 12)
-+#define AR7240_VTU_VID_S 16
-+#define AR7240_VTU_PRIO BITS(28, 3)
-+#define AR7240_VTU_PRIO_S 28
-+#define AR7240_VTU_PRIO_EN BIT(31)
-+
-+#define AR7240_REG_VTU_DATA 0x0044
-+#define AR7240_VTUDATA_MEMBER BITS(0, 10)
-+#define AR7240_VTUDATA_VALID BIT(11)
-+
-+#define AR7240_REG_ATU 0x50
-+#define AR7240_ATU_FLUSH_ALL 0x1
-+
-+#define AR7240_REG_AT_CTRL 0x5c
-+#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
-+#define AR7240_AT_CTRL_AGE_EN BIT(17)
-+#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
-+#define AR7240_AT_CTRL_RESERVED BIT(19)
-+#define AR7240_AT_CTRL_ARP_EN BIT(20)
-+
-+#define AR7240_REG_TAG_PRIORITY 0x70
-+
-+#define AR7240_REG_SERVICE_TAG 0x74
-+#define AR7240_SERVICE_TAG_M BITM(16)
-+
-+#define AR7240_REG_CPU_PORT 0x78
-+#define AR7240_MIRROR_PORT_S 4
-+#define AR7240_CPU_PORT_EN BIT(8)
-+
-+#define AR7240_REG_MIB_FUNCTION0 0x80
-+#define AR7240_MIB_TIMER_M BITM(16)
-+#define AR7240_MIB_AT_HALF_EN BIT(16)
-+#define AR7240_MIB_BUSY BIT(17)
-+#define AR7240_MIB_FUNC_S 24
-+#define AR7240_MIB_FUNC_M BITM(3)
-+#define AR7240_MIB_FUNC_NO_OP 0x0
-+#define AR7240_MIB_FUNC_FLUSH 0x1
-+#define AR7240_MIB_FUNC_CAPTURE 0x3
-+
-+#define AR7240_REG_MDIO_CTRL 0x98
-+#define AR7240_MDIO_CTRL_DATA_M BITM(16)
-+#define AR7240_MDIO_CTRL_REG_ADDR_S 16
-+#define AR7240_MDIO_CTRL_PHY_ADDR_S 21
-+#define AR7240_MDIO_CTRL_CMD_WRITE 0
-+#define AR7240_MDIO_CTRL_CMD_READ BIT(27)
-+#define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
-+#define AR7240_MDIO_CTRL_BUSY BIT(31)
-+
-+#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
-+
-+#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
-+#define AR7240_PORT_STATUS_SPEED_S 0
-+#define AR7240_PORT_STATUS_SPEED_M BITM(2)
-+#define AR7240_PORT_STATUS_SPEED_10 0
-+#define AR7240_PORT_STATUS_SPEED_100 1
-+#define AR7240_PORT_STATUS_SPEED_1000 2
-+#define AR7240_PORT_STATUS_TXMAC BIT(2)
-+#define AR7240_PORT_STATUS_RXMAC BIT(3)
-+#define AR7240_PORT_STATUS_TXFLOW BIT(4)
-+#define AR7240_PORT_STATUS_RXFLOW BIT(5)
-+#define AR7240_PORT_STATUS_DUPLEX BIT(6)
-+#define AR7240_PORT_STATUS_LINK_UP BIT(8)
-+#define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
-+#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
-+
-+#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
-+#define AR7240_PORT_CTRL_STATE_M BITM(3)
-+#define AR7240_PORT_CTRL_STATE_DISABLED 0
-+#define AR7240_PORT_CTRL_STATE_BLOCK 1
-+#define AR7240_PORT_CTRL_STATE_LISTEN 2
-+#define AR7240_PORT_CTRL_STATE_LEARN 3
-+#define AR7240_PORT_CTRL_STATE_FORWARD 4
-+#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
-+#define AR7240_PORT_CTRL_VLAN_MODE_S 8
-+#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
-+#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
-+#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
-+#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
-+#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
-+#define AR7240_PORT_CTRL_HEADER BIT(11)
-+#define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
-+#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
-+#define AR7240_PORT_CTRL_LEARN BIT(14)
-+#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
-+#define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
-+#define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
-+
-+#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
-+
-+#define AR7240_PORT_VLAN_DEFAULT_ID_S 0
-+#define AR7240_PORT_VLAN_DEST_PORTS_S 16
-+#define AR7240_PORT_VLAN_MODE_S 30
-+#define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
-+#define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
-+#define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
-+#define AR7240_PORT_VLAN_MODE_SECURE 3
-+
-+
-+#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
-+
-+#define AR7240_STATS_RXBROAD 0x00
-+#define AR7240_STATS_RXPAUSE 0x04
-+#define AR7240_STATS_RXMULTI 0x08
-+#define AR7240_STATS_RXFCSERR 0x0c
-+#define AR7240_STATS_RXALIGNERR 0x10
-+#define AR7240_STATS_RXRUNT 0x14
-+#define AR7240_STATS_RXFRAGMENT 0x18
-+#define AR7240_STATS_RX64BYTE 0x1c
-+#define AR7240_STATS_RX128BYTE 0x20
-+#define AR7240_STATS_RX256BYTE 0x24
-+#define AR7240_STATS_RX512BYTE 0x28
-+#define AR7240_STATS_RX1024BYTE 0x2c
-+#define AR7240_STATS_RX1518BYTE 0x30
-+#define AR7240_STATS_RXMAXBYTE 0x34
-+#define AR7240_STATS_RXTOOLONG 0x38
-+#define AR7240_STATS_RXGOODBYTE 0x3c
-+#define AR7240_STATS_RXBADBYTE 0x44
-+#define AR7240_STATS_RXOVERFLOW 0x4c
-+#define AR7240_STATS_FILTERED 0x50
-+#define AR7240_STATS_TXBROAD 0x54
-+#define AR7240_STATS_TXPAUSE 0x58
-+#define AR7240_STATS_TXMULTI 0x5c
-+#define AR7240_STATS_TXUNDERRUN 0x60
-+#define AR7240_STATS_TX64BYTE 0x64
-+#define AR7240_STATS_TX128BYTE 0x68
-+#define AR7240_STATS_TX256BYTE 0x6c
-+#define AR7240_STATS_TX512BYTE 0x70
-+#define AR7240_STATS_TX1024BYTE 0x74
-+#define AR7240_STATS_TX1518BYTE 0x78
-+#define AR7240_STATS_TXMAXBYTE 0x7c
-+#define AR7240_STATS_TXOVERSIZE 0x80
-+#define AR7240_STATS_TXBYTE 0x84
-+#define AR7240_STATS_TXCOLLISION 0x8c
-+#define AR7240_STATS_TXABORTCOL 0x90
-+#define AR7240_STATS_TXMULTICOL 0x94
-+#define AR7240_STATS_TXSINGLECOL 0x98
-+#define AR7240_STATS_TXEXCDEFER 0x9c
-+#define AR7240_STATS_TXDEFER 0xa0
-+#define AR7240_STATS_TXLATECOL 0xa4
-+
-+#define AR7240_PORT_CPU 0
-+#define AR7240_NUM_PORTS 6
-+#define AR7240_NUM_PHYS 5
-+
-+#define AR7240_PHY_ID1 0x004d
-+#define AR7240_PHY_ID2 0xd041
-+
-+#define AR934X_PHY_ID1 0x004d
-+#define AR934X_PHY_ID2 0xd042
-+
-+#define AR7240_MAX_VLANS 16
-+
-+#define AR934X_REG_OPER_MODE0 0x04
-+#define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
-+#define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
-+
-+#define AR934X_REG_OPER_MODE1 0x08
-+#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
-+
-+#define AR934X_REG_FLOOD_MASK 0x2c
-+#define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
-+#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
-+
-+#define AR934X_REG_QM_CTRL 0x3c
-+#define AR934X_QM_CTRL_ARP_EN BIT(15)
-+
-+#define AR934X_REG_AT_CTRL 0x5c
-+#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
-+#define AR934X_AT_CTRL_AGE_EN BIT(17)
-+#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
-+
-+#define AR934X_MIB_ENABLE BIT(30)
-+
-+#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
-+
-+#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
-+#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
-+#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
-+#define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
-+#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
-+#define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
-+#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
-+#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
-+#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
-+
-+#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
-+#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
-+#define AR934X_PORT_VLAN2_8021Q_MODE_S 30
-+#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
-+#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
-+#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
-+#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
-+
-+#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
-+
-+struct ar7240sw_port_stat {
-+ unsigned long rx_broadcast;
-+ unsigned long rx_pause;
-+ unsigned long rx_multicast;
-+ unsigned long rx_fcs_error;
-+ unsigned long rx_align_error;
-+ unsigned long rx_runt;
-+ unsigned long rx_fragments;
-+ unsigned long rx_64byte;
-+ unsigned long rx_128byte;
-+ unsigned long rx_256byte;
-+ unsigned long rx_512byte;
-+ unsigned long rx_1024byte;
-+ unsigned long rx_1518byte;
-+ unsigned long rx_maxbyte;
-+ unsigned long rx_toolong;
-+ unsigned long rx_good_byte;
-+ unsigned long rx_bad_byte;
-+ unsigned long rx_overflow;
-+ unsigned long filtered;
-+
-+ unsigned long tx_broadcast;
-+ unsigned long tx_pause;
-+ unsigned long tx_multicast;
-+ unsigned long tx_underrun;
-+ unsigned long tx_64byte;
-+ unsigned long tx_128byte;
-+ unsigned long tx_256byte;
-+ unsigned long tx_512byte;
-+ unsigned long tx_1024byte;
-+ unsigned long tx_1518byte;
-+ unsigned long tx_maxbyte;
-+ unsigned long tx_oversize;
-+ unsigned long tx_byte;
-+ unsigned long tx_collision;
-+ unsigned long tx_abortcol;
-+ unsigned long tx_multicol;
-+ unsigned long tx_singlecol;
-+ unsigned long tx_excdefer;
-+ unsigned long tx_defer;
-+ unsigned long tx_xlatecol;
-+};
-+
-+struct ar7240sw {
-+ struct mii_bus *mii_bus;
-+ struct ag71xx_switch_platform_data *swdata;
-+ struct switch_dev swdev;
-+ int num_ports;
-+ u8 ver;
-+ bool vlan;
-+ u16 vlan_id[AR7240_MAX_VLANS];
-+ u8 vlan_table[AR7240_MAX_VLANS];
-+ u8 vlan_tagged;
-+ u16 pvid[AR7240_NUM_PORTS];
-+ char buf[80];
-+
-+ rwlock_t stats_lock;
-+ struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
-+};
-+
-+struct ar7240sw_hw_stat {
-+ char string[ETH_GSTRING_LEN];
-+ int sizeof_stat;
-+ int reg;
-+};
-+
-+static DEFINE_MUTEX(reg_mutex);
-+
-+static inline int sw_is_ar7240(struct ar7240sw *as)
-+{
-+ return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
-+}
-+
-+static inline int sw_is_ar934x(struct ar7240sw *as)
-+{
-+ return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
-+}
-+
-+static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
-+{
-+ return BIT(port);
-+}
-+
-+static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
-+{
-+ return BIT(as->swdev.ports) - 1;
-+}
-+
-+static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
-+{
-+ return ar7240sw_port_mask_all(as) & ~BIT(port);
-+}
-+
-+static inline u16 mk_phy_addr(u32 reg)
-+{
-+ return 0x17 & ((reg >> 4) | 0x10);
-+}
-+
-+static inline u16 mk_phy_reg(u32 reg)
-+{
-+ return (reg << 1) & 0x1e;
-+}
-+
-+static inline u16 mk_high_addr(u32 reg)
-+{
-+ return (reg >> 7) & 0x1ff;
-+}
-+
-+static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
-+{
-+ unsigned long flags;
-+ u16 phy_addr;
-+ u16 phy_reg;
-+ u32 hi, lo;
-+
-+ reg = (reg & 0xfffffffc) >> 2;
-+ phy_addr = mk_phy_addr(reg);
-+ phy_reg = mk_phy_reg(reg);
-+
-+ local_irq_save(flags);
-+ ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
-+ lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
-+ hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
-+ local_irq_restore(flags);
-+
-+ return (hi << 16) | lo;
-+}
-+
-+static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
-+{
-+ unsigned long flags;
-+ u16 phy_addr;
-+ u16 phy_reg;
-+
-+ reg = (reg & 0xfffffffc) >> 2;
-+ phy_addr = mk_phy_addr(reg);
-+ phy_reg = mk_phy_reg(reg);
-+
-+ local_irq_save(flags);
-+ ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
-+ ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
-+ ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
-+ local_irq_restore(flags);
-+}
-+
-+static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
-+{
-+ u32 ret;
-+
-+ mutex_lock(®_mutex);
-+ ret = __ar7240sw_reg_read(mii, reg_addr);
-+ mutex_unlock(®_mutex);
-+
-+ return ret;
-+}
-+
-+static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
-+{
-+ mutex_lock(®_mutex);
-+ __ar7240sw_reg_write(mii, reg_addr, reg_val);
-+ mutex_unlock(®_mutex);
-+}
-+
-+static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
-+{
-+ u32 t;
-+
-+ mutex_lock(®_mutex);
-+ t = __ar7240sw_reg_read(mii, reg);
-+ t &= ~mask;
-+ t |= val;
-+ __ar7240sw_reg_write(mii, reg, t);
-+ mutex_unlock(®_mutex);
-+
-+ return t;
-+}
-+
-+static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
-+{
-+ u32 t;
-+
-+ mutex_lock(®_mutex);
-+ t = __ar7240sw_reg_read(mii, reg);
-+ t |= val;
-+ __ar7240sw_reg_write(mii, reg, t);
-+ mutex_unlock(®_mutex);
-+}
-+
-+static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
-+ unsigned timeout)
-+{
-+ int i;
-+
-+ for (i = 0; i < timeout; i++) {
-+ u32 t;
-+
-+ t = __ar7240sw_reg_read(mii, reg);
-+ if ((t & mask) == val)
-+ return 0;
-+
-+ msleep(1);
-+ }
-+
-+ return -ETIMEDOUT;
-+}
-+
-+static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
-+ unsigned timeout)
-+{
-+ int ret;
-+
-+ mutex_lock(®_mutex);
-+ ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
-+ mutex_unlock(®_mutex);
-+ return ret;
-+}
-+
-+u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
-+ unsigned reg_addr)
-+{
-+ u32 t, val = 0xffff;
-+ int err;
-+
-+ if (phy_addr >= AR7240_NUM_PHYS)
-+ return 0xffff;
-+
-+ mutex_lock(®_mutex);
-+ t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
-+ (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
-+ AR7240_MDIO_CTRL_MASTER_EN |
-+ AR7240_MDIO_CTRL_BUSY |
-+ AR7240_MDIO_CTRL_CMD_READ;
-+
-+ __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
-+ err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
-+ AR7240_MDIO_CTRL_BUSY, 0, 5);
-+ if (!err)
-+ val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
-+ mutex_unlock(®_mutex);
-+
-+ return val & AR7240_MDIO_CTRL_DATA_M;
-+}
-+
-+int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
-+ unsigned reg_addr, u16 reg_val)
-+{
-+ u32 t;
-+ int ret;
-+
-+ if (phy_addr >= AR7240_NUM_PHYS)
-+ return -EINVAL;
-+
-+ mutex_lock(®_mutex);
-+ t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
-+ (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
-+ AR7240_MDIO_CTRL_MASTER_EN |
-+ AR7240_MDIO_CTRL_BUSY |
-+ AR7240_MDIO_CTRL_CMD_WRITE |
-+ reg_val;
-+
-+ __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
-+ ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
-+ AR7240_MDIO_CTRL_BUSY, 0, 5);
-+ mutex_unlock(®_mutex);
-+
-+ return ret;
-+}
-+
-+static int ar7240sw_capture_stats(struct ar7240sw *as)
-+{
-+ struct mii_bus *mii = as->mii_bus;
-+ int port;
-+ int ret;
-+
-+ write_lock(&as->stats_lock);
-+
-+ /* Capture the hardware statistics for all ports */
-+ ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0,
-+ (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S),
-+ (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
-+
-+ /* Wait for the capturing to complete. */
-+ ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
-+ AR7240_MIB_BUSY, 0, 10);
-+
-+ if (ret)
-+ goto unlock;
-+
-+ for (port = 0; port < AR7240_NUM_PORTS; port++) {
-+ unsigned int base;
-+ struct ar7240sw_port_stat *stats;
-+
-+ base = AR7240_REG_STATS_BASE(port);
-+ stats = &as->port_stats[port];
-+
-+#define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
-+
-+ stats->rx_good_byte += READ_STAT(RXGOODBYTE);
-+ stats->tx_byte += READ_STAT(TXBYTE);
-+
-+#undef READ_STAT
-+ }
-+
-+ ret = 0;
-+
-+unlock:
-+ write_unlock(&as->stats_lock);
-+ return ret;
-+}
-+
-+static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
-+{
-+ ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
-+ AR7240_PORT_CTRL_STATE_DISABLED);
-+}
-+
-+static void ar7240sw_setup(struct ar7240sw *as)
-+{
-+ struct mii_bus *mii = as->mii_bus;
-+
-+ /* Enable CPU port, and disable mirror port */
-+ ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
-+ AR7240_CPU_PORT_EN |
-+ (15 << AR7240_MIRROR_PORT_S));
-+
-+ /* Setup TAG priority mapping */
-+ ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
-+
-+ if (sw_is_ar934x(as)) {
-+ /* Enable aging, MAC replacing */
-+ ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
-+ 0x2b /* 5 min age time */ |
-+ AR934X_AT_CTRL_AGE_EN |
-+ AR934X_AT_CTRL_LEARN_CHANGE);
-+ /* Enable ARP frame acknowledge */
-+ ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
-+ AR934X_QM_CTRL_ARP_EN);
-+ /* Enable Broadcast/Multicast frames transmitted to the CPU */
-+ ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
-+ AR934X_FLOOD_MASK_BC_DP(0) |
-+ AR934X_FLOOD_MASK_MC_DP(0));
-+
-+ /* setup MTU */
-+ ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
-+ AR9340_GLOBAL_CTRL_MTU_M,
-+ AR9340_GLOBAL_CTRL_MTU_M);
-+
-+ /* Enable MIB counters */
-+ ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
-+ AR934X_MIB_ENABLE);
-+
-+ } else {
-+ /* Enable ARP frame acknowledge, aging, MAC replacing */
-+ ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
-+ AR7240_AT_CTRL_RESERVED |
-+ 0x2b /* 5 min age time */ |
-+ AR7240_AT_CTRL_AGE_EN |
-+ AR7240_AT_CTRL_ARP_EN |
-+ AR7240_AT_CTRL_LEARN_CHANGE);
-+ /* Enable Broadcast frames transmitted to the CPU */
-+ ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
-+ AR7240_FLOOD_MASK_BROAD_TO_CPU);
-+
-+ /* setup MTU */
-+ ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
-+ AR7240_GLOBAL_CTRL_MTU_M,
-+ AR7240_GLOBAL_CTRL_MTU_M);
-+ }
-+
-+ /* setup Service TAG */
-+ ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
-+}
-+
-+static int ar7240sw_reset(struct ar7240sw *as)
-+{
-+ struct mii_bus *mii = as->mii_bus;
-+ int ret;
-+ int i;
-+
-+ /* Set all ports to disabled state. */
-+ for (i = 0; i < AR7240_NUM_PORTS; i++)
-+ ar7240sw_disable_port(as, i);
-+
-+ /* Wait for transmit queues to drain. */
-+ msleep(2);
-+
-+ /* Reset the switch. */
-+ ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
-+ AR7240_MASK_CTRL_SOFT_RESET);
-+
-+ ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
-+ AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
-+
-+ /* setup PHYs */
-+ for (i = 0; i < AR7240_NUM_PHYS; i++) {
-+ ar7240sw_phy_write(mii, i, MII_ADVERTISE,
-+ ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
-+ ADVERTISE_PAUSE_ASYM);
-+ ar7240sw_phy_write(mii, i, MII_BMCR,
-+ BMCR_RESET | BMCR_ANENABLE);
-+ }
-+ msleep(1000);
-+
-+ ar7240sw_setup(as);
-+ return ret;
-+}
-+
-+static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
-+{
-+ struct mii_bus *mii = as->mii_bus;
-+ u32 ctrl;
-+ u32 vid, mode;
-+
-+ ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
-+ AR7240_PORT_CTRL_SINGLE_VLAN;
-+
-+ if (port == AR7240_PORT_CPU) {
-+ ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
-+ AR7240_PORT_STATUS_SPEED_1000 |
-+ AR7240_PORT_STATUS_TXFLOW |
-+ AR7240_PORT_STATUS_RXFLOW |
-+ AR7240_PORT_STATUS_TXMAC |
-+ AR7240_PORT_STATUS_RXMAC |
-+ AR7240_PORT_STATUS_DUPLEX);
-+ } else {
-+ ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
-+ AR7240_PORT_STATUS_LINK_AUTO);
-+ }
-+
-+ /* Set the default VID for this port */
-+ if (as->vlan) {
-+ vid = as->vlan_id[as->pvid[port]];
-+ mode = AR7240_PORT_VLAN_MODE_SECURE;
-+ } else {
-+ vid = port;
-+ mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
-+ }
-+
-+ if (as->vlan) {
-+ if (as->vlan_tagged & BIT(port))
-+ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
-+ AR7240_PORT_CTRL_VLAN_MODE_S;
-+ else
-+ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
-+ AR7240_PORT_CTRL_VLAN_MODE_S;
-+ } else {
-+ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP <<
-+ AR7240_PORT_CTRL_VLAN_MODE_S;
-+ }
-+
-+ if (!portmask) {
-+ if (port == AR7240_PORT_CPU)
-+ portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
-+ else
-+ portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
-+ }
-+
-+ /* allow the port to talk to all other ports, but exclude its
-+ * own ID to prevent frames from being reflected back to the
-+ * port that they came from */
-+ portmask &= ar7240sw_port_mask_but(as, port);
-+
-+ ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
-+ if (sw_is_ar934x(as)) {
-+ u32 vlan1, vlan2;
-+
-+ vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
-+ vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
-+ (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
-+ ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
-+ ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
-+ } else {
-+ u32 vlan;
-+
-+ vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
-+ (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
-+
-+ ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
-+ }
-+}
-+
-+static int ar7240_set_addr(stru