From da5c3b1c8535d8f8455b5283ddaf5c38b45d477e Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Thu, 10 Nov 2011 19:02:53 +0100 Subject: update to latest stable kernels --- target/linux/patches/2.6.39.4/arm-statcmd.patch | 12 + .../linux/patches/2.6.39.4/bsd-compatibility.patch | 2512 + target/linux/patches/2.6.39.4/cris-etrax.patch | 12 + .../linux/patches/2.6.39.4/cris-thread-macro.patch | 12 + target/linux/patches/2.6.39.4/cris.patch | 5739 ++ target/linux/patches/2.6.39.4/defaults.patch | 26 + target/linux/patches/2.6.39.4/fon2100.patch | 6279 ++ target/linux/patches/2.6.39.4/gemalto.patch | 11 + target/linux/patches/2.6.39.4/mips-malta.patch | 135 + target/linux/patches/2.6.39.4/mmc-host.patch | 36 + target/linux/patches/2.6.39.4/non-static.patch | 33 + target/linux/patches/2.6.39.4/ocf-20100325.patch | 90176 +++++++++++++++++ target/linux/patches/2.6.39.4/rb4xx.patch | 25253 +++++ target/linux/patches/2.6.39.4/sparc-include.patch | 11 + target/linux/patches/2.6.39.4/startup.patch | 20 + .../linux/patches/2.6.39.4/usb-defaults-off.patch | 32 + target/linux/patches/2.6.39.4/uuid.patch | 255 + .../patches/2.6.39.4/vga-cons-default-off.patch | 12 + target/linux/patches/2.6.39.4/wlan-cf.patch | 11 + target/linux/patches/2.6.39.4/x86-build.patch | 11 + target/linux/patches/2.6.39.4/zlib-inflate.patch | 12 + target/linux/patches/3.0.8/bsd-compatibility.patch | 2512 + target/linux/patches/3.0.8/cris-etrax.patch | 12 + target/linux/patches/3.0.8/defaults.patch | 22 + target/linux/patches/3.0.8/fon2100.patch | 6279 ++ target/linux/patches/3.0.8/gemalto.patch | 11 + target/linux/patches/3.0.8/mips-malta.patch | 135 + target/linux/patches/3.0.8/mmc-host.patch | 36 + target/linux/patches/3.0.8/non-static.patch | 33 + target/linux/patches/3.0.8/ocf-20110720.patch | 99170 +++++++++++++++++++ target/linux/patches/3.0.8/sparc-include.patch | 11 + target/linux/patches/3.0.8/startup.patch | 20 + target/linux/patches/3.0.8/usb-defaults-off.patch | 32 + target/linux/patches/3.0.8/uuid.patch | 255 + .../linux/patches/3.0.8/vga-cons-default-off.patch | 12 + target/linux/patches/3.0.8/wlan-cf.patch | 11 + target/linux/patches/3.0.8/x86-build.patch | 11 + target/linux/patches/3.0.8/zlib-inflate.patch | 12 + 38 files changed, 239174 insertions(+) create mode 100644 target/linux/patches/2.6.39.4/arm-statcmd.patch create mode 100644 target/linux/patches/2.6.39.4/bsd-compatibility.patch create mode 100644 target/linux/patches/2.6.39.4/cris-etrax.patch create mode 100644 target/linux/patches/2.6.39.4/cris-thread-macro.patch create mode 100644 target/linux/patches/2.6.39.4/cris.patch create mode 100644 target/linux/patches/2.6.39.4/defaults.patch create mode 100644 target/linux/patches/2.6.39.4/fon2100.patch create mode 100644 target/linux/patches/2.6.39.4/gemalto.patch create mode 100644 target/linux/patches/2.6.39.4/mips-malta.patch create mode 100644 target/linux/patches/2.6.39.4/mmc-host.patch create mode 100644 target/linux/patches/2.6.39.4/non-static.patch create mode 100644 target/linux/patches/2.6.39.4/ocf-20100325.patch create mode 100644 target/linux/patches/2.6.39.4/rb4xx.patch create mode 100644 target/linux/patches/2.6.39.4/sparc-include.patch create mode 100644 target/linux/patches/2.6.39.4/startup.patch create mode 100644 target/linux/patches/2.6.39.4/usb-defaults-off.patch create mode 100644 target/linux/patches/2.6.39.4/uuid.patch create mode 100644 target/linux/patches/2.6.39.4/vga-cons-default-off.patch create mode 100644 target/linux/patches/2.6.39.4/wlan-cf.patch create mode 100644 target/linux/patches/2.6.39.4/x86-build.patch create mode 100644 target/linux/patches/2.6.39.4/zlib-inflate.patch create mode 100644 target/linux/patches/3.0.8/bsd-compatibility.patch create mode 100644 target/linux/patches/3.0.8/cris-etrax.patch create mode 100644 target/linux/patches/3.0.8/defaults.patch create mode 100644 target/linux/patches/3.0.8/fon2100.patch create mode 100644 target/linux/patches/3.0.8/gemalto.patch create mode 100644 target/linux/patches/3.0.8/mips-malta.patch create mode 100644 target/linux/patches/3.0.8/mmc-host.patch create mode 100644 target/linux/patches/3.0.8/non-static.patch create mode 100644 target/linux/patches/3.0.8/ocf-20110720.patch create mode 100644 target/linux/patches/3.0.8/sparc-include.patch create mode 100644 target/linux/patches/3.0.8/startup.patch create mode 100644 target/linux/patches/3.0.8/usb-defaults-off.patch create mode 100644 target/linux/patches/3.0.8/uuid.patch create mode 100644 target/linux/patches/3.0.8/vga-cons-default-off.patch create mode 100644 target/linux/patches/3.0.8/wlan-cf.patch create mode 100644 target/linux/patches/3.0.8/x86-build.patch create mode 100644 target/linux/patches/3.0.8/zlib-inflate.patch (limited to 'target/linux/patches') diff --git a/target/linux/patches/2.6.39.4/arm-statcmd.patch b/target/linux/patches/2.6.39.4/arm-statcmd.patch new file mode 100644 index 000000000..3aed60cbc --- /dev/null +++ b/target/linux/patches/2.6.39.4/arm-statcmd.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.39-rc6.orig/arch/arm/boot/compressed/Makefile linux-2.6.39-rc6/arch/arm/boot/compressed/Makefile +--- linux-2.6.39-rc6.orig/arch/arm/boot/compressed/Makefile 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/arch/arm/boot/compressed/Makefile 2011-05-10 10:35:34.000000000 +0200 +@@ -99,7 +99,7 @@ + asflags-y := -Wa,-march=all + + # Provide size of uncompressed kernel to the decompressor via a linker symbol. +-LDFLAGS_vmlinux = --defsym _image_size=$(shell stat -c "%s" $(obj)/../Image) ++LDFLAGS_vmlinux = --defsym _image_size=$(shell if stat -qs .>/dev/null 2>&1;then statcmd='stat -f %z';else statcmd='stat -c %s';fi; $$statcmd "%s" $(obj)/../Image) + # Supply ZRELADDR to the decompressor via a linker symbol. + ifneq ($(CONFIG_AUTO_ZRELADDR),y) + LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR) diff --git a/target/linux/patches/2.6.39.4/bsd-compatibility.patch b/target/linux/patches/2.6.39.4/bsd-compatibility.patch new file mode 100644 index 000000000..9e91a62de --- /dev/null +++ b/target/linux/patches/2.6.39.4/bsd-compatibility.patch @@ -0,0 +1,2512 @@ +diff -Nur linux-2.6.36.orig/scripts/Makefile.lib linux-2.6.36/scripts/Makefile.lib +--- linux-2.6.36.orig/scripts/Makefile.lib 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/Makefile.lib 2010-11-28 18:34:22.000000000 +0100 +@@ -216,7 +216,12 @@ + size_append = printf $(shell \ + dec_size=0; \ + for F in $1; do \ +- fsize=$$(stat -c "%s" $$F); \ ++ if stat -qs .>/dev/null 2>&1; then \ ++ statcmd='stat -f %z'; \ ++ else \ ++ statcmd='stat -c %s'; \ ++ fi; \ ++ fsize=$$($$statcmd $$F); \ + dec_size=$$(expr $$dec_size + $$fsize); \ + done; \ + printf "%08x\n" $$dec_size | \ +diff -Nur linux-2.6.36.orig/scripts/mod/mk_elfconfig.c linux-2.6.36/scripts/mod/mk_elfconfig.c +--- linux-2.6.36.orig/scripts/mod/mk_elfconfig.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/mod/mk_elfconfig.c 2010-11-28 18:33:24.000000000 +0100 +@@ -1,7 +1,18 @@ + #include + #include + #include +-#include ++ ++#define EI_NIDENT (16) ++#define ELFMAG "\177ELF" ++ ++#define SELFMAG 4 ++#define EI_CLASS 4 ++#define ELFCLASS32 1 /* 32-bit objects */ ++#define ELFCLASS64 2 /* 64-bit objects */ ++ ++#define EI_DATA 5 /* Data encoding byte index */ ++#define ELFDATA2LSB 1 /* 2's complement, little endian */ ++#define ELFDATA2MSB 2 /* 2's complement, big endian */ + + int + main(int argc, char **argv) +diff -Nur linux-2.6.36.orig/scripts/mod/modpost.h linux-2.6.36/scripts/mod/modpost.h +--- linux-2.6.36.orig/scripts/mod/modpost.h 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/mod/modpost.h 2010-11-28 18:33:24.000000000 +0100 +@@ -7,7 +7,2453 @@ + #include + #include + #include +-#include ++ ++ ++/* This file defines standard ELF types, structures, and macros. ++ Copyright (C) 1995-1999,2000,2001,2002,2003 Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, write to the Free ++ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA ++ 02111-1307 USA. */ ++ ++#ifndef _ELF_H ++#define _ELF_H 1 ++ ++__BEGIN_DECLS ++ ++/* Standard ELF types. */ ++ ++#include ++ ++/* Type for a 16-bit quantity. */ ++typedef uint16_t Elf32_Half; ++typedef uint16_t Elf64_Half; ++ ++/* Types for signed and unsigned 32-bit quantities. */ ++typedef uint32_t Elf32_Word; ++typedef int32_t Elf32_Sword; ++typedef uint32_t Elf64_Word; ++typedef int32_t Elf64_Sword; ++ ++/* Types for signed and unsigned 64-bit quantities. */ ++typedef uint64_t Elf32_Xword; ++typedef int64_t Elf32_Sxword; ++typedef uint64_t Elf64_Xword; ++typedef int64_t Elf64_Sxword; ++ ++/* Type of addresses. */ ++typedef uint32_t Elf32_Addr; ++typedef uint64_t Elf64_Addr; ++ ++/* Type of file offsets. */ ++typedef uint32_t Elf32_Off; ++typedef uint64_t Elf64_Off; ++ ++/* Type for section indices, which are 16-bit quantities. */ ++typedef uint16_t Elf32_Section; ++typedef uint16_t Elf64_Section; ++ ++/* Type for version symbol information. */ ++typedef Elf32_Half Elf32_Versym; ++typedef Elf64_Half Elf64_Versym; ++ ++ ++/* The ELF file header. This appears at the start of every ELF file. */ ++ ++#define EI_NIDENT (16) ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf32_Half e_type; /* Object file type */ ++ Elf32_Half e_machine; /* Architecture */ ++ Elf32_Word e_version; /* Object file version */ ++ Elf32_Addr e_entry; /* Entry point virtual address */ ++ Elf32_Off e_phoff; /* Program header table file offset */ ++ Elf32_Off e_shoff; /* Section header table file offset */ ++ Elf32_Word e_flags; /* Processor-specific flags */ ++ Elf32_Half e_ehsize; /* ELF header size in bytes */ ++ Elf32_Half e_phentsize; /* Program header table entry size */ ++ Elf32_Half e_phnum; /* Program header table entry count */ ++ Elf32_Half e_shentsize; /* Section header table entry size */ ++ Elf32_Half e_shnum; /* Section header table entry count */ ++ Elf32_Half e_shstrndx; /* Section header string table index */ ++} Elf32_Ehdr; ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf64_Half e_type; /* Object file type */ ++ Elf64_Half e_machine; /* Architecture */ ++ Elf64_Word e_version; /* Object file version */ ++ Elf64_Addr e_entry; /* Entry point virtual address */ ++ Elf64_Off e_phoff; /* Program header table file offset */ ++ Elf64_Off e_shoff; /* Section header table file offset */ ++ Elf64_Word e_flags; /* Processor-specific flags */ ++ Elf64_Half e_ehsize; /* ELF header size in bytes */ ++ Elf64_Half e_phentsize; /* Program header table entry size */ ++ Elf64_Half e_phnum; /* Program header table entry count */ ++ Elf64_Half e_shentsize; /* Section header table entry size */ ++ Elf64_Half e_shnum; /* Section header table entry count */ ++ Elf64_Half e_shstrndx; /* Section header string table index */ ++} Elf64_Ehdr; ++ ++/* Fields in the e_ident array. The EI_* macros are indices into the ++ array. The macros under each EI_* macro are the values the byte ++ may have. */ ++ ++#define EI_MAG0 0 /* File identification byte 0 index */ ++#define ELFMAG0 0x7f /* Magic number byte 0 */ ++ ++#define EI_MAG1 1 /* File identification byte 1 index */ ++#define ELFMAG1 'E' /* Magic number byte 1 */ ++ ++#define EI_MAG2 2 /* File identification byte 2 index */ ++#define ELFMAG2 'L' /* Magic number byte 2 */ ++ ++#define EI_MAG3 3 /* File identification byte 3 index */ ++#define ELFMAG3 'F' /* Magic number byte 3 */ ++ ++/* Conglomeration of the identification bytes, for easy testing as a word. */ ++#define ELFMAG "\177ELF" ++#define SELFMAG 4 ++ ++#define EI_CLASS 4 /* File class byte index */ ++#define ELFCLASSNONE 0 /* Invalid class */ ++#define ELFCLASS32 1 /* 32-bit objects */ ++#define ELFCLASS64 2 /* 64-bit objects */ ++#define ELFCLASSNUM 3 ++ ++#define EI_DATA 5 /* Data encoding byte index */ ++#define ELFDATANONE 0 /* Invalid data encoding */ ++#define ELFDATA2LSB 1 /* 2's complement, little endian */ ++#define ELFDATA2MSB 2 /* 2's complement, big endian */ ++#define ELFDATANUM 3 ++ ++#define EI_VERSION 6 /* File version byte index */ ++ /* Value must be EV_CURRENT */ ++ ++#define EI_OSABI 7 /* OS ABI identification */ ++#define ELFOSABI_NONE 0 /* UNIX System V ABI */ ++#define ELFOSABI_SYSV 0 /* Alias. */ ++#define ELFOSABI_HPUX 1 /* HP-UX */ ++#define ELFOSABI_NETBSD 2 /* NetBSD. */ ++#define ELFOSABI_LINUX 3 /* Linux. */ ++#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ ++#define ELFOSABI_AIX 7 /* IBM AIX. */ ++#define ELFOSABI_IRIX 8 /* SGI Irix. */ ++#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ ++#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ ++#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ ++#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ ++#define ELFOSABI_ARM 97 /* ARM */ ++#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ ++ ++#define EI_ABIVERSION 8 /* ABI version */ ++ ++#define EI_PAD 9 /* Byte index of padding bytes */ ++ ++/* Legal values for e_type (object file type). */ ++ ++#define ET_NONE 0 /* No file type */ ++#define ET_REL 1 /* Relocatable file */ ++#define ET_EXEC 2 /* Executable file */ ++#define ET_DYN 3 /* Shared object file */ ++#define ET_CORE 4 /* Core file */ ++#define ET_NUM 5 /* Number of defined types */ ++#define ET_LOOS 0xfe00 /* OS-specific range start */ ++#define ET_HIOS 0xfeff /* OS-specific range end */ ++#define ET_LOPROC 0xff00 /* Processor-specific range start */ ++#define ET_HIPROC 0xffff /* Processor-specific range end */ ++ ++/* Legal values for e_machine (architecture). */ ++ ++#define EM_NONE 0 /* No machine */ ++#define EM_M32 1 /* AT&T WE 32100 */ ++#define EM_SPARC 2 /* SUN SPARC */ ++#define EM_386 3 /* Intel 80386 */ ++#define EM_68K 4 /* Motorola m68k family */ ++#define EM_88K 5 /* Motorola m88k family */ ++#define EM_860 7 /* Intel 80860 */ ++#define EM_MIPS 8 /* MIPS R3000 big-endian */ ++#define EM_S370 9 /* IBM System/370 */ ++#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ ++ ++#define EM_PARISC 15 /* HPPA */ ++#define EM_VPP500 17 /* Fujitsu VPP500 */ ++#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ ++#define EM_960 19 /* Intel 80960 */ ++#define EM_PPC 20 /* PowerPC */ ++#define EM_PPC64 21 /* PowerPC 64-bit */ ++#define EM_S390 22 /* IBM S390 */ ++ ++#define EM_V800 36 /* NEC V800 series */ ++#define EM_FR20 37 /* Fujitsu FR20 */ ++#define EM_RH32 38 /* TRW RH-32 */ ++#define EM_RCE 39 /* Motorola RCE */ ++#define EM_ARM 40 /* ARM */ ++#define EM_FAKE_ALPHA 41 /* Digital Alpha */ ++#define EM_SH 42 /* Hitachi SH */ ++#define EM_SPARCV9 43 /* SPARC v9 64-bit */ ++#define EM_TRICORE 44 /* Siemens Tricore */ ++#define EM_ARC 45 /* Argonaut RISC Core */ ++#define EM_H8_300 46 /* Hitachi H8/300 */ ++#define EM_H8_300H 47 /* Hitachi H8/300H */ ++#define EM_H8S 48 /* Hitachi H8S */ ++#define EM_H8_500 49 /* Hitachi H8/500 */ ++#define EM_IA_64 50 /* Intel Merced */ ++#define EM_MIPS_X 51 /* Stanford MIPS-X */ ++#define EM_COLDFIRE 52 /* Motorola Coldfire */ ++#define EM_68HC12 53 /* Motorola M68HC12 */ ++#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ ++#define EM_PCP 55 /* Siemens PCP */ ++#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ ++#define EM_NDR1 57 /* Denso NDR1 microprocessor */ ++#define EM_STARCORE 58 /* Motorola Start*Core processor */ ++#define EM_ME16 59 /* Toyota ME16 processor */ ++#define EM_ST100 60 /* STMicroelectronic ST100 processor */ ++#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ ++#define EM_X86_64 62 /* AMD x86-64 architecture */ ++#define EM_PDSP 63 /* Sony DSP Processor */ ++ ++#define EM_FX66 66 /* Siemens FX66 microcontroller */ ++#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ ++#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ ++#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ ++#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ ++#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ ++#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ ++#define EM_SVX 73 /* Silicon Graphics SVx */ ++#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ ++#define EM_VAX 75 /* Digital VAX */ ++#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ ++#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ ++#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ ++#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ ++#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ ++#define EM_HUANY 81 /* Harvard University machine-independent object files */ ++#define EM_PRISM 82 /* SiTera Prism */ ++#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ ++#define EM_FR30 84 /* Fujitsu FR30 */ ++#define EM_D10V 85 /* Mitsubishi D10V */ ++#define EM_D30V 86 /* Mitsubishi D30V */ ++#define EM_V850 87 /* NEC v850 */ ++#define EM_M32R 88 /* Mitsubishi M32R */ ++#define EM_MN10300 89 /* Matsushita MN10300 */ ++#define EM_MN10200 90 /* Matsushita MN10200 */ ++#define EM_PJ 91 /* picoJava */ ++#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ ++#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ ++#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ ++#define EM_NUM 95 ++ ++/* If it is necessary to assign new unofficial EM_* values, please ++ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the ++ chances of collision with official or non-GNU unofficial values. */ ++ ++#define EM_ALPHA 0x9026 ++ ++/* Legal values for e_version (version). */ ++ ++#define EV_NONE 0 /* Invalid ELF version */ ++#define EV_CURRENT 1 /* Current version */ ++#define EV_NUM 2 ++ ++/* Section header. */ ++ ++typedef struct ++{ ++ Elf32_Word sh_name; /* Section name (string tbl index) */ ++ Elf32_Word sh_type; /* Section type */ ++ Elf32_Word sh_flags; /* Section flags */ ++ Elf32_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf32_Off sh_offset; /* Section file offset */ ++ Elf32_Word sh_size; /* Section size in bytes */ ++ Elf32_Word sh_link; /* Link to another section */ ++ Elf32_Word sh_info; /* Additional section information */ ++ Elf32_Word sh_addralign; /* Section alignment */ ++ Elf32_Word sh_entsize; /* Entry size if section holds table */ ++} Elf32_Shdr; ++ ++typedef struct ++{ ++ Elf64_Word sh_name; /* Section name (string tbl index) */ ++ Elf64_Word sh_type; /* Section type */ ++ Elf64_Xword sh_flags; /* Section flags */ ++ Elf64_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf64_Off sh_offset; /* Section file offset */ ++ Elf64_Xword sh_size; /* Section size in bytes */ ++ Elf64_Word sh_link; /* Link to another section */ ++ Elf64_Word sh_info; /* Additional section information */ ++ Elf64_Xword sh_addralign; /* Section alignment */ ++ Elf64_Xword sh_entsize; /* Entry size if section holds table */ ++} Elf64_Shdr; ++ ++/* Special section indices. */ ++ ++#define SHN_UNDEF 0 /* Undefined section */ ++#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ ++#define SHN_LOPROC 0xff00 /* Start of processor-specific */ ++#define SHN_HIPROC 0xff1f /* End of processor-specific */ ++#define SHN_LOOS 0xff20 /* Start of OS-specific */ ++#define SHN_HIOS 0xff3f /* End of OS-specific */ ++#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ ++#define SHN_COMMON 0xfff2 /* Associated symbol is common */ ++#define SHN_XINDEX 0xffff /* Index is in extra table. */ ++#define SHN_HIRESERVE 0xffff /* End of reserved indices */ ++ ++/* Legal values for sh_type (section type). */ ++ ++#define SHT_NULL 0 /* Section header table entry unused */ ++#define SHT_PROGBITS 1 /* Program data */ ++#define SHT_SYMTAB 2 /* Symbol table */ ++#define SHT_STRTAB 3 /* String table */ ++#define SHT_RELA 4 /* Relocation entries with addends */ ++#define SHT_HASH 5 /* Symbol hash table */ ++#define SHT_DYNAMIC 6 /* Dynamic linking information */ ++#define SHT_NOTE 7 /* Notes */ ++#define SHT_NOBITS 8 /* Program space with no data (bss) */ ++#define SHT_REL 9 /* Relocation entries, no addends */ ++#define SHT_SHLIB 10 /* Reserved */ ++#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ ++#define SHT_INIT_ARRAY 14 /* Array of constructors */ ++#define SHT_FINI_ARRAY 15 /* Array of destructors */ ++#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ ++#define SHT_GROUP 17 /* Section group */ ++#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ ++#define SHT_NUM 19 /* Number of defined types. */ ++#define SHT_LOOS 0x60000000 /* Start OS-specific */ ++#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ ++#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ ++#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ ++#define SHT_SUNW_move 0x6ffffffa ++#define SHT_SUNW_COMDAT 0x6ffffffb ++#define SHT_SUNW_syminfo 0x6ffffffc ++#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ ++#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ ++#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ ++#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ ++#define SHT_HIOS 0x6fffffff /* End OS-specific type */ ++#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define SHT_LOUSER 0x80000000 /* Start of application-specific */ ++#define SHT_HIUSER 0x8fffffff /* End of application-specific */ ++ ++/* Legal values for sh_flags (section flags). */ ++ ++#define SHF_WRITE (1 << 0) /* Writable */ ++#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ ++#define SHF_EXECINSTR (1 << 2) /* Executable */ ++#define SHF_MERGE (1 << 4) /* Might be merged */ ++#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ ++#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ ++#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ ++#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling ++ required */ ++#define SHF_GROUP (1 << 9) /* Section is member of a group. */ ++#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ ++#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ ++#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ ++ ++/* Section group handling. */ ++#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ ++ ++/* Symbol table entry. */ ++ ++typedef struct ++{ ++ Elf32_Word st_name; /* Symbol name (string tbl index) */ ++ Elf32_Addr st_value; /* Symbol value */ ++ Elf32_Word st_size; /* Symbol size */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf32_Section st_shndx; /* Section index */ ++} Elf32_Sym; ++ ++typedef struct ++{ ++ Elf64_Word st_name; /* Symbol name (string tbl index) */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf64_Section st_shndx; /* Section index */ ++ Elf64_Addr st_value; /* Symbol value */ ++ Elf64_Xword st_size; /* Symbol size */ ++} Elf64_Sym; ++ ++/* The syminfo section if available contains additional information about ++ every dynamic symbol. */ ++ ++typedef struct ++{ ++ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf32_Half si_flags; /* Per symbol flags */ ++} Elf32_Syminfo; ++ ++typedef struct ++{ ++ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf64_Half si_flags; /* Per symbol flags */ ++} Elf64_Syminfo; ++ ++/* Possible values for si_boundto. */ ++#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ ++#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ ++#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ ++ ++/* Possible bitmasks for si_flags. */ ++#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ ++#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ ++#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ ++#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy ++ loaded */ ++/* Syminfo version values. */ ++#define SYMINFO_NONE 0 ++#define SYMINFO_CURRENT 1 ++#define SYMINFO_NUM 2 ++ ++ ++/* How to extract and insert information held in the st_info field. */ ++ ++#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) ++#define ELF32_ST_TYPE(val) ((val) & 0xf) ++#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) ++ ++/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ ++#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) ++#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) ++#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) ++ ++/* Legal values for ST_BIND subfield of st_info (symbol binding). */ ++ ++#define STB_LOCAL 0 /* Local symbol */ ++#define STB_GLOBAL 1 /* Global symbol */ ++#define STB_WEAK 2 /* Weak symbol */ ++#define STB_NUM 3 /* Number of defined types. */ ++#define STB_LOOS 10 /* Start of OS-specific */ ++#define STB_HIOS 12 /* End of OS-specific */ ++#define STB_LOPROC 13 /* Start of processor-specific */ ++#define STB_HIPROC 15 /* End of processor-specific */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_NOTYPE 0 /* Symbol type is unspecified */ ++#define STT_OBJECT 1 /* Symbol is a data object */ ++#define STT_FUNC 2 /* Symbol is a code object */ ++#define STT_SECTION 3 /* Symbol associated with a section */ ++#define STT_FILE 4 /* Symbol's name is file name */ ++#define STT_COMMON 5 /* Symbol is a common data object */ ++#define STT_TLS 6 /* Symbol is thread-local data object*/ ++#define STT_NUM 7 /* Number of defined types. */ ++#define STT_LOOS 10 /* Start of OS-specific */ ++#define STT_HIOS 12 /* End of OS-specific */ ++#define STT_LOPROC 13 /* Start of processor-specific */ ++#define STT_HIPROC 15 /* End of processor-specific */ ++ ++ ++/* Symbol table indices are found in the hash buckets and chain table ++ of a symbol hash table section. This special index value indicates ++ the end of a chain, meaning no further symbols are found in that bucket. */ ++ ++#define STN_UNDEF 0 /* End of a chain. */ ++ ++ ++/* How to extract and insert information held in the st_other field. */ ++ ++#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) ++ ++/* For ELF64 the definitions are the same. */ ++#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) ++ ++/* Symbol visibility specification encoded in the st_other field. */ ++#define STV_DEFAULT 0 /* Default symbol visibility rules */ ++#define STV_INTERNAL 1 /* Processor specific hidden class */ ++#define STV_HIDDEN 2 /* Sym unavailable in other modules */ ++#define STV_PROTECTED 3 /* Not preemptible, not exported */ ++ ++ ++/* Relocation table entry without addend (in section of type SHT_REL). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++} Elf32_Rel; ++ ++/* I have seen two different definitions of the Elf64_Rel and ++ Elf64_Rela structures, so we'll leave them out until Novell (or ++ whoever) gets their act together. */ ++/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++} Elf64_Rel; ++ ++/* Relocation table entry with addend (in section of type SHT_RELA). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++ Elf32_Sword r_addend; /* Addend */ ++} Elf32_Rela; ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++ Elf64_Sxword r_addend; /* Addend */ ++} Elf64_Rela; ++ ++/* How to extract and insert information held in the r_info field. */ ++ ++#define ELF32_R_SYM(val) ((val) >> 8) ++#define ELF32_R_TYPE(val) ((val) & 0xff) ++#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) ++ ++#define ELF64_R_SYM(i) ((i) >> 32) ++#define ELF64_R_TYPE(i) ((i) & 0xffffffff) ++#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) ++ ++/* Program segment header. */ ++ ++typedef struct ++{ ++ Elf32_Word p_type; /* Segment type */ ++ Elf32_Off p_offset; /* Segment file offset */ ++ Elf32_Addr p_vaddr; /* Segment virtual address */ ++ Elf32_Addr p_paddr; /* Segment physical address */ ++ Elf32_Word p_filesz; /* Segment size in file */ ++ Elf32_Word p_memsz; /* Segment size in memory */ ++ Elf32_Word p_flags; /* Segment flags */ ++ Elf32_Word p_align; /* Segment alignment */ ++} Elf32_Phdr; ++ ++typedef struct ++{ ++ Elf64_Word p_type; /* Segment type */ ++ Elf64_Word p_flags; /* Segment flags */ ++ Elf64_Off p_offset; /* Segment file offset */ ++ Elf64_Addr p_vaddr; /* Segment virtual address */ ++ Elf64_Addr p_paddr; /* Segment physical address */ ++ Elf64_Xword p_filesz; /* Segment size in file */ ++ Elf64_Xword p_memsz; /* Segment size in memory */ ++ Elf64_Xword p_align; /* Segment alignment */ ++} Elf64_Phdr; ++ ++/* Legal values for p_type (segment type). */ ++ ++#define PT_NULL 0 /* Program header table entry unused */ ++#define PT_LOAD 1 /* Loadable program segment */ ++#define PT_DYNAMIC 2 /* Dynamic linking information */ ++#define PT_INTERP 3 /* Program interpreter */ ++#define PT_NOTE 4 /* Auxiliary information */ ++#define PT_SHLIB 5 /* Reserved */ ++#define PT_PHDR 6 /* Entry for header table itself */ ++#define PT_TLS 7 /* Thread-local storage segment */ ++#define PT_NUM 8 /* Number of defined types */ ++#define PT_LOOS 0x60000000 /* Start of OS-specific */ ++#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ ++#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ ++#define PT_LOSUNW 0x6ffffffa ++#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ ++#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ ++#define PT_HISUNW 0x6fffffff ++#define PT_HIOS 0x6fffffff /* End of OS-specific */ ++#define PT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define PT_HIPROC 0x7fffffff /* End of processor-specific */ ++ ++/* Legal values for p_flags (segment flags). */ ++ ++#define PF_X (1 << 0) /* Segment is executable */ ++#define PF_W (1 << 1) /* Segment is writable */ ++#define PF_R (1 << 2) /* Segment is readable */ ++#define PF_MASKOS 0x0ff00000 /* OS-specific */ ++#define PF_MASKPROC 0xf0000000 /* Processor-specific */ ++ ++/* Legal values for note segment descriptor types for core files. */ ++ ++#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ ++#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ ++#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ ++#define NT_PRXREG 4 /* Contains copy of prxregset struct */ ++#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ ++#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ ++#define NT_AUXV 6 /* Contains copy of auxv array */ ++#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ ++#define NT_ASRS 8 /* Contains copy of asrset struct */ ++#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ ++#define NT_PSINFO 13 /* Contains copy of psinfo struct */ ++#define NT_PRCRED 14 /* Contains copy of prcred struct */ ++#define NT_UTSNAME 15 /* Contains copy of utsname struct */ ++#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ ++#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ ++#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct*/ ++ ++/* Legal values for the note segment descriptor types for object files. */ ++ ++#define NT_VERSION 1 /* Contains a version string. */ ++ ++ ++/* Dynamic section entry. */ ++ ++typedef struct ++{ ++ Elf32_Sword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf32_Word d_val; /* Integer value */ ++ Elf32_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf32_Dyn; ++ ++typedef struct ++{ ++ Elf64_Sxword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf64_Xword d_val; /* Integer value */ ++ Elf64_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf64_Dyn; ++ ++/* Legal values for d_tag (dynamic entry type). */ ++ ++#define DT_NULL 0 /* Marks end of dynamic section */ ++#define DT_NEEDED 1 /* Name of needed library */ ++#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ ++#define DT_PLTGOT 3 /* Processor defined value */ ++#define DT_HASH 4 /* Address of symbol hash table */ ++#define DT_STRTAB 5 /* Address of string table */ ++#define DT_SYMTAB 6 /* Address of symbol table */ ++#define DT_RELA 7 /* Address of Rela relocs */ ++#define DT_RELASZ 8 /* Total size of Rela relocs */ ++#define DT_RELAENT 9 /* Size of one Rela reloc */ ++#define DT_STRSZ 10 /* Size of string table */ ++#define DT_SYMENT 11 /* Size of one symbol table entry */ ++#define DT_INIT 12 /* Address of init function */ ++#define DT_FINI 13 /* Address of termination function */ ++#define DT_SONAME 14 /* Name of shared object */ ++#define DT_RPATH 15 /* Library search path (deprecated) */ ++#define DT_SYMBOLIC 16 /* Start symbol search here */ ++#define DT_REL 17 /* Address of Rel relocs */ ++#define DT_RELSZ 18 /* Total size of Rel relocs */ ++#define DT_RELENT 19 /* Size of one Rel reloc */ ++#define DT_PLTREL 20 /* Type of reloc in PLT */ ++#define DT_DEBUG 21 /* For debugging; unspecified */ ++#define DT_TEXTREL 22 /* Reloc might modify .text */ ++#define DT_JMPREL 23 /* Address of PLT relocs */ ++#define DT_BIND_NOW 24 /* Process relocations of object */ ++#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ ++#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ ++#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ ++#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ ++#define DT_RUNPATH 29 /* Library search path */ ++#define DT_FLAGS 30 /* Flags for the object being loaded */ ++#define DT_ENCODING 32 /* Start of encoded range */ ++#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ ++#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ ++#define DT_NUM 34 /* Number used */ ++#define DT_LOOS 0x6000000d /* Start of OS-specific */ ++#define DT_HIOS 0x6ffff000 /* End of OS-specific */ ++#define DT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define DT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ ++ ++/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the ++ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's ++ approach. */ ++#define DT_VALRNGLO 0x6ffffd00 ++#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ ++#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ ++#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ ++#define DT_CHECKSUM 0x6ffffdf8 ++#define DT_PLTPADSZ 0x6ffffdf9 ++#define DT_MOVEENT 0x6ffffdfa ++#define DT_MOVESZ 0x6ffffdfb ++#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ ++#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting ++ the following DT_* entry. */ ++#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ ++#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ ++#define DT_VALRNGHI 0x6ffffdff ++#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ ++#define DT_VALNUM 12 ++ ++/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the ++ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. ++ ++ If any adjustment is made to the ELF object after it has been ++ built these entries will need to be adjusted. */ ++#define DT_ADDRRNGLO 0x6ffffe00 ++#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ ++#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ ++#define DT_CONFIG 0x6ffffefa /* Configuration information. */ ++#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ ++#define DT_AUDIT 0x6ffffefc /* Object auditing. */ ++#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ ++#define DT_MOVETAB 0x6ffffefe /* Move table. */ ++#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ ++#define DT_ADDRRNGHI 0x6ffffeff ++#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ ++#define DT_ADDRNUM 10 ++ ++/* The versioning entry types. The next are defined as part of the ++ GNU extension. */ ++#define DT_VERSYM 0x6ffffff0 ++ ++#define DT_RELACOUNT 0x6ffffff9 ++#define DT_RELCOUNT 0x6ffffffa ++ ++/* These were chosen by Sun. */ ++#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ ++#define DT_VERDEF 0x6ffffffc /* Address of version definition ++ table */ ++#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ ++#define DT_VERNEED 0x6ffffffe /* Address of table with needed ++ versions */ ++#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ ++#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ ++#define DT_VERSIONTAGNUM 16 ++ ++/* Sun added these machine-independent extensions in the "processor-specific" ++ range. Be compatible. */ ++#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ ++#define DT_FILTER 0x7fffffff /* Shared object to get values from */ ++#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) ++#define DT_EXTRANUM 3 ++ ++/* Values of `d_un.d_val' in the DT_FLAGS entry. */ ++#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ ++#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ ++#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ ++#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ ++#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ ++ ++/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 ++ entry in the dynamic section. */ ++#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ ++#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ ++#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ ++#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ ++#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ ++#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ ++#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ ++#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ ++#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ ++#define DF_1_TRANS 0x00000200 ++#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ ++#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ ++#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ ++#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ ++#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ ++#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ ++#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ ++ ++/* Flags for the feature selection in DT_FEATURE_1. */ ++#define DTF_1_PARINIT 0x00000001 ++#define DTF_1_CONFEXP 0x00000002 ++ ++/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ ++#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ ++#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not ++ generally available. */ ++ ++/* Version definition sections. */ ++ ++typedef struct ++{ ++ Elf32_Half vd_version; /* Version revision */ ++ Elf32_Half vd_flags; /* Version information */ ++ Elf32_Half vd_ndx; /* Version Index */ ++ Elf32_Half vd_cnt; /* Number of associated aux entries */ ++ Elf32_Word vd_hash; /* Version name hash value */ ++ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf32_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf32_Verdef; ++ ++typedef struct ++{ ++ Elf64_Half vd_version; /* Version revision */ ++ Elf64_Half vd_flags; /* Version information */ ++ Elf64_Half vd_ndx; /* Version Index */ ++ Elf64_Half vd_cnt; /* Number of associated aux entries */ ++ Elf64_Word vd_hash; /* Version name hash value */ ++ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf64_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf64_Verdef; ++ ++ ++/* Legal values for vd_version (version revision). */ ++#define VER_DEF_NONE 0 /* No version */ ++#define VER_DEF_CURRENT 1 /* Current version */ ++#define VER_DEF_NUM 2 /* Given version number */ ++ ++/* Legal values for vd_flags (version information flags). */ ++#define VER_FLG_BASE 0x1 /* Version definition of file itself */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++/* Versym symbol index values. */ ++#define VER_NDX_LOCAL 0 /* Symbol is local. */ ++#define VER_NDX_GLOBAL 1 /* Symbol is global. */ ++#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ ++#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ ++ ++/* Auxialiary version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vda_name; /* Version or dependency names */ ++ Elf32_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf32_Verdaux; ++ ++typedef struct ++{ ++ Elf64_Word vda_name; /* Version or dependency names */ ++ Elf64_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf64_Verdaux; ++ ++ ++/* Version dependency section. */ ++ ++typedef struct ++{ ++ Elf32_Half vn_version; /* Version of structure */ ++ Elf32_Half vn_cnt; /* Number of associated aux entries */ ++ Elf32_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf32_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf32_Verneed; ++ ++typedef struct ++{ ++ Elf64_Half vn_version; /* Version of structure */ ++ Elf64_Half vn_cnt; /* Number of associated aux entries */ ++ Elf64_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf64_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf64_Verneed; ++ ++ ++/* Legal values for vn_version (version revision). */ ++#define VER_NEED_NONE 0 /* No version */ ++#define VER_NEED_CURRENT 1 /* Current version */ ++#define VER_NEED_NUM 2 /* Given version number */ ++ ++/* Auxiliary needed version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vna_hash; /* Hash value of dependency name */ ++ Elf32_Half vna_flags; /* Dependency specific information */ ++ Elf32_Half vna_other; /* Unused */ ++ Elf32_Word vna_name; /* Dependency name string offset */ ++ Elf32_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf32_Vernaux; ++ ++typedef struct ++{ ++ Elf64_Word vna_hash; /* Hash value of dependency name */ ++ Elf64_Half vna_flags; /* Dependency specific information */ ++ Elf64_Half vna_other; /* Unused */ ++ Elf64_Word vna_name; /* Dependency name string offset */ ++ Elf64_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf64_Vernaux; ++ ++ ++/* Legal values for vna_flags. */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++ ++/* Auxiliary vector. */ ++ ++/* This vector is normally only used by the program interpreter. The ++ usual definition in an ABI supplement uses the name auxv_t. The ++ vector is not usually defined in a standard file, but it ++ can't hurt. We rename it to avoid conflicts. The sizes of these ++ types are an arrangement between the exec server and the program ++ interpreter, so we don't fully specify them here. */ ++ ++typedef struct ++{ ++ int a_type; /* Entry type */ ++ union ++ { ++ long int a_val; /* Integer value */ ++ void *a_ptr; /* Pointer value */ ++ void (*a_fcn) (void); /* Function pointer value */ ++ } a_un; ++} Elf32_auxv_t; ++ ++typedef struct ++{ ++ long int a_type; /* Entry type */ ++ union ++ { ++ long int a_val; /* Integer value */ ++ void *a_ptr; /* Pointer value */ ++ void (*a_fcn) (void); /* Function pointer value */ ++ } a_un; ++} Elf64_auxv_t; ++ ++/* Legal values for a_type (entry type). */ ++ ++#define AT_NULL 0 /* End of vector */ ++#define AT_IGNORE 1 /* Entry should be ignored */ ++#define AT_EXECFD 2 /* File descriptor of program */ ++#define AT_PHDR 3 /* Program headers for program */ ++#define AT_PHENT 4 /* Size of program header entry */ ++#define AT_PHNUM 5 /* Number of program headers */ ++#define AT_PAGESZ 6 /* System page size */ ++#define AT_BASE 7 /* Base address of interpreter */ ++#define AT_FLAGS 8 /* Flags */ ++#define AT_ENTRY 9 /* Entry point of program */ ++#define AT_NOTELF 10 /* Program is not ELF */ ++#define AT_UID 11 /* Real uid */ ++#define AT_EUID 12 /* Effective uid */ ++#define AT_GID 13 /* Real gid */ ++#define AT_EGID 14 /* Effective gid */ ++#define AT_CLKTCK 17 /* Frequency of times() */ ++ ++/* Some more special a_type values describing the hardware. */ ++#define AT_PLATFORM 15 /* String identifying platform. */ ++#define AT_HWCAP 16 /* Machine dependent hints about ++ processor capabilities. */ ++ ++/* This entry gives some information about the FPU initialization ++ performed by the kernel. */ ++#define AT_FPUCW 18 /* Used FPU control word. */ ++ ++/* Cache block sizes. */ ++#define AT_DCACHEBSIZE 19 /* Data cache block size. */ ++#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ ++#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ ++ ++/* A special ignored value for PPC, used by the kernel to control the ++ interpretation of the AUXV. Must be > 16. */ ++#define AT_IGNOREPPC 22 /* Entry should be ignored. */ ++ ++#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ ++ ++/* Pointer to the global system page used for system calls and other ++ nice things. */ ++#define AT_SYSINFO 32 ++#define AT_SYSINFO_EHDR 33 ++ ++ ++/* Note section contents. Each entry in the note section begins with ++ a header of a fixed form. */ ++ ++typedef struct ++{ ++ Elf32_Word n_namesz; /* Length of the note's name. */ ++ Elf32_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf32_Word n_type; /* Type of the note. */ ++} Elf32_Nhdr; ++ ++typedef struct ++{ ++ Elf64_Word n_namesz; /* Length of the note's name. */ ++ Elf64_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf64_Word n_type; /* Type of the note. */ ++} Elf64_Nhdr; ++ ++/* Known names of notes. */ ++ ++/* Solaris entries in the note section have this name. */ ++#define ELF_NOTE_SOLARIS "SUNW Solaris" ++ ++/* Note entries for GNU systems have this name. */ ++#define ELF_NOTE_GNU "GNU" ++ ++ ++/* Defined types of notes for Solaris. */ ++ ++/* Value of descriptor (one word) is desired pagesize for the binary. */ ++#define ELF_NOTE_PAGESIZE_HINT 1 ++ ++ ++/* Defined note types for GNU systems. */ ++ ++/* ABI information. The descriptor consists of words: ++ word 0: OS descriptor ++ word 1: major version of the ABI ++ word 2: minor version of the ABI ++ word 3: subminor version of the ABI ++*/ ++#define ELF_NOTE_ABI 1 ++ ++/* Known OSes. These value can appear in word 0 of an ELF_NOTE_ABI ++ note section entry. */ ++#define ELF_NOTE_OS_LINUX 0 ++#define ELF_NOTE_OS_GNU 1 ++#define ELF_NOTE_OS_SOLARIS2 2 ++#define ELF_NOTE_OS_FREEBSD 3 ++ ++ ++/* Move records. */ ++typedef struct ++{ ++ Elf32_Xword m_value; /* Symbol value. */ ++ Elf32_Word m_info; /* Size and index. */ ++ Elf32_Word m_poffset; /* Symbol offset. */ ++ Elf32_Half m_repeat; /* Repeat count. */ ++ Elf32_Half m_stride; /* Stride info. */ ++} Elf32_Move; ++ ++typedef struct ++{ ++ Elf64_Xword m_value; /* Symbol value. */ ++ Elf64_Xword m_info; /* Size and index. */ ++ Elf64_Xword m_poffset; /* Symbol offset. */ ++ Elf64_Half m_repeat; /* Repeat count. */ ++ Elf64_Half m_stride; /* Stride info. */ ++} Elf64_Move; ++ ++/* Macro to construct move records. */ ++#define ELF32_M_SYM(info) ((info) >> 8) ++#define ELF32_M_SIZE(info) ((unsigned char) (info)) ++#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) ++ ++#define ELF64_M_SYM(info) ELF32_M_SYM (info) ++#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) ++#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) ++ ++ ++/* Motorola 68k specific definitions. */ ++ ++/* Values for Elf32_Ehdr.e_flags. */ ++#define EF_CPU32 0x00810000 ++ ++/* m68k relocs. */ ++ ++#define R_68K_NONE 0 /* No reloc */ ++#define R_68K_32 1 /* Direct 32 bit */ ++#define R_68K_16 2 /* Direct 16 bit */ ++#define R_68K_8 3 /* Direct 8 bit */ ++#define R_68K_PC32 4 /* PC relative 32 bit */ ++#define R_68K_PC16 5 /* PC relative 16 bit */ ++#define R_68K_PC8 6 /* PC relative 8 bit */ ++#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ ++#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ ++#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ ++#define R_68K_GOT32O 10 /* 32 bit GOT offset */ ++#define R_68K_GOT16O 11 /* 16 bit GOT offset */ ++#define R_68K_GOT8O 12 /* 8 bit GOT offset */ ++#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ ++#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ ++#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ ++#define R_68K_PLT32O 16 /* 32 bit PLT offset */ ++#define R_68K_PLT16O 17 /* 16 bit PLT offset */ ++#define R_68K_PLT8O 18 /* 8 bit PLT offset */ ++#define R_68K_COPY 19 /* Copy symbol at runtime */ ++#define R_68K_GLOB_DAT 20 /* Create GOT entry */ ++#define R_68K_JMP_SLOT 21 /* Create PLT entry */ ++#define R_68K_RELATIVE 22 /* Adjust by program base */ ++/* Keep this the last entry. */ ++#define R_68K_NUM 23 ++ ++/* Intel 80386 specific definitions. */ ++ ++/* i386 relocs. */ ++ ++#define R_386_NONE 0 /* No reloc */ ++#define R_386_32 1 /* Direct 32 bit */ ++#define R_386_PC32 2 /* PC relative 32 bit */ ++#define R_386_GOT32 3 /* 32 bit GOT entry */ ++#define R_386_PLT32 4 /* 32 bit PLT address */ ++#define R_386_COPY 5 /* Copy symbol at runtime */ ++#define R_386_GLOB_DAT 6 /* Create GOT entry */ ++#define R_386_JMP_SLOT 7 /* Create PLT entry */ ++#define R_386_RELATIVE 8 /* Adjust by program base */ ++#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ ++#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ ++#define R_386_32PLT 11 ++#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ ++#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS ++ block offset */ ++#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block ++ offset */ ++#define R_386_TLS_LE 17 /* Offset relative to static TLS ++ block */ ++#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of ++ general dynamic thread local data */ ++#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of ++ local dynamic thread local data ++ in LE code */ ++#define R_386_16 20 ++#define R_386_PC16 21 ++#define R_386_8 22 ++#define R_386_PC8 23 ++#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic ++ thread local data */ ++#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ ++#define R_386_TLS_GD_CALL 26 /* Relocation for call to ++ __tls_get_addr() */ ++#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ ++#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic ++ thread local data in LE code */ ++#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ ++#define R_386_TLS_LDM_CALL 30 /* Relocation for call to ++ __tls_get_addr() in LDM code */ ++#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ ++#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ ++#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS ++ block offset */ ++#define R_386_TLS_LE_32 34 /* Negated offset relative to static ++ TLS block */ ++#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ ++#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ ++#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ ++/* Keep this the last entry. */ ++#define R_386_NUM 38 ++ ++/* SUN SPARC specific definitions. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_REGISTER 13 /* Global register reserved to app. */ ++ ++/* Values for Elf64_Ehdr.e_flags. */ ++ ++#define EF_SPARCV9_MM 3 ++#define EF_SPARCV9_TSO 0 ++#define EF_SPARCV9_PSO 1 ++#define EF_SPARCV9_RMO 2 ++#define EF_SPARC_LEDATA 0x800000 /* little endian data */ ++#define EF_SPARC_EXT_MASK 0xFFFF00 ++#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ ++#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ ++#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ ++#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ ++ ++/* SPARC relocs. */ ++ ++#define R_SPARC_NONE 0 /* No reloc */ ++#define R_SPARC_8 1 /* Direct 8 bit */ ++#define R_SPARC_16 2 /* Direct 16 bit */ ++#define R_SPARC_32 3 /* Direct 32 bit */ ++#define R_SPARC_DISP8 4 /* PC relative 8 bit */ ++#define R_SPARC_DISP16 5 /* PC relative 16 bit */ ++#define R_SPARC_DISP32 6 /* PC relative 32 bit */ ++#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ ++#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ ++#define R_SPARC_HI22 9 /* High 22 bit */ ++#define R_SPARC_22 10 /* Direct 22 bit */ ++#define R_SPARC_13 11 /* Direct 13 bit */ ++#define R_SPARC_LO10 12 /* Truncated 10 bit */ ++#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ ++#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ ++#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ ++#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ ++#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ ++#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ ++#define R_SPARC_COPY 19 /* Copy symbol at runtime */ ++#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ ++#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ ++#define R_SPARC_RELATIVE 22 /* Adjust by program base */ ++#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ ++ ++/* Additional Sparc64 relocs. */ ++ ++#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ ++#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ ++#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ ++#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ ++#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ ++#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ ++#define R_SPARC_10 30 /* Direct 10 bit */ ++#define R_SPARC_11 31 /* Direct 11 bit */ ++#define R_SPARC_64 32 /* Direct 64 bit */ ++#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ ++#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ ++#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ ++#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ ++#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ ++#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ ++#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ ++#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ ++#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ ++#define R_SPARC_7 43 /* Direct 7 bit */ ++#define R_SPARC_5 44 /* Direct 5 bit */ ++#define R_SPARC_6 45 /* Direct 6 bit */ ++#define R_SPARC_DISP64 46 /* PC relative 64 bit */ ++#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ ++#define R_SPARC_HIX22 48 /* High 22 bit complemented */ ++#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ ++#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ ++#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ ++#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ ++#define R_SPARC_REGISTER 53 /* Global register usage */ ++#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ ++#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ ++#define R_SPARC_TLS_GD_HI22 56 ++#define R_SPARC_TLS_GD_LO10 57 ++#define R_SPARC_TLS_GD_ADD 58 ++#define R_SPARC_TLS_GD_CALL 59 ++#define R_SPARC_TLS_LDM_HI22 60 ++#define R_SPARC_TLS_LDM_LO10 61 ++#define R_SPARC_TLS_LDM_ADD 62 ++#define R_SPARC_TLS_LDM_CALL 63 ++#define R_SPARC_TLS_LDO_HIX22 64 ++#define R_SPARC_TLS_LDO_LOX10 65 ++#define R_SPARC_TLS_LDO_ADD 66 ++#define R_SPARC_TLS_IE_HI22 67 ++#define R_SPARC_TLS_IE_LO10 68 ++#define R_SPARC_TLS_IE_LD 69 ++#define R_SPARC_TLS_IE_LDX 70 ++#define R_SPARC_TLS_IE_ADD 71 ++#define R_SPARC_TLS_LE_HIX22 72 ++#define R_SPARC_TLS_LE_LOX10 73 ++#define R_SPARC_TLS_DTPMOD32 74 ++#define R_SPARC_TLS_DTPMOD64 75 ++#define R_SPARC_TLS_DTPOFF32 76 ++#define R_SPARC_TLS_DTPOFF64 77 ++#define R_SPARC_TLS_TPOFF32 78 ++#define R_SPARC_TLS_TPOFF64 79 ++/* Keep this the last entry. */ ++#define R_SPARC_NUM 80 ++ ++/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ ++ ++#define DT_SPARC_REGISTER 0x70000001 ++#define DT_SPARC_NUM 2 ++ ++/* Bits present in AT_HWCAP, primarily for Sparc32. */ ++ ++#define HWCAP_SPARC_FLUSH 1 /* The cpu supports flush insn. */ ++#define HWCAP_SPARC_STBAR 2 ++#define HWCAP_SPARC_SWAP 4 ++#define HWCAP_SPARC_MULDIV 8 ++#define HWCAP_SPARC_V9 16 /* The cpu is v9, so v8plus is ok. */ ++#define HWCAP_SPARC_ULTRA3 32 ++ ++/* MIPS R3000 specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ ++#define EF_MIPS_PIC 2 /* Contains PIC code */ ++#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ ++#define EF_MIPS_XGOT 8 ++#define EF_MIPS_64BIT_WHIRL 16 ++#define EF_MIPS_ABI2 32 ++#define EF_MIPS_ABI_ON32 64 ++#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ ++ ++/* Legal values for MIPS architecture level. */ ++ ++#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* The following are non-official names and should not be used. */ ++ ++#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* Special section indices. */ ++ ++#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ ++#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ ++#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ ++#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ ++#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ ++#define SHT_MIPS_MSYM 0x70000001 ++#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ ++#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ ++#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ ++#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ ++#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ ++#define SHT_MIPS_PACKAGE 0x70000007 ++#define SHT_MIPS_PACKSYM 0x70000008 ++#define SHT_MIPS_RELD 0x70000009 ++#define SHT_MIPS_IFACE 0x7000000b ++#define SHT_MIPS_CONTENT 0x7000000c ++#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ ++#define SHT_MIPS_SHDR 0x70000010 ++#define SHT_MIPS_FDESC 0x70000011 ++#define SHT_MIPS_EXTSYM 0x70000012 ++#define SHT_MIPS_DENSE 0x70000013 ++#define SHT_MIPS_PDESC 0x70000014 ++#define SHT_MIPS_LOCSYM 0x70000015 ++#define SHT_MIPS_AUXSYM 0x70000016 ++#define SHT_MIPS_OPTSYM 0x70000017 ++#define SHT_MIPS_LOCSTR 0x70000018 ++#define SHT_MIPS_LINE 0x70000019 ++#define SHT_MIPS_RFDESC 0x7000001a ++#define SHT_MIPS_DELTASYM 0x7000001b ++#define SHT_MIPS_DELTAINST 0x7000001c ++#define SHT_MIPS_DELTACLASS 0x7000001d ++#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ ++#define SHT_MIPS_DELTADECL 0x7000001f ++#define SHT_MIPS_SYMBOL_LIB 0x70000020 ++#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ ++#define SHT_MIPS_TRANSLATE 0x70000022 ++#define SHT_MIPS_PIXIE 0x70000023 ++#define SHT_MIPS_XLATE 0x70000024 ++#define SHT_MIPS_XLATE_DEBUG 0x70000025 ++#define SHT_MIPS_WHIRL 0x70000026 ++#define SHT_MIPS_EH_REGION 0x70000027 ++#define SHT_MIPS_XLATE_OLD 0x70000028 ++#define SHT_MIPS_PDR_EXCEPTION 0x70000029 ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ ++#define SHF_MIPS_MERGE 0x20000000 ++#define SHF_MIPS_ADDR 0x40000000 ++#define SHF_MIPS_STRINGS 0x80000000 ++#define SHF_MIPS_NOSTRIP 0x08000000 ++#define SHF_MIPS_LOCAL 0x04000000 ++#define SHF_MIPS_NAMES 0x02000000 ++#define SHF_MIPS_NODUPE 0x01000000 ++ ++ ++/* Symbol tables. */ ++ ++/* MIPS specific values for `st_other'. */ ++#define STO_MIPS_DEFAULT 0x0 ++#define STO_MIPS_INTERNAL 0x1 ++#define STO_MIPS_HIDDEN 0x2 ++#define STO_MIPS_PROTECTED 0x3 ++#define STO_MIPS_SC_ALIGN_UNUSED 0xff ++ ++/* MIPS specific values for `st_info'. */ ++#define STB_MIPS_SPLIT_COMMON 13 ++ ++/* Entries found in sections of type SHT_MIPS_GPTAB. */ ++ ++typedef union ++{ ++ struct ++ { ++ Elf32_Word gt_current_g_value; /* -G value used for compilation */ ++ Elf32_Word gt_unused; /* Not used */ ++ } gt_header; /* First entry in section */ ++ struct ++ { ++ Elf32_Word gt_g_value; /* If this value were used for -G */ ++ Elf32_Word gt_bytes; /* This many bytes would be used */ ++ } gt_entry; /* Subsequent entries in section */ ++} Elf32_gptab; ++ ++/* Entry found in sections of type SHT_MIPS_REGINFO. */ ++ ++typedef struct ++{ ++ Elf32_Word ri_gprmask; /* General registers used */ ++ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ ++ Elf32_Sword ri_gp_value; /* $gp register value */ ++} Elf32_RegInfo; ++ ++/* Entries found in sections of type SHT_MIPS_OPTIONS. */ ++ ++typedef struct ++{ ++ unsigned char kind; /* Determines interpretation of the ++ variable part of descriptor. */ ++ unsigned char size; /* Size of descriptor, including header. */ ++ Elf32_Section section; /* Section header index of section affected, ++ 0 for global options. */ ++ Elf32_Word info; /* Kind-specific information. */ ++} Elf_Options; ++ ++/* Values for `kind' field in Elf_Options. */ ++ ++#define ODK_NULL 0 /* Undefined. */ ++#define ODK_REGINFO 1 /* Register usage information. */ ++#define ODK_EXCEPTIONS 2 /* Exception processing options. */ ++#define ODK_PAD 3 /* Section padding options. */ ++#define ODK_HWPATCH 4 /* Hardware workarounds performed */ ++#define ODK_FILL 5 /* record the fill value used by the linker. */ ++#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ ++#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ ++#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ ++ ++/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ ++ ++#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ ++#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ ++#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ ++#define OEX_SMM 0x20000 /* Force sequential memory mode? */ ++#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ ++#define OEX_PRECISEFP OEX_FPDBUG ++#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ ++ ++#define OEX_FPU_INVAL 0x10 ++#define OEX_FPU_DIV0 0x08 ++#define OEX_FPU_OFLO 0x04 ++#define OEX_FPU_UFLO 0x02 ++#define OEX_FPU_INEX 0x01 ++ ++/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ ++ ++#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ ++#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ ++#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ ++#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ ++ ++#define OPAD_PREFIX 0x1 ++#define OPAD_POSTFIX 0x2 ++#define OPAD_SYMBOL 0x4 ++ ++/* Entry found in `.options' section. */ ++ ++typedef struct ++{ ++ Elf32_Word hwp_flags1; /* Extra flags. */ ++ Elf32_Word hwp_flags2; /* Extra flags. */ ++} Elf_Options_Hw; ++ ++/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ ++ ++#define OHWA0_R4KEOP_CHECKED 0x00000001 ++#define OHWA1_R4KEOP_CLEAN 0x00000002 ++ ++/* MIPS relocs. */ ++ ++#define R_MIPS_NONE 0 /* No reloc */ ++#define R_MIPS_16 1 /* Direct 16 bit */ ++#define R_MIPS_32 2 /* Direct 32 bit */ ++#define R_MIPS_REL32 3 /* PC relative 32 bit */ ++#define R_MIPS_26 4 /* Direct 26 bit shifted */ ++#define R_MIPS_HI16 5 /* High 16 bit */ ++#define R_MIPS_LO16 6 /* Low 16 bit */ ++#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ ++#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ ++#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ ++#define R_MIPS_PC16 10 /* PC relative 16 bit */ ++#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ ++#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ ++ ++#define R_MIPS_SHIFT5 16 ++#define R_MIPS_SHIFT6 17 ++#define R_MIPS_64 18 ++#define R_MIPS_GOT_DISP 19 ++#define R_MIPS_GOT_PAGE 20 ++#define R_MIPS_GOT_OFST 21 ++#define R_MIPS_GOT_HI16 22 ++#define R_MIPS_GOT_LO16 23 ++#define R_MIPS_SUB 24 ++#define R_MIPS_INSERT_A 25 ++#define R_MIPS_INSERT_B 26 ++#define R_MIPS_DELETE 27 ++#define R_MIPS_HIGHER 28 ++#define R_MIPS_HIGHEST 29 ++#define R_MIPS_CALL_HI16 30 ++#define R_MIPS_CALL_LO16 31 ++#define R_MIPS_SCN_DISP 32 ++#define R_MIPS_REL16 33 ++#define R_MIPS_ADD_IMMEDIATE 34 ++#define R_MIPS_PJUMP 35 ++#define R_MIPS_RELGOT 36 ++#define R_MIPS_JALR 37 ++/* Keep this the last entry. */ ++#define R_MIPS_NUM 38 ++ ++/* Legal values for p_type field of Elf32_Phdr. */ ++ ++#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ ++#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ ++#define PT_MIPS_OPTIONS 0x70000002 ++ ++/* Special program header types. */ ++ ++#define PF_MIPS_LOCAL 0x10000000 ++ ++/* Legal values for d_tag field of Elf32_Dyn. */ ++ ++#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ ++#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ ++#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ ++#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ ++#define DT_MIPS_FLAGS 0x70000005 /* Flags */ ++#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ ++#define DT_MIPS_MSYM 0x70000007 ++#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ ++#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ ++#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ ++#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ ++#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ ++#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ ++#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ ++#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ ++#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ ++#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ ++#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ ++#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in ++ DT_MIPS_DELTA_CLASS. */ ++#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ ++#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in ++ DT_MIPS_DELTA_INSTANCE. */ ++#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ ++#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in ++ DT_MIPS_DELTA_RELOC. */ ++#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta ++ relocations refer to. */ ++#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in ++ DT_MIPS_DELTA_SYM. */ ++#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the ++ class declaration. */ ++#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in ++ DT_MIPS_DELTA_CLASSSYM. */ ++#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ ++#define DT_MIPS_PIXIE_INIT 0x70000023 ++#define DT_MIPS_SYMBOL_LIB 0x70000024 ++#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 ++#define DT_MIPS_LOCAL_GOTIDX 0x70000026 ++#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 ++#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 ++#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ ++#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ ++#define DT_MIPS_DYNSTR_ALIGN 0x7000002b ++#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ ++#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve ++ function stored in GOT. */ ++#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added ++ by rld on dlopen() calls. */ ++#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ ++#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ ++#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ ++#define DT_MIPS_NUM 0x32 ++ ++/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ ++ ++#define RHF_NONE 0 /* No flags */ ++#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ ++#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ ++#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ ++#define RHF_NO_MOVE (1 << 3) ++#define RHF_SGI_ONLY (1 << 4) ++#define RHF_GUARANTEE_INIT (1 << 5) ++#define RHF_DELTA_C_PLUS_PLUS (1 << 6) ++#define RHF_GUARANTEE_START_INIT (1 << 7) ++#define RHF_PIXIE (1 << 8) ++#define RHF_DEFAULT_DELAY_LOAD (1 << 9) ++#define RHF_REQUICKSTART (1 << 10) ++#define RHF_REQUICKSTARTED (1 << 11) ++#define RHF_CORD (1 << 12) ++#define RHF_NO_UNRES_UNDEF (1 << 13) ++#define RHF_RLD_ORDER_SAFE (1 << 14) ++ ++/* Entries found in sections of type SHT_MIPS_LIBLIST. */ ++ ++typedef struct ++{ ++ Elf32_Word l_name; /* Name (string table index) */ ++ Elf32_Word l_time_stamp; /* Timestamp */ ++ Elf32_Word l_checksum; /* Checksum */ ++ Elf32_Word l_version; /* Interface version */ ++ Elf32_Word l_flags; /* Flags */ ++} Elf32_Lib; ++ ++typedef struct ++{ ++ Elf64_Word l_name; /* Name (string table index) */ ++ Elf64_Word l_time_stamp; /* Timestamp */ ++ Elf64_Word l_checksum; /* Checksum */ ++ Elf64_Word l_version; /* Interface version */ ++ Elf64_Word l_flags; /* Flags */ ++} Elf64_Lib; ++ ++ ++/* Legal values for l_flags. */ ++ ++#define LL_NONE 0 ++#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ ++#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ ++#define LL_REQUIRE_MINOR (1 << 2) ++#define LL_EXPORTS (1 << 3) ++#define LL_DELAY_LOAD (1 << 4) ++#define LL_DELTA (1 << 5) ++ ++/* Entries found in sections of type SHT_MIPS_CONFLICT. */ ++ ++typedef Elf32_Addr Elf32_Conflict; ++ ++ ++/* HPPA specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ ++#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ ++#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ ++#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ ++#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch ++ prediction. */ ++#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ ++#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ ++ ++/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ ++ ++#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ ++#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ ++#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ ++ ++/* Additional section indeces. */ ++ ++#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared ++ symbols in ANSI C. */ ++#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ ++#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ ++#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ ++#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ ++#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ ++ ++#define STT_HP_OPAQUE (STT_LOOS + 0x1) ++#define STT_HP_STUB (STT_LOOS + 0x2) ++ ++/* HPPA relocs. */ ++ ++#define R_PARISC_NONE 0 /* No reloc. */ ++#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ ++#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ ++#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ ++#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ ++#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ ++#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ ++#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ ++#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ ++#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ ++#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ ++#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ ++#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ ++#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ ++#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ ++#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ ++#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ ++#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ ++#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ ++#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ ++#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ ++#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ ++#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ ++#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ ++#define R_PARISC_FPTR64 64 /* 64 bits function address. */ ++#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ ++#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ ++#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ ++#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ ++#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ ++#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ ++#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ ++#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ ++#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ ++#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ ++#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ ++#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ ++#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ ++#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ ++#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ ++#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LORESERVE 128 ++#define R_PARISC_COPY 128 /* Copy relocation. */ ++#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ ++#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ ++#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ ++#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ ++#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ ++#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ ++#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ ++#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ ++#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_HIRESERVE 255 ++ ++/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PT_HP_TLS (PT_LOOS + 0x0) ++#define PT_HP_CORE_NONE (PT_LOOS + 0x1) ++#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) ++#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) ++#define PT_HP_CORE_COMM (PT_LOOS + 0x4) ++#define PT_HP_CORE_PROC (PT_LOOS + 0x5) ++#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) ++#define PT_HP_CORE_STACK (PT_LOOS + 0x7) ++#define PT_HP_CORE_SHM (PT_LOOS + 0x8) ++#define PT_HP_CORE_MMF (PT_LOOS + 0x9) ++#define PT_HP_PARALLEL (PT_LOOS + 0x10) ++#define PT_HP_FASTBIND (PT_LOOS + 0x11) ++#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) ++#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) ++#define PT_HP_STACK (PT_LOOS + 0x14) ++ ++#define PT_PARISC_ARCHEXT 0x70000000 ++#define PT_PARISC_UNWIND 0x70000001 ++ ++/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PF_PARISC_SBP 0x08000000 ++ ++#define PF_HP_PAGE_SIZE 0x00100000 ++#define PF_HP_FAR_SHARED 0x00200000 ++#define PF_HP_NEAR_SHARED 0x00400000 ++#define PF_HP_CODE 0x01000000 ++#define PF_HP_MODIFY 0x02000000 ++#define PF_HP_LAZYSWAP 0x04000000 ++#define PF_HP_SBP 0x08000000 ++ ++ ++/* Alpha specific definitions. */ ++ ++/* Legal values for e_flags field of Elf64_Ehdr. */ ++ ++#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ ++#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ ++ ++/* Legal values for sh_type field of Elf64_Shdr. */ ++ ++/* These two are primerily concerned with ECOFF debugging info. */ ++#define SHT_ALPHA_DEBUG 0x70000001 ++#define SHT_ALPHA_REGINFO 0x70000002 ++ ++/* Legal values for sh_flags field of Elf64_Shdr. */ ++ ++#define SHF_ALPHA_GPREL 0x10000000 ++ ++/* Legal values for st_other field of Elf64_Sym. */ ++#define STO_ALPHA_NOPV 0x80 /* No PV required. */ ++#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ ++ ++/* Alpha relocs. */ ++ ++#define R_ALPHA_NONE 0 /* No reloc */ ++#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ ++#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ ++#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ ++#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ ++#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ ++#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ ++#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ ++#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ ++#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ ++#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ ++#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ ++#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ ++#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ ++#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ ++#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ ++#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ ++#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ ++#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ ++#define R_ALPHA_TLS_GD_HI 28 ++#define R_ALPHA_TLSGD 29 ++#define R_ALPHA_TLS_LDM 30 ++#define R_ALPHA_DTPMOD64 31 ++#define R_ALPHA_GOTDTPREL 32 ++#define R_ALPHA_DTPREL64 33 ++#define R_ALPHA_DTPRELHI 34 ++#define R_ALPHA_DTPRELLO 35 ++#define R_ALPHA_DTPREL16 36 ++#define R_ALPHA_GOTTPREL 37 ++#define R_ALPHA_TPREL64 38 ++#define R_ALPHA_TPRELHI 39 ++#define R_ALPHA_TPRELLO 40 ++#define R_ALPHA_TPREL16 41 ++/* Keep this the last entry. */ ++#define R_ALPHA_NUM 46 ++ ++/* Magic values of the LITUSE relocation addend. */ ++#define LITUSE_ALPHA_ADDR 0 ++#define LITUSE_ALPHA_BASE 1 ++#define LITUSE_ALPHA_BYTOFF 2 ++#define LITUSE_ALPHA_JSR 3 ++#define LITUSE_ALPHA_TLS_GD 4 ++#define LITUSE_ALPHA_TLS_LDM 5 ++ ++ ++/* PowerPC specific declarations */ ++ ++/* Values for Elf32/64_Ehdr.e_flags. */ ++#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ ++ ++/* Cygnus local bits below */ ++#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ ++#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib ++ flag */ ++ ++/* PowerPC relocations defined by the ABIs */ ++#define R_PPC_NONE 0 ++#define R_PPC_ADDR32 1 /* 32bit absolute address */ ++#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ ++#define R_PPC_ADDR16 3 /* 16bit absolute address */ ++#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ ++#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ ++#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ ++#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ ++#define R_PPC_ADDR14_BRTAKEN 8 ++#define R_PPC_ADDR14_BRNTAKEN 9 ++#define R_PPC_REL24 10 /* PC relative 26 bit */ ++#define R_PPC_REL14 11 /* PC relative 16 bit */ ++#define R_PPC_REL14_BRTAKEN 12 ++#define R_PPC_REL14_BRNTAKEN 13 ++#define R_PPC_GOT16 14 ++#define R_PPC_GOT16_LO 15 ++#define R_PPC_GOT16_HI 16 ++#define R_PPC_GOT16_HA 17 ++#define R_PPC_PLTREL24 18 ++#define R_PPC_COPY 19 ++#define R_PPC_GLOB_DAT 20 ++#define R_PPC_JMP_SLOT 21 ++#define R_PPC_RELATIVE 22 ++#define R_PPC_LOCAL24PC 23 ++#define R_PPC_UADDR32 24 ++#define R_PPC_UADDR16 25 ++#define R_PPC_REL32 26 ++#define R_PPC_PLT32 27 ++#define R_PPC_PLTREL32 28 ++#define R_PPC_PLT16_LO 29 ++#define R_PPC_PLT16_HI 30 ++#define R_PPC_PLT16_HA 31 ++#define R_PPC_SDAREL16 32 ++#define R_PPC_SECTOFF 33 ++#define R_PPC_SECTOFF_LO 34 ++#define R_PPC_SECTOFF_HI 35 ++#define R_PPC_SECTOFF_HA 36 ++ ++/* PowerPC relocations defined for the TLS access ABI. */ ++#define R_PPC_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ ++#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ ++#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ ++#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ ++#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ ++#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ ++#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ ++#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ ++#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ ++ ++/* Keep this the last entry. */ ++#define R_PPC_NUM 95 ++ ++/* The remaining relocs are from the Embedded ELF ABI, and are not ++ in the SVR4 ELF ABI. */ ++#define R_PPC_EMB_NADDR32 101 ++#define R_PPC_EMB_NADDR16 102 ++#define R_PPC_EMB_NADDR16_LO 103 ++#define R_PPC_EMB_NADDR16_HI 104 ++#define R_PPC_EMB_NADDR16_HA 105 ++#define R_PPC_EMB_SDAI16 106 ++#define R_PPC_EMB_SDA2I16 107 ++#define R_PPC_EMB_SDA2REL 108 ++#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ ++#define R_PPC_EMB_MRKREF 110 ++#define R_PPC_EMB_RELSEC16 111 ++#define R_PPC_EMB_RELST_LO 112 ++#define R_PPC_EMB_RELST_HI 113 ++#define R_PPC_EMB_RELST_HA 114 ++#define R_PPC_EMB_BIT_FLD 115 ++#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ ++ ++/* Diab tool relocations. */ ++#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ ++#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ ++#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ ++#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ ++#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ ++#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ ++ ++/* This is a phony reloc to handle any old fashioned TOC16 references ++ that may still be in object files. */ ++#define R_PPC_TOC16 255 ++ ++ ++/* PowerPC64 relocations defined by the ABIs */ ++#define R_PPC64_NONE R_PPC_NONE ++#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ ++#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ ++#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ ++#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ ++#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ ++#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ ++#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ ++#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN ++#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN ++#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ ++#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ ++#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN ++#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN ++#define R_PPC64_GOT16 R_PPC_GOT16 ++#define R_PPC64_GOT16_LO R_PPC_GOT16_LO ++#define R_PPC64_GOT16_HI R_PPC_GOT16_HI ++#define R_PPC64_GOT16_HA R_PPC_GOT16_HA ++ ++#define R_PPC64_COPY R_PPC_COPY ++#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT ++#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT ++#define R_PPC64_RELATIVE R_PPC_RELATIVE ++ ++#define R_PPC64_UADDR32 R_PPC_UADDR32 ++#define R_PPC64_UADDR16 R_PPC_UADDR16 ++#define R_PPC64_REL32 R_PPC_REL32 ++#define R_PPC64_PLT32 R_PPC_PLT32 ++#define R_PPC64_PLTREL32 R_PPC_PLTREL32 ++#define R_PPC64_PLT16_LO R_PPC_PLT16_LO ++#define R_PPC64_PLT16_HI R_PPC_PLT16_HI ++#define R_PPC64_PLT16_HA R_PPC_PLT16_HA ++ ++#define R_PPC64_SECTOFF R_PPC_SECTOFF ++#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO ++#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI ++#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA ++#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ ++#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ ++#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ ++#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ ++#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ ++#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ ++#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ ++#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ ++#define R_PPC64_PLT64 45 /* doubleword64 L + A */ ++#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ ++#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ ++#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ ++#define R_PPC64_TOC 51 /* doubleword64 .TOC */ ++#define R_PPC64_PLTGOT16 52 /* half16* M + A */ ++#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ ++#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ ++#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ ++ ++#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ ++#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ ++#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ ++#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ ++#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ ++#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ ++#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ ++#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ ++#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ ++#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ ++#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ ++ ++/* PowerPC64 relocations defined for the TLS access ABI. */ ++#define R_PPC64_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ ++#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ ++#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ ++#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ ++#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ ++#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ ++#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ ++#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ ++#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ ++#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ ++#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ ++#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ ++#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ ++#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ ++#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ ++#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ ++#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ ++ ++/* Keep this the last entry. */ ++#define R_PPC64_NUM 107 ++ ++/* PowerPC64 specific values for the Dyn d_tag field. */ ++#define DT_PPC64_GLINK (DT_LOPROC + 0) ++#define DT_PPC64_NUM 1 ++ ++ ++/* ARM specific declarations */ ++ ++/* Processor specific flags for the ELF header e_flags field. */ ++#define EF_ARM_RELEXEC 0x01 ++#define EF_ARM_HASENTRY 0x02 ++#define EF_ARM_INTERWORK 0x04 ++#define EF_ARM_APCS_26 0x08 ++#define EF_ARM_APCS_FLOAT 0x10 ++#define EF_ARM_PIC 0x20 ++#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ ++#define EF_ARM_NEW_ABI 0x80 ++#define EF_ARM_OLD_ABI 0x100 ++ ++/* Other constants defined in the ARM ELF spec. version B-01. */ ++/* NB. These conflict with values defined above. */ ++#define EF_ARM_SYMSARESORTED 0x04 ++#define EF_ARM_DYNSYMSUSESEGIDX 0x08 ++#define EF_ARM_MAPSYMSFIRST 0x10 ++#define EF_ARM_EABIMASK 0XFF000000 ++ ++#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) ++#define EF_ARM_EABI_UNKNOWN 0x00000000 ++#define EF_ARM_EABI_VER1 0x01000000 ++#define EF_ARM_EABI_VER2 0x02000000 ++ ++/* Additional symbol types for Thumb */ ++#define STT_ARM_TFUNC 0xd ++ ++/* ARM-specific values for sh_flags */ ++#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ ++#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined ++ in the input to a link step */ ++ ++/* ARM-specific program header flags */ ++#define PF_ARM_SB 0x10000000 /* Segment contains the location ++ addressed by the static base */ ++ ++/* ARM relocs. */ ++#define R_ARM_NONE 0 /* No reloc */ ++#define R_ARM_PC24 1 /* PC relative 26 bit branch */ ++#define R_ARM_ABS32 2 /* Direct 32 bit */ ++#define R_ARM_REL32 3 /* PC relative 32 bit */ ++#define R_ARM_PC13 4 ++#define R_ARM_ABS16 5 /* Direct 16 bit */ ++#define R_ARM_ABS12 6 /* Direct 12 bit */ ++#define R_ARM_THM_ABS5 7 ++#define R_ARM_ABS8 8 /* Direct 8 bit */ ++#define R_ARM_SBREL32 9 ++#define R_ARM_THM_PC22 10 ++#define R_ARM_THM_PC8 11 ++#define R_ARM_AMP_VCALL9 12 ++#define R_ARM_SWI24 13 ++#define R_ARM_THM_SWI8 14 ++#define R_ARM_XPC25 15 ++#define R_ARM_THM_XPC22 16 ++#define R_ARM_COPY 20 /* Copy symbol at runtime */ ++#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ ++#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ ++#define R_ARM_RELATIVE 23 /* Adjust by program base */ ++#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ ++#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ ++#define R_ARM_GOT32 26 /* 32 bit GOT entry */ ++#define R_ARM_PLT32 27 /* 32 bit PLT address */ ++#define R_ARM_ALU_PCREL_7_0 32 ++#define R_ARM_ALU_PCREL_15_8 33 ++#define R_ARM_ALU_PCREL_23_15 34 ++#define R_ARM_LDR_SBREL_11_0 35 ++#define R_ARM_ALU_SBREL_19_12 36 ++#define R_ARM_ALU_SBREL_27_20 37 ++#define R_ARM_GNU_VTENTRY 100 ++#define R_ARM_GNU_VTINHERIT 101 ++#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ ++#define R_ARM_THM_PC9 103 /* thumb conditional branch */ ++#define R_ARM_RXPC25 249 ++#define R_ARM_RSBREL32 250 ++#define R_ARM_THM_RPC22 251 ++#define R_ARM_RREL32 252 ++#define R_ARM_RABS22 253 ++#define R_ARM_RPC24 254 ++#define R_ARM_RBASE 255 ++/* Keep this the last entry. */ ++#define R_ARM_NUM 256 ++ ++/* IA-64 specific declarations. */ ++ ++/* Processor specific flags for the Ehdr e_flags field. */ ++#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ ++#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ ++#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ ++ ++/* Processor specific values for the Phdr p_type field. */ ++#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ ++#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ ++ ++/* Processor specific flags for the Phdr p_flags field. */ ++#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Shdr sh_type field. */ ++#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ ++#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ ++ ++/* Processor specific flags for the Shdr sh_flags field. */ ++#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ ++#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Dyn d_tag field. */ ++#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) ++#define DT_IA_64_NUM 1 ++ ++/* IA-64 relocations. */ ++#define R_IA64_NONE 0x00 /* none */ ++#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ ++#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ ++#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ ++#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ ++#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ ++#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ ++#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ ++#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ ++#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ ++#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ ++#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ ++#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ ++#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ ++#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ ++#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ ++#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ ++#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ ++#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ ++#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ ++#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ ++#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ ++#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ ++#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ ++#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ ++#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ ++#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ ++#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ ++#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ ++#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ ++#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ ++#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ ++#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ ++#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ ++#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ ++#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ ++#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ ++#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ ++#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ ++#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ ++#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ ++#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ ++#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ ++#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ ++#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ ++#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ ++#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ ++#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ ++#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ ++#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ ++#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ ++#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ ++#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ ++#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ ++#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ ++#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ ++#define R_IA64_COPY 0x84 /* copy relocation */ ++#define R_IA64_SUB 0x85 /* Addend and symbol difference */ ++#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ ++#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ ++#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ ++#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ ++#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ ++#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ ++#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ ++#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ ++#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ ++#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ ++#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ ++#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ ++#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ ++#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ ++#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ ++#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ ++ ++/* SH specific declarations */ ++ ++/* SH relocs. */ ++#define R_SH_NONE 0 ++#define R_SH_DIR32 1 ++#define R_SH_REL32 2 ++#define R_SH_DIR8WPN 3 ++#define R_SH_IND12W 4 ++#define R_SH_DIR8WPL 5 ++#define R_SH_DIR8WPZ 6 ++#define R_SH_DIR8BP 7 ++#define R_SH_DIR8W 8 ++#define R_SH_DIR8L 9 ++#define R_SH_SWITCH16 25 ++#define R_SH_SWITCH32 26 ++#define R_SH_USES 27 ++#define R_SH_COUNT 28 ++#define R_SH_ALIGN 29 ++#define R_SH_CODE 30 ++#define R_SH_DATA 31 ++#define R_SH_LABEL 32 ++#define R_SH_SWITCH8 33 ++#define R_SH_GNU_VTINHERIT 34 ++#define R_SH_GNU_VTENTRY 35 ++#define R_SH_TLS_GD_32 144 ++#define R_SH_TLS_LD_32 145 ++#define R_SH_TLS_LDO_32 146 ++#define R_SH_TLS_IE_32 147 ++#define R_SH_TLS_LE_32 148 ++#define R_SH_TLS_DTPMOD32 149 ++#define R_SH_TLS_DTPOFF32 150 ++#define R_SH_TLS_TPOFF32 151 ++#define R_SH_GOT32 160 ++#define R_SH_PLT32 161 ++#define R_SH_COPY 162 ++#define R_SH_GLOB_DAT 163 ++#define R_SH_JMP_SLOT 164 ++#define R_SH_RELATIVE 165 ++#define R_SH_GOTOFF 166 ++#define R_SH_GOTPC 167 ++/* Keep this the last entry. */ ++#define R_SH_NUM 256 ++ ++/* Additional s390 relocs */ ++ ++#define R_390_NONE 0 /* No reloc. */ ++#define R_390_8 1 /* Direct 8 bit. */ ++#define R_390_12 2 /* Direct 12 bit. */ ++#define R_390_16 3 /* Direct 16 bit. */ ++#define R_390_32 4 /* Direct 32 bit. */ ++#define R_390_PC32 5 /* PC relative 32 bit. */ ++#define R_390_GOT12 6 /* 12 bit GOT offset. */ ++#define R_390_GOT32 7 /* 32 bit GOT offset. */ ++#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ ++#define R_390_COPY 9 /* Copy symbol at runtime. */ ++#define R_390_GLOB_DAT 10 /* Create GOT entry. */ ++#define R_390_JMP_SLOT 11 /* Create PLT entry. */ ++#define R_390_RELATIVE 12 /* Adjust by program base. */ ++#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ ++#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ ++#define R_390_GOT16 15 /* 16 bit GOT offset. */ ++#define R_390_PC16 16 /* PC relative 16 bit. */ ++#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ ++#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ ++#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ ++#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ ++#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ ++#define R_390_64 22 /* Direct 64 bit. */ ++#define R_390_PC64 23 /* PC relative 64 bit. */ ++#define R_390_GOT64 24 /* 64 bit GOT offset. */ ++#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ ++#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ ++#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ ++#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ ++#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ ++#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ ++#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ ++#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ ++#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ ++#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ ++#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ ++#define R_390_TLS_GDCALL 38 /* Tag for function call in general ++ dynamic TLS code. */ ++#define R_390_TLS_LDCALL 39 /* Tag for function call in local ++ dynamic TLS code. */ ++#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ ++#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ ++#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS ++ block. */ ++ ++/* Keep this the last entry. */ ++#define R_390_NUM 57 ++ ++/* CRIS relocations. */ ++#define R_CRIS_NONE 0 ++#define R_CRIS_8 1 ++#define R_CRIS_16 2 ++#define R_CRIS_32 3 ++#define R_CRIS_8_PCREL 4 ++#define R_CRIS_16_PCREL 5 ++#define R_CRIS_32_PCREL 6 ++#define R_CRIS_GNU_VTINHERIT 7 ++#define R_CRIS_GNU_VTENTRY 8 ++#define R_CRIS_COPY 9 ++#define R_CRIS_GLOB_DAT 10 ++#define R_CRIS_JUMP_SLOT 11 ++#define R_CRIS_RELATIVE 12 ++#define R_CRIS_16_GOT 13 ++#define R_CRIS_32_GOT 14 ++#define R_CRIS_16_GOTPLT 15 ++#define R_CRIS_32_GOTPLT 16 ++#define R_CRIS_32_GOTREL 17 ++#define R_CRIS_32_PLT_GOTREL 18 ++#define R_CRIS_32_PLT_PCREL 19 ++ ++#define R_CRIS_NUM 20 ++ ++/* AMD x86-64 relocations. */ ++#define R_X86_64_NONE 0 /* No reloc */ ++#define R_X86_64_64 1 /* Direct 64 bit */ ++#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ ++#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ ++#define R_X86_64_PLT32 4 /* 32 bit PLT address */ ++#define R_X86_64_COPY 5 /* Copy symbol at runtime */ ++#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ ++#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ ++#define R_X86_64_RELATIVE 8 /* Adjust by program base */ ++#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative ++ offset to GOT */ ++#define R_X86_64_32 10 /* Direct 32 bit zero extended */ ++#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ ++#define R_X86_64_16 12 /* Direct 16 bit zero extended */ ++#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ ++#define R_X86_64_8 14 /* Direct 8 bit sign extended */ ++#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ ++#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ ++#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ ++#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ ++#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset ++ to two GOT entries for GD symbol */ ++#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset ++ to two GOT entries for LD symbol */ ++#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ ++#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset ++ to GOT entry for IE symbol */ ++#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ ++ ++#define R_X86_64_NUM 24 ++ ++__END_DECLS ++ ++#endif /* elf.h */ + + #include "elfconfig.h" + +@@ -195,3 +2641,4 @@ + void fatal(const char *fmt, ...); + void warn(const char *fmt, ...); + void merror(const char *fmt, ...); ++ +diff -Nur linux-2.6.36.orig/scripts/mod/sumversion.c linux-2.6.36/scripts/mod/sumversion.c +--- linux-2.6.36.orig/scripts/mod/sumversion.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/mod/sumversion.c 2010-11-28 18:33:24.000000000 +0100 +@@ -1,4 +1,4 @@ +-#include ++/* #include */ + #ifdef __sun__ + #include + #else diff --git a/target/linux/patches/2.6.39.4/cris-etrax.patch b/target/linux/patches/2.6.39.4/cris-etrax.patch new file mode 100644 index 000000000..a80d9a8b8 --- /dev/null +++ b/target/linux/patches/2.6.39.4/cris-etrax.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h +--- linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h 2011-08-24 19:15:05.000000000 +0200 +@@ -2,7 +2,7 @@ + #include + + /* High level I2C actions */ +-int __init i2c_init(void); ++static int __init i2c_init(void); + int i2c_write(unsigned char theSlave, void *data, size_t nbytes); + int i2c_read(unsigned char theSlave, void *data, size_t nbytes); + int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue); diff --git a/target/linux/patches/2.6.39.4/cris-thread-macro.patch b/target/linux/patches/2.6.39.4/cris-thread-macro.patch new file mode 100644 index 000000000..717b31636 --- /dev/null +++ b/target/linux/patches/2.6.39.4/cris-thread-macro.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.39.orig/arch/cris/include/asm/thread_info.h linux-2.6.39/arch/cris/include/asm/thread_info.h +--- linux-2.6.39.orig/arch/cris/include/asm/thread_info.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/include/asm/thread_info.h 2011-06-28 13:07:09.712682140 +0200 +@@ -68,7 +68,7 @@ + #define init_thread_info (init_thread_union.thread_info) + + /* thread information allocation */ +-#define alloc_thread_info(tsk, node) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1)) ++#define alloc_thread_info_node(tsk, node) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1)) + #define free_thread_info(ti) free_pages((unsigned long) (ti), 1) + + #endif /* !__ASSEMBLY__ */ diff --git a/target/linux/patches/2.6.39.4/cris.patch b/target/linux/patches/2.6.39.4/cris.patch new file mode 100644 index 000000000..2d56de399 --- /dev/null +++ b/target/linux/patches/2.6.39.4/cris.patch @@ -0,0 +1,5739 @@ +diff -Nur linux-2.6.39.orig/arch/cris/arch-v10/drivers/axisflashmap.c linux-2.6.39/arch/cris/arch-v10/drivers/axisflashmap.c +--- linux-2.6.39.orig/arch/cris/arch-v10/drivers/axisflashmap.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/arch-v10/drivers/axisflashmap.c 2011-08-25 07:43:00.179230147 +0200 +@@ -113,7 +113,7 @@ + + /* If no partition-table was found, we use this default-set. */ + #define MAX_PARTITIONS 7 +-#define NUM_DEFAULT_PARTITIONS 3 ++#define NUM_DEFAULT_PARTITIONS 4 + + /* + * Default flash size is 2MB. CONFIG_ETRAX_PTABLE_SECTOR is most likely the +@@ -122,19 +122,24 @@ + */ + static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = { + { +- .name = "boot firmware", +- .size = CONFIG_ETRAX_PTABLE_SECTOR, ++ .name = "kernel", ++ .size = 0x00, + .offset = 0 + }, + { +- .name = "kernel", +- .size = 0x200000 - (6 * CONFIG_ETRAX_PTABLE_SECTOR), +- .offset = CONFIG_ETRAX_PTABLE_SECTOR ++ .name = "rootfs", ++ .size = 0x200000 , ++ .offset = 0x200000 ++ }, ++ { ++ .name = "cfgfs", ++ .size = 0x20000 , ++ .offset = CONFIG_ETRAX_MTD_SIZE - 0x20000 + }, + { +- .name = "filesystem", +- .size = 5 * CONFIG_ETRAX_PTABLE_SECTOR, +- .offset = 0x200000 - (5 * CONFIG_ETRAX_PTABLE_SECTOR) ++ .name = "linux", ++ .size = CONFIG_ETRAX_MTD_SIZE - 0x20000, ++ .offset = 0 + } + }; + +@@ -275,6 +280,11 @@ + struct partitiontable_entry *ptable; + int use_default_ptable = 1; /* Until proven otherwise. */ + const char pmsg[] = " /dev/flash%d at 0x%08x, size 0x%08x\n"; ++ unsigned int kernel_part_size = 0; ++ unsigned char *flash_mem = (unsigned char*)(FLASH_CACHED_ADDR); ++ unsigned int flash_scan_count = 0; ++ const char *part_magic = "ACME_PART_MAGIC"; ++ unsigned int magic_len = strlen(part_magic); + + if (!(mymtd = flash_probe())) { + /* There's no reason to use this module if no flash chip can +@@ -286,6 +296,31 @@ + mymtd->name, mymtd->size); + axisflash_mtd = mymtd; + } ++ /* scan flash to findout where out partition starts */ ++ ++ printk(KERN_INFO "Scanning flash for end of kernel magic\n"); ++ for(flash_scan_count = 0; flash_scan_count < 100000; flash_scan_count++){ ++ if(strncmp(&flash_mem[flash_scan_count], part_magic, magic_len - 1) == 0) ++ { ++ kernel_part_size = flash_mem[flash_scan_count + magic_len ]; ++ kernel_part_size <<= 8; ++ kernel_part_size += flash_mem[flash_scan_count + magic_len + 2]; ++ kernel_part_size <<= 8; ++ kernel_part_size += flash_mem[flash_scan_count + magic_len + 1]; ++ kernel_part_size <<= 8; ++ kernel_part_size += flash_mem[flash_scan_count + magic_len + 3]; ++ printk(KERN_INFO "Kernel ends at 0x%.08X\n", kernel_part_size); ++ flash_scan_count = 1100000; ++ } ++ } ++ ++ ++ if(kernel_part_size){ ++ kernel_part_size = (kernel_part_size & 0xffff0000); ++ axis_default_partitions[0].size = kernel_part_size; ++ axis_default_partitions[1].size = mymtd->size - axis_default_partitions[0].size - axis_default_partitions[2].size; ++ axis_default_partitions[1].offset = axis_default_partitions[0].size; ++ } + + if (mymtd) { + mymtd->owner = THIS_MODULE; +@@ -354,21 +389,6 @@ + use_default_ptable = !ptable_ok; + } + +- if (romfs_in_flash) { +- /* Add an overlapping device for the root partition (romfs). */ +- +- axis_partitions[pidx].name = "romfs"; +- axis_partitions[pidx].size = romfs_length; +- axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR; +- axis_partitions[pidx].mask_flags |= MTD_WRITEABLE; +- +- printk(KERN_INFO +- " Adding readonly flash partition for romfs image:\n"); +- printk(pmsg, pidx, axis_partitions[pidx].offset, +- axis_partitions[pidx].size); +- pidx++; +- } +- + #ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE + if (mymtd) { + main_partition.size = mymtd->size; +@@ -391,36 +411,6 @@ + if (err) + panic("axisflashmap could not add MTD partitions!\n"); + } +- +- if (!romfs_in_flash) { +- /* Create an RAM device for the root partition (romfs). */ +- +-#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0) || (CONFIG_MTDRAM_ABS_POS != 0) +- /* No use trying to boot this kernel from RAM. Panic! */ +- printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM " +- "device due to kernel (mis)configuration!\n"); +- panic("This kernel cannot boot from RAM!\n"); +-#else +- struct mtd_info *mtd_ram; +- +- mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL); +- if (!mtd_ram) +- panic("axisflashmap couldn't allocate memory for " +- "mtd_info!\n"); +- +- printk(KERN_INFO " Adding RAM partition for romfs image:\n"); +- printk(pmsg, pidx, (unsigned)romfs_start, +- (unsigned)romfs_length); +- +- err = mtdram_init_device(mtd_ram, +- (void *)romfs_start, +- romfs_length, +- "romfs"); +- if (err) +- panic("axisflashmap could not initialize MTD RAM " +- "device!\n"); +-#endif +- } + return err; + } + +diff -Nur linux-2.6.39.orig/arch/cris/arch-v10/drivers/ds1302.c linux-2.6.39/arch/cris/arch-v10/drivers/ds1302.c +--- linux-2.6.39.orig/arch/cris/arch-v10/drivers/ds1302.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/arch-v10/drivers/ds1302.c 2011-08-25 07:43:00.339229517 +0200 +@@ -22,6 +22,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -501,6 +502,10 @@ + return 0; + } + ++#ifdef CONFIG_SYSFS ++static struct class *rtc_class; ++#endif ++ + static int __init ds1302_register(void) + { + ds1302_init(); +@@ -509,6 +514,12 @@ + ds1302_name, RTC_MAJOR_NR); + return -1; + } ++ #ifdef CONFIG_SYSFS ++ rtc_class = class_create(THIS_MODULE, "rtc"); ++ class_device_create(rtc_class, NULL, MKDEV(RTC_MAJOR_NR, 0), ++ NULL, "rtc"); ++ #endif ++ + return 0; + + } +diff -Nur linux-2.6.39.orig/arch/cris/arch-v10/drivers/gpio.c linux-2.6.39/arch/cris/arch-v10/drivers/gpio.c +--- linux-2.6.39.orig/arch/cris/arch-v10/drivers/gpio.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/arch-v10/drivers/gpio.c 2011-08-25 07:43:00.588029746 +0200 +@@ -20,6 +20,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -798,6 +799,10 @@ + + /* main driver initialization routine, called from mem.c */ + ++#ifdef CONFIG_SYSFS ++static struct class *gpio_class; ++#endif ++ + static int __init gpio_init(void) + { + int res; +@@ -811,6 +816,13 @@ + return res; + } + ++#ifdef CONFIG_SYSFS ++ gpio_class = class_create(THIS_MODULE, "gpio"); ++ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 0), NULL, "gpioa"); ++ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 1), NULL, "gpiob"); ++ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 2), NULL, "leds"); ++ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 3), NULL, "gpiog"); ++#endif + /* Clear all leds */ + #if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS) + CRIS_LED_NETWORK_SET(0); +diff -Nur linux-2.6.39.orig/arch/cris/arch-v10/lib/hw_settings.S linux-2.6.39/arch/cris/arch-v10/lib/hw_settings.S +--- linux-2.6.39.orig/arch/cris/arch-v10/lib/hw_settings.S 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/arch-v10/lib/hw_settings.S 2011-08-25 07:43:00.799228984 +0200 +@@ -58,3 +58,5 @@ + .dword R_PORT_PB_SET + .dword PB_SET_VALUE + .dword 0 ; No more register values ++ .ascii "ACME_PART_MAGIC" ++ .dword 0xdeadc0de +diff -Nur linux-2.6.39.orig/arch/cris/arch-v10/mm/init.c linux-2.6.39/arch/cris/arch-v10/mm/init.c +--- linux-2.6.39.orig/arch/cris/arch-v10/mm/init.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/arch-v10/mm/init.c 2011-08-25 07:43:01.069229695 +0200 +@@ -184,6 +184,9 @@ + + free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0); + } ++void free_initrd_mem(unsigned long start, unsigned long end) ++{ ++} + + /* Initialize remaps of some I/O-ports. It is important that this + * is called before any driver is initialized. +diff -Nur linux-2.6.39.orig/arch/cris/boot/compressed/Makefile linux-2.6.39/arch/cris/boot/compressed/Makefile +--- linux-2.6.39.orig/arch/cris/boot/compressed/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/boot/compressed/Makefile 2011-08-25 07:43:01.847994855 +0200 +@@ -18,7 +18,7 @@ + OBJECTS-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o + OBJECTS-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o + OBJECTS= $(OBJECTS-y) $(obj)/misc.o +-OBJCOPYFLAGS = -O binary --remove-section=.bss ++#OBJCOPYFLAGS = -O binary --remove-section=.bss + + quiet_cmd_image = BUILD $@ + cmd_image = cat $(obj)/decompress.bin $(obj)/piggy.gz > $@ +diff -Nur linux-2.6.39.orig/arch/cris/boot/Makefile linux-2.6.39/arch/cris/boot/Makefile +--- linux-2.6.39.orig/arch/cris/boot/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/boot/Makefile 2011-08-25 07:43:01.989240448 +0200 +@@ -5,7 +5,7 @@ + objcopyflags-$(CONFIG_ETRAX_ARCH_V10) += -R .note -R .comment + objcopyflags-$(CONFIG_ETRAX_ARCH_V32) += --remove-section=.bss --remove-section=.note.gnu.build-id + +-OBJCOPYFLAGS = -O binary $(objcopyflags-y) ++#OBJCOPYFLAGS = -O binary $(objcopyflags-y) + + + subdir- := compressed rescue +@@ -17,7 +17,6 @@ + + $(obj)/compressed/vmlinux: $(obj)/Image FORCE + $(Q)$(MAKE) $(build)=$(obj)/compressed $@ +- $(Q)$(MAKE) $(build)=$(obj)/rescue $(obj)/rescue/rescue.bin + + $(obj)/zImage: $(obj)/compressed/vmlinux + @cp $< $@ +diff -Nur linux-2.6.39.orig/arch/cris/Kconfig linux-2.6.39/arch/cris/Kconfig +--- linux-2.6.39.orig/arch/cris/Kconfig 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/Kconfig 2011-08-25 07:43:57.197980003 +0200 +@@ -168,6 +168,12 @@ + help + Size of DRAM (decimal in MB) typically 2, 8 or 16. + ++config ETRAX_MTD_SIZE ++ hex "MTD size (hex)" ++ default "0x00800000" ++ help ++ Size of MTD device typically 4 or 8 MB. ++ + config ETRAX_VMEM_SIZE + int "Video memory size (dec, in MB)" + depends on ETRAX_ARCH_V32 && !ETRAXFS +@@ -273,7 +279,7 @@ + select MTD_CFI_AMDSTD + select MTD_JEDECPROBE if ETRAX_ARCH_V32 + select MTD_CHAR +- select MTD_BLOCK ++ select MTD_BLOCK_RO + select MTD_PARTITIONS + select MTD_COMPLEX_MAPPINGS + help +@@ -660,6 +666,13 @@ + + source "drivers/ide/Kconfig" + ++#mysteriously part of this standard linux driver was removed from cris build! - info@crisos.org ++source "drivers/scsi/Kconfig" ++ ++source "drivers/media/Kconfig" ++ ++source "drivers/misc/Kconfig" ++ + source "drivers/net/Kconfig" + + source "drivers/i2c/Kconfig" +@@ -675,6 +688,8 @@ + + source "fs/Kconfig" + ++source "sound/Kconfig" ++ + source "drivers/usb/Kconfig" + + source "drivers/uwb/Kconfig" +diff -Nur linux-2.6.39.orig/arch/cris/Makefile linux-2.6.39/arch/cris/Makefile +--- linux-2.6.39.orig/arch/cris/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/Makefile 2011-08-25 07:43:02.329230084 +0200 +@@ -40,10 +40,10 @@ + + LD = $(CROSS_COMPILE)ld -mcrislinux + +-OBJCOPYFLAGS := -O binary -R .note -R .comment -S ++OBJCOPYFLAGS := -O binary -R .bss -R .note -R .note.gnu.build-id -R .comment -S + + KBUILD_AFLAGS += -mlinux -march=$(arch-y) $(inc) +-KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe $(inc) ++KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe -fno-peephole2 $(inc) + KBUILD_CPPFLAGS += $(inc) + + ifdef CONFIG_FRAME_POINTER +diff -Nur linux-2.6.39.orig/arch/cris/mm/init.c linux-2.6.39/arch/cris/mm/init.c +--- linux-2.6.39.orig/arch/cris/mm/init.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/mm/init.c 2011-08-25 07:43:02.489240456 +0200 +@@ -16,6 +16,7 @@ + DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); + + unsigned long empty_zero_page; ++EXPORT_SYMBOL(empty_zero_page); + + extern char _stext, _edata, _etext; /* From linkerscript */ + extern char __init_begin, __init_end; +@@ -81,3 +82,10 @@ + printk (KERN_INFO "Freeing unused kernel memory: %luk freed\n", + (unsigned long)((&__init_end - &__init_begin) >> 10)); + } ++ ++#ifdef CONFIG_BLK_DEV_INITRD ++void free_initrd_mem(unsigned long start, unsigned long end) ++{ ++ return 0; ++} ++#endif +diff -Nur linux-2.6.39.orig/drivers/net/cris/eth_v10.c linux-2.6.39/drivers/net/cris/eth_v10.c +--- linux-2.6.39.orig/drivers/net/cris/eth_v10.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/net/cris/eth_v10.c 2011-08-25 07:43:02.627979938 +0200 +@@ -1714,7 +1714,7 @@ + static void + e100_netpoll(struct net_device* netdev) + { +- e100rxtx_interrupt(NETWORK_DMA_TX_IRQ_NBR, netdev, NULL); ++ e100rxtx_interrupt(NETWORK_DMA_TX_IRQ_NBR, netdev); + } + #endif + +diff -Nur linux-2.6.39.orig/drivers/tty/serial/crisv10.c linux-2.6.39/drivers/tty/serial/crisv10.c +--- linux-2.6.39.orig/drivers/tty/serial/crisv10.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/tty/serial/crisv10.c 2011-08-25 07:43:02.637980323 +0200 +@@ -26,6 +26,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -4430,6 +4431,7 @@ + #endif + }; + ++static struct class *rs_class; + static int __init rs_init(void) + { + int i; +@@ -4564,6 +4566,24 @@ + #endif + #endif /* CONFIG_SVINTO_SIM */ + ++ rs_class = class_create(THIS_MODULE, "rs_tty"); ++#ifdef CONFIG_ETRAX_SERIAL_PORT0 ++ device_create(rs_class, NULL, ++ MKDEV(TTY_MAJOR, 64), NULL, "ttyS0"); ++#endif ++#ifdef CONFIG_ETRAX_SERIAL_PORT1 ++ device_create(rs_class, NULL, ++ MKDEV(TTY_MAJOR, 65), NULL, "ttyS1"); ++#endif ++#ifdef CONFIG_ETRAX_SERIAL_PORT2 ++ device_create(rs_class, NULL, ++ MKDEV(TTY_MAJOR, 66), NULL, "ttyS2"); ++#endif ++#ifdef CONFIG_ETRAX_SERIAL_PORT3 ++ device_create(rs_class, NULL, ++ MKDEV(TTY_MAJOR, 67), NULL, "ttyS3"); ++#endif ++ + return 0; + } + +diff -Nur linux-2.6.39.orig/drivers/usb/host/hc-cris-dbg.h linux-2.6.39/drivers/usb/host/hc-cris-dbg.h +--- linux-2.6.39.orig/drivers/usb/host/hc-cris-dbg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/usb/host/hc-cris-dbg.h 2011-08-25 07:43:02.837990398 +0200 +@@ -0,0 +1,146 @@ ++ ++/* macros for debug output */ ++ ++#define warn(fmt, args...) \ ++ printk(KERN_INFO "crisv10 warn: ");printk(fmt, ## args) ++ ++#define hcd_dbg(hcd, fmt, args...) \ ++ dev_info(hcd->self.controller, fmt, ## args) ++#define hcd_err(hcd, fmt, args...) \ ++ dev_err(hcd->self.controller, fmt, ## args) ++#define hcd_info(hcd, fmt, args...) \ ++ dev_info(hcd->self.controller, fmt, ## args) ++#define hcd_warn(hcd, fmt, args...) \ ++ dev_warn(hcd->self.controller, fmt, ## args) ++ ++/* ++#define devdrv_dbg(fmt, args...) \ ++ printk(KERN_INFO "usb_devdrv dbg: ");printk(fmt, ## args) ++*/ ++#define devdrv_dbg(fmt, args...) {} ++ ++#define devdrv_err(fmt, args...) \ ++ printk(KERN_ERR "usb_devdrv error: ");printk(fmt, ## args) ++#define devdrv_info(fmt, args...) \ ++ printk(KERN_INFO "usb_devdrv: ");printk(fmt, ## args) ++ ++#define irq_dbg(fmt, args...) \ ++ printk(KERN_INFO "crisv10_irq dbg: ");printk(fmt, ## args) ++#define irq_err(fmt, args...) \ ++ printk(KERN_ERR "crisv10_irq error: ");printk(fmt, ## args) ++#define irq_warn(fmt, args...) \ ++ printk(KERN_INFO "crisv10_irq warn: ");printk(fmt, ## args) ++#define irq_info(fmt, args...) \ ++ printk(KERN_INFO "crisv10_hcd: ");printk(fmt, ## args) ++ ++/* ++#define rh_dbg(fmt, args...) \ ++ printk(KERN_DEBUG "crisv10_rh dbg: ");printk(fmt, ## args) ++*/ ++#define rh_dbg(fmt, args...) {} ++ ++#define rh_err(fmt, args...) \ ++ printk(KERN_ERR "crisv10_rh error: ");printk(fmt, ## args) ++#define rh_warn(fmt, args...) \ ++ printk(KERN_INFO "crisv10_rh warning: ");printk(fmt, ## args) ++#define rh_info(fmt, args...) \ ++ printk(KERN_INFO "crisv10_rh: ");printk(fmt, ## args) ++ ++/* ++#define tc_dbg(fmt, args...) \ ++ printk(KERN_INFO "crisv10_tc dbg: ");printk(fmt, ## args) ++*/ ++#define tc_dbg(fmt, args...) {while(0){}} ++ ++#define tc_err(fmt, args...) \ ++ printk(KERN_ERR "crisv10_tc error: ");printk(fmt, ## args) ++/* ++#define tc_warn(fmt, args...) \ ++ printk(KERN_INFO "crisv10_tc warning: ");printk(fmt, ## args) ++*/ ++#define tc_warn(fmt, args...) {while(0){}} ++ ++#define tc_info(fmt, args...) \ ++ printk(KERN_INFO "crisv10_tc: ");printk(fmt, ## args) ++ ++ ++/* Debug print-outs for various traffic types */ ++ ++#define intr_warn(fmt, args...) \ ++ printk(KERN_INFO "crisv10_intr warning: ");printk(fmt, ## args) ++ ++#define intr_dbg(fmt, args...) \ ++ printk(KERN_DEBUG "crisv10_intr dbg: ");printk(fmt, ## args) ++/* ++#define intr_dbg(fmt, args...) {while(0){}} ++*/ ++ ++ ++#define isoc_err(fmt, args...) \ ++ printk(KERN_ERR "crisv10_isoc error: ");printk(fmt, ## args) ++/* ++#define isoc_warn(fmt, args...) \ ++ printk(KERN_INFO "crisv10_isoc warning: ");printk(fmt, ## args) ++*/ ++#define isoc_warn(fmt, args...) {while(0){}} ++ ++/* ++#define isoc_dbg(fmt, args...) \ ++ printk(KERN_INFO "crisv10_isoc dbg: ");printk(fmt, ## args) ++*/ ++#define isoc_dbg(fmt, args...) {while(0){}} ++ ++/* ++#define timer_warn(fmt, args...) \ ++ printk(KERN_INFO "crisv10_timer warning: ");printk(fmt, ## args) ++*/ ++#define timer_warn(fmt, args...) {while(0){}} ++ ++/* ++#define timer_dbg(fmt, args...) \ ++ printk(KERN_INFO "crisv10_timer dbg: ");printk(fmt, ## args) ++*/ ++#define timer_dbg(fmt, args...) {while(0){}} ++ ++ ++/* Debug printouts for events related to late finishing of URBs */ ++ ++#define late_dbg(fmt, args...) \ ++ printk(KERN_INFO "crisv10_late dbg: ");printk(fmt, ## args) ++/* ++#define late_dbg(fmt, args...) {while(0){}} ++*/ ++ ++#define late_warn(fmt, args...) \ ++ printk(KERN_INFO "crisv10_late warning: ");printk(fmt, ## args) ++/* ++#define errno_dbg(fmt, args...) \ ++ printk(KERN_INFO "crisv10_errno dbg: ");printk(fmt, ## args) ++*/ ++#define errno_dbg(fmt, args...) {while(0){}} ++ ++ ++#define dma_dbg(fmt, args...) \ ++ printk(KERN_INFO "crisv10_dma dbg: ");printk(fmt, ## args) ++#define dma_err(fmt, args...) \ ++ printk(KERN_ERR "crisv10_dma error: ");printk(fmt, ## args) ++#define dma_warn(fmt, args...) \ ++ printk(KERN_INFO "crisv10_dma warning: ");printk(fmt, ## args) ++#define dma_info(fmt, args...) \ ++ printk(KERN_INFO "crisv10_dma: ");printk(fmt, ## args) ++ ++ ++ ++#define str_dir(pipe) \ ++ (usb_pipeout(pipe) ? "out" : "in") ++#define str_type(pipe) \ ++ ({ \ ++ char *s = "?"; \ ++ switch (usb_pipetype(pipe)) { \ ++ case PIPE_ISOCHRONOUS: s = "iso"; break; \ ++ case PIPE_INTERRUPT: s = "intr"; break; \ ++ case PIPE_CONTROL: s = "ctrl"; break; \ ++ case PIPE_BULK: s = "bulk"; break; \ ++ }; \ ++ s; \ ++ }) +diff -Nur linux-2.6.39.orig/drivers/usb/host/hc-crisv10.c linux-2.6.39/drivers/usb/host/hc-crisv10.c +--- linux-2.6.39.orig/drivers/usb/host/hc-crisv10.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/usb/host/hc-crisv10.c 2011-08-25 07:43:02.897981683 +0200 +@@ -0,0 +1,4801 @@ ++/* ++ * ++ * ETRAX 100LX USB Host Controller Driver ++ * ++ * Copyright (C) 2005, 2006 Axis Communications AB ++ * ++ * Author: Konrad Eriksson ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "hc-crisv10.h" ++#include "hc-cris-dbg.h" ++ ++ ++/***************************************************************************/ ++/***************************************************************************/ ++/* Host Controller settings */ ++/***************************************************************************/ ++/***************************************************************************/ ++ ++#define VERSION "1.00 hinko.4" ++#define COPYRIGHT "(c) 2005, 2006 Axis Communications AB" ++#define DESCRIPTION "ETRAX 100LX USB Host Controller" ++ ++#define ETRAX_USB_HC_IRQ USB_HC_IRQ_NBR ++#define ETRAX_USB_RX_IRQ USB_DMA_RX_IRQ_NBR ++#define ETRAX_USB_TX_IRQ USB_DMA_TX_IRQ_NBR ++ ++/* Number of physical ports in Etrax 100LX */ ++#define USB_ROOT_HUB_PORTS 2 ++ ++const char hc_name[] = "hc-crisv10"; ++const char product_desc[] = DESCRIPTION; ++ ++/* The number of epids is, among other things, used for pre-allocating ++ ctrl, bulk and isoc EP descriptors (one for each epid). ++ Assumed to be > 1 when initiating the DMA lists. */ ++#define NBR_OF_EPIDS 32 ++ ++/* Support interrupt traffic intervals up to 128 ms. */ ++#define MAX_INTR_INTERVAL 128 ++ ++/* If periodic traffic (intr or isoc) is to be used, then one entry in the EP ++ table must be "invalid". By this we mean that we shouldn't care about epid ++ attentions for this epid, or at least handle them differently from epid ++ attentions for "valid" epids. This define determines which one to use ++ (don't change it). */ ++#define INVALID_EPID 31 ++/* A special epid for the bulk dummys. */ ++#define DUMMY_EPID 30 ++ ++/* Module settings */ ++ ++MODULE_DESCRIPTION(DESCRIPTION); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Konrad Eriksson "); ++ ++ ++/* Module parameters */ ++ ++/* 0 = No ports enabled ++ 1 = Only port 1 enabled (on board ethernet on devboard) ++ 2 = Only port 2 enabled (external connector on devboard) ++ 3 = Both ports enabled ++*/ ++static unsigned int ports = 3; ++module_param(ports, uint, S_IRUGO); ++MODULE_PARM_DESC(ports, "Bitmask indicating USB ports to use"); ++ ++ ++/***************************************************************************/ ++/***************************************************************************/ ++/* Shared global variables for this module */ ++/***************************************************************************/ ++/***************************************************************************/ ++ ++/* EP descriptor lists for non period transfers. Must be 32-bit aligned. */ ++static volatile struct USB_EP_Desc TxBulkEPList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); ++ ++static volatile struct USB_EP_Desc TxCtrlEPList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); ++ ++/* EP descriptor lists for period transfers. Must be 32-bit aligned. */ ++static volatile struct USB_EP_Desc TxIntrEPList[MAX_INTR_INTERVAL] __attribute__ ((aligned (4))); ++static volatile struct USB_SB_Desc TxIntrSB_zout __attribute__ ((aligned (4))); ++ ++static volatile struct USB_EP_Desc TxIsocEPList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); ++static volatile struct USB_SB_Desc TxIsocSB_zout __attribute__ ((aligned (4))); ++ ++//static volatile struct USB_SB_Desc TxIsocSBList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); ++ ++/* After each enabled bulk EP IN we put two disabled EP descriptors with the eol flag set, ++ causing the DMA to stop the DMA channel. The first of these two has the intr flag set, which ++ gives us a dma8_sub0_descr interrupt. When we receive this, we advance the DMA one step in the ++ EP list and then restart the bulk channel, thus forcing a switch between bulk EP descriptors ++ in each frame. */ ++static volatile struct USB_EP_Desc TxBulkDummyEPList[NBR_OF_EPIDS][2] __attribute__ ((aligned (4))); ++ ++/* List of URB pointers, where each points to the active URB for a epid. ++ For Bulk, Ctrl and Intr this means which URB that currently is added to ++ DMA lists (Isoc URBs are all directly added to DMA lists). As soon as ++ URB has completed is the queue examined and the first URB in queue is ++ removed and moved to the activeUrbList while its state change to STARTED and ++ its transfer(s) gets added to DMA list (exception Isoc where URBs enter ++ state STARTED directly and added transfers added to DMA lists). */ ++static struct urb *activeUrbList[NBR_OF_EPIDS]; ++ ++/* Additional software state info for each epid */ ++static struct etrax_epid epid_state[NBR_OF_EPIDS]; ++ ++/* Timer handles for bulk traffic timer used to avoid DMA bug where DMA stops ++ even if there is new data waiting to be processed */ ++static struct timer_list bulk_start_timer = TIMER_INITIALIZER(NULL, 0, 0); ++static struct timer_list bulk_eot_timer = TIMER_INITIALIZER(NULL, 0, 0); ++ ++/* We want the start timer to expire before the eot timer, because the former ++ might start traffic, thus making it unnecessary for the latter to time ++ out. */ ++#define BULK_START_TIMER_INTERVAL (HZ/50) /* 20 ms */ ++#define BULK_EOT_TIMER_INTERVAL (HZ/16) /* 60 ms */ ++ ++/* Delay before a URB completion happen when it's scheduled to be delayed */ ++#define LATER_TIMER_DELAY (HZ/50) /* 20 ms */ ++ ++/* Simplifying macros for checking software state info of a epid */ ++/* ----------------------------------------------------------------------- */ ++#define epid_inuse(epid) epid_state[epid].inuse ++#define epid_out_traffic(epid) epid_state[epid].out_traffic ++#define epid_isoc(epid) (epid_state[epid].type == PIPE_ISOCHRONOUS ? 1 : 0) ++#define epid_intr(epid) (epid_state[epid].type == PIPE_INTERRUPT ? 1 : 0) ++ ++ ++/***************************************************************************/ ++/***************************************************************************/ ++/* DEBUG FUNCTIONS */ ++/***************************************************************************/ ++/***************************************************************************/ ++/* Note that these functions are always available in their "__" variants, ++ for use in error situations. The "__" missing variants are controlled by ++ the USB_DEBUG_DESC/USB_DEBUG_URB macros. */ ++static void __dump_urb(struct urb* purb) ++{ ++ struct crisv10_urb_priv *urb_priv = purb->hcpriv; ++ int urb_num = -1; ++ if(urb_priv) { ++ urb_num = urb_priv->urb_num; ++ } ++ printk("\nURB:0x%x[%d]\n", (unsigned int)purb, urb_num); ++ printk("dev :0x%08lx\n", (unsigned long)purb->dev); ++ printk("pipe :0x%08x\n", purb->pipe); ++ printk("status :%d\n", purb->status); ++ printk("transfer_flags :0x%08x\n", purb->transfer_flags); ++ printk("transfer_buffer :0x%08lx\n", (unsigned long)purb->transfer_buffer); ++ printk("transfer_buffer_length:%d\n", purb->transfer_buffer_length); ++ printk("actual_length :%d\n", purb->actual_length); ++ printk("setup_packet :0x%08lx\n", (unsigned long)purb->setup_packet); ++ printk("start_frame :%d\n", purb->start_frame); ++ printk("number_of_packets :%d\n", purb->number_of_packets); ++ printk("interval :%d\n", purb->interval); ++ printk("error_count :%d\n", purb->error_count); ++ printk("context :0x%08lx\n", (unsigned long)purb->context); ++ printk("complete :0x%08lx\n\n", (unsigned long)purb->complete); ++} ++ ++static void __dump_in_desc(volatile struct USB_IN_Desc *in) ++{ ++ printk("\nUSB_IN_Desc at 0x%08lx\n", (unsigned long)in); ++ printk(" sw_len : 0x%04x (%d)\n", in->sw_len, in->sw_len); ++ printk(" command : 0x%04x\n", in->command); ++ printk(" next : 0x%08lx\n", in->next); ++ printk(" buf : 0x%08lx\n", in->buf); ++ printk(" hw_len : 0x%04x (%d)\n", in->hw_len, in->hw_len); ++ printk(" status : 0x%04x\n\n", in->status); ++} ++ ++static void __dump_sb_desc(volatile struct USB_SB_Desc *sb) ++{ ++ char tt = (sb->command & 0x30) >> 4; ++ char *tt_string; ++ ++ switch (tt) { ++ case 0: ++ tt_string = "zout"; ++ break; ++ case 1: ++ tt_string = "in"; ++ break; ++ case 2: ++ tt_string = "out"; ++ break; ++ case 3: ++ tt_string = "setup"; ++ break; ++ default: ++ tt_string = "unknown (weird)"; ++ } ++ ++ printk(" USB_SB_Desc at 0x%08lx ", (unsigned long)sb); ++ printk(" command:0x%04x (", sb->command); ++ printk("rem:%d ", (sb->command & 0x3f00) >> 8); ++ printk("full:%d ", (sb->command & 0x40) >> 6); ++ printk("tt:%d(%s) ", tt, tt_string); ++ printk("intr:%d ", (sb->command & 0x8) >> 3); ++ printk("eot:%d ", (sb->command & 0x2) >> 1); ++ printk("eol:%d)", sb->command & 0x1); ++ printk(" sw_len:0x%04x(%d)", sb->sw_len, sb->sw_len); ++ printk(" next:0x%08lx", sb->next); ++ printk(" buf:0x%08lx\n", sb->buf); ++} ++ ++ ++static void __dump_ep_desc(volatile struct USB_EP_Desc *ep) ++{ ++ printk("USB_EP_Desc at 0x%08lx ", (unsigned long)ep); ++ printk(" command:0x%04x (", ep->command); ++ printk("ep_id:%d ", (ep->command & 0x1f00) >> 8); ++ printk("enable:%d ", (ep->command & 0x10) >> 4); ++ printk("intr:%d ", (ep->command & 0x8) >> 3); ++ printk("eof:%d ", (ep->command & 0x2) >> 1); ++ printk("eol:%d)", ep->command & 0x1); ++ printk(" hw_len:0x%04x(%d)", ep->hw_len, ep->hw_len); ++ printk(" next:0x%08lx", ep->next); ++ printk(" sub:0x%08lx\n", ep->sub); ++} ++ ++static inline void __dump_ep_list(int pipe_type) ++{ ++ volatile struct USB_EP_Desc *ep; ++ volatile struct USB_EP_Desc *first_ep; ++ volatile struct USB_SB_Desc *sb; ++ ++ switch (pipe_type) ++ { ++ case PIPE_BULK: ++ first_ep = &TxBulkEPList[0]; ++ break; ++ case PIPE_CONTROL: ++ first_ep = &TxCtrlEPList[0]; ++ break; ++ case PIPE_INTERRUPT: ++ first_ep = &TxIntrEPList[0]; ++ break; ++ case PIPE_ISOCHRONOUS: ++ first_ep = &TxIsocEPList[0]; ++ break; ++ default: ++ warn("Cannot dump unknown traffic type"); ++ return; ++ } ++ ep = first_ep; ++ ++ printk("\n\nDumping EP list...\n\n"); ++ ++ do { ++ __dump_ep_desc(ep); ++ /* Cannot phys_to_virt on 0 as it turns into 80000000, which is != 0. */ ++ sb = ep->sub ? phys_to_virt(ep->sub) : 0; ++ while (sb) { ++ __dump_sb_desc(sb); ++ sb = sb->next ? phys_to_virt(sb->next) : 0; ++ } ++ ep = (volatile struct USB_EP_Desc *)(phys_to_virt(ep->next)); ++ ++ } while (ep != first_ep); ++} ++ ++static inline void __dump_ept_data(int epid) ++{ ++ unsigned long flags; ++ __u32 r_usb_ept_data; ++ ++ if (epid < 0 || epid > 31) { ++ printk("Cannot dump ept data for invalid epid %d\n", epid); ++ return; ++ } ++ ++ local_irq_save(flags); ++ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, epid); ++ nop(); ++ r_usb_ept_data = *R_USB_EPT_DATA; ++ local_irq_restore(flags); ++ ++ printk(" R_USB_EPT_DATA = 0x%x for epid %d :\n", r_usb_ept_data, epid); ++ if (r_usb_ept_data == 0) { ++ /* No need for more detailed printing. */ ++ return; ++ } ++ printk(" valid : %d\n", (r_usb_ept_data & 0x80000000) >> 31); ++ printk(" hold : %d\n", (r_usb_ept_data & 0x40000000) >> 30); ++ printk(" error_count_in : %d\n", (r_usb_ept_data & 0x30000000) >> 28); ++ printk(" t_in : %d\n", (r_usb_ept_data & 0x08000000) >> 27); ++ printk(" low_speed : %d\n", (r_usb_ept_data & 0x04000000) >> 26); ++ printk(" port : %d\n", (r_usb_ept_data & 0x03000000) >> 24); ++ printk(" error_code : %d\n", (r_usb_ept_data & 0x00c00000) >> 22); ++ printk(" t_out : %d\n", (r_usb_ept_data & 0x00200000) >> 21); ++ printk(" error_count_out : %d\n", (r_usb_ept_data & 0x00180000) >> 19); ++ printk(" max_len : %d\n", (r_usb_ept_data & 0x0003f800) >> 11); ++ printk(" ep : %d\n", (r_usb_ept_data & 0x00000780) >> 7); ++ printk(" dev : %d\n", (r_usb_ept_data & 0x0000003f)); ++} ++ ++static inline void __dump_ept_data_iso(int epid) ++{ ++ unsigned long flags; ++ __u32 ept_data; ++ ++ if (epid < 0 || epid > 31) { ++ printk("Cannot dump ept data for invalid epid %d\n", epid); ++ return; ++ } ++ ++ local_irq_save(flags); ++ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, epid); ++ nop(); ++ ept_data = *R_USB_EPT_DATA_ISO; ++ local_irq_restore(flags); ++ ++ printk(" R_USB_EPT_DATA = 0x%x for epid %d :\n", ept_data, epid); ++ if (ept_data == 0) { ++ /* No need for more detailed printing. */ ++ return; ++ } ++ printk(" valid : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, valid, ++ ept_data)); ++ printk(" port : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, port, ++ ept_data)); ++ printk(" error_code : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, error_code, ++ ept_data)); ++ printk(" max_len : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, max_len, ++ ept_data)); ++ printk(" ep : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, ep, ++ ept_data)); ++ printk(" dev : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, dev, ++ ept_data)); ++} ++ ++static inline void __dump_ept_data_list(void) ++{ ++ int i; ++ ++ printk("Dumping the whole R_USB_EPT_DATA list\n"); ++ ++ for (i = 0; i < 32; i++) { ++ __dump_ept_data(i); ++ } ++} ++ ++static void debug_epid(int epid) { ++ int i; ++ ++ if(epid_isoc(epid)) { ++ __dump_ept_data_iso(epid); ++ } else { ++ __dump_ept_data(epid); ++ } ++ ++ printk("Bulk:\n"); ++ for(i = 0; i < 32; i++) { ++ if(IO_EXTRACT(USB_EP_command, epid, TxBulkEPList[i].command) == ++ epid) { ++ printk("%d: ", i); __dump_ep_desc(&(TxBulkEPList[i])); ++ } ++ } ++ ++ printk("Ctrl:\n"); ++ for(i = 0; i < 32; i++) { ++ if(IO_EXTRACT(USB_EP_command, epid, TxCtrlEPList[i].command) == ++ epid) { ++ printk("%d: ", i); __dump_ep_desc(&(TxCtrlEPList[i])); ++ } ++ } ++ ++ printk("Intr:\n"); ++ for(i = 0; i < MAX_INTR_INTERVAL; i++) { ++ if(IO_EXTRACT(USB_EP_command, epid, TxIntrEPList[i].command) == ++ epid) { ++ printk("%d: ", i); __dump_ep_desc(&(TxIntrEPList[i])); ++ } ++ } ++ ++ printk("Isoc:\n"); ++ for(i = 0; i < 32; i++) { ++ if(IO_EXTRACT(USB_EP_command, epid, TxIsocEPList[i].command) == ++ epid) { ++ printk("%d: ", i); __dump_ep_desc(&(TxIsocEPList[i])); ++ } ++ } ++ ++ __dump_ept_data_list(); ++ __dump_ep_list(PIPE_INTERRUPT); ++ printk("\n\n"); ++} ++ ++ ++ ++char* hcd_status_to_str(__u8 bUsbStatus) { ++ static char hcd_status_str[128]; ++ hcd_status_str[0] = '\0'; ++ if(bUsbStatus & IO_STATE(R_USB_STATUS, ourun, yes)) { ++ strcat(hcd_status_str, "ourun "); ++ } ++ if(bUsbStatus & IO_STATE(R_USB_STATUS, perror, yes)) { ++ strcat(hcd_status_str, "perror "); ++ } ++ if(bUsbStatus & IO_STATE(R_USB_STATUS, device_mode, yes)) { ++ strcat(hcd_status_str, "device_mode "); ++ } ++ if(bUsbStatus & IO_STATE(R_USB_STATUS, host_mode, yes)) { ++ strcat(hcd_status_str, "host_mode "); ++ } ++ if(bUsbStatus & IO_STATE(R_USB_STATUS, started, yes)) { ++ strcat(hcd_status_str, "started "); ++ } ++ if(bUsbStatus & IO_STATE(R_USB_STATUS, running, yes)) { ++ strcat(hcd_status_str, "running "); ++ } ++ return hcd_status_str; ++} ++ ++ ++char* sblist_to_str(struct USB_SB_Desc* sb_desc) { ++ static char sblist_to_str_buff[128]; ++ char tmp[32], tmp2[32]; ++ sblist_to_str_buff[0] = '\0'; ++ while(sb_desc != NULL) { ++ switch(IO_EXTRACT(USB_SB_command, tt, sb_desc->command)) { ++ case 0: sprintf(tmp, "zout"); break; ++ case 1: sprintf(tmp, "in"); break; ++ case 2: sprintf(tmp, "out"); break; ++ case 3: sprintf(tmp, "setup"); break; ++ } ++ sprintf(tmp2, "(%s %d)", tmp, sb_desc->sw_len); ++ strcat(sblist_to_str_buff, tmp2); ++ if(sb_desc->next != 0) { ++ sb_desc = phys_to_virt(sb_desc->next); ++ } else { ++ sb_desc = NULL; ++ } ++ } ++ return sblist_to_str_buff; ++} ++ ++char* port_status_to_str(__u16 wPortStatus) { ++ static char port_status_str[128]; ++ port_status_str[0] = '\0'; ++ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, connected, yes)) { ++ strcat(port_status_str, "connected "); ++ } ++ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, enabled, yes)) { ++ strcat(port_status_str, "enabled "); ++ } ++ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, suspended, yes)) { ++ strcat(port_status_str, "suspended "); ++ } ++ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, reset, yes)) { ++ strcat(port_status_str, "reset "); ++ } ++ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, speed, full)) { ++ strcat(port_status_str, "full-speed "); ++ } else { ++ strcat(port_status_str, "low-speed "); ++ } ++ return port_status_str; ++} ++ ++ ++char* endpoint_to_str(struct usb_endpoint_descriptor *ed) { ++ static char endpoint_to_str_buff[128]; ++ char tmp[32]; ++ int epnum = ed->bEndpointAddress & 0x0F; ++ int dir = ed->bEndpointAddress & 0x80; ++ int type = ed->bmAttributes & 0x03; ++ endpoint_to_str_buff[0] = '\0'; ++ sprintf(endpoint_to_str_buff, "ep:%d ", epnum); ++ switch(type) { ++ case 0: ++ sprintf(tmp, " ctrl"); ++ break; ++ case 1: ++ sprintf(tmp, " isoc"); ++ break; ++ case 2: ++ sprintf(tmp, " bulk"); ++ break; ++ case 3: ++ sprintf(tmp, " intr"); ++ break; ++ } ++ strcat(endpoint_to_str_buff, tmp); ++ if(dir) { ++ sprintf(tmp, " in"); ++ } else { ++ sprintf(tmp, " out"); ++ } ++ strcat(endpoint_to_str_buff, tmp); ++ ++ return endpoint_to_str_buff; ++} ++ ++/* Debug helper functions for Transfer Controller */ ++char* pipe_to_str(unsigned int pipe) { ++ static char pipe_to_str_buff[128]; ++ char tmp[64]; ++ sprintf(pipe_to_str_buff, "dir:%s", str_dir(pipe)); ++ sprintf(tmp, " type:%s", str_type(pipe)); ++ strcat(pipe_to_str_buff, tmp); ++ ++ sprintf(tmp, " dev:%d", usb_pipedevice(pipe)); ++ strcat(pipe_to_str_buff, tmp); ++ sprintf(tmp, " ep:%d", usb_pipeendpoint(pipe)); ++ strcat(pipe_to_str_buff, tmp); ++ return pipe_to_str_buff; ++} ++ ++ ++#define USB_DEBUG_DESC 1 ++ ++#ifdef USB_DEBUG_DESC ++#define dump_in_desc(x) __dump_in_desc(x) ++#define dump_sb_desc(...) __dump_sb_desc(...) ++#define dump_ep_desc(x) __dump_ep_desc(x) ++#define dump_ept_data(x) __dump_ept_data(x) ++#else ++#define dump_in_desc(...) do {} while (0) ++#define dump_sb_desc(...) do {} while (0) ++#define dump_ep_desc(...) do {} while (0) ++#endif ++ ++ ++/* Uncomment this to enable massive function call trace ++ #define USB_DEBUG_TRACE */ ++//#define USB_DEBUG_TRACE 1 ++ ++#ifdef USB_DEBUG_TRACE ++#define DBFENTER (printk(": Entering: %s\n", __FUNCTION__)) ++#define DBFEXIT (printk(": Exiting: %s\n", __FUNCTION__)) ++#else ++#define DBFENTER do {} while (0) ++#define DBFEXIT do {} while (0) ++#endif ++ ++#define CHECK_ALIGN(x) if (((__u32)(x)) & 0x00000003) \ ++{panic("Alignment check (DWORD) failed at %s:%s:%d\n", __FILE__, __FUNCTION__, __LINE__);} ++ ++/* Most helpful debugging aid */ ++#define ASSERT(expr) ((void) ((expr) ? 0 : (err("assert failed at: %s %d",__FUNCTION__, __LINE__)))) ++ ++ ++/***************************************************************************/ ++/***************************************************************************/ ++/* Forward declarations */ ++/***************************************************************************/ ++/***************************************************************************/ ++void crisv10_hcd_epid_attn_irq(struct crisv10_irq_reg *reg); ++void crisv10_hcd_port_status_irq(struct crisv10_irq_reg *reg); ++void crisv10_hcd_ctl_status_irq(struct crisv10_irq_reg *reg); ++void crisv10_hcd_isoc_eof_irq(struct crisv10_irq_reg *reg); ++ ++void rh_port_status_change(__u16[]); ++int rh_clear_port_feature(__u8, __u16); ++int rh_set_port_feature(__u8, __u16); ++static void rh_disable_port(unsigned int port); ++ ++static void check_finished_bulk_tx_epids(struct usb_hcd *hcd, ++ int timer); ++ ++//static int tc_setup_epid(struct usb_host_endpoint *ep, struct urb *urb, ++// int mem_flags); ++static int tc_setup_epid(struct urb *urb, int mem_flags); ++static void tc_free_epid(struct usb_host_endpoint *ep); ++static int tc_allocate_epid(void); ++static void tc_finish_urb(struct usb_hcd *hcd, struct urb *urb, int status); ++static void tc_finish_urb_later(struct usb_hcd *hcd, struct urb *urb, ++ int status); ++ ++static int urb_priv_create(struct usb_hcd *hcd, struct urb *urb, int epid, ++ int mem_flags); ++static void urb_priv_free(struct usb_hcd *hcd, struct urb *urb); ++ ++static inline struct urb *urb_list_first(int epid); ++static inline void urb_list_add(struct urb *urb, int epid, ++ int mem_flags); ++static inline urb_entry_t *urb_list_entry(struct urb *urb, int epid); ++static inline void urb_list_del(struct urb *urb, int epid); ++static inline void urb_list_move_last(struct urb *urb, int epid); ++static inline struct urb *urb_list_next(struct urb *urb, int epid); ++ ++int create_sb_for_urb(struct urb *urb, int mem_flags); ++int init_intr_urb(struct urb *urb, int mem_flags); ++ ++static inline void etrax_epid_set(__u8 index, __u32 data); ++static inline void etrax_epid_clear_error(__u8 index); ++static inline void etrax_epid_set_toggle(__u8 index, __u8 dirout, ++ __u8 toggle); ++static inline __u8 etrax_epid_get_toggle(__u8 index, __u8 dirout); ++static inline __u32 etrax_epid_get(__u8 index); ++ ++/* We're accessing the same register position in Etrax so ++ when we do full access the internal difference doesn't matter */ ++#define etrax_epid_iso_set(index, data) etrax_epid_set(index, data) ++#define etrax_epid_iso_get(index) etrax_epid_get(index) ++ ++ ++//static void tc_dma_process_isoc_urb(struct urb *urb); ++static void tc_dma_process_queue(int epid); ++static void tc_dma_unlink_intr_urb(struct urb *urb); ++static irqreturn_t tc_dma_tx_interrupt(int irq, void *vhc); ++static irqreturn_t tc_dma_rx_interrupt(int irq, void *vhc); ++ ++static void tc_bulk_start_timer_func(unsigned long dummy); ++static void tc_bulk_eot_timer_func(unsigned long dummy); ++ ++ ++/*************************************************************/ ++/*************************************************************/ ++/* Host Controler Driver block */ ++/*************************************************************/ ++/*************************************************************/ ++ ++/* HCD operations */ ++static irqreturn_t crisv10_hcd_top_irq(int irq, void*); ++static int crisv10_hcd_reset(struct usb_hcd *); ++static int crisv10_hcd_start(struct usb_hcd *); ++static void crisv10_hcd_stop(struct usb_hcd *); ++#ifdef CONFIG_PM ++static int crisv10_hcd_suspend(struct device *, u32, u32); ++static int crisv10_hcd_resume(struct device *, u32); ++#endif /* CONFIG_PM */ ++static int crisv10_hcd_get_frame(struct usb_hcd *); ++ ++//static int tc_urb_enqueue(struct usb_hcd *, struct usb_host_endpoint *ep, struct urb *, gfp_t mem_flags); ++static int tc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); ++//static int tc_urb_dequeue(struct usb_hcd *, struct urb *); ++static int tc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); ++static void tc_endpoint_disable(struct usb_hcd *, struct usb_host_endpoint *ep); ++ ++static int rh_status_data_request(struct usb_hcd *, char *); ++static int rh_control_request(struct usb_hcd *, u16, u16, u16, char*, u16); ++ ++#ifdef CONFIG_PM ++static int crisv10_hcd_hub_suspend(struct usb_hcd *); ++static int crisv10_hcd_hub_resume(struct usb_hcd *); ++#endif /* CONFIG_PM */ ++#ifdef CONFIG_USB_OTG ++static int crisv10_hcd_start_port_reset(struct usb_hcd *, unsigned); ++#endif /* CONFIG_USB_OTG */ ++ ++/* host controller driver interface */ ++static const struct hc_driver crisv10_hc_driver = ++ { ++ .description = hc_name, ++ .product_desc = product_desc, ++ .hcd_priv_size = sizeof(struct crisv10_hcd), ++ ++ /* Attaching IRQ handler manualy in probe() */ ++ /* .irq = crisv10_hcd_irq, */ ++ ++ .flags = HCD_USB11, ++ ++ /* called to init HCD and root hub */ ++ .reset = crisv10_hcd_reset, ++ .start = crisv10_hcd_start, ++ ++ /* cleanly make HCD stop writing memory and doing I/O */ ++ .stop = crisv10_hcd_stop, ++ ++ /* return current frame number */ ++ .get_frame_number = crisv10_hcd_get_frame, ++ ++ ++ /* Manage i/o requests via the Transfer Controller */ ++ .urb_enqueue = tc_urb_enqueue, ++ .urb_dequeue = tc_urb_dequeue, ++ ++ /* hw synch, freeing endpoint resources that urb_dequeue can't */ ++ .endpoint_disable = tc_endpoint_disable, ++ ++ ++ /* Root Hub support */ ++ .hub_status_data = rh_status_data_request, ++ .hub_control = rh_control_request, ++#ifdef CONFIG_PM ++ .hub_suspend = rh_suspend_request, ++ .hub_resume = rh_resume_request, ++#endif /* CONFIG_PM */ ++#ifdef CONFIG_USB_OTG ++ .start_port_reset = crisv10_hcd_start_port_reset, ++#endif /* CONFIG_USB_OTG */ ++ }; ++ ++ ++/* ++ * conversion between pointers to a hcd and the corresponding ++ * crisv10_hcd ++ */ ++ ++static inline struct crisv10_hcd *hcd_to_crisv10_hcd(struct usb_hcd *hcd) ++{ ++ return (struct crisv10_hcd *) hcd->hcd_priv; ++} ++ ++static inline struct usb_hcd *crisv10_hcd_to_hcd(struct crisv10_hcd *hcd) ++{ ++ return container_of((void *) hcd, struct usb_hcd, hcd_priv); ++} ++ ++/* check if specified port is in use */ ++static inline int port_in_use(unsigned int port) ++{ ++ return ports & (1 << port); ++} ++ ++/* number of ports in use */ ++static inline unsigned int num_ports(void) ++{ ++ unsigned int i, num = 0; ++ for (i = 0; i < USB_ROOT_HUB_PORTS; i++) ++ if (port_in_use(i)) ++ num++; ++ return num; ++} ++ ++/* map hub port number to the port number used internally by the HC */ ++static inline unsigned int map_port(unsigned int port) ++{ ++ unsigned int i, num = 0; ++ for (i = 0; i < USB_ROOT_HUB_PORTS; i++) ++ if (port_in_use(i)) ++ if (++num == port) ++ return i; ++ return -1; ++} ++ ++/* size of descriptors in slab cache */ ++#ifndef MAX ++#define MAX(x, y) ((x) > (y) ? (x) : (y)) ++#endif ++ ++ ++/******************************************************************/ ++/* Hardware Interrupt functions */ ++/******************************************************************/ ++ ++/* Fast interrupt handler for HC */ ++static irqreturn_t crisv10_hcd_top_irq(int irq, void *vcd) ++{ ++ struct usb_hcd *hcd = vcd; ++ struct crisv10_irq_reg reg; ++ __u32 irq_mask; ++ unsigned long flags; ++ ++ DBFENTER; ++ ++ ASSERT(hcd != NULL); ++ reg.hcd = hcd; ++ ++ /* Turn of other interrupts while handling these sensitive cases */ ++ local_irq_save(flags); ++ ++ /* Read out which interrupts that are flaged */ ++ irq_mask = *R_USB_IRQ_MASK_READ; ++ reg.r_usb_irq_mask_read = irq_mask; ++ ++ /* Reading R_USB_STATUS clears the ctl_status interrupt. Note that ++ R_USB_STATUS must be read before R_USB_EPID_ATTN since reading the latter ++ clears the ourun and perror fields of R_USB_STATUS. */ ++ reg.r_usb_status = *R_USB_STATUS; ++ ++ /* Reading R_USB_EPID_ATTN clears the iso_eof, bulk_eot and epid_attn ++ interrupts. */ ++ reg.r_usb_epid_attn = *R_USB_EPID_ATTN; ++ ++ /* Reading R_USB_RH_PORT_STATUS_1 and R_USB_RH_PORT_STATUS_2 clears the ++ port_status interrupt. */ ++ reg.r_usb_rh_port_status_1 = *R_USB_RH_PORT_STATUS_1; ++ reg.r_usb_rh_port_status_2 = *R_USB_RH_PORT_STATUS_2; ++ ++ /* Reading R_USB_FM_NUMBER clears the sof interrupt. */ ++ /* Note: the lower 11 bits contain the actual frame number, sent with each ++ sof. */ ++ reg.r_usb_fm_number = *R_USB_FM_NUMBER; ++ ++ /* Interrupts are handled in order of priority. */ ++ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, port_status)) { ++ crisv10_hcd_port_status_irq(®); ++ } ++ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, epid_attn)) { ++ crisv10_hcd_epid_attn_irq(®); ++ } ++ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, ctl_status)) { ++ crisv10_hcd_ctl_status_irq(®); ++ } ++ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, iso_eof)) { ++ crisv10_hcd_isoc_eof_irq(®); ++ } ++ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, bulk_eot)) { ++ /* Update/restart the bulk start timer since obviously the channel is ++ running. */ ++ mod_timer(&bulk_start_timer, jiffies + BULK_START_TIMER_INTERVAL); ++ /* Update/restart the bulk eot timer since we just received an bulk eot ++ interrupt. */ ++ mod_timer(&bulk_eot_timer, jiffies + BULK_EOT_TIMER_INTERVAL); ++ ++ /* Check for finished bulk transfers on epids */ ++ check_finished_bulk_tx_epids(hcd, 0); ++ } ++ local_irq_restore(flags); ++ ++ DBFEXIT; ++ return IRQ_HANDLED; ++} ++ ++ ++void crisv10_hcd_epid_attn_irq(struct crisv10_irq_reg *reg) { ++ struct usb_hcd *hcd = reg->hcd; ++ struct crisv10_urb_priv *urb_priv; ++ int epid; ++ DBFENTER; ++ ++ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { ++ if (test_bit(epid, (void *)®->r_usb_epid_attn)) { ++ struct urb *urb; ++ __u32 ept_data; ++ int error_code; ++ ++ if (epid == DUMMY_EPID || epid == INVALID_EPID) { ++ /* We definitely don't care about these ones. Besides, they are ++ always disabled, so any possible disabling caused by the ++ epid attention interrupt is irrelevant. */ ++ warn("Got epid_attn for INVALID_EPID or DUMMY_EPID (%d).", epid); ++ continue; ++ } ++ ++ if(!epid_inuse(epid)) { ++ irq_err("Epid attention on epid:%d that isn't in use\n", epid); ++ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); ++ debug_epid(epid); ++ continue; ++ } ++ ++ /* Note that although there are separate R_USB_EPT_DATA and ++ R_USB_EPT_DATA_ISO registers, they are located at the same address and ++ are of the same size. In other words, this read should be ok for isoc ++ also. */ ++ ept_data = etrax_epid_get(epid); ++ error_code = IO_EXTRACT(R_USB_EPT_DATA, error_code, ept_data); ++ ++ /* Get the active URB for this epid. We blatantly assume ++ that only this URB could have caused the epid attention. */ ++ urb = activeUrbList[epid]; ++ if (urb == NULL) { ++ irq_err("Attention on epid:%d error:%d with no active URB.\n", ++ epid, error_code); ++ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); ++ debug_epid(epid); ++ continue; ++ } ++ ++ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; ++ ASSERT(urb_priv); ++ ++ /* Using IO_STATE_VALUE on R_USB_EPT_DATA should be ok for isoc also. */ ++ if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { ++ ++ /* Isoc traffic doesn't have error_count_in/error_count_out. */ ++ if ((usb_pipetype(urb->pipe) != PIPE_ISOCHRONOUS) && ++ (IO_EXTRACT(R_USB_EPT_DATA, error_count_in, ept_data) == 3 || ++ IO_EXTRACT(R_USB_EPT_DATA, error_count_out, ept_data) == 3)) { ++ /* Check if URB allready is marked for late-finish, we can get ++ several 3rd error for Intr traffic when a device is unplugged */ ++ if(urb_priv->later_data == NULL) { ++ /* 3rd error. */ ++ irq_warn("3rd error for epid:%d (%s %s) URB:0x%x[%d]\n", epid, ++ str_dir(urb->pipe), str_type(urb->pipe), ++ (unsigned int)urb, urb_priv->urb_num); ++ ++ tc_finish_urb_later(hcd, urb, -EPROTO); ++ } ++ ++ } else if (reg->r_usb_status & IO_MASK(R_USB_STATUS, perror)) { ++ irq_warn("Perror for epid:%d\n", epid); ++ printk("FM_NUMBER: %d\n", reg->r_usb_fm_number & 0x7ff); ++ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); ++ __dump_urb(urb); ++ debug_epid(epid); ++ ++ if (!(ept_data & IO_MASK(R_USB_EPT_DATA, valid))) { ++ /* invalid ep_id */ ++ panic("Perror because of invalid epid." ++ " Deconfigured too early?"); ++ } else { ++ /* past eof1, near eof, zout transfer, setup transfer */ ++ /* Dump the urb and the relevant EP descriptor. */ ++ panic("Something wrong with DMA descriptor contents." ++ " Too much traffic inserted?"); ++ } ++ } else if (reg->r_usb_status & IO_MASK(R_USB_STATUS, ourun)) { ++ /* buffer ourun */ ++ printk("FM_NUMBER: %d\n", reg->r_usb_fm_number & 0x7ff); ++ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); ++ __dump_urb(urb); ++ debug_epid(epid); ++ ++ panic("Buffer overrun/underrun for epid:%d. DMA too busy?", epid); ++ } else { ++ irq_warn("Attention on epid:%d (%s %s) with no error code\n", epid, ++ str_dir(urb->pipe), str_type(urb->pipe)); ++ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); ++ __dump_urb(urb); ++ debug_epid(epid); ++ } ++ ++ } else if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, ++ stall)) { ++ /* Not really a protocol error, just says that the endpoint gave ++ a stall response. Note that error_code cannot be stall for isoc. */ ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ panic("Isoc traffic cannot stall"); ++ } ++ ++ tc_dbg("Stall for epid:%d (%s %s) URB:0x%x\n", epid, ++ str_dir(urb->pipe), str_type(urb->pipe), (unsigned int)urb); ++ tc_finish_urb(hcd, urb, -EPIPE); ++ ++ } else if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, ++ bus_error)) { ++ /* Two devices responded to a transaction request. Must be resolved ++ by software. FIXME: Reset ports? */ ++ panic("Bus error for epid %d." ++ " Two devices responded to transaction request\n", ++ epid); ++ ++ } else if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, ++ buffer_error)) { ++ /* DMA overrun or underrun. */ ++ irq_warn("Buffer overrun/underrun for epid:%d (%s %s)\n", epid, ++ str_dir(urb->pipe), str_type(urb->pipe)); ++ ++ /* It seems that error_code = buffer_error in ++ R_USB_EPT_DATA/R_USB_EPT_DATA_ISO and ourun = yes in R_USB_STATUS ++ are the same error. */ ++ tc_finish_urb(hcd, urb, -EPROTO); ++ } else { ++ irq_warn("Unknown attention on epid:%d (%s %s)\n", epid, ++ str_dir(urb->pipe), str_type(urb->pipe)); ++ dump_ept_data(epid); ++ } ++ } ++ } ++ DBFEXIT; ++} ++ ++void crisv10_hcd_port_status_irq(struct crisv10_irq_reg *reg) ++{ ++ __u16 port_reg[USB_ROOT_HUB_PORTS]; ++ DBFENTER; ++ port_reg[0] = reg->r_usb_rh_port_status_1; ++ port_reg[1] = reg->r_usb_rh_port_status_2; ++ rh_port_status_change(port_reg); ++ DBFEXIT; ++} ++ ++void crisv10_hcd_isoc_eof_irq(struct crisv10_irq_reg *reg) ++{ ++ int epid; ++ struct urb *urb; ++ struct crisv10_urb_priv *urb_priv; ++ ++ DBFENTER; ++ ++ for (epid = 0; epid < NBR_OF_EPIDS - 1; epid++) { ++ ++ /* Only check epids that are in use, is valid and has SB list */ ++ if (!epid_inuse(epid) || epid == INVALID_EPID || ++ TxIsocEPList[epid].sub == 0 || epid == DUMMY_EPID) { ++ /* Nothing here to see. */ ++ continue; ++ } ++ ASSERT(epid_isoc(epid)); ++ ++ /* Get the active URB for this epid (if any). */ ++ urb = activeUrbList[epid]; ++ if (urb == 0) { ++ isoc_warn("Ignoring NULL urb for epid:%d\n", epid); ++ continue; ++ } ++ if(!epid_out_traffic(epid)) { ++ /* Sanity check. */ ++ ASSERT(usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS); ++ ++ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; ++ ASSERT(urb_priv); ++ ++ if (urb_priv->urb_state == NOT_STARTED) { ++ /* If ASAP is not set and urb->start_frame is the current frame, ++ start the transfer. */ ++ if (!(urb->transfer_flags & URB_ISO_ASAP) && ++ (urb->start_frame == (*R_USB_FM_NUMBER & 0x7ff))) { ++ /* EP should not be enabled if we're waiting for start_frame */ ++ ASSERT((TxIsocEPList[epid].command & ++ IO_STATE(USB_EP_command, enable, yes)) == 0); ++ ++ isoc_warn("Enabling isoc IN EP descr for epid %d\n", epid); ++ TxIsocEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); ++ ++ /* This urb is now active. */ ++ urb_priv->urb_state = STARTED; ++ continue; ++ } ++ } ++ } ++ } ++ ++ DBFEXIT; ++} ++ ++void crisv10_hcd_ctl_status_irq(struct crisv10_irq_reg *reg) ++{ ++ struct crisv10_hcd* crisv10_hcd = hcd_to_crisv10_hcd(reg->hcd); ++ ++ DBFENTER; ++ ASSERT(crisv10_hcd); ++ ++ irq_dbg("ctr_status_irq, controller status: %s\n", ++ hcd_status_to_str(reg->r_usb_status)); ++ ++ /* FIXME: What should we do if we get ourun or perror? Dump the EP and SB ++ list for the corresponding epid? */ ++ if (reg->r_usb_status & IO_MASK(R_USB_STATUS, ourun)) { ++ panic("USB controller got ourun."); ++ } ++ if (reg->r_usb_status & IO_MASK(R_USB_STATUS, perror)) { ++ ++ /* Before, etrax_usb_do_intr_recover was called on this epid if it was ++ an interrupt pipe. I don't see how re-enabling all EP descriptors ++ will help if there was a programming error. */ ++ panic("USB controller got perror."); ++ } ++ ++ /* Keep track of USB Controller, if it's running or not */ ++ if(reg->r_usb_status & IO_STATE(R_USB_STATUS, running, yes)) { ++ crisv10_hcd->running = 1; ++ } else { ++ crisv10_hcd->running = 0; ++ } ++ ++ if (reg->r_usb_status & IO_MASK(R_USB_STATUS, device_mode)) { ++ /* We should never operate in device mode. */ ++ panic("USB controller in device mode."); ++ } ++ ++ /* Set the flag to avoid getting "Unlink after no-IRQ? Controller is probably ++ using the wrong IRQ" from hcd_unlink_urb() in drivers/usb/core/hcd.c */ ++ set_bit(HCD_FLAG_SAW_IRQ, ®->hcd->flags); ++ ++ DBFEXIT; ++} ++ ++ ++/******************************************************************/ ++/* Host Controller interface functions */ ++/******************************************************************/ ++ ++static inline void crisv10_ready_wait(void) { ++ volatile int timeout = 10000; ++ /* Check the busy bit of USB controller in Etrax */ ++ while((*R_USB_COMMAND & IO_MASK(R_USB_COMMAND, busy)) && ++ (timeout-- > 0)); ++ if(timeout == 0) { ++ warn("Timeout while waiting for USB controller to be idle\n"); ++ } ++} ++ ++/* reset host controller */ ++static int crisv10_hcd_reset(struct usb_hcd *hcd) ++{ ++ DBFENTER; ++ hcd_dbg(hcd, "reset\n"); ++ ++ ++ /* Reset the USB interface. */ ++ /* ++ *R_USB_COMMAND = ++ IO_STATE(R_USB_COMMAND, port_sel, nop) | ++ IO_STATE(R_USB_COMMAND, port_cmd, reset) | ++ IO_STATE(R_USB_COMMAND, ctrl_cmd, reset); ++ nop(); ++ */ ++ DBFEXIT; ++ return 0; ++} ++ ++/* start host controller */ ++static int crisv10_hcd_start(struct usb_hcd *hcd) ++{ ++ DBFENTER; ++ hcd_dbg(hcd, "start\n"); ++ ++ crisv10_ready_wait(); ++ ++ /* Start processing of USB traffic. */ ++ *R_USB_COMMAND = ++ IO_STATE(R_USB_COMMAND, port_sel, nop) | ++ IO_STATE(R_USB_COMMAND, port_cmd, reset) | ++ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_run); ++ ++ nop(); ++ ++ hcd->state = HC_STATE_RUNNING; ++ ++ DBFEXIT; ++ return 0; ++} ++ ++/* stop host controller */ ++static void crisv10_hcd_stop(struct usb_hcd *hcd) ++{ ++ DBFENTER; ++ hcd_dbg(hcd, "stop\n"); ++ crisv10_hcd_reset(hcd); ++ DBFEXIT; ++} ++ ++/* return the current frame number */ ++static int crisv10_hcd_get_frame(struct usb_hcd *hcd) ++{ ++ DBFENTER; ++ DBFEXIT; ++ return (*R_USB_FM_NUMBER & 0x7ff); ++} ++ ++#ifdef CONFIG_USB_OTG ++ ++static int crisv10_hcd_start_port_reset(struct usb_hcd *hcd, unsigned port) ++{ ++ return 0; /* no-op for now */ ++} ++ ++#endif /* CONFIG_USB_OTG */ ++ ++ ++/******************************************************************/ ++/* Root Hub functions */ ++/******************************************************************/ ++ ++/* root hub status */ ++static const struct usb_hub_status rh_hub_status = ++ { ++ .wHubStatus = 0, ++ .wHubChange = 0, ++ }; ++ ++/* root hub descriptor */ ++static const u8 rh_hub_descr[] = ++ { ++ 0x09, /* bDescLength */ ++ 0x29, /* bDescriptorType */ ++ USB_ROOT_HUB_PORTS, /* bNbrPorts */ ++ 0x00, /* wHubCharacteristics */ ++ 0x00, ++ 0x01, /* bPwrOn2pwrGood */ ++ 0x00, /* bHubContrCurrent */ ++ 0x00, /* DeviceRemovable */ ++ 0xff /* PortPwrCtrlMask */ ++ }; ++ ++/* Actual holder of root hub status*/ ++struct crisv10_rh rh; ++ ++/* Initialize root hub data structures (called from dvdrv_hcd_probe()) */ ++int rh_init(void) { ++ int i; ++ /* Reset port status flags */ ++ for (i = 0; i < USB_ROOT_HUB_PORTS; i++) { ++ rh.wPortChange[i] = 0; ++ rh.wPortStatusPrev[i] = 0; ++ } ++ return 0; ++} ++ ++#define RH_FEAT_MASK ((1<lock); ++ for (i = 1; i <= crisv10_hcd->num_ports; i++) { ++ if (rh.wPortChange[map_port(i)]) { ++ *buf |= (1 << i); ++ rh_dbg("rh_status_data_request, change on port %d: %s Current Status: %s\n", i, ++ port_status_to_str(rh.wPortChange[map_port(i)]), ++ port_status_to_str(rh.wPortStatusPrev[map_port(i)])); ++ } ++ } ++ spin_unlock(&crisv10_hcd->lock); ++ ++// DBFEXIT; ++ ++ return *buf == 0 ? 0 : 1; ++} ++ ++/* Handle a control request for the root hub (called from hcd_driver) */ ++static int rh_control_request(struct usb_hcd *hcd, ++ u16 typeReq, ++ u16 wValue, ++ u16 wIndex, ++ char *buf, ++ u16 wLength) { ++ ++ struct crisv10_hcd *crisv10_hcd = hcd_to_crisv10_hcd(hcd); ++ int retval = 0; ++ int len; ++ DBFENTER; ++ ++ switch (typeReq) { ++ case GetHubDescriptor: ++ rh_dbg("GetHubDescriptor\n"); ++ len = min_t(unsigned int, sizeof rh_hub_descr, wLength); ++ memcpy(buf, rh_hub_descr, len); ++ buf[2] = crisv10_hcd->num_ports; ++ break; ++ case GetHubStatus: ++ rh_dbg("GetHubStatus\n"); ++ len = min_t(unsigned int, sizeof rh_hub_status, wLength); ++ memcpy(buf, &rh_hub_status, len); ++ break; ++ case GetPortStatus: ++ if (!wIndex || wIndex > crisv10_hcd->num_ports) ++ goto error; ++ rh_dbg("GetportStatus, port:%d change:%s status:%s\n", wIndex, ++ port_status_to_str(rh.wPortChange[map_port(wIndex)]), ++ port_status_to_str(rh.wPortStatusPrev[map_port(wIndex)])); ++ *(u16 *) buf = cpu_to_le16(rh.wPortStatusPrev[map_port(wIndex)]); ++ *(u16 *) (buf + 2) = cpu_to_le16(rh.wPortChange[map_port(wIndex)]); ++ break; ++ case SetHubFeature: ++ rh_dbg("SetHubFeature\n"); ++ case ClearHubFeature: ++ rh_dbg("ClearHubFeature\n"); ++ switch (wValue) { ++ case C_HUB_OVER_CURRENT: ++ case C_HUB_LOCAL_POWER: ++ rh_warn("Not implemented hub request:%d \n", typeReq); ++ /* not implemented */ ++ break; ++ default: ++ goto error; ++ } ++ break; ++ case SetPortFeature: ++ if (!wIndex || wIndex > crisv10_hcd->num_ports) ++ goto error; ++ if(rh_set_port_feature(map_port(wIndex), wValue)) ++ goto error; ++ break; ++ case ClearPortFeature: ++ if (!wIndex || wIndex > crisv10_hcd->num_ports) ++ goto error; ++ if(rh_clear_port_feature(map_port(wIndex), wValue)) ++ goto error; ++ break; ++ default: ++ rh_warn("Unknown hub request: %d\n", typeReq); ++ error: ++ retval = -EPIPE; ++ } ++ DBFEXIT; ++ return retval; ++} ++ ++int rh_set_port_feature(__u8 bPort, __u16 wFeature) { ++ __u8 bUsbCommand = 0; ++ switch(wFeature) { ++ case USB_PORT_FEAT_RESET: ++ rh_dbg("SetPortFeature: reset\n"); ++ bUsbCommand |= IO_STATE(R_USB_COMMAND, port_cmd, reset); ++ goto set; ++ break; ++ case USB_PORT_FEAT_SUSPEND: ++ rh_dbg("SetPortFeature: suspend\n"); ++ bUsbCommand |= IO_STATE(R_USB_COMMAND, port_cmd, suspend); ++ goto set; ++ break; ++ case USB_PORT_FEAT_POWER: ++ rh_dbg("SetPortFeature: power\n"); ++ break; ++ case USB_PORT_FEAT_C_CONNECTION: ++ rh_dbg("SetPortFeature: c_connection\n"); ++ break; ++ case USB_PORT_FEAT_C_RESET: ++ rh_dbg("SetPortFeature: c_reset\n"); ++ break; ++ case USB_PORT_FEAT_C_OVER_CURRENT: ++ rh_dbg("SetPortFeature: c_over_current\n"); ++ break; ++ ++ set: ++ /* Select which port via the port_sel field */ ++ bUsbCommand |= IO_FIELD(R_USB_COMMAND, port_sel, bPort+1); ++ ++ /* Make sure the controller isn't busy. */ ++ crisv10_ready_wait(); ++ /* Send out the actual command to the USB controller */ ++ *R_USB_COMMAND = bUsbCommand; ++ ++ /* If port reset then also bring USB controller into running state */ ++ if(wFeature == USB_PORT_FEAT_RESET) { ++ /* Wait a while for controller to first become started after port reset */ ++ udelay(12000); /* 12ms blocking wait */ ++ ++ /* Make sure the controller isn't busy. */ ++ crisv10_ready_wait(); ++ ++ /* If all enabled ports were disabled the host controller goes down into ++ started mode, so we need to bring it back into the running state. ++ (This is safe even if it's already in the running state.) */ ++ *R_USB_COMMAND = ++ IO_STATE(R_USB_COMMAND, port_sel, nop) | ++ IO_STATE(R_USB_COMMAND, port_cmd, reset) | ++ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_run); ++ } ++ ++ break; ++ default: ++ rh_dbg("SetPortFeature: unknown feature\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++int rh_clear_port_feature(__u8 bPort, __u16 wFeature) { ++ switch(wFeature) { ++ case USB_PORT_FEAT_ENABLE: ++ rh_dbg("ClearPortFeature: enable\n"); ++ rh_disable_port(bPort); ++ break; ++ case USB_PORT_FEAT_SUSPEND: ++ rh_dbg("ClearPortFeature: suspend\n"); ++ break; ++ case USB_PORT_FEAT_POWER: ++ rh_dbg("ClearPortFeature: power\n"); ++ break; ++ ++ case USB_PORT_FEAT_C_ENABLE: ++ rh_dbg("ClearPortFeature: c_enable\n"); ++ goto clear; ++ case USB_PORT_FEAT_C_SUSPEND: ++ rh_dbg("ClearPortFeature: c_suspend\n"); ++ goto clear; ++ case USB_PORT_FEAT_C_CONNECTION: ++ rh_dbg("ClearPortFeature: c_connection\n"); ++ goto clear; ++ case USB_PORT_FEAT_C_OVER_CURRENT: ++ rh_dbg("ClearPortFeature: c_over_current\n"); ++ goto clear; ++ case USB_PORT_FEAT_C_RESET: ++ rh_dbg("ClearPortFeature: c_reset\n"); ++ goto clear; ++ clear: ++ rh.wPortChange[bPort] &= ~(1 << (wFeature - 16)); ++ break; ++ default: ++ rh_dbg("ClearPortFeature: unknown feature\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++ ++#ifdef CONFIG_PM ++/* Handle a suspend request for the root hub (called from hcd_driver) */ ++static int rh_suspend_request(struct usb_hcd *hcd) ++{ ++ return 0; /* no-op for now */ ++} ++ ++/* Handle a resume request for the root hub (called from hcd_driver) */ ++static int rh_resume_request(struct usb_hcd *hcd) ++{ ++ return 0; /* no-op for now */ ++} ++#endif /* CONFIG_PM */ ++ ++ ++ ++/* Wrapper function for workaround port disable registers in USB controller */ ++static void rh_disable_port(unsigned int port) { ++ volatile int timeout = 10000; ++ volatile char* usb_portx_disable; ++ switch(port) { ++ case 0: ++ usb_portx_disable = R_USB_PORT1_DISABLE; ++ break; ++ case 1: ++ usb_portx_disable = R_USB_PORT2_DISABLE; ++ break; ++ default: ++ /* Invalid port index */ ++ return; ++ } ++ /* Set disable flag in special register */ ++ *usb_portx_disable = IO_STATE(R_USB_PORT1_DISABLE, disable, yes); ++ /* Wait until not enabled anymore */ ++ while((rh.wPortStatusPrev[port] & ++ IO_STATE(R_USB_RH_PORT_STATUS_1, enabled, yes)) && ++ (timeout-- > 0)); ++ if(timeout == 0) { ++ warn("Timeout while waiting for port %d to become disabled\n", port); ++ } ++ /* clear disable flag in special register */ ++ *usb_portx_disable = IO_STATE(R_USB_PORT1_DISABLE, disable, no); ++ rh_info("Physical port %d disabled\n", port+1); ++} ++ ++ ++/******************************************************************/ ++/* Transfer Controller (TC) functions */ ++/******************************************************************/ ++ ++/* FIXME: Should RX_BUF_SIZE be a config option, or maybe we should adjust it ++ dynamically? ++ To adjust it dynamically we would have to get an interrupt when we reach ++ the end of the rx descriptor list, or when we get close to the end, and ++ then allocate more descriptors. */ ++#define NBR_OF_RX_DESC 512 ++#define RX_DESC_BUF_SIZE 1024 ++#define RX_BUF_SIZE (NBR_OF_RX_DESC * RX_DESC_BUF_SIZE) ++ ++ ++/* Local variables for Transfer Controller */ ++/* --------------------------------------- */ ++ ++/* This is a circular (double-linked) list of the active urbs for each epid. ++ The head is never removed, and new urbs are linked onto the list as ++ urb_entry_t elements. Don't reference urb_list directly; use the wrapper ++ functions instead (which includes spin_locks) */ ++static struct list_head urb_list[NBR_OF_EPIDS]; ++ ++/* Read about the need and usage of this lock in submit_ctrl_urb. */ ++/* Lock for URB lists for each EPID */ ++static spinlock_t urb_list_lock; ++ ++/* Lock for EPID array register (R_USB_EPT_x) in Etrax */ ++static spinlock_t etrax_epid_lock; ++ ++/* Lock for dma8 sub0 handling */ ++static spinlock_t etrax_dma8_sub0_lock; ++ ++/* DMA IN cache bug. Align the DMA IN buffers to 32 bytes, i.e. a cache line. ++ Since RX_DESC_BUF_SIZE is 1024 is a multiple of 32, all rx buffers will be ++ cache aligned. */ ++static volatile unsigned char RxBuf[RX_BUF_SIZE] __attribute__ ((aligned (32))); ++static volatile struct USB_IN_Desc RxDescList[NBR_OF_RX_DESC] __attribute__ ((aligned (4))); ++ ++/* Pointers into RxDescList. */ ++static volatile struct USB_IN_Desc *myNextRxDesc; ++static volatile struct USB_IN_Desc *myLastRxDesc; ++ ++/* A zout transfer makes a memory access at the address of its buf pointer, ++ which means that setting this buf pointer to 0 will cause an access to the ++ flash. In addition to this, setting sw_len to 0 results in a 16/32 bytes ++ (depending on DMA burst size) transfer. ++ Instead, we set it to 1, and point it to this buffer. */ ++static int zout_buffer[4] __attribute__ ((aligned (4))); ++ ++/* Cache for allocating new EP and SB descriptors. */ ++//static kmem_cache_t *usb_desc_cache; ++static struct kmem_cache *usb_desc_cache; ++ ++/* Cache for the data allocated in the isoc descr top half. */ ++//static kmem_cache_t *isoc_compl_cache; ++static struct kmem_cache *isoc_compl_cache; ++ ++/* Cache for the data allocated when delayed finishing of URBs */ ++//static kmem_cache_t *later_data_cache; ++static struct kmem_cache *later_data_cache; ++ ++/* Counter to keep track of how many Isoc EP we have sat up. Used to enable ++ and disable iso_eof interrupt. We only need these interrupts when we have ++ Isoc data endpoints (consumes CPU cycles). ++ FIXME: This could be more fine granular, so this interrupt is only enabled ++ when we have a In Isoc URB not URB_ISO_ASAP flaged queued. */ ++static int isoc_epid_counter; ++ ++/* Protecting wrapper functions for R_USB_EPT_x */ ++/* -------------------------------------------- */ ++static inline void etrax_epid_set(__u8 index, __u32 data) { ++ unsigned long flags; ++ spin_lock_irqsave(&etrax_epid_lock, flags); ++ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); ++ nop(); ++ *R_USB_EPT_DATA = data; ++ spin_unlock_irqrestore(&etrax_epid_lock, flags); ++} ++ ++static inline void etrax_epid_clear_error(__u8 index) { ++ unsigned long flags; ++ spin_lock_irqsave(&etrax_epid_lock, flags); ++ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); ++ nop(); ++ *R_USB_EPT_DATA &= ++ ~(IO_MASK(R_USB_EPT_DATA, error_count_in) | ++ IO_MASK(R_USB_EPT_DATA, error_count_out) | ++ IO_MASK(R_USB_EPT_DATA, error_code)); ++ spin_unlock_irqrestore(&etrax_epid_lock, flags); ++} ++ ++static inline void etrax_epid_set_toggle(__u8 index, __u8 dirout, ++ __u8 toggle) { ++ unsigned long flags; ++ spin_lock_irqsave(&etrax_epid_lock, flags); ++ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); ++ nop(); ++ if(dirout) { ++ *R_USB_EPT_DATA &= ~IO_MASK(R_USB_EPT_DATA, t_out); ++ *R_USB_EPT_DATA |= IO_FIELD(R_USB_EPT_DATA, t_out, toggle); ++ } else { ++ *R_USB_EPT_DATA &= ~IO_MASK(R_USB_EPT_DATA, t_in); ++ *R_USB_EPT_DATA |= IO_FIELD(R_USB_EPT_DATA, t_in, toggle); ++ } ++ spin_unlock_irqrestore(&etrax_epid_lock, flags); ++} ++ ++static inline __u8 etrax_epid_get_toggle(__u8 index, __u8 dirout) { ++ unsigned long flags; ++ __u8 toggle; ++ spin_lock_irqsave(&etrax_epid_lock, flags); ++ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); ++ nop(); ++ if (dirout) { ++ toggle = IO_EXTRACT(R_USB_EPT_DATA, t_out, *R_USB_EPT_DATA); ++ } else { ++ toggle = IO_EXTRACT(R_USB_EPT_DATA, t_in, *R_USB_EPT_DATA); ++ } ++ spin_unlock_irqrestore(&etrax_epid_lock, flags); ++ return toggle; ++} ++ ++ ++static inline __u32 etrax_epid_get(__u8 index) { ++ unsigned long flags; ++ __u32 data; ++ spin_lock_irqsave(&etrax_epid_lock, flags); ++ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); ++ nop(); ++ data = *R_USB_EPT_DATA; ++ spin_unlock_irqrestore(&etrax_epid_lock, flags); ++ return data; ++} ++ ++ ++ ++ ++/* Main functions for Transfer Controller */ ++/* -------------------------------------- */ ++ ++/* Init structs, memories and lists used by Transfer Controller */ ++int tc_init(struct usb_hcd *hcd) { ++ int i; ++ /* Clear software state info for all epids */ ++ memset(epid_state, 0, sizeof(struct etrax_epid) * NBR_OF_EPIDS); ++ ++ /* Set Invalid and Dummy as being in use and disabled */ ++ epid_state[INVALID_EPID].inuse = 1; ++ epid_state[DUMMY_EPID].inuse = 1; ++ epid_state[INVALID_EPID].disabled = 1; ++ epid_state[DUMMY_EPID].disabled = 1; ++ ++ /* Clear counter for how many Isoc epids we have sat up */ ++ isoc_epid_counter = 0; ++ ++ /* Initialize the urb list by initiating a head for each list. ++ Also reset list hodling active URB for each epid */ ++ for (i = 0; i < NBR_OF_EPIDS; i++) { ++ INIT_LIST_HEAD(&urb_list[i]); ++ activeUrbList[i] = NULL; ++ } ++ ++ /* Init lock for URB lists */ ++ spin_lock_init(&urb_list_lock); ++ /* Init lock for Etrax R_USB_EPT register */ ++ spin_lock_init(&etrax_epid_lock); ++ /* Init lock for Etrax dma8 sub0 handling */ ++ spin_lock_init(&etrax_dma8_sub0_lock); ++ ++ /* We use kmem_cache_* to make sure that all DMA desc. are dword aligned */ ++ ++ /* Note that we specify sizeof(struct USB_EP_Desc) as the size, but also ++ allocate SB descriptors from this cache. This is ok since ++ sizeof(struct USB_EP_Desc) == sizeof(struct USB_SB_Desc). */ ++// usb_desc_cache = kmem_cache_create("usb_desc_cache", ++// sizeof(struct USB_EP_Desc), 0, ++// SLAB_HWCACHE_ALIGN, 0, 0); ++ usb_desc_cache = kmem_cache_create( ++ "usb_desc_cache", ++ sizeof(struct USB_EP_Desc), ++ 0, ++ SLAB_HWCACHE_ALIGN, ++ NULL); ++ if(usb_desc_cache == NULL) { ++ return -ENOMEM; ++ } ++ ++ /* Create slab cache for speedy allocation of memory for isoc bottom-half ++ interrupt handling */ ++// isoc_compl_cache = ++// kmem_cache_create("isoc_compl_cache", ++// sizeof(struct crisv10_isoc_complete_data), ++// 0, SLAB_HWCACHE_ALIGN, 0, 0); ++ isoc_compl_cache = kmem_cache_create( ++ "isoc_compl_cache", ++ sizeof(struct crisv10_isoc_complete_data), ++ 0, ++ SLAB_HWCACHE_ALIGN, ++ NULL ++ ); ++ ++ if(isoc_compl_cache == NULL) { ++ return -ENOMEM; ++ } ++ ++ /* Create slab cache for speedy allocation of memory for later URB finish ++ struct */ ++// later_data_cache = ++// kmem_cache_create("later_data_cache", ++// sizeof(struct urb_later_data), ++// 0, SLAB_HWCACHE_ALIGN, 0, 0); ++ ++ later_data_cache = kmem_cache_create( ++ "later_data_cache", ++ sizeof(struct urb_later_data), ++ 0, ++ SLAB_HWCACHE_ALIGN, ++ NULL ++ ); ++ ++ if(later_data_cache == NULL) { ++ return -ENOMEM; ++ } ++ ++ ++ /* Initiate the bulk start timer. */ ++ init_timer(&bulk_start_timer); ++ bulk_start_timer.expires = jiffies + BULK_START_TIMER_INTERVAL; ++ bulk_start_timer.function = tc_bulk_start_timer_func; ++ add_timer(&bulk_start_timer); ++ ++ ++ /* Initiate the bulk eot timer. */ ++ init_timer(&bulk_eot_timer); ++ bulk_eot_timer.expires = jiffies + BULK_EOT_TIMER_INTERVAL; ++ bulk_eot_timer.function = tc_bulk_eot_timer_func; ++ bulk_eot_timer.data = (unsigned long)hcd; ++ add_timer(&bulk_eot_timer); ++ ++ return 0; ++} ++ ++/* Uninitialize all resources used by Transfer Controller */ ++void tc_destroy(void) { ++ ++ /* Destroy all slab cache */ ++ kmem_cache_destroy(usb_desc_cache); ++ kmem_cache_destroy(isoc_compl_cache); ++ kmem_cache_destroy(later_data_cache); ++ ++ /* Remove timers */ ++ del_timer(&bulk_start_timer); ++ del_timer(&bulk_eot_timer); ++} ++ ++static void restart_dma8_sub0(void) { ++ unsigned long flags; ++ spin_lock_irqsave(&etrax_dma8_sub0_lock, flags); ++ /* Verify that the dma is not running */ ++ if ((*R_DMA_CH8_SUB0_CMD & IO_MASK(R_DMA_CH8_SUB0_CMD, cmd)) == 0) { ++ struct USB_EP_Desc *ep = (struct USB_EP_Desc *)phys_to_virt(*R_DMA_CH8_SUB0_EP); ++ while (DUMMY_EPID == IO_EXTRACT(USB_EP_command, epid, ep->command)) { ++ ep = (struct USB_EP_Desc *)phys_to_virt(ep->next); ++ } ++ /* Advance the DMA to the next EP descriptor that is not a DUMMY_EPID. ++ * ep->next is already a physical address. virt_to_phys is needed, see ++ * http://mhonarc.axis.se/dev-etrax/msg08630.html ++ */ ++ //*R_DMA_CH8_SUB0_EP = ep->next; ++ *R_DMA_CH8_SUB0_EP = virt_to_phys(ep); ++ /* Restart the DMA */ ++ *R_DMA_CH8_SUB0_CMD = IO_STATE(R_DMA_CH8_SUB0_CMD, cmd, start); ++ } ++ spin_unlock_irqrestore(&etrax_dma8_sub0_lock, flags); ++} ++ ++/* queue an URB with the transfer controller (called from hcd_driver) */ ++//static int tc_urb_enqueue(struct usb_hcd *hcd, ++// struct usb_host_endpoint *ep, ++// struct urb *urb, ++// gfp_t mem_flags) { ++static int tc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) ++{ ++ int epid; ++ int retval; ++// int bustime = 0; ++ int maxpacket; ++ unsigned long flags; ++ struct crisv10_urb_priv *urb_priv; ++ struct crisv10_hcd* crisv10_hcd = hcd_to_crisv10_hcd(hcd); ++ DBFENTER; ++ ++ if(!(crisv10_hcd->running)) { ++ /* The USB Controller is not running, probably because no device is ++ attached. No idea to enqueue URBs then */ ++ tc_warn("Rejected enqueueing of URB:0x%x because no dev attached\n", ++ (unsigned int)urb); ++ return -ENOENT; ++ } ++ ++ maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); ++ ++ /* hinko ignore usb_pipeisoc */ ++#if 0 ++ /* Special case check for In Isoc transfers. Specification states that each ++ In Isoc transfer consists of one packet and therefore it should fit into ++ the transfer-buffer of an URB. ++ We do the check here to be sure (an invalid scenario can be produced with ++ parameters to the usbtest suite) */ ++ if(usb_pipeisoc(urb->pipe) && usb_pipein(urb->pipe) && ++ (urb->transfer_buffer_length < maxpacket)) { ++ tc_err("Submit In Isoc URB with buffer length:%d to pipe with maxpacketlen: %d\n", urb->transfer_buffer_length, maxpacket); ++ return -EMSGSIZE; ++ } ++ ++ /* Check if there is enough bandwidth for periodic transfer */ ++ if(usb_pipeint(urb->pipe) || usb_pipeisoc(urb->pipe)) { ++ /* only check (and later claim) if not already claimed */ ++ if (urb->bandwidth == 0) { ++ bustime = usb_check_bandwidth(urb->dev, urb); ++ if (bustime < 0) { ++ tc_err("Not enough periodic bandwidth\n"); ++ return -ENOSPC; ++ } ++ } ++ } ++#endif ++ ++ /* Check if there is a epid for URBs destination, if not this function ++ set up one. */ ++ //epid = tc_setup_epid(ep, urb, mem_flags); ++ epid = tc_setup_epid(urb, mem_flags); ++ if (epid < 0) { ++ tc_err("Failed setup epid:%d for URB:0x%x\n", epid, (unsigned int)urb); ++ DBFEXIT; ++ return -ENOMEM; ++ } ++ ++ if(urb == activeUrbList[epid]) { ++ tc_err("Resubmition of allready active URB:0x%x\n", (unsigned int)urb); ++ return -ENXIO; ++ } ++ ++ if(urb_list_entry(urb, epid)) { ++ tc_err("Resubmition of allready queued URB:0x%x\n", (unsigned int)urb); ++ return -ENXIO; ++ } ++ ++ /* If we actively have flaged endpoint as disabled then refuse submition */ ++ if(epid_state[epid].disabled) { ++ return -ENOENT; ++ } ++ ++ /* Allocate and init HC-private data for URB */ ++ if(urb_priv_create(hcd, urb, epid, mem_flags) != 0) { ++ DBFEXIT; ++ return -ENOMEM; ++ } ++ urb_priv = urb->hcpriv; ++ ++ tc_dbg("Enqueue URB:0x%x[%d] epid:%d (%s) bufflen:%d\n", ++ (unsigned int)urb, urb_priv->urb_num, epid, ++ pipe_to_str(urb->pipe), urb->transfer_buffer_length); ++ ++ /* Create and link SBs required for this URB */ ++ retval = create_sb_for_urb(urb, mem_flags); ++ if(retval != 0) { ++ tc_err("Failed to create SBs for URB:0x%x[%d]\n", (unsigned int)urb, ++ urb_priv->urb_num); ++ urb_priv_free(hcd, urb); ++ DBFEXIT; ++ return retval; ++ } ++ ++ /* Init intr EP pool if this URB is a INTR transfer. This pool is later ++ used when inserting EPs in the TxIntrEPList. We do the alloc here ++ so we can't run out of memory later */ ++ if(usb_pipeint(urb->pipe)) { ++ retval = init_intr_urb(urb, mem_flags); ++ if(retval != 0) { ++ tc_warn("Failed to init Intr URB\n"); ++ urb_priv_free(hcd, urb); ++ DBFEXIT; ++ return retval; ++ } ++ } ++ ++ /* Disable other access when inserting USB */ ++ ++ /* BUG on sleeping inside int disabled if using local_irq_save/local_irq_restore ++ * her - because urb_list_add() and tc_dma_process_queue() save irqs again !??! ++ */ ++// local_irq_save(flags); ++ ++ /* hinko ignore usb_pipeisoc */ ++#if 0 ++ /* Claim bandwidth, if needed */ ++ if(bustime) { ++ usb_claim_bandwidth(urb->dev, urb, bustime, 0); ++ } ++ ++ /* Add URB to EP queue */ ++ urb_list_add(urb, epid, mem_flags); ++ ++ if(usb_pipeisoc(urb->pipe)) { ++ /* Special processing of Isoc URBs. */ ++ tc_dma_process_isoc_urb(urb); ++ } else { ++ /* Process EP queue for rest of the URB types (Bulk, Ctrl, Intr) */ ++ tc_dma_process_queue(epid); ++ } ++#endif ++ /* Add URB to EP queue */ ++ urb_list_add(urb, epid, mem_flags); ++ ++ /*hinko link/unlink urb -> ep */ ++ spin_lock_irqsave(&crisv10_hcd->lock, flags); ++ //spin_lock(&crisv10_hcd->lock); ++ retval = usb_hcd_link_urb_to_ep(hcd, urb); ++ if (retval) { ++ spin_unlock_irqrestore(&crisv10_hcd->lock, flags); ++ tc_warn("Failed to link urb to ep\n"); ++ urb_priv_free(hcd, urb); ++ DBFEXIT; ++ return retval; ++ } ++ spin_unlock_irqrestore(&crisv10_hcd->lock, flags); ++ //spin_unlock(&crisv10_hcd->lock); ++ ++ /* Process EP queue for rest of the URB types (Bulk, Ctrl, Intr) */ ++ tc_dma_process_queue(epid); ++ ++// local_irq_restore(flags); ++ ++ DBFEXIT; ++ return 0; ++} ++ ++/* remove an URB from the transfer controller queues (called from hcd_driver)*/ ++//static int tc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb) ++static int tc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) ++{ ++ struct crisv10_urb_priv *urb_priv; ++ unsigned long flags; ++ int epid; ++ ++ DBFENTER; ++ /* Disable interrupts here since a descriptor interrupt for the isoc epid ++ will modify the sb list. This could possibly be done more granular, but ++ urb_dequeue should not be used frequently anyway. ++ */ ++ local_irq_save(flags); ++ ++ urb_priv = urb->hcpriv; ++ ++ if (!urb_priv) { ++ /* This happens if a device driver calls unlink on an urb that ++ was never submitted (lazy driver) or if the urb was completed ++ while dequeue was being called. */ ++ tc_warn("Dequeing of not enqueued URB:0x%x\n", (unsigned int)urb); ++ local_irq_restore(flags); ++ return 0; ++ } ++ epid = urb_priv->epid; ++ ++ tc_warn("Dequeing %s URB:0x%x[%d] (%s %s epid:%d) status:%d %s\n", ++ (urb == activeUrbList[epid]) ? "active" : "queued", ++ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), ++ str_type(urb->pipe), epid, urb->status, ++ (urb_priv->later_data) ? "later-sched" : ""); ++ ++ /* For Bulk, Ctrl and Intr are only one URB active at a time. So any URB ++ that isn't active can be dequeued by just removing it from the queue */ ++ if(usb_pipebulk(urb->pipe) || usb_pipecontrol(urb->pipe) || ++ usb_pipeint(urb->pipe)) { ++ ++ /* Check if URB haven't gone further than the queue */ ++ if(urb != activeUrbList[epid]) { ++ ASSERT(urb_priv->later_data == NULL); ++ tc_warn("Dequeing URB:0x%x[%d] (%s %s epid:%d) from queue" ++ " (not active)\n", (unsigned int)urb, urb_priv->urb_num, ++ str_dir(urb->pipe), str_type(urb->pipe), epid); ++ ++ /* Finish the URB with error status from USB core */ ++ tc_finish_urb(hcd, urb, urb->status); ++ local_irq_restore(flags); ++ return 0; ++ } ++ } ++ ++ /* Set URB status to Unlink for handling when interrupt comes. */ ++ urb_priv->urb_state = UNLINK; ++ ++ /* Differentiate dequeing of Bulk and Ctrl from Isoc and Intr */ ++ switch(usb_pipetype(urb->pipe)) { ++ case PIPE_BULK: ++ /* Check if EP still is enabled */ ++ if (TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) { ++ /* The EP was enabled, disable it. */ ++ TxBulkEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); ++ } ++ /* Kicking dummy list out of the party. */ ++ TxBulkEPList[epid].next = virt_to_phys(&TxBulkEPList[(epid + 1) % NBR_OF_EPIDS]); ++ break; ++ case PIPE_CONTROL: ++ /* Check if EP still is enabled */ ++ if (TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) { ++ /* The EP was enabled, disable it. */ ++ TxCtrlEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); ++ } ++ break; ++ case PIPE_ISOCHRONOUS: ++ /* Disabling, busy-wait and unlinking of Isoc SBs will be done in ++ finish_isoc_urb(). Because there might the case when URB is dequeued ++ but there are other valid URBs waiting */ ++ ++ /* Check if In Isoc EP still is enabled */ ++ if (TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable)) { ++ /* The EP was enabled, disable it. */ ++ TxIsocEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); ++ } ++ break; ++ case PIPE_INTERRUPT: ++ /* Special care is taken for interrupt URBs. EPs are unlinked in ++ tc_finish_urb */ ++ break; ++ default: ++ break; ++ } ++ ++ /* Asynchronous unlink, finish the URB later from scheduled or other ++ event (data finished, error) */ ++ tc_finish_urb_later(hcd, urb, urb->status); ++ ++ local_irq_restore(flags); ++ DBFEXIT; ++ return 0; ++} ++ ++ ++static void tc_sync_finish_epid(struct usb_hcd *hcd, int epid) { ++ volatile int timeout = 10000; ++ struct urb* urb; ++ struct crisv10_urb_priv* urb_priv; ++ unsigned long flags; ++ ++ volatile struct USB_EP_Desc *first_ep; /* First EP in the list. */ ++ volatile struct USB_EP_Desc *curr_ep; /* Current EP, the iterator. */ ++ volatile struct USB_EP_Desc *next_ep; /* The EP after current. */ ++ ++ int type = epid_state[epid].type; ++ ++ /* Setting this flag will cause enqueue() to return -ENOENT for new ++ submitions on this endpoint and finish_urb() wont process queue further */ ++ epid_state[epid].disabled = 1; ++ ++ switch(type) { ++ case PIPE_BULK: ++ /* Check if EP still is enabled */ ++ if (TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) { ++ /* The EP was enabled, disable it. */ ++ TxBulkEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); ++ tc_warn("sync_finish: Disabling EP for epid:%d\n", epid); ++ ++ /* Do busy-wait until DMA not using this EP descriptor anymore */ ++ while((*R_DMA_CH8_SUB0_EP == ++ virt_to_phys(&TxBulkEPList[epid])) && ++ (timeout-- > 0)); ++ if(timeout == 0) { ++ warn("Timeout while waiting for DMA-TX-Bulk to leave EP for" ++ " epid:%d\n", epid); ++ } ++ } ++ break; ++ ++ case PIPE_CONTROL: ++ /* Check if EP still is enabled */ ++ if (TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) { ++ /* The EP was enabled, disable it. */ ++ TxCtrlEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); ++ tc_warn("sync_finish: Disabling EP for epid:%d\n", epid); ++ ++ /* Do busy-wait until DMA not using this EP descriptor anymore */ ++ while((*R_DMA_CH8_SUB1_EP == ++ virt_to_phys(&TxCtrlEPList[epid])) && ++ (timeout-- > 0)); ++ if(timeout == 0) { ++ warn("Timeout while waiting for DMA-TX-Ctrl to leave EP for" ++ " epid:%d\n", epid); ++ } ++ } ++ break; ++ ++ case PIPE_INTERRUPT: ++ local_irq_save(flags); ++ /* Disable all Intr EPs belonging to epid */ ++ first_ep = &TxIntrEPList[0]; ++ curr_ep = first_ep; ++ do { ++ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); ++ if (IO_EXTRACT(USB_EP_command, epid, next_ep->command) == epid) { ++ /* Disable EP */ ++ next_ep->command &= ~IO_MASK(USB_EP_command, enable); ++ } ++ curr_ep = phys_to_virt(curr_ep->next); ++ } while (curr_ep != first_ep); ++ ++ local_irq_restore(flags); ++ break; ++ ++ case PIPE_ISOCHRONOUS: ++ /* Check if EP still is enabled */ ++ if (TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable)) { ++ tc_warn("sync_finish: Disabling Isoc EP for epid:%d\n", epid); ++ /* The EP was enabled, disable it. */ ++ TxIsocEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); ++ ++ while((*R_DMA_CH8_SUB3_EP == virt_to_phys(&TxIsocEPList[epid])) && ++ (timeout-- > 0)); ++ if(timeout == 0) { ++ warn("Timeout while waiting for DMA-TX-Isoc to leave EP for" ++ " epid:%d\n", epid); ++ } ++ } ++ break; ++ } ++ ++ local_irq_save(flags); ++ ++ /* Finish if there is active URB for this endpoint */ ++ if(activeUrbList[epid] != NULL) { ++ urb = activeUrbList[epid]; ++ urb_priv = urb->hcpriv; ++ ASSERT(urb_priv); ++ tc_warn("Sync finish %s URB:0x%x[%d] (%s %s epid:%d) status:%d %s\n", ++ (urb == activeUrbList[epid]) ? "active" : "queued", ++ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), ++ str_type(urb->pipe), epid, urb->status, ++ (urb_priv->later_data) ? "later-sched" : ""); ++ ++ tc_finish_urb(hcd, activeUrbList[epid], -ENOENT); ++ ASSERT(activeUrbList[epid] == NULL); ++ } ++ ++ /* Finish any queued URBs for this endpoint. There won't be any resubmitions ++ because epid_disabled causes enqueue() to fail for this endpoint */ ++ while((urb = urb_list_first(epid)) != NULL) { ++ urb_priv = urb->hcpriv; ++ ASSERT(urb_priv); ++ ++ tc_warn("Sync finish %s URB:0x%x[%d] (%s %s epid:%d) status:%d %s\n", ++ (urb == activeUrbList[epid]) ? "active" : "queued", ++ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), ++ str_type(urb->pipe), epid, urb->status, ++ (urb_priv->later_data) ? "later-sched" : ""); ++ ++ tc_finish_urb(hcd, urb, -ENOENT); ++ } ++ epid_state[epid].disabled = 0; ++ local_irq_restore(flags); ++} ++ ++/* free resources associated with an endpoint (called from hcd_driver) */ ++static void tc_endpoint_disable(struct usb_hcd *hcd, ++ struct usb_host_endpoint *ep) { ++ DBFENTER; ++ /* Only free epid if it has been allocated. We get two endpoint_disable ++ requests for ctrl endpoints so ignore the second one */ ++ if(ep->hcpriv != NULL) { ++ struct crisv10_ep_priv *ep_priv = ep->hcpriv; ++ int epid = ep_priv->epid; ++ tc_warn("endpoint_disable ep:0x%x ep-priv:0x%x (%s) (epid:%d freed)\n", ++ (unsigned int)ep, (unsigned int)ep->hcpriv, ++ endpoint_to_str(&(ep->desc)), epid); ++ ++ tc_sync_finish_epid(hcd, epid); ++ ++ ASSERT(activeUrbList[epid] == NULL); ++ ASSERT(list_empty(&urb_list[epid])); ++ ++ tc_free_epid(ep); ++ } else { ++ tc_dbg("endpoint_disable ep:0x%x ep-priv:0x%x (%s)\n", (unsigned int)ep, ++ (unsigned int)ep->hcpriv, endpoint_to_str(&(ep->desc))); ++ } ++ DBFEXIT; ++} ++ ++//static void tc_finish_urb_later_proc(void *data) { ++static void tc_finish_urb_later_proc(struct work_struct *work) { ++ unsigned long flags; ++ //struct urb_later_data* uld = (struct urb_later_data*)data; ++ struct urb_later_data* uld = container_of(work, struct urb_later_data, ws.work); ++ local_irq_save(flags); ++ if(uld->urb == NULL) { ++ late_dbg("Later finish of URB = NULL (allready finished)\n"); ++ } else { ++ struct crisv10_urb_priv* urb_priv = uld->urb->hcpriv; ++ ASSERT(urb_priv); ++ if(urb_priv->urb_num == uld->urb_num) { ++ late_dbg("Later finish of URB:0x%x[%d]\n", (unsigned int)(uld->urb), ++ urb_priv->urb_num); ++ if(uld->status != uld->urb->status) { ++ errno_dbg("Later-finish URB with status:%d, later-status:%d\n", ++ uld->urb->status, uld->status); ++ } ++ if(uld != urb_priv->later_data) { ++ panic("Scheduled uld not same as URBs uld\n"); ++ } ++ tc_finish_urb(uld->hcd, uld->urb, uld->status); ++ } else { ++ late_warn("Ignoring later finish of URB:0x%x[%d]" ++ ", urb_num doesn't match current URB:0x%x[%d]", ++ (unsigned int)(uld->urb), uld->urb_num, ++ (unsigned int)(uld->urb), urb_priv->urb_num); ++ } ++ } ++ local_irq_restore(flags); ++ kmem_cache_free(later_data_cache, uld); ++} ++ ++static void tc_finish_urb_later(struct usb_hcd *hcd, struct urb *urb, ++ int status) { ++ struct crisv10_urb_priv *urb_priv = urb->hcpriv; ++ struct urb_later_data* uld; ++ ++ ASSERT(urb_priv); ++ ++ if(urb_priv->later_data != NULL) { ++ /* Later-finish allready scheduled for this URB, just update status to ++ return when finishing later */ ++ errno_dbg("Later-finish schedule change URB status:%d with new" ++ " status:%d\n", urb_priv->later_data->status, status); ++ ++ urb_priv->later_data->status = status; ++ return; ++ } ++ ++ uld = kmem_cache_alloc(later_data_cache, GFP_ATOMIC); ++ ASSERT(uld); ++ ++ uld->hcd = hcd; ++ uld->urb = urb; ++ uld->urb_num = urb_priv->urb_num; ++ uld->status = status; ++ ++ //INIT_WORK(&uld->ws, tc_finish_urb_later_proc, uld); ++ INIT_DELAYED_WORK(&uld->ws, tc_finish_urb_later_proc); ++ urb_priv->later_data = uld; ++ ++ /* Schedule the finishing of the URB to happen later */ ++ schedule_delayed_work(&uld->ws, LATER_TIMER_DELAY); ++} ++ ++ /* hinko ignore usb_pipeisoc */ ++#if 0 ++static void tc_finish_isoc_urb(struct usb_hcd *hcd, struct urb *urb, ++ int status); ++#endif ++ ++static void tc_finish_urb(struct usb_hcd *hcd, struct urb *urb, int status) { ++ struct crisv10_hcd* crisv10_hcd = hcd_to_crisv10_hcd(hcd); ++ struct crisv10_urb_priv *urb_priv = urb->hcpriv; ++ int epid; ++ char toggle; ++ int urb_num; ++ unsigned long flags; ++ ++ DBFENTER; ++ ASSERT(urb_priv != NULL); ++ epid = urb_priv->epid; ++ urb_num = urb_priv->urb_num; ++ ++ if(urb != activeUrbList[epid]) { ++ if(urb_list_entry(urb, epid)) { ++ /* Remove this URB from the list. Only happens when URB are finished ++ before having been processed (dequeing) */ ++ urb_list_del(urb, epid); ++ } else { ++ tc_warn("Finishing of URB:0x%x[%d] neither active or in queue for" ++ " epid:%d\n", (unsigned int)urb, urb_num, epid); ++ } ++ } ++ ++ /* Cancel any pending later-finish of this URB */ ++ if(urb_priv->later_data) { ++ urb_priv->later_data->urb = NULL; ++ } ++ ++ /* For an IN pipe, we always set the actual length, regardless of whether ++ there was an error or not (which means the device driver can use the data ++ if it wants to). */ ++ if(usb_pipein(urb->pipe)) { ++ urb->actual_length = urb_priv->rx_offset; ++ } else { ++ /* Set actual_length for OUT urbs also; the USB mass storage driver seems ++ to want that. */ ++ if (status == 0 && urb->status == -EINPROGRESS) { ++ urb->actual_length = urb->transfer_buffer_length; ++ } else { ++ /* We wouldn't know of any partial writes if there was an error. */ ++ urb->actual_length = 0; ++ } ++ } ++ ++ ++ /* URB status mangling */ ++ if(urb->status == -EINPROGRESS) { ++ /* The USB core hasn't changed the status, let's set our finish status */ ++ urb->status = status; ++ ++ if ((status == 0) && (urb->transfer_flags & URB_SHORT_NOT_OK) && ++ usb_pipein(urb->pipe) && ++ (urb->actual_length != urb->transfer_buffer_length)) { ++ /* URB_SHORT_NOT_OK means that short reads (shorter than the endpoint's ++ max length) is to be treated as an error. */ ++ errno_dbg("Finishing URB:0x%x[%d] with SHORT_NOT_OK flag and short" ++ " data:%d\n", (unsigned int)urb, urb_num, ++ urb->actual_length); ++ urb->status = -EREMOTEIO; ++ } ++ ++ if(urb_priv->urb_state == UNLINK) { ++ /* URB has been requested to be unlinked asynchronously */ ++ urb->status = -ECONNRESET; ++ errno_dbg("Fixing unlink status of URB:0x%x[%d] to:%d\n", ++ (unsigned int)urb, urb_num, urb->status); ++ } ++ } else { ++ /* The USB Core wants to signal some error via the URB, pass it through */ ++ } ++ ++ /* hinko ignore usb_pipeisoc */ ++#if 0 ++ /* use completely different finish function for Isoc URBs */ ++ if(usb_pipeisoc(urb->pipe)) { ++ tc_finish_isoc_urb(hcd, urb, status); ++ return; ++ } ++#endif ++ ++ /* Do special unlinking of EPs for Intr traffic */ ++ if(usb_pipeint(urb->pipe)) { ++ tc_dma_unlink_intr_urb(urb); ++ } ++ ++ /* hinko ignore usb_pipeisoc */ ++#if 0 ++ /* Release allocated bandwidth for periodic transfers */ ++ if(usb_pipeint(urb->pipe) || usb_pipeisoc(urb->pipe)) ++ usb_release_bandwidth(urb->dev, urb, 0); ++#endif ++ ++ /* This URB is active on EP */ ++ if(urb == activeUrbList[epid]) { ++ /* We need to fiddle with the toggle bits because the hardware doesn't do ++ it for us. */ ++ toggle = etrax_epid_get_toggle(epid, usb_pipeout(urb->pipe)); ++ usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), ++ usb_pipeout(urb->pipe), toggle); ++ ++ /* Checks for Ctrl and Bulk EPs */ ++ switch(usb_pipetype(urb->pipe)) { ++ case PIPE_BULK: ++ /* Check so Bulk EP realy is disabled before finishing active URB */ ++ ASSERT((TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) == ++ IO_STATE(USB_EP_command, enable, no)); ++ /* Disable sub-pointer for EP to avoid next tx_interrupt() to ++ process Bulk EP. */ ++ TxBulkEPList[epid].sub = 0; ++ /* No need to wait for the DMA before changing the next pointer. ++ The modulo NBR_OF_EPIDS isn't actually necessary, since we will never use ++ the last one (INVALID_EPID) for actual traffic. */ ++ TxBulkEPList[epid].next = ++ virt_to_phys(&TxBulkEPList[(epid + 1) % NBR_OF_EPIDS]); ++ break; ++ case PIPE_CONTROL: ++ /* Check so Ctrl EP realy is disabled before finishing active URB */ ++ ASSERT((TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) == ++ IO_STATE(USB_EP_command, enable, no)); ++ /* Disable sub-pointer for EP to avoid next tx_interrupt() to ++ process Ctrl EP. */ ++ TxCtrlEPList[epid].sub = 0; ++ break; ++ } ++ } ++ ++ /* Free HC-private URB data*/ ++ urb_priv_free(hcd, urb); ++ ++ if(urb->status) { ++ errno_dbg("finish_urb (URB:0x%x[%d] %s %s) (data:%d) status:%d\n", ++ (unsigned int)urb, urb_num, str_dir(urb->pipe), ++ str_type(urb->pipe), urb->actual_length, urb->status); ++ } else { ++ tc_dbg("finish_urb (URB:0x%x[%d] %s %s) (data:%d) status:%d\n", ++ (unsigned int)urb, urb_num, str_dir(urb->pipe), ++ str_type(urb->pipe), urb->actual_length, urb->status); ++ } ++ ++ /* If we just finished an active URB, clear active pointer. */ ++ if (urb == activeUrbList[epid]) { ++ /* Make URB not active on EP anymore */ ++ activeUrbList[epid] = NULL; ++ ++ if(urb->status == 0) { ++ /* URB finished sucessfully, process queue to see if there are any more ++ URBs waiting before we call completion function.*/ ++ if(crisv10_hcd->running) { ++ /* Only process queue if USB controller is running */ ++ tc_dma_process_queue(epid); ++ } else { ++ tc_warn("No processing of queue for epid:%d, USB Controller not" ++ " running\n", epid); ++ } ++ } ++ } ++ ++ /* Hand the URB from HCD to its USB device driver, using its completion ++ functions */ ++// usb_hcd_giveback_urb (hcd, urb); ++ /** ++ * usb_hcd_unlink_urb_from_ep - remove an URB from its endpoint queue ++ * @hcd: host controller to which @urb was submitted ++ * @urb: URB being unlinked ++ * ++ * Host controller drivers should call this routine before calling ++ * usb_hcd_giveback_urb(). The HCD's private spinlock must be held and ++ * interrupts must be disabled. The actions carried out here are required ++ * for URB completion. ++ */ ++ ++ /*hinko link/unlink urb -> ep */ ++ //spin_lock(&crisv10_hcd->lock); ++ spin_lock_irqsave(&crisv10_hcd->lock, flags); ++ usb_hcd_unlink_urb_from_ep(hcd, urb); ++ usb_hcd_giveback_urb(hcd, urb, status); ++ //spin_unlock(&crisv10_hcd->lock); ++ spin_unlock_irqrestore(&crisv10_hcd->lock, flags); ++ ++ /* Check the queue once more if the URB returned with error, because we ++ didn't do it before the completion function because the specification ++ states that the queue should not restart until all it's unlinked ++ URBs have been fully retired, with the completion functions run */ ++ if(crisv10_hcd->running) { ++ /* Only process queue if USB controller is running */ ++ tc_dma_process_queue(epid); ++ } else { ++ tc_warn("No processing of queue for epid:%d, USB Controller not running\n", ++ epid); ++ } ++ ++ DBFEXIT; ++} ++ ++ /* hinko ignore usb_pipeisoc */ ++#if 0 ++static void tc_finish_isoc_urb(struct usb_hcd *hcd, struct urb *urb, ++ int status) { ++ struct crisv10_urb_priv *urb_priv = urb->hcpriv; ++ int epid, i; ++ volatile int timeout = 10000; ++ ++ ASSERT(urb_priv); ++ epid = urb_priv->epid; ++ ++ ASSERT(usb_pipeisoc(urb->pipe)); ++ ++ /* Set that all isoc packets have status and length set before ++ completing the urb. */ ++ for (i = urb_priv->isoc_packet_counter; i < urb->number_of_packets; i++){ ++ urb->iso_frame_desc[i].actual_length = 0; ++ urb->iso_frame_desc[i].status = -EPROTO; ++ } ++ ++ /* Check if the URB is currently active (done or error) */ ++ if(urb == activeUrbList[epid]) { ++ /* Check if there are another In Isoc URB queued for this epid */ ++ if (!list_empty(&urb_list[epid])&& !epid_state[epid].disabled) { ++ /* Move it from queue to active and mark it started so Isoc transfers ++ won't be interrupted. ++ All Isoc URBs data transfers are already added to DMA lists so we ++ don't have to insert anything in DMA lists here. */ ++ activeUrbList[epid] = urb_list_first(epid); ++ ((struct crisv10_urb_priv *)(activeUrbList[epid]->hcpriv))->urb_state = ++ STARTED; ++ urb_list_del(activeUrbList[epid], epid); ++ ++ if(urb->status) { ++ errno_dbg("finish_isoc_urb (URB:0x%x[%d] %s %s) (%d of %d packets)" ++ " status:%d, new waiting URB:0x%x[%d]\n", ++ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), ++ str_type(urb->pipe), urb_priv->isoc_packet_counter, ++ urb->number_of_packets, urb->status, ++ (unsigned int)activeUrbList[epid], ++ ((struct crisv10_urb_priv *)(activeUrbList[epid]->hcpriv))->urb_num); ++ } ++ ++ } else { /* No other URB queued for this epid */ ++ if(urb->status) { ++ errno_dbg("finish_isoc_urb (URB:0x%x[%d] %s %s) (%d of %d packets)" ++ " status:%d, no new URB waiting\n", ++ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), ++ str_type(urb->pipe), urb_priv->isoc_packet_counter, ++ urb->number_of_packets, urb->status); ++ } ++ ++ /* Check if EP is still enabled, then shut it down. */ ++ if (TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable)) { ++ isoc_dbg("Isoc EP enabled for epid:%d, disabling it\n", epid); ++ ++ /* Should only occur for In Isoc EPs where SB isn't consumed. */ ++ ASSERT(usb_pipein(urb->pipe)); ++ ++ /* Disable it and wait for it to stop */ ++ TxIsocEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); ++ ++ /* Ah, the luxury of busy-wait. */ ++ while((*R_DMA_CH8_SUB3_EP == virt_to_phys(&TxIsocEPList[epid])) && ++ (timeout-- > 0)); ++ if(timeout == 0) { ++ warn("Timeout while waiting for DMA-TX-Isoc to leave EP for epid:%d\n", epid); ++ } ++ } ++ ++ /* Unlink SB to say that epid is finished. */ ++ TxIsocEPList[epid].sub = 0; ++ TxIsocEPList[epid].hw_len = 0; ++ ++ /* No URB active for EP anymore */ ++ activeUrbList[epid] = NULL; ++ } ++ } else { /* Finishing of not active URB (queued up with SBs thought) */ ++ isoc_warn("finish_isoc_urb (URB:0x%x %s) (%d of %d packets) status:%d," ++ " SB queued but not active\n", ++ (unsigned int)urb, str_dir(urb->pipe), ++ urb_priv->isoc_packet_counter, urb->number_of_packets, ++ urb->status); ++ if(usb_pipeout(urb->pipe)) { ++ /* Finishing of not yet active Out Isoc URB needs unlinking of SBs. */ ++ struct USB_SB_Desc *iter_sb, *prev_sb, *next_sb; ++ ++ iter_sb = TxIsocEPList[epid].sub ? ++ phys_to_virt(TxIsocEPList[epid].sub) : 0; ++ prev_sb = 0; ++ ++ /* SB that is linked before this URBs first SB */ ++ while (iter_sb && (iter_sb != urb_priv->first_sb)) { ++ prev_sb = iter_sb; ++ iter_sb = iter_sb->next ? phys_to_virt(iter_sb->next) : 0; ++ } ++ ++ if (iter_sb == 0) { ++ /* Unlink of the URB currently being transmitted. */ ++ prev_sb = 0; ++ iter_sb = TxIsocEPList[epid].sub ? phys_to_virt(TxIsocEPList[epid].sub) : 0; ++ } ++ ++ while (iter_sb && (iter_sb != urb_priv->last_sb)) { ++ iter_sb = iter_sb->next ? phys_to_virt(iter_sb->next) : 0; ++ } ++ ++ if (iter_sb) { ++ next_sb = iter_sb->next ? phys_to_virt(iter_sb->next) : 0; ++ } else { ++ /* This should only happen if the DMA has completed ++ processing the SB list for this EP while interrupts ++ are disabled. */ ++ isoc_dbg("Isoc urb not found, already sent?\n"); ++ next_sb = 0; ++ } ++ if (prev_sb) { ++ prev_sb->next = next_sb ? virt_to_phys(next_sb) : 0; ++ } else { ++ TxIsocEPList[epid].sub = next_sb ? virt_to_phys(next_sb) : 0; ++ } ++ } ++ } ++ ++ /* Free HC-private URB data*/ ++ urb_priv_free(hcd, urb); ++ ++ usb_release_bandwidth(urb->dev, urb, 0); ++ ++ /* Hand the URB from HCD to its USB device driver, using its completion ++ functions */ ++ usb_hcd_giveback_urb (hcd, urb); ++} ++#endif ++ ++static __u32 urb_num = 0; ++ ++/* allocate and initialize URB private data */ ++static int urb_priv_create(struct usb_hcd *hcd, struct urb *urb, int epid, ++ int mem_flags) { ++ struct crisv10_urb_priv *urb_priv; ++ ++ urb_priv = kmalloc(sizeof *urb_priv, mem_flags); ++ if (!urb_priv) ++ return -ENOMEM; ++ memset(urb_priv, 0, sizeof *urb_priv); ++ ++ urb_priv->epid = epid; ++ urb_priv->urb_state = NOT_STARTED; ++ ++ urb->hcpriv = urb_priv; ++ /* Assign URB a sequence number, and increment counter */ ++ urb_priv->urb_num = urb_num; ++ urb_num++; ++ return 0; ++} ++ ++/* free URB private data */ ++static void urb_priv_free(struct usb_hcd *hcd, struct urb *urb) { ++ int i; ++ struct crisv10_urb_priv *urb_priv = urb->hcpriv; ++ ASSERT(urb_priv != 0); ++ ++ /* Check it has any SBs linked that needs to be freed*/ ++ if(urb_priv->first_sb != NULL) { ++ struct USB_SB_Desc *next_sb, *first_sb, *last_sb; ++ int i = 0; ++ first_sb = urb_priv->first_sb; ++ last_sb = urb_priv->last_sb; ++ ASSERT(last_sb); ++ while(first_sb != last_sb) { ++ next_sb = (struct USB_SB_Desc *)phys_to_virt(first_sb->next); ++ kmem_cache_free(usb_desc_cache, first_sb); ++ first_sb = next_sb; ++ i++; ++ } ++ kmem_cache_free(usb_desc_cache, last_sb); ++ i++; ++ } ++ ++ /* Check if it has any EPs in its Intr pool that also needs to be freed */ ++ if(urb_priv->intr_ep_pool_length > 0) { ++ for(i = 0; i < urb_priv->intr_ep_pool_length; i++) { ++ kfree(urb_priv->intr_ep_pool[i]); ++ } ++ /* ++ tc_dbg("Freed %d EPs from URB:0x%x EP pool\n", ++ urb_priv->intr_ep_pool_length, (unsigned int)urb); ++ */ ++ } ++ ++ kfree(urb_priv); ++ urb->hcpriv = NULL; ++} ++ ++static int ep_priv_create(struct usb_host_endpoint *ep, int mem_flags) { ++ struct crisv10_ep_priv *ep_priv; ++ ++ ep_priv = kmalloc(sizeof *ep_priv, mem_flags); ++ if (!ep_priv) ++ return -ENOMEM; ++ memset(ep_priv, 0, sizeof *ep_priv); ++ ++ ep->hcpriv = ep_priv; ++ return 0; ++} ++ ++static void ep_priv_free(struct usb_host_endpoint *ep) { ++ struct crisv10_ep_priv *ep_priv = ep->hcpriv; ++ ASSERT(ep_priv); ++ kfree(ep_priv); ++ ep->hcpriv = NULL; ++} ++ ++/* EPID handling functions, managing EP-list in Etrax through wrappers */ ++/* ------------------------------------------------------------------- */ ++ ++/* Sets up a new EPID for an endpoint or returns existing if found */ ++//static int tc_setup_epid(struct usb_host_endpoint *ep, struct urb *urb, ++// int mem_flags) { ++static int tc_setup_epid(struct urb *urb, int mem_flags) ++{ ++ int epid; ++ char devnum, endpoint, out_traffic, slow; ++ int maxlen; ++ __u32 epid_data; ++ struct usb_host_endpoint *ep = urb->ep; ++ struct crisv10_ep_priv *ep_priv = ep->hcpriv; ++ ++ DBFENTER; ++ ++ /* Check if a valid epid already is setup for this endpoint */ ++ if(ep_priv != NULL) { ++ return ep_priv->epid; ++ } ++ ++ /* We must find and initiate a new epid for this urb. */ ++ epid = tc_allocate_epid(); ++ ++ if (epid == -1) { ++ /* Failed to allocate a new epid. */ ++ DBFEXIT; ++ return epid; ++ } ++ ++ /* We now have a new epid to use. Claim it. */ ++ epid_state[epid].inuse = 1; ++ ++ /* Init private data for new endpoint */ ++ if(ep_priv_create(ep, mem_flags) != 0) { ++ return -ENOMEM; ++ } ++ ep_priv = ep->hcpriv; ++ ep_priv->epid = epid; ++ ++ devnum = usb_pipedevice(urb->pipe); ++ endpoint = usb_pipeendpoint(urb->pipe); ++ slow = (urb->dev->speed == USB_SPEED_LOW); ++ maxlen = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); ++ ++ if (usb_pipetype(urb->pipe) == PIPE_CONTROL) { ++ /* We want both IN and OUT control traffic to be put on the same ++ EP/SB list. */ ++ out_traffic = 1; ++ } else { ++ out_traffic = usb_pipeout(urb->pipe); ++ } ++ ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ epid_data = IO_STATE(R_USB_EPT_DATA_ISO, valid, yes) | ++ /* FIXME: Change any to the actual port? */ ++ IO_STATE(R_USB_EPT_DATA_ISO, port, any) | ++ IO_FIELD(R_USB_EPT_DATA_ISO, max_len, maxlen) | ++ IO_FIELD(R_USB_EPT_DATA_ISO, ep, endpoint) | ++ IO_FIELD(R_USB_EPT_DATA_ISO, dev, devnum); ++ etrax_epid_iso_set(epid, epid_data); ++ } else { ++ epid_data = IO_STATE(R_USB_EPT_DATA, valid, yes) | ++ IO_FIELD(R_USB_EPT_DATA, low_speed, slow) | ++ /* FIXME: Change any to the actual port? */ ++ IO_STATE(R_USB_EPT_DATA, port, any) | ++ IO_FIELD(R_USB_EPT_DATA, max_len, maxlen) | ++ IO_FIELD(R_USB_EPT_DATA, ep, endpoint) | ++ IO_FIELD(R_USB_EPT_DATA, dev, devnum); ++ etrax_epid_set(epid, epid_data); ++ } ++ ++ epid_state[epid].out_traffic = out_traffic; ++ epid_state[epid].type = usb_pipetype(urb->pipe); ++ ++ tc_warn("Setting up ep:0x%x epid:%d (addr:%d endp:%d max_len:%d %s %s %s)\n", ++ (unsigned int)ep, epid, devnum, endpoint, maxlen, ++ str_type(urb->pipe), out_traffic ? "out" : "in", ++ slow ? "low" : "full"); ++ ++ /* Enable Isoc eof interrupt if we set up the first Isoc epid */ ++ if(usb_pipeisoc(urb->pipe)) { ++ isoc_epid_counter++; ++ if(isoc_epid_counter == 1) { ++ isoc_warn("Enabled Isoc eof interrupt\n"); ++ *R_USB_IRQ_MASK_SET |= IO_STATE(R_USB_IRQ_MASK_SET, iso_eof, set); ++ } ++ } ++ ++ DBFEXIT; ++ return epid; ++} ++ ++static void tc_free_epid(struct usb_host_endpoint *ep) { ++ unsigned long flags; ++ struct crisv10_ep_priv *ep_priv = ep->hcpriv; ++ int epid; ++ volatile int timeout = 10000; ++ ++ DBFENTER; ++ ++ if (ep_priv == NULL) { ++ tc_warn("Trying to free unused epid on ep:0x%x\n", (unsigned int)ep); ++ DBFEXIT; ++ return; ++ } ++ ++ epid = ep_priv->epid; ++ ++ /* Disable Isoc eof interrupt if we free the last Isoc epid */ ++ if(epid_isoc(epid)) { ++ ASSERT(isoc_epid_counter > 0); ++ isoc_epid_counter--; ++ if(isoc_epid_counter == 0) { ++ *R_USB_IRQ_MASK_SET &= ~IO_STATE(R_USB_IRQ_MASK_SET, iso_eof, set); ++ isoc_warn("Disabled Isoc eof interrupt\n"); ++ } ++ } ++ ++ /* Take lock manualy instead of in epid_x_x wrappers, ++ because we need to be polling here */ ++ spin_lock_irqsave(&etrax_epid_lock, flags); ++ ++ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, epid); ++ nop(); ++ while((*R_USB_EPT_DATA & IO_MASK(R_USB_EPT_DATA, hold)) && ++ (timeout-- > 0)); ++ if(timeout == 0) { ++ warn("Timeout while waiting for epid:%d to drop hold\n", epid); ++ } ++ /* This will, among other things, set the valid field to 0. */ ++ *R_USB_EPT_DATA = 0; ++ spin_unlock_irqrestore(&etrax_epid_lock, flags); ++ ++ /* Free resource in software state info list */ ++ epid_state[epid].inuse = 0; ++ ++ /* Free private endpoint data */ ++ ep_priv_free(ep); ++ ++ DBFEXIT; ++} ++ ++static int tc_allocate_epid(void) { ++ int i; ++ DBFENTER; ++ for (i = 0; i < NBR_OF_EPIDS; i++) { ++ if (!epid_inuse(i)) { ++ DBFEXIT; ++ return i; ++ } ++ } ++ ++ tc_warn("Found no free epids\n"); ++ DBFEXIT; ++ return -1; ++} ++ ++ ++/* Wrappers around the list functions (include/linux/list.h). */ ++/* ---------------------------------------------------------- */ ++static inline int __urb_list_empty(int epid) { ++ int retval; ++ retval = list_empty(&urb_list[epid]); ++ return retval; ++} ++ ++/* Returns first urb for this epid, or NULL if list is empty. */ ++static inline struct urb *urb_list_first(int epid) { ++ unsigned long flags; ++ struct urb *first_urb = 0; ++ spin_lock_irqsave(&urb_list_lock, flags); ++ if (!__urb_list_empty(epid)) { ++ /* Get the first urb (i.e. head->next). */ ++ urb_entry_t *urb_entry = list_entry((&urb_list[epid])->next, urb_entry_t, list); ++ first_urb = urb_entry->urb; ++ } ++ spin_unlock_irqrestore(&urb_list_lock, flags); ++ return first_urb; ++} ++ ++/* Adds an urb_entry last in the list for this epid. */ ++static inline void urb_list_add(struct urb *urb, int epid, int mem_flags) { ++ unsigned long flags; ++ urb_entry_t *urb_entry = (urb_entry_t *)kmalloc(sizeof(urb_entry_t), mem_flags); ++ ASSERT(urb_entry); ++ ++ urb_entry->urb = urb; ++ spin_lock_irqsave(&urb_list_lock, flags); ++ list_add_tail(&urb_entry->list, &urb_list[epid]); ++ spin_unlock_irqrestore(&urb_list_lock, flags); ++} ++ ++/* Search through the list for an element that contains this urb. (The list ++ is expected to be short and the one we are about to delete will often be ++ the first in the list.) ++ Should be protected by spin_locks in calling function */ ++static inline urb_entry_t *__urb_list_entry(struct urb *urb, int epid) { ++ struct list_head *entry; ++ struct list_head *tmp; ++ urb_entry_t *urb_entry; ++ ++ list_for_each_safe(entry, tmp, &urb_list[epid]) { ++ urb_entry = list_entry(entry, urb_entry_t, list); ++ ASSERT(urb_entry); ++ ASSERT(urb_entry->urb); ++ ++ if (urb_entry->urb == urb) { ++ return urb_entry; ++ } ++ } ++ return 0; ++} ++ ++/* Same function as above but for global use. Protects list by spinlock */ ++static inline urb_entry_t *urb_list_entry(struct urb *urb, int epid) { ++ unsigned long flags; ++ urb_entry_t *urb_entry; ++ spin_lock_irqsave(&urb_list_lock, flags); ++ urb_entry = __urb_list_entry(urb, epid); ++ spin_unlock_irqrestore(&urb_list_lock, flags); ++ return (urb_entry); ++} ++ ++/* Delete an urb from the list. */ ++static inline void urb_list_del(struct urb *urb, int epid) { ++ unsigned long flags; ++ urb_entry_t *urb_entry; ++ ++ /* Delete entry and free. */ ++ spin_lock_irqsave(&urb_list_lock, flags); ++ urb_entry = __urb_list_entry(urb, epid); ++ ASSERT(urb_entry); ++ ++ list_del(&urb_entry->list); ++ spin_unlock_irqrestore(&urb_list_lock, flags); ++ kfree(urb_entry); ++} ++ ++/* Move an urb to the end of the list. */ ++static inline void urb_list_move_last(struct urb *urb, int epid) { ++ unsigned long flags; ++ urb_entry_t *urb_entry; ++ ++ spin_lock_irqsave(&urb_list_lock, flags); ++ urb_entry = __urb_list_entry(urb, epid); ++ ASSERT(urb_entry); ++ ++ list_del(&urb_entry->list); ++ list_add_tail(&urb_entry->list, &urb_list[epid]); ++ spin_unlock_irqrestore(&urb_list_lock, flags); ++} ++ ++/* Get the next urb in the list. */ ++static inline struct urb *urb_list_next(struct urb *urb, int epid) { ++ unsigned long flags; ++ urb_entry_t *urb_entry; ++ ++ spin_lock_irqsave(&urb_list_lock, flags); ++ urb_entry = __urb_list_entry(urb, epid); ++ ASSERT(urb_entry); ++ ++ if (urb_entry->list.next != &urb_list[epid]) { ++ struct list_head *elem = urb_entry->list.next; ++ urb_entry = list_entry(elem, urb_entry_t, list); ++ spin_unlock_irqrestore(&urb_list_lock, flags); ++ return urb_entry->urb; ++ } else { ++ spin_unlock_irqrestore(&urb_list_lock, flags); ++ return NULL; ++ } ++} ++ ++struct USB_EP_Desc* create_ep(int epid, struct USB_SB_Desc* sb_desc, ++ int mem_flags) { ++ struct USB_EP_Desc *ep_desc; ++ ep_desc = (struct USB_EP_Desc *) kmem_cache_alloc(usb_desc_cache, mem_flags); ++ if(ep_desc == NULL) ++ return NULL; ++ memset(ep_desc, 0, sizeof(struct USB_EP_Desc)); ++ ++ ep_desc->hw_len = 0; ++ ep_desc->command = (IO_FIELD(USB_EP_command, epid, epid) | ++ IO_STATE(USB_EP_command, enable, yes)); ++ if(sb_desc == NULL) { ++ ep_desc->sub = 0; ++ } else { ++ ep_desc->sub = virt_to_phys(sb_desc); ++ } ++ return ep_desc; ++} ++ ++#define TT_ZOUT 0 ++#define TT_IN 1 ++#define TT_OUT 2 ++#define TT_SETUP 3 ++ ++#define CMD_EOL IO_STATE(USB_SB_command, eol, yes) ++#define CMD_INTR IO_STATE(USB_SB_command, intr, yes) ++#define CMD_FULL IO_STATE(USB_SB_command, full, yes) ++ ++/* Allocation and setup of a generic SB. Used to create SETUP, OUT and ZOUT ++ SBs. Also used by create_sb_in() to avoid same allocation procedure at two ++ places */ ++struct USB_SB_Desc* create_sb(struct USB_SB_Desc* sb_prev, int tt, void* data, ++ int datalen, int mem_flags) { ++ struct USB_SB_Desc *sb_desc; ++ sb_desc = (struct USB_SB_Desc*)kmem_cache_alloc(usb_desc_cache, mem_flags); ++ if(sb_desc == NULL) ++ return NULL; ++ memset(sb_desc, 0, sizeof(struct USB_SB_Desc)); ++ ++ sb_desc->command = IO_FIELD(USB_SB_command, tt, tt) | ++ IO_STATE(USB_SB_command, eot, yes); ++ ++ sb_desc->sw_len = datalen; ++ if(data != NULL) { ++ sb_desc->buf = virt_to_phys(data); ++ } else { ++ sb_desc->buf = 0; ++ } ++ if(sb_prev != NULL) { ++ sb_prev->next = virt_to_phys(sb_desc); ++ } ++ return sb_desc; ++} ++ ++/* Creates a copy of an existing SB by allocation space for it and copy ++ settings */ ++struct USB_SB_Desc* create_sb_copy(struct USB_SB_Desc* sb_orig, int mem_flags) { ++ struct USB_SB_Desc *sb_desc; ++ sb_desc = (struct USB_SB_Desc*)kmem_cache_alloc(usb_desc_cache, mem_flags); ++ if(sb_desc == NULL) ++ return NULL; ++ ++ memcpy(sb_desc, sb_orig, sizeof(struct USB_SB_Desc)); ++ return sb_desc; ++} ++ ++/* A specific create_sb function for creation of in SBs. This is due to ++ that datalen in In SBs shows how many packets we are expecting. It also ++ sets up the rem field to show if how many bytes we expect in last packet ++ if it's not a full one */ ++struct USB_SB_Desc* create_sb_in(struct USB_SB_Desc* sb_prev, int datalen, ++ int maxlen, int mem_flags) { ++ struct USB_SB_Desc *sb_desc; ++ sb_desc = create_sb(sb_prev, TT_IN, NULL, ++ datalen ? (datalen - 1) / maxlen + 1 : 0, mem_flags); ++ if(sb_desc == NULL) ++ return NULL; ++ sb_desc->command |= IO_FIELD(USB_SB_command, rem, datalen % maxlen); ++ return sb_desc; ++} ++ ++void set_sb_cmds(struct USB_SB_Desc *sb_desc, __u16 flags) { ++ sb_desc->command |= flags; ++} ++ ++int create_sb_for_urb(struct urb *urb, int mem_flags) { ++ int is_out = !usb_pipein(urb->pipe); ++ int type = usb_pipetype(urb->pipe); ++ int maxlen = usb_maxpacket(urb->dev, urb->pipe, is_out); ++ int buf_len = urb->transfer_buffer_length; ++ void *buf = buf_len > 0 ? urb->transfer_buffer : NULL; ++ struct USB_SB_Desc *sb_desc = NULL; ++ ++ struct crisv10_urb_priv *urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; ++ ASSERT(urb_priv != NULL); ++ ++ switch(type) { ++ case PIPE_CONTROL: ++ /* Setup stage */ ++ sb_desc = create_sb(NULL, TT_SETUP, urb->setup_packet, 8, mem_flags); ++ if(sb_desc == NULL) ++ return -ENOMEM; ++ set_sb_cmds(sb_desc, CMD_FULL); ++ ++ /* Attach first SB to URB */ ++ urb_priv->first_sb = sb_desc; ++ ++ if (is_out) { /* Out Control URB */ ++ /* If this Control OUT transfer has an optional data stage we add ++ an OUT token before the mandatory IN (status) token */ ++ if ((buf_len > 0) && buf) { ++ sb_desc = create_sb(sb_desc, TT_OUT, buf, buf_len, mem_flags); ++ if(sb_desc == NULL) ++ return -ENOMEM; ++ set_sb_cmds(sb_desc, CMD_FULL); ++ } ++ ++ /* Status stage */ ++ /* The data length has to be exactly 1. This is due to a requirement ++ of the USB specification that a host must be prepared to receive ++ data in the status phase */ ++ sb_desc = create_sb(sb_desc, TT_IN, NULL, 1, mem_flags); ++ if(sb_desc == NULL) ++ return -ENOMEM; ++ } else { /* In control URB */ ++ /* Data stage */ ++ sb_desc = create_sb_in(sb_desc, buf_len, maxlen, mem_flags); ++ if(sb_desc == NULL) ++ return -ENOMEM; ++ ++ /* Status stage */ ++ /* Read comment at zout_buffer declaration for an explanation to this. */ ++ sb_desc = create_sb(sb_desc, TT_ZOUT, &zout_buffer[0], 1, mem_flags); ++ if(sb_desc == NULL) ++ return -ENOMEM; ++ /* Set descriptor interrupt flag for in URBs so we can finish URB after ++ zout-packet has been sent */ ++ set_sb_cmds(sb_desc, CMD_INTR | CMD_FULL); ++ } ++ /* Set end-of-list flag in last SB */ ++ set_sb_cmds(sb_desc, CMD_EOL); ++ /* Attach last SB to URB */ ++ urb_priv->last_sb = sb_desc; ++ break; ++ ++ case PIPE_BULK: ++ if (is_out) { /* Out Bulk URB */ ++ sb_desc = create_sb(NULL, TT_OUT, buf, buf_len, mem_flags); ++ if(sb_desc == NULL) ++ return -ENOMEM; ++ /* The full field is set to yes, even if we don't actually check that ++ this is a full-length transfer (i.e., that transfer_buffer_length % ++ maxlen = 0). ++ Setting full prevents the USB controller from sending an empty packet ++ in that case. However, if URB_ZERO_PACKET was set we want that. */ ++ if (!(urb->transfer_flags & URB_ZERO_PACKET)) { ++ set_sb_cmds(sb_desc, CMD_FULL); ++ } ++ } else { /* In Bulk URB */ ++ sb_desc = create_sb_in(NULL, buf_len, maxlen, mem_flags); ++ if(sb_desc == NULL) ++ return -ENOMEM; ++ } ++ /* Set end-of-list flag for last SB */ ++ set_sb_cmds(sb_desc, CMD_EOL); ++ ++ /* Attach SB to URB */ ++ urb_priv->first_sb = sb_desc; ++ urb_priv->last_sb = sb_desc; ++ break; ++ ++ case PIPE_INTERRUPT: ++ if(is_out) { /* Out Intr URB */ ++ sb_desc = create_sb(NULL, TT_OUT, buf, buf_len, mem_flags); ++ if(sb_desc == NULL) ++ return -ENOMEM; ++ ++ /* The full field is set to yes, even if we don't actually check that ++ this is a full-length transfer (i.e., that transfer_buffer_length % ++ maxlen = 0). ++ Setting full prevents the USB controller from sending an empty packet ++ in that case. However, if URB_ZERO_PACKET was set we want that. */ ++ if (!(urb->transfer_flags & URB_ZERO_PACKET)) { ++ set_sb_cmds(sb_desc, CMD_FULL); ++ } ++ /* Only generate TX interrupt if it's a Out URB*/ ++ set_sb_cmds(sb_desc, CMD_INTR); ++ ++ } else { /* In Intr URB */ ++ sb_desc = create_sb_in(NULL, buf_len, maxlen, mem_flags); ++ if(sb_desc == NULL) ++ return -ENOMEM; ++ } ++ /* Set end-of-list flag for last SB */ ++ set_sb_cmds(sb_desc, CMD_EOL); ++ ++ /* Attach SB to URB */ ++ urb_priv->first_sb = sb_desc; ++ urb_priv->last_sb = sb_desc; ++ ++ break; ++ case PIPE_ISOCHRONOUS: ++ if(is_out) { /* Out Isoc URB */ ++ int i; ++ if(urb->number_of_packets == 0) { ++ tc_err("Can't create SBs for Isoc URB with zero packets\n"); ++ return -EPIPE; ++ } ++ /* Create one SB descriptor for each packet and link them together. */ ++ for(i = 0; i < urb->number_of_packets; i++) { ++ if (urb->iso_frame_desc[i].length > 0) { ++ ++ sb_desc = create_sb(sb_desc, TT_OUT, urb->transfer_buffer + ++ urb->iso_frame_desc[i].offset, ++ urb->iso_frame_desc[i].length, mem_flags); ++ if(sb_desc == NULL) ++ return -ENOMEM; ++ ++ /* Check if it's a full length packet */ ++ if (urb->iso_frame_desc[i].length == ++ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))) { ++ set_sb_cmds(sb_desc, CMD_FULL); ++ } ++ ++ } else { /* zero length packet */ ++ sb_desc = create_sb(sb_desc, TT_ZOUT, &zout_buffer[0], 1, mem_flags); ++ if(sb_desc == NULL) ++ return -ENOMEM; ++ set_sb_cmds(sb_desc, CMD_FULL); ++ } ++ /* Attach first SB descriptor to URB */ ++ if (i == 0) { ++ urb_priv->first_sb = sb_desc; ++ } ++ } ++ /* Set interrupt and end-of-list flags in last SB */ ++ set_sb_cmds(sb_desc, CMD_INTR | CMD_EOL); ++ /* Attach last SB descriptor to URB */ ++ urb_priv->last_sb = sb_desc; ++ tc_dbg("Created %d out SBs for Isoc URB:0x%x\n", ++ urb->number_of_packets, (unsigned int)urb); ++ } else { /* In Isoc URB */ ++ /* Actual number of packets is not relevant for periodic in traffic as ++ long as it is more than zero. Set to 1 always. */ ++ sb_desc = create_sb(sb_desc, TT_IN, NULL, 1, mem_flags); ++ if(sb_desc == NULL) ++ return -ENOMEM; ++ /* Set end-of-list flags for SB */ ++ set_sb_cmds(sb_desc, CMD_EOL); ++ ++ /* Attach SB to URB */ ++ urb_priv->first_sb = sb_desc; ++ urb_priv->last_sb = sb_desc; ++ } ++ break; ++ default: ++ tc_err("Unknown pipe-type\n"); ++ return -EPIPE; ++ break; ++ } ++ return 0; ++} ++ ++int init_intr_urb(struct urb *urb, int mem_flags) { ++ struct crisv10_urb_priv *urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; ++ struct USB_EP_Desc* ep_desc; ++ int interval; ++ int i; ++ int ep_count; ++ ++ ASSERT(urb_priv != NULL); ++ ASSERT(usb_pipeint(urb->pipe)); ++ /* We can't support interval longer than amount of eof descriptors in ++ TxIntrEPList */ ++ if(urb->interval > MAX_INTR_INTERVAL) { ++ tc_err("Interrupt interval %dms too big (max: %dms)\n", urb->interval, ++ MAX_INTR_INTERVAL); ++ return -EINVAL; ++ } ++ ++ /* We assume that the SB descriptors already have been setup */ ++ ASSERT(urb_priv->first_sb != NULL); ++ ++ /* Round of the interval to 2^n, it is obvious that this code favours ++ smaller numbers, but that is actually a good thing */ ++ /* FIXME: The "rounding error" for larger intervals will be quite ++ large. For in traffic this shouldn't be a problem since it will only ++ mean that we "poll" more often. */ ++ interval = urb->interval; ++ for (i = 0; interval; i++) { ++ interval = interval >> 1; ++ } ++ urb_priv->interval = 1 << (i - 1); ++ ++ /* We can only have max interval for Out Interrupt due to that we can only ++ handle one linked in EP for a certain epid in the Intr descr array at the ++ time. The USB Controller in the Etrax 100LX continues to process Intr EPs ++ so we have no way of knowing which one that caused the actual transfer if ++ we have several linked in. */ ++ if(usb_pipeout(urb->pipe)) { ++ urb_priv->interval = MAX_INTR_INTERVAL; ++ } ++ ++ /* Calculate amount of EPs needed */ ++ ep_count = MAX_INTR_INTERVAL / urb_priv->interval; ++ ++ for(i = 0; i < ep_count; i++) { ++ ep_desc = create_ep(urb_priv->epid, urb_priv->first_sb, mem_flags); ++ if(ep_desc == NULL) { ++ /* Free any descriptors that we may have allocated before failure */ ++ while(i > 0) { ++ i--; ++ kfree(urb_priv->intr_ep_pool[i]); ++ } ++ return -ENOMEM; ++ } ++ urb_priv->intr_ep_pool[i] = ep_desc; ++ } ++ urb_priv->intr_ep_pool_length = ep_count; ++ return 0; ++} ++ ++/* DMA RX/TX functions */ ++/* ----------------------- */ ++ ++static void tc_dma_init_rx_list(void) { ++ int i; ++ ++ /* Setup descriptor list except last one */ ++ for (i = 0; i < (NBR_OF_RX_DESC - 1); i++) { ++ RxDescList[i].sw_len = RX_DESC_BUF_SIZE; ++ RxDescList[i].command = 0; ++ RxDescList[i].next = virt_to_phys(&RxDescList[i + 1]); ++ RxDescList[i].buf = virt_to_phys(RxBuf + (i * RX_DESC_BUF_SIZE)); ++ RxDescList[i].hw_len = 0; ++ RxDescList[i].status = 0; ++ ++ /* DMA IN cache bug. (struct etrax_dma_descr has the same layout as ++ USB_IN_Desc for the relevant fields.) */ ++ prepare_rx_descriptor((struct etrax_dma_descr*)&RxDescList[i]); ++ ++ } ++ /* Special handling of last descriptor */ ++ RxDescList[i].sw_len = RX_DESC_BUF_SIZE; ++ RxDescList[i].command = IO_STATE(USB_IN_command, eol, yes); ++ RxDescList[i].next = virt_to_phys(&RxDescList[0]); ++ RxDescList[i].buf = virt_to_phys(RxBuf + (i * RX_DESC_BUF_SIZE)); ++ RxDescList[i].hw_len = 0; ++ RxDescList[i].status = 0; ++ ++ /* Setup list pointers that show progress in list */ ++ myNextRxDesc = &RxDescList[0]; ++ myLastRxDesc = &RxDescList[NBR_OF_RX_DESC - 1]; ++ ++ flush_etrax_cache(); ++ /* Point DMA to first descriptor in list and start it */ ++ *R_DMA_CH9_FIRST = virt_to_phys(myNextRxDesc); ++ *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, start); ++} ++ ++ ++static void tc_dma_init_tx_bulk_list(void) { ++ int i; ++ volatile struct USB_EP_Desc *epDescr; ++ ++ for (i = 0; i < (NBR_OF_EPIDS - 1); i++) { ++ epDescr = &(TxBulkEPList[i]); ++ CHECK_ALIGN(epDescr); ++ epDescr->hw_len = 0; ++ epDescr->command = IO_FIELD(USB_EP_command, epid, i); ++ epDescr->sub = 0; ++ epDescr->next = virt_to_phys(&TxBulkEPList[i + 1]); ++ ++ /* Initiate two EPs, disabled and with the eol flag set. No need for any ++ preserved epid. */ ++ ++ /* The first one has the intr flag set so we get an interrupt when the DMA ++ channel is about to become disabled. */ ++ CHECK_ALIGN(&TxBulkDummyEPList[i][0]); ++ TxBulkDummyEPList[i][0].hw_len = 0; ++ TxBulkDummyEPList[i][0].command = (IO_FIELD(USB_EP_command, epid, DUMMY_EPID) | ++ IO_STATE(USB_EP_command, eol, yes) | ++ IO_STATE(USB_EP_command, intr, yes)); ++ TxBulkDummyEPList[i][0].sub = 0; ++ TxBulkDummyEPList[i][0].next = virt_to_phys(&TxBulkDummyEPList[i][1]); ++ ++ /* The second one. */ ++ CHECK_ALIGN(&TxBulkDummyEPList[i][1]); ++ TxBulkDummyEPList[i][1].hw_len = 0; ++ TxBulkDummyEPList[i][1].command = (IO_FIELD(USB_EP_command, epid, DUMMY_EPID) | ++ IO_STATE(USB_EP_command, eol, yes)); ++ TxBulkDummyEPList[i][1].sub = 0; ++ /* The last dummy's next pointer is the same as the current EP's next pointer. */ ++ TxBulkDummyEPList[i][1].next = virt_to_phys(&TxBulkEPList[i + 1]); ++ } ++ ++ /* Special handling of last descr in list, make list circular */ ++ epDescr = &TxBulkEPList[i]; ++ CHECK_ALIGN(epDescr); ++ epDescr->hw_len = 0; ++ epDescr->command = IO_STATE(USB_EP_command, eol, yes) | ++ IO_FIELD(USB_EP_command, epid, i); ++ epDescr->sub = 0; ++ epDescr->next = virt_to_phys(&TxBulkEPList[0]); ++ ++ /* Init DMA sub-channel pointers to last item in each list */ ++ *R_DMA_CH8_SUB0_EP = virt_to_phys(&TxBulkEPList[i]); ++ /* No point in starting the bulk channel yet. ++ *R_DMA_CH8_SUB0_CMD = IO_STATE(R_DMA_CH8_SUB0_CMD, cmd, start); */ ++} ++ ++static void tc_dma_init_tx_ctrl_list(void) { ++ int i; ++ volatile struct USB_EP_Desc *epDescr; ++ ++ for (i = 0; i < (NBR_OF_EPIDS - 1); i++) { ++ epDescr = &(TxCtrlEPList[i]); ++ CHECK_ALIGN(epDescr); ++ epDescr->hw_len = 0; ++ epDescr->command = IO_FIELD(USB_EP_command, epid, i); ++ epDescr->sub = 0; ++ epDescr->next = virt_to_phys(&TxCtrlEPList[i + 1]); ++ } ++ /* Special handling of last descr in list, make list circular */ ++ epDescr = &TxCtrlEPList[i]; ++ CHECK_ALIGN(epDescr); ++ epDescr->hw_len = 0; ++ epDescr->command = IO_STATE(USB_EP_command, eol, yes) | ++ IO_FIELD(USB_EP_command, epid, i); ++ epDescr->sub = 0; ++ epDescr->next = virt_to_phys(&TxCtrlEPList[0]); ++ ++ /* Init DMA sub-channel pointers to last item in each list */ ++ *R_DMA_CH8_SUB1_EP = virt_to_phys(&TxCtrlEPList[i]); ++ /* No point in starting the ctrl channel yet. ++ *R_DMA_CH8_SUB1_CMD = IO_STATE(R_DMA_CH8_SUB0_CMD, cmd, start); */ ++} ++ ++ ++static void tc_dma_init_tx_intr_list(void) { ++ int i; ++ ++ TxIntrSB_zout.sw_len = 1; ++ TxIntrSB_zout.next = 0; ++ TxIntrSB_zout.buf = virt_to_phys(&zout_buffer[0]); ++ TxIntrSB_zout.command = (IO_FIELD(USB_SB_command, rem, 0) | ++ IO_STATE(USB_SB_command, tt, zout) | ++ IO_STATE(USB_SB_command, full, yes) | ++ IO_STATE(USB_SB_command, eot, yes) | ++ IO_STATE(USB_SB_command, eol, yes)); ++ ++ for (i = 0; i < (MAX_INTR_INTERVAL - 1); i++) { ++ CHECK_ALIGN(&TxIntrEPList[i]); ++ TxIntrEPList[i].hw_len = 0; ++ TxIntrEPList[i].command = ++ (IO_STATE(USB_EP_command, eof, yes) | ++ IO_STATE(USB_EP_command, enable, yes) | ++ IO_FIELD(USB_EP_command, epid, INVALID_EPID)); ++ TxIntrEPList[i].sub = virt_to_phys(&TxIntrSB_zout); ++ TxIntrEPList[i].next = virt_to_phys(&TxIntrEPList[i + 1]); ++ } ++ ++ /* Special handling of last descr in list, make list circular */ ++ CHECK_ALIGN(&TxIntrEPList[i]); ++ TxIntrEPList[i].hw_len = 0; ++ TxIntrEPList[i].command = ++ (IO_STATE(USB_EP_command, eof, yes) | ++ IO_STATE(USB_EP_command, eol, yes) | ++ IO_STATE(USB_EP_command, enable, yes) | ++ IO_FIELD(USB_EP_command, epid, INVALID_EPID)); ++ TxIntrEPList[i].sub = virt_to_phys(&TxIntrSB_zout); ++ TxIntrEPList[i].next = virt_to_phys(&TxIntrEPList[0]); ++ ++ intr_dbg("Initiated Intr EP descriptor list\n"); ++ ++ ++ /* Connect DMA 8 sub-channel 2 to first in list */ ++ *R_DMA_CH8_SUB2_EP = virt_to_phys(&TxIntrEPList[0]); ++} ++ ++static void tc_dma_init_tx_isoc_list(void) { ++ int i; ++ ++ DBFENTER; ++ ++ /* Read comment at zout_buffer declaration for an explanation to this. */ ++ TxIsocSB_zout.sw_len = 1; ++ TxIsocSB_zout.next = 0; ++ TxIsocSB_zout.buf = virt_to_phys(&zout_buffer[0]); ++ TxIsocSB_zout.command = (IO_FIELD(USB_SB_command, rem, 0) | ++ IO_STATE(USB_SB_command, tt, zout) | ++ IO_STATE(USB_SB_command, full, yes) | ++ IO_STATE(USB_SB_command, eot, yes) | ++ IO_STATE(USB_SB_command, eol, yes)); ++ ++ /* The last isochronous EP descriptor is a dummy. */ ++ for (i = 0; i < (NBR_OF_EPIDS - 1); i++) { ++ CHECK_ALIGN(&TxIsocEPList[i]); ++ TxIsocEPList[i].hw_len = 0; ++ TxIsocEPList[i].command = IO_FIELD(USB_EP_command, epid, i); ++ TxIsocEPList[i].sub = 0; ++ TxIsocEPList[i].next = virt_to_phys(&TxIsocEPList[i + 1]); ++ } ++ ++ CHECK_ALIGN(&TxIsocEPList[i]); ++ TxIsocEPList[i].hw_len = 0; ++ ++ /* Must enable the last EP descr to get eof interrupt. */ ++ TxIsocEPList[i].command = (IO_STATE(USB_EP_command, enable, yes) | ++ IO_STATE(USB_EP_command, eof, yes) | ++ IO_STATE(USB_EP_command, eol, yes) | ++ IO_FIELD(USB_EP_command, epid, INVALID_EPID)); ++ TxIsocEPList[i].sub = virt_to_phys(&TxIsocSB_zout); ++ TxIsocEPList[i].next = virt_to_phys(&TxIsocEPList[0]); ++ ++ *R_DMA_CH8_SUB3_EP = virt_to_phys(&TxIsocEPList[0]); ++ *R_DMA_CH8_SUB3_CMD = IO_STATE(R_DMA_CH8_SUB3_CMD, cmd, start); ++} ++ ++static int tc_dma_init(struct usb_hcd *hcd) { ++ tc_dma_init_rx_list(); ++ tc_dma_init_tx_bulk_list(); ++ tc_dma_init_tx_ctrl_list(); ++ tc_dma_init_tx_intr_list(); ++ tc_dma_init_tx_isoc_list(); ++ ++ if (cris_request_dma(USB_TX_DMA_NBR, ++ "ETRAX 100LX built-in USB (Tx)", ++ DMA_VERBOSE_ON_ERROR, ++ dma_usb)) { ++ err("Could not allocate DMA ch 8 for USB"); ++ return -EBUSY; ++ } ++ ++ if (cris_request_dma(USB_RX_DMA_NBR, ++ "ETRAX 100LX built-in USB (Rx)", ++ DMA_VERBOSE_ON_ERROR, ++ dma_usb)) { ++ err("Could not allocate DMA ch 9 for USB"); ++ return -EBUSY; ++ } ++ ++ *R_IRQ_MASK2_SET = ++ /* Note that these interrupts are not used. */ ++ IO_STATE(R_IRQ_MASK2_SET, dma8_sub0_descr, set) | ++ /* Sub channel 1 (ctrl) descr. interrupts are used. */ ++ IO_STATE(R_IRQ_MASK2_SET, dma8_sub1_descr, set) | ++ IO_STATE(R_IRQ_MASK2_SET, dma8_sub2_descr, set) | ++ /* Sub channel 3 (isoc) descr. interrupts are used. */ ++ IO_STATE(R_IRQ_MASK2_SET, dma8_sub3_descr, set); ++ ++ /* Note that the dma9_descr interrupt is not used. */ ++ *R_IRQ_MASK2_SET = ++ IO_STATE(R_IRQ_MASK2_SET, dma9_eop, set) | ++ IO_STATE(R_IRQ_MASK2_SET, dma9_descr, set); ++ ++ if (request_irq(ETRAX_USB_RX_IRQ, tc_dma_rx_interrupt, 0, ++ "ETRAX 100LX built-in USB (Rx)", hcd)) { ++ err("Could not allocate IRQ %d for USB", ETRAX_USB_RX_IRQ); ++ return -EBUSY; ++ } ++ ++ if (request_irq(ETRAX_USB_TX_IRQ, tc_dma_tx_interrupt, 0, ++ "ETRAX 100LX built-in USB (Tx)", hcd)) { ++ err("Could not allocate IRQ %d for USB", ETRAX_USB_TX_IRQ); ++ return -EBUSY; ++ } ++ ++ return 0; ++} ++ ++static void tc_dma_destroy(void) { ++ free_irq(ETRAX_USB_RX_IRQ, NULL); ++ free_irq(ETRAX_USB_TX_IRQ, NULL); ++ ++ cris_free_dma(USB_TX_DMA_NBR, "ETRAX 100LX built-in USB (Tx)"); ++ cris_free_dma(USB_RX_DMA_NBR, "ETRAX 100LX built-in USB (Rx)"); ++ ++} ++ ++static void tc_dma_link_intr_urb(struct urb *urb); ++ ++/* Handle processing of Bulk, Ctrl and Intr queues */ ++static void tc_dma_process_queue(int epid) { ++ struct urb *urb; ++ struct crisv10_urb_priv *urb_priv = urb->hcpriv; ++ unsigned long flags; ++ char toggle; ++ ++ if(epid_state[epid].disabled) { ++ /* Don't process any URBs on a disabled endpoint */ ++ return; ++ } ++ ++ /* Do not disturb us while fiddling with EPs and epids */ ++ local_irq_save(flags); ++ ++ /* For bulk, Ctrl and Intr can we only have one URB active at a time for ++ a specific EP. */ ++ if(activeUrbList[epid] != NULL) { ++ /* An URB is already active on EP, skip checking queue */ ++ local_irq_restore(flags); ++ return; ++ } ++ ++ urb = urb_list_first(epid); ++ if(urb == NULL) { ++ /* No URB waiting in EP queue. Nothing do to */ ++ local_irq_restore(flags); ++ return; ++ } ++ ++ urb_priv = urb->hcpriv; ++ ASSERT(urb_priv != NULL); ++ ASSERT(urb_priv->urb_state == NOT_STARTED); ++ ASSERT(!usb_pipeisoc(urb->pipe)); ++ ++ /* Remove this URB from the queue and move it to active */ ++ activeUrbList[epid] = urb; ++ urb_list_del(urb, epid); ++ ++ urb_priv->urb_state = STARTED; ++ ++ /* Reset error counters (regardless of which direction this traffic is). */ ++ etrax_epid_clear_error(epid); ++ ++ /* Special handling of Intr EP lists */ ++ if(usb_pipeint(urb->pipe)) { ++ tc_dma_link_intr_urb(urb); ++ local_irq_restore(flags); ++ return; ++ } ++ ++ /* Software must preset the toggle bits for Bulk and Ctrl */ ++ if(usb_pipecontrol(urb->pipe)) { ++ /* Toggle bits are initialized only during setup transaction in a ++ CTRL transfer */ ++ etrax_epid_set_toggle(epid, 0, 0); ++ etrax_epid_set_toggle(epid, 1, 0); ++ } else { ++ toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), ++ usb_pipeout(urb->pipe)); ++ etrax_epid_set_toggle(epid, usb_pipeout(urb->pipe), toggle); ++ } ++ ++ tc_dbg("Added SBs from (URB:0x%x %s %s) to epid %d: %s\n", ++ (unsigned int)urb, str_dir(urb->pipe), str_type(urb->pipe), epid, ++ sblist_to_str(urb_priv->first_sb)); ++ ++ /* We start the DMA sub channel without checking if it's running or not, ++ because: ++ 1) If it's already running, issuing the start command is a nop. ++ 2) We avoid a test-and-set race condition. */ ++ switch(usb_pipetype(urb->pipe)) { ++ case PIPE_BULK: ++ /* Assert that the EP descriptor is disabled. */ ++ ASSERT(!(TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable))); ++ ++ /* Set up and enable the EP descriptor. */ ++ TxBulkEPList[epid].sub = virt_to_phys(urb_priv->first_sb); ++ TxBulkEPList[epid].hw_len = 0; ++ TxBulkEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); ++ ++ /* Check if the dummy list is already with us (if several urbs were queued). */ ++ if (usb_pipein(urb->pipe) && (TxBulkEPList[epid].next != virt_to_phys(&TxBulkDummyEPList[epid][0]))) { ++ tc_dbg("Inviting dummy list to the party for urb 0x%lx, epid %d", ++ (unsigned long)urb, epid); ++ ++ /* We don't need to check if the DMA is at this EP or not before changing the ++ next pointer, since we will do it in one 32-bit write (EP descriptors are ++ 32-bit aligned). */ ++ TxBulkEPList[epid].next = virt_to_phys(&TxBulkDummyEPList[epid][0]); ++ } ++ ++ restart_dma8_sub0(); ++ ++ /* Update/restart the bulk start timer since we just started the channel.*/ ++ mod_timer(&bulk_start_timer, jiffies + BULK_START_TIMER_INTERVAL); ++ /* Update/restart the bulk eot timer since we just inserted traffic. */ ++ mod_timer(&bulk_eot_timer, jiffies + BULK_EOT_TIMER_INTERVAL); ++ break; ++ case PIPE_CONTROL: ++ /* Assert that the EP descriptor is disabled. */ ++ ASSERT(!(TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable))); ++ ++ /* Set up and enable the EP descriptor. */ ++ TxCtrlEPList[epid].sub = virt_to_phys(urb_priv->first_sb); ++ TxCtrlEPList[epid].hw_len = 0; ++ TxCtrlEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); ++ ++ *R_DMA_CH8_SUB1_CMD = IO_STATE(R_DMA_CH8_SUB1_CMD, cmd, start); ++ break; ++ } ++ local_irq_restore(flags); ++} ++ ++static void tc_dma_link_intr_urb(struct urb *urb) { ++ struct crisv10_urb_priv *urb_priv = urb->hcpriv; ++ volatile struct USB_EP_Desc *tmp_ep; ++ struct USB_EP_Desc *ep_desc; ++ int i = 0, epid; ++ int pool_idx = 0; ++ ++ ASSERT(urb_priv != NULL); ++ epid = urb_priv->epid; ++ ASSERT(urb_priv->interval > 0); ++ ASSERT(urb_priv->intr_ep_pool_length > 0); ++ ++ tmp_ep = &TxIntrEPList[0]; ++ ++ /* Only insert one EP descriptor in list for Out Intr URBs. ++ We can only handle Out Intr with interval of 128ms because ++ it's not possible to insert several Out Intr EPs because they ++ are not consumed by the DMA. */ ++ if(usb_pipeout(urb->pipe)) { ++ ep_desc = urb_priv->intr_ep_pool[0]; ++ ASSERT(ep_desc); ++ ep_desc->next = tmp_ep->next; ++ tmp_ep->next = virt_to_phys(ep_desc); ++ i++; ++ } else { ++ /* Loop through Intr EP descriptor list and insert EP for URB at ++ specified interval */ ++ do { ++ /* Each EP descriptor with eof flag sat signals a new frame */ ++ if (tmp_ep->command & IO_MASK(USB_EP_command, eof)) { ++ /* Insert a EP from URBs EP pool at correct interval */ ++ if ((i % urb_priv->interval) == 0) { ++ ep_desc = urb_priv->intr_ep_pool[pool_idx]; ++ ASSERT(ep_desc); ++ ep_desc->next = tmp_ep->next; ++ tmp_ep->next = virt_to_phys(ep_desc); ++ pool_idx++; ++ ASSERT(pool_idx <= urb_priv->intr_ep_pool_length); ++ } ++ i++; ++ } ++ tmp_ep = (struct USB_EP_Desc *)phys_to_virt(tmp_ep->next); ++ } while(tmp_ep != &TxIntrEPList[0]); ++ } ++ ++ intr_dbg("Added SBs to intr epid %d: %s interval:%d (%d EP)\n", epid, ++ sblist_to_str(urb_priv->first_sb), urb_priv->interval, pool_idx); ++ ++ /* We start the DMA sub channel without checking if it's running or not, ++ because: ++ 1) If it's already running, issuing the start command is a nop. ++ 2) We avoid a test-and-set race condition. */ ++ *R_DMA_CH8_SUB2_CMD = IO_STATE(R_DMA_CH8_SUB2_CMD, cmd, start); ++} ++ ++ /* hinko ignore usb_pipeisoc */ ++#if 0 ++static void tc_dma_process_isoc_urb(struct urb *urb) { ++ unsigned long flags; ++ struct crisv10_urb_priv *urb_priv = urb->hcpriv; ++ int epid; ++ ++ /* Do not disturb us while fiddling with EPs and epids */ ++ local_irq_save(flags); ++ ++ ASSERT(urb_priv); ++ ASSERT(urb_priv->first_sb); ++ epid = urb_priv->epid; ++ ++ if(activeUrbList[epid] == NULL) { ++ /* EP is idle, so make this URB active */ ++ activeUrbList[epid] = urb; ++ urb_list_del(urb, epid); ++ ASSERT(TxIsocEPList[epid].sub == 0); ++ ASSERT(!(TxIsocEPList[epid].command & ++ IO_STATE(USB_EP_command, enable, yes))); ++ ++ /* Differentiate between In and Out Isoc. Because In SBs are not consumed*/ ++ if(usb_pipein(urb->pipe)) { ++ /* Each EP for In Isoc will have only one SB descriptor, setup when ++ submitting the first active urb. We do it here by copying from URBs ++ pre-allocated SB. */ ++ memcpy((void *)&(TxIsocSBList[epid]), urb_priv->first_sb, ++ sizeof(TxIsocSBList[epid])); ++ TxIsocEPList[epid].hw_len = 0; ++ TxIsocEPList[epid].sub = virt_to_phys(&(TxIsocSBList[epid])); ++ } else { ++ /* For Out Isoc we attach the pre-allocated list of SBs for the URB */ ++ TxIsocEPList[epid].hw_len = 0; ++ TxIsocEPList[epid].sub = virt_to_phys(urb_priv->first_sb); ++ ++ isoc_dbg("Attached first URB:0x%x[%d] to epid:%d first_sb:0x%x" ++ " last_sb::0x%x\n", ++ (unsigned int)urb, urb_priv->urb_num, epid, ++ (unsigned int)(urb_priv->first_sb), ++ (unsigned int)(urb_priv->last_sb)); ++ } ++ ++ if (urb->transfer_flags & URB_ISO_ASAP) { ++ /* The isoc transfer should be started as soon as possible. The ++ start_frame field is a return value if URB_ISO_ASAP was set. Comparing ++ R_USB_FM_NUMBER with a USB Chief trace shows that the first isoc IN ++ token is sent 2 frames later. I'm not sure how this affects usage of ++ the start_frame field by the device driver, or how it affects things ++ when USB_ISO_ASAP is not set, so therefore there's no compensation for ++ the 2 frame "lag" here. */ ++ urb->start_frame = (*R_USB_FM_NUMBER & 0x7ff); ++ TxIsocEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); ++ urb_priv->urb_state = STARTED; ++ isoc_dbg("URB_ISO_ASAP set, urb->start_frame set to %d\n", ++ urb->start_frame); ++ } else { ++ /* Not started yet. */ ++ urb_priv->urb_state = NOT_STARTED; ++ isoc_warn("urb_priv->urb_state set to NOT_STARTED for URB:0x%x\n", ++ (unsigned int)urb); ++ } ++ ++ } else { ++ /* An URB is already active on the EP. Leave URB in queue and let ++ finish_isoc_urb process it after current active URB */ ++ ASSERT(TxIsocEPList[epid].sub != 0); ++ ++ if(usb_pipein(urb->pipe)) { ++ /* Because there already is a active In URB on this epid we do nothing ++ and the finish_isoc_urb() function will handle switching to next URB*/ ++ ++ } else { /* For Out Isoc, insert new URBs traffic last in SB-list. */ ++ struct USB_SB_Desc *temp_sb_desc; ++ ++ /* Set state STARTED to all Out Isoc URBs added to SB list because we ++ don't know how many of them that are finished before descr interrupt*/ ++ urb_priv->urb_state = STARTED; ++ ++ /* Find end of current SB list by looking for SB with eol flag sat */ ++ temp_sb_desc = phys_to_virt(TxIsocEPList[epid].sub); ++ while ((temp_sb_desc->command & IO_MASK(USB_SB_command, eol)) != ++ IO_STATE(USB_SB_command, eol, yes)) { ++ ASSERT(temp_sb_desc->next); ++ temp_sb_desc = phys_to_virt(temp_sb_desc->next); ++ } ++ ++ isoc_dbg("Appended URB:0x%x[%d] (first:0x%x last:0x%x) to epid:%d" ++ " sub:0x%x eol:0x%x\n", ++ (unsigned int)urb, urb_priv->urb_num, ++ (unsigned int)(urb_priv->first_sb), ++ (unsigned int)(urb_priv->last_sb), epid, ++ (unsigned int)phys_to_virt(TxIsocEPList[epid].sub), ++ (unsigned int)temp_sb_desc); ++ ++ /* Next pointer must be set before eol is removed. */ ++ temp_sb_desc->next = virt_to_phys(urb_priv->first_sb); ++ /* Clear the previous end of list flag since there is a new in the ++ added SB descriptor list. */ ++ temp_sb_desc->command &= ~IO_MASK(USB_SB_command, eol); ++ ++ if (!(TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable))) { ++ __u32 epid_data; ++ /* 8.8.5 in Designer's Reference says we should check for and correct ++ any errors in the EP here. That should not be necessary if ++ epid_attn is handled correctly, so we assume all is ok. */ ++ epid_data = etrax_epid_iso_get(epid); ++ if (IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data) != ++ IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { ++ isoc_err("Disabled Isoc EP with error:%d on epid:%d when appending" ++ " URB:0x%x[%d]\n", ++ IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data), epid, ++ (unsigned int)urb, urb_priv->urb_num); ++ } ++ ++ /* The SB list was exhausted. */ ++ if (virt_to_phys(urb_priv->last_sb) != TxIsocEPList[epid].sub) { ++ /* The new sublist did not get processed before the EP was ++ disabled. Setup the EP again. */ ++ ++ if(virt_to_phys(temp_sb_desc) == TxIsocEPList[epid].sub) { ++ isoc_dbg("EP for epid:%d stoped at SB:0x%x before newly inserted" ++ ", restarting from this URBs SB:0x%x\n", ++ epid, (unsigned int)temp_sb_desc, ++ (unsigned int)(urb_priv->first_sb)); ++ TxIsocEPList[epid].hw_len = 0; ++ TxIsocEPList[epid].sub = virt_to_phys(urb_priv->first_sb); ++ urb->start_frame = (*R_USB_FM_NUMBER & 0x7ff); ++ /* Enable the EP again so data gets processed this time */ ++ TxIsocEPList[epid].command |= ++ IO_STATE(USB_EP_command, enable, yes); ++ ++ } else { ++ /* The EP has been disabled but not at end this URB (god knows ++ where). This should generate an epid_attn so we should not be ++ here */ ++ isoc_warn("EP was disabled on sb:0x%x before SB list for" ++ " URB:0x%x[%d] got processed\n", ++ (unsigned int)phys_to_virt(TxIsocEPList[epid].sub), ++ (unsigned int)urb, urb_priv->urb_num); ++ } ++ } else { ++ /* This might happend if we are slow on this function and isn't ++ an error. */ ++ isoc_dbg("EP was disabled and finished with SBs from appended" ++ " URB:0x%x[%d]\n", (unsigned int)urb, urb_priv->urb_num); ++ } ++ } ++ } ++ } ++ ++ /* Start the DMA sub channel */ ++ *R_DMA_CH8_SUB3_CMD = IO_STATE(R_DMA_CH8_SUB3_CMD, cmd, start); ++ ++ local_irq_restore(flags); ++} ++#endif ++ ++static void tc_dma_unlink_intr_urb(struct urb *urb) { ++ struct crisv10_urb_priv *urb_priv = urb->hcpriv; ++ volatile struct USB_EP_Desc *first_ep; /* First EP in the list. */ ++ volatile struct USB_EP_Desc *curr_ep; /* Current EP, the iterator. */ ++ volatile struct USB_EP_Desc *next_ep; /* The EP after current. */ ++ volatile struct USB_EP_Desc *unlink_ep; /* The one we should remove from ++ the list. */ ++ int count = 0; ++ volatile int timeout = 10000; ++ int epid; ++ ++ /* Read 8.8.4 in Designer's Reference, "Removing an EP Descriptor from the ++ List". */ ++ ASSERT(urb_priv); ++ ASSERT(urb_priv->intr_ep_pool_length > 0); ++ epid = urb_priv->epid; ++ ++ /* First disable all Intr EPs belonging to epid for this URB */ ++ first_ep = &TxIntrEPList[0]; ++ curr_ep = first_ep; ++ do { ++ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); ++ if (IO_EXTRACT(USB_EP_command, epid, next_ep->command) == epid) { ++ /* Disable EP */ ++ next_ep->command &= ~IO_MASK(USB_EP_command, enable); ++ } ++ curr_ep = phys_to_virt(curr_ep->next); ++ } while (curr_ep != first_ep); ++ ++ ++ /* Now unlink all EPs belonging to this epid from Descr list */ ++ first_ep = &TxIntrEPList[0]; ++ curr_ep = first_ep; ++ do { ++ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); ++ if (IO_EXTRACT(USB_EP_command, epid, next_ep->command) == epid) { ++ /* This is the one we should unlink. */ ++ unlink_ep = next_ep; ++ ++ /* Actually unlink the EP from the DMA list. */ ++ curr_ep->next = unlink_ep->next; ++ ++ /* Wait until the DMA is no longer at this descriptor. */ ++ while((*R_DMA_CH8_SUB2_EP == virt_to_phys(unlink_ep)) && ++ (timeout-- > 0)); ++ if(timeout == 0) { ++ warn("Timeout while waiting for DMA-TX-Intr to leave unlink EP\n"); ++ } ++ ++ count++; ++ } ++ curr_ep = phys_to_virt(curr_ep->next); ++ } while (curr_ep != first_ep); ++ ++ if(count != urb_priv->intr_ep_pool_length) { ++ intr_warn("Unlinked %d of %d Intr EPs for URB:0x%x[%d]\n", count, ++ urb_priv->intr_ep_pool_length, (unsigned int)urb, ++ urb_priv->urb_num); ++ } else { ++ intr_dbg("Unlinked %d of %d interrupt EPs for URB:0x%x\n", count, ++ urb_priv->intr_ep_pool_length, (unsigned int)urb); ++ } ++} ++ ++static void check_finished_bulk_tx_epids(struct usb_hcd *hcd, ++ int timer) { ++ unsigned long flags; ++ int epid; ++ struct urb *urb; ++ struct crisv10_urb_priv * urb_priv; ++ __u32 epid_data; ++ ++ /* Protect TxEPList */ ++ local_irq_save(flags); ++ ++ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { ++ /* A finished EP descriptor is disabled and has a valid sub pointer */ ++ if (!(TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) && ++ (TxBulkEPList[epid].sub != 0)) { ++ ++ /* Get the active URB for this epid */ ++ urb = activeUrbList[epid]; ++ /* Sanity checks */ ++ ASSERT(urb); ++ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; ++ ASSERT(urb_priv); ++ ++ /* Only handle finished out Bulk EPs here, ++ and let RX interrupt take care of the rest */ ++ if(!epid_out_traffic(epid)) { ++ continue; ++ } ++ ++ if(timer) { ++ tc_warn("Found finished %s Bulk epid:%d URB:0x%x[%d] from timeout\n", ++ epid_out_traffic(epid) ? "Out" : "In", epid, (unsigned int)urb, ++ urb_priv->urb_num); ++ } else { ++ tc_dbg("Found finished %s Bulk epid:%d URB:0x%x[%d] from interrupt\n", ++ epid_out_traffic(epid) ? "Out" : "In", epid, (unsigned int)urb, ++ urb_priv->urb_num); ++ } ++ ++ if(urb_priv->urb_state == UNLINK) { ++ /* This Bulk URB is requested to be unlinked, that means that the EP ++ has been disabled and we might not have sent all data */ ++ tc_finish_urb(hcd, urb, urb->status); ++ continue; ++ } ++ ++ ASSERT(urb_priv->urb_state == STARTED); ++ if (phys_to_virt(TxBulkEPList[epid].sub) != urb_priv->last_sb) { ++ tc_err("Endpoint got disabled before reaching last sb\n"); ++ } ++ ++ epid_data = etrax_epid_get(epid); ++ if (IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data) == ++ IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { ++ /* This means that the endpoint has no error, is disabled ++ and had inserted traffic, i.e. transfer successfully completed. */ ++ tc_finish_urb(hcd, urb, 0); ++ } else { ++ /* Shouldn't happen. We expect errors to be caught by epid ++ attention. */ ++ tc_err("Found disabled bulk EP desc (epid:%d error:%d)\n", ++ epid, IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data)); ++ } ++ } else { ++ tc_dbg("Ignoring In Bulk epid:%d, let RX interrupt handle it\n", epid); ++ } ++ } ++ ++ local_irq_restore(flags); ++} ++ ++static void check_finished_ctrl_tx_epids(struct usb_hcd *hcd) { ++ unsigned long flags; ++ int epid; ++ struct urb *urb; ++ struct crisv10_urb_priv * urb_priv; ++ __u32 epid_data; ++ ++ /* Protect TxEPList */ ++ local_irq_save(flags); ++ ++ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { ++ if(epid == DUMMY_EPID) ++ continue; ++ ++ /* A finished EP descriptor is disabled and has a valid sub pointer */ ++ if (!(TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) && ++ (TxCtrlEPList[epid].sub != 0)) { ++ ++ /* Get the active URB for this epid */ ++ urb = activeUrbList[epid]; ++ ++ if(urb == NULL) { ++ tc_warn("Found finished Ctrl epid:%d with no active URB\n", epid); ++ continue; ++ } ++ ++ /* Sanity checks */ ++ ASSERT(usb_pipein(urb->pipe)); ++ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; ++ ASSERT(urb_priv); ++ if (phys_to_virt(TxCtrlEPList[epid].sub) != urb_priv->last_sb) { ++ tc_err("Endpoint got disabled before reaching last sb\n"); ++ } ++ ++ epid_data = etrax_epid_get(epid); ++ if (IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data) == ++ IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { ++ /* This means that the endpoint has no error, is disabled ++ and had inserted traffic, i.e. transfer successfully completed. */ ++ ++ /* Check if RX-interrupt for In Ctrl has been processed before ++ finishing the URB */ ++ if(urb_priv->ctrl_rx_done) { ++ tc_dbg("Finishing In Ctrl URB:0x%x[%d] in tx_interrupt\n", ++ (unsigned int)urb, urb_priv->urb_num); ++ tc_finish_urb(hcd, urb, 0); ++ } else { ++ /* If we get zout descriptor interrupt before RX was done for a ++ In Ctrl transfer, then we flag that and it will be finished ++ in the RX-Interrupt */ ++ urb_priv->ctrl_zout_done = 1; ++ tc_dbg("Got zout descr interrupt before RX interrupt\n"); ++ } ++ } else { ++ /* Shouldn't happen. We expect errors to be caught by epid ++ attention. */ ++ tc_err("Found disabled Ctrl EP desc (epid:%d URB:0x%x[%d]) error_code:%d\n", epid, (unsigned int)urb, urb_priv->urb_num, IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data)); ++ __dump_ep_desc(&(TxCtrlEPList[epid])); ++ __dump_ept_data(epid); ++ } ++ } ++ } ++ local_irq_restore(flags); ++} ++ ++ /* hinko ignore usb_pipeisoc */ ++#if 0 ++/* This function goes through all epids that are setup for Out Isoc transfers ++ and marks (isoc_out_done) all queued URBs that the DMA has finished ++ transfer for. ++ No URB completetion is done here to make interrupt routine return quickly. ++ URBs are completed later with help of complete_isoc_bottom_half() that ++ becomes schedules when this functions is finished. */ ++static void check_finished_isoc_tx_epids(void) { ++ unsigned long flags; ++ int epid; ++ struct urb *urb; ++ struct crisv10_urb_priv * urb_priv; ++ struct USB_SB_Desc* sb_desc; ++ int epid_done; ++ ++ /* Protect TxIsocEPList */ ++ local_irq_save(flags); ++ ++ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { ++ if (TxIsocEPList[epid].sub == 0 || epid == INVALID_EPID || ++ !epid_out_traffic(epid)) { ++ /* Nothing here to see. */ ++ continue; ++ } ++ ASSERT(epid_inuse(epid)); ++ ASSERT(epid_isoc(epid)); ++ ++ sb_desc = phys_to_virt(TxIsocEPList[epid].sub); ++ /* Find the last descriptor of the currently active URB for this ep. ++ This is the first descriptor in the sub list marked for a descriptor ++ interrupt. */ ++ while (sb_desc && !IO_EXTRACT(USB_SB_command, intr, sb_desc->command)) { ++ sb_desc = sb_desc->next ? phys_to_virt(sb_desc->next) : 0; ++ } ++ ASSERT(sb_desc); ++ ++ isoc_dbg("Descr IRQ checking epid:%d sub:0x%x intr:0x%x\n", ++ epid, (unsigned int)phys_to_virt(TxIsocEPList[epid].sub), ++ (unsigned int)sb_desc); ++ ++ urb = activeUrbList[epid]; ++ if(urb == NULL) { ++ isoc_err("Isoc Descr irq on epid:%d with no active URB\n", epid); ++ continue; ++ } ++ ++ epid_done = 0; ++ while(urb && !epid_done) { ++ /* Sanity check. */ ++ ASSERT(usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS); ++ ASSERT(usb_pipeout(urb->pipe)); ++ ++ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; ++ ASSERT(urb_priv); ++ ASSERT(urb_priv->urb_state == STARTED || ++ urb_priv->urb_state == UNLINK); ++ ++ if (sb_desc != urb_priv->last_sb) { ++ /* This urb has been sent. */ ++ urb_priv->isoc_out_done = 1; ++ ++ } else { /* Found URB that has last_sb as the interrupt reason */ ++ ++ /* Check if EP has been disabled, meaning that all transfers are done*/ ++ if(!(TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable))) { ++ ASSERT((sb_desc->command & IO_MASK(USB_SB_command, eol)) == ++ IO_STATE(USB_SB_command, eol, yes)); ++ ASSERT(sb_desc->next == 0); ++ urb_priv->isoc_out_done = 1; ++ } else { ++ isoc_dbg("Skipping URB:0x%x[%d] because EP not disabled yet\n", ++ (unsigned int)urb, urb_priv->urb_num); ++ } ++ /* Stop looking any further in queue */ ++ epid_done = 1; ++ } ++ ++ if (!epid_done) { ++ if(urb == activeUrbList[epid]) { ++ urb = urb_list_first(epid); ++ } else { ++ urb = urb_list_next(urb, epid); ++ } ++ } ++ } /* END: while(urb && !epid_done) */ ++ } ++ ++ local_irq_restore(flags); ++} ++ ++ ++/* This is where the Out Isoc URBs are realy completed. This function is ++ scheduled from tc_dma_tx_interrupt() when one or more Out Isoc transfers ++ are done. This functions completes all URBs earlier marked with ++ isoc_out_done by fast interrupt routine check_finished_isoc_tx_epids() */ ++ ++static void complete_isoc_bottom_half(void *data) { ++ struct crisv10_isoc_complete_data *comp_data; ++ struct usb_iso_packet_descriptor *packet; ++ struct crisv10_urb_priv * urb_priv; ++ unsigned long flags; ++ struct urb* urb; ++ int epid_done; ++ int epid; ++ int i; ++ ++ comp_data = (struct crisv10_isoc_complete_data*)data; ++ ++ local_irq_save(flags); ++ ++ for (epid = 0; epid < NBR_OF_EPIDS - 1; epid++) { ++ if(!epid_inuse(epid) || !epid_isoc(epid) || !epid_out_traffic(epid) || epid == DUMMY_EPID) { ++ /* Only check valid Out Isoc epids */ ++ continue; ++ } ++ ++ isoc_dbg("Isoc bottom-half checking epid:%d, sub:0x%x\n", epid, ++ (unsigned int)phys_to_virt(TxIsocEPList[epid].sub)); ++ ++ /* The descriptor interrupt handler has marked all transmitted Out Isoc ++ URBs with isoc_out_done. Now we traverse all epids and for all that ++ have out Isoc traffic we traverse its URB list and complete the ++ transmitted URBs. */ ++ epid_done = 0; ++ while (!epid_done) { ++ ++ /* Get the active urb (if any) */ ++ urb = activeUrbList[epid]; ++ if (urb == 0) { ++ isoc_dbg("No active URB on epid:%d anymore\n", epid); ++ epid_done = 1; ++ continue; ++ } ++ ++ /* Sanity check. */ ++ ASSERT(usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS); ++ ASSERT(usb_pipeout(urb->pipe)); ++ ++ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; ++ ASSERT(urb_priv); ++ ++ if (!(urb_priv->isoc_out_done)) { ++ /* We have reached URB that isn't flaged done yet, stop traversing. */ ++ isoc_dbg("Stoped traversing Out Isoc URBs on epid:%d" ++ " before not yet flaged URB:0x%x[%d]\n", ++ epid, (unsigned int)urb, urb_priv->urb_num); ++ epid_done = 1; ++ continue; ++ } ++ ++ /* This urb has been sent. */ ++ isoc_dbg("Found URB:0x%x[%d] that is flaged isoc_out_done\n", ++ (unsigned int)urb, urb_priv->urb_num); ++ ++ /* Set ok on transfered packets for this URB and finish it */ ++ for (i = 0; i < urb->number_of_packets; i++) { ++ packet = &urb->iso_frame_desc[i]; ++ packet->status = 0; ++ packet->actual_length = packet->length; ++ } ++ urb_priv->isoc_packet_counter = urb->number_of_packets; ++ tc_finish_urb(comp_data->hcd, urb, 0); ++ ++ } /* END: while(!epid_done) */ ++ } /* END: for(epid...) */ ++ ++ local_irq_restore(flags); ++ kmem_cache_free(isoc_compl_cache, comp_data); ++} ++#endif ++ ++static void check_finished_intr_tx_epids(struct usb_hcd *hcd) { ++ unsigned long flags; ++ int epid; ++ struct urb *urb; ++ struct crisv10_urb_priv * urb_priv; ++ volatile struct USB_EP_Desc *curr_ep; /* Current EP, the iterator. */ ++ volatile struct USB_EP_Desc *next_ep; /* The EP after current. */ ++ ++ /* Protect TxintrEPList */ ++ local_irq_save(flags); ++ ++ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { ++ if(!epid_inuse(epid) || !epid_intr(epid) || !epid_out_traffic(epid)) { ++ /* Nothing to see on this epid. Only check valid Out Intr epids */ ++ continue; ++ } ++ ++ urb = activeUrbList[epid]; ++ if(urb == 0) { ++ intr_warn("Found Out Intr epid:%d with no active URB\n", epid); ++ continue; ++ } ++ ++ /* Sanity check. */ ++ ASSERT(usb_pipetype(urb->pipe) == PIPE_INTERRUPT); ++ ASSERT(usb_pipeout(urb->pipe)); ++ ++ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; ++ ASSERT(urb_priv); ++ ++ /* Go through EPs between first and second sof-EP. It's here Out Intr EPs ++ are inserted.*/ ++ curr_ep = &TxIntrEPList[0]; ++ do { ++ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); ++ if(next_ep == urb_priv->intr_ep_pool[0]) { ++ /* We found the Out Intr EP for this epid */ ++ ++ /* Disable it so it doesn't get processed again */ ++ next_ep->command &= ~IO_MASK(USB_EP_command, enable); ++ ++ /* Finish the active Out Intr URB with status OK */ ++ tc_finish_urb(hcd, urb, 0); ++ } ++ curr_ep = phys_to_virt(curr_ep->next); ++ } while (curr_ep != &TxIntrEPList[1]); ++ ++ } ++ local_irq_restore(flags); ++} ++ ++/* Interrupt handler for DMA8/IRQ24 with subchannels (called from hardware intr) */ ++static irqreturn_t tc_dma_tx_interrupt(int irq, void *vhc) { ++ struct usb_hcd *hcd = (struct usb_hcd*)vhc; ++ ASSERT(hcd); ++ ++ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub0_descr)) { ++ /* Clear this interrupt */ ++ *R_DMA_CH8_SUB0_CLR_INTR = IO_STATE(R_DMA_CH8_SUB0_CLR_INTR, clr_descr, do); ++ restart_dma8_sub0(); ++ } ++ ++ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub1_descr)) { ++ /* Clear this interrupt */ ++ *R_DMA_CH8_SUB1_CLR_INTR = IO_STATE(R_DMA_CH8_SUB1_CLR_INTR, clr_descr, do); ++ check_finished_ctrl_tx_epids(hcd); ++ } ++ ++ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub2_descr)) { ++ /* Clear this interrupt */ ++ *R_DMA_CH8_SUB2_CLR_INTR = IO_STATE(R_DMA_CH8_SUB2_CLR_INTR, clr_descr, do); ++ check_finished_intr_tx_epids(hcd); ++ } ++ ++ /* hinko ignore usb_pipeisoc */ ++#if 0 ++ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub3_descr)) { ++ struct crisv10_isoc_complete_data* comp_data; ++ ++ /* Flag done Out Isoc for later completion */ ++ check_finished_isoc_tx_epids(); ++ ++ /* Clear this interrupt */ ++ *R_DMA_CH8_SUB3_CLR_INTR = IO_STATE(R_DMA_CH8_SUB3_CLR_INTR, clr_descr, do); ++ /* Schedule bottom half of Out Isoc completion function. This function ++ finishes the URBs marked with isoc_out_done */ ++ comp_data = (struct crisv10_isoc_complete_data*) ++ kmem_cache_alloc(isoc_compl_cache, GFP_ATOMIC); ++ ASSERT(comp_data != NULL); ++ comp_data ->hcd = hcd; ++ ++ //INIT_WORK(&comp_data->usb_bh, complete_isoc_bottom_half, comp_data); ++ INIT_WORK(&comp_data->usb_bh, complete_isoc_bottom_half); ++ schedule_work(&comp_data->usb_bh); ++ } ++#endif ++ ++ return IRQ_HANDLED; ++} ++ ++/* Interrupt handler for DMA9/IRQ25 (called from hardware intr) */ ++static irqreturn_t tc_dma_rx_interrupt(int irq, void *vhc) { ++ unsigned long flags; ++ struct urb *urb; ++ struct usb_hcd *hcd = (struct usb_hcd*)vhc; ++ struct crisv10_urb_priv *urb_priv; ++ int epid = 0; ++ int real_error; ++ ++ ASSERT(hcd); ++ ++ /* Clear this interrupt. */ ++ *R_DMA_CH9_CLR_INTR = IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop, do); ++ ++ /* Custom clear interrupt for this interrupt */ ++ /* The reason we cli here is that we call the driver's callback functions. */ ++ local_irq_save(flags); ++ ++ /* Note that this while loop assumes that all packets span only ++ one rx descriptor. */ ++ while(myNextRxDesc->status & IO_MASK(USB_IN_status, eop)) { ++ epid = IO_EXTRACT(USB_IN_status, epid, myNextRxDesc->status); ++ /* Get the active URB for this epid */ ++ urb = activeUrbList[epid]; ++ ++ ASSERT(epid_inuse(epid)); ++ if (!urb) { ++ dma_err("No urb for epid %d in rx interrupt\n", epid); ++ goto skip_out; ++ } ++ ++ /* Check if any errors on epid */ ++ real_error = 0; ++ if (myNextRxDesc->status & IO_MASK(USB_IN_status, error)) { ++ __u32 r_usb_ept_data; ++ ++ if (usb_pipeisoc(urb->pipe)) { ++ r_usb_ept_data = etrax_epid_iso_get(epid); ++ if((r_usb_ept_data & IO_MASK(R_USB_EPT_DATA_ISO, valid)) && ++ (IO_EXTRACT(R_USB_EPT_DATA_ISO, error_code, r_usb_ept_data) == 0) && ++ (myNextRxDesc->status & IO_MASK(USB_IN_status, nodata))) { ++ /* Not an error, just a failure to receive an expected iso ++ in packet in this frame. This is not documented ++ in the designers reference. Continue processing. ++ */ ++ } else real_error = 1; ++ } else real_error = 1; ++ } ++ ++ if(real_error) { ++ dma_err("Error in RX descr on epid:%d for URB 0x%x", ++ epid, (unsigned int)urb); ++ dump_ept_data(epid); ++ dump_in_desc(myNextRxDesc); ++ goto skip_out; ++ } ++ ++ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; ++ ASSERT(urb_priv); ++ ASSERT(urb_priv->urb_state == STARTED || ++ urb_priv->urb_state == UNLINK); ++ ++ if ((usb_pipetype(urb->pipe) == PIPE_BULK) || ++ (usb_pipetype(urb->pipe) == PIPE_CONTROL) || ++ (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) { ++ ++ /* We get nodata for empty data transactions, and the rx descriptor's ++ hw_len field is not valid in that case. No data to copy in other ++ words. */ ++ if (myNextRxDesc->status & IO_MASK(USB_IN_status, nodata)) { ++ /* No data to copy */ ++ } else { ++ /* ++ dma_dbg("Processing RX for URB:0x%x epid:%d (data:%d ofs:%d)\n", ++ (unsigned int)urb, epid, myNextRxDesc->hw_len, ++ urb_priv->rx_offset); ++ */ ++ /* Only copy data if URB isn't flaged to be unlinked*/ ++ if(urb_priv->urb_state != UNLINK) { ++ /* Make sure the data fits in the buffer. */ ++ if(urb_priv->rx_offset + myNextRxDesc->hw_len ++ <= urb->transfer_buffer_length) { ++ ++ /* Copy the data to URBs buffer */ ++ memcpy(urb->transfer_buffer + urb_priv->rx_offset, ++ phys_to_virt(myNextRxDesc->buf), myNextRxDesc->hw_len); ++ urb_priv->rx_offset += myNextRxDesc->hw_len; ++ } else { ++ /* Signal overflow when returning URB */ ++ urb->status = -EOVERFLOW; ++ tc_finish_urb_later(hcd, urb, urb->status); ++ } ++ } ++ } ++ ++ /* Check if it was the last packet in the transfer */ ++ if (myNextRxDesc->status & IO_MASK(USB_IN_status, eot)) { ++ /* Special handling for In Ctrl URBs. */ ++ if(usb_pipecontrol(urb->pipe) && usb_pipein(urb->pipe) && ++ !(urb_priv->ctrl_zout_done)) { ++ /* Flag that RX part of Ctrl transfer is done. Because zout descr ++ interrupt hasn't happend yet will the URB be finished in the ++ TX-Interrupt. */ ++ urb_priv->ctrl_rx_done = 1; ++ tc_dbg("Not finishing In Ctrl URB:0x%x from rx_interrupt, waiting" ++ " for zout\n", (unsigned int)urb); ++ } else { ++ tc_finish_urb(hcd, urb, 0); ++ } ++ } ++ } else { /* ISOC RX */ ++ /* ++ isoc_dbg("Processing RX for epid:%d (URB:0x%x) ISOC pipe\n", ++ epid, (unsigned int)urb); ++ */ ++ ++ struct usb_iso_packet_descriptor *packet; ++ ++ if (urb_priv->urb_state == UNLINK) { ++ isoc_warn("Ignoring Isoc Rx data for urb being unlinked.\n"); ++ goto skip_out; ++ } else if (urb_priv->urb_state == NOT_STARTED) { ++ isoc_err("What? Got Rx data for Isoc urb that isn't started?\n"); ++ goto skip_out; ++ } ++ ++ packet = &urb->iso_frame_desc[urb_priv->isoc_packet_counter]; ++ ASSERT(packet); ++ packet->status = 0; ++ ++ if (myNextRxDesc->status & IO_MASK(USB_IN_status, nodata)) { ++ /* We get nodata for empty data transactions, and the rx descriptor's ++ hw_len field is not valid in that case. We copy 0 bytes however to ++ stay in synch. */ ++ packet->actual_length = 0; ++ } else { ++ packet->actual_length = myNextRxDesc->hw_len; ++ /* Make sure the data fits in the buffer. */ ++ ASSERT(packet->actual_length <= packet->length); ++ memcpy(urb->transfer_buffer + packet->offset, ++ phys_to_virt(myNextRxDesc->buf), packet->actual_length); ++ if(packet->actual_length > 0) ++ isoc_dbg("Copied %d bytes, packet %d for URB:0x%x[%d]\n", ++ packet->actual_length, urb_priv->isoc_packet_counter, ++ (unsigned int)urb, urb_priv->urb_num); ++ } ++ ++ /* Increment the packet counter. */ ++ urb_priv->isoc_packet_counter++; ++ ++ /* Note that we don't care about the eot field in the rx descriptor's ++ status. It will always be set for isoc traffic. */ ++ if (urb->number_of_packets == urb_priv->isoc_packet_counter) { ++ /* Complete the urb with status OK. */ ++ tc_finish_urb(hcd, urb, 0); ++ } ++ } ++ ++ skip_out: ++ myNextRxDesc->status = 0; ++ myNextRxDesc->command |= IO_MASK(USB_IN_command, eol); ++ myLastRxDesc->command &= ~IO_MASK(USB_IN_command, eol); ++ myLastRxDesc = myNextRxDesc; ++ myNextRxDesc = phys_to_virt(myNextRxDesc->next); ++ flush_etrax_cache(); ++ *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, restart); ++ } ++ ++ local_irq_restore(flags); ++ ++ return IRQ_HANDLED; ++} ++ ++static void tc_bulk_start_timer_func(unsigned long dummy) { ++ /* We might enable an EP descriptor behind the current DMA position when ++ it's about to decide that there are no more bulk traffic and it should ++ stop the bulk channel. ++ Therefore we periodically check if the bulk channel is stopped and there ++ is an enabled bulk EP descriptor, in which case we start the bulk ++ channel. */ ++ ++ if (!(*R_DMA_CH8_SUB0_CMD & IO_MASK(R_DMA_CH8_SUB0_CMD, cmd))) { ++ int epid; ++ ++ timer_dbg("bulk_start_timer: Bulk DMA channel not running.\n"); ++ ++ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { ++ if (TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) { ++ timer_warn("Found enabled EP for epid %d, starting bulk channel.\n", ++ epid); ++ restart_dma8_sub0(); ++ ++ /* Restart the bulk eot timer since we just started the bulk channel.*/ ++ mod_timer(&bulk_eot_timer, jiffies + BULK_EOT_TIMER_INTERVAL); ++ ++ /* No need to search any further. */ ++ break; ++ } ++ } ++ } else { ++ timer_dbg("bulk_start_timer: Bulk DMA channel running.\n"); ++ } ++} ++ ++static void tc_bulk_eot_timer_func(unsigned long dummy) { ++ struct usb_hcd *hcd = (struct usb_hcd*)dummy; ++ ASSERT(hcd); ++ /* Because of a race condition in the top half, we might miss a bulk eot. ++ This timer "simulates" a bulk eot if we don't get one for a while, ++ hopefully correcting the situation. */ ++ timer_dbg("bulk_eot_timer timed out.\n"); ++ check_finished_bulk_tx_epids(hcd, 1); ++} ++ ++ ++/*************************************************************/ ++/*************************************************************/ ++/* Device driver block */ ++/*************************************************************/ ++/*************************************************************/ ++ ++/* Forward declarations for device driver functions */ ++static int devdrv_hcd_probe(struct device *); ++static int devdrv_hcd_remove(struct device *); ++#ifdef CONFIG_PM ++static int devdrv_hcd_suspend(struct device *, u32, u32); ++static int devdrv_hcd_resume(struct device *, u32); ++#endif /* CONFIG_PM */ ++ ++/* the device */ ++static struct platform_device *devdrv_hc_platform_device; ++ ++/* device driver interface */ ++static struct device_driver devdrv_hc_device_driver = { ++ .name = (char *) hc_name, ++ .bus = &platform_bus_type, ++ ++ .probe = devdrv_hcd_probe, ++ .remove = devdrv_hcd_remove, ++ ++#ifdef CONFIG_PM ++ .suspend = devdrv_hcd_suspend, ++ .resume = devdrv_hcd_resume, ++#endif /* CONFIG_PM */ ++}; ++ ++/* initialize the host controller and driver */ ++static int __init_or_module devdrv_hcd_probe(struct device *dev) ++{ ++ struct usb_hcd *hcd; ++ struct crisv10_hcd *crisv10_hcd; ++ int retval; ++ int rev_maj, rev_min; ++ ++ /* Check DMA burst length */ ++ if(IO_EXTRACT(R_BUS_CONFIG, dma_burst, *R_BUS_CONFIG) != ++ IO_STATE(R_BUS_CONFIG, dma_burst, burst32)) { ++ devdrv_err("Invalid DMA burst length in Etrax 100LX," ++ " needs to be 32\n"); ++ return -EPERM; ++ } ++ ++ hcd = usb_create_hcd(&crisv10_hc_driver, dev, dev_name(dev)); ++ if (!hcd) ++ return -ENOMEM; ++ ++ crisv10_hcd = hcd_to_crisv10_hcd(hcd); ++ spin_lock_init(&crisv10_hcd->lock); ++ crisv10_hcd->num_ports = num_ports(); ++ crisv10_hcd->running = 0; ++ ++ dev_set_drvdata(dev, crisv10_hcd); ++ ++ devdrv_dbg("ETRAX USB IRQs HC:%d RX:%d TX:%d\n", ETRAX_USB_HC_IRQ, ++ ETRAX_USB_RX_IRQ, ETRAX_USB_TX_IRQ); ++ ++ /* Print out chip version read from registers */ ++ rev_maj = *R_USB_REVISION & IO_MASK(R_USB_REVISION, major); ++ rev_min = *R_USB_REVISION & IO_MASK(R_USB_REVISION, minor); ++ if(rev_min == 0) { ++ devdrv_info("Etrax 100LX USB Revision %d v1,2\n", rev_maj); ++ } else { ++ devdrv_info("Etrax 100LX USB Revision %d v%d\n", rev_maj, rev_min); ++ } ++ ++ devdrv_info("Bulk timer interval, start:%d eot:%d\n", ++ BULK_START_TIMER_INTERVAL, ++ BULK_EOT_TIMER_INTERVAL); ++ ++ ++ /* Init root hub data structures */ ++ if(rh_init()) { ++ devdrv_err("Failed init data for Root Hub\n"); ++ retval = -ENOMEM; ++ } ++ ++ if(port_in_use(0)) { ++ if (cris_request_io_interface(if_usb_1, "ETRAX100LX USB-HCD")) { ++ printk(KERN_CRIT "usb-host: request IO interface usb1 failed"); ++ retval = -EBUSY; ++ goto out; ++ } ++ devdrv_info("Claimed interface for USB physical port 1\n"); ++ } ++ if(port_in_use(1)) { ++ if (cris_request_io_interface(if_usb_2, "ETRAX100LX USB-HCD")) { ++ /* Free first interface if second failed to be claimed */ ++ if(port_in_use(0)) { ++ cris_free_io_interface(if_usb_1); ++ } ++ printk(KERN_CRIT "usb-host: request IO interface usb2 failed"); ++ retval = -EBUSY; ++ goto out; ++ } ++ devdrv_info("Claimed interface for USB physical port 2\n"); ++ } ++ ++ /* Init transfer controller structs and locks */ ++ if((retval = tc_init(hcd)) != 0) { ++ goto out; ++ } ++ ++ /* Attach interrupt functions for DMA and init DMA controller */ ++ if((retval = tc_dma_init(hcd)) != 0) { ++ goto out; ++ } ++ ++ /* Attach the top IRQ handler for USB controller interrupts */ ++ if (request_irq(ETRAX_USB_HC_IRQ, crisv10_hcd_top_irq, 0, ++ "ETRAX 100LX built-in USB (HC)", hcd)) { ++ err("Could not allocate IRQ %d for USB", ETRAX_USB_HC_IRQ); ++ retval = -EBUSY; ++ goto out; ++ } ++ ++ /* iso_eof is only enabled when isoc traffic is running. */ ++ *R_USB_IRQ_MASK_SET = ++ /* IO_STATE(R_USB_IRQ_MASK_SET, iso_eof, set) | */ ++ IO_STATE(R_USB_IRQ_MASK_SET, bulk_eot, set) | ++ IO_STATE(R_USB_IRQ_MASK_SET, epid_attn, set) | ++ IO_STATE(R_USB_IRQ_MASK_SET, port_status, set) | ++ IO_STATE(R_USB_IRQ_MASK_SET, ctl_status, set); ++ ++ ++ crisv10_ready_wait(); ++ /* Reset the USB interface. */ ++ *R_USB_COMMAND = ++ IO_STATE(R_USB_COMMAND, port_sel, nop) | ++ IO_STATE(R_USB_COMMAND, port_cmd, reset) | ++ IO_STATE(R_USB_COMMAND, ctrl_cmd, reset); ++ ++ /* Designer's Reference, p. 8 - 10 says we should Initate R_USB_FM_PSTART to ++ 0x2A30 (10800), to guarantee that control traffic gets 10% of the ++ bandwidth, and periodic transfer may allocate the rest (90%). ++ This doesn't work though. ++ The value 11960 is chosen to be just after the SOF token, with a couple ++ of bit times extra for possible bit stuffing. */ ++ *R_USB_FM_PSTART = IO_FIELD(R_USB_FM_PSTART, value, 11960); ++ ++ crisv10_ready_wait(); ++ /* Configure the USB interface as a host controller. */ ++ *R_USB_COMMAND = ++ IO_STATE(R_USB_COMMAND, port_sel, nop) | ++ IO_STATE(R_USB_COMMAND, port_cmd, reset) | ++ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_config); ++ ++ ++ /* Check so controller not busy before enabling ports */ ++ crisv10_ready_wait(); ++ ++ /* Enable selected USB ports */ ++ if(port_in_use(0)) { ++ *R_USB_PORT1_DISABLE = IO_STATE(R_USB_PORT1_DISABLE, disable, no); ++ } else { ++ *R_USB_PORT1_DISABLE = IO_STATE(R_USB_PORT1_DISABLE, disable, yes); ++ } ++ if(port_in_use(1)) { ++ *R_USB_PORT2_DISABLE = IO_STATE(R_USB_PORT2_DISABLE, disable, no); ++ } else { ++ *R_USB_PORT2_DISABLE = IO_STATE(R_USB_PORT2_DISABLE, disable, yes); ++ } ++ ++ crisv10_ready_wait(); ++ /* Start processing of USB traffic. */ ++ *R_USB_COMMAND = ++ IO_STATE(R_USB_COMMAND, port_sel, nop) | ++ IO_STATE(R_USB_COMMAND, port_cmd, reset) | ++ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_run); ++ ++ /* Do not continue probing initialization before USB interface is done */ ++ crisv10_ready_wait(); ++ ++ /* Register our Host Controller to USB Core ++ * Finish the remaining parts of generic HCD initialization: allocate the ++ * buffers of consistent memory, register the bus ++ * and call the driver's reset() and start() routines. */ ++ retval = usb_add_hcd(hcd, ETRAX_USB_HC_IRQ, IRQF_DISABLED); ++ if (retval != 0) { ++ devdrv_err("Failed registering HCD driver\n"); ++ goto out; ++ } ++ ++ return 0; ++ ++ out: ++ devdrv_hcd_remove(dev); ++ return retval; ++} ++ ++ ++/* cleanup after the host controller and driver */ ++static int __init_or_module devdrv_hcd_remove(struct device *dev) ++{ ++ struct crisv10_hcd *crisv10_hcd = dev_get_drvdata(dev); ++ struct usb_hcd *hcd; ++ ++ if (!crisv10_hcd) ++ return 0; ++ hcd = crisv10_hcd_to_hcd(crisv10_hcd); ++ ++ ++ /* Stop USB Controller in Etrax 100LX */ ++ crisv10_hcd_reset(hcd); ++ ++ usb_remove_hcd(hcd); ++ devdrv_dbg("Removed HCD from USB Core\n"); ++ ++ /* Free USB Controller IRQ */ ++ free_irq(ETRAX_USB_HC_IRQ, NULL); ++ ++ /* Free resources */ ++ tc_dma_destroy(); ++ tc_destroy(); ++ ++ ++ if(port_in_use(0)) { ++ cris_free_io_interface(if_usb_1); ++ } ++ if(port_in_use(1)) { ++ cris_free_io_interface(if_usb_2); ++ } ++ ++ devdrv_dbg("Freed all claimed resources\n"); ++ ++ return 0; ++} ++ ++ ++#ifdef CONFIG_PM ++ ++static int devdrv_hcd_suspend(struct usb_hcd *hcd, u32 state, u32 level) ++{ ++ return 0; /* no-op for now */ ++} ++ ++static int devdrv_hcd_resume(struct usb_hcd *hcd, u32 level) ++{ ++ return 0; /* no-op for now */ ++} ++ ++#endif /* CONFIG_PM */ ++ ++ ++ ++/*************************************************************/ ++/*************************************************************/ ++/* Module block */ ++/*************************************************************/ ++/*************************************************************/ ++ ++/* register driver */ ++static int __init module_hcd_init(void) ++{ ++ ++ if (usb_disabled()) ++ return -ENODEV; ++ ++ /* Here we select enabled ports by following defines created from ++ menuconfig */ ++#ifndef CONFIG_ETRAX_USB_HOST_PORT1 ++ ports &= ~(1<<0); ++#endif ++#ifndef CONFIG_ETRAX_USB_HOST_PORT2 ++ ports &= ~(1<<1); ++#endif ++ ++ printk(KERN_INFO "%s version "VERSION" "COPYRIGHT"\n", product_desc); ++ ++ devdrv_hc_platform_device = ++ platform_device_register_simple((char *) hc_name, 0, NULL, 0); ++ ++ if (IS_ERR(devdrv_hc_platform_device)) ++ return PTR_ERR(devdrv_hc_platform_device); ++ return driver_register(&devdrv_hc_device_driver); ++ /* ++ * Note that we do not set the DMA mask for the device, ++ * i.e. we pretend that we will use PIO, since no specific ++ * allocation routines are needed for DMA buffers. This will ++ * cause the HCD buffer allocation routines to fall back to ++ * kmalloc(). ++ */ ++} ++ ++/* unregister driver */ ++static void __exit module_hcd_exit(void) ++{ ++ driver_unregister(&devdrv_hc_device_driver); ++} ++ ++ ++/* Module hooks */ ++module_init(module_hcd_init); ++module_exit(module_hcd_exit); +diff -Nur linux-2.6.39.orig/drivers/usb/host/hc-crisv10.h linux-2.6.39/drivers/usb/host/hc-crisv10.h +--- linux-2.6.39.orig/drivers/usb/host/hc-crisv10.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/usb/host/hc-crisv10.h 2011-08-25 07:43:03.100480030 +0200 +@@ -0,0 +1,331 @@ ++#ifndef __LINUX_ETRAX_USB_H ++#define __LINUX_ETRAX_USB_H ++ ++#include ++#include ++ ++struct USB_IN_Desc { ++ volatile __u16 sw_len; ++ volatile __u16 command; ++ volatile unsigned long next; ++ volatile unsigned long buf; ++ volatile __u16 hw_len; ++ volatile __u16 status; ++}; ++ ++struct USB_SB_Desc { ++ volatile __u16 sw_len; ++ volatile __u16 command; ++ volatile unsigned long next; ++ volatile unsigned long buf; ++}; ++ ++struct USB_EP_Desc { ++ volatile __u16 hw_len; ++ volatile __u16 command; ++ volatile unsigned long sub; ++ volatile unsigned long next; ++}; ++ ++ ++/* Root Hub port status struct */ ++struct crisv10_rh { ++ volatile __u16 wPortChange[2]; ++ volatile __u16 wPortStatusPrev[2]; ++}; ++ ++/* HCD description */ ++struct crisv10_hcd { ++ spinlock_t lock; ++ __u8 num_ports; ++ __u8 running; ++}; ++ ++ ++/* Endpoint HC private data description */ ++struct crisv10_ep_priv { ++ int epid; ++}; ++ ++/* Additional software state info for a USB Controller epid */ ++struct etrax_epid { ++ __u8 inuse; /* !0 = setup in Etrax and used for a endpoint */ ++ __u8 disabled; /* !0 = Temporarly disabled to avoid resubmission */ ++ __u8 type; /* Setup as: PIPE_BULK, PIPE_CONTROL ... */ ++ __u8 out_traffic; /* !0 = This epid is for out traffic */ ++}; ++ ++/* Struct to hold information of scheduled later URB completion */ ++struct urb_later_data { ++// struct work_struct ws; ++ struct delayed_work ws; ++ struct usb_hcd *hcd; ++ struct urb *urb; ++ int urb_num; ++ int status; ++}; ++ ++ ++typedef enum { ++ STARTED, ++ NOT_STARTED, ++ UNLINK, ++} crisv10_urb_state_t; ++ ++ ++struct crisv10_urb_priv { ++ /* Sequence number for this URB. Every new submited URB gets this from ++ a incrementing counter. Used when a URB is scheduled for later finish to ++ be sure that the intended URB hasn't already been completed (device ++ drivers has a tendency to reuse URBs once they are completed, causing us ++ to not be able to single old ones out only based on the URB pointer.) */ ++ __u32 urb_num; ++ ++ /* The first_sb field is used for freeing all SB descriptors belonging ++ to an urb. The corresponding ep descriptor's sub pointer cannot be ++ used for this since the DMA advances the sub pointer as it processes ++ the sb list. */ ++ struct USB_SB_Desc *first_sb; ++ ++ /* The last_sb field referes to the last SB descriptor that belongs to ++ this urb. This is important to know so we can free the SB descriptors ++ that ranges between first_sb and last_sb. */ ++ struct USB_SB_Desc *last_sb; ++ ++ /* The rx_offset field is used in ctrl and bulk traffic to keep track ++ of the offset in the urb's transfer_buffer where incoming data should be ++ copied to. */ ++ __u32 rx_offset; ++ ++ /* Counter used in isochronous transfers to keep track of the ++ number of packets received/transmitted. */ ++ __u32 isoc_packet_counter; ++ ++ /* Flag that marks if this Isoc Out URB has finished it's transfer. Used ++ because several URBs can be finished before list is processed */ ++ __u8 isoc_out_done; ++ ++ /* This field is used to pass information about the urb's current state ++ between the various interrupt handlers (thus marked volatile). */ ++ volatile crisv10_urb_state_t urb_state; ++ ++ /* In Ctrl transfers consist of (at least) 3 packets: SETUP, IN and ZOUT. ++ When DMA8 sub-channel 2 has processed the SB list for this sequence we ++ get a interrupt. We also get a interrupt for In transfers and which ++ one of these interrupts that comes first depends of data size and device. ++ To be sure that we have got both interrupts before we complete the URB ++ we have these to flags that shows which part that has completed. ++ We can then check when we get one of the interrupts that if the other has ++ occured it's safe for us to complete the URB, otherwise we set appropriate ++ flag and do the completion when we get the other interrupt. */ ++ volatile unsigned char ctrl_zout_done; ++ volatile unsigned char ctrl_rx_done; ++ ++ /* Connection between the submitted urb and ETRAX epid number */ ++ __u8 epid; ++ ++ /* The rx_data_list field is used for periodic traffic, to hold ++ received data for later processing in the the complete_urb functions, ++ where the data us copied to the urb's transfer_buffer. Basically, we ++ use this intermediate storage because we don't know when it's safe to ++ reuse the transfer_buffer (FIXME?). */ ++ struct list_head rx_data_list; ++ ++ ++ /* The interval time rounded up to closest 2^N */ ++ int interval; ++ ++ /* Pool of EP descriptors needed if it's a INTR transfer. ++ Amount of EPs in pool correspons to how many INTR that should ++ be inserted in TxIntrEPList (max 128, defined by MAX_INTR_INTERVAL) */ ++ struct USB_EP_Desc* intr_ep_pool[128]; ++ ++ /* The mount of EPs allocated for this INTR URB */ ++ int intr_ep_pool_length; ++ ++ /* Pointer to info struct if URB is scheduled to be finished later */ ++ struct urb_later_data* later_data; ++}; ++ ++ ++/* This struct is for passing data from the top half to the bottom half irq ++ handlers */ ++struct crisv10_irq_reg { ++ struct usb_hcd* hcd; ++ __u32 r_usb_epid_attn; ++ __u8 r_usb_status; ++ __u16 r_usb_rh_port_status_1; ++ __u16 r_usb_rh_port_status_2; ++ __u32 r_usb_irq_mask_read; ++ __u32 r_usb_fm_number; ++ struct work_struct usb_bh; ++}; ++ ++ ++/* This struct is for passing data from the isoc top half to the isoc bottom ++ half. */ ++struct crisv10_isoc_complete_data { ++ struct usb_hcd *hcd; ++ struct urb *urb; ++ struct work_struct usb_bh; ++}; ++ ++/* Entry item for URB lists for each endpint */ ++typedef struct urb_entry ++{ ++ struct urb *urb; ++ struct list_head list; ++} urb_entry_t; ++ ++/* --------------------------------------------------------------------------- ++ Virtual Root HUB ++ ------------------------------------------------------------------------- */ ++/* destination of request */ ++#define RH_INTERFACE 0x01 ++#define RH_ENDPOINT 0x02 ++#define RH_OTHER 0x03 ++ ++#define RH_CLASS 0x20 ++#define RH_VENDOR 0x40 ++ ++/* Requests: bRequest << 8 | bmRequestType */ ++#define RH_GET_STATUS 0x0080 ++#define RH_CLEAR_FEATURE 0x0100 ++#define RH_SET_FEATURE 0x0300 ++#define RH_SET_ADDRESS 0x0500 ++#define RH_GET_DESCRIPTOR 0x0680 ++#define RH_SET_DESCRIPTOR 0x0700 ++#define RH_GET_CONFIGURATION 0x0880 ++#define RH_SET_CONFIGURATION 0x0900 ++#define RH_GET_STATE 0x0280 ++#define RH_GET_INTERFACE 0x0A80 ++#define RH_SET_INTERFACE 0x0B00 ++#define RH_SYNC_FRAME 0x0C80 ++/* Our Vendor Specific Request */ ++#define RH_SET_EP 0x2000 ++ ++ ++/* Hub port features */ ++#define RH_PORT_CONNECTION 0x00 ++#define RH_PORT_ENABLE 0x01 ++#define RH_PORT_SUSPEND 0x02 ++#define RH_PORT_OVER_CURRENT 0x03 ++#define RH_PORT_RESET 0x04 ++#define RH_PORT_POWER 0x08 ++#define RH_PORT_LOW_SPEED 0x09 ++#define RH_C_PORT_CONNECTION 0x10 ++#define RH_C_PORT_ENABLE 0x11 ++#define RH_C_PORT_SUSPEND 0x12 ++#define RH_C_PORT_OVER_CURRENT 0x13 ++#define RH_C_PORT_RESET 0x14 ++ ++/* Hub features */ ++#define RH_C_HUB_LOCAL_POWER 0x00 ++#define RH_C_HUB_OVER_CURRENT 0x01 ++ ++#define RH_DEVICE_REMOTE_WAKEUP 0x00 ++#define RH_ENDPOINT_STALL 0x01 ++ ++/* Our Vendor Specific feature */ ++#define RH_REMOVE_EP 0x00 ++ ++ ++#define RH_ACK 0x01 ++#define RH_REQ_ERR -1 ++#define RH_NACK 0x00 ++ ++/* Field definitions for */ ++ ++#define USB_IN_command__eol__BITNR 0 /* command macros */ ++#define USB_IN_command__eol__WIDTH 1 ++#define USB_IN_command__eol__no 0 ++#define USB_IN_command__eol__yes 1 ++ ++#define USB_IN_command__intr__BITNR 3 ++#define USB_IN_command__intr__WIDTH 1 ++#define USB_IN_command__intr__no 0 ++#define USB_IN_command__intr__yes 1 ++ ++#define USB_IN_status__eop__BITNR 1 /* status macros. */ ++#define USB_IN_status__eop__WIDTH 1 ++#define USB_IN_status__eop__no 0 ++#define USB_IN_status__eop__yes 1 ++ ++#define USB_IN_status__eot__BITNR 5 ++#define USB_IN_status__eot__WIDTH 1 ++#define USB_IN_status__eot__no 0 ++#define USB_IN_status__eot__yes 1 ++ ++#define USB_IN_status__error__BITNR 6 ++#define USB_IN_status__error__WIDTH 1 ++#define USB_IN_status__error__no 0 ++#define USB_IN_status__error__yes 1 ++ ++#define USB_IN_status__nodata__BITNR 7 ++#define USB_IN_status__nodata__WIDTH 1 ++#define USB_IN_status__nodata__no 0 ++#define USB_IN_status__nodata__yes 1 ++ ++#define USB_IN_status__epid__BITNR 8 ++#define USB_IN_status__epid__WIDTH 5 ++ ++#define USB_EP_command__eol__BITNR 0 ++#define USB_EP_command__eol__WIDTH 1 ++#define USB_EP_command__eol__no 0 ++#define USB_EP_command__eol__yes 1 ++ ++#define USB_EP_command__eof__BITNR 1 ++#define USB_EP_command__eof__WIDTH 1 ++#define USB_EP_command__eof__no 0 ++#define USB_EP_command__eof__yes 1 ++ ++#define USB_EP_command__intr__BITNR 3 ++#define USB_EP_command__intr__WIDTH 1 ++#define USB_EP_command__intr__no 0 ++#define USB_EP_command__intr__yes 1 ++ ++#define USB_EP_command__enable__BITNR 4 ++#define USB_EP_command__enable__WIDTH 1 ++#define USB_EP_command__enable__no 0 ++#define USB_EP_command__enable__yes 1 ++ ++#define USB_EP_command__hw_valid__BITNR 5 ++#define USB_EP_command__hw_valid__WIDTH 1 ++#define USB_EP_command__hw_valid__no 0 ++#define USB_EP_command__hw_valid__yes 1 ++ ++#define USB_EP_command__epid__BITNR 8 ++#define USB_EP_command__epid__WIDTH 5 ++ ++#define USB_SB_command__eol__BITNR 0 /* command macros. */ ++#define USB_SB_command__eol__WIDTH 1 ++#define USB_SB_command__eol__no 0 ++#define USB_SB_command__eol__yes 1 ++ ++#define USB_SB_command__eot__BITNR 1 ++#define USB_SB_command__eot__WIDTH 1 ++#define USB_SB_command__eot__no 0 ++#define USB_SB_command__eot__yes 1 ++ ++#define USB_SB_command__intr__BITNR 3 ++#define USB_SB_command__intr__WIDTH 1 ++#define USB_SB_command__intr__no 0 ++#define USB_SB_command__intr__yes 1 ++ ++#define USB_SB_command__tt__BITNR 4 ++#define USB_SB_command__tt__WIDTH 2 ++#define USB_SB_command__tt__zout 0 ++#define USB_SB_command__tt__in 1 ++#define USB_SB_command__tt__out 2 ++#define USB_SB_command__tt__setup 3 ++ ++ ++#define USB_SB_command__rem__BITNR 8 ++#define USB_SB_command__rem__WIDTH 6 ++ ++#define USB_SB_command__full__BITNR 6 ++#define USB_SB_command__full__WIDTH 1 ++#define USB_SB_command__full__no 0 ++#define USB_SB_command__full__yes 1 ++ ++#endif +diff -Nur linux-2.6.39.orig/drivers/usb/host/Makefile linux-2.6.39/drivers/usb/host/Makefile +--- linux-2.6.39.orig/drivers/usb/host/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/usb/host/Makefile 2011-08-25 07:43:03.209057611 +0200 +@@ -32,6 +32,7 @@ + obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o + obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o + obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o ++obj-$(CONFIG_ETRAX_USB_HOST) += hc-crisv10.o + obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o + obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o + obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o +diff -Nur linux-2.6.39.orig/drivers/usb/Makefile linux-2.6.39/drivers/usb/Makefile +--- linux-2.6.39.orig/drivers/usb/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/usb/Makefile 2011-08-25 07:43:03.380490677 +0200 +@@ -21,6 +21,7 @@ + obj-$(CONFIG_USB_R8A66597_HCD) += host/ + obj-$(CONFIG_USB_HWA_HCD) += host/ + obj-$(CONFIG_USB_ISP1760_HCD) += host/ ++obj-$(CONFIG_ETRAX_USB_HOST) += host/ + obj-$(CONFIG_USB_IMX21_HCD) += host/ + + obj-$(CONFIG_USB_C67X00_HCD) += c67x00/ +diff -Nur linux-2.6.39.orig/lib/klist.c linux-2.6.39/lib/klist.c +--- linux-2.6.39.orig/lib/klist.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/lib/klist.c 2011-08-25 07:43:03.558483154 +0200 +@@ -60,7 +60,7 @@ + { + knode->n_klist = klist; + /* no knode deserves to start its life dead */ +- WARN_ON(knode_dead(knode)); ++ //WARN_ON(knode_dead(knode)); + } + + static void knode_kill(struct klist_node *knode) diff --git a/target/linux/patches/2.6.39.4/defaults.patch b/target/linux/patches/2.6.39.4/defaults.patch new file mode 100644 index 000000000..d24c1c367 --- /dev/null +++ b/target/linux/patches/2.6.39.4/defaults.patch @@ -0,0 +1,26 @@ +diff -Nur linux-2.6.39.orig/fs/Kconfig linux-2.6.39/fs/Kconfig +--- linux-2.6.39.orig/fs/Kconfig 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/fs/Kconfig 2011-08-08 20:33:22.618014757 +0200 +@@ -44,10 +44,10 @@ + # this symbol for ifdefs in core code. + # + config FS_POSIX_ACL +- def_bool n ++ def_bool y + + config EXPORTFS +- bool ++ def_bool y + + config FILE_LOCKING + bool "Enable POSIX file locking API" if EXPERT +diff -Nur linux-2.6.39.orig/fs/notify/Kconfig linux-2.6.39/fs/notify/Kconfig +--- linux-2.6.39.orig/fs/notify/Kconfig 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/fs/notify/Kconfig 2011-08-08 20:33:38.328017344 +0200 +@@ -1,5 +1,5 @@ + config FSNOTIFY +- def_bool n ++ def_bool y + + source "fs/notify/dnotify/Kconfig" + source "fs/notify/inotify/Kconfig" diff --git a/target/linux/patches/2.6.39.4/fon2100.patch b/target/linux/patches/2.6.39.4/fon2100.patch new file mode 100644 index 000000000..038ff7020 --- /dev/null +++ b/target/linux/patches/2.6.39.4/fon2100.patch @@ -0,0 +1,6279 @@ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms linux-2.6.39-rc7/arch/mips/Kbuild.platforms +--- linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/mips/Kbuild.platforms 2011-05-15 21:34:57.000000000 +0200 +@@ -6,6 +6,7 @@ + platforms += bcm47xx + platforms += bcm63xx + platforms += cavium-octeon ++platforms += ar231x + platforms += cobalt + platforms += dec + platforms += emma +diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kconfig linux-2.6.39-rc7/arch/mips/Kconfig +--- linux-2.6.39-rc7.orig/arch/mips/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/mips/Kconfig 2011-05-16 12:11:11.000000000 +0200 +@@ -121,6 +121,21 @@ + help + Support for BCM63XX based boards + ++config ATHEROS_AR231X ++ bool "Atheros 231x/531x SoC support" ++ select CEVT_R4K ++ select CSRC_R4K ++ select DMA_NONCOHERENT ++ select IRQ_CPU ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select GENERIC_GPIO ++ select SYS_HAS_EARLY_PRINTK ++ select SYS_SUPPORTS_ZBOOT ++ help ++ Support for AR231x and AR531x based boards ++ + config MIPS_COBALT + bool "Cobalt Server" + select CEVT_R4K +@@ -738,6 +753,7 @@ + + endchoice + ++source "arch/mips/ar231x/Kconfig" + source "arch/mips/alchemy/Kconfig" + source "arch/mips/ath79/Kconfig" + source "arch/mips/bcm63xx/Kconfig" +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig linux-2.6.39-rc7/arch/mips/ar231x/Kconfig +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,27 @@ ++config ATHEROS_AR5312 ++ bool "Atheros 5312/2312+ support" ++ depends on ATHEROS_AR231X ++ default y ++ ++config ATHEROS_AR2315 ++ bool "Atheros 2315+ support" ++ depends on ATHEROS_AR231X ++ select DMA_NONCOHERENT ++ select CEVT_R4K ++ select CSRC_R4K ++ select IRQ_CPU ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select GENERIC_GPIO ++ default y ++ ++config ATHEROS_AR2315_PCI ++ bool "PCI support" ++ depends on ATHEROS_AR2315 ++ select HW_HAS_PCI ++ select PCI ++ select USB_ARCH_HAS_HCD ++ select USB_ARCH_HAS_OHCI ++ select USB_ARCH_HAS_EHCI ++ default n +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile linux-2.6.39-rc7/arch/mips/ar231x/Makefile +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,17 @@ ++# ++# This file is subject to the terms and conditions of the GNU General Public ++# License. See the file "COPYING" in the main directory of this archive ++# for more details. ++# ++# Copyright (C) 2006 FON Technology, SL. ++# Copyright (C) 2006 Imre Kaloz ++# Copyright (C) 2006-2009 Felix Fietkau ++# ++ ++obj-y += board.o prom.o devices.o ++ ++obj-$(CONFIG_EARLY_PRINTK) += early_printk.o ++ ++obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o ++obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o ++obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform linux-2.6.39-rc7/arch/mips/ar231x/Platform +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/Platform 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,6 @@ ++# ++# Atheros AR5312/AR2312 WiSoC ++# ++platform-$(CONFIG_ATHEROS_AR231X) += ar231x/ ++cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x ++load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000 +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c 2011-05-15 21:47:07.000000000 +0200 +@@ -0,0 +1,654 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++/* ++ * Platform devices for Atheros SoCs ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "devices.h" ++#include "ar2315.h" ++ ++static u32 gpiointmask = 0, gpiointval = 0; ++ ++static inline void ar2315_gpio_irq(void) ++{ ++ u32 pend; ++ int bit = -1; ++ ++ /* only do one gpio interrupt at a time */ ++ pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask; ++ ++ if (pend) { ++ bit = fls(pend) - 1; ++ pend &= ~(1 << bit); ++ gpiointval ^= (1 << bit); ++ } ++ ++ if (!pend) ++ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO); ++ ++ /* Enable interrupt with edge detection */ ++ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit)) ++ return; ++ ++ if (bit >= 0) ++ do_IRQ(AR531X_GPIO_IRQ_BASE + bit); ++} ++ ++#ifdef CONFIG_ATHEROS_AR2315_PCI ++static inline void pci_abort_irq(void) ++{ ++ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT); ++} ++ ++static inline void pci_ack_irq(void) ++{ ++ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT); ++} ++ ++void ar2315_pci_irq(int irq) ++{ ++ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT) ++ pci_abort_irq(); ++ else { ++ do_IRQ(irq); ++ pci_ack_irq(); ++ } ++} ++#endif /* CONFIG_ATHEROS_AR2315_PCI */ ++ ++/* ++ * Called when an interrupt is received, this function ++ * determines exactly which interrupt it was, and it ++ * invokes the appropriate handler. ++ * ++ * Implicitly, we also define interrupt priority by ++ * choosing which to dispatch first. ++ */ ++static asmlinkage void ++ar2315_irq_dispatch(void) ++{ ++ int pending = read_c0_status() & read_c0_cause(); ++ ++ if (pending & CAUSEF_IP3) ++ do_IRQ(AR2315_IRQ_WLAN0_INTRS); ++ else if (pending & CAUSEF_IP4) ++ do_IRQ(AR2315_IRQ_ENET0_INTRS); ++#ifdef CONFIG_ATHEROS_AR2315_PCI ++ else if (pending & CAUSEF_IP5) ++ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI); ++#endif ++ else if (pending & CAUSEF_IP2) { ++ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR); ++ ++ if (misc_intr & AR2315_ISR_SPI) ++ do_IRQ(AR531X_MISC_IRQ_SPI); ++ else if (misc_intr & AR2315_ISR_TIMER) ++ do_IRQ(AR531X_MISC_IRQ_TIMER); ++ else if (misc_intr & AR2315_ISR_AHB) ++ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); ++ else if (misc_intr & AR2315_ISR_GPIO) ++ ar2315_gpio_irq(); ++ else if (misc_intr & AR2315_ISR_UART0) ++ do_IRQ(AR531X_MISC_IRQ_UART0); ++ else if (misc_intr & AR2315_ISR_WD) ++ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); ++ else ++ do_IRQ(AR531X_MISC_IRQ_NONE); ++ } else if (pending & CAUSEF_IP7) ++ do_IRQ(AR531X_IRQ_CPU_CLOCK); ++} ++ ++static void ar2315_set_gpiointmask(int gpio, int level) ++{ ++ u32 reg; ++ ++ reg = ar231x_read_reg(AR2315_GPIO_INT); ++ reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M); ++ reg |= gpio | AR2315_GPIO_INT_LVL(level); ++ ar231x_write_reg(AR2315_GPIO_INT, reg); ++} ++ ++static void ar2315_gpio_intr_enable(struct irq_data *d) ++{ ++ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; ++ ++ /* Enable interrupt with edge detection */ ++ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio)) ++ return; ++ ++ gpiointmask |= (1 << gpio); ++ ar2315_set_gpiointmask(gpio, 3); ++} ++ ++static void ar2315_gpio_intr_disable(struct irq_data *d) ++{ ++ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; ++ ++ /* Disable interrupt */ ++ gpiointmask &= ~(1 << gpio); ++ ar2315_set_gpiointmask(gpio, 0); ++} ++ ++static struct irq_chip ar2315_gpio_intr_controller = { ++ .name = "AR2315-GPIO", ++ .irq_ack = ar2315_gpio_intr_disable, ++ .irq_mask_ack = ar2315_gpio_intr_disable, ++ .irq_mask = ar2315_gpio_intr_disable, ++ .irq_unmask = ar2315_gpio_intr_enable, ++}; ++ ++static void ++ar2315_misc_intr_enable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR2315_IMR); ++ switch(d->irq) { ++ case AR531X_MISC_IRQ_SPI: ++ imr |= AR2315_ISR_SPI; ++ break; ++ case AR531X_MISC_IRQ_TIMER: ++ imr |= AR2315_ISR_TIMER; ++ break; ++ case AR531X_MISC_IRQ_AHB_PROC: ++ imr |= AR2315_ISR_AHB; ++ break; ++ case AR531X_MISC_IRQ_GPIO: ++ imr |= AR2315_ISR_GPIO; ++ break; ++ case AR531X_MISC_IRQ_UART0: ++ imr |= AR2315_ISR_UART0; ++ break; ++ case AR531X_MISC_IRQ_WATCHDOG: ++ imr |= AR2315_ISR_WD; ++ break; ++ default: ++ break; ++ } ++ ar231x_write_reg(AR2315_IMR, imr); ++} ++ ++static void ++ar2315_misc_intr_disable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR2315_IMR); ++ switch(d->irq) { ++ case AR531X_MISC_IRQ_SPI: ++ imr &= ~AR2315_ISR_SPI; ++ break; ++ case AR531X_MISC_IRQ_TIMER: ++ imr &= ~AR2315_ISR_TIMER; ++ break; ++ case AR531X_MISC_IRQ_AHB_PROC: ++ imr &= ~AR2315_ISR_AHB; ++ break; ++ case AR531X_MISC_IRQ_GPIO: ++ imr &= ~AR2315_ISR_GPIO; ++ break; ++ case AR531X_MISC_IRQ_UART0: ++ imr &= ~AR2315_ISR_UART0; ++ break; ++ case AR531X_MISC_IRQ_WATCHDOG: ++ imr &= ~AR2315_ISR_WD; ++ break; ++ default: ++ break; ++ } ++ ar231x_write_reg(AR2315_IMR, imr); ++} ++ ++ ++static struct irq_chip ar2315_misc_intr_controller = { ++ .name = "AR2315-MISC", ++ .irq_mask = ar2315_misc_intr_disable, ++ .irq_unmask = ar2315_misc_intr_enable, ++}; ++ ++static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id) ++{ ++ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET); ++ ar231x_read_reg(AR2315_AHB_ERR1); ++ ++ printk(KERN_ERR "AHB fatal error\n"); ++ machine_restart("AHB error"); /* Catastrophic failure */ ++ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction ar2315_ahb_proc_interrupt = { ++ .handler = ar2315_ahb_proc_handler, ++ .flags = IRQF_DISABLED, ++ .name = "ar2315_ahb_proc_interrupt", ++}; ++ ++static struct irqaction cascade = { ++ .handler = no_action, ++ .flags = IRQF_DISABLED, ++ .name = "cascade", ++}; ++ ++void ++ar2315_irq_init(void) ++{ ++ int i; ++ ++ if (!is_2315()) ++ return; ++ ++ ar231x_irq_dispatch = ar2315_irq_dispatch; ++ gpiointval = ar231x_read_reg(AR2315_GPIO_DI); ++ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { ++ int irq = AR531X_MISC_IRQ_BASE + i; ++ irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller, ++ handle_level_irq); ++ } ++ for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) { ++ int irq = AR531X_GPIO_IRQ_BASE + i; ++ irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller, ++ handle_level_irq); ++ } ++ setup_irq(AR531X_MISC_IRQ_GPIO, &cascade); ++ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt); ++ setup_irq(AR2315_IRQ_MISC_INTRS, &cascade); ++} ++ ++const struct ar231x_gpiodev ar2315_gpiodev; ++ ++static u32 ++ar2315_gpio_get_output(void) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR2315_GPIO_CR); ++ reg &= ar2315_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar2315_gpio_set_output(u32 mask, u32 val) ++{ ++ u32 reg; ++ ++ reg = ar231x_read_reg(AR2315_GPIO_CR); ++ reg &= ~mask; ++ reg |= val; ++ ar231x_write_reg(AR2315_GPIO_CR, reg); ++ return reg; ++} ++ ++static u32 ++ar2315_gpio_get(void) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR2315_GPIO_DI); ++ reg &= ar2315_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar2315_gpio_set(u32 mask, u32 value) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR2315_GPIO_DO); ++ reg &= ~mask; ++ reg |= value; ++ ar231x_write_reg(AR2315_GPIO_DO, reg); ++ return reg; ++} ++ ++const struct ar231x_gpiodev ar2315_gpiodev = { ++ .valid_mask = (1 << 22) - 1, ++ .get_output = ar2315_gpio_get_output, ++ .set_output = ar2315_gpio_set_output, ++ .get = ar2315_gpio_get, ++ .set = ar2315_gpio_set, ++}; ++ ++static struct ar231x_eth ar2315_eth_data = { ++ .reset_base = AR2315_RESET, ++ .reset_mac = AR2315_RESET_ENET0, ++ .reset_phy = AR2315_RESET_EPHY0, ++ .phy_base = KSEG1ADDR(AR2315_ENET0), ++ .config = &ar231x_board, ++}; ++ ++static struct resource ar2315_spiflash_res[] = { ++ { ++ .name = "flash_base", ++ .flags = IORESOURCE_MEM, ++ .start = KSEG1ADDR(AR2315_SPI_READ), ++ .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1, ++ }, ++ { ++ .name = "flash_regs", ++ .flags = IORESOURCE_MEM, ++ .start = 0x11300000, ++ .end = 0x11300012, ++ }, ++}; ++ ++static struct platform_device ar2315_spiflash = { ++ .id = 0, ++ .name = "spiflash", ++ .resource = ar2315_spiflash_res, ++ .num_resources = ARRAY_SIZE(ar2315_spiflash_res) ++}; ++ ++static struct platform_device ar2315_wdt = { ++ .id = 0, ++ .name = "ar2315_wdt", ++}; ++ ++#define SPI_FLASH_CTL 0x00 ++#define SPI_FLASH_OPCODE 0x04 ++#define SPI_FLASH_DATA 0x08 ++ ++static inline u32 ++spiflash_read_reg(int reg) ++{ ++ return ar231x_read_reg(AR2315_SPI + reg); ++} ++ ++static inline void ++spiflash_write_reg(int reg, u32 data) ++{ ++ ar231x_write_reg(AR2315_SPI + reg, data); ++} ++ ++static u32 ++spiflash_wait_status(void) ++{ ++ u32 reg; ++ ++ do { ++ reg = spiflash_read_reg(SPI_FLASH_CTL); ++ } while (reg & SPI_CTL_BUSY); ++ ++ return reg; ++} ++ ++static u8 ++spiflash_probe(void) ++{ ++ u32 reg; ++ ++ reg = spiflash_wait_status(); ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= (1 << 4) | 4 | SPI_CTL_START; ++ ++ spiflash_write_reg(SPI_FLASH_OPCODE, 0xab); ++ spiflash_write_reg(SPI_FLASH_CTL, reg); ++ ++ reg = spiflash_wait_status(); ++ reg = spiflash_read_reg(SPI_FLASH_DATA); ++ reg &= 0xff; ++ ++ return (u8) reg; ++} ++ ++ ++#define STM_8MBIT_SIGNATURE 0x13 ++#define STM_16MBIT_SIGNATURE 0x14 ++#define STM_32MBIT_SIGNATURE 0x15 ++#define STM_64MBIT_SIGNATURE 0x16 ++#define STM_128MBIT_SIGNATURE 0x17 ++ ++static u8 __init * ++ar2315_flash_limit(void) ++{ ++ u32 flash_size = 0; ++ ++ /* probe the flash chip size */ ++ switch(spiflash_probe()) { ++ case STM_8MBIT_SIGNATURE: ++ flash_size = 0x00100000; ++ break; ++ case STM_16MBIT_SIGNATURE: ++ flash_size = 0x00200000; ++ break; ++ case STM_32MBIT_SIGNATURE: ++ flash_size = 0x00400000; ++ break; ++ case STM_64MBIT_SIGNATURE: ++ flash_size = 0x00800000; ++ break; ++ case STM_128MBIT_SIGNATURE: ++ flash_size = 0x01000000; ++ break; ++ } ++ ++ ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start + ++ flash_size - 1; ++ return (u8 *) ar2315_spiflash_res[0].end + 1; ++} ++ ++#ifdef CONFIG_LEDS_GPIO ++static struct gpio_led ar2315_leds[6]; ++static struct gpio_led_platform_data ar2315_led_data = { ++ .leds = (void *) ar2315_leds, ++}; ++ ++static struct platform_device ar2315_gpio_leds = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev = { ++ .platform_data = (void *) &ar2315_led_data, ++ } ++}; ++ ++static void __init ++ar2315_init_gpio(void) ++{ ++ static char led_names[6][6]; ++ int i, led = 0; ++ ++ ar2315_led_data.num_leds = 0; ++ for(i = 1; i < 8; i++) ++ { ++ if((i == AR2315_RESET_GPIO) || ++ (i == ar231x_board.config->resetConfigGpio)) ++ continue; ++ ++ if(i == ar231x_board.config->sysLedGpio) ++ strcpy(led_names[led], "wlan"); ++ else ++ sprintf(led_names[led], "gpio%d", i); ++ ++ ar2315_leds[led].name = led_names[led]; ++ ar2315_leds[led].gpio = i; ++ ar2315_leds[led].active_low = 0; ++ led++; ++ } ++ ar2315_led_data.num_leds = led; ++ platform_device_register(&ar2315_gpio_leds); ++} ++#else ++static inline void ar2315_init_gpio(void) ++{ ++} ++#endif ++ ++int __init ++ar2315_init_devices(void) ++{ ++ if (!is_2315()) ++ return 0; ++ ++ /* Find board configuration */ ++ ar231x_find_config(ar2315_flash_limit()); ++ ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac; ++ ++ ar2315_init_gpio(); ++ platform_device_register(&ar2315_wdt); ++ platform_device_register(&ar2315_spiflash); ++ ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS, ++ &ar2315_eth_data); ++ ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS); ++ ++ return 0; ++} ++ ++static void ++ar2315_restart(char *command) ++{ ++ void (*mips_reset_vec)(void) = (void *) 0xbfc00000; ++ ++ local_irq_disable(); ++ ++ /* try reset the system via reset control */ ++ ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM); ++ ++ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround. ++ * give it some time to attempt a gpio based hardware reset ++ * (atheros reference design workaround) */ ++ gpio_direction_output(AR2315_RESET_GPIO, 0); ++ mdelay(100); ++ ++ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic ++ * workaround. Attempt to jump to the mips reset location - ++ * the boot loader itself might be able to recover the system */ ++ mips_reset_vec(); ++} ++ ++ ++/* ++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register ++ * to determine the predevisor value. ++ */ ++static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; ++static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 }; ++ ++static unsigned int __init ++ar2315_sys_clk(unsigned int clockCtl) ++{ ++ unsigned int pllcCtrl,cpuDiv; ++ unsigned int pllcOut,refdiv,fdiv,divby2; ++ unsigned int clkDiv; ++ ++ pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL); ++ refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S; ++ refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv]; ++ fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S; ++ divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S; ++ divby2 += 1; ++ pllcOut = (40000000/refdiv)*(2*divby2)*fdiv; ++ ++ ++ /* clkm input selected */ ++ switch(clockCtl & CPUCLK_CLK_SEL_M) { ++ case 0: ++ case 1: ++ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S]; ++ break; ++ case 2: ++ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S]; ++ break; ++ default: ++ pllcOut = 40000000; ++ clkDiv = 1; ++ break; ++ } ++ cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S; ++ cpuDiv = cpuDiv * 2 ?: 1; ++ return (pllcOut/(clkDiv * cpuDiv)); ++} ++ ++static inline unsigned int ++ar2315_cpu_frequency(void) ++{ ++ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK)); ++} ++ ++static inline unsigned int ++ar2315_apb_frequency(void) ++{ ++ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK)); ++} ++ ++void __init ++ar2315_time_init(void) ++{ ++ if (!is_2315()) ++ return; ++ ++ mips_hpt_frequency = ar2315_cpu_frequency() / 2; ++} ++ ++void __init ++ar2315_prom_init(void) ++{ ++ u32 memsize, memcfg, devid; ++ ++ if (!is_2315()) ++ return; ++ ++ memcfg = ar231x_read_reg(AR2315_MEM_CFG); ++ memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S); ++ memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S); ++ memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S); ++ memsize <<= 3; ++ add_memory_region(0, memsize, BOOT_MEM_RAM); ++ ++ /* Detect the hardware based on the device ID */ ++ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP; ++ switch(devid) { ++ case 0x90: ++ case 0x91: ++ ar231x_devtype = DEV_TYPE_AR2317; ++ break; ++ default: ++ ar231x_devtype = DEV_TYPE_AR2315; ++ break; ++ } ++ ar231x_gpiodev = &ar2315_gpiodev; ++ ar231x_board.devid = devid; ++} ++ ++void __init ++ar2315_plat_setup(void) ++{ ++ u32 config; ++ ++ if (!is_2315()) ++ return; ++ ++ /* Clear any lingering AHB errors */ ++ config = read_c0_config(); ++ write_c0_config(config & ~0x3); ++ ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET); ++ ar231x_read_reg(AR2315_AHB_ERR1); ++ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION); ++ ++ _machine_restart = ar2315_restart; ++ ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency()); ++} +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,37 @@ ++#ifndef __AR2315_H ++#define __AR2315_H ++ ++#ifdef CONFIG_ATHEROS_AR2315 ++ ++extern void ar2315_irq_init(void); ++extern int ar2315_init_devices(void); ++extern void ar2315_prom_init(void); ++extern void ar2315_plat_setup(void); ++extern void ar2315_time_init(void); ++ ++#else ++ ++static inline void ar2315_irq_init(void) ++{ ++} ++ ++static inline int ar2315_init_devices(void) ++{ ++ return 0; ++} ++ ++static inline void ar2315_prom_init(void) ++{ ++} ++ ++static inline void ar2315_plat_setup(void) ++{ ++} ++ ++static inline void ar2315_time_init(void) ++{ ++} ++ ++#endif ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,538 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ */ ++ ++/* ++ * Platform devices for Atheros SoCs ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "devices.h" ++#include "ar5312.h" ++ ++static void ++ar5312_misc_irq_dispatch(void) ++{ ++ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR); ++ ++ if (ar231x_misc_intrs & AR531X_ISR_TIMER) { ++ do_IRQ(AR531X_MISC_IRQ_TIMER); ++ (void)ar231x_read_reg(AR531X_TIMER); ++ } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC) ++ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); ++ else if ((ar231x_misc_intrs & AR531X_ISR_UART0)) ++ do_IRQ(AR531X_MISC_IRQ_UART0); ++ else if (ar231x_misc_intrs & AR531X_ISR_WD) ++ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); ++ else ++ do_IRQ(AR531X_MISC_IRQ_NONE); ++} ++ ++static asmlinkage void ++ar5312_irq_dispatch(void) ++{ ++ int pending = read_c0_status() & read_c0_cause(); ++ ++ if (pending & CAUSEF_IP2) ++ do_IRQ(AR5312_IRQ_WLAN0_INTRS); ++ else if (pending & CAUSEF_IP3) ++ do_IRQ(AR5312_IRQ_ENET0_INTRS); ++ else if (pending & CAUSEF_IP4) ++ do_IRQ(AR5312_IRQ_ENET1_INTRS); ++ else if (pending & CAUSEF_IP5) ++ do_IRQ(AR5312_IRQ_WLAN1_INTRS); ++ else if (pending & CAUSEF_IP6) ++ ar5312_misc_irq_dispatch(); ++ else if (pending & CAUSEF_IP7) ++ do_IRQ(AR531X_IRQ_CPU_CLOCK); ++} ++ ++ ++/* Enable the specified AR531X_MISC_IRQ interrupt */ ++static void ++ar5312_misc_intr_enable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR531X_IMR); ++ imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); ++ ar231x_write_reg(AR531X_IMR, imr); ++} ++ ++/* Disable the specified AR531X_MISC_IRQ interrupt */ ++static void ++ar5312_misc_intr_disable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR531X_IMR); ++ imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); ++ ar231x_write_reg(AR531X_IMR, imr); ++ ar231x_read_reg(AR531X_IMR); /* flush write buffer */ ++} ++ ++static struct irq_chip ar5312_misc_intr_controller = { ++ .name = "AR5312-MISC", ++ .irq_mask = ar5312_misc_intr_disable, ++ .irq_unmask = ar5312_misc_intr_enable, ++}; ++ ++ ++static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id) ++{ ++ u32 proc1 = ar231x_read_reg(AR531X_PROC1); ++ u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */ ++ u32 dma1 = ar231x_read_reg(AR531X_DMA1); ++ u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */ ++ ++ printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", ++ procAddr, proc1, dmaAddr, dma1); ++ ++ machine_restart("AHB error"); /* Catastrophic failure */ ++ return IRQ_HANDLED; ++} ++ ++ ++static struct irqaction ar5312_ahb_proc_interrupt = { ++ .handler = ar5312_ahb_proc_handler, ++ .flags = IRQF_DISABLED, ++ .name = "ar5312_ahb_proc_interrupt", ++}; ++ ++ ++static struct irqaction cascade = { ++ .handler = no_action, ++ .flags = IRQF_DISABLED, ++ .name = "cascade", ++}; ++ ++void __init ar5312_irq_init(void) ++{ ++ int i; ++ ++ if (!is_5312()) ++ return; ++ ++ ar231x_irq_dispatch = ar5312_irq_dispatch; ++ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { ++ int irq = AR531X_MISC_IRQ_BASE + i; ++ irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller, ++ handle_level_irq); ++ } ++ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt); ++ setup_irq(AR5312_IRQ_MISC_INTRS, &cascade); ++} ++ ++const struct ar231x_gpiodev ar5312_gpiodev; ++ ++static u32 ++ar5312_gpio_get_output(void) ++{ ++ u32 reg; ++ reg = ~(ar231x_read_reg(AR531X_GPIO_CR)); ++ reg &= ar5312_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar5312_gpio_set_output(u32 mask, u32 val) ++{ ++ u32 reg; ++ ++ reg = ar231x_read_reg(AR531X_GPIO_CR); ++ reg |= mask; ++ reg &= ~val; ++ ar231x_write_reg(AR531X_GPIO_CR, reg); ++ return reg; ++} ++ ++static u32 ++ar5312_gpio_get(void) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR531X_GPIO_DI); ++ reg &= ar5312_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar5312_gpio_set(u32 mask, u32 value) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR531X_GPIO_DO); ++ reg &= ~mask; ++ reg |= value; ++ ar231x_write_reg(AR531X_GPIO_DO, reg); ++ return reg; ++} ++ ++const struct ar231x_gpiodev ar5312_gpiodev = { ++ .valid_mask = (1 << 8) - 1, ++ .get_output = ar5312_gpio_get_output, ++ .set_output = ar5312_gpio_set_output, ++ .get = ar5312_gpio_get, ++ .set = ar5312_gpio_set, ++}; ++ ++static struct physmap_flash_data ar5312_flash_data = { ++ .width = 2, ++}; ++ ++static struct resource ar5312_flash_resource = { ++ .start = AR531X_FLASH, ++ .end = AR531X_FLASH + 0x800000 - 1, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct ar231x_eth ar5312_eth0_data = { ++ .reset_base = AR531X_RESET, ++ .reset_mac = AR531X_RESET_ENET0, ++ .reset_phy = AR531X_RESET_EPHY0, ++ .phy_base = KSEG1ADDR(AR531X_ENET0), ++ .config = &ar231x_board, ++}; ++ ++static struct ar231x_eth ar5312_eth1_data = { ++ .reset_base = AR531X_RESET, ++ .reset_mac = AR531X_RESET_ENET1, ++ .reset_phy = AR531X_RESET_EPHY1, ++ .phy_base = KSEG1ADDR(AR531X_ENET1), ++ .config = &ar231x_board, ++}; ++ ++static struct platform_device ar5312_physmap_flash = { ++ .name = "physmap-flash", ++ .id = 0, ++ .dev.platform_data = &ar5312_flash_data, ++ .resource = &ar5312_flash_resource, ++ .num_resources = 1, ++}; ++ ++#ifdef CONFIG_LEDS_GPIO ++static struct gpio_led ar5312_leds[] = { ++ { .name = "wlan", .gpio = 0, .active_low = 1, }, ++}; ++ ++static const struct gpio_led_platform_data ar5312_led_data = { ++ .num_leds = ARRAY_SIZE(ar5312_leds), ++ .leds = (void *) ar5312_leds, ++}; ++ ++static struct platform_device ar5312_gpio_leds = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = (void *) &ar5312_led_data, ++}; ++#endif ++ ++/* ++ * NB: This mapping size is larger than the actual flash size, ++ * but this shouldn't be a problem here, because the flash ++ * will simply be mapped multiple times. ++ */ ++static char __init *ar5312_flash_limit(void) ++{ ++ u32 ctl; ++ /* ++ * Configure flash bank 0. ++ * Assume 8M window size. Flash will be aliased if it's smaller ++ */ ++ ctl = FLASHCTL_E | ++ FLASHCTL_AC_8M | ++ FLASHCTL_RBLE | ++ (0x01 << FLASHCTL_IDCY_S) | ++ (0x07 << FLASHCTL_WST1_S) | ++ (0x07 << FLASHCTL_WST2_S) | ++ (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW); ++ ++ ar231x_write_reg(AR531X_FLASHCTL0, ctl); ++ ++ /* Disable other flash banks */ ++ ar231x_write_reg(AR531X_FLASHCTL1, ++ ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC)); ++ ++ ar231x_write_reg(AR531X_FLASHCTL2, ++ ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC)); ++ ++ return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000); ++} ++ ++int __init ar5312_init_devices(void) ++{ ++ struct ar231x_boarddata *config; ++ u32 fctl = 0; ++ const u8 *radio; ++ u8 *c; ++ ++ if (!is_5312()) ++ return 0; ++ ++ /* Locate board/radio config data */ ++ ar231x_find_config(ar5312_flash_limit()); ++ config = ar231x_board.config; ++ ++ ++ /* ++ * Chip IDs and hardware detection for some Atheros ++ * models are really broken! ++ * ++ * Atheros uses a disabled WMAC0 and Silicon ID of AR5312 ++ * as indication for AR2312, which is otherwise ++ * indistinguishable from the real AR5312. ++ */ ++ if (ar231x_board.radio) { ++ radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF; ++ if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0) ++ config->flags |= BD_ISCASPER; ++ } else ++ radio = NULL; ++ ++ /* AR2313 has CPU minor rev. 10 */ ++ if ((current_cpu_data.processor_id & 0xff) == 0x0a) ++ ar231x_devtype = DEV_TYPE_AR2313; ++ ++ /* AR2312 shares the same Silicon ID as AR5312 */ ++ else if (config->flags & BD_ISCASPER) ++ ar231x_devtype = DEV_TYPE_AR2312; ++ ++ /* Everything else is probably AR5312 or compatible */ ++ else ++ ar231x_devtype = DEV_TYPE_AR5312; ++ ++ /* fixup flash width */ ++ fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW; ++ switch (fctl) { ++ case FLASHCTL_MWx16: ++ ar5312_flash_data.width = 2; ++ break; ++ case FLASHCTL_MWx8: ++ default: ++ ar5312_flash_data.width = 1; ++ break; ++ } ++ ++ platform_device_register(&ar5312_physmap_flash); ++ ++#ifdef CONFIG_LEDS_GPIO ++ ar5312_leds[0].gpio = config->sysLedGpio; ++ platform_device_register(&ar5312_gpio_leds); ++#endif ++ ++ /* Fix up MAC addresses if necessary */ ++ if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6)) ++ memcpy(config->enet0_mac, config->enet1_mac, 6); ++ ++ /* If ENET0 and ENET1 have the same mac address, ++ * increment the one from ENET1 */ ++ if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) { ++ c = config->enet1_mac + 5; ++ while ((c >= config->enet1_mac) && !(++(*c))) ++ c--; ++ } ++ ++ switch(ar231x_devtype) { ++ case DEV_TYPE_AR5312: ++ ar5312_eth0_data.macaddr = config->enet0_mac; ++ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0), ++ AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data); ++ ++ ar5312_eth1_data.macaddr = config->enet1_mac; ++ ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1), ++ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); ++ ++ if (!ar231x_board.radio) ++ return 0; ++ ++ if ((*((u32 *) radio) & AR531X_RADIO0_MASK) && ++ (config->flags & BD_WLAN0)) ++ ar231x_add_wmac(0, AR531X_WLAN0, ++ AR5312_IRQ_WLAN0_INTRS); ++ ++ break; ++ /* ++ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC ++ * of ENET1. Atheros calls it 'twisted' for a reason :) ++ */ ++ case DEV_TYPE_AR2312: ++ case DEV_TYPE_AR2313: ++ ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base; ++ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy; ++ ar5312_eth1_data.macaddr = config->enet0_mac; ++ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1), ++ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); ++ ++ if (!ar231x_board.radio) ++ return 0; ++ break; ++ default: ++ break; ++ } ++ ++ if ((*((u32 *) radio) & AR531X_RADIO1_MASK) && ++ (config->flags & BD_WLAN1)) ++ ar231x_add_wmac(1, AR531X_WLAN1, ++ AR5312_IRQ_WLAN1_INTRS); ++ ++ return 0; ++} ++ ++ ++static void ar5312_restart(char *command) ++{ ++ /* reset the system */ ++ local_irq_disable(); ++ while(1) { ++ ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM); ++ } ++} ++ ++ ++/* ++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register ++ * to determine the predevisor value. ++ */ ++static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; ++ ++ ++static int __init ++ar5312_cpu_frequency(void) ++{ ++ unsigned int result; ++ unsigned int predivide_mask, predivide_shift; ++ unsigned int multiplier_mask, multiplier_shift; ++ unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier; ++ unsigned int doubler_mask; ++ u16 devid; ++ ++ /* Trust the bootrom's idea of cpu frequency. */ ++ if ((result = ar231x_read_reg(AR5312_SCRATCH))) ++ return result; ++ ++ devid = ar231x_read_reg(AR531X_REV); ++ devid &= AR531X_REV_MAJ; ++ devid >>= AR531X_REV_MAJ_S; ++ if (devid == AR531X_REV_MAJ_AR2313) { ++ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK; ++ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT; ++ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK; ++ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT; ++ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK; ++ } else { /* AR5312 and AR2312 */ ++ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK; ++ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT; ++ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK; ++ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT; ++ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK; ++ } ++ ++ /* ++ * Clocking is derived from a fixed 40MHz input clock. ++ * ++ * cpuFreq = InputClock * MULT (where MULT is PLL multiplier) ++ * sysFreq = cpuFreq / 4 (used for APB clock, serial, ++ * flash, Timer, Watchdog Timer) ++ * ++ * cntFreq = cpuFreq / 2 (use for CPU count/compare) ++ * ++ * So, for example, with a PLL multiplier of 5, we have ++ * ++ * cpuFreq = 200MHz ++ * sysFreq = 50MHz ++ * cntFreq = 100MHz ++ * ++ * We compute the CPU frequency, based on PLL settings. ++ */ ++ ++ clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1); ++ preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift; ++ preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect]; ++ multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift; ++ ++ if (clockCtl1 & doubler_mask) { ++ multiplier = multiplier << 1; ++ } ++ return (40000000 / preDivisor) * multiplier; ++} ++ ++static inline int ++ar5312_sys_frequency(void) ++{ ++ return ar5312_cpu_frequency() / 4; ++} ++ ++void __init ++ar5312_time_init(void) ++{ ++ if (!is_5312()) ++ return; ++ ++ mips_hpt_frequency = ar5312_cpu_frequency() / 2; ++} ++ ++ ++void __init ++ar5312_prom_init(void) ++{ ++ u32 memsize, memcfg, bank0AC, bank1AC; ++ u32 devid; ++ ++ if (!is_5312()) ++ return; ++ ++ /* Detect memory size */ ++ memcfg = ar231x_read_reg(AR531X_MEM_CFG1); ++ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S; ++ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S; ++ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) ++ + (bank1AC ? (1 << (bank1AC+1)) : 0); ++ memsize <<= 20; ++ add_memory_region(0, memsize, BOOT_MEM_RAM); ++ ++ devid = ar231x_read_reg(AR531X_REV); ++ devid >>= AR531X_REV_WMAC_MIN_S; ++ devid &= AR531X_REV_CHIP; ++ ar231x_board.devid = (u16) devid; ++ ar231x_gpiodev = &ar5312_gpiodev; ++} ++ ++void __init ++ar5312_plat_setup(void) ++{ ++ if (!is_5312()) ++ return; ++ ++ /* Clear any lingering AHB errors */ ++ ar231x_read_reg(AR531X_PROCADDR); ++ ar231x_read_reg(AR531X_DMAADDR); ++ ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION); ++ ++ _machine_restart = ar5312_restart; ++ ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency()); ++} ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,38 @@ ++#ifndef __AR5312_H ++#define __AR5312_H ++ ++#ifdef CONFIG_ATHEROS_AR5312 ++ ++extern void ar5312_irq_init(void); ++extern int ar5312_init_devices(void); ++extern void ar5312_prom_init(void); ++extern void ar5312_plat_setup(void); ++extern void ar5312_time_init(void); ++extern void ar5312_time_init(void); ++ ++#else ++ ++static inline void ar5312_irq_init(void) ++{ ++} ++ ++static inline int ar5312_init_devices(void) ++{ ++ return 0; ++} ++ ++static inline void ar5312_prom_init(void) ++{ ++} ++ ++static inline void ar5312_plat_setup(void) ++{ ++} ++ ++static inline void ar5312_time_init(void) ++{ ++} ++ ++#endif ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c linux-2.6.39-rc7/arch/mips/ar231x/board.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/board.c 2011-05-15 22:16:11.000000000 +0200 +@@ -0,0 +1,261 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "devices.h" ++#include "ar5312.h" ++#include "ar2315.h" ++ ++void (*ar231x_irq_dispatch)(void); ++ ++static inline bool ++check_radio_magic(u8 *addr) ++{ ++ addr += 0x7a; /* offset for flash magic */ ++ if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) { ++ return 1; ++ } ++ return 0; ++} ++ ++static inline bool ++check_board_data(u8 *flash_limit, u8 *addr, bool broken) ++{ ++ /* config magic found */ ++ if (*((u32 *)addr) == AR531X_BD_MAGIC) ++ return 1; ++ ++ if (!broken) ++ return 0; ++ ++ if (check_radio_magic(addr + 0xf8)) ++ ar231x_board.radio = addr + 0xf8; ++ if ((addr < flash_limit + 0x10000) && ++ check_radio_magic(addr + 0x10000)) ++ ar231x_board.radio = addr + 0x10000; ++ ++ if (ar231x_board.radio) { ++ /* broken board data detected, use radio data to find the offset, ++ * user will fix this */ ++ return 1; ++ } ++ return 0; ++} ++ ++static u8 * ++find_board_config(u8 *flash_limit, bool broken) ++{ ++ u8 *addr; ++ int found = 0; ++ ++ for (addr = flash_limit - 0x1000; ++ addr >= flash_limit - 0x30000; ++ addr -= 0x1000) { ++ ++ if (check_board_data(flash_limit, addr, broken)) { ++ found = 1; ++ break; ++ } ++ } ++ ++ if (!found) ++ addr = NULL; ++ ++ return addr; ++} ++ ++static u8 * ++find_radio_config(u8 *flash_limit, u8 *board_config) ++{ ++ int found; ++ u8 *radio_config; ++ ++ /* ++ * Now find the start of Radio Configuration data, using heuristics: ++ * Search forward from Board Configuration data by 0x1000 bytes ++ * at a time until we find non-0xffffffff. ++ */ ++ found = 0; ++ for (radio_config = board_config + 0x1000; ++ (radio_config < flash_limit); ++ radio_config += 0x1000) { ++ if ((*(u32 *)radio_config != 0xffffffff) && ++ check_radio_magic(radio_config)) { ++ found = 1; ++ break; ++ } ++ } ++ ++ /* AR2316 relocates radio config to new location */ ++ if (!found) { ++ for (radio_config = board_config + 0xf8; ++ (radio_config < flash_limit - 0x1000 + 0xf8); ++ radio_config += 0x1000) { ++ if ((*(u32 *)radio_config != 0xffffffff) && ++ check_radio_magic(radio_config)) { ++ found = 1; ++ break; ++ } ++ } ++ } ++ ++ if (!found) { ++ printk("Could not find Radio Configuration data\n"); ++ radio_config = 0; ++ } ++ ++ return (u8 *) radio_config; ++} ++ ++int __init ++ar231x_find_config(u8 *flash_limit) ++{ ++ struct ar231x_boarddata *config; ++ unsigned int rcfg_size; ++ int broken_boarddata = 0, i, tmp; ++ u8 *bcfg, *rcfg; ++ u8 *board_data; ++ u8 *radio_data; ++ u32 offset; ++ ++ ar231x_board.config = NULL; ++ ar231x_board.radio = NULL; ++ /* Copy the board and radio data to RAM, because accessing the mapped ++ * memory of the flash directly after booting is not safe */ ++ ++ /* Try to find valid board and radio data */ ++ bcfg = find_board_config(flash_limit, false); ++ ++ /* If that fails, try to at least find valid radio data */ ++ if (!bcfg) { ++ bcfg = find_board_config(flash_limit, true); ++ broken_boarddata = 1; ++ } ++ ++ if (!bcfg) { ++ printk(KERN_WARNING "WARNING: No board configuration data found!\n"); ++ return -ENODEV; ++ } ++ ++ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL); ++ ar231x_board.config = (struct ar231x_boarddata *) board_data; ++ memcpy(board_data, bcfg, 0x100); ++ if (broken_boarddata) { ++ printk(KERN_WARNING "WARNING: broken board data detected\n"); ++ config = ar231x_board.config; ++ if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) { ++ printk(KERN_INFO "Fixing up empty mac addresses\n"); ++ config->resetConfigGpio = 0xffff; ++ config->sysLedGpio = 0xffff; ++ random_ether_addr(config->wlan0_mac); ++ config->wlan0_mac[0] &= ~0x06; ++ random_ether_addr(config->enet0_mac); ++ random_ether_addr(config->enet1_mac); ++ } ++ } ++ ++ ++ /* Radio config starts 0x100 bytes after board config, regardless ++ * of what the physical layout on the flash chip looks like */ ++ ++ if (ar231x_board.radio) ++ rcfg = (u8 *) ar231x_board.radio; ++ else ++ rcfg = find_radio_config(flash_limit, bcfg); ++ ++ if (!rcfg) ++ return -ENODEV; ++ ++ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff); ++ ar231x_board.radio = radio_data; ++ offset = radio_data - board_data; ++ printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset); ++ rcfg_size = BOARD_CONFIG_BUFSZ - offset; ++ memcpy(radio_data, rcfg, rcfg_size); ++ ++ for (tmp = 0xff, i = 0; i < ETH_ALEN; i++) ++ tmp &= radio_data[i + 0x1d * 2]; ++ if (tmp == 0xff) { ++ u16 *eep = (u16 *)radio_data, *bcfgs = (u16 *)bcfg; ++ printk(KERN_INFO "Radio MAC is blank; using board-data\n"); ++ eep[0x1f] = bcfgs[0x30]; ++ eep[0x1e] = bcfgs[0x34]; ++ eep[0x1d] = bcfgs[0x32]; ++ } ++ ++ return 0; ++} ++ ++static void ++ar231x_halt(void) ++{ ++ local_irq_disable(); ++ while (1); ++} ++ ++void __init ++plat_mem_setup(void) ++{ ++ _machine_halt = ar231x_halt; ++ pm_power_off = ar231x_halt; ++ ++ ar5312_plat_setup(); ++ ar2315_plat_setup(); ++ ++ /* Disable data watchpoints */ ++ write_c0_watchlo0(0); ++} ++ ++ ++asmlinkage void ++plat_irq_dispatch(void) ++{ ++ ar231x_irq_dispatch(); ++} ++ ++void __init ++plat_time_init(void) ++{ ++ ar5312_time_init(); ++ ar2315_time_init(); ++} ++ ++unsigned int __cpuinit ++get_c0_compare_int(void) ++{ ++ return CP0_LEGACY_COMPARE_IRQ; ++} ++ ++void __init ++arch_init_irq(void) ++{ ++ clear_c0_status(ST0_IM); ++ mips_cpu_irq_init(); ++ ++ /* Initialize interrupt controllers */ ++ ar5312_irq_init(); ++ ar2315_irq_init(); ++} ++ ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c linux-2.6.39-rc7/arch/mips/ar231x/devices.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/devices.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,175 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "devices.h" ++#include "ar5312.h" ++#include "ar2315.h" ++ ++struct ar231x_board_config ar231x_board; ++int ar231x_devtype = DEV_TYPE_UNKNOWN; ++const struct ar231x_gpiodev *ar231x_gpiodev; ++EXPORT_SYMBOL(ar231x_gpiodev); ++ ++static struct resource ar231x_eth0_res[] = { ++ { ++ .name = "eth0_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "eth0_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct resource ar231x_eth1_res[] = { ++ { ++ .name = "eth1_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "eth1_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device ar231x_eth[] = { ++ { ++ .id = 0, ++ .name = "ar231x-eth", ++ .resource = ar231x_eth0_res, ++ .num_resources = ARRAY_SIZE(ar231x_eth0_res) ++ }, ++ { ++ .id = 1, ++ .name = "ar231x-eth", ++ .resource = ar231x_eth1_res, ++ .num_resources = ARRAY_SIZE(ar231x_eth1_res) ++ } ++}; ++ ++static struct resource ar231x_wmac0_res[] = { ++ { ++ .name = "wmac0_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "wmac0_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct resource ar231x_wmac1_res[] = { ++ { ++ .name = "wmac1_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "wmac1_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++ ++static struct platform_device ar231x_wmac[] = { ++ { ++ .id = 0, ++ .name = "ar231x-wmac", ++ .resource = ar231x_wmac0_res, ++ .num_resources = ARRAY_SIZE(ar231x_wmac0_res), ++ .dev.platform_data = &ar231x_board, ++ }, ++ { ++ .id = 1, ++ .name = "ar231x-wmac", ++ .resource = ar231x_wmac1_res, ++ .num_resources = ARRAY_SIZE(ar231x_wmac1_res), ++ .dev.platform_data = &ar231x_board, ++ }, ++}; ++ ++static const char *devtype_strings[] = { ++ [DEV_TYPE_AR5312] = "Atheros AR5312", ++ [DEV_TYPE_AR2312] = "Atheros AR2312", ++ [DEV_TYPE_AR2313] = "Atheros AR2313", ++ [DEV_TYPE_AR2315] = "Atheros AR2315", ++ [DEV_TYPE_AR2316] = "Atheros AR2316", ++ [DEV_TYPE_AR2317] = "Atheros AR2317", ++ [DEV_TYPE_UNKNOWN] = "Atheros (unknown)", ++}; ++ ++const char *get_system_type(void) ++{ ++ if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) || ++ !devtype_strings[ar231x_devtype]) ++ return devtype_strings[DEV_TYPE_UNKNOWN]; ++ return devtype_strings[ar231x_devtype]; ++} ++ ++ ++int __init ++ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata) ++{ ++ struct resource *res; ++ ++ ar231x_eth[nr].dev.platform_data = pdata; ++ res = &ar231x_eth[nr].resource[0]; ++ res->start = base; ++ res->end = base + 0x2000 - 1; ++ res++; ++ res->start = irq; ++ res->end = irq; ++ return platform_device_register(&ar231x_eth[nr]); ++} ++ ++void __init ++ar231x_serial_setup(u32 mapbase, unsigned int uartclk) ++{ ++ struct uart_port s; ++ ++ memset(&s, 0, sizeof(s)); ++ ++ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; ++ s.iotype = UPIO_MEM; ++ s.irq = AR531X_MISC_IRQ_UART0; ++ s.regshift = 2; ++ s.mapbase = mapbase; ++ s.uartclk = uartclk; ++ s.membase = (void __iomem *)s.mapbase; ++ ++ early_serial_setup(&s); ++} ++ ++int __init ++ar231x_add_wmac(int nr, u32 base, int irq) ++{ ++ struct resource *res; ++ ++ ar231x_wmac[nr].dev.platform_data = &ar231x_board; ++ res = &ar231x_wmac[nr].resource[0]; ++ res->start = base; ++ res->end = base + 0x10000 - 1; ++ res++; ++ res->start = irq; ++ res->end = irq; ++ return platform_device_register(&ar231x_wmac[nr]); ++} ++ ++static int __init ar231x_register_devices(void) ++{ ++ static struct resource res = { ++ .start = 0xFFFFFFFF, ++ }; ++ ++ platform_device_register_simple("GPIODEV", 0, &res, 1); ++ ar5312_init_devices(); ++ ar2315_init_devices(); ++ ++ return 0; ++} ++ ++device_initcall(ar231x_register_devices); +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h linux-2.6.39-rc7/arch/mips/ar231x/devices.h +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/devices.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,37 @@ ++#ifndef __AR231X_DEVICES_H ++#define __AR231X_DEVICES_H ++ ++enum { ++ /* handled by ar5312.c */ ++ DEV_TYPE_AR2312, ++ DEV_TYPE_AR2313, ++ DEV_TYPE_AR5312, ++ ++ /* handled by ar2315.c */ ++ DEV_TYPE_AR2315, ++ DEV_TYPE_AR2316, ++ DEV_TYPE_AR2317, ++ ++ DEV_TYPE_UNKNOWN ++}; ++ ++extern int ar231x_devtype; ++extern struct ar231x_board_config ar231x_board; ++extern asmlinkage void (*ar231x_irq_dispatch)(void); ++ ++extern int ar231x_find_config(u8 *flash_limit); ++extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk); ++extern int ar231x_add_wmac(int nr, u32 base, int irq); ++extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata); ++ ++static inline bool is_2315(void) ++{ ++ return (current_cpu_data.cputype == CPU_4KEC); ++} ++ ++static inline bool is_5312(void) ++{ ++ return !is_2315(); ++} ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "devices.h" ++ ++static inline void prom_uart_wr(void __iomem *base, unsigned reg, ++ unsigned char ch) ++{ ++ __raw_writeb(ch, base + 4 * reg); ++} ++ ++static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) ++{ ++ return __raw_readb(base + 4 * reg); ++} ++ ++void prom_putchar(unsigned char ch) ++{ ++ static void __iomem *base; ++ ++ if (unlikely(base == NULL)) { ++ if (is_2315()) ++ base = (void __iomem *)(KSEG1ADDR(AR2315_UART0)); ++ else ++ base = (void __iomem *)(KSEG1ADDR(AR531X_UART0)); ++ } ++ ++ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); ++ prom_uart_wr(base, UART_TX, ch); ++ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); ++} ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c linux-2.6.39-rc7/arch/mips/ar231x/pci.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/pci.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,230 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "devices.h" ++ ++#define AR531X_MEM_BASE 0x80800000UL ++#define AR531X_MEM_SIZE 0x00ffffffUL ++#define AR531X_IO_SIZE 0x00007fffUL ++ ++static unsigned long configspace; ++ ++static int config_access(int devfn, int where, int size, u32 *ptr, bool write) ++{ ++ unsigned long flags; ++ int func = PCI_FUNC(devfn); ++ int dev = PCI_SLOT(devfn); ++ u32 value = 0; ++ int err = 0; ++ u32 addr; ++ ++ if (((dev != 0) && (dev != 3)) || (func > 2)) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ /* Select Configuration access */ ++ local_irq_save(flags); ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL); ++ mb(); ++ ++ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where; ++ if (size == 1) ++ addr ^= 0x3; ++ else if (size == 2) ++ addr ^= 0x2; ++ ++ if (write) { ++ value = *ptr; ++ if (size == 1) ++ err = put_dbe(value, (u8 *) addr); ++ else if (size == 2) ++ err = put_dbe(value, (u16 *) addr); ++ else if (size == 4) ++ err = put_dbe(value, (u32 *) addr); ++ } else { ++ if (size == 1) ++ err = get_dbe(value, (u8 *) addr); ++ else if (size == 2) ++ err = get_dbe(value, (u16 *) addr); ++ else if (size == 4) ++ err = get_dbe(value, (u32 *) addr); ++ if (err) ++ *ptr = 0xffffffff; ++ else ++ *ptr = value; ++ } ++ ++ /* Select Memory access */ ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0); ++ local_irq_restore(flags); ++ ++ return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL); ++} ++ ++static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value) ++{ ++ return config_access(devfn, where, size, value, 0); ++} ++ ++static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) ++{ ++ return config_access(devfn, where, size, &value, 1); ++} ++ ++struct pci_ops ar231x_pci_ops = { ++ .read = ar231x_pci_read, ++ .write = ar231x_pci_write, ++}; ++ ++static struct resource ar231x_mem_resource = { ++ .name = "AR531x PCI MEM", ++ .start = AR531X_MEM_BASE, ++ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct resource ar231x_io_resource = { ++ .name = "AR531x PCI I/O", ++ .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE, ++ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1, ++ .flags = IORESOURCE_IO, ++}; ++ ++struct pci_controller ar231x_pci_controller = { ++ .pci_ops = &ar231x_pci_ops, ++ .mem_resource = &ar231x_mem_resource, ++ .io_resource = &ar231x_io_resource, ++ .mem_offset = 0x00000000UL, ++ .io_offset = 0x00000000UL, ++}; ++ ++int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ return AR2315_IRQ_LCBUS_PCI; ++} ++ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5); ++ pci_write_config_word(dev, 0x40, 0); ++ ++ /* Clear any pending Abort or external Interrupts ++ * and enable interrupt processing */ ++ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0); ++ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); ++ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); ++ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE); ++ ++ return 0; ++} ++ ++static void ++ar2315_pci_fixup(struct pci_dev *dev) ++{ ++ unsigned int devfn = dev->devfn; ++ ++ if (dev->bus->number != 0) ++ return; ++ ++ /* Only fix up the PCI host settings */ ++ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0)) ++ return; ++ ++ /* Fix up MBARs */ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2); ++ pci_write_config_dword(dev, PCI_COMMAND, ++ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | ++ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | ++ PCI_COMMAND_FAST_BACK); ++} ++DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup); ++ ++static int __init ++ar2315_pci_init(void) ++{ ++ u32 reg; ++ ++ if (ar231x_devtype != DEV_TYPE_AR2315) ++ return -ENODEV; ++ ++ configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */ ++ ar231x_pci_controller.io_map_base = ++ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE); ++ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */ ++ ++ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA); ++ msleep(10); ++ ++ reg &= ~AR2315_RESET_PCIDMA; ++ ar231x_write_reg(AR2315_RESET, reg); ++ msleep(10); ++ ++ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0, ++ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE); ++ ++ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | ++ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S)); ++ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); ++ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK, ++ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | ++ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT)); ++ ++ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */ ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, ++ AR2315_PCIRST_LOW); ++ msleep(100); ++ ++ /* Bring the PCI out of reset */ ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, ++ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8); ++ ++ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG, ++ 0x1E | /* 1GB uncached */ ++ (1 << 5) | /* Enable uncached */ ++ (0x2 << 30) /* Base: 0x80000000 */ ++ ); ++ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG); ++ ++ msleep(500); ++ ++ /* dirty hack - anyone with a datasheet that knows the memory map ? */ ++ ioport_resource.start = 0x10000000; ++ ioport_resource.end = 0xffffffff; ++ iomem_resource.start = 0x10000000; ++ iomem_resource.end = 0xffffffff; ++ ++ register_pci_controller(&ar231x_pci_controller); ++ ++ return 0; ++} ++ ++arch_initcall(ar2315_pci_init); +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c linux-2.6.39-rc7/arch/mips/ar231x/prom.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/prom.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,37 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright MontaVista Software Inc ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++/* ++ * Prom setup file for ar531x ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "ar5312.h" ++#include "ar2315.h" ++ ++void __init prom_init(void) ++{ ++ ar5312_prom_init(); ++ ar2315_prom_init(); ++} ++ ++void __init prom_free_prom_memory(void) ++{ ++} +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c linux-2.6.39-rc7/arch/mips/ar231x/reset.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/reset.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,161 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "devices.h" ++ ++#define AR531X_RESET_GPIO_IRQ (AR531X_GPIO_IRQ(ar231x_board.config->resetConfigGpio)) ++ ++struct event_t { ++ struct work_struct wq; ++ int set; ++ unsigned long jiffies; ++}; ++ ++static struct timer_list rst_button_timer; ++static unsigned long seen; ++ ++struct sock *uevent_sock = NULL; ++EXPORT_SYMBOL_GPL(uevent_sock); ++extern u64 uevent_next_seqnum(void); ++ ++static int no_release_workaround = 1; ++module_param(no_release_workaround, int, 0); ++ ++static inline void ++add_msg(struct sk_buff *skb, char *msg) ++{ ++ char *scratch; ++ scratch = skb_put(skb, strlen(msg) + 1); ++ sprintf(scratch, msg); ++} ++ ++static void ++hotplug_button(struct work_struct *wq) ++{ ++ struct sk_buff *skb; ++ struct event_t *event; ++ size_t len; ++ char *scratch, *s; ++ char buf[128]; ++ ++ event = container_of(wq, struct event_t, wq); ++ if (!uevent_sock) ++ goto done; ++ ++ /* allocate message with the maximum possible size */ ++ s = event->set ? "pressed" : "released"; ++ len = strlen(s) + 2; ++ skb = alloc_skb(NLMSG_GOODSIZE, GFP_KERNEL); ++ if (!skb) ++ goto done; ++ ++ /* add header */ ++ scratch = skb_put(skb, len); ++ sprintf(scratch, "%s@",s); ++ ++ /* copy keys to our continuous event payload buffer */ ++ add_msg(skb, "HOME=/"); ++ add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin"); ++ add_msg(skb, "SUBSYSTEM=button"); ++ add_msg(skb, "BUTTON=reset"); ++ add_msg(skb, (event->set ? "ACTION=pressed" : "ACTION=released")); ++ sprintf(buf, "SEEN=%ld", (event->jiffies - seen)/HZ); ++ add_msg(skb, buf); ++ snprintf(buf, 128, "SEQNUM=%llu", uevent_next_seqnum()); ++ add_msg(skb, buf); ++ ++ NETLINK_CB(skb).dst_group = 1; ++ netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL); ++ ++done: ++ kfree(event); ++} ++ ++static void ++reset_button_poll(unsigned long unused) ++{ ++ struct event_t *event; ++ int gpio = ~0; ++ ++ if(!no_release_workaround) ++ return; ++ ++ gpio = ar231x_gpiodev->get(); ++ gpio &= (1 << (AR531X_RESET_GPIO_IRQ - AR531X_GPIO_IRQ_BASE)); ++ if(gpio) { ++ rst_button_timer.expires = jiffies + (HZ / 4); ++ add_timer(&rst_button_timer); ++ return; ++ } ++ ++ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); ++ if (!event) ++ return; ++ ++ event->set = 0; ++ event->jiffies = jiffies; ++ INIT_WORK(&event->wq, hotplug_button); ++ schedule_work(&event->wq); ++} ++ ++static irqreturn_t ++button_handler(int irq, void *dev_id) ++{ ++ static int pressed = 0; ++ struct event_t *event; ++ u32 gpio = ~0; ++ ++ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); ++ if (!event) ++ return IRQ_NONE; ++ ++ pressed = !pressed; ++ ++ gpio = ar231x_gpiodev->get() & (1 << (irq - AR531X_GPIO_IRQ_BASE)); ++ ++ event->set = gpio; ++ if(!event->set) ++ no_release_workaround = 0; ++ ++ event->jiffies = jiffies; ++ ++ INIT_WORK(&event->wq, hotplug_button); ++ schedule_work(&event->wq); ++ ++ seen = jiffies; ++ if(event->set && no_release_workaround) ++ mod_timer(&rst_button_timer, jiffies + (HZ / 4)); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++static int __init ++ar231x_init_reset(void) ++{ ++ seen = jiffies; ++ ++ if (ar231x_board.config->resetConfigGpio == 0xffff) ++ return -ENODEV; ++ ++ init_timer(&rst_button_timer); ++ rst_button_timer.function = reset_button_poll; ++ rst_button_timer.expires = jiffies + HZ / 50; ++ add_timer(&rst_button_timer); ++ ++ request_irq(AR531X_RESET_GPIO_IRQ, &button_handler, IRQF_SAMPLE_RANDOM, "ar231x_reset", NULL); ++ ++ return 0; ++} ++ ++module_init(ar231x_init_reset); +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 2011-05-15 21:44:12.000000000 +0200 +@@ -0,0 +1,580 @@ ++/* ++ * Register definitions for AR2315+ ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2008 Felix Fietkau ++ */ ++ ++#ifndef __AR2315_REG_H ++#define __AR2315_REG_H ++ ++/* ++ * IRQs ++ */ ++#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ ++#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ ++#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ ++#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ ++#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ ++ ++/* ++ * Address map ++ */ ++#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */ ++#define AR2315_WLAN0 0x10000000 /* Wireless MMR */ ++#define AR2315_PCI 0x10100000 /* PCI MMR */ ++#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */ ++#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */ ++#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */ ++#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */ ++#define AR2315_UART0 0x11100003 /* UART MMR */ ++#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */ ++#define AR2315_PCIEXT 0x80000000 /* pci external */ ++ ++/* ++ * Reset Register ++ */ ++#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000) ++ ++#define AR2315_RESET_COLD_AHB 0x00000001 ++#define AR2315_RESET_COLD_APB 0x00000002 ++#define AR2315_RESET_COLD_CPU 0x00000004 ++#define AR2315_RESET_COLD_CPUWARM 0x00000008 ++#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */ ++#define AR2317_RESET_SYSTEM 0x00000010 ++ ++ ++#define AR2315_RESET (AR2315_DSLBASE + 0x0004) ++ ++#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */ ++#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */ ++#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */ ++#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */ ++#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */ ++#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */ ++#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */ ++#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */ ++#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */ ++#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */ ++#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */ ++#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */ ++ ++/* ++ * AHB master arbitration control ++ */ ++#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008) ++ ++#define AR2315_ARB_CPU 0x00000001 /* CPU, default */ ++#define AR2315_ARB_WLAN 0x00000002 /* WLAN */ ++#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ ++#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */ ++#define AR2315_ARB_PCI 0x00000010 /* PCI */ ++#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */ ++#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */ ++ ++/* ++ * Config Register ++ */ ++#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c) ++ ++#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */ ++#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ ++#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */ ++#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */ ++#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */ ++#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */ ++#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */ ++ ++#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */ ++#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */ ++#define AR2315_CONFIG_PCIAHB 0x00000800 ++#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000 ++#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */ ++#define AR2315_CONFIG_CPU_DRAM 0x00010000 ++#define AR2315_CONFIG_CPU_PCI 0x00020000 ++#define AR2315_CONFIG_CPU_MMR 0x00040000 ++#define AR2315_CONFIG_BIG 0x00000400 ++ ++ ++/* ++ * NMI control ++ */ ++#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010) ++ ++#define AR2315_NMI_EN 1 ++ ++/* ++ * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0). ++ */ ++#define AR2315_SREV (AR2315_DSLBASE + 0x0014) ++ ++#define AR2315_REV_MAJ 0x00f0 ++#define AR2315_REV_MAJ_S 4 ++#define AR2315_REV_MIN 0x000f ++#define AR2315_REV_MIN_S 0 ++#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN) ++ ++/* ++ * Interface Enable ++ */ ++#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018) ++ ++#define AR2315_IF_MASK 0x00000007 ++#define AR2315_IF_DISABLED 0 ++#define AR2315_IF_PCI 1 ++#define AR2315_IF_TS_LOCAL 2 ++#define AR2315_IF_ALL 3 /* only for emulation with separate pins */ ++#define AR2315_IF_LOCAL_HOST 0x00000008 ++#define AR2315_IF_PCI_HOST 0x00000010 ++#define AR2315_IF_PCI_INTR 0x00000020 ++#define AR2315_IF_PCI_CLK_MASK 0x00030000 ++#define AR2315_IF_PCI_CLK_INPUT 0 ++#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1 ++#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2 ++#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3 ++#define AR2315_IF_PCI_CLK_SHIFT 16 ++ ++/* ++ * APB Interrupt control ++ */ ++ ++#define AR2315_ISR (AR2315_DSLBASE + 0x0020) ++#define AR2315_IMR (AR2315_DSLBASE + 0x0024) ++#define AR2315_GISR (AR2315_DSLBASE + 0x0028) ++ ++#define AR2315_ISR_UART0 0x0001 /* high speed UART */ ++#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */ ++#define AR2315_ISR_SPI 0x0004 /* SPI bus */ ++#define AR2315_ISR_AHB 0x0008 /* AHB error */ ++#define AR2315_ISR_APB 0x0010 /* APB error */ ++#define AR2315_ISR_TIMER 0x0020 /* timer */ ++#define AR2315_ISR_GPIO 0x0040 /* GPIO */ ++#define AR2315_ISR_WD 0x0080 /* watchdog */ ++#define AR2315_ISR_IR_RSVD 0x0100 /* IR */ ++ ++#define AR2315_GISR_MISC 0x0001 ++#define AR2315_GISR_WLAN0 0x0002 ++#define AR2315_GISR_MPEGTS_RSVD 0x0004 ++#define AR2315_GISR_LOCALPCI 0x0008 ++#define AR2315_GISR_WMACPOLL 0x0010 ++#define AR2315_GISR_TIMER 0x0020 ++#define AR2315_GISR_ETHERNET 0x0040 ++ ++/* ++ * Interrupt routing from IO to the processor IP bits ++ * Define our inter mask and level ++ */ ++#define AR2315_INTR_MISCIO SR_IBIT3 ++#define AR2315_INTR_WLAN0 SR_IBIT4 ++#define AR2315_INTR_ENET0 SR_IBIT5 ++#define AR2315_INTR_LOCALPCI SR_IBIT6 ++#define AR2315_INTR_WMACPOLL SR_IBIT7 ++#define AR2315_INTR_COMPARE SR_IBIT8 ++ ++/* ++ * Timers ++ */ ++#define AR2315_TIMER (AR2315_DSLBASE + 0x0030) ++#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034) ++#define AR2315_WD (AR2315_DSLBASE + 0x0038) ++#define AR2315_WDC (AR2315_DSLBASE + 0x003c) ++ ++#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000 ++#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */ ++#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */ ++ ++/* ++ * CPU Performance Counters ++ */ ++#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048) ++#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c) ++ ++#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */ ++#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */ ++#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */ ++#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */ ++#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */ ++#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */ ++#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */ ++ ++#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */ ++#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */ ++#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */ ++#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */ ++#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */ ++#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */ ++#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */ ++ ++/* ++ * AHB Error Reporting. ++ */ ++#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */ ++#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */ ++#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */ ++#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */ ++#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */ ++ ++#define AHB_ERROR_DET 1 /* AHB Error has been detected, */ ++ /* write 1 to clear all bits in ERR0 */ ++#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */ ++#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */ ++ ++#define AR2315_PROCERR_HMAST 0x0000000f ++#define AR2315_PROCERR_HMAST_DFLT 0 ++#define AR2315_PROCERR_HMAST_WMAC 1 ++#define AR2315_PROCERR_HMAST_ENET 2 ++#define AR2315_PROCERR_HMAST_PCIENDPT 3 ++#define AR2315_PROCERR_HMAST_LOCAL 4 ++#define AR2315_PROCERR_HMAST_CPU 5 ++#define AR2315_PROCERR_HMAST_PCITGT 6 ++ ++#define AR2315_PROCERR_HMAST_S 0 ++#define AR2315_PROCERR_HWRITE 0x00000010 ++#define AR2315_PROCERR_HSIZE 0x00000060 ++#define AR2315_PROCERR_HSIZE_S 5 ++#define AR2315_PROCERR_HTRANS 0x00000180 ++#define AR2315_PROCERR_HTRANS_S 7 ++#define AR2315_PROCERR_HBURST 0x00000e00 ++#define AR2315_PROCERR_HBURST_S 9 ++ ++/* ++ * Clock Control ++ */ ++#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064) ++#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068) ++#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c) ++#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070) ++#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074) ++#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080) ++#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084) ++ ++/* PLLc Control fields */ ++#define PLLC_REF_DIV_M 0x00000003 ++#define PLLC_REF_DIV_S 0 ++#define PLLC_FDBACK_DIV_M 0x0000007C ++#define PLLC_FDBACK_DIV_S 2 ++#define PLLC_ADD_FDBACK_DIV_M 0x00000080 ++#define PLLC_ADD_FDBACK_DIV_S 7 ++#define PLLC_CLKC_DIV_M 0x0001c000 ++#define PLLC_CLKC_DIV_S 14 ++#define PLLC_CLKM_DIV_M 0x00700000 ++#define PLLC_CLKM_DIV_S 20 ++ ++/* CPU CLK Control fields */ ++#define CPUCLK_CLK_SEL_M 0x00000003 ++#define CPUCLK_CLK_SEL_S 0 ++#define CPUCLK_CLK_DIV_M 0x0000000c ++#define CPUCLK_CLK_DIV_S 2 ++ ++/* AMBA CLK Control fields */ ++#define AMBACLK_CLK_SEL_M 0x00000003 ++#define AMBACLK_CLK_SEL_S 0 ++#define AMBACLK_CLK_DIV_M 0x0000000c ++#define AMBACLK_CLK_DIV_S 2 ++ ++/* ++ * GPIO ++ */ ++#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088) ++#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090) ++#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098) ++#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0) ++ ++#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ ++#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */ ++#define AR2315_GPIO_CR_I(x) (0) /* input */ ++ ++#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */ ++#define AR2315_GPIO_INT_M (0x3F) /* mask for int */ ++#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */ ++#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */ ++ ++#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */ ++#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */ ++#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */ ++#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */ ++#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */ ++ ++#define AR2315_RESET_GPIO 5 ++#define AR2315_NUM_GPIO 22 ++ ++/* ++ * PCI Clock Control ++ */ ++#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4) ++ ++#define AR2315_PCICLK_INPUT_M 0x3 ++#define AR2315_PCICLK_INPUT_S 0 ++ ++#define AR2315_PCICLK_PLLC_CLKM 0 ++#define AR2315_PCICLK_PLLC_CLKM1 1 ++#define AR2315_PCICLK_PLLC_CLKC 2 ++#define AR2315_PCICLK_REF_CLK 3 ++ ++#define AR2315_PCICLK_DIV_M 0xc ++#define AR2315_PCICLK_DIV_S 2 ++ ++#define AR2315_PCICLK_IN_FREQ 0 ++#define AR2315_PCICLK_IN_FREQ_DIV_6 1 ++#define AR2315_PCICLK_IN_FREQ_DIV_8 2 ++#define AR2315_PCICLK_IN_FREQ_DIV_10 3 ++ ++/* ++ * Observation Control Register ++ */ ++#define AR2315_OCR (AR2315_DSLBASE + 0x00b0) ++#define OCR_GPIO0_IRIN 0x0040 ++#define OCR_GPIO1_IROUT 0x0080 ++#define OCR_GPIO3_RXCLR 0x0200 ++ ++/* ++ * General Clock Control ++ */ ++ ++#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4) ++#define MISCCLK_PLLBYPASS_EN 0x00000001 ++#define MISCCLK_PROCREFCLK 0x00000002 ++ ++/* ++ * SDRAM Controller ++ * - No read or write buffers are included. ++ */ ++#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00) ++#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c) ++#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10) ++ ++#define SDRAM_DATA_WIDTH_M 0x00006000 ++#define SDRAM_DATA_WIDTH_S 13 ++ ++#define SDRAM_COL_WIDTH_M 0x00001E00 ++#define SDRAM_COL_WIDTH_S 9 ++ ++#define SDRAM_ROW_WIDTH_M 0x000001E0 ++#define SDRAM_ROW_WIDTH_S 5 ++ ++#define SDRAM_BANKADDR_BITS_M 0x00000018 ++#define SDRAM_BANKADDR_BITS_S 3 ++ ++/* ++ * SPI Flash Interface Registers ++ */ ++ ++#define AR2315_SPI_CTL (AR2315_SPI + 0x00) ++#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04) ++#define AR2315_SPI_DATA (AR2315_SPI + 0x08) ++ ++#define SPI_CTL_START 0x00000100 ++#define SPI_CTL_BUSY 0x00010000 ++#define SPI_CTL_TXCNT_MASK 0x0000000f ++#define SPI_CTL_RXCNT_MASK 0x000000f0 ++#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff ++#define SPI_CTL_SIZE_MASK 0x00060000 ++ ++#define SPI_CTL_CLK_SEL_MASK 0x03000000 ++#define SPI_OPCODE_MASK 0x000000ff ++ ++/* ++ * PCI Bus Interface Registers ++ */ ++#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008) ++#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ ++ ++#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c) ++#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */ ++#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */ ++#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */ ++#define AR2315_PCIMISC_RST_MODE 0x00000030 ++#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */ ++#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */ ++#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */ ++#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */ ++#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */ ++#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */ ++#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */ ++#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */ ++ ++#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010) ++ ++#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014) ++ ++#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100) ++#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */ ++#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */ ++#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */ ++#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */ ++ ++#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104) ++#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */ ++#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */ ++#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */ ++#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */ ++ ++#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200) ++ ++#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400) ++#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */ ++ ++#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404) ++#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */ ++ ++#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408) ++ ++#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */ ++#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */ ++#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */ ++#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */ ++#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */ ++#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */ ++#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */ ++#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */ ++#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */ ++#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */ ++#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */ ++#define AR2315_PCI_EXT_INT 0x02000000 ++#define AR2315_PCI_ABORT_INT 0x04000000 ++ ++#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */ ++ ++#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508) ++#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */ ++#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */ ++ ++#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800) ++#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804) ++#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810) ++#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900) ++#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904) ++#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908) ++ ++ ++/* ++ * Local Bus Interface Registers ++ */ ++#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000) ++#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */ ++#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */ ++#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */ ++#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */ ++#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */ ++#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */ ++#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */ ++#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */ ++#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */ ++#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */ ++#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */ ++#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */ ++#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */ ++#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */ ++#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */ ++#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */ ++#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */ ++#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */ ++#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */ ++#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */ ++#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */ ++#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */ ++#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */ ++#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */ ++#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */ ++ ++#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004) ++#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */ ++ ++#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008) ++#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ ++ ++#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C) ++#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */ ++#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */ ++#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */ ++#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */ ++#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */ ++#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80 ++#define AR2315_LBM_TIMEOUT_SHFT 7 ++#define AR2315_LBM_PORTMUX 0x07000000 ++ ++ ++#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010) ++ ++#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100) ++#define AR2315_LB_TXEN_0 0x01 ++#define AR2315_LB_TXEN_1 0x02 ++#define AR2315_LB_TXEN_2 0x04 ++#define AR2315_LB_TXEN_3 0x08 ++ ++#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104) ++#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200) ++ ++#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400) ++#define AR2315_LB_RXEN 0x01 ++ ++#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404) ++#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408) ++ ++#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500) ++#define AR2315_INT_TX_DESC 0x0001 ++#define AR2315_INT_TX_OK 0x0002 ++#define AR2315_INT_TX_ERR 0x0004 ++#define AR2315_INT_TX_EOF 0x0008 ++#define AR2315_INT_RX_DESC 0x0010 ++#define AR2315_INT_RX_OK 0x0020 ++#define AR2315_INT_RX_ERR 0x0040 ++#define AR2315_INT_RX_EOF 0x0080 ++#define AR2315_INT_TX_TRUNC 0x0100 ++#define AR2315_INT_TX_STARVE 0x0200 ++#define AR2315_INT_LB_TIMEOUT 0x0400 ++#define AR2315_INT_LB_ERR 0x0800 ++#define AR2315_INT_MBOX_WR 0x1000 ++#define AR2315_INT_MBOX_RD 0x2000 ++ ++/* Bit definitions for INT MASK are the same as INT_STATUS */ ++#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504) ++ ++#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508) ++#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600) ++ ++/* ++ * IR Interface Registers ++ */ ++#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000) ++ ++#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */ ++ ++#define AR2315_IR_CONTROL (AR2315_IR + 0x0800) ++#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */ ++#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */ ++#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */ ++#define AR2315_IRCTL_SAMPLECLK_SHFT 1 ++#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */ ++#define AR2315_IRCTL_OUTPUTCLK_SHFT 14 ++ ++#define AR2315_IR_STATUS (AR2315_IR + 0x0804) ++#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */ ++#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */ ++ ++#define AR2315_IR_CONFIG (AR2315_IR + 0x0808) ++#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */ ++#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */ ++#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */ ++#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */ ++#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */ ++#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */ ++#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */ ++#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */ ++#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */ ++ ++#define HOST_PCI_DEV_ID 3 ++#define HOST_PCI_MBAR0 0x10000000 ++#define HOST_PCI_MBAR1 0x20000000 ++#define HOST_PCI_MBAR2 0x30000000 ++ ++#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1 ++#define PCI_DEVICE_MEM_SPACE 0x800000 ++ ++#endif /* __AR2315_REG_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,116 @@ ++/* ++ * SPI Flash Memory support header file. ++ * ++ * Copyright (c) 2005, Atheros Communications Inc. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * This code is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#ifndef __AR2315_SPIFLASH_H ++#define __AR2315_SPIFLASH_H ++ ++#define STM_PAGE_SIZE 256 ++ ++#define SFI_WRITE_BUFFER_SIZE 4 ++#define SFI_FLASH_ADDR_MASK 0x00ffffff ++ ++#define STM_8MBIT_SIGNATURE 0x13 ++#define STM_M25P80_BYTE_COUNT 1048576 ++#define STM_M25P80_SECTOR_COUNT 16 ++#define STM_M25P80_SECTOR_SIZE 0x10000 ++ ++#define STM_16MBIT_SIGNATURE 0x14 ++#define STM_M25P16_BYTE_COUNT 2097152 ++#define STM_M25P16_SECTOR_COUNT 32 ++#define STM_M25P16_SECTOR_SIZE 0x10000 ++ ++#define STM_32MBIT_SIGNATURE 0x15 ++#define STM_M25P32_BYTE_COUNT 4194304 ++#define STM_M25P32_SECTOR_COUNT 64 ++#define STM_M25P32_SECTOR_SIZE 0x10000 ++ ++#define STM_64MBIT_SIGNATURE 0x16 ++#define STM_M25P64_BYTE_COUNT 8388608 ++#define STM_M25P64_SECTOR_COUNT 128 ++#define STM_M25P64_SECTOR_SIZE 0x10000 ++ ++#define STM_128MBIT_SIGNATURE 0x17 ++#define STM_M25P128_BYTE_COUNT 16777216 ++#define STM_M25P128_SECTOR_COUNT 256 ++#define STM_M25P128_SECTOR_SIZE 0x10000 ++ ++#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT ++#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT ++#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE ++#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT ++#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT ++#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE ++#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT ++#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT ++#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE ++#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT ++#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT ++#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE ++#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT ++#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT ++#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE ++ ++/* ++ * ST Microelectronics Opcodes for Serial Flash ++ */ ++ ++#define STM_OP_WR_ENABLE 0x06 /* Write Enable */ ++#define STM_OP_WR_DISABLE 0x04 /* Write Disable */ ++#define STM_OP_RD_STATUS 0x05 /* Read Status */ ++#define STM_OP_WR_STATUS 0x01 /* Write Status */ ++#define STM_OP_RD_DATA 0x03 /* Read Data */ ++#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */ ++#define STM_OP_PAGE_PGRM 0x02 /* Page Program */ ++#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */ ++#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */ ++#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */ ++#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */ ++ ++#define STM_STATUS_WIP 0x01 /* Write-In-Progress */ ++#define STM_STATUS_WEL 0x02 /* Write Enable Latch */ ++#define STM_STATUS_BP0 0x04 /* Block Protect 0 */ ++#define STM_STATUS_BP1 0x08 /* Block Protect 1 */ ++#define STM_STATUS_BP2 0x10 /* Block Protect 2 */ ++#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */ ++ ++/* ++ * SPI Flash Interface Registers ++ */ ++#define AR531XPLUS_SPI_READ 0x08000000 ++#define AR531XPLUS_SPI_MMR 0x11300000 ++#define AR531XPLUS_SPI_MMR_SIZE 12 ++ ++#define AR531XPLUS_SPI_CTL 0x00 ++#define AR531XPLUS_SPI_OPCODE 0x04 ++#define AR531XPLUS_SPI_DATA 0x08 ++ ++#define SPI_FLASH_READ AR531XPLUS_SPI_READ ++#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR ++#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE ++#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL ++#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE ++#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA ++ ++#define SPI_CTL_START 0x00000100 ++#define SPI_CTL_BUSY 0x00010000 ++#define SPI_CTL_TXCNT_MASK 0x0000000f ++#define SPI_CTL_RXCNT_MASK 0x000000f0 ++#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff ++#define SPI_CTL_SIZE_MASK 0x00060000 ++ ++#define SPI_CTL_CLK_SEL_MASK 0x03000000 ++#define SPI_OPCODE_MASK 0x000000ff ++ ++#define SPI_STATUS_WIP STM_STATUS_WIP ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,54 @@ ++#ifndef __AR531X_H ++#define __AR531X_H ++ ++#define AR531X_MISC_IRQ_BASE 0x20 ++#define AR531X_GPIO_IRQ_BASE 0x30 ++ ++/* Software's idea of interrupts handled by "CPU Interrupt Controller" */ ++#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0 ++#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */ ++ ++/* Miscellaneous interrupts, which share IP6 */ ++#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0 ++#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1 ++#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2 ++#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3 ++#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4 ++#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5 ++#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6 ++#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7 ++#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8 ++#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9 ++#define AR531X_MISC_IRQ_COUNT 10 ++ ++/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */ ++#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0 ++#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n ++#define AR531X_GPIO_IRQ_COUNT 22 ++ ++static inline u32 ++ar231x_read_reg(u32 reg) ++{ ++ return __raw_readl((u32 *) KSEG1ADDR(reg)); ++} ++ ++static inline void ++ar231x_write_reg(u32 reg, u32 val) ++{ ++ __raw_writel(val, (u32 *) KSEG1ADDR(reg)); ++} ++ ++static inline u32 ++ar231x_mask_reg(u32 reg, u32 mask, u32 val) ++{ ++ u32 ret; ++ ++ ret = ar231x_read_reg(reg); ++ ret &= ~mask; ++ ret |= val; ++ ar231x_write_reg(reg, ret); ++ ++ return ret; ++} ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,83 @@ ++#ifndef __AR531X_PLATFORM_H ++#define __AR531X_PLATFORM_H ++ ++/* ++ * This is board-specific data that is stored in a "fixed" location in flash. ++ * It is shared across operating systems, so it should not be changed lightly. ++ * The main reason we need it is in order to extract the ethernet MAC ++ * address(es). ++ */ ++struct ar231x_boarddata { ++ u32 magic; /* board data is valid */ ++#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */ ++ u16 cksum; /* checksum (starting with BD_REV 2) */ ++ u16 rev; /* revision of this struct */ ++#define BD_REV 4 ++ char boardName[64]; /* Name of board */ ++ u16 major; /* Board major number */ ++ u16 minor; /* Board minor number */ ++ u32 flags; /* Board configuration */ ++#define BD_ENET0 0x00000001 /* ENET0 is stuffed */ ++#define BD_ENET1 0x00000002 /* ENET1 is stuffed */ ++#define BD_UART1 0x00000004 /* UART1 is stuffed */ ++#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */ ++#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */ ++#define BD_SYSLED 0x00000020 /* System LED stuffed */ ++#define BD_EXTUARTCLK 0x00000040 /* External UART clock */ ++#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */ ++#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */ ++#define BD_WLAN0 0x00000200 /* Enable WLAN0 */ ++#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */ ++#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */ ++#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */ ++#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */ ++#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */ ++#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */ ++#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */ ++#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */ ++ u16 resetConfigGpio; /* Reset factory GPIO pin */ ++ u16 sysLedGpio; /* System LED GPIO pin */ ++ ++ u32 cpuFreq; /* CPU core frequency in Hz */ ++ u32 sysFreq; /* System frequency in Hz */ ++ u32 cntFreq; /* Calculated C0_COUNT frequency */ ++ ++ u8 wlan0_mac[6]; ++ u8 enet0_mac[6]; ++ u8 enet1_mac[6]; ++ ++ u16 pciId; /* Pseudo PCIID for common code */ ++ u16 memCap; /* cap bank1 in MB */ ++ ++ /* version 3 */ ++ u8 wlan1_mac[6]; /* (ar5212) */ ++}; ++ ++#define BOARD_CONFIG_BUFSZ 0x1000 ++ ++/* ++ * Platform device information for the Wireless MAC ++ */ ++struct ar231x_board_config { ++ u16 devid; ++ ++ /* board config data */ ++ struct ar231x_boarddata *config; ++ ++ /* radio calibration data */ ++ const char *radio; ++}; ++ ++/* ++ * Platform device information for the Ethernet MAC ++ */ ++struct ar231x_eth { ++ u32 reset_base; ++ u32 reset_mac; ++ u32 reset_phy; ++ u32 phy_base; ++ struct ar231x_board_config *config; ++ char *macaddr; ++}; ++ ++#endif /* __AR531X_PLATFORM_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,236 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++#ifndef AR5312_H ++#define AR5312_H ++ ++#include ++ ++/* ++ * IRQs ++ */ ++ ++#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ ++#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ ++#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ ++#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ ++#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ ++ ++ ++/* Address Map */ ++#define AR531X_WLAN0 0x18000000 ++#define AR531X_WLAN1 0x18500000 ++#define AR531X_ENET0 0x18100000 ++#define AR531X_ENET1 0x18200000 ++#define AR531X_SDRAMCTL 0x18300000 ++#define AR531X_FLASHCTL 0x18400000 ++#define AR531X_APBBASE 0x1c000000 ++#define AR531X_FLASH 0x1e000000 ++#define AR531X_UART0 0xbc000003 /* UART MMR */ ++ ++/* ++ * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that ++ * should be considered available. The AR5312 supports 2 enet MACS, ++ * even though many reference boards only actually use 1 of them ++ * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch. ++ * The AR2312 supports 1 enet MAC. ++ */ ++#define AR531X_NUM_ENET_MAC 2 ++ ++/* ++ * Need these defines to determine true number of ethernet MACs ++ */ ++#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ ++#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ ++#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ ++#define AR531X_RADIO_MASK_OFF 0xc8 ++#define AR531X_RADIO0_MASK 0x0003 ++#define AR531X_RADIO1_MASK 0x000c ++#define AR531X_RADIO1_S 2 ++ ++/* ++ * AR531X_NUM_WMAC defines the number of Wireless MACs that\ ++ * should be considered available. ++ */ ++#define AR531X_NUM_WMAC 2 ++ ++/* Reset/Timer Block Address Map */ ++#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000) ++#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */ ++#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */ ++#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */ ++#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */ ++#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */ ++#define AR531X_RESET (AR531X_RESETTMR + 0x0020) ++#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064) ++#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c) ++#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070) ++#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074) ++#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078) ++#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c) ++#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */ ++#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */ ++ ++/* AR531X_WD_CTRL register bit field definitions */ ++#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000 ++#define AR531X_WD_CTRL_NMI 0x0001 ++#define AR531X_WD_CTRL_RESET 0x0002 ++ ++/* AR531X_ISR register bit field definitions */ ++#define AR531X_ISR_NONE 0x0000 ++#define AR531X_ISR_TIMER 0x0001 ++#define AR531X_ISR_AHBPROC 0x0002 ++#define AR531X_ISR_AHBDMA 0x0004 ++#define AR531X_ISR_GPIO 0x0008 ++#define AR531X_ISR_UART0 0x0010 ++#define AR531X_ISR_UART0DMA 0x0020 ++#define AR531X_ISR_WD 0x0040 ++#define AR531X_ISR_LOCAL 0x0080 ++ ++/* AR531X_RESET register bit field definitions */ ++#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */ ++#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */ ++#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */ ++#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */ ++#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */ ++#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */ ++#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */ ++#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */ ++#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */ ++#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */ ++#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */ ++#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */ ++#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */ ++#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */ ++#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */ ++#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */ ++#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */ ++#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */ ++ ++#define AR531X_RESET_WMAC0_BITS \ ++ AR531X_RESET_WLAN0 |\ ++ AR531X_RESET_WARM_WLAN0_MAC |\ ++ AR531X_RESET_WARM_WLAN0_BB ++ ++#define AR531X_RESERT_WMAC1_BITS \ ++ AR531X_RESET_WLAN1 |\ ++ AR531X_RESET_WARM_WLAN1_MAC |\ ++ AR531X_RESET_WARM_WLAN1_BB ++ ++/* AR5312_CLOCKCTL1 register bit field definitions */ ++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 ++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 ++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 ++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 ++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 ++ ++/* Valid for AR5312 and AR2312 */ ++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 ++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 ++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 ++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 ++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 ++ ++/* Valid for AR2313 */ ++#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000 ++#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12 ++#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000 ++#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16 ++#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000 ++ ++ ++/* AR531X_ENABLE register bit field definitions */ ++#define AR531X_ENABLE_WLAN0 0x0001 ++#define AR531X_ENABLE_ENET0 0x0002 ++#define AR531X_ENABLE_ENET1 0x0004 ++#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */ ++#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */ ++#define AR531X_ENABLE_WLAN1 \ ++ (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA) ++ ++/* AR531X_REV register bit field definitions */ ++#define AR531X_REV_WMAC_MAJ 0xf000 ++#define AR531X_REV_WMAC_MAJ_S 12 ++#define AR531X_REV_WMAC_MIN 0x0f00 ++#define AR531X_REV_WMAC_MIN_S 8 ++#define AR531X_REV_MAJ 0x00f0 ++#define AR531X_REV_MAJ_S 4 ++#define AR531X_REV_MIN 0x000f ++#define AR531X_REV_MIN_S 0 ++#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN) ++ ++/* Major revision numbers, bits 7..4 of Revision ID register */ ++#define AR531X_REV_MAJ_AR5312 0x4 ++#define AR531X_REV_MAJ_AR2313 0x5 ++ ++/* Minor revision numbers, bits 3..0 of Revision ID register */ ++#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */ ++#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */ ++ ++/* AR531X_FLASHCTL register bit field definitions */ ++#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */ ++#define FLASHCTL_IDCY_S 0 ++#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */ ++#define FLASHCTL_WST1_S 5 ++#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */ ++#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */ ++#define FLASHCTL_WST2_S 11 ++#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */ ++#define FLASHCTL_AC_S 16 ++#define FLASHCTL_AC_128K 0x00000000 ++#define FLASHCTL_AC_256K 0x00010000 ++#define FLASHCTL_AC_512K 0x00020000 ++#define FLASHCTL_AC_1M 0x00030000 ++#define FLASHCTL_AC_2M 0x00040000 ++#define FLASHCTL_AC_4M 0x00050000 ++#define FLASHCTL_AC_8M 0x00060000 ++#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */ ++#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */ ++#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */ ++#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */ ++#define FLASHCTL_WP 0x04000000 /* Write protect */ ++#define FLASHCTL_BM 0x08000000 /* Burst mode */ ++#define FLASHCTL_MW 0x30000000 /* Memory width */ ++#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */ ++#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */ ++#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */ ++#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */ ++#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */ ++#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */ ++ ++/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */ ++#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00) ++#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04) ++#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08) ++ ++/* ARM SDRAM Controller -- just enough to determine memory size */ ++#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04) ++#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */ ++#define MEM_CFG1_AC0_S 8 ++#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */ ++#define MEM_CFG1_AC1_S 12 ++ ++/* GPIO Address Map */ ++#define AR531X_GPIO (AR531X_APBBASE + 0x2000) ++#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */ ++#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */ ++#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */ ++ ++/* GPIO Control Register bit field definitions */ ++#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ ++#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */ ++#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */ ++#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */ ++#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */ ++#define AR531X_NUM_GPIO 8 ++ ++ ++#endif ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,84 @@ ++/* ++ * Atheros SoC specific CPU feature overrides ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * ++ * This file was derived from: include/asm-mips/cpu-features.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * Copyright (C) 2004 Maciej W. Rozycki ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H ++#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H ++ ++/* ++ * The ATHEROS SoCs have MIPS 4Kc/4KEc core. ++ */ ++#define cpu_has_tlb 1 ++#define cpu_has_4kex 1 ++#define cpu_has_3k_cache 0 ++#define cpu_has_4k_cache 1 ++#define cpu_has_tx39_cache 0 ++#define cpu_has_sb1_cache 0 ++#define cpu_has_fpu 0 ++#define cpu_has_32fpr 0 ++#define cpu_has_counter 1 ++/* #define cpu_has_watch ? */ ++/* #define cpu_has_divec ? */ ++/* #define cpu_has_vce ? */ ++/* #define cpu_has_cache_cdex_p ? */ ++/* #define cpu_has_cache_cdex_s ? */ ++/* #define cpu_has_prefetch ? */ ++/* #define cpu_has_mcheck ? */ ++#define cpu_has_ejtag 1 ++ ++#if !defined(CONFIG_ATHEROS_AR5312) ++# define cpu_has_llsc 1 ++#else ++/* ++ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the ++ * ll/sc instructions. ++ */ ++# define cpu_has_llsc 0 ++#endif ++ ++#define cpu_has_mips16 0 ++#define cpu_has_mdmx 0 ++#define cpu_has_mips3d 0 ++#define cpu_has_smartmips 0 ++ ++/* #define cpu_has_vtag_icache ? */ ++/* #define cpu_has_dc_aliases ? */ ++/* #define cpu_has_ic_fills_f_dc ? */ ++/* #define cpu_has_pindexed_dcache ? */ ++ ++/* #define cpu_icache_snoops_remote_store ? */ ++ ++#define cpu_has_mips32r1 1 ++ ++#if !defined(CONFIG_ATHEROS_AR5312) ++# define cpu_has_mips32r2 1 ++#endif ++ ++#define cpu_has_mips64r1 0 ++#define cpu_has_mips64r2 0 ++ ++#define cpu_has_dsp 0 ++#define cpu_has_mipsmt 0 ++ ++/* #define cpu_has_nofpuex ? */ ++#define cpu_has_64bits 0 ++#define cpu_has_64bit_zero_reg 0 ++#define cpu_has_64bit_gp_regs 0 ++#define cpu_has_64bit_addresses 0 ++ ++/* #define cpu_has_inclusive_pcaches ? */ ++ ++/* #define cpu_dcache_line_size() ? */ ++/* #define cpu_icache_line_size() ? */ ++ ++#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h 2011-05-15 21:41:19.000000000 +0200 +@@ -0,0 +1,76 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2006 Ralf Baechle ++ * Copyright (C) 2007 Felix Fietkau ++ * ++ */ ++#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H ++#define __ASM_MACH_GENERIC_DMA_COHERENCE_H ++ ++#define PCI_DMA_OFFSET 0x20000000 ++ ++#include ++ ++static inline dma_addr_t ar231x_dev_offset(struct device *dev) ++{ ++#ifdef CONFIG_PCI ++ extern struct bus_type pci_bus_type; ++ ++ if (dev && dev->bus == &pci_bus_type) ++ return PCI_DMA_OFFSET; ++ else ++#endif ++ return 0; ++} ++ ++static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) ++{ ++ return virt_to_phys(addr) + ar231x_dev_offset(dev); ++} ++ ++static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) ++{ ++ return page_to_phys(page) + ar231x_dev_offset(dev); ++} ++ ++static inline unsigned long plat_dma_addr_to_phys(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return dma_addr - ar231x_dev_offset(dev); ++} ++ ++static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, ++ size_t size, enum dma_data_direction direction) ++{ ++} ++ ++static inline int plat_dma_supported(struct device *dev, u64 mask) ++{ ++ return 1; ++} ++ ++static inline void plat_extra_sync_for_device(struct device *dev) ++{ ++ return; ++} ++ ++static inline int plat_dma_mapping_error(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return 0; ++} ++ ++static inline int plat_device_is_coherent(struct device *dev) ++{ ++#ifdef CONFIG_DMA_COHERENT ++ return 1; ++#endif ++#ifdef CONFIG_DMA_NONCOHERENT ++ return 0; ++#endif ++} ++ ++#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,84 @@ ++#ifndef _ATHEROS_GPIO_H_ ++#define _ATHEROS_GPIO_H_ ++ ++#include ++ ++struct ar231x_gpiodev { ++ u32 valid_mask; ++ u32 (*get_output)(void); ++ u32 (*set_output)(u32 mask, u32 val); ++ u32 (*get)(void); ++ u32 (*set)(u32 mask, u32 val); ++}; ++ ++extern const struct ar231x_gpiodev *ar231x_gpiodev; ++ ++/* ++ * Wrappers for the generic GPIO layer ++ */ ++ ++static inline int gpio_direction_input(unsigned gpio) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return -ENXIO; ++ ++ ar231x_gpiodev->set_output(mask, 0); ++ return 0; ++} ++ ++static inline void gpio_set_value(unsigned gpio, int value) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return; ++ ++ ar231x_gpiodev->set(mask, (!!value) * mask); ++} ++ ++static inline int gpio_direction_output(unsigned gpio, int value) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return -ENXIO; ++ ++ ar231x_gpiodev->set_output(mask, mask); ++ ar231x_gpiodev->set(mask, (!!value) * mask); ++ return 0; ++} ++ ++/* Reads the gpio pin. Unchecked function */ ++static inline int gpio_get_value(unsigned gpio) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return 0; ++ ++ return !!(ar231x_gpiodev->get() & mask); ++} ++ ++static inline int gpio_request(unsigned gpio, const char *label) { ++ return 0; ++} ++ ++static inline void gpio_free(unsigned gpio) { ++} ++ ++/* Returns IRQ to attach for gpio. Unchecked function */ ++static inline int gpio_to_irq(unsigned gpio) { ++ return AR531X_GPIO_IRQ(gpio); ++} ++ ++/* Returns gpio for IRQ attached. Unchecked function */ ++static inline int irq_to_gpio(unsigned irq) { ++ return (irq - (AR531X_GPIO_IRQ(0))); ++} ++ ++static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) ++{ ++ return -ENOSYS; ++} ++ ++#include /* cansleep wrappers */ ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,6 @@ ++#ifndef __AR531X_RESET_H ++#define __AR531X_RESET_H ++ ++void ar531x_disable_reset_button(void); ++ ++#endif /* __AR531X_RESET_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,25 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Felix Fietkau ++ */ ++#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H ++#define __ASM_MIPS_MACH_ATHEROS_WAR_H ++ ++#define R4600_V1_INDEX_ICACHEOP_WAR 0 ++#define R4600_V1_HIT_CACHEOP_WAR 0 ++#define R4600_V2_HIT_CACHEOP_WAR 0 ++#define R5432_CP0_INTERRUPT_WAR 0 ++#define BCM1250_M3_WAR 0 ++#define SIBYTE_1956_WAR 0 ++#define MIPS4K_ICACHE_REFILL_WAR 0 ++#define MIPS_CACHE_SYNC_WAR 0 ++#define TX49XX_ICACHE_INDEX_INV_WAR 0 ++#define RM9000_CDEX_SMP_WAR 0 ++#define ICACHE_REFILLS_WORKAROUND_WAR 0 ++#define R10000_LLSC_WAR 0 ++#define MIPS34K_MISSED_ITLB_WAR 0 ++ ++#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c +--- linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c 2011-05-15 21:34:57.000000000 +0200 +@@ -168,20 +168,23 @@ + struct clock_event_device *cd; + unsigned int irq; + +- if (!cpu_has_counter || !mips_hpt_frequency) +- return -ENXIO; +- +- if (!c0_compare_int_usable()) +- return -ENXIO; +- + /* + * With vectored interrupts things are getting platform specific. + * get_c0_compare_int is a hook to allow a platform to return the + * interrupt number of it's liking. + */ + irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; +- if (get_c0_compare_int) ++ if (get_c0_compare_int) { + irq = get_c0_compare_int(); ++ if ((irq >= MIPS_CPU_IRQ_BASE) && (irq < MIPS_CPU_IRQ_BASE + 8)) ++ cp0_compare_irq = irq - MIPS_CPU_IRQ_BASE; ++ } ++ ++ if (!cpu_has_counter || !mips_hpt_frequency) ++ return -ENXIO; ++ ++ if (!c0_compare_int_usable()) ++ return -ENXIO; + + cd = &per_cpu(mips_clockevent_device, cpu); + +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig linux-2.6.39-rc7/drivers/mtd/devices/Kconfig +--- linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/mtd/devices/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -112,6 +112,10 @@ + Set up your spi devices with the right board-specific platform data, + if you want to specify device partitioning. + ++config MTD_AR2315 ++ tristate "Atheros AR2315+ SPI Flash support" ++ depends on ATHEROS_AR2315 ++ + config MTD_SLRAM + tristate "Uncached system RAM" + help +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile linux-2.6.39-rc7/drivers/mtd/devices/Makefile +--- linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/mtd/devices/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -17,3 +17,4 @@ + obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o + obj-$(CONFIG_MTD_M25P80) += m25p80.o + obj-$(CONFIG_MTD_SST25L) += sst25l.o ++obj-$(CONFIG_MTD_AR2315) += ar2315.o +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c +--- linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,517 @@ ++ ++/* ++ * MTD driver for the SPI Flash Memory support on Atheros AR2315 ++ * ++ * Copyright (c) 2005-2006 Atheros Communications Inc. ++ * Copyright (C) 2006-2007 FON Technology, SL. ++ * Copyright (C) 2006-2007 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * This code is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++ ++#define SPIFLASH "spiflash: " ++#define busy_wait(_priv, _condition, _wait) do { \ ++ while (_condition) { \ ++ spin_unlock_bh(&_priv->lock); \ ++ if (_wait > 1) \ ++ msleep(_wait); \ ++ else if ((_wait == 1) && need_resched()) \ ++ schedule(); \ ++ else \ ++ udelay(1); \ ++ spin_lock_bh(&_priv->lock); \ ++ } \ ++} while (0) ++ ++enum { ++ FLASH_NONE, ++ FLASH_1MB, ++ FLASH_2MB, ++ FLASH_4MB, ++ FLASH_8MB, ++ FLASH_16MB, ++}; ++ ++/* Flash configuration table */ ++struct flashconfig { ++ u32 byte_cnt; ++ u32 sector_cnt; ++ u32 sector_size; ++}; ++ ++const struct flashconfig flashconfig_tbl[] = { ++ [FLASH_NONE] = { 0, 0, 0}, ++ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE}, ++ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE}, ++ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE}, ++ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE}, ++ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE} ++}; ++ ++/* Mapping of generic opcodes to STM serial flash opcodes */ ++enum { ++ SPI_WRITE_ENABLE, ++ SPI_WRITE_DISABLE, ++ SPI_RD_STATUS, ++ SPI_WR_STATUS, ++ SPI_RD_DATA, ++ SPI_FAST_RD_DATA, ++ SPI_PAGE_PROGRAM, ++ SPI_SECTOR_ERASE, ++ SPI_BULK_ERASE, ++ SPI_DEEP_PWRDOWN, ++ SPI_RD_SIG, ++}; ++ ++struct opcodes { ++ __u16 code; ++ __s8 tx_cnt; ++ __s8 rx_cnt; ++}; ++const struct opcodes stm_opcodes[] = { ++ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0}, ++ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0}, ++ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1}, ++ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0}, ++ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4}, ++ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0}, ++ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0}, ++ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0}, ++ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0}, ++ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0}, ++ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1}, ++}; ++ ++/* Driver private data structure */ ++struct spiflash_priv { ++ struct mtd_info mtd; ++ void *readaddr; /* memory mapped data for read */ ++ void *mmraddr; /* memory mapped register space */ ++ wait_queue_head_t wq; ++ spinlock_t lock; ++ int state; ++}; ++ ++#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd) ++ ++enum { ++ FL_READY, ++ FL_READING, ++ FL_ERASING, ++ FL_WRITING ++}; ++ ++/***************************************************************************************************/ ++ ++static u32 ++spiflash_read_reg(struct spiflash_priv *priv, int reg) ++{ ++ return ar231x_read_reg((u32) priv->mmraddr + reg); ++} ++ ++static void ++spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data) ++{ ++ ar231x_write_reg((u32) priv->mmraddr + reg, data); ++} ++ ++static u32 ++spiflash_wait_busy(struct spiflash_priv *priv) ++{ ++ u32 reg; ++ ++ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) & ++ SPI_CTL_BUSY, 0); ++ return reg; ++} ++ ++static u32 ++spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr) ++{ ++ const struct opcodes *op; ++ u32 reg, mask; ++ ++ op = &stm_opcodes[opcode]; ++ reg = spiflash_wait_busy(priv); ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, ++ ((u32) op->code) | (addr << 8)); ++ ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4); ++ ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ spiflash_wait_busy(priv); ++ ++ if (!op->rx_cnt) ++ return 0; ++ ++ reg = spiflash_read_reg(priv, SPI_FLASH_DATA); ++ ++ switch (op->rx_cnt) { ++ case 1: ++ mask = 0x000000ff; ++ break; ++ case 2: ++ mask = 0x0000ffff; ++ break; ++ case 3: ++ mask = 0x00ffffff; ++ break; ++ default: ++ mask = 0xffffffff; ++ break; ++ } ++ reg &= mask; ++ ++ return reg; ++} ++ ++ ++/* ++ * Probe SPI flash device ++ * Function returns 0 for failure. ++ * and flashconfig_tbl array index for success. ++ */ ++static int ++spiflash_probe_chip (struct spiflash_priv *priv) ++{ ++ u32 sig; ++ int flash_size; ++ ++ /* Read the signature on the flash device */ ++ spin_lock_bh(&priv->lock); ++ sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0); ++ spin_unlock_bh(&priv->lock); ++ ++ switch (sig) { ++ case STM_8MBIT_SIGNATURE: ++ flash_size = FLASH_1MB; ++ break; ++ case STM_16MBIT_SIGNATURE: ++ flash_size = FLASH_2MB; ++ break; ++ case STM_32MBIT_SIGNATURE: ++ flash_size = FLASH_4MB; ++ break; ++ case STM_64MBIT_SIGNATURE: ++ flash_size = FLASH_8MB; ++ break; ++ case STM_128MBIT_SIGNATURE: ++ flash_size = FLASH_16MB; ++ break; ++ default: ++ printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n"); ++ return 0; ++ } ++ ++ return flash_size; ++} ++ ++ ++/* wait until the flash chip is ready and grab a lock */ ++static int spiflash_wait_ready(struct spiflash_priv *priv, int state) ++{ ++ DECLARE_WAITQUEUE(wait, current); ++ ++retry: ++ spin_lock_bh(&priv->lock); ++ if (priv->state != FL_READY) { ++ set_current_state(TASK_UNINTERRUPTIBLE); ++ add_wait_queue(&priv->wq, &wait); ++ spin_unlock_bh(&priv->lock); ++ schedule(); ++ remove_wait_queue(&priv->wq, &wait); ++ ++ if(signal_pending(current)) ++ return 0; ++ ++ goto retry; ++ } ++ priv->state = state; ++ ++ return 1; ++} ++ ++static inline void spiflash_done(struct spiflash_priv *priv) ++{ ++ priv->state = FL_READY; ++ spin_unlock_bh(&priv->lock); ++ wake_up(&priv->wq); ++} ++ ++static void ++spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout) ++{ ++ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) & ++ SPI_STATUS_WIP, timeout); ++ spiflash_done(priv); ++} ++ ++ ++ ++static int ++spiflash_erase (struct mtd_info *mtd, struct erase_info *instr) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ const struct opcodes *op; ++ u32 temp, reg; ++ ++ if (instr->addr + instr->len > mtd->size) ++ return -EINVAL; ++ ++ if (!spiflash_wait_ready(priv, FL_ERASING)) ++ return -EINTR; ++ ++ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); ++ reg = spiflash_wait_busy(priv); ++ ++ op = &stm_opcodes[SPI_SECTOR_ERASE]; ++ temp = ((u32)instr->addr << 8) | (u32)(op->code); ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp); ++ ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= op->tx_cnt | SPI_CTL_START; ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ ++ spiflash_wait_complete(priv, 20); ++ ++ instr->state = MTD_ERASE_DONE; ++ mtd_erase_callback(instr); ++ ++ return 0; ++} ++ ++static int ++spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ u8 *read_addr; ++ ++ if (!len) ++ return 0; ++ ++ if (from + len > mtd->size) ++ return -EINVAL; ++ ++ *retlen = len; ++ ++ if (!spiflash_wait_ready(priv, FL_READING)) ++ return -EINTR; ++ ++ read_addr = (u8 *)(priv->readaddr + from); ++ memcpy_fromio(buf, read_addr, len); ++ spiflash_done(priv); ++ ++ return 0; ++} ++ ++static int ++spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ u32 opcode, bytes_left; ++ ++ *retlen = 0; ++ ++ if (!len) ++ return 0; ++ ++ if (to + len > mtd->size) ++ return -EINVAL; ++ ++ bytes_left = len; ++ ++ do { ++ u32 read_len, reg, page_offset, spi_data = 0; ++ ++ read_len = min(bytes_left, sizeof(u32)); ++ ++ /* 32-bit writes cannot span across a page boundary ++ * (256 bytes). This types of writes require two page ++ * program operations to handle it correctly. The STM part ++ * will write the overflow data to the beginning of the ++ * current page as opposed to the subsequent page. ++ */ ++ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len; ++ ++ if (page_offset > STM_PAGE_SIZE) ++ read_len -= (page_offset - STM_PAGE_SIZE); ++ ++ if (!spiflash_wait_ready(priv, FL_WRITING)) ++ return -EINTR; ++ ++ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); ++ spi_data = 0; ++ switch (read_len) { ++ case 4: ++ spi_data |= buf[3] << 24; ++ /* fall through */ ++ case 3: ++ spi_data |= buf[2] << 16; ++ /* fall through */ ++ case 2: ++ spi_data |= buf[1] << 8; ++ /* fall through */ ++ case 1: ++ spi_data |= buf[0] & 0xff; ++ break; ++ default: ++ break; ++ } ++ ++ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data); ++ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code | ++ (to & 0x00ffffff) << 8; ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode); ++ ++ reg = spiflash_read_reg(priv, SPI_FLASH_CTL); ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= (read_len + 4) | SPI_CTL_START; ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ ++ spiflash_wait_complete(priv, 1); ++ ++ bytes_left -= read_len; ++ to += read_len; ++ buf += read_len; ++ ++ *retlen += read_len; ++ } while (bytes_left != 0); ++ ++ return 0; ++} ++ ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL }; ++#endif ++ ++ ++static int ++spiflash_probe(struct platform_device *pdev) ++{ ++ struct spiflash_priv *priv; ++ struct mtd_partition *parts; ++ struct mtd_info *mtd; ++ int index, num_parts; ++ int result = 0; ++ ++ priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL); ++ spin_lock_init(&priv->lock); ++ init_waitqueue_head(&priv->wq); ++ priv->state = FL_READY; ++ mtd = &priv->mtd; ++ ++ priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE); ++ if (!priv->mmraddr) { ++ printk(KERN_WARNING SPIFLASH "Failed to map flash device\n"); ++ goto error; ++ } ++ ++ index = spiflash_probe_chip(priv); ++ if (!index) { ++ printk (KERN_WARNING SPIFLASH "Found no serial flash device\n"); ++ goto error; ++ } ++ ++ priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt); ++ if (!priv->readaddr) { ++ printk (KERN_WARNING SPIFLASH "Failed to map flash device\n"); ++ goto error; ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ mtd->name = "spiflash"; ++ mtd->type = MTD_NORFLASH; ++ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE); ++ mtd->size = flashconfig_tbl[index].byte_cnt; ++ mtd->erasesize = flashconfig_tbl[index].sector_size; ++ mtd->writesize = 1; ++ mtd->numeraseregions = 0; ++ mtd->eraseregions = NULL; ++ mtd->erase = spiflash_erase; ++ mtd->read = spiflash_read; ++ mtd->write = spiflash_write; ++ mtd->owner = THIS_MODULE; ++ ++#ifdef CONFIG_MTD_PARTITIONS ++ /* parse redboot partitions */ ++ num_parts = parse_mtd_partitions(mtd, part_probe_types, &parts, 0); ++ if (!num_parts) ++ goto error; ++ ++ result = add_mtd_partitions(mtd, parts, num_parts); ++#endif ++ ++ return result; ++ ++error: ++ if (priv->mmraddr) ++ iounmap(priv->mmraddr); ++ kfree(priv); ++ return -ENXIO; ++} ++ ++static int ++spiflash_remove (struct platform_device *pdev) ++{ ++ struct spiflash_priv *priv = platform_get_drvdata(pdev); ++ struct mtd_info *mtd = &priv->mtd; ++ ++ del_mtd_partitions(mtd); ++ iounmap(priv->mmraddr); ++ iounmap(priv->readaddr); ++ kfree(priv); ++ ++ return 0; ++} ++ ++struct platform_driver spiflash_driver = { ++ .driver.name = "spiflash", ++ .probe = spiflash_probe, ++ .remove = spiflash_remove, ++}; ++ ++int __init ++spiflash_init (void) ++{ ++ return platform_driver_register(&spiflash_driver); ++} ++ ++void __exit ++spiflash_exit (void) ++{ ++ return platform_driver_unregister(&spiflash_driver); ++} ++ ++module_init (spiflash_init); ++module_exit (spiflash_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc"); ++MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC"); ++ +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/redboot.c linux-2.6.39-rc7/drivers/mtd/redboot.c +--- linux-2.6.39-rc7.orig/drivers/mtd/redboot.c 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/mtd/redboot.c 2011-05-15 21:34:57.000000000 +0200 +@@ -55,6 +55,22 @@ + return 1; + } + ++static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset) ++{ ++ struct mtd_erase_region_info *regions = mtd->eraseregions; ++ int i; ++ ++ for (i = 0; i < mtd->numeraseregions; i++) { ++ if (regions[i].offset + ++ regions[i].numblocks * regions[i].erasesize <= offset) ++ continue; ++ ++ return regions[i].erasesize; ++ } ++ ++ return mtd->erasesize; ++} ++ + static int parse_redboot_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + unsigned long fis_origin) +@@ -70,36 +86,38 @@ + int namelen = 0; + int nulllen = 0; + int numslots; ++ int first_slot; + unsigned long offset; + #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + static char nullstring[] = "unallocated"; + #endif + ++ buf = vmalloc(master->erasesize); ++ if (!buf) ++ return -ENOMEM; ++ ++ restart: + if ( directory < 0 ) { + offset = master->size + directory * master->erasesize; +- while (master->block_isbad && ++ while (master->block_isbad && + master->block_isbad(master, offset)) { + if (!offset) { + nogood: + printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); ++ vfree(buf); + return -EIO; + } + offset -= master->erasesize; + } + } else { + offset = directory * master->erasesize; +- while (master->block_isbad && ++ while (master->block_isbad && + master->block_isbad(master, offset)) { + offset += master->erasesize; + if (offset == master->size) + goto nogood; + } + } +- buf = vmalloc(master->erasesize); +- +- if (!buf) +- return -ENOMEM; +- + printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", + master->name, offset); + +@@ -171,13 +189,21 @@ + } + if (i == numslots) { + /* Didn't find it */ ++ if (offset + master->erasesize < master->size) { ++ /* not at the end of the flash yet, maybe next block :) */ ++ directory++; ++ goto restart; ++ } + printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", + master->name); + ret = 0; + goto out; + } + +- for (i = 0; i < numslots; i++) { ++ first_slot = (buf[i].flash_base & (master->erasesize - 1)) / ++ sizeof(struct fis_image_desc); ++ ++ for (i = first_slot; i < first_slot + numslots; i++) { + struct fis_list *new_fl, **prev; + + if (buf[i].name[0] == 0xff) { +diff -Nur linux-2.6.39-rc7.orig/drivers/net/Kconfig linux-2.6.39-rc7/drivers/net/Kconfig +--- linux-2.6.39-rc7.orig/drivers/net/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/net/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -251,6 +251,12 @@ + help + Select this if your platform comes with an external 93CX6 eeprom. + ++config AR231X_ETHERNET ++ tristate "AR231x Ethernet support" ++ depends on ATHEROS_AR231X ++ help ++ Support for the AR231x/531x ethernet controller ++ + config MACE + tristate "MACE (Power Mac ethernet) support" + depends on PPC_PMAC && PPC32 +diff -Nur linux-2.6.39-rc7.orig/drivers/net/Makefile linux-2.6.39-rc7/drivers/net/Makefile +--- linux-2.6.39-rc7.orig/drivers/net/Makefile 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/net/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -226,6 +226,7 @@ + obj-$(CONFIG_KORINA) += korina.o + obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o + obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o ++obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o + obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o + obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o + obj-$(CONFIG_DECLANCE) += declance.o +diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.c linux-2.6.39-rc7/drivers/net/ar231x.c +--- linux-2.6.39-rc7.orig/drivers/net/ar231x.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/net/ar231x.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,1293 @@ ++/* ++ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device. ++ * ++ * Copyright (C) 2004 by Sameer Dekate ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * Thanks to Atheros for providing hardware and documentation ++ * enabling me to write this driver. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * Additional credits: ++ * This code is taken from John Taylor's Sibyte driver and then ++ * modified for the AR2313. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define AR2313_MTU 1692 ++#define AR2313_PRIOS 1 ++#define AR2313_QUEUES (2*AR2313_PRIOS) ++#define AR2313_DESCR_ENTRIES 64 ++ ++ ++#ifndef min ++#define min(a,b) (((a)<(b))?(a):(b)) ++#endif ++ ++#ifndef SMP_CACHE_BYTES ++#define SMP_CACHE_BYTES L1_CACHE_BYTES ++#endif ++ ++#define AR2313_MBOX_SET_BIT 0x8 ++ ++#include "ar231x.h" ++ ++/* ++ * New interrupt handler strategy: ++ * ++ * An old interrupt handler worked using the traditional method of ++ * replacing an skbuff with a new one when a packet arrives. However ++ * the rx rings do not need to contain a static number of buffer ++ * descriptors, thus it makes sense to move the memory allocation out ++ * of the main interrupt handler and do it in a bottom half handler ++ * and only allocate new buffers when the number of buffers in the ++ * ring is below a certain threshold. In order to avoid starving the ++ * NIC under heavy load it is however necessary to force allocation ++ * when hitting a minimum threshold. The strategy for alloction is as ++ * follows: ++ * ++ * RX_LOW_BUF_THRES - allocate buffers in the bottom half ++ * RX_PANIC_LOW_THRES - we are very low on buffers, allocate ++ * the buffers in the interrupt handler ++ * RX_RING_THRES - maximum number of buffers in the rx ring ++ * ++ * One advantagous side effect of this allocation approach is that the ++ * entire rx processing can be done without holding any spin lock ++ * since the rx rings and registers are totally independent of the tx ++ * ring and its registers. This of course includes the kmalloc's of ++ * new skb's. Thus start_xmit can run in parallel with rx processing ++ * and the memory allocation on SMP systems. ++ * ++ * Note that running the skb reallocation in a bottom half opens up ++ * another can of races which needs to be handled properly. In ++ * particular it can happen that the interrupt handler tries to run ++ * the reallocation while the bottom half is either running on another ++ * CPU or was interrupted on the same CPU. To get around this the ++ * driver uses bitops to prevent the reallocation routines from being ++ * reentered. ++ * ++ * TX handling can also be done without holding any spin lock, wheee ++ * this is fun! since tx_csm is only written to by the interrupt ++ * handler. ++ */ ++ ++/* ++ * Threshold values for RX buffer allocation - the low water marks for ++ * when to start refilling the rings are set to 75% of the ring ++ * sizes. It seems to make sense to refill the rings entirely from the ++ * intrrupt handler once it gets below the panic threshold, that way ++ * we don't risk that the refilling is moved to another CPU when the ++ * one running the interrupt handler just got the slab code hot in its ++ * cache. ++ */ ++#define RX_RING_SIZE AR2313_DESCR_ENTRIES ++#define RX_PANIC_THRES (RX_RING_SIZE/4) ++#define RX_LOW_THRES ((3*RX_RING_SIZE)/4) ++#define CRC_LEN 4 ++#define RX_OFFSET 2 ++ ++#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) ++#define VLAN_HDR 4 ++#else ++#define VLAN_HDR 0 ++#endif ++ ++#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET) ++ ++#ifdef MODULE ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Sameer Dekate , Imre Kaloz , Felix Fietkau "); ++MODULE_DESCRIPTION("AR231x Ethernet driver"); ++#endif ++ ++#define virt_to_phys(x) ((u32)(x) & 0x1fffffff) ++ ++// prototypes ++static void ar231x_halt(struct net_device *dev); ++static void rx_tasklet_func(unsigned long data); ++static void rx_tasklet_cleanup(struct net_device *dev); ++static void ar231x_multicast_list(struct net_device *dev); ++static void ar231x_tx_timeout(struct net_device *dev); ++ ++static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum); ++static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value); ++static int ar231x_mdiobus_reset(struct mii_bus *bus); ++static int ar231x_mdiobus_probe (struct net_device *dev); ++static void ar231x_adjust_link(struct net_device *dev); ++ ++#ifndef ERR ++#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) ++#endif ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++static void ++ar231x_netpoll(struct net_device *dev) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ ar231x_interrupt(dev->irq, dev); ++ local_irq_restore(flags); ++} ++#endif ++ ++static const struct net_device_ops ar231x_ops = { ++ .ndo_open = ar231x_open, ++ .ndo_stop = ar231x_close, ++ .ndo_start_xmit = ar231x_start_xmit, ++ .ndo_set_multicast_list = ar231x_multicast_list, ++ .ndo_do_ioctl = ar231x_ioctl, ++ .ndo_change_mtu = eth_change_mtu, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_set_mac_address = eth_mac_addr, ++ .ndo_tx_timeout = ar231x_tx_timeout, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = ar231x_netpoll, ++#endif ++}; ++ ++int __init ar231x_probe(struct platform_device *pdev) ++{ ++ struct net_device *dev; ++ struct ar231x_private *sp; ++ struct resource *res; ++ unsigned long ar_eth_base; ++ char buf[64]; ++ ++ dev = alloc_etherdev(sizeof(struct ar231x_private)); ++ ++ if (dev == NULL) { ++ printk(KERN_ERR ++ "ar231x: Unable to allocate net_device structure!\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(pdev, dev); ++ ++ sp = netdev_priv(dev); ++ sp->dev = dev; ++ sp->cfg = pdev->dev.platform_data; ++ ++ sprintf(buf, "eth%d_membase", pdev->id); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf); ++ if (!res) ++ return -ENODEV; ++ ++ sp->link = 0; ++ ar_eth_base = res->start; ++ ++ sprintf(buf, "eth%d_irq", pdev->id); ++ dev->irq = platform_get_irq_byname(pdev, buf); ++ ++ spin_lock_init(&sp->lock); ++ ++ dev->features |= NETIF_F_HIGHDMA; ++ dev->netdev_ops = &ar231x_ops; ++ ++ tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev); ++ tasklet_disable(&sp->rx_tasklet); ++ ++ sp->eth_regs = ++ ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs)); ++ if (!sp->eth_regs) { ++ printk("Can't remap eth registers\n"); ++ return (-ENXIO); ++ } ++ ++ /* ++ * When there's only one MAC, PHY regs are typically on ENET0, ++ * even though the MAC might be on ENET1. ++ * Needto remap PHY regs separately in this case ++ */ ++ if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs)) ++ sp->phy_regs = sp->eth_regs; ++ else { ++ sp->phy_regs = ++ ioremap_nocache(virt_to_phys(sp->cfg->phy_base), ++ sizeof(*sp->phy_regs)); ++ if (!sp->phy_regs) { ++ printk("Can't remap phy registers\n"); ++ return (-ENXIO); ++ } ++ } ++ ++ sp->dma_regs = ++ ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000), ++ sizeof(*sp->dma_regs)); ++ dev->base_addr = (unsigned int) sp->dma_regs; ++ if (!sp->dma_regs) { ++ printk("Can't remap DMA registers\n"); ++ return (-ENXIO); ++ } ++ ++ sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4); ++ if (!sp->int_regs) { ++ printk("Can't remap INTERRUPT registers\n"); ++ return (-ENXIO); ++ } ++ ++ strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1); ++ sp->name[sizeof(sp->name) - 1] = '\0'; ++ memcpy(dev->dev_addr, sp->cfg->macaddr, 6); ++ ++ if (ar231x_init(dev)) { ++ /* ++ * ar231x_init() calls ar231x_init_cleanup() on error. ++ */ ++ kfree(dev); ++ return -ENODEV; ++ } ++ ++ if (register_netdev(dev)) { ++ printk("%s: register_netdev failed\n", __func__); ++ return -1; ++ } ++ ++ printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n", ++ dev->name, sp->name, ++ dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], ++ dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq); ++ ++ sp->mii_bus = mdiobus_alloc(); ++ if (sp->mii_bus == NULL) ++ return -1; ++ ++ sp->mii_bus->priv = dev; ++ sp->mii_bus->read = ar231x_mdiobus_read; ++ sp->mii_bus->write = ar231x_mdiobus_write; ++ sp->mii_bus->reset = ar231x_mdiobus_reset; ++ sp->mii_bus->name = "ar231x_eth_mii"; ++ snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); ++ sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL); ++ *sp->mii_bus->irq = PHY_POLL; ++ ++ mdiobus_register(sp->mii_bus); ++ ++ if (ar231x_mdiobus_probe(dev) != 0) { ++ printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name); ++ rx_tasklet_cleanup(dev); ++ ar231x_init_cleanup(dev); ++ unregister_netdev(dev); ++ kfree(dev); ++ return -ENODEV; ++ } ++ ++ /* start link poll timer */ ++ ar231x_setup_timer(dev); ++ ++ return 0; ++} ++ ++ ++static void ar231x_multicast_list(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int filter; ++ ++ filter = sp->eth_regs->mac_control; ++ ++ if (dev->flags & IFF_PROMISC) ++ filter |= MAC_CONTROL_PR; ++ else ++ filter &= ~MAC_CONTROL_PR; ++ if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0)) ++ filter |= MAC_CONTROL_PM; ++ else ++ filter &= ~MAC_CONTROL_PM; ++ ++ sp->eth_regs->mac_control = filter; ++} ++ ++static void rx_tasklet_cleanup(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ /* ++ * Tasklet may be scheduled. Need to get it removed from the list ++ * since we're about to free the struct. ++ */ ++ ++ sp->unloading = 1; ++ tasklet_enable(&sp->rx_tasklet); ++ tasklet_kill(&sp->rx_tasklet); ++} ++ ++static int __devexit ar231x_remove(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ struct ar231x_private *sp = netdev_priv(dev); ++ rx_tasklet_cleanup(dev); ++ ar231x_init_cleanup(dev); ++ unregister_netdev(dev); ++ mdiobus_unregister(sp->mii_bus); ++ mdiobus_free(sp->mii_bus); ++ kfree(dev); ++ return 0; ++} ++ ++ ++/* ++ * Restart the AR2313 ethernet controller. ++ */ ++static int ar231x_restart(struct net_device *dev) ++{ ++ /* disable interrupts */ ++ disable_irq(dev->irq); ++ ++ /* stop mac */ ++ ar231x_halt(dev); ++ ++ /* initialize */ ++ ar231x_init(dev); ++ ++ /* enable interrupts */ ++ enable_irq(dev->irq); ++ ++ return 0; ++} ++ ++static struct platform_driver ar231x_driver = { ++ .driver.name = "ar231x-eth", ++ .probe = ar231x_probe, ++ .remove = __devexit_p(ar231x_remove), ++}; ++ ++int __init ar231x_module_init(void) ++{ ++ return platform_driver_register(&ar231x_driver); ++} ++ ++void __exit ar231x_module_cleanup(void) ++{ ++ platform_driver_unregister(&ar231x_driver); ++} ++ ++module_init(ar231x_module_init); ++module_exit(ar231x_module_cleanup); ++ ++ ++static void ar231x_free_descriptors(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ if (sp->rx_ring != NULL) { ++ kfree((void *) KSEG0ADDR(sp->rx_ring)); ++ sp->rx_ring = NULL; ++ sp->tx_ring = NULL; ++ } ++} ++ ++ ++static int ar231x_allocate_descriptors(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int size; ++ int j; ++ ar231x_descr_t *space; ++ ++ if (sp->rx_ring != NULL) { ++ printk("%s: already done.\n", __FUNCTION__); ++ return 0; ++ } ++ ++ size = ++ (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES)); ++ space = kmalloc(size, GFP_KERNEL); ++ if (space == NULL) ++ return 1; ++ ++ /* invalidate caches */ ++ dma_cache_inv((unsigned int) space, size); ++ ++ /* now convert pointer to KSEG1 */ ++ space = (ar231x_descr_t *) KSEG1ADDR(space); ++ ++ memset((void *) space, 0, size); ++ ++ sp->rx_ring = space; ++ space += AR2313_DESCR_ENTRIES; ++ ++ sp->tx_ring = space; ++ space += AR2313_DESCR_ENTRIES; ++ ++ /* Initialize the transmit Descriptors */ ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ ar231x_descr_t *td = &sp->tx_ring[j]; ++ td->status = 0; ++ td->devcs = DMA_TX1_CHAINED; ++ td->addr = 0; ++ td->descr = ++ virt_to_phys(&sp-> ++ tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]); ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * Generic cleanup handling data allocated during init. Used when the ++ * module is unloaded or if an error occurs during initialization ++ */ ++static void ar231x_init_cleanup(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ struct sk_buff *skb; ++ int j; ++ ++ ar231x_free_descriptors(dev); ++ ++ if (sp->eth_regs) ++ iounmap((void *) sp->eth_regs); ++ if (sp->dma_regs) ++ iounmap((void *) sp->dma_regs); ++ ++ if (sp->rx_skb) { ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ skb = sp->rx_skb[j]; ++ if (skb) { ++ sp->rx_skb[j] = NULL; ++ dev_kfree_skb(skb); ++ } ++ } ++ kfree(sp->rx_skb); ++ sp->rx_skb = NULL; ++ } ++ ++ if (sp->tx_skb) { ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ skb = sp->tx_skb[j]; ++ if (skb) { ++ sp->tx_skb[j] = NULL; ++ dev_kfree_skb(skb); ++ } ++ } ++ kfree(sp->tx_skb); ++ sp->tx_skb = NULL; ++ } ++} ++ ++static int ar231x_setup_timer(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ init_timer(&sp->link_timer); ++ ++ sp->link_timer.function = ar231x_link_timer_fn; ++ sp->link_timer.data = (int) dev; ++ sp->link_timer.expires = jiffies + HZ; ++ ++ add_timer(&sp->link_timer); ++ return 0; ++ ++} ++ ++static void ar231x_link_timer_fn(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *) data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ // see if the link status changed ++ // This was needed to make sure we set the PHY to the ++ // autonegotiated value of half or full duplex. ++ ar231x_check_link(dev); ++ ++ // Loop faster when we don't have link. ++ // This was needed to speed up the AP bootstrap time. ++ if (sp->link == 0) { ++ mod_timer(&sp->link_timer, jiffies + HZ / 2); ++ } else { ++ mod_timer(&sp->link_timer, jiffies + LINK_TIMER); ++ } ++} ++ ++static void ar231x_check_link(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ u16 phyData; ++ ++ phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR); ++ if (sp->phyData != phyData) { ++ if (phyData & BMSR_LSTATUS) { ++ /* link is present, ready link partner ability to deterine ++ duplexity */ ++ int duplex = 0; ++ u16 reg; ++ ++ sp->link = 1; ++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR); ++ if (reg & BMCR_ANENABLE) { ++ /* auto neg enabled */ ++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA); ++ duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0; ++ } else { ++ /* no auto neg, just read duplex config */ ++ duplex = (reg & BMCR_FULLDPLX) ? 1 : 0; ++ } ++ ++ printk(KERN_INFO "%s: Configuring MAC for %s duplex\n", ++ dev->name, (duplex) ? "full" : "half"); ++ ++ if (duplex) { ++ /* full duplex */ ++ sp->eth_regs->mac_control = ++ ((sp->eth_regs-> ++ mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO); ++ } else { ++ /* half duplex */ ++ sp->eth_regs->mac_control = ++ ((sp->eth_regs-> ++ mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F); ++ } ++ } else { ++ /* no link */ ++ sp->link = 0; ++ } ++ sp->phyData = phyData; ++ } ++} ++ ++static int ar231x_reset_reg(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int ethsal, ethsah; ++ unsigned int flags; ++ ++ *sp->int_regs |= sp->cfg->reset_mac; ++ mdelay(10); ++ *sp->int_regs &= ~sp->cfg->reset_mac; ++ mdelay(10); ++ *sp->int_regs |= sp->cfg->reset_phy; ++ mdelay(10); ++ *sp->int_regs &= ~sp->cfg->reset_phy; ++ mdelay(10); ++ ++ sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR); ++ mdelay(10); ++ sp->dma_regs->bus_mode = ++ ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE); ++ ++ /* enable interrupts */ ++ sp->dma_regs->intr_ena = (DMA_STATUS_AIS | ++ DMA_STATUS_NIS | ++ DMA_STATUS_RI | ++ DMA_STATUS_TI | DMA_STATUS_FBE); ++ sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring); ++ sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring); ++ sp->dma_regs->control = ++ (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF); ++ ++ sp->eth_regs->flow_control = (FLOW_CONTROL_FCE); ++ sp->eth_regs->vlan_tag = (0x8100); ++ ++ /* Enable Ethernet Interface */ ++ flags = (MAC_CONTROL_TE | /* transmit enable */ ++ MAC_CONTROL_PM | /* pass mcast */ ++ MAC_CONTROL_F | /* full duplex */ ++ MAC_CONTROL_HBD); /* heart beat disabled */ ++ ++ if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ ++ flags |= MAC_CONTROL_PR; ++ } ++ sp->eth_regs->mac_control = flags; ++ ++ /* Set all Ethernet station address registers to their initial values */ ++ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); ++ ++ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | ++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | ++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); ++ ++ sp->eth_regs->mac_addr[0] = ethsah; ++ sp->eth_regs->mac_addr[1] = ethsal; ++ ++ mdelay(10); ++ ++ return (0); ++} ++ ++ ++static int ar231x_init(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int ecode = 0; ++ ++ /* ++ * Allocate descriptors ++ */ ++ if (ar231x_allocate_descriptors(dev)) { ++ printk("%s: %s: ar231x_allocate_descriptors failed\n", ++ dev->name, __FUNCTION__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ ++ /* ++ * Get the memory for the skb rings. ++ */ ++ if (sp->rx_skb == NULL) { ++ sp->rx_skb = ++ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, ++ GFP_KERNEL); ++ if (!(sp->rx_skb)) { ++ printk("%s: %s: rx_skb kmalloc failed\n", ++ dev->name, __FUNCTION__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ } ++ memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); ++ ++ if (sp->tx_skb == NULL) { ++ sp->tx_skb = ++ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, ++ GFP_KERNEL); ++ if (!(sp->tx_skb)) { ++ printk("%s: %s: tx_skb kmalloc failed\n", ++ dev->name, __FUNCTION__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ } ++ memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); ++ ++ /* ++ * Set tx_csm before we start receiving interrupts, otherwise ++ * the interrupt handler might think it is supposed to process ++ * tx ints before we are up and running, which may cause a null ++ * pointer access in the int handler. ++ */ ++ sp->rx_skbprd = 0; ++ sp->cur_rx = 0; ++ sp->tx_prd = 0; ++ sp->tx_csm = 0; ++ ++ /* ++ * Zero the stats before starting the interface ++ */ ++ memset(&dev->stats, 0, sizeof(dev->stats)); ++ ++ /* ++ * We load the ring here as there seem to be no way to tell the ++ * firmware to wipe the ring without re-initializing it. ++ */ ++ ar231x_load_rx_ring(dev, RX_RING_SIZE); ++ ++ /* ++ * Init hardware ++ */ ++ ar231x_reset_reg(dev); ++ ++ /* ++ * Get the IRQ ++ */ ++ ecode = ++ request_irq(dev->irq, &ar231x_interrupt, ++ IRQF_DISABLED | IRQF_SAMPLE_RANDOM, ++ dev->name, dev); ++ if (ecode) { ++ printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n", ++ dev->name, __FUNCTION__, dev->irq); ++ goto init_error; ++ } ++ ++ ++ tasklet_enable(&sp->rx_tasklet); ++ ++ return 0; ++ ++ init_error: ++ ar231x_init_cleanup(dev); ++ return ecode; ++} ++ ++/* ++ * Load the rx ring. ++ * ++ * Loading rings is safe without holding the spin lock since this is ++ * done only before the device is enabled, thus no interrupts are ++ * generated and by the interrupt handler/tasklet handler. ++ */ ++static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs) ++{ ++ ++ struct ar231x_private *sp = netdev_priv(dev); ++ short i, idx; ++ ++ idx = sp->rx_skbprd; ++ ++ for (i = 0; i < nr_bufs; i++) { ++ struct sk_buff *skb; ++ ar231x_descr_t *rd; ++ ++ if (sp->rx_skb[idx]) ++ break; ++ ++ skb = netdev_alloc_skb(dev, AR2313_BUFSIZE); ++ if (!skb) { ++ printk("\n\n\n\n %s: No memory in system\n\n\n\n", ++ __FUNCTION__); ++ break; ++ } ++ ++ /* ++ * Make sure IP header starts on a fresh cache line. ++ */ ++ skb->dev = dev; ++ skb_reserve(skb, RX_OFFSET); ++ sp->rx_skb[idx] = skb; ++ ++ rd = (ar231x_descr_t *) & sp->rx_ring[idx]; ++ ++ /* initialize dma descriptor */ ++ rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | ++ DMA_RX1_CHAINED); ++ rd->addr = virt_to_phys(skb->data); ++ rd->descr = ++ virt_to_phys(&sp-> ++ rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]); ++ rd->status = DMA_RX_OWN; ++ ++ idx = DSC_NEXT(idx); ++ } ++ ++ if (i) ++ sp->rx_skbprd = idx; ++ ++ return; ++} ++ ++#define AR2313_MAX_PKTS_PER_CALL 64 ++ ++static int ar231x_rx_int(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ struct sk_buff *skb, *skb_new; ++ ar231x_descr_t *rxdesc; ++ unsigned int status; ++ u32 idx; ++ int pkts = 0; ++ int rval; ++ ++ idx = sp->cur_rx; ++ ++ /* process at most the entire ring and then wait for another interrupt ++ */ ++ while (1) { ++ ++ rxdesc = &sp->rx_ring[idx]; ++ status = rxdesc->status; ++ if (status & DMA_RX_OWN) { ++ /* SiByte owns descriptor or descr not yet filled in */ ++ rval = 0; ++ break; ++ } ++ ++ if (++pkts > AR2313_MAX_PKTS_PER_CALL) { ++ rval = 1; ++ break; ++ } ++ ++ if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) { ++ dev->stats.rx_errors++; ++ dev->stats.rx_dropped++; ++ ++ /* add statistics counters */ ++ if (status & DMA_RX_ERR_CRC) ++ dev->stats.rx_crc_errors++; ++ if (status & DMA_RX_ERR_COL) ++ dev->stats.rx_over_errors++; ++ if (status & DMA_RX_ERR_LENGTH) ++ dev->stats.rx_length_errors++; ++ if (status & DMA_RX_ERR_RUNT) ++ dev->stats.rx_over_errors++; ++ if (status & DMA_RX_ERR_DESC) ++ dev->stats.rx_over_errors++; ++ ++ } else { ++ /* alloc new buffer. */ ++ skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET); ++ if (skb_new != NULL) { ++ ++ skb = sp->rx_skb[idx]; ++ /* set skb */ ++ skb_put(skb, ++ ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN); ++ ++ dev->stats.rx_bytes += skb->len; ++ skb->protocol = eth_type_trans(skb, dev); ++ /* pass the packet to upper layers */ ++ netif_rx(skb); ++ ++ skb_new->dev = dev; ++ /* 16 bit align */ ++ skb_reserve(skb_new, RX_OFFSET); ++ /* reset descriptor's curr_addr */ ++ rxdesc->addr = virt_to_phys(skb_new->data); ++ ++ dev->stats.rx_packets++; ++ sp->rx_skb[idx] = skb_new; ++ } else { ++ dev->stats.rx_dropped++; ++ } ++ } ++ ++ rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | ++ DMA_RX1_CHAINED); ++ rxdesc->status = DMA_RX_OWN; ++ ++ idx = DSC_NEXT(idx); ++ } ++ ++ sp->cur_rx = idx; ++ ++ return rval; ++} ++ ++ ++static void ar231x_tx_int(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ u32 idx; ++ struct sk_buff *skb; ++ ar231x_descr_t *txdesc; ++ unsigned int status = 0; ++ ++ idx = sp->tx_csm; ++ ++ while (idx != sp->tx_prd) { ++ txdesc = &sp->tx_ring[idx]; ++ ++ if ((status = txdesc->status) & DMA_TX_OWN) { ++ /* ar231x dma still owns descr */ ++ break; ++ } ++ /* done with this descriptor */ ++ dma_unmap_single(NULL, txdesc->addr, ++ txdesc->devcs & DMA_TX1_BSIZE_MASK, ++ DMA_TO_DEVICE); ++ txdesc->status = 0; ++ ++ if (status & DMA_TX_ERROR) { ++ dev->stats.tx_errors++; ++ dev->stats.tx_dropped++; ++ if (status & DMA_TX_ERR_UNDER) ++ dev->stats.tx_fifo_errors++; ++ if (status & DMA_TX_ERR_HB) ++ dev->stats.tx_heartbeat_errors++; ++ if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK)) ++ dev->stats.tx_carrier_errors++; ++ if (status & (DMA_TX_ERR_LATE | ++ DMA_TX_ERR_COL | ++ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER)) ++ dev->stats.tx_aborted_errors++; ++ } else { ++ /* transmit OK */ ++ dev->stats.tx_packets++; ++ } ++ ++ skb = sp->tx_skb[idx]; ++ sp->tx_skb[idx] = NULL; ++ idx = DSC_NEXT(idx); ++ dev->stats.tx_bytes += skb->len; ++ dev_kfree_skb_irq(skb); ++ } ++ ++ sp->tx_csm = idx; ++ ++ return; ++} ++ ++ ++static void rx_tasklet_func(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *) data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ if (sp->unloading) { ++ return; ++ } ++ ++ if (ar231x_rx_int(dev)) { ++ tasklet_hi_schedule(&sp->rx_tasklet); ++ } else { ++ unsigned long flags; ++ spin_lock_irqsave(&sp->lock, flags); ++ sp->dma_regs->intr_ena |= DMA_STATUS_RI; ++ spin_unlock_irqrestore(&sp->lock, flags); ++ } ++} ++ ++static void rx_schedule(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ sp->dma_regs->intr_ena &= ~DMA_STATUS_RI; ++ ++ tasklet_hi_schedule(&sp->rx_tasklet); ++} ++ ++static irqreturn_t ar231x_interrupt(int irq, void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *) dev_id; ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int status, enabled; ++ ++ /* clear interrupt */ ++ /* ++ * Don't clear RI bit if currently disabled. ++ */ ++ status = sp->dma_regs->status; ++ enabled = sp->dma_regs->intr_ena; ++ sp->dma_regs->status = status & enabled; ++ ++ if (status & DMA_STATUS_NIS) { ++ /* normal status */ ++ /* ++ * Don't schedule rx processing if interrupt ++ * is already disabled. ++ */ ++ if (status & enabled & DMA_STATUS_RI) { ++ /* receive interrupt */ ++ rx_schedule(dev); ++ } ++ if (status & DMA_STATUS_TI) { ++ /* transmit interrupt */ ++ ar231x_tx_int(dev); ++ } ++ } ++ ++ /* abnormal status */ ++ if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) { ++ ar231x_restart(dev); ++ } ++ return IRQ_HANDLED; ++} ++ ++ ++static int ar231x_open(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int ethsal, ethsah; ++ ++ /* reset the hardware, in case the MAC address changed */ ++ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); ++ ++ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | ++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | ++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); ++ ++ sp->eth_regs->mac_addr[0] = ethsah; ++ sp->eth_regs->mac_addr[1] = ethsal; ++ ++ mdelay(10); ++ ++ dev->mtu = 1500; ++ netif_start_queue(dev); ++ ++ sp->eth_regs->mac_control |= MAC_CONTROL_RE; ++ ++ return 0; ++} ++ ++static void ar231x_tx_timeout(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sp->lock, flags); ++ ar231x_restart(dev); ++ spin_unlock_irqrestore(&sp->lock, flags); ++} ++ ++static void ar231x_halt(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int j; ++ ++ tasklet_disable(&sp->rx_tasklet); ++ ++ /* kill the MAC */ ++ sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */ ++ MAC_CONTROL_TE); /* disable Transmits */ ++ /* stop dma */ ++ sp->dma_regs->control = 0; ++ sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR; ++ ++ /* place phy and MAC in reset */ ++ *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy); ++ ++ /* free buffers on tx ring */ ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ struct sk_buff *skb; ++ ar231x_descr_t *txdesc; ++ ++ txdesc = &sp->tx_ring[j]; ++ txdesc->descr = 0; ++ ++ skb = sp->tx_skb[j]; ++ if (skb) { ++ dev_kfree_skb(skb); ++ sp->tx_skb[j] = NULL; ++ } ++ } ++} ++ ++/* ++ * close should do nothing. Here's why. It's called when ++ * 'ifconfig bond0 down' is run. If it calls free_irq then ++ * the irq is gone forever ! When bond0 is made 'up' again, ++ * the ar231x_open () does not call request_irq (). Worse, ++ * the call to ar231x_halt() generates a WDOG reset due to ++ * the write to 'sp->int_regs' and the box reboots. ++ * Commenting this out is good since it allows the ++ * system to resume when bond0 is made up again. ++ */ ++static int ar231x_close(struct net_device *dev) ++{ ++#if 0 ++ /* ++ * Disable interrupts ++ */ ++ disable_irq(dev->irq); ++ ++ /* ++ * Without (or before) releasing irq and stopping hardware, this ++ * is an absolute non-sense, by the way. It will be reset instantly ++ * by the first irq. ++ */ ++ netif_stop_queue(dev); ++ ++ /* stop the MAC and DMA engines */ ++ ar231x_halt(dev); ++ ++ /* release the interrupt */ ++ free_irq(dev->irq, dev); ++ ++#endif ++ return 0; ++} ++ ++static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ar231x_descr_t *td; ++ u32 idx; ++ ++ idx = sp->tx_prd; ++ td = &sp->tx_ring[idx]; ++ ++ if (td->status & DMA_TX_OWN) { ++ /* free skbuf and lie to the caller that we sent it out */ ++ dev->stats.tx_dropped++; ++ dev_kfree_skb(skb); ++ ++ /* restart transmitter in case locked */ ++ sp->dma_regs->xmt_poll = 0; ++ return 0; ++ } ++ ++ /* Setup the transmit descriptor. */ ++ td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) | ++ (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED)); ++ td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); ++ td->status = DMA_TX_OWN; ++ ++ /* kick transmitter last */ ++ sp->dma_regs->xmt_poll = 0; ++ ++ sp->tx_skb[idx] = skb; ++ idx = DSC_NEXT(idx); ++ sp->tx_prd = idx; ++ ++ return 0; ++} ++ ++static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ++{ ++ struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ int ret; ++ ++ switch (cmd) { ++ ++ case SIOCETHTOOL: ++ spin_lock_irq(&sp->lock); ++ ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data); ++ spin_unlock_irq(&sp->lock); ++ return ret; ++ ++ case SIOCSIFHWADDR: ++ if (copy_from_user ++ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) ++ return -EFAULT; ++ return 0; ++ ++ case SIOCGIFHWADDR: ++ if (copy_to_user ++ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) ++ return -EFAULT; ++ return 0; ++ ++ case SIOCGMIIPHY: ++ case SIOCGMIIREG: ++ case SIOCSMIIREG: ++ return phy_mii_ioctl(sp->phy_dev, data, cmd); ++ ++ default: ++ break; ++ } ++ ++ return -EOPNOTSUPP; ++} ++ ++static void ar231x_adjust_link(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int mc; ++ ++ if (!sp->phy_dev->link) ++ return; ++ ++ if (sp->phy_dev->duplex != sp->oldduplex) { ++ mc = readl(&sp->eth_regs->mac_control); ++ mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO); ++ if (sp->phy_dev->duplex) ++ mc |= MAC_CONTROL_F; ++ else ++ mc |= MAC_CONTROL_DRO; ++ writel(mc, &sp->eth_regs->mac_control); ++ sp->oldduplex = sp->phy_dev->duplex; ++ } ++} ++ ++#define MII_ADDR(phy, reg) \ ++ ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT)) ++ ++static int ++ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) ++{ ++ struct net_device *const dev = bus->priv; ++ struct ar231x_private *sp = netdev_priv(dev); ++ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; ++ ++ ethernet->mii_addr = MII_ADDR(phy_addr, regnum); ++ while (ethernet->mii_addr & MII_ADDR_BUSY); ++ return (ethernet->mii_data >> MII_DATA_SHIFT); ++} ++ ++static int ++ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, ++ u16 value) ++{ ++ struct net_device *const dev = bus->priv; ++ struct ar231x_private *sp = netdev_priv(dev); ++ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; ++ ++ while (ethernet->mii_addr & MII_ADDR_BUSY); ++ ethernet->mii_data = value << MII_DATA_SHIFT; ++ ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE; ++ ++ return 0; ++} ++ ++static int ar231x_mdiobus_reset(struct mii_bus *bus) ++{ ++ struct net_device *const dev = bus->priv; ++ ++ ar231x_reset_reg(dev); ++ ++ return 0; ++} ++ ++static int ar231x_mdiobus_probe (struct net_device *dev) ++{ ++ struct ar231x_private *const sp = netdev_priv(dev); ++ struct phy_device *phydev = NULL; ++ int phy_addr; ++ ++ /* find the first (lowest address) PHY on the current MAC's MII bus */ ++ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) ++ if (sp->mii_bus->phy_map[phy_addr]) { ++ phydev = sp->mii_bus->phy_map[phy_addr]; ++ sp->phy = phy_addr; ++ break; /* break out with first one found */ ++ } ++ ++ if (!phydev) { ++ printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name); ++ return -1; ++ } ++ ++ /* now we are supposed to have a proper phydev, to attach to... */ ++ BUG_ON(!phydev); ++ BUG_ON(phydev->attached_dev); ++ ++ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0, ++ PHY_INTERFACE_MODE_MII); ++ ++ if (IS_ERR(phydev)) { ++ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); ++ return PTR_ERR(phydev); ++ } ++ ++ /* mask with MAC supported features */ ++ phydev->supported &= (SUPPORTED_10baseT_Half ++ | SUPPORTED_10baseT_Full ++ | SUPPORTED_100baseT_Half ++ | SUPPORTED_100baseT_Full ++ | SUPPORTED_Autoneg ++ /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ ++ | SUPPORTED_MII ++ | SUPPORTED_TP); ++ ++ phydev->advertising = phydev->supported; ++ ++ sp->oldduplex = -1; ++ sp->phy_dev = phydev; ++ ++ printk(KERN_INFO "%s: attached PHY driver [%s] " ++ "(mii_bus:phy_addr=%s)\n", ++ dev->name, phydev->drv->name, dev_name(&phydev->dev)); ++ ++ return 0; ++} ++ +diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.h linux-2.6.39-rc7/drivers/net/ar231x.h +--- linux-2.6.39-rc7.orig/drivers/net/ar231x.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/net/ar231x.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,302 @@ ++/* ++ * ar231x.h: Linux driver for the Atheros AR231x Ethernet device. ++ * ++ * Copyright (C) 2004 by Sameer Dekate ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * Thanks to Atheros for providing hardware and documentation ++ * enabling me to write this driver. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef _AR2313_H_ ++#define _AR2313_H_ ++ ++#include ++#include ++#include ++#include ++ ++/* ++ * probe link timer - 5 secs ++ */ ++#define LINK_TIMER (5*HZ) ++ ++#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0) ++#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0) ++#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0) ++ ++#define AR2313_TX_TIMEOUT (HZ/4) ++ ++/* ++ * Rings ++ */ ++#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc)) ++#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1)) ++ ++#define AR2313_MBGET 2 ++#define AR2313_MBSET 3 ++#define AR2313_PCI_RECONFIG 4 ++#define AR2313_PCI_DUMP 5 ++#define AR2313_TEST_PANIC 6 ++#define AR2313_TEST_NULLPTR 7 ++#define AR2313_READ_DATA 8 ++#define AR2313_WRITE_DATA 9 ++#define AR2313_GET_VERSION 10 ++#define AR2313_TEST_HANG 11 ++#define AR2313_SYNC 12 ++ ++#define DMA_RX_ERR_CRC BIT(1) ++#define DMA_RX_ERR_DRIB BIT(2) ++#define DMA_RX_ERR_MII BIT(3) ++#define DMA_RX_EV2 BIT(5) ++#define DMA_RX_ERR_COL BIT(6) ++#define DMA_RX_LONG BIT(7) ++#define DMA_RX_LS BIT(8) /* last descriptor */ ++#define DMA_RX_FS BIT(9) /* first descriptor */ ++#define DMA_RX_MF BIT(10) /* multicast frame */ ++#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */ ++#define DMA_RX_ERR_LENGTH BIT(12) /* length error */ ++#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */ ++#define DMA_RX_ERROR BIT(15) /* error summary */ ++#define DMA_RX_LEN_MASK 0x3fff0000 ++#define DMA_RX_LEN_SHIFT 16 ++#define DMA_RX_FILT BIT(30) ++#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */ ++ ++#define DMA_RX1_BSIZE_MASK 0x000007ff ++#define DMA_RX1_BSIZE_SHIFT 0 ++#define DMA_RX1_CHAINED BIT(24) ++#define DMA_RX1_RER BIT(25) ++ ++#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */ ++#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */ ++#define DMA_TX_COL_MASK 0x78 ++#define DMA_TX_COL_SHIFT 3 ++#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */ ++#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */ ++#define DMA_TX_ERR_LATE BIT(9) /* late collision */ ++#define DMA_TX_ERR_LINK BIT(10) /* no carrier */ ++#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */ ++#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */ ++#define DMA_TX_ERROR BIT(15) /* frame aborted */ ++#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */ ++ ++#define DMA_TX1_BSIZE_MASK 0x000007ff ++#define DMA_TX1_BSIZE_SHIFT 0 ++#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */ ++#define DMA_TX1_TER BIT(25) /* transmit end of ring */ ++#define DMA_TX1_FS BIT(29) /* first segment */ ++#define DMA_TX1_LS BIT(30) /* last segment */ ++#define DMA_TX1_IC BIT(31) /* interrupt on completion */ ++ ++#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ ++ ++#define MAC_CONTROL_RE BIT(2) /* receive enable */ ++#define MAC_CONTROL_TE BIT(3) /* transmit enable */ ++#define MAC_CONTROL_DC BIT(5) /* Deferral check */ ++#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */ ++#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */ ++#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */ ++#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */ ++#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */ ++#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */ ++#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */ ++#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */ ++#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */ ++#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */ ++#define MAC_CONTROL_PM BIT(19) /* pass multicast */ ++#define MAC_CONTROL_F BIT(20) /* full-duplex */ ++#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */ ++#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */ ++#define MAC_CONTROL_BLE BIT(30) /* big endian mode */ ++#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */ ++ ++#define MII_ADDR_BUSY BIT(0) ++#define MII_ADDR_WRITE BIT(1) ++#define MII_ADDR_REG_SHIFT 6 ++#define MII_ADDR_PHY_SHIFT 11 ++#define MII_DATA_SHIFT 0 ++ ++#define FLOW_CONTROL_FCE BIT(1) ++ ++#define DMA_BUS_MODE_SWR BIT(0) /* software reset */ ++#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */ ++#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ ++#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */ ++ ++#define DMA_STATUS_TI BIT(0) /* transmit interrupt */ ++#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */ ++#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */ ++#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */ ++#define DMA_STATUS_UNF BIT(5) /* transmit underflow */ ++#define DMA_STATUS_RI BIT(6) /* receive interrupt */ ++#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */ ++#define DMA_STATUS_RPS BIT(8) /* receive process stopped */ ++#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */ ++#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */ ++#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */ ++#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */ ++#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */ ++#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ ++#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ ++#define DMA_STATUS_EB_SHIFT 23 /* error bits */ ++ ++#define DMA_CONTROL_SR BIT(1) /* start receive */ ++#define DMA_CONTROL_ST BIT(13) /* start transmit */ ++#define DMA_CONTROL_SF BIT(21) /* store and forward */ ++ ++ ++typedef struct { ++ volatile unsigned int status; // OWN, Device control and status. ++ volatile unsigned int devcs; // pkt Control bits + Length ++ volatile unsigned int addr; // Current Address. ++ volatile unsigned int descr; // Next descriptor in chain. ++} ar231x_descr_t; ++ ++ ++ ++// ++// New Combo structure for Both Eth0 AND eth1 ++// ++typedef struct { ++ volatile unsigned int mac_control; /* 0x00 */ ++ volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */ ++ volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */ ++ volatile unsigned int mii_addr; /* 0x14 */ ++ volatile unsigned int mii_data; /* 0x18 */ ++ volatile unsigned int flow_control; /* 0x1c */ ++ volatile unsigned int vlan_tag; /* 0x20 */ ++ volatile unsigned int pad[7]; /* 0x24 - 0x3c */ ++ volatile unsigned int ucast_table[8]; /* 0x40-0x5c */ ++ ++} ETHERNET_STRUCT; ++ ++/******************************************************************** ++ * Interrupt controller ++ ********************************************************************/ ++ ++typedef struct { ++ volatile unsigned int wdog_control; /* 0x08 */ ++ volatile unsigned int wdog_timer; /* 0x0c */ ++ volatile unsigned int misc_status; /* 0x10 */ ++ volatile unsigned int misc_mask; /* 0x14 */ ++ volatile unsigned int global_status; /* 0x18 */ ++ volatile unsigned int reserved; /* 0x1c */ ++ volatile unsigned int reset_control; /* 0x20 */ ++} INTERRUPT; ++ ++/******************************************************************** ++ * DMA controller ++ ********************************************************************/ ++typedef struct { ++ volatile unsigned int bus_mode; /* 0x00 (CSR0) */ ++ volatile unsigned int xmt_poll; /* 0x04 (CSR1) */ ++ volatile unsigned int rcv_poll; /* 0x08 (CSR2) */ ++ volatile unsigned int rcv_base; /* 0x0c (CSR3) */ ++ volatile unsigned int xmt_base; /* 0x10 (CSR4) */ ++ volatile unsigned int status; /* 0x14 (CSR5) */ ++ volatile unsigned int control; /* 0x18 (CSR6) */ ++ volatile unsigned int intr_ena; /* 0x1c (CSR7) */ ++ volatile unsigned int rcv_missed; /* 0x20 (CSR8) */ ++ volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */ ++ volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */ ++ volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */ ++} DMA; ++ ++/* ++ * Struct private for the Sibyte. ++ * ++ * Elements are grouped so variables used by the tx handling goes ++ * together, and will go into the same cache lines etc. in order to ++ * avoid cache line contention between the rx and tx handling on SMP. ++ * ++ * Frequently accessed variables are put at the beginning of the ++ * struct to help the compiler generate better/shorter code. ++ */ ++struct ar231x_private { ++ struct net_device *dev; ++ int version; ++ u32 mb[2]; ++ ++ volatile ETHERNET_STRUCT *phy_regs; ++ volatile ETHERNET_STRUCT *eth_regs; ++ volatile DMA *dma_regs; ++ volatile u32 *int_regs; ++ struct ar231x_eth *cfg; ++ ++ spinlock_t lock; /* Serialise access to device */ ++ ++ /* ++ * RX and TX descriptors, must be adjacent ++ */ ++ ar231x_descr_t *rx_ring; ++ ar231x_descr_t *tx_ring; ++ ++ ++ struct sk_buff **rx_skb; ++ struct sk_buff **tx_skb; ++ ++ /* ++ * RX elements ++ */ ++ u32 rx_skbprd; ++ u32 cur_rx; ++ ++ /* ++ * TX elements ++ */ ++ u32 tx_prd; ++ u32 tx_csm; ++ ++ /* ++ * Misc elements ++ */ ++ char name[48]; ++ struct { ++ u32 address; ++ u32 length; ++ char *mapping; ++ } desc; ++ ++ ++ struct timer_list link_timer; ++ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */ ++ unsigned short mac; ++ unsigned short link; /* 0 - link down, 1 - link up */ ++ u16 phyData; ++ ++ struct tasklet_struct rx_tasklet; ++ int unloading; ++ ++ struct phy_device *phy_dev; ++ struct mii_bus *mii_bus; ++ int oldduplex; ++}; ++ ++ ++/* ++ * Prototypes ++ */ ++static int ar231x_init(struct net_device *dev); ++#ifdef TX_TIMEOUT ++static void ar231x_tx_timeout(struct net_device *dev); ++#endif ++static int ar231x_restart(struct net_device *dev); ++static void ar231x_load_rx_ring(struct net_device *dev, int bufs); ++static irqreturn_t ar231x_interrupt(int irq, void *dev_id); ++static int ar231x_open(struct net_device *dev); ++static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev); ++static int ar231x_close(struct net_device *dev); ++static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, ++ int cmd); ++static void ar231x_init_cleanup(struct net_device *dev); ++static int ar231x_setup_timer(struct net_device *dev); ++static void ar231x_link_timer_fn(unsigned long data); ++static void ar231x_check_link(struct net_device *dev); ++#endif /* _AR2313_H_ */ +diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig linux-2.6.39-rc7/drivers/watchdog/Kconfig +--- linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/watchdog/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -990,6 +990,12 @@ + To compile this driver as a loadable module, choose M here. + The module will be called bcm63xx_wdt. + ++config ATHEROS_WDT ++ tristate "Atheros wisoc Watchdog Timer" ++ depends on ATHEROS_AR231X ++ help ++ Hardware driver for the Atheros wisoc Watchdog Timer. ++ + # PARISC Architecture + + # POWERPC Architecture +diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Makefile linux-2.6.39-rc7/drivers/watchdog/Makefile +--- linux-2.6.39-rc7.orig/drivers/watchdog/Makefile 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/watchdog/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -120,6 +120,7 @@ + obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o ++obj-$(CONFIG_ATHEROS_WDT) += ar2315-wtd.o + obj-$(CONFIG_TXX9_WDT) += txx9wdt.o + obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o + octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o +diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c +--- linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,200 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (C) 2008 John Crispin ++ * Based on EP93xx and ifxmips wdt driver ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define CLOCK_RATE 40000000 ++#define HEARTBEAT(x) (x < 1 || x > 90)?(20):(x) ++ ++static int wdt_timeout = 20; ++static int started = 0; ++static int in_use = 0; ++ ++static void ++ar2315_wdt_enable(void) ++{ ++ ar231x_write_reg(AR2315_WD, wdt_timeout * CLOCK_RATE); ++ ar231x_write_reg(AR2315_ISR, 0x80); ++} ++ ++static ssize_t ++ar2315_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) ++{ ++ if(len) ++ ar2315_wdt_enable(); ++ return len; ++} ++ ++static int ++ar2315_wdt_open(struct inode *inode, struct file *file) ++{ ++ if(in_use) ++ return -EBUSY; ++ ar2315_wdt_enable(); ++ in_use = started = 1; ++ return nonseekable_open(inode, file); ++} ++ ++static int ++ar2315_wdt_release(struct inode *inode, struct file *file) ++{ ++ in_use = 0; ++ return 0; ++} ++ ++static irqreturn_t ++ar2315_wdt_interrupt(int irq, void *dev_id) ++{ ++ if(started) ++ { ++ printk(KERN_CRIT "watchdog expired, rebooting system\n"); ++ emergency_restart(); ++ } else { ++ ar231x_write_reg(AR2315_WDC, 0); ++ ar231x_write_reg(AR2315_WD, 0); ++ ar231x_write_reg(AR2315_ISR, 0x80); ++ } ++ return IRQ_HANDLED; ++} ++ ++static struct watchdog_info ident = { ++ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, ++ .identity = "ar2315 Watchdog", ++}; ++ ++static int ++ar2315_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int new_wdt_timeout; ++ int ret = -ENOIOCTLCMD; ++ ++ switch(cmd) ++ { ++ case WDIOC_GETSUPPORT: ++ ret = copy_to_user((struct watchdog_info __user *)arg, &ident, sizeof(ident)) ? -EFAULT : 0; ++ break; ++ ++ case WDIOC_KEEPALIVE: ++ ar2315_wdt_enable(); ++ ret = 0; ++ break; ++ ++ case WDIOC_SETTIMEOUT: ++ if((ret = get_user(new_wdt_timeout, (int __user *)arg))) ++ break; ++ wdt_timeout = HEARTBEAT(new_wdt_timeout); ++ ar2315_wdt_enable(); ++ break; ++ ++ case WDIOC_GETTIMEOUT: ++ ret = put_user(wdt_timeout, (int __user *)arg); ++ break; ++ } ++ return ret; ++} ++ ++static struct file_operations ar2315_wdt_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .write = ar2315_wdt_write, ++ .unlocked_ioctl = ar2315_wdt_ioctl, ++ .open = ar2315_wdt_open, ++ .release = ar2315_wdt_release, ++}; ++ ++static struct miscdevice ar2315_wdt_miscdev = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &ar2315_wdt_fops, ++}; ++ ++static int ++ar2315_wdt_probe(struct platform_device *dev) ++{ ++ int ret = 0; ++ ++ ar2315_wdt_enable(); ++ ret = request_irq(AR531X_MISC_IRQ_WATCHDOG, ar2315_wdt_interrupt, IRQF_DISABLED, "ar2315_wdt", NULL); ++ if(ret) ++ { ++ printk(KERN_ERR "ar2315wdt: failed to register inetrrupt\n"); ++ goto out; ++ } ++ ++ ret = misc_register(&ar2315_wdt_miscdev); ++ if(ret) ++ printk(KERN_ERR "ar2315wdt: failed to register miscdev\n"); ++ ++out: ++ return ret; ++} ++ ++static int ++ar2315_wdt_remove(struct platform_device *dev) ++{ ++ misc_deregister(&ar2315_wdt_miscdev); ++ free_irq(AR531X_MISC_IRQ_WATCHDOG, NULL); ++ return 0; ++} ++ ++static struct platform_driver ar2315_wdt_driver = { ++ .probe = ar2315_wdt_probe, ++ .remove = ar2315_wdt_remove, ++ .driver = { ++ .name = "ar2315_wdt", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init ++init_ar2315_wdt(void) ++{ ++ int ret = platform_driver_register(&ar2315_wdt_driver); ++ if(ret) ++ printk(KERN_INFO "ar2315_wdt: error registering platfom driver!"); ++ return ret; ++} ++ ++static void __exit ++exit_ar2315_wdt(void) ++{ ++ platform_driver_unregister(&ar2315_wdt_driver); ++} ++ ++module_init(init_ar2315_wdt); ++module_exit(exit_ar2315_wdt); diff --git a/target/linux/patches/2.6.39.4/gemalto.patch b/target/linux/patches/2.6.39.4/gemalto.patch new file mode 100644 index 000000000..f3c223b5e --- /dev/null +++ b/target/linux/patches/2.6.39.4/gemalto.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.36.orig/drivers/tty/serial/serial_cs.c linux-2.6.36/drivers/serial/serial_cs.c +--- linux-2.6.36.orig/drivers/tty/serial/serial_cs.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/tty/serial/serial_cs.c 2010-12-13 23:03:40.000000000 +0100 +@@ -794,6 +794,7 @@ + PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025), + PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045), + PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052), ++ PCMCIA_DEVICE_MANF_CARD(0x0157, 0x0100), /* Gemalto SCR */ + PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */ + PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */ + PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae), diff --git a/target/linux/patches/2.6.39.4/mips-malta.patch b/target/linux/patches/2.6.39.4/mips-malta.patch new file mode 100644 index 000000000..cc8789dca --- /dev/null +++ b/target/linux/patches/2.6.39.4/mips-malta.patch @@ -0,0 +1,135 @@ +http://lkml.indiana.edu/hypermail/linux/kernel/1105.3/02199.html + +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/smp-ops.h linux-2.6.39/arch/mips/include/asm/smp-ops.h +--- linux-2.6.39.orig/arch/mips/include/asm/smp-ops.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/include/asm/smp-ops.h 2011-08-29 04:39:03.360480881 +0200 +@@ -56,8 +56,43 @@ + + #endif /* !CONFIG_SMP */ + +-extern struct plat_smp_ops up_smp_ops; +-extern struct plat_smp_ops cmp_smp_ops; +-extern struct plat_smp_ops vsmp_smp_ops; ++static inline int register_up_smp_ops(void) ++{ ++#ifdef CONFIG_SMP_UP ++ extern struct plat_smp_ops up_smp_ops; ++ ++ register_smp_ops(&up_smp_ops); ++ ++ return 0; ++#else ++ return -ENODEV; ++#endif ++} ++ ++static inline int register_cmp_smp_ops(void) ++{ ++#ifdef CONFIG_MIPS_CMP ++ extern struct plat_smp_ops cmp_smp_ops; ++ ++ register_smp_ops(&cmp_smp_ops); ++ ++ return 0; ++#else ++ return -ENODEV; ++#endif ++} ++ ++static inline int register_vsmp_smp_ops(void) ++{ ++#ifdef CONFIG_MIPS_MT_SMP ++ extern struct plat_smp_ops vsmp_smp_ops; ++ ++ register_smp_ops(&vsmp_smp_ops); ++ ++ return 0; ++#else ++ return -ENODEV; ++#endif ++} + + #endif /* __ASM_SMP_OPS_H */ +diff -Nur linux-2.6.39.orig/arch/mips/mipssim/sim_setup.c linux-2.6.39/arch/mips/mipssim/sim_setup.c +--- linux-2.6.39.orig/arch/mips/mipssim/sim_setup.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/mipssim/sim_setup.c 2011-08-29 04:39:03.390480572 +0200 +@@ -59,18 +59,17 @@ + + prom_meminit(); + +-#ifdef CONFIG_MIPS_MT_SMP +- if (cpu_has_mipsmt) +- register_smp_ops(&vsmp_smp_ops); +- else +- register_smp_ops(&up_smp_ops); +-#endif ++ if (cpu_has_mipsmt) { ++ if (!register_vsmp_smp_ops()) ++ return; ++ + #ifdef CONFIG_MIPS_MT_SMTC +- if (cpu_has_mipsmt) + register_smp_ops(&ssmtc_smp_ops); +- else +- register_smp_ops(&up_smp_ops); ++ return; + #endif ++ } ++ ++ register_up_smp_ops(); + } + + static void __init serial_init(void) +diff -Nur linux-2.6.39.orig/arch/mips/mti-malta/malta-init.c linux-2.6.39/arch/mips/mti-malta/malta-init.c +--- linux-2.6.39.orig/arch/mips/mti-malta/malta-init.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/mti-malta/malta-init.c 2011-08-29 04:39:03.700480601 +0200 +@@ -29,6 +29,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -358,15 +359,14 @@ + #ifdef CONFIG_SERIAL_8250_CONSOLE + console_config(); + #endif +-#ifdef CONFIG_MIPS_CMP + /* Early detection of CMP support */ + if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ)) +- register_smp_ops(&cmp_smp_ops); +- else +-#endif +-#ifdef CONFIG_MIPS_MT_SMP +- register_smp_ops(&vsmp_smp_ops); +-#endif ++ if (!register_cmp_smp_ops()) ++ return; ++ ++ if (!register_vsmp_smp_ops()) ++ return; ++ + #ifdef CONFIG_MIPS_MT_SMTC + register_smp_ops(&msmtc_smp_ops); + #endif +diff -Nur linux-2.6.39.orig/arch/mips/pmc-sierra/msp71xx/msp_setup.c linux-2.6.39/arch/mips/pmc-sierra/msp71xx/msp_setup.c +--- linux-2.6.39.orig/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2011-08-29 04:39:03.790480302 +0200 +@@ -228,13 +228,11 @@ + */ + msp_serial_setup(); + +-#ifdef CONFIG_MIPS_MT_SMP +- register_smp_ops(&vsmp_smp_ops); +-#endif +- ++ if (register_vsmp_smp_ops()) { + #ifdef CONFIG_MIPS_MT_SMTC +- register_smp_ops(&msp_smtc_smp_ops); ++ register_smp_ops(&msp_smtc_smp_ops); + #endif ++ } + + #ifdef CONFIG_PMCTWILED + /* diff --git a/target/linux/patches/2.6.39.4/mmc-host.patch b/target/linux/patches/2.6.39.4/mmc-host.patch new file mode 100644 index 000000000..3d0e37add --- /dev/null +++ b/target/linux/patches/2.6.39.4/mmc-host.patch @@ -0,0 +1,36 @@ +diff -Nur linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig linux-2.6.39-rc6/drivers/mmc/host/Kconfig +--- linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/drivers/mmc/host/Kconfig 2011-05-10 23:39:01.000000000 +0200 +@@ -253,13 +253,6 @@ + + If unsure, say N. + +-choice +- prompt "Atmel SD/MMC Driver" +- depends on AVR32 || ARCH_AT91 +- default MMC_ATMELMCI if AVR32 +- help +- Choose which driver to use for the Atmel MCI Silicon +- + config MMC_AT91 + tristate "AT91 SD/MMC Card Interface support" + depends on ARCH_AT91 +@@ -268,18 +261,6 @@ + + If unsure, say N. + +-config MMC_ATMELMCI +- tristate "Atmel Multimedia Card Interface support" +- depends on AVR32 || ARCH_AT91 +- help +- This selects the Atmel Multimedia Card Interface driver. If +- you have an AT32 (AVR32) or AT91 platform with a Multimedia +- Card slot, say Y or M here. +- +- If unsure, say N. +- +-endchoice +- + config MMC_ATMELMCI_DMA + bool "Atmel MCI DMA support (EXPERIMENTAL)" + depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45) && DMA_ENGINE && EXPERIMENTAL diff --git a/target/linux/patches/2.6.39.4/non-static.patch b/target/linux/patches/2.6.39.4/non-static.patch new file mode 100644 index 000000000..a967703d0 --- /dev/null +++ b/target/linux/patches/2.6.39.4/non-static.patch @@ -0,0 +1,33 @@ +diff -Nur linux-2.6.39-rc6.orig/fs/namei.c linux-2.6.39-rc6/fs/namei.c +--- linux-2.6.39-rc6.orig/fs/namei.c 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/fs/namei.c 2011-05-05 11:30:14.000000000 +0200 +@@ -1769,7 +1769,7 @@ + * needs parent already locked. Doesn't follow mounts. + * SMP-safe. + */ +-static struct dentry *lookup_hash(struct nameidata *nd) ++struct dentry *lookup_hash(struct nameidata *nd) + { + return __lookup_hash(&nd->last, nd->path.dentry, nd); + } +diff -Nur linux-2.6.39-rc6.orig/fs/splice.c linux-2.6.39-rc6/fs/splice.c +--- linux-2.6.39-rc6.orig/fs/splice.c 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/fs/splice.c 2011-05-05 11:31:04.000000000 +0200 +@@ -1081,7 +1081,7 @@ + /* + * Attempt to initiate a splice from pipe to file. + */ +-static long do_splice_from(struct pipe_inode_info *pipe, struct file *out, ++long do_splice_from(struct pipe_inode_info *pipe, struct file *out, + loff_t *ppos, size_t len, unsigned int flags) + { + ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, +@@ -1109,7 +1109,7 @@ + /* + * Attempt to initiate a splice from a file to a pipe. + */ +-static long do_splice_to(struct file *in, loff_t *ppos, ++long do_splice_to(struct file *in, loff_t *ppos, + struct pipe_inode_info *pipe, size_t len, + unsigned int flags) + { diff --git a/target/linux/patches/2.6.39.4/ocf-20100325.patch b/target/linux/patches/2.6.39.4/ocf-20100325.patch new file mode 100644 index 000000000..b26a65bc1 --- /dev/null +++ b/target/linux/patches/2.6.39.4/ocf-20100325.patch @@ -0,0 +1,90176 @@ +diff -Nur linux-2.6.39.orig/crypto/Kconfig linux-2.6.39/crypto/Kconfig +--- linux-2.6.39.orig/crypto/Kconfig 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/crypto/Kconfig 2011-08-01 14:38:18.000000000 +0200 +@@ -866,3 +866,6 @@ + source "drivers/crypto/Kconfig" + + endif # if CRYPTO ++ ++source "crypto/ocf/Kconfig" ++ +diff -Nur linux-2.6.39.orig/crypto/Kconfig.orig linux-2.6.39/crypto/Kconfig.orig +--- linux-2.6.39.orig/crypto/Kconfig.orig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/Kconfig.orig 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,868 @@ ++# ++# Generic algorithms support ++# ++config XOR_BLOCKS ++ tristate ++ ++# ++# async_tx api: hardware offloaded memory transfer/transform support ++# ++source "crypto/async_tx/Kconfig" ++ ++# ++# Cryptographic API Configuration ++# ++menuconfig CRYPTO ++ tristate "Cryptographic API" ++ help ++ This option provides the core Cryptographic API. ++ ++if CRYPTO ++ ++comment "Crypto core or helper" ++ ++config CRYPTO_FIPS ++ bool "FIPS 200 compliance" ++ depends on CRYPTO_ANSI_CPRNG && !CRYPTO_MANAGER_DISABLE_TESTS ++ help ++ This options enables the fips boot option which is ++ required if you want to system to operate in a FIPS 200 ++ certification. You should say no unless you know what ++ this is. ++ ++config CRYPTO_ALGAPI ++ tristate ++ select CRYPTO_ALGAPI2 ++ help ++ This option provides the API for cryptographic algorithms. ++ ++config CRYPTO_ALGAPI2 ++ tristate ++ ++config CRYPTO_AEAD ++ tristate ++ select CRYPTO_AEAD2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_AEAD2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ ++config CRYPTO_BLKCIPHER ++ tristate ++ select CRYPTO_BLKCIPHER2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_BLKCIPHER2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ select CRYPTO_RNG2 ++ select CRYPTO_WORKQUEUE ++ ++config CRYPTO_HASH ++ tristate ++ select CRYPTO_HASH2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_HASH2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ ++config CRYPTO_RNG ++ tristate ++ select CRYPTO_RNG2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_RNG2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ ++config CRYPTO_PCOMP ++ tristate ++ select CRYPTO_PCOMP2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_PCOMP2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ ++config CRYPTO_MANAGER ++ tristate "Cryptographic algorithm manager" ++ select CRYPTO_MANAGER2 ++ help ++ Create default cryptographic template instantiations such as ++ cbc(aes). ++ ++config CRYPTO_MANAGER2 ++ def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y) ++ select CRYPTO_AEAD2 ++ select CRYPTO_HASH2 ++ select CRYPTO_BLKCIPHER2 ++ select CRYPTO_PCOMP2 ++ ++config CRYPTO_MANAGER_DISABLE_TESTS ++ bool "Disable run-time self tests" ++ default y ++ depends on CRYPTO_MANAGER2 ++ help ++ Disable run-time self tests that normally take place at ++ algorithm registration. ++ ++config CRYPTO_GF128MUL ++ tristate "GF(2^128) multiplication functions (EXPERIMENTAL)" ++ help ++ Efficient table driven implementation of multiplications in the ++ field GF(2^128). This is needed by some cypher modes. This ++ option will be selected automatically if you select such a ++ cipher mode. Only select this option by hand if you expect to load ++ an external module that requires these functions. ++ ++config CRYPTO_NULL ++ tristate "Null algorithms" ++ select CRYPTO_ALGAPI ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_HASH ++ help ++ These are 'Null' algorithms, used by IPsec, which do nothing. ++ ++config CRYPTO_PCRYPT ++ tristate "Parallel crypto engine (EXPERIMENTAL)" ++ depends on SMP && EXPERIMENTAL ++ select PADATA ++ select CRYPTO_MANAGER ++ select CRYPTO_AEAD ++ help ++ This converts an arbitrary crypto algorithm into a parallel ++ algorithm that executes in kernel threads. ++ ++config CRYPTO_WORKQUEUE ++ tristate ++ ++config CRYPTO_CRYPTD ++ tristate "Software async crypto daemon" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_HASH ++ select CRYPTO_MANAGER ++ select CRYPTO_WORKQUEUE ++ help ++ This is a generic software asynchronous crypto daemon that ++ converts an arbitrary synchronous software crypto algorithm ++ into an asynchronous algorithm that executes in a kernel thread. ++ ++config CRYPTO_AUTHENC ++ tristate "Authenc support" ++ select CRYPTO_AEAD ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ select CRYPTO_HASH ++ help ++ Authenc: Combined mode wrapper for IPsec. ++ This is required for IPSec. ++ ++config CRYPTO_TEST ++ tristate "Testing module" ++ depends on m ++ select CRYPTO_MANAGER ++ help ++ Quick & dirty crypto test module. ++ ++comment "Authenticated Encryption with Associated Data" ++ ++config CRYPTO_CCM ++ tristate "CCM support" ++ select CRYPTO_CTR ++ select CRYPTO_AEAD ++ help ++ Support for Counter with CBC MAC. Required for IPsec. ++ ++config CRYPTO_GCM ++ tristate "GCM/GMAC support" ++ select CRYPTO_CTR ++ select CRYPTO_AEAD ++ select CRYPTO_GHASH ++ help ++ Support for Galois/Counter Mode (GCM) and Galois Message ++ Authentication Code (GMAC). Required for IPSec. ++ ++config CRYPTO_SEQIV ++ tristate "Sequence Number IV Generator" ++ select CRYPTO_AEAD ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_RNG ++ help ++ This IV generator generates an IV based on a sequence number by ++ xoring it with a salt. This algorithm is mainly useful for CTR ++ ++comment "Block modes" ++ ++config CRYPTO_CBC ++ tristate "CBC support" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ help ++ CBC: Cipher Block Chaining mode ++ This block cipher algorithm is required for IPSec. ++ ++config CRYPTO_CTR ++ tristate "CTR support" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_SEQIV ++ select CRYPTO_MANAGER ++ help ++ CTR: Counter mode ++ This block cipher algorithm is required for IPSec. ++ ++config CRYPTO_CTS ++ tristate "CTS support" ++ select CRYPTO_BLKCIPHER ++ help ++ CTS: Cipher Text Stealing ++ This is the Cipher Text Stealing mode as described by ++ Section 8 of rfc2040 and referenced by rfc3962. ++ (rfc3962 includes errata information in its Appendix A) ++ This mode is required for Kerberos gss mechanism support ++ for AES encryption. ++ ++config CRYPTO_ECB ++ tristate "ECB support" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ help ++ ECB: Electronic CodeBook mode ++ This is the simplest block cipher algorithm. It simply encrypts ++ the input block by block. ++ ++config CRYPTO_LRW ++ tristate "LRW support (EXPERIMENTAL)" ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ select CRYPTO_GF128MUL ++ help ++ LRW: Liskov Rivest Wagner, a tweakable, non malleable, non movable ++ narrow block cipher mode for dm-crypt. Use it with cipher ++ specification string aes-lrw-benbi, the key must be 256, 320 or 384. ++ The first 128, 192 or 256 bits in the key are used for AES and the ++ rest is used to tie each cipher block to its logical position. ++ ++config CRYPTO_PCBC ++ tristate "PCBC support" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ help ++ PCBC: Propagating Cipher Block Chaining mode ++ This block cipher algorithm is required for RxRPC. ++ ++config CRYPTO_XTS ++ tristate "XTS support (EXPERIMENTAL)" ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ select CRYPTO_GF128MUL ++ help ++ XTS: IEEE1619/D16 narrow block cipher use with aes-xts-plain, ++ key size 256, 384 or 512 bits. This implementation currently ++ can't handle a sectorsize which is not a multiple of 16 bytes. ++ ++config CRYPTO_FPU ++ tristate ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ ++comment "Hash modes" ++ ++config CRYPTO_HMAC ++ tristate "HMAC support" ++ select CRYPTO_HASH ++ select CRYPTO_MANAGER ++ help ++ HMAC: Keyed-Hashing for Message Authentication (RFC2104). ++ This is required for IPSec. ++ ++config CRYPTO_XCBC ++ tristate "XCBC support" ++ depends on EXPERIMENTAL ++ select CRYPTO_HASH ++ select CRYPTO_MANAGER ++ help ++ XCBC: Keyed-Hashing with encryption algorithm ++ http://www.ietf.org/rfc/rfc3566.txt ++ http://csrc.nist.gov/encryption/modes/proposedmodes/ ++ xcbc-mac/xcbc-mac-spec.pdf ++ ++config CRYPTO_VMAC ++ tristate "VMAC support" ++ depends on EXPERIMENTAL ++ select CRYPTO_HASH ++ select CRYPTO_MANAGER ++ help ++ VMAC is a message authentication algorithm designed for ++ very high speed on 64-bit architectures. ++ ++ See also: ++ ++ ++comment "Digest" ++ ++config CRYPTO_CRC32C ++ tristate "CRC32c CRC algorithm" ++ select CRYPTO_HASH ++ help ++ Castagnoli, et al Cyclic Redundancy-Check Algorithm. Used ++ by iSCSI for header and data digests and by others. ++ See Castagnoli93. Module will be crc32c. ++ ++config CRYPTO_CRC32C_INTEL ++ tristate "CRC32c INTEL hardware acceleration" ++ depends on X86 ++ select CRYPTO_HASH ++ help ++ In Intel processor with SSE4.2 supported, the processor will ++ support CRC32C implementation using hardware accelerated CRC32 ++ instruction. This option will create 'crc32c-intel' module, ++ which will enable any routine to use the CRC32 instruction to ++ gain performance compared with software implementation. ++ Module will be crc32c-intel. ++ ++config CRYPTO_GHASH ++ tristate "GHASH digest algorithm" ++ select CRYPTO_SHASH ++ select CRYPTO_GF128MUL ++ help ++ GHASH is message digest algorithm for GCM (Galois/Counter Mode). ++ ++config CRYPTO_MD4 ++ tristate "MD4 digest algorithm" ++ select CRYPTO_HASH ++ help ++ MD4 message digest algorithm (RFC1320). ++ ++config CRYPTO_MD5 ++ tristate "MD5 digest algorithm" ++ select CRYPTO_HASH ++ help ++ MD5 message digest algorithm (RFC1321). ++ ++config CRYPTO_MICHAEL_MIC ++ tristate "Michael MIC keyed digest algorithm" ++ select CRYPTO_HASH ++ help ++ Michael MIC is used for message integrity protection in TKIP ++ (IEEE 802.11i). This algorithm is required for TKIP, but it ++ should not be used for other purposes because of the weakness ++ of the algorithm. ++ ++config CRYPTO_RMD128 ++ tristate "RIPEMD-128 digest algorithm" ++ select CRYPTO_HASH ++ help ++ RIPEMD-128 (ISO/IEC 10118-3:2004). ++ ++ RIPEMD-128 is a 128-bit cryptographic hash function. It should only ++ to be used as a secure replacement for RIPEMD. For other use cases ++ RIPEMD-160 should be used. ++ ++ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. ++ See ++ ++config CRYPTO_RMD160 ++ tristate "RIPEMD-160 digest algorithm" ++ select CRYPTO_HASH ++ help ++ RIPEMD-160 (ISO/IEC 10118-3:2004). ++ ++ RIPEMD-160 is a 160-bit cryptographic hash function. It is intended ++ to be used as a secure replacement for the 128-bit hash functions ++ MD4, MD5 and it's predecessor RIPEMD ++ (not to be confused with RIPEMD-128). ++ ++ It's speed is comparable to SHA1 and there are no known attacks ++ against RIPEMD-160. ++ ++ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. ++ See ++ ++config CRYPTO_RMD256 ++ tristate "RIPEMD-256 digest algorithm" ++ select CRYPTO_HASH ++ help ++ RIPEMD-256 is an optional extension of RIPEMD-128 with a ++ 256 bit hash. It is intended for applications that require ++ longer hash-results, without needing a larger security level ++ (than RIPEMD-128). ++ ++ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. ++ See ++ ++config CRYPTO_RMD320 ++ tristate "RIPEMD-320 digest algorithm" ++ select CRYPTO_HASH ++ help ++ RIPEMD-320 is an optional extension of RIPEMD-160 with a ++ 320 bit hash. It is intended for applications that require ++ longer hash-results, without needing a larger security level ++ (than RIPEMD-160). ++ ++ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. ++ See ++ ++config CRYPTO_SHA1 ++ tristate "SHA1 digest algorithm" ++ select CRYPTO_HASH ++ help ++ SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2). ++ ++config CRYPTO_SHA256 ++ tristate "SHA224 and SHA256 digest algorithm" ++ select CRYPTO_HASH ++ help ++ SHA256 secure hash standard (DFIPS 180-2). ++ ++ This version of SHA implements a 256 bit hash with 128 bits of ++ security against collision attacks. ++ ++ This code also includes SHA-224, a 224 bit hash with 112 bits ++ of security against collision attacks. ++ ++config CRYPTO_SHA512 ++ tristate "SHA384 and SHA512 digest algorithms" ++ select CRYPTO_HASH ++ help ++ SHA512 secure hash standard (DFIPS 180-2). ++ ++ This version of SHA implements a 512 bit hash with 256 bits of ++ security against collision attacks. ++ ++ This code also includes SHA-384, a 384 bit hash with 192 bits ++ of security against collision attacks. ++ ++config CRYPTO_TGR192 ++ tristate "Tiger digest algorithms" ++ select CRYPTO_HASH ++ help ++ Tiger hash algorithm 192, 160 and 128-bit hashes ++ ++ Tiger is a hash function optimized for 64-bit processors while ++ still having decent performance on 32-bit processors. ++ Tiger was developed by Ross Anderson and Eli Biham. ++ ++ See also: ++ . ++ ++config CRYPTO_WP512 ++ tristate "Whirlpool digest algorithms" ++ select CRYPTO_HASH ++ help ++ Whirlpool hash algorithm 512, 384 and 256-bit hashes ++ ++ Whirlpool-512 is part of the NESSIE cryptographic primitives. ++ Whirlpool will be part of the ISO/IEC 10118-3:2003(E) standard ++ ++ See also: ++ ++ ++config CRYPTO_GHASH_CLMUL_NI_INTEL ++ tristate "GHASH digest algorithm (CLMUL-NI accelerated)" ++ depends on (X86 || UML_X86) && 64BIT ++ select CRYPTO_SHASH ++ select CRYPTO_CRYPTD ++ help ++ GHASH is message digest algorithm for GCM (Galois/Counter Mode). ++ The implementation is accelerated by CLMUL-NI of Intel. ++ ++comment "Ciphers" ++ ++config CRYPTO_AES ++ tristate "AES cipher algorithms" ++ select CRYPTO_ALGAPI ++ help ++ AES cipher algorithms (FIPS-197). AES uses the Rijndael ++ algorithm. ++ ++ Rijndael appears to be consistently a very good performer in ++ both hardware and software across a wide range of computing ++ environments regardless of its use in feedback or non-feedback ++ modes. Its key setup time is excellent, and its key agility is ++ good. Rijndael's very low memory requirements make it very well ++ suited for restricted-space environments, in which it also ++ demonstrates excellent performance. Rijndael's operations are ++ among the easiest to defend against power and timing attacks. ++ ++ The AES specifies three key sizes: 128, 192 and 256 bits ++ ++ See for more information. ++ ++config CRYPTO_AES_586 ++ tristate "AES cipher algorithms (i586)" ++ depends on (X86 || UML_X86) && !64BIT ++ select CRYPTO_ALGAPI ++ select CRYPTO_AES ++ help ++ AES cipher algorithms (FIPS-197). AES uses the Rijndael ++ algorithm. ++ ++ Rijndael appears to be consistently a very good performer in ++ both hardware and software across a wide range of computing ++ environments regardless of its use in feedback or non-feedback ++ modes. Its key setup time is excellent, and its key agility is ++ good. Rijndael's very low memory requirements make it very well ++ suited for restricted-space environments, in which it also ++ demonstrates excellent performance. Rijndael's operations are ++ among the easiest to defend against power and timing attacks. ++ ++ The AES specifies three key sizes: 128, 192 and 256 bits ++ ++ See for more information. ++ ++config CRYPTO_AES_X86_64 ++ tristate "AES cipher algorithms (x86_64)" ++ depends on (X86 || UML_X86) && 64BIT ++ select CRYPTO_ALGAPI ++ select CRYPTO_AES ++ help ++ AES cipher algorithms (FIPS-197). AES uses the Rijndael ++ algorithm. ++ ++ Rijndael appears to be consistently a very good performer in ++ both hardware and software across a wide range of computing ++ environments regardless of its use in feedback or non-feedback ++ modes. Its key setup time is excellent, and its key agility is ++ good. Rijndael's very low memory requirements make it very well ++ suited for restricted-space environments, in which it also ++ demonstrates excellent performance. Rijndael's operations are ++ among the easiest to defend against power and timing attacks. ++ ++ The AES specifies three key sizes: 128, 192 and 256 bits ++ ++ See for more information. ++ ++config CRYPTO_AES_NI_INTEL ++ tristate "AES cipher algorithms (AES-NI)" ++ depends on (X86 || UML_X86) ++ select CRYPTO_AES_X86_64 if 64BIT ++ select CRYPTO_AES_586 if !64BIT ++ select CRYPTO_CRYPTD ++ select CRYPTO_ALGAPI ++ select CRYPTO_FPU ++ help ++ Use Intel AES-NI instructions for AES algorithm. ++ ++ AES cipher algorithms (FIPS-197). AES uses the Rijndael ++ algorithm. ++ ++ Rijndael appears to be consistently a very good performer in ++ both hardware and software across a wide range of computing ++ environments regardless of its use in feedback or non-feedback ++ modes. Its key setup time is excellent, and its key agility is ++ good. Rijndael's very low memory requirements make it very well ++ suited for restricted-space environments, in which it also ++ demonstrates excellent performance. Rijndael's operations are ++ among the easiest to defend against power and timing attacks. ++ ++ The AES specifies three key sizes: 128, 192 and 256 bits ++ ++ See for more information. ++ ++ In addition to AES cipher algorithm support, the acceleration ++ for some popular block cipher mode is supported too, including ++ ECB, CBC, LRW, PCBC, XTS. The 64 bit version has additional ++ acceleration for CTR. ++ ++config CRYPTO_ANUBIS ++ tristate "Anubis cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ Anubis cipher algorithm. ++ ++ Anubis is a variable key length cipher which can use keys from ++ 128 bits to 320 bits in length. It was evaluated as a entrant ++ in the NESSIE competition. ++ ++ See also: ++ ++ ++ ++config CRYPTO_ARC4 ++ tristate "ARC4 cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ ARC4 cipher algorithm. ++ ++ ARC4 is a stream cipher using keys ranging from 8 bits to 2048 ++ bits in length. This algorithm is required for driver-based ++ WEP, but it should not be for other purposes because of the ++ weakness of the algorithm. ++ ++config CRYPTO_BLOWFISH ++ tristate "Blowfish cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ Blowfish cipher algorithm, by Bruce Schneier. ++ ++ This is a variable key length cipher which can use keys from 32 ++ bits to 448 bits in length. It's fast, simple and specifically ++ designed for use on "large microprocessors". ++ ++ See also: ++ ++ ++config CRYPTO_CAMELLIA ++ tristate "Camellia cipher algorithms" ++ depends on CRYPTO ++ select CRYPTO_ALGAPI ++ help ++ Camellia cipher algorithms module. ++ ++ Camellia is a symmetric key block cipher developed jointly ++ at NTT and Mitsubishi Electric Corporation. ++ ++ The Camellia specifies three key sizes: 128, 192 and 256 bits. ++ ++ See also: ++ ++ ++config CRYPTO_CAST5 ++ tristate "CAST5 (CAST-128) cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ The CAST5 encryption algorithm (synonymous with CAST-128) is ++ described in RFC2144. ++ ++config CRYPTO_CAST6 ++ tristate "CAST6 (CAST-256) cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ The CAST6 encryption algorithm (synonymous with CAST-256) is ++ described in RFC2612. ++ ++config CRYPTO_DES ++ tristate "DES and Triple DES EDE cipher algorithms" ++ select CRYPTO_ALGAPI ++ help ++ DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3). ++ ++config CRYPTO_FCRYPT ++ tristate "FCrypt cipher algorithm" ++ select CRYPTO_ALGAPI ++ select CRYPTO_BLKCIPHER ++ help ++ FCrypt algorithm used by RxRPC. ++ ++config CRYPTO_KHAZAD ++ tristate "Khazad cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ Khazad cipher algorithm. ++ ++ Khazad was a finalist in the initial NESSIE competition. It is ++ an algorithm optimized for 64-bit processors with good performance ++ on 32-bit processors. Khazad uses an 128 bit key size. ++ ++ See also: ++ ++ ++config CRYPTO_SALSA20 ++ tristate "Salsa20 stream cipher algorithm (EXPERIMENTAL)" ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ help ++ Salsa20 stream cipher algorithm. ++ ++ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT ++ Stream Cipher Project. See ++ ++ The Salsa20 stream cipher algorithm is designed by Daniel J. ++ Bernstein . See ++ ++config CRYPTO_SALSA20_586 ++ tristate "Salsa20 stream cipher algorithm (i586) (EXPERIMENTAL)" ++ depends on (X86 || UML_X86) && !64BIT ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ help ++ Salsa20 stream cipher algorithm. ++ ++ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT ++ Stream Cipher Project. See ++ ++ The Salsa20 stream cipher algorithm is designed by Daniel J. ++ Bernstein . See ++ ++config CRYPTO_SALSA20_X86_64 ++ tristate "Salsa20 stream cipher algorithm (x86_64) (EXPERIMENTAL)" ++ depends on (X86 || UML_X86) && 64BIT ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ help ++ Salsa20 stream cipher algorithm. ++ ++ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT ++ Stream Cipher Project. See ++ ++ The Salsa20 stream cipher algorithm is designed by Daniel J. ++ Bernstein . See ++ ++config CRYPTO_SEED ++ tristate "SEED cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ SEED cipher algorithm (RFC4269). ++ ++ SEED is a 128-bit symmetric key block cipher that has been ++ developed by KISA (Korea Information Security Agency) as a ++ national standard encryption algorithm of the Republic of Korea. ++ It is a 16 round block cipher with the key size of 128 bit. ++ ++ See also: ++ ++ ++config CRYPTO_SERPENT ++ tristate "Serpent cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ Serpent cipher algorithm, by Anderson, Biham & Knudsen. ++ ++ Keys are allowed to be from 0 to 256 bits in length, in steps ++ of 8 bits. Also includes the 'Tnepres' algorithm, a reversed ++ variant of Serpent for compatibility with old kerneli.org code. ++ ++ See also: ++ ++ ++config CRYPTO_TEA ++ tristate "TEA, XTEA and XETA cipher algorithms" ++ select CRYPTO_ALGAPI ++ help ++ TEA cipher algorithm. ++ ++ Tiny Encryption Algorithm is a simple cipher that uses ++ many rounds for security. It is very fast and uses ++ little memory. ++ ++ Xtendend Tiny Encryption Algorithm is a modification to ++ the TEA algorithm to address a potential key weakness ++ in the TEA algorithm. ++ ++ Xtendend Encryption Tiny Algorithm is a mis-implementation ++ of the XTEA algorithm for compatibility purposes. ++ ++config CRYPTO_TWOFISH ++ tristate "Twofish cipher algorithm" ++ select CRYPTO_ALGAPI ++ select CRYPTO_TWOFISH_COMMON ++ help ++ Twofish cipher algorithm. ++ ++ Twofish was submitted as an AES (Advanced Encryption Standard) ++ candidate cipher by researchers at CounterPane Systems. It is a ++ 16 round block cipher supporting key sizes of 128, 192, and 256 ++ bits. ++ ++ See also: ++ ++ ++config CRYPTO_TWOFISH_COMMON ++ tristate ++ help ++ Common parts of the Twofish cipher algorithm shared by the ++ generic c and the assembler implementations. ++ ++config CRYPTO_TWOFISH_586 ++ tristate "Twofish cipher algorithms (i586)" ++ depends on (X86 || UML_X86) && !64BIT ++ select CRYPTO_ALGAPI ++ select CRYPTO_TWOFISH_COMMON ++ help ++ Twofish cipher algorithm. ++ ++ Twofish was submitted as an AES (Advanced Encryption Standard) ++ candidate cipher by researchers at CounterPane Systems. It is a ++ 16 round block cipher supporting key sizes of 128, 192, and 256 ++ bits. ++ ++ See also: ++ ++ ++config CRYPTO_TWOFISH_X86_64 ++ tristate "Twofish cipher algorithm (x86_64)" ++ depends on (X86 || UML_X86) && 64BIT ++ select CRYPTO_ALGAPI ++ select CRYPTO_TWOFISH_COMMON ++ help ++ Twofish cipher algorithm (x86_64). ++ ++ Twofish was submitted as an AES (Advanced Encryption Standard) ++ candidate cipher by researchers at CounterPane Systems. It is a ++ 16 round block cipher supporting key sizes of 128, 192, and 256 ++ bits. ++ ++ See also: ++ ++ ++comment "Compression" ++ ++config CRYPTO_DEFLATE ++ tristate "Deflate compression algorithm" ++ select CRYPTO_ALGAPI ++ select ZLIB_INFLATE ++ select ZLIB_DEFLATE ++ help ++ This is the Deflate algorithm (RFC1951), specified for use in ++ IPSec with the IPCOMP protocol (RFC3173, RFC2394). ++ ++ You will most probably want this if using IPSec. ++ ++config CRYPTO_ZLIB ++ tristate "Zlib compression algorithm" ++ select CRYPTO_PCOMP ++ select ZLIB_INFLATE ++ select ZLIB_DEFLATE ++ select NLATTR ++ help ++ This is the zlib algorithm. ++ ++config CRYPTO_LZO ++ tristate "LZO compression algorithm" ++ select CRYPTO_ALGAPI ++ select LZO_COMPRESS ++ select LZO_DECOMPRESS ++ help ++ This is the LZO algorithm. ++ ++comment "Random Number Generation" ++ ++config CRYPTO_ANSI_CPRNG ++ tristate "Pseudo Random Number Generation for Cryptographic modules" ++ default m ++ select CRYPTO_AES ++ select CRYPTO_RNG ++ help ++ This option enables the generic pseudo random number generator ++ for cryptographic modules. Uses the Algorithm specified in ++ ANSI X9.31 A.2.4. Note that this option must be enabled if ++ CRYPTO_FIPS is selected ++ ++config CRYPTO_USER_API ++ tristate ++ ++config CRYPTO_USER_API_HASH ++ tristate "User-space interface for hash algorithms" ++ depends on NET ++ select CRYPTO_HASH ++ select CRYPTO_USER_API ++ help ++ This option enables the user-spaces interface for hash ++ algorithms. ++ ++config CRYPTO_USER_API_SKCIPHER ++ tristate "User-space interface for symmetric key cipher algorithms" ++ depends on NET ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_USER_API ++ help ++ This option enables the user-spaces interface for symmetric ++ key cipher algorithms. ++ ++source "drivers/crypto/Kconfig" ++ ++endif # if CRYPTO +diff -Nur linux-2.6.39.orig/crypto/Makefile linux-2.6.39/crypto/Makefile +--- linux-2.6.39.orig/crypto/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/crypto/Makefile 2011-08-01 14:38:18.000000000 +0200 +@@ -89,6 +89,8 @@ + obj-$(CONFIG_CRYPTO_USER_API_HASH) += algif_hash.o + obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) += algif_skcipher.o + ++obj-$(CONFIG_OCF_OCF) += ocf/ ++ + # + # generic algorithms and the async_tx api + # +diff -Nur linux-2.6.39.orig/crypto/Makefile.orig linux-2.6.39/crypto/Makefile.orig +--- linux-2.6.39.orig/crypto/Makefile.orig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/Makefile.orig 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,96 @@ ++# ++# Cryptographic API ++# ++ ++obj-$(CONFIG_CRYPTO) += crypto.o ++crypto-y := api.o cipher.o compress.o ++ ++obj-$(CONFIG_CRYPTO_WORKQUEUE) += crypto_wq.o ++ ++obj-$(CONFIG_CRYPTO_FIPS) += fips.o ++ ++crypto_algapi-$(CONFIG_PROC_FS) += proc.o ++crypto_algapi-y := algapi.o scatterwalk.o $(crypto_algapi-y) ++obj-$(CONFIG_CRYPTO_ALGAPI2) += crypto_algapi.o ++ ++obj-$(CONFIG_CRYPTO_AEAD2) += aead.o ++ ++crypto_blkcipher-y := ablkcipher.o ++crypto_blkcipher-y += blkcipher.o ++obj-$(CONFIG_CRYPTO_BLKCIPHER2) += crypto_blkcipher.o ++obj-$(CONFIG_CRYPTO_BLKCIPHER2) += chainiv.o ++obj-$(CONFIG_CRYPTO_BLKCIPHER2) += eseqiv.o ++obj-$(CONFIG_CRYPTO_SEQIV) += seqiv.o ++ ++crypto_hash-y += ahash.o ++crypto_hash-y += shash.o ++obj-$(CONFIG_CRYPTO_HASH2) += crypto_hash.o ++ ++obj-$(CONFIG_CRYPTO_PCOMP2) += pcompress.o ++ ++cryptomgr-y := algboss.o testmgr.o ++ ++obj-$(CONFIG_CRYPTO_MANAGER2) += cryptomgr.o ++obj-$(CONFIG_CRYPTO_HMAC) += hmac.o ++obj-$(CONFIG_CRYPTO_VMAC) += vmac.o ++obj-$(CONFIG_CRYPTO_XCBC) += xcbc.o ++obj-$(CONFIG_CRYPTO_NULL) += crypto_null.o ++obj-$(CONFIG_CRYPTO_MD4) += md4.o ++obj-$(CONFIG_CRYPTO_MD5) += md5.o ++obj-$(CONFIG_CRYPTO_RMD128) += rmd128.o ++obj-$(CONFIG_CRYPTO_RMD160) += rmd160.o ++obj-$(CONFIG_CRYPTO_RMD256) += rmd256.o ++obj-$(CONFIG_CRYPTO_RMD320) += rmd320.o ++obj-$(CONFIG_CRYPTO_SHA1) += sha1_generic.o ++obj-$(CONFIG_CRYPTO_SHA256) += sha256_generic.o ++obj-$(CONFIG_CRYPTO_SHA512) += sha512_generic.o ++obj-$(CONFIG_CRYPTO_WP512) += wp512.o ++obj-$(CONFIG_CRYPTO_TGR192) += tgr192.o ++obj-$(CONFIG_CRYPTO_GF128MUL) += gf128mul.o ++obj-$(CONFIG_CRYPTO_ECB) += ecb.o ++obj-$(CONFIG_CRYPTO_CBC) += cbc.o ++obj-$(CONFIG_CRYPTO_PCBC) += pcbc.o ++obj-$(CONFIG_CRYPTO_CTS) += cts.o ++obj-$(CONFIG_CRYPTO_LRW) += lrw.o ++obj-$(CONFIG_CRYPTO_XTS) += xts.o ++obj-$(CONFIG_CRYPTO_CTR) += ctr.o ++obj-$(CONFIG_CRYPTO_GCM) += gcm.o ++obj-$(CONFIG_CRYPTO_CCM) += ccm.o ++obj-$(CONFIG_CRYPTO_PCRYPT) += pcrypt.o ++obj-$(CONFIG_CRYPTO_CRYPTD) += cryptd.o ++obj-$(CONFIG_CRYPTO_DES) += des_generic.o ++obj-$(CONFIG_CRYPTO_FCRYPT) += fcrypt.o ++obj-$(CONFIG_CRYPTO_BLOWFISH) += blowfish.o ++obj-$(CONFIG_CRYPTO_TWOFISH) += twofish_generic.o ++obj-$(CONFIG_CRYPTO_TWOFISH_COMMON) += twofish_common.o ++obj-$(CONFIG_CRYPTO_SERPENT) += serpent.o ++obj-$(CONFIG_CRYPTO_AES) += aes_generic.o ++obj-$(CONFIG_CRYPTO_CAMELLIA) += camellia.o ++obj-$(CONFIG_CRYPTO_CAST5) += cast5.o ++obj-$(CONFIG_CRYPTO_CAST6) += cast6.o ++obj-$(CONFIG_CRYPTO_ARC4) += arc4.o ++obj-$(CONFIG_CRYPTO_TEA) += tea.o ++obj-$(CONFIG_CRYPTO_KHAZAD) += khazad.o ++obj-$(CONFIG_CRYPTO_ANUBIS) += anubis.o ++obj-$(CONFIG_CRYPTO_SEED) += seed.o ++obj-$(CONFIG_CRYPTO_SALSA20) += salsa20_generic.o ++obj-$(CONFIG_CRYPTO_DEFLATE) += deflate.o ++obj-$(CONFIG_CRYPTO_ZLIB) += zlib.o ++obj-$(CONFIG_CRYPTO_MICHAEL_MIC) += michael_mic.o ++obj-$(CONFIG_CRYPTO_CRC32C) += crc32c.o ++obj-$(CONFIG_CRYPTO_AUTHENC) += authenc.o authencesn.o ++obj-$(CONFIG_CRYPTO_LZO) += lzo.o ++obj-$(CONFIG_CRYPTO_RNG2) += rng.o ++obj-$(CONFIG_CRYPTO_RNG2) += krng.o ++obj-$(CONFIG_CRYPTO_ANSI_CPRNG) += ansi_cprng.o ++obj-$(CONFIG_CRYPTO_TEST) += tcrypt.o ++obj-$(CONFIG_CRYPTO_GHASH) += ghash-generic.o ++obj-$(CONFIG_CRYPTO_USER_API) += af_alg.o ++obj-$(CONFIG_CRYPTO_USER_API_HASH) += algif_hash.o ++obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) += algif_skcipher.o ++ ++# ++# generic algorithms and the async_tx api ++# ++obj-$(CONFIG_XOR_BLOCKS) += xor.o ++obj-$(CONFIG_ASYNC_CORE) += async_tx/ +diff -Nur linux-2.6.39.orig/crypto/ocf/Config.in linux-2.6.39/crypto/ocf/Config.in +--- linux-2.6.39.orig/crypto/ocf/Config.in 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/Config.in 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,36 @@ ++############################################################################# ++ ++mainmenu_option next_comment ++comment 'OCF Configuration' ++tristate 'OCF (Open Cryptograhic Framework)' CONFIG_OCF_OCF ++dep_mbool ' enable fips RNG checks (fips check on RNG data before use)' \ ++ CONFIG_OCF_FIPS $CONFIG_OCF_OCF ++dep_mbool ' enable harvesting entropy for /dev/random' \ ++ CONFIG_OCF_RANDOMHARVEST $CONFIG_OCF_OCF ++dep_tristate ' cryptodev (user space support)' \ ++ CONFIG_OCF_CRYPTODEV $CONFIG_OCF_OCF ++dep_tristate ' cryptosoft (software crypto engine)' \ ++ CONFIG_OCF_CRYPTOSOFT $CONFIG_OCF_OCF ++dep_tristate ' safenet (HW crypto engine)' \ ++ CONFIG_OCF_SAFE $CONFIG_OCF_OCF ++dep_tristate ' IXP4xx (HW crypto engine)' \ ++ CONFIG_OCF_IXP4XX $CONFIG_OCF_OCF ++dep_mbool ' Enable IXP4xx HW to perform SHA1 and MD5 hashing (very slow)' \ ++ CONFIG_OCF_IXP4XX_SHA1_MD5 $CONFIG_OCF_IXP4XX ++dep_tristate ' hifn (HW crypto engine)' \ ++ CONFIG_OCF_HIFN $CONFIG_OCF_OCF ++dep_tristate ' talitos (HW crypto engine)' \ ++ CONFIG_OCF_TALITOS $CONFIG_OCF_OCF ++dep_tristate ' pasemi (HW crypto engine)' \ ++ CONFIG_OCF_PASEMI $CONFIG_OCF_OCF ++dep_tristate ' ep80579 (HW crypto engine)' \ ++ CONFIG_OCF_EP80579 $CONFIG_OCF_OCF ++dep_tristate ' Micronas c7108 (HW crypto engine)' \ ++ CONFIG_OCF_C7108 $CONFIG_OCF_OCF ++dep_tristate ' ocfnull (does no crypto)' \ ++ CONFIG_OCF_OCFNULL $CONFIG_OCF_OCF ++dep_tristate ' ocf-bench (HW crypto in-kernel benchmark)' \ ++ CONFIG_OCF_BENCH $CONFIG_OCF_OCF ++endmenu ++ ++############################################################################# +diff -Nur linux-2.6.39.orig/crypto/ocf/Kconfig linux-2.6.39/crypto/ocf/Kconfig +--- linux-2.6.39.orig/crypto/ocf/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/Kconfig 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,119 @@ ++menu "OCF Configuration" ++ ++config OCF_OCF ++ tristate "OCF (Open Cryptograhic Framework)" ++ help ++ A linux port of the OpenBSD/FreeBSD crypto framework. ++ ++config OCF_RANDOMHARVEST ++ bool "crypto random --- harvest entropy for /dev/random" ++ depends on OCF_OCF ++ help ++ Includes code to harvest random numbers from devices that support it. ++ ++config OCF_FIPS ++ bool "enable fips RNG checks" ++ depends on OCF_OCF && OCF_RANDOMHARVEST ++ help ++ Run all RNG provided data through a fips check before ++ adding it /dev/random's entropy pool. ++ ++config OCF_CRYPTODEV ++ tristate "cryptodev (user space support)" ++ depends on OCF_OCF ++ help ++ The user space API to access crypto hardware. ++ ++config OCF_CRYPTOSOFT ++ tristate "cryptosoft (software crypto engine)" ++ depends on OCF_OCF ++ help ++ A software driver for the OCF framework that uses ++ the kernel CryptoAPI. ++ ++config OCF_SAFE ++ tristate "safenet (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ A driver for a number of the safenet Excel crypto accelerators. ++ Currently tested and working on the 1141 and 1741. ++ ++config OCF_IXP4XX ++ tristate "IXP4xx (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ XScale IXP4xx crypto accelerator driver. Requires the ++ Intel Access library. ++ ++config OCF_IXP4XX_SHA1_MD5 ++ bool "IXP4xx SHA1 and MD5 Hashing" ++ depends on OCF_IXP4XX ++ help ++ Allows the IXP4xx crypto accelerator to perform SHA1 and MD5 hashing. ++ Note: this is MUCH slower than using cryptosoft (software crypto engine). ++ ++config OCF_HIFN ++ tristate "hifn (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for various HIFN based crypto accelerators. ++ (7951, 7955, 7956, 7751, 7811) ++ ++config OCF_HIFNHIPP ++ tristate "Hifn HIPP (HW packet crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for various HIFN (HIPP) based crypto accelerators ++ (7855) ++ ++config OCF_TALITOS ++ tristate "talitos (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for Freescale's security engine (SEC/talitos). ++ ++config OCF_PASEMI ++ tristate "pasemi (HW crypto engine)" ++ depends on OCF_OCF && PPC_PASEMI ++ help ++ OCF driver for the PA Semi PWRficient DMA Engine ++ ++config OCF_EP80579 ++ tristate "ep80579 (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Intel EP80579 Integrated Processor Product Line. ++ ++config OCF_CRYPTOCTEON ++ tristate "cryptocteon (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Cavium OCTEON Processors. ++ ++config OCF_KIRKWOOD ++ tristate "kirkwood (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Marvell Kirkwood (88F6xxx) Processors. ++ ++config OCF_C7108 ++ tristate "Micronas 7108 (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Microna 7108 Cipher processors. ++ ++config OCF_OCFNULL ++ tristate "ocfnull (fake crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for measuring ipsec overheads (does no crypto) ++ ++config OCF_BENCH ++ tristate "ocf-bench (HW crypto in-kernel benchmark)" ++ depends on OCF_OCF ++ help ++ A very simple encryption test for the in-kernel interface ++ of OCF. Also includes code to benchmark the IXP Access library ++ for comparison. ++ ++endmenu +diff -Nur linux-2.6.39.orig/crypto/ocf/Makefile linux-2.6.39/crypto/ocf/Makefile +--- linux-2.6.39.orig/crypto/ocf/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/Makefile 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,124 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++OCF_OBJS = crypto.o criov.o ++ ++ifdef CONFIG_OCF_RANDOMHARVEST ++ OCF_OBJS += random.o ++endif ++ ++ifdef CONFIG_OCF_FIPS ++ OCF_OBJS += rndtest.o ++endif ++ ++# Add in autoconf.h to get #defines for CONFIG_xxx ++AUTOCONF_H=$(ROOTDIR)/modules/autoconf.h ++ifeq ($(AUTOCONF_H), $(wildcard $(AUTOCONF_H))) ++ EXTRA_CFLAGS += -include $(AUTOCONF_H) ++ export EXTRA_CFLAGS ++endif ++ ++ifndef obj ++ obj ?= . ++ _obj = subdir ++ mod-subdirs := safe hifn ixp4xx talitos ocfnull ++ export-objs += crypto.o criov.o random.o ++ list-multi += ocf.o ++ _slash := ++else ++ _obj = obj ++ _slash := / ++endif ++ ++EXTRA_CFLAGS += -I$(obj)/. ++ ++obj-$(CONFIG_OCF_OCF) += ocf.o ++obj-$(CONFIG_OCF_CRYPTODEV) += cryptodev.o ++obj-$(CONFIG_OCF_CRYPTOSOFT) += cryptosoft.o ++obj-$(CONFIG_OCF_BENCH) += ocf-bench.o ++ ++$(_obj)-$(CONFIG_OCF_SAFE) += safe$(_slash) ++$(_obj)-$(CONFIG_OCF_HIFN) += hifn$(_slash) ++$(_obj)-$(CONFIG_OCF_IXP4XX) += ixp4xx$(_slash) ++$(_obj)-$(CONFIG_OCF_TALITOS) += talitos$(_slash) ++$(_obj)-$(CONFIG_OCF_PASEMI) += pasemi$(_slash) ++$(_obj)-$(CONFIG_OCF_EP80579) += ep80579$(_slash) ++$(_obj)-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon$(_slash) ++$(_obj)-$(CONFIG_OCF_KIRKWOOD) += kirkwood$(_slash) ++$(_obj)-$(CONFIG_OCF_OCFNULL) += ocfnull$(_slash) ++$(_obj)-$(CONFIG_OCF_C7108) += c7108$(_slash) ++ ++ocf-objs := $(OCF_OBJS) ++ ++$(list-multi) dummy1: $(ocf-objs) ++ $(LD) -r -o $@ $(ocf-objs) ++ ++.PHONY: ++clean: ++ rm -f *.o *.ko .*.o.flags .*.ko.cmd .*.o.cmd .*.mod.o.cmd *.mod.c ++ rm -f */*.o */*.ko */.*.o.cmd */.*.ko.cmd */.*.mod.o.cmd */*.mod.c */.*.o.flags ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ ++# ++# release gen targets ++# ++ ++.PHONY: patch ++patch: ++ REL=`date +%Y%m%d`; \ ++ patch=ocf-linux-$$REL.patch; \ ++ patch24=ocf-linux-24-$$REL.patch; \ ++ patch26=ocf-linux-26-$$REL.patch; \ ++ ( \ ++ find . -name Makefile; \ ++ find . -name Config.in; \ ++ find . -name Kconfig; \ ++ find . -name README; \ ++ find . -name '*.[ch]' | grep -v '.mod.c'; \ ++ ) | while read t; do \ ++ diff -Nau /dev/null $$t | sed 's?^+++ \./?+++ linux/crypto/ocf/?'; \ ++ done > $$patch; \ ++ cat patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \ ++ cat patches/linux-2.6.33-ocf.patch $$patch > $$patch26 ++ ++.PHONY: tarball ++tarball: ++ REL=`date +%Y%m%d`; RELDIR=/tmp/ocf-linux-$$REL; \ ++ CURDIR=`pwd`; \ ++ rm -rf /tmp/ocf-linux-$$REL*; \ ++ mkdir -p $$RELDIR/tools; \ ++ cp README* $$RELDIR; \ ++ cp patches/openss*.patch $$RELDIR; \ ++ cp patches/crypto-tools.patch $$RELDIR; \ ++ cp tools/[!C]* $$RELDIR/tools; \ ++ cd ..; \ ++ tar cvf $$RELDIR/ocf-linux.tar \ ++ --exclude=CVS \ ++ --exclude=.* \ ++ --exclude=*.o \ ++ --exclude=*.ko \ ++ --exclude=*.mod.* \ ++ --exclude=README* \ ++ --exclude=ocf-*.patch \ ++ --exclude=ocf/patches/openss*.patch \ ++ --exclude=ocf/patches/crypto-tools.patch \ ++ --exclude=ocf/tools \ ++ ocf; \ ++ gzip -9 $$RELDIR/ocf-linux.tar; \ ++ cd /tmp; \ ++ tar cvf ocf-linux-$$REL.tar ocf-linux-$$REL; \ ++ gzip -9 ocf-linux-$$REL.tar; \ ++ cd $$CURDIR/../../user; \ ++ rm -rf /tmp/crypto-tools-$$REL*; \ ++ tar cvf /tmp/crypto-tools-$$REL.tar \ ++ --exclude=CVS \ ++ --exclude=.* \ ++ --exclude=*.o \ ++ --exclude=cryptotest \ ++ --exclude=cryptokeytest \ ++ crypto-tools; \ ++ gzip -9 /tmp/crypto-tools-$$REL.tar ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/README linux-2.6.39/crypto/ocf/README +--- linux-2.6.39.orig/crypto/ocf/README 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/README 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,167 @@ ++README - ocf-linux-20100325 ++--------------------------- ++ ++This README provides instructions for getting ocf-linux compiled and ++operating in a generic linux environment. For other information you ++might like to visit the home page for this project: ++ ++ http://ocf-linux.sourceforge.net/ ++ ++Adding OCF to linux ++------------------- ++ ++ Not much in this file for now, just some notes. I usually build ++ the ocf support as modules but it can be built into the kernel as ++ well. To use it: ++ ++ * mknod /dev/crypto c 10 70 ++ ++ * to add OCF to your kernel source, you have two options. Apply ++ the kernel specific patch: ++ ++ cd linux-2.4*; gunzip < ocf-linux-24-XXXXXXXX.patch.gz | patch -p1 ++ cd linux-2.6*; gunzip < ocf-linux-26-XXXXXXXX.patch.gz | patch -p1 ++ ++ if you do one of the above, then you can proceed to the next step, ++ or you can do the above process by hand with using the patches against ++ linux-2.4.35 and 2.6.33 to include the ocf code under crypto/ocf. ++ Here's how to add it: ++ ++ for 2.4.35 (and later) ++ ++ cd linux-2.4.35/crypto ++ tar xvzf ocf-linux.tar.gz ++ cd .. ++ patch -p1 < crypto/ocf/patches/linux-2.4.35-ocf.patch ++ ++ for 2.6.23 (and later), find the kernel patch specific (or nearest) ++ to your kernel versions and then: ++ ++ cd linux-2.6.NN/crypto ++ tar xvzf ocf-linux.tar.gz ++ cd .. ++ patch -p1 < crypto/ocf/patches/linux-2.6.NN-ocf.patch ++ ++ It should be easy to take this patch and apply it to other more ++ recent versions of the kernels. The same patches should also work ++ relatively easily on kernels as old as 2.6.11 and 2.4.18. ++ ++ * under 2.4 if you are on a non-x86 platform, you may need to: ++ ++ cp linux-2.X.x/include/asm-i386/kmap_types.h linux-2.X.x/include/asm-YYY ++ ++ so that you can build the kernel crypto support needed for the cryptosoft ++ driver. ++ ++ * For simplicity you should enable all the crypto support in your kernel ++ except for the test driver. Likewise for the OCF options. Do not ++ enable OCF crypto drivers for HW that you do not have (for example ++ ixp4xx will not compile on non-Xscale systems). ++ ++ * make sure that cryptodev.h (from ocf-linux.tar.gz) is installed as ++ crypto/cryptodev.h in an include directory that is used for building ++ applications for your platform. For example on a host system that ++ might be: ++ ++ /usr/include/crypto/cryptodev.h ++ ++ * patch your openssl-0.9.8n code with the openssl-0.9.8n.patch. ++ (NOTE: there is no longer a need to patch ssh). The patch is against: ++ openssl-0_9_8e ++ ++ If you need a patch for an older version of openssl, you should look ++ to older OCF releases. This patch is unlikely to work on older ++ openssl versions. ++ ++ openssl-0.9.8n.patch ++ - enables --with-cryptodev for non BSD systems ++ - adds -cpu option to openssl speed for calculating CPU load ++ under linux ++ - fixes null pointer in openssl speed multi thread output. ++ - fixes test keys to work with linux crypto's more stringent ++ key checking. ++ - adds MD5/SHA acceleration (Ronen Shitrit), only enabled ++ with the --with-cryptodev-digests option ++ - fixes bug in engine code caching. ++ ++ * build crypto-tools-XXXXXXXX.tar.gz if you want to try some of the BSD ++ tools for testing OCF (ie., cryptotest). ++ ++How to load the OCF drivers ++--------------------------- ++ ++ First insert the base modules: ++ ++ insmod ocf ++ insmod cryptodev ++ ++ You can then install the software OCF driver with: ++ ++ insmod cryptosoft ++ ++ and one or more of the OCF HW drivers with: ++ ++ insmod safe ++ insmod hifn7751 ++ insmod ixp4xx ++ ... ++ ++ all the drivers take a debug option to enable verbose debug so that ++ you can see what is going on. For debug you load them as: ++ ++ insmod ocf crypto_debug=1 ++ insmod cryptodev cryptodev_debug=1 ++ insmod cryptosoft swcr_debug=1 ++ ++ You may load more than one OCF crypto driver but then there is no guarantee ++ as to which will be used. ++ ++ You can also enable debug at run time on 2.6 systems with the following: ++ ++ echo 1 > /sys/module/ocf/parameters/crypto_debug ++ echo 1 > /sys/module/cryptodev/parameters/cryptodev_debug ++ echo 1 > /sys/module/cryptosoft/parameters/swcr_debug ++ echo 1 > /sys/module/hifn7751/parameters/hifn_debug ++ echo 1 > /sys/module/safe/parameters/safe_debug ++ echo 1 > /sys/module/ixp4xx/parameters/ixp_debug ++ ... ++ ++Testing the OCF support ++----------------------- ++ ++ run "cryptotest", it should do a short test for a couple of ++ des packets. If it does everything is working. ++ ++ If this works, then ssh will use the driver when invoked as: ++ ++ ssh -c 3des username@host ++ ++ to see for sure that it is operating, enable debug as defined above. ++ ++ To get a better idea of performance run: ++ ++ cryptotest 100 4096 ++ ++ There are more options to cryptotest, see the help. ++ ++ It is also possible to use openssl to test the speed of the crypto ++ drivers. ++ ++ openssl speed -evp des -engine cryptodev -elapsed ++ openssl speed -evp des3 -engine cryptodev -elapsed ++ openssl speed -evp aes128 -engine cryptodev -elapsed ++ ++ and multiple threads (10) with: ++ ++ openssl speed -evp des -engine cryptodev -elapsed -multi 10 ++ openssl speed -evp des3 -engine cryptodev -elapsed -multi 10 ++ openssl speed -evp aes128 -engine cryptodev -elapsed -multi 10 ++ ++ for public key testing you can try: ++ ++ cryptokeytest ++ openssl speed -engine cryptodev rsa -elapsed ++ openssl speed -engine cryptodev dsa -elapsed ++ ++David McCullough ++david_mccullough@mcafee.com +diff -Nur linux-2.6.39.orig/crypto/ocf/c7108/Makefile linux-2.6.39/crypto/ocf/c7108/Makefile +--- linux-2.6.39.orig/crypto/ocf/c7108/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/c7108/Makefile 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_C7108) += aes-7108.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/c7108/aes-7108.c linux-2.6.39/crypto/ocf/c7108/aes-7108.c +--- linux-2.6.39.orig/crypto/ocf/c7108/aes-7108.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/c7108/aes-7108.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,839 @@ ++/* ++ * Copyright (C) 2006 Micronas USA ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Runtime mode */ ++static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; ++//static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; ++ ++static int32_t c7108_id = -1; ++static struct cipher_7108 **c7108_sessions = NULL; ++static u_int32_t c7108_sesnum = 0; ++static unsigned long iobar; ++ ++/* Crypto entry points */ ++static int c7108_process(void *, struct cryptop *, int); ++static int c7108_newsession(void *, u_int32_t *, struct cryptoini *); ++static int c7108_freesession(void *, u_int64_t); ++ ++/* Globals */ ++static int debug = 0; ++static spinlock_t csr_mutex; ++ ++/* Generic controller-based lock */ ++#define AES_LOCK()\ ++ spin_lock(&csr_mutex) ++#define AES_UNLOCK()\ ++ spin_unlock(&csr_mutex) ++ ++/* 7108 AES register access */ ++#define c7108_reg_wr8(a,d) iowrite8(d, (void*)(iobar+(a))) ++#define c7108_reg_wr16(a,d) iowrite16(d, (void*)(iobar+(a))) ++#define c7108_reg_wr32(a,d) iowrite32(d, (void*)(iobar+(a))) ++#define c7108_reg_rd8(a) ioread8((void*)(iobar+(a))) ++#define c7108_reg_rd16(a) ioread16((void*)(iobar+(a))) ++#define c7108_reg_rd32(a) ioread32((void*)(iobar+(a))) ++ ++static int ++c7108_xlate_key(int klen, u8* k8ptr, u32* k32ptr) ++{ ++ int i, nw=0; ++ nw = ((klen >= 256) ? 8 : (klen >= 192) ? 6 : 4); ++ for ( i = 0; i < nw; i++) { ++ k32ptr[i] = (k8ptr[i+3] << 24) | (k8ptr[i+2] << 16) | ++ (k8ptr[i+1] << 8) | k8ptr[i]; ++ ++ } ++ return 0; ++} ++ ++static int ++c7108_cache_key(int klen, u32* k32ptr, u8* k8ptr) ++{ ++ int i, nb=0; ++ u8* ptr = (u8*)k32ptr; ++ nb = ((klen >= 256) ? 32 : (klen >= 192) ? 24 : 16); ++ for ( i = 0; i < nb; i++) ++ k8ptr[i] = ptr[i]; ++ return 0; ++} ++ ++static int ++c7108_aes_setup_dma(u32 src, u32 dst, u32 len) ++{ ++ if (len < 16) { ++ printk("len < 16\n"); ++ return -10; ++ } ++ if (len % 16) { ++ printk("len not multiple of 16\n"); ++ return -11; ++ } ++ c7108_reg_wr16(C7108_AES_DMA_SRC0_LO, (u16) src); ++ c7108_reg_wr16(C7108_AES_DMA_SRC0_HI, (u16)((src & 0xffff0000) >> 16)); ++ c7108_reg_wr16(C7108_AES_DMA_DST0_LO, (u16) dst); ++ c7108_reg_wr16(C7108_AES_DMA_DST0_HI, (u16)((dst & 0xffff0000) >> 16)); ++ c7108_reg_wr16(C7108_AES_DMA_LEN, (u16) ((len / 16) - 1)); ++ ++ return 0; ++} ++ ++static int ++c7108_aes_set_hw_iv(u8 iv[16]) ++{ ++ c7108_reg_wr16(C7108_AES_IV0_LO, (u16) ((iv[1] << 8) | iv[0])); ++ c7108_reg_wr16(C7108_AES_IV0_HI, (u16) ((iv[3] << 8) | iv[2])); ++ c7108_reg_wr16(C7108_AES_IV1_LO, (u16) ((iv[5] << 8) | iv[4])); ++ c7108_reg_wr16(C7108_AES_IV1_HI, (u16) ((iv[7] << 8) | iv[6])); ++ c7108_reg_wr16(C7108_AES_IV2_LO, (u16) ((iv[9] << 8) | iv[8])); ++ c7108_reg_wr16(C7108_AES_IV2_HI, (u16) ((iv[11] << 8) | iv[10])); ++ c7108_reg_wr16(C7108_AES_IV3_LO, (u16) ((iv[13] << 8) | iv[12])); ++ c7108_reg_wr16(C7108_AES_IV3_HI, (u16) ((iv[15] << 8) | iv[14])); ++ ++ return 0; ++} ++ ++static void ++c7108_aes_read_dkey(u32 * dkey) ++{ ++ dkey[0] = (c7108_reg_rd16(C7108_AES_EKEY0_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY0_LO); ++ dkey[1] = (c7108_reg_rd16(C7108_AES_EKEY1_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY1_LO); ++ dkey[2] = (c7108_reg_rd16(C7108_AES_EKEY2_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY2_LO); ++ dkey[3] = (c7108_reg_rd16(C7108_AES_EKEY3_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY3_LO); ++ dkey[4] = (c7108_reg_rd16(C7108_AES_EKEY4_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY4_LO); ++ dkey[5] = (c7108_reg_rd16(C7108_AES_EKEY5_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY5_LO); ++ dkey[6] = (c7108_reg_rd16(C7108_AES_EKEY6_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY6_LO); ++ dkey[7] = (c7108_reg_rd16(C7108_AES_EKEY7_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY7_LO); ++} ++ ++static int ++c7108_aes_cipher(int op, ++ u32 dst, ++ u32 src, ++ u32 len, ++ int klen, ++ u16 mode, ++ u32 key[8], ++ u8 iv[16]) ++{ ++ int rv = 0, cnt=0; ++ u16 ctrl = 0, stat = 0; ++ ++ AES_LOCK(); ++ ++ /* Setup key length */ ++ if (klen == 128) { ++ ctrl |= C7108_AES_KEY_LEN_128; ++ } else if (klen == 192) { ++ ctrl |= C7108_AES_KEY_LEN_192; ++ } else if (klen == 256) { ++ ctrl |= C7108_AES_KEY_LEN_256; ++ } else { ++ AES_UNLOCK(); ++ return -3; ++ } ++ ++ /* Check opcode */ ++ if (C7108_AES_ENCRYPT == op) { ++ ctrl |= C7108_AES_ENCRYPT; ++ } else if (C7108_AES_DECRYPT == op) { ++ ctrl |= C7108_AES_DECRYPT; ++ } else { ++ AES_UNLOCK(); ++ return -4; ++ } ++ ++ /* check mode */ ++ if ( (mode != C7108_AES_CTRL_MODE_CBC) && ++ (mode != C7108_AES_CTRL_MODE_CFB) && ++ (mode != C7108_AES_CTRL_MODE_OFB) && ++ (mode != C7108_AES_CTRL_MODE_CTR) && ++ (mode != C7108_AES_CTRL_MODE_ECB) ) { ++ AES_UNLOCK(); ++ return -5; ++ } ++ ++ /* Now set mode */ ++ ctrl |= mode; ++ ++ /* For CFB, OFB, and CTR, neither backward key ++ * expansion nor key inversion is required. ++ */ ++ if ( (C7108_AES_DECRYPT == op) && ++ (C7108_AES_CTRL_MODE_CBC == mode || ++ C7108_AES_CTRL_MODE_ECB == mode ) ){ ++ ++ /* Program Key */ ++ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[4]); ++ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[4] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[5]); ++ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[5] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[6]); ++ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[6] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[7] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[2]); ++ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[2] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[3]); ++ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[3] >> 16)); ++ ++ ++ if (192 == klen) { ++ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[7] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[7] >> 16)); ++ ++ } else if (256 == klen) { ++ /* 256 */ ++ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[0]); ++ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[0] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[1]); ++ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[1] >> 16)); ++ ++ } ++ ++ } else { ++ /* Program Key */ ++ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[0]); ++ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[0] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[1]); ++ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[1] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[2]); ++ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[2] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[3]); ++ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[3] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[4]); ++ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[4] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[5]); ++ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[5] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[6]); ++ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[6] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[7] >> 16)); ++ ++ } ++ ++ /* Set IV always */ ++ c7108_aes_set_hw_iv(iv); ++ ++ /* Program DMA addresses */ ++ if ((rv = c7108_aes_setup_dma(src, dst, len)) < 0) { ++ AES_UNLOCK(); ++ return rv; ++ } ++ ++ ++ /* Start AES cipher */ ++ c7108_reg_wr16(C7108_AES_CTRL, ctrl | C7108_AES_GO); ++ ++ //printk("Ctrl: 0x%x\n", ctrl | C7108_AES_GO); ++ do { ++ /* TODO: interrupt mode */ ++ // printk("aes_stat=0x%x\n", stat); ++ //udelay(100); ++ } while ((cnt++ < 1000000) && ++ !((stat=c7108_reg_rd16(C7108_AES_CTRL))&C7108_AES_OP_DONE)); ++ ++ ++ if ((mode == C7108_AES_CTRL_MODE_ECB)|| ++ (mode == C7108_AES_CTRL_MODE_CBC)) { ++ /* Save out key when the lock is held ... */ ++ c7108_aes_read_dkey(key); ++ } ++ ++ AES_UNLOCK(); ++ return 0; ++ ++} ++ ++/* ++ * Generate a new crypto device session. ++ */ ++static int ++c7108_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct cipher_7108 **swd; ++ u_int32_t i; ++ char *algo; ++ int mode, xfm_type; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (c7108_sessions) { ++ for (i = 1; i < c7108_sesnum; i++) ++ if (c7108_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (c7108_sessions == NULL || i == c7108_sesnum) { ++ if (c7108_sessions == NULL) { ++ i = 1; /* We leave c7108_sessions[0] empty */ ++ c7108_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ c7108_sesnum *= 2; ++ ++ swd = kmalloc(c7108_sesnum * sizeof(struct cipher_7108 *), ++ GFP_ATOMIC); ++ if (swd == NULL) { ++ /* Reset session number */ ++ if (c7108_sesnum == CRYPTO_SW_SESSIONS) ++ c7108_sesnum = 0; ++ else ++ c7108_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(swd, 0, c7108_sesnum * sizeof(struct cipher_7108 *)); ++ ++ /* Copy existing sessions */ ++ if (c7108_sessions) { ++ memcpy(swd, c7108_sessions, ++ (c7108_sesnum / 2) * sizeof(struct cipher_7108 *)); ++ kfree(c7108_sessions); ++ } ++ ++ c7108_sessions = swd; ++ ++ } ++ ++ swd = &c7108_sessions[i]; ++ *sid = i; ++ ++ while (cri) { ++ *swd = (struct cipher_7108 *) ++ kmalloc(sizeof(struct cipher_7108), GFP_ATOMIC); ++ if (*swd == NULL) { ++ c7108_freesession(NULL, i); ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(*swd, 0, sizeof(struct cipher_7108)); ++ ++ algo = NULL; ++ mode = 0; ++ xfm_type = HW_TYPE_CIPHER; ++ ++ switch (cri->cri_alg) { ++ ++ case CRYPTO_AES_CBC: ++ algo = "aes"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; ++ break; ++#if 0 ++ case CRYPTO_AES_CTR: ++ algo = "aes_ctr"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; ++ break; ++ case CRYPTO_AES_ECB: ++ algo = "aes_ecb"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_ECB; ++ break; ++ case CRYPTO_AES_OFB: ++ algo = "aes_ofb"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_OFB; ++ break; ++ case CRYPTO_AES_CFB: ++ algo = "aes_cfb"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_CFB; ++ break; ++#endif ++ default: ++ printk("unsupported crypto algorithm: %d\n", ++ cri->cri_alg); ++ return -EINVAL; ++ break; ++ } ++ ++ ++ if (!algo || !*algo) { ++ printk("cypher_7108_crypto: Unknown algo 0x%x\n", ++ cri->cri_alg); ++ c7108_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ if (xfm_type == HW_TYPE_CIPHER) { ++ if (debug) { ++ dprintk("%s key:", __FUNCTION__); ++ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) ++ dprintk("%s0x%02x", (i % 8) ? " " : "\n ", ++ cri->cri_key[i]); ++ dprintk("\n"); ++ } ++ ++ } else if (xfm_type == SW_TYPE_HMAC || ++ xfm_type == SW_TYPE_HASH) { ++ printk("cypher_7108_crypto: HMAC unsupported!\n"); ++ return -EINVAL; ++ c7108_freesession(NULL, i); ++ } else { ++ printk("cypher_7108_crypto: " ++ "Unhandled xfm_type %d\n", xfm_type); ++ c7108_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ (*swd)->cri_alg = cri->cri_alg; ++ (*swd)->xfm_type = xfm_type; ++ ++ cri = cri->cri_next; ++ swd = &((*swd)->next); ++ } ++ return 0; ++} ++ ++/* ++ * Free a session. ++ */ ++static int ++c7108_freesession(void *arg, u_int64_t tid) ++{ ++ struct cipher_7108 *swd; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > c7108_sesnum || c7108_sessions == NULL || ++ c7108_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ while ((swd = c7108_sessions[sid]) != NULL) { ++ c7108_sessions[sid] = swd->next; ++ kfree(swd); ++ } ++ return 0; ++} ++ ++/* ++ * Process a hardware request. ++ */ ++static int ++c7108_process(void *arg, struct cryptop *crp, int hint) ++{ ++ struct cryptodesc *crd; ++ struct cipher_7108 *sw; ++ u_int32_t lid; ++ int type; ++ u32 hwkey[8]; ++ ++#define SCATTERLIST_MAX 16 ++ struct scatterlist sg[SCATTERLIST_MAX]; ++ int sg_num, sg_len, skip; ++ struct sk_buff *skb = NULL; ++ struct uio *uiop = NULL; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= c7108_sesnum || lid == 0 || c7108_sessions == NULL || ++ c7108_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ /* ++ * do some error checking outside of the loop for SKB and IOV ++ * processing this leaves us with valid skb or uiop pointers ++ * for later ++ */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ skb = (struct sk_buff *) crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { ++ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", ++ __FILE__, __LINE__, ++ skb_shinfo(skb)->nr_frags); ++ goto done; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ uiop = (struct uio *) crp->crp_buf; ++ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { ++ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", ++ __FILE__, __LINE__, ++ uiop->uio_iovcnt); ++ goto done; ++ } ++ } ++ ++ /* Go through crypto descriptors, processing as we go */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ /* ++ * Find the crypto context. ++ * ++ * XXX Note that the logic here prevents us from having ++ * XXX the same algorithm multiple times in a session ++ * XXX (or rather, we can but it won't give us the right ++ * XXX results). To do that, we'd need some way of differentiating ++ * XXX between the various instances of an algorithm (so we can ++ * XXX locate the correct crypto context). ++ */ ++ for (sw = c7108_sessions[lid]; ++ sw && sw->cri_alg != crd->crd_alg; ++ sw = sw->next) ++ ; ++ ++ /* No such context ? */ ++ if (sw == NULL) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ skip = crd->crd_skip; ++ ++ /* ++ * setup the SG list skip from the start of the buffer ++ */ ++ memset(sg, 0, sizeof(sg)); ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ int i, len; ++ type = CRYPTO_BUF_SKBUF; ++ ++ sg_num = 0; ++ sg_len = 0; ++ ++ if (skip < skb_headlen(skb)) { ++ //sg[sg_num].page = virt_to_page(skb->data + skip); ++ //sg[sg_num].offset = offset_in_page(skb->data + skip); ++ len = skb_headlen(skb) - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ //sg[sg_num].length = len; ++ sg_set_page(&sg[sg_num], virt_to_page(skb->data + skip), len, offset_in_page(skb->data + skip)); ++ sg_len += sg[sg_num].length; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_headlen(skb); ++ ++ for (i = 0; sg_len < crd->crd_len && ++ i < skb_shinfo(skb)->nr_frags && ++ sg_num < SCATTERLIST_MAX; i++) { ++ if (skip < skb_shinfo(skb)->frags[i].size) { ++ //sg[sg_num].page = skb_shinfo(skb)->frags[i].page; ++ //sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip; ++ len = skb_shinfo(skb)->frags[i].size - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ //sg[sg_num].length = len; ++ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, len, skb_shinfo(skb)->frags[i].page_offset + skip); ++ sg_len += sg[sg_num].length; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_shinfo(skb)->frags[i].size; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ int len; ++ type = CRYPTO_BUF_IOV; ++ sg_len = 0; ++ for (sg_num = 0; sg_len < crd->crd_len && ++ sg_num < uiop->uio_iovcnt && ++ sg_num < SCATTERLIST_MAX; sg_num++) { ++ if (skip < uiop->uio_iov[sg_num].iov_len) { ++ //sg[sg_num].page = virt_to_page(uiop->uio_iov[sg_num].iov_base+skip); ++ //sg[sg_num].offset = offset_in_page(uiop->uio_iov[sg_num].iov_base+skip); ++ len = uiop->uio_iov[sg_num].iov_len - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ //sg[sg_num].length = len; ++ sg_set_page(&sg[sg_num], virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), len, offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); ++ sg_len += sg[sg_num].length; ++ skip = 0; ++ } else ++ skip -= uiop->uio_iov[sg_num].iov_len; ++ } ++ } else { ++ type = CRYPTO_BUF_CONTIG; ++ //sg[0].page = virt_to_page(crp->crp_buf + skip); ++ //sg[0].offset = offset_in_page(crp->crp_buf + skip); ++ sg_len = (crp->crp_ilen - skip); ++ if (sg_len > crd->crd_len) ++ sg_len = crd->crd_len; ++ //sg[0].length = sg_len; ++ sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip)); ++ sg_num = 1; ++ } ++ ++ ++ switch (sw->xfm_type) { ++ ++ case HW_TYPE_CIPHER: { ++ ++ unsigned char iv[64]; ++ unsigned char *ivp = iv; ++ int i; ++ int ivsize = 16; /* fixed for AES */ ++ int blocksize = 16; /* fixed for AES */ ++ ++ if (sg_len < blocksize) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL len %d < %d\n", ++ __FILE__, __LINE__, ++ sg_len, ++ blocksize); ++ goto done; ++ } ++ ++ if (ivsize > sizeof(iv)) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ get_random_bytes(ivp, ivsize); ++ } ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_buf, ++ crd->crd_inject, ++ ivsize, ++ (caddr_t)ivp); ++ } ++ ++ c7108_xlate_key(crd->crd_klen, ++ (u8*)crd->crd_key, (u32*)hwkey); ++ ++ /* Encrypt SG list */ ++ for (i = 0; i < sg_num; i++) { ++ sg[i].dma_address = ++ dma_map_single(NULL, ++ kmap(sg_page(&sg[i])) + sg[i].offset, sg_len, DMA_BIDIRECTIONAL); ++#if 0 ++ printk("sg[%d]:0x%08x, off 0x%08x " ++ "kmap 0x%08x phys 0x%08x\n", ++ i, sg[i].page, sg[i].offset, ++ kmap(sg[i].page) + sg[i].offset, ++ sg[i].dma_address); ++#endif ++ c7108_aes_cipher(C7108_AES_ENCRYPT, ++ sg[i].dma_address, ++ sg[i].dma_address, ++ sg_len, ++ crd->crd_klen, ++ c7108_crypto_mode, ++ hwkey, ++ ivp); ++ ++ if ((c7108_crypto_mode == C7108_AES_CTRL_MODE_CBC)|| ++ (c7108_crypto_mode == C7108_AES_CTRL_MODE_ECB)) { ++ /* Read back expanded key and cache it in key ++ * context. ++ * NOTE: for ECB/CBC modes only (not CTR, CFB, OFB) ++ * where you set the key once. ++ */ ++ c7108_cache_key(crd->crd_klen, ++ (u32*)hwkey, (u8*)crd->crd_key); ++#if 0 ++ printk("%s expanded key:", __FUNCTION__); ++ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) ++ printk("%s0x%02x", (i % 8) ? " " : "\n ", ++ crd->crd_key[i]); ++ printk("\n"); ++#endif ++ } ++ } ++ } ++ else { /*decrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ crypto_copydata(crp->crp_buf, crd->crd_inject, ++ ivsize, (caddr_t)ivp); ++ } ++ ++ c7108_xlate_key(crd->crd_klen, ++ (u8*)crd->crd_key, (u32*)hwkey); ++ ++ /* Decrypt SG list */ ++ for (i = 0; i < sg_num; i++) { ++ sg[i].dma_address = ++ dma_map_single(NULL, ++ kmap(sg_page(&sg[i])) + sg[i].offset, ++ sg_len, DMA_BIDIRECTIONAL); ++ ++#if 0 ++ printk("sg[%d]:0x%08x, off 0x%08x " ++ "kmap 0x%08x phys 0x%08x\n", ++ i, sg[i].page, sg[i].offset, ++ kmap(sg[i].page) + sg[i].offset, ++ sg[i].dma_address); ++#endif ++ c7108_aes_cipher(C7108_AES_DECRYPT, ++ sg[i].dma_address, ++ sg[i].dma_address, ++ sg_len, ++ crd->crd_klen, ++ c7108_crypto_mode, ++ hwkey, ++ ivp); ++ } ++ } ++ } break; ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ crp->crp_etype = EINVAL; ++ goto done; ++ break; ++ ++ case SW_TYPE_COMP: ++ crp->crp_etype = EINVAL; ++ goto done; ++ break; ++ ++ default: ++ /* Unknown/unsupported algorithm */ ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ } ++ ++done: ++ crypto_done(crp); ++ return 0; ++} ++ ++static struct { ++ softc_device_decl sc_dev; ++} a7108dev; ++ ++static device_method_t a7108_methods = { ++/* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, c7108_newsession), ++ DEVMETHOD(cryptodev_freesession, c7108_freesession), ++ DEVMETHOD(cryptodev_process, c7108_process), ++ DEVMETHOD(cryptodev_kprocess, NULL) ++}; ++ ++static int ++cypher_7108_crypto_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, cypher_7108_crypto_init); ++ ++ iobar = (unsigned long)ioremap(CCU_AES_REG_BASE, 0x4000); ++ printk("7108: AES @ 0x%08x (0x%08x phys) %s mode\n", ++ iobar, CCU_AES_REG_BASE, ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_CBC ? "CBC" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_ECB ? "ECB" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_CTR ? "CTR" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_CFB ? "CFB" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_OFB ? "OFB" : "???"); ++ csr_mutex = SPIN_LOCK_UNLOCKED; ++ ++ memset(&a7108dev, 0, sizeof(a7108dev)); ++ softc_device_init(&a7108dev, "aes7108", 0, a7108_methods); ++ ++ c7108_id = crypto_get_driverid(softc_get_device(&a7108dev), CRYPTOCAP_F_HARDWARE); ++ if (c7108_id < 0) ++ panic("7108: crypto device cannot initialize!"); ++ ++// crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0, c7108_newsession, c7108_freesession, c7108_process, NULL); ++ crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0); ++ ++ return(0); ++} ++ ++static void ++cypher_7108_crypto_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(c7108_id); ++ c7108_id = -1; ++} ++ ++module_init(cypher_7108_crypto_init); ++module_exit(cypher_7108_crypto_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_DESCRIPTION("Cypher 7108 Crypto (OCF module for kernel crypto)"); +diff -Nur linux-2.6.39.orig/crypto/ocf/c7108/aes-7108.h linux-2.6.39/crypto/ocf/c7108/aes-7108.h +--- linux-2.6.39.orig/crypto/ocf/c7108/aes-7108.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/c7108/aes-7108.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,134 @@ ++/* ++ * Copyright (C) 2006 Micronas USA ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++#ifndef __AES_7108_H__ ++#define __AES_7108_H__ ++ ++/* Cypher 7108 AES Controller Hardware */ ++#define CCU_REG_BASE 0x1b500000 ++#define CCU_AES_REG_BASE (CCU_REG_BASE + 0x100) ++#define C7108_AES_KEY0_LO (0x0000) ++#define C7108_AES_KEY0_HI (0x0004) ++#define C7108_AES_KEY1_LO (0x0008) ++#define C7108_AES_KEY1_HI (0x000c) ++#define C7108_AES_KEY2_LO (0x0010) ++#define C7108_AES_KEY2_HI (0x0014) ++#define C7108_AES_KEY3_LO (0x0018) ++#define C7108_AES_KEY3_HI (0x001c) ++#define C7108_AES_KEY4_LO (0x0020) ++#define C7108_AES_KEY4_HI (0x0024) ++#define C7108_AES_KEY5_LO (0x0028) ++#define C7108_AES_KEY5_HI (0x002c) ++#define C7108_AES_KEY6_LO (0x0030) ++#define C7108_AES_KEY6_HI (0x0034) ++#define C7108_AES_KEY7_LO (0x0038) ++#define C7108_AES_KEY7_HI (0x003c) ++#define C7108_AES_IV0_LO (0x0040) ++#define C7108_AES_IV0_HI (0x0044) ++#define C7108_AES_IV1_LO (0x0048) ++#define C7108_AES_IV1_HI (0x004c) ++#define C7108_AES_IV2_LO (0x0050) ++#define C7108_AES_IV2_HI (0x0054) ++#define C7108_AES_IV3_LO (0x0058) ++#define C7108_AES_IV3_HI (0x005c) ++ ++#define C7108_AES_DMA_SRC0_LO (0x0068) /* Bits 0:15 */ ++#define C7108_AES_DMA_SRC0_HI (0x006c) /* Bits 27:16 */ ++#define C7108_AES_DMA_DST0_LO (0x0070) /* Bits 0:15 */ ++#define C7108_AES_DMA_DST0_HI (0x0074) /* Bits 27:16 */ ++#define C7108_AES_DMA_LEN (0x0078) /*Bytes:(Count+1)x16 */ ++ ++/* AES/Copy engine control register */ ++#define C7108_AES_CTRL (0x007c) /* AES control */ ++#define C7108_AES_CTRL_RS (1<<0) /* Which set of src/dst to use */ ++ ++/* AES Cipher mode, controlled by setting Bits 2:0 */ ++#define C7108_AES_CTRL_MODE_CBC 0 ++#define C7108_AES_CTRL_MODE_CFB (1<<0) ++#define C7108_AES_CTRL_MODE_OFB (1<<1) ++#define C7108_AES_CTRL_MODE_CTR ((1<<0)|(1<<1)) ++#define C7108_AES_CTRL_MODE_ECB (1<<2) ++ ++/* AES Key length , Bits 5:4 */ ++#define C7108_AES_KEY_LEN_128 0 /* 00 */ ++#define C7108_AES_KEY_LEN_192 (1<<4) /* 01 */ ++#define C7108_AES_KEY_LEN_256 (1<<5) /* 10 */ ++ ++/* AES Operation (crypt/decrypt), Bit 3 */ ++#define C7108_AES_DECRYPT (1<<3) /* Clear for encrypt */ ++#define C7108_AES_ENCRYPT 0 ++#define C7108_AES_INTR (1<<13) /* Set on done trans from 0->1*/ ++#define C7108_AES_GO (1<<14) /* Run */ ++#define C7108_AES_OP_DONE (1<<15) /* Set when complete */ ++ ++ ++/* Expanded key registers */ ++#define C7108_AES_EKEY0_LO (0x0080) ++#define C7108_AES_EKEY0_HI (0x0084) ++#define C7108_AES_EKEY1_LO (0x0088) ++#define C7108_AES_EKEY1_HI (0x008c) ++#define C7108_AES_EKEY2_LO (0x0090) ++#define C7108_AES_EKEY2_HI (0x0094) ++#define C7108_AES_EKEY3_LO (0x0098) ++#define C7108_AES_EKEY3_HI (0x009c) ++#define C7108_AES_EKEY4_LO (0x00a0) ++#define C7108_AES_EKEY4_HI (0x00a4) ++#define C7108_AES_EKEY5_LO (0x00a8) ++#define C7108_AES_EKEY5_HI (0x00ac) ++#define C7108_AES_EKEY6_LO (0x00b0) ++#define C7108_AES_EKEY6_HI (0x00b4) ++#define C7108_AES_EKEY7_LO (0x00b8) ++#define C7108_AES_EKEY7_HI (0x00bc) ++#define C7108_AES_OK (0x00fc) /* Reset: "OK" */ ++ ++#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) ++ ++/* Software session entry */ ++ ++#define HW_TYPE_CIPHER 0 ++#define SW_TYPE_HMAC 1 ++#define SW_TYPE_AUTH2 2 ++#define SW_TYPE_HASH 3 ++#define SW_TYPE_COMP 4 ++ ++struct cipher_7108 { ++ int xfm_type; ++ int cri_alg; ++ union { ++ struct { ++ char sw_key[HMAC_BLOCK_LEN]; ++ int sw_klen; ++ int sw_authlen; ++ } hmac; ++ } u; ++ struct cipher_7108 *next; ++}; ++ ++ ++ ++#endif /* __C7108_AES_7108_H__ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/criov.c linux-2.6.39/crypto/ocf/criov.c +--- linux-2.6.39.orig/crypto/ocf/criov.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/criov.c 2011-08-01 14:39:10.000000000 +0200 +@@ -0,0 +1,212 @@ ++/* $OpenBSD: criov.c,v 1.9 2002/01/29 15:48:29 jason Exp $ */ ++ ++/* ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 1999 Theo de Raadt ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++__FBSDID("$FreeBSD: src/sys/opencrypto/criov.c,v 1.5 2006/06/04 22:15:13 pjd Exp $"); ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/* ++ * This macro is only for avoiding code duplication, as we need to skip ++ * given number of bytes in the same way in three functions below. ++ */ ++#define CUIO_SKIP() do { \ ++ KASSERT(off >= 0, ("%s: off %d < 0", __func__, off)); \ ++ KASSERT(len >= 0, ("%s: len %d < 0", __func__, len)); \ ++ while (off > 0) { \ ++ KASSERT(iol >= 0, ("%s: empty in skip", __func__)); \ ++ if (off < iov->iov_len) \ ++ break; \ ++ off -= iov->iov_len; \ ++ iol--; \ ++ iov++; \ ++ } \ ++} while (0) ++ ++void ++cuio_copydata(struct uio* uio, int off, int len, caddr_t cp) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int iol = uio->uio_iovcnt; ++ unsigned count; ++ ++ CUIO_SKIP(); ++ while (len > 0) { ++ KASSERT(iol >= 0, ("%s: empty", __func__)); ++ count = min((int)(iov->iov_len - off), len); ++ memcpy(cp, ((caddr_t)iov->iov_base) + off, count); ++ len -= count; ++ cp += count; ++ off = 0; ++ iol--; ++ iov++; ++ } ++} ++ ++void ++cuio_copyback(struct uio* uio, int off, int len, caddr_t cp) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int iol = uio->uio_iovcnt; ++ unsigned count; ++ ++ CUIO_SKIP(); ++ while (len > 0) { ++ KASSERT(iol >= 0, ("%s: empty", __func__)); ++ count = min((int)(iov->iov_len - off), len); ++ memcpy(((caddr_t)iov->iov_base) + off, cp, count); ++ len -= count; ++ cp += count; ++ off = 0; ++ iol--; ++ iov++; ++ } ++} ++ ++/* ++ * Return a pointer to iov/offset of location in iovec list. ++ */ ++struct iovec * ++cuio_getptr(struct uio *uio, int loc, int *off) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int iol = uio->uio_iovcnt; ++ ++ while (loc >= 0) { ++ /* Normal end of search */ ++ if (loc < iov->iov_len) { ++ *off = loc; ++ return (iov); ++ } ++ ++ loc -= iov->iov_len; ++ if (iol == 0) { ++ if (loc == 0) { ++ /* Point at the end of valid data */ ++ *off = iov->iov_len; ++ return (iov); ++ } else ++ return (NULL); ++ } else { ++ iov++, iol--; ++ } ++ } ++ ++ return (NULL); ++} ++ ++EXPORT_SYMBOL(cuio_copyback); ++EXPORT_SYMBOL(cuio_copydata); ++EXPORT_SYMBOL(cuio_getptr); ++ ++ ++static void ++skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len) ++{ ++ int i; ++ if (offset < skb_headlen(skb)) { ++ memcpy(skb->data + offset, cp, min_t(int, skb_headlen(skb), len)); ++ len -= skb_headlen(skb); ++ cp += skb_headlen(skb); ++ } ++ offset -= skb_headlen(skb); ++ for (i = 0; len > 0 && i < skb_shinfo(skb)->nr_frags; i++) { ++ if (offset < skb_shinfo(skb)->frags[i].size) { ++ memcpy(page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ cp, min_t(int, skb_shinfo(skb)->frags[i].size, len)); ++ len -= skb_shinfo(skb)->frags[i].size; ++ cp += skb_shinfo(skb)->frags[i].size; ++ } ++ offset -= skb_shinfo(skb)->frags[i].size; ++ } ++} ++ ++void ++crypto_copyback(int flags, caddr_t buf, int off, int size, caddr_t in) ++{ ++ ++ if ((flags & CRYPTO_F_SKBUF) != 0) ++ skb_copy_bits_back((struct sk_buff *)buf, off, in, size); ++ else if ((flags & CRYPTO_F_IOV) != 0) ++ cuio_copyback((struct uio *)buf, off, size, in); ++ else ++ bcopy(in, buf + off, size); ++} ++ ++void ++crypto_copydata(int flags, caddr_t buf, int off, int size, caddr_t out) ++{ ++ ++ if ((flags & CRYPTO_F_SKBUF) != 0) ++ skb_copy_bits((struct sk_buff *)buf, off, out, size); ++ else if ((flags & CRYPTO_F_IOV) != 0) ++ cuio_copydata((struct uio *)buf, off, size, out); ++ else ++ bcopy(buf + off, out, size); ++} ++ ++int ++crypto_apply(int flags, caddr_t buf, int off, int len, ++ int (*f)(void *, void *, u_int), void *arg) ++{ ++#if 0 ++ int error; ++ ++ if ((flags & CRYPTO_F_SKBUF) != 0) ++ error = XXXXXX((struct mbuf *)buf, off, len, f, arg); ++ else if ((flags & CRYPTO_F_IOV) != 0) ++ error = cuio_apply((struct uio *)buf, off, len, f, arg); ++ else ++ error = (*f)(arg, buf + off, len); ++ return (error); ++#else ++ KASSERT(0, ("crypto_apply not implemented!\n")); ++#endif ++ return 0; ++} ++ ++EXPORT_SYMBOL(crypto_copyback); ++EXPORT_SYMBOL(crypto_copydata); ++EXPORT_SYMBOL(crypto_apply); ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/crypto.c linux-2.6.39/crypto/ocf/crypto.c +--- linux-2.6.39.orig/crypto/ocf/crypto.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/crypto.c 2011-08-01 14:38:42.000000000 +0200 +@@ -0,0 +1,1781 @@ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * Copyright (c) 2002-2006 Sam Leffler. All rights reserved. ++ * ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#if 0 ++#include ++__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.27 2007/03/21 03:42:51 sam Exp $"); ++#endif ++ ++/* ++ * Cryptographic Subsystem. ++ * ++ * This code is derived from the Openbsd Cryptographic Framework (OCF) ++ * that has the copyright shown below. Very little of the original ++ * code remains. ++ */ ++/*- ++ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) ++ * ++ * This code was written by Angelos D. Keromytis in Athens, Greece, in ++ * February 2000. Network Security Technologies Inc. (NSTI) kindly ++ * supported the development of this code. ++ * ++ * Copyright (c) 2000, 2001 Angelos D. Keromytis ++ * ++ * Permission to use, copy, and modify this software with or without fee ++ * is hereby granted, provided that this entire notice is included in ++ * all source code copies of any software which is or includes a copy or ++ * modification of this software. ++ * ++ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY ++ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE ++ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR ++ * PURPOSE. ++ * ++__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.16 2005/01/07 02:29:16 imp Exp $"); ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * keep track of whether or not we have been initialised, a big ++ * issue if we are linked into the kernel and a driver gets started before ++ * us ++ */ ++static int crypto_initted = 0; ++ ++/* ++ * Crypto drivers register themselves by allocating a slot in the ++ * crypto_drivers table with crypto_get_driverid() and then registering ++ * each algorithm they support with crypto_register() and crypto_kregister(). ++ */ ++ ++/* ++ * lock on driver table ++ * we track its state as spin_is_locked does not do anything on non-SMP boxes ++ */ ++static spinlock_t crypto_drivers_lock; ++static int crypto_drivers_locked; /* for non-SMP boxes */ ++ ++#define CRYPTO_DRIVER_LOCK() \ ++ ({ \ ++ spin_lock_irqsave(&crypto_drivers_lock, d_flags); \ ++ crypto_drivers_locked = 1; \ ++ dprintk("%s,%d: DRIVER_LOCK()\n", __FILE__, __LINE__); \ ++ }) ++#define CRYPTO_DRIVER_UNLOCK() \ ++ ({ \ ++ dprintk("%s,%d: DRIVER_UNLOCK()\n", __FILE__, __LINE__); \ ++ crypto_drivers_locked = 0; \ ++ spin_unlock_irqrestore(&crypto_drivers_lock, d_flags); \ ++ }) ++#define CRYPTO_DRIVER_ASSERT() \ ++ ({ \ ++ if (!crypto_drivers_locked) { \ ++ dprintk("%s,%d: DRIVER_ASSERT!\n", __FILE__, __LINE__); \ ++ } \ ++ }) ++ ++/* ++ * Crypto device/driver capabilities structure. ++ * ++ * Synchronization: ++ * (d) - protected by CRYPTO_DRIVER_LOCK() ++ * (q) - protected by CRYPTO_Q_LOCK() ++ * Not tagged fields are read-only. ++ */ ++struct cryptocap { ++ device_t cc_dev; /* (d) device/driver */ ++ u_int32_t cc_sessions; /* (d) # of sessions */ ++ u_int32_t cc_koperations; /* (d) # os asym operations */ ++ /* ++ * Largest possible operator length (in bits) for each type of ++ * encryption algorithm. XXX not used ++ */ ++ u_int16_t cc_max_op_len[CRYPTO_ALGORITHM_MAX + 1]; ++ u_int8_t cc_alg[CRYPTO_ALGORITHM_MAX + 1]; ++ u_int8_t cc_kalg[CRK_ALGORITHM_MAX + 1]; ++ ++ int cc_flags; /* (d) flags */ ++#define CRYPTOCAP_F_CLEANUP 0x80000000 /* needs resource cleanup */ ++ int cc_qblocked; /* (q) symmetric q blocked */ ++ int cc_kqblocked; /* (q) asymmetric q blocked */ ++ ++ int cc_unqblocked; /* (q) symmetric q blocked */ ++ int cc_unkqblocked; /* (q) asymmetric q blocked */ ++}; ++static struct cryptocap *crypto_drivers = NULL; ++static int crypto_drivers_num = 0; ++ ++/* ++ * There are two queues for crypto requests; one for symmetric (e.g. ++ * cipher) operations and one for asymmetric (e.g. MOD)operations. ++ * A single mutex is used to lock access to both queues. We could ++ * have one per-queue but having one simplifies handling of block/unblock ++ * operations. ++ */ ++static int crp_sleep = 0; ++static LIST_HEAD(crp_q); /* request queues */ ++static LIST_HEAD(crp_kq); ++ ++static spinlock_t crypto_q_lock; ++ ++int crypto_all_qblocked = 0; /* protect with Q_LOCK */ ++module_param(crypto_all_qblocked, int, 0444); ++MODULE_PARM_DESC(crypto_all_qblocked, "Are all crypto queues blocked"); ++ ++int crypto_all_kqblocked = 0; /* protect with Q_LOCK */ ++module_param(crypto_all_kqblocked, int, 0444); ++MODULE_PARM_DESC(crypto_all_kqblocked, "Are all asym crypto queues blocked"); ++ ++#define CRYPTO_Q_LOCK() \ ++ ({ \ ++ spin_lock_irqsave(&crypto_q_lock, q_flags); \ ++ dprintk("%s,%d: Q_LOCK()\n", __FILE__, __LINE__); \ ++ }) ++#define CRYPTO_Q_UNLOCK() \ ++ ({ \ ++ dprintk("%s,%d: Q_UNLOCK()\n", __FILE__, __LINE__); \ ++ spin_unlock_irqrestore(&crypto_q_lock, q_flags); \ ++ }) ++ ++/* ++ * There are two queues for processing completed crypto requests; one ++ * for the symmetric and one for the asymmetric ops. We only need one ++ * but have two to avoid type futzing (cryptop vs. cryptkop). A single ++ * mutex is used to lock access to both queues. Note that this lock ++ * must be separate from the lock on request queues to insure driver ++ * callbacks don't generate lock order reversals. ++ */ ++static LIST_HEAD(crp_ret_q); /* callback queues */ ++static LIST_HEAD(crp_ret_kq); ++ ++static spinlock_t crypto_ret_q_lock; ++#define CRYPTO_RETQ_LOCK() \ ++ ({ \ ++ spin_lock_irqsave(&crypto_ret_q_lock, r_flags); \ ++ dprintk("%s,%d: RETQ_LOCK\n", __FILE__, __LINE__); \ ++ }) ++#define CRYPTO_RETQ_UNLOCK() \ ++ ({ \ ++ dprintk("%s,%d: RETQ_UNLOCK\n", __FILE__, __LINE__); \ ++ spin_unlock_irqrestore(&crypto_ret_q_lock, r_flags); \ ++ }) ++#define CRYPTO_RETQ_EMPTY() (list_empty(&crp_ret_q) && list_empty(&crp_ret_kq)) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++static kmem_cache_t *cryptop_zone; ++static kmem_cache_t *cryptodesc_zone; ++#else ++static struct kmem_cache *cryptop_zone; ++static struct kmem_cache *cryptodesc_zone; ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++#include ++#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) ++#endif ++ ++#define debug crypto_debug ++int crypto_debug = 0; ++module_param(crypto_debug, int, 0644); ++MODULE_PARM_DESC(crypto_debug, "Enable debug"); ++EXPORT_SYMBOL(crypto_debug); ++ ++/* ++ * Maximum number of outstanding crypto requests before we start ++ * failing requests. We need this to prevent DOS when too many ++ * requests are arriving for us to keep up. Otherwise we will ++ * run the system out of memory. Since crypto is slow, we are ++ * usually the bottleneck that needs to say, enough is enough. ++ * ++ * We cannot print errors when this condition occurs, we are already too ++ * slow, printing anything will just kill us ++ */ ++ ++static int crypto_q_cnt = 0; ++module_param(crypto_q_cnt, int, 0444); ++MODULE_PARM_DESC(crypto_q_cnt, ++ "Current number of outstanding crypto requests"); ++ ++static int crypto_q_max = 1000; ++module_param(crypto_q_max, int, 0644); ++MODULE_PARM_DESC(crypto_q_max, ++ "Maximum number of outstanding crypto requests"); ++ ++#define bootverbose crypto_verbose ++static int crypto_verbose = 0; ++module_param(crypto_verbose, int, 0644); ++MODULE_PARM_DESC(crypto_verbose, ++ "Enable verbose crypto startup"); ++ ++int crypto_usercrypto = 1; /* userland may do crypto reqs */ ++module_param(crypto_usercrypto, int, 0644); ++MODULE_PARM_DESC(crypto_usercrypto, ++ "Enable/disable user-mode access to crypto support"); ++ ++int crypto_userasymcrypto = 1; /* userland may do asym crypto reqs */ ++module_param(crypto_userasymcrypto, int, 0644); ++MODULE_PARM_DESC(crypto_userasymcrypto, ++ "Enable/disable user-mode access to asymmetric crypto support"); ++ ++int crypto_devallowsoft = 0; /* only use hardware crypto */ ++module_param(crypto_devallowsoft, int, 0644); ++MODULE_PARM_DESC(crypto_devallowsoft, ++ "Enable/disable use of software crypto support"); ++ ++/* ++ * This parameter controls the maximum number of crypto operations to ++ * do consecutively in the crypto kernel thread before scheduling to allow ++ * other processes to run. Without it, it is possible to get into a ++ * situation where the crypto thread never allows any other processes to run. ++ * Default to 1000 which should be less than one second. ++ */ ++static int crypto_max_loopcount = 1000; ++module_param(crypto_max_loopcount, int, 0644); ++MODULE_PARM_DESC(crypto_max_loopcount, ++ "Maximum number of crypto ops to do before yielding to other processes"); ++ ++static pid_t cryptoproc = (pid_t) -1; ++static struct completion cryptoproc_exited; ++static DECLARE_WAIT_QUEUE_HEAD(cryptoproc_wait); ++static pid_t cryptoretproc = (pid_t) -1; ++static struct completion cryptoretproc_exited; ++static DECLARE_WAIT_QUEUE_HEAD(cryptoretproc_wait); ++ ++static int crypto_proc(void *arg); ++static int crypto_ret_proc(void *arg); ++static int crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint); ++static int crypto_kinvoke(struct cryptkop *krp, int flags); ++static void crypto_exit(void); ++static int crypto_init(void); ++ ++static struct cryptostats cryptostats; ++ ++static struct cryptocap * ++crypto_checkdriver(u_int32_t hid) ++{ ++ if (crypto_drivers == NULL) ++ return NULL; ++ return (hid >= crypto_drivers_num ? NULL : &crypto_drivers[hid]); ++} ++ ++/* ++ * Compare a driver's list of supported algorithms against another ++ * list; return non-zero if all algorithms are supported. ++ */ ++static int ++driver_suitable(const struct cryptocap *cap, const struct cryptoini *cri) ++{ ++ const struct cryptoini *cr; ++ ++ /* See if all the algorithms are supported. */ ++ for (cr = cri; cr; cr = cr->cri_next) ++ if (cap->cc_alg[cr->cri_alg] == 0) ++ return 0; ++ return 1; ++} ++ ++/* ++ * Select a driver for a new session that supports the specified ++ * algorithms and, optionally, is constrained according to the flags. ++ * The algorithm we use here is pretty stupid; just use the ++ * first driver that supports all the algorithms we need. If there ++ * are multiple drivers we choose the driver with the fewest active ++ * sessions. We prefer hardware-backed drivers to software ones. ++ * ++ * XXX We need more smarts here (in real life too, but that's ++ * XXX another story altogether). ++ */ ++static struct cryptocap * ++crypto_select_driver(const struct cryptoini *cri, int flags) ++{ ++ struct cryptocap *cap, *best; ++ int match, hid; ++ ++ CRYPTO_DRIVER_ASSERT(); ++ ++ /* ++ * Look first for hardware crypto devices if permitted. ++ */ ++ if (flags & CRYPTOCAP_F_HARDWARE) ++ match = CRYPTOCAP_F_HARDWARE; ++ else ++ match = CRYPTOCAP_F_SOFTWARE; ++ best = NULL; ++again: ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ cap = &crypto_drivers[hid]; ++ /* ++ * If it's not initialized, is in the process of ++ * going away, or is not appropriate (hardware ++ * or software based on match), then skip. ++ */ ++ if (cap->cc_dev == NULL || ++ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || ++ (cap->cc_flags & match) == 0) ++ continue; ++ ++ /* verify all the algorithms are supported. */ ++ if (driver_suitable(cap, cri)) { ++ if (best == NULL || ++ cap->cc_sessions < best->cc_sessions) ++ best = cap; ++ } ++ } ++ if (best != NULL) ++ return best; ++ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { ++ /* sort of an Algol 68-style for loop */ ++ match = CRYPTOCAP_F_SOFTWARE; ++ goto again; ++ } ++ return best; ++} ++ ++/* ++ * Create a new session. The crid argument specifies a crypto ++ * driver to use or constraints on a driver to select (hardware ++ * only, software only, either). Whatever driver is selected ++ * must be capable of the requested crypto algorithms. ++ */ ++int ++crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int crid) ++{ ++ struct cryptocap *cap; ++ u_int32_t hid, lid; ++ int err; ++ unsigned long d_flags; ++ ++ CRYPTO_DRIVER_LOCK(); ++ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { ++ /* ++ * Use specified driver; verify it is capable. ++ */ ++ cap = crypto_checkdriver(crid); ++ if (cap != NULL && !driver_suitable(cap, cri)) ++ cap = NULL; ++ } else { ++ /* ++ * No requested driver; select based on crid flags. ++ */ ++ cap = crypto_select_driver(cri, crid); ++ /* ++ * if NULL then can't do everything in one session. ++ * XXX Fix this. We need to inject a "virtual" session ++ * XXX layer right about here. ++ */ ++ } ++ if (cap != NULL) { ++ /* Call the driver initialization routine. */ ++ hid = cap - crypto_drivers; ++ lid = hid; /* Pass the driver ID. */ ++ cap->cc_sessions++; ++ CRYPTO_DRIVER_UNLOCK(); ++ err = CRYPTODEV_NEWSESSION(cap->cc_dev, &lid, cri); ++ CRYPTO_DRIVER_LOCK(); ++ if (err == 0) { ++ (*sid) = (cap->cc_flags & 0xff000000) ++ | (hid & 0x00ffffff); ++ (*sid) <<= 32; ++ (*sid) |= (lid & 0xffffffff); ++ } else ++ cap->cc_sessions--; ++ } else ++ err = EINVAL; ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++static void ++crypto_remove(struct cryptocap *cap) ++{ ++ CRYPTO_DRIVER_ASSERT(); ++ if (cap->cc_sessions == 0 && cap->cc_koperations == 0) ++ bzero(cap, sizeof(*cap)); ++} ++ ++/* ++ * Delete an existing session (or a reserved session on an unregistered ++ * driver). ++ */ ++int ++crypto_freesession(u_int64_t sid) ++{ ++ struct cryptocap *cap; ++ u_int32_t hid; ++ int err = 0; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ ++ if (crypto_drivers == NULL) { ++ err = EINVAL; ++ goto done; ++ } ++ ++ /* Determine two IDs. */ ++ hid = CRYPTO_SESID2HID(sid); ++ ++ if (hid >= crypto_drivers_num) { ++ dprintk("%s - INVALID DRIVER NUM %d\n", __FUNCTION__, hid); ++ err = ENOENT; ++ goto done; ++ } ++ cap = &crypto_drivers[hid]; ++ ++ if (cap->cc_dev) { ++ CRYPTO_DRIVER_UNLOCK(); ++ /* Call the driver cleanup routine, if available, unlocked. */ ++ err = CRYPTODEV_FREESESSION(cap->cc_dev, sid); ++ CRYPTO_DRIVER_LOCK(); ++ } ++ ++ if (cap->cc_sessions) ++ cap->cc_sessions--; ++ ++ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) ++ crypto_remove(cap); ++ ++done: ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++/* ++ * Return an unused driver id. Used by drivers prior to registering ++ * support for the algorithms they handle. ++ */ ++int32_t ++crypto_get_driverid(device_t dev, int flags) ++{ ++ struct cryptocap *newdrv; ++ int i; ++ unsigned long d_flags; ++ ++ if ((flags & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { ++ printf("%s: no flags specified when registering driver\n", ++ device_get_nameunit(dev)); ++ return -1; ++ } ++ ++ CRYPTO_DRIVER_LOCK(); ++ ++ for (i = 0; i < crypto_drivers_num; i++) { ++ if (crypto_drivers[i].cc_dev == NULL && ++ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP) == 0) { ++ break; ++ } ++ } ++ ++ /* Out of entries, allocate some more. */ ++ if (i == crypto_drivers_num) { ++ /* Be careful about wrap-around. */ ++ if (2 * crypto_drivers_num <= crypto_drivers_num) { ++ CRYPTO_DRIVER_UNLOCK(); ++ printk("crypto: driver count wraparound!\n"); ++ return -1; ++ } ++ ++ newdrv = kmalloc(2 * crypto_drivers_num * sizeof(struct cryptocap), ++ GFP_KERNEL); ++ if (newdrv == NULL) { ++ CRYPTO_DRIVER_UNLOCK(); ++ printk("crypto: no space to expand driver table!\n"); ++ return -1; ++ } ++ ++ memcpy(newdrv, crypto_drivers, ++ crypto_drivers_num * sizeof(struct cryptocap)); ++ memset(&newdrv[crypto_drivers_num], 0, ++ crypto_drivers_num * sizeof(struct cryptocap)); ++ ++ crypto_drivers_num *= 2; ++ ++ kfree(crypto_drivers); ++ crypto_drivers = newdrv; ++ } ++ ++ /* NB: state is zero'd on free */ ++ crypto_drivers[i].cc_sessions = 1; /* Mark */ ++ crypto_drivers[i].cc_dev = dev; ++ crypto_drivers[i].cc_flags = flags; ++ if (bootverbose) ++ printf("crypto: assign %s driver id %u, flags %u\n", ++ device_get_nameunit(dev), i, flags); ++ ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ return i; ++} ++ ++/* ++ * Lookup a driver by name. We match against the full device ++ * name and unit, and against just the name. The latter gives ++ * us a simple widlcarding by device name. On success return the ++ * driver/hardware identifier; otherwise return -1. ++ */ ++int ++crypto_find_driver(const char *match) ++{ ++ int i, len = strlen(match); ++ unsigned long d_flags; ++ ++ CRYPTO_DRIVER_LOCK(); ++ for (i = 0; i < crypto_drivers_num; i++) { ++ device_t dev = crypto_drivers[i].cc_dev; ++ if (dev == NULL || ++ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP)) ++ continue; ++ if (strncmp(match, device_get_nameunit(dev), len) == 0 || ++ strncmp(match, device_get_name(dev), len) == 0) ++ break; ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ return i < crypto_drivers_num ? i : -1; ++} ++ ++/* ++ * Return the device_t for the specified driver or NULL ++ * if the driver identifier is invalid. ++ */ ++device_t ++crypto_find_device_byhid(int hid) ++{ ++ struct cryptocap *cap = crypto_checkdriver(hid); ++ return cap != NULL ? cap->cc_dev : NULL; ++} ++ ++/* ++ * Return the device/driver capabilities. ++ */ ++int ++crypto_getcaps(int hid) ++{ ++ struct cryptocap *cap = crypto_checkdriver(hid); ++ return cap != NULL ? cap->cc_flags : 0; ++} ++ ++/* ++ * Register support for a key-related algorithm. This routine ++ * is called once for each algorithm supported a driver. ++ */ ++int ++crypto_kregister(u_int32_t driverid, int kalg, u_int32_t flags) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL && ++ (CRK_ALGORITM_MIN <= kalg && kalg <= CRK_ALGORITHM_MAX)) { ++ /* ++ * XXX Do some performance testing to determine placing. ++ * XXX We probably need an auxiliary data structure that ++ * XXX describes relative performances. ++ */ ++ ++ cap->cc_kalg[kalg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; ++ if (bootverbose) ++ printf("crypto: %s registers key alg %u flags %u\n" ++ , device_get_nameunit(cap->cc_dev) ++ , kalg ++ , flags ++ ); ++ err = 0; ++ } else ++ err = EINVAL; ++ ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++/* ++ * Register support for a non-key-related algorithm. This routine ++ * is called once for each such algorithm supported by a driver. ++ */ ++int ++crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, ++ u_int32_t flags) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long d_flags; ++ ++ dprintk("%s(id=0x%x, alg=%d, maxoplen=%d, flags=0x%x)\n", __FUNCTION__, ++ driverid, alg, maxoplen, flags); ++ ++ CRYPTO_DRIVER_LOCK(); ++ ++ cap = crypto_checkdriver(driverid); ++ /* NB: algorithms are in the range [1..max] */ ++ if (cap != NULL && ++ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX)) { ++ /* ++ * XXX Do some performance testing to determine placing. ++ * XXX We probably need an auxiliary data structure that ++ * XXX describes relative performances. ++ */ ++ ++ cap->cc_alg[alg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; ++ cap->cc_max_op_len[alg] = maxoplen; ++ if (bootverbose) ++ printf("crypto: %s registers alg %u flags %u maxoplen %u\n" ++ , device_get_nameunit(cap->cc_dev) ++ , alg ++ , flags ++ , maxoplen ++ ); ++ cap->cc_sessions = 0; /* Unmark */ ++ err = 0; ++ } else ++ err = EINVAL; ++ ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++static void ++driver_finis(struct cryptocap *cap) ++{ ++ u_int32_t ses, kops; ++ ++ CRYPTO_DRIVER_ASSERT(); ++ ++ ses = cap->cc_sessions; ++ kops = cap->cc_koperations; ++ bzero(cap, sizeof(*cap)); ++ if (ses != 0 || kops != 0) { ++ /* ++ * If there are pending sessions, ++ * just mark as invalid. ++ */ ++ cap->cc_flags |= CRYPTOCAP_F_CLEANUP; ++ cap->cc_sessions = ses; ++ cap->cc_koperations = kops; ++ } ++} ++ ++/* ++ * Unregister a crypto driver. If there are pending sessions using it, ++ * leave enough information around so that subsequent calls using those ++ * sessions will correctly detect the driver has been unregistered and ++ * reroute requests. ++ */ ++int ++crypto_unregister(u_int32_t driverid, int alg) ++{ ++ struct cryptocap *cap; ++ int i, err; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL && ++ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX) && ++ cap->cc_alg[alg] != 0) { ++ cap->cc_alg[alg] = 0; ++ cap->cc_max_op_len[alg] = 0; ++ ++ /* Was this the last algorithm ? */ ++ for (i = 1; i <= CRYPTO_ALGORITHM_MAX; i++) ++ if (cap->cc_alg[i] != 0) ++ break; ++ ++ if (i == CRYPTO_ALGORITHM_MAX + 1) ++ driver_finis(cap); ++ err = 0; ++ } else ++ err = EINVAL; ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++/* ++ * Unregister all algorithms associated with a crypto driver. ++ * If there are pending sessions using it, leave enough information ++ * around so that subsequent calls using those sessions will ++ * correctly detect the driver has been unregistered and reroute ++ * requests. ++ */ ++int ++crypto_unregister_all(u_int32_t driverid) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL) { ++ driver_finis(cap); ++ err = 0; ++ } else ++ err = EINVAL; ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ return err; ++} ++ ++/* ++ * Clear blockage on a driver. The what parameter indicates whether ++ * the driver is now ready for cryptop's and/or cryptokop's. ++ */ ++int ++crypto_unblock(u_int32_t driverid, int what) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long q_flags; ++ ++ CRYPTO_Q_LOCK(); ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL) { ++ if (what & CRYPTO_SYMQ) { ++ cap->cc_qblocked = 0; ++ cap->cc_unqblocked = 0; ++ crypto_all_qblocked = 0; ++ } ++ if (what & CRYPTO_ASYMQ) { ++ cap->cc_kqblocked = 0; ++ cap->cc_unkqblocked = 0; ++ crypto_all_kqblocked = 0; ++ } ++ if (crp_sleep) ++ wake_up_interruptible(&cryptoproc_wait); ++ err = 0; ++ } else ++ err = EINVAL; ++ CRYPTO_Q_UNLOCK(); //DAVIDM should this be a driver lock ++ ++ return err; ++} ++ ++/* ++ * Add a crypto request to a queue, to be processed by the kernel thread. ++ */ ++int ++crypto_dispatch(struct cryptop *crp) ++{ ++ struct cryptocap *cap; ++ int result = -1; ++ unsigned long q_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ cryptostats.cs_ops++; ++ ++ CRYPTO_Q_LOCK(); ++ if (crypto_q_cnt >= crypto_q_max) { ++ CRYPTO_Q_UNLOCK(); ++ cryptostats.cs_drops++; ++ return ENOMEM; ++ } ++ crypto_q_cnt++; ++ ++ /* make sure we are starting a fresh run on this crp. */ ++ crp->crp_flags &= ~CRYPTO_F_DONE; ++ crp->crp_etype = 0; ++ ++ /* ++ * Caller marked the request to be processed immediately; dispatch ++ * it directly to the driver unless the driver is currently blocked. ++ */ ++ if ((crp->crp_flags & CRYPTO_F_BATCH) == 0) { ++ int hid = CRYPTO_SESID2HID(crp->crp_sid); ++ cap = crypto_checkdriver(hid); ++ /* Driver cannot disappear when there is an active session. */ ++ KASSERT(cap != NULL, ("%s: Driver disappeared.", __func__)); ++ if (!cap->cc_qblocked) { ++ crypto_all_qblocked = 0; ++ crypto_drivers[hid].cc_unqblocked = 1; ++ CRYPTO_Q_UNLOCK(); ++ result = crypto_invoke(cap, crp, 0); ++ CRYPTO_Q_LOCK(); ++ if (result == ERESTART) ++ if (crypto_drivers[hid].cc_unqblocked) ++ crypto_drivers[hid].cc_qblocked = 1; ++ crypto_drivers[hid].cc_unqblocked = 0; ++ } ++ } ++ if (result == ERESTART) { ++ /* ++ * The driver ran out of resources, mark the ++ * driver ``blocked'' for cryptop's and put ++ * the request back in the queue. It would ++ * best to put the request back where we got ++ * it but that's hard so for now we put it ++ * at the front. This should be ok; putting ++ * it at the end does not work. ++ */ ++ list_add(&crp->crp_next, &crp_q); ++ cryptostats.cs_blocks++; ++ result = 0; ++ } else if (result == -1) { ++ TAILQ_INSERT_TAIL(&crp_q, crp, crp_next); ++ result = 0; ++ } ++ if (crp_sleep) ++ wake_up_interruptible(&cryptoproc_wait); ++ CRYPTO_Q_UNLOCK(); ++ return result; ++} ++ ++/* ++ * Add an asymetric crypto request to a queue, ++ * to be processed by the kernel thread. ++ */ ++int ++crypto_kdispatch(struct cryptkop *krp) ++{ ++ int error; ++ unsigned long q_flags; ++ ++ cryptostats.cs_kops++; ++ ++ error = crypto_kinvoke(krp, krp->krp_crid); ++ if (error == ERESTART) { ++ CRYPTO_Q_LOCK(); ++ TAILQ_INSERT_TAIL(&crp_kq, krp, krp_next); ++ if (crp_sleep) ++ wake_up_interruptible(&cryptoproc_wait); ++ CRYPTO_Q_UNLOCK(); ++ error = 0; ++ } ++ return error; ++} ++ ++/* ++ * Verify a driver is suitable for the specified operation. ++ */ ++static __inline int ++kdriver_suitable(const struct cryptocap *cap, const struct cryptkop *krp) ++{ ++ return (cap->cc_kalg[krp->krp_op] & CRYPTO_ALG_FLAG_SUPPORTED) != 0; ++} ++ ++/* ++ * Select a driver for an asym operation. The driver must ++ * support the necessary algorithm. The caller can constrain ++ * which device is selected with the flags parameter. The ++ * algorithm we use here is pretty stupid; just use the first ++ * driver that supports the algorithms we need. If there are ++ * multiple suitable drivers we choose the driver with the ++ * fewest active operations. We prefer hardware-backed ++ * drivers to software ones when either may be used. ++ */ ++static struct cryptocap * ++crypto_select_kdriver(const struct cryptkop *krp, int flags) ++{ ++ struct cryptocap *cap, *best, *blocked; ++ int match, hid; ++ ++ CRYPTO_DRIVER_ASSERT(); ++ ++ /* ++ * Look first for hardware crypto devices if permitted. ++ */ ++ if (flags & CRYPTOCAP_F_HARDWARE) ++ match = CRYPTOCAP_F_HARDWARE; ++ else ++ match = CRYPTOCAP_F_SOFTWARE; ++ best = NULL; ++ blocked = NULL; ++again: ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ cap = &crypto_drivers[hid]; ++ /* ++ * If it's not initialized, is in the process of ++ * going away, or is not appropriate (hardware ++ * or software based on match), then skip. ++ */ ++ if (cap->cc_dev == NULL || ++ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || ++ (cap->cc_flags & match) == 0) ++ continue; ++ ++ /* verify all the algorithms are supported. */ ++ if (kdriver_suitable(cap, krp)) { ++ if (best == NULL || ++ cap->cc_koperations < best->cc_koperations) ++ best = cap; ++ } ++ } ++ if (best != NULL) ++ return best; ++ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { ++ /* sort of an Algol 68-style for loop */ ++ match = CRYPTOCAP_F_SOFTWARE; ++ goto again; ++ } ++ return best; ++} ++ ++/* ++ * Dispatch an assymetric crypto request. ++ */ ++static int ++crypto_kinvoke(struct cryptkop *krp, int crid) ++{ ++ struct cryptocap *cap = NULL; ++ int error; ++ unsigned long d_flags; ++ ++ KASSERT(krp != NULL, ("%s: krp == NULL", __func__)); ++ KASSERT(krp->krp_callback != NULL, ++ ("%s: krp->crp_callback == NULL", __func__)); ++ ++ CRYPTO_DRIVER_LOCK(); ++ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { ++ cap = crypto_checkdriver(crid); ++ if (cap != NULL) { ++ /* ++ * Driver present, it must support the necessary ++ * algorithm and, if s/w drivers are excluded, ++ * it must be registered as hardware-backed. ++ */ ++ if (!kdriver_suitable(cap, krp) || ++ (!crypto_devallowsoft && ++ (cap->cc_flags & CRYPTOCAP_F_HARDWARE) == 0)) ++ cap = NULL; ++ } ++ } else { ++ /* ++ * No requested driver; select based on crid flags. ++ */ ++ if (!crypto_devallowsoft) /* NB: disallow s/w drivers */ ++ crid &= ~CRYPTOCAP_F_SOFTWARE; ++ cap = crypto_select_kdriver(krp, crid); ++ } ++ if (cap != NULL && !cap->cc_kqblocked) { ++ krp->krp_hid = cap - crypto_drivers; ++ cap->cc_koperations++; ++ CRYPTO_DRIVER_UNLOCK(); ++ error = CRYPTODEV_KPROCESS(cap->cc_dev, krp, 0); ++ CRYPTO_DRIVER_LOCK(); ++ if (error == ERESTART) { ++ cap->cc_koperations--; ++ CRYPTO_DRIVER_UNLOCK(); ++ return (error); ++ } ++ /* return the actual device used */ ++ krp->krp_crid = krp->krp_hid; ++ } else { ++ /* ++ * NB: cap is !NULL if device is blocked; in ++ * that case return ERESTART so the operation ++ * is resubmitted if possible. ++ */ ++ error = (cap == NULL) ? ENODEV : ERESTART; ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ if (error) { ++ krp->krp_status = error; ++ crypto_kdone(krp); ++ } ++ return 0; ++} ++ ++ ++/* ++ * Dispatch a crypto request to the appropriate crypto devices. ++ */ ++static int ++crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint) ++{ ++ KASSERT(crp != NULL, ("%s: crp == NULL", __func__)); ++ KASSERT(crp->crp_callback != NULL, ++ ("%s: crp->crp_callback == NULL", __func__)); ++ KASSERT(crp->crp_desc != NULL, ("%s: crp->crp_desc == NULL", __func__)); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++#ifdef CRYPTO_TIMING ++ if (crypto_timing) ++ crypto_tstat(&cryptostats.cs_invoke, &crp->crp_tstamp); ++#endif ++ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) { ++ struct cryptodesc *crd; ++ u_int64_t nid; ++ ++ /* ++ * Driver has unregistered; migrate the session and return ++ * an error to the caller so they'll resubmit the op. ++ * ++ * XXX: What if there are more already queued requests for this ++ * session? ++ */ ++ crypto_freesession(crp->crp_sid); ++ ++ for (crd = crp->crp_desc; crd->crd_next; crd = crd->crd_next) ++ crd->CRD_INI.cri_next = &(crd->crd_next->CRD_INI); ++ ++ /* XXX propagate flags from initial session? */ ++ if (crypto_newsession(&nid, &(crp->crp_desc->CRD_INI), ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE) == 0) ++ crp->crp_sid = nid; ++ ++ crp->crp_etype = EAGAIN; ++ crypto_done(crp); ++ return 0; ++ } else { ++ /* ++ * Invoke the driver to process the request. ++ */ ++ return CRYPTODEV_PROCESS(cap->cc_dev, crp, hint); ++ } ++} ++ ++/* ++ * Release a set of crypto descriptors. ++ */ ++void ++crypto_freereq(struct cryptop *crp) ++{ ++ struct cryptodesc *crd; ++ ++ if (crp == NULL) ++ return; ++ ++#ifdef DIAGNOSTIC ++ { ++ struct cryptop *crp2; ++ unsigned long q_flags; ++ ++ CRYPTO_Q_LOCK(); ++ TAILQ_FOREACH(crp2, &crp_q, crp_next) { ++ KASSERT(crp2 != crp, ++ ("Freeing cryptop from the crypto queue (%p).", ++ crp)); ++ } ++ CRYPTO_Q_UNLOCK(); ++ CRYPTO_RETQ_LOCK(); ++ TAILQ_FOREACH(crp2, &crp_ret_q, crp_next) { ++ KASSERT(crp2 != crp, ++ ("Freeing cryptop from the return queue (%p).", ++ crp)); ++ } ++ CRYPTO_RETQ_UNLOCK(); ++ } ++#endif ++ ++ while ((crd = crp->crp_desc) != NULL) { ++ crp->crp_desc = crd->crd_next; ++ kmem_cache_free(cryptodesc_zone, crd); ++ } ++ kmem_cache_free(cryptop_zone, crp); ++} ++ ++/* ++ * Acquire a set of crypto descriptors. ++ */ ++struct cryptop * ++crypto_getreq(int num) ++{ ++ struct cryptodesc *crd; ++ struct cryptop *crp; ++ ++ crp = kmem_cache_alloc(cryptop_zone, SLAB_ATOMIC); ++ if (crp != NULL) { ++ memset(crp, 0, sizeof(*crp)); ++ INIT_LIST_HEAD(&crp->crp_next); ++ init_waitqueue_head(&crp->crp_waitq); ++ while (num--) { ++ crd = kmem_cache_alloc(cryptodesc_zone, SLAB_ATOMIC); ++ if (crd == NULL) { ++ crypto_freereq(crp); ++ return NULL; ++ } ++ memset(crd, 0, sizeof(*crd)); ++ crd->crd_next = crp->crp_desc; ++ crp->crp_desc = crd; ++ } ++ } ++ return crp; ++} ++ ++/* ++ * Invoke the callback on behalf of the driver. ++ */ ++void ++crypto_done(struct cryptop *crp) ++{ ++ unsigned long q_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if ((crp->crp_flags & CRYPTO_F_DONE) == 0) { ++ crp->crp_flags |= CRYPTO_F_DONE; ++ CRYPTO_Q_LOCK(); ++ crypto_q_cnt--; ++ CRYPTO_Q_UNLOCK(); ++ } else ++ printk("crypto: crypto_done op already done, flags 0x%x", ++ crp->crp_flags); ++ if (crp->crp_etype != 0) ++ cryptostats.cs_errs++; ++ /* ++ * CBIMM means unconditionally do the callback immediately; ++ * CBIFSYNC means do the callback immediately only if the ++ * operation was done synchronously. Both are used to avoid ++ * doing extraneous context switches; the latter is mostly ++ * used with the software crypto driver. ++ */ ++ if ((crp->crp_flags & CRYPTO_F_CBIMM) || ++ ((crp->crp_flags & CRYPTO_F_CBIFSYNC) && ++ (CRYPTO_SESID2CAPS(crp->crp_sid) & CRYPTOCAP_F_SYNC))) { ++ /* ++ * Do the callback directly. This is ok when the ++ * callback routine does very little (e.g. the ++ * /dev/crypto callback method just does a wakeup). ++ */ ++ crp->crp_callback(crp); ++ } else { ++ unsigned long r_flags; ++ /* ++ * Normal case; queue the callback for the thread. ++ */ ++ CRYPTO_RETQ_LOCK(); ++ if (CRYPTO_RETQ_EMPTY()) ++ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ ++ TAILQ_INSERT_TAIL(&crp_ret_q, crp, crp_next); ++ CRYPTO_RETQ_UNLOCK(); ++ } ++} ++ ++/* ++ * Invoke the callback on behalf of the driver. ++ */ ++void ++crypto_kdone(struct cryptkop *krp) ++{ ++ struct cryptocap *cap; ++ unsigned long d_flags; ++ ++ if ((krp->krp_flags & CRYPTO_KF_DONE) != 0) ++ printk("crypto: crypto_kdone op already done, flags 0x%x", ++ krp->krp_flags); ++ krp->krp_flags |= CRYPTO_KF_DONE; ++ if (krp->krp_status != 0) ++ cryptostats.cs_kerrs++; ++ ++ CRYPTO_DRIVER_LOCK(); ++ /* XXX: What if driver is loaded in the meantime? */ ++ if (krp->krp_hid < crypto_drivers_num) { ++ cap = &crypto_drivers[krp->krp_hid]; ++ cap->cc_koperations--; ++ KASSERT(cap->cc_koperations >= 0, ("cc_koperations < 0")); ++ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) ++ crypto_remove(cap); ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ /* ++ * CBIMM means unconditionally do the callback immediately; ++ * This is used to avoid doing extraneous context switches ++ */ ++ if ((krp->krp_flags & CRYPTO_KF_CBIMM)) { ++ /* ++ * Do the callback directly. This is ok when the ++ * callback routine does very little (e.g. the ++ * /dev/crypto callback method just does a wakeup). ++ */ ++ krp->krp_callback(krp); ++ } else { ++ unsigned long r_flags; ++ /* ++ * Normal case; queue the callback for the thread. ++ */ ++ CRYPTO_RETQ_LOCK(); ++ if (CRYPTO_RETQ_EMPTY()) ++ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ ++ TAILQ_INSERT_TAIL(&crp_ret_kq, krp, krp_next); ++ CRYPTO_RETQ_UNLOCK(); ++ } ++} ++ ++int ++crypto_getfeat(int *featp) ++{ ++ int hid, kalg, feat = 0; ++ unsigned long d_flags; ++ ++ CRYPTO_DRIVER_LOCK(); ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ const struct cryptocap *cap = &crypto_drivers[hid]; ++ ++ if ((cap->cc_flags & CRYPTOCAP_F_SOFTWARE) && ++ !crypto_devallowsoft) { ++ continue; ++ } ++ for (kalg = 0; kalg < CRK_ALGORITHM_MAX; kalg++) ++ if (cap->cc_kalg[kalg] & CRYPTO_ALG_FLAG_SUPPORTED) ++ feat |= 1 << kalg; ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ *featp = feat; ++ return (0); ++} ++ ++/* ++ * Crypto thread, dispatches crypto requests. ++ */ ++static int ++crypto_proc(void *arg) ++{ ++ struct cryptop *crp, *submit; ++ struct cryptkop *krp, *krpp; ++ struct cryptocap *cap; ++ u_int32_t hid; ++ int result, hint; ++ unsigned long q_flags; ++ int loopcount = 0; ++ ++ ocf_daemonize("crypto"); ++ ++ CRYPTO_Q_LOCK(); ++ for (;;) { ++ /* ++ * we need to make sure we don't get into a busy loop with nothing ++ * to do, the two crypto_all_*blocked vars help us find out when ++ * we are all full and can do nothing on any driver or Q. If so we ++ * wait for an unblock. ++ */ ++ crypto_all_qblocked = !list_empty(&crp_q); ++ ++ /* ++ * Find the first element in the queue that can be ++ * processed and look-ahead to see if multiple ops ++ * are ready for the same driver. ++ */ ++ submit = NULL; ++ hint = 0; ++ list_for_each_entry(crp, &crp_q, crp_next) { ++ hid = CRYPTO_SESID2HID(crp->crp_sid); ++ cap = crypto_checkdriver(hid); ++ /* ++ * Driver cannot disappear when there is an active ++ * session. ++ */ ++ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", ++ __func__, __LINE__)); ++ if (cap == NULL || cap->cc_dev == NULL) { ++ /* Op needs to be migrated, process it. */ ++ if (submit == NULL) ++ submit = crp; ++ break; ++ } ++ if (!cap->cc_qblocked) { ++ if (submit != NULL) { ++ /* ++ * We stop on finding another op, ++ * regardless whether its for the same ++ * driver or not. We could keep ++ * searching the queue but it might be ++ * better to just use a per-driver ++ * queue instead. ++ */ ++ if (CRYPTO_SESID2HID(submit->crp_sid) == hid) ++ hint = CRYPTO_HINT_MORE; ++ break; ++ } else { ++ submit = crp; ++ if ((submit->crp_flags & CRYPTO_F_BATCH) == 0) ++ break; ++ /* keep scanning for more are q'd */ ++ } ++ } ++ } ++ if (submit != NULL) { ++ hid = CRYPTO_SESID2HID(submit->crp_sid); ++ crypto_all_qblocked = 0; ++ list_del(&submit->crp_next); ++ crypto_drivers[hid].cc_unqblocked = 1; ++ cap = crypto_checkdriver(hid); ++ CRYPTO_Q_UNLOCK(); ++ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", ++ __func__, __LINE__)); ++ result = crypto_invoke(cap, submit, hint); ++ CRYPTO_Q_LOCK(); ++ if (result == ERESTART) { ++ /* ++ * The driver ran out of resources, mark the ++ * driver ``blocked'' for cryptop's and put ++ * the request back in the queue. It would ++ * best to put the request back where we got ++ * it but that's hard so for now we put it ++ * at the front. This should be ok; putting ++ * it at the end does not work. ++ */ ++ /* XXX validate sid again? */ ++ list_add(&submit->crp_next, &crp_q); ++ cryptostats.cs_blocks++; ++ if (crypto_drivers[hid].cc_unqblocked) ++ crypto_drivers[hid].cc_qblocked=0; ++ crypto_drivers[hid].cc_unqblocked=0; ++ } ++ crypto_drivers[hid].cc_unqblocked = 0; ++ } ++ ++ crypto_all_kqblocked = !list_empty(&crp_kq); ++ ++ /* As above, but for key ops */ ++ krp = NULL; ++ list_for_each_entry(krpp, &crp_kq, krp_next) { ++ cap = crypto_checkdriver(krpp->krp_hid); ++ if (cap == NULL || cap->cc_dev == NULL) { ++ /* ++ * Operation needs to be migrated, invalidate ++ * the assigned device so it will reselect a ++ * new one below. Propagate the original ++ * crid selection flags if supplied. ++ */ ++ krp->krp_hid = krp->krp_crid & ++ (CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE); ++ if (krp->krp_hid == 0) ++ krp->krp_hid = ++ CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE; ++ break; ++ } ++ if (!cap->cc_kqblocked) { ++ krp = krpp; ++ break; ++ } ++ } ++ if (krp != NULL) { ++ crypto_all_kqblocked = 0; ++ list_del(&krp->krp_next); ++ crypto_drivers[krp->krp_hid].cc_kqblocked = 1; ++ CRYPTO_Q_UNLOCK(); ++ result = crypto_kinvoke(krp, krp->krp_hid); ++ CRYPTO_Q_LOCK(); ++ if (result == ERESTART) { ++ /* ++ * The driver ran out of resources, mark the ++ * driver ``blocked'' for cryptkop's and put ++ * the request back in the queue. It would ++ * best to put the request back where we got ++ * it but that's hard so for now we put it ++ * at the front. This should be ok; putting ++ * it at the end does not work. ++ */ ++ /* XXX validate sid again? */ ++ list_add(&krp->krp_next, &crp_kq); ++ cryptostats.cs_kblocks++; ++ } else ++ crypto_drivers[krp->krp_hid].cc_kqblocked = 0; ++ } ++ ++ if (submit == NULL && krp == NULL) { ++ /* ++ * Nothing more to be processed. Sleep until we're ++ * woken because there are more ops to process. ++ * This happens either by submission or by a driver ++ * becoming unblocked and notifying us through ++ * crypto_unblock. Note that when we wakeup we ++ * start processing each queue again from the ++ * front. It's not clear that it's important to ++ * preserve this ordering since ops may finish ++ * out of order if dispatched to different devices ++ * and some become blocked while others do not. ++ */ ++ dprintk("%s - sleeping (qe=%d qb=%d kqe=%d kqb=%d)\n", ++ __FUNCTION__, ++ list_empty(&crp_q), crypto_all_qblocked, ++ list_empty(&crp_kq), crypto_all_kqblocked); ++ loopcount = 0; ++ CRYPTO_Q_UNLOCK(); ++ crp_sleep = 1; ++ wait_event_interruptible(cryptoproc_wait, ++ !(list_empty(&crp_q) || crypto_all_qblocked) || ++ !(list_empty(&crp_kq) || crypto_all_kqblocked) || ++ cryptoproc == (pid_t) -1); ++ crp_sleep = 0; ++ if (signal_pending (current)) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_lock_irq(¤t->sigmask_lock); ++#endif ++ flush_signals(current); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_unlock_irq(¤t->sigmask_lock); ++#endif ++ } ++ CRYPTO_Q_LOCK(); ++ dprintk("%s - awake\n", __FUNCTION__); ++ if (cryptoproc == (pid_t) -1) ++ break; ++ cryptostats.cs_intrs++; ++ } else if (loopcount > crypto_max_loopcount) { ++ /* ++ * Give other processes a chance to run if we've ++ * been using the CPU exclusively for a while. ++ */ ++ loopcount = 0; ++ schedule(); ++ } ++ loopcount++; ++ } ++ CRYPTO_Q_UNLOCK(); ++ complete_and_exit(&cryptoproc_exited, 0); ++} ++ ++/* ++ * Crypto returns thread, does callbacks for processed crypto requests. ++ * Callbacks are done here, rather than in the crypto drivers, because ++ * callbacks typically are expensive and would slow interrupt handling. ++ */ ++static int ++crypto_ret_proc(void *arg) ++{ ++ struct cryptop *crpt; ++ struct cryptkop *krpt; ++ unsigned long r_flags; ++ ++ ocf_daemonize("crypto_ret"); ++ ++ CRYPTO_RETQ_LOCK(); ++ for (;;) { ++ /* Harvest return q's for completed ops */ ++ crpt = NULL; ++ if (!list_empty(&crp_ret_q)) ++ crpt = list_entry(crp_ret_q.next, typeof(*crpt), crp_next); ++ if (crpt != NULL) ++ list_del(&crpt->crp_next); ++ ++ krpt = NULL; ++ if (!list_empty(&crp_ret_kq)) ++ krpt = list_entry(crp_ret_kq.next, typeof(*krpt), krp_next); ++ if (krpt != NULL) ++ list_del(&krpt->krp_next); ++ ++ if (crpt != NULL || krpt != NULL) { ++ CRYPTO_RETQ_UNLOCK(); ++ /* ++ * Run callbacks unlocked. ++ */ ++ if (crpt != NULL) ++ crpt->crp_callback(crpt); ++ if (krpt != NULL) ++ krpt->krp_callback(krpt); ++ CRYPTO_RETQ_LOCK(); ++ } else { ++ /* ++ * Nothing more to be processed. Sleep until we're ++ * woken because there are more returns to process. ++ */ ++ dprintk("%s - sleeping\n", __FUNCTION__); ++ CRYPTO_RETQ_UNLOCK(); ++ wait_event_interruptible(cryptoretproc_wait, ++ cryptoretproc == (pid_t) -1 || ++ !list_empty(&crp_ret_q) || ++ !list_empty(&crp_ret_kq)); ++ if (signal_pending (current)) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_lock_irq(¤t->sigmask_lock); ++#endif ++ flush_signals(current); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_unlock_irq(¤t->sigmask_lock); ++#endif ++ } ++ CRYPTO_RETQ_LOCK(); ++ dprintk("%s - awake\n", __FUNCTION__); ++ if (cryptoretproc == (pid_t) -1) { ++ dprintk("%s - EXITING!\n", __FUNCTION__); ++ break; ++ } ++ cryptostats.cs_rets++; ++ } ++ } ++ CRYPTO_RETQ_UNLOCK(); ++ complete_and_exit(&cryptoretproc_exited, 0); ++} ++ ++ ++#if 0 /* should put this into /proc or something */ ++static void ++db_show_drivers(void) ++{ ++ int hid; ++ ++ db_printf("%12s %4s %4s %8s %2s %2s\n" ++ , "Device" ++ , "Ses" ++ , "Kops" ++ , "Flags" ++ , "QB" ++ , "KB" ++ ); ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ const struct cryptocap *cap = &crypto_drivers[hid]; ++ if (cap->cc_dev == NULL) ++ continue; ++ db_printf("%-12s %4u %4u %08x %2u %2u\n" ++ , device_get_nameunit(cap->cc_dev) ++ , cap->cc_sessions ++ , cap->cc_koperations ++ , cap->cc_flags ++ , cap->cc_qblocked ++ , cap->cc_kqblocked ++ ); ++ } ++} ++ ++DB_SHOW_COMMAND(crypto, db_show_crypto) ++{ ++ struct cryptop *crp; ++ ++ db_show_drivers(); ++ db_printf("\n"); ++ ++ db_printf("%4s %8s %4s %4s %4s %4s %8s %8s\n", ++ "HID", "Caps", "Ilen", "Olen", "Etype", "Flags", ++ "Desc", "Callback"); ++ TAILQ_FOREACH(crp, &crp_q, crp_next) { ++ db_printf("%4u %08x %4u %4u %4u %04x %8p %8p\n" ++ , (int) CRYPTO_SESID2HID(crp->crp_sid) ++ , (int) CRYPTO_SESID2CAPS(crp->crp_sid) ++ , crp->crp_ilen, crp->crp_olen ++ , crp->crp_etype ++ , crp->crp_flags ++ , crp->crp_desc ++ , crp->crp_callback ++ ); ++ } ++ if (!TAILQ_EMPTY(&crp_ret_q)) { ++ db_printf("\n%4s %4s %4s %8s\n", ++ "HID", "Etype", "Flags", "Callback"); ++ TAILQ_FOREACH(crp, &crp_ret_q, crp_next) { ++ db_printf("%4u %4u %04x %8p\n" ++ , (int) CRYPTO_SESID2HID(crp->crp_sid) ++ , crp->crp_etype ++ , crp->crp_flags ++ , crp->crp_callback ++ ); ++ } ++ } ++} ++ ++DB_SHOW_COMMAND(kcrypto, db_show_kcrypto) ++{ ++ struct cryptkop *krp; ++ ++ db_show_drivers(); ++ db_printf("\n"); ++ ++ db_printf("%4s %5s %4s %4s %8s %4s %8s\n", ++ "Op", "Status", "#IP", "#OP", "CRID", "HID", "Callback"); ++ TAILQ_FOREACH(krp, &crp_kq, krp_next) { ++ db_printf("%4u %5u %4u %4u %08x %4u %8p\n" ++ , krp->krp_op ++ , krp->krp_status ++ , krp->krp_iparams, krp->krp_oparams ++ , krp->krp_crid, krp->krp_hid ++ , krp->krp_callback ++ ); ++ } ++ if (!TAILQ_EMPTY(&crp_ret_q)) { ++ db_printf("%4s %5s %8s %4s %8s\n", ++ "Op", "Status", "CRID", "HID", "Callback"); ++ TAILQ_FOREACH(krp, &crp_ret_kq, krp_next) { ++ db_printf("%4u %5u %08x %4u %8p\n" ++ , krp->krp_op ++ , krp->krp_status ++ , krp->krp_crid, krp->krp_hid ++ , krp->krp_callback ++ ); ++ } ++ } ++} ++#endif ++ ++ ++static int ++crypto_init(void) ++{ ++ int error; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, (void *) crypto_init); ++ ++ if (crypto_initted) ++ return 0; ++ crypto_initted = 1; ++ ++ spin_lock_init(&crypto_drivers_lock); ++ spin_lock_init(&crypto_q_lock); ++ spin_lock_init(&crypto_ret_q_lock); ++ ++ cryptop_zone = kmem_cache_create("cryptop", sizeof(struct cryptop), ++ 0, SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ ++ cryptodesc_zone = kmem_cache_create("cryptodesc", sizeof(struct cryptodesc), ++ 0, SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ ++ if (cryptodesc_zone == NULL || cryptop_zone == NULL) { ++ printk("crypto: crypto_init cannot setup crypto zones\n"); ++ error = ENOMEM; ++ goto bad; ++ } ++ ++ crypto_drivers_num = CRYPTO_DRIVERS_INITIAL; ++ crypto_drivers = kmalloc(crypto_drivers_num * sizeof(struct cryptocap), ++ GFP_KERNEL); ++ if (crypto_drivers == NULL) { ++ printk("crypto: crypto_init cannot setup crypto drivers\n"); ++ error = ENOMEM; ++ goto bad; ++ } ++ ++ memset(crypto_drivers, 0, crypto_drivers_num * sizeof(struct cryptocap)); ++ ++ init_completion(&cryptoproc_exited); ++ init_completion(&cryptoretproc_exited); ++ ++ cryptoproc = 0; /* to avoid race condition where proc runs first */ ++ cryptoproc = kernel_thread(crypto_proc, NULL, CLONE_FS|CLONE_FILES); ++ if (cryptoproc < 0) { ++ error = cryptoproc; ++ printk("crypto: crypto_init cannot start crypto thread; error %d", ++ error); ++ goto bad; ++ } ++ ++ cryptoretproc = 0; /* to avoid race condition where proc runs first */ ++ cryptoretproc = kernel_thread(crypto_ret_proc, NULL, CLONE_FS|CLONE_FILES); ++ if (cryptoretproc < 0) { ++ error = cryptoretproc; ++ printk("crypto: crypto_init cannot start cryptoret thread; error %d", ++ error); ++ goto bad; ++ } ++ ++ return 0; ++bad: ++ crypto_exit(); ++ return error; ++} ++ ++ ++static void ++crypto_exit(void) ++{ ++ pid_t p; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* ++ * Terminate any crypto threads. ++ */ ++ ++ CRYPTO_DRIVER_LOCK(); ++ p = cryptoproc; ++ cryptoproc = (pid_t) -1; ++ kill_proc(p, SIGTERM, 1); ++ wake_up_interruptible(&cryptoproc_wait); ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ wait_for_completion(&cryptoproc_exited); ++ ++ CRYPTO_DRIVER_LOCK(); ++ p = cryptoretproc; ++ cryptoretproc = (pid_t) -1; ++ kill_proc(p, SIGTERM, 1); ++ wake_up_interruptible(&cryptoretproc_wait); ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ wait_for_completion(&cryptoretproc_exited); ++ ++ /* XXX flush queues??? */ ++ ++ /* ++ * Reclaim dynamically allocated resources. ++ */ ++ if (crypto_drivers != NULL) ++ kfree(crypto_drivers); ++ ++ if (cryptodesc_zone != NULL) ++ kmem_cache_destroy(cryptodesc_zone); ++ if (cryptop_zone != NULL) ++ kmem_cache_destroy(cryptop_zone); ++} ++ ++ ++EXPORT_SYMBOL(crypto_newsession); ++EXPORT_SYMBOL(crypto_freesession); ++EXPORT_SYMBOL(crypto_get_driverid); ++EXPORT_SYMBOL(crypto_kregister); ++EXPORT_SYMBOL(crypto_register); ++EXPORT_SYMBOL(crypto_unregister); ++EXPORT_SYMBOL(crypto_unregister_all); ++EXPORT_SYMBOL(crypto_unblock); ++EXPORT_SYMBOL(crypto_dispatch); ++EXPORT_SYMBOL(crypto_kdispatch); ++EXPORT_SYMBOL(crypto_freereq); ++EXPORT_SYMBOL(crypto_getreq); ++EXPORT_SYMBOL(crypto_done); ++EXPORT_SYMBOL(crypto_kdone); ++EXPORT_SYMBOL(crypto_getfeat); ++EXPORT_SYMBOL(crypto_userasymcrypto); ++EXPORT_SYMBOL(crypto_getcaps); ++EXPORT_SYMBOL(crypto_find_driver); ++EXPORT_SYMBOL(crypto_find_device_byhid); ++ ++module_init(crypto_init); ++module_exit(crypto_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("OCF (OpenBSD Cryptographic Framework)"); +diff -Nur linux-2.6.39.orig/crypto/ocf/cryptocteon/Makefile linux-2.6.39/crypto/ocf/cryptocteon/Makefile +--- linux-2.6.39.orig/crypto/ocf/cryptocteon/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/cryptocteon/Makefile 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,17 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef CONFIG_OCF_CRYPTOCTEON ++# you need the cavium crypto component installed ++EXTRA_CFLAGS += -I$(ROOTDIR)/prop/include ++endif ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/cryptocteon/cavium_crypto.c linux-2.6.39/crypto/ocf/cryptocteon/cavium_crypto.c +--- linux-2.6.39.orig/crypto/ocf/cryptocteon/cavium_crypto.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/cryptocteon/cavium_crypto.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,2283 @@ ++/* ++ * Copyright (c) 2009 David McCullough ++ * ++ * Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights ++ * reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by Cavium Networks ++ * 4. Cavium Networks' name may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * This Software, including technical data, may be subject to U.S. export ++ * control laws, including the U.S. Export Administration Act and its ++ * associated regulations, and may be subject to export or import regulations ++ * in other countries. You warrant that You will comply strictly in all ++ * respects with all such regulations and acknowledge that you have the ++ * responsibility to obtain licenses to export, re-export or import the ++ * Software. ++ * ++ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" AND ++ * WITH ALL FAULTS AND CAVIUM MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, ++ * EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE ++ * SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR ++ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM ++ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, ++ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF ++ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR ++ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR ++ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ++*/ ++/****************************************************************************/ ++ ++#include ++#include ++#include "octeon-asm.h" ++ ++/****************************************************************************/ ++ ++extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *); ++extern void octeon_crypto_disable(struct octeon_cop2_state *, unsigned long); ++ ++#define SG_INIT(s, p, i, l) \ ++ { \ ++ (i) = 0; \ ++ (l) = (s)[0].length; \ ++ (p) = (typeof(p)) sg_virt((s)); \ ++ CVMX_PREFETCH0((p)); \ ++ } ++ ++#define SG_CONSUME(s, p, i, l) \ ++ { \ ++ (p)++; \ ++ (l) -= sizeof(*(p)); \ ++ if ((l) < 0) { \ ++ dprintk("%s, %d: l = %d\n", __FILE__, __LINE__, l); \ ++ } else if ((l) == 0) { \ ++ (i)++; \ ++ (l) = (s)[0].length; \ ++ (p) = (typeof(p)) sg_virt(s); \ ++ CVMX_PREFETCH0((p)); \ ++ } \ ++ } ++ ++#define ESP_HEADER_LENGTH 8 ++#define DES_CBC_IV_LENGTH 8 ++#define AES_CBC_IV_LENGTH 16 ++#define ESP_HMAC_LEN 12 ++ ++#define ESP_HEADER_LENGTH 8 ++#define DES_CBC_IV_LENGTH 8 ++ ++/****************************************************************************/ ++ ++#define CVM_LOAD_SHA_UNIT(dat, next) { \ ++ if (next == 0) { \ ++ next = 1; \ ++ CVMX_MT_HSH_DAT (dat, 0); \ ++ } else if (next == 1) { \ ++ next = 2; \ ++ CVMX_MT_HSH_DAT (dat, 1); \ ++ } else if (next == 2) { \ ++ next = 3; \ ++ CVMX_MT_HSH_DAT (dat, 2); \ ++ } else if (next == 3) { \ ++ next = 4; \ ++ CVMX_MT_HSH_DAT (dat, 3); \ ++ } else if (next == 4) { \ ++ next = 5; \ ++ CVMX_MT_HSH_DAT (dat, 4); \ ++ } else if (next == 5) { \ ++ next = 6; \ ++ CVMX_MT_HSH_DAT (dat, 5); \ ++ } else if (next == 6) { \ ++ next = 7; \ ++ CVMX_MT_HSH_DAT (dat, 6); \ ++ } else { \ ++ CVMX_MT_HSH_STARTSHA (dat); \ ++ next = 0; \ ++ } \ ++} ++ ++#define CVM_LOAD2_SHA_UNIT(dat1, dat2, next) { \ ++ if (next == 0) { \ ++ CVMX_MT_HSH_DAT (dat1, 0); \ ++ CVMX_MT_HSH_DAT (dat2, 1); \ ++ next = 2; \ ++ } else if (next == 1) { \ ++ CVMX_MT_HSH_DAT (dat1, 1); \ ++ CVMX_MT_HSH_DAT (dat2, 2); \ ++ next = 3; \ ++ } else if (next == 2) { \ ++ CVMX_MT_HSH_DAT (dat1, 2); \ ++ CVMX_MT_HSH_DAT (dat2, 3); \ ++ next = 4; \ ++ } else if (next == 3) { \ ++ CVMX_MT_HSH_DAT (dat1, 3); \ ++ CVMX_MT_HSH_DAT (dat2, 4); \ ++ next = 5; \ ++ } else if (next == 4) { \ ++ CVMX_MT_HSH_DAT (dat1, 4); \ ++ CVMX_MT_HSH_DAT (dat2, 5); \ ++ next = 6; \ ++ } else if (next == 5) { \ ++ CVMX_MT_HSH_DAT (dat1, 5); \ ++ CVMX_MT_HSH_DAT (dat2, 6); \ ++ next = 7; \ ++ } else if (next == 6) { \ ++ CVMX_MT_HSH_DAT (dat1, 6); \ ++ CVMX_MT_HSH_STARTSHA (dat2); \ ++ next = 0; \ ++ } else { \ ++ CVMX_MT_HSH_STARTSHA (dat1); \ ++ CVMX_MT_HSH_DAT (dat2, 0); \ ++ next = 1; \ ++ } \ ++} ++ ++/****************************************************************************/ ++ ++#define CVM_LOAD_MD5_UNIT(dat, next) { \ ++ if (next == 0) { \ ++ next = 1; \ ++ CVMX_MT_HSH_DAT (dat, 0); \ ++ } else if (next == 1) { \ ++ next = 2; \ ++ CVMX_MT_HSH_DAT (dat, 1); \ ++ } else if (next == 2) { \ ++ next = 3; \ ++ CVMX_MT_HSH_DAT (dat, 2); \ ++ } else if (next == 3) { \ ++ next = 4; \ ++ CVMX_MT_HSH_DAT (dat, 3); \ ++ } else if (next == 4) { \ ++ next = 5; \ ++ CVMX_MT_HSH_DAT (dat, 4); \ ++ } else if (next == 5) { \ ++ next = 6; \ ++ CVMX_MT_HSH_DAT (dat, 5); \ ++ } else if (next == 6) { \ ++ next = 7; \ ++ CVMX_MT_HSH_DAT (dat, 6); \ ++ } else { \ ++ CVMX_MT_HSH_STARTMD5 (dat); \ ++ next = 0; \ ++ } \ ++} ++ ++#define CVM_LOAD2_MD5_UNIT(dat1, dat2, next) { \ ++ if (next == 0) { \ ++ CVMX_MT_HSH_DAT (dat1, 0); \ ++ CVMX_MT_HSH_DAT (dat2, 1); \ ++ next = 2; \ ++ } else if (next == 1) { \ ++ CVMX_MT_HSH_DAT (dat1, 1); \ ++ CVMX_MT_HSH_DAT (dat2, 2); \ ++ next = 3; \ ++ } else if (next == 2) { \ ++ CVMX_MT_HSH_DAT (dat1, 2); \ ++ CVMX_MT_HSH_DAT (dat2, 3); \ ++ next = 4; \ ++ } else if (next == 3) { \ ++ CVMX_MT_HSH_DAT (dat1, 3); \ ++ CVMX_MT_HSH_DAT (dat2, 4); \ ++ next = 5; \ ++ } else if (next == 4) { \ ++ CVMX_MT_HSH_DAT (dat1, 4); \ ++ CVMX_MT_HSH_DAT (dat2, 5); \ ++ next = 6; \ ++ } else if (next == 5) { \ ++ CVMX_MT_HSH_DAT (dat1, 5); \ ++ CVMX_MT_HSH_DAT (dat2, 6); \ ++ next = 7; \ ++ } else if (next == 6) { \ ++ CVMX_MT_HSH_DAT (dat1, 6); \ ++ CVMX_MT_HSH_STARTMD5 (dat2); \ ++ next = 0; \ ++ } else { \ ++ CVMX_MT_HSH_STARTMD5 (dat1); \ ++ CVMX_MT_HSH_DAT (dat2, 0); \ ++ next = 1; \ ++ } \ ++} ++ ++/****************************************************************************/ ++ ++static inline uint64_t ++swap64(uint64_t a) ++{ ++ return ((a >> 56) | ++ (((a >> 48) & 0xfful) << 8) | ++ (((a >> 40) & 0xfful) << 16) | ++ (((a >> 32) & 0xfful) << 24) | ++ (((a >> 24) & 0xfful) << 32) | ++ (((a >> 16) & 0xfful) << 40) | ++ (((a >> 8) & 0xfful) << 48) | (((a >> 0) & 0xfful) << 56)); ++} ++ ++/****************************************************************************/ ++ ++void ++octo_calc_hash(__u8 auth, unsigned char *key, uint64_t *inner, uint64_t *outer) ++{ ++ uint8_t hash_key[64]; ++ uint64_t *key1; ++ register uint64_t xor1 = 0x3636363636363636ULL; ++ register uint64_t xor2 = 0x5c5c5c5c5c5c5c5cULL; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ memset(hash_key, 0, sizeof(hash_key)); ++ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); ++ key1 = (uint64_t *) hash_key; ++ flags = octeon_crypto_enable(&state); ++ if (auth) { ++ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); ++ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); ++ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); ++ } else { ++ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); ++ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); ++ } ++ ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 0); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 1); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 2); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 3); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 4); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 5); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 6); ++ key1++; ++ if (auth) ++ CVMX_MT_HSH_STARTSHA((*key1 ^ xor1)); ++ else ++ CVMX_MT_HSH_STARTMD5((*key1 ^ xor1)); ++ ++ CVMX_MF_HSH_IV(inner[0], 0); ++ CVMX_MF_HSH_IV(inner[1], 1); ++ if (auth) { ++ inner[2] = 0; ++ CVMX_MF_HSH_IV(((uint64_t *) inner)[2], 2); ++ } ++ ++ memset(hash_key, 0, sizeof(hash_key)); ++ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); ++ key1 = (uint64_t *) hash_key; ++ if (auth) { ++ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); ++ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); ++ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); ++ } else { ++ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); ++ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); ++ } ++ ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 0); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 1); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 2); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 3); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 4); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 5); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 6); ++ key1++; ++ if (auth) ++ CVMX_MT_HSH_STARTSHA((*key1 ^ xor2)); ++ else ++ CVMX_MT_HSH_STARTMD5((*key1 ^ xor2)); ++ ++ CVMX_MF_HSH_IV(outer[0], 0); ++ CVMX_MF_HSH_IV(outer[1], 1); ++ if (auth) { ++ outer[2] = 0; ++ CVMX_MF_HSH_IV(outer[2], 2); ++ } ++ octeon_crypto_disable(&state, flags); ++ return; ++} ++ ++/****************************************************************************/ ++/* DES functions */ ++ ++int ++octo_des_cbc_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ CVMX_MT_3DES_ENC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 8; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++ ++int ++octo_des_cbc_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ CVMX_MT_3DES_DEC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 8; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* AES functions */ ++ ++int ++octo_aes_cbc_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data, *pdata; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ pdata = data; ++ CVMX_MT_AES_ENC_CBC0(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MT_AES_ENC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 16; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++ ++int ++octo_aes_cbc_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data, *pdata; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ pdata = data; ++ CVMX_MT_AES_DEC_CBC0(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MT_AES_DEC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 16; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* MD5 */ ++ ++int ++octo_null_md5_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ uint64_t *data; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ++ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (auth_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ auth_off -= 8; ++ } ++ ++ while (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ SG_CONSUME(sg, data, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ icv_off -= 8; ++ } ++ CVMX_MF_HSH_IV(*data, 0); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* SHA1 */ ++ ++int ++octo_null_sha1_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ uint64_t *data; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ++ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (auth_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ auth_off -= 8; ++ } ++ ++ while (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ SG_CONSUME(sg, data, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ icv_off -= 8; ++ } ++ CVMX_MF_HSH_IV(*data, 0); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* DES MD5 */ ++ ++int ++octo_des_cbc_md5_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_ENC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_des_cbc_md5_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_DEC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* DES SHA */ ++ ++int ++octo_des_cbc_sha1_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_ENC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_des_cbc_sha1_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_DEC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* AES MD5 */ ++ ++int ++octo_aes_cbc_md5_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ ++ mydata[1].data32[1] = *data32; ++ ++ CVMX_MT_AES_ENC_CBC0(*pdata); ++ CVMX_MT_AES_ENC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish any left over hashing */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_aes_cbc_md5_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[1].data32[1] = *data32; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ CVMX_MT_AES_DEC_CBC0(*pdata); ++ CVMX_MT_AES_DEC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish left over hash if any */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* AES SHA1 */ ++ ++int ++octo_aes_cbc_sha1_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", ++ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load SHA IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[1].data32[1] = *data32; ++ ++ CVMX_MT_AES_ENC_CBC0(*pdata); ++ CVMX_MT_AES_ENC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish and hashing */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_aes_cbc_sha1_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", ++ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[1].data32[1] = *data32; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ CVMX_MT_AES_DEC_CBC0(*pdata); ++ CVMX_MT_AES_DEC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish and leftover hashing */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ +diff -Nur linux-2.6.39.orig/crypto/ocf/cryptocteon/cryptocteon.c linux-2.6.39/crypto/ocf/cryptocteon/cryptocteon.c +--- linux-2.6.39.orig/crypto/ocf/cryptocteon/cryptocteon.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/cryptocteon/cryptocteon.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,574 @@ ++/* ++ * Octeon Crypto for OCF ++ * ++ * Written by David McCullough ++ * Copyright (C) 2009-2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ * --------------------------------------------------------------------------- ++ */ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++struct { ++ softc_device_decl sc_dev; ++} octo_softc; ++ ++#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) ++ ++struct octo_sess { ++ int octo_encalg; ++ #define MAX_CIPHER_KEYLEN 64 ++ char octo_enckey[MAX_CIPHER_KEYLEN]; ++ int octo_encklen; ++ ++ int octo_macalg; ++ #define MAX_HASH_KEYLEN 64 ++ char octo_mackey[MAX_HASH_KEYLEN]; ++ int octo_macklen; ++ int octo_mackey_set; ++ ++ int octo_mlen; ++ int octo_ivsize; ++ ++#if 0 ++ int (*octo_decrypt)(struct scatterlist *sg, int sg_len, ++ uint8_t *key, int key_len, uint8_t * iv, ++ uint64_t *hminner, uint64_t *hmouter); ++ ++ int (*octo_encrypt)(struct scatterlist *sg, int sg_len, ++ uint8_t *key, int key_len, uint8_t * iv, ++ uint64_t *hminner, uint64_t *hmouter); ++#else ++ int (*octo_encrypt)(struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp); ++ int (*octo_decrypt)(struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp); ++#endif ++ ++ uint64_t octo_hminner[3]; ++ uint64_t octo_hmouter[3]; ++}; ++ ++int32_t octo_id = -1; ++module_param(octo_id, int, 0444); ++MODULE_PARM_DESC(octo_id, "Read-Only OCF ID for cryptocteon driver"); ++ ++static struct octo_sess **octo_sessions = NULL; ++static u_int32_t octo_sesnum = 0; ++ ++static int octo_process(device_t, struct cryptop *, int); ++static int octo_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int octo_freesession(device_t, u_int64_t); ++ ++static device_method_t octo_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, octo_newsession), ++ DEVMETHOD(cryptodev_freesession,octo_freesession), ++ DEVMETHOD(cryptodev_process, octo_process), ++}; ++ ++#define debug octo_debug ++int octo_debug = 0; ++module_param(octo_debug, int, 0644); ++MODULE_PARM_DESC(octo_debug, "Enable debug"); ++ ++ ++#include "cavium_crypto.c" ++ ++ ++/* ++ * Generate a new octo session. We artifically limit it to a single ++ * hash/cipher or hash-cipher combo just to make it easier, most callers ++ * do not expect more than this anyway. ++ */ ++static int ++octo_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct octo_sess **ocd; ++ int i; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* ++ * To keep it simple, we only handle hash, cipher or hash/cipher in a ++ * session, you cannot currently do multiple ciphers/hashes in one ++ * session even though it would be possibel to code this driver to ++ * handle it. ++ */ ++ for (i = 0, c = cri; c && i < 2; i++) { ++ if (c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1_HMAC || ++ c->cri_alg == CRYPTO_NULL_HMAC) { ++ if (macini) { ++ break; ++ } ++ macini = c; ++ } ++ if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC || ++ c->cri_alg == CRYPTO_NULL_CBC) { ++ if (encini) { ++ break; ++ } ++ encini = c; ++ } ++ c = c->cri_next; ++ } ++ if (!macini && !encini) { ++ dprintk("%s,%d - EINVAL bad cipher/hash or combination\n", ++ __FILE__, __LINE__); ++ return EINVAL; ++ } ++ if (c) { ++ dprintk("%s,%d - EINVAL cannot handle chained cipher/hash combos\n", ++ __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* ++ * So we have something we can do, lets setup the session ++ */ ++ ++ if (octo_sessions) { ++ for (i = 1; i < octo_sesnum; i++) ++ if (octo_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (octo_sessions == NULL || i == octo_sesnum) { ++ if (octo_sessions == NULL) { ++ i = 1; /* We leave octo_sessions[0] empty */ ++ octo_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ octo_sesnum *= 2; ++ ++ ocd = kmalloc(octo_sesnum * sizeof(struct octo_sess *), SLAB_ATOMIC); ++ if (ocd == NULL) { ++ /* Reset session number */ ++ if (octo_sesnum == CRYPTO_SW_SESSIONS) ++ octo_sesnum = 0; ++ else ++ octo_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(ocd, 0, octo_sesnum * sizeof(struct octo_sess *)); ++ ++ /* Copy existing sessions */ ++ if (octo_sessions) { ++ memcpy(ocd, octo_sessions, ++ (octo_sesnum / 2) * sizeof(struct octo_sess *)); ++ kfree(octo_sessions); ++ } ++ ++ octo_sessions = ocd; ++ } ++ ++ ocd = &octo_sessions[i]; ++ *sid = i; ++ ++ ++ *ocd = (struct octo_sess *) kmalloc(sizeof(struct octo_sess), SLAB_ATOMIC); ++ if (*ocd == NULL) { ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(*ocd, 0, sizeof(struct octo_sess)); ++ ++ if (encini && encini->cri_key) { ++ (*ocd)->octo_encklen = (encini->cri_klen + 7) / 8; ++ memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen); ++ } ++ ++ if (macini && macini->cri_key) { ++ (*ocd)->octo_macklen = (macini->cri_klen + 7) / 8; ++ memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen); ++ } ++ ++ (*ocd)->octo_mlen = 0; ++ if (encini && encini->cri_mlen) ++ (*ocd)->octo_mlen = encini->cri_mlen; ++ else if (macini && macini->cri_mlen) ++ (*ocd)->octo_mlen = macini->cri_mlen; ++ else ++ (*ocd)->octo_mlen = 12; ++ ++ /* ++ * point c at the enc if it exists, otherwise the mac ++ */ ++ c = encini ? encini : macini; ++ ++ switch (c->cri_alg) { ++ case CRYPTO_DES_CBC: ++ case CRYPTO_3DES_CBC: ++ (*ocd)->octo_ivsize = 8; ++ switch (macini ? macini->cri_alg : -1) { ++ case CRYPTO_MD5_HMAC: ++ (*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt; ++ (*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt; ++ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ (*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt; ++ (*ocd)->octo_decrypt = octo_des_cbc_sha1_encrypt; ++ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case -1: ++ (*ocd)->octo_encrypt = octo_des_cbc_encrypt; ++ (*ocd)->octo_decrypt = octo_des_cbc_decrypt; ++ break; ++ default: ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ break; ++ case CRYPTO_AES_CBC: ++ (*ocd)->octo_ivsize = 16; ++ switch (macini ? macini->cri_alg : -1) { ++ case CRYPTO_MD5_HMAC: ++ (*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt; ++ (*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt; ++ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ (*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt; ++ (*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt; ++ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case -1: ++ (*ocd)->octo_encrypt = octo_aes_cbc_encrypt; ++ (*ocd)->octo_decrypt = octo_aes_cbc_decrypt; ++ break; ++ default: ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ break; ++ case CRYPTO_MD5_HMAC: ++ (*ocd)->octo_encrypt = octo_null_md5_encrypt; ++ (*ocd)->octo_decrypt = octo_null_md5_encrypt; ++ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ (*ocd)->octo_encrypt = octo_null_sha1_encrypt; ++ (*ocd)->octo_decrypt = octo_null_sha1_encrypt; ++ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ default: ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ (*ocd)->octo_encalg = encini ? encini->cri_alg : -1; ++ (*ocd)->octo_macalg = macini ? macini->cri_alg : -1; ++ ++ return 0; ++} ++ ++/* ++ * Free a session. ++ */ ++static int ++octo_freesession(device_t dev, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > octo_sesnum || octo_sessions == NULL || ++ octo_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ if (octo_sessions[sid]) ++ kfree(octo_sessions[sid]); ++ octo_sessions[sid] = NULL; ++ return 0; ++} ++ ++/* ++ * Process a request. ++ */ ++static int ++octo_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct cryptodesc *crd; ++ struct octo_sess *od; ++ u_int32_t lid; ++#define SCATTERLIST_MAX 16 ++ struct scatterlist sg[SCATTERLIST_MAX]; ++ int sg_num, sg_len; ++ struct sk_buff *skb = NULL; ++ struct uio *uiop = NULL; ++ struct cryptodesc *enccrd = NULL, *maccrd = NULL; ++ unsigned char *ivp = NULL; ++ unsigned char iv_data[HASH_MAX_LEN]; ++ int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= octo_sesnum || lid == 0 || octo_sessions == NULL || ++ octo_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ od = octo_sessions[lid]; ++ ++ /* ++ * do some error checking outside of the loop for SKB and IOV processing ++ * this leaves us with valid skb or uiop pointers for later ++ */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ skb = (struct sk_buff *) crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { ++ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, ++ skb_shinfo(skb)->nr_frags); ++ goto done; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ uiop = (struct uio *) crp->crp_buf; ++ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { ++ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, ++ uiop->uio_iovcnt); ++ goto done; ++ } ++ } ++ ++ /* point our enccrd and maccrd appropriately */ ++ crd = crp->crp_desc; ++ if (crd->crd_alg == od->octo_encalg) enccrd = crd; ++ if (crd->crd_alg == od->octo_macalg) maccrd = crd; ++ crd = crd->crd_next; ++ if (crd) { ++ if (crd->crd_alg == od->octo_encalg) enccrd = crd; ++ if (crd->crd_alg == od->octo_macalg) maccrd = crd; ++ crd = crd->crd_next; ++ } ++ if (crd) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: ENOENT - descriptors do not match session\n", ++ __FILE__, __LINE__); ++ goto done; ++ } ++ ++ if (enccrd) { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = enccrd->crd_iv; ++ } else { ++ ivp = iv_data; ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp); ++ } ++ ++ if (maccrd) { ++ auth_off = maccrd->crd_skip; ++ auth_len = maccrd->crd_len; ++ icv_off = maccrd->crd_inject; ++ } ++ ++ crypt_off = enccrd->crd_skip; ++ crypt_len = enccrd->crd_len; ++ } else { /* if (maccrd) */ ++ auth_off = maccrd->crd_skip; ++ auth_len = maccrd->crd_len; ++ icv_off = maccrd->crd_inject; ++ } ++ ++ ++ /* ++ * setup the SG list to cover the buffer ++ */ ++ memset(sg, 0, sizeof(sg)); ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ int i, len; ++ ++ sg_num = 0; ++ sg_len = 0; ++ ++ len = skb_headlen(skb); ++ sg_set_page(&sg[sg_num], virt_to_page(skb->data), len, ++ offset_in_page(skb->data)); ++ sg_len += len; ++ sg_num++; ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags && sg_num < SCATTERLIST_MAX; ++ i++) { ++ len = skb_shinfo(skb)->frags[i].size; ++ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, ++ len, skb_shinfo(skb)->frags[i].page_offset); ++ sg_len += len; ++ sg_num++; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ int len; ++ ++ sg_len = 0; ++ for (sg_num = 0; sg_len < crp->crp_ilen && ++ sg_num < uiop->uio_iovcnt && ++ sg_num < SCATTERLIST_MAX; sg_num++) { ++ len = uiop->uio_iov[sg_num].iov_len; ++ sg_set_page(&sg[sg_num], ++ virt_to_page(uiop->uio_iov[sg_num].iov_base), len, ++ offset_in_page(uiop->uio_iov[sg_num].iov_base)); ++ sg_len += len; ++ } ++ } else { ++ sg_len = crp->crp_ilen; ++ sg_set_page(&sg[0], virt_to_page(crp->crp_buf), sg_len, ++ offset_in_page(crp->crp_buf)); ++ sg_num = 1; ++ } ++ ++ ++ /* ++ * setup a new explicit key ++ */ ++ if (enccrd) { ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ od->octo_encklen = (enccrd->crd_klen + 7) / 8; ++ memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen); ++ } ++ } ++ if (maccrd) { ++ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ od->octo_macklen = (maccrd->crd_klen + 7) / 8; ++ memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen); ++ od->octo_mackey_set = 0; ++ } ++ if (!od->octo_mackey_set) { ++ octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1, ++ maccrd->crd_key, od->octo_hminner, od->octo_hmouter); ++ od->octo_mackey_set = 1; ++ } ++ } ++ ++ ++ if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT)) ++ (*od->octo_encrypt)(od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ else ++ (*od->octo_decrypt)(od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ ++done: ++ crypto_done(crp); ++ return 0; ++} ++ ++static int ++cryptocteon_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, cryptocteon_init); ++ ++ softc_device_init(&octo_softc, "cryptocteon", 0, octo_methods); ++ ++ octo_id = crypto_get_driverid(softc_get_device(&octo_softc), ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC); ++ if (octo_id < 0) { ++ printk("Cryptocteon device cannot initialize!"); ++ return -ENODEV; ++ } ++ ++ crypto_register(octo_id, CRYPTO_MD5_HMAC, 0,0); ++ crypto_register(octo_id, CRYPTO_SHA1_HMAC, 0,0); ++ //crypto_register(octo_id, CRYPTO_MD5, 0,0); ++ //crypto_register(octo_id, CRYPTO_SHA1, 0,0); ++ crypto_register(octo_id, CRYPTO_DES_CBC, 0,0); ++ crypto_register(octo_id, CRYPTO_3DES_CBC, 0,0); ++ crypto_register(octo_id, CRYPTO_AES_CBC, 0,0); ++ ++ return(0); ++} ++ ++static void ++cryptocteon_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(octo_id); ++ octo_id = -1; ++} ++ ++module_init(cryptocteon_init); ++module_exit(cryptocteon_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Cryptocteon (OCF module for Cavium OCTEON crypto)"); +diff -Nur linux-2.6.39.orig/crypto/ocf/cryptodev.c linux-2.6.39/crypto/ocf/cryptodev.c +--- linux-2.6.39.orig/crypto/ocf/cryptodev.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/cryptodev.c 2011-08-01 14:38:54.000000000 +0200 +@@ -0,0 +1,1057 @@ ++/* $OpenBSD: cryptodev.c,v 1.52 2002/06/19 07:22:46 deraadt Exp $ */ ++ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2001 Theo de Raadt ++ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++__FBSDID("$FreeBSD: src/sys/opencrypto/cryptodev.c,v 1.34 2007/05/09 19:37:02 gnn Exp $"); ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++extern asmlinkage long sys_dup(unsigned int fildes); ++ ++#define debug cryptodev_debug ++int cryptodev_debug = 0; ++module_param(cryptodev_debug, int, 0644); ++MODULE_PARM_DESC(cryptodev_debug, "Enable cryptodev debug"); ++ ++struct csession_info { ++ u_int16_t blocksize; ++ u_int16_t minkey, maxkey; ++ ++ u_int16_t keysize; ++ /* u_int16_t hashsize; */ ++ u_int16_t authsize; ++ u_int16_t authkey; ++ /* u_int16_t ctxsize; */ ++}; ++ ++struct csession { ++ struct list_head list; ++ u_int64_t sid; ++ u_int32_t ses; ++ ++ wait_queue_head_t waitq; ++ ++ u_int32_t cipher; ++ ++ u_int32_t mac; ++ ++ caddr_t key; ++ int keylen; ++ u_char tmp_iv[EALG_MAX_BLOCK_LEN]; ++ ++ caddr_t mackey; ++ int mackeylen; ++ ++ struct csession_info info; ++ ++ struct iovec iovec; ++ struct uio uio; ++ int error; ++}; ++ ++struct fcrypt { ++ struct list_head csessions; ++ int sesn; ++}; ++ ++static struct csession *csefind(struct fcrypt *, u_int); ++static int csedelete(struct fcrypt *, struct csession *); ++static struct csession *cseadd(struct fcrypt *, struct csession *); ++static struct csession *csecreate(struct fcrypt *, u_int64_t, ++ struct cryptoini *crie, struct cryptoini *cria, struct csession_info *); ++static int csefree(struct csession *); ++ ++static int cryptodev_op(struct csession *, struct crypt_op *); ++static int cryptodev_key(struct crypt_kop *); ++static int cryptodev_find(struct crypt_find_op *); ++ ++static int cryptodev_cb(void *); ++static int cryptodev_open(struct inode *inode, struct file *filp); ++ ++/* ++ * Check a crypto identifier to see if it requested ++ * a valid crid and it's capabilities match. ++ */ ++static int ++checkcrid(int crid) ++{ ++ int hid = crid & ~(CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); ++ int typ = crid & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); ++ int caps = 0; ++ ++ /* if the user hasn't selected a driver, then just call newsession */ ++ if (hid == 0 && typ != 0) ++ return 0; ++ ++ caps = crypto_getcaps(hid); ++ ++ /* didn't find anything with capabilities */ ++ if (caps == 0) { ++ dprintk("%s: hid=%x typ=%x not matched\n", __FUNCTION__, hid, typ); ++ return EINVAL; ++ } ++ ++ /* the user didn't specify SW or HW, so the driver is ok */ ++ if (typ == 0) ++ return 0; ++ ++ /* if the type specified didn't match */ ++ if (typ != (caps & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE))) { ++ dprintk("%s: hid=%x typ=%x caps=%x not matched\n", __FUNCTION__, ++ hid, typ, caps); ++ return EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int ++cryptodev_op(struct csession *cse, struct crypt_op *cop) ++{ ++ struct cryptop *crp = NULL; ++ struct cryptodesc *crde = NULL, *crda = NULL; ++ int error = 0; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (cop->len > CRYPTO_MAX_DATA_LEN) { ++ dprintk("%s: %d > %d\n", __FUNCTION__, cop->len, CRYPTO_MAX_DATA_LEN); ++ return (E2BIG); ++ } ++ ++ if (cse->info.blocksize && (cop->len % cse->info.blocksize) != 0) { ++ dprintk("%s: blocksize=%d len=%d\n", __FUNCTION__, cse->info.blocksize, ++ cop->len); ++ return (EINVAL); ++ } ++ ++ cse->uio.uio_iov = &cse->iovec; ++ cse->uio.uio_iovcnt = 1; ++ cse->uio.uio_offset = 0; ++#if 0 ++ cse->uio.uio_resid = cop->len; ++ cse->uio.uio_segflg = UIO_SYSSPACE; ++ cse->uio.uio_rw = UIO_WRITE; ++ cse->uio.uio_td = td; ++#endif ++ cse->uio.uio_iov[0].iov_len = cop->len; ++ if (cse->info.authsize) ++ cse->uio.uio_iov[0].iov_len += cse->info.authsize; ++ cse->uio.uio_iov[0].iov_base = kmalloc(cse->uio.uio_iov[0].iov_len, ++ GFP_KERNEL); ++ ++ if (cse->uio.uio_iov[0].iov_base == NULL) { ++ dprintk("%s: iov_base kmalloc(%d) failed\n", __FUNCTION__, ++ (int)cse->uio.uio_iov[0].iov_len); ++ return (ENOMEM); ++ } ++ ++ crp = crypto_getreq((cse->info.blocksize != 0) + (cse->info.authsize != 0)); ++ if (crp == NULL) { ++ dprintk("%s: ENOMEM\n", __FUNCTION__); ++ error = ENOMEM; ++ goto bail; ++ } ++ ++ if (cse->info.authsize && cse->info.blocksize) { ++ if (cop->op == COP_ENCRYPT) { ++ crde = crp->crp_desc; ++ crda = crde->crd_next; ++ } else { ++ crda = crp->crp_desc; ++ crde = crda->crd_next; ++ } ++ } else if (cse->info.authsize) { ++ crda = crp->crp_desc; ++ } else if (cse->info.blocksize) { ++ crde = crp->crp_desc; ++ } else { ++ dprintk("%s: bad request\n", __FUNCTION__); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ if ((error = copy_from_user(cse->uio.uio_iov[0].iov_base, cop->src, ++ cop->len))) { ++ dprintk("%s: bad copy\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (crda) { ++ crda->crd_skip = 0; ++ crda->crd_len = cop->len; ++ crda->crd_inject = cop->len; ++ ++ crda->crd_alg = cse->mac; ++ crda->crd_key = cse->mackey; ++ crda->crd_klen = cse->mackeylen * 8; ++ } ++ ++ if (crde) { ++ if (cop->op == COP_ENCRYPT) ++ crde->crd_flags |= CRD_F_ENCRYPT; ++ else ++ crde->crd_flags &= ~CRD_F_ENCRYPT; ++ crde->crd_len = cop->len; ++ crde->crd_inject = 0; ++ ++ crde->crd_alg = cse->cipher; ++ crde->crd_key = cse->key; ++ crde->crd_klen = cse->keylen * 8; ++ } ++ ++ crp->crp_ilen = cse->uio.uio_iov[0].iov_len; ++ crp->crp_flags = CRYPTO_F_IOV | CRYPTO_F_CBIMM ++ | (cop->flags & COP_F_BATCH); ++ crp->crp_buf = (caddr_t)&cse->uio; ++ crp->crp_callback = (int (*) (struct cryptop *)) cryptodev_cb; ++ crp->crp_sid = cse->sid; ++ crp->crp_opaque = (void *)cse; ++ ++ if (cop->iv) { ++ if (crde == NULL) { ++ error = EINVAL; ++ dprintk("%s no crde\n", __FUNCTION__); ++ goto bail; ++ } ++ if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ ++ error = EINVAL; ++ dprintk("%s arc4 with IV\n", __FUNCTION__); ++ goto bail; ++ } ++ if ((error = copy_from_user(cse->tmp_iv, cop->iv, ++ cse->info.blocksize))) { ++ dprintk("%s bad iv copy\n", __FUNCTION__); ++ goto bail; ++ } ++ memcpy(crde->crd_iv, cse->tmp_iv, cse->info.blocksize); ++ crde->crd_flags |= CRD_F_IV_EXPLICIT | CRD_F_IV_PRESENT; ++ crde->crd_skip = 0; ++ } else if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ ++ crde->crd_skip = 0; ++ } else if (crde) { ++ crde->crd_flags |= CRD_F_IV_PRESENT; ++ crde->crd_skip = cse->info.blocksize; ++ crde->crd_len -= cse->info.blocksize; ++ } ++ ++ if (cop->mac && crda == NULL) { ++ error = EINVAL; ++ dprintk("%s no crda\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ /* ++ * Let the dispatch run unlocked, then, interlock against the ++ * callback before checking if the operation completed and going ++ * to sleep. This insures drivers don't inherit our lock which ++ * results in a lock order reversal between crypto_dispatch forced ++ * entry and the crypto_done callback into us. ++ */ ++ error = crypto_dispatch(crp); ++ if (error) { ++ dprintk("%s error in crypto_dispatch\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ dprintk("%s about to WAIT\n", __FUNCTION__); ++ /* ++ * we really need to wait for driver to complete to maintain ++ * state, luckily interrupts will be remembered ++ */ ++ do { ++ error = wait_event_interruptible(crp->crp_waitq, ++ ((crp->crp_flags & CRYPTO_F_DONE) != 0)); ++ /* ++ * we can't break out of this loop or we will leave behind ++ * a huge mess, however, staying here means if your driver ++ * is broken user applications can hang and not be killed. ++ * The solution, fix your driver :-) ++ */ ++ if (error) { ++ schedule(); ++ error = 0; ++ } ++ } while ((crp->crp_flags & CRYPTO_F_DONE) == 0); ++ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); ++ ++ if (crp->crp_etype != 0) { ++ error = crp->crp_etype; ++ dprintk("%s error in crp processing\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (cse->error) { ++ error = cse->error; ++ dprintk("%s error in cse processing\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (cop->dst && (error = copy_to_user(cop->dst, ++ cse->uio.uio_iov[0].iov_base, cop->len))) { ++ dprintk("%s bad dst copy\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (cop->mac && ++ (error=copy_to_user(cop->mac, ++ (caddr_t)cse->uio.uio_iov[0].iov_base + cop->len, ++ cse->info.authsize))) { ++ dprintk("%s bad mac copy\n", __FUNCTION__); ++ goto bail; ++ } ++ ++bail: ++ if (crp) ++ crypto_freereq(crp); ++ if (cse->uio.uio_iov[0].iov_base) ++ kfree(cse->uio.uio_iov[0].iov_base); ++ ++ return (error); ++} ++ ++static int ++cryptodev_cb(void *op) ++{ ++ struct cryptop *crp = (struct cryptop *) op; ++ struct csession *cse = (struct csession *)crp->crp_opaque; ++ int error; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ error = crp->crp_etype; ++ if (error == EAGAIN) { ++ crp->crp_flags &= ~CRYPTO_F_DONE; ++#ifdef NOTYET ++ /* ++ * DAVIDM I am fairly sure that we should turn this into a batch ++ * request to stop bad karma/lockup, revisit ++ */ ++ crp->crp_flags |= CRYPTO_F_BATCH; ++#endif ++ return crypto_dispatch(crp); ++ } ++ if (error != 0 || (crp->crp_flags & CRYPTO_F_DONE)) { ++ cse->error = error; ++ wake_up_interruptible(&crp->crp_waitq); ++ } ++ return (0); ++} ++ ++static int ++cryptodevkey_cb(void *op) ++{ ++ struct cryptkop *krp = (struct cryptkop *) op; ++ dprintk("%s()\n", __FUNCTION__); ++ wake_up_interruptible(&krp->krp_waitq); ++ return (0); ++} ++ ++static int ++cryptodev_key(struct crypt_kop *kop) ++{ ++ struct cryptkop *krp = NULL; ++ int error = EINVAL; ++ int in, out, size, i; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (kop->crk_iparams + kop->crk_oparams > CRK_MAXPARAM) { ++ dprintk("%s params too big\n", __FUNCTION__); ++ return (EFBIG); ++ } ++ ++ in = kop->crk_iparams; ++ out = kop->crk_oparams; ++ switch (kop->crk_op) { ++ case CRK_MOD_EXP: ++ if (in == 3 && out == 1) ++ break; ++ return (EINVAL); ++ case CRK_MOD_EXP_CRT: ++ if (in == 6 && out == 1) ++ break; ++ return (EINVAL); ++ case CRK_DSA_SIGN: ++ if (in == 5 && out == 2) ++ break; ++ return (EINVAL); ++ case CRK_DSA_VERIFY: ++ if (in == 7 && out == 0) ++ break; ++ return (EINVAL); ++ case CRK_DH_COMPUTE_KEY: ++ if (in == 3 && out == 1) ++ break; ++ return (EINVAL); ++ default: ++ return (EINVAL); ++ } ++ ++ krp = (struct cryptkop *)kmalloc(sizeof *krp, GFP_KERNEL); ++ if (!krp) ++ return (ENOMEM); ++ bzero(krp, sizeof *krp); ++ krp->krp_op = kop->crk_op; ++ krp->krp_status = kop->crk_status; ++ krp->krp_iparams = kop->crk_iparams; ++ krp->krp_oparams = kop->crk_oparams; ++ krp->krp_crid = kop->crk_crid; ++ krp->krp_status = 0; ++ krp->krp_flags = CRYPTO_KF_CBIMM; ++ krp->krp_callback = (int (*) (struct cryptkop *)) cryptodevkey_cb; ++ init_waitqueue_head(&krp->krp_waitq); ++ ++ for (i = 0; i < CRK_MAXPARAM; i++) ++ krp->krp_param[i].crp_nbits = kop->crk_param[i].crp_nbits; ++ for (i = 0; i < krp->krp_iparams + krp->krp_oparams; i++) { ++ size = (krp->krp_param[i].crp_nbits + 7) / 8; ++ if (size == 0) ++ continue; ++ krp->krp_param[i].crp_p = (caddr_t) kmalloc(size, GFP_KERNEL); ++ if (i >= krp->krp_iparams) ++ continue; ++ error = copy_from_user(krp->krp_param[i].crp_p, ++ kop->crk_param[i].crp_p, size); ++ if (error) ++ goto fail; ++ } ++ ++ error = crypto_kdispatch(krp); ++ if (error) ++ goto fail; ++ ++ do { ++ error = wait_event_interruptible(krp->krp_waitq, ++ ((krp->krp_flags & CRYPTO_KF_DONE) != 0)); ++ /* ++ * we can't break out of this loop or we will leave behind ++ * a huge mess, however, staying here means if your driver ++ * is broken user applications can hang and not be killed. ++ * The solution, fix your driver :-) ++ */ ++ if (error) { ++ schedule(); ++ error = 0; ++ } ++ } while ((krp->krp_flags & CRYPTO_KF_DONE) == 0); ++ ++ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); ++ ++ kop->crk_crid = krp->krp_crid; /* device that did the work */ ++ if (krp->krp_status != 0) { ++ error = krp->krp_status; ++ goto fail; ++ } ++ ++ for (i = krp->krp_iparams; i < krp->krp_iparams + krp->krp_oparams; i++) { ++ size = (krp->krp_param[i].crp_nbits + 7) / 8; ++ if (size == 0) ++ continue; ++ error = copy_to_user(kop->crk_param[i].crp_p, krp->krp_param[i].crp_p, ++ size); ++ if (error) ++ goto fail; ++ } ++ ++fail: ++ if (krp) { ++ kop->crk_status = krp->krp_status; ++ for (i = 0; i < CRK_MAXPARAM; i++) { ++ if (krp->krp_param[i].crp_p) ++ kfree(krp->krp_param[i].crp_p); ++ } ++ kfree(krp); ++ } ++ return (error); ++} ++ ++static int ++cryptodev_find(struct crypt_find_op *find) ++{ ++ device_t dev; ++ ++ if (find->crid != -1) { ++ dev = crypto_find_device_byhid(find->crid); ++ if (dev == NULL) ++ return (ENOENT); ++ strlcpy(find->name, device_get_nameunit(dev), ++ sizeof(find->name)); ++ } else { ++ find->crid = crypto_find_driver(find->name); ++ if (find->crid == -1) ++ return (ENOENT); ++ } ++ return (0); ++} ++ ++static struct csession * ++csefind(struct fcrypt *fcr, u_int ses) ++{ ++ struct csession *cse; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ list_for_each_entry(cse, &fcr->csessions, list) ++ if (cse->ses == ses) ++ return (cse); ++ return (NULL); ++} ++ ++static int ++csedelete(struct fcrypt *fcr, struct csession *cse_del) ++{ ++ struct csession *cse; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ list_for_each_entry(cse, &fcr->csessions, list) { ++ if (cse == cse_del) { ++ list_del(&cse->list); ++ return (1); ++ } ++ } ++ return (0); ++} ++ ++static struct csession * ++cseadd(struct fcrypt *fcr, struct csession *cse) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ list_add_tail(&cse->list, &fcr->csessions); ++ cse->ses = fcr->sesn++; ++ return (cse); ++} ++ ++static struct csession * ++csecreate(struct fcrypt *fcr, u_int64_t sid, struct cryptoini *crie, ++ struct cryptoini *cria, struct csession_info *info) ++{ ++ struct csession *cse; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ cse = (struct csession *) kmalloc(sizeof(struct csession), GFP_KERNEL); ++ if (cse == NULL) ++ return NULL; ++ memset(cse, 0, sizeof(struct csession)); ++ ++ INIT_LIST_HEAD(&cse->list); ++ init_waitqueue_head(&cse->waitq); ++ ++ cse->key = crie->cri_key; ++ cse->keylen = crie->cri_klen/8; ++ cse->mackey = cria->cri_key; ++ cse->mackeylen = cria->cri_klen/8; ++ cse->sid = sid; ++ cse->cipher = crie->cri_alg; ++ cse->mac = cria->cri_alg; ++ cse->info = *info; ++ cseadd(fcr, cse); ++ return (cse); ++} ++ ++static int ++csefree(struct csession *cse) ++{ ++ int error; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ error = crypto_freesession(cse->sid); ++ if (cse->key) ++ kfree(cse->key); ++ if (cse->mackey) ++ kfree(cse->mackey); ++ kfree(cse); ++ return(error); ++} ++ ++static int ++cryptodev_ioctl( ++ struct inode *inode, ++ struct file *filp, ++ unsigned int cmd, ++ unsigned long arg) ++{ ++ struct cryptoini cria, crie; ++ struct fcrypt *fcr = filp->private_data; ++ struct csession *cse; ++ struct csession_info info; ++ struct session2_op sop; ++ struct crypt_op cop; ++ struct crypt_kop kop; ++ struct crypt_find_op fop; ++ u_int64_t sid; ++ u_int32_t ses = 0; ++ int feat, fd, error = 0, crid; ++ mm_segment_t fs; ++ ++ dprintk("%s(cmd=%x arg=%lx)\n", __FUNCTION__, cmd, arg); ++ ++ switch (cmd) { ++ ++ case CRIOGET: { ++ dprintk("%s(CRIOGET)\n", __FUNCTION__); ++ fs = get_fs(); ++ set_fs(get_ds()); ++ for (fd = 0; fd < files_fdtable(current->files)->max_fds; fd++) ++ if (files_fdtable(current->files)->fd[fd] == filp) ++ break; ++ fd = sys_dup(fd); ++ set_fs(fs); ++ put_user(fd, (int *) arg); ++ return IS_ERR_VALUE(fd) ? fd : 0; ++ } ++ ++#define CIOCGSESSSTR (cmd == CIOCGSESSION ? "CIOCGSESSION" : "CIOCGSESSION2") ++ case CIOCGSESSION: ++ case CIOCGSESSION2: ++ dprintk("%s(%s)\n", __FUNCTION__, CIOCGSESSSTR); ++ memset(&crie, 0, sizeof(crie)); ++ memset(&cria, 0, sizeof(cria)); ++ memset(&info, 0, sizeof(info)); ++ memset(&sop, 0, sizeof(sop)); ++ ++ if (copy_from_user(&sop, (void*)arg, (cmd == CIOCGSESSION) ? ++ sizeof(struct session_op) : sizeof(sop))) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ goto bail; ++ } ++ ++ switch (sop.cipher) { ++ case 0: ++ dprintk("%s(%s) - no cipher\n", __FUNCTION__, CIOCGSESSSTR); ++ break; ++ case CRYPTO_NULL_CBC: ++ info.blocksize = NULL_BLOCK_LEN; ++ info.minkey = NULL_MIN_KEY_LEN; ++ info.maxkey = NULL_MAX_KEY_LEN; ++ break; ++ case CRYPTO_DES_CBC: ++ info.blocksize = DES_BLOCK_LEN; ++ info.minkey = DES_MIN_KEY_LEN; ++ info.maxkey = DES_MAX_KEY_LEN; ++ break; ++ case CRYPTO_3DES_CBC: ++ info.blocksize = DES3_BLOCK_LEN; ++ info.minkey = DES3_MIN_KEY_LEN; ++ info.maxkey = DES3_MAX_KEY_LEN; ++ break; ++ case CRYPTO_BLF_CBC: ++ info.blocksize = BLOWFISH_BLOCK_LEN; ++ info.minkey = BLOWFISH_MIN_KEY_LEN; ++ info.maxkey = BLOWFISH_MAX_KEY_LEN; ++ break; ++ case CRYPTO_CAST_CBC: ++ info.blocksize = CAST128_BLOCK_LEN; ++ info.minkey = CAST128_MIN_KEY_LEN; ++ info.maxkey = CAST128_MAX_KEY_LEN; ++ break; ++ case CRYPTO_SKIPJACK_CBC: ++ info.blocksize = SKIPJACK_BLOCK_LEN; ++ info.minkey = SKIPJACK_MIN_KEY_LEN; ++ info.maxkey = SKIPJACK_MAX_KEY_LEN; ++ break; ++ case CRYPTO_AES_CBC: ++ info.blocksize = AES_BLOCK_LEN; ++ info.minkey = AES_MIN_KEY_LEN; ++ info.maxkey = AES_MAX_KEY_LEN; ++ break; ++ case CRYPTO_ARC4: ++ info.blocksize = ARC4_BLOCK_LEN; ++ info.minkey = ARC4_MIN_KEY_LEN; ++ info.maxkey = ARC4_MAX_KEY_LEN; ++ break; ++ case CRYPTO_CAMELLIA_CBC: ++ info.blocksize = CAMELLIA_BLOCK_LEN; ++ info.minkey = CAMELLIA_MIN_KEY_LEN; ++ info.maxkey = CAMELLIA_MAX_KEY_LEN; ++ break; ++ default: ++ dprintk("%s(%s) - bad cipher\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ switch (sop.mac) { ++ case 0: ++ dprintk("%s(%s) - no mac\n", __FUNCTION__, CIOCGSESSSTR); ++ break; ++ case CRYPTO_NULL_HMAC: ++ info.authsize = NULL_HASH_LEN; ++ break; ++ case CRYPTO_MD5: ++ info.authsize = MD5_HASH_LEN; ++ break; ++ case CRYPTO_SHA1: ++ info.authsize = SHA1_HASH_LEN; ++ break; ++ case CRYPTO_SHA2_256: ++ info.authsize = SHA2_256_HASH_LEN; ++ break; ++ case CRYPTO_SHA2_384: ++ info.authsize = SHA2_384_HASH_LEN; ++ break; ++ case CRYPTO_SHA2_512: ++ info.authsize = SHA2_512_HASH_LEN; ++ break; ++ case CRYPTO_RIPEMD160: ++ info.authsize = RIPEMD160_HASH_LEN; ++ break; ++ case CRYPTO_MD5_HMAC: ++ info.authsize = MD5_HASH_LEN; ++ info.authkey = 16; ++ break; ++ case CRYPTO_SHA1_HMAC: ++ info.authsize = SHA1_HASH_LEN; ++ info.authkey = 20; ++ break; ++ case CRYPTO_SHA2_256_HMAC: ++ info.authsize = SHA2_256_HASH_LEN; ++ info.authkey = 32; ++ break; ++ case CRYPTO_SHA2_384_HMAC: ++ info.authsize = SHA2_384_HASH_LEN; ++ info.authkey = 48; ++ break; ++ case CRYPTO_SHA2_512_HMAC: ++ info.authsize = SHA2_512_HASH_LEN; ++ info.authkey = 64; ++ break; ++ case CRYPTO_RIPEMD160_HMAC: ++ info.authsize = RIPEMD160_HASH_LEN; ++ info.authkey = 20; ++ break; ++ default: ++ dprintk("%s(%s) - bad mac\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ if (info.blocksize) { ++ crie.cri_alg = sop.cipher; ++ crie.cri_klen = sop.keylen * 8; ++ if ((info.maxkey && sop.keylen > info.maxkey) || ++ sop.keylen < info.minkey) { ++ dprintk("%s(%s) - bad key\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ crie.cri_key = (u_int8_t *) kmalloc(crie.cri_klen/8+1, GFP_KERNEL); ++ if (copy_from_user(crie.cri_key, sop.key, ++ crie.cri_klen/8)) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ goto bail; ++ } ++ if (info.authsize) ++ crie.cri_next = &cria; ++ } ++ ++ if (info.authsize) { ++ cria.cri_alg = sop.mac; ++ cria.cri_klen = sop.mackeylen * 8; ++ if (info.authkey && sop.mackeylen != info.authkey) { ++ dprintk("%s(%s) - mackeylen %d != %d\n", __FUNCTION__, ++ CIOCGSESSSTR, sop.mackeylen, info.authkey); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ if (cria.cri_klen) { ++ cria.cri_key = (u_int8_t *) kmalloc(cria.cri_klen/8,GFP_KERNEL); ++ if (copy_from_user(cria.cri_key, sop.mackey, ++ cria.cri_klen / 8)) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ goto bail; ++ } ++ } ++ } ++ ++ /* NB: CIOGSESSION2 has the crid */ ++ if (cmd == CIOCGSESSION2) { ++ crid = sop.crid; ++ error = checkcrid(crid); ++ if (error) { ++ dprintk("%s(%s) - checkcrid %x\n", __FUNCTION__, ++ CIOCGSESSSTR, error); ++ goto bail; ++ } ++ } else { ++ /* allow either HW or SW to be used */ ++ crid = CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; ++ } ++ error = crypto_newsession(&sid, (info.blocksize ? &crie : &cria), crid); ++ if (error) { ++ dprintk("%s(%s) - newsession %d\n",__FUNCTION__,CIOCGSESSSTR,error); ++ goto bail; ++ } ++ ++ cse = csecreate(fcr, sid, &crie, &cria, &info); ++ if (cse == NULL) { ++ crypto_freesession(sid); ++ error = EINVAL; ++ dprintk("%s(%s) - csecreate failed\n", __FUNCTION__, CIOCGSESSSTR); ++ goto bail; ++ } ++ sop.ses = cse->ses; ++ ++ if (cmd == CIOCGSESSION2) { ++ /* return hardware/driver id */ ++ sop.crid = CRYPTO_SESID2HID(cse->sid); ++ } ++ ++ if (copy_to_user((void*)arg, &sop, (cmd == CIOCGSESSION) ? ++ sizeof(struct session_op) : sizeof(sop))) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ } ++bail: ++ if (error) { ++ dprintk("%s(%s) - bail %d\n", __FUNCTION__, CIOCGSESSSTR, error); ++ if (crie.cri_key) ++ kfree(crie.cri_key); ++ if (cria.cri_key) ++ kfree(cria.cri_key); ++ } ++ break; ++ case CIOCFSESSION: ++ dprintk("%s(CIOCFSESSION)\n", __FUNCTION__); ++ get_user(ses, (uint32_t*)arg); ++ cse = csefind(fcr, ses); ++ if (cse == NULL) { ++ error = EINVAL; ++ dprintk("%s(CIOCFSESSION) - Fail %d\n", __FUNCTION__, error); ++ break; ++ } ++ csedelete(fcr, cse); ++ error = csefree(cse); ++ break; ++ case CIOCCRYPT: ++ dprintk("%s(CIOCCRYPT)\n", __FUNCTION__); ++ if(copy_from_user(&cop, (void*)arg, sizeof(cop))) { ++ dprintk("%s(CIOCCRYPT) - bad copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ cse = csefind(fcr, cop.ses); ++ if (cse == NULL) { ++ error = EINVAL; ++ dprintk("%s(CIOCCRYPT) - Fail %d\n", __FUNCTION__, error); ++ break; ++ } ++ error = cryptodev_op(cse, &cop); ++ if(copy_to_user((void*)arg, &cop, sizeof(cop))) { ++ dprintk("%s(CIOCCRYPT) - bad return copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ break; ++ case CIOCKEY: ++ case CIOCKEY2: ++ dprintk("%s(CIOCKEY)\n", __FUNCTION__); ++ if (!crypto_userasymcrypto) ++ return (EPERM); /* XXX compat? */ ++ if(copy_from_user(&kop, (void*)arg, sizeof(kop))) { ++ dprintk("%s(CIOCKEY) - bad copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ if (cmd == CIOCKEY) { ++ /* NB: crypto core enforces s/w driver use */ ++ kop.crk_crid = ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; ++ } ++ error = cryptodev_key(&kop); ++ if(copy_to_user((void*)arg, &kop, sizeof(kop))) { ++ dprintk("%s(CIOCGKEY) - bad return copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ break; ++ case CIOCASYMFEAT: ++ dprintk("%s(CIOCASYMFEAT)\n", __FUNCTION__); ++ if (!crypto_userasymcrypto) { ++ /* ++ * NB: if user asym crypto operations are ++ * not permitted return "no algorithms" ++ * so well-behaved applications will just ++ * fallback to doing them in software. ++ */ ++ feat = 0; ++ } else ++ error = crypto_getfeat(&feat); ++ if (!error) { ++ error = copy_to_user((void*)arg, &feat, sizeof(feat)); ++ } ++ break; ++ case CIOCFINDDEV: ++ if (copy_from_user(&fop, (void*)arg, sizeof(fop))) { ++ dprintk("%s(CIOCFINDDEV) - bad copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ error = cryptodev_find(&fop); ++ if (copy_to_user((void*)arg, &fop, sizeof(fop))) { ++ dprintk("%s(CIOCFINDDEV) - bad return copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ break; ++ default: ++ dprintk("%s(unknown ioctl 0x%x)\n", __FUNCTION__, cmd); ++ error = EINVAL; ++ break; ++ } ++ return(-error); ++} ++ ++#ifdef HAVE_UNLOCKED_IOCTL ++static long ++cryptodev_unlocked_ioctl( ++ struct file *filp, ++ unsigned int cmd, ++ unsigned long arg) ++{ ++ return cryptodev_ioctl(NULL, filp, cmd, arg); ++} ++#endif ++ ++static int ++cryptodev_open(struct inode *inode, struct file *filp) ++{ ++ struct fcrypt *fcr; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (filp->private_data) { ++ printk("cryptodev: Private data already exists !\n"); ++ return(0); ++ } ++ ++ fcr = kmalloc(sizeof(*fcr), GFP_KERNEL); ++ if (!fcr) { ++ dprintk("%s() - malloc failed\n", __FUNCTION__); ++ return(-ENOMEM); ++ } ++ memset(fcr, 0, sizeof(*fcr)); ++ ++ INIT_LIST_HEAD(&fcr->csessions); ++ filp->private_data = fcr; ++ return(0); ++} ++ ++static int ++cryptodev_release(struct inode *inode, struct file *filp) ++{ ++ struct fcrypt *fcr = filp->private_data; ++ struct csession *cse, *tmp; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (!filp) { ++ printk("cryptodev: No private data on release\n"); ++ return(0); ++ } ++ ++ list_for_each_entry_safe(cse, tmp, &fcr->csessions, list) { ++ list_del(&cse->list); ++ (void)csefree(cse); ++ } ++ filp->private_data = NULL; ++ kfree(fcr); ++ return(0); ++} ++ ++static struct file_operations cryptodev_fops = { ++ .owner = THIS_MODULE, ++ .open = cryptodev_open, ++ .release = cryptodev_release, ++#ifdef HAVE_UNLOCKED_IOCTL ++ .unlocked_ioctl = cryptodev_unlocked_ioctl, ++#endif ++}; ++ ++static struct miscdevice cryptodev = { ++ .minor = CRYPTODEV_MINOR, ++ .name = "crypto", ++ .fops = &cryptodev_fops, ++}; ++ ++static int __init ++cryptodev_init(void) ++{ ++ int rc; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, cryptodev_init); ++ rc = misc_register(&cryptodev); ++ if (rc) { ++ printk(KERN_ERR "cryptodev: registration of /dev/crypto failed\n"); ++ return(rc); ++ } ++ ++ return(0); ++} ++ ++static void __exit ++cryptodev_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ misc_deregister(&cryptodev); ++} ++ ++module_init(cryptodev_init); ++module_exit(cryptodev_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Cryptodev (user interface to OCF)"); +diff -Nur linux-2.6.39.orig/crypto/ocf/cryptodev.h linux-2.6.39/crypto/ocf/cryptodev.h +--- linux-2.6.39.orig/crypto/ocf/cryptodev.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/cryptodev.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,479 @@ ++/* $FreeBSD: src/sys/opencrypto/cryptodev.h,v 1.25 2007/05/09 19:37:02 gnn Exp $ */ ++/* $OpenBSD: cryptodev.h,v 1.31 2002/06/11 11:14:29 beck Exp $ */ ++ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) ++ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting ++ * ++ * This code was written by Angelos D. Keromytis in Athens, Greece, in ++ * February 2000. Network Security Technologies Inc. (NSTI) kindly ++ * supported the development of this code. ++ * ++ * Copyright (c) 2000 Angelos D. Keromytis ++ * ++ * Permission to use, copy, and modify this software with or without fee ++ * is hereby granted, provided that this entire notice is included in ++ * all source code copies of any software which is or includes a copy or ++ * modification of this software. ++ * ++ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY ++ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE ++ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR ++ * PURPOSE. ++ * ++ * Copyright (c) 2001 Theo de Raadt ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++#ifndef _CRYPTO_CRYPTO_H_ ++#define _CRYPTO_CRYPTO_H_ ++ ++/* Some initial values */ ++#define CRYPTO_DRIVERS_INITIAL 4 ++#define CRYPTO_SW_SESSIONS 32 ++ ++/* Hash values */ ++#define NULL_HASH_LEN 0 ++#define MD5_HASH_LEN 16 ++#define SHA1_HASH_LEN 20 ++#define RIPEMD160_HASH_LEN 20 ++#define SHA2_256_HASH_LEN 32 ++#define SHA2_384_HASH_LEN 48 ++#define SHA2_512_HASH_LEN 64 ++#define MD5_KPDK_HASH_LEN 16 ++#define SHA1_KPDK_HASH_LEN 20 ++/* Maximum hash algorithm result length */ ++#define HASH_MAX_LEN SHA2_512_HASH_LEN /* Keep this updated */ ++ ++/* HMAC values */ ++#define NULL_HMAC_BLOCK_LEN 1 ++#define MD5_HMAC_BLOCK_LEN 64 ++#define SHA1_HMAC_BLOCK_LEN 64 ++#define RIPEMD160_HMAC_BLOCK_LEN 64 ++#define SHA2_256_HMAC_BLOCK_LEN 64 ++#define SHA2_384_HMAC_BLOCK_LEN 128 ++#define SHA2_512_HMAC_BLOCK_LEN 128 ++/* Maximum HMAC block length */ ++#define HMAC_MAX_BLOCK_LEN SHA2_512_HMAC_BLOCK_LEN /* Keep this updated */ ++#define HMAC_IPAD_VAL 0x36 ++#define HMAC_OPAD_VAL 0x5C ++ ++/* Encryption algorithm block sizes */ ++#define NULL_BLOCK_LEN 1 ++#define DES_BLOCK_LEN 8 ++#define DES3_BLOCK_LEN 8 ++#define BLOWFISH_BLOCK_LEN 8 ++#define SKIPJACK_BLOCK_LEN 8 ++#define CAST128_BLOCK_LEN 8 ++#define RIJNDAEL128_BLOCK_LEN 16 ++#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN ++#define CAMELLIA_BLOCK_LEN 16 ++#define ARC4_BLOCK_LEN 1 ++#define EALG_MAX_BLOCK_LEN AES_BLOCK_LEN /* Keep this updated */ ++ ++/* Encryption algorithm min and max key sizes */ ++#define NULL_MIN_KEY_LEN 0 ++#define NULL_MAX_KEY_LEN 0 ++#define DES_MIN_KEY_LEN 8 ++#define DES_MAX_KEY_LEN 8 ++#define DES3_MIN_KEY_LEN 24 ++#define DES3_MAX_KEY_LEN 24 ++#define BLOWFISH_MIN_KEY_LEN 4 ++#define BLOWFISH_MAX_KEY_LEN 56 ++#define SKIPJACK_MIN_KEY_LEN 10 ++#define SKIPJACK_MAX_KEY_LEN 10 ++#define CAST128_MIN_KEY_LEN 5 ++#define CAST128_MAX_KEY_LEN 16 ++#define RIJNDAEL128_MIN_KEY_LEN 16 ++#define RIJNDAEL128_MAX_KEY_LEN 32 ++#define AES_MIN_KEY_LEN RIJNDAEL128_MIN_KEY_LEN ++#define AES_MAX_KEY_LEN RIJNDAEL128_MAX_KEY_LEN ++#define CAMELLIA_MIN_KEY_LEN 16 ++#define CAMELLIA_MAX_KEY_LEN 32 ++#define ARC4_MIN_KEY_LEN 1 ++#define ARC4_MAX_KEY_LEN 256 ++ ++/* Max size of data that can be processed */ ++#define CRYPTO_MAX_DATA_LEN 64*1024 - 1 ++ ++#define CRYPTO_ALGORITHM_MIN 1 ++#define CRYPTO_DES_CBC 1 ++#define CRYPTO_3DES_CBC 2 ++#define CRYPTO_BLF_CBC 3 ++#define CRYPTO_CAST_CBC 4 ++#define CRYPTO_SKIPJACK_CBC 5 ++#define CRYPTO_MD5_HMAC 6 ++#define CRYPTO_SHA1_HMAC 7 ++#define CRYPTO_RIPEMD160_HMAC 8 ++#define CRYPTO_MD5_KPDK 9 ++#define CRYPTO_SHA1_KPDK 10 ++#define CRYPTO_RIJNDAEL128_CBC 11 /* 128 bit blocksize */ ++#define CRYPTO_AES_CBC 11 /* 128 bit blocksize -- the same as above */ ++#define CRYPTO_ARC4 12 ++#define CRYPTO_MD5 13 ++#define CRYPTO_SHA1 14 ++#define CRYPTO_NULL_HMAC 15 ++#define CRYPTO_NULL_CBC 16 ++#define CRYPTO_DEFLATE_COMP 17 /* Deflate compression algorithm */ ++#define CRYPTO_SHA2_256_HMAC 18 ++#define CRYPTO_SHA2_384_HMAC 19 ++#define CRYPTO_SHA2_512_HMAC 20 ++#define CRYPTO_CAMELLIA_CBC 21 ++#define CRYPTO_SHA2_256 22 ++#define CRYPTO_SHA2_384 23 ++#define CRYPTO_SHA2_512 24 ++#define CRYPTO_RIPEMD160 25 ++#define CRYPTO_ALGORITHM_MAX 25 /* Keep updated - see below */ ++ ++/* Algorithm flags */ ++#define CRYPTO_ALG_FLAG_SUPPORTED 0x01 /* Algorithm is supported */ ++#define CRYPTO_ALG_FLAG_RNG_ENABLE 0x02 /* Has HW RNG for DH/DSA */ ++#define CRYPTO_ALG_FLAG_DSA_SHA 0x04 /* Can do SHA on msg */ ++ ++/* ++ * Crypto driver/device flags. They can set in the crid ++ * parameter when creating a session or submitting a key ++ * op to affect the device/driver assigned. If neither ++ * of these are specified then the crid is assumed to hold ++ * the driver id of an existing (and suitable) device that ++ * must be used to satisfy the request. ++ */ ++#define CRYPTO_FLAG_HARDWARE 0x01000000 /* hardware accelerated */ ++#define CRYPTO_FLAG_SOFTWARE 0x02000000 /* software implementation */ ++ ++/* NB: deprecated */ ++struct session_op { ++ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ ++ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ ++ ++ u_int32_t keylen; /* cipher key */ ++ caddr_t key; ++ int mackeylen; /* mac key */ ++ caddr_t mackey; ++ ++ u_int32_t ses; /* returns: session # */ ++}; ++ ++struct session2_op { ++ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ ++ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ ++ ++ u_int32_t keylen; /* cipher key */ ++ caddr_t key; ++ int mackeylen; /* mac key */ ++ caddr_t mackey; ++ ++ u_int32_t ses; /* returns: session # */ ++ int crid; /* driver id + flags (rw) */ ++ int pad[4]; /* for future expansion */ ++}; ++ ++struct crypt_op { ++ u_int32_t ses; ++ u_int16_t op; /* i.e. COP_ENCRYPT */ ++#define COP_NONE 0 ++#define COP_ENCRYPT 1 ++#define COP_DECRYPT 2 ++ u_int16_t flags; ++#define COP_F_BATCH 0x0008 /* Batch op if possible */ ++ u_int len; ++ caddr_t src, dst; /* become iov[] inside kernel */ ++ caddr_t mac; /* must be big enough for chosen MAC */ ++ caddr_t iv; ++}; ++ ++/* ++ * Parameters for looking up a crypto driver/device by ++ * device name or by id. The latter are returned for ++ * created sessions (crid) and completed key operations. ++ */ ++struct crypt_find_op { ++ int crid; /* driver id + flags */ ++ char name[32]; /* device/driver name */ ++}; ++ ++/* bignum parameter, in packed bytes, ... */ ++struct crparam { ++ caddr_t crp_p; ++ u_int crp_nbits; ++}; ++ ++#define CRK_MAXPARAM 8 ++ ++struct crypt_kop { ++ u_int crk_op; /* ie. CRK_MOD_EXP or other */ ++ u_int crk_status; /* return status */ ++ u_short crk_iparams; /* # of input parameters */ ++ u_short crk_oparams; /* # of output parameters */ ++ u_int crk_crid; /* NB: only used by CIOCKEY2 (rw) */ ++ struct crparam crk_param[CRK_MAXPARAM]; ++}; ++#define CRK_ALGORITM_MIN 0 ++#define CRK_MOD_EXP 0 ++#define CRK_MOD_EXP_CRT 1 ++#define CRK_DSA_SIGN 2 ++#define CRK_DSA_VERIFY 3 ++#define CRK_DH_COMPUTE_KEY 4 ++#define CRK_ALGORITHM_MAX 4 /* Keep updated - see below */ ++ ++#define CRF_MOD_EXP (1 << CRK_MOD_EXP) ++#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT) ++#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN) ++#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY) ++#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY) ++ ++/* ++ * done against open of /dev/crypto, to get a cloned descriptor. ++ * Please use F_SETFD against the cloned descriptor. ++ */ ++#define CRIOGET _IOWR('c', 100, u_int32_t) ++#define CRIOASYMFEAT CIOCASYMFEAT ++#define CRIOFINDDEV CIOCFINDDEV ++ ++/* the following are done against the cloned descriptor */ ++#define CIOCGSESSION _IOWR('c', 101, struct session_op) ++#define CIOCFSESSION _IOW('c', 102, u_int32_t) ++#define CIOCCRYPT _IOWR('c', 103, struct crypt_op) ++#define CIOCKEY _IOWR('c', 104, struct crypt_kop) ++#define CIOCASYMFEAT _IOR('c', 105, u_int32_t) ++#define CIOCGSESSION2 _IOWR('c', 106, struct session2_op) ++#define CIOCKEY2 _IOWR('c', 107, struct crypt_kop) ++#define CIOCFINDDEV _IOWR('c', 108, struct crypt_find_op) ++ ++struct cryptotstat { ++ struct timespec acc; /* total accumulated time */ ++ struct timespec min; /* min time */ ++ struct timespec max; /* max time */ ++ u_int32_t count; /* number of observations */ ++}; ++ ++struct cryptostats { ++ u_int32_t cs_ops; /* symmetric crypto ops submitted */ ++ u_int32_t cs_errs; /* symmetric crypto ops that failed */ ++ u_int32_t cs_kops; /* asymetric/key ops submitted */ ++ u_int32_t cs_kerrs; /* asymetric/key ops that failed */ ++ u_int32_t cs_intrs; /* crypto swi thread activations */ ++ u_int32_t cs_rets; /* crypto return thread activations */ ++ u_int32_t cs_blocks; /* symmetric op driver block */ ++ u_int32_t cs_kblocks; /* symmetric op driver block */ ++ /* ++ * When CRYPTO_TIMING is defined at compile time and the ++ * sysctl debug.crypto is set to 1, the crypto system will ++ * accumulate statistics about how long it takes to process ++ * crypto requests at various points during processing. ++ */ ++ struct cryptotstat cs_invoke; /* crypto_dipsatch -> crypto_invoke */ ++ struct cryptotstat cs_done; /* crypto_invoke -> crypto_done */ ++ struct cryptotstat cs_cb; /* crypto_done -> callback */ ++ struct cryptotstat cs_finis; /* callback -> callback return */ ++ ++ u_int32_t cs_drops; /* crypto ops dropped due to congestion */ ++}; ++ ++#ifdef __KERNEL__ ++ ++/* Standard initialization structure beginning */ ++struct cryptoini { ++ int cri_alg; /* Algorithm to use */ ++ int cri_klen; /* Key length, in bits */ ++ int cri_mlen; /* Number of bytes we want from the ++ entire hash. 0 means all. */ ++ caddr_t cri_key; /* key to use */ ++ u_int8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */ ++ struct cryptoini *cri_next; ++}; ++ ++/* Describe boundaries of a single crypto operation */ ++struct cryptodesc { ++ int crd_skip; /* How many bytes to ignore from start */ ++ int crd_len; /* How many bytes to process */ ++ int crd_inject; /* Where to inject results, if applicable */ ++ int crd_flags; ++ ++#define CRD_F_ENCRYPT 0x01 /* Set when doing encryption */ ++#define CRD_F_IV_PRESENT 0x02 /* When encrypting, IV is already in ++ place, so don't copy. */ ++#define CRD_F_IV_EXPLICIT 0x04 /* IV explicitly provided */ ++#define CRD_F_DSA_SHA_NEEDED 0x08 /* Compute SHA-1 of buffer for DSA */ ++#define CRD_F_KEY_EXPLICIT 0x10 /* Key explicitly provided */ ++#define CRD_F_COMP 0x0f /* Set when doing compression */ ++ ++ struct cryptoini CRD_INI; /* Initialization/context data */ ++#define crd_iv CRD_INI.cri_iv ++#define crd_key CRD_INI.cri_key ++#define crd_alg CRD_INI.cri_alg ++#define crd_klen CRD_INI.cri_klen ++#define crd_mlen CRD_INI.cri_mlen ++ ++ struct cryptodesc *crd_next; ++}; ++ ++/* Structure describing complete operation */ ++struct cryptop { ++ struct list_head crp_next; ++ wait_queue_head_t crp_waitq; ++ ++ u_int64_t crp_sid; /* Session ID */ ++ int crp_ilen; /* Input data total length */ ++ int crp_olen; /* Result total length */ ++ ++ int crp_etype; /* ++ * Error type (zero means no error). ++ * All error codes except EAGAIN ++ * indicate possible data corruption (as in, ++ * the data have been touched). On all ++ * errors, the crp_sid may have changed ++ * (reset to a new one), so the caller ++ * should always check and use the new ++ * value on future requests. ++ */ ++ int crp_flags; ++ ++#define CRYPTO_F_SKBUF 0x0001 /* Input/output are skbuf chains */ ++#define CRYPTO_F_IOV 0x0002 /* Input/output are uio */ ++#define CRYPTO_F_REL 0x0004 /* Must return data in same place */ ++#define CRYPTO_F_BATCH 0x0008 /* Batch op if possible */ ++#define CRYPTO_F_CBIMM 0x0010 /* Do callback immediately */ ++#define CRYPTO_F_DONE 0x0020 /* Operation completed */ ++#define CRYPTO_F_CBIFSYNC 0x0040 /* Do CBIMM if op is synchronous */ ++ ++ caddr_t crp_buf; /* Data to be processed */ ++ caddr_t crp_opaque; /* Opaque pointer, passed along */ ++ struct cryptodesc *crp_desc; /* Linked list of processing descriptors */ ++ ++ int (*crp_callback)(struct cryptop *); /* Callback function */ ++}; ++ ++#define CRYPTO_BUF_CONTIG 0x0 ++#define CRYPTO_BUF_IOV 0x1 ++#define CRYPTO_BUF_SKBUF 0x2 ++ ++#define CRYPTO_OP_DECRYPT 0x0 ++#define CRYPTO_OP_ENCRYPT 0x1 ++ ++/* ++ * Hints passed to process methods. ++ */ ++#define CRYPTO_HINT_MORE 0x1 /* more ops coming shortly */ ++ ++struct cryptkop { ++ struct list_head krp_next; ++ wait_queue_head_t krp_waitq; ++ ++ int krp_flags; ++#define CRYPTO_KF_DONE 0x0001 /* Operation completed */ ++#define CRYPTO_KF_CBIMM 0x0002 /* Do callback immediately */ ++ ++ u_int krp_op; /* ie. CRK_MOD_EXP or other */ ++ u_int krp_status; /* return status */ ++ u_short krp_iparams; /* # of input parameters */ ++ u_short krp_oparams; /* # of output parameters */ ++ u_int krp_crid; /* desired device, etc. */ ++ u_int32_t krp_hid; ++ struct crparam krp_param[CRK_MAXPARAM]; /* kvm */ ++ int (*krp_callback)(struct cryptkop *); ++}; ++ ++#include ++ ++/* ++ * Session ids are 64 bits. The lower 32 bits contain a "local id" which ++ * is a driver-private session identifier. The upper 32 bits contain a ++ * "hardware id" used by the core crypto code to identify the driver and ++ * a copy of the driver's capabilities that can be used by client code to ++ * optimize operation. ++ */ ++#define CRYPTO_SESID2HID(_sid) (((_sid) >> 32) & 0x00ffffff) ++#define CRYPTO_SESID2CAPS(_sid) (((_sid) >> 32) & 0xff000000) ++#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff) ++ ++extern int crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int hard); ++extern int crypto_freesession(u_int64_t sid); ++#define CRYPTOCAP_F_HARDWARE CRYPTO_FLAG_HARDWARE ++#define CRYPTOCAP_F_SOFTWARE CRYPTO_FLAG_SOFTWARE ++#define CRYPTOCAP_F_SYNC 0x04000000 /* operates synchronously */ ++extern int32_t crypto_get_driverid(device_t dev, int flags); ++extern int crypto_find_driver(const char *); ++extern device_t crypto_find_device_byhid(int hid); ++extern int crypto_getcaps(int hid); ++extern int crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, ++ u_int32_t flags); ++extern int crypto_kregister(u_int32_t, int, u_int32_t); ++extern int crypto_unregister(u_int32_t driverid, int alg); ++extern int crypto_unregister_all(u_int32_t driverid); ++extern int crypto_dispatch(struct cryptop *crp); ++extern int crypto_kdispatch(struct cryptkop *); ++#define CRYPTO_SYMQ 0x1 ++#define CRYPTO_ASYMQ 0x2 ++extern int crypto_unblock(u_int32_t, int); ++extern void crypto_done(struct cryptop *crp); ++extern void crypto_kdone(struct cryptkop *); ++extern int crypto_getfeat(int *); ++ ++extern void crypto_freereq(struct cryptop *crp); ++extern struct cryptop *crypto_getreq(int num); ++ ++extern int crypto_usercrypto; /* userland may do crypto requests */ ++extern int crypto_userasymcrypto; /* userland may do asym crypto reqs */ ++extern int crypto_devallowsoft; /* only use hardware crypto */ ++ ++/* ++ * random number support, crypto_unregister_all will unregister ++ */ ++extern int crypto_rregister(u_int32_t driverid, ++ int (*read_random)(void *arg, u_int32_t *buf, int len), void *arg); ++extern int crypto_runregister_all(u_int32_t driverid); ++ ++/* ++ * Crypto-related utility routines used mainly by drivers. ++ * ++ * XXX these don't really belong here; but for now they're ++ * kept apart from the rest of the system. ++ */ ++struct uio; ++extern void cuio_copydata(struct uio* uio, int off, int len, caddr_t cp); ++extern void cuio_copyback(struct uio* uio, int off, int len, caddr_t cp); ++extern struct iovec *cuio_getptr(struct uio *uio, int loc, int *off); ++ ++extern void crypto_copyback(int flags, caddr_t buf, int off, int size, ++ caddr_t in); ++extern void crypto_copydata(int flags, caddr_t buf, int off, int size, ++ caddr_t out); ++extern int crypto_apply(int flags, caddr_t buf, int off, int len, ++ int (*f)(void *, void *, u_int), void *arg); ++ ++#endif /* __KERNEL__ */ ++#endif /* _CRYPTO_CRYPTO_H_ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/cryptosoft.c linux-2.6.39/crypto/ocf/cryptosoft.c +--- linux-2.6.39.orig/crypto/ocf/cryptosoft.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/cryptosoft.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,1210 @@ ++/* ++ * An OCF module that uses the linux kernel cryptoapi, based on the ++ * original cryptosoft for BSD by Angelos D. Keromytis (angelos@cis.upenn.edu) ++ * but is mostly unrecognisable, ++ * ++ * Written by David McCullough ++ * Copyright (C) 2004-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ * --------------------------------------------------------------------------- ++ */ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) ++#include ++#endif ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) ++#include ++#endif ++ ++#include ++#include ++ ++struct { ++ softc_device_decl sc_dev; ++} swcr_softc; ++ ++#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) ++ ++#define SW_TYPE_CIPHER 0x01 ++#define SW_TYPE_HMAC 0x02 ++#define SW_TYPE_HASH 0x04 ++#define SW_TYPE_COMP 0x08 ++#define SW_TYPE_BLKCIPHER 0x10 ++#define SW_TYPE_ALG_MASK 0x1f ++ ++#define SW_TYPE_ASYNC 0x8000 ++ ++/* We change some of the above if we have an async interface */ ++ ++#define SW_TYPE_ALG_AMASK (SW_TYPE_ALG_MASK | SW_TYPE_ASYNC) ++ ++#define SW_TYPE_ABLKCIPHER (SW_TYPE_BLKCIPHER | SW_TYPE_ASYNC) ++#define SW_TYPE_AHASH (SW_TYPE_HASH | SW_TYPE_ASYNC) ++#define SW_TYPE_AHMAC (SW_TYPE_HMAC | SW_TYPE_ASYNC) ++ ++#define SCATTERLIST_MAX 16 ++ ++struct swcr_data { ++ int sw_type; ++ int sw_alg; ++ struct crypto_tfm *sw_tfm; ++ union { ++ struct { ++ char *sw_key; ++ int sw_klen; ++ int sw_mlen; ++ } hmac; ++ void *sw_comp_buf; ++ } u; ++ struct swcr_data *sw_next; ++}; ++ ++struct swcr_req { ++ struct swcr_data *sw_head; ++ struct swcr_data *sw; ++ struct cryptop *crp; ++ struct cryptodesc *crd; ++ struct scatterlist sg[SCATTERLIST_MAX]; ++ unsigned char iv[EALG_MAX_BLOCK_LEN]; ++ char result[HASH_MAX_LEN]; ++ void *crypto_req; ++}; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++static kmem_cache_t *swcr_req_cache; ++#else ++static struct kmem_cache *swcr_req_cache; ++#endif ++ ++#ifndef CRYPTO_TFM_MODE_CBC ++/* ++ * As of linux-2.6.21 this is no longer defined, and presumably no longer ++ * needed to be passed into the crypto core code. ++ */ ++#define CRYPTO_TFM_MODE_CBC 0 ++#define CRYPTO_TFM_MODE_ECB 0 ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ++ /* ++ * Linux 2.6.19 introduced a new Crypto API, setup macro's to convert new ++ * API into old API. ++ */ ++ ++ /* Symmetric/Block Cipher */ ++ struct blkcipher_desc ++ { ++ struct crypto_tfm *tfm; ++ void *info; ++ }; ++ #define ecb(X) #X , CRYPTO_TFM_MODE_ECB ++ #define cbc(X) #X , CRYPTO_TFM_MODE_CBC ++ #define crypto_has_blkcipher(X, Y, Z) crypto_alg_available(X, 0) ++ #define crypto_blkcipher_cast(X) X ++ #define crypto_blkcipher_tfm(X) X ++ #define crypto_alloc_blkcipher(X, Y, Z) crypto_alloc_tfm(X, mode) ++ #define crypto_blkcipher_ivsize(X) crypto_tfm_alg_ivsize(X) ++ #define crypto_blkcipher_blocksize(X) crypto_tfm_alg_blocksize(X) ++ #define crypto_blkcipher_setkey(X, Y, Z) crypto_cipher_setkey(X, Y, Z) ++ #define crypto_blkcipher_encrypt_iv(W, X, Y, Z) \ ++ crypto_cipher_encrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) ++ #define crypto_blkcipher_decrypt_iv(W, X, Y, Z) \ ++ crypto_cipher_decrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) ++ #define crypto_blkcipher_set_flags(x, y) /* nop */ ++ ++ /* Hash/HMAC/Digest */ ++ struct hash_desc ++ { ++ struct crypto_tfm *tfm; ++ }; ++ #define hmac(X) #X , 0 ++ #define crypto_has_hash(X, Y, Z) crypto_alg_available(X, 0) ++ #define crypto_hash_cast(X) X ++ #define crypto_hash_tfm(X) X ++ #define crypto_alloc_hash(X, Y, Z) crypto_alloc_tfm(X, mode) ++ #define crypto_hash_digestsize(X) crypto_tfm_alg_digestsize(X) ++ #define crypto_hash_digest(W, X, Y, Z) \ ++ crypto_digest_digest((W)->tfm, X, sg_num, Z) ++ ++ /* Asymmetric Cipher */ ++ #define crypto_has_cipher(X, Y, Z) crypto_alg_available(X, 0) ++ ++ /* Compression */ ++ #define crypto_has_comp(X, Y, Z) crypto_alg_available(X, 0) ++ #define crypto_comp_tfm(X) X ++ #define crypto_comp_cast(X) X ++ #define crypto_alloc_comp(X, Y, Z) crypto_alloc_tfm(X, mode) ++ #define plain(X) #X , 0 ++#else ++ #define ecb(X) "ecb(" #X ")" , 0 ++ #define cbc(X) "cbc(" #X ")" , 0 ++ #define hmac(X) "hmac(" #X ")" , 0 ++ #define plain(X) #X , 0 ++#endif /* if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) ++/* no ablkcipher in older kernels */ ++#define crypto_alloc_ablkcipher(a,b,c) (NULL) ++#define crypto_ablkcipher_tfm(x) ((struct crypto_tfm *)(x)) ++#define crypto_ablkcipher_set_flags(a, b) /* nop */ ++#define crypto_ablkcipher_setkey(x, y, z) (-EINVAL) ++#define crypto_has_ablkcipher(a,b,c) (0) ++#else ++#define HAVE_ABLKCIPHER ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) ++/* no ahash in older kernels */ ++#define crypto_ahash_tfm(x) ((struct crypto_tfm *)(x)) ++#define crypto_alloc_ahash(a,b,c) (NULL) ++#define crypto_ahash_digestsize(x) 0 ++#else ++#define HAVE_AHASH ++#endif ++ ++struct crypto_details { ++ char *alg_name; ++ int mode; ++ int sw_type; ++}; ++ ++static struct crypto_details crypto_details[] = { ++ [CRYPTO_DES_CBC] = { cbc(des), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_3DES_CBC] = { cbc(des3_ede), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_BLF_CBC] = { cbc(blowfish), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_CAST_CBC] = { cbc(cast5), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_SKIPJACK_CBC] = { cbc(skipjack), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_MD5_HMAC] = { hmac(md5), SW_TYPE_HMAC, }, ++ [CRYPTO_SHA1_HMAC] = { hmac(sha1), SW_TYPE_HMAC, }, ++ [CRYPTO_RIPEMD160_HMAC] = { hmac(ripemd160), SW_TYPE_HMAC, }, ++ [CRYPTO_MD5_KPDK] = { plain(md5-kpdk), SW_TYPE_HASH, }, ++ [CRYPTO_SHA1_KPDK] = { plain(sha1-kpdk), SW_TYPE_HASH, }, ++ [CRYPTO_AES_CBC] = { cbc(aes), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_ARC4] = { ecb(arc4), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_MD5] = { plain(md5), SW_TYPE_HASH, }, ++ [CRYPTO_SHA1] = { plain(sha1), SW_TYPE_HASH, }, ++ [CRYPTO_NULL_HMAC] = { hmac(digest_null), SW_TYPE_HMAC, }, ++ [CRYPTO_NULL_CBC] = { cbc(cipher_null), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_DEFLATE_COMP] = { plain(deflate), SW_TYPE_COMP, }, ++ [CRYPTO_SHA2_256_HMAC] = { hmac(sha256), SW_TYPE_HMAC, }, ++ [CRYPTO_SHA2_384_HMAC] = { hmac(sha384), SW_TYPE_HMAC, }, ++ [CRYPTO_SHA2_512_HMAC] = { hmac(sha512), SW_TYPE_HMAC, }, ++ [CRYPTO_CAMELLIA_CBC] = { cbc(camellia), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_SHA2_256] = { plain(sha256), SW_TYPE_HASH, }, ++ [CRYPTO_SHA2_384] = { plain(sha384), SW_TYPE_HASH, }, ++ [CRYPTO_SHA2_512] = { plain(sha512), SW_TYPE_HASH, }, ++ [CRYPTO_RIPEMD160] = { plain(ripemd160), SW_TYPE_HASH, }, ++}; ++ ++int32_t swcr_id = -1; ++module_param(swcr_id, int, 0444); ++MODULE_PARM_DESC(swcr_id, "Read-Only OCF ID for cryptosoft driver"); ++ ++int swcr_fail_if_compression_grows = 1; ++module_param(swcr_fail_if_compression_grows, int, 0644); ++MODULE_PARM_DESC(swcr_fail_if_compression_grows, ++ "Treat compression that results in more data as a failure"); ++ ++int swcr_no_ahash = 0; ++module_param(swcr_no_ahash, int, 0644); ++MODULE_PARM_DESC(swcr_no_ahash, ++ "Do not use async hash/hmac even if available"); ++ ++int swcr_no_ablk = 0; ++module_param(swcr_no_ablk, int, 0644); ++MODULE_PARM_DESC(swcr_no_ablk, ++ "Do not use async blk ciphers even if available"); ++ ++static struct swcr_data **swcr_sessions = NULL; ++static u_int32_t swcr_sesnum = 0; ++ ++static int swcr_process(device_t, struct cryptop *, int); ++static int swcr_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int swcr_freesession(device_t, u_int64_t); ++ ++static device_method_t swcr_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, swcr_newsession), ++ DEVMETHOD(cryptodev_freesession,swcr_freesession), ++ DEVMETHOD(cryptodev_process, swcr_process), ++}; ++ ++#define debug swcr_debug ++int swcr_debug = 0; ++module_param(swcr_debug, int, 0644); ++MODULE_PARM_DESC(swcr_debug, "Enable debug"); ++ ++static void swcr_process_req(struct swcr_req *req); ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++swcr_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct swcr_data **swd; ++ u_int32_t i; ++ int error; ++ char *algo; ++ int mode; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (swcr_sessions) { ++ for (i = 1; i < swcr_sesnum; i++) ++ if (swcr_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (swcr_sessions == NULL || i == swcr_sesnum) { ++ if (swcr_sessions == NULL) { ++ i = 1; /* We leave swcr_sessions[0] empty */ ++ swcr_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ swcr_sesnum *= 2; ++ ++ swd = kmalloc(swcr_sesnum * sizeof(struct swcr_data *), SLAB_ATOMIC); ++ if (swd == NULL) { ++ /* Reset session number */ ++ if (swcr_sesnum == CRYPTO_SW_SESSIONS) ++ swcr_sesnum = 0; ++ else ++ swcr_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(swd, 0, swcr_sesnum * sizeof(struct swcr_data *)); ++ ++ /* Copy existing sessions */ ++ if (swcr_sessions) { ++ memcpy(swd, swcr_sessions, ++ (swcr_sesnum / 2) * sizeof(struct swcr_data *)); ++ kfree(swcr_sessions); ++ } ++ ++ swcr_sessions = swd; ++ } ++ ++ swd = &swcr_sessions[i]; ++ *sid = i; ++ ++ while (cri) { ++ *swd = (struct swcr_data *) kmalloc(sizeof(struct swcr_data), ++ SLAB_ATOMIC); ++ if (*swd == NULL) { ++ swcr_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(*swd, 0, sizeof(struct swcr_data)); ++ ++ if (cri->cri_alg < 0 || ++ cri->cri_alg>=sizeof(crypto_details)/sizeof(crypto_details[0])){ ++ printk("cryptosoft: Unknown algorithm 0x%x\n", cri->cri_alg); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ algo = crypto_details[cri->cri_alg].alg_name; ++ if (!algo || !*algo) { ++ printk("cryptosoft: Unsupported algorithm 0x%x\n", cri->cri_alg); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ mode = crypto_details[cri->cri_alg].mode; ++ (*swd)->sw_type = crypto_details[cri->cri_alg].sw_type; ++ (*swd)->sw_alg = cri->cri_alg; ++ ++ /* Algorithm specific configuration */ ++ switch (cri->cri_alg) { ++ case CRYPTO_NULL_CBC: ++ cri->cri_klen = 0; /* make it work with crypto API */ ++ break; ++ default: ++ break; ++ } ++ ++ if ((*swd)->sw_type & SW_TYPE_BLKCIPHER) { ++ dprintk("%s crypto_alloc_*blkcipher(%s, 0x%x)\n", __FUNCTION__, ++ algo, mode); ++ ++ /* try async first */ ++ (*swd)->sw_tfm = swcr_no_ablk ? NULL : ++ crypto_ablkcipher_tfm(crypto_alloc_ablkcipher(algo, 0, 0)); ++ if ((*swd)->sw_tfm) { ++ dprintk("%s %s cipher is async\n", __FUNCTION__, algo); ++ (*swd)->sw_type |= SW_TYPE_ASYNC; ++ } else { ++ dprintk("%s %s cipher is sync\n", __FUNCTION__, algo); ++ (*swd)->sw_tfm = crypto_blkcipher_tfm( ++ crypto_alloc_blkcipher(algo, 0, CRYPTO_ALG_ASYNC)); ++ } ++ if (!(*swd)->sw_tfm) { ++ dprintk("cryptosoft: crypto_alloc_blkcipher failed(%s, 0x%x)\n", ++ algo,mode); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ if (debug) { ++ dprintk("%s key:cri->cri_klen=%d,(cri->cri_klen + 7)/8=%d", ++ __FUNCTION__, cri->cri_klen, (cri->cri_klen + 7) / 8); ++ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) ++ dprintk("%s0x%x", (i % 8) ? " " : "\n ", ++ cri->cri_key[i] & 0xff); ++ dprintk("\n"); ++ } ++ if ((*swd)->sw_type & SW_TYPE_ASYNC) { ++ /* OCF doesn't enforce keys */ ++ crypto_ablkcipher_set_flags( ++ __crypto_ablkcipher_cast((*swd)->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_ablkcipher_setkey( ++ __crypto_ablkcipher_cast((*swd)->sw_tfm), ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } else { ++ /* OCF doesn't enforce keys */ ++ crypto_blkcipher_set_flags( ++ crypto_blkcipher_cast((*swd)->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_blkcipher_setkey( ++ crypto_blkcipher_cast((*swd)->sw_tfm), ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ if (error) { ++ printk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", error, ++ (*swd)->sw_tfm->crt_flags); ++ swcr_freesession(NULL, i); ++ return error; ++ } ++ } else if ((*swd)->sw_type & (SW_TYPE_HMAC | SW_TYPE_HASH)) { ++ dprintk("%s crypto_alloc_*hash(%s, 0x%x)\n", __FUNCTION__, ++ algo, mode); ++ ++ /* try async first */ ++ (*swd)->sw_tfm = swcr_no_ahash ? NULL : ++ crypto_ahash_tfm(crypto_alloc_ahash(algo, 0, 0)); ++ if ((*swd)->sw_tfm) { ++ dprintk("%s %s hash is async\n", __FUNCTION__, algo); ++ (*swd)->sw_type |= SW_TYPE_ASYNC; ++ } else { ++ dprintk("%s %s hash is sync\n", __FUNCTION__, algo); ++ (*swd)->sw_tfm = crypto_hash_tfm( ++ crypto_alloc_hash(algo, 0, CRYPTO_ALG_ASYNC)); ++ } ++ ++ if (!(*swd)->sw_tfm) { ++ dprintk("cryptosoft: crypto_alloc_hash failed(%s,0x%x)\n", ++ algo, mode); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ (*swd)->u.hmac.sw_klen = (cri->cri_klen + 7) / 8; ++ (*swd)->u.hmac.sw_key = (char *)kmalloc((*swd)->u.hmac.sw_klen, ++ SLAB_ATOMIC); ++ if ((*swd)->u.hmac.sw_key == NULL) { ++ swcr_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memcpy((*swd)->u.hmac.sw_key, cri->cri_key, (*swd)->u.hmac.sw_klen); ++ if (cri->cri_mlen) { ++ (*swd)->u.hmac.sw_mlen = cri->cri_mlen; ++ } else if ((*swd)->sw_type & SW_TYPE_ASYNC) { ++ (*swd)->u.hmac.sw_mlen = crypto_ahash_digestsize( ++ __crypto_ahash_cast((*swd)->sw_tfm)); ++ } else { ++ (*swd)->u.hmac.sw_mlen = crypto_hash_digestsize( ++ crypto_hash_cast((*swd)->sw_tfm)); ++ } ++ } else if ((*swd)->sw_type & SW_TYPE_COMP) { ++ (*swd)->sw_tfm = crypto_comp_tfm( ++ crypto_alloc_comp(algo, 0, CRYPTO_ALG_ASYNC)); ++ if (!(*swd)->sw_tfm) { ++ dprintk("cryptosoft: crypto_alloc_comp failed(%s,0x%x)\n", ++ algo, mode); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ (*swd)->u.sw_comp_buf = kmalloc(CRYPTO_MAX_DATA_LEN, SLAB_ATOMIC); ++ if ((*swd)->u.sw_comp_buf == NULL) { ++ swcr_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ } else { ++ printk("cryptosoft: Unhandled sw_type %d\n", (*swd)->sw_type); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ cri = cri->cri_next; ++ swd = &((*swd)->sw_next); ++ } ++ return 0; ++} ++ ++/* ++ * Free a session. ++ */ ++static int ++swcr_freesession(device_t dev, u_int64_t tid) ++{ ++ struct swcr_data *swd; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > swcr_sesnum || swcr_sessions == NULL || ++ swcr_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ while ((swd = swcr_sessions[sid]) != NULL) { ++ swcr_sessions[sid] = swd->sw_next; ++ if (swd->sw_tfm) { ++ switch (swd->sw_type & SW_TYPE_ALG_AMASK) { ++#ifdef HAVE_AHASH ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++ crypto_free_ahash(__crypto_ahash_cast(swd->sw_tfm)); ++ break; ++#endif ++#ifdef HAVE_ABLKCIPHER ++ case SW_TYPE_ABLKCIPHER: ++ crypto_free_ablkcipher(__crypto_ablkcipher_cast(swd->sw_tfm)); ++ break; ++#endif ++ case SW_TYPE_BLKCIPHER: ++ crypto_free_blkcipher(crypto_blkcipher_cast(swd->sw_tfm)); ++ break; ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ crypto_free_hash(crypto_hash_cast(swd->sw_tfm)); ++ break; ++ case SW_TYPE_COMP: ++ crypto_free_comp(crypto_comp_cast(swd->sw_tfm)); ++ default: ++ crypto_free_tfm(swd->sw_tfm); ++ break; ++ } ++ swd->sw_tfm = NULL; ++ } ++ if (swd->sw_type & SW_TYPE_COMP) { ++ if (swd->u.sw_comp_buf) ++ kfree(swd->u.sw_comp_buf); ++ } else { ++ if (swd->u.hmac.sw_key) ++ kfree(swd->u.hmac.sw_key); ++ } ++ kfree(swd); ++ } ++ return 0; ++} ++ ++#if defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) ++/* older kernels had no async interface */ ++ ++static void swcr_process_callback(struct crypto_async_request *creq, int err) ++{ ++ struct swcr_req *req = creq->data; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (err) { ++ if (err == -EINPROGRESS) ++ return; ++ dprintk("%s() fail %d\n", __FUNCTION__, -err); ++ req->crp->crp_etype = -err; ++ goto done; ++ } ++ ++ switch (req->sw->sw_type & SW_TYPE_ALG_AMASK) { ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++ crypto_copyback(req->crp->crp_flags, req->crp->crp_buf, ++ req->crd->crd_inject, req->sw->u.hmac.sw_mlen, req->result); ++ ahash_request_free(req->crypto_req); ++ break; ++ case SW_TYPE_ABLKCIPHER: ++ ablkcipher_request_free(req->crypto_req); ++ break; ++ default: ++ req->crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ req->crd = req->crd->crd_next; ++ if (req->crd) { ++ swcr_process_req(req); ++ return; ++ } ++ ++done: ++ dprintk("%s crypto_done %p\n", __FUNCTION__, req); ++ crypto_done(req->crp); ++ kmem_cache_free(swcr_req_cache, req); ++} ++#endif /* defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) */ ++ ++ ++static void swcr_process_req(struct swcr_req *req) ++{ ++ struct swcr_data *sw; ++ struct cryptop *crp = req->crp; ++ struct cryptodesc *crd = req->crd; ++ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; ++ struct uio *uiop = (struct uio *) crp->crp_buf; ++ int sg_num, sg_len, skip; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* ++ * Find the crypto context. ++ * ++ * XXX Note that the logic here prevents us from having ++ * XXX the same algorithm multiple times in a session ++ * XXX (or rather, we can but it won't give us the right ++ * XXX results). To do that, we'd need some way of differentiating ++ * XXX between the various instances of an algorithm (so we can ++ * XXX locate the correct crypto context). ++ */ ++ for (sw = req->sw_head; sw && sw->sw_alg != crd->crd_alg; sw = sw->sw_next) ++ ; ++ ++ /* No such context ? */ ++ if (sw == NULL) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ req->sw = sw; ++ skip = crd->crd_skip; ++ ++ /* ++ * setup the SG list skip from the start of the buffer ++ */ ++ memset(req->sg, 0, sizeof(req->sg)); ++ sg_init_table(req->sg, SCATTERLIST_MAX); ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ int i, len; ++ ++ sg_num = 0; ++ sg_len = 0; ++ ++ if (skip < skb_headlen(skb)) { ++ len = skb_headlen(skb) - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ sg_set_page(&req->sg[sg_num], ++ virt_to_page(skb->data + skip), len, ++ offset_in_page(skb->data + skip)); ++ sg_len += len; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_headlen(skb); ++ ++ for (i = 0; sg_len < crd->crd_len && ++ i < skb_shinfo(skb)->nr_frags && ++ sg_num < SCATTERLIST_MAX; i++) { ++ if (skip < skb_shinfo(skb)->frags[i].size) { ++ len = skb_shinfo(skb)->frags[i].size - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ sg_set_page(&req->sg[sg_num], ++ skb_shinfo(skb)->frags[i].page, ++ len, ++ skb_shinfo(skb)->frags[i].page_offset + skip); ++ sg_len += len; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_shinfo(skb)->frags[i].size; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ int len; ++ ++ sg_len = 0; ++ for (sg_num = 0; sg_len < crd->crd_len && ++ sg_num < uiop->uio_iovcnt && ++ sg_num < SCATTERLIST_MAX; sg_num++) { ++ if (skip <= uiop->uio_iov[sg_num].iov_len) { ++ len = uiop->uio_iov[sg_num].iov_len - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ sg_set_page(&req->sg[sg_num], ++ virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), ++ len, ++ offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); ++ sg_len += len; ++ skip = 0; ++ } else ++ skip -= uiop->uio_iov[sg_num].iov_len; ++ } ++ } else { ++ sg_len = (crp->crp_ilen - skip); ++ if (sg_len > crd->crd_len) ++ sg_len = crd->crd_len; ++ sg_set_page(&req->sg[0], virt_to_page(crp->crp_buf + skip), ++ sg_len, offset_in_page(crp->crp_buf + skip)); ++ sg_num = 1; ++ } ++ ++ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { ++ ++#ifdef HAVE_AHASH ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++ { ++ int ret; ++ ++ /* check we have room for the result */ ++ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { ++ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " ++ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, ++ crd->crd_inject, sw->u.hmac.sw_mlen); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ req->crypto_req = ++ ahash_request_alloc(__crypto_ahash_cast(sw->sw_tfm),GFP_KERNEL); ++ if (!req->crypto_req) { ++ crp->crp_etype = ENOMEM; ++ dprintk("%s,%d: ENOMEM ahash_request_alloc", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ ahash_request_set_callback(req->crypto_req, ++ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); ++ ++ memset(req->result, 0, sizeof(req->result)); ++ ++ if (sw->sw_type & SW_TYPE_AHMAC) ++ crypto_ahash_setkey(__crypto_ahash_cast(sw->sw_tfm), ++ sw->u.hmac.sw_key, sw->u.hmac.sw_klen); ++ ahash_request_set_crypt(req->crypto_req, req->sg, req->result, sg_len); ++ ret = crypto_ahash_digest(req->crypto_req); ++ switch (ret) { ++ case -EINPROGRESS: ++ case -EBUSY: ++ return; ++ default: ++ case 0: ++ dprintk("hash OP %s %d\n", ret ? "failed" : "success", ret); ++ crp->crp_etype = ret; ++ ahash_request_free(req->crypto_req); ++ goto done; ++ } ++ } break; ++#endif /* HAVE_AHASH */ ++ ++#ifdef HAVE_ABLKCIPHER ++ case SW_TYPE_ABLKCIPHER: { ++ int ret; ++ unsigned char *ivp = req->iv; ++ int ivsize = ++ crypto_ablkcipher_ivsize(__crypto_ablkcipher_cast(sw->sw_tfm)); ++ ++ if (sg_len < crypto_ablkcipher_blocksize( ++ __crypto_ablkcipher_cast(sw->sw_tfm))) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, ++ sg_len, crypto_ablkcipher_blocksize( ++ __crypto_ablkcipher_cast(sw->sw_tfm))); ++ goto done; ++ } ++ ++ if (ivsize > sizeof(req->iv)) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ req->crypto_req = ablkcipher_request_alloc( ++ __crypto_ablkcipher_cast(sw->sw_tfm), GFP_KERNEL); ++ if (!req->crypto_req) { ++ crp->crp_etype = ENOMEM; ++ dprintk("%s,%d: ENOMEM ablkcipher_request_alloc", ++ __FILE__, __LINE__); ++ goto done; ++ } ++ ++ ablkcipher_request_set_callback(req->crypto_req, ++ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); ++ ++ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ int i, error; ++ ++ if (debug) { ++ dprintk("%s key:", __FUNCTION__); ++ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) ++ dprintk("%s0x%x", (i % 8) ? " " : "\n ", ++ crd->crd_key[i] & 0xff); ++ dprintk("\n"); ++ } ++ /* OCF doesn't enforce keys */ ++ crypto_ablkcipher_set_flags(__crypto_ablkcipher_cast(sw->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_ablkcipher_setkey( ++ __crypto_ablkcipher_cast(sw->sw_tfm), crd->crd_key, ++ (crd->crd_klen + 7) / 8); ++ if (error) { ++ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", ++ error, sw->sw_tfm->crt_flags); ++ crp->crp_etype = -error; ++ } ++ } ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) ++ ivp = crd->crd_iv; ++ else ++ get_random_bytes(ivp, ivsize); ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ } ++ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, ++ sg_len, ivp); ++ ret = crypto_ablkcipher_encrypt(req->crypto_req); ++ ++ } else { /*decrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) ++ ivp = crd->crd_iv; ++ else ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, ++ sg_len, ivp); ++ ret = crypto_ablkcipher_decrypt(req->crypto_req); ++ } ++ ++ switch (ret) { ++ case -EINPROGRESS: ++ case -EBUSY: ++ return; ++ default: ++ case 0: ++ dprintk("crypto OP %s %d\n", ret ? "failed" : "success", ret); ++ crp->crp_etype = ret; ++ goto done; ++ } ++ } break; ++#endif /* HAVE_ABLKCIPHER */ ++ ++ case SW_TYPE_BLKCIPHER: { ++ unsigned char iv[EALG_MAX_BLOCK_LEN]; ++ unsigned char *ivp = iv; ++ struct blkcipher_desc desc; ++ int ivsize = crypto_blkcipher_ivsize(crypto_blkcipher_cast(sw->sw_tfm)); ++ ++ if (sg_len < crypto_blkcipher_blocksize( ++ crypto_blkcipher_cast(sw->sw_tfm))) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, ++ sg_len, crypto_blkcipher_blocksize( ++ crypto_blkcipher_cast(sw->sw_tfm))); ++ goto done; ++ } ++ ++ if (ivsize > sizeof(iv)) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ int i, error; ++ ++ if (debug) { ++ dprintk("%s key:", __FUNCTION__); ++ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) ++ dprintk("%s0x%x", (i % 8) ? " " : "\n ", ++ crd->crd_key[i] & 0xff); ++ dprintk("\n"); ++ } ++ /* OCF doesn't enforce keys */ ++ crypto_blkcipher_set_flags(crypto_blkcipher_cast(sw->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_blkcipher_setkey( ++ crypto_blkcipher_cast(sw->sw_tfm), crd->crd_key, ++ (crd->crd_klen + 7) / 8); ++ if (error) { ++ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", ++ error, sw->sw_tfm->crt_flags); ++ crp->crp_etype = -error; ++ } ++ } ++ ++ memset(&desc, 0, sizeof(desc)); ++ desc.tfm = crypto_blkcipher_cast(sw->sw_tfm); ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ get_random_bytes(ivp, ivsize); ++ } ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ } ++ desc.info = ivp; ++ crypto_blkcipher_encrypt_iv(&desc, req->sg, req->sg, sg_len); ++ ++ } else { /*decrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ } ++ desc.info = ivp; ++ crypto_blkcipher_decrypt_iv(&desc, req->sg, req->sg, sg_len); ++ } ++ } break; ++ ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ { ++ char result[HASH_MAX_LEN]; ++ struct hash_desc desc; ++ ++ /* check we have room for the result */ ++ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { ++ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " ++ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, ++ crd->crd_inject, sw->u.hmac.sw_mlen); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ memset(&desc, 0, sizeof(desc)); ++ desc.tfm = crypto_hash_cast(sw->sw_tfm); ++ ++ memset(result, 0, sizeof(result)); ++ ++ if (sw->sw_type & SW_TYPE_HMAC) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ++ crypto_hmac(sw->sw_tfm, sw->u.hmac.sw_key, &sw->u.hmac.sw_klen, ++ req->sg, sg_num, result); ++#else ++ crypto_hash_setkey(desc.tfm, sw->u.hmac.sw_key, ++ sw->u.hmac.sw_klen); ++ crypto_hash_digest(&desc, req->sg, sg_len, result); ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ ++ ++ } else { /* SW_TYPE_HASH */ ++ crypto_hash_digest(&desc, req->sg, sg_len, result); ++ } ++ ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, sw->u.hmac.sw_mlen, result); ++ } ++ break; ++ ++ case SW_TYPE_COMP: { ++ void *ibuf = NULL; ++ void *obuf = sw->u.sw_comp_buf; ++ int ilen = sg_len, olen = CRYPTO_MAX_DATA_LEN; ++ int ret = 0; ++ ++ /* ++ * we need to use an additional copy if there is more than one ++ * input chunk since the kernel comp routines do not handle ++ * SG yet. Otherwise we just use the input buffer as is. ++ * Rather than allocate another buffer we just split the tmp ++ * buffer we already have. ++ * Perhaps we should just use zlib directly ? ++ */ ++ if (sg_num > 1) { ++ int blk; ++ ++ ibuf = obuf; ++ for (blk = 0; blk < sg_num; blk++) { ++ memcpy(obuf, sg_virt(&req->sg[blk]), ++ req->sg[blk].length); ++ obuf += req->sg[blk].length; ++ } ++ olen -= sg_len; ++ } else ++ ibuf = sg_virt(&req->sg[0]); ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* compress */ ++ ret = crypto_comp_compress(crypto_comp_cast(sw->sw_tfm), ++ ibuf, ilen, obuf, &olen); ++ if (!ret && olen > crd->crd_len) { ++ dprintk("cryptosoft: ERANGE compress %d into %d\n", ++ crd->crd_len, olen); ++ if (swcr_fail_if_compression_grows) ++ ret = ERANGE; ++ } ++ } else { /* decompress */ ++ ret = crypto_comp_decompress(crypto_comp_cast(sw->sw_tfm), ++ ibuf, ilen, obuf, &olen); ++ if (!ret && (olen + crd->crd_inject) > crp->crp_olen) { ++ dprintk("cryptosoft: ETOOSMALL decompress %d into %d, " ++ "space for %d,at offset %d\n", ++ crd->crd_len, olen, crp->crp_olen, crd->crd_inject); ++ ret = ETOOSMALL; ++ } ++ } ++ if (ret) ++ dprintk("%s,%d: ret = %d\n", __FILE__, __LINE__, ret); ++ ++ /* ++ * on success copy result back, ++ * linux crpyto API returns -errno, we need to fix that ++ */ ++ crp->crp_etype = ret < 0 ? -ret : ret; ++ if (ret == 0) { ++ /* copy back the result and return it's size */ ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, olen, obuf); ++ crp->crp_olen = olen; ++ } ++ ++ ++ } break; ++ ++ default: ++ /* Unknown/unsupported algorithm */ ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++done: ++ crypto_done(crp); ++ kmem_cache_free(swcr_req_cache, req); ++} ++ ++ ++/* ++ * Process a crypto request. ++ */ ++static int ++swcr_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct swcr_req *req = NULL; ++ u_int32_t lid; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= swcr_sesnum || lid == 0 || swcr_sessions == NULL || ++ swcr_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ /* ++ * do some error checking outside of the loop for SKB and IOV processing ++ * this leaves us with valid skb or uiop pointers for later ++ */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { ++ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, ++ skb_shinfo(skb)->nr_frags); ++ goto done; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ struct uio *uiop = (struct uio *) crp->crp_buf; ++ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { ++ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, ++ uiop->uio_iovcnt); ++ goto done; ++ } ++ } ++ ++ /* ++ * setup a new request ready for queuing ++ */ ++ req = kmem_cache_alloc(swcr_req_cache, SLAB_ATOMIC); ++ if (req == NULL) { ++ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); ++ crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ memset(req, 0, sizeof(*req)); ++ ++ req->sw_head = swcr_sessions[lid]; ++ req->crp = crp; ++ req->crd = crp->crp_desc; ++ ++ swcr_process_req(req); ++ return 0; ++ ++done: ++ crypto_done(crp); ++ if (req) ++ kmem_cache_free(swcr_req_cache, req); ++ return 0; ++} ++ ++ ++static int ++cryptosoft_init(void) ++{ ++ int i, sw_type, mode; ++ char *algo; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, cryptosoft_init); ++ ++ swcr_req_cache = kmem_cache_create("cryptosoft_req", ++ sizeof(struct swcr_req), 0, SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ if (!swcr_req_cache) { ++ printk("cryptosoft: failed to create request cache\n"); ++ return -ENOENT; ++ } ++ ++ softc_device_init(&swcr_softc, "cryptosoft", 0, swcr_methods); ++ ++ swcr_id = crypto_get_driverid(softc_get_device(&swcr_softc), ++ CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_SYNC); ++ if (swcr_id < 0) { ++ printk("cryptosoft: Software crypto device cannot initialize!"); ++ return -ENODEV; ++ } ++ ++#define REGISTER(alg) \ ++ crypto_register(swcr_id, alg, 0,0) ++ ++ for (i = 0; i < sizeof(crypto_details)/sizeof(crypto_details[0]); i++) { ++ int found; ++ ++ algo = crypto_details[i].alg_name; ++ if (!algo || !*algo) { ++ dprintk("%s:Algorithm %d not supported\n", __FUNCTION__, i); ++ continue; ++ } ++ ++ mode = crypto_details[i].mode; ++ sw_type = crypto_details[i].sw_type; ++ ++ found = 0; ++ switch (sw_type & SW_TYPE_ALG_MASK) { ++ case SW_TYPE_CIPHER: ++ found = crypto_has_cipher(algo, 0, CRYPTO_ALG_ASYNC); ++ break; ++ case SW_TYPE_HMAC: ++ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); ++ break; ++ case SW_TYPE_HASH: ++ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); ++ break; ++ case SW_TYPE_COMP: ++ found = crypto_has_comp(algo, 0, CRYPTO_ALG_ASYNC); ++ break; ++ case SW_TYPE_BLKCIPHER: ++ found = crypto_has_blkcipher(algo, 0, CRYPTO_ALG_ASYNC); ++ if (!found && !swcr_no_ablk) ++ found = crypto_has_ablkcipher(algo, 0, 0); ++ break; ++ } ++ if (found) { ++ REGISTER(i); ++ } else { ++ dprintk("%s:Algorithm Type %d not supported (algorithm %d:'%s')\n", ++ __FUNCTION__, sw_type, i, algo); ++ } ++ } ++ return 0; ++} ++ ++static void ++cryptosoft_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(swcr_id); ++ swcr_id = -1; ++ kmem_cache_destroy(swcr_req_cache); ++} ++ ++late_initcall(cryptosoft_init); ++module_exit(cryptosoft_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Cryptosoft (OCF module for kernel crypto)"); +diff -Nur linux-2.6.39.orig/crypto/ocf/ep80579/Makefile linux-2.6.39/crypto/ocf/ep80579/Makefile +--- linux-2.6.39.orig/crypto/ocf/ep80579/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/ep80579/Makefile 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,119 @@ ++######################################################################### ++# ++# Targets supported ++# all - builds everything and installs ++# install - identical to all ++# depend - build dependencies ++# clean - clears derived objects except the .depend files ++# distclean- clears all derived objects and the .depend file ++# ++# @par ++# This file is provided under a dual BSD/GPLv2 license. When using or ++# redistributing this file, you may do so under either license. ++# ++# GPL LICENSE SUMMARY ++# ++# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of version 2 of the GNU General Public License as ++# published by the Free Software Foundation. ++# ++# This program is distributed in the hope that it will be useful, but ++# WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++# General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++# The full GNU General Public License is included in this distribution ++# in the file called LICENSE.GPL. ++# ++# Contact Information: ++# Intel Corporation ++# ++# BSD LICENSE ++# ++# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++# All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of Intel Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++# ++# ++# version: Security.L.1.0.2-229 ++############################################################################ ++ ++ ++####################Common variables and definitions######################## ++ ++ifndef ICP_ROOT ++$(warning ICP_ROOT is undefined. Please set the path to EP80579 release package directory \ ++ "-> setenv ICP_ROOT ") ++all fastdep: ++ : ++else ++ ++ifndef KERNEL_SOURCE_ROOT ++$(error KERNEL_SOURCE_ROOT is undefined. Please set the path to the kernel source directory \ ++ "-> setenv KERNEL_SOURCE_ROOT ") ++endif ++ ++# Ensure The ENV_DIR environmental var is defined. ++ifndef ICP_ENV_DIR ++$(error ICP_ENV_DIR is undefined. Please set the path to EP80579 driver environment.mk file \ ++ "-> setenv ICP_ENV_DIR ") ++endif ++ ++#Add your project environment Makefile ++include ${ICP_ENV_DIR}/environment.mk ++ ++#include the makefile with all the default and common Make variable definitions ++include ${ICP_BUILDSYSTEM_PATH}/build_files/common.mk ++ ++#Add the name for the executable, Library or Module output definitions ++OUTPUT_NAME= icp_ocf ++ ++# List of Source Files to be compiled ++SOURCES= icp_common.c icp_sym.c icp_asym.c icp_ocf_linux.c ++ ++#common includes between all supported OSes ++INCLUDES= -I ${ICP_API_DIR} -I${ICP_LAC_API} \ ++-I${ICP_OCF_SRC_DIR} ++ ++# The location of the os level makefile needs to be changed. ++include ${ICP_ENV_DIR}/${ICP_OS}_${ICP_OS_LEVEL}.mk ++ ++# On the line directly below list the outputs you wish to build for, ++# e.g "lib_static lib_shared exe module" as shown below ++install: module ++ ++###################Include rules makefiles######################## ++include ${ICP_BUILDSYSTEM_PATH}/build_files/rules.mk ++###################End of Rules inclusion######################### ++ ++endif +diff -Nur linux-2.6.39.orig/crypto/ocf/ep80579/icp_asym.c linux-2.6.39/crypto/ocf/ep80579/icp_asym.c +--- linux-2.6.39.orig/crypto/ocf/ep80579/icp_asym.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/ep80579/icp_asym.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,1334 @@ ++/*************************************************************************** ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++ ++#include "icp_ocf.h" ++ ++/*The following define values (containing the word 'INDEX') are used to find ++the index of each input buffer of the crypto_kop struct (see OCF cryptodev.h). ++These values were found through analysis of the OCF OpenSSL patch. If the ++calling program uses different input buffer positions, these defines will have ++to be changed.*/ ++ ++/*DIFFIE HELLMAN buffer index values*/ ++#define ICP_DH_KRP_PARAM_PRIME_INDEX (0) ++#define ICP_DH_KRP_PARAM_BASE_INDEX (1) ++#define ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX (2) ++#define ICP_DH_KRP_PARAM_RESULT_INDEX (3) ++ ++/*MOD EXP buffer index values*/ ++#define ICP_MOD_EXP_KRP_PARAM_BASE_INDEX (0) ++#define ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX (1) ++#define ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX (2) ++#define ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX (3) ++ ++/*MOD EXP CRT buffer index values*/ ++#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX (0) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX (1) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX (2) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX (3) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX (4) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX (5) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX (6) ++ ++/*DSA sign buffer index values*/ ++#define ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX (0) ++#define ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX (1) ++#define ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX (2) ++#define ICP_DSA_SIGN_KRP_PARAM_G_INDEX (3) ++#define ICP_DSA_SIGN_KRP_PARAM_X_INDEX (4) ++#define ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX (5) ++#define ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX (6) ++ ++/*DSA verify buffer index values*/ ++#define ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX (0) ++#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX (1) ++#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX (2) ++#define ICP_DSA_VERIFY_KRP_PARAM_G_INDEX (3) ++#define ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX (4) ++#define ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX (5) ++#define ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX (6) ++ ++/*DSA sign prime Q vs random number K size check values*/ ++#define DONT_RUN_LESS_THAN_CHECK (0) ++#define FAIL_A_IS_GREATER_THAN_B (1) ++#define FAIL_A_IS_EQUAL_TO_B (1) ++#define SUCCESS_A_IS_LESS_THAN_B (0) ++#define DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS (500) ++ ++/* We need to set a cryptokp success value just in case it is set or allocated ++ and not set to zero outside of this module */ ++#define CRYPTO_OP_SUCCESS (0) ++ ++/*Function to compute Diffie Hellman (DH) phase 1 or phase 2 key values*/ ++static int icp_ocfDrvDHComputeKey(struct cryptkop *krp); ++ ++/*Function to compute a Modular Exponentiation (Mod Exp)*/ ++static int icp_ocfDrvModExp(struct cryptkop *krp); ++ ++/*Function to compute a Mod Exp using the Chinease Remainder Theorem*/ ++static int icp_ocfDrvModExpCRT(struct cryptkop *krp); ++ ++/*Helper function to compute whether the first big number argument is less than ++ the second big number argument */ ++static int ++icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck); ++ ++/*Function to sign an input with DSA R and S keys*/ ++static int icp_ocfDrvDsaSign(struct cryptkop *krp); ++ ++/*Function to Verify a DSA buffer signature*/ ++static int icp_ocfDrvDsaVerify(struct cryptkop *krp); ++ ++/*Callback function for DH operation*/ ++static void ++icp_ocfDrvDhP1CallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV); ++ ++/*Callback function for ME operation*/ ++static void ++icp_ocfDrvModExpCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pResult); ++ ++/*Callback function for ME CRT operation*/ ++static void ++icp_ocfDrvModExpCRTCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pOutputData); ++ ++/*Callback function for DSA sign operation*/ ++static void ++icp_ocfDrvDsaRSSignCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, ++ CpaBoolean protocolStatus, ++ CpaFlatBuffer * pR, CpaFlatBuffer * pS); ++ ++/*Callback function for DSA Verify operation*/ ++static void ++icp_ocfDrvDsaVerifyCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaBoolean verifyStatus); ++ ++/* Name : icp_ocfDrvPkeProcess ++ * ++ * Description : This function will choose which PKE process to follow ++ * based on the input arguments ++ */ ++int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ ++ if (NULL == krp) { ++ DPRINTK("%s(): Invalid input parameters, cryptkop = %p\n", ++ __FUNCTION__, krp); ++ return EINVAL; ++ } ++ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ switch (krp->krp_op) { ++ case CRK_DH_COMPUTE_KEY: ++ DPRINTK("%s() doing DH_COMPUTE_KEY\n", __FUNCTION__); ++ lacStatus = icp_ocfDrvDHComputeKey(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvDHComputeKey failed " ++ "(%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_MOD_EXP: ++ DPRINTK("%s() doing MOD_EXP \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvModExp(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvModExp failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_MOD_EXP_CRT: ++ DPRINTK("%s() doing MOD_EXP_CRT \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvModExpCRT(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvModExpCRT " ++ "failed (%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_DSA_SIGN: ++ DPRINTK("%s() doing DSA_SIGN \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvDsaSign(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvDsaSign " ++ "failed (%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_DSA_VERIFY: ++ DPRINTK("%s() doing DSA_VERIFY \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvDsaVerify(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvDsaVerify " ++ "failed (%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ default: ++ EPRINTK("%s(): Asymettric function not " ++ "supported (%d).\n", __FUNCTION__, krp->krp_op); ++ krp->krp_status = EOPNOTSUPP; ++ return EOPNOTSUPP; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvSwapBytes ++ * ++ * Description : This function is used to swap the byte order of a buffer. ++ * It has been seen that in general we are passed little endian byte order ++ * buffers, but LAC only accepts big endian byte order buffers. ++ */ ++static void inline icp_ocfDrvSwapBytes(u_int8_t * num, u_int32_t buff_len_bytes) ++{ ++ ++ int i; ++ u_int8_t *end_ptr; ++ u_int8_t hold_val; ++ ++ end_ptr = num + (buff_len_bytes - 1); ++ buff_len_bytes = buff_len_bytes >> 1; ++ for (i = 0; i < buff_len_bytes; i++) { ++ hold_val = *num; ++ *num = *end_ptr; ++ num++; ++ *end_ptr = hold_val; ++ end_ptr--; ++ } ++} ++ ++/* Name : icp_ocfDrvDHComputeKey ++ * ++ * Description : This function will map Diffie Hellman calls from OCF ++ * to the LAC API. OCF uses this function for Diffie Hellman Phase1 and ++ * Phase2. LAC has a separate Diffie Hellman Phase2 call, however both phases ++ * break down to a modular exponentiation. ++ */ ++static int icp_ocfDrvDHComputeKey(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ void *callbackTag = NULL; ++ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; ++ CpaFlatBuffer *pLocalOctetStringPV = NULL; ++ uint32_t dh_prime_len_bytes = 0, dh_prime_len_bits = 0; ++ ++ /* Input checks - check prime is a multiple of 8 bits to allow for ++ allocation later */ ++ dh_prime_len_bits = ++ (krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_nbits); ++ ++ /* LAC can reject prime lengths based on prime key sizes, we just ++ need to make sure we can allocate space for the base and ++ exponent buffers correctly */ ++ if ((dh_prime_len_bits % NUM_BITS_IN_BYTE) != 0) { ++ APRINTK("%s(): Warning Prime number buffer size is not a " ++ "multiple of 8 bits\n", __FUNCTION__); ++ } ++ ++ /* Result storage space should be the same size as the prime as this ++ value can take up the same amount of storage space */ ++ if (dh_prime_len_bits != ++ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits) { ++ DPRINTK("%s(): Return Buffer must be the same size " ++ "as the Prime buffer\n", __FUNCTION__); ++ krp->krp_status = EINVAL; ++ return EINVAL; ++ } ++ /* Switch to size in bytes */ ++ BITS_TO_BYTES(dh_prime_len_bytes, dh_prime_len_bits); ++ ++ callbackTag = krp; ++ ++/*All allocations are set to ICP_M_NOWAIT due to the possibility of getting ++called in interrupt context*/ ++ pPhase1OpData = icp_kmem_cache_zalloc(drvDH_zone, ICP_M_NOWAIT); ++ if (NULL == pPhase1OpData) { ++ APRINTK("%s():Failed to get memory for key gen data\n", ++ __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pLocalOctetStringPV = ++ icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pLocalOctetStringPV) { ++ APRINTK("%s():Failed to get memory for pLocalOctetStringPV\n", ++ __FUNCTION__); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /* Link parameters */ ++ pPhase1OpData->primeP.pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_p; ++ ++ pPhase1OpData->primeP.dataLenInBytes = dh_prime_len_bytes; ++ ++ icp_ocfDrvSwapBytes(pPhase1OpData->primeP.pData, dh_prime_len_bytes); ++ ++ pPhase1OpData->baseG.pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_p; ++ ++ BITS_TO_BYTES(pPhase1OpData->baseG.dataLenInBytes, ++ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pPhase1OpData->baseG.pData, ++ pPhase1OpData->baseG.dataLenInBytes); ++ ++ pPhase1OpData->privateValueX.pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX].crp_p; ++ ++ BITS_TO_BYTES(pPhase1OpData->privateValueX.dataLenInBytes, ++ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pPhase1OpData->privateValueX.pData, ++ pPhase1OpData->privateValueX.dataLenInBytes); ++ ++ /* Output parameters */ ++ pLocalOctetStringPV->pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_p; ++ ++ BITS_TO_BYTES(pLocalOctetStringPV->dataLenInBytes, ++ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits); ++ ++ lacStatus = cpaCyDhKeyGenPhase1(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvDhP1CallBack, ++ callbackTag, pPhase1OpData, ++ pLocalOctetStringPV); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): DH Phase 1 Key Gen failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvModExp ++ * ++ * Description : This function will map ordinary Modular Exponentiation calls ++ * from OCF to the LAC API. ++ * ++ */ ++static int icp_ocfDrvModExp(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ void *callbackTag = NULL; ++ CpaCyLnModExpOpData *pModExpOpData = NULL; ++ CpaFlatBuffer *pResult = NULL; ++ ++ if ((krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits % ++ NUM_BITS_IN_BYTE) != 0) { ++ DPRINTK("%s(): Warning - modulus buffer size (%d) is not a " ++ "multiple of 8 bits\n", __FUNCTION__, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. ++ crp_nbits); ++ } ++ ++ /* Result storage space should be the same size as the prime as this ++ value can take up the same amount of storage space */ ++ if (krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits > ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_nbits) { ++ APRINTK("%s(): Return Buffer size must be the same or" ++ " greater than the Modulus buffer\n", __FUNCTION__); ++ krp->krp_status = EINVAL; ++ return EINVAL; ++ } ++ ++ callbackTag = krp; ++ ++ pModExpOpData = icp_kmem_cache_zalloc(drvLnModExp_zone, ICP_M_NOWAIT); ++ if (NULL == pModExpOpData) { ++ APRINTK("%s():Failed to get memory for key gen data\n", ++ __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pResult = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pResult) { ++ APRINTK("%s():Failed to get memory for ModExp result\n", ++ __FUNCTION__); ++ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /* Link parameters */ ++ pModExpOpData->modulus.pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_p; ++ BITS_TO_BYTES(pModExpOpData->modulus.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pModExpOpData->modulus.pData, ++ pModExpOpData->modulus.dataLenInBytes); ++ ++ DPRINTK("%s : base (%d)\n", __FUNCTION__, krp-> ++ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits); ++ pModExpOpData->base.pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_p; ++ BITS_TO_BYTES(pModExpOpData->base.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(pModExpOpData->base.pData, ++ pModExpOpData->base.dataLenInBytes); ++ ++ pModExpOpData->exponent.pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX].crp_p; ++ BITS_TO_BYTES(pModExpOpData->exponent.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pModExpOpData->exponent.pData, ++ pModExpOpData->exponent.dataLenInBytes); ++ /* Output parameters */ ++ pResult->pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_p, ++ BITS_TO_BYTES(pResult->dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX]. ++ crp_nbits); ++ ++ lacStatus = cpaCyLnModExp(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvModExpCallBack, ++ callbackTag, pModExpOpData, pResult); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): Mod Exp Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ icp_ocfDrvFreeFlatBuffer(pResult); ++ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvModExpCRT ++ * ++ * Description : This function will map ordinary Modular Exponentiation Chinese ++ * Remainder Theorem implementaion calls from OCF to the LAC API. ++ * ++ * Note : Mod Exp CRT for this driver is accelerated through LAC RSA type 2 ++ * decrypt operation. Therefore P and Q input values must always be prime ++ * numbers. Although basic primality checks are done in LAC, it is up to the ++ * user to do any correct prime number checking before passing the inputs. ++ */ ++static int icp_ocfDrvModExpCRT(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ CpaCyRsaDecryptOpData *rsaDecryptOpData = NULL; ++ void *callbackTag = NULL; ++ CpaFlatBuffer *pOutputData = NULL; ++ ++ /*Parameter input checks are all done by LAC, no need to repeat ++ them here. */ ++ callbackTag = krp; ++ ++ rsaDecryptOpData = ++ icp_kmem_cache_zalloc(drvRSADecrypt_zone, ICP_M_NOWAIT); ++ if (NULL == rsaDecryptOpData) { ++ APRINTK("%s():Failed to get memory" ++ " for MOD EXP CRT Op data struct\n", __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ rsaDecryptOpData->pRecipientPrivateKey ++ = icp_kmem_cache_zalloc(drvRSAPrivateKey_zone, ICP_M_NOWAIT); ++ if (NULL == rsaDecryptOpData->pRecipientPrivateKey) { ++ APRINTK("%s():Failed to get memory for MOD EXP CRT" ++ " private key values struct\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ version = CPA_CY_RSA_VERSION_TWO_PRIME; ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; ++ ++ pOutputData = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pOutputData) { ++ APRINTK("%s():Failed to get memory" ++ " for MOD EXP CRT output data\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ rsaDecryptOpData->pRecipientPrivateKey); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ version = CPA_CY_RSA_VERSION_TWO_PRIME; ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; ++ ++ /* Link parameters */ ++ rsaDecryptOpData->inputData.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->inputData.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->inputData.pData, ++ rsaDecryptOpData->inputData.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime1P.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. ++ prime1P.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime1P.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime1P.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime2Q.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. ++ prime2Q.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime2Q.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime2Q.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent1Dp.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. ++ exponent1Dp.dataLenInBytes, ++ krp-> ++ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent1Dp.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent1Dp.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.dataLenInBytes, ++ krp-> ++ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.dataLenInBytes, ++ krp-> ++ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.dataLenInBytes); ++ ++ /* Output Parameter */ ++ pOutputData->pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX].crp_p; ++ BITS_TO_BYTES(pOutputData->dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX]. ++ crp_nbits); ++ ++ lacStatus = cpaCyRsaDecrypt(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvModExpCRTCallBack, ++ callbackTag, rsaDecryptOpData, pOutputData); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): Mod Exp CRT Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ icp_ocfDrvFreeFlatBuffer(pOutputData); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ rsaDecryptOpData->pRecipientPrivateKey); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvCheckALessThanB ++ * ++ * Description : This function will check whether the first argument is less ++ * than the second. It is used to check whether the DSA RS sign Random K ++ * value is less than the Prime Q value (as defined in the specification) ++ * ++ */ ++static int ++icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck) ++{ ++ ++ uint8_t *MSB_K = pK->pData; ++ uint8_t *MSB_Q = pQ->pData; ++ uint32_t buffer_lengths_in_bytes = pQ->dataLenInBytes; ++ ++ if (DONT_RUN_LESS_THAN_CHECK == *doCheck) { ++ return FAIL_A_IS_GREATER_THAN_B; ++ } ++ ++/*Check MSBs ++if A == B, check next MSB ++if A > B, return A_IS_GREATER_THAN_B ++if A < B, return A_IS_LESS_THAN_B (success) ++*/ ++ while (*MSB_K == *MSB_Q) { ++ MSB_K++; ++ MSB_Q++; ++ ++ buffer_lengths_in_bytes--; ++ if (0 == buffer_lengths_in_bytes) { ++ DPRINTK("%s() Buffers have equal value!!\n", ++ __FUNCTION__); ++ return FAIL_A_IS_EQUAL_TO_B; ++ } ++ ++ } ++ ++ if (*MSB_K < *MSB_Q) { ++ return SUCCESS_A_IS_LESS_THAN_B; ++ } else { ++ return FAIL_A_IS_GREATER_THAN_B; ++ } ++ ++} ++ ++/* Name : icp_ocfDrvDsaSign ++ * ++ * Description : This function will map DSA RS Sign from OCF to the LAC API. ++ * ++ * NOTE: From looking at OCF patch to OpenSSL and even the number of input ++ * parameters, OCF expects us to generate the random seed value. This value ++ * is generated and passed to LAC, however the number is discared in the ++ * callback and not returned to the user. ++ */ ++static int icp_ocfDrvDsaSign(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ CpaCyDsaRSSignOpData *dsaRsSignOpData = NULL; ++ void *callbackTag = NULL; ++ CpaCyRandGenOpData randGenOpData; ++ int primeQSizeInBytes = 0; ++ int doCheck = 0; ++ CpaFlatBuffer randData; ++ CpaBoolean protocolStatus = CPA_FALSE; ++ CpaFlatBuffer *pR = NULL; ++ CpaFlatBuffer *pS = NULL; ++ ++ callbackTag = krp; ++ ++ BITS_TO_BYTES(primeQSizeInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ ++ if (DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES != primeQSizeInBytes) { ++ APRINTK("%s(): DSA PRIME Q size not equal to the " ++ "FIPS defined 20bytes, = %d\n", ++ __FUNCTION__, primeQSizeInBytes); ++ krp->krp_status = EDOM; ++ return EDOM; ++ } ++ ++ dsaRsSignOpData = ++ icp_kmem_cache_zalloc(drvDSARSSign_zone, ICP_M_NOWAIT); ++ if (NULL == dsaRsSignOpData) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA RS Sign Op data struct\n", __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ dsaRsSignOpData->K.pData = ++ icp_kmem_cache_alloc(drvDSARSSignKValue_zone, ICP_M_NOWAIT); ++ ++ if (NULL == dsaRsSignOpData->K.pData) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA RS Sign Op Random value\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pR = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pR) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA signature R\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pS = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pS) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA signature S\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /*link prime number parameter for ease of processing */ ++ dsaRsSignOpData->P.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->P.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->P.pData, ++ dsaRsSignOpData->P.dataLenInBytes); ++ ++ dsaRsSignOpData->Q.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->Q.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->Q.pData, ++ dsaRsSignOpData->Q.dataLenInBytes); ++ ++ /*generate random number with equal buffer size to Prime value Q, ++ but value less than Q */ ++ dsaRsSignOpData->K.dataLenInBytes = dsaRsSignOpData->Q.dataLenInBytes; ++ ++ randGenOpData.generateBits = CPA_TRUE; ++ randGenOpData.lenInBytes = dsaRsSignOpData->K.dataLenInBytes; ++ ++ icp_ocfDrvPtrAndLenToFlatBuffer(dsaRsSignOpData->K.pData, ++ dsaRsSignOpData->K.dataLenInBytes, ++ &randData); ++ ++ doCheck = 0; ++ while (icp_ocfDrvCheckALessThanB(&(dsaRsSignOpData->K), ++ &(dsaRsSignOpData->Q), &doCheck)) { ++ ++ if (CPA_STATUS_SUCCESS ++ != cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, ++ NULL, NULL, &randGenOpData, &randData)) { ++ APRINTK("%s(): ERROR - Failed to generate DSA RS Sign K" ++ "value\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = EAGAIN; ++ return EAGAIN; ++ } ++ ++ doCheck++; ++ if (DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS == doCheck) { ++ APRINTK("%s(): ERROR - Failed to find DSA RS Sign K " ++ "value less than Q value\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = EAGAIN; ++ return EAGAIN; ++ } ++ ++ } ++ /*Rand Data - no need to swap bytes for pK */ ++ ++ /* Link parameters */ ++ dsaRsSignOpData->G.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->G.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_nbits); ++ ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->G.pData, ++ dsaRsSignOpData->G.dataLenInBytes); ++ ++ dsaRsSignOpData->X.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->X.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_nbits); ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->X.pData, ++ dsaRsSignOpData->X.dataLenInBytes); ++ ++ /*OpenSSL dgst parameter is left in big endian byte order, ++ therefore no byte swap is required */ ++ dsaRsSignOpData->M.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->M.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX]. ++ crp_nbits); ++ ++ /* Output Parameters */ ++ pS->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX].crp_p; ++ BITS_TO_BYTES(pS->dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX]. ++ crp_nbits); ++ ++ pR->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX].crp_p; ++ BITS_TO_BYTES(pR->dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX]. ++ crp_nbits); ++ ++ lacStatus = cpaCyDsaSignRS(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvDsaRSSignCallBack, ++ callbackTag, dsaRsSignOpData, ++ &protocolStatus, pR, pS); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): DSA RS Sign Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ icp_ocfDrvFreeFlatBuffer(pS); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvDsaVerify ++ * ++ * Description : This function will map DSA RS Verify from OCF to the LAC API. ++ * ++ */ ++static int icp_ocfDrvDsaVerify(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ CpaCyDsaVerifyOpData *dsaVerifyOpData = NULL; ++ void *callbackTag = NULL; ++ CpaBoolean verifyStatus = CPA_FALSE; ++ ++ callbackTag = krp; ++ ++ dsaVerifyOpData = ++ icp_kmem_cache_zalloc(drvDSAVerify_zone, ICP_M_NOWAIT); ++ if (NULL == dsaVerifyOpData) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA Verify Op data struct\n", __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /* Link parameters */ ++ dsaVerifyOpData->P.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->P.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->P.pData, ++ dsaVerifyOpData->P.dataLenInBytes); ++ ++ dsaVerifyOpData->Q.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->Q.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->Q.pData, ++ dsaVerifyOpData->Q.dataLenInBytes); ++ ++ dsaVerifyOpData->G.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->G.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->G.pData, ++ dsaVerifyOpData->G.dataLenInBytes); ++ ++ dsaVerifyOpData->Y.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->Y.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->Y.pData, ++ dsaVerifyOpData->Y.dataLenInBytes); ++ ++ /*OpenSSL dgst parameter is left in big endian byte order, ++ therefore no byte swap is required */ ++ dsaVerifyOpData->M.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->M.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX]. ++ crp_nbits); ++ ++ dsaVerifyOpData->R.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->R.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->R.pData, ++ dsaVerifyOpData->R.dataLenInBytes); ++ ++ dsaVerifyOpData->S.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->S.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->S.pData, ++ dsaVerifyOpData->S.dataLenInBytes); ++ ++ lacStatus = cpaCyDsaVerify(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvDsaVerifyCallBack, ++ callbackTag, dsaVerifyOpData, &verifyStatus); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): DSA Verify Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ ICP_CACHE_FREE(drvDSAVerify_zone, dsaVerifyOpData); ++ krp->krp_status = ECANCELED; ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvDhP1Callback ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the DH operation. ++ */ ++static void ++icp_ocfDrvDhP1CallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pPhase1OpData = (CpaCyDhPhase1KeyGenOpData *) pOpData; ++ ++ if (NULL == pLocalOctetStringPV) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "pLocalOctetStringPV Data is NULL\n", __FUNCTION__); ++ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ } else { ++ APRINTK("%s(): Diffie Hellman Phase1 Key Gen failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } ++ ++ icp_ocfDrvSwapBytes(pLocalOctetStringPV->pData, ++ pLocalOctetStringPV->dataLenInBytes); ++ ++ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); ++ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ ++ crypto_kdone(krp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvModExpCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the Mod Exp operation. ++ */ ++static void ++icp_ocfDrvModExpCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpdata, CpaFlatBuffer * pResult) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyLnModExpOpData *pLnModExpOpData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpdata) { ++ DPRINTK("%s(): Invalid Mod Exp input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pLnModExpOpData = (CpaCyLnModExpOpData *) pOpdata; ++ ++ if (NULL == pResult) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "pResult data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); ++ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ } else { ++ APRINTK("%s(): LAC Mod Exp Operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } ++ ++ icp_ocfDrvSwapBytes(pResult->pData, pResult->dataLenInBytes); ++ ++ /*switch base size value back to original */ ++ if (pLnModExpOpData->base.pData == ++ (uint8_t *) & (krp-> ++ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. ++ crp_nbits)) { ++ *((uint32_t *) pLnModExpOpData->base.pData) = ++ ntohl(*((uint32_t *) pLnModExpOpData->base.pData)); ++ } ++ icp_ocfDrvFreeFlatBuffer(pResult); ++ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); ++ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); ++ ++ crypto_kdone(krp); ++ ++ return; ++ ++} ++ ++/* Name : icp_ocfDrvModExpCRTCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the Mod Exp CRT operation. ++ */ ++static void ++icp_ocfDrvModExpCRTCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pOutputData) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyRsaDecryptOpData *pDecryptData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pDecryptData = (CpaCyRsaDecryptOpData *) pOpData; ++ ++ if (NULL == pOutputData) { ++ DPRINTK("%s(): Invalid input parameter - " ++ "pOutputData is NULL\n", __FUNCTION__); ++ memset(pDecryptData->pRecipientPrivateKey, 0, ++ sizeof(CpaCyRsaPrivateKey)); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ pDecryptData->pRecipientPrivateKey); ++ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ } else { ++ APRINTK("%s(): LAC Mod Exp CRT operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } ++ ++ icp_ocfDrvSwapBytes(pOutputData->pData, pOutputData->dataLenInBytes); ++ ++ icp_ocfDrvFreeFlatBuffer(pOutputData); ++ memset(pDecryptData->pRecipientPrivateKey, 0, ++ sizeof(CpaCyRsaPrivateKey)); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ pDecryptData->pRecipientPrivateKey); ++ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); ++ ++ crypto_kdone(krp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvDsaRSSignCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the DSA RS sign operation. ++ */ ++static void ++icp_ocfDrvDsaRSSignCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, ++ CpaBoolean protocolStatus, ++ CpaFlatBuffer * pR, CpaFlatBuffer * pS) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyDsaRSSignOpData *pSignData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pSignData = (CpaCyDsaRSSignOpData *) pOpData; ++ ++ if (NULL == pR) { ++ DPRINTK("%s(): Invalid input parameter - " ++ "pR sign is NULL\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (NULL == pS) { ++ DPRINTK("%s(): Invalid input parameter - " ++ "pS sign is NULL\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS != status) { ++ APRINTK("%s(): LAC DSA RS Sign operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } else { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ ++ if (CPA_TRUE != protocolStatus) { ++ DPRINTK("%s(): LAC DSA RS Sign operation failed due " ++ "to protocol error\n", __FUNCTION__); ++ krp->krp_status = EIO; ++ } ++ } ++ ++ /* Swap bytes only when the callback status is successful and ++ protocolStatus is set to true */ ++ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == protocolStatus) { ++ icp_ocfDrvSwapBytes(pR->pData, pR->dataLenInBytes); ++ icp_ocfDrvSwapBytes(pS->pData, pS->dataLenInBytes); ++ } ++ ++ icp_ocfDrvFreeFlatBuffer(pR); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ memset(pSignData->K.pData, 0, pSignData->K.dataLenInBytes); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, pSignData->K.pData); ++ memset(pSignData, 0, sizeof(CpaCyDsaRSSignOpData)); ++ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); ++ crypto_kdone(krp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvDsaVerifyCallback ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the DSA Verify operation. ++ */ ++static void ++icp_ocfDrvDsaVerifyCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaBoolean verifyStatus) ++{ ++ ++ struct cryptkop *krp = NULL; ++ CpaCyDsaVerifyOpData *pVerData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pVerData = (CpaCyDsaVerifyOpData *) pOpData; ++ ++ if (CPA_STATUS_SUCCESS != status) { ++ APRINTK("%s(): LAC DSA Verify operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } else { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ ++ if (CPA_TRUE != verifyStatus) { ++ DPRINTK("%s(): DSA signature invalid\n", __FUNCTION__); ++ krp->krp_status = EIO; ++ } ++ } ++ ++ /* Swap bytes only when the callback status is successful and ++ verifyStatus is set to true */ ++ /*Just swapping back the key values for now. Possibly all ++ swapped buffers need to be reverted */ ++ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == verifyStatus) { ++ icp_ocfDrvSwapBytes(pVerData->R.pData, ++ pVerData->R.dataLenInBytes); ++ icp_ocfDrvSwapBytes(pVerData->S.pData, ++ pVerData->S.dataLenInBytes); ++ } ++ ++ memset(pVerData, 0, sizeof(CpaCyDsaVerifyOpData)); ++ ICP_CACHE_FREE(drvDSAVerify_zone, pVerData); ++ crypto_kdone(krp); ++ ++ return; ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/ep80579/icp_common.c linux-2.6.39/crypto/ocf/ep80579/icp_common.c +--- linux-2.6.39.orig/crypto/ocf/ep80579/icp_common.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/ep80579/icp_common.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,773 @@ ++/************************************************************************* ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++ ++/* ++ * An OCF module that uses Intel® QuickAssist Integrated Accelerator to do the ++ * crypto. ++ * ++ * This driver requires the ICP Access Library that is available from Intel in ++ * order to operate. ++ */ ++ ++#include "icp_ocf.h" ++ ++#define ICP_OCF_COMP_NAME "ICP_OCF" ++#define ICP_OCF_VER_MAIN (2) ++#define ICP_OCF_VER_MJR (1) ++#define ICP_OCF_VER_MNR (0) ++ ++#define MAX_DEREG_RETRIES (100) ++#define DEFAULT_DEREG_RETRIES (10) ++#define DEFAULT_DEREG_DELAY_IN_JIFFIES (10) ++ ++/* This defines the maximum number of sessions possible between OCF ++ and the OCF EP80579 Driver. If set to zero, there is no limit. */ ++#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0) ++#define NUM_SUPPORTED_CAPABILITIES (21) ++ ++/*Slab zone names*/ ++#define ICP_SESSION_DATA_NAME "icp_ocf.SesDat" ++#define ICP_OP_DATA_NAME "icp_ocf.OpDat" ++#define ICP_DH_NAME "icp_ocf.DH" ++#define ICP_MODEXP_NAME "icp_ocf.ModExp" ++#define ICP_RSA_DECRYPT_NAME "icp_ocf.RSAdec" ++#define ICP_RSA_PKEY_NAME "icp_ocf.RSApk" ++#define ICP_DSA_SIGN_NAME "icp_ocf.DSAsg" ++#define ICP_DSA_VER_NAME "icp_ocf.DSAver" ++#define ICP_RAND_VAL_NAME "icp_ocf.DSArnd" ++#define ICP_FLAT_BUFF_NAME "icp_ocf.FB" ++ ++/*Slabs zones*/ ++icp_kmem_cache drvSessionData_zone = NULL; ++icp_kmem_cache drvOpData_zone = NULL; ++icp_kmem_cache drvDH_zone = NULL; ++icp_kmem_cache drvLnModExp_zone = NULL; ++icp_kmem_cache drvRSADecrypt_zone = NULL; ++icp_kmem_cache drvRSAPrivateKey_zone = NULL; ++icp_kmem_cache drvDSARSSign_zone = NULL; ++icp_kmem_cache drvDSARSSignKValue_zone = NULL; ++icp_kmem_cache drvDSAVerify_zone = NULL; ++ ++/*Slab zones for flatbuffers and bufferlist*/ ++icp_kmem_cache drvFlatBuffer_zone = NULL; ++ ++static inline int icp_cache_null_check(void) ++{ ++ return (drvSessionData_zone && drvOpData_zone ++ && drvDH_zone && drvLnModExp_zone && drvRSADecrypt_zone ++ && drvRSAPrivateKey_zone && drvDSARSSign_zone ++ && drvDSARSSign_zone && drvDSARSSignKValue_zone ++ && drvDSAVerify_zone && drvFlatBuffer_zone); ++} ++ ++/*Function to free all allocated slab caches before exiting the module*/ ++static void icp_ocfDrvFreeCaches(void); ++ ++int32_t icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ ++/* Module parameter - gives the number of times LAC deregistration shall be ++ re-tried */ ++int num_dereg_retries = DEFAULT_DEREG_RETRIES; ++ ++/* Module parameter - gives the delay time in jiffies before a LAC session ++ shall be attempted to be deregistered again */ ++int dereg_retry_delay_in_jiffies = DEFAULT_DEREG_DELAY_IN_JIFFIES; ++ ++/* Module parameter - gives the maximum number of sessions possible between ++ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ ++int max_sessions = DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT; ++ ++/* This is set when the module is removed from the system, no further ++ processing can take place if this is set */ ++icp_atomic_t icp_ocfDrvIsExiting = ICP_ATOMIC_INIT(0); ++ ++/* This is used to show how many lac sessions were not deregistered*/ ++icp_atomic_t lac_session_failed_dereg_count = ICP_ATOMIC_INIT(0); ++ ++/* This is used to track the number of registered sessions between OCF and ++ * and the OCF EP80579 driver, when max_session is set to value other than ++ * zero. This ensures that the max_session set for the OCF and the driver ++ * is equal to the LAC registered sessions */ ++icp_atomic_t num_ocf_to_drv_registered_sessions = ICP_ATOMIC_INIT(0); ++ ++/* Head of linked list used to store session data */ ++icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; ++icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; ++ ++icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; ++ ++/*Below pointer is only used in linux, FreeBSD uses the name to ++create its own variable name*/ ++icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ = NULL; ++ICP_WORKQUEUE_DEFINE_THREAD(icp_ocfDrvFreeLacSessionWorkQ); ++ ++struct icp_drvBuffListInfo defBuffListInfo; ++ ++/* Name : icp_ocfDrvInit ++ * ++ * Description : This function will register all the symmetric and asymmetric ++ * functionality that will be accelerated by the hardware. It will also ++ * get a unique driver ID from the OCF and initialise all slab caches ++ */ ++ICP_MODULE_INIT_FUNC(icp_ocfDrvInit) ++{ ++ int ocfStatus = 0; ++ ++ IPRINTK("=== %s ver %d.%d.%d ===\n", ICP_OCF_COMP_NAME, ++ ICP_OCF_VER_MAIN, ICP_OCF_VER_MJR, ICP_OCF_VER_MNR); ++ ++ if (MAX_DEREG_RETRIES < num_dereg_retries) { ++ EPRINTK("Session deregistration retry count set to greater " ++ "than %d", MAX_DEREG_RETRIES); ++ icp_module_return_code(EINVAL); ++ } ++ ++ /* Initialize and Start the Cryptographic component */ ++ if (CPA_STATUS_SUCCESS != ++ cpaCyStartInstance(CPA_INSTANCE_HANDLE_SINGLE)) { ++ EPRINTK("Failed to initialize and start the instance " ++ "of the Cryptographic component.\n"); ++ return icp_module_return_code(EINVAL); ++ } ++ ++ icp_spin_lock_init(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ /* Set the default size of BufferList to allocate */ ++ memset(&defBuffListInfo, 0, sizeof(struct icp_drvBuffListInfo)); ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvBufferListMemInfo(ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS, ++ &defBuffListInfo)) { ++ EPRINTK("Failed to get bufferlist memory info.\n"); ++ return icp_module_return_code(ENOMEM); ++ } ++ ++ /*Register OCF EP80579 Driver with OCF */ ++ icp_ocfDrvDriverId = ICP_CRYPTO_GET_DRIVERID(); ++ ++ if (icp_ocfDrvDriverId < 0) { ++ EPRINTK("%s : ICP driver failed to register with OCF!\n", ++ __FUNCTION__); ++ return icp_module_return_code(ENODEV); ++ } ++ ++ /*Create all the slab caches used by the OCF EP80579 Driver */ ++ drvSessionData_zone = ++ ICP_CACHE_CREATE(ICP_SESSION_DATA_NAME, struct icp_drvSessionData); ++ ++ /* ++ * Allocation of the OpData includes the allocation space for meta data. ++ * The memory after the opData structure is reserved for this meta data. ++ */ ++ drvOpData_zone = ++ icp_kmem_cache_create(ICP_OP_DATA_NAME, ++ sizeof(struct icp_drvOpData) + ++ defBuffListInfo.metaSize, ++ ICP_KERNEL_CACHE_ALIGN, ++ ICP_KERNEL_CACHE_NOINIT); ++ ++ drvDH_zone = ICP_CACHE_CREATE(ICP_DH_NAME, CpaCyDhPhase1KeyGenOpData); ++ ++ drvLnModExp_zone = ++ ICP_CACHE_CREATE(ICP_MODEXP_NAME, CpaCyLnModExpOpData); ++ ++ drvRSADecrypt_zone = ++ ICP_CACHE_CREATE(ICP_RSA_DECRYPT_NAME, CpaCyRsaDecryptOpData); ++ ++ drvRSAPrivateKey_zone = ++ ICP_CACHE_CREATE(ICP_RSA_PKEY_NAME, CpaCyRsaPrivateKey); ++ ++ drvDSARSSign_zone = ++ ICP_CACHE_CREATE(ICP_DSA_SIGN_NAME, CpaCyDsaRSSignOpData); ++ ++ /*too awkward to use a macro here */ ++ drvDSARSSignKValue_zone = ++ ICP_CACHE_CREATE(ICP_RAND_VAL_NAME, ++ DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES); ++ ++ drvDSAVerify_zone = ++ ICP_CACHE_CREATE(ICP_DSA_VER_NAME, CpaCyDsaVerifyOpData); ++ ++ drvFlatBuffer_zone = ++ ICP_CACHE_CREATE(ICP_FLAT_BUFF_NAME, CpaFlatBuffer); ++ ++ if (0 == icp_cache_null_check()) { ++ icp_ocfDrvFreeCaches(); ++ EPRINTK("%s() line %d: Not enough memory!\n", ++ __FUNCTION__, __LINE__); ++ return ENOMEM; ++ } ++ ++ /* Register the ICP symmetric crypto support. */ ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_NULL_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_DES_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_3DES_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_AES_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_ARC4, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5_HMAC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1_HMAC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256_HMAC, ++ ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384_HMAC, ++ ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512_HMAC, ++ ocfStatus); ++ ++ /* Register the ICP asymmetric algorithm support */ ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DH_COMPUTE_KEY, ++ ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP, ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP_CRT, ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_SIGN, ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_VERIFY, ocfStatus); ++ ++ /* Register the ICP random number generator support */ ++ ICP_REG_RAND_WITH_OCF(icp_ocfDrvDriverId, ++ icp_ocfDrvReadRandom, NULL, ocfStatus); ++ ++ if (OCF_ZERO_FUNCTIONALITY_REGISTERED == ocfStatus) { ++ DPRINTK("%s: Failed to register any device capabilities\n", ++ __FUNCTION__); ++ icp_ocfDrvFreeCaches(); ++ icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ return icp_module_return_code(ECANCELED); ++ } ++ ++ DPRINTK("%s: Registered %d of %d device capabilities\n", ++ __FUNCTION__, ocfStatus, NUM_SUPPORTED_CAPABILITIES); ++ ++ /*Session data linked list used during module exit */ ++ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead); ++ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList); ++ ++ ICP_WORKQUEUE_CREATE(icp_ocfDrvFreeLacSessionWorkQ, "icpwq"); ++ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { ++ EPRINTK("%s: Failed to create single " ++ "thread workqueue\n", __FUNCTION__); ++ icp_ocfDrvFreeCaches(); ++ icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ return icp_module_return_code(ENOMEM); ++ } ++ ++ return icp_module_return_code(0); ++} ++ ++/* Name : icp_ocfDrvExit ++ * ++ * Description : This function will deregister all the symmetric sessions ++ * registered with the LAC component. It will also deregister all symmetric ++ * and asymmetric functionality that can be accelerated by the hardware via OCF ++ * and random number generation if it is enabled. ++ */ ++ICP_MODULE_EXIT_FUNC(icp_ocfDrvExit) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ struct icp_drvSessionData *sessionData = NULL; ++ struct icp_drvSessionData *tempSessionData = NULL; ++ int i, remaining_delay_time_in_jiffies = 0; ++ ++ /* For FreeBSD the invariant macro below makes function to return */ ++ /* with EBUSY value in the case of any session which has been regi- */ ++ /* stered with LAC not being deregistered. */ ++ /* The Linux implementation is empty since it is purely to compensate */ ++ /* for a limitation of the FreeBSD 7.1 Opencrypto framework. */ ++ ++ ICP_MODULE_EXIT_INV(); ++ ++ /* There is a possibility of a process or new session command being */ ++ /* sent before this variable is incremented. The aim of this variable */ ++ /* is to stop a loop of calls creating a deadlock situation which */ ++ /* would prevent the driver from exiting. */ ++ icp_atomic_set(&icp_ocfDrvIsExiting, 1); ++ ++ /*Existing sessions will be routed to another driver after these calls */ ++ crypto_unregister_all(icp_ocfDrvDriverId); ++ crypto_runregister_all(icp_ocfDrvDriverId); ++ ++ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { ++ DPRINTK("%s: workqueue already " ++ "destroyed, therefore module exit " ++ " function already called. Exiting.\n", __FUNCTION__); ++ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; ++ } ++ /*If any sessions are waiting to be deregistered, do that. This also ++ flushes the work queue */ ++ ICP_WORKQUEUE_DESTROY(icp_ocfDrvFreeLacSessionWorkQ); ++ ++ /*ENTER CRITICAL SECTION */ ++ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, ++ &icp_ocfDrvGlobalSymListHead, listNode) { ++ for (i = 0; i < num_dereg_retries; i++) { ++ /*No harm if bad input - LAC will handle error cases */ ++ if (ICP_SESSION_RUNNING == tempSessionData->inUse) { ++ lacStatus = ++ cpaCySymRemoveSession ++ (CPA_INSTANCE_HANDLE_SINGLE, ++ tempSessionData->sessHandle); ++ if (CPA_STATUS_SUCCESS == lacStatus) { ++ /* Succesfully deregistered */ ++ break; ++ } else if (CPA_STATUS_RETRY != lacStatus) { ++ icp_atomic_inc ++ (&lac_session_failed_dereg_count); ++ break; ++ } ++ ++ /*schedule_timout returns the time left for completion if ++ * this task is set to TASK_INTERRUPTIBLE */ ++ remaining_delay_time_in_jiffies = ++ dereg_retry_delay_in_jiffies; ++ while (0 > remaining_delay_time_in_jiffies) { ++ remaining_delay_time_in_jiffies = ++ icp_schedule_timeout ++ (&icp_ocfDrvSymSessInfoListSpinlock, ++ remaining_delay_time_in_jiffies); ++ } ++ ++ DPRINTK ++ ("%s(): Retry %d to deregistrate the session\n", ++ __FUNCTION__, i); ++ } ++ } ++ ++ /*remove from current list */ ++ ICP_LIST_DEL(tempSessionData, listNode); ++ /*add to free mem linked list */ ++ ICP_LIST_ADD(tempSessionData, ++ &icp_ocfDrvGlobalSymListHead_FreeMemList, ++ listNode); ++ ++ } ++ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ /*set back to initial values */ ++ sessionData = NULL; ++ /*still have a reference in our list! */ ++ tempSessionData = NULL; ++ /*free memory */ ++ ++ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, ++ &icp_ocfDrvGlobalSymListHead_FreeMemList, ++ listNode) { ++ ++ ICP_LIST_DEL(tempSessionData, listNode); ++ /* Free allocated CpaCySymSessionCtx */ ++ if (NULL != tempSessionData->sessHandle) { ++ icp_kfree(tempSessionData->sessHandle); ++ } ++ memset(tempSessionData, 0, sizeof(struct icp_drvSessionData)); ++ ICP_CACHE_FREE(drvSessionData_zone, tempSessionData); ++ } ++ ++ if (0 != icp_atomic_read(&lac_session_failed_dereg_count)) { ++ DPRINTK("%s(): %d LAC sessions were not deregistered " ++ "correctly. This is not a clean exit! \n", ++ __FUNCTION__, ++ icp_atomic_read(&lac_session_failed_dereg_count)); ++ } ++ ++ icp_ocfDrvFreeCaches(); ++ icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ ++ icp_spin_lock_destroy(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ /* Shutdown the Cryptographic component */ ++ lacStatus = cpaCyStopInstance(CPA_INSTANCE_HANDLE_SINGLE); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ DPRINTK("%s(): Failed to stop instance of the " ++ "Cryptographic component.(status == %d)\n", ++ __FUNCTION__, lacStatus); ++ } ++ ++ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; ++} ++ ++/* Name : icp_ocfDrvFreeCaches ++ * ++ * Description : This function deregisters all slab caches ++ */ ++static void icp_ocfDrvFreeCaches(void) ++{ ++ icp_atomic_set(&icp_ocfDrvIsExiting, 1); ++ ++ /*Sym Zones */ ++ ICP_CACHE_DESTROY(drvSessionData_zone); ++ ICP_CACHE_DESTROY(drvOpData_zone); ++ ++ /*Asym zones */ ++ ICP_CACHE_DESTROY(drvDH_zone); ++ ICP_CACHE_DESTROY(drvLnModExp_zone); ++ ICP_CACHE_DESTROY(drvRSADecrypt_zone); ++ ICP_CACHE_DESTROY(drvRSAPrivateKey_zone); ++ ICP_CACHE_DESTROY(drvDSARSSignKValue_zone); ++ ICP_CACHE_DESTROY(drvDSARSSign_zone); ++ ICP_CACHE_DESTROY(drvDSAVerify_zone); ++ ++ /*FlatBuffer and BufferList Zones */ ++ ICP_CACHE_DESTROY(drvFlatBuffer_zone); ++ ++} ++ ++/* Name : icp_ocfDrvDeregRetry ++ * ++ * Description : This function will try to farm the session deregistration ++ * off to a work queue. If it fails, nothing more can be done and it ++ * returns an error ++ */ ++int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister) ++{ ++ struct icp_ocfDrvFreeLacSession *workstore = NULL; ++ ++ DPRINTK("%s(): Retry - Deregistering session (%p)\n", ++ __FUNCTION__, sessionToDeregister); ++ ++ /*make sure the session is not available to be allocated during this ++ process */ ++ icp_atomic_inc(&lac_session_failed_dereg_count); ++ ++ /*Farm off to work queue */ ++ workstore = ++ icp_kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), ICP_M_NOWAIT); ++ if (NULL == workstore) { ++ DPRINTK("%s(): unable to free session - no memory available " ++ "for work queue\n", __FUNCTION__); ++ return ENOMEM; ++ } ++ ++ workstore->sessionToDeregister = sessionToDeregister; ++ ++ icp_init_work(&(workstore->work), ++ icp_ocfDrvDeferedFreeLacSessionTaskFn, workstore); ++ ++ ICP_WORKQUEUE_ENQUEUE(icp_ocfDrvFreeLacSessionWorkQ, ++ &(workstore->work)); ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++ ++} ++ ++/* Name : icp_ocfDrvDeferedFreeLacSessionProcess ++ * ++ * Description : This function will retry (module input parameter) ++ * 'num_dereg_retries' times to deregister any symmetric session that recieves a ++ * CPA_STATUS_RETRY message from the LAC component. This function is run in ++ * Thread context because it is called from a worker thread ++ */ ++void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg) ++{ ++ struct icp_ocfDrvFreeLacSession *workstore = NULL; ++ CpaCySymSessionCtx sessionToDeregister = NULL; ++ int i = 0; ++ int remaining_delay_time_in_jiffies = 0; ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ ++ workstore = (struct icp_ocfDrvFreeLacSession *)arg; ++ if (NULL == workstore) { ++ DPRINTK("%s() function called with null parameter \n", ++ __FUNCTION__); ++ return; ++ } ++ ++ sessionToDeregister = workstore->sessionToDeregister; ++ icp_kfree(workstore); ++ ++ /*if exiting, give deregistration one more blast only */ ++ if (icp_atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) { ++ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, ++ sessionToDeregister); ++ ++ if (lacStatus != CPA_STATUS_SUCCESS) { ++ DPRINTK("%s() Failed to Dereg LAC session %p " ++ "during module exit\n", __FUNCTION__, ++ sessionToDeregister); ++ return; ++ } ++ ++ icp_atomic_dec(&lac_session_failed_dereg_count); ++ return; ++ } ++ ++ for (i = 0; i <= num_dereg_retries; i++) { ++ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, ++ sessionToDeregister); ++ ++ if (lacStatus == CPA_STATUS_SUCCESS) { ++ icp_atomic_dec(&lac_session_failed_dereg_count); ++ return; ++ } ++ if (lacStatus != CPA_STATUS_RETRY) { ++ DPRINTK("%s() Failed to deregister session - lacStatus " ++ " = %d", __FUNCTION__, lacStatus); ++ break; ++ } ++ ++ /*schedule_timout returns the time left for completion if this ++ task is set to TASK_INTERRUPTIBLE */ ++ remaining_delay_time_in_jiffies = dereg_retry_delay_in_jiffies; ++ while (0 < remaining_delay_time_in_jiffies) { ++ remaining_delay_time_in_jiffies = ++ icp_schedule_timeout(NULL, ++ remaining_delay_time_in_jiffies); ++ } ++ ++ } ++ ++ DPRINTK("%s(): Unable to deregister session\n", __FUNCTION__); ++ DPRINTK("%s(): Number of unavailable LAC sessions = %d\n", __FUNCTION__, ++ icp_atomic_read(&lac_session_failed_dereg_count)); ++} ++ ++/* Name : icp_ocfDrvPtrAndLenToFlatBuffer ++ * ++ * Description : This function converts a "pointer and length" buffer ++ * structure to Fredericksburg Flat Buffer (CpaFlatBuffer) format. ++ * ++ * This function assumes that the data passed in are valid. ++ */ ++inline void ++icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, ++ CpaFlatBuffer * pFlatBuffer) ++{ ++ pFlatBuffer->pData = pData; ++ pFlatBuffer->dataLenInBytes = len; ++} ++ ++/* Name : icp_ocfDrvPtrAndLenToBufferList ++ * ++ * Description : This function converts a "pointer and length" buffer ++ * structure to Fredericksburg Scatter/Gather Buffer (CpaBufferList) format. ++ * ++ * This function assumes that the data passed in are valid. ++ */ ++inline void ++icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, ++ CpaBufferList * pBufferList) ++{ ++ pBufferList->numBuffers = 1; ++ pBufferList->pBuffers->pData = pDataIn; ++ pBufferList->pBuffers->dataLenInBytes = length; ++} ++ ++/* Name : icp_ocfDrvBufferListToPtrAndLen ++ * ++ * Description : This function converts Fredericksburg Scatter/Gather Buffer ++ * (CpaBufferList) format to a "pointer and length" buffer structure. ++ * ++ * This function assumes that the data passed in are valid. ++ */ ++inline void ++icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, ++ void **ppDataOut, uint32_t * pLength) ++{ ++ *ppDataOut = pBufferList->pBuffers->pData; ++ *pLength = pBufferList->pBuffers->dataLenInBytes; ++} ++ ++/* Name : icp_ocfDrvBufferListMemInfo ++ * ++ * Description : This function will set the number of flat buffers in ++ * bufferlist, the size of memory to allocate for the pPrivateMetaData ++ * member of the CpaBufferList. ++ */ ++int ++icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, ++ struct icp_drvBuffListInfo *buffListInfo) ++{ ++ buffListInfo->numBuffers = numBuffers; ++ ++ if (CPA_STATUS_SUCCESS != ++ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, ++ buffListInfo->numBuffers, ++ &(buffListInfo->metaSize))) { ++ EPRINTK("%s() Failed to get buffer list meta size.\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvFreeFlatBuffer ++ * ++ * Description : This function will deallocate flat buffer. ++ */ ++inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer) ++{ ++ if (pFlatBuffer != NULL) { ++ memset(pFlatBuffer, 0, sizeof(CpaFlatBuffer)); ++ ICP_CACHE_FREE(drvFlatBuffer_zone, pFlatBuffer); ++ } ++} ++ ++/* Name : icp_ocfDrvAllocMetaData ++ * ++ * Description : This function will allocate memory for the ++ * pPrivateMetaData member of CpaBufferList. ++ */ ++inline int ++icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, ++ struct icp_drvOpData *pOpData) ++{ ++ Cpa32U metaSize = 0; ++ ++ if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { ++ uint8_t *pOpDataStartAddr = (uint8_t *) pOpData; ++ ++ if (0 == defBuffListInfo.metaSize) { ++ pBufferList->pPrivateMetaData = NULL; ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++ } ++ /* ++ * The meta data allocation has been included as part of the ++ * op data. It has been pre-allocated in memory just after the ++ * icp_drvOpData structure. ++ */ ++ pBufferList->pPrivateMetaData = (void *)(pOpDataStartAddr + ++ sizeof(struct ++ icp_drvOpData)); ++ } else { ++ if (CPA_STATUS_SUCCESS != ++ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, ++ pBufferList->numBuffers, ++ &metaSize)) { ++ EPRINTK("%s() Failed to get buffer list meta size.\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ if (0 == metaSize) { ++ pBufferList->pPrivateMetaData = NULL; ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++ } ++ ++ pBufferList->pPrivateMetaData = ++ icp_kmalloc(metaSize, ICP_M_NOWAIT); ++ } ++ if (NULL == pBufferList->pPrivateMetaData) { ++ EPRINTK("%s() Failed to allocate pPrivateMetaData.\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvFreeMetaData ++ * ++ * Description : This function will deallocate pPrivateMetaData memory. ++ */ ++inline void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList) ++{ ++ if (NULL == pBufferList->pPrivateMetaData) { ++ return; ++ } ++ ++ /* ++ * Only free the meta data if the BufferList has more than ++ * ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS number of buffers. ++ * Otherwise, the meta data shall be freed when the icp_drvOpData is ++ * freed. ++ */ ++ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers) { ++ icp_kfree(pBufferList->pPrivateMetaData); ++ } ++} ++ ++/* Module declaration, init and exit functions */ ++ICP_DECLARE_MODULE(icp_ocf, icp_ocfDrvInit, icp_ocfDrvExit); ++ICP_MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration"); ++ICP_MODULE_VERSION(icp_ocf, ICP_OCF_VER_MJR); ++ICP_MODULE_LICENSE("Dual BSD/GPL"); ++ICP_MODULE_AUTHOR("Intel"); ++ ++/* Module parameters */ ++ICP_MODULE_PARAM_INT(icp_ocf, num_dereg_retries, ++ "Number of times to retry LAC Sym Session Deregistration. " ++ "Default 10, Max 100"); ++ICP_MODULE_PARAM_INT(icp_ocf, dereg_retry_delay_in_jiffies, "Delay in jiffies " ++ "(added to a schedule() function call) before a LAC Sym " ++ "Session Dereg is retried. Default 10"); ++ICP_MODULE_PARAM_INT(icp_ocf, max_sessions, ++ "This sets the maximum number of sessions " ++ "between OCF and this driver. If this value is set to zero," ++ "max session count checking is disabled. Default is zero(0)"); ++ ++/* Module dependencies */ ++#define MODULE_MIN_VER 1 ++#define CRYPTO_MAX_VER 3 ++#define LAC_MAX_VER 2 ++ ++ICP_MODULE_DEPEND(icp_ocf, crypto, MODULE_MIN_VER, MODULE_MIN_VER, ++ CRYPTO_MAX_VER); ++ICP_MODULE_DEPEND(icp_ocf, cryptodev, MODULE_MIN_VER, MODULE_MIN_VER, ++ CRYPTO_MAX_VER); ++ICP_MODULE_DEPEND(icp_ocf, icp_crypto, MODULE_MIN_VER, MODULE_MIN_VER, ++ LAC_MAX_VER); +diff -Nur linux-2.6.39.orig/crypto/ocf/ep80579/icp_ocf.h linux-2.6.39/crypto/ocf/ep80579/icp_ocf.h +--- linux-2.6.39.orig/crypto/ocf/ep80579/icp_ocf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/ep80579/icp_ocf.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,376 @@ ++/*************************************************************************** ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++ ++/* ++ * OCF driver header file for the Intel ICP processor. ++ */ ++ ++#ifndef ICP_OCF_H_ ++#define ICP_OCF_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "icp_os.h" ++ ++#define NUM_BITS_IN_BYTE (8) ++#define NUM_BITS_IN_BYTE_MINUS_ONE (NUM_BITS_IN_BYTE -1) ++#define INVALID_DRIVER_ID (-1) ++#define RETURN_RAND_NUM_GEN_FAILED (-1) ++ ++/*This is the max block cipher initialisation vector*/ ++#define MAX_IV_LEN_IN_BYTES (20) ++/*This is used to check whether the OCF to this driver session limit has ++ been disabled*/ ++#define NO_OCF_TO_DRV_MAX_SESSIONS (0) ++ ++/*OCF values mapped here*/ ++#define ICP_SHA1_DIGEST_SIZE_IN_BYTES (SHA1_HASH_LEN) ++#define ICP_SHA256_DIGEST_SIZE_IN_BYTES (SHA2_256_HASH_LEN) ++#define ICP_SHA384_DIGEST_SIZE_IN_BYTES (SHA2_384_HASH_LEN) ++#define ICP_SHA512_DIGEST_SIZE_IN_BYTES (SHA2_512_HASH_LEN) ++#define ICP_MD5_DIGEST_SIZE_IN_BYTES (MD5_HASH_LEN) ++#define ARC4_COUNTER_LEN (ARC4_BLOCK_LEN) ++ ++#define OCF_REGISTRATION_STATUS_SUCCESS (0) ++#define OCF_ZERO_FUNCTIONALITY_REGISTERED (0) ++#define ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR (0) ++#define ICP_OCF_DRV_STATUS_SUCCESS (0) ++#define ICP_OCF_DRV_STATUS_FAIL (1) ++ ++/*Turn on/off debug options*/ ++#define ICP_OCF_PRINT_DEBUG_MESSAGES (0) ++#define ICP_OCF_PRINT_KERN_ALERT (1) ++#define ICP_OCF_PRINT_KERN_ERRS (1) ++ ++#if ICP_OCF_PRINT_DEBUG_MESSAGES == 1 ++#define DPRINTK(args...) \ ++{ \ ++ ICP_IPRINTK(args); \ ++} ++ ++#else //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 ++ ++#define DPRINTK(args...) ++ ++#endif //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 ++ ++#if ICP_OCF_PRINT_KERN_ALERT == 1 ++#define APRINTK(args...) \ ++{ \ ++ ICP_APRINTK(args); \ ++} ++ ++#else //ICP_OCF_PRINT_KERN_ALERT == 1 ++ ++#define APRINTK(args...) ++ ++#endif //ICP_OCF_PRINT_KERN_ALERT == 1 ++ ++#if ICP_OCF_PRINT_KERN_ERRS == 1 ++#define EPRINTK(args...) \ ++{ \ ++ ICP_EPRINTK(args); \ ++} ++ ++#else //ICP_OCF_PRINT_KERN_ERRS == 1 ++ ++#define EPRINTK(args...) ++ ++#endif //ICP_OCF_PRINT_KERN_ERRS == 1 ++ ++#define IPRINTK(args...) \ ++{ \ ++ ICP_IPRINTK(args); \ ++} ++ ++/*DSA Prime Q size in bytes (as defined in the standard) */ ++#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20) ++ ++#define BITS_TO_BYTES(bytes, bits) \ ++ bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE ++ ++typedef enum { ++ ICP_OCF_DRV_ALG_CIPHER = 0, ++ ICP_OCF_DRV_ALG_HASH ++} icp_ocf_drv_alg_type_t; ++ ++typedef ICP_LIST_HEAD(icp_drvSessionListHead_s, ++ icp_drvSessionData) icp_drvSessionListHead_t; ++ ++/*Values used to derisk chances of performs being called against ++deregistered sessions (for which the slab page has been reclaimed) ++This is not a fix - since page frames are reclaimed from a slab, one cannot ++rely on that memory not being re-used by another app.*/ ++typedef enum { ++ ICP_SESSION_INITIALISED = 0x5C5C5C, ++ ICP_SESSION_RUNNING = 0x005C00, ++ ICP_SESSION_DEREGISTERED = 0xC5C5C5 ++} usage_derisk; ++ ++/* This struct is required for deferred session ++ deregistration as a work queue function can ++ only have one argument*/ ++struct icp_ocfDrvFreeLacSession { ++ CpaCySymSessionCtx sessionToDeregister; ++ icp_workstruct work; ++}; ++ ++/* ++This is the OCF<->OCF_DRV session object: ++ ++1.listNode ++ The first member is a listNode. These session objects are added to a linked ++ list in order to make it easier to remove them all at session exit time. ++ ++2.inUse ++ The second member is used to give the session object state and derisk the ++ possibility of OCF batch calls executing against a deregistered session (as ++ described above). ++ ++3.sessHandle ++ The third member is a LAC<->OCF_DRV session handle (initialised with the first ++ perform request for that session). ++ ++4.lacSessCtx ++ The fourth is the LAC session context. All the parameters for this structure ++ are only known when the first perform request for this session occurs. That is ++ why the OCF EP80579 Driver only registers a new LAC session at perform time ++*/ ++struct icp_drvSessionData { ++ ICP_LIST_ENTRY(icp_drvSessionData) listNode; ++ usage_derisk inUse; ++ CpaCySymSessionCtx sessHandle; ++ CpaCySymSessionSetupData lacSessCtx; ++}; ++ ++/* These are all defined in icp_common.c */ ++extern icp_atomic_t lac_session_failed_dereg_count; ++extern icp_atomic_t icp_ocfDrvIsExiting; ++extern icp_atomic_t num_ocf_to_drv_registered_sessions; ++ ++extern int32_t icp_ocfDrvDriverId; ++ ++extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; ++extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; ++extern icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ; ++extern icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; ++ ++/*Slab zones for symettric functionality, instantiated in icp_common.c*/ ++extern icp_kmem_cache drvSessionData_zone; ++extern icp_kmem_cache drvOpData_zone; ++ ++/*Slabs zones for asymettric functionality, instantiated in icp_common.c*/ ++extern icp_kmem_cache drvDH_zone; ++extern icp_kmem_cache drvLnModExp_zone; ++extern icp_kmem_cache drvRSADecrypt_zone; ++extern icp_kmem_cache drvRSAPrivateKey_zone; ++extern icp_kmem_cache drvDSARSSign_zone; ++extern icp_kmem_cache drvDSARSSignKValue_zone; ++extern icp_kmem_cache drvDSAVerify_zone; ++ ++/* Module parameters defined in icp_cpmmon.c*/ ++ ++/* Module parameters - gives the number of times LAC deregistration shall be ++ re-tried */ ++extern int num_dereg_retries; ++ ++/* Module parameter - gives the delay time in jiffies before a LAC session ++ shall be attempted to be deregistered again */ ++extern int dereg_retry_delay_in_jiffies; ++ ++/* Module parameter - gives the maximum number of sessions possible between ++ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ ++extern int max_sessions; ++ ++/*Slab zones for flatbuffers and bufferlist*/ ++extern icp_kmem_cache drvFlatBuffer_zone; ++ ++#define ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS (16) ++ ++struct icp_drvBuffListInfo { ++ Cpa16U numBuffers; ++ Cpa32U metaSize; ++ Cpa32U metaOffset; ++ Cpa32U buffListSize; ++}; ++ ++extern struct icp_drvBuffListInfo defBuffListInfo; ++ ++/* This struct is used to keep a reference to the relevant node in the list ++ of sessionData structs, to the buffer type required by OCF and to the OCF ++ provided crp struct that needs to be returned. All this info is needed in ++ the callback function.*/ ++struct icp_drvOpData { ++ CpaCySymOpData lacOpData; ++ uint32_t digestSizeInBytes; ++ struct cryptop *crp; ++ uint8_t bufferType; ++ uint8_t ivData[MAX_IV_LEN_IN_BYTES]; ++ uint16_t numBufferListArray; ++ CpaBufferList srcBuffer; ++ CpaFlatBuffer bufferListArray[ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS]; ++ CpaBoolean verifyResult; ++}; ++ ++/* Create a new session between OCF and this driver*/ ++int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sild, ++ struct cryptoini *cri); ++ ++/* Free a session between this driver and the Quick Assist Framework*/ ++int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid); ++ ++/* Defer freeing a Quick Assist session*/ ++void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg); ++ ++/* Process OCF cryptographic request for a symmetric algorithm*/ ++int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint); ++ ++/* Process OCF cryptographic request for an asymmetric algorithm*/ ++int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint); ++ ++/* Populate a buffer with random data*/ ++int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords); ++ ++/* Retry Quick Assist session deregistration*/ ++int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister); ++ ++/* Convert an OS scatter gather list to a CPA buffer list*/ ++int icp_ocfDrvPacketBuffToBufferList(icp_packet_buffer_t * pPacketBuffer, ++ CpaBufferList * bufferList); ++ ++/* Convert a CPA buffer list to an OS scatter gather list*/ ++int icp_ocfDrvBufferListToPacketBuff(CpaBufferList * bufferList, ++ icp_packet_buffer_t ** pPacketBuffer); ++ ++/* Get the number of buffers in an OS scatter gather list*/ ++uint16_t icp_ocfDrvGetPacketBuffFrags(icp_packet_buffer_t * pPacketBuffer); ++ ++/* Convert a single OS buffer to a CPA Flat Buffer*/ ++void icp_ocfDrvSinglePacketBuffToFlatBuffer(icp_packet_buffer_t * pPacketBuffer, ++ CpaFlatBuffer * pFlatBuffer); ++ ++/* Add pointer and length to a CPA Flat Buffer structure*/ ++void icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, ++ CpaFlatBuffer * pFlatBuffer); ++ ++/* Convert pointer and length values to a CPA buffer list*/ ++void icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, ++ CpaBufferList * pBufferList); ++ ++/* Convert a CPA buffer list to pointer and length values*/ ++void icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, ++ void **ppDataOut, uint32_t * pLength); ++ ++/* Set the number of flat buffers in bufferlist and the size of memory ++ to allocate for the pPrivateMetaData member of the CpaBufferList.*/ ++int icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, ++ struct icp_drvBuffListInfo *buffListInfo); ++ ++/* Find pointer position of the digest within an OS scatter gather list*/ ++uint8_t *icp_ocfDrvPacketBufferDigestPointerFind(struct icp_drvOpData ++ *drvOpData, ++ int offsetInBytes, ++ uint32_t digestSizeInBytes); ++ ++/*This top level function is used to find a pointer to where a digest is ++ stored/needs to be inserted. */ ++uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData, ++ struct cryptodesc *crp_desc); ++ ++/* Free a CPA flat buffer*/ ++void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer); ++ ++/* This function will allocate memory for the pPrivateMetaData ++ member of CpaBufferList. */ ++int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, ++ struct icp_drvOpData *pOpData); ++ ++/* Free data allocated for the pPrivateMetaData ++ member of CpaBufferList.*/ ++void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList); ++ ++#define ICP_CACHE_CREATE(cache_ID, cache_name) \ ++ icp_kmem_cache_create(cache_ID, sizeof(cache_name),ICP_KERNEL_CACHE_ALIGN,\ ++ ICP_KERNEL_CACHE_NOINIT) ++ ++#define ICP_CACHE_FREE(args...) \ ++ icp_kmem_cache_free (args) ++ ++#define ICP_CACHE_DESTROY(slab_zone)\ ++{\ ++ if(NULL != slab_zone){\ ++ icp_kmem_cache_destroy(slab_zone);\ ++ slab_zone = NULL;\ ++ }\ ++} ++ ++#endif ++/* ICP_OCF_H_ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/ep80579/icp_sym.c linux-2.6.39/crypto/ocf/ep80579/icp_sym.c +--- linux-2.6.39.orig/crypto/ocf/ep80579/icp_sym.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/ep80579/icp_sym.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,1153 @@ ++/*************************************************************************** ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++/* ++ * An OCF module that uses the API for Intel® QuickAssist Technology to do the ++ * cryptography. ++ * ++ * This driver requires the ICP Access Library that is available from Intel in ++ * order to operate. ++ */ ++ ++#include "icp_ocf.h" ++ ++/*This is the call back function for all symmetric cryptographic processes. ++ Its main functionality is to free driver crypto operation structure and to ++ call back to OCF*/ ++static void ++icp_ocfDrvSymCallBack(void *callbackTag, ++ CpaStatus status, ++ const CpaCySymOp operationType, ++ void *pOpData, ++ CpaBufferList * pDstBuffer, CpaBoolean verifyResult); ++ ++/*This function is used to extract crypto processing information from the OCF ++ inputs, so as that it may be passed onto LAC*/ ++static int ++icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, ++ struct cryptodesc *crp_desc); ++ ++/*This function checks whether the crp_desc argument pertains to a digest or a ++ cipher operation*/ ++static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc); ++ ++/*This function copies all the passed in session context information and stores ++ it in a LAC context structure*/ ++static int ++icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, ++ CpaCySymSessionSetupData * lacSessCtx); ++ ++/*This function is used to free an OCF->OCF_DRV session object*/ ++static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData); ++ ++/*max IOV buffs supported in a UIO structure*/ ++#define NUM_IOV_SUPPORTED (1) ++ ++/* Name : icp_ocfDrvSymCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the relevant symmetric operation. ++ * ++ * Notes : The callbackTag is a pointer to an icp_drvOpData. This memory ++ * object was passed to LAC for the cryptographic processing and contains all ++ * the relevant information for cleaning up buffer handles etc. so that the ++ * OCF EP80579 Driver portion of this crypto operation can be fully completed. ++ */ ++static void ++icp_ocfDrvSymCallBack(void *callbackTag, ++ CpaStatus status, ++ const CpaCySymOp operationType, ++ void *pOpData, ++ CpaBufferList * pDstBuffer, CpaBoolean verifyResult) ++{ ++ struct cryptop *crp = NULL; ++ struct icp_drvOpData *temp_drvOpData = ++ (struct icp_drvOpData *)callbackTag; ++ uint64_t *tempBasePtr = NULL; ++ uint32_t tempLen = 0; ++ ++ if (NULL == temp_drvOpData) { ++ DPRINTK("%s(): The callback from the LAC component" ++ " has failed due to Null userOpaque data" ++ "(status == %d).\n", __FUNCTION__, status); ++ DPRINTK("%s(): Unable to call OCF back! \n", __FUNCTION__); ++ return; ++ } ++ ++ crp = temp_drvOpData->crp; ++ crp->crp_etype = ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): The callback from the LAC component" ++ " has failed due to Null Symmetric Op data" ++ "(status == %d).\n", __FUNCTION__, status); ++ crp->crp_etype = ECANCELED; ++ crypto_done(crp); ++ return; ++ } ++ ++ if (NULL == pDstBuffer) { ++ DPRINTK("%s(): The callback from the LAC component" ++ " has failed due to Null Dst Bufferlist data" ++ "(status == %d).\n", __FUNCTION__, status); ++ crp->crp_etype = ECANCELED; ++ crypto_done(crp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ ++ if (temp_drvOpData->bufferType == ICP_CRYPTO_F_PACKET_BUF) { ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvBufferListToPacketBuff(pDstBuffer, ++ (icp_packet_buffer_t ++ **) ++ & (crp->crp_buf))) { ++ EPRINTK("%s(): BufferList to SkBuff " ++ "conversion error.\n", __FUNCTION__); ++ crp->crp_etype = EPERM; ++ } ++ } else { ++ icp_ocfDrvBufferListToPtrAndLen(pDstBuffer, ++ (void **)&tempBasePtr, ++ &tempLen); ++ crp->crp_olen = (int)tempLen; ++ } ++ ++ } else { ++ DPRINTK("%s(): The callback from the LAC component has failed" ++ "(status == %d).\n", __FUNCTION__, status); ++ ++ crp->crp_etype = ECANCELED; ++ } ++ ++ if (temp_drvOpData->numBufferListArray > ++ ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { ++ icp_kfree(pDstBuffer->pBuffers); ++ } ++ icp_ocfDrvFreeMetaData(pDstBuffer); ++ ICP_CACHE_FREE(drvOpData_zone, temp_drvOpData); ++ ++ /* Invoke the OCF callback function */ ++ crypto_done(crp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvNewSession ++ * ++ * Description : This function will create a new Driver<->OCF session ++ * ++ * Notes : LAC session registration happens during the first perform call. ++ * That is the first time we know all information about a given session. ++ */ ++int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sid, ++ struct cryptoini *cri) ++{ ++ struct icp_drvSessionData *sessionData = NULL; ++ uint32_t delete_session = 0; ++ ++ /* The SID passed in should be our driver ID. We can return the */ ++ /* local ID (LID) which is a unique identifier which we can use */ ++ /* to differentiate between the encrypt/decrypt LAC session handles */ ++ if (NULL == sid) { ++ EPRINTK("%s(): Invalid input parameters - NULL sid.\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (NULL == cri) { ++ EPRINTK("%s(): Invalid input parameters - NULL cryptoini.\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (icp_ocfDrvDriverId != *sid) { ++ EPRINTK("%s(): Invalid input parameters - bad driver ID\n", ++ __FUNCTION__); ++ EPRINTK("\t sid = 0x08%p \n \t cri = 0x08%p \n", sid, cri); ++ return EINVAL; ++ } ++ ++ sessionData = icp_kmem_cache_zalloc(drvSessionData_zone, ICP_M_NOWAIT); ++ if (NULL == sessionData) { ++ DPRINTK("%s():No memory for Session Data\n", __FUNCTION__); ++ return ENOMEM; ++ } ++ ++ /*ENTER CRITICAL SECTION */ ++ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); ++ /*put this check in the spinlock so no new sessions can be added to the ++ linked list when we are exiting */ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ delete_session++; ++ ++ } else if (NO_OCF_TO_DRV_MAX_SESSIONS != max_sessions) { ++ if (icp_atomic_read(&num_ocf_to_drv_registered_sessions) >= ++ (max_sessions - ++ icp_atomic_read(&lac_session_failed_dereg_count))) { ++ delete_session++; ++ } else { ++ icp_atomic_inc(&num_ocf_to_drv_registered_sessions); ++ /* Add to session data linked list */ ++ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, ++ listNode); ++ } ++ ++ } else if (NO_OCF_TO_DRV_MAX_SESSIONS == max_sessions) { ++ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, ++ listNode); ++ } ++ ++ sessionData->inUse = ICP_SESSION_INITIALISED; ++ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ if (delete_session) { ++ DPRINTK("%s():No Session handles available\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvSessionData_zone, sessionData); ++ return EPERM; ++ } ++ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvAlgorithmSetup(cri, &(sessionData->lacSessCtx))) { ++ DPRINTK("%s():algorithm not supported\n", __FUNCTION__); ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return EINVAL; ++ } ++ ++ if (cri->cri_next) { ++ if (cri->cri_next->cri_next != NULL) { ++ DPRINTK("%s():only two chained algorithms supported\n", ++ __FUNCTION__); ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return EPERM; ++ } ++ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvAlgorithmSetup(cri->cri_next, ++ &(sessionData->lacSessCtx))) { ++ DPRINTK("%s():second algorithm not supported\n", ++ __FUNCTION__); ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return EINVAL; ++ } ++ ++ sessionData->lacSessCtx.symOperation = ++ CPA_CY_SYM_OP_ALGORITHM_CHAINING; ++ } ++ ++ *sid = (uint32_t) sessionData; ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvAlgorithmSetup ++ * ++ * Description : This function builds the session context data from the ++ * information supplied through OCF. Algorithm chain order and whether the ++ * session is Encrypt/Decrypt can only be found out at perform time however, so ++ * the session is registered with LAC at that time. ++ */ ++static int ++icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, ++ CpaCySymSessionSetupData * lacSessCtx) ++{ ++ ++ lacSessCtx->sessionPriority = CPA_CY_PRIORITY_NORMAL; ++ ++ switch (cri->cri_alg) { ++ ++ case CRYPTO_NULL_CBC: ++ DPRINTK("%s(): NULL CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_NULL; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_DES_CBC: ++ DPRINTK("%s(): DES CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_DES_CBC; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_3DES_CBC: ++ DPRINTK("%s(): 3DES CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_3DES_CBC; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_AES_CBC: ++ DPRINTK("%s(): AES CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_AES_CBC; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_ARC4: ++ DPRINTK("%s(): ARC4\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_ARC4; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_SHA1: ++ DPRINTK("%s(): SHA1\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA1_HMAC: ++ DPRINTK("%s(): SHA1_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_SHA2_256: ++ DPRINTK("%s(): SHA256\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA256; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA2_256_HMAC: ++ DPRINTK("%s(): SHA256_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA256; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_SHA2_384: ++ DPRINTK("%s(): SHA384\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA384; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA2_384_HMAC: ++ DPRINTK("%s(): SHA384_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA384; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_SHA2_512: ++ DPRINTK("%s(): SHA512\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA512; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA2_512_HMAC: ++ DPRINTK("%s(): SHA512_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA512; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_MD5: ++ DPRINTK("%s(): MD5\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_MD5_HMAC: ++ DPRINTK("%s(): MD5_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ default: ++ DPRINTK("%s(): ALG Setup FAIL\n", __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvFreeOCFSession ++ * ++ * Description : This function deletes all existing Session data representing ++ * the Cryptographic session established between OCF and this driver. This ++ * also includes freeing the memory allocated for the session context. The ++ * session object is also removed from the session linked list. ++ */ ++static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData) ++{ ++ ++ sessionData->inUse = ICP_SESSION_DEREGISTERED; ++ ++ /*ENTER CRITICAL SECTION */ ++ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ /*If the Driver is exiting, allow that process to ++ handle any deletions */ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ return; ++ } ++ ++ icp_atomic_dec(&num_ocf_to_drv_registered_sessions); ++ ++ ICP_LIST_DEL(sessionData, listNode); ++ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ if (NULL != sessionData->sessHandle) { ++ icp_kfree(sessionData->sessHandle); ++ } ++ ICP_CACHE_FREE(drvSessionData_zone, sessionData); ++} ++ ++/* Name : icp_ocfDrvFreeLACSession ++ * ++ * Description : This attempts to deregister a LAC session. If it fails, the ++ * deregistation retry function is called. ++ */ ++int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid) ++{ ++ CpaCySymSessionCtx sessionToDeregister = NULL; ++ struct icp_drvSessionData *sessionData = NULL; ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ int retval = 0; ++ ++ sessionData = (struct icp_drvSessionData *)CRYPTO_SESID2LID(sid); ++ if (NULL == sessionData) { ++ EPRINTK("%s(): OCF Free session called with Null Session ID.\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ sessionToDeregister = sessionData->sessHandle; ++ ++ if ((ICP_SESSION_INITIALISED != sessionData->inUse) && ++ (ICP_SESSION_RUNNING != sessionData->inUse) && ++ (ICP_SESSION_DEREGISTERED != sessionData->inUse)) { ++ DPRINTK("%s() Session not initialised.\n", __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (ICP_SESSION_RUNNING == sessionData->inUse) { ++ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, ++ sessionToDeregister); ++ if (CPA_STATUS_RETRY == lacStatus) { ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvDeregRetry(&sessionToDeregister)) { ++ /* the retry function increments the ++ dereg failed count */ ++ DPRINTK("%s(): LAC failed to deregister the " ++ "session. (localSessionId= %p)\n", ++ __FUNCTION__, sessionToDeregister); ++ retval = EPERM; ++ } ++ ++ } else if (CPA_STATUS_SUCCESS != lacStatus) { ++ DPRINTK("%s(): LAC failed to deregister the session. " ++ "localSessionId= %p, lacStatus = %d\n", ++ __FUNCTION__, sessionToDeregister, lacStatus); ++ icp_atomic_inc(&lac_session_failed_dereg_count); ++ retval = EPERM; ++ } ++ } else { ++ DPRINTK("%s() Session not registered with LAC.\n", ++ __FUNCTION__); ++ } ++ ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return retval; ++ ++} ++ ++/* Name : icp_ocfDrvAlgCheck ++ * ++ * Description : This function checks whether the cryptodesc argument pertains ++ * to a sym or hash function ++ */ ++static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc) ++{ ++ ++ if (crp_desc->crd_alg == CRYPTO_3DES_CBC || ++ crp_desc->crd_alg == CRYPTO_AES_CBC || ++ crp_desc->crd_alg == CRYPTO_DES_CBC || ++ crp_desc->crd_alg == CRYPTO_NULL_CBC || ++ crp_desc->crd_alg == CRYPTO_ARC4) { ++ return ICP_OCF_DRV_ALG_CIPHER; ++ } ++ ++ return ICP_OCF_DRV_ALG_HASH; ++} ++ ++/* Name : icp_ocfDrvSymProcess ++ * ++ * Description : This function will map symmetric functionality calls from OCF ++ * to the LAC API. It will also allocate memory to store the session context. ++ * ++ * Notes: If it is the first perform call for a given session, then a LAC ++ * session is registered. After the session is registered, no checks as ++ * to whether session paramaters have changed (e.g. alg chain order) are ++ * done. ++ */ ++int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint) ++{ ++ struct icp_drvSessionData *sessionData = NULL; ++ struct icp_drvOpData *drvOpData = NULL; ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ Cpa32U sessionCtxSizeInBytes = 0; ++ ++ if (NULL == crp) { ++ DPRINTK("%s(): Invalid input parameters, cryptop is NULL\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (NULL == crp->crp_desc) { ++ DPRINTK("%s(): Invalid input parameters, no crp_desc attached " ++ "to crp\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ if (NULL == crp->crp_buf) { ++ DPRINTK("%s(): Invalid input parameters, no buffer attached " ++ "to crp\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ crp->crp_etype = EFAULT; ++ return EFAULT; ++ } ++ ++ sessionData = (struct icp_drvSessionData *) ++ (CRYPTO_SESID2LID(crp->crp_sid)); ++ if (NULL == sessionData) { ++ DPRINTK("%s(): Invalid input parameters, Null Session ID \n", ++ __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++/*If we get a request against a deregisted session, cancel operation*/ ++ if (ICP_SESSION_DEREGISTERED == sessionData->inUse) { ++ DPRINTK("%s(): Session ID %d was deregistered \n", ++ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); ++ crp->crp_etype = EFAULT; ++ return EFAULT; ++ } ++ ++/*If none of the session states are set, then the session structure was either ++ not initialised properly or we are reading from a freed memory area (possible ++ due to OCF batch mode not removing queued requests against deregistered ++ sessions*/ ++ if (ICP_SESSION_INITIALISED != sessionData->inUse && ++ ICP_SESSION_RUNNING != sessionData->inUse) { ++ DPRINTK("%s(): Session - ID %d - not properly initialised or " ++ "memory freed back to the kernel \n", ++ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ /*For the below checks, remember error checking is already done in LAC. ++ We're not validating inputs subsequent to registration */ ++ if (sessionData->inUse == ICP_SESSION_INITIALISED) { ++ DPRINTK("%s(): Initialising session\n", __FUNCTION__); ++ ++ if (NULL != crp->crp_desc->crd_next) { ++ if (ICP_OCF_DRV_ALG_CIPHER == ++ icp_ocfDrvAlgCheck(crp->crp_desc)) { ++ ++ sessionData->lacSessCtx.algChainOrder = ++ CPA_CY_SYM_ALG_CHAIN_ORDER_CIPHER_THEN_HASH; ++ ++ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; ++ } else { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; ++ } ++ } else { ++ sessionData->lacSessCtx.algChainOrder = ++ CPA_CY_SYM_ALG_CHAIN_ORDER_HASH_THEN_CIPHER; ++ ++ if (crp->crp_desc->crd_next->crd_flags & ++ CRD_F_ENCRYPT) { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; ++ } else { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; ++ } ++ ++ } ++ ++ } else if (ICP_OCF_DRV_ALG_CIPHER == ++ icp_ocfDrvAlgCheck(crp->crp_desc)) { ++ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; ++ } else { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; ++ } ++ ++ } ++ ++ /*No action required for standalone Auth here */ ++ ++ /* Allocate memory for SymSessionCtx before the Session Registration */ ++ lacStatus = ++ cpaCySymSessionCtxGetSize(CPA_INSTANCE_HANDLE_SINGLE, ++ &(sessionData->lacSessCtx), ++ &sessionCtxSizeInBytes); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): cpaCySymSessionCtxGetSize failed - %d\n", ++ __FUNCTION__, lacStatus); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ sessionData->sessHandle = ++ icp_kmalloc(sessionCtxSizeInBytes, ICP_M_NOWAIT); ++ if (NULL == sessionData->sessHandle) { ++ EPRINTK ++ ("%s(): Failed to get memory for SymSessionCtx\n", ++ __FUNCTION__); ++ crp->crp_etype = ENOMEM; ++ return ENOMEM; ++ } ++ ++ lacStatus = cpaCySymInitSession(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvSymCallBack, ++ &(sessionData->lacSessCtx), ++ sessionData->sessHandle); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): cpaCySymInitSession failed -%d \n", ++ __FUNCTION__, lacStatus); ++ crp->crp_etype = EFAULT; ++ return EFAULT; ++ } ++ ++ sessionData->inUse = ICP_SESSION_RUNNING; ++ } ++ ++ drvOpData = icp_kmem_cache_zalloc(drvOpData_zone, ICP_M_NOWAIT); ++ if (NULL == drvOpData) { ++ EPRINTK("%s():Failed to get memory for drvOpData\n", ++ __FUNCTION__); ++ crp->crp_etype = ENOMEM; ++ return ENOMEM; ++ } ++ ++ drvOpData->lacOpData.pSessionCtx = sessionData->sessHandle; ++ drvOpData->digestSizeInBytes = sessionData->lacSessCtx.hashSetupData. ++ digestResultLenInBytes; ++ drvOpData->crp = crp; ++ ++ /* Set the default buffer list array memory allocation */ ++ drvOpData->srcBuffer.pBuffers = drvOpData->bufferListArray; ++ drvOpData->numBufferListArray = ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS; ++ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->crp_desc)) { ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ if (drvOpData->crp->crp_desc->crd_next != NULL) { ++ if (icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp-> ++ crp_desc->crd_next)) { ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ } ++ ++ /* ++ * Allocate buffer list array memory if the data fragment is more than ++ * the default number (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) and not ++ * calculated already ++ */ ++ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { ++ if (NULL == drvOpData->lacOpData.pDigestResult) { ++ drvOpData->numBufferListArray = ++ icp_ocfDrvGetPacketBuffFrags((icp_packet_buffer_t *) ++ crp->crp_buf); ++ } ++ ++ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < ++ drvOpData->numBufferListArray) { ++ DPRINTK("%s() numBufferListArray more than default\n", ++ __FUNCTION__); ++ drvOpData->srcBuffer.pBuffers = NULL; ++ drvOpData->srcBuffer.pBuffers = ++ icp_kmalloc(drvOpData->numBufferListArray * ++ sizeof(CpaFlatBuffer), ICP_M_NOWAIT); ++ if (NULL == drvOpData->srcBuffer.pBuffers) { ++ EPRINTK("%s() Failed to get memory for " ++ "pBuffers\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvOpData_zone, drvOpData); ++ crp->crp_etype = ENOMEM; ++ return ENOMEM; ++ } ++ } ++ } ++ ++ /* ++ * Check the type of buffer structure we got and convert it into ++ * CpaBufferList format. ++ */ ++ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvPacketBuffToBufferList((icp_packet_buffer_t *) ++ crp->crp_buf, ++ &(drvOpData->srcBuffer))) { ++ EPRINTK("%s():Failed to translate from packet buffer " ++ "to bufferlist\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ drvOpData->bufferType = ICP_CRYPTO_F_PACKET_BUF; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ /* OCF only supports IOV of one entry. */ ++ if (NUM_IOV_SUPPORTED == ++ ((struct uio *)(crp->crp_buf))->uio_iovcnt) { ++ ++ icp_ocfDrvPtrAndLenToBufferList(((struct uio *)(crp-> ++ crp_buf))-> ++ uio_iov[0].iov_base, ++ ((struct uio *)(crp-> ++ crp_buf))-> ++ uio_iov[0].iov_len, ++ &(drvOpData-> ++ srcBuffer)); ++ ++ drvOpData->bufferType = CRYPTO_F_IOV; ++ ++ } else { ++ DPRINTK("%s():Unable to handle IOVs with lengths of " ++ "greater than one!\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ } else { ++ icp_ocfDrvPtrAndLenToBufferList(crp->crp_buf, ++ crp->crp_ilen, ++ &(drvOpData->srcBuffer)); ++ ++ drvOpData->bufferType = CRYPTO_BUF_CONTIG; ++ } ++ ++ /* Allocate srcBuffer's private meta data */ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvAllocMetaData(&(drvOpData->srcBuffer), drvOpData)) { ++ EPRINTK("%s() icp_ocfDrvAllocMetaData failed\n", __FUNCTION__); ++ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ /* Perform "in-place" crypto operation */ ++ lacStatus = cpaCySymPerformOp(CPA_INSTANCE_HANDLE_SINGLE, ++ (void *)drvOpData, ++ &(drvOpData->lacOpData), ++ &(drvOpData->srcBuffer), ++ &(drvOpData->srcBuffer), ++ &(drvOpData->verifyResult)); ++ if (CPA_STATUS_RETRY == lacStatus) { ++ DPRINTK("%s(): cpaCySymPerformOp retry, lacStatus = %d\n", ++ __FUNCTION__, lacStatus); ++ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); ++ crp->crp_etype = ERESTART; ++ goto err; ++ } ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): cpaCySymPerformOp failed, lacStatus = %d\n", ++ __FUNCTION__, lacStatus); ++ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ return 0; //OCF success status value ++ ++ err: ++ if (drvOpData->numBufferListArray > ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { ++ icp_kfree(drvOpData->srcBuffer.pBuffers); ++ } ++ icp_ocfDrvFreeMetaData(&(drvOpData->srcBuffer)); ++ ICP_CACHE_FREE(drvOpData_zone, drvOpData); ++ ++ return crp->crp_etype; ++} ++ ++/* Name : icp_ocfDrvProcessDataSetup ++ * ++ * Description : This function will setup all the cryptographic operation data ++ * that is required by LAC to execute the operation. ++ */ ++static int icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, ++ struct cryptodesc *crp_desc) ++{ ++ CpaCyRandGenOpData randGenOpData; ++ CpaFlatBuffer randData; ++ ++ drvOpData->lacOpData.packetType = CPA_CY_SYM_PACKET_TYPE_FULL; ++ ++ /* Convert from the cryptop to the ICP LAC crypto parameters */ ++ switch (crp_desc->crd_alg) { ++ case CRYPTO_NULL_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = NULL_BLOCK_LEN; ++ break; ++ case CRYPTO_DES_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = DES_BLOCK_LEN; ++ break; ++ case CRYPTO_3DES_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = DES3_BLOCK_LEN; ++ break; ++ case CRYPTO_ARC4: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = ARC4_COUNTER_LEN; ++ break; ++ case CRYPTO_AES_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = RIJNDAEL128_BLOCK_LEN; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ case CRYPTO_SHA2_256: ++ case CRYPTO_SHA2_256_HMAC: ++ case CRYPTO_SHA2_384: ++ case CRYPTO_SHA2_384_HMAC: ++ case CRYPTO_SHA2_512: ++ case CRYPTO_SHA2_512_HMAC: ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ drvOpData->lacOpData. ++ hashStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToHashInBytes = crp_desc->crd_len; ++ drvOpData->lacOpData. ++ pDigestResult = ++ icp_ocfDrvDigestPointerFind(drvOpData, crp_desc); ++ ++ if (NULL == drvOpData->lacOpData.pDigestResult) { ++ DPRINTK("%s(): ERROR - could not calculate " ++ "Digest Result memory address\n", __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ drvOpData->lacOpData.digestVerify = CPA_FALSE; ++ break; ++ default: ++ DPRINTK("%s(): Crypto process error - algorithm not " ++ "found \n", __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ /* Figure out what the IV is supposed to be */ ++ if ((crp_desc->crd_alg == CRYPTO_DES_CBC) || ++ (crp_desc->crd_alg == CRYPTO_3DES_CBC) || ++ (crp_desc->crd_alg == CRYPTO_AES_CBC)) { ++ /*ARC4 doesn't use an IV */ ++ if (crp_desc->crd_flags & CRD_F_IV_EXPLICIT) { ++ /* Explicit IV provided to OCF */ ++ drvOpData->lacOpData.pIv = crp_desc->crd_iv; ++ } else { ++ /* IV is not explicitly provided to OCF */ ++ ++ /* Point the LAC OP Data IV pointer to our allocated ++ storage location for this session. */ ++ drvOpData->lacOpData.pIv = drvOpData->ivData; ++ ++ if ((crp_desc->crd_flags & CRD_F_ENCRYPT) && ++ ((crp_desc->crd_flags & CRD_F_IV_PRESENT) == 0)) { ++ ++ /* Encrypting - need to create IV */ ++ randGenOpData.generateBits = CPA_TRUE; ++ randGenOpData.lenInBytes = MAX_IV_LEN_IN_BYTES; ++ ++ icp_ocfDrvPtrAndLenToFlatBuffer((Cpa8U *) ++ drvOpData-> ++ ivData, ++ MAX_IV_LEN_IN_BYTES, ++ &randData); ++ ++ if (CPA_STATUS_SUCCESS != ++ cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, ++ NULL, NULL, ++ &randGenOpData, &randData)) { ++ DPRINTK("%s(): ERROR - Failed to" ++ " generate" ++ " Initialisation Vector\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ crypto_copyback(drvOpData->crp-> ++ crp_flags, ++ drvOpData->crp->crp_buf, ++ crp_desc->crd_inject, ++ drvOpData->lacOpData. ++ ivLenInBytes, ++ (caddr_t) (drvOpData->lacOpData. ++ pIv)); ++ } else { ++ /* Reading IV from buffer */ ++ crypto_copydata(drvOpData->crp-> ++ crp_flags, ++ drvOpData->crp->crp_buf, ++ crp_desc->crd_inject, ++ drvOpData->lacOpData. ++ ivLenInBytes, ++ (caddr_t) (drvOpData->lacOpData. ++ pIv)); ++ } ++ ++ } ++ ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvDigestPointerFind ++ * ++ * Description : This function is used to find the memory address of where the ++ * digest information shall be stored in. Input buffer types are an skbuff, iov ++ * or flat buffer. The address is found using the buffer data start address and ++ * an offset. ++ * ++ * Note: In the case of a linux skbuff, the digest address may exist within ++ * a memory space linked to from the start buffer. These linked memory spaces ++ * must be traversed by the data length offset in order to find the digest start ++ * address. Whether there is enough space for the digest must also be checked. ++ */ ++uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData * drvOpData, ++ struct cryptodesc * crp_desc) ++{ ++ ++ int offsetInBytes = crp_desc->crd_inject; ++ uint32_t digestSizeInBytes = drvOpData->digestSizeInBytes; ++ uint8_t *flat_buffer_base = NULL; ++ int flat_buffer_length = 0; ++ ++ if (drvOpData->crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { ++ ++ return icp_ocfDrvPacketBufferDigestPointerFind(drvOpData, ++ offsetInBytes, ++ digestSizeInBytes); ++ ++ } else { ++ /* IOV or flat buffer */ ++ if (drvOpData->crp->crp_flags & CRYPTO_F_IOV) { ++ /*single IOV check has already been done */ ++ flat_buffer_base = ((struct uio *) ++ (drvOpData->crp->crp_buf))-> ++ uio_iov[0].iov_base; ++ flat_buffer_length = ((struct uio *) ++ (drvOpData->crp->crp_buf))-> ++ uio_iov[0].iov_len; ++ } else { ++ flat_buffer_base = (uint8_t *) drvOpData->crp->crp_buf; ++ flat_buffer_length = drvOpData->crp->crp_ilen; ++ } ++ ++ if (flat_buffer_length < (offsetInBytes + digestSizeInBytes)) { ++ DPRINTK("%s() Not enough space for Digest " ++ "(IOV/Flat Buffer) \n", __FUNCTION__); ++ return NULL; ++ } else { ++ return (uint8_t *) (flat_buffer_base + offsetInBytes); ++ } ++ } ++ DPRINTK("%s() Should not reach this point\n", __FUNCTION__); ++ return NULL; ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/Makefile linux-2.6.39/crypto/ocf/hifn/Makefile +--- linux-2.6.39.orig/crypto/ocf/hifn/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/hifn/Makefile 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,13 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_HIFN) += hifn7751.o ++obj-$(CONFIG_OCF_HIFNHIPP) += hifnHIPP.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/hifn7751.c linux-2.6.39/crypto/ocf/hifn/hifn7751.c +--- linux-2.6.39.orig/crypto/ocf/hifn/hifn7751.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/hifn/hifn7751.c 2011-08-01 14:39:27.000000000 +0200 +@@ -0,0 +1,2973 @@ ++/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ ++ ++/*- ++ * Invertex AEON / Hifn 7751 driver ++ * Copyright (c) 1999 Invertex Inc. All rights reserved. ++ * Copyright (c) 1999 Theo de Raadt ++ * Copyright (c) 2000-2001 Network Security Technologies, Inc. ++ * http://www.netsec.net ++ * Copyright (c) 2003 Hifn Inc. ++ * ++ * This driver is based on a previous driver by Invertex, for which they ++ * requested: Please send any comments, feedback, bug-fixes, or feature ++ * requests to software@invertex.com. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ * ++__FBSDID("$FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.40 2007/03/21 03:42:49 sam Exp $"); ++ */ ++ ++/* ++ * Driver for various Hifn encryption processors. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#if 1 ++#define DPRINTF(a...) if (hifn_debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_dev) : "hifn"); \ ++ printk(a); \ ++ } else ++#else ++#define DPRINTF(a...) ++#endif ++ ++static inline int ++pci_get_revid(struct pci_dev *dev) ++{ ++ u8 rid = 0; ++ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); ++ return rid; ++} ++ ++static struct hifn_stats hifnstats; ++ ++#define debug hifn_debug ++int hifn_debug = 0; ++module_param(hifn_debug, int, 0644); ++MODULE_PARM_DESC(hifn_debug, "Enable debug"); ++ ++int hifn_maxbatch = 1; ++module_param(hifn_maxbatch, int, 0644); ++MODULE_PARM_DESC(hifn_maxbatch, "max ops to batch w/o interrupt"); ++ ++int hifn_cache_linesize = 0x10; ++module_param(hifn_cache_linesize, int, 0444); ++MODULE_PARM_DESC(hifn_cache_linesize, "PCI config cache line size"); ++ ++#ifdef MODULE_PARM ++char *hifn_pllconfig = NULL; ++MODULE_PARM(hifn_pllconfig, "s"); ++#else ++char hifn_pllconfig[32]; /* This setting is RO after loading */ ++module_param_string(hifn_pllconfig, hifn_pllconfig, 32, 0444); ++#endif ++MODULE_PARM_DESC(hifn_pllconfig, "PLL config, ie., pci66, ext33, ..."); ++ ++#ifdef HIFN_VULCANDEV ++#include ++#include ++ ++static struct cdevsw vulcanpk_cdevsw; /* forward declaration */ ++#endif ++ ++/* ++ * Prototypes and count for the pci_device structure ++ */ ++static int hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent); ++static void hifn_remove(struct pci_dev *dev); ++ ++static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int hifn_freesession(device_t, u_int64_t); ++static int hifn_process(device_t, struct cryptop *, int); ++ ++static device_method_t hifn_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, hifn_newsession), ++ DEVMETHOD(cryptodev_freesession,hifn_freesession), ++ DEVMETHOD(cryptodev_process, hifn_process), ++}; ++ ++static void hifn_reset_board(struct hifn_softc *, int); ++static void hifn_reset_puc(struct hifn_softc *); ++static void hifn_puc_wait(struct hifn_softc *); ++static int hifn_enable_crypto(struct hifn_softc *); ++static void hifn_set_retry(struct hifn_softc *sc); ++static void hifn_init_dma(struct hifn_softc *); ++static void hifn_init_pci_registers(struct hifn_softc *); ++static int hifn_sramsize(struct hifn_softc *); ++static int hifn_dramsize(struct hifn_softc *); ++static int hifn_ramtype(struct hifn_softc *); ++static void hifn_sessions(struct hifn_softc *); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++static irqreturn_t hifn_intr(int irq, void *arg); ++#else ++static irqreturn_t hifn_intr(int irq, void *arg, struct pt_regs *regs); ++#endif ++static u_int hifn_write_command(struct hifn_command *, u_int8_t *); ++static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); ++static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); ++static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); ++static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); ++static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); ++static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); ++static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); ++static int hifn_init_pubrng(struct hifn_softc *); ++static void hifn_tick(unsigned long arg); ++static void hifn_abort(struct hifn_softc *); ++static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); ++ ++static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); ++static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++static int hifn_read_random(void *arg, u_int32_t *buf, int len); ++#endif ++ ++#define HIFN_MAX_CHIPS 8 ++static struct hifn_softc *hifn_chip_idx[HIFN_MAX_CHIPS]; ++ ++static __inline u_int32_t ++READ_REG_0(struct hifn_softc *sc, bus_size_t reg) ++{ ++ u_int32_t v = readl(sc->sc_bar0 + reg); ++ sc->sc_bar0_lastreg = (bus_size_t) -1; ++ return (v); ++} ++#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) ++ ++static __inline u_int32_t ++READ_REG_1(struct hifn_softc *sc, bus_size_t reg) ++{ ++ u_int32_t v = readl(sc->sc_bar1 + reg); ++ sc->sc_bar1_lastreg = (bus_size_t) -1; ++ return (v); ++} ++#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) ++ ++/* ++ * map in a given buffer (great on some arches :-) ++ */ ++ ++static int ++pci_map_uio(struct hifn_softc *sc, struct hifn_operand *buf, struct uio *uio) ++{ ++ struct iovec *iov = uio->uio_iov; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf->mapsize = 0; ++ for (buf->nsegs = 0; buf->nsegs < uio->uio_iovcnt; ) { ++ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, ++ iov->iov_base, iov->iov_len, ++ PCI_DMA_BIDIRECTIONAL); ++ buf->segs[buf->nsegs].ds_len = iov->iov_len; ++ buf->mapsize += iov->iov_len; ++ iov++; ++ buf->nsegs++; ++ } ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++/* ++ * map in a given sk_buff ++ */ ++ ++static int ++pci_map_skb(struct hifn_softc *sc,struct hifn_operand *buf,struct sk_buff *skb) ++{ ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf->mapsize = 0; ++ ++ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, ++ skb->data, skb_headlen(skb), PCI_DMA_BIDIRECTIONAL); ++ buf->segs[0].ds_len = skb_headlen(skb); ++ buf->mapsize += buf->segs[0].ds_len; ++ ++ buf->nsegs = 1; ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; ) { ++ buf->segs[buf->nsegs].ds_len = skb_shinfo(skb)->frags[i].size; ++ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, ++ page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ buf->segs[buf->nsegs].ds_len, PCI_DMA_BIDIRECTIONAL); ++ buf->mapsize += buf->segs[buf->nsegs].ds_len; ++ buf->nsegs++; ++ } ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++/* ++ * map in a given contiguous buffer ++ */ ++ ++static int ++pci_map_buf(struct hifn_softc *sc,struct hifn_operand *buf, void *b, int len) ++{ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf->mapsize = 0; ++ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, ++ b, len, PCI_DMA_BIDIRECTIONAL); ++ buf->segs[0].ds_len = len; ++ buf->mapsize += buf->segs[0].ds_len; ++ buf->nsegs = 1; ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++#if 0 /* not needed at this time */ ++static void ++pci_sync_iov(struct hifn_softc *sc, struct hifn_operand *buf) ++{ ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ for (i = 0; i < buf->nsegs; i++) ++ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); ++} ++#endif ++ ++static void ++pci_unmap_buf(struct hifn_softc *sc, struct hifn_operand *buf) ++{ ++ int i; ++ DPRINTF("%s()\n", __FUNCTION__); ++ for (i = 0; i < buf->nsegs; i++) { ++ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); ++ buf->segs[i].ds_addr = 0; ++ buf->segs[i].ds_len = 0; ++ } ++ buf->nsegs = 0; ++ buf->mapsize = 0; ++ buf->map = 0; ++} ++ ++static const char* ++hifn_partname(struct hifn_softc *sc) ++{ ++ /* XXX sprintf numbers when not decoded */ ++ switch (pci_get_vendor(sc->sc_pcidev)) { ++ case PCI_VENDOR_HIFN: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; ++ case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; ++ case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; ++ case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; ++ case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; ++ case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; ++ } ++ return "Hifn unknown-part"; ++ case PCI_VENDOR_INVERTEX: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; ++ } ++ return "Invertex unknown-part"; ++ case PCI_VENDOR_NETSEC: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; ++ } ++ return "NetSec unknown-part"; ++ } ++ return "Unknown-vendor unknown-part"; ++} ++ ++static u_int ++checkmaxmin(struct pci_dev *dev, const char *what, u_int v, u_int min, u_int max) ++{ ++ struct hifn_softc *sc = pci_get_drvdata(dev); ++ if (v > max) { ++ device_printf(sc->sc_dev, "Warning, %s %u out of range, " ++ "using max %u\n", what, v, max); ++ v = max; ++ } else if (v < min) { ++ device_printf(sc->sc_dev, "Warning, %s %u out of range, " ++ "using min %u\n", what, v, min); ++ v = min; ++ } ++ return v; ++} ++ ++/* ++ * Select PLL configuration for 795x parts. This is complicated in ++ * that we cannot determine the optimal parameters without user input. ++ * The reference clock is derived from an external clock through a ++ * multiplier. The external clock is either the host bus (i.e. PCI) ++ * or an external clock generator. When using the PCI bus we assume ++ * the clock is either 33 or 66 MHz; for an external source we cannot ++ * tell the speed. ++ * ++ * PLL configuration is done with a string: "pci" for PCI bus, or "ext" ++ * for an external source, followed by the frequency. We calculate ++ * the appropriate multiplier and PLL register contents accordingly. ++ * When no configuration is given we default to "pci66" since that ++ * always will allow the card to work. If a card is using the PCI ++ * bus clock and in a 33MHz slot then it will be operating at half ++ * speed until the correct information is provided. ++ * ++ * We use a default setting of "ext66" because according to Mike Ham ++ * of HiFn, almost every board in existence has an external crystal ++ * populated at 66Mhz. Using PCI can be a problem on modern motherboards, ++ * because PCI33 can have clocks from 0 to 33Mhz, and some have ++ * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. ++ */ ++static void ++hifn_getpllconfig(struct pci_dev *dev, u_int *pll) ++{ ++ const char *pllspec = hifn_pllconfig; ++ u_int freq, mul, fl, fh; ++ u_int32_t pllconfig; ++ char *nxt; ++ ++ if (pllspec == NULL) ++ pllspec = "ext66"; ++ fl = 33, fh = 66; ++ pllconfig = 0; ++ if (strncmp(pllspec, "ext", 3) == 0) { ++ pllspec += 3; ++ pllconfig |= HIFN_PLL_REF_SEL; ++ switch (pci_get_device(dev)) { ++ case PCI_PRODUCT_HIFN_7955: ++ case PCI_PRODUCT_HIFN_7956: ++ fl = 20, fh = 100; ++ break; ++#ifdef notyet ++ case PCI_PRODUCT_HIFN_7954: ++ fl = 20, fh = 66; ++ break; ++#endif ++ } ++ } else if (strncmp(pllspec, "pci", 3) == 0) ++ pllspec += 3; ++ freq = strtoul(pllspec, &nxt, 10); ++ if (nxt == pllspec) ++ freq = 66; ++ else ++ freq = checkmaxmin(dev, "frequency", freq, fl, fh); ++ /* ++ * Calculate multiplier. We target a Fck of 266 MHz, ++ * allowing only even values, possibly rounded down. ++ * Multipliers > 8 must set the charge pump current. ++ */ ++ mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); ++ pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; ++ if (mul > 8) ++ pllconfig |= HIFN_PLL_IS; ++ *pll = pllconfig; ++} ++ ++/* ++ * Attach an interface that successfully probed. ++ */ ++static int ++hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent) ++{ ++ struct hifn_softc *sc = NULL; ++ char rbase; ++ u_int16_t ena, rev; ++ int rseg, rc; ++ unsigned long mem_start, mem_len; ++ static int num_chips = 0; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (pci_enable_device(dev) < 0) ++ return(-ENODEV); ++ ++ if (pci_set_mwi(dev)) ++ return(-ENODEV); ++ ++ if (!dev->irq) { ++ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); ++ pci_disable_device(dev); ++ return(-ENODEV); ++ } ++ ++ sc = (struct hifn_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, "hifn", num_chips, hifn_methods); ++ ++ sc->sc_pcidev = dev; ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++ sc->sc_num = num_chips++; ++ if (sc->sc_num < HIFN_MAX_CHIPS) ++ hifn_chip_idx[sc->sc_num] = sc; ++ ++ pci_set_drvdata(sc->sc_pcidev, sc); ++ ++ spin_lock_init(&sc->sc_mtx); ++ ++ /* XXX handle power management */ ++ ++ /* ++ * The 7951 and 795x have a random number generator and ++ * public key support; note this. ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && ++ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) ++ sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; ++ /* ++ * The 7811 has a random number generator and ++ * we also note it's identity 'cuz of some quirks. ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) ++ sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; ++ ++ /* ++ * The 795x parts support AES. ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && ++ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { ++ sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; ++ /* ++ * Select PLL configuration. This depends on the ++ * bus and board design and must be manually configured ++ * if the default setting is unacceptable. ++ */ ++ hifn_getpllconfig(dev, &sc->sc_pllconfig); ++ } ++ ++ /* ++ * Setup PCI resources. Note that we record the bus ++ * tag and handle for each register mapping, this is ++ * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, ++ * and WRITE_REG_1 macros throughout the driver. ++ */ ++ mem_start = pci_resource_start(sc->sc_pcidev, 0); ++ mem_len = pci_resource_len(sc->sc_pcidev, 0); ++ sc->sc_bar0 = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_bar0) { ++ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 0); ++ goto fail; ++ } ++ sc->sc_bar0_lastreg = (bus_size_t) -1; ++ ++ mem_start = pci_resource_start(sc->sc_pcidev, 1); ++ mem_len = pci_resource_len(sc->sc_pcidev, 1); ++ sc->sc_bar1 = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_bar1) { ++ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 1); ++ goto fail; ++ } ++ sc->sc_bar1_lastreg = (bus_size_t) -1; ++ ++ /* fix up the bus size */ ++ if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); ++ goto fail; ++ } ++ if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, ++ "No usable consistent DMA configuration, aborting.\n"); ++ goto fail; ++ } ++ ++ hifn_set_retry(sc); ++ ++ /* ++ * Setup the area where the Hifn DMA's descriptors ++ * and associated data structures. ++ */ ++ sc->sc_dma = (struct hifn_dma *) pci_alloc_consistent(dev, ++ sizeof(*sc->sc_dma), ++ &sc->sc_dma_physaddr); ++ if (!sc->sc_dma) { ++ device_printf(sc->sc_dev, "cannot alloc sc_dma\n"); ++ goto fail; ++ } ++ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); ++ ++ /* ++ * Reset the board and do the ``secret handshake'' ++ * to enable the crypto support. Then complete the ++ * initialization procedure by setting up the interrupt ++ * and hooking in to the system crypto support so we'll ++ * get used for system services like the crypto device, ++ * IPsec, RNG device, etc. ++ */ ++ hifn_reset_board(sc, 0); ++ ++ if (hifn_enable_crypto(sc) != 0) { ++ device_printf(sc->sc_dev, "crypto enabling failed\n"); ++ goto fail; ++ } ++ hifn_reset_puc(sc); ++ ++ hifn_init_dma(sc); ++ hifn_init_pci_registers(sc); ++ ++ pci_set_master(sc->sc_pcidev); ++ ++ /* XXX can't dynamically determine ram type for 795x; force dram */ ++ if (sc->sc_flags & HIFN_IS_7956) ++ sc->sc_drammodel = 1; ++ else if (hifn_ramtype(sc)) ++ goto fail; ++ ++ if (sc->sc_drammodel == 0) ++ hifn_sramsize(sc); ++ else ++ hifn_dramsize(sc); ++ ++ /* ++ * Workaround for NetSec 7751 rev A: half ram size because two ++ * of the address lines were left floating ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && ++ pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && ++ pci_get_revid(dev) == 0x61) /*XXX???*/ ++ sc->sc_ramsize >>= 1; ++ ++ /* ++ * Arrange the interrupt line. ++ */ ++ rc = request_irq(dev->irq, hifn_intr, IRQF_SHARED, "hifn", sc); ++ if (rc) { ++ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); ++ goto fail; ++ } ++ sc->sc_irq = dev->irq; ++ ++ hifn_sessions(sc); ++ ++ /* ++ * NB: Keep only the low 16 bits; this masks the chip id ++ * from the 7951. ++ */ ++ rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; ++ ++ rseg = sc->sc_ramsize / 1024; ++ rbase = 'K'; ++ if (sc->sc_ramsize >= (1024 * 1024)) { ++ rbase = 'M'; ++ rseg /= 1024; ++ } ++ device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", ++ hifn_partname(sc), rev, ++ rseg, rbase, sc->sc_drammodel ? 'd' : 's'); ++ if (sc->sc_flags & HIFN_IS_7956) ++ printf(", pll=0x%x<%s clk, %ux mult>", ++ sc->sc_pllconfig, ++ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", ++ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); ++ printf("\n"); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ goto fail; ++ } ++ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ++ READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); ++ ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; ++ ++ switch (ena) { ++ case HIFN_PUSTAT_ENA_2: ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); ++ if (sc->sc_flags & HIFN_HAS_AES) ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ /*FALLTHROUGH*/ ++ case HIFN_PUSTAT_ENA_1: ++ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ break; ++ } ++ ++ if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) ++ hifn_init_pubrng(sc); ++ ++ init_timer(&sc->sc_tickto); ++ sc->sc_tickto.function = hifn_tick; ++ sc->sc_tickto.data = (unsigned long) sc->sc_num; ++ mod_timer(&sc->sc_tickto, jiffies + HZ); ++ ++ return (0); ++ ++fail: ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_dma) { ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ pci_free_consistent(sc->sc_pcidev, ++ sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++ } ++ kfree(sc); ++ return (-ENXIO); ++} ++ ++/* ++ * Detach an interface that successfully probed. ++ */ ++static void ++hifn_remove(struct pci_dev *dev) ++{ ++ struct hifn_softc *sc = pci_get_drvdata(dev); ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); ++ ++ /* disable interrupts */ ++ HIFN_LOCK(sc); ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); ++ HIFN_UNLOCK(sc); ++ ++ /*XXX other resources */ ++ del_timer_sync(&sc->sc_tickto); ++ ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ crypto_unregister_all(sc->sc_cid); ++ ++ free_irq(sc->sc_irq, sc); ++ ++ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++} ++ ++ ++static int ++hifn_init_pubrng(struct hifn_softc *sc) ++{ ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if ((sc->sc_flags & HIFN_IS_7811) == 0) { ++ /* Reset 7951 public key/rng engine */ ++ WRITE_REG_1(sc, HIFN_1_PUB_RESET, ++ READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); ++ ++ for (i = 0; i < 100; i++) { ++ DELAY(1000); ++ if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & ++ HIFN_PUBRST_RESET) == 0) ++ break; ++ } ++ ++ if (i == 100) { ++ device_printf(sc->sc_dev, "public key init failed\n"); ++ return (1); ++ } ++ } ++ ++ /* Enable the rng, if available */ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ if (sc->sc_flags & HIFN_HAS_RNG) { ++ if (sc->sc_flags & HIFN_IS_7811) { ++ u_int32_t r; ++ r = READ_REG_1(sc, HIFN_1_7811_RNGENA); ++ if (r & HIFN_7811_RNGENA_ENA) { ++ r &= ~HIFN_7811_RNGENA_ENA; ++ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); ++ } ++ WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, ++ HIFN_7811_RNGCFG_DEFL); ++ r |= HIFN_7811_RNGENA_ENA; ++ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); ++ } else ++ WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, ++ READ_REG_1(sc, HIFN_1_RNG_CONFIG) | ++ HIFN_RNGCFG_ENA); ++ ++ sc->sc_rngfirst = 1; ++ crypto_rregister(sc->sc_cid, hifn_read_random, sc); ++ } ++#endif ++ ++ /* Enable public key engine, if available */ ++ if (sc->sc_flags & HIFN_HAS_PUBLIC) { ++ WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); ++ sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++#ifdef HIFN_VULCANDEV ++ sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, ++ UID_ROOT, GID_WHEEL, 0666, ++ "vulcanpk"); ++ sc->sc_pkdev->si_drv1 = sc; ++#endif ++ } ++ ++ return (0); ++} ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++static int ++hifn_read_random(void *arg, u_int32_t *buf, int len) ++{ ++ struct hifn_softc *sc = (struct hifn_softc *) arg; ++ u_int32_t sts; ++ int i, rc = 0; ++ ++ if (len <= 0) ++ return rc; ++ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ /* ONLY VALID ON 7811!!!! */ ++ for (i = 0; i < 5; i++) { ++ sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); ++ if (sts & HIFN_7811_RNGSTS_UFL) { ++ device_printf(sc->sc_dev, ++ "RNG underflow: disabling\n"); ++ /* DAVIDM perhaps return -1 */ ++ break; ++ } ++ if ((sts & HIFN_7811_RNGSTS_RDY) == 0) ++ break; ++ ++ /* ++ * There are at least two words in the RNG FIFO ++ * at this point. ++ */ ++ if (rc < len) ++ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); ++ if (rc < len) ++ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); ++ } ++ } else ++ buf[rc++] = READ_REG_1(sc, HIFN_1_RNG_DATA); ++ ++ /* NB: discard first data read */ ++ if (sc->sc_rngfirst) { ++ sc->sc_rngfirst = 0; ++ rc = 0; ++ } ++ ++ return(rc); ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++static void ++hifn_puc_wait(struct hifn_softc *sc) ++{ ++ int i; ++ int reg = HIFN_0_PUCTRL; ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ reg = HIFN_0_PUCTRL2; ++ } ++ ++ for (i = 5000; i > 0; i--) { ++ DELAY(1); ++ if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) ++ break; ++ } ++ if (!i) ++ device_printf(sc->sc_dev, "proc unit did not reset(0x%x)\n", ++ READ_REG_0(sc, HIFN_0_PUCTRL)); ++} ++ ++/* ++ * Reset the processing unit. ++ */ ++static void ++hifn_reset_puc(struct hifn_softc *sc) ++{ ++ /* Reset processing unit */ ++ int reg = HIFN_0_PUCTRL; ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ reg = HIFN_0_PUCTRL2; ++ } ++ WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); ++ ++ hifn_puc_wait(sc); ++} ++ ++/* ++ * Set the Retry and TRDY registers; note that we set them to ++ * zero because the 7811 locks up when forced to retry (section ++ * 3.6 of "Specification Update SU-0014-04". Not clear if we ++ * should do this for all Hifn parts, but it doesn't seem to hurt. ++ */ ++static void ++hifn_set_retry(struct hifn_softc *sc) ++{ ++ DPRINTF("%s()\n", __FUNCTION__); ++ /* NB: RETRY only responds to 8-bit reads/writes */ ++ pci_write_config_byte(sc->sc_pcidev, HIFN_RETRY_TIMEOUT, 0); ++ pci_write_config_dword(sc->sc_pcidev, HIFN_TRDY_TIMEOUT, 0); ++ /* piggy back the cache line setting here */ ++ pci_write_config_byte(sc->sc_pcidev, PCI_CACHE_LINE_SIZE, hifn_cache_linesize); ++} ++ ++/* ++ * Resets the board. Values in the regesters are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++static void ++hifn_reset_board(struct hifn_softc *sc, int full) ++{ ++ u_int32_t reg; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ /* ++ * Set polling in the DMA configuration register to zero. 0x7 avoids ++ * resetting the board and zeros out the other fields. ++ */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ /* ++ * Now that polling has been disabled, we have to wait 1 ms ++ * before resetting the board. ++ */ ++ DELAY(1000); ++ ++ /* Reset the DMA unit */ ++ if (full) { ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); ++ DELAY(1000); ++ } else { ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, ++ HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); ++ hifn_reset_puc(sc); ++ } ++ ++ KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); ++ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); ++ ++ /* Bring dma unit out of reset */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ hifn_puc_wait(sc); ++ hifn_set_retry(sc); ++ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ for (reg = 0; reg < 1000; reg++) { ++ if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & ++ HIFN_MIPSRST_CRAMINIT) ++ break; ++ DELAY(1000); ++ } ++ if (reg == 1000) ++ device_printf(sc->sc_dev, ": cram init timeout\n"); ++ } else { ++ /* set up DMA configuration register #2 */ ++ /* turn off all PK and BAR0 swaps */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, ++ (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| ++ (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| ++ (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| ++ (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); ++ } ++} ++ ++static u_int32_t ++hifn_next_signature(u_int32_t a, u_int cnt) ++{ ++ int i; ++ u_int32_t v; ++ ++ for (i = 0; i < cnt; i++) { ++ ++ /* get the parity */ ++ v = a & 0x80080125; ++ v ^= v >> 16; ++ v ^= v >> 8; ++ v ^= v >> 4; ++ v ^= v >> 2; ++ v ^= v >> 1; ++ ++ a = (v & 1) ^ (a << 1); ++ } ++ ++ return a; ++} ++ ++ ++/* ++ * Checks to see if crypto is already enabled. If crypto isn't enable, ++ * "hifn_enable_crypto" is called to enable it. The check is important, ++ * as enabling crypto twice will lock the board. ++ */ ++static int ++hifn_enable_crypto(struct hifn_softc *sc) ++{ ++ u_int32_t dmacfg, ramcfg, encl, addr, i; ++ char offtbl[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00 }; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); ++ dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); ++ ++ /* ++ * The RAM config register's encrypt level bit needs to be set before ++ * every read performed on the encryption level register. ++ */ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); ++ ++ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; ++ ++ /* ++ * Make sure we don't re-unlock. Two unlocks kills chip until the ++ * next reboot. ++ */ ++ if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, ++ "Strong crypto already enabled!\n"); ++#endif ++ goto report; ++ } ++ ++ if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, ++ "Unknown encryption level 0x%x\n", encl); ++#endif ++ return 1; ++ } ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | ++ HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ DELAY(1000); ++ addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); ++ DELAY(1000); ++ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); ++ DELAY(1000); ++ ++ for (i = 0; i <= 12; i++) { ++ addr = hifn_next_signature(addr, offtbl[i] + 0x101); ++ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); ++ ++ DELAY(1000); ++ } ++ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); ++ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) ++ device_printf(sc->sc_dev, "Engine is permanently " ++ "locked until next system reset!\n"); ++ else ++ device_printf(sc->sc_dev, "Engine enabled " ++ "successfully!\n"); ++ } ++#endif ++ ++report: ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); ++ ++ switch (encl) { ++ case HIFN_PUSTAT_ENA_1: ++ case HIFN_PUSTAT_ENA_2: ++ break; ++ case HIFN_PUSTAT_ENA_0: ++ default: ++ device_printf(sc->sc_dev, "disabled\n"); ++ break; ++ } ++ ++ return 0; ++} ++ ++/* ++ * Give initial values to the registers listed in the "Register Space" ++ * section of the HIFN Software Development reference manual. ++ */ ++static void ++hifn_init_pci_registers(struct hifn_softc *sc) ++{ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* write fixed values needed by the Initialization registers */ ++ WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); ++ WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); ++ WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); ++ ++ /* write all 4 ring address registers */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, cmdr[0])); ++ WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, srcr[0])); ++ WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, dstr[0])); ++ WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, resr[0])); ++ ++ DELAY(2000); ++ ++ /* write status register */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | ++ HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | ++ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | ++ HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | ++ HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | ++ HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | ++ HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | ++ HIFN_DMACSR_S_WAIT | ++ HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | ++ HIFN_DMACSR_C_WAIT | ++ HIFN_DMACSR_ENGINE | ++ ((sc->sc_flags & HIFN_HAS_PUBLIC) ? ++ HIFN_DMACSR_PUBDONE : 0) | ++ ((sc->sc_flags & HIFN_IS_7811) ? ++ HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); ++ ++ sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; ++ sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | ++ HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | ++ HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | ++ ((sc->sc_flags & HIFN_IS_7811) ? ++ HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); ++ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++ ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ u_int32_t pll; ++ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | ++ HIFN_PUCNFG_TCALLPHASES | ++ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); ++ ++ /* turn off the clocks and insure bypass is set */ ++ pll = READ_REG_1(sc, HIFN_1_PLL); ++ pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) ++ | HIFN_PLL_BP | HIFN_PLL_MBSET; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ DELAY(10*1000); /* 10ms */ ++ ++ /* change configuration */ ++ pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ DELAY(10*1000); /* 10ms */ ++ ++ /* disable bypass */ ++ pll &= ~HIFN_PLL_BP; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ /* enable clocks with new configuration */ ++ pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ } else { ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | ++ HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | ++ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | ++ (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); ++ } ++ ++ WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | ++ ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | ++ ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); ++} ++ ++/* ++ * The maximum number of sessions supported by the card ++ * is dependent on the amount of context ram, which ++ * encryption algorithms are enabled, and how compression ++ * is configured. This should be configured before this ++ * routine is called. ++ */ ++static void ++hifn_sessions(struct hifn_softc *sc) ++{ ++ u_int32_t pucnfg; ++ int ctxsize; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); ++ ++ if (pucnfg & HIFN_PUCNFG_COMPSING) { ++ if (pucnfg & HIFN_PUCNFG_ENCCNFG) ++ ctxsize = 128; ++ else ++ ctxsize = 512; ++ /* ++ * 7955/7956 has internal context memory of 32K ++ */ ++ if (sc->sc_flags & HIFN_IS_7956) ++ sc->sc_maxses = 32768 / ctxsize; ++ else ++ sc->sc_maxses = 1 + ++ ((sc->sc_ramsize - 32768) / ctxsize); ++ } else ++ sc->sc_maxses = sc->sc_ramsize / 16384; ++ ++ if (sc->sc_maxses > 2048) ++ sc->sc_maxses = 2048; ++} ++ ++/* ++ * Determine ram type (sram or dram). Board should be just out of a reset ++ * state when this is called. ++ */ ++static int ++hifn_ramtype(struct hifn_softc *sc) ++{ ++ u_int8_t data[8], dataexpect[8]; ++ int i; ++ ++ for (i = 0; i < sizeof(data); i++) ++ data[i] = dataexpect[i] = 0x55; ++ if (hifn_writeramaddr(sc, 0, data)) ++ return (-1); ++ if (hifn_readramaddr(sc, 0, data)) ++ return (-1); ++ if (bcmp(data, dataexpect, sizeof(data)) != 0) { ++ sc->sc_drammodel = 1; ++ return (0); ++ } ++ ++ for (i = 0; i < sizeof(data); i++) ++ data[i] = dataexpect[i] = 0xaa; ++ if (hifn_writeramaddr(sc, 0, data)) ++ return (-1); ++ if (hifn_readramaddr(sc, 0, data)) ++ return (-1); ++ if (bcmp(data, dataexpect, sizeof(data)) != 0) { ++ sc->sc_drammodel = 1; ++ return (0); ++ } ++ ++ return (0); ++} ++ ++#define HIFN_SRAM_MAX (32 << 20) ++#define HIFN_SRAM_STEP_SIZE 16384 ++#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) ++ ++static int ++hifn_sramsize(struct hifn_softc *sc) ++{ ++ u_int32_t a; ++ u_int8_t data[8]; ++ u_int8_t dataexpect[sizeof(data)]; ++ int32_t i; ++ ++ for (i = 0; i < sizeof(data); i++) ++ data[i] = dataexpect[i] = i ^ 0x5a; ++ ++ for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { ++ a = i * HIFN_SRAM_STEP_SIZE; ++ bcopy(&i, data, sizeof(i)); ++ hifn_writeramaddr(sc, a, data); ++ } ++ ++ for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { ++ a = i * HIFN_SRAM_STEP_SIZE; ++ bcopy(&i, dataexpect, sizeof(i)); ++ if (hifn_readramaddr(sc, a, data) < 0) ++ return (0); ++ if (bcmp(data, dataexpect, sizeof(data)) != 0) ++ return (0); ++ sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; ++ } ++ ++ return (0); ++} ++ ++/* ++ * XXX For dram boards, one should really try all of the ++ * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG ++ * is already set up correctly. ++ */ ++static int ++hifn_dramsize(struct hifn_softc *sc) ++{ ++ u_int32_t cnfg; ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ /* ++ * 7955/7956 have a fixed internal ram of only 32K. ++ */ ++ sc->sc_ramsize = 32768; ++ } else { ++ cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & ++ HIFN_PUCNFG_DRAMMASK; ++ sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); ++ } ++ return (0); ++} ++ ++static void ++hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (dma->cmdi == HIFN_D_CMD_RSIZE) { ++ dma->cmdi = 0; ++ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *cmdp = dma->cmdi++; ++ dma->cmdk = dma->cmdi; ++ ++ if (dma->srci == HIFN_D_SRC_RSIZE) { ++ dma->srci = 0; ++ dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->srcr[HIFN_D_SRC_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *srcp = dma->srci++; ++ dma->srck = dma->srci; ++ ++ if (dma->dsti == HIFN_D_DST_RSIZE) { ++ dma->dsti = 0; ++ dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->dstr[HIFN_D_DST_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *dstp = dma->dsti++; ++ dma->dstk = dma->dsti; ++ ++ if (dma->resi == HIFN_D_RES_RSIZE) { ++ dma->resi = 0; ++ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *resp = dma->resi++; ++ dma->resk = dma->resi; ++} ++ ++static int ++hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ hifn_base_command_t wc; ++ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; ++ int r, cmdi, resi, srci, dsti; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ wc.masks = htole16(3 << 13); ++ wc.session_num = htole16(addr >> 14); ++ wc.total_source_count = htole16(8); ++ wc.total_dest_count = htole16(addr & 0x3fff); ++ ++ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | ++ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); ++ ++ /* build write command */ ++ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); ++ *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; ++ bcopy(data, &dma->test_src, sizeof(dma->test_src)); ++ ++ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr ++ + offsetof(struct hifn_dma, test_src)); ++ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr ++ + offsetof(struct hifn_dma, test_dst)); ++ ++ dma->cmdr[cmdi].l = htole32(16 | masks); ++ dma->srcr[srci].l = htole32(8 | masks); ++ dma->dstr[dsti].l = htole32(4 | masks); ++ dma->resr[resi].l = htole32(4 | masks); ++ ++ for (r = 10000; r >= 0; r--) { ++ DELAY(10); ++ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) ++ break; ++ } ++ if (r == 0) { ++ device_printf(sc->sc_dev, "writeramaddr -- " ++ "result[%d](addr %d) still valid\n", resi, addr); ++ r = -1; ++ return (-1); ++ } else ++ r = 0; ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | ++ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); ++ ++ return (r); ++} ++ ++static int ++hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ hifn_base_command_t rc; ++ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; ++ int r, cmdi, srci, dsti, resi; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ rc.masks = htole16(2 << 13); ++ rc.session_num = htole16(addr >> 14); ++ rc.total_source_count = htole16(addr & 0x3fff); ++ rc.total_dest_count = htole16(8); ++ ++ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | ++ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); ++ ++ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); ++ *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; ++ ++ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, test_src)); ++ dma->test_src = 0; ++ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, test_dst)); ++ dma->test_dst = 0; ++ dma->cmdr[cmdi].l = htole32(8 | masks); ++ dma->srcr[srci].l = htole32(8 | masks); ++ dma->dstr[dsti].l = htole32(8 | masks); ++ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); ++ ++ for (r = 10000; r >= 0; r--) { ++ DELAY(10); ++ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) ++ break; ++ } ++ if (r == 0) { ++ device_printf(sc->sc_dev, "readramaddr -- " ++ "result[%d](addr %d) still valid\n", resi, addr); ++ r = -1; ++ } else { ++ r = 0; ++ bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); ++ } ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | ++ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); ++ ++ return (r); ++} ++ ++/* ++ * Initialize the descriptor rings. ++ */ ++static void ++hifn_init_dma(struct hifn_softc *sc) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ hifn_set_retry(sc); ++ ++ /* initialize static pointer values */ ++ for (i = 0; i < HIFN_D_CMD_RSIZE; i++) ++ dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, command_bufs[i][0])); ++ for (i = 0; i < HIFN_D_RES_RSIZE; i++) ++ dma->resr[i].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, result_bufs[i][0])); ++ ++ dma->cmdr[HIFN_D_CMD_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); ++ dma->srcr[HIFN_D_SRC_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); ++ dma->dstr[HIFN_D_DST_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); ++ dma->resr[HIFN_D_RES_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); ++ ++ dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; ++ dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; ++ dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; ++} ++ ++/* ++ * Writes out the raw command buffer space. Returns the ++ * command buffer size. ++ */ ++static u_int ++hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) ++{ ++ struct hifn_softc *sc = NULL; ++ u_int8_t *buf_pos; ++ hifn_base_command_t *base_cmd; ++ hifn_mac_command_t *mac_cmd; ++ hifn_crypt_command_t *cry_cmd; ++ int using_mac, using_crypt, len, ivlen; ++ u_int32_t dlen, slen; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf_pos = buf; ++ using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; ++ using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; ++ ++ base_cmd = (hifn_base_command_t *)buf_pos; ++ base_cmd->masks = htole16(cmd->base_masks); ++ slen = cmd->src_mapsize; ++ if (cmd->sloplen) ++ dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); ++ else ++ dlen = cmd->dst_mapsize; ++ base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); ++ base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); ++ dlen >>= 16; ++ slen >>= 16; ++ base_cmd->session_num = htole16( ++ ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | ++ ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); ++ buf_pos += sizeof(hifn_base_command_t); ++ ++ if (using_mac) { ++ mac_cmd = (hifn_mac_command_t *)buf_pos; ++ dlen = cmd->maccrd->crd_len; ++ mac_cmd->source_count = htole16(dlen & 0xffff); ++ dlen >>= 16; ++ mac_cmd->masks = htole16(cmd->mac_masks | ++ ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); ++ mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); ++ mac_cmd->reserved = 0; ++ buf_pos += sizeof(hifn_mac_command_t); ++ } ++ ++ if (using_crypt) { ++ cry_cmd = (hifn_crypt_command_t *)buf_pos; ++ dlen = cmd->enccrd->crd_len; ++ cry_cmd->source_count = htole16(dlen & 0xffff); ++ dlen >>= 16; ++ cry_cmd->masks = htole16(cmd->cry_masks | ++ ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); ++ cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); ++ cry_cmd->reserved = 0; ++ buf_pos += sizeof(hifn_crypt_command_t); ++ } ++ ++ if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { ++ bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); ++ buf_pos += HIFN_MAC_KEY_LENGTH; ++ } ++ ++ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { ++ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { ++ case HIFN_CRYPT_CMD_ALG_3DES: ++ bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); ++ buf_pos += HIFN_3DES_KEY_LENGTH; ++ break; ++ case HIFN_CRYPT_CMD_ALG_DES: ++ bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); ++ buf_pos += HIFN_DES_KEY_LENGTH; ++ break; ++ case HIFN_CRYPT_CMD_ALG_RC4: ++ len = 256; ++ do { ++ int clen; ++ ++ clen = MIN(cmd->cklen, len); ++ bcopy(cmd->ck, buf_pos, clen); ++ len -= clen; ++ buf_pos += clen; ++ } while (len > 0); ++ bzero(buf_pos, 4); ++ buf_pos += 4; ++ break; ++ case HIFN_CRYPT_CMD_ALG_AES: ++ /* ++ * AES keys are variable 128, 192 and ++ * 256 bits (16, 24 and 32 bytes). ++ */ ++ bcopy(cmd->ck, buf_pos, cmd->cklen); ++ buf_pos += cmd->cklen; ++ break; ++ } ++ } ++ ++ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { ++ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { ++ case HIFN_CRYPT_CMD_ALG_AES: ++ ivlen = HIFN_AES_IV_LENGTH; ++ break; ++ default: ++ ivlen = HIFN_IV_LENGTH; ++ break; ++ } ++ bcopy(cmd->iv, buf_pos, ivlen); ++ buf_pos += ivlen; ++ } ++ ++ if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { ++ bzero(buf_pos, 8); ++ buf_pos += 8; ++ } ++ ++ return (buf_pos - buf); ++} ++ ++static int ++hifn_dmamap_aligned(struct hifn_operand *op) ++{ ++ struct hifn_softc *sc = NULL; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ for (i = 0; i < op->nsegs; i++) { ++ if (op->segs[i].ds_addr & 3) ++ return (0); ++ if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) ++ return (0); ++ } ++ return (1); ++} ++ ++static __inline int ++hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ ++ if (++idx == HIFN_D_DST_RSIZE) { ++ dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | ++ HIFN_D_MASKDONEIRQ); ++ HIFN_DSTR_SYNC(sc, idx, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ idx = 0; ++ } ++ return (idx); ++} ++ ++static int ++hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct hifn_operand *dst = &cmd->dst; ++ u_int32_t p, l; ++ int idx, used = 0, i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ idx = dma->dsti; ++ for (i = 0; i < dst->nsegs - 1; i++) { ++ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); ++ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); ++ wmb(); ++ dma->dstr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, idx, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ used++; ++ ++ idx = hifn_dmamap_dstwrap(sc, idx); ++ } ++ ++ if (cmd->sloplen == 0) { ++ p = dst->segs[i].ds_addr; ++ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | ++ dst->segs[i].ds_len; ++ } else { ++ p = sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, slop[cmd->slopidx]); ++ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | ++ sizeof(u_int32_t); ++ ++ if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { ++ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); ++ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | ++ (dst->segs[i].ds_len - cmd->sloplen)); ++ wmb(); ++ dma->dstr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, idx, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ used++; ++ ++ idx = hifn_dmamap_dstwrap(sc, idx); ++ } ++ } ++ dma->dstr[idx].p = htole32(p); ++ dma->dstr[idx].l = htole32(l); ++ wmb(); ++ dma->dstr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ used++; ++ ++ idx = hifn_dmamap_dstwrap(sc, idx); ++ ++ dma->dsti = idx; ++ dma->dstu += used; ++ return (idx); ++} ++ ++static __inline int ++hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ ++ if (++idx == HIFN_D_SRC_RSIZE) { ++ dma->srcr[idx].l = htole32(HIFN_D_VALID | ++ HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); ++ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ idx = 0; ++ } ++ return (idx); ++} ++ ++static int ++hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct hifn_operand *src = &cmd->src; ++ int idx, i; ++ u_int32_t last = 0; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ idx = dma->srci; ++ for (i = 0; i < src->nsegs; i++) { ++ if (i == src->nsegs - 1) ++ last = HIFN_D_LAST; ++ ++ dma->srcr[idx].p = htole32(src->segs[i].ds_addr); ++ dma->srcr[idx].l = htole32(src->segs[i].ds_len | ++ HIFN_D_MASKDONEIRQ | last); ++ wmb(); ++ dma->srcr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_SRCR_SYNC(sc, idx, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ ++ idx = hifn_dmamap_srcwrap(sc, idx); ++ } ++ dma->srci = idx; ++ dma->srcu += src->nsegs; ++ return (idx); ++} ++ ++ ++static int ++hifn_crypto( ++ struct hifn_softc *sc, ++ struct hifn_command *cmd, ++ struct cryptop *crp, ++ int hint) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ u_int32_t cmdlen, csr; ++ int cmdi, resi, err = 0; ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* ++ * need 1 cmd, and 1 res ++ * ++ * NB: check this first since it's easy. ++ */ ++ HIFN_LOCK(sc); ++ if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || ++ (dma->resu + 1) > HIFN_D_RES_RSIZE) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "cmd/result exhaustion, cmdu %u resu %u\n", ++ dma->cmdu, dma->resu); ++ } ++#endif ++ hifnstats.hst_nomem_cr++; ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ HIFN_UNLOCK(sc); ++ return (ERESTART); ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (pci_map_skb(sc, &cmd->src, cmd->src_skb)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_srcmap1; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (pci_map_uio(sc, &cmd->src, cmd->src_io)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_srcmap1; ++ } ++ } else { ++ if (pci_map_buf(sc, &cmd->src, cmd->src_buf, crp->crp_ilen)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_srcmap1; ++ } ++ } ++ ++ if (hifn_dmamap_aligned(&cmd->src)) { ++ cmd->sloplen = cmd->src_mapsize & 3; ++ cmd->dst = cmd->src; ++ } else { ++ if (crp->crp_flags & CRYPTO_F_IOV) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto err_srcmap; ++ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { ++#ifdef NOTYET ++ int totlen, len; ++ struct mbuf *m, *m0, *mlast; ++ ++ KASSERT(cmd->dst_m == cmd->src_m, ++ ("hifn_crypto: dst_m initialized improperly")); ++ hifnstats.hst_unaligned++; ++ /* ++ * Source is not aligned on a longword boundary. ++ * Copy the data to insure alignment. If we fail ++ * to allocate mbufs or clusters while doing this ++ * we return ERESTART so the operation is requeued ++ * at the crypto later, but only if there are ++ * ops already posted to the hardware; otherwise we ++ * have no guarantee that we'll be re-entered. ++ */ ++ totlen = cmd->src_mapsize; ++ if (cmd->src_m->m_flags & M_PKTHDR) { ++ len = MHLEN; ++ MGETHDR(m0, M_DONTWAIT, MT_DATA); ++ if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { ++ m_free(m0); ++ m0 = NULL; ++ } ++ } else { ++ len = MLEN; ++ MGET(m0, M_DONTWAIT, MT_DATA); ++ } ++ if (m0 == NULL) { ++ hifnstats.hst_nomem_mbuf++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ goto err_srcmap; ++ } ++ if (totlen >= MINCLSIZE) { ++ MCLGET(m0, M_DONTWAIT); ++ if ((m0->m_flags & M_EXT) == 0) { ++ hifnstats.hst_nomem_mcl++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ m_freem(m0); ++ goto err_srcmap; ++ } ++ len = MCLBYTES; ++ } ++ totlen -= len; ++ m0->m_pkthdr.len = m0->m_len = len; ++ mlast = m0; ++ ++ while (totlen > 0) { ++ MGET(m, M_DONTWAIT, MT_DATA); ++ if (m == NULL) { ++ hifnstats.hst_nomem_mbuf++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ m_freem(m0); ++ goto err_srcmap; ++ } ++ len = MLEN; ++ if (totlen >= MINCLSIZE) { ++ MCLGET(m, M_DONTWAIT); ++ if ((m->m_flags & M_EXT) == 0) { ++ hifnstats.hst_nomem_mcl++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ mlast->m_next = m; ++ m_freem(m0); ++ goto err_srcmap; ++ } ++ len = MCLBYTES; ++ } ++ ++ m->m_len = len; ++ m0->m_pkthdr.len += len; ++ totlen -= len; ++ ++ mlast->m_next = m; ++ mlast = m; ++ } ++ cmd->dst_m = m0; ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", ++ __FILE__, __LINE__); ++ err = EINVAL; ++ goto err_srcmap; ++#endif ++ } else { ++ device_printf(sc->sc_dev, ++ "%s,%d: unaligned contig buffers not implemented\n", ++ __FILE__, __LINE__); ++ err = EINVAL; ++ goto err_srcmap; ++ } ++ } ++ ++ if (cmd->dst_map == NULL) { ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (pci_map_skb(sc, &cmd->dst, cmd->dst_skb)) { ++ hifnstats.hst_nomem_map++; ++ err = ENOMEM; ++ goto err_dstmap1; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (pci_map_uio(sc, &cmd->dst, cmd->dst_io)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_dstmap1; ++ } ++ } else { ++ if (pci_map_buf(sc, &cmd->dst, cmd->dst_buf, crp->crp_ilen)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_dstmap1; ++ } ++ } ++ } ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", ++ READ_REG_1(sc, HIFN_1_DMA_CSR), ++ READ_REG_1(sc, HIFN_1_DMA_IER), ++ dma->cmdu, dma->srcu, dma->dstu, dma->resu, ++ cmd->src_nsegs, cmd->dst_nsegs); ++ } ++#endif ++ ++#if 0 ++ if (cmd->src_map == cmd->dst_map) { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); ++ } else { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_PREWRITE); ++ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, ++ BUS_DMASYNC_PREREAD); ++ } ++#endif ++ ++ /* ++ * need N src, and N dst ++ */ ++ if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || ++ (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", ++ dma->srcu, cmd->src_nsegs, ++ dma->dstu, cmd->dst_nsegs); ++ } ++#endif ++ hifnstats.hst_nomem_sd++; ++ err = ERESTART; ++ goto err_dstmap; ++ } ++ ++ if (dma->cmdi == HIFN_D_CMD_RSIZE) { ++ dma->cmdi = 0; ++ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ cmdi = dma->cmdi++; ++ cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); ++ HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); ++ ++ /* .p for command/result already set */ ++ dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_LAST | ++ HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->cmdr[cmdi].l |= htole32(HIFN_D_VALID); ++ HIFN_CMDR_SYNC(sc, cmdi, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ dma->cmdu++; ++ ++ /* ++ * We don't worry about missing an interrupt (which a "command wait" ++ * interrupt salvages us from), unless there is more than one command ++ * in the queue. ++ */ ++ if (dma->cmdu > 1) { ++ sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++ } ++ ++ hifnstats.hst_ipackets++; ++ hifnstats.hst_ibytes += cmd->src_mapsize; ++ ++ hifn_dmamap_load_src(sc, cmd); ++ ++ /* ++ * Unlike other descriptors, we don't mask done interrupt from ++ * result descriptor. ++ */ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, "load res\n"); ++#endif ++ if (dma->resi == HIFN_D_RES_RSIZE) { ++ dma->resi = 0; ++ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ } ++ resi = dma->resi++; ++ KASSERT(dma->hifn_commands[resi] == NULL, ++ ("hifn_crypto: command slot %u busy", resi)); ++ dma->hifn_commands[resi] = cmd; ++ HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); ++ if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { ++ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | ++ HIFN_D_LAST | HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->resr[resi].l |= htole32(HIFN_D_VALID); ++ sc->sc_curbatch++; ++ if (sc->sc_curbatch > hifnstats.hst_maxbatch) ++ hifnstats.hst_maxbatch = sc->sc_curbatch; ++ hifnstats.hst_totbatch++; ++ } else { ++ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | HIFN_D_LAST); ++ wmb(); ++ dma->resr[resi].l |= htole32(HIFN_D_VALID); ++ sc->sc_curbatch = 0; ++ } ++ HIFN_RESR_SYNC(sc, resi, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ dma->resu++; ++ ++ if (cmd->sloplen) ++ cmd->slopidx = resi; ++ ++ hifn_dmamap_load_dst(sc, cmd); ++ ++ csr = 0; ++ if (sc->sc_c_busy == 0) { ++ csr |= HIFN_DMACSR_C_CTRL_ENA; ++ sc->sc_c_busy = 1; ++ } ++ if (sc->sc_s_busy == 0) { ++ csr |= HIFN_DMACSR_S_CTRL_ENA; ++ sc->sc_s_busy = 1; ++ } ++ if (sc->sc_r_busy == 0) { ++ csr |= HIFN_DMACSR_R_CTRL_ENA; ++ sc->sc_r_busy = 1; ++ } ++ if (sc->sc_d_busy == 0) { ++ csr |= HIFN_DMACSR_D_CTRL_ENA; ++ sc->sc_d_busy = 1; ++ } ++ if (csr) ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", ++ READ_REG_1(sc, HIFN_1_DMA_CSR), ++ READ_REG_1(sc, HIFN_1_DMA_IER)); ++ } ++#endif ++ ++ sc->sc_active = 5; ++ HIFN_UNLOCK(sc); ++ KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); ++ return (err); /* success */ ++ ++err_dstmap: ++ if (cmd->src_map != cmd->dst_map) ++ pci_unmap_buf(sc, &cmd->dst); ++err_dstmap1: ++err_srcmap: ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (cmd->src_skb != cmd->dst_skb) ++#ifdef NOTYET ++ m_freem(cmd->dst_m); ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", ++ __FILE__, __LINE__); ++#endif ++ } ++ pci_unmap_buf(sc, &cmd->src); ++err_srcmap1: ++ HIFN_UNLOCK(sc); ++ return (err); ++} ++ ++static void ++hifn_tick(unsigned long arg) ++{ ++ struct hifn_softc *sc; ++ unsigned long l_flags; ++ ++ if (arg >= HIFN_MAX_CHIPS) ++ return; ++ sc = hifn_chip_idx[arg]; ++ if (!sc) ++ return; ++ ++ HIFN_LOCK(sc); ++ if (sc->sc_active == 0) { ++ struct hifn_dma *dma = sc->sc_dma; ++ u_int32_t r = 0; ++ ++ if (dma->cmdu == 0 && sc->sc_c_busy) { ++ sc->sc_c_busy = 0; ++ r |= HIFN_DMACSR_C_CTRL_DIS; ++ } ++ if (dma->srcu == 0 && sc->sc_s_busy) { ++ sc->sc_s_busy = 0; ++ r |= HIFN_DMACSR_S_CTRL_DIS; ++ } ++ if (dma->dstu == 0 && sc->sc_d_busy) { ++ sc->sc_d_busy = 0; ++ r |= HIFN_DMACSR_D_CTRL_DIS; ++ } ++ if (dma->resu == 0 && sc->sc_r_busy) { ++ sc->sc_r_busy = 0; ++ r |= HIFN_DMACSR_R_CTRL_DIS; ++ } ++ if (r) ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); ++ } else ++ sc->sc_active--; ++ HIFN_UNLOCK(sc); ++ mod_timer(&sc->sc_tickto, jiffies + HZ); ++} ++ ++static irqreturn_t ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++hifn_intr(int irq, void *arg) ++#else ++hifn_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct hifn_softc *sc = arg; ++ struct hifn_dma *dma; ++ u_int32_t dmacsr, restart; ++ int i, u; ++ unsigned long l_flags; ++ ++ dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); ++ ++ /* Nothing in the DMA unit interrupted */ ++ if ((dmacsr & sc->sc_dmaier) == 0) ++ return IRQ_NONE; ++ ++ HIFN_LOCK(sc); ++ ++ dma = sc->sc_dma; ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", ++ dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, ++ dma->cmdi, dma->srci, dma->dsti, dma->resi, ++ dma->cmdk, dma->srck, dma->dstk, dma->resk, ++ dma->cmdu, dma->srcu, dma->dstu, dma->resu); ++ } ++#endif ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); ++ ++ if ((sc->sc_flags & HIFN_HAS_PUBLIC) && ++ (dmacsr & HIFN_DMACSR_PUBDONE)) ++ WRITE_REG_1(sc, HIFN_1_PUB_STATUS, ++ READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); ++ ++ restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); ++ if (restart) ++ device_printf(sc->sc_dev, "overrun %x\n", dmacsr); ++ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ if (dmacsr & HIFN_DMACSR_ILLR) ++ device_printf(sc->sc_dev, "illegal read\n"); ++ if (dmacsr & HIFN_DMACSR_ILLW) ++ device_printf(sc->sc_dev, "illegal write\n"); ++ } ++ ++ restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | ++ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); ++ if (restart) { ++ device_printf(sc->sc_dev, "abort, resetting.\n"); ++ hifnstats.hst_abort++; ++ hifn_abort(sc); ++ HIFN_UNLOCK(sc); ++ return IRQ_HANDLED; ++ } ++ ++ if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { ++ /* ++ * If no slots to process and we receive a "waiting on ++ * command" interrupt, we disable the "waiting on command" ++ * (by clearing it). ++ */ ++ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++ } ++ ++ /* clear the rings */ ++ i = dma->resk; u = dma->resu; ++ while (u != 0) { ++ HIFN_RESR_SYNC(sc, i, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ if (dma->resr[i].l & htole32(HIFN_D_VALID)) { ++ HIFN_RESR_SYNC(sc, i, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ break; ++ } ++ ++ if (i != HIFN_D_RES_RSIZE) { ++ struct hifn_command *cmd; ++ u_int8_t *macbuf = NULL; ++ ++ HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); ++ cmd = dma->hifn_commands[i]; ++ KASSERT(cmd != NULL, ++ ("hifn_intr: null command slot %u", i)); ++ dma->hifn_commands[i] = NULL; ++ ++ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { ++ macbuf = dma->result_bufs[i]; ++ macbuf += 12; ++ } ++ ++ hifn_callback(sc, cmd, macbuf); ++ hifnstats.hst_opackets++; ++ u--; ++ } ++ ++ if (++i == (HIFN_D_RES_RSIZE + 1)) ++ i = 0; ++ } ++ dma->resk = i; dma->resu = u; ++ ++ i = dma->srck; u = dma->srcu; ++ while (u != 0) { ++ if (i == HIFN_D_SRC_RSIZE) ++ i = 0; ++ HIFN_SRCR_SYNC(sc, i, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { ++ HIFN_SRCR_SYNC(sc, i, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ break; ++ } ++ i++, u--; ++ } ++ dma->srck = i; dma->srcu = u; ++ ++ i = dma->cmdk; u = dma->cmdu; ++ while (u != 0) { ++ HIFN_CMDR_SYNC(sc, i, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { ++ HIFN_CMDR_SYNC(sc, i, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ break; ++ } ++ if (i != HIFN_D_CMD_RSIZE) { ++ u--; ++ HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); ++ } ++ if (++i == (HIFN_D_CMD_RSIZE + 1)) ++ i = 0; ++ } ++ dma->cmdk = i; dma->cmdu = u; ++ ++ HIFN_UNLOCK(sc); ++ ++ if (sc->sc_needwakeup) { /* XXX check high watermark */ ++ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, ++ "wakeup crypto (%x) u %d/%d/%d/%d\n", ++ sc->sc_needwakeup, ++ dma->cmdu, dma->srcu, dma->dstu, dma->resu); ++#endif ++ sc->sc_needwakeup &= ~wakeup; ++ crypto_unblock(sc->sc_cid, wakeup); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Allocate a new 'session' and return an encoded session id. 'sidp' ++ * contains our registration id, and should contain an encoded session ++ * id on successful allocation. ++ */ ++static int ++hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct hifn_softc *sc = device_get_softc(dev); ++ struct cryptoini *c; ++ int mac = 0, cry = 0, sesn; ++ struct hifn_session *ses = NULL; ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ KASSERT(sc != NULL, ("hifn_newsession: null softc")); ++ if (sidp == NULL || cri == NULL || sc == NULL) { ++ DPRINTF("%s,%d: %s - EINVAL\n", __FILE__, __LINE__, __FUNCTION__); ++ return (EINVAL); ++ } ++ ++ HIFN_LOCK(sc); ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct hifn_session *)kmalloc(sizeof(*ses), ++ SLAB_ATOMIC); ++ if (ses == NULL) { ++ HIFN_UNLOCK(sc); ++ return (ENOMEM); ++ } ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (!sc->sc_sessions[sesn].hs_used) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sesn = sc->sc_nsessions; ++ ses = (struct hifn_session *)kmalloc((sesn + 1) * sizeof(*ses), ++ SLAB_ATOMIC); ++ if (ses == NULL) { ++ HIFN_UNLOCK(sc); ++ return (ENOMEM); ++ } ++ bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); ++ bzero(sc->sc_sessions, sesn * sizeof(*ses)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ HIFN_UNLOCK(sc); ++ ++ bzero(ses, sizeof(*ses)); ++ ses->hs_used = 1; ++ ++ for (c = cri; c != NULL; c = c->cri_next) { ++ switch (c->cri_alg) { ++ case CRYPTO_MD5: ++ case CRYPTO_SHA1: ++ case CRYPTO_MD5_HMAC: ++ case CRYPTO_SHA1_HMAC: ++ if (mac) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ mac = 1; ++ ses->hs_mlen = c->cri_mlen; ++ if (ses->hs_mlen == 0) { ++ switch (c->cri_alg) { ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ ses->hs_mlen = 16; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ ses->hs_mlen = 20; ++ break; ++ } ++ } ++ break; ++ case CRYPTO_DES_CBC: ++ case CRYPTO_3DES_CBC: ++ case CRYPTO_AES_CBC: ++ /* XXX this may read fewer, does it matter? */ ++ read_random(ses->hs_iv, ++ c->cri_alg == CRYPTO_AES_CBC ? ++ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); ++ /*FALLTHROUGH*/ ++ case CRYPTO_ARC4: ++ if (cry) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ cry = 1; ++ break; ++ default: ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ } ++ if (mac == 0 && cry == 0) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ ++ *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); ++ ++ return (0); ++} ++ ++/* ++ * Deallocate a session. ++ * XXX this routine should run a zero'd mac/encrypt key into context ram. ++ * XXX to blow away any keys already stored there. ++ */ ++static int ++hifn_freesession(device_t dev, u_int64_t tid) ++{ ++ struct hifn_softc *sc = device_get_softc(dev); ++ int session, error; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ KASSERT(sc != NULL, ("hifn_freesession: null softc")); ++ if (sc == NULL) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ ++ HIFN_LOCK(sc); ++ session = HIFN_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); ++ error = 0; ++ } else { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ error = EINVAL; ++ } ++ HIFN_UNLOCK(sc); ++ ++ return (error); ++} ++ ++static int ++hifn_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct hifn_softc *sc = device_get_softc(dev); ++ struct hifn_command *cmd = NULL; ++ int session, err, ivlen; ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (crp == NULL || crp->crp_callback == NULL) { ++ hifnstats.hst_invalid++; ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ session = HIFN_SESSION(crp->crp_sid); ++ ++ if (sc == NULL || session >= sc->sc_nsessions) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ ++ cmd = kmalloc(sizeof(struct hifn_command), SLAB_ATOMIC); ++ if (cmd == NULL) { ++ hifnstats.hst_nomem++; ++ err = ENOMEM; ++ goto errout; ++ } ++ memset(cmd, 0, sizeof(*cmd)); ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ cmd->src_skb = (struct sk_buff *)crp->crp_buf; ++ cmd->dst_skb = (struct sk_buff *)crp->crp_buf; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ cmd->src_io = (struct uio *)crp->crp_buf; ++ cmd->dst_io = (struct uio *)crp->crp_buf; ++ } else { ++ cmd->src_buf = crp->crp_buf; ++ cmd->dst_buf = crp->crp_buf; ++ } ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ if (crd2 == NULL) { ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1 || ++ crd1->crd_alg == CRYPTO_MD5) { ++ maccrd = crd1; ++ enccrd = NULL; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4) { ++ if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) ++ cmd->base_masks |= HIFN_BASE_CMD_DECODE; ++ maccrd = NULL; ++ enccrd = crd1; ++ } else { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_MD5 || ++ crd1->crd_alg == CRYPTO_SHA1) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC || ++ crd2->crd_alg == CRYPTO_ARC4) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ cmd->base_masks = HIFN_BASE_CMD_DECODE; ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4 || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC || ++ crd2->crd_alg == CRYPTO_MD5 || ++ crd2->crd_alg == CRYPTO_SHA1) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ /* ++ * We cannot order the 7751 as requested ++ */ ++ DPRINTF("%s,%d: %s %d,%d,%d - EINVAL\n",__FILE__,__LINE__,__FUNCTION__, crd1->crd_alg, crd2->crd_alg, crd1->crd_flags & CRD_F_ENCRYPT); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ ++ if (enccrd) { ++ cmd->enccrd = enccrd; ++ cmd->base_masks |= HIFN_BASE_CMD_CRYPT; ++ switch (enccrd->crd_alg) { ++ case CRYPTO_ARC4: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; ++ break; ++ case CRYPTO_DES_CBC: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | ++ HIFN_CRYPT_CMD_MODE_CBC | ++ HIFN_CRYPT_CMD_NEW_IV; ++ break; ++ case CRYPTO_3DES_CBC: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | ++ HIFN_CRYPT_CMD_MODE_CBC | ++ HIFN_CRYPT_CMD_NEW_IV; ++ break; ++ case CRYPTO_AES_CBC: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | ++ HIFN_CRYPT_CMD_MODE_CBC | ++ HIFN_CRYPT_CMD_NEW_IV; ++ break; ++ default: ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ if (enccrd->crd_alg != CRYPTO_ARC4) { ++ ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? ++ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ bcopy(enccrd->crd_iv, cmd->iv, ivlen); ++ else ++ bcopy(sc->sc_sessions[session].hs_iv, ++ cmd->iv, ivlen); ++ ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) ++ == 0) { ++ crypto_copyback(crp->crp_flags, ++ crp->crp_buf, enccrd->crd_inject, ++ ivlen, cmd->iv); ++ } ++ } else { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ bcopy(enccrd->crd_iv, cmd->iv, ivlen); ++ else { ++ crypto_copydata(crp->crp_flags, ++ crp->crp_buf, enccrd->crd_inject, ++ ivlen, cmd->iv); ++ } ++ } ++ } ++ ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) ++ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; ++ cmd->ck = enccrd->crd_key; ++ cmd->cklen = enccrd->crd_klen >> 3; ++ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; ++ ++ /* ++ * Need to specify the size for the AES key in the masks. ++ */ ++ if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == ++ HIFN_CRYPT_CMD_ALG_AES) { ++ switch (cmd->cklen) { ++ case 16: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; ++ break; ++ case 24: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; ++ break; ++ case 32: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; ++ break; ++ default: ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ } ++ ++ if (maccrd) { ++ cmd->maccrd = maccrd; ++ cmd->base_masks |= HIFN_BASE_CMD_MAC; ++ ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | ++ HIFN_MAC_CMD_POS_IPSEC; ++ break; ++ case CRYPTO_MD5_HMAC: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | ++ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; ++ break; ++ case CRYPTO_SHA1: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | ++ HIFN_MAC_CMD_POS_IPSEC; ++ break; ++ case CRYPTO_SHA1_HMAC: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | ++ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; ++ break; ++ } ++ ++ if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || ++ maccrd->crd_alg == CRYPTO_MD5_HMAC) { ++ cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; ++ bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); ++ bzero(cmd->mac + (maccrd->crd_klen >> 3), ++ HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); ++ } ++ } ++ ++ cmd->crp = crp; ++ cmd->session_num = session; ++ cmd->softc = sc; ++ ++ err = hifn_crypto(sc, cmd, crp, hint); ++ if (!err) { ++ return 0; ++ } else if (err == ERESTART) { ++ /* ++ * There weren't enough resources to dispatch the request ++ * to the part. Notify the caller so they'll requeue this ++ * request and resubmit it again soon. ++ */ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, "requeue request\n"); ++#endif ++ kfree(cmd); ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ return (err); ++ } ++ ++errout: ++ if (cmd != NULL) ++ kfree(cmd); ++ if (err == EINVAL) ++ hifnstats.hst_invalid++; ++ else ++ hifnstats.hst_nomem++; ++ crp->crp_etype = err; ++ crypto_done(crp); ++ return (err); ++} ++ ++static void ++hifn_abort(struct hifn_softc *sc) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct hifn_command *cmd; ++ struct cryptop *crp; ++ int i, u; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ i = dma->resk; u = dma->resu; ++ while (u != 0) { ++ cmd = dma->hifn_commands[i]; ++ KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); ++ dma->hifn_commands[i] = NULL; ++ crp = cmd->crp; ++ ++ if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { ++ /* Salvage what we can. */ ++ u_int8_t *macbuf; ++ ++ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { ++ macbuf = dma->result_bufs[i]; ++ macbuf += 12; ++ } else ++ macbuf = NULL; ++ hifnstats.hst_opackets++; ++ hifn_callback(sc, cmd, macbuf); ++ } else { ++#if 0 ++ if (cmd->src_map == cmd->dst_map) { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); ++ } else { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, ++ BUS_DMASYNC_POSTREAD); ++ } ++#endif ++ ++ if (cmd->src_skb != cmd->dst_skb) { ++#ifdef NOTYET ++ m_freem(cmd->src_m); ++ crp->crp_buf = (caddr_t)cmd->dst_m; ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", ++ __FILE__, __LINE__); ++#endif ++ } ++ ++ /* non-shared buffers cannot be restarted */ ++ if (cmd->src_map != cmd->dst_map) { ++ /* ++ * XXX should be EAGAIN, delayed until ++ * after the reset. ++ */ ++ crp->crp_etype = ENOMEM; ++ pci_unmap_buf(sc, &cmd->dst); ++ } else ++ crp->crp_etype = ENOMEM; ++ ++ pci_unmap_buf(sc, &cmd->src); ++ ++ kfree(cmd); ++ if (crp->crp_etype != EAGAIN) ++ crypto_done(crp); ++ } ++ ++ if (++i == HIFN_D_RES_RSIZE) ++ i = 0; ++ u--; ++ } ++ dma->resk = i; dma->resu = u; ++ ++ hifn_reset_board(sc, 1); ++ hifn_init_dma(sc); ++ hifn_init_pci_registers(sc); ++} ++ ++static void ++hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct cryptop *crp = cmd->crp; ++ struct cryptodesc *crd; ++ int i, u, ivlen; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++#if 0 ++ if (cmd->src_map == cmd->dst_map) { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); ++ } else { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, ++ BUS_DMASYNC_POSTREAD); ++ } ++#endif ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (cmd->src_skb != cmd->dst_skb) { ++#ifdef NOTYET ++ crp->crp_buf = (caddr_t)cmd->dst_m; ++ totlen = cmd->src_mapsize; ++ for (m = cmd->dst_m; m != NULL; m = m->m_next) { ++ if (totlen < m->m_len) { ++ m->m_len = totlen; ++ totlen = 0; ++ } else ++ totlen -= m->m_len; ++ } ++ cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; ++ m_freem(cmd->src_m); ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", ++ __FILE__, __LINE__); ++#endif ++ } ++ } ++ ++ if (cmd->sloplen != 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ cmd->src_mapsize - cmd->sloplen, cmd->sloplen, ++ (caddr_t)&dma->slop[cmd->slopidx]); ++ } ++ ++ i = dma->dstk; u = dma->dstu; ++ while (u != 0) { ++ if (i == HIFN_D_DST_RSIZE) ++ i = 0; ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++#endif ++ if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++#endif ++ break; ++ } ++ i++, u--; ++ } ++ dma->dstk = i; dma->dstu = u; ++ ++ hifnstats.hst_obytes += cmd->dst_mapsize; ++ ++ if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == ++ HIFN_BASE_CMD_CRYPT) { ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ if (crd->crd_alg != CRYPTO_DES_CBC && ++ crd->crd_alg != CRYPTO_3DES_CBC && ++ crd->crd_alg != CRYPTO_AES_CBC) ++ continue; ++ ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? ++ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ crd->crd_skip + crd->crd_len - ivlen, ivlen, ++ cmd->softc->sc_sessions[cmd->session_num].hs_iv); ++ break; ++ } ++ } ++ ++ if (macbuf != NULL) { ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ int len; ++ ++ if (crd->crd_alg != CRYPTO_MD5 && ++ crd->crd_alg != CRYPTO_SHA1 && ++ crd->crd_alg != CRYPTO_MD5_HMAC && ++ crd->crd_alg != CRYPTO_SHA1_HMAC) { ++ continue; ++ } ++ len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, len, macbuf); ++ break; ++ } ++ } ++ ++ if (cmd->src_map != cmd->dst_map) ++ pci_unmap_buf(sc, &cmd->dst); ++ pci_unmap_buf(sc, &cmd->src); ++ kfree(cmd); ++ crypto_done(crp); ++} ++ ++/* ++ * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 ++ * and Group 1 registers; avoid conditions that could create ++ * burst writes by doing a read in between the writes. ++ * ++ * NB: The read we interpose is always to the same register; ++ * we do this because reading from an arbitrary (e.g. last) ++ * register may not always work. ++ */ ++static void ++hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) ++{ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ if (sc->sc_bar0_lastreg == reg - 4) ++ readl(sc->sc_bar0 + HIFN_0_PUCNFG); ++ sc->sc_bar0_lastreg = reg; ++ } ++ writel(val, sc->sc_bar0 + reg); ++} ++ ++static void ++hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) ++{ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ if (sc->sc_bar1_lastreg == reg - 4) ++ readl(sc->sc_bar1 + HIFN_1_REVID); ++ sc->sc_bar1_lastreg = reg; ++ } ++ writel(val, sc->sc_bar1 + reg); ++} ++ ++ ++static struct pci_device_id hifn_pci_tbl[] = { ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7951, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7955, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7956, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_NETSEC, PCI_PRODUCT_NETSEC_7751, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_INVERTEX, PCI_PRODUCT_INVERTEX_AEON, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7811, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ /* ++ * Other vendors share this PCI ID as well, such as ++ * http://www.powercrypt.com, and obviously they also ++ * use the same key. ++ */ ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { 0, 0, 0, 0, 0, 0, } ++}; ++MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); ++ ++static struct pci_driver hifn_driver = { ++ .name = "hifn", ++ .id_table = hifn_pci_tbl, ++ .probe = hifn_probe, ++ .remove = hifn_remove, ++ /* add PM stuff here one day */ ++}; ++ ++static int __init hifn_init (void) ++{ ++ struct hifn_softc *sc = NULL; ++ int rc; ++ ++ DPRINTF("%s(%p)\n", __FUNCTION__, hifn_init); ++ ++ rc = pci_register_driver(&hifn_driver); ++ pci_register_driver_compat(&hifn_driver, rc); ++ ++ return rc; ++} ++ ++static void __exit hifn_exit (void) ++{ ++ pci_unregister_driver(&hifn_driver); ++} ++ ++module_init(hifn_init); ++module_exit(hifn_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("OCF driver for hifn PCI crypto devices"); +diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/hifn7751reg.h linux-2.6.39/crypto/ocf/hifn/hifn7751reg.h +--- linux-2.6.39.orig/crypto/ocf/hifn/hifn7751reg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/hifn/hifn7751reg.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,540 @@ ++/* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.7 2007/03/21 03:42:49 sam Exp $ */ ++/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ ++ ++/*- ++ * Invertex AEON / Hifn 7751 driver ++ * Copyright (c) 1999 Invertex Inc. All rights reserved. ++ * Copyright (c) 1999 Theo de Raadt ++ * Copyright (c) 2000-2001 Network Security Technologies, Inc. ++ * http://www.netsec.net ++ * ++ * Please send any comments, feedback, bug-fixes, or feature requests to ++ * software@invertex.com. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++#ifndef __HIFN_H__ ++#define __HIFN_H__ ++ ++/* ++ * Some PCI configuration space offset defines. The names were made ++ * identical to the names used by the Linux kernel. ++ */ ++#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ ++#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ ++#define HIFN_TRDY_TIMEOUT 0x40 ++#define HIFN_RETRY_TIMEOUT 0x41 ++ ++/* ++ * PCI vendor and device identifiers ++ * (the names are preserved from their OpenBSD source). ++ */ ++#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ ++#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ ++#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ ++#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ ++#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ ++#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ ++#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ ++#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ ++ ++#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ ++#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ ++ ++#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ ++#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ ++ ++/* ++ * The values below should multiple of 4 -- and be large enough to handle ++ * any command the driver implements. ++ * ++ * MAX_COMMAND = base command + mac command + encrypt command + ++ * mac-key + rc4-key ++ * MAX_RESULT = base result + mac result + mac + encrypt result ++ * ++ * ++ */ ++#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) ++#define HIFN_MAX_RESULT (8 + 4 + 20 + 4) ++ ++/* ++ * hifn_desc_t ++ * ++ * Holds an individual descriptor for any of the rings. ++ */ ++typedef struct hifn_desc { ++ volatile u_int32_t l; /* length and status bits */ ++ volatile u_int32_t p; ++} hifn_desc_t; ++ ++/* ++ * Masks for the "length" field of struct hifn_desc. ++ */ ++#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ ++#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ ++#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ ++#define HIFN_D_OVER 0x08000000 /* overflow */ ++#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ ++#define HIFN_D_JUMP 0x40000000 /* jump descriptor */ ++#define HIFN_D_VALID 0x80000000 /* valid bit */ ++ ++ ++/* ++ * Processing Unit Registers (offset from BASEREG0) ++ */ ++#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ ++#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ ++#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ ++#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ ++#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ ++#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ ++#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ ++#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ ++#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ ++#define HIFN_0_MUTE1 0x80 ++#define HIFN_0_MUTE2 0x90 ++#define HIFN_0_SPACESIZE 0x100 /* Register space size */ ++ ++/* Processing Unit Control Register (HIFN_0_PUCTRL) */ ++#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ ++#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ ++#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ ++#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ ++#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ ++ ++/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ ++#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ ++#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ ++#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ ++#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ ++#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ ++#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ ++#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ ++#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ ++#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ ++#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ ++ ++/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ ++#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ ++#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ ++#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ ++#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ ++#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ ++#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ ++#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ ++#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ ++#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ ++#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ ++#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ ++#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ ++#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ ++#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ ++#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ ++#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ ++#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ ++#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ ++#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ ++#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ ++#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ ++#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ ++#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ ++ ++/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ ++#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ ++#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ ++#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ ++#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ ++#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ ++#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ ++#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ ++#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ ++#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ ++#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ ++ ++/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ ++#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ ++#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ ++#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ ++#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ ++#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ ++#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ ++#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ ++#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ ++#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ ++#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ ++#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ ++#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ ++#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ ++#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ ++#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ ++#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ ++#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ ++ ++/* FIFO Status Register (HIFN_0_FIFOSTAT) */ ++#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ ++#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ ++ ++/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ ++#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */ ++ ++/* ++ * DMA Interface Registers (offset from BASEREG1) ++ */ ++#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ ++#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ ++#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ ++#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ ++#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ ++#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ ++#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ ++#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ ++#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ ++#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ ++#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ ++#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ ++#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ ++#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ ++#define HIFN_1_REVID 0x98 /* Revision ID */ ++ ++#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ ++#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ ++#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */ ++#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */ ++#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */ ++#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ ++#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ ++#define HIFN_1_RNG_DATA 0x318 /* RNG data */ ++#define HIFN_1_PUB_MODE 0x320 /* PK mode */ ++#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ ++#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ ++#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ ++#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ ++ ++/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ ++#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ ++#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ ++#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ ++#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ ++#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ ++#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ ++#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ ++#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ ++#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ ++#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ ++#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ ++#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ ++#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ ++#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ ++#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ ++#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ ++#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ ++#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ ++#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ ++#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ ++#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ ++#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ ++#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ ++#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ ++#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ ++#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ ++#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ ++#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ ++#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ ++#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ ++#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ ++#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ ++#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ ++#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ ++#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ ++#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ ++#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ ++#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ ++ ++/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ ++#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ ++#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ ++#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ ++#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ ++#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ ++#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ ++#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ ++#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ ++#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ ++#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ ++#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ ++#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ ++#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ ++#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ ++#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ ++#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ ++#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ ++#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ ++#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ ++#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ ++#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ ++#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ ++ ++/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ ++#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ ++#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ ++#define HIFN_DMACNFG_UNLOCK 0x00000800 ++#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ ++#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ ++#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ ++#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ ++#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ ++ ++/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ ++#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ ++#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ ++#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ ++#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ ++#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 ++#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 ++#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 ++#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 ++ ++/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ ++#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ ++ ++/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ ++#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ ++#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ ++#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ ++ ++/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ ++#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ ++#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ ++ ++/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ ++#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ ++#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ ++#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ ++#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ ++#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ ++#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ ++#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ ++#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ ++#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ ++ ++/* Public key reset register (HIFN_1_PUB_RESET) */ ++#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ ++ ++/* Public operation register (HIFN_1_PUB_OP) */ ++#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ ++#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ ++#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ ++#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ ++#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ ++#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ ++#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ ++#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ ++#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ ++#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ ++#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ ++#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ ++#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ ++#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ ++#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ ++#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ ++#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ ++ ++/* Public operand length register (HIFN_1_PUB_OPLEN) */ ++#define HIFN_PUBOPLEN_MODLEN 0x0000007f ++#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 ++#define HIFN_PUBOPLEN_REDLEN 0x003c0000 ++ ++/* Public status register (HIFN_1_PUB_STATUS) */ ++#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ ++#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ ++#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ ++#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ ++#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ ++#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ ++#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ ++ ++/* Public interrupt enable register (HIFN_1_PUB_IEN) */ ++#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ ++ ++/* Random number generator config register (HIFN_1_RNG_CONFIG) */ ++#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ ++ ++/* ++ * Register offsets in register set 1 ++ */ ++ ++#define HIFN_UNLOCK_SECRET1 0xf4 ++#define HIFN_UNLOCK_SECRET2 0xfc ++ ++/* ++ * PLL config register ++ * ++ * This register is present only on 7954/7955/7956 parts. It must be ++ * programmed according to the bus interface method used by the h/w. ++ * Note that the parts require a stable clock. Since the PCI clock ++ * may vary the reference clock must usually be used. To avoid ++ * overclocking the core logic, setup must be done carefully, refer ++ * to the driver for details. The exact multiplier required varies ++ * by part and system configuration; refer to the Hifn documentation. ++ */ ++#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ ++#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ ++/* bit 2 reserved */ ++#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ ++#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ ++/* bits 5-9 reserved */ ++#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ ++#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ ++#define HIFN_PLL_ND_SHIFT 11 ++#define HIFN_PLL_ND_2 0x00000000 /* 2x */ ++#define HIFN_PLL_ND_4 0x00000800 /* 4x */ ++#define HIFN_PLL_ND_6 0x00001000 /* 6x */ ++#define HIFN_PLL_ND_8 0x00001800 /* 8x */ ++#define HIFN_PLL_ND_10 0x00002000 /* 10x */ ++#define HIFN_PLL_ND_12 0x00002800 /* 12x */ ++/* bits 14-15 reserved */ ++#define HIFN_PLL_IS 0x00010000 /* charge pump current select */ ++/* bits 17-31 reserved */ ++ ++/* ++ * Board configuration specifies only these bits. ++ */ ++#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) ++ ++/* ++ * Public Key Engine Mode Register ++ */ ++#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ ++#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ ++ ++ ++/********************************************************************* ++ * Structs for board commands ++ * ++ *********************************************************************/ ++ ++/* ++ * Structure to help build up the command data structure. ++ */ ++typedef struct hifn_base_command { ++ volatile u_int16_t masks; ++ volatile u_int16_t session_num; ++ volatile u_int16_t total_source_count; ++ volatile u_int16_t total_dest_count; ++} hifn_base_command_t; ++ ++#define HIFN_BASE_CMD_MAC 0x0400 ++#define HIFN_BASE_CMD_CRYPT 0x0800 ++#define HIFN_BASE_CMD_DECODE 0x2000 ++#define HIFN_BASE_CMD_SRCLEN_M 0xc000 ++#define HIFN_BASE_CMD_SRCLEN_S 14 ++#define HIFN_BASE_CMD_DSTLEN_M 0x3000 ++#define HIFN_BASE_CMD_DSTLEN_S 12 ++#define HIFN_BASE_CMD_LENMASK_HI 0x30000 ++#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff ++ ++/* ++ * Structure to help build up the command data structure. ++ */ ++typedef struct hifn_crypt_command { ++ volatile u_int16_t masks; ++ volatile u_int16_t header_skip; ++ volatile u_int16_t source_count; ++ volatile u_int16_t reserved; ++} hifn_crypt_command_t; ++ ++#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ ++#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ ++#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ ++#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ ++#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ ++#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ ++#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ ++#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ ++#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ ++#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ ++#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ ++#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ ++#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ ++ ++#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 ++#define HIFN_CRYPT_CMD_SRCLEN_S 14 ++ ++#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ ++#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ ++#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ ++#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ ++ ++/* ++ * Structure to help build up the command data structure. ++ */ ++typedef struct hifn_mac_command { ++ volatile u_int16_t masks; ++ volatile u_int16_t header_skip; ++ volatile u_int16_t source_count; ++ volatile u_int16_t reserved; ++} hifn_mac_command_t; ++ ++#define HIFN_MAC_CMD_ALG_MASK 0x0001 ++#define HIFN_MAC_CMD_ALG_SHA1 0x0000 ++#define HIFN_MAC_CMD_ALG_MD5 0x0001 ++#define HIFN_MAC_CMD_MODE_MASK 0x000c ++#define HIFN_MAC_CMD_MODE_HMAC 0x0000 ++#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 ++#define HIFN_MAC_CMD_MODE_HASH 0x0008 ++#define HIFN_MAC_CMD_MODE_FULL 0x0004 ++#define HIFN_MAC_CMD_TRUNC 0x0010 ++#define HIFN_MAC_CMD_RESULT 0x0020 ++#define HIFN_MAC_CMD_APPEND 0x0040 ++#define HIFN_MAC_CMD_SRCLEN_M 0xc000 ++#define HIFN_MAC_CMD_SRCLEN_S 14 ++ ++/* ++ * MAC POS IPsec initiates authentication after encryption on encodes ++ * and before decryption on decodes. ++ */ ++#define HIFN_MAC_CMD_POS_IPSEC 0x0200 ++#define HIFN_MAC_CMD_NEW_KEY 0x0800 ++ ++/* ++ * The poll frequency and poll scalar defines are unshifted values used ++ * to set fields in the DMA Configuration Register. ++ */ ++#ifndef HIFN_POLL_FREQUENCY ++#define HIFN_POLL_FREQUENCY 0x1 ++#endif ++ ++#ifndef HIFN_POLL_SCALAR ++#define HIFN_POLL_SCALAR 0x0 ++#endif ++ ++#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ ++#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ ++#endif /* __HIFN_H__ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/hifn7751var.h linux-2.6.39/crypto/ocf/hifn/hifn7751var.h +--- linux-2.6.39.orig/crypto/ocf/hifn/hifn7751var.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/hifn/hifn7751var.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,369 @@ ++/* $FreeBSD: src/sys/dev/hifn/hifn7751var.h,v 1.9 2007/03/21 03:42:49 sam Exp $ */ ++/* $OpenBSD: hifn7751var.h,v 1.42 2002/04/08 17:49:42 jason Exp $ */ ++ ++/*- ++ * Invertex AEON / Hifn 7751 driver ++ * Copyright (c) 1999 Invertex Inc. All rights reserved. ++ * Copyright (c) 1999 Theo de Raadt ++ * Copyright (c) 2000-2001 Network Security Technologies, Inc. ++ * http://www.netsec.net ++ * ++ * Please send any comments, feedback, bug-fixes, or feature requests to ++ * software@invertex.com. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++#ifndef __HIFN7751VAR_H__ ++#define __HIFN7751VAR_H__ ++ ++#ifdef __KERNEL__ ++ ++/* ++ * Some configurable values for the driver. By default command+result ++ * descriptor rings are the same size. The src+dst descriptor rings ++ * are sized at 3.5x the number of potential commands. Slower parts ++ * (e.g. 7951) tend to run out of src descriptors; faster parts (7811) ++ * src+cmd/result descriptors. It's not clear that increasing the size ++ * of the descriptor rings helps performance significantly as other ++ * factors tend to come into play (e.g. copying misaligned packets). ++ */ ++#define HIFN_D_CMD_RSIZE 24 /* command descriptors */ ++#define HIFN_D_SRC_RSIZE ((HIFN_D_CMD_RSIZE * 7) / 2) /* source descriptors */ ++#define HIFN_D_RES_RSIZE HIFN_D_CMD_RSIZE /* result descriptors */ ++#define HIFN_D_DST_RSIZE HIFN_D_SRC_RSIZE /* destination descriptors */ ++ ++/* ++ * Length values for cryptography ++ */ ++#define HIFN_DES_KEY_LENGTH 8 ++#define HIFN_3DES_KEY_LENGTH 24 ++#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH ++#define HIFN_IV_LENGTH 8 ++#define HIFN_AES_IV_LENGTH 16 ++#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH ++ ++/* ++ * Length values for authentication ++ */ ++#define HIFN_MAC_KEY_LENGTH 64 ++#define HIFN_MD5_LENGTH 16 ++#define HIFN_SHA1_LENGTH 20 ++#define HIFN_MAC_TRUNC_LENGTH 12 ++ ++#define MAX_SCATTER 64 ++ ++/* ++ * Data structure to hold all 4 rings and any other ring related data. ++ */ ++struct hifn_dma { ++ /* ++ * Descriptor rings. We add +1 to the size to accomidate the ++ * jump descriptor. ++ */ ++ struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; ++ struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; ++ struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; ++ struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; ++ ++ struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE]; ++ ++ u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; ++ u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; ++ u_int32_t slop[HIFN_D_CMD_RSIZE]; ++ ++ u_int64_t test_src, test_dst; ++ ++ /* ++ * Our current positions for insertion and removal from the desriptor ++ * rings. ++ */ ++ int cmdi, srci, dsti, resi; ++ volatile int cmdu, srcu, dstu, resu; ++ int cmdk, srck, dstk, resk; ++}; ++ ++struct hifn_session { ++ int hs_used; ++ int hs_mlen; ++ u_int8_t hs_iv[HIFN_MAX_IV_LENGTH]; ++}; ++ ++#define HIFN_RING_SYNC(sc, r, i, f) \ ++ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ ++ ++#define HIFN_CMDR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), cmdr, (i), (f)) ++#define HIFN_RESR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), resr, (i), (f)) ++#define HIFN_SRCR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), srcr, (i), (f)) ++#define HIFN_DSTR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), dstr, (i), (f)) ++ ++#define HIFN_CMD_SYNC(sc, i, f) \ ++ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ ++ ++#define HIFN_RES_SYNC(sc, i, f) \ ++ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ ++ ++typedef int bus_size_t; ++ ++/* ++ * Holds data specific to a single HIFN board. ++ */ ++struct hifn_softc { ++ softc_device_decl sc_dev; ++ ++ struct pci_dev *sc_pcidev; /* PCI device pointer */ ++ spinlock_t sc_mtx; /* per-instance lock */ ++ ++ int sc_num; /* for multiple devs */ ++ ++ ocf_iomem_t sc_bar0; ++ bus_size_t sc_bar0_lastreg;/* bar0 last reg written */ ++ ocf_iomem_t sc_bar1; ++ bus_size_t sc_bar1_lastreg;/* bar1 last reg written */ ++ ++ int sc_irq; ++ ++ u_int32_t sc_dmaier; ++ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ ++ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ ++ ++ struct hifn_dma *sc_dma; ++ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ ++ ++ int sc_dmansegs; ++ int32_t sc_cid; ++ int sc_maxses; ++ int sc_nsessions; ++ struct hifn_session *sc_sessions; ++ int sc_ramsize; ++ int sc_flags; ++#define HIFN_HAS_RNG 0x1 /* includes random number generator */ ++#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ ++#define HIFN_HAS_AES 0x4 /* includes AES support */ ++#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ ++#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ ++ ++ struct timer_list sc_tickto; /* for managing DMA */ ++ ++ int sc_rngfirst; ++ int sc_rnghz; /* RNG polling frequency */ ++ ++ int sc_c_busy; /* command ring busy */ ++ int sc_s_busy; /* source data ring busy */ ++ int sc_d_busy; /* destination data ring busy */ ++ int sc_r_busy; /* result ring busy */ ++ int sc_active; /* for initial countdown */ ++ int sc_needwakeup; /* ops q'd wating on resources */ ++ int sc_curbatch; /* # ops submitted w/o int */ ++ int sc_suspended; ++#ifdef HIFN_VULCANDEV ++ struct cdev *sc_pkdev; ++#endif ++}; ++ ++#define HIFN_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) ++#define HIFN_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) ++ ++/* ++ * hifn_command_t ++ * ++ * This is the control structure used to pass commands to hifn_encrypt(). ++ * ++ * flags ++ * ----- ++ * Flags is the bitwise "or" values for command configuration. A single ++ * encrypt direction needs to be set: ++ * ++ * HIFN_ENCODE or HIFN_DECODE ++ * ++ * To use cryptography, a single crypto algorithm must be included: ++ * ++ * HIFN_CRYPT_3DES or HIFN_CRYPT_DES ++ * ++ * To use authentication is used, a single MAC algorithm must be included: ++ * ++ * HIFN_MAC_MD5 or HIFN_MAC_SHA1 ++ * ++ * By default MD5 uses a 16 byte hash and SHA-1 uses a 20 byte hash. ++ * If the value below is set, hash values are truncated or assumed ++ * truncated to 12 bytes: ++ * ++ * HIFN_MAC_TRUNC ++ * ++ * Keys for encryption and authentication can be sent as part of a command, ++ * or the last key value used with a particular session can be retrieved ++ * and used again if either of these flags are not specified. ++ * ++ * HIFN_CRYPT_NEW_KEY, HIFN_MAC_NEW_KEY ++ * ++ * session_num ++ * ----------- ++ * A number between 0 and 2048 (for DRAM models) or a number between ++ * 0 and 768 (for SRAM models). Those who don't want to use session ++ * numbers should leave value at zero and send a new crypt key and/or ++ * new MAC key on every command. If you use session numbers and ++ * don't send a key with a command, the last key sent for that same ++ * session number will be used. ++ * ++ * Warning: Using session numbers and multiboard at the same time ++ * is currently broken. ++ * ++ * mbuf ++ * ---- ++ * Either fill in the mbuf pointer and npa=0 or ++ * fill packp[] and packl[] and set npa to > 0 ++ * ++ * mac_header_skip ++ * --------------- ++ * The number of bytes of the source_buf that are skipped over before ++ * authentication begins. This must be a number between 0 and 2^16-1 ++ * and can be used by IPsec implementers to skip over IP headers. ++ * *** Value ignored if authentication not used *** ++ * ++ * crypt_header_skip ++ * ----------------- ++ * The number of bytes of the source_buf that are skipped over before ++ * the cryptographic operation begins. This must be a number between 0 ++ * and 2^16-1. For IPsec, this number will always be 8 bytes larger ++ * than the auth_header_skip (to skip over the ESP header). ++ * *** Value ignored if cryptography not used *** ++ * ++ */ ++struct hifn_operand { ++ union { ++ struct sk_buff *skb; ++ struct uio *io; ++ unsigned char *buf; ++ } u; ++ void *map; ++ bus_size_t mapsize; ++ int nsegs; ++ struct { ++ dma_addr_t ds_addr; ++ int ds_len; ++ } segs[MAX_SCATTER]; ++}; ++ ++struct hifn_command { ++ u_int16_t session_num; ++ u_int16_t base_masks, cry_masks, mac_masks; ++ u_int8_t iv[HIFN_MAX_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH]; ++ int cklen; ++ int sloplen, slopidx; ++ ++ struct hifn_operand src; ++ struct hifn_operand dst; ++ ++ struct hifn_softc *softc; ++ struct cryptop *crp; ++ struct cryptodesc *enccrd, *maccrd; ++}; ++ ++#define src_skb src.u.skb ++#define src_io src.u.io ++#define src_map src.map ++#define src_mapsize src.mapsize ++#define src_segs src.segs ++#define src_nsegs src.nsegs ++#define src_buf src.u.buf ++ ++#define dst_skb dst.u.skb ++#define dst_io dst.u.io ++#define dst_map dst.map ++#define dst_mapsize dst.mapsize ++#define dst_segs dst.segs ++#define dst_nsegs dst.nsegs ++#define dst_buf dst.u.buf ++ ++/* ++ * Return values for hifn_crypto() ++ */ ++#define HIFN_CRYPTO_SUCCESS 0 ++#define HIFN_CRYPTO_BAD_INPUT (-1) ++#define HIFN_CRYPTO_RINGS_FULL (-2) ++ ++/************************************************************************** ++ * ++ * Function: hifn_crypto ++ * ++ * Purpose: Called by external drivers to begin an encryption on the ++ * HIFN board. ++ * ++ * Blocking/Non-blocking Issues ++ * ============================ ++ * The driver cannot block in hifn_crypto (no calls to tsleep) currently. ++ * hifn_crypto() returns HIFN_CRYPTO_RINGS_FULL if there is not enough ++ * room in any of the rings for the request to proceed. ++ * ++ * Return Values ++ * ============= ++ * 0 for success, negative values on error ++ * ++ * Defines for negative error codes are: ++ * ++ * HIFN_CRYPTO_BAD_INPUT : The passed in command had invalid settings. ++ * HIFN_CRYPTO_RINGS_FULL : All DMA rings were full and non-blocking ++ * behaviour was requested. ++ * ++ *************************************************************************/ ++ ++/* ++ * Convert back and forth from 'sid' to 'card' and 'session' ++ */ ++#define HIFN_CARD(sid) (((sid) & 0xf0000000) >> 28) ++#define HIFN_SESSION(sid) ((sid) & 0x000007ff) ++#define HIFN_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) ++ ++#endif /* _KERNEL */ ++ ++struct hifn_stats { ++ u_int64_t hst_ibytes; ++ u_int64_t hst_obytes; ++ u_int32_t hst_ipackets; ++ u_int32_t hst_opackets; ++ u_int32_t hst_invalid; ++ u_int32_t hst_nomem; /* malloc or one of hst_nomem_* */ ++ u_int32_t hst_abort; ++ u_int32_t hst_noirq; /* IRQ for no reason */ ++ u_int32_t hst_totbatch; /* ops submitted w/o interrupt */ ++ u_int32_t hst_maxbatch; /* max ops submitted together */ ++ u_int32_t hst_unaligned; /* unaligned src caused copy */ ++ /* ++ * The following divides hst_nomem into more specific buckets. ++ */ ++ u_int32_t hst_nomem_map; /* bus_dmamap_create failed */ ++ u_int32_t hst_nomem_load; /* bus_dmamap_load_* failed */ ++ u_int32_t hst_nomem_mbuf; /* MGET* failed */ ++ u_int32_t hst_nomem_mcl; /* MCLGET* failed */ ++ u_int32_t hst_nomem_cr; /* out of command/result descriptor */ ++ u_int32_t hst_nomem_sd; /* out of src/dst descriptors */ ++}; ++ ++#endif /* __HIFN7751VAR_H__ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/hifnHIPP.c linux-2.6.39/crypto/ocf/hifn/hifnHIPP.c +--- linux-2.6.39.orig/crypto/ocf/hifn/hifnHIPP.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/hifn/hifnHIPP.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,420 @@ ++/*- ++ * Driver for Hifn HIPP-I/II chipset ++ * Copyright (c) 2006 Michael Richardson ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored by Hifn Inc. ++ * ++ */ ++ ++/* ++ * Driver for various Hifn encryption processors. ++ */ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "hifnHIPPreg.h" ++#include "hifnHIPPvar.h" ++ ++#if 1 ++#define DPRINTF(a...) if (hipp_debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_dev) : "hifn"); \ ++ printk(a); \ ++ } else ++#else ++#define DPRINTF(a...) ++#endif ++ ++typedef int bus_size_t; ++ ++static inline int ++pci_get_revid(struct pci_dev *dev) ++{ ++ u8 rid = 0; ++ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); ++ return rid; ++} ++ ++#define debug hipp_debug ++int hipp_debug = 0; ++module_param(hipp_debug, int, 0644); ++MODULE_PARM_DESC(hipp_debug, "Enable debug"); ++ ++int hipp_maxbatch = 1; ++module_param(hipp_maxbatch, int, 0644); ++MODULE_PARM_DESC(hipp_maxbatch, "max ops to batch w/o interrupt"); ++ ++static int hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent); ++static void hipp_remove(struct pci_dev *dev); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++static irqreturn_t hipp_intr(int irq, void *arg); ++#else ++static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs); ++#endif ++ ++static int hipp_num_chips = 0; ++static struct hipp_softc *hipp_chip_idx[HIPP_MAX_CHIPS]; ++ ++static int hipp_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int hipp_freesession(device_t, u_int64_t); ++static int hipp_process(device_t, struct cryptop *, int); ++ ++static device_method_t hipp_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, hipp_newsession), ++ DEVMETHOD(cryptodev_freesession,hipp_freesession), ++ DEVMETHOD(cryptodev_process, hipp_process), ++}; ++ ++static __inline u_int32_t ++READ_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg) ++{ ++ u_int32_t v = readl(sc->sc_bar[barno] + reg); ++ //sc->sc_bar0_lastreg = (bus_size_t) -1; ++ return (v); ++} ++static __inline void ++WRITE_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg, u_int32_t val) ++{ ++ writel(val, sc->sc_bar[barno] + reg); ++} ++ ++#define READ_REG_0(sc, reg) READ_REG(sc, 0, reg) ++#define WRITE_REG_0(sc, reg, val) WRITE_REG(sc,0, reg, val) ++#define READ_REG_1(sc, reg) READ_REG(sc, 1, reg) ++#define WRITE_REG_1(sc, reg, val) WRITE_REG(sc,1, reg, val) ++ ++static int ++hipp_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ return EINVAL; ++} ++ ++static int ++hipp_freesession(device_t dev, u_int64_t tid) ++{ ++ return EINVAL; ++} ++ ++static int ++hipp_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ return EINVAL; ++} ++ ++static const char* ++hipp_partname(struct hipp_softc *sc, char buf[128], size_t blen) ++{ ++ char *n = NULL; ++ ++ switch (pci_get_vendor(sc->sc_pcidev)) { ++ case PCI_VENDOR_HIFN: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_HIFN_7855: n = "Hifn 7855"; ++ case PCI_PRODUCT_HIFN_8155: n = "Hifn 8155"; ++ case PCI_PRODUCT_HIFN_6500: n = "Hifn 6500"; ++ } ++ } ++ ++ if(n==NULL) { ++ snprintf(buf, blen, "VID=%02x,PID=%02x", ++ pci_get_vendor(sc->sc_pcidev), ++ pci_get_device(sc->sc_pcidev)); ++ } else { ++ buf[0]='\0'; ++ strncat(buf, n, blen); ++ } ++ return buf; ++} ++ ++struct hipp_fs_entry { ++ struct attribute attr; ++ /* other stuff */ ++}; ++ ++ ++static ssize_t ++cryptoid_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct hipp_softc *sc; ++ ++ sc = pci_get_drvdata(to_pci_dev (dev)); ++ return sprintf (buf, "%d\n", sc->sc_cid); ++} ++ ++struct device_attribute hipp_dev_cryptoid = __ATTR_RO(cryptoid); ++ ++/* ++ * Attach an interface that successfully probed. ++ */ ++static int ++hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent) ++{ ++ struct hipp_softc *sc = NULL; ++ int i; ++ //char rbase; ++ //u_int16_t ena; ++ int rev; ++ //int rseg; ++ int rc; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (pci_enable_device(dev) < 0) ++ return(-ENODEV); ++ ++ if (pci_set_mwi(dev)) ++ return(-ENODEV); ++ ++ if (!dev->irq) { ++ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); ++ pci_disable_device(dev); ++ return(-ENODEV); ++ } ++ ++ sc = (struct hipp_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, "hifn-hipp", hipp_num_chips, hipp_methods); ++ ++ sc->sc_pcidev = dev; ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++ sc->sc_num = hipp_num_chips++; ++ ++ if (sc->sc_num < HIPP_MAX_CHIPS) ++ hipp_chip_idx[sc->sc_num] = sc; ++ ++ pci_set_drvdata(sc->sc_pcidev, sc); ++ ++ spin_lock_init(&sc->sc_mtx); ++ ++ /* ++ * Setup PCI resources. ++ * The READ_REG_0, WRITE_REG_0, READ_REG_1, ++ * and WRITE_REG_1 macros throughout the driver are used ++ * to permit better debugging. ++ */ ++ for(i=0; i<4; i++) { ++ unsigned long mem_start, mem_len; ++ mem_start = pci_resource_start(sc->sc_pcidev, i); ++ mem_len = pci_resource_len(sc->sc_pcidev, i); ++ sc->sc_barphy[i] = (caddr_t)mem_start; ++ sc->sc_bar[i] = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_bar[i]) { ++ device_printf(sc->sc_dev, "cannot map bar%d register space\n", i); ++ goto fail; ++ } ++ } ++ ++ //hipp_reset_board(sc, 0); ++ pci_set_master(sc->sc_pcidev); ++ ++ /* ++ * Arrange the interrupt line. ++ */ ++ rc = request_irq(dev->irq, hipp_intr, IRQF_SHARED, "hifn", sc); ++ if (rc) { ++ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); ++ goto fail; ++ } ++ sc->sc_irq = dev->irq; ++ ++ rev = READ_REG_1(sc, HIPP_1_REVID) & 0xffff; ++ ++ { ++ char b[32]; ++ device_printf(sc->sc_dev, "%s, rev %u", ++ hipp_partname(sc, b, sizeof(b)), rev); ++ } ++ ++#if 0 ++ if (sc->sc_flags & HIFN_IS_7956) ++ printf(", pll=0x%x<%s clk, %ux mult>", ++ sc->sc_pllconfig, ++ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", ++ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); ++#endif ++ printf("\n"); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ goto fail; ++ } ++ ++#if 0 /* cannot work with a non-GPL module */ ++ /* make a sysfs entry to let the world know what entry we got */ ++ sysfs_create_file(&sc->sc_pcidev->dev.kobj, &hipp_dev_cryptoid.attr); ++#endif ++ ++#if 0 ++ init_timer(&sc->sc_tickto); ++ sc->sc_tickto.function = hifn_tick; ++ sc->sc_tickto.data = (unsigned long) sc->sc_num; ++ mod_timer(&sc->sc_tickto, jiffies + HZ); ++#endif ++ ++#if 0 /* no code here yet ?? */ ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++#endif ++ ++ return (0); ++ ++fail: ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ ++#if 0 ++ if (sc->sc_dma) { ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ pci_free_consistent(sc->sc_pcidev, ++ sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++ } ++#endif ++ kfree(sc); ++ return (-ENXIO); ++} ++ ++/* ++ * Detach an interface that successfully probed. ++ */ ++static void ++hipp_remove(struct pci_dev *dev) ++{ ++ struct hipp_softc *sc = pci_get_drvdata(dev); ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* disable interrupts */ ++ HIPP_LOCK(sc); ++ ++#if 0 ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); ++ HIFN_UNLOCK(sc); ++ ++ /*XXX other resources */ ++ del_timer_sync(&sc->sc_tickto); ++ ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++#endif ++ ++ crypto_unregister_all(sc->sc_cid); ++ ++ free_irq(sc->sc_irq, sc); ++ ++#if 0 ++ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++#endif ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++static irqreturn_t hipp_intr(int irq, void *arg) ++#else ++static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct hipp_softc *sc = arg; ++ ++ sc = sc; /* shut up compiler */ ++ ++ return IRQ_HANDLED; ++} ++ ++static struct pci_device_id hipp_pci_tbl[] = { ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7855, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++}; ++MODULE_DEVICE_TABLE(pci, hipp_pci_tbl); ++ ++static struct pci_driver hipp_driver = { ++ .name = "hipp", ++ .id_table = hipp_pci_tbl, ++ .probe = hipp_probe, ++ .remove = hipp_remove, ++ /* add PM stuff here one day */ ++}; ++ ++static int __init hipp_init (void) ++{ ++ struct hipp_softc *sc = NULL; ++ int rc; ++ ++ DPRINTF("%s(%p)\n", __FUNCTION__, hipp_init); ++ ++ rc = pci_register_driver(&hipp_driver); ++ pci_register_driver_compat(&hipp_driver, rc); ++ ++ return rc; ++} ++ ++static void __exit hipp_exit (void) ++{ ++ pci_unregister_driver(&hipp_driver); ++} ++ ++module_init(hipp_init); ++module_exit(hipp_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("Michael Richardson "); ++MODULE_DESCRIPTION("OCF driver for hifn HIPP-I/II PCI crypto devices"); +diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/hifnHIPPreg.h linux-2.6.39/crypto/ocf/hifn/hifnHIPPreg.h +--- linux-2.6.39.orig/crypto/ocf/hifn/hifnHIPPreg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/hifn/hifnHIPPreg.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,46 @@ ++/*- ++ * Hifn HIPP-I/HIPP-II (7855/8155) driver. ++ * Copyright (c) 2006 Michael Richardson ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored by Hifn inc. ++ * ++ */ ++ ++#ifndef __HIFNHIPP_H__ ++#define __HIFNHIPP_H__ ++ ++/* ++ * PCI vendor and device identifiers ++ */ ++#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ ++#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ ++#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ ++#define PCI_PRODUCT_HIFN_8155 0x999 /* XXX 8155 */ ++ ++#define HIPP_1_REVID 0x01 /* BOGUS */ ++ ++#endif /* __HIPP_H__ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/hifnHIPPvar.h linux-2.6.39/crypto/ocf/hifn/hifnHIPPvar.h +--- linux-2.6.39.orig/crypto/ocf/hifn/hifnHIPPvar.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/hifn/hifnHIPPvar.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,93 @@ ++/* ++ * Hifn HIPP-I/HIPP-II (7855/8155) driver. ++ * Copyright (c) 2006 Michael Richardson * ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored by Hifn inc. ++ * ++ */ ++ ++#ifndef __HIFNHIPPVAR_H__ ++#define __HIFNHIPPVAR_H__ ++ ++#define HIPP_MAX_CHIPS 8 ++ ++/* ++ * Holds data specific to a single Hifn HIPP-I board. ++ */ ++struct hipp_softc { ++ softc_device_decl sc_dev; ++ ++ struct pci_dev *sc_pcidev; /* device backpointer */ ++ ocf_iomem_t sc_bar[5]; ++ caddr_t sc_barphy[5]; /* physical address */ ++ int sc_num; /* for multiple devs */ ++ spinlock_t sc_mtx; /* per-instance lock */ ++ int32_t sc_cid; ++ int sc_irq; ++ ++#if 0 ++ ++ u_int32_t sc_dmaier; ++ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ ++ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ ++ ++ struct hifn_dma *sc_dma; ++ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ ++ ++ int sc_dmansegs; ++ int sc_maxses; ++ int sc_nsessions; ++ struct hifn_session *sc_sessions; ++ int sc_ramsize; ++ int sc_flags; ++#define HIFN_HAS_RNG 0x1 /* includes random number generator */ ++#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ ++#define HIFN_HAS_AES 0x4 /* includes AES support */ ++#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ ++#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ ++ ++ struct timer_list sc_tickto; /* for managing DMA */ ++ ++ int sc_rngfirst; ++ int sc_rnghz; /* RNG polling frequency */ ++ ++ int sc_c_busy; /* command ring busy */ ++ int sc_s_busy; /* source data ring busy */ ++ int sc_d_busy; /* destination data ring busy */ ++ int sc_r_busy; /* result ring busy */ ++ int sc_active; /* for initial countdown */ ++ int sc_needwakeup; /* ops q'd wating on resources */ ++ int sc_curbatch; /* # ops submitted w/o int */ ++ int sc_suspended; ++ struct miscdevice sc_miscdev; ++#endif ++}; ++ ++#define HIPP_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) ++#define HIPP_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) ++ ++#endif /* __HIFNHIPPVAR_H__ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/ixp4xx/Makefile linux-2.6.39/crypto/ocf/ixp4xx/Makefile +--- linux-2.6.39.orig/crypto/ocf/ixp4xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/ixp4xx/Makefile 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,104 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++# ++# You will need to point this at your Intel ixp425 includes, this portion ++# of the Makefile only really works under SGLinux with the appropriate libs ++# installed. They can be downloaded from http://www.snapgear.org/ ++# ++ifeq ($(CONFIG_CPU_IXP46X),y) ++IXPLATFORM = ixp46X ++else ++ifeq ($(CONFIG_CPU_IXP43X),y) ++IXPLATFORM = ixp43X ++else ++IXPLATFORM = ixp42X ++endif ++endif ++ ++ifdef CONFIG_IXP400_LIB_2_4 ++IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp400_xscale_sw ++OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp_osal ++endif ++ifdef CONFIG_IXP400_LIB_2_1 ++IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp400_xscale_sw ++OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp_osal ++endif ++ifdef CONFIG_IXP400_LIB_2_0 ++IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp400_xscale_sw ++OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp_osal ++endif ++ifdef IX_XSCALE_SW ++ifdef CONFIG_IXP400_LIB_2_4 ++IXP_CFLAGS = \ ++ -I$(ROOTDIR)/. \ ++ -I$(IX_XSCALE_SW)/src/include \ ++ -I$(OSAL_DIR)/common/include/ \ ++ -I$(OSAL_DIR)/common/include/modules/ \ ++ -I$(OSAL_DIR)/common/include/modules/ddk/ \ ++ -I$(OSAL_DIR)/common/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/common/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/core/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/ddk/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/include/ \ ++ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/os/linux/include/ \ ++ -DENABLE_IOMEM -DENABLE_BUFFERMGT -DENABLE_DDK \ ++ -DUSE_IXP4XX_CRYPTO ++else ++IXP_CFLAGS = \ ++ -I$(ROOTDIR)/. \ ++ -I$(IX_XSCALE_SW)/src/include \ ++ -I$(OSAL_DIR)/ \ ++ -I$(OSAL_DIR)/os/linux/include/ \ ++ -I$(OSAL_DIR)/os/linux/include/modules/ \ ++ -I$(OSAL_DIR)/os/linux/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/os/linux/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/os/linux/include/core/ \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp425 \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp465 \ ++ -I$(OSAL_DIR)/os/linux/include/core/ \ ++ -I$(OSAL_DIR)/include/ \ ++ -I$(OSAL_DIR)/include/modules/ \ ++ -I$(OSAL_DIR)/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/include/platforms/ \ ++ -I$(OSAL_DIR)/include/platforms/ixp400/ \ ++ -DUSE_IXP4XX_CRYPTO ++endif ++endif ++ifdef CONFIG_IXP400_LIB_1_4 ++IXP_CFLAGS = \ ++ -I$(ROOTDIR)/. \ ++ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/include \ ++ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/linux \ ++ -DUSE_IXP4XX_CRYPTO ++endif ++ifndef IXPDIR ++IXPDIR = ixp-version-is-not-supported ++endif ++ ++ifeq ($(CONFIG_CPU_IXP46X),y) ++IXP_CFLAGS += -D__ixp46X ++else ++ifeq ($(CONFIG_CPU_IXP43X),y) ++IXP_CFLAGS += -D__ixp43X ++else ++IXP_CFLAGS += -D__ixp42X ++endif ++endif ++ ++obj-$(CONFIG_OCF_IXP4XX) += ixp4xx.o ++ ++obj ?= . ++EXTRA_CFLAGS += $(IXP_CFLAGS) -I$(obj)/.. -I$(obj)/. ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/ixp4xx/ixp4xx.c linux-2.6.39/crypto/ocf/ixp4xx/ixp4xx.c +--- linux-2.6.39.orig/crypto/ocf/ixp4xx/ixp4xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/ixp4xx/ixp4xx.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,1324 @@ ++/* ++ * An OCF module that uses Intels IXP CryptACC API to do the crypto. ++ * This driver requires the IXP400 Access Library that is available ++ * from Intel in order to operate (or compile). ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#ifndef IX_MBUF_PRIV ++#define IX_MBUF_PRIV(x) ((x)->priv) ++#endif ++ ++struct ixp_data; ++ ++struct ixp_q { ++ struct list_head ixp_q_list; ++ struct ixp_data *ixp_q_data; ++ struct cryptop *ixp_q_crp; ++ struct cryptodesc *ixp_q_ccrd; ++ struct cryptodesc *ixp_q_acrd; ++ IX_MBUF ixp_q_mbuf; ++ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ ++ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ ++ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; ++ unsigned char *ixp_q_iv; ++}; ++ ++struct ixp_data { ++ int ixp_registered; /* is the context registered */ ++ int ixp_crd_flags; /* detect direction changes */ ++ ++ int ixp_cipher_alg; ++ int ixp_auth_alg; ++ ++ UINT32 ixp_ctx_id; ++ UINT32 ixp_hash_key_id; /* used when hashing */ ++ IxCryptoAccCtx ixp_ctx; ++ IX_MBUF ixp_pri_mbuf; ++ IX_MBUF ixp_sec_mbuf; ++ ++ struct work_struct ixp_pending_work; ++ struct work_struct ixp_registration_work; ++ struct list_head ixp_q; /* unprocessed requests */ ++}; ++ ++#ifdef __ixp46X ++ ++#define MAX_IOP_SIZE 64 /* words */ ++#define MAX_OOP_SIZE 128 ++ ++#define MAX_PARAMS 3 ++ ++struct ixp_pkq { ++ struct list_head pkq_list; ++ struct cryptkop *pkq_krp; ++ ++ IxCryptoAccPkeEauInOperands pkq_op; ++ IxCryptoAccPkeEauOpResult pkq_result; ++ ++ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; ++ UINT32 pkq_obuf[MAX_OOP_SIZE]; ++}; ++ ++static LIST_HEAD(ixp_pkq); /* current PK wait list */ ++static struct ixp_pkq *ixp_pk_cur; ++static spinlock_t ixp_pkq_lock; ++ ++#endif /* __ixp46X */ ++ ++static int ixp_blocked = 0; ++ ++static int32_t ixp_id = -1; ++static struct ixp_data **ixp_sessions = NULL; ++static u_int32_t ixp_sesnum = 0; ++ ++static int ixp_process(device_t, struct cryptop *, int); ++static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int ixp_freesession(device_t, u_int64_t); ++#ifdef __ixp46X ++static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++static kmem_cache_t *qcache; ++#else ++static struct kmem_cache *qcache; ++#endif ++ ++#define debug ixp_debug ++static int ixp_debug = 0; ++module_param(ixp_debug, int, 0644); ++MODULE_PARM_DESC(ixp_debug, "Enable debug"); ++ ++static int ixp_init_crypto = 1; ++module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ ++MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); ++ ++static void ixp_process_pending(void *arg); ++static void ixp_registration(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ixp_process_pending_wq(struct work_struct *work); ++static void ixp_registration_wq(struct work_struct *work); ++#endif ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} ixpdev; ++ ++static device_method_t ixp_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, ixp_newsession), ++ DEVMETHOD(cryptodev_freesession,ixp_freesession), ++ DEVMETHOD(cryptodev_process, ixp_process), ++#ifdef __ixp46X ++ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), ++#endif ++}; ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct ixp_data *ixp; ++ u_int32_t i; ++#define AUTH_LEN(cri, def) \ ++ (cri->cri_mlen ? cri->cri_mlen : (def)) ++ ++ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (ixp_sessions) { ++ for (i = 1; i < ixp_sesnum; i++) ++ if (ixp_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (ixp_sessions == NULL || i == ixp_sesnum) { ++ struct ixp_data **ixpd; ++ ++ if (ixp_sessions == NULL) { ++ i = 1; /* We leave ixp_sessions[0] empty */ ++ ixp_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ ixp_sesnum *= 2; ++ ++ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); ++ if (ixpd == NULL) { ++ /* Reset session number */ ++ if (ixp_sesnum == CRYPTO_SW_SESSIONS) ++ ixp_sesnum = 0; ++ else ++ ixp_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); ++ ++ /* Copy existing sessions */ ++ if (ixp_sessions) { ++ memcpy(ixpd, ixp_sessions, ++ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); ++ kfree(ixp_sessions); ++ } ++ ++ ixp_sessions = ixpd; ++ } ++ ++ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), ++ SLAB_ATOMIC); ++ if (ixp_sessions[i] == NULL) { ++ ixp_freesession(NULL, i); ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ ++ *sid = i; ++ ++ ixp = ixp_sessions[i]; ++ memset(ixp, 0, sizeof(*ixp)); ++ ++ ixp->ixp_cipher_alg = -1; ++ ixp->ixp_auth_alg = -1; ++ ixp->ixp_ctx_id = -1; ++ INIT_LIST_HEAD(&ixp->ixp_q); ++ ++ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; ++ ++ while (cri) { ++ switch (cri->cri_alg) { ++ case CRYPTO_DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_3DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_RIJNDAEL128_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only MD5_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_MD5_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only SHA1_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ default: ++ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ cri = cri->cri_next; ++ } ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); ++#else ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); ++#endif ++ ++ return 0; ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++ixp_freesession(device_t dev, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > ixp_sesnum || ixp_sessions == NULL || ++ ixp_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return 0; ++ ++ if (ixp_sessions[sid]) { ++ if (ixp_sessions[sid]->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); ++ ixp_sessions[sid]->ixp_ctx_id = -1; ++ } ++ kfree(ixp_sessions[sid]); ++ } ++ ixp_sessions[sid] = NULL; ++ if (ixp_blocked) { ++ ixp_blocked = 0; ++ crypto_unblock(ixp_id, CRYPTO_SYMQ); ++ } ++ return 0; ++} ++ ++ ++/* ++ * callback for when hash processing is complete ++ */ ++ ++static void ++ixp_hash_perform_cb( ++ UINT32 hash_key_id, ++ IX_MBUF *bufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); ++ ++ if (bufp == NULL) { ++ printk("ixp: NULL buf in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(bufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ /* On success, need to copy hash back into original client buffer */ ++ memcpy(q->ixp_hash_dest, q->ixp_hash_src, ++ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? ++ SHA1_HASH_LEN : MD5_HASH_LEN); ++ } ++ else { ++ printk("ixp: hash perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ /* Free internal buffer used for hashing */ ++ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++/* ++ * setup a request and perform it ++ */ ++static void ++ixp_q_process(struct ixp_q *q) ++{ ++ IxCryptoAccStatus status; ++ struct ixp_data *ixp = q->ixp_q_data; ++ int auth_off = 0; ++ int auth_len = 0; ++ int crypt_off = 0; ++ int crypt_len = 0; ++ int icv_off = 0; ++ char *crypt_func; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, q); ++ ++ if (q->ixp_q_ccrd) { ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; ++ } else { ++ q->ixp_q_iv = q->ixp_q_iv_data; ++ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, ++ q->ixp_q_ccrd->crd_inject, ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, ++ (caddr_t) q->ixp_q_iv); ++ } ++ ++ if (q->ixp_q_acrd) { ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ crypt_off = q->ixp_q_ccrd->crd_skip; ++ crypt_len = q->ixp_q_ccrd->crd_len; ++ } else { /* if (q->ixp_q_acrd) */ ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { ++ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle fragmented skb's yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; ++ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { ++ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; ++ if (uiop->uio_iovcnt != 1) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle more than 1 iovec yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; ++ } else /* contig buffer */ { ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; ++ } ++ ++ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; ++ ++ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { ++ /* ++ * For SHA1 and MD5 hash, need to create an internal buffer that is big ++ * enough to hold the original data + the appropriate padding for the ++ * hash algorithm. ++ */ ++ UINT8 *tbuf = NULL; ++ ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = ++ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; ++ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); ++ ++ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { ++ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", ++ IX_MBUF_MLEN(&q->ixp_q_mbuf)); ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); ++ ++ /* Set location in client buffer to copy hash into */ ++ q->ixp_hash_dest = ++ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; ++ ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; ++ ++ /* Set location in internal buffer for where hash starts */ ++ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; ++ ++ crypt_func = "ixCryptoAccHashPerform"; ++ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, ++ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, ++ &ixp->ixp_hash_key_id); ++ } ++ else { ++ crypt_func = "ixCryptoAccAuthCryptPerform"; ++ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, ++ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, ++ q->ixp_q_iv); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ return; ++ ++ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ ++ printk("ixp: %s failed %u\n", crypt_func, status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ ++done: ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * because we cannot process the Q from the Register callback ++ * we do it here on a task Q. ++ */ ++ ++static void ++ixp_process_pending(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, arg); ++ ++ if (!ixp) ++ return; ++ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ ixp_q_process(q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_process_pending_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ixp_pending_work); ++ ixp_process_pending(ixp); ++} ++#endif ++ ++/* ++ * callback for when context registration is complete ++ */ ++ ++static void ++ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) ++{ ++ int i; ++ struct ixp_data *ixp; ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); ++ ++ /* ++ * free any buffer passed in to this routine ++ */ ++ if (bufp) { ++ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; ++ kfree(IX_MBUF_MDATA(bufp)); ++ IX_MBUF_MDATA(bufp) = NULL; ++ } ++ ++ for (i = 0; i < ixp_sesnum; i++) { ++ ixp = ixp_sessions[i]; ++ if (ixp && ixp->ixp_ctx_id == ctx_id) ++ break; ++ } ++ if (i >= ixp_sesnum) { ++ printk("ixp: invalid context id %d\n", ctx_id); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { ++ /* this is normal to free the first of two buffers */ ++ dprintk("ixp: register not finished yet.\n"); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("ixp: register failed 0x%x\n", status); ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++ return; ++ } ++ ++ /* ++ * we are now registered, we cannot start processing the Q here ++ * or we get strange errors with AES (DES/3DES seem to be ok). ++ */ ++ ixp->ixp_registered = 1; ++ schedule_work(&ixp->ixp_pending_work); ++} ++ ++ ++/* ++ * callback for when data processing is complete ++ */ ++ ++static void ++ixp_perform_cb( ++ UINT32 ctx_id, ++ IX_MBUF *sbufp, ++ IX_MBUF *dbufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, ++ dbufp, status); ++ ++ if (sbufp == NULL) { ++ printk("ixp: NULL sbuf in ixp_perform_cb\n"); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(sbufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in ixp_perform_cb\n"); ++ return; ++ } ++ ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ printk("ixp: perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * registration is not callable at IRQ time, so we defer ++ * to a task queue, this routines completes the registration for us ++ * when the task queue runs ++ * ++ * Unfortunately this means we cannot tell OCF that the driver is blocked, ++ * we do that on the next request. ++ */ ++ ++static void ++ixp_registration(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ IX_MBUF *pri = NULL, *sec = NULL; ++ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; ++ ++ if (!ixp) { ++ printk("ixp: ixp_registration with no arg\n"); ++ return; ++ } ++ ++ if (ixp->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); ++ ixp->ixp_ctx_id = -1; ++ } ++ ++ if (list_empty(&ixp->ixp_q)) { ++ printk("ixp: ixp_registration with no Q\n"); ++ return; ++ } ++ ++ /* ++ * setup the primary and secondary buffers ++ */ ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ if (q->ixp_q_acrd) { ++ pri = &ixp->ixp_pri_mbuf; ++ sec = &ixp->ixp_sec_mbuf; ++ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; ++ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; ++ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ } ++ ++ /* Only need to register if a crypt op or HMAC op */ ++ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || ++ ixp->ixp_auth_alg == CRYPTO_MD5)) { ++ status = ixCryptoAccCtxRegister( ++ &ixp->ixp_ctx, ++ pri, sec, ++ ixp_register_cb, ++ ixp_perform_cb, ++ &ixp->ixp_ctx_id); ++ } ++ else { ++ /* Otherwise we start processing pending q */ ++ schedule_work(&ixp->ixp_pending_work); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ return; ++ ++ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { ++ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); ++ ixp_blocked = 1; ++ /* perhaps we should return EGAIN on queued ops ? */ ++ return; ++ } ++ ++ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); ++ ixp->ixp_ctx_id = -1; ++ ++ /* ++ * everything waiting is toasted ++ */ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_registration_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ++ ixp_registration_work); ++ ixp_registration(ixp); ++} ++#endif ++ ++/* ++ * Process a request. ++ */ ++static int ++ixp_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct ixp_data *ixp; ++ unsigned int lid; ++ struct ixp_q *q = NULL; ++ int status; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (ixp_blocked) ++ return ERESTART; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ /* ++ * find the session we are using ++ */ ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || ++ ixp_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ixp = ixp_sessions[lid]; ++ ++ /* ++ * setup a new request ready for queuing ++ */ ++ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); ++ if (q == NULL) { ++ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); ++ crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ /* ++ * save some cycles by only zeroing the important bits ++ */ ++ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); ++ q->ixp_q_ccrd = NULL; ++ q->ixp_q_acrd = NULL; ++ q->ixp_q_crp = crp; ++ q->ixp_q_data = ixp; ++ ++ /* ++ * point the cipher and auth descriptors appropriately ++ * check that we have something to do ++ */ ++ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc; ++ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ if (crp->crp_desc->crd_next) { ++ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc->crd_next; ++ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc->crd_next; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ } ++ ++ /* ++ * If there is a direction change for this context then we mark it as ++ * unregistered and re-register is for the new direction. This is not ++ * a very expensive operation and currently only tends to happen when ++ * user-space application are doing benchmarks ++ * ++ * DM - we should be checking for pending requests before unregistering. ++ */ ++ if (q->ixp_q_ccrd && ixp->ixp_registered && ++ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { ++ dprintk("%s - detected direction change on session\n", __FUNCTION__); ++ ixp->ixp_registered = 0; ++ } ++ ++ /* ++ * if we are registered, call straight into the perform code ++ */ ++ if (ixp->ixp_registered) { ++ ixp_q_process(q); ++ return 0; ++ } ++ ++ /* ++ * the only part of the context not set in newsession is the direction ++ * dependent parts ++ */ ++ if (q->ixp_q_ccrd) { ++ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; ++ } else { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; ++ } ++ } else { ++ /* q->ixp_q_acrd must be set if we are here */ ++ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; ++ } ++ ++ status = list_empty(&ixp->ixp_q); ++ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); ++ if (status) ++ schedule_work(&ixp->ixp_registration_work); ++ return 0; ++ ++done: ++ if (q) ++ kmem_cache_free(qcache, q); ++ crypto_done(crp); ++ return 0; ++} ++ ++ ++#ifdef __ixp46X ++/* ++ * key processing support for the ixp465 ++ */ ++ ++ ++/* ++ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately ++ * assume zeroed and only copy bits that are significant ++ */ ++ ++static int ++ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) ++{ ++ unsigned char *src = (unsigned char *) p->crp_p; ++ unsigned char *dst; ++ int len, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { ++ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, ++ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); ++ return -1; ++ } ++ ++ len = (bits + 31) / 32; /* the number UINT32's needed */ ++ ++ dst = (unsigned char *) &buf[len]; ++ dst--; ++ ++ while (bits > 0) { ++ *dst-- = *src++; ++ bits -= 8; ++ } ++ ++#if 0 /* no need to zero remaining bits as it is done during request alloc */ ++ while (dst > (unsigned char *) buf) ++ *dst-- = '\0'; ++#endif ++ ++ op->pData = buf; ++ op->dataLen = len; ++ return 0; ++} ++ ++/* ++ * copy out the result, be as forgiving as we can about small output buffers ++ */ ++ ++static int ++ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) ++{ ++ unsigned char *dst = (unsigned char *) p->crp_p; ++ unsigned char *src = (unsigned char *) buf; ++ int len, z, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ len = op->dataLen * sizeof(UINT32); ++ ++ /* skip leading zeroes to be small buffer friendly */ ++ z = 0; ++ while (z < len && src[z] == '\0') ++ z++; ++ ++ src += len; ++ src--; ++ len -= z; ++ ++ while (len > 0 && bits > 0) { ++ *dst++ = *src--; ++ len--; ++ bits -= 8; ++ } ++ ++ while (bits > 0) { ++ *dst++ = '\0'; ++ bits -= 8; ++ } ++ ++ if (len > 0) { ++ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", ++ __FUNCTION__, len, z, p->crp_nbits / 8); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * the parameter offsets for exp_mod ++ */ ++ ++#define IXP_PARAM_BASE 0 ++#define IXP_PARAM_EXP 1 ++#define IXP_PARAM_MOD 2 ++#define IXP_PARAM_RES 3 ++ ++/* ++ * key processing complete callback, is also used to start processing ++ * by passing a NULL for pResult ++ */ ++ ++static void ++ixp_kperform_cb( ++ IxCryptoAccPkeEauOperation operation, ++ IxCryptoAccPkeEauOpResult *pResult, ++ BOOL carryOrBorrow, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_pkq *q, *tmp; ++ unsigned long flags; ++ ++ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, ++ carryOrBorrow, status); ++ ++ /* handle a completed request */ ++ if (pResult) { ++ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { ++ q = ixp_pk_cur; ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ } else { ++ /* copy out the result */ ++ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], ++ &q->pkq_result, q->pkq_obuf)) ++ q->pkq_krp->krp_status = ERANGE; ++ } ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ ixp_pk_cur = NULL; ++ } else ++ printk("%s - callback with invalid result pointer\n", __FUNCTION__); ++ } ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ if (ixp_pk_cur || list_empty(&ixp_pkq)) { ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ return; ++ } ++ ++ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { ++ ++ list_del(&q->pkq_list); ++ ixp_pk_cur = q; ++ ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ status = ixCryptoAccPkeEauPerform( ++ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, ++ &q->pkq_op, ++ ixp_kperform_cb, ++ &q->pkq_result); ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); ++ return; /* callback will return here for callback */ ++ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { ++ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); ++ } else { ++ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", ++ __FUNCTION__, status); ++ } ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ } ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++} ++ ++ ++static int ++ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) ++{ ++ struct ixp_pkq *q; ++ int rc = 0; ++ unsigned long flags; ++ ++ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, ++ krp->krp_param[IXP_PARAM_BASE].crp_nbits, ++ krp->krp_param[IXP_PARAM_EXP].crp_nbits, ++ krp->krp_param[IXP_PARAM_MOD].crp_nbits, ++ krp->krp_param[IXP_PARAM_RES].crp_nbits); ++ ++ ++ if (krp->krp_op != CRK_MOD_EXP) { ++ krp->krp_status = EOPNOTSUPP; ++ goto err; ++ } ++ ++ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); ++ if (q == NULL) { ++ krp->krp_status = ENOMEM; ++ goto err; ++ } ++ ++ /* ++ * The PKE engine does not appear to zero the output buffer ++ * appropriately, so we need to do it all here. ++ */ ++ memset(q, 0, sizeof(*q)); ++ ++ q->pkq_krp = krp; ++ INIT_LIST_HEAD(&q->pkq_list); ++ ++ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, ++ q->pkq_ibuf0)) ++ rc = 1; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], ++ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) ++ rc = 2; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], ++ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) ++ rc = 3; ++ ++ if (rc) { ++ kfree(q); ++ krp->krp_status = ERANGE; ++ goto err; ++ } ++ ++ q->pkq_result.pData = q->pkq_obuf; ++ q->pkq_result.dataLen = ++ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ list_add_tail(&q->pkq_list, &ixp_pkq); ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ if (!ixp_pk_cur) ++ ixp_kperform_cb(0, NULL, 0, 0); ++ return (0); ++ ++err: ++ crypto_kdone(krp); ++ return (0); ++} ++ ++ ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++/* ++ * We run the random number generator output through SHA so that it ++ * is FIPS compliant. ++ */ ++ ++static volatile int sha_done = 0; ++static unsigned char sha_digest[20]; ++ ++static void ++ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) ++{ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); ++ if (sha_digest != digest) ++ printk("digest error\n"); ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ sha_done = 1; ++ else ++ sha_done = -status; ++} ++ ++static int ++ixp_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ IxCryptoAccStatus status; ++ int i, n, rc; ++ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); ++ memset(buf, 0, maxwords * sizeof(*buf)); ++ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", ++ __FUNCTION__, status); ++ return 0; ++ } ++ ++ /* ++ * run the random data through SHA to make it look more random ++ */ ++ ++ n = sizeof(sha_digest); /* process digest bytes at a time */ ++ ++ rc = 0; ++ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { ++ if ((maxwords - i) * sizeof(*buf) < n) ++ n = (maxwords - i) * sizeof(*buf); ++ sha_done = 0; ++ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, ++ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); ++ return -EIO; ++ } ++ while (!sha_done) ++ schedule(); ++ if (sha_done < 0) { ++ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); ++ return 0; ++ } ++ memcpy(&buf[i], sha_digest, n); ++ rc += n / sizeof(*buf);; ++ } ++ ++ return rc; ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++#endif /* __ixp46X */ ++ ++ ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++ ++static int ++ixp_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); ++ ++ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) ++ printk("ixCryptoAccInit failed, assuming already initialised!\n"); ++ ++ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, ++ SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ if (!qcache) { ++ printk("failed to create Qcache\n"); ++ return -ENOENT; ++ } ++ ++ memset(&ixpdev, 0, sizeof(ixpdev)); ++ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); ++ ++ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), ++ CRYPTOCAP_F_HARDWARE); ++ if (ixp_id < 0) ++ panic("IXP/OCF crypto device cannot initialize!"); ++ ++#define REGISTER(alg) \ ++ crypto_register(ixp_id,alg,0,0) ++ ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_RIJNDAEL128_CBC); ++#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_SHA1); ++#endif ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++#ifdef __ixp46X ++ spin_lock_init(&ixp_pkq_lock); ++ /* ++ * we do not enable the go fast options here as they can potentially ++ * allow timing based attacks ++ * ++ * http://www.openssl.org/news/secadv_20030219.txt ++ */ ++ ixCryptoAccPkeEauExpConfig(0, 0); ++ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ crypto_rregister(ixp_id, ixp_read_random, NULL); ++#endif ++#endif ++ ++ return 0; ++} ++ ++static void ++ixp_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(ixp_id); ++ ixp_id = -1; ++ kmem_cache_destroy(qcache); ++ qcache = NULL; ++} ++ ++module_init(ixp_init); ++module_exit(ixp_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/Makefile linux-2.6.39/crypto/ocf/kirkwood/Makefile +--- linux-2.6.39.orig/crypto/ocf/kirkwood/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/Makefile 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,19 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_KIRKWOOD) += mv_cesa.o ++ ++mv_cesa-y := cesa/mvCesa.o cesa/mvLru.o cesa/mvMD5.o cesa/mvSHA1.o cesa/AES/mvAesAlg.o cesa/AES/mvAesApi.o cesa/mvCesaDebug.o cesa_ocf_drv.o ++ ++# Extra objects required by the CESA driver ++mv_cesa-y += mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.o mvHal/kw_family/boardEnv/mvBoardEnvLib.o mvHal/mv_hal/twsi/mvTwsi.o mvHal/kw_family/ctrlEnv/sys/mvCpuIf.o mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.o mvHal/kw_family/ctrlEnv/sys/mvSysDram.o mvHal/linux_oss/mvOs.o mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.o mvHal/mv_hal/gpp/mvGpp.o mvHal/kw_family/ctrlEnv/sys/mvSysPex.o mvHal/mv_hal/pex/mvPex.o mvHal/kw_family/boardEnv/mvBoardEnvSpec.o mvHal/common/mvCommon.o mvHal/common/mvDebug.o mvHal/kw_family/ctrlEnv/sys/mvSysCesa.o ++ ++ifdef src ++EXTRA_CFLAGS += -I$(src)/.. -I$(src)/cesa -I$(src)/mvHal -I$(src)/mvHal/common -I$(src)/mvHal/kw_family -I$(src)/mvHal/mv_hal -I$(src)/mvHal/linux_oss -I$(src) ++endif ++ ++EXTRA_CFLAGS += -DMV_LINUX -DMV_CPU_LE -DMV_ARM -DMV_INCLUDE_CESA -DMV_INCLUDE_PEX -DMV_CACHE_COHERENCY=3 ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAes.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAes.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,62 @@ ++/* mvAes.h v2.0 August '99 ++ * Reference ANSI C code ++ */ ++ ++/* AES Cipher header file for ANSI C Submissions ++ Lawrence E. Bassham III ++ Computer Security Division ++ National Institute of Standards and Technology ++ ++ April 15, 1998 ++ ++ This sample is to assist implementers developing to the Cryptographic ++API Profile for AES Candidate Algorithm Submissions. Please consult this ++document as a cross-reference. ++ ++ ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE ++MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH ++THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT ++BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE ++IMPLEMENTATION SPECIFIC INFORMATION. ++*/ ++ ++/* Includes: ++ Standard include files ++*/ ++ ++#include "mvOs.h" ++ ++ ++/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */ ++ ++/* Key direction is invalid, e.g., unknown value */ ++#define AES_BAD_KEY_DIR -1 ++ ++/* Key material not of correct length */ ++#define AES_BAD_KEY_MAT -2 ++ ++/* Key passed is not valid */ ++#define AES_BAD_KEY_INSTANCE -3 ++ ++/* Params struct passed to cipherInit invalid */ ++#define AES_BAD_CIPHER_MODE -4 ++ ++/* Cipher in wrong state (e.g., not initialized) */ ++#define AES_BAD_CIPHER_STATE -5 ++ ++#define AES_BAD_CIPHER_INSTANCE -7 ++ ++ ++/* Function protoypes */ ++/* CHANGED: makeKey(): parameter blockLen added ++ this parameter is absolutely necessary if you want to ++ setup the round keys in a variable block length setting ++ cipherInit(): parameter blockLen added (for obvious reasons) ++ */ ++int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen); ++int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, ++ MV_U32 *plain, int numBlocks, MV_U32 *cipher); ++int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, ++ MV_U32 *plain, int numBlocks, MV_U32 *cipher); ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,317 @@ ++/* rijndael-alg-ref.c v2.0 August '99 ++ * Reference ANSI C code ++ * authors: Paulo Barreto ++ * Vincent Rijmen, K.U.Leuven ++ * ++ * This code is placed in the public domain. ++ */ ++ ++#include "mvOs.h" ++ ++#include "mvAesAlg.h" ++ ++#include "mvAesBoxes.dat" ++ ++ ++MV_U8 mul1(MV_U8 aa, MV_U8 bb); ++void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); ++void ShiftRow128Enc(MV_U8 a[4][MAXBC]); ++void ShiftRow128Dec(MV_U8 a[4][MAXBC]); ++void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); ++void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); ++void InvMixColumn(MV_U8 a[4][MAXBC]); ++ ++ ++#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) ++ ++MV_U8 mul1(MV_U8 aa, MV_U8 bb) ++{ ++ return mask[bb] & Alogtable[aa + Logtable[bb]]; ++} ++ ++ ++void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) ++{ ++ /* Exor corresponding text input and round key input bytes ++ */ ++ ((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0]; ++ ((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0]; ++ ((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0]; ++ ((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0]; ++ ++} ++ ++void ShiftRow128Enc(MV_U8 a[4][MAXBC]) { ++ /* Row 0 remains unchanged ++ * The other three rows are shifted a variable amount ++ */ ++ MV_U8 tmp[MAXBC]; ++ ++ tmp[0] = a[1][1]; ++ tmp[1] = a[1][2]; ++ tmp[2] = a[1][3]; ++ tmp[3] = a[1][0]; ++ ++ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[1][0] = tmp[0]; ++ a[1][1] = tmp[1]; ++ a[1][2] = tmp[2]; ++ a[1][3] = tmp[3]; ++ */ ++ tmp[0] = a[2][2]; ++ tmp[1] = a[2][3]; ++ tmp[2] = a[2][0]; ++ tmp[3] = a[2][1]; ++ ++ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[2][0] = tmp[0]; ++ a[2][1] = tmp[1]; ++ a[2][2] = tmp[2]; ++ a[2][3] = tmp[3]; ++ */ ++ tmp[0] = a[3][3]; ++ tmp[1] = a[3][0]; ++ tmp[2] = a[3][1]; ++ tmp[3] = a[3][2]; ++ ++ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[3][0] = tmp[0]; ++ a[3][1] = tmp[1]; ++ a[3][2] = tmp[2]; ++ a[3][3] = tmp[3]; ++ */ ++} ++ ++void ShiftRow128Dec(MV_U8 a[4][MAXBC]) { ++ /* Row 0 remains unchanged ++ * The other three rows are shifted a variable amount ++ */ ++ MV_U8 tmp[MAXBC]; ++ ++ tmp[0] = a[1][3]; ++ tmp[1] = a[1][0]; ++ tmp[2] = a[1][1]; ++ tmp[3] = a[1][2]; ++ ++ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[1][0] = tmp[0]; ++ a[1][1] = tmp[1]; ++ a[1][2] = tmp[2]; ++ a[1][3] = tmp[3]; ++ */ ++ ++ tmp[0] = a[2][2]; ++ tmp[1] = a[2][3]; ++ tmp[2] = a[2][0]; ++ tmp[3] = a[2][1]; ++ ++ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[2][0] = tmp[0]; ++ a[2][1] = tmp[1]; ++ a[2][2] = tmp[2]; ++ a[2][3] = tmp[3]; ++ */ ++ ++ tmp[0] = a[3][1]; ++ tmp[1] = a[3][2]; ++ tmp[2] = a[3][3]; ++ tmp[3] = a[3][0]; ++ ++ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[3][0] = tmp[0]; ++ a[3][1] = tmp[1]; ++ a[3][2] = tmp[2]; ++ a[3][3] = tmp[3]; ++ */ ++} ++ ++void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) { ++ /* Replace every byte of the input by the byte at that place ++ * in the nonlinear S-box ++ */ ++ int i, j; ++ ++ for(i = 0; i < 4; i++) ++ for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ; ++} ++ ++void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) { ++ /* Mix the four bytes of every column in a linear way ++ */ ++ MV_U8 b[4][MAXBC]; ++ int i, j; ++ ++ for(j = 0; j < 4; j++){ ++ b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j]; ++ b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j]; ++ b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j]; ++ b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j]; ++ } ++ for(i = 0; i < 4; i++) ++ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ ++ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; ++} ++ ++void InvMixColumn(MV_U8 a[4][MAXBC]) { ++ /* Mix the four bytes of every column in a linear way ++ * This is the opposite operation of Mixcolumn ++ */ ++ MV_U8 b[4][MAXBC]; ++ int i, j; ++ ++ for(j = 0; j < 4; j++){ ++ b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]); ++ b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]); ++ b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]); ++ b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]); ++ } ++ for(i = 0; i < 4; i++) ++ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ ++ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0]; ++} ++ ++int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC]) ++{ ++ /* Calculate the necessary round keys ++ * The number of calculations depends on keyBits and blockBits ++ */ ++ int KC, BC, ROUNDS; ++ int i, j, t, rconpointer = 0; ++ MV_U8 tk[4][MAXKC]; ++ ++ switch (keyBits) { ++ case 128: KC = 4; break; ++ case 192: KC = 6; break; ++ case 256: KC = 8; break; ++ default : return (-1); ++ } ++ ++ switch (blockBits) { ++ case 128: BC = 4; break; ++ case 192: BC = 6; break; ++ case 256: BC = 8; break; ++ default : return (-2); ++ } ++ ++ switch (keyBits >= blockBits ? keyBits : blockBits) { ++ case 128: ROUNDS = 10; break; ++ case 192: ROUNDS = 12; break; ++ case 256: ROUNDS = 14; break; ++ default : return (-3); /* this cannot happen */ ++ } ++ ++ ++ for(j = 0; j < KC; j++) ++ for(i = 0; i < 4; i++) ++ tk[i][j] = k[i][j]; ++ t = 0; ++ /* copy values into round key array */ ++ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) ++ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; ++ ++ while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */ ++ /* calculate new values */ ++ for(i = 0; i < 4; i++) ++ tk[i][0] ^= S[tk[(i+1)%4][KC-1]]; ++ tk[0][0] ^= rcon[rconpointer++]; ++ ++ if (KC != 8) ++ for(j = 1; j < KC; j++) ++ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; ++ else { ++ for(j = 1; j < KC/2; j++) ++ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; ++ for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]]; ++ for(j = KC/2 + 1; j < KC; j++) ++ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; ++ } ++ /* copy values into round key array */ ++ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) ++ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; ++ } ++ ++ return 0; ++} ++ ++ ++ ++int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) ++{ ++ /* Encryption of one block. ++ */ ++ int r, BC, ROUNDS; ++ ++ BC = 4; ++ ROUNDS = rounds; ++ ++ /* begin with a key addition ++ */ ++ ++ KeyAddition(a,rk[0],BC); ++ ++ /* ROUNDS-1 ordinary rounds ++ */ ++ for(r = 1; r < ROUNDS; r++) { ++ Substitution(a,S); ++ ShiftRow128Enc(a); ++ MixColumn(a, rk[r]); ++ /*KeyAddition(a,rk[r],BC);*/ ++ } ++ ++ /* Last round is special: there is no MixColumn ++ */ ++ Substitution(a,S); ++ ShiftRow128Enc(a); ++ KeyAddition(a,rk[ROUNDS],BC); ++ ++ return 0; ++} ++ ++ ++int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) ++{ ++ int r, BC, ROUNDS; ++ ++ BC = 4; ++ ROUNDS = rounds; ++ ++ /* To decrypt: apply the inverse operations of the encrypt routine, ++ * in opposite order ++ * ++ * (KeyAddition is an involution: it 's equal to its inverse) ++ * (the inverse of Substitution with table S is Substitution with the inverse table of S) ++ * (the inverse of Shiftrow is Shiftrow over a suitable distance) ++ */ ++ ++ /* First the special round: ++ * without InvMixColumn ++ * with extra KeyAddition ++ */ ++ KeyAddition(a,rk[ROUNDS],BC); ++ ShiftRow128Dec(a); ++ Substitution(a,Si); ++ ++ /* ROUNDS-1 ordinary rounds ++ */ ++ for(r = ROUNDS-1; r > 0; r--) { ++ KeyAddition(a,rk[r],BC); ++ InvMixColumn(a); ++ ShiftRow128Dec(a); ++ Substitution(a,Si); ++ ++ } ++ ++ /* End with the extra key addition ++ */ ++ ++ KeyAddition(a,rk[0],BC); ++ ++ return 0; ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,19 @@ ++/* rijndael-alg-ref.h v2.0 August '99 ++ * Reference ANSI C code ++ * authors: Paulo Barreto ++ * Vincent Rijmen, K.U.Leuven ++ */ ++#ifndef __RIJNDAEL_ALG_H ++#define __RIJNDAEL_ALG_H ++ ++#define MAXBC (128/32) ++#define MAXKC (256/32) ++#define MAXROUNDS 14 ++ ++ ++int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]); ++ ++int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); ++int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); ++ ++#endif /* __RIJNDAEL_ALG_H */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,312 @@ ++/* rijndael-api-ref.c v2.1 April 2000 ++ * Reference ANSI C code ++ * authors: v2.0 Paulo Barreto ++ * Vincent Rijmen, K.U.Leuven ++ * v2.1 Vincent Rijmen, K.U.Leuven ++ * ++ * This code is placed in the public domain. ++ */ ++#include "mvOs.h" ++ ++#include "mvAes.h" ++#include "mvAesAlg.h" ++ ++ ++/* Defines: ++ Add any additional defines you need ++*/ ++ ++#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ ++#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ ++#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ ++ ++ ++int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) ++{ ++ MV_U8 W[MAXROUNDS+1][4][MAXBC]; ++ MV_U8 k[4][MAXKC]; ++ MV_U8 j; ++ int i, rounds, KC; ++ ++ if (expandedKey == NULL) ++ { ++ return AES_BAD_KEY_INSTANCE; ++ } ++ ++ if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) ++ { ++ return AES_BAD_KEY_MAT; ++ } ++ ++ if (keyMaterial == NULL) ++ { ++ return AES_BAD_KEY_MAT; ++ } ++ ++ /* initialize key schedule: */ ++ for(i=0; i= 3) ++MV_U32 cesaChainLength = 0; ++int chainReqNum = 0; ++MV_U32 chainIndex = 0; ++MV_CESA_REQ* pNextActiveChain = 0; ++MV_CESA_REQ* pEndCurrChain = 0; ++MV_BOOL isFirstReq = MV_TRUE; ++#endif ++ ++static INLINE MV_U8* mvCesaSramAddrGet(void) ++{ ++#ifdef MV_CESA_NO_SRAM ++ return (MV_U8*)cesaSramVirtPtr; ++#else ++ return (MV_U8*)cesaCryptEngBase; ++#endif /* MV_CESA_NO_SRAM */ ++} ++ ++static INLINE MV_ULONG mvCesaSramVirtToPhys(void* pDev, MV_U8* pSramVirt) ++{ ++#ifdef MV_CESA_NO_SRAM ++ return (MV_ULONG)mvOsIoVirtToPhy(NULL, pSramVirt); ++#else ++ return (MV_ULONG)pSramVirt; ++#endif /* MV_CESA_NO_SRAM */ ++} ++ ++/* Internal Function prototypes */ ++ ++static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, ++ int cryptoOffset, int ivOffset, int cryptoLength, ++ int macOffset, int digestOffset, int macLength, int macTotalLen, ++ MV_CESA_REQ *pCesaReq, MV_DMA_DESC* pDmaDesc); ++ ++static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); ++ ++static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, ++ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, ++ int offset, int copySize, MV_BOOL skipFlush); ++ ++static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, ++ unsigned char innerIV[], unsigned char outerIV[]); ++ ++static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ* pReq, MV_CESA_SA* pSA, ++ int macDataSize); ++ ++static MV_CESA_COMMAND* mvCesaCtrModeInit(void); ++ ++static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); ++static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); ++static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); ++ ++static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq); ++static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag); ++ ++static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset); ++static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd); ++ ++static INLINE void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, ++ int cryptoOffset, int macOffset, ++ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize); ++static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size); ++ ++ ++/* Go to the next request in the request queue */ ++static INLINE MV_CESA_REQ* MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ* pReq) ++{ ++ if(pReq == pCesaReqLast) ++ return pCesaReqFirst; ++ ++ return pReq+1; ++} ++ ++#if (MV_CESA_VERSION >= 3) ++/* Go to the previous request in the request queue */ ++static INLINE MV_CESA_REQ* MV_CESA_REQ_PREV_PTR(MV_CESA_REQ* pReq) ++{ ++ if(pReq == pCesaReqFirst) ++ return pCesaReqLast; ++ ++ return pReq-1; ++} ++ ++#endif ++ ++ ++static INLINE void mvCesaReqProcessStart(MV_CESA_REQ* pReq) ++{ ++ int frag; ++ ++#if (MV_CESA_VERSION >= 3) ++ pReq->state = MV_CESA_CHAIN; ++#else ++ pReq->state = MV_CESA_PROCESS; ++#endif ++ cesaStats.startCount++; ++ ++ if(pReq->fragMode == MV_CESA_FRAG_NONE) ++ { ++ frag = 0; ++ } ++ else ++ { ++ frag = pReq->frags.nextFrag; ++ pReq->frags.nextFrag++; ++ } ++#if (MV_CESA_VERSION >= 2) ++ /* Enable TDMA engine */ ++ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); ++ MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, ++ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); ++#else ++ /* Enable IDMA engine */ ++ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); ++ MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), ++ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); ++#endif /* MV_CESA_VERSION >= 2 */ ++ ++#if defined(MV_BRIDGE_SYNC_REORDER) ++ mvOsBridgeReorderWA(); ++#endif ++ ++ /* Start Accelerator */ ++ MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); ++} ++ ++ ++/******************************************************************************* ++* mvCesaHalInit - Initialize the CESA driver ++* ++* DESCRIPTION: ++* This function initialize the CESA driver. ++* 1) Session database ++* 2) Request queue ++* 4) DMA descriptor lists - one list per request. Each list ++* has MV_CESA_MAX_DMA_DESC descriptors. ++* ++* INPUT: ++* numOfSession - maximum number of supported sessions ++* queueDepth - number of elements in the request queue. ++* pSramBase - virtual address of Sram ++* osHandle - A handle used by the OS to allocate memory for the ++* module (Passed to the OS Services layer) ++* ++* RETURN: ++* MV_OK - Success ++* MV_NO_RESOURCE - Fail, can't allocate resources: ++* Session database, request queue, ++* DMA descriptors list, LRU cache database. ++* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, ++ void *osHandle) ++{ ++ int i, req; ++ MV_U32 descOffsetReg, configReg; ++ MV_CESA_SRAM_SA *pSramSA; ++ ++ ++ mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSram=%p\n", ++ numOfSession, queueDepth, pSramBase); ++ ++ cesaOsHandle = osHandle; ++ /* Create Session database */ ++ pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA)*numOfSession); ++ if(pCesaSAD == NULL) ++ { ++ mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", ++ sizeof(MV_CESA_SA)*numOfSession, numOfSession); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(pCesaSAD, 0, sizeof(MV_CESA_SA)*numOfSession); ++ cesaMaxSA = numOfSession; ++ ++ /* Allocate imag of sramSA in the DRAM */ ++ cesaSramSaBuf.bufSize = sizeof(MV_CESA_SRAM_SA)*numOfSession + ++ CPU_D_CACHE_LINE_SIZE; ++ ++ cesaSramSaBuf.bufVirtPtr = mvOsIoCachedMalloc(osHandle,cesaSramSaBuf.bufSize, ++ &cesaSramSaBuf.bufPhysAddr, ++ &cesaSramSaBuf.memHandle); ++ ++ if(cesaSramSaBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("mvCesaInit: Can't allocate %d bytes for sramSA structures\n", ++ cesaSramSaBuf.bufSize); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(cesaSramSaBuf.bufVirtPtr, 0, cesaSramSaBuf.bufSize); ++ pSramSA = (MV_CESA_SRAM_SA*)MV_ALIGN_UP((MV_ULONG)cesaSramSaBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ for(i=0; i= 3) ++ cesaChainLength = MAX_CESA_CHAIN_LENGTH; ++#endif ++ /* pSramBase must be 8 byte aligned */ ++ if( MV_IS_NOT_ALIGN((MV_ULONG)pSramBase, 8) ) ++ { ++ mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", ++ pSramBase); ++ mvCesaFinish(); ++ return MV_NOT_ALIGNED; ++ } ++ cesaSramVirtPtr = (MV_CESA_SRAM_MAP*)pSramBase; ++ ++ cesaCryptEngBase = cryptEngBase; ++ ++ /*memset(cesaSramVirtPtr, 0, sizeof(MV_CESA_SRAM_MAP));*/ ++ ++ /* Clear registers */ ++ MV_REG_WRITE( MV_CESA_CFG_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); ++ ++ /* Initialize DMA descriptor lists for all requests in Request queue */ ++ descOffsetReg = configReg = 0; ++ for(req=0; reqcesaDescBuf.bufSize = sizeof(MV_CESA_DESC)*MV_CESA_MAX_REQ_FRAGS + ++ CPU_D_CACHE_LINE_SIZE; ++ ++ pReq->cesaDescBuf.bufVirtPtr = ++ mvOsIoCachedMalloc(osHandle,pReq->cesaDescBuf.bufSize, ++ &pReq->cesaDescBuf.bufPhysAddr, ++ &pReq->cesaDescBuf.memHandle); ++ ++ if(pReq->cesaDescBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", ++ req, pReq->cesaDescBuf.bufSize); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); ++ pReq->pCesaDesc = (MV_CESA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->cesaDescBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC)*MV_CESA_MAX_DMA_DESC*MV_CESA_MAX_REQ_FRAGS + ++ CPU_D_CACHE_LINE_SIZE; ++ ++ pReq->dmaDescBuf.bufVirtPtr = ++ mvOsIoCachedMalloc(osHandle,pReq->dmaDescBuf.bufSize, ++ &pReq->dmaDescBuf.bufPhysAddr, ++ &pReq->dmaDescBuf.memHandle); ++ ++ if(pReq->dmaDescBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", ++ req, pReq->dmaDescBuf.bufSize); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); ++ pDmaDesc = (MV_DMA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->dmaDescBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ for(frag=0; fragdma[frag]; ++ ++ pDma->pDmaFirst = pDmaDesc; ++ pDma->pDmaLast = NULL; ++ ++ for(i=0; ipDmaFirst[i].phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i+1])); ++ } ++ pDma->pDmaFirst[i].phyNextDescPtr = 0; ++ mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC*sizeof(MV_DMA_DESC)); ++ ++ pDmaDesc += MV_CESA_MAX_DMA_DESC; ++ } ++ } ++ /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH);*/ ++ descOffsetReg = (MV_U16)((MV_U8*)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); ++ MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); ++ ++ configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); ++#if (MV_CESA_VERSION >= 3) ++ configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; ++#endif ++ ++#if (MV_CESA_VERSION >= 2) ++ /* Initialize TDMA engine */ ++ MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); ++ MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); ++ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); ++#else ++ /* Initialize IDMA #0 engine */ ++ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); ++ MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); ++ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); ++ MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE ++#ifdef MV_CPU_LE ++ | ICCHR_DESC_BYTE_SWAP_EN ++#endif ++ ); ++ /* Clear Cause Byte of IDMA channel to be used */ ++ MV_REG_WRITE( IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); ++ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); ++#endif /* (MV_CESA_VERSION >= 2) */ ++ ++ /* Set CESA configuration registers */ ++ MV_REG_WRITE( MV_CESA_CFG_REG, configReg); ++ mvCesaDebugStatsClear(); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaFinish - Shutdown the CESA driver ++* ++* DESCRIPTION: ++* This function shutdown the CESA driver and free all allocted resources. ++* ++* INPUT: None ++* ++* RETURN: ++* MV_OK - Success ++* Other - Fail ++* ++*******************************************************************************/ ++MV_STATUS mvCesaFinish (void) ++{ ++ int req; ++ MV_CESA_REQ* pReq; ++ ++ mvOsPrintf("mvCesaFinish: \n"); ++ ++ cesaSramVirtPtr = NULL; ++ ++ /* Free all resources: DMA list, etc. */ ++ for(req=0; reqdmaDescBuf.bufVirtPtr != NULL) ++ { ++ mvOsIoCachedFree(cesaOsHandle,pReq->dmaDescBuf.bufSize, ++ pReq->dmaDescBuf.bufPhysAddr, ++ pReq->dmaDescBuf.bufVirtPtr, ++ pReq->dmaDescBuf.memHandle); ++ } ++ if(pReq->cesaDescBuf.bufVirtPtr != NULL) ++ { ++ mvOsIoCachedFree(cesaOsHandle,pReq->cesaDescBuf.bufSize, ++ pReq->cesaDescBuf.bufPhysAddr, ++ pReq->cesaDescBuf.bufVirtPtr, ++ pReq->cesaDescBuf.memHandle); ++ } ++ } ++#if (MV_CESA_VERSION < 2) ++ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); ++#endif /* (MV_CESA_VERSION < 2) */ ++ ++ /* Free request queue */ ++ if(pCesaReqFirst != NULL) ++ { ++ mvOsFree(pCesaReqFirst); ++ pCesaReqFirst = pCesaReqLast = NULL; ++ pCesaReqEmpty = pCesaReqProcess = NULL; ++ cesaQueueDepth = cesaReqResources = 0; ++ } ++ /* Free SA database */ ++ if(pCesaSAD != NULL) ++ { ++ mvOsFree(pCesaSAD); ++ pCesaSAD = NULL; ++ cesaMaxSA = 0; ++ } ++ MV_REG_WRITE( MV_CESA_CFG_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode ++* ++* DESCRIPTION: ++* This function set IV value using by Crypto algorithms in CBC mode. ++* Each channel has its own IV value. ++* This function gets IV value from the caller. If no IV value passed from ++* the caller or only part of IV passed, the function will init the rest part ++* of IV value (or the whole IV) by random value. ++* ++* INPUT: ++* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL ++* the function will generate random IV value. ++* int ivSize - size (in bytes) of IV provided by user. If ivSize is ++* smaller than maximum IV size, the function will complete ++* IV by random value. ++* ++* RETURN: ++* MV_OK - Success ++* Other - Fail ++* ++*******************************************************************************/ ++MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize) ++{ ++ MV_U8* pSramIV; ++#if defined(MV646xx) ++ mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); ++#endif ++ pSramIV = cesaSramVirtPtr->cryptoIV; ++ if(ivSize > MV_CESA_MAX_IV_LENGTH) ++ { ++ mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); ++ ivSize = MV_CESA_MAX_IV_LENGTH; ++ } ++ if(pIV != NULL) ++ { ++ memcpy(pSramIV, pIV, ivSize); ++ ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; ++ pSramIV += ivSize; ++ } ++ ++ while(ivSize > 0) ++ { ++ int size, mv_random = mvOsRand(); ++ ++ size = MV_MIN(ivSize, sizeof(mv_random)); ++ memcpy(pSramIV, (void*)&mv_random, size); ++ ++ pSramIV += size; ++ ivSize -= size; ++ } ++/* ++ mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, ++ MV_CESA_MAX_IV_LENGTH); ++ mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, ++ MV_CESA_MAX_IV_LENGTH); ++*/ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaSessionOpen - Open new uni-directional crypto session ++* ++* DESCRIPTION: ++* This function open new session. ++* ++* INPUT: ++* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters ++* ++* OUTPUT: ++* short *pSid - session ID, should be used for all future ++* requests over this session. ++* ++* RETURN: ++* MV_OK - Session opend successfully. ++* MV_FULL - All sessions are in use, no free place in ++* SA database. ++* MV_BAD_PARAM - One of session input parameters is invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid) ++{ ++ short sid; ++ MV_U32 config = 0; ++ int digestSize; ++ ++ cesaStats.openedCount++; ++ ++ /* Find free entry in SAD */ ++ for(sid=0; sidoperation >= MV_CESA_MAX_OPERATION) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", ++ pSession->operation); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); ++ ++ if( (pSession->direction != MV_CESA_DIR_ENCODE) && ++ (pSession->direction != MV_CESA_DIR_DECODE) ) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", ++ pSession->direction); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->direction << MV_CESA_DIRECTION_BIT); ++ /* Clear SA entry */ ++ /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ ++ ++ /* Check AUTH parameters and update SA entry */ ++ if(pSession->operation != MV_CESA_CRYPTO_ONLY) ++ { ++ /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ ++ if( (pSession->macMode == MV_CESA_MAC_HMAC_MD5) || ++ (pSession->macMode == MV_CESA_MAC_HMAC_SHA1) ) ++ { ++ if(pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) ++ { ++ mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", ++ pSession->macKeyLength); ++ return MV_BAD_PARAM; ++ } ++ mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, ++ pCesaSAD[sid].pSramSA->macInnerIV, ++ pCesaSAD[sid].pSramSA->macOuterIV); ++ pCesaSAD[sid].macKeyLength = pSession->macKeyLength; ++ } ++ switch(pSession->macMode) ++ { ++ case MV_CESA_MAC_MD5: ++ case MV_CESA_MAC_HMAC_MD5: ++ digestSize = MV_CESA_MD5_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_SHA1: ++ case MV_CESA_MAC_HMAC_SHA1: ++ digestSize = MV_CESA_SHA1_DIGEST_SIZE; ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", ++ pSession->macMode); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); ++ ++ /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ ++ /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ ++ if( (pSession->digestSize != digestSize) && (pSession->digestSize != 12)) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", ++ pSession->digestSize); ++ mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); ++ return MV_BAD_PARAM; ++ } ++ pCesaSAD[sid].digestSize = pSession->digestSize; ++ ++ if(pCesaSAD[sid].digestSize == 12) ++ { ++ /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ ++ config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); ++ } ++ } ++ ++ /* Check CRYPTO parameters and update SA entry */ ++ if(pSession->operation != MV_CESA_MAC_ONLY) ++ { ++ switch(pSession->cryptoAlgorithm) ++ { ++ case MV_CESA_CRYPTO_DES: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; ++ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; ++ break; ++ ++ case MV_CESA_CRYPTO_3DES: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; ++ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; ++ /* Only EDE mode is supported */ ++ config |= (MV_CESA_CRYPTO_3DES_EDE << ++ MV_CESA_CRYPTO_3DES_MODE_BIT); ++ break; ++ ++ case MV_CESA_CRYPTO_AES: ++ switch(pSession->cryptoKeyLength) ++ { ++ case 16: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; ++ config |= (MV_CESA_CRYPTO_AES_KEY_128 << ++ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); ++ break; ++ ++ case 24: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; ++ config |= (MV_CESA_CRYPTO_AES_KEY_192 << ++ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); ++ break; ++ ++ case 32: ++ default: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; ++ config |= (MV_CESA_CRYPTO_AES_KEY_256 << ++ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); ++ break; ++ } ++ pCesaSAD[sid].cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", ++ pSession->cryptoAlgorithm); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); ++ ++ if(pSession->cryptoKeyLength != pCesaSAD[sid].cryptoKeyLength) ++ { ++ mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", ++ pSession->cryptoKeyLength, pCesaSAD[sid].cryptoKeyLength); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Copy Crypto key */ ++ if( (pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && ++ (pSession->direction == MV_CESA_DIR_DECODE)) ++ { ++ /* Crypto Key for AES decode is computed from original key material */ ++ /* and depend on cryptoKeyLength (128/192/256 bits) */ ++ aesMakeKey(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, ++ pSession->cryptoKeyLength*8, MV_CESA_AES_BLOCK_SIZE*8); ++ } ++ else ++ { ++ /*panic("mvCesaSessionOpen2");*/ ++ memcpy(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, ++ pCesaSAD[sid].cryptoKeyLength); ++ ++ } ++ ++ switch(pSession->cryptoMode) ++ { ++ case MV_CESA_CRYPTO_ECB: ++ pCesaSAD[sid].cryptoIvSize = 0; ++ break; ++ ++ case MV_CESA_CRYPTO_CBC: ++ pCesaSAD[sid].cryptoIvSize = pCesaSAD[sid].cryptoBlockSize; ++ break; ++ ++ case MV_CESA_CRYPTO_CTR: ++ /* Supported only for AES algorithm */ ++ if(pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) ++ { ++ mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); ++ return MV_BAD_PARAM; ++ } ++ pCesaSAD[sid].cryptoIvSize = 0; ++ pCesaSAD[sid].ctrMode = 1; ++ /* Replace to ECB mode for HW */ ++ pSession->cryptoMode = MV_CESA_CRYPTO_ECB; ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", ++ pSession->cryptoMode); ++ return MV_BAD_PARAM; ++ } ++ ++ config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); ++ } ++ pCesaSAD[sid].config = config; ++ ++ mvOsCacheFlush(NULL, pCesaSAD[sid].pSramSA, sizeof(MV_CESA_SRAM_SA)); ++ if(pSid != NULL) ++ *pSid = sid; ++ ++ pCesaSAD[sid].valid = 1; ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaSessionClose - Close active crypto session ++* ++* DESCRIPTION: ++* This function closes existing session ++* ++* INPUT: ++* short sid - Unique identifier of the session to be closed ++* ++* RETURN: ++* MV_OK - Session closed successfully. ++* MV_BAD_PARAM - Session identifier is out of valid range. ++* MV_NOT_FOUND - There is no active session with such ID. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaSessionClose(short sid) ++{ ++ cesaStats.closedCount++; ++ ++ if(sid >= cesaMaxSA) ++ { ++ mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); ++ return MV_BAD_PARAM; ++ } ++ if(pCesaSAD[sid].valid == 0) ++ { ++ mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); ++ return MV_NOT_FOUND; ++ } ++ if(cesaLastSid == sid) ++ cesaLastSid = -1; ++ ++ pCesaSAD[sid].valid = 0; ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaAction - Perform crypto operation ++* ++* DESCRIPTION: ++* This function set new CESA request FIFO queue for further HW processing. ++* The function checks request parameters before set new request to the queue. ++* If one of the CESA channels is ready for processing the request will be ++* passed to HW. When request processing is finished the CESA interrupt will ++* be generated by HW. The caller should call mvCesaReadyGet() function to ++* complete request processing and get result. ++* ++* INPUT: ++* MV_CESA_COMMAND *pCmd - pointer to new CESA request. ++* It includes pointers to Source and Destination ++* buffers, session identifier get from ++* mvCesaSessionOpen() function, pointer to caller ++* private data and all needed crypto parameters. ++* ++* RETURN: ++* MV_OK - request successfully added to request queue ++* and will be processed. ++* MV_NO_MORE - request successfully added to request queue and will ++* be processed, but request queue became Full and next ++* request will not be accepted. ++* MV_NO_RESOURCE - request queue is FULL and the request can not ++* be processed. ++* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is ++* failed. Request can not be processed. ++* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed ++* as one request and should be splitted for two requests: ++* CRYPTO_ONLY and MAC_ONLY. ++* MV_BAD_PARAM - One of the request parameters is out of valid range. ++* The request can not be processed. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaAction (MV_CESA_COMMAND *pCmd) ++{ ++ MV_STATUS status; ++ MV_CESA_REQ* pReq = pCesaReqEmpty; ++ int sid = pCmd->sessionId; ++ MV_CESA_SA* pSA = &pCesaSAD[sid]; ++#if (MV_CESA_VERSION >= 3) ++ MV_CESA_REQ* pFromReq; ++ MV_CESA_REQ* pToReq; ++#endif ++ cesaStats.reqCount++; ++ ++ /* Check that the request queue is not FULL */ ++ if(cesaReqResources == 0) ++ return MV_NO_RESOURCE; ++ ++ if( (sid >= cesaMaxSA) || (!pSA->valid) ) ++ { ++ mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); ++ return MV_BAD_PARAM; ++ } ++ pSA->count++; ++ ++ if(pSA->ctrMode) ++ { ++ /* AES in CTR mode can't be mixed with Authentication */ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); ++ return MV_NOT_ALLOWED; ++ } ++ /* All other request parameters should not be checked because key stream */ ++ /* (not user data) processed by AES HW engine */ ++ pReq->pOrgCmd = pCmd; ++ /* Allocate temporary pCmd structure for Key stream */ ++ pCmd = mvCesaCtrModeInit(); ++ if(pCmd == NULL) ++ return MV_OUT_OF_CPU_MEM; ++ ++ /* Prepare Key stream */ ++ mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); ++ pReq->fixOffset = 0; ++ } ++ else ++ { ++ /* Check request parameters and calculae fixOffset */ ++ status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); ++ if(status != MV_OK) ++ { ++ return status; ++ } ++ } ++ pReq->pCmd = pCmd; ++ ++ /* Check if the packet need fragmentation */ ++ if(pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf) ) ++ { ++ /* request size is smaller than single buffer size */ ++ pReq->fragMode = MV_CESA_FRAG_NONE; ++ ++ /* Prepare NOT fragmented packets */ ++ status = mvCesaReqProcess(pReq); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", ++ pReq, status); ++ } ++#if (MV_CESA_VERSION >= 3) ++ pReq->frags.numFrag = 1; ++#endif ++ } ++ else ++ { ++ MV_U8 frag = 0; ++ ++ /* request size is larger than buffer size - needs fragmentation */ ++ ++ /* Check restrictions for processing fragmented packets */ ++ status = mvCesaFragParamCheck(pSA, pCmd); ++ if(status != MV_OK) ++ return status; ++ ++ pReq->fragMode = MV_CESA_FRAG_FIRST; ++ pReq->frags.nextFrag = 0; ++ ++ /* Prepare Process Fragmented packets */ ++ while(pReq->fragMode != MV_CESA_FRAG_LAST) ++ { ++ if(frag >= MV_CESA_MAX_REQ_FRAGS) ++ { ++ mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); ++ return MV_OUT_OF_CPU_MEM; ++ } ++ status = mvCesaFragReqProcess(pReq, frag); ++ if(status == MV_OK) { ++#if (MV_CESA_VERSION >= 3) ++ if(frag) { ++ pReq->dma[frag-1].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); ++ mvOsCacheFlush(NULL, pReq->dma[frag-1].pDmaLast, sizeof(MV_DMA_DESC)); ++ } ++#endif ++ frag++; ++ } ++ } ++ pReq->frags.numFrag = frag; ++#if (MV_CESA_VERSION >= 3) ++ if(chainReqNum) { ++ chainReqNum += pReq->frags.numFrag; ++ if(chainReqNum >= MAX_CESA_CHAIN_LENGTH) ++ chainReqNum = MAX_CESA_CHAIN_LENGTH; ++ } ++#endif ++ } ++ ++ pReq->state = MV_CESA_PENDING; ++ ++ pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); ++ cesaReqResources -= 1; ++ ++/* #ifdef CESA_DEBUG */ ++ if( (cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) ++ cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); ++/* #endif CESA_DEBUG */ ++ ++ cesaLastSid = sid; ++ ++#if (MV_CESA_VERSION >= 3) ++ /* Are we within chain bounderies and follows the first request ? */ ++ if((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { ++ if(chainIndex) { ++ pFromReq = MV_CESA_REQ_PREV_PTR(pReq); ++ pToReq = pReq; ++ pReq->state = MV_CESA_CHAIN; ++ /* assume concatenating is possible */ ++ pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); ++ mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast, sizeof(MV_DMA_DESC)); ++ ++ /* align active & next pointers */ ++ if(pNextActiveChain->state != MV_CESA_PENDING) ++ pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); ++ } ++ else { /* we have only one chain, start new one */ ++ chainReqNum = 0; ++ chainIndex++; ++ /* align active & next pointers */ ++ if(pNextActiveChain->state != MV_CESA_PENDING) ++ pEndCurrChain = pNextActiveChain = pReq; ++ } ++ } ++ else { ++ /* In case we concatenate full chain */ ++ if(chainReqNum == MAX_CESA_CHAIN_LENGTH) { ++ chainIndex++; ++ if(pNextActiveChain->state != MV_CESA_PENDING) ++ pEndCurrChain = pNextActiveChain = pReq; ++ chainReqNum = 0; ++ } ++ ++ pReq = pCesaReqProcess; ++ if(pReq->state == MV_CESA_PENDING) { ++ pNextActiveChain = pReq; ++ pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); ++ /* Start Process new request */ ++ mvCesaReqProcessStart(pReq); ++ } ++ } ++ ++ chainReqNum++; ++ ++ if((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) ++ cesaStats.maxChainUsage = chainReqNum; ++ ++#else ++ ++ /* Check status of CESA channels and process requests if possible */ ++ pReq = pCesaReqProcess; ++ if(pReq->state == MV_CESA_PENDING) ++ { ++ /* Start Process new request */ ++ mvCesaReqProcessStart(pReq); ++ } ++#endif ++ /* If request queue became FULL - return MV_NO_MORE */ ++ if(cesaReqResources == 0) ++ return MV_NO_MORE; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCesaReadyGet - Get crypto request that processing is finished ++* ++* DESCRIPTION: ++* This function complete request processing and return ready request to ++* caller. To don't miss interrupts the caller must call this function ++* while MV_OK or MV_TERMINATE values returned. ++* ++* INPUT: ++* MV_U32 chanMap - map of CESA channels finished thier job ++* accordingly with CESA Cause register. ++* MV_CESA_RESULT* pResult - pointer to structure contains information ++* about ready request. It includes pointer to ++* user private structure "pReqPrv", session identifier ++* for this request "sessionId" and return code. ++* Return code set to MV_FAIL if calculated digest value ++* on decode direction is different than digest value ++* in the packet. ++* ++* RETURN: ++* MV_OK - Success, ready request is returned. ++* MV_NOT_READY - Next request is not ready yet. New interrupt will ++* be generated for futher request processing. ++* MV_EMPTY - There is no more request for processing. ++* MV_BUSY - Fragmented request is not ready yet. ++* MV_TERMINATE - Call this function once more to complete processing ++* of fragmented request. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult) ++{ ++ MV_STATUS status, readyStatus = MV_NOT_READY; ++ MV_U32 statusReg; ++ MV_CESA_REQ* pReq; ++ MV_CESA_SA* pSA; ++ ++#if (MV_CESA_VERSION >= 3) ++ if(isFirstReq == MV_TRUE) { ++ if(chainIndex == 0) ++ chainReqNum = 0; ++ ++ isFirstReq = MV_FALSE; ++ ++ if(pNextActiveChain->state == MV_CESA_PENDING) { ++ /* Start request Process */ ++ mvCesaReqProcessStart(pNextActiveChain); ++ pEndCurrChain = pNextActiveChain; ++ if(chainIndex > 0) ++ chainIndex--; ++ /* Update pNextActiveChain to next chain head */ ++ while(pNextActiveChain->state == MV_CESA_CHAIN) ++ pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); ++ } ++ } ++ ++ /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ ++ if(pCesaReqProcess == pEndCurrChain) { ++ isFirstReq = MV_TRUE; ++ pEndCurrChain = pNextActiveChain; ++#else ++ if(pCesaReqProcess->state != MV_CESA_PROCESS) { ++#endif ++ return MV_EMPTY; ++ } ++ ++#ifdef CESA_DEBUG ++ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); ++ if( statusReg & MV_CESA_STATUS_ACTIVE_MASK ) ++ { ++ mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); ++ cesaStats.notReadyCount++; ++ return MV_NOT_READY; ++ } ++#endif /* CESA_DEBUG */ ++ ++ cesaStats.readyCount++; ++ ++ pReq = pCesaReqProcess; ++ pSA = &pCesaSAD[pReq->pCmd->sessionId]; ++ ++ pResult->retCode = MV_OK; ++ if(pReq->fragMode != MV_CESA_FRAG_NONE) ++ { ++ MV_U8* pNewDigest; ++ int frag; ++#if (MV_CESA_VERSION >= 3) ++ pReq->frags.nextFrag = 1; ++ while(pReq->frags.nextFrag <= pReq->frags.numFrag) { ++#endif ++ frag = (pReq->frags.nextFrag - 1); ++ ++ /* Restore DMA descriptor list */ ++ pReq->dma[frag].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); ++ pReq->dma[frag].pDmaLast = NULL; ++ ++ /* Special processing for finished fragmented request */ ++ if(pReq->frags.nextFrag >= pReq->frags.numFrag) ++ { ++ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); ++ ++ /* Fragmented packet is ready */ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; ++ ++ if(macDataSize != 0) ++ { ++ /* Calculate all other blocks by SW */ ++ mvCesaFragAuthComplete(pReq, pSA, macDataSize); ++ } ++ ++ /* Copy new digest from SRAM to the Destination buffer */ ++ pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; ++ status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, ++ pReq->pCmd->digestOffset, pSA->digestSize); ++ ++ /* For decryption: Compare new digest value with original one */ ++ if((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ++ { ++ if( memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) ++ { ++/* ++ mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", ++ chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); ++*/ ++ /* Signiture verification is failed */ ++ pResult->retCode = MV_FAIL; ++ } ++ } ++ } ++ readyStatus = MV_OK; ++ } ++#if (MV_CESA_VERSION >= 3) ++ pReq->frags.nextFrag++; ++ } ++#endif ++ } ++ else ++ { ++ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); ++ ++ /* Restore DMA descriptor list */ ++ pReq->dma[0].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); ++ pReq->dma[0].pDmaLast = NULL; ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) && ++ ((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ) ++ { ++ /* For AUTH on decode : Check Digest result in Status register */ ++ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); ++ if(statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) ++ { ++/* ++ mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", ++ chan, statusReg); ++*/ ++ /* Signiture verification is failed */ ++ pResult->retCode = MV_FAIL; ++ } ++ } ++ readyStatus = MV_OK; ++ } ++ ++ if(readyStatus == MV_OK) ++ { ++ /* If Request is ready - Prepare pResult structure */ ++ pResult->pReqPrv = pReq->pCmd->pReqPrv; ++ pResult->sessionId = pReq->pCmd->sessionId; ++ ++ pReq->state = MV_CESA_IDLE; ++ pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); ++ cesaReqResources++; ++ ++ if(pSA->ctrMode) ++ { ++ /* For AES CTR mode - complete processing and free allocated resources */ ++ mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); ++ mvCesaCtrModeFinish(pReq->pCmd); ++ pReq->pOrgCmd = NULL; ++ } ++ } ++ ++#if (MV_CESA_VERSION < 3) ++ if(pCesaReqProcess->state == MV_CESA_PROCESS) ++ { ++ /* Start request Process */ ++ mvCesaReqProcessStart(pCesaReqProcess); ++ if(readyStatus == MV_NOT_READY) ++ readyStatus = MV_BUSY; ++ } ++ else if(pCesaReqProcess != pCesaReqEmpty) ++ { ++ /* Start process new request from the queue */ ++ mvCesaReqProcessStart(pCesaReqProcess); ++ } ++#endif ++ return readyStatus; ++} ++ ++/***************** Functions to work with CESA_MBUF structure ******************/ ++ ++/******************************************************************************* ++* mvCesaMbufOffset - Locate offset in the Mbuf structure ++* ++* DESCRIPTION: ++* This function locates offset inside Multi-Bufeer structure. ++* It get fragment number and place in the fragment where the offset ++* is located. ++* ++* ++* INPUT: ++* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure ++* int offset - Offset from the beginning of the data presented by ++* the Mbuf structure. ++* ++* OUTPUT: ++* int* pBufOffset - Offset from the beginning of the fragment where ++* the offset is located. ++* ++* RETURN: ++* int - Number of fragment, where the offset is located\ ++* ++*******************************************************************************/ ++int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset) ++{ ++ int frag = 0; ++ ++ while(offset > 0) ++ { ++ if(frag >= pMbuf->numFrags) ++ { ++ mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", ++ frag, pMbuf->numFrags); ++ return MV_INVALID; ++ } ++ if(offset < pMbuf->pFrags[frag].bufSize) ++ { ++ break; ++ } ++ offset -= pMbuf->pFrags[frag].bufSize; ++ frag++; ++ } ++ if(pBufOffset != NULL) ++ *pBufOffset = offset; ++ ++ return frag; ++} ++ ++/******************************************************************************* ++* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_U8* pDstBuf - Pointer to continuous buffer, where data is ++* copied to. ++* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is ++* copied from. ++* int offset - Offset in the Mbuf structure where located first ++* byte of data should be copied. ++* int size - Size of data should be copied ++* ++* RETURN: ++* MV_OK - Success, all data is copied successfully. ++* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. ++* No data is copied. ++* MV_EMPTY - Multi-buffer structure has not enough data to copy ++* Data from the offset to end of Mbuf data is copied. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDstBuf, MV_CESA_MBUF* pSrcMbuf, ++ int offset, int size) ++{ ++ int frag, fragOffset, bufSize; ++ MV_U8* pBuf; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; ++ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; ++ while(MV_TRUE) ++ { ++ if(size <= bufSize) ++ { ++ memcpy(pDstBuf, pBuf, size); ++ return MV_OK; ++ } ++ memcpy(pDstBuf, pBuf, bufSize); ++ size -= bufSize; ++ frag++; ++ pDstBuf += bufSize; ++ if(frag >= pSrcMbuf->numFrags) ++ break; ++ ++ bufSize = pSrcMbuf->pFrags[frag].bufSize; ++ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; ++ } ++ mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", ++ size); ++ return MV_EMPTY; ++} ++ ++/******************************************************************************* ++* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is ++* copied from. ++* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is ++* copied to. ++* int offset - Offset in the Mbuf structure where located first ++* byte of data should be copied. ++* int size - Size of data should be copied ++* ++* RETURN: ++* MV_OK - Success, all data is copied successfully. ++* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. ++* No data is copied. ++* MV_FULL - Multi-buffer structure has not enough place to copy ++* all data. Data from the offset to end of Mbuf data ++* is copied. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrcBuf, MV_CESA_MBUF* pDstMbuf, ++ int offset, int size) ++{ ++ int frag, fragOffset, bufSize; ++ MV_U8* pBuf; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; ++ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; ++ while(MV_TRUE) ++ { ++ if(size <= bufSize) ++ { ++ memcpy(pBuf, pSrcBuf, size); ++ return MV_OK; ++ } ++ memcpy(pBuf, pSrcBuf, bufSize); ++ size -= bufSize; ++ frag++; ++ pSrcBuf += bufSize; ++ if(frag >= pDstMbuf->numFrags) ++ break; ++ ++ bufSize = pDstMbuf->pFrags[frag].bufSize; ++ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; ++ } ++ mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", ++ size); ++ return MV_FULL; ++} ++ ++/******************************************************************************* ++* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* ++* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is ++* copied to. ++* int dstMbufOffset - Offset in the dstMbuf structure where first byte ++* of data should be copied to. ++* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is ++* copied from. ++* int srcMbufOffset - Offset in the srcMbuf structure where first byte ++* of data should be copied from. ++* int size - Size of data should be copied ++* ++* RETURN: ++* MV_OK - Success, all data is copied successfully. ++* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of ++* srcMbuf or dstMbuf structure correspondently. ++* No data is copied. ++* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy ++* all data. Partial data is copied ++* ++*******************************************************************************/ ++MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, ++ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size) ++{ ++ int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; ++ int copySize; ++ MV_U8 *pSrc, *pDst; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); ++ if(srcFrag == MV_INVALID) ++ { ++ mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); ++ return MV_OUT_OF_RANGE; ++ } ++ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; ++ srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; ++ ++ dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); ++ if(dstFrag == MV_INVALID) ++ { ++ mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); ++ return MV_OUT_OF_RANGE; ++ } ++ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; ++ dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; ++ ++ while(size > 0) ++ { ++ copySize = MV_MIN(srcSize, dstSize); ++ if(size <= copySize) ++ { ++ memcpy(pDst, pSrc, size); ++ return MV_OK; ++ } ++ memcpy(pDst, pSrc, copySize); ++ size -= copySize; ++ srcSize -= copySize; ++ dstSize -= copySize; ++ ++ if(srcSize == 0) ++ { ++ srcFrag++; ++ if(srcFrag >= pMbufSrc->numFrags) ++ break; ++ ++ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; ++ srcSize = pMbufSrc->pFrags[srcFrag].bufSize; ++ } ++ ++ if(dstSize == 0) ++ { ++ dstFrag++; ++ if(dstFrag >= pMbufDst->numFrags) ++ break; ++ ++ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; ++ dstSize = pMbufDst->pFrags[dstFrag].bufSize; ++ } ++ } ++ mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", ++ size); ++ ++ return MV_BAD_SIZE; ++} ++ ++static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size) ++{ ++ int frag, fragOffset, bufSize; ++ MV_U8* pBuf; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; ++ while(MV_TRUE) ++ { ++ if(size <= bufSize) ++ { ++ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); ++ return MV_OK; ++ } ++ ++ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); ++ size -= bufSize; ++ frag++; ++ if(frag >= pMbuf->numFrags) ++ break; ++ ++ bufSize = pMbuf->pFrags[frag].bufSize; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr; ++ } ++ mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", ++ __FUNCTION__, size); ++ return MV_FULL; ++} ++ ++ ++/*************************************** Local Functions ******************************/ ++ ++/******************************************************************************* ++* mvCesaFragReqProcess - Process fragmented request ++* ++* DESCRIPTION: ++* This function processes a fragment of fragmented request (First, Middle or Last) ++* ++* ++* INPUT: ++* MV_CESA_REQ* pReq - Pointer to the request in the request queue. ++* ++* RETURN: ++* MV_OK - The fragment is successfully passed to HW for processing. ++* MV_TERMINATE - Means, that HW finished its work on this packet and no more ++* interrupts will be generated for this request. ++* Function mvCesaReadyGet() must be called to complete request ++* processing and get request result. ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag) ++{ ++ int i, copySize, cryptoDataSize, macDataSize, sid; ++ int cryptoIvOffset, digestOffset; ++ MV_U32 config; ++ MV_CESA_COMMAND* pCmd = pReq->pCmd; ++ MV_CESA_SA* pSA; ++ MV_CESA_MBUF* pMbuf; ++ MV_DMA_DESC* pDmaDesc = pReq->dma[frag].pDmaFirst; ++ MV_U8* pSramBuf = cesaSramVirtPtr->buf; ++ int macTotalLen = 0; ++ int fixOffset, cryptoOffset, macOffset; ++ ++ cesaStats.fragCount++; ++ ++ sid = pReq->pCmd->sessionId; ++ ++ pSA = &pCesaSAD[sid]; ++ ++ cryptoIvOffset = digestOffset = 0; ++ i = macDataSize = 0; ++ cryptoDataSize = 0; ++ ++ /* First fragment processing */ ++ if(pReq->fragMode == MV_CESA_FRAG_FIRST) ++ { ++ /* pReq->frags monitors processing of fragmented request between fragments */ ++ pReq->frags.bufOffset = 0; ++ pReq->frags.cryptoSize = 0; ++ pReq->frags.macSize = 0; ++ ++ config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); ++ ++ /* fixOffset can be not equal to zero only for FIRST fragment */ ++ fixOffset = pReq->fixOffset; ++ /* For FIRST fragment crypto and mac offsets are taken from pCmd */ ++ cryptoOffset = pCmd->cryptoOffset; ++ macOffset = pCmd->macOffset; ++ ++ copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; ++ ++ /* Find fragment size: Must meet all requirements for CRYPTO and MAC ++ * cryptoDataSize - size of data will be encrypted/decrypted in this fragment ++ * macDataSize - size of data will be signed/verified in this fragment ++ * copySize - size of data will be copied from srcMbuf to SRAM and ++ * back to dstMbuf for this fragment ++ */ ++ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, ++ ©Size, &cryptoDataSize, &macDataSize); ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ++ { ++ /* CryptoIV special processing */ ++ if( (pSA->config & MV_CESA_CRYPTO_MODE_MASK) == ++ (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT) ) ++ { ++ /* In CBC mode for encode direction when IV from user */ ++ if( (pCmd->ivFromUser) && ++ ((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) ) ++ { ++ ++ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, ++ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place ++ * in the buffer to SRAM IVPointer ++ */ ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], ++ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ ++ /* Special processing when IV is not located in the first fragment */ ++ if(pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) ++ { ++ /* Prepare dummy place for cryptoIV in SRAM */ ++ cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); ++ ++ /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ ++ if((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ++ { ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, &pDmaDesc[i], ++ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ else ++ { ++ /* For Encryption when IV is NOT from User: */ ++ /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ ++ if(pCmd->ivFromUser == 0) ++ { ++ /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], ++ MV_TRUE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ } ++ } ++ else ++ { ++ cryptoIvOffset = pCmd->ivOffset; ++ } ++ } ++ } ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ /* MAC digest special processing on Decode direction */ ++ if((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ++ { ++ /* Save digest from pCmd->digestOffset */ ++ mvCesaCopyFromMbuf(pReq->frags.orgDigest, ++ pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); ++ ++ /* If pCmd->digestOffset is not located on the first */ ++ if(pCmd->digestOffset > (copySize - pSA->digestSize)) ++ { ++ MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; ++ ++ /* Set zeros to pCmd->digestOffset (DRAM) */ ++ memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); ++ mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); ++ ++ /* Prepare dummy place for digest in SRAM */ ++ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); ++ } ++ else ++ { ++ digestOffset = pCmd->digestOffset; ++ } ++ } ++ } ++ /* Update SA in SRAM */ ++ if(cesaLastSid != sid) ++ { ++ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); ++ i++; ++ } ++ ++ pReq->fragMode = MV_CESA_FRAG_MIDDLE; ++ } ++ else ++ { ++ /* Continue fragment */ ++ fixOffset = 0; ++ cryptoOffset = 0; ++ macOffset = 0; ++ if( (pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) ++ { ++ /* Last fragment */ ++ config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); ++ pReq->fragMode = MV_CESA_FRAG_LAST; ++ copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ macDataSize = pCmd->macLength - pReq->frags.macSize; ++ ++ /* If pCmd->digestOffset is not located on last fragment */ ++ if(pCmd->digestOffset < pReq->frags.bufOffset) ++ { ++ /* Prepare dummy place for digest in SRAM */ ++ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); ++ } ++ else ++ { ++ digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; ++ } ++ pReq->frags.newDigestOffset = digestOffset; ++ macTotalLen = pCmd->macLength; ++ ++ /* HW can't calculate the Digest correctly for fragmented packets ++ * in the following cases: ++ * - MV88F5182 || ++ * - MV88F5181L when total macLength more that 16 Kbytes || ++ * - total macLength more that 64 Kbytes ++ */ ++ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || ++ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && ++ (mvCtrlRevGet() >= MV_5181L_A0_REV) && ++ (pCmd->macLength >= (1 << 14)) ) ) ++ { ++ return MV_TERMINATE; ++ } ++ } ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; ++ } ++ ++ /* cryptoIvOffset - don't care */ ++ } ++ else ++ { ++ /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ ++ if( (mvCtrlModelGet() == MV_5182_DEV_ID) && ++ (((pSA->config & MV_CESA_MAC_MODE_MASK) == ++ (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || ++ ((pSA->config & MV_CESA_MAC_MODE_MASK) == ++ (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET))) ) ++ { ++ pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); ++ pReq->fragMode = MV_CESA_FRAG_LAST; ++ ++ return MV_TERMINATE; ++ } ++ /* Middle fragment */ ++ config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); ++ copySize = sizeof(cesaSramVirtPtr->buf); ++ /* digestOffset and cryptoIvOffset - don't care */ ++ ++ /* Find fragment size */ ++ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, ++ ©Size, &cryptoDataSize, &macDataSize); ++ } ++ } ++ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ ++ pMbuf = pCmd->pSrc; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); ++ ++ /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ ++ mvCesaSramDescrBuild(config, frag, ++ cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, ++ cryptoDataSize, macOffset + fixOffset, ++ digestOffset + fixOffset, macDataSize, macTotalLen, ++ pReq, &pDmaDesc[i]); ++ i++; ++ ++ /* Add special descriptor Ownership for CPU */ ++ pDmaDesc[i].byteCnt = 0; ++ pDmaDesc[i].phySrcAdd = 0; ++ pDmaDesc[i].phyDestAdd = 0; ++ i++; ++ ++ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ ++ pMbuf = pCmd->pDst; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); ++ ++ /* Next field of Last DMA descriptor must be NULL */ ++ pDmaDesc[i-1].phyNextDescPtr = 0; ++ pReq->dma[frag].pDmaLast = &pDmaDesc[i-1]; ++ mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, ++ i*sizeof(MV_DMA_DESC)); ++ ++ /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]);*/ ++ ++ pReq->frags.bufOffset += copySize; ++ pReq->frags.cryptoSize += cryptoDataSize; ++ pReq->frags.macSize += macDataSize; ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCesaReqProcess - Process regular (Non-fragmented) request ++* ++* DESCRIPTION: ++* This function processes the whole (not fragmented) request ++* ++* INPUT: ++* MV_CESA_REQ* pReq - Pointer to the request in the request queue. ++* ++* RETURN: ++* MV_OK - The request is successfully passed to HW for processing. ++* Other - Failure. The request will not be processed ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq) ++{ ++ MV_CESA_MBUF *pMbuf; ++ MV_DMA_DESC *pDmaDesc; ++ MV_U8 *pSramBuf; ++ int sid, i, fixOffset; ++ MV_CESA_SA *pSA; ++ MV_CESA_COMMAND *pCmd = pReq->pCmd; ++ ++ cesaStats.procCount++; ++ ++ sid = pCmd->sessionId; ++ pSA = &pCesaSAD[sid]; ++ pDmaDesc = pReq->dma[0].pDmaFirst; ++ pSramBuf = cesaSramVirtPtr->buf; ++ fixOffset = pReq->fixOffset; ++ ++/* ++ mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", ++ sid, pSA, pDmaDesc, pSramBuf); ++*/ ++ i = 0; ++ ++ /* Crypto IV Special processing in CBC mode for Encryption direction */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && ++ ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && ++ ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && ++ (pCmd->ivFromUser) ) ++ { ++ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, ++ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place ++ * in the buffer to SRAM IVPointer ++ */ ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], ++ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ ++ /* Update SA in SRAM */ ++ if(cesaLastSid != sid) ++ { ++ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); ++ i++; ++ } ++ ++ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ ++ pMbuf = pCmd->pSrc; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); ++ ++ /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ ++ mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, ++ pCmd->ivOffset + fixOffset, pCmd->cryptoLength, ++ pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, ++ pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); ++ i++; ++ ++ /* Add special descriptor Ownership for CPU */ ++ pDmaDesc[i].byteCnt = 0; ++ pDmaDesc[i].phySrcAdd = 0; ++ pDmaDesc[i].phyDestAdd = 0; ++ i++; ++ ++ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ ++ pMbuf = pCmd->pDst; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); ++ ++ /* Next field of Last DMA descriptor must be NULL */ ++ pDmaDesc[i-1].phyNextDescPtr = 0; ++ pReq->dma[0].pDmaLast = &pDmaDesc[i-1]; ++ mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i*sizeof(MV_DMA_DESC)); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCesaSramDescrBuild - Set CESA descriptor in SRAM ++* ++* DESCRIPTION: ++* This function builds CESA descriptor in SRAM from all Command parameters ++* ++* ++* INPUT: ++* int chan - CESA channel uses the descriptor ++* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure ++* int cryptoOffset - Offset from the beginning of SRAM buffer where ++* data for encryption/decription is started. ++* int ivOffset - Offset of crypto IV from the SRAM base. Valid only ++* for first fragment. ++* int cryptoLength - Size (in bytes) of data for encryption/descryption ++* operation on this fragment. ++* int macOffset - Offset from the beginning of SRAM buffer where ++* data for Authentication is started ++* int digestOffset - Offset from the beginning of SRAM buffer where ++* digest is located. Valid for first and last fragments. ++* int macLength - Size (in bytes) of data for Authentication ++* operation on this fragment. ++* int macTotalLen - Toatl size (in bytes) of data for Authentication ++* operation on the whole request (packet). Valid for ++* last fragment only. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static void mvCesaSramDescrBuild(MV_U32 config, int frag, ++ int cryptoOffset, int ivOffset, int cryptoLength, ++ int macOffset, int digestOffset, int macLength, ++ int macTotalLen, MV_CESA_REQ* pReq, MV_DMA_DESC* pDmaDesc) ++{ ++ MV_CESA_DESC* pCesaDesc = &pReq->pCesaDesc[frag]; ++ MV_CESA_DESC* pSramDesc = pSramDesc = &cesaSramVirtPtr->desc; ++ MV_U16 sramBufOffset = (MV_U16)((MV_U8*)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); ++ ++ pCesaDesc->config = MV_32BIT_LE(config); ++ ++ if( (config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ /* word 1 */ ++ pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); ++ pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); ++ /* word 2 */ ++ pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); ++ /* word 3 */ ++ pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.cryptoKey - ++ mvCesaSramAddrGet())); ++ /* word 4 */ ++ pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->cryptoIV - ++ mvCesaSramAddrGet())); ++ pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); ++ } ++ ++ if( (config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ /* word 5 */ ++ pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); ++ pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); ++ ++ /* word 6 */ ++ pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); ++ pCesaDesc->macDataLen = MV_16BIT_LE(macLength); ++ ++ /* word 7 */ ++ pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macInnerIV - ++ mvCesaSramAddrGet())); ++ pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macOuterIV - ++ mvCesaSramAddrGet())); ++ } ++ /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ ++ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); ++ pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)pSramDesc)); ++ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); ++ ++ /* flush Source buffer */ ++ mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); ++} ++ ++/******************************************************************************* ++* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. ++* ++* DESCRIPTION: ++* Copy to SRAM values of the required SA. ++* ++* ++* INPUT: ++* short sid - Session ID needs SRAM Cache update ++* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to ++* copy SA values from DRAM to SRAM. ++* ++* RETURN: ++* MV_OK - Cache entry for this SA copied to SRAM. ++* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM ++* ++*******************************************************************************/ ++static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) ++{ ++ MV_CESA_SA *pSA = &pCesaSAD[sid]; ++ ++ /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ ++ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); ++ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pSA->pSramSA)); ++ pDmaDesc->phyDestAdd = ++ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)&cesaSramVirtPtr->sramSA)); ++ ++ /* Source buffer is already flushed during OpenSession*/ ++ /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA));*/ ++} ++ ++/******************************************************************************* ++* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by ++* Mbuf structure from DRAM to SRAM ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request ++* data in DRAM ++* MV_U8* pSramBuf - pointer to buffer in SRAM where data should ++* be copied to. ++* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. ++* The function set number of DMA descriptors needed ++* to copy the copySize bytes from Mbuf. ++* MV_BOOL isToMbuf - Copy direction. ++* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. ++* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. ++* int offset - Offset in the Mbuf structure that copy should be ++* started from. ++* int copySize - Size of data should be copied. ++* ++* RETURN: ++* int - number of DMA descriptors used for the copy. ++* ++*******************************************************************************/ ++#ifndef MV_NETBSD ++static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, ++ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, ++ int offset, int copySize, MV_BOOL skipFlush) ++{ ++ int bufOffset, bufSize, size, frag, i; ++ MV_U8* pBuf; ++ ++ i = 0; ++ ++ /* Calculate start place for copy: fragment number and offset in the fragment */ ++ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); ++ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; ++ ++ /* Size accumulate total copy size */ ++ size = 0; ++ ++ /* Create DMA lists to copy mBuf from pSrc to SRAM */ ++ while(size < copySize) ++ { ++ /* Find copy size for each DMA descriptor */ ++ bufSize = MV_MIN(bufSize, (copySize - size)); ++ pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); ++ if(isToMbuf) ++ { ++ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); ++ pDmaDesc[i].phySrcAdd = ++ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); ++ /* invalidate the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheInvalidate(NULL, pBuf, bufSize); ++ } ++ else ++ { ++ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); ++ pDmaDesc[i].phyDestAdd = ++ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); ++ /* flush the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheFlush(NULL, pBuf, bufSize); ++ } ++ ++ /* Count number of used DMA descriptors */ ++ i++; ++ size += bufSize; ++ ++ /* go to next fragment in the Mbuf */ ++ frag++; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr; ++ bufSize = pMbuf->pFrags[frag].bufSize; ++ } ++ return i; ++} ++#else /* MV_NETBSD */ ++static int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, ++ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, ++ int offset, int copySize, MV_BOOL skipFlush) ++{ ++ int bufOffset, bufSize, thisSize, size, frag, i; ++ MV_ULONG bufPhys, sramPhys; ++ MV_U8* pBuf; ++ ++ /* ++ * Calculate start place for copy: fragment number and offset in ++ * the fragment ++ */ ++ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); ++ ++ /* ++ * Get SRAM physical address only once. We can update it in-place ++ * as we build the descriptor chain. ++ */ ++ sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); ++ ++ /* ++ * 'size' accumulates total copy size, 'i' counts desccriptors. ++ */ ++ size = i = 0; ++ ++ /* Create DMA lists to copy mBuf from pSrc to SRAM */ ++ while (size < copySize) { ++ /* ++ * Calculate # of bytes to copy from the current fragment, ++ * and the pointer to the start of data ++ */ ++ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; ++ bufOffset = 0; /* First frag may be non-zero */ ++ frag++; ++ ++ /* ++ * As long as there is data in the current fragment... ++ */ ++ while (bufSize > 0) { ++ /* ++ * Ensure we don't cross an MMU page boundary. ++ * XXX: This is NetBSD-specific, but it is a ++ * quick and dirty way to fix the problem. ++ * A true HAL would rely on the OS-specific ++ * driver to do this... ++ */ ++ thisSize = PAGE_SIZE - ++ (((MV_ULONG)pBuf) & (PAGE_SIZE - 1)); ++ thisSize = MV_MIN(bufSize, thisSize); ++ /* ++ * Make sure we don't copy more than requested ++ */ ++ if (thisSize > (copySize - size)) { ++ thisSize = copySize - size; ++ bufSize = 0; ++ } ++ ++ /* ++ * Physicall address of this fragment ++ */ ++ bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); ++ ++ /* ++ * Set up the descriptor ++ */ ++ pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); ++ if(isToMbuf) { ++ pDmaDesc[i].phyDestAdd = bufPhys; ++ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); ++ /* invalidate the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheInvalidate(NULL, pBuf, thisSize); ++ } else { ++ pDmaDesc[i].phySrcAdd = bufPhys; ++ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); ++ /* flush the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheFlush(NULL, pBuf, thisSize); ++ } ++ ++ pDmaDesc[i].phyNextDescPtr = ++ MV_32BIT_LE(mvOsIoVirtToPhy(NULL,(&pDmaDesc[i+1]))); ++ ++ /* flush the DMA desc */ ++ mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); ++ ++ /* Update state */ ++ bufSize -= thisSize; ++ sramPhys += thisSize; ++ pBuf += thisSize; ++ size += thisSize; ++ i++; ++ } ++ } ++ ++ return i; ++} ++#endif /* MV_NETBSD */ ++/******************************************************************************* ++* mvCesaHmacIvGet - Calculate Inner and Outter values from HMAC key ++* ++* DESCRIPTION: ++* This function calculate Inner and Outer values used for HMAC algorithm. ++* This operation allows improve performance fro the whole HMAC processing. ++* ++* INPUT: ++* MV_CESA_MAC_MODE macMode - Authentication mode: HMAC_MD5 or HMAC_SHA1. ++* unsigned char key[] - Pointer to HMAC key. ++* int keyLength - Size of HMAC key (maximum 64 bytes) ++* ++* OUTPUT: ++* unsigned char innerIV[] - HASH(key^inner) ++* unsigned char outerIV[] - HASH(key^outter) ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, ++ unsigned char innerIV[], unsigned char outerIV[]) ++{ ++ unsigned char inner[MV_CESA_MAX_MAC_KEY_LENGTH]; ++ unsigned char outer[MV_CESA_MAX_MAC_KEY_LENGTH]; ++ int i, digestSize = 0; ++#if defined(MV_CPU_LE) || defined(MV_PPC) ++ MV_U32 swapped32, val32, *pVal32; ++#endif ++ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; ++ size = pMbuf->pFrags[frag].bufSize - fragOffset; ++ ++ /* Complete Inner part */ ++ while(macLeftSize > 0) ++ { ++ if(macLeftSize <= size) ++ { ++ mvSHA1Update(&ctx, pData, macLeftSize); ++ break; ++ } ++ mvSHA1Update(&ctx, pData, size); ++ macLeftSize -= size; ++ frag++; ++ pData = pMbuf->pFrags[frag].bufVirtPtr; ++ size = pMbuf->pFrags[frag].bufSize; ++ } ++ mvSHA1Final(pDigest, &ctx); ++/* ++ mvOsPrintf("mvCesaFragSha1Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", ++ pOuterIV, macLeftSize, macTotalSize); ++ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); ++*/ ++ ++ if(pOuterIV != NULL) ++ { ++ /* If HMAC - Complete Outer part */ ++ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; ++ size = pMbuf->pFrags[frag].bufSize - fragOffset; ++ ++ /* Complete Inner part */ ++ while(macLeftSize > 0) ++ { ++ if(macLeftSize <= size) ++ { ++ mvMD5Update(&ctx, pData, macLeftSize); ++ break; ++ } ++ mvMD5Update(&ctx, pData, size); ++ macLeftSize -= size; ++ frag++; ++ pData = pMbuf->pFrags[frag].bufVirtPtr; ++ size = pMbuf->pFrags[frag].bufSize; ++ } ++ mvMD5Final(pDigest, &ctx); ++ ++/* ++ mvOsPrintf("mvCesaFragMd5Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", ++ pOuterIV, macLeftSize, macTotalSize); ++ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); ++*/ ++ if(pOuterIV != NULL) ++ { ++ /* Complete Outer part */ ++ for(i=0; ipCmd; ++ MV_U8* pDigest; ++ MV_CESA_MAC_MODE macMode; ++ MV_U8* pOuterIV = NULL; ++ ++ /* Copy data from Source fragment to Destination */ ++ if(pCmd->pSrc != pCmd->pDst) ++ { ++ mvCesaMbufCopy(pCmd->pDst, pReq->frags.bufOffset, ++ pCmd->pSrc, pReq->frags.bufOffset, macDataSize); ++ } ++ ++/* ++ mvCesaCopyFromMbuf(cesaSramVirtPtr->buf[0], pCmd->pSrc, pReq->frags.bufOffset, macDataSize); ++ mvCesaCopyToMbuf(cesaSramVirtPtr->buf[0], pCmd->pDst, pReq->frags.bufOffset, macDataSize); ++*/ ++ pDigest = (mvCesaSramAddrGet() + pReq->frags.newDigestOffset); ++ ++ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; ++/* ++ mvOsPrintf("macDataSize=%d, macLength=%d, digestOffset=%d, macMode=%d\n", ++ macDataSize, pCmd->macLength, pCmd->digestOffset, macMode); ++*/ ++ switch(macMode) ++ { ++ case MV_CESA_MAC_HMAC_MD5: ++ pOuterIV = pSA->pSramSA->macOuterIV; ++ ++ case MV_CESA_MAC_MD5: ++ mvCesaFragMd5Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, ++ macDataSize, pCmd->macLength, pDigest); ++ break; ++ ++ case MV_CESA_MAC_HMAC_SHA1: ++ pOuterIV = pSA->pSramSA->macOuterIV; ++ ++ case MV_CESA_MAC_SHA1: ++ mvCesaFragSha1Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, ++ macDataSize, pCmd->macLength, pDigest); ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaFragAuthComplete: Unexpected macMode %d\n", macMode); ++ return MV_BAD_PARAM; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModeInit - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: NONE ++* ++* ++* RETURN: ++* MV_CESA_COMMAND* ++* ++*******************************************************************************/ ++static MV_CESA_COMMAND* mvCesaCtrModeInit(void) ++{ ++ MV_CESA_MBUF *pMbuf; ++ MV_U8 *pBuf; ++ MV_CESA_COMMAND *pCmd; ++ ++ pBuf = mvOsMalloc(sizeof(MV_CESA_COMMAND) + ++ sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) + 100); ++ if(pBuf == NULL) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Can't allocate %u bytes for CTR Mode\n", ++ sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) ); ++ return NULL; ++ } ++ pCmd = (MV_CESA_COMMAND*)pBuf; ++ pBuf += sizeof(MV_CESA_COMMAND); ++ ++ pMbuf = (MV_CESA_MBUF*)pBuf; ++ pBuf += sizeof(MV_CESA_MBUF); ++ ++ pMbuf->pFrags = (MV_BUF_INFO*)pBuf; ++ ++ pMbuf->numFrags = 1; ++ pCmd->pSrc = pMbuf; ++ pCmd->pDst = pMbuf; ++/* ++ mvOsPrintf("CtrModeInit: pCmd=%p, pSrc=%p, pDst=%p, pFrags=%p\n", ++ pCmd, pCmd->pSrc, pCmd->pDst, ++ pMbuf->pFrags); ++*/ ++ return pCmd; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModePrepare - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd) ++{ ++ MV_CESA_MBUF *pMbuf; ++ MV_U8 *pBuf, *pIV; ++ MV_U32 counter, *pCounter; ++ int cryptoSize = MV_ALIGN_UP(pCmd->cryptoLength, MV_CESA_AES_BLOCK_SIZE); ++/* ++ mvOsPrintf("CtrModePrepare: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", ++ pCmd, pCmd->pSrc, pCmd->pDst, ++ pCtrModeCmd, pCtrModeCmd->pSrc, pCtrModeCmd->pDst); ++*/ ++ pMbuf = pCtrModeCmd->pSrc; ++ ++ /* Allocate buffer for Key stream */ ++ pBuf = mvOsIoCachedMalloc(cesaOsHandle,cryptoSize, ++ &pMbuf->pFrags[0].bufPhysAddr, ++ &pMbuf->pFrags[0].memHandle); ++ if(pBuf == NULL) ++ { ++ mvOsPrintf("mvCesaCtrModePrepare: Can't allocate %d bytes\n", cryptoSize); ++ return MV_OUT_OF_CPU_MEM; ++ } ++ memset(pBuf, 0, cryptoSize); ++ mvOsCacheFlush(NULL, pBuf, cryptoSize); ++ ++ pMbuf->pFrags[0].bufVirtPtr = pBuf; ++ pMbuf->mbufSize = cryptoSize; ++ pMbuf->pFrags[0].bufSize = cryptoSize; ++ ++ pCtrModeCmd->pReqPrv = pCmd->pReqPrv; ++ pCtrModeCmd->sessionId = pCmd->sessionId; ++ ++ /* ivFromUser and ivOffset are don't care */ ++ pCtrModeCmd->cryptoOffset = 0; ++ pCtrModeCmd->cryptoLength = cryptoSize; ++ ++ /* digestOffset, macOffset and macLength are don't care */ ++ ++ mvCesaCopyFromMbuf(pBuf, pCmd->pSrc, pCmd->ivOffset, MV_CESA_AES_BLOCK_SIZE); ++ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); ++ counter = *pCounter; ++ counter = MV_32BIT_BE(counter); ++ pIV = pBuf; ++ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; ++ ++ /* fill key stream */ ++ while(cryptoSize > 0) ++ { ++ pBuf += MV_CESA_AES_BLOCK_SIZE; ++ memcpy(pBuf, pIV, MV_CESA_AES_BLOCK_SIZE - sizeof(counter)); ++ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); ++ counter++; ++ *pCounter = MV_32BIT_BE(counter); ++ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModeComplete - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd) ++{ ++ int srcFrag, dstFrag, srcOffset, dstOffset, keyOffset, srcSize, dstSize; ++ int cryptoSize = pCmd->cryptoLength; ++ MV_U8 *pSrc, *pDst, *pKey; ++ MV_STATUS status = MV_OK; ++/* ++ mvOsPrintf("CtrModeComplete: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", ++ pCmd, pCmd->pSrc, pCmd->pDst, ++ pOrgCmd, pOrgCmd->pSrc, pOrgCmd->pDst); ++*/ ++ /* XOR source data with key stream to destination data */ ++ pKey = pCmd->pDst->pFrags[0].bufVirtPtr; ++ keyOffset = 0; ++ ++ if( (pOrgCmd->pSrc != pOrgCmd->pDst) && ++ (pOrgCmd->cryptoOffset > 0) ) ++ { ++ /* Copy Prefix from source buffer to destination buffer */ ++ ++ status = mvCesaMbufCopy(pOrgCmd->pDst, 0, ++ pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); ++/* ++ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, ++ 0, pOrgCmd->cryptoOffset); ++ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, ++ 0, pOrgCmd->cryptoOffset); ++*/ ++ } ++ ++ srcFrag = mvCesaMbufOffset(pOrgCmd->pSrc, pOrgCmd->cryptoOffset, &srcOffset); ++ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; ++ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; ++ ++ dstFrag = mvCesaMbufOffset(pOrgCmd->pDst, pOrgCmd->cryptoOffset, &dstOffset); ++ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; ++ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; ++ ++ while(cryptoSize > 0) ++ { ++ pDst[dstOffset] = (pSrc[srcOffset] ^ pKey[keyOffset]); ++ ++ cryptoSize--; ++ dstOffset++; ++ srcOffset++; ++ keyOffset++; ++ ++ if(srcOffset >= srcSize) ++ { ++ srcFrag++; ++ srcOffset = 0; ++ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; ++ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; ++ } ++ ++ if(dstOffset >= dstSize) ++ { ++ dstFrag++; ++ dstOffset = 0; ++ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; ++ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; ++ } ++ } ++ ++ if(pOrgCmd->pSrc != pOrgCmd->pDst) ++ { ++ /* Copy Suffix from source buffer to destination buffer */ ++ srcOffset = pOrgCmd->cryptoOffset + pOrgCmd->cryptoLength; ++ ++ if( (pOrgCmd->pDst->mbufSize - srcOffset) > 0) ++ { ++ status = mvCesaMbufCopy(pOrgCmd->pDst, srcOffset, ++ pOrgCmd->pSrc, srcOffset, ++ pOrgCmd->pDst->mbufSize - srcOffset); ++ } ++ ++/* ++ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, ++ srcOffset, pOrgCmd->pSrc->mbufSize - srcOffset); ++ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, ++ srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); ++*/ ++ } ++ ++ /* Free buffer used for Key stream */ ++ mvOsIoCachedFree(cesaOsHandle,pCmd->pDst->pFrags[0].bufSize, ++ pCmd->pDst->pFrags[0].bufPhysAddr, ++ pCmd->pDst->pFrags[0].bufVirtPtr, ++ pCmd->pDst->pFrags[0].memHandle); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModeFinish - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_COMMAND* pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static void mvCesaCtrModeFinish(MV_CESA_COMMAND* pCmd) ++{ ++ mvOsFree(pCmd); ++} ++ ++/******************************************************************************* ++* mvCesaParamCheck - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, ++ MV_U8* pFixOffset) ++{ ++ MV_U8 fixOffset = 0xFF; ++ ++ /* Check AUTH operation parameters */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* MAC offset should be at least 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->macOffset, 4) ) ++ { ++ mvOsPrintf("mvCesaAction: macOffset %d must be 4 byte aligned\n", ++ pCmd->macOffset); ++ return MV_BAD_PARAM; ++ } ++ /* Digest offset must be 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->digestOffset, 4) ) ++ { ++ mvOsPrintf("mvCesaAction: digestOffset %d must be 4 byte aligned\n", ++ pCmd->digestOffset); ++ return MV_BAD_PARAM; ++ } ++ /* In addition all offsets should be the same alignment: 8 or 4 */ ++ if(fixOffset == 0xFF) ++ { ++ fixOffset = (pCmd->macOffset % 8); ++ } ++ else ++ { ++ if( (pCmd->macOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: macOffset %d mod 8 must be equal %d\n", ++ pCmd->macOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ if( (pCmd->digestOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: digestOffset %d mod 8 must be equal %d\n", ++ pCmd->digestOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ /* Check CRYPTO operation parameters */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* CryptoOffset should be at least 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->cryptoOffset, 4) ) ++ { ++ mvOsPrintf("CesaAction: cryptoOffset=%d must be 4 byte aligned\n", ++ pCmd->cryptoOffset); ++ return MV_BAD_PARAM; ++ } ++ /* cryptoLength should be the whole number of blocks */ ++ if( MV_IS_NOT_ALIGN(pCmd->cryptoLength, pSA->cryptoBlockSize) ) ++ { ++ mvOsPrintf("mvCesaAction: cryptoLength=%d must be %d byte aligned\n", ++ pCmd->cryptoLength, pSA->cryptoBlockSize); ++ return MV_BAD_PARAM; ++ } ++ if(fixOffset == 0xFF) ++ { ++ fixOffset = (pCmd->cryptoOffset % 8); ++ } ++ else ++ { ++ /* In addition all offsets should be the same alignment: 8 or 4 */ ++ if( (pCmd->cryptoOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: cryptoOffset %d mod 8 must be equal %d \n", ++ pCmd->cryptoOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ ++ /* check for CBC mode */ ++ if(pSA->cryptoIvSize > 0) ++ { ++ /* cryptoIV must not be part of CryptoLength */ ++ if( ((pCmd->ivOffset + pSA->cryptoIvSize) > pCmd->cryptoOffset) && ++ (pCmd->ivOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: cryptoIvOffset (%d) is part of cryptoLength (%d+%d)\n", ++ pCmd->ivOffset, pCmd->macOffset, pCmd->macLength); ++ return MV_BAD_PARAM; ++ } ++ ++ /* ivOffset must be 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->ivOffset, 4) ) ++ { ++ mvOsPrintf("CesaAction: ivOffset=%d must be 4 byte aligned\n", ++ pCmd->ivOffset); ++ return MV_BAD_PARAM; ++ } ++ /* In addition all offsets should be the same alignment: 8 or 4 */ ++ if( (pCmd->ivOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: ivOffset %d mod 8 must be %d\n", ++ pCmd->ivOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaFragParamCheck - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd) ++{ ++ int offset; ++ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* macOffset must be less that SRAM buffer size */ ++ if(pCmd->macOffset > (sizeof(cesaSramVirtPtr->buf) - MV_CESA_AUTH_BLOCK_SIZE)) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: macOffset is too large (%d)\n", ++ pCmd->macOffset); ++ return MV_BAD_PARAM; ++ } ++ /* macOffset+macSize must be more than mbufSize - SRAM buffer size */ ++ if( ((pCmd->macOffset + pCmd->macLength) > pCmd->pSrc->mbufSize) || ++ ((pCmd->pSrc->mbufSize - (pCmd->macOffset + pCmd->macLength)) >= ++ sizeof(cesaSramVirtPtr->buf)) ) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: macLength is too large (%d), mbufSize=%d\n", ++ pCmd->macLength, pCmd->pSrc->mbufSize); ++ return MV_BAD_PARAM; ++ } ++ } ++ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* cryptoOffset must be less that SRAM buffer size */ ++ /* 4 for possible fixOffset */ ++ if( (pCmd->cryptoOffset + 4) > (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: cryptoOffset is too large (%d)\n", ++ pCmd->cryptoOffset); ++ return MV_BAD_PARAM; ++ } ++ ++ /* cryptoOffset+cryptoSize must be more than mbufSize - SRAM buffer size */ ++ if( ((pCmd->cryptoOffset + pCmd->cryptoLength) > pCmd->pSrc->mbufSize) || ++ ((pCmd->pSrc->mbufSize - (pCmd->cryptoOffset + pCmd->cryptoLength)) >= ++ (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: cryptoLength is too large (%d), mbufSize=%d\n", ++ pCmd->cryptoLength, pCmd->pSrc->mbufSize); ++ return MV_BAD_PARAM; ++ } ++ } ++ ++ /* When MAC_THEN_CRYPTO or CRYPTO_THEN_MAC */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) == ++ (MV_CESA_MAC_THEN_CRYPTO << MV_CESA_OPERATION_OFFSET)) || ++ ((pSA->config & MV_CESA_OPERATION_MASK) == ++ (MV_CESA_CRYPTO_THEN_MAC << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || ++ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && ++ (mvCtrlRevGet() >= MV_5181L_A0_REV) && ++ (pCmd->macLength >= (1 << 14)) ) ) ++ { ++ return MV_NOT_ALLOWED; ++ } ++ ++ /* abs(cryptoOffset-macOffset) must be aligned cryptoBlockSize */ ++ if(pCmd->cryptoOffset > pCmd->macOffset) ++ { ++ offset = pCmd->cryptoOffset - pCmd->macOffset; ++ } ++ else ++ { ++ offset = pCmd->macOffset - pCmd->cryptoOffset; ++ } ++ ++ if( MV_IS_NOT_ALIGN(offset, pSA->cryptoBlockSize) ) ++ { ++/* ++ mvOsPrintf("mvCesaFragParamCheck: (cryptoOffset - macOffset) must be %d byte aligned\n", ++ pSA->cryptoBlockSize); ++*/ ++ return MV_NOT_ALLOWED; ++ } ++ /* Digest must not be part of CryptoLength */ ++ if( ((pCmd->digestOffset + pSA->digestSize) > pCmd->cryptoOffset) && ++ (pCmd->digestOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) ++ { ++/* ++ mvOsPrintf("mvCesaFragParamCheck: digestOffset (%d) is part of cryptoLength (%d+%d)\n", ++ pCmd->digestOffset, pCmd->cryptoOffset, pCmd->cryptoLength); ++*/ ++ return MV_NOT_ALLOWED; ++ } ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaFragSizeFind - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, ++* int cryptoOffset, int macOffset, ++* ++* OUTPUT: ++* int* pCopySize, int* pCryptoDataSize, int* pMacDataSize ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, ++ int cryptoOffset, int macOffset, ++ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize) ++{ ++ MV_CESA_COMMAND *pCmd = pReq->pCmd; ++ int cryptoDataSize, macDataSize, copySize; ++ ++ cryptoDataSize = macDataSize = 0; ++ copySize = *pCopySize; ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ cryptoDataSize = MV_MIN( (copySize - cryptoOffset), ++ (pCmd->cryptoLength - (pReq->frags.cryptoSize + 1)) ); ++ ++ /* cryptoSize for each fragment must be the whole number of blocksSize */ ++ if( MV_IS_NOT_ALIGN(cryptoDataSize, pSA->cryptoBlockSize) ) ++ { ++ cryptoDataSize = MV_ALIGN_DOWN(cryptoDataSize, pSA->cryptoBlockSize); ++ copySize = cryptoOffset + cryptoDataSize; ++ } ++ } ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ macDataSize = MV_MIN( (copySize - macOffset), ++ (pCmd->macLength - (pReq->frags.macSize + 1))); ++ ++ /* macSize for each fragment (except last) must be the whole number of blocksSize */ ++ if( MV_IS_NOT_ALIGN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE) ) ++ { ++ macDataSize = MV_ALIGN_DOWN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE); ++ copySize = macOffset + macDataSize; ++ } ++ cryptoDataSize = copySize - cryptoOffset; ++ } ++ *pCopySize = copySize; ++ ++ if(pCryptoDataSize != NULL) ++ *pCryptoDataSize = cryptoDataSize; ++ ++ if(pMacDataSize != NULL) ++ *pMacDataSize = macDataSize; ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvCesa.h linux-2.6.39/crypto/ocf/kirkwood/cesa/mvCesa.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvCesa.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvCesa.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,412 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator ++* ++* DESCRIPTION: ++* This header file contains macros typedefs and function declaration for ++* the Marvell Cryptographic Engines and Security Accelerator. ++* ++*******************************************************************************/ ++ ++#ifndef __mvCesa_h__ ++#define __mvCesa_h__ ++ ++#include "mvOs.h" ++#include "mvCommon.h" ++#include "mvDebug.h" ++ ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#include "cesa/mvCesa.h" ++#include "cesa/AES/mvAes.h" ++#include "mvSysHwConfig.h" ++ ++#ifdef MV_INCLUDE_IDMA ++#include "idma/mvIdma.h" ++#include "idma/mvIdmaRegs.h" ++#else ++/* Redefine MV_DMA_DESC structure */ ++typedef struct _mvDmaDesc ++{ ++ MV_U32 byteCnt; /* The total number of bytes to transfer */ ++ MV_U32 phySrcAdd; /* The physical source address */ ++ MV_U32 phyDestAdd; /* The physical destination address */ ++ MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ ++ /* then this pointer should point to the */ ++ /* physical address of the next descriptor, */ ++ /* otherwise it should be NULL. */ ++}MV_DMA_DESC; ++#endif /* MV_INCLUDE_IDMA */ ++ ++#include "cesa/mvCesaRegs.h" ++ ++#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */ ++ ++#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */ ++#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */ ++ ++#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE ++ ++#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */ ++#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */ ++#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */ ++#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */ ++#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */ ++ ++#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH ++ ++#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */ ++#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */ ++ ++#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */ ++ ++#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE ++ ++#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */ ++ ++typedef struct ++{ ++ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; ++ MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH]; ++ MV_CESA_OPERATION operation; ++ MV_CESA_DIRECTION direction; ++ MV_CESA_CRYPTO_ALG cryptoAlgorithm; ++ MV_CESA_CRYPTO_MODE cryptoMode; ++ MV_U8 cryptoKeyLength; ++ MV_CESA_MAC_MODE macMode; ++ MV_U8 macKeyLength; ++ MV_U8 digestSize; ++ ++} MV_CESA_OPEN_SESSION; ++ ++typedef struct ++{ ++ MV_BUF_INFO *pFrags; ++ MV_U16 numFrags; ++ MV_U16 mbufSize; ++ ++} MV_CESA_MBUF; ++ ++typedef struct ++{ ++ void* pReqPrv; /* instead of reqId */ ++ MV_U32 retCode; ++ MV_16 sessionId; ++ ++} MV_CESA_RESULT; ++ ++typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult); ++ ++ ++typedef struct ++{ ++ void* pReqPrv; /* instead of reqId */ ++ MV_CESA_MBUF* pSrc; ++ MV_CESA_MBUF* pDst; ++ MV_CESA_CALLBACK* pFuncCB; ++ MV_16 sessionId; ++ MV_U16 ivFromUser; ++ MV_U16 ivOffset; ++ MV_U16 cryptoOffset; ++ MV_U16 cryptoLength; ++ MV_U16 digestOffset; ++ MV_U16 macOffset; ++ MV_U16 macLength; ++ MV_BOOL skipFlush; ++} MV_CESA_COMMAND; ++ ++ ++ ++MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle); ++MV_STATUS mvCesaFinish (void); ++MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid); ++MV_STATUS mvCesaSessionClose(short sid); ++MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize); ++ ++MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd); ++ ++MV_U32 mvCesaInProcessGet(void); ++MV_STATUS mvCesaReadyDispatch(void); ++MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult); ++MV_BOOL mvCesaIsReady(void); ++ ++int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset); ++MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf, ++ int offset, int size); ++MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf, ++ int offset, int size); ++MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, ++ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size); ++ ++/********** Debug functions ********/ ++ ++void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size); ++void mvCesaDebugSA(short sid, int mode); ++void mvCesaDebugStats(void); ++void mvCesaDebugStatsClear(void); ++void mvCesaDebugRegs(void); ++void mvCesaDebugStatus(void); ++void mvCesaDebugQueue(int mode); ++void mvCesaDebugSram(int mode); ++void mvCesaDebugSAD(int mode); ++ ++ ++/******** CESA Private definitions ********/ ++#if (MV_CESA_VERSION >= 2) ++#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW) ++#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ ++ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ ++ | MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \ ++ | MV_CESA_TDMA_NO_BYTE_SWAP_MASK \ ++ | MV_CESA_TDMA_ENABLE_MASK ++#else ++#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \ ++ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ ++ /*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\ ++ | MV_CESA_TDMA_ENABLE_MASK ++ ++#endif ++#else ++#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \ ++ | ICCLR_SRC_BURST_LIM_128BYTE \ ++ | ICCLR_INT_MODE_MASK \ ++ | ICCLR_BLOCK_MODE \ ++ | ICCLR_CHAN_ENABLE \ ++ | ICCLR_DESC_MODE_16M ++#endif /* MV_CESA_VERSION >= 2 */ ++ ++#define MV_CESA_MAX_PKT_SIZE (64 * 1024) ++#define MV_CESA_MAX_MBUF_FRAGS 20 ++ ++#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1) ++ ++#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5) ++ ++#define MAX_CESA_CHAIN_LENGTH 20 ++ ++typedef enum ++{ ++ MV_CESA_IDLE = 0, ++ MV_CESA_PENDING, ++ MV_CESA_PROCESS, ++ MV_CESA_READY, ++#if (MV_CESA_VERSION >= 3) ++ MV_CESA_CHAIN, ++#endif ++} MV_CESA_STATE; ++ ++ ++/* Session database */ ++ ++/* Map of Key materials of the session in SRAM. ++ * Each field must be 8 byte aligned ++ * Total size: 32 + 24 + 24 = 80 bytes ++ */ ++typedef struct ++{ ++ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; ++ MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE]; ++ MV_U8 reservedInner[4]; ++ MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE]; ++ MV_U8 reservedOuter[4]; ++ ++} MV_CESA_SRAM_SA; ++ ++typedef struct ++{ ++ MV_CESA_SRAM_SA* pSramSA; ++ MV_U32 config; ++ MV_U8 cryptoKeyLength; ++ MV_U8 cryptoIvSize; ++ MV_U8 cryptoBlockSize; ++ MV_U8 digestSize; ++ MV_U8 macKeyLength; ++ MV_U8 valid; ++ MV_U8 ctrMode; ++ MV_U32 count; ++ ++} MV_CESA_SA; ++ ++/* DMA list management */ ++typedef struct ++{ ++ MV_DMA_DESC* pDmaFirst; ++ MV_DMA_DESC* pDmaLast; ++ ++} MV_CESA_DMA; ++ ++ ++typedef struct ++{ ++ MV_U8 numFrag; ++ MV_U8 nextFrag; ++ int bufOffset; ++ int cryptoSize; ++ int macSize; ++ int newDigestOffset; ++ MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; ++ ++} MV_CESA_FRAGS; ++ ++/* Request queue */ ++typedef struct ++{ ++ MV_U8 state; ++ MV_U8 fragMode; ++ MV_U8 fixOffset; ++ MV_CESA_COMMAND* pCmd; ++ MV_CESA_COMMAND* pOrgCmd; ++ MV_BUF_INFO dmaDescBuf; ++ MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS]; ++ MV_BUF_INFO cesaDescBuf; ++ MV_CESA_DESC* pCesaDesc; ++ MV_CESA_FRAGS frags; ++ ++ ++} MV_CESA_REQ; ++ ++ ++/* SRAM map */ ++/* Total SRAM size calculation */ ++/* SRAM size = ++ * MV_CESA_MAX_BUF_SIZE + ++ * sizeof(MV_CESA_DESC) + ++ * MV_CESA_MAX_IV_LENGTH + ++ * MV_CESA_MAX_IV_LENGTH + ++ * MV_CESA_MAX_DIGEST_SIZE + ++ * sizeof(MV_CESA_SRAM_SA) ++ * = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes ++ * = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes ++ */ ++typedef struct ++{ ++ MV_U8 buf[MV_CESA_MAX_BUF_SIZE]; ++ MV_CESA_DESC desc; ++ MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH]; ++ MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH]; ++ MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4]; ++ MV_CESA_SRAM_SA sramSA; ++ ++} MV_CESA_SRAM_MAP; ++ ++ ++typedef struct ++{ ++ MV_U32 openedCount; ++ MV_U32 closedCount; ++ MV_U32 fragCount; ++ MV_U32 reqCount; ++ MV_U32 maxReqCount; ++ MV_U32 procCount; ++ MV_U32 readyCount; ++ MV_U32 notReadyCount; ++ MV_U32 startCount; ++#if (MV_CESA_VERSION >= 3) ++ MV_U32 maxChainUsage; ++#endif ++ ++} MV_CESA_STATS; ++ ++ ++/* External variables */ ++ ++extern MV_CESA_STATS cesaStats; ++extern MV_CESA_FRAGS cesaFrags; ++ ++extern MV_BUF_INFO cesaSramSaBuf; ++ ++extern MV_CESA_SA* pCesaSAD; ++extern MV_U16 cesaMaxSA; ++ ++extern MV_CESA_REQ* pCesaReqFirst; ++extern MV_CESA_REQ* pCesaReqLast; ++extern MV_CESA_REQ* pCesaReqEmpty; ++extern MV_CESA_REQ* pCesaReqProcess; ++extern int cesaQueueDepth; ++extern int cesaReqResources; ++#if (MV_CESA_VERSION>= 3) ++extern MV_U32 cesaChainLength; ++#endif ++ ++extern MV_CESA_SRAM_MAP* cesaSramVirtPtr; ++extern MV_U32 cesaSramPhysAddr; ++ ++static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt) ++{ ++ return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr)); ++} ++ ++/* Additional DEBUG functions */ ++void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode); ++void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode); ++void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc); ++ ++ ++ ++#endif /* __mvCesa_h__ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c linux-2.6.39/crypto/ocf/kirkwood/cesa/mvCesaDebug.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,484 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvDebug.h" ++ ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#include "cesa/mvCesa.h" ++#include "cesa/mvCesaRegs.h" ++#include "cesa/AES/mvAes.h" ++ ++static const char* mvCesaDebugStateStr(MV_CESA_STATE state) ++{ ++ switch(state) ++ { ++ case MV_CESA_IDLE: ++ return "Idle"; ++ ++ case MV_CESA_PENDING: ++ return "Pend"; ++ ++ case MV_CESA_PROCESS: ++ return "Proc"; ++ ++ case MV_CESA_READY: ++ return "Ready"; ++ ++ default: ++ break; ++ } ++ return "Unknown"; ++} ++ ++static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper) ++{ ++ switch(oper) ++ { ++ case MV_CESA_MAC_ONLY: ++ return "MacOnly"; ++ ++ case MV_CESA_CRYPTO_ONLY: ++ return "CryptoOnly"; ++ ++ case MV_CESA_MAC_THEN_CRYPTO: ++ return "MacCrypto"; ++ ++ case MV_CESA_CRYPTO_THEN_MAC: ++ return "CryptoMac"; ++ ++ default: ++ break; ++ } ++ return "Null"; ++} ++ ++static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg) ++{ ++ switch(cryptoAlg) ++ { ++ case MV_CESA_CRYPTO_DES: ++ return "DES"; ++ ++ case MV_CESA_CRYPTO_3DES: ++ return "3DES"; ++ ++ case MV_CESA_CRYPTO_AES: ++ return "AES"; ++ ++ default: ++ break; ++ } ++ return "Null"; ++} ++ ++static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode) ++{ ++ switch(macMode) ++ { ++ case MV_CESA_MAC_MD5: ++ return "MD5"; ++ ++ case MV_CESA_MAC_SHA1: ++ return "SHA1"; ++ ++ case MV_CESA_MAC_HMAC_MD5: ++ return "HMAC-MD5"; ++ ++ case MV_CESA_MAC_HMAC_SHA1: ++ return "HMAC_SHA1"; ++ ++ default: ++ break; ++ } ++ return "Null"; ++} ++ ++void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode) ++{ ++ mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n", ++ pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst, ++ pCmd->pFuncCB, pCmd->sessionId); ++ mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n", ++ pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength, ++ pCmd->digestOffset, pCmd->macOffset, pCmd->macLength); ++} ++ ++/* no need to use in tool */ ++void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size) ++{ ++ int frag, len, fragOffset; ++ ++ if(str != NULL) ++ mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n", ++ str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize); ++ ++ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return; ++ } ++ ++ for(; fragnumFrags; frag++) ++ { ++ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", ++ frag, pMbuf->pFrags[frag].bufVirtPtr, ++ pMbuf->pFrags[frag].bufSize); ++ if(size > 0) ++ { ++ len = MV_MIN(pMbuf->pFrags[frag].bufSize, size); ++ mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1); ++ size -= len; ++ fragOffset = 0; ++ } ++ } ++} ++ ++void mvCesaDebugRegs(void) ++{ ++ mvOsPrintf("\t CESA Registers:\n"); ++ ++ mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n", ++ MV_CESA_CMD_REG, ++ MV_REG_READ( MV_CESA_CMD_REG ) ); ++ ++ mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n", ++ MV_CESA_CHAN_DESC_OFFSET_REG, ++ MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) ); ++ ++ mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n", ++ MV_CESA_CFG_REG, ++ MV_REG_READ( MV_CESA_CFG_REG ) ); ++ ++ mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n", ++ MV_CESA_STATUS_REG, ++ MV_REG_READ( MV_CESA_STATUS_REG ) ); ++ ++ mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n", ++ MV_CESA_ISR_CAUSE_REG, ++ MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) ); ++ ++ mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n", ++ MV_CESA_ISR_MASK_REG, ++ MV_REG_READ( MV_CESA_ISR_MASK_REG ) ); ++#if (MV_CESA_VERSION >= 2) ++ mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_CTRL_REG, ++ MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_BYTE_COUNT_REG, ++ MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_SRC_ADDR_REG, ++ MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_DST_ADDR_REG, ++ MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_NEXT_DESC_PTR_REG, ++ MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_CURR_DESC_PTR_REG, ++ MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_ERROR_CAUSE_REG, ++ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_ERROR_MASK_REG, ++ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); ++ ++#endif ++} ++ ++void mvCesaDebugStatus(void) ++{ ++ mvOsPrintf("\n\t CESA Status\n\n"); ++ ++ mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ", ++ pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ), ++ cesaReqResources); ++#if (MV_CESA_VERSION >= 3) ++ mvOsPrintf("chainLength=%u\n",cesaChainLength); ++#else ++ mvOsPrintf("\n"); ++#endif ++ ++ mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n", ++ pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA)); ++ ++ mvOsPrintf("\n"); ++ ++ mvCesaDebugRegs(); ++ mvCesaDebugStats(); ++ mvCesaDebugStatsClear(); ++} ++ ++void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc) ++{ ++ mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n", ++ pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset); ++ ++ mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n", ++ pDesc->cryptoDataLen, pDesc->cryptoKeyOffset, ++ pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset); ++ ++ mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n", ++ pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen, ++ pDesc->macInnerIvOffset, pDesc->macOuterIvOffset); ++} ++ ++void mvCesaDebugQueue(int mode) ++{ ++ mvOsPrintf("\n\t CESA Request Queue:\n\n"); ++ ++ mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n", ++ pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ)); ++ ++ mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n", ++ pCesaReqEmpty, pCesaReqProcess, ++ cesaReqResources); ++ ++ if(mode != 0) ++ { ++ int count = 0; ++ MV_CESA_REQ* pReq = pCesaReqFirst; ++ ++ for(count=0; countstate), ++ pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]); ++ if(pReq->fragMode != MV_CESA_FRAG_NONE) ++ { ++ int frag; ++ ++ mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n", ++ &pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag, ++ pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize); ++ for(frag=0; fragfrags.numFrag; frag++) ++ { ++ mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag, ++ pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]); ++ } ++ } ++ if(mode > 1) ++ { ++ /* Print out Command */ ++ mvCesaDebugCmd(pReq->pCmd, mode); ++ ++ /* Print out Descriptor */ ++ mvCesaDebugDescriptor(&pReq->pCesaDesc[0]); ++ } ++ pReq++; ++ } ++ } ++} ++ ++ ++void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode) ++{ ++ if(pSramSA == NULL) ++ { ++ mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA); ++ return; ++ } ++ mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n", ++ pSramSA, sizeof(MV_CESA_SRAM_SA)); ++ ++ if(mode != 0) ++ { ++ mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n", ++ pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH); ++ mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1); ++ ++ mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n", ++ pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE); ++ mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1); ++ ++ mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n", ++ pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE); ++ mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1); ++ } ++} ++ ++void mvCesaDebugSA(short sid, int mode) ++{ ++ MV_CESA_OPERATION oper; ++ MV_CESA_DIRECTION dir; ++ MV_CESA_CRYPTO_ALG cryptoAlg; ++ MV_CESA_CRYPTO_MODE cryptoMode; ++ MV_CESA_MAC_MODE macMode; ++ MV_CESA_SA* pSA = &pCesaSAD[sid]; ++ ++ if( (pSA->valid) || ((pSA->count != 0) && (mode > 0)) || (mode >= 2) ) ++ { ++ mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n", ++ sid, pSA, ++ pSA->valid ? "Valid" : "Invalid", pSA->count); ++ ++ oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET; ++ dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT; ++ mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper), ++ (dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode"); ++ if(oper != MV_CESA_MAC_ONLY) ++ { ++ cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET; ++ cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT; ++ mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg), ++ (cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC"); ++ } ++ if(oper != MV_CESA_CRYPTO_ONLY) ++ { ++ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; ++ mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode)); ++ } ++ mvOsPrintf("\n"); ++ ++ if(mode > 0) ++ { ++ mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n", ++ pCesaSAD[sid].config, pCesaSAD[sid].cryptoKeyLength, ++ pCesaSAD[sid].digestSize); ++ ++ mvCesaDebugSramSA(pCesaSAD[sid].pSramSA, mode); ++ } ++ } ++} ++ ++ ++/**/ ++void mvCesaDebugSram(int mode) ++{ ++ mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n", ++ sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr); ++ ++ mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n", ++ MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf); ++ if(mode != 0) ++ mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1); ++ ++ mvOsPrintf("\n"); ++ mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n", ++ sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc); ++ if(mode != 0) ++ { ++ mvOsPrintf("\n"); ++ mvCesaDebugDescriptor(&cesaSramVirtPtr->desc); ++ } ++ mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n", ++ MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV); ++ if(mode != 0) ++ { ++ mvOsPrintf("\n"); ++ mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1); ++ } ++ mvOsPrintf("\n"); ++ mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0); ++} ++ ++void mvCesaDebugSAD(int mode) ++{ ++ int sid; ++ ++ mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n", ++ pCesaSAD, cesaMaxSA); ++ ++ for(sid=0; sid= 3) ++ mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage); ++#endif ++ mvOsPrintf("\n"); ++ mvOsPrintf("proc=%u, ready=%u, notReady=%u\n", ++ cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount); ++} ++ ++void mvCesaDebugStatsClear(void) ++{ ++ memset(&cesaStats, 0, sizeof(cesaStats)); ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h linux-2.6.39/crypto/ocf/kirkwood/cesa/mvCesaRegs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,357 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvCesaRegs_h__ ++#define __mvCesaRegs_h__ ++ ++#include "mvTypes.h" ++ ++typedef struct ++{ ++ /* word 0 */ ++ MV_U32 config; ++ /* word 1 */ ++ MV_U16 cryptoSrcOffset; ++ MV_U16 cryptoDstOffset; ++ /* word 2 */ ++ MV_U16 cryptoDataLen; ++ MV_U16 reserved1; ++ /* word 3 */ ++ MV_U16 cryptoKeyOffset; ++ MV_U16 reserved2; ++ /* word 4 */ ++ MV_U16 cryptoIvOffset; ++ MV_U16 cryptoIvBufOffset; ++ /* word 5 */ ++ MV_U16 macSrcOffset; ++ MV_U16 macTotalLen; ++ /* word 6 */ ++ MV_U16 macDigestOffset; ++ MV_U16 macDataLen; ++ /* word 7 */ ++ MV_U16 macInnerIvOffset; ++ MV_U16 macOuterIvOffset; ++ ++} MV_CESA_DESC; ++ ++/* operation */ ++typedef enum ++{ ++ MV_CESA_MAC_ONLY = 0, ++ MV_CESA_CRYPTO_ONLY = 1, ++ MV_CESA_MAC_THEN_CRYPTO = 2, ++ MV_CESA_CRYPTO_THEN_MAC = 3, ++ ++ MV_CESA_MAX_OPERATION ++ ++} MV_CESA_OPERATION; ++ ++#define MV_CESA_OPERATION_OFFSET 0 ++#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET) ++ ++/* mac algorithm */ ++typedef enum ++{ ++ MV_CESA_MAC_NULL = 0, ++ MV_CESA_MAC_MD5 = 4, ++ MV_CESA_MAC_SHA1 = 5, ++ MV_CESA_MAC_HMAC_MD5 = 6, ++ MV_CESA_MAC_HMAC_SHA1 = 7, ++ ++} MV_CESA_MAC_MODE; ++ ++#define MV_CESA_MAC_MODE_OFFSET 4 ++#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET) ++ ++typedef enum ++{ ++ MV_CESA_MAC_DIGEST_FULL = 0, ++ MV_CESA_MAC_DIGEST_96B = 1, ++ ++} MV_CESA_MAC_DIGEST_SIZE; ++ ++#define MV_CESA_MAC_DIGEST_SIZE_BIT 7 ++#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT) ++ ++ ++typedef enum ++{ ++ MV_CESA_CRYPTO_NULL = 0, ++ MV_CESA_CRYPTO_DES = 1, ++ MV_CESA_CRYPTO_3DES = 2, ++ MV_CESA_CRYPTO_AES = 3, ++ ++} MV_CESA_CRYPTO_ALG; ++ ++#define MV_CESA_CRYPTO_ALG_OFFSET 8 ++#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET) ++ ++ ++/* direction */ ++typedef enum ++{ ++ MV_CESA_DIR_ENCODE = 0, ++ MV_CESA_DIR_DECODE = 1, ++ ++} MV_CESA_DIRECTION; ++ ++#define MV_CESA_DIRECTION_BIT 12 ++#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT) ++ ++/* crypto IV mode */ ++typedef enum ++{ ++ MV_CESA_CRYPTO_ECB = 0, ++ MV_CESA_CRYPTO_CBC = 1, ++ ++ /* NO HW Support */ ++ MV_CESA_CRYPTO_CTR = 10, ++ ++} MV_CESA_CRYPTO_MODE; ++ ++#define MV_CESA_CRYPTO_MODE_BIT 16 ++#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) ++ ++/* 3DES mode */ ++typedef enum ++{ ++ MV_CESA_CRYPTO_3DES_EEE = 0, ++ MV_CESA_CRYPTO_3DES_EDE = 1, ++ ++} MV_CESA_CRYPTO_3DES_MODE; ++ ++#define MV_CESA_CRYPTO_3DES_MODE_BIT 20 ++#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT) ++ ++ ++/* AES Key Length */ ++typedef enum ++{ ++ MV_CESA_CRYPTO_AES_KEY_128 = 0, ++ MV_CESA_CRYPTO_AES_KEY_192 = 1, ++ MV_CESA_CRYPTO_AES_KEY_256 = 2, ++ ++} MV_CESA_CRYPTO_AES_KEY_LEN; ++ ++#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24 ++#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET) ++ ++/* Fragmentation mode */ ++typedef enum ++{ ++ MV_CESA_FRAG_NONE = 0, ++ MV_CESA_FRAG_FIRST = 1, ++ MV_CESA_FRAG_LAST = 2, ++ MV_CESA_FRAG_MIDDLE = 3, ++ ++} MV_CESA_FRAG_MODE; ++ ++#define MV_CESA_FRAG_MODE_OFFSET 30 ++#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET) ++/*---------------------------------------------------------------------------*/ ++ ++/********** Security Accelerator Command Register **************/ ++#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00) ++ ++#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 ++#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT) ++ ++#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 ++#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) ++ ++/********** Security Accelerator Descriptor Pointers Register **********/ ++#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04) ++ ++/********** Security Accelerator Configuration Register **********/ ++#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08) ++ ++#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0 ++#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT) ++ ++#define MV_CESA_CFG_WAIT_DMA_BIT 7 ++#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT) ++ ++#define MV_CESA_CFG_ACT_DMA_BIT 9 ++#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT) ++ ++#define MV_CESA_CFG_CHAIN_MODE_BIT 11 ++#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT) ++ ++/********** Security Accelerator Status Register ***********/ ++#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C) ++ ++#define MV_CESA_STATUS_ACTIVE_BIT 0 ++#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT) ++ ++#define MV_CESA_STATUS_DIGEST_ERR_BIT 8 ++#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT) ++ ++ ++/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */ ++#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20) ++ ++/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */ ++#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24) ++ ++#define MV_CESA_CAUSE_AUTH_MASK (1 << 0) ++#define MV_CESA_CAUSE_DES_MASK (1 << 1) ++#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2) ++#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3) ++#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4) ++ ++#define MV_CESA_CAUSE_ACC_BIT 5 ++#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT) ++ ++#define MV_CESA_CAUSE_ACC_DMA_BIT 7 ++#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT) ++#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT) ++ ++#define MV_CESA_CAUSE_DMA_COMPL_BIT 9 ++#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT) ++ ++#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10 ++#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT) ++ ++#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11 ++#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT) ++ ++ ++#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38) ++#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20) ++#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24) ++ ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2)) ++ ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10) ++#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18) ++ ++#define MV_CESA_AUTH_ALGORITHM_BIT 0 ++#define MV_CESA_AUTH_ALGORITHM_MD5 (0< ++wait_queue_head_t cesaTest_waitq; ++spinlock_t cesaLock; ++ ++#define CESA_TEST_LOCK(flags) spin_lock_irqsave( &cesaLock, flags) ++#define CESA_TEST_UNLOCK(flags) spin_unlock_irqrestore( &cesaLock, flags); ++ ++#define CESA_TEST_WAIT_INIT() init_waitqueue_head(&cesaTest_waitq) ++#define CESA_TEST_WAKE_UP() wake_up(&cesaTest_waitq) ++#define CESA_TEST_WAIT(cond, ms) wait_event_timeout(cesaTest_waitq, (cond), msecs_to_jiffies(ms)) ++ ++#define CESA_TEST_TICK_GET() jiffies ++#define CESA_TEST_TICK_TO_MS(tick) jiffies_to_msecs(tick) ++ ++#elif defined(MV_NETBSD) ++ ++#include ++#include ++static int cesaLock; ++ ++#define CESA_TEST_LOCK(flags) flags = splnet() ++#define CESA_TEST_UNLOCK(flags) splx(flags) ++ ++#define CESA_TEST_WAIT_INIT() /* nothing */ ++#define CESA_TEST_WAKE_UP() wakeup(&cesaLock) ++#define CESA_TEST_WAIT(cond, ms) \ ++do { \ ++ while (!(cond)) \ ++ tsleep(&cesaLock, PWAIT, "cesatest",mstohz(ms)); \ ++} while (/*CONSTCOND*/0) ++ ++#define CESA_TEST_TICK_GET() hardclock_ticks ++#define CESA_TEST_TICK_TO_MS(tick) ((1000/hz)*(tick)) ++ ++#define request_irq(i,h,t,n,a) \ ++ !mv_intr_establish((i),IPL_NET,(int(*)(void *))(h),(a)) ++ ++#else ++#error "Only Linux, VxWorks, or NetBSD OS are supported" ++#endif ++ ++#include "mvDebug.h" ++ ++#include "mvSysHwConfig.h" ++#include "boardEnv/mvBoardEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "cntmr/mvCntmr.h" ++#include "cesa/mvCesa.h" ++#include "cesa/mvCesaRegs.h" ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#if defined(CONFIG_MV646xx) ++#include "marvell_pic.h" ++#endif ++ ++#define MV_CESA_USE_TIMER_ID 0 ++#define CESA_DEF_BUF_SIZE 1500 ++#define CESA_DEF_BUF_NUM 1 ++#define CESA_DEF_SESSION_NUM 32 ++ ++#define CESA_DEF_ITER_NUM 100 ++ ++#define CESA_DEF_REQ_SIZE 256 ++ ++ ++/* CESA Tests Debug */ ++#undef CESA_TEST_DEBUG ++ ++#ifdef CESA_TEST_DEBUG ++ ++# define CESA_TEST_DEBUG_PRINT(msg) mvOsPrintf msg ++# define CESA_TEST_DEBUG_CODE(code) code ++ ++typedef struct ++{ ++ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ ++ MV_U32 timeStamp; ++ MV_U32 cause; ++ MV_U32 realCause; ++ MV_U32 dmaCause; ++ int resources; ++ MV_CESA_REQ* pReqReady; ++ MV_CESA_REQ* pReqEmpty; ++ MV_CESA_REQ* pReqProcess; ++} MV_CESA_TEST_TRACE; ++ ++#define MV_CESA_TEST_TRACE_SIZE 25 ++ ++static int cesaTestTraceIdx = 0; ++static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; ++ ++static void cesaTestTraceAdd(int type, MV_U32 cause) ++{ ++ cesaTestTrace[cesaTestTraceIdx].type = type; ++ cesaTestTrace[cesaTestTraceIdx].cause = cause; ++ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ cesaTestTrace[cesaTestTraceIdx].dmaCause = MV_REG_READ(IDMA_CAUSE_REG); ++ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; ++ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; ++ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; ++ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; ++ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); ++ cesaTestTraceIdx++; ++ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) ++ cesaTestTraceIdx = 0; ++} ++ ++#else ++ ++# define CESA_TEST_DEBUG_PRINT(msg) ++# define CESA_TEST_DEBUG_CODE(code) ++ ++#endif /* CESA_TEST_DEBUG */ ++ ++int cesaExpReqId=0; ++int cesaCbIter=0; ++ ++int cesaIdx; ++int cesaIteration; ++int cesaRateSize; ++int cesaReqSize; ++unsigned long cesaTaskId; ++int cesaBufNum; ++int cesaBufSize; ++int cesaCheckOffset; ++int cesaCheckSize; ++int cesaCheckMode; ++int cesaTestIdx; ++int cesaCaseIdx; ++ ++ ++MV_U32 cesaTestIsrCount = 0; ++MV_U32 cesaTestIsrMissCount = 0; ++ ++MV_U32 cesaCryptoError = 0; ++MV_U32 cesaReqIdError = 0; ++MV_U32 cesaError = 0; ++ ++char* cesaHexBuffer = NULL; ++ ++char* cesaBinBuffer = NULL; ++char* cesaExpBinBuffer = NULL; ++ ++char* cesaInputHexStr = NULL; ++char* cesaOutputHexStr = NULL; ++ ++MV_BUF_INFO cesaReqBufs[CESA_DEF_REQ_SIZE]; ++ ++MV_CESA_COMMAND* cesaCmdRing; ++MV_CESA_RESULT cesaResult; ++ ++int cesaTestFull = 0; ++ ++MV_BOOL cesaIsReady = MV_FALSE; ++MV_U32 cesaCycles = 0; ++MV_U32 cesaBeginTicks = 0; ++MV_U32 cesaEndTicks = 0; ++MV_U32 cesaRate = 0; ++MV_U32 cesaRateAfterDot = 0; ++ ++void *cesaTestOSHandle = NULL; ++ ++enum ++{ ++ CESA_FAST_CHECK_MODE = 0, ++ CESA_FULL_CHECK_MODE, ++ CESA_NULL_CHECK_MODE, ++ CESA_SHOW_CHECK_MODE, ++ CESA_SW_SHOW_CHECK_MODE, ++ CESA_SW_NULL_CHECK_MODE, ++ ++ CESA_MAX_CHECK_MODE ++}; ++ ++enum ++{ ++ DES_TEST_TYPE = 0, ++ TRIPLE_DES_TEST_TYPE = 1, ++ AES_TEST_TYPE = 2, ++ MD5_TEST_TYPE = 3, ++ SHA_TEST_TYPE = 4, ++ COMBINED_TEST_TYPE = 5, ++ ++ MAX_TEST_TYPE ++}; ++ ++/* Tests data base */ ++typedef struct ++{ ++ short sid; ++ char cryptoAlgorithm; /* DES/3DES/AES */ ++ char cryptoMode; /* ECB or CBC */ ++ char macAlgorithm; /* MD5 / SHA1 */ ++ char operation; /* CRYPTO/HMAC/CRYPTO+HMAC/HMAC+CRYPTO */ ++ char direction; /* ENCODE(SIGN)/DECODE(VERIFY) */ ++ unsigned char* pCryptoKey; ++ int cryptoKeySize; ++ unsigned char* pMacKey; ++ int macKeySize; ++ const char* name; ++ ++} MV_CESA_TEST_SESSION; ++ ++typedef struct ++{ ++ MV_CESA_TEST_SESSION* pSessions; ++ int numSessions; ++ ++} MV_CESA_TEST_DB_ENTRY; ++ ++typedef struct ++{ ++ char* plainHexStr; ++ char* cipherHexStr; ++ unsigned char* pCryptoIV; ++ int cryptoLength; ++ int macLength; ++ int digestOffset; ++ ++} MV_CESA_TEST_CASE; ++ ++typedef struct ++{ ++ int size; ++ const char* outputHexStr; ++ ++} MV_CESA_SIZE_TEST; ++ ++static unsigned char cryptoKey1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, ++ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, ++ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; ++ ++static unsigned char cryptoKey7[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; ++static unsigned char iv1[] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef}; ++ ++ ++static unsigned char cryptoKey2[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; ++ ++static unsigned char cryptoKey3[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; ++ ++static unsigned char cryptoKey4[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, ++ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}; ++ ++static unsigned char cryptoKey5[] = {0x56, 0xe4, 0x7a, 0x38, 0xc5, 0x59, 0x89, 0x74, ++ 0xbc, 0x46, 0x90, 0x3d, 0xba, 0x29, 0x03, 0x49}; ++ ++ ++static unsigned char key3des1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, ++ 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, ++ 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, 0x23}; ++ ++/* Input ASCII string: The quick brown fox jump */ ++static char plain3des1[] = "54686520717566636B2062726F776E20666F78206A756D70"; ++static char cipher3des1[] = "A826FD8CE53B855FCCE21C8112256FE668D5C05DD9B6B900"; ++ ++static unsigned char key3des2[] = {0x62, 0x7f, 0x46, 0x0e, 0x08, 0x10, 0x4a, 0x10, ++ 0x43, 0xcd, 0x26, 0x5d, 0x58, 0x40, 0xea, 0xf1, ++ 0x31, 0x3e, 0xdf, 0x97, 0xdf, 0x2a, 0x8a, 0x8c}; ++ ++static unsigned char iv3des2[] = {0x8e, 0x29, 0xf7, 0x5e, 0xa7, 0x7e, 0x54, 0x75}; ++ ++static char plain3des2[] = "326a494cd33fe756"; ++ ++static char cipher3desCbc2[] = "8e29f75ea77e5475" ++ "b22b8d66de970692"; ++ ++static unsigned char key3des3[] = {0x37, 0xae, 0x5e, 0xbf, 0x46, 0xdf, 0xf2, 0xdc, ++ 0x07, 0x54, 0xb9, 0x4f, 0x31, 0xcb, 0xb3, 0x85, ++ 0x5e, 0x7f, 0xd3, 0x6d, 0xc8, 0x70, 0xbf, 0xae}; ++ ++static unsigned char iv3des3[] = {0x3d, 0x1d, 0xe3, 0xcc, 0x13, 0x2e, 0x3b, 0x65}; ++ ++static char plain3des3[] = "84401f78fe6c10876d8ea23094ea5309"; ++ ++static char cipher3desCbc3[] = "3d1de3cc132e3b65" ++ "7b1f7c7e3b1c948ebd04a75ffba7d2f5"; ++ ++static unsigned char iv5[] = {0x8c, 0xe8, 0x2e, 0xef, 0xbe, 0xa0, 0xda, 0x3c, ++ 0x44, 0x69, 0x9e, 0xd7, 0xdb, 0x51, 0xb7, 0xd9}; ++ ++static unsigned char aesCtrKey[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, ++ 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; ++ ++static unsigned char mdKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, ++ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b}; ++ ++static unsigned char mdKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}; ++ ++static unsigned char shaKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, ++ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, ++ 0x0b, 0x0b, 0x0b, 0x0b}; ++ ++static unsigned char shaKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ 0xaa, 0xaa, 0xaa, 0xaa}; ++ ++static unsigned char mdKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10}; ++ ++static unsigned char shaKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, ++ 0x11, 0x12, 0x13, 0x14}; ++ ++ ++static MV_CESA_TEST_SESSION desTestSessions[] = ++{ ++/*000*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES ECB encode", ++ }, ++/*001*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES ECB decode", ++ }, ++/*002*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES CBC encode" ++ }, ++/*003*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES CBC decode" ++ }, ++/*004*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, NULL, 0, ++ "NULL Crypto Algorithm encode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION tripleDesTestSessions[] = ++{ ++/*100*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES ECB encode", ++ }, ++/*101*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES ECB decode", ++ }, ++/*102*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES CBC encode" ++ }, ++/*103*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES CBC decode" ++ }, ++/*104*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ key3des1, sizeof(key3des1), ++ NULL, 0, ++ "3DES ECB encode" ++ }, ++/*105*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ key3des2, sizeof(key3des2), ++ NULL, 0, ++ "3DES ECB encode" ++ }, ++/*106*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ key3des3, sizeof(key3des3), ++ NULL, 0, ++ "3DES ECB encode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION aesTestSessions[] = ++{ ++/*200*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), ++ NULL, 0, ++ "AES-128 ECB encode" ++ }, ++/*201*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), ++ NULL, 0, ++ "AES-128 ECB decode" ++ }, ++/*202*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ NULL, 0, ++ "AES-128 CBC encode" ++ }, ++/*203*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ NULL, 0, ++ "AES-128 CBC decode" ++ }, ++/*204*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), ++ NULL, 0, ++ "AES-192 ECB encode" ++ }, ++/*205*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), ++ NULL, 0, ++ "AES-192 ECB decode" ++ }, ++/*206*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), ++ NULL, 0, ++ "AES-256 ECB encode" ++ }, ++/*207*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), ++ NULL, 0, ++ "AES-256 ECB decode" ++ }, ++/*208*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CTR, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ aesCtrKey, sizeof(aesCtrKey)/sizeof(aesCtrKey[0]), ++ NULL, 0, ++ "AES-128 CTR encode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION md5TestSessions[] = ++{ ++/*300*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ mdKey1, sizeof(mdKey1), ++ "HMAC-MD5 Generate Signature" ++ }, ++/*301*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ mdKey1, sizeof(mdKey1), ++ "HMAC-MD5 Verify Signature" ++ }, ++/*302*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ mdKey2, sizeof(mdKey2), ++ "HMAC-MD5 Generate Signature" ++ }, ++/*303*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ mdKey2, sizeof(mdKey2), ++ "HMAC-MD5 Verify Signature" ++ }, ++/*304*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ mdKey4, sizeof(mdKey4), ++ "HMAC-MD5 Generate Signature" ++ }, ++/*305*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ NULL, 0, ++ "HASH-MD5 Generate Signature" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION shaTestSessions[] = ++{ ++/*400*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ shaKey1, sizeof(shaKey1), ++ "HMAC-SHA1 Generate Signature" ++ }, ++/*401*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ shaKey1, sizeof(shaKey1), ++ "HMAC-SHA1 Verify Signature" ++ }, ++/*402*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ shaKey2, sizeof(shaKey2), ++ "HMAC-SHA1 Generate Signature" ++ }, ++/*403*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ shaKey2, sizeof(shaKey2), ++ "HMAC-SHA1 Verify Signature" ++ }, ++/*404*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ shaKey4, sizeof(shaKey4), ++ "HMAC-SHA1 Generate Signature" ++ }, ++/*405*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ NULL, 0, ++ "HASH-SHA1 Generate Signature" ++ }, ++}; ++ ++static MV_CESA_TEST_SESSION combinedTestSessions[] = ++{ ++/*500*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, MV_CESA_DES_KEY_LENGTH, ++ mdKey4, sizeof(mdKey4), ++ "DES + MD5 encode" ++ }, ++/*501*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, MV_CESA_DES_KEY_LENGTH, ++ shaKey4, sizeof(shaKey4), ++ "DES + SHA1 encode" ++ }, ++/*502*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ mdKey4, sizeof(mdKey4), ++ "3DES + MD5 encode" ++ }, ++/*503*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ shaKey4, sizeof(shaKey4), ++ "3DES + SHA1 encode" ++ }, ++/*504*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ mdKey4, sizeof(mdKey4), ++ "3DES CBC + MD5 encode" ++ }, ++/*505*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ shaKey4, sizeof(shaKey4), ++ "3DES CBC + SHA1 encode" ++ }, ++/*506*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ mdKey4, sizeof(mdKey4), ++ "AES-128 CBC + MD5 encode" ++ }, ++/*507*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ shaKey4, sizeof(shaKey4), ++ "AES-128 CBC + SHA1 encode" ++ }, ++/*508*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_THEN_CRYPTO, ++ MV_CESA_DIR_DECODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ mdKey4, sizeof(mdKey4), ++ "HMAC-MD5 + 3DES decode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_DB_ENTRY cesaTestsDB[MAX_TEST_TYPE+1] = ++{ ++ { desTestSessions, sizeof(desTestSessions)/sizeof(desTestSessions[0]) }, ++ { tripleDesTestSessions, sizeof(tripleDesTestSessions)/sizeof(tripleDesTestSessions[0]) }, ++ { aesTestSessions, sizeof(aesTestSessions)/sizeof(aesTestSessions[0]) }, ++ { md5TestSessions, sizeof(md5TestSessions)/sizeof(md5TestSessions[0]) }, ++ { shaTestSessions, sizeof(shaTestSessions)/sizeof(shaTestSessions[0]) }, ++ { combinedTestSessions, sizeof(combinedTestSessions)/sizeof(combinedTestSessions[0]) }, ++ { NULL, 0 } ++}; ++ ++ ++char cesaNullPlainHexText[] = "000000000000000000000000000000000000000000000000"; ++ ++char cesaPlainAsciiText[] = "Now is the time for all "; ++char cesaPlainHexEbc[] = "4e6f77206973207468652074696d6520666f7220616c6c20"; ++char cesaCipherHexEcb[] = "3fa40e8a984d48156a271787ab8883f9893d51ec4b563b53"; ++char cesaPlainHexCbc[] = "1234567890abcdef4e6f77206973207468652074696d6520666f7220616c6c20"; ++char cesaCipherHexCbc[] = "1234567890abcdefe5c7cdde872bf27c43e934008c389c0f683788499a7c05f6"; ++ ++char cesaAesPlainHexEcb[] = "000102030405060708090a0b0c0d0e0f"; ++char cesaAes128cipherHexEcb[] = "0a940bb5416ef045f1c39458c653ea5a"; ++char cesaAes192cipherHexEcb[] = "0060bffe46834bb8da5cf9a61ff220ae"; ++char cesaAes256cipherHexEcb[] = "5a6e045708fb7196f02e553d02c3a692"; ++ ++char cesaAsciiStr1[] = "Hi There"; ++char cesaDataHexStr1[] = "4869205468657265"; ++char cesaHmacMd5digestHex1[] = "9294727a3638bb1c13f48ef8158bfc9d"; ++char cesaHmacSha1digestHex1[] = "b617318655057264e28bc0b6fb378c8ef146be00"; ++char cesaDataAndMd5digest1[] = "48692054686572659294727a3638bb1c13f48ef8158bfc9d"; ++char cesaDataAndSha1digest1[] = "4869205468657265b617318655057264e28bc0b6fb378c8ef146be00"; ++ ++char cesaAesPlainText[] = "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" ++ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" ++ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" ++ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; ++ ++char cesaAes128CipherCbc[] = "c30e32ffedc0774e6aff6af0869f71aa" ++ "0f3af07a9a31a9c684db207eb0ef8e4e" ++ "35907aa632c3ffdf868bb7b29d3d46ad" ++ "83ce9f9a102ee99d49a53e87f4c3da55"; ++ ++char cesaAesIvPlainText[] = "8ce82eefbea0da3c44699ed7db51b7d9" ++ "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" ++ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" ++ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" ++ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; ++ ++char cesaAes128IvCipherCbc[] = "8ce82eefbea0da3c44699ed7db51b7d9" ++ "c30e32ffedc0774e6aff6af0869f71aa" ++ "0f3af07a9a31a9c684db207eb0ef8e4e" ++ "35907aa632c3ffdf868bb7b29d3d46ad" ++ "83ce9f9a102ee99d49a53e87f4c3da55"; ++ ++char cesaAesCtrPlain[] = "00E0017B27777F3F4A1786F000000001" ++ "000102030405060708090A0B0C0D0E0F" ++ "101112131415161718191A1B1C1D1E1F" ++ "20212223"; ++ ++char cesaAesCtrCipher[] = "00E0017B27777F3F4A1786F000000001" ++ "C1CF48A89F2FFDD9CF4652E9EFDB72D7" ++ "4540A42BDE6D7836D59A5CEAAEF31053" ++ "25B2072F"; ++ ++ ++ ++/* Input cesaHmacHex3 is '0xdd' repeated 50 times */ ++char cesaHmacMd5digestHex3[] = "56be34521d144c88dbb8c733f0e8b3f6"; ++char cesaHmacSha1digestHex3[] = "125d7342b9ac11cd91a39af48aa17b4f63f175d3"; ++char cesaDataHexStr3[50*2+1] = ""; ++char cesaDataAndMd5digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacMd5digestHex3)+8*2+1] = ""; ++char cesaDataAndSha1digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacSha1digestHex3)+8*2+1] = ""; ++ ++/* Ascii string is "abc" */ ++char hashHexStr3[] = "616263"; ++char hashMd5digest3[] = "900150983cd24fb0d6963f7d28e17f72"; ++char hashSha1digest3[] = "a9993e364706816aba3e25717850c26c9cd0d89d"; ++ ++char hashHexStr80[] = "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930"; ++ ++char hashMd5digest80[] = "57edf4a22be3c955ac49da2e2107b67a"; ++ ++char tripleDesThenMd5digest80[] = "b7726a03aad490bd6c5a452a89a1b271"; ++char tripleDesThenSha1digest80[] = "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"; ++ ++char cbc3desThenMd5digest80[] = "6f463057e1a90e0e91ae505b527bcec0"; ++char cbc3desThenSha1digest80[] = "1b002ed050be743aa98860cf35659646bb8efcc0"; ++ ++char cbcAes128ThenMd5digest80[] = "6b6e863ac5a71d15e3e9b1c86c9ba05f"; ++char cbcAes128ThenSha1digest80[] = "13558472d1fc1c90dffec6e5136c7203452d509b"; ++ ++ ++static MV_CESA_TEST_CASE cesaTestCases[] = ++{ ++ /* plainHexStr cipherHexStr IV crypto mac digest */ ++ /* Length Length Offset */ ++ /*0*/ { NULL, NULL, NULL, 0, 0, -1 }, ++ /*1*/ { cesaPlainHexEbc, cesaCipherHexEcb, NULL, 24, 0, -1 }, ++ /*2*/ { cesaPlainHexCbc, cesaCipherHexCbc, NULL, 24, 0, -1 }, ++ /*3*/ { cesaAesPlainHexEcb, cesaAes128cipherHexEcb, NULL, 16, 0, -1 }, ++ /*4*/ { cesaAesPlainHexEcb, cesaAes192cipherHexEcb, NULL, 16, 0, -1 }, ++ /*5*/ { cesaAesPlainHexEcb, cesaAes256cipherHexEcb, NULL, 16, 0, -1 }, ++ /*6*/ { cesaDataHexStr1, cesaHmacMd5digestHex1, NULL, 0, 8, -1 }, ++ /*7*/ { NULL, cesaDataAndMd5digest1, NULL, 0, 8, -1 }, ++ /*8*/ { cesaDataHexStr3, cesaHmacMd5digestHex3, NULL, 0, 50, -1 }, ++ /*9*/ { NULL, cesaDataAndMd5digest3, NULL, 0, 50, -1 }, ++/*10*/ { cesaAesPlainText, cesaAes128IvCipherCbc, iv5, 64, 0, -1 }, ++/*11*/ { cesaDataHexStr1, cesaHmacSha1digestHex1, NULL, 0, 8, -1 }, ++/*12*/ { NULL, cesaDataAndSha1digest1, NULL, 0, 8, -1 }, ++/*13*/ { cesaDataHexStr3, cesaHmacSha1digestHex3, NULL, 0, 50, -1 }, ++/*14*/ { NULL, cesaDataAndSha1digest3, NULL, 0, 50, -1 }, ++/*15*/ { hashHexStr3, hashMd5digest3, NULL, 0, 3, -1 }, ++/*16*/ { hashHexStr3, hashSha1digest3, NULL, 0, 3, -1 }, ++/*17*/ { hashHexStr80, tripleDesThenMd5digest80, NULL, 80, 80, -1 }, ++/*18*/ { hashHexStr80, tripleDesThenSha1digest80, NULL, 80, 80, -1 }, ++/*19*/ { hashHexStr80, cbc3desThenMd5digest80, iv1, 80, 80, -1 }, ++/*20*/ { hashHexStr80, cbc3desThenSha1digest80, iv1, 80, 80, -1 }, ++/*21*/ { hashHexStr80, cbcAes128ThenMd5digest80, iv5, 80, 80, -1 }, ++/*22*/ { hashHexStr80, cbcAes128ThenSha1digest80, iv5, 80, 80, -1 }, ++/*23*/ { cesaAesCtrPlain, cesaAesCtrCipher, NULL, 36, 0, -1 }, ++/*24*/ { cesaAesIvPlainText, cesaAes128IvCipherCbc, NULL, 64, 0, -1 }, ++/*25*/ { plain3des1, cipher3des1, NULL, 0, 0, -1 }, ++/*26*/ { plain3des2, cipher3desCbc2, iv3des2,0, 0, -1 }, ++/*27*/ { plain3des3, cipher3desCbc3, iv3des3,0, 0, -1 }, ++}; ++ ++ ++/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa ++ * Input 0xdd repeated "size" times ++ */ ++static MV_CESA_SIZE_TEST mdMultiSizeTest302[] = ++{ ++ { 80, "7a031a640c14a4872814930b1ef3a5b2" }, ++ { 512, "5488e6c5a14dc72a79f28312ca5b939b" }, ++ { 1000, "d00814f586a8b78a05724239d2531821" }, ++ { 1001, "bf07df7b7f49d3f5b5ecacd4e9e63281" }, ++ { 1002, "1ed4a1a802e87817a819d4e37bb4d0f7" }, ++ { 1003, "5972ab64a4f265ee371dac2f2f137f90" }, ++ { 1004, "71f95e7ec3aa7df2548e90898abdb28e" }, ++ { 1005, "e082790b4857fcfc266e92e59e608814" }, ++ { 1006, "9500f02fd8ac7fde8b10e4fece9a920d" }, ++ { 1336, "e42edcce57d0b75b01aa09d71427948b" }, ++ { 1344, "bb5454ada0deb49ba0a97ffd60f57071" }, ++ { 1399, "0f44d793e744b24d53f44f295082ee8c" }, ++ { 1400, "359de8a03a9b707928c6c60e0e8d79f1" }, ++ { 1401, "e913858b484cbe2b384099ea88d8855b" }, ++ { 1402, "d9848a164af53620e0540c1d7d87629e" }, ++ { 1403, "0c9ee1c2c9ef45e9b625c26cbaf3e822" }, ++ { 1404, "12edd4f609416e3c936170360561b064" }, ++ { 1405, "7fc912718a05446395345009132bf562" }, ++ { 1406, "882f17425e579ff0d85a91a59f308aa0" }, ++ { 1407, "005cae408630a2fb5db82ad9db7e59da" }, ++ { 1408, "64655f8b404b3fea7a3e3e609bc5088f" }, ++ { 1409, "4a145284a7f74e01b6bb1a0ec6a0dd80" }, ++ { 2048, "67caf64475650732def374ebb8bde3fd" }, ++ { 2049, "6c84f11f472825f7e6cd125c2981884b" }, ++ { 2050, "8999586754a73a99efbe4dbad2816d41" }, ++ { 2051, "ba6946b610e098d286bc81091659dfff" }, ++ { 2052, "d0afa01c92d4d13def2b024f36faed83" }, ++ { 3072, "61d8beac61806afa2585d74a9a0e6974" }, ++ { 3074, "f6501a28dcc24d1e4770505c51a87ed3" }, ++ { 3075, "ea4a6929be67e33e61ff475369248b73" }, ++ { 4048, "aa8c4d68f282a07e7385acdfa69f4bed" }, ++ { 4052, "afb5ed2c0e1d430ea59e59ed5ed6b18a" }, ++ { 4058, "9e8553f9bdd43aebe0bd729f0e600c99" }, ++ { 6144, "f628f3e5d183fe5cdd3a5abee39cf872" }, ++ { 6150, "89a3efcea9a2f25f919168ad4a1fd292" }, ++ { 6400, "cdd176b7fb747873efa4da5e32bdf88f" }, ++ { 6528, "b1d707b027354aca152c45ee559ccd3f" }, ++ { 8192, "c600ea4429ac47f9941f09182166e51a" }, ++ {16384, "16e8754bfbeb4c649218422792267a37" }, ++ {18432, "0fd0607521b0aa8b52219cfbe215f63e" }, ++ { 0, NULL }, ++}; ++ ++/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ */ ++static MV_CESA_SIZE_TEST mdMultiSizeTest304[] = ++{ ++ { 80, "a456c4723fee6068530af5a2afa71627" }, ++ { 512, "f85c2a2344f5de68b432208ad13e5794" }, ++ { 1000, "35464d6821fd4a293a41eb84e274c8c5" }, ++ { 1001, "c08eedbdce60cceb54bc2d732bb32c8b" }, ++ { 1002, "5664f71800c011cc311cb6943339c1b8" }, ++ { 1003, "779c723b044c585dc7802b13e8501bdc" }, ++ { 1004, "55e500766a2c307bc5c5fdd15e4cacd4" }, ++ { 1005, "d5f978954f5c38529d1679d2b714f068" }, ++ { 1006, "cd3efc827ce628b7281b72172693abf9" }, ++ { 1336, "6f04479910785878ae6335b8d1e87edf" }, ++ { 1344, "b6d27b50c2bce1ba2a8e1b5cc4324368" }, ++ { 1399, "65f70a1d4c86e5eaeb0704c8a7816795" }, ++ { 1400, "3394b5adc4cb3ff98843ca260a44a88a" }, ++ { 1401, "3a06f3582033a66a4e57e0603ce94e74" }, ++ { 1402, "e4d97f5ed51edc48abfa46eeb5c31752" }, ++ { 1403, "3d05e40b080ee3bedf293cb87b7140e7" }, ++ { 1404, "8cf294fc3cd153ab18dccb2a52cbf244" }, ++ { 1405, "d1487bd42f6edd9b4dab316631159221" }, ++ { 1406, "0527123b6bf6936cf5d369dc18c6c70f" }, ++ { 1407, "3224a06639db70212a0cd1ae1fcc570a" }, ++ { 1408, "a9e13335612c0356f5e2c27086e86c43" }, ++ { 1409, "a86d1f37d1ed8a3552e9a4f04dceea98" }, ++ { 2048, "396905c9b961cd0f6152abfb69c4449c" }, ++ { 2049, "49f39bff85d9dcf059fadb89efc4a70f" }, ++ { 2050, "3a2b4823bc4d0415656550226a63e34a" }, ++ { 2051, "dec60580d406c782540f398ad0bcc7e0" }, ++ { 2052, "32f76610a14310309eb748fe025081bf" }, ++ { 3072, "45edc1a42bf9d708a621076b63b774da" }, ++ { 3074, "9be1b333fe7c0c9f835fb369dc45f778" }, ++ { 3075, "8c06fcac7bd0e7b7a17fd6508c09a549" }, ++ { 4048, "0ddaef848184bf0ad98507a10f1e90e4" }, ++ { 4052, "81976bcaeb274223983996c137875cb8" }, ++ { 4058, "0b0a7a1c82bc7cbc64d8b7cd2dc2bb22" }, ++ { 6144, "1c24056f52725ede2dff0d7f9fc9855f" }, ++ { 6150, "b7f4b65681c4e43ee68ca466ca9ca4ec" }, ++ { 6400, "443bbaab9f7331ddd4bf11b659cd43c8" }, ++ { 6528, "216f44f23047cfee03a7a64f88f9a995" }, ++ { 8192, "ac7a993b2cad54879dba1bde63e39097" }, ++ { 8320, "55ed7be9682d6c0025b3221a62088d08" }, ++ {16384, "c6c722087653b62007aea668277175e5" }, ++ {18432, "f1faca8e907872c809e14ffbd85792d6" }, ++ { 0, NULL }, ++}; ++ ++/* HASH-MD5 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * repeated "size" times ++ */ ++static MV_CESA_SIZE_TEST mdMultiSizeTest305[] = ++{ ++ { 80, "57edf4a22be3c955ac49da2e2107b67a" }, ++ { 512, "c729ae8f0736cc377a9767a660eaa04e" }, ++ { 1000, "f1257a8659eb92d36fe14c6bf3852a6a" }, ++ { 1001, "f8a46fe8ea04fdc8c7de0e84042d3878" }, ++ { 1002, "da188dd67bff87d58aa3c02af2d0cc0f" }, ++ { 1003, "961753017feee04c9b93a8e51658a829" }, ++ { 1004, "dd68c4338608dcc87807a711636bf2af" }, ++ { 1005, "e338d567d3ce66bf69ada29658a8759b" }, ++ { 1006, "443c9811e8b92599b0b149e8d7ec700a" }, ++ { 1336, "89a98511706008ba4cbd0b4a24fa5646" }, ++ { 1344, "335a919805f370b9e402a62c6fe01739" }, ++ { 1399, "5d18d0eddcd84212fe28d812b5e80e3b" }, ++ { 1400, "6b695c240d2dffd0dffc99459ca76db6" }, ++ { 1401, "49590f61298a76719bc93a57a30136f5" }, ++ { 1402, "94c2999fa3ef1910a683d69b2b8476f2" }, ++ { 1403, "37073a02ab00ecba2645c57c228860db" }, ++ { 1404, "1bcd06994fce28b624f0c5fdc2dcdd2b" }, ++ { 1405, "11b93671a64c95079e8cf9e7cddc8b3d" }, ++ { 1406, "4b6695772a4c66313fa4871017d05f36" }, ++ { 1407, "d1539b97fbfda1c075624e958de19c5b" }, ++ { 1408, "b801b9b69920907cd018e8063092ede9" }, ++ { 1409, "b765f1406cfe78e238273ed01bbcaf7e" }, ++ { 2048, "1d7e2c64ac29e2b3fb4c272844ed31f5" }, ++ { 2049, "71d38fac49c6b1f4478d8d88447bcdd0" }, ++ { 2050, "141c34a5592b1bebfa731e0b23d0cdba" }, ++ { 2051, "c5e1853f21c59f5d6039bd13d4b380d8" }, ++ { 2052, "dd44a0d128b63d4b5cccd967906472d7" }, ++ { 3072, "37d158e33b21390822739d13db7b87fe" }, ++ { 3074, "aef3b209d01d39d0597fe03634bbf441" }, ++ { 3075, "335ffb428eabf210bada96d74d5a4012" }, ++ { 4048, "2434c2b43d798d2819487a886261fc64" }, ++ { 4052, "ac2fa84a8a33065b2e92e36432e861f8" }, ++ { 4058, "856781f85616c341c3533d090c1e1e84" }, ++ { 6144, "e5d134c652c18bf19833e115f7a82e9b" }, ++ { 6150, "a09a353be7795fac2401dac5601872e6" }, ++ { 6400, "08b9033ac6a1821398f50af75a2dbc83" }, ++ { 6528, "3d47aa193a8540c091e7e02f779e6751" }, ++ { 8192, "d3164e710c0626f6f395b38f20141cb7" }, ++ { 8320, "b727589d9183ff4e8491dd24466974a3" }, ++ {16384, "3f54d970793d2274d5b20d10a69938ac" }, ++ {18432, "f558511dcf81985b7a1bb57fad970531" }, ++ { 0, NULL }, ++}; ++ ++ ++/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa ++ * 0xaa, 0xaa, 0xaa, 0xaa ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ */ ++static MV_CESA_SIZE_TEST shaMultiSizeTest402[] = ++{ ++ { 80, "e812f370e659705a1649940d1f78cd7af18affd3" }, ++ { 512, "e547f886b2c15d995ed76a8a924cb408c8080f66" }, ++ { 1000, "239443194409f1a5342ecde1a092c8f3a3ed790a" }, ++ { 1001, "f278ab9a102850a9f48dc4e9e6822afe2d0c52b5" }, ++ { 1002, "8bcc667df5ab6ece988b3af361d09747c77f4e72" }, ++ { 1003, "0fae6046c7dc1d3e356b25af836f6077a363f338" }, ++ { 1004, "0ea48401cc92ae6bc92ae76685269cb0167fbe1a" }, ++ { 1005, "ecbcd7c879b295bafcd8766cbeac58cc371e31d1" }, ++ { 1006, "eb4a4a3d07d1e9a15e6f1ab8a9c47f243e27324c" }, ++ { 1336, "f5950ee1d77c10e9011d2149699c9366fe52529c" }, ++ { 1344, "b04263604a63c351b0b3b9cf1785b4bdba6c8838" }, ++ { 1399, "8cb1cff61d5b784045974a2fc69386e3b8d24218" }, ++ { 1400, "9bb2f3fcbeddb2b90f0be797cd647334a2816d51" }, ++ { 1401, "23ae462a7a0cb440f7445791079a5d75a535dd33" }, ++ { 1402, "832974b524a4d3f9cc2f45a3cabf5ccef65cd2aa" }, ++ { 1403, "d1c683742fe404c3c20d5704a5430e7832a7ec95" }, ++ { 1404, "867c79042e64f310628e219d8b85594cd0c7adc3" }, ++ { 1405, "c9d81d49d13d94358f56ccfd61af02b36c69f7c3" }, ++ { 1406, "0df43daab2786172f9b8d07d61f14a070cf1287a" }, ++ { 1407, "0fd8f3ad7f169534b274d4c66bbddd89f759e391" }, ++ { 1408, "3987511182b18473a564436003139b808fa46343" }, ++ { 1409, "ef667e063c9e9f539a8987a8d0bd3066ee85d901" }, ++ { 2048, "921109c99f3fedaca21727156d5f2b4460175327" }, ++ { 2049, "47188600dd165eb45f27c27196d3c46f4f042c1b" }, ++ { 2050, "8831939904009338de10e7fa670847041387807d" }, ++ { 2051, "2f8ebb5db2997d614e767be1050366f3641e7520" }, ++ { 2052, "669e51cd730dae158d3bef8adba075bd95a0d011" }, ++ { 3072, "cfee66cfd83abc8451af3c96c6b35a41cc6c55f5" }, ++ { 3074, "216ea26f02976a261b7d21a4dd3085157bedfabd" }, ++ { 3075, "bd612ebba021fd8e012b14c3bd60c8c5161fabc0" }, ++ { 4048, "c2564c1fdf2d5e9d7dde7aace2643428e90662e8" }, ++ { 4052, "91ce61fe924b445dfe7b5a1dcd10a27caec16df6" }, ++ { 4058, "db2a9be5ee8124f091c7ebd699266c5de223c164" }, ++ { 6144, "855109903feae2ba3a7a05a326b8a171116eb368" }, ++ { 6150, "37520bb3a668294d9c7b073e7e3daf8fee248a78" }, ++ { 6400, "60a353c841b6d2b1a05890349dad2fa33c7536b7" }, ++ { 6528, "9e53a43a69bb42d7c8522ca8bd632e421d5edb36" }, ++ { 8192, "a918cb0da862eaea0a33ee0efea50243e6b4927c" }, ++ { 8320, "29a5dcf55d1db29cd113fcf0572ae414f1c71329" }, ++ {16384, "6fb27966138e0c8d5a0d65ace817ebd53633cee1" }, ++ {18432, "ca09900d891c7c9ae2a559b10f63a217003341c1" }, ++ { 0, NULL }, ++}; ++ ++/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ */ ++static MV_CESA_SIZE_TEST shaMultiSizeTest404[] = ++{ ++ { 80, "beaf20a34b06a87558d156c0949bc3957d40222e" }, ++ { 512, "3353955358d886bc2940a3c7f337ff7dafb59c7b" }, ++ { 1000, "8737a542c5e9b2b6244b757ebb69d5bd602a829f" }, ++ { 1001, "fd9e7582d8a5d3c9fe3b923e4e6a41b07a1eb4d4" }, ++ { 1002, "a146d14a6fc3c274ff600568f4d75b977989e00d" }, ++ { 1003, "be22601bbc027ddef2dec97d30b3dc424fd803c5" }, ++ { 1004, "3e71fe99b2fe2b7bfdf4dbf0c7f3da25d7ea35e7" }, ++ { 1005, "2c422735d7295408fddd76f5e8a83a2a8da13df3" }, ++ { 1006, "6d875319049314b61855101a647b9ba3313428e6" }, ++ { 1336, "c1631ea80bad9dc43a180712461b65a0598c711c" }, ++ { 1344, "816069bf91d34581005746e2e0283d0f9c7b7605" }, ++ { 1399, "4e139866dc61cfcb8b67ca2ebd637b3a538593af" }, ++ { 1400, "ff2a0f8dd2b02c5417910f6f55d33a78e081a723" }, ++ { 1401, "ab00c12be62336964cbce31ae97fe2a0002984d5" }, ++ { 1402, "61349e7f999f3a1acc56c3e9a5060a9c4a7b05b6" }, ++ { 1403, "3edbc0f61e435bc1317fa27d840076093fb79353" }, ++ { 1404, "d052c6dfdbe63d45dab23ef9893e2aa4636aca1e" }, ++ { 1405, "0cc16b7388d67bf0add15a31e6e6c753cfae4987" }, ++ { 1406, "c96ba7eaad74253c38c22101b558d2850b1d1b90" }, ++ { 1407, "3445428a40d2c6556e7c55797ad8d323b61a48d9" }, ++ { 1408, "8d6444f937a09317c89834187b8ea9b8d3a8c56b" }, ++ { 1409, "c700acd3ecd19014ea2bdb4d42510c467e088475" }, ++ { 2048, "ee27d2a0cb77470c2f496212dfd68b5bb7b04e4b" }, ++ { 2049, "683762d7a02983b26a6d046e6451d9cd82c25932" }, ++ { 2050, "0fd20f1d55a9ee18363c2a6fd54aa13aee69992f" }, ++ { 2051, "86c267d8cc4bc8d59090e4f8b303da960fd228b7" }, ++ { 2052, "452395ae05b3ec503eea34f86fc0832485ad97c1" }, ++ { 3072, "75198e3cfd0b9bcff2dabdf8e38e6fdaa33ca49a" }, ++ { 3074, "4e24785ef080141ce4aab4675986d9acea624d7c" }, ++ { 3075, "3a20c5978dd637ec0e809bf84f0d9ccf30bc65bf" }, ++ { 4048, "3c32da256be7a7554922bf5fed51b0d2d09e59ad" }, ++ { 4052, "fff898426ea16e54325ae391a32c6c9bce4c23c0" }, ++ { 4058, "c800b9e562e1c91e1310116341a3c91d37f848ec" }, ++ { 6144, "d91d509d0cc4376c2d05bf9a5097717a373530e6" }, ++ { 6150, "d957030e0f13c5df07d9eec298542d8f94a07f12" }, ++ { 6400, "bb745313c3d7dc17b3f955e5534ad500a1082613" }, ++ { 6528, "77905f80d9ca82080bbb3e5654896dabfcfd1bdb" }, ++ { 8192, "5237fd9a81830c974396f99f32047586612ff3c0" }, ++ { 8320, "57668e28d5f2dba0839518a11db0f6af3d7e08bf" }, ++ {16384, "62e093fde467f0748087beea32e9af97d5c61241" }, ++ {18432, "845fb33130c7d6ea554fd5aacb9c50cf7ccb5929" }, ++ { 0, NULL }, ++}; ++ ++/* HASH-SHA1 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * repeated "size" times ++ */ ++static MV_CESA_SIZE_TEST shaMultiSizeTest405[] = ++{ ++ { 80, "50abf5706a150990a08b2c5ea40fa0e585554732" }, ++ { 512, "f14516a08948fa27917a974d219741a697ba0087" }, ++ { 1000, "0bd18c378d5788817eb4f1e5dc07d867efa5cbf4" }, ++ { 1001, "ca29b85c35db1b8aef83c977893a11159d1b7aa2" }, ++ { 1002, "d83bc973eaaedb8a31437994dabbb3304b0be086" }, ++ { 1003, "2cf7bbef0acd6c00536b5c58ca470df9a3a90b6c" }, ++ { 1004, "e4375d09b1223385a8a393066f8209acfd936a80" }, ++ { 1005, "1029b38043e027745d019ce1d2d68e3d8b9d8f99" }, ++ { 1006, "deea16dcebbd8ac137e2b984deb639b9fb5e9680" }, ++ { 1336, "ea031b065fff63dcfb6a41956e4777520cdbc55d" }, ++ { 1344, "b52096c6445e6c0a8355995c70dc36ae186c863c" }, ++ { 1399, "cde2f6f8379870db4b32cf17471dc828a8dbff2b" }, ++ { 1400, "e53ff664064bc09fe5054c650806bd42d8179518" }, ++ { 1401, "d1156db5ddafcace64cdb510ff0d4af9b9a8ad64" }, ++ { 1402, "34ede0e9a909dd84a2ae291539105c0507b958e1" }, ++ { 1403, "a772ca3536da77e6ad3251e4f9e1234a4d7b87c0" }, ++ { 1404, "29740fd2b04e7a8bfd32242db6233156ad699948" }, ++ { 1405, "65b17397495b70ce4865dad93bf991b74c97cce1" }, ++ { 1406, "a7ee89cd0754061fdb91af7ea6abad2c69d542e3" }, ++ { 1407, "3eebf82f7420188e23d328b7ce93580b279a5715" }, ++ { 1408, "e08d3363a8b9a490dfb3a4c453452b8f114deeec" }, ++ { 1409, "95d74df739181a4ff30b8c39e28793a36598e924" }, ++ { 2048, "aa40262509c2abf84aab0197f83187fc90056d91" }, ++ { 2049, "7dec28ef105bc313bade8d9a7cdeac58b99de5ea" }, ++ { 2050, "d2e30f77ec81197de20f56588a156094ecb88450" }, ++ { 2051, "6b22ccc874833e96551a39da0c0edcaa0d969d92" }, ++ { 2052, "f843141e57875cd669af58744bc60aa9ea59549c" }, ++ { 3072, "09c5fedeaa62c132e673cc3c608a00142273d086" }, ++ { 3074, "b09e95eea9c7b1b007a58accec488301901a7f3d" }, ++ { 3075, "e6226b77b4ada287a8c9bbcf4ed71eec5ce632dc" }, ++ { 4048, "e99394894f855821951ddddf5bfc628547435f5c" }, ++ { 4052, "32d2f1af38be9cfba6cd03d55a254d0b3e1eb382" }, ++ { 4058, "d906552a4f2aca3a22e1fecccbcd183d7289d0ef" }, ++ { 6144, "2e7f62d35a860988e1224dc0543204af19316041" }, ++ { 6150, "d6b89698ee133df46fec9d552fadc328aa5a1b51" }, ++ { 6400, "dff50e90c46853988fa3a4b4ce5dda6945aae976" }, ++ { 6528, "9e63ec0430b96db02d38bc78357a2f63de2ab7f8" }, ++ { 8192, "971eb71ed60394d5ab5abb12e88420bdd41b5992" }, ++ { 8320, "91606a31b46afeaac965cecf87297e791b211013" }, ++ {16384, "547f830a5ec1f5f170ce818f156b1002cabc7569" }, ++ {18432, "f16f272787f3b8d539652e4dc315af6ab4fda0ef" }, ++ { 0, NULL }, ++}; ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST tripleDesMdMultiSizeTest502[] = ++{ ++ { 64, "9586962a2aaaef28803dec2e17807a7f" }, ++ { 80, "b7726a03aad490bd6c5a452a89a1b271" }, ++ { 352, "f1ed9563aecc3c0d2766eb2bed3b4e4c" }, ++ { 512, "0f9decb11ab40fe86f4d4d9397bc020e" }, ++ { 1000, "3ba69deac12cab8ff9dff7dbd9669927" }, ++ { 1336, "6cf47bf1e80e03e2c1d0945bc50d37d2" }, ++ { 1344, "4be388dab21ceb3fa1b8d302e9b821f7" }, ++ { 1400, "a58b79fb21dd9bfc6ec93e3b99fb0ef1" }, ++ { 1408, "8bc97379fc2ac3237effcdd4f7a86528" }, ++ { 2048, "1339f03ab3076f25a20bc4cba16eb5bf" }, ++ { 3072, "731204d2d90c4b36ae41f5e1fb874288" }, ++ { 4048, "c028d998cfda5642547b7e1ed5ea16e4" }, ++ { 6144, "b1b19cd910cc51bd22992f1e59f1e068" }, ++ { 6400, "44e4613496ba622deb0e7cb768135a2f" }, ++ { 6528, "3b06b0a86f8db9cd67f9448dfcf10549" }, ++ { 8192, "d581780b7163138a0f412be681457d82" }, ++ {16384, "03b8ac05527faaf1bed03df149c65ccf" }, ++ {18432, "677c8a86a41dab6c5d81b85b8fb10ff6" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST tripleDesShaMultiSizeTest503[] = ++{ ++ { 64, "44a1e9bcbfc1429630d9ea68b7a48b0427a684f2" }, ++ { 80, "b2ddeaca91030eab5b95a234ef2c0f6e738ff883" }, ++ { 352, "4b91864c7ff629bdff75d9726421f76705452aaf" }, ++ { 512, "6dd37faceeb2aa98ba74f4242ed6734a4d546af5" }, ++ { 1000, "463661c30300be512a9df40904f0757cde5f1141" }, ++ { 1336, "b931f831d9034fe59c65176400b039fe9c1f44a5" }, ++ { 1344, "af8866b1cd4a4887d6185bfe72470ffdfb3648e1" }, ++ { 1400, "49c6caf07296d5e31d2504d088bc5b20c3ee7cdb" }, ++ { 1408, "fcae8deedbc6ebf0763575dc7e9de075b448a0f4" }, ++ { 2048, "edece5012146c1faa0dd10f50b183ba5d2af58ac" }, ++ { 3072, "5b83625adb43a488b8d64fecf39bb766818547b7" }, ++ { 4048, "d2c533678d26c970293af60f14c8279dc708bfc9" }, ++ { 6144, "b8f67af4f991b08b725f969b049ebf813bfacc5c" }, ++ { 6400, "d9a6c7f746ac7a60ef2edbed2841cf851c25cfb0" }, ++ { 6528, "376792b8c8d18161d15579fb7829e6e3a27e9946" }, ++ { 8192, "d890eabdca195b34ef8724b28360cffa92ae5655" }, ++ {16384, "a167ee52639ec7bf19aee9c6e8f76667c14134b9" }, ++ {18432, "e4396ab56f67296b220985a12078f4a0e365d2cc" }, ++ { 0, NULL }, ++}; ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbc3desMdMultiSizeTest504[] = ++{ ++ { 64, "8d10e00802460ede0058c139ba48bd2d" }, ++ { 80, "6f463057e1a90e0e91ae505b527bcec0" }, ++ { 352, "4938d48bdf86aece2c6851e7c6079788" }, ++ { 512, "516705d59f3cf810ebf2a13a23a7d42e" }, ++ { 1000, "a5a000ee5c830e67ddc6a2d2e5644b31" }, ++ { 1336, "44af60087b74ed07950088efbe3b126a" }, ++ { 1344, "1f5b39e0577920af731dabbfcf6dfc2a" }, ++ { 1400, "6804ea640e29b9cd39e08bc37dbce734" }, ++ { 1408, "4fb436624b02516fc9d1535466574bf9" }, ++ { 2048, "c909b0985c423d8d86719f701e9e83db" }, ++ { 3072, "cfe0bc34ef97213ee3d3f8b10122db21" }, ++ { 4048, "03ea10b5ae4ddeb20aed6af373082ed1" }, ++ { 6144, "b9a0ff4f87fc14b3c2dc6f0ed0998fdf" }, ++ { 6400, "6995f85d9d4985dd99e974ec7dda9dd6" }, ++ { 6528, "bbbb548ce2fa3d58467f6a6a5168a0e6" }, ++ { 8192, "afe101fbe745bb449ae4f50d10801456" }, ++ {16384, "9741706d0b1c923340c4660ff97cacdf" }, ++ {18432, "b0217becb73cb8f61fd79c7ce9d023fb" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbc3desShaMultiSizeTest505[] = ++{ ++ { 64, "409187e5bdb0be4a7754ca3747f7433dc4f01b98" }, ++ { 80, "1b002ed050be743aa98860cf35659646bb8efcc0" }, ++ { 352, "6cbf7ebe50fa4fa6eecc19eca23f9eae553ccfff" }, ++ { 512, "cfb5253fb4bf72b743320c30c7e48c54965853b0" }, ++ { 1000, "95e04e1ca2937e7c5a9aba9e42d2bcdb8a7af21f" }, ++ { 1336, "3b5c1f5eee5837ebf67b83ae01405542d77a6627" }, ++ { 1344, "2b3d42ab25615437f98a1ee310b81d07a02badc2" }, ++ { 1400, "7f8687df7c1af44e4baf3c934b6cca5ab6bc993e" }, ++ { 1408, "473a581c5f04f7527d50793c845471ac87e86430" }, ++ { 2048, "e41d20cae7ebe34e6e828ed62b1e5734019037bb" }, ++ { 3072, "275664afd7a561d804e6b0d204e53939cde653ae" }, ++ { 4048, "0d220cc5b34aeeb46bbbd637dde6290b5a8285a3" }, ++ { 6144, "cb393ddcc8b1c206060625b7d822ef9839e67bc5" }, ++ { 6400, "dd3317e2a627fc04800f74a4b05bfda00fab0347" }, ++ { 6528, "8a74c3b2441ab3f5a7e08895cc432566219a7c41" }, ++ { 8192, "b8e6ef3a549ed0e005bd5b8b1a5fe6689e9711a7" }, ++ {16384, "55f59404008276cdac0e2ba0d193af2d40eac5ce" }, ++ {18432, "86ae6c4fc72369a54cce39938e2d0296cd9c6ec5" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to AES block size (16 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbcAes128md5multiSizeTest506[] = ++{ ++ { 16, "7ca4c2ba866751598720c5c4aa0d6786" }, ++ { 64, "7dba7fb988e80da609b1fea7254bced8" }, ++ { 80, "6b6e863ac5a71d15e3e9b1c86c9ba05f" }, ++ { 352, "a1ceb9c2e3021002400d525187a9f38c" }, ++ { 512, "596c055c1c55db748379223164075641" }, ++ { 1008, "f920989c02f3b3603f53c99d89492377" }, ++ { 1344, "2e496b73759d77ed32ea222dbd2e7b41" }, ++ { 1408, "7178c046b3a8d772efdb6a71c4991ea4" }, ++ { 2048, "a917f0099c69eb94079a8421714b6aad" }, ++ { 3072, "693cd5033d7f5391d3c958519fa9e934" }, ++ { 4048, "139dca91bcff65b3c40771749052906b" }, ++ { 6144, "428d9cef6df4fb70a6e9b6bbe4819e55" }, ++ { 6400, "9c0b909e76daa811e12b1fc17000a0c4" }, ++ { 6528, "ad876f6297186a7be1f1b907ed860eda" }, ++ { 8192, "479cbbaca37dd3191ea1f3e8134a0ef4" }, ++ {16384, "60fda559c74f91df538100c9842f2f15" }, ++ {18432, "4a3eb1cba1fa45f3981270953f720c42" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to AES block size (16 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbcAes128sha1multiSizeTest507[] = ++{ ++ { 16, "9aa8dc1c45f0946daf78057fa978759c625c1fee" }, ++ { 64, "9f588fc1ede851e5f8b20256abc9979465ae2189" }, ++ { 80, "13558472d1fc1c90dffec6e5136c7203452d509b" }, ++ { 352, "6b93518e006cfaa1f7adb24615e7291fb0a27e06" }, ++ { 512, "096874951a77fbbf333e49d80c096ee2016e09bd" }, ++ { 1008, "696fc203c2e4b5ae0ec5d1db3f623c490bc6dbac" }, ++ { 1344, "79bf77509935ccd3528caaac6a5eb6481f74029b" }, ++ { 1408, "627f9462b95fc188e8cfa7eec15119bdc5d4fcf1" }, ++ { 2048, "3d50d0c005feba92fe41502d609fced9c882b4d1" }, ++ { 3072, "758807e5b983e3a91c06fb218fe0f73f77111e94" }, ++ { 4048, "ca90e85242e33f005da3504416a52098d0d31fb2" }, ++ { 6144, "8044c1d4fd06642dfc46990b4f18b61ef1e972cf" }, ++ { 6400, "166f1f4ea57409f04feba9fb1e39af0e00bd6f43" }, ++ { 6528, "0389016a39485d6e330f8b4215ddf718b404f7e9" }, ++ { 8192, "6df7ee2a8b61d6f7f860ce8dbf778f0c2a5b508b" }, ++ {16384, "a70a6d8dfa1f91ded621c3dbaed34162bc48783f" }, ++ {18432, "8dfad627922ce15df1eed10bdbed49244efa57db" }, ++ { 0, NULL }, ++}; ++ ++ ++void cesaTestPrintStatus(void); ++ ++ ++/*------------------------- LOCAL FUNCTIONs ---------------------------------*/ ++MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, ++ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize); ++MV_STATUS testClose(int idx); ++MV_STATUS testOpen(int idx); ++void close_session(int sid); ++void cesaTestCheckReady(const MV_CESA_RESULT *r); ++void cesaCheckReady(MV_CESA_RESULT* r); ++void printTestResults(int idx, MV_STATUS status, int checkMode); ++void cesaLastResult(void); ++void cesaTestPrintReq(int req, int offset, int size); ++ ++void cesaTestPrintStatus(void); ++void cesaTestPrintSession(int idx); ++void sizeTest(int testIdx, int iter, int checkMode); ++void multiTest(int iter, int reqSize, int checkMode); ++void oneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); ++void multiSizeTest(int idx, int iter, int checkMode, char* inputData); ++void cesaTest(int iter, int reqSize, int checkMode); ++void cesaOneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); ++void combiTest(int iter, int reqSize, int checkMode); ++void shaTest(int iter, int reqSize, int checkMode); ++void mdTest(int iter, int reqSize, int checkMode); ++void aesTest(int iter, int reqSize, int checkMode); ++void tripleDesTest(int iter, int reqSize, int checkMode); ++void desTest(int iter, int reqSize, int checkMode); ++void cesaTestStop(void); ++MV_STATUS testRun(int idx, int caseIdx, int iter,int reqSize, int checkMode); ++void cesaTestStart(int bufNum, int bufSize); ++ ++ ++static MV_U32 getRate(MV_U32* remainder) ++{ ++ MV_U32 kBits, milliSec, rate; ++ ++ milliSec = 0; ++ if( (cesaEndTicks - cesaBeginTicks) > 0) ++ { ++ milliSec = CESA_TEST_TICK_TO_MS(cesaEndTicks - cesaBeginTicks); ++ } ++ if(milliSec == 0) ++ { ++ if(remainder != NULL) ++ *remainder = 0; ++ return 0; ++ } ++ ++ kBits = (cesaIteration*cesaRateSize*8)/1000; ++ rate = kBits/milliSec; ++ if(remainder != NULL) ++ *remainder = ((kBits % milliSec)*10)/milliSec; ++ ++ return rate; ++} ++ ++static char* extractMbuf(MV_CESA_MBUF *pMbuf, ++ int offset, int size, char* hexStr) ++{ ++ mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, size); ++ mvBinToHex((const MV_U8*)cesaBinBuffer, hexStr, size); ++ ++ return hexStr; ++} ++ ++static MV_BOOL cesaCheckMbuf(MV_CESA_MBUF *pMbuf, ++ const char* hexString, int offset, ++ int checkSize) ++{ ++ MV_BOOL isFailed = MV_FALSE; ++ MV_STATUS status; ++ int size = strlen(hexString)/2; ++ int checkedSize = 0; ++/* ++ mvOsPrintf("cesaCheckMbuf: pMbuf=%p, offset=%d, checkSize=%d, mBufSize=%d\n", ++ pMbuf, offset, checkSize, pMbuf->mbufSize); ++*/ ++ if(pMbuf->mbufSize < (checkSize + offset)) ++ { ++ mvOsPrintf("checkSize (%d) is too large: offset=%d, mbufSize=%d\n", ++ checkSize, offset, pMbuf->mbufSize); ++ return MV_TRUE; ++ } ++ status = mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, checkSize); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaTest: Can't copy %d bytes from Mbuf=%p to checkBuf=%p\n", ++ checkSize, pMbuf, cesaBinBuffer); ++ return MV_TRUE; ++ } ++/* ++ mvDebugMemDump(cesaBinBuffer, size, 1); ++*/ ++ mvHexToBin(hexString, (MV_U8*)cesaExpBinBuffer, size); ++ ++ /* Compare buffers */ ++ while(checkSize > checkedSize) ++ { ++ size = MV_MIN(size, (checkSize - checkedSize)); ++ if(memcmp(cesaExpBinBuffer, &cesaBinBuffer[checkedSize], size) != 0) ++ { ++ mvOsPrintf("CheckMbuf failed: checkSize=%d, size=%d, checkedSize=%d\n", ++ checkSize, size, checkedSize); ++ mvDebugMemDump(&cesaBinBuffer[checkedSize], size, 1); ++ mvDebugMemDump(cesaExpBinBuffer, size, 1); ++ ++ isFailed = MV_TRUE; ++ break; ++ } ++ checkedSize += size; ++ } ++ ++ return isFailed; ++} ++ ++static MV_STATUS cesaSetMbuf(MV_CESA_MBUF *pMbuf, ++ const char* hexString, ++ int offset, int reqSize) ++{ ++ MV_STATUS status = MV_OK; ++ int copySize, size = strlen(hexString)/2; ++ ++ mvHexToBin(hexString, (MV_U8*)cesaBinBuffer, size); ++ ++ copySize = 0; ++ while(reqSize > copySize) ++ { ++ size = MV_MIN(size, (reqSize - copySize)); ++ ++ status = mvCesaCopyToMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset+copySize, size); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("cesaSetMbuf Error: Copy %d of %d bytes to MBuf\n", ++ copySize, reqSize); ++ break; ++ } ++ copySize += size; ++ } ++ pMbuf->mbufSize = offset+copySize; ++ return status; ++} ++ ++static MV_CESA_TEST_SESSION* getTestSessionDb(int idx, int* pTestIdx) ++{ ++ int testIdx, dbIdx = idx/100; ++ ++ if(dbIdx > MAX_TEST_TYPE) ++ { ++ mvOsPrintf("Wrong index %d - No such test type\n", idx); ++ return NULL; ++ } ++ testIdx = idx % 100; ++ ++ if(testIdx >= cesaTestsDB[dbIdx].numSessions) ++ { ++ mvOsPrintf("Wrong index %d - No such test\n", idx); ++ return NULL; ++ } ++ if(pTestIdx != NULL) ++ *pTestIdx = testIdx; ++ ++ return cesaTestsDB[dbIdx].pSessions; ++} ++ ++/* Debug */ ++void cesaTestPrintReq(int req, int offset, int size) ++{ ++ MV_CESA_MBUF* pMbuf; ++ ++ mvOsPrintf("cesaTestPrintReq: req=%d, offset=%d, size=%d\n", ++ req, offset, size); ++ mvDebugMemDump(cesaCmdRing, 128, 4); ++ ++ pMbuf = cesaCmdRing[req].pSrc; ++ mvCesaDebugMbuf("src", pMbuf, offset,size); ++ pMbuf = cesaCmdRing[req].pDst; ++ mvCesaDebugMbuf("dst", pMbuf, offset, size); ++ ++ cesaTestPrintStatus(); ++} ++ ++void cesaLastResult(void) ++{ ++ mvOsPrintf("Last Result: ReqId = %d, SessionId = %d, rc = (%d)\n", ++ (MV_U32)cesaResult.pReqPrv, cesaResult.sessionId, ++ cesaResult.retCode); ++} ++ ++void printTestResults(int idx, MV_STATUS status, int checkMode) ++{ ++ int testIdx; ++ MV_CESA_TEST_SESSION* pTestSessions = getTestSessionDb(idx, &testIdx); ++ ++ if(pTestSessions == NULL) ++ return; ++ ++ mvOsPrintf("%-35s %4dx%-4d : ", pTestSessions[testIdx].name, ++ cesaIteration, cesaReqSize); ++ if( (status == MV_OK) && ++ (cesaCryptoError == 0) && ++ (cesaError == 0) && ++ (cesaReqIdError == 0) ) ++ { ++ mvOsPrintf("Passed, Rate=%3u.%u Mbps (%5u cpp)\n", ++ cesaRate, cesaRateAfterDot, cesaEndTicks - cesaBeginTicks); ++ } ++ else ++ { ++ mvOsPrintf("Failed, Status = 0x%x\n", status); ++ if(cesaCryptoError > 0) ++ mvOsPrintf("cryptoError : %d\n", cesaCryptoError); ++ if(cesaReqIdError > 0) ++ mvOsPrintf("reqIdError : %d\n", cesaReqIdError); ++ if(cesaError > 0) ++ mvOsPrintf("cesaError : %d\n", cesaError); ++ } ++ if(cesaTestIsrMissCount > 0) ++ mvOsPrintf("cesaIsrMissed : %d\n", cesaTestIsrMissCount); ++} ++ ++void cesaCheckReady(MV_CESA_RESULT* r) ++{ ++ int reqId; ++ MV_CESA_MBUF *pMbuf; ++ MV_BOOL isFailed; ++ ++ cesaResult = *r; ++ reqId = (int)cesaResult.pReqPrv; ++ pMbuf = cesaCmdRing[reqId].pDst; ++ ++/* ++ mvOsPrintf("cesaCheckReady: reqId=%d, checkOffset=%d, checkSize=%d\n", ++ reqId, cesaCheckOffset, cesaCheckSize); ++*/ ++ /* Check expected reqId */ ++ if(reqId != cesaExpReqId) ++ { ++ cesaReqIdError++; ++/* ++ mvOsPrintf("CESA reqId Error: cbIter=%d (%d), reqId=%d, expReqId=%d\n", ++ cesaCbIter, cesaIteration, reqId, cesaExpReqId); ++*/ ++ } ++ else ++ { ++ if( (cesaCheckMode == CESA_FULL_CHECK_MODE) || ++ (cesaCheckMode == CESA_FAST_CHECK_MODE) ) ++ { ++ if(cesaResult.retCode != MV_OK) ++ { ++ cesaError++; ++ ++ mvOsPrintf("CESA Error: cbIter=%d (%d), reqId=%d, rc=%d\n", ++ cesaCbIter, cesaIteration, reqId, cesaResult.retCode); ++ } ++ else ++ { ++ if( (cesaCheckSize > 0) && (cesaOutputHexStr != NULL) ) ++ { ++ /* Check expected output */ ++ ++ isFailed = cesaCheckMbuf(pMbuf, cesaOutputHexStr, cesaCheckOffset, cesaCheckSize); ++ if(isFailed) ++ { ++ mvOsPrintf("CESA Crypto Error: cbIter=%d (%d), reqId=%d\n", ++ cesaCbIter, cesaIteration, reqId); ++ ++ CESA_TEST_DEBUG_PRINT(("Error: reqId=%d, reqSize=%d, checkOffset=%d, checkSize=%d\n", ++ reqId, cesaReqSize, cesaCheckOffset, cesaCheckSize)); ++ ++ CESA_TEST_DEBUG_PRINT(("Output str: %s\n", cesaOutputHexStr)); ++ ++ CESA_TEST_DEBUG_CODE( mvCesaDebugMbuf("error", pMbuf, 0, cesaCheckOffset+cesaCheckSize) ); ++ ++ cesaCryptoError++; ++ } ++ } ++ } ++ } ++ } ++ if(cesaCheckMode == CESA_SHOW_CHECK_MODE) ++ { ++ extractMbuf(pMbuf, cesaCheckOffset, cesaCheckSize, cesaHexBuffer); ++ mvOsPrintf("%4d, %s\n", cesaCheckOffset, cesaHexBuffer); ++ } ++ ++ cesaCbIter++; ++ if(cesaCbIter >= cesaIteration) ++ { ++ cesaCbIter = 0; ++ cesaExpReqId = 0; ++ cesaIsReady = MV_TRUE; ++ ++ cesaEndTicks = CESA_TEST_TICK_GET(); ++ cesaRate = getRate(&cesaRateAfterDot); ++ } ++ else ++ { ++ cesaExpReqId = reqId + 1; ++ if(cesaExpReqId == CESA_DEF_REQ_SIZE) ++ cesaExpReqId = 0; ++ } ++} ++ ++ ++#ifdef MV_NETBSD ++static int cesaTestReadyIsr(void *arg) ++#else ++#ifdef __KERNEL__ ++static irqreturn_t cesaTestReadyIsr( int irq , void *dev_id) ++#endif ++#ifdef MV_VXWORKS ++void cesaTestReadyIsr(void) ++#endif ++#endif ++{ ++ MV_U32 cause; ++ MV_STATUS status; ++ MV_CESA_RESULT result; ++ ++ cesaTestIsrCount++; ++ /* Clear cause register */ ++ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) ++ { ++ mvOsPrintf("cesaTestReadyIsr: cause=0x%x\n", cause); ++#ifdef MV_NETBSD ++ return 0; ++#else ++#ifdef __KERNEL__ ++ return 1; ++#else ++ return; ++#endif ++#endif ++ } ++ ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++ ++ while(MV_TRUE) ++ { ++ /* Get Ready requests */ ++ status = mvCesaReadyGet(&result); ++ if(status == MV_OK) ++ cesaCheckReady(&result); ++ ++ break; ++ } ++ if( (cesaTestFull == 1) && (status != MV_BUSY) ) ++ { ++ cesaTestFull = 0; ++ CESA_TEST_WAKE_UP(); ++ } ++ ++#ifdef __KERNEL__ ++ return 1; ++#endif ++} ++ ++void ++cesaTestCheckReady(const MV_CESA_RESULT *r) ++{ ++ MV_CESA_RESULT result = *r; ++ ++ cesaCheckReady(&result); ++ ++ if (cesaTestFull == 1) { ++ cesaTestFull = 0; ++ CESA_TEST_WAKE_UP(); ++ } ++} ++ ++static INLINE int open_session(MV_CESA_OPEN_SESSION* pOs) ++{ ++ MV_U16 sid; ++ MV_STATUS status; ++ ++ status = mvCesaSessionOpen(pOs, (short*)&sid); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaTest: Can't open new session - status = 0x%x\n", ++ status); ++ return -1; ++ } ++ ++ return (int)sid; ++} ++ ++void close_session(int sid) ++{ ++ MV_STATUS status; ++ ++ status = mvCesaSessionClose(sid); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaTest: Can't close session %d - status = 0x%x\n", ++ sid, status); ++ } ++} ++ ++MV_STATUS testOpen(int idx) ++{ ++ MV_CESA_OPEN_SESSION os; ++ int sid, i, testIdx; ++ MV_CESA_TEST_SESSION* pTestSession; ++ MV_U16 digestSize = 0; ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return MV_BAD_PARAM; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ if(pTestSession->sid != -1) ++ { ++ mvOsPrintf("Session for test %d already created: sid=%d\n", ++ idx, pTestSession->sid); ++ return MV_OK; ++ } ++ ++ os.cryptoAlgorithm = pTestSession->cryptoAlgorithm; ++ os.macMode = pTestSession->macAlgorithm; ++ switch(os.macMode) ++ { ++ case MV_CESA_MAC_MD5: ++ case MV_CESA_MAC_HMAC_MD5: ++ digestSize = MV_CESA_MD5_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_SHA1: ++ case MV_CESA_MAC_HMAC_SHA1: ++ digestSize = MV_CESA_SHA1_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_NULL: ++ digestSize = 0; ++ } ++ os.cryptoMode = pTestSession->cryptoMode; ++ os.direction = pTestSession->direction; ++ os.operation = pTestSession->operation; ++ ++ for(i=0; icryptoKeySize; i++) ++ os.cryptoKey[i] = pTestSession->pCryptoKey[i]; ++ ++ os.cryptoKeyLength = pTestSession->cryptoKeySize; ++ ++ for(i=0; imacKeySize; i++) ++ os.macKey[i] = pTestSession->pMacKey[i]; ++ ++ os.macKeyLength = pTestSession->macKeySize; ++ os.digestSize = digestSize; ++ ++ sid = open_session(&os); ++ if(sid == -1) ++ { ++ mvOsPrintf("Can't open session for test %d: rc=0x%x\n", ++ idx, cesaResult.retCode); ++ return cesaResult.retCode; ++ } ++ CESA_TEST_DEBUG_PRINT(("Opened session: sid = %d\n", sid)); ++ pTestSession->sid = sid; ++ return MV_OK; ++} ++ ++MV_STATUS testClose(int idx) ++{ ++ int testIdx; ++ MV_CESA_TEST_SESSION* pTestSession; ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return MV_BAD_PARAM; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ if(pTestSession->sid == -1) ++ { ++ mvOsPrintf("Test session %d is not opened\n", idx); ++ return MV_NO_SUCH; ++ } ++ ++ close_session(pTestSession->sid); ++ pTestSession->sid = -1; ++ ++ return MV_OK; ++} ++ ++MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, ++ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize) ++{ ++ int cmdReqId = 0; ++ int i; ++ MV_STATUS rc = MV_OK; ++ char ivZeroHex[] = "0000"; ++ ++ if(iter == 0) ++ iter = CESA_DEF_ITER_NUM; ++ ++ if(pCmd == NULL) ++ { ++ mvOsPrintf("testCmd failed: pCmd=NULL\n"); ++ return MV_BAD_PARAM; ++ } ++ pCmd->sessionId = sid; ++ ++ cesaCryptoError = 0; ++ cesaReqIdError = 0; ++ cesaError = 0; ++ cesaTestIsrMissCount = 0; ++ cesaIsReady = MV_FALSE; ++ cesaIteration = iter; ++ ++ if(cesaInputHexStr == NULL) ++ cesaInputHexStr = cesaPlainHexEbc; ++ ++ for(i=0; ipSrc = (MV_CESA_MBUF*)(cesaCmdRing[i].pSrc); ++ if(pIV != NULL) ++ { ++ /* If IV from SA - set IV in Source buffer to zeros */ ++ cesaSetMbuf(pCmd->pSrc, ivZeroHex, 0, pCmd->cryptoOffset); ++ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, pCmd->cryptoOffset, ++ (cesaReqSize - pCmd->cryptoOffset)); ++ } ++ else ++ { ++ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, 0, cesaReqSize); ++ } ++ pCmd->pDst = (MV_CESA_MBUF*)(cesaCmdRing[i].pDst); ++ cesaSetMbuf(pCmd->pDst, cesaNullPlainHexText, 0, cesaReqSize); ++ ++ memcpy(&cesaCmdRing[i], pCmd, sizeof(*pCmd)); ++ } ++ ++ if(cesaCheckMode == CESA_SW_SHOW_CHECK_MODE) ++ { ++ MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; ++ ++ if(pTestSession->macAlgorithm == MV_CESA_MAC_MD5) ++ { ++ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); ++ mvOsPrintf("SW HASH_MD5: reqSize=%d, macLength=%d\n", ++ cesaReqSize, pCmd->macLength); ++ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); ++ return MV_OK; ++ } ++ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) ++ { ++ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); ++ mvOsPrintf("SW HASH_SHA1: reqSize=%d, macLength=%d\n", ++ cesaReqSize, pCmd->macLength); ++ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); ++ return MV_OK; ++ } ++ } ++ ++ cesaBeginTicks = CESA_TEST_TICK_GET(); ++ CESA_TEST_DEBUG_CODE( memset(cesaTestTrace, 0, sizeof(cesaTestTrace)); ++ cesaTestTraceIdx = 0; ++ ); ++ ++ if(cesaCheckMode == CESA_SW_NULL_CHECK_MODE) ++ { ++ volatile MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; ++ ++ for(i=0; imacAlgorithm == MV_CESA_MAC_MD5) ++ { ++ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (unsigned char*)pDigest); ++ } ++ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) ++ { ++ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (MV_U8 *)pDigest); ++ } ++ } ++ cesaEndTicks = CESA_TEST_TICK_GET(); ++ cesaRate = getRate(&cesaRateAfterDot); ++ cesaIsReady = MV_TRUE; ++ ++ return MV_OK; ++ } ++ ++ /*cesaTestIsrCount = 0;*/ ++ /*mvCesaDebugStatsClear();*/ ++ ++#ifndef MV_NETBSD ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++#endif ++ ++ for(i=0; ipReqPrv = (void*)cmdReqId; ++ ++ CESA_TEST_LOCK(flags); ++ ++ rc = mvCesaAction(pCmd); ++ if(rc == MV_NO_RESOURCE) ++ cesaTestFull = 1; ++ ++ CESA_TEST_UNLOCK(flags); ++ ++ if(rc == MV_NO_RESOURCE) ++ { ++ CESA_TEST_LOCK(flags); ++ CESA_TEST_WAIT( (cesaTestFull == 0), 100); ++ CESA_TEST_UNLOCK(flags); ++ if(cesaTestFull == 1) ++ { ++ mvOsPrintf("CESA Test timeout: i=%d, iter=%d, cesaTestFull=%d\n", ++ i, iter, cesaTestFull); ++ cesaTestFull = 0; ++ return MV_TIMEOUT; ++ } ++ ++ CESA_TEST_LOCK(flags); ++ ++ rc = mvCesaAction(pCmd); ++ ++ CESA_TEST_UNLOCK(flags); ++ } ++ if( (rc != MV_OK) && (rc != MV_NO_MORE) ) ++ { ++ mvOsPrintf("mvCesaAction failed: rc=%d\n", rc); ++ return rc; ++ } ++ ++ cmdReqId++; ++ if(cmdReqId >= CESA_DEF_REQ_SIZE) ++ cmdReqId = 0; ++ ++#ifdef MV_LINUX ++ /* Reschedule each 16 requests */ ++ if( (i & 0xF) == 0) ++ schedule(); ++#endif ++ } ++ return MV_OK; ++} ++ ++void cesaTestStart(int bufNum, int bufSize) ++{ ++ int i, j, idx; ++ MV_CESA_MBUF *pMbufSrc, *pMbufDst; ++ MV_BUF_INFO *pFragsSrc, *pFragsDst; ++ char *pBuf; ++#ifndef MV_NETBSD ++ int numOfSessions, queueDepth; ++ char *pSram; ++ MV_STATUS status; ++ MV_CPU_DEC_WIN addrDecWin; ++#endif ++ ++ cesaCmdRing = mvOsMalloc(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); ++ if(cesaCmdRing == NULL) ++ { ++ mvOsPrintf("testStart: Can't allocate %ld bytes of memory\n", ++ sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); ++ return; ++ } ++ memset(cesaCmdRing, 0, sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); ++ ++ if(bufNum == 0) ++ bufNum = CESA_DEF_BUF_NUM; ++ ++ if(bufSize == 0) ++ bufSize = CESA_DEF_BUF_SIZE; ++ ++ cesaBufNum = bufNum; ++ cesaBufSize = bufSize; ++ mvOsPrintf("CESA test started: bufNum = %d, bufSize = %d\n", ++ bufNum, bufSize); ++ ++ cesaHexBuffer = mvOsMalloc(2*bufNum*bufSize); ++ if(cesaHexBuffer == NULL) ++ { ++ mvOsPrintf("testStart: Can't malloc %d bytes for cesaHexBuffer.\n", ++ 2*bufNum*bufSize); ++ return; ++ } ++ memset(cesaHexBuffer, 0, (2*bufNum*bufSize)); ++ ++ cesaBinBuffer = mvOsMalloc(bufNum*bufSize); ++ if(cesaBinBuffer == NULL) ++ { ++ mvOsPrintf("testStart: Can't malloc %d bytes for cesaBinBuffer\n", ++ bufNum*bufSize); ++ return; ++ } ++ memset(cesaBinBuffer, 0, (bufNum*bufSize)); ++ ++ cesaExpBinBuffer = mvOsMalloc(bufNum*bufSize); ++ if(cesaExpBinBuffer == NULL) ++ { ++ mvOsPrintf("testStart: Can't malloc %d bytes for cesaExpBinBuffer\n", ++ bufNum*bufSize); ++ return; ++ } ++ memset(cesaExpBinBuffer, 0, (bufNum*bufSize)); ++ ++ CESA_TEST_WAIT_INIT(); ++ ++ pMbufSrc = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ pFragsSrc = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ pMbufDst = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ pFragsDst = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ if( (pMbufSrc == NULL) || (pFragsSrc == NULL) || ++ (pMbufDst == NULL) || (pFragsDst == NULL) ) ++ { ++ mvOsPrintf("testStart: Can't malloc Src and Dst pMbuf and pFrags structures.\n"); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ ++ memset(pMbufSrc, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ memset(pFragsSrc, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ memset(pMbufDst, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ memset(pFragsDst, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ mvOsPrintf("Cesa Test Start: pMbufSrc=%p, pFragsSrc=%p, pMbufDst=%p, pFragsDst=%p\n", ++ pMbufSrc, pFragsSrc, pMbufDst, pFragsDst); ++ ++ idx = 0; ++ for(i=0; ipFrags = &pFragsSrc[idx]; ++ cesaCmdRing[i].pSrc->numFrags = bufNum; ++ cesaCmdRing[i].pSrc->mbufSize = 0; ++ ++ cesaCmdRing[i].pDst = &pMbufDst[i]; ++ cesaCmdRing[i].pDst->pFrags = &pFragsDst[idx]; ++ cesaCmdRing[i].pDst->numFrags = bufNum; ++ cesaCmdRing[i].pDst->mbufSize = 0; ++ ++ for(j=0; jpFrags[j].bufVirtPtr = (MV_U8*)pBuf; ++ cesaCmdRing[i].pSrc->pFrags[j].bufSize = bufSize; ++ pBuf += bufSize; ++ cesaCmdRing[i].pDst->pFrags[j].bufVirtPtr = (MV_U8*)pBuf; ++ cesaCmdRing[i].pDst->pFrags[j].bufSize = bufSize; ++ pBuf += bufSize; ++ } ++ idx += bufNum; ++ } ++ ++#ifndef MV_NETBSD ++ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) ++ pSram = (char*)addrDecWin.addrWin.baseLow; ++ else ++ { ++ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); ++ return; ++ } ++ ++#ifdef MV_CESA_NO_SRAM ++ pSram = mvOsMalloc(4*1024+8); ++ if(pSram == NULL) ++ { ++ mvOsPrintf("CesaTest: can't allocate %d bytes for SRAM simulation\n", ++ 4*1024+8); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ pSram = (MV_U8*)MV_ALIGN_UP((MV_U32)pSram, 8); ++#endif /* MV_CESA_NO_SRAM */ ++ ++ numOfSessions = CESA_DEF_SESSION_NUM; ++ queueDepth = CESA_DEF_REQ_SIZE - MV_CESA_MAX_CHAN; ++ ++ status = mvCesaInit(numOfSessions, queueDepth, pSram, NULL); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("mvCesaInit is Failed: status = 0x%x\n", status); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++#endif /* !MV_NETBSD */ ++ ++ /* Prepare data for tests */ ++ for(i=0; i<50; i++) ++ strcat((char*)cesaDataHexStr3, "dd"); ++ ++ strcpy((char*)cesaDataAndMd5digest3, cesaDataHexStr3); ++ strcpy((char*)cesaDataAndSha1digest3, cesaDataHexStr3); ++ ++ /* Digest must be 8 byte aligned */ ++ for(; i<56; i++) ++ { ++ strcat((char*)cesaDataAndMd5digest3, "00"); ++ strcat((char*)cesaDataAndSha1digest3, "00"); ++ } ++ strcat((char*)cesaDataAndMd5digest3, cesaHmacMd5digestHex3); ++ strcat((char*)cesaDataAndSha1digest3, cesaHmacSha1digestHex3); ++ ++#ifndef MV_NETBSD ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); ++#endif ++ ++#ifdef MV_VXWORKS ++ { ++ MV_STATUS status; ++ ++ status = intConnect((VOIDFUNCPTR *)INT_LVL_CESA, cesaTestReadyIsr, (int)NULL); ++ if (status != OK) ++ { ++ mvOsPrintf("CESA: Can't connect CESA (%d) interrupt, status=0x%x \n", ++ INT_LVL_CESA, status); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ cesaSemId = semMCreate(SEM_Q_PRIORITY | SEM_INVERSION_SAFE | SEM_DELETE_SAFE); ++ if(cesaSemId == NULL) ++ { ++ mvOsPrintf("cesaTestStart: Can't create semaphore\n"); ++ return; ++ } ++ intEnable(INT_LVL_CESA); ++ } ++#endif /* MV_VXWORKS */ ++ ++#if !defined(MV_NETBSD) && defined(__KERNEL__) ++ if( request_irq(CESA_IRQ, cesaTestReadyIsr, (SA_INTERRUPT) , "cesa_test", NULL ) ) ++ { ++ mvOsPrintf( "cannot assign irq\n" ); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ spin_lock_init( &cesaLock ); ++#endif ++} ++ ++MV_STATUS testRun(int idx, int caseIdx, int iter, ++ int reqSize, int checkMode) ++{ ++ int testIdx, count, sid, digestSize; ++ int blockSize; ++ MV_CESA_TEST_SESSION* pTestSession; ++ MV_CESA_COMMAND cmd; ++ MV_STATUS status; ++ ++ memset(&cmd, 0, sizeof(cmd)); ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return MV_BAD_PARAM; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ sid = pTestSession->sid; ++ if(sid == -1) ++ { ++ mvOsPrintf("Test %d is not opened\n", idx); ++ return MV_BAD_STATE; ++ } ++ switch(pTestSession->cryptoAlgorithm) ++ { ++ case MV_CESA_CRYPTO_DES: ++ case MV_CESA_CRYPTO_3DES: ++ blockSize = MV_CESA_DES_BLOCK_SIZE; ++ break; ++ ++ case MV_CESA_CRYPTO_AES: ++ blockSize = MV_CESA_AES_BLOCK_SIZE; ++ break; ++ ++ case MV_CESA_CRYPTO_NULL: ++ blockSize = 0; ++ break; ++ ++ default: ++ mvOsPrintf("cesaTestRun: Bad CryptoAlgorithm=%d\n", ++ pTestSession->cryptoAlgorithm); ++ return MV_BAD_PARAM; ++ } ++ switch(pTestSession->macAlgorithm) ++ { ++ case MV_CESA_MAC_MD5: ++ case MV_CESA_MAC_HMAC_MD5: ++ digestSize = MV_CESA_MD5_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_SHA1: ++ case MV_CESA_MAC_HMAC_SHA1: ++ digestSize = MV_CESA_SHA1_DIGEST_SIZE; ++ break; ++ default: ++ digestSize = 0; ++ } ++ ++ if(iter == 0) ++ iter = CESA_DEF_ITER_NUM; ++ ++ if(pTestSession->direction == MV_CESA_DIR_ENCODE) ++ { ++ cesaOutputHexStr = cesaTestCases[caseIdx].cipherHexStr; ++ cesaInputHexStr = cesaTestCases[caseIdx].plainHexStr; ++ } ++ else ++ { ++ cesaOutputHexStr = cesaTestCases[caseIdx].plainHexStr; ++ cesaInputHexStr = cesaTestCases[caseIdx].cipherHexStr; ++ } ++ ++ cmd.sessionId = sid; ++ if(checkMode == CESA_FAST_CHECK_MODE) ++ { ++ cmd.cryptoLength = cesaTestCases[caseIdx].cryptoLength; ++ cmd.macLength = cesaTestCases[caseIdx].macLength; ++ } ++ else ++ { ++ cmd.cryptoLength = reqSize; ++ cmd.macLength = reqSize; ++ } ++ cesaRateSize = cmd.cryptoLength; ++ cesaReqSize = cmd.cryptoLength; ++ cmd.cryptoOffset = 0; ++ if(pTestSession->operation != MV_CESA_MAC_ONLY) ++ { ++ if( (pTestSession->cryptoMode == MV_CESA_CRYPTO_CBC) || ++ (pTestSession->cryptoMode == MV_CESA_CRYPTO_CTR) ) ++ { ++ cmd.ivOffset = 0; ++ cmd.cryptoOffset = blockSize; ++ if(cesaTestCases[caseIdx].pCryptoIV == NULL) ++ { ++ cmd.ivFromUser = 1; ++ } ++ else ++ { ++ cmd.ivFromUser = 0; ++ mvCesaCryptoIvSet(cesaTestCases[caseIdx].pCryptoIV, blockSize); ++ } ++ cesaReqSize = cmd.cryptoOffset + cmd.cryptoLength; ++ } ++ } ++ ++/* ++ mvOsPrintf("ivFromUser=%d, cryptoLength=%d, cesaReqSize=%d, cryptoOffset=%d\n", ++ cmd.ivFromUser, cmd.cryptoLength, cesaReqSize, cmd.cryptoOffset); ++*/ ++ if(pTestSession->operation != MV_CESA_CRYPTO_ONLY) ++ { ++ cmd.macOffset = cmd.cryptoOffset; ++ ++ if(cesaTestCases[caseIdx].digestOffset == -1) ++ { ++ cmd.digestOffset = cmd.macOffset + cmd.macLength; ++ cmd.digestOffset = MV_ALIGN_UP(cmd.digestOffset, 8); ++ } ++ else ++ { ++ cmd.digestOffset = cesaTestCases[caseIdx].digestOffset; ++ } ++ if( (cmd.digestOffset + digestSize) > cesaReqSize) ++ cesaReqSize = cmd.digestOffset + digestSize; ++ } ++ ++ cesaCheckMode = checkMode; ++ ++ if(checkMode == CESA_NULL_CHECK_MODE) ++ { ++ cesaCheckSize = 0; ++ cesaCheckOffset = 0; ++ } ++ else ++ { ++ if(pTestSession->operation == MV_CESA_CRYPTO_ONLY) ++ { ++ cesaCheckOffset = 0; ++ cesaCheckSize = cmd.cryptoLength; ++ } ++ else ++ { ++ cesaCheckSize = digestSize; ++ cesaCheckOffset = cmd.digestOffset; ++ } ++ } ++/* ++ mvOsPrintf("reqSize=%d, checkSize=%d, checkOffset=%d, checkMode=%d\n", ++ cesaReqSize, cesaCheckSize, cesaCheckOffset, cesaCheckMode); ++ ++ mvOsPrintf("blockSize=%d, ivOffset=%d, ivFromUser=%d, crOffset=%d, crLength=%d\n", ++ blockSize, cmd.ivOffset, cmd.ivFromUser, ++ cmd.cryptoOffset, cmd.cryptoLength); ++ ++ mvOsPrintf("macOffset=%d, digestOffset=%d, macLength=%d\n", ++ cmd.macOffset, cmd.digestOffset, cmd.macLength); ++*/ ++ status = testCmd(sid, iter, &cmd, pTestSession, ++ cesaTestCases[caseIdx].pCryptoIV, blockSize); ++ ++ if(status != MV_OK) ++ return status; ++ ++ /* Wait when all callbacks is received */ ++ count = 0; ++ while(cesaIsReady == MV_FALSE) ++ { ++ mvOsSleep(10); ++ count++; ++ if(count > 100) ++ { ++ mvOsPrintf("testRun: Timeout occured\n"); ++ return MV_TIMEOUT; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++ ++void cesaTestStop(void) ++{ ++ MV_CESA_MBUF *pMbufSrc, *pMbufDst; ++ MV_BUF_INFO *pFragsSrc, *pFragsDst; ++ int i; ++ ++ /* Release all allocated memories */ ++ pMbufSrc = (MV_CESA_MBUF*)(cesaCmdRing[0].pSrc); ++ pFragsSrc = cesaCmdRing[0].pSrc->pFrags; ++ ++ pMbufDst = (MV_CESA_MBUF*)(cesaCmdRing[0].pDst); ++ pFragsDst = cesaCmdRing[0].pDst->pFrags; ++ ++ mvOsFree(pMbufSrc); ++ mvOsFree(pMbufDst); ++ mvOsFree(pFragsSrc); ++ mvOsFree(pFragsDst); ++ ++ for(i=0; i 0) ++ cryptoError++; ++ if(cesaReqIdError > 0) ++ reqIdError++; ++ ++ testClose(idx); ++ } ++ } ++ if(cryptoError > 0) ++ mvOsPrintf("cryptoError : %d\n", cryptoError); ++ if(reqIdError > 0) ++ mvOsPrintf("reqIdError : %d\n", reqIdError); ++ ++ if(openErrors > 0) ++ { ++ mvOsPrintf("Open Errors = %d\n", openErrors); ++ for(i=0; i<100; i++) ++ { ++ if(openErrDisp[i] != 0) ++ mvOsPrintf("Error %d - occurs %d times\n", i, openErrDisp[i]); ++ } ++ } ++} ++ ++ ++void loopback_test(int idx, int iter, int size, char* pPlainData) ++{ ++} ++ ++ ++#if defined(MV_VXWORKS) ++int testMode = 0; ++unsigned __TASKCONV cesaTask(void* args) ++{ ++ int reqSize = cesaReqSize; ++ ++ if(testMode == 0) ++ { ++ cesaOneTest(cesaTestIdx, cesaCaseIdx, cesaIteration, ++ reqSize, cesaCheckMode); ++ } ++ else ++ { ++ if(testMode == 1) ++ { ++ cesaTest(cesaIteration, reqSize, cesaCheckMode); ++ combiTest(cesaIteration, reqSize, cesaCheckMode); ++ } ++ else ++ { ++ multiSizeTest(cesaIdx, cesaIteration, cesaCheckMode, NULL); ++ } ++ } ++ return 0; ++} ++ ++void oneTest(int testIdx, int caseIdx, ++ int iter, int reqSize, int checkMode) ++{ ++ long rc; ++ ++ cesaIteration = iter; ++ cesaReqSize = cesaRateSize = reqSize; ++ cesaCheckMode = checkMode; ++ testMode = 0; ++ cesaTestIdx = testIdx; ++ cesaCaseIdx = caseIdx; ++ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); ++ if (rc != MV_OK) ++ { ++ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); ++ } ++} ++ ++void multiTest(int iter, int reqSize, int checkMode) ++{ ++ long rc; ++ ++ cesaIteration = iter; ++ cesaCheckMode = checkMode; ++ cesaReqSize = reqSize; ++ testMode = 1; ++ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); ++ if (rc != MV_OK) ++ { ++ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); ++ } ++} ++ ++void sizeTest(int testIdx, int iter, int checkMode) ++{ ++ long rc; ++ ++ cesaIteration = iter; ++ cesaCheckMode = checkMode; ++ testMode = 2; ++ cesaIdx = testIdx; ++ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); ++ if (rc != MV_OK) ++ { ++ mvOsPrintf("hMW: Can't create CESA test task, rc = %ld\n", rc); ++ } ++} ++ ++#endif /* MV_VXWORKS */ ++ ++extern void mvCesaDebugSA(short sid, int mode); ++void cesaTestPrintSession(int idx) ++{ ++ int testIdx; ++ MV_CESA_TEST_SESSION* pTestSession; ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ if(pTestSession->sid == -1) ++ { ++ mvOsPrintf("Test session %d is not opened\n", idx); ++ return; ++ } ++ ++ mvCesaDebugSA(pTestSession->sid, 1); ++} ++ ++void cesaTestPrintStatus(void) ++{ ++ mvOsPrintf("\n\t Cesa Test Status\n\n"); ++ ++ mvOsPrintf("isrCount=%d\n", ++ cesaTestIsrCount); ++ ++#ifdef CESA_TEST_DEBUG ++ { ++ int i, j; ++ j = cesaTestTraceIdx; ++ mvOsPrintf("No Type Cause rCause iCause Res Time pReady pProc pEmpty\n"); ++ for(i=0; itable = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY)); ++ if(pLruCache->table == NULL) ++ { ++ mvOsFree(pLruCache); ++ return NULL; ++ } ++ memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY)); ++ pLruCache->tableSize = numOfEntries; ++ ++ for(i=0; itable[i].next = i+1; ++ pLruCache->table[i].prev = i-1; ++ } ++ pLruCache->least = 0; ++ pLruCache->most = numOfEntries-1; ++ ++ return pLruCache; ++} ++ ++void mvLruCacheFinish(MV_LRU_CACHE* pLruCache) ++{ ++ mvOsFree(pLruCache->table); ++ mvOsFree(pLruCache); ++} ++ ++/* Update LRU cache database after using cache Index */ ++void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx) ++{ ++ int prev, next; ++ ++ if(cacheIdx == pLruHndl->most) ++ return; ++ ++ next = pLruHndl->table[cacheIdx].next; ++ if(cacheIdx == pLruHndl->least) ++ { ++ pLruHndl->least = next; ++ } ++ else ++ { ++ prev = pLruHndl->table[cacheIdx].prev; ++ ++ pLruHndl->table[next].prev = prev; ++ pLruHndl->table[prev].next = next; ++ } ++ ++ pLruHndl->table[pLruHndl->most].next = cacheIdx; ++ pLruHndl->table[cacheIdx].prev = pLruHndl->most; ++ pLruHndl->most = cacheIdx; ++} ++ ++/* Delete LRU cache entry */ ++void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx) ++{ ++ int prev, next; ++ ++ if(cacheIdx == pLruHndl->least) ++ return; ++ ++ prev = pLruHndl->table[cacheIdx].prev; ++ if(cacheIdx == pLruHndl->most) ++ { ++ pLruHndl->most = prev; ++ } ++ else ++ { ++ next = pLruHndl->table[cacheIdx].next; ++ ++ pLruHndl->table[next].prev = prev; ++ pLruHndl->table[prev].next = next; ++ } ++ pLruHndl->table[pLruHndl->least].prev = cacheIdx; ++ pLruHndl->table[cacheIdx].next = pLruHndl->least; ++ pLruHndl->least = cacheIdx; ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvLru.h linux-2.6.39/crypto/ocf/kirkwood/cesa/mvLru.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvLru.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvLru.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,112 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++/******************************************************************************* ++* mvLru.h - Header File for Least Recently Used Cache algorithm ++* ++* DESCRIPTION: ++* This header file contains macros typedefs and function declaration for ++* the Least Recently Used Cache algorithm. ++* ++*******************************************************************************/ ++ ++#ifndef __mvLru_h__ ++#define __mvLru_h__ ++ ++ ++typedef struct ++{ ++ int next; ++ int prev; ++} MV_LRU_ENTRY; ++ ++typedef struct ++{ ++ int least; ++ int most; ++ MV_LRU_ENTRY* table; ++ int tableSize; ++ ++}MV_LRU_CACHE; ++ ++ ++/* Find Cache index for replacement LRU */ ++static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl) ++{ ++ return pLruHndl->least; ++} ++ ++/* Init LRU cache module */ ++MV_LRU_CACHE* mvLruCacheInit(int numOfEntries); ++ ++/* Finish LRU cache module */ ++void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl); ++ ++/* Update LRU cache database after using cache Index */ ++void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx); ++ ++/* Delete LRU cache entry */ ++void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx); ++ ++ ++#endif /* __mvLru_h__ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvMD5.c linux-2.6.39/crypto/ocf/kirkwood/cesa/mvMD5.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvMD5.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvMD5.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,349 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvMD5.h" ++ ++static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]); ++ ++#ifdef MV_CPU_LE ++#define mvByteReverse(buf, len) /* Nothing */ ++#else ++static void mvByteReverse(unsigned char *buf, unsigned longs); ++ ++/* ++ * Note: this code is harmless on little-endian machines. ++ */ ++static void mvByteReverse(unsigned char *buf, unsigned longs) ++{ ++ MV_U32 t; ++ ++ do ++ { ++ t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 | ++ ((unsigned) buf[1] << 8 | buf[0]); ++ *(MV_U32 *) buf = t; ++ buf += 4; ++ } while (--longs); ++} ++#endif ++ ++/* ++ * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious ++ * initialization constants. ++ */ ++void mvMD5Init(MV_MD5_CONTEXT *ctx) ++{ ++ ctx->buf[0] = 0x67452301; ++ ctx->buf[1] = 0xefcdab89; ++ ctx->buf[2] = 0x98badcfe; ++ ctx->buf[3] = 0x10325476; ++ ++ ctx->bits[0] = 0; ++ ctx->bits[1] = 0; ++} ++ ++/* ++ * Update context to reflect the concatenation of another buffer full ++ * of bytes. ++ */ ++void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len) ++{ ++ MV_U32 t; ++ ++ /* Update bitcount */ ++ ++ t = ctx->bits[0]; ++ if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t) ++ ctx->bits[1]++; /* Carry from low to high */ ++ ctx->bits[1] += len >> 29; ++ ++ t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */ ++ ++ /* Handle any leading odd-sized chunks */ ++ ++ if (t) ++ { ++ unsigned char *p = (unsigned char *) ctx->in + t; ++ ++ t = 64 - t; ++ if (len < t) ++ { ++ memcpy(p, buf, len); ++ return; ++ } ++ memcpy(p, buf, t); ++ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ buf += t; ++ len -= t; ++ } ++ /* Process data in 64-byte chunks */ ++ ++ while (len >= 64) ++ { ++ memcpy(ctx->in, buf, 64); ++ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ buf += 64; ++ len -= 64; ++ } ++ ++ /* Handle any remaining bytes of data. */ ++ ++ memcpy(ctx->in, buf, len); ++} ++ ++/* ++ * Final wrapup - pad to 64-byte boundary with the bit pattern ++ * 1 0* (64-bit count of bits processed, MSB-first) ++ */ ++void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx) ++{ ++ unsigned count; ++ unsigned char *p; ++ ++ /* Compute number of bytes mod 64 */ ++ count = (ctx->bits[0] >> 3) & 0x3F; ++ ++ /* Set the first char of padding to 0x80. This is safe since there is ++ always at least one byte free */ ++ p = ctx->in + count; ++ *p++ = 0x80; ++ ++ /* Bytes of padding needed to make 64 bytes */ ++ count = 64 - 1 - count; ++ ++ /* Pad out to 56 mod 64 */ ++ if (count < 8) ++ { ++ /* Two lots of padding: Pad the first block to 64 bytes */ ++ memset(p, 0, count); ++ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ ++ /* Now fill the next block with 56 bytes */ ++ memset(ctx->in, 0, 56); ++ } ++ else ++ { ++ /* Pad block to 56 bytes */ ++ memset(p, 0, count - 8); ++ } ++ mvByteReverse(ctx->in, 14); ++ ++ /* Append length in bits and transform */ ++ ((MV_U32 *) ctx->in)[14] = ctx->bits[0]; ++ ((MV_U32 *) ctx->in)[15] = ctx->bits[1]; ++ ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ mvByteReverse((unsigned char *) ctx->buf, 4); ++ memcpy(digest, ctx->buf, MV_MD5_MAC_LEN); ++ memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */ ++} ++ ++/* The four core functions - F1 is optimized somewhat */ ++ ++/* #define F1(x, y, z) (x & y | ~x & z) */ ++#define F1(x, y, z) (z ^ (x & (y ^ z))) ++#define F2(x, y, z) F1(z, x, y) ++#define F3(x, y, z) (x ^ y ^ z) ++#define F4(x, y, z) (y ^ (x | ~z)) ++ ++/* This is the central step in the MD5 algorithm. */ ++#define MD5STEP(f, w, x, y, z, data, s) \ ++ ( w += f(x, y, z) + data, w = w<>(32-s), w += x ) ++ ++/* ++ * The core of the MD5 algorithm, this alters an existing MD5 hash to ++ * reflect the addition of 16 longwords of new data. MD5Update blocks ++ * the data and converts bytes into longwords for this routine. ++ */ ++static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]) ++{ ++ register MV_U32 a, b, c, d; ++ ++ a = buf[0]; ++ b = buf[1]; ++ c = buf[2]; ++ d = buf[3]; ++ ++ MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); ++ MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); ++ MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); ++ MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); ++ MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); ++ MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); ++ MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); ++ MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); ++ MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); ++ MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); ++ MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); ++ MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); ++ MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); ++ MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); ++ MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); ++ MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); ++ ++ MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); ++ MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); ++ MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); ++ MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); ++ MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); ++ MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); ++ MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); ++ MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); ++ MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); ++ MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); ++ MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); ++ MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); ++ MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); ++ MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); ++ MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); ++ MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); ++ ++ MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); ++ MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); ++ MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); ++ MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); ++ MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); ++ MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); ++ MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); ++ MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); ++ MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); ++ MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); ++ MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); ++ MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); ++ MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); ++ MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); ++ MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); ++ MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); ++ ++ MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); ++ MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); ++ MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); ++ MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); ++ MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); ++ MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); ++ MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); ++ MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); ++ MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); ++ MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); ++ MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); ++ MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); ++ MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); ++ MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); ++ MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); ++ MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); ++ ++ buf[0] += a; ++ buf[1] += b; ++ buf[2] += c; ++ buf[3] += d; ++} ++ ++void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest) ++{ ++ MV_MD5_CONTEXT ctx; ++ ++ mvMD5Init(&ctx); ++ mvMD5Update(&ctx, buf, len); ++ mvMD5Final(digest, &ctx); ++} ++ ++ ++void mvHmacMd5(unsigned char const* text, int text_len, ++ unsigned char const* key, int key_len, ++ unsigned char* digest) ++{ ++ int i; ++ MV_MD5_CONTEXT ctx; ++ unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */ ++ unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */ ++ ++ /* start out by storing key in pads */ ++ memset(k_ipad, 0, 64); ++ memcpy(k_ipad, key, key_len); ++ memset(k_opad, 0, 64); ++ memcpy(k_opad, key, key_len); ++ ++ /* XOR key with ipad and opad values */ ++ for (i=0; i<64; i++) ++ { ++ k_ipad[i] ^= 0x36; ++ k_opad[i] ^= 0x5c; ++ } ++ ++ /* perform inner MD5 */ ++ mvMD5Init(&ctx); /* init ctx for 1st pass */ ++ mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */ ++ mvMD5Update(&ctx, text, text_len); /* then text of datagram */ ++ mvMD5Final(digest, &ctx); /* finish up 1st pass */ ++ ++ /* perform outer MD5 */ ++ mvMD5Init(&ctx); /* init ctx for 2nd pass */ ++ mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */ ++ mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */ ++ mvMD5Final(digest, &ctx); /* finish up 2nd pass */ ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvMD5.h linux-2.6.39/crypto/ocf/kirkwood/cesa/mvMD5.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvMD5.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvMD5.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,93 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvMD5_h__ ++#define __mvMD5_h__ ++ ++#include "mvMD5.h" ++ ++#define MV_MD5_MAC_LEN 16 ++ ++ ++typedef struct ++{ ++ MV_U32 buf[4]; ++ MV_U32 bits[2]; ++ MV_U8 in[64]; ++ ++} MV_MD5_CONTEXT; ++ ++void mvMD5Init(MV_MD5_CONTEXT *context); ++void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf, ++ unsigned len); ++void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context); ++ ++void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest); ++ ++void mvHmacMd5(unsigned char const* text, int text_len, ++ unsigned char const* key, int key_len, ++ unsigned char* digest); ++ ++ ++#endif /* __mvMD5_h__ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c linux-2.6.39/crypto/ocf/kirkwood/cesa/mvSHA1.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvSHA1.c 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,239 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvSHA1.h" ++ ++#define SHA1HANDSOFF ++ ++typedef union ++{ ++ MV_U8 c[64]; ++ MV_U32 l[16]; ++ ++} CHAR64LONG16; ++ ++static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer); ++ ++#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) ++ ++ ++#ifdef MV_CPU_LE ++#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \ ++ (rol(block->l[i], 8) & 0x00FF00FF)) ++#else ++#define blk0(i) block->l[i] ++#endif ++#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \ ++ block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1)) ++ ++/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */ ++#define R0(v,w,x,y,z,i) \ ++ z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \ ++ w = rol(w, 30); ++#define R1(v,w,x,y,z,i) \ ++ z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \ ++ w = rol(w, 30); ++#define R2(v,w,x,y,z,i) \ ++ z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30); ++#define R3(v,w,x,y,z,i) \ ++ z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \ ++ w = rol(w, 30); ++#define R4(v,w,x,y,z,i) \ ++ z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \ ++ w=rol(w, 30); ++ ++/* Hash a single 512-bit block. This is the core of the algorithm. */ ++static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer) ++{ ++ MV_U32 a, b, c, d, e; ++ CHAR64LONG16* block; ++ ++#ifdef SHA1HANDSOFF ++ static MV_U32 workspace[16]; ++ ++ block = (CHAR64LONG16 *) workspace; ++ memcpy(block, buffer, 64); ++#else ++ block = (CHAR64LONG16 *) buffer; ++#endif ++ /* Copy context->state[] to working vars */ ++ a = state[0]; ++ b = state[1]; ++ c = state[2]; ++ d = state[3]; ++ e = state[4]; ++ /* 4 rounds of 20 operations each. Loop unrolled. */ ++ R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); ++ R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); ++ R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); ++ R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); ++ R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); ++ R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); ++ R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); ++ R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); ++ R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); ++ R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); ++ R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); ++ R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); ++ R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); ++ R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); ++ R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); ++ R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); ++ R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); ++ R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); ++ R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); ++ R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); ++ /* Add the working vars back into context.state[] */ ++ state[0] += a; ++ state[1] += b; ++ state[2] += c; ++ state[3] += d; ++ state[4] += e; ++ /* Wipe variables */ ++ a = b = c = d = e = 0; ++} ++ ++void mvSHA1Init(MV_SHA1_CTX* context) ++{ ++ /* SHA1 initialization constants */ ++ context->state[0] = 0x67452301; ++ context->state[1] = 0xEFCDAB89; ++ context->state[2] = 0x98BADCFE; ++ context->state[3] = 0x10325476; ++ context->state[4] = 0xC3D2E1F0; ++ context->count[0] = context->count[1] = 0; ++} ++ ++ ++/* Run your data through this. */ ++void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data, ++ unsigned int len) ++{ ++ MV_U32 i, j; ++ ++ j = (context->count[0] >> 3) & 63; ++ if ((context->count[0] += len << 3) < (len << 3)) ++ context->count[1]++; ++ context->count[1] += (len >> 29); ++ if ((j + len) > 63) ++ { ++ memcpy(&context->buffer[j], data, (i = 64-j)); ++ mvSHA1Transform(context->state, context->buffer); ++ for ( ; i + 63 < len; i += 64) ++ { ++ mvSHA1Transform(context->state, &data[i]); ++ } ++ j = 0; ++ } ++ else ++ { ++ i = 0; ++ } ++ memcpy(&context->buffer[j], &data[i], len - i); ++} ++ ++void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context) ++{ ++ MV_U32 i; ++ MV_U8 finalcount[8]; ++ ++ for (i = 0; i < 8; i++) ++ { ++ finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >> ++ ((3-(i & 3)) * 8) ) & 255); /* Endian independent */ ++ } ++ mvSHA1Update(context, (const unsigned char *) "\200", 1); ++ while ((context->count[0] & 504) != 448) ++ { ++ mvSHA1Update(context, (const unsigned char *) "\0", 1); ++ } ++ mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform() ++ */ ++ for (i = 0; i < 20; i++) ++ { ++ digest[i] = (unsigned char) ++ ((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255); ++ } ++ /* Wipe variables */ ++ i = 0; ++ memset(context->buffer, 0, 64); ++ memset(context->state, 0, 20); ++ memset(context->count, 0, 8); ++ memset(finalcount, 0, 8); ++ ++#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */ ++ mvSHA1Transform(context->state, context->buffer); ++#endif ++} ++ ++ ++void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest) ++{ ++ MV_SHA1_CTX ctx; ++ ++ mvSHA1Init(&ctx); ++ mvSHA1Update(&ctx, buf, len); ++ mvSHA1Final(digest, &ctx); ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h linux-2.6.39/crypto/ocf/kirkwood/cesa/mvSHA1.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvSHA1.h 2011-08-01 14:38:18.000000000 +0200 +@@ -0,0 +1,88 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvSHA1_h__ ++#define __mvSHA1_h__ ++ ++#include "mvSHA1.h" ++ ++#define MV_SHA1_MAC_LEN 20 ++ ++ ++typedef struct ++{ ++ MV_U32 state[5]; ++ MV_U32 count[2]; ++ MV_U8 buffer[64]; ++ ++} MV_SHA1_CTX; ++ ++void mvSHA1Init(MV_SHA1_CTX *context); ++void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len); ++void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context); ++ ++void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest); ++ ++ ++#endif /* __mvSHA1_h__ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c linux-2.6.39/crypto/ocf/kirkwood/cesa_ocf_drv.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/cesa_ocf_drv.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,1296 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ctrlEnv/sys/mvSysCesa.h" ++#include "cesa/mvCesa.h" /* moved here before cryptodev.h due to include dependencies */ ++#include ++#include ++#include ++#include ++#include "mvDebug.h" ++ ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#include "cesa/mvCesaRegs.h" ++#include "cesa/AES/mvAes.h" ++#include "cesa/mvLru.h" ++ ++#undef RT_DEBUG ++#ifdef RT_DEBUG ++static int debug = 1; ++module_param(debug, int, 1); ++MODULE_PARM_DESC(debug, "Enable debug"); ++#undef dprintk ++#define dprintk(a...) if (debug) { printk(a); } else ++#else ++static int debug = 0; ++#undef dprintk ++#define dprintk(a...) ++#endif ++ ++ ++/* TDMA Regs */ ++#define WINDOW_BASE(i) 0xA00 + (i << 3) ++#define WINDOW_CTRL(i) 0xA04 + (i << 3) ++ ++/* interrupt handling */ ++#undef CESA_OCF_POLLING ++#undef CESA_OCF_TASKLET ++ ++#if defined(CESA_OCF_POLLING) && defined(CESA_OCF_TASKLET) ++#error "don't use both tasklet and polling mode" ++#endif ++ ++extern int cesaReqResources; ++/* support for spliting action into 2 actions */ ++#define CESA_OCF_SPLIT ++ ++/* general defines */ ++#define CESA_OCF_MAX_SES 128 ++#define CESA_Q_SIZE 64 ++ ++ ++/* data structures */ ++struct cesa_ocf_data { ++ int cipher_alg; ++ int auth_alg; ++ int encrypt_tn_auth; ++#define auth_tn_decrypt encrypt_tn_auth ++ int ivlen; ++ int digestlen; ++ short sid_encrypt; ++ short sid_decrypt; ++ /* fragment workaround sessions */ ++ short frag_wa_encrypt; ++ short frag_wa_decrypt; ++ short frag_wa_auth; ++}; ++ ++/* CESA device data */ ++struct cesa_dev { ++ void __iomem *sram; ++ void __iomem *reg; ++ struct mv_cesa_platform_data *plat_data; ++ int irq; ++}; ++ ++#define DIGEST_BUF_SIZE 32 ++struct cesa_ocf_process { ++ MV_CESA_COMMAND cesa_cmd; ++ MV_CESA_MBUF cesa_mbuf; ++ MV_BUF_INFO cesa_bufs[MV_CESA_MAX_MBUF_FRAGS]; ++ char digest[DIGEST_BUF_SIZE]; ++ int digest_len; ++ struct cryptop *crp; ++ int need_cb; ++}; ++ ++/* global variables */ ++static int32_t cesa_ocf_id = -1; ++static struct cesa_ocf_data *cesa_ocf_sessions[CESA_OCF_MAX_SES]; ++static spinlock_t cesa_lock; ++static struct cesa_dev cesa_device; ++ ++/* static APIs */ ++static int cesa_ocf_process (device_t, struct cryptop *, int); ++static int cesa_ocf_newsession (device_t, u_int32_t *, struct cryptoini *); ++static int cesa_ocf_freesession (device_t, u_int64_t); ++static void cesa_callback (unsigned long); ++static irqreturn_t cesa_interrupt_handler (int, void *); ++#ifdef CESA_OCF_POLLING ++static void cesa_interrupt_polling(void); ++#endif ++#ifdef CESA_OCF_TASKLET ++static struct tasklet_struct cesa_ocf_tasklet; ++#endif ++ ++static struct timeval tt_start; ++static struct timeval tt_end; ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} mv_cesa_dev; ++ ++static device_method_t mv_cesa_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, cesa_ocf_newsession), ++ DEVMETHOD(cryptodev_freesession,cesa_ocf_freesession), ++ DEVMETHOD(cryptodev_process, cesa_ocf_process), ++ DEVMETHOD(cryptodev_kprocess, NULL), ++}; ++ ++ ++ ++/* Add debug Trace */ ++#undef CESA_OCF_TRACE_DEBUG ++#ifdef CESA_OCF_TRACE_DEBUG ++ ++#define MV_CESA_USE_TIMER_ID 0 ++ ++typedef struct ++{ ++ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ ++ MV_U32 timeStamp; ++ MV_U32 cause; ++ MV_U32 realCause; ++ MV_U32 dmaCause; ++ int resources; ++ MV_CESA_REQ* pReqReady; ++ MV_CESA_REQ* pReqEmpty; ++ MV_CESA_REQ* pReqProcess; ++} MV_CESA_TEST_TRACE; ++ ++#define MV_CESA_TEST_TRACE_SIZE 50 ++ ++static int cesaTestTraceIdx = 0; ++static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; ++ ++static void cesaTestTraceAdd(int type) ++{ ++ cesaTestTrace[cesaTestTraceIdx].type = type; ++ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ //cesaTestTrace[cesaTestTraceIdx].idmaCause = MV_REG_READ(IDMA_CAUSE_REG); ++ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; ++ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; ++ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; ++ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; ++ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); ++ cesaTestTraceIdx++; ++ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) ++ cesaTestTraceIdx = 0; ++} ++ ++#else /* CESA_OCF_TRACE_DEBUG */ ++ ++#define cesaTestTraceAdd(x) ++ ++#endif /* CESA_OCF_TRACE_DEBUG */ ++ ++unsigned int ++get_usec(unsigned int start) ++{ ++ if(start) { ++ do_gettimeofday (&tt_start); ++ return 0; ++ } ++ else { ++ do_gettimeofday (&tt_end); ++ tt_end.tv_sec -= tt_start.tv_sec; ++ tt_end.tv_usec -= tt_start.tv_usec; ++ if (tt_end.tv_usec < 0) { ++ tt_end.tv_usec += 1000 * 1000; ++ tt_end.tv_sec -= 1; ++ } ++ } ++ printk("time taken is %d\n", (unsigned int)(tt_end.tv_usec + tt_end.tv_sec * 1000000)); ++ return (tt_end.tv_usec + tt_end.tv_sec * 1000000); ++} ++ ++#ifdef RT_DEBUG ++/* ++ * check that the crp action match the current session ++ */ ++static int ++ocf_check_action(struct cryptop *crp, struct cesa_ocf_data *cesa_ocf_cur_ses) { ++ int count = 0; ++ int encrypt = 0, decrypt = 0, auth = 0; ++ struct cryptodesc *crd; ++ ++ /* Go through crypto descriptors, processing as we go */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next, count++) { ++ if(count > 2) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ ++ /* Encryption /Decryption */ ++ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { ++ /* check that the action is compatible with session */ ++ if(encrypt || decrypt) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ ++ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ if( (count == 2) && (cesa_ocf_cur_ses->encrypt_tn_auth) ) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ encrypt++; ++ } ++ else { /* decrypt */ ++ if( (count == 2) && !(cesa_ocf_cur_ses->auth_tn_decrypt) ) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ decrypt++; ++ } ++ ++ } ++ /* Authentication */ ++ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { ++ /* check that the action is compatible with session */ ++ if(auth) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ if( (count == 2) && (decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ if( (count == 2) && (encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ auth++; ++ } ++ else { ++ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ } ++ return 0; ++ ++} ++#endif ++ ++/* ++ * Process a request. ++ */ ++static int ++cesa_ocf_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct cesa_ocf_process *cesa_ocf_cmd = NULL; ++ struct cesa_ocf_process *cesa_ocf_cmd_wa = NULL; ++ MV_CESA_COMMAND *cesa_cmd; ++ struct cryptodesc *crd; ++ struct cesa_ocf_data *cesa_ocf_cur_ses; ++ int sid = 0, temp_len = 0, i; ++ int encrypt = 0, decrypt = 0, auth = 0; ++ int status; ++ struct sk_buff *skb = NULL; ++ struct uio *uiop = NULL; ++ unsigned char *ivp; ++ MV_BUF_INFO *p_buf_info; ++ MV_CESA_MBUF *p_mbuf_info; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if( cesaReqResources <= 1 ) { ++ dprintk("%s,%d: ERESTART\n", __FILE__, __LINE__); ++ return ERESTART; ++ } ++ ++#ifdef RT_DEBUG ++ /* Sanity check */ ++ if (crp == NULL) { ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL ) { ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ sid = crp->crp_sid & 0xffffffff; ++ if ((sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL)) { ++ crp->crp_etype = ENOENT; ++ printk("%s,%d: ENOENT session %d \n", __FILE__, __LINE__, sid); ++ return EINVAL; ++ } ++#endif ++ ++ sid = crp->crp_sid & 0xffffffff; ++ crp->crp_etype = 0; ++ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; ++ ++#ifdef RT_DEBUG ++ if(ocf_check_action(crp, cesa_ocf_cur_ses)){ ++ goto p_error; ++ } ++#endif ++ ++ /* malloc a new cesa process */ ++ cesa_ocf_cmd = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); ++ ++ if (cesa_ocf_cmd == NULL) { ++ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ memset(cesa_ocf_cmd, 0, sizeof(struct cesa_ocf_process)); ++ ++ /* init cesa_process */ ++ cesa_ocf_cmd->crp = crp; ++ /* always call callback */ ++ cesa_ocf_cmd->need_cb = 1; ++ ++ /* init cesa_cmd for usage of the HALs */ ++ cesa_cmd = &cesa_ocf_cmd->cesa_cmd; ++ cesa_cmd->pReqPrv = (void *)cesa_ocf_cmd; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_encrypt; /* defualt use encrypt */ ++ ++ /* prepare src buffer */ ++ /* we send the entire buffer to the HAL, even if only part of it should be encrypt/auth. */ ++ /* if not using seesions for both encrypt and auth, then it will be wiser to to copy only */ ++ /* from skip to crd_len. */ ++ p_buf_info = cesa_ocf_cmd->cesa_bufs; ++ p_mbuf_info = &cesa_ocf_cmd->cesa_mbuf; ++ ++ p_buf_info += 2; /* save 2 first buffers for IV and digest - ++ we won't append them to the end since, they ++ might be places in an unaligned addresses. */ ++ ++ p_mbuf_info->pFrags = p_buf_info; ++ temp_len = 0; ++ ++ /* handle SKB */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ ++ dprintk("%s,%d: handle SKB.\n", __FILE__, __LINE__); ++ skb = (struct sk_buff *) crp->crp_buf; ++ ++ if (skb_shinfo(skb)->nr_frags >= (MV_CESA_MAX_MBUF_FRAGS - 1)) { ++ printk("%s,%d: %d nr_frags > MV_CESA_MAX_MBUF_FRAGS", __FILE__, __LINE__, skb_shinfo(skb)->nr_frags); ++ goto p_error; ++ } ++ ++ p_mbuf_info->mbufSize = skb->len; ++ temp_len = skb->len; ++ /* first skb fragment */ ++ p_buf_info->bufSize = skb_headlen(skb); ++ p_buf_info->bufVirtPtr = skb->data; ++ p_buf_info++; ++ ++ /* now handle all other skb fragments */ ++ for ( i = 0; i < skb_shinfo(skb)->nr_frags; i++ ) { ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ p_buf_info->bufSize = frag->size; ++ p_buf_info->bufVirtPtr = page_address(frag->page) + frag->page_offset; ++ p_buf_info++; ++ } ++ p_mbuf_info->numFrags = skb_shinfo(skb)->nr_frags + 1; ++ } ++ /* handle UIO */ ++ else if(crp->crp_flags & CRYPTO_F_IOV) { ++ ++ dprintk("%s,%d: handle UIO.\n", __FILE__, __LINE__); ++ uiop = (struct uio *) crp->crp_buf; ++ ++ if (uiop->uio_iovcnt > (MV_CESA_MAX_MBUF_FRAGS - 1)) { ++ printk("%s,%d: %d uio_iovcnt > MV_CESA_MAX_MBUF_FRAGS \n", __FILE__, __LINE__, uiop->uio_iovcnt); ++ goto p_error; ++ } ++ ++ p_mbuf_info->mbufSize = crp->crp_ilen; ++ p_mbuf_info->numFrags = uiop->uio_iovcnt; ++ for(i = 0; i < uiop->uio_iovcnt; i++) { ++ p_buf_info->bufVirtPtr = uiop->uio_iov[i].iov_base; ++ p_buf_info->bufSize = uiop->uio_iov[i].iov_len; ++ temp_len += p_buf_info->bufSize; ++ dprintk("%s,%d: buf %x-> addr %x, size %x \n" ++ , __FILE__, __LINE__, i, (unsigned int)p_buf_info->bufVirtPtr, p_buf_info->bufSize); ++ p_buf_info++; ++ } ++ ++ } ++ /* handle CONTIG */ ++ else { ++ dprintk("%s,%d: handle CONTIG.\n", __FILE__, __LINE__); ++ p_mbuf_info->numFrags = 1; ++ p_mbuf_info->mbufSize = crp->crp_ilen; ++ p_buf_info->bufVirtPtr = crp->crp_buf; ++ p_buf_info->bufSize = crp->crp_ilen; ++ temp_len = crp->crp_ilen; ++ p_buf_info++; ++ } ++ ++ /* Support up to 64K why? cause! */ ++ if(crp->crp_ilen > 64*1024) { ++ printk("%s,%d: buf too big %x \n", __FILE__, __LINE__, crp->crp_ilen); ++ goto p_error; ++ } ++ ++ if( temp_len != crp->crp_ilen ) { ++ printk("%s,%d: warning size don't match.(%x %x) \n", __FILE__, __LINE__, temp_len, crp->crp_ilen); ++ } ++ ++ cesa_cmd->pSrc = p_mbuf_info; ++ cesa_cmd->pDst = p_mbuf_info; ++ ++ /* restore p_buf_info to point to first available buf */ ++ p_buf_info = cesa_ocf_cmd->cesa_bufs; ++ p_buf_info += 1; ++ ++ ++ /* Go through crypto descriptors, processing as we go */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ ++ /* Encryption /Decryption */ ++ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { ++ ++ dprintk("%s,%d: cipher", __FILE__, __LINE__); ++ ++ cesa_cmd->cryptoOffset = crd->crd_skip; ++ cesa_cmd->cryptoLength = crd->crd_len; ++ ++ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ dprintk(" encrypt \n"); ++ encrypt++; ++ ++ /* handle IV */ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { /* IV from USER */ ++ dprintk("%s,%d: IV from USER (offset %x) \n", __FILE__, __LINE__, crd->crd_inject); ++ cesa_cmd->ivFromUser = 1; ++ ivp = crd->crd_iv; ++ ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ dprintk("%s,%d: copy the IV back to the buffer\n", __FILE__, __LINE__); ++ cesa_cmd->ivOffset = crd->crd_inject; ++ crypto_copy_bits_back(crp->crp_buf, crd->crd_inject, ivp, cesa_ocf_cur_ses->ivlen); ++ } ++ else { ++ dprintk("%s,%d: don't copy the IV back to the buffer \n", __FILE__, __LINE__); ++ p_mbuf_info->numFrags++; ++ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; ++ p_mbuf_info->pFrags = p_buf_info; ++ ++ p_buf_info->bufVirtPtr = ivp; ++ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; ++ p_buf_info--; ++ ++ /* offsets */ ++ cesa_cmd->ivOffset = 0; ++ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; ++ if(auth) { ++ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; ++ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; ++ } ++ } ++ } ++ else { /* random IV */ ++ dprintk("%s,%d: random IV \n", __FILE__, __LINE__); ++ cesa_cmd->ivFromUser = 0; ++ ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ /* in this mode the HAL will always copy the IV */ ++ /* given by the session to the ivOffset */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ cesa_cmd->ivOffset = crd->crd_inject; ++ } ++ else { ++ /* if IV isn't copy, then how will the user know which IV did we use??? */ ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ } ++ } ++ else { /* decrypt */ ++ dprintk(" decrypt \n"); ++ decrypt++; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_decrypt; ++ ++ /* handle IV */ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ dprintk("%s,%d: IV from USER \n", __FILE__, __LINE__); ++ /* append the IV buf to the mbuf */ ++ cesa_cmd->ivFromUser = 1; ++ p_mbuf_info->numFrags++; ++ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; ++ p_mbuf_info->pFrags = p_buf_info; ++ ++ p_buf_info->bufVirtPtr = crd->crd_iv; ++ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; ++ p_buf_info--; ++ ++ /* offsets */ ++ cesa_cmd->ivOffset = 0; ++ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; ++ if(auth) { ++ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; ++ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; ++ } ++ } ++ else { ++ dprintk("%s,%d: IV inside the buffer \n", __FILE__, __LINE__); ++ cesa_cmd->ivFromUser = 0; ++ cesa_cmd->ivOffset = crd->crd_inject; ++ } ++ } ++ ++ } ++ /* Authentication */ ++ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { ++ dprintk("%s,%d: Authentication \n", __FILE__, __LINE__); ++ auth++; ++ cesa_cmd->macOffset = crd->crd_skip; ++ cesa_cmd->macLength = crd->crd_len; ++ ++ /* digest + mac */ ++ cesa_cmd->digestOffset = crd->crd_inject; ++ } ++ else { ++ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ } ++ ++ dprintk("\n"); ++ dprintk("%s,%d: Sending Action: \n", __FILE__, __LINE__); ++ dprintk("%s,%d: IV from user: %d. IV offset %x \n", __FILE__, __LINE__, cesa_cmd->ivFromUser, cesa_cmd->ivOffset); ++ dprintk("%s,%d: crypt offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->cryptoOffset, cesa_cmd->cryptoLength); ++ dprintk("%s,%d: Auth offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->macOffset, cesa_cmd->macLength); ++ dprintk("%s,%d: set digest in offset %x . \n", __FILE__, __LINE__, cesa_cmd->digestOffset); ++ if(debug) { ++ mvCesaDebugMbuf("SRC BUFFER", cesa_cmd->pSrc, 0, cesa_cmd->pSrc->mbufSize); ++ } ++ ++ ++ /* send action to HAL */ ++ spin_lock_irqsave(&cesa_lock, flags); ++ status = mvCesaAction(cesa_cmd); ++ spin_unlock_irqrestore(&cesa_lock, flags); ++ ++ /* action not allowed */ ++ if(status == MV_NOT_ALLOWED) { ++#ifdef CESA_OCF_SPLIT ++ /* if both encrypt and auth try to split */ ++ if(auth && (encrypt || decrypt)) { ++ MV_CESA_COMMAND *cesa_cmd_wa; ++ ++ /* malloc a new cesa process and init it */ ++ cesa_ocf_cmd_wa = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); ++ ++ if (cesa_ocf_cmd_wa == NULL) { ++ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ memcpy(cesa_ocf_cmd_wa, cesa_ocf_cmd, sizeof(struct cesa_ocf_process)); ++ cesa_cmd_wa = &cesa_ocf_cmd_wa->cesa_cmd; ++ cesa_cmd_wa->pReqPrv = (void *)cesa_ocf_cmd_wa; ++ cesa_ocf_cmd_wa->need_cb = 0; ++ ++ /* break requests to two operation, first operation completion won't call callback */ ++ if((decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; ++ } ++ else if((decrypt) && !(cesa_ocf_cur_ses->auth_tn_decrypt)) { ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ } ++ else if((encrypt) && (cesa_ocf_cur_ses->encrypt_tn_auth)) { ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ } ++ else if((encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)){ ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; ++ } ++ else { ++ printk("%s,%d: Unsupporterd fragment wa mode \n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ ++ /* send the 2 actions to the HAL */ ++ spin_lock_irqsave(&cesa_lock, flags); ++ status = mvCesaAction(cesa_cmd_wa); ++ spin_unlock_irqrestore(&cesa_lock, flags); ++ ++ if((status != MV_NO_MORE) && (status != MV_OK)) { ++ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); ++ goto p_error; ++ } ++ spin_lock_irqsave(&cesa_lock, flags); ++ status = mvCesaAction(cesa_cmd); ++ spin_unlock_irqrestore(&cesa_lock, flags); ++ ++ } ++ /* action not allowed and can't split */ ++ else ++#endif ++ { ++ goto p_error; ++ } ++ } ++ ++ /* Hal Q is full, send again. This should never happen */ ++ if(status == MV_NO_RESOURCE) { ++ printk("%s,%d: cesa no more resources \n", __FILE__, __LINE__); ++ if(cesa_ocf_cmd) ++ kfree(cesa_ocf_cmd); ++ if(cesa_ocf_cmd_wa) ++ kfree(cesa_ocf_cmd_wa); ++ return ERESTART; ++ } ++ else if((status != MV_NO_MORE) && (status != MV_OK)) { ++ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); ++ goto p_error; ++ } ++ ++ ++#ifdef CESA_OCF_POLLING ++ cesa_interrupt_polling(); ++#endif ++ cesaTestTraceAdd(5); ++ ++ return 0; ++p_error: ++ crp->crp_etype = EINVAL; ++ if(cesa_ocf_cmd) ++ kfree(cesa_ocf_cmd); ++ if(cesa_ocf_cmd_wa) ++ kfree(cesa_ocf_cmd_wa); ++ return EINVAL; ++} ++ ++/* ++ * cesa callback. ++ */ ++static void ++cesa_callback(unsigned long dummy) ++{ ++ struct cesa_ocf_process *cesa_ocf_cmd = NULL; ++ struct cryptop *crp = NULL; ++ MV_CESA_RESULT result[MV_CESA_MAX_CHAN]; ++ int res_idx = 0,i; ++ MV_STATUS status; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++#ifdef CESA_OCF_TASKLET ++ disable_irq(cesa_device.irq); ++#endif ++ while(MV_TRUE) { ++ ++ /* Get Ready requests */ ++ spin_lock(&cesa_lock); ++ status = mvCesaReadyGet(&result[res_idx]); ++ spin_unlock(&cesa_lock); ++ ++ cesaTestTraceAdd(2); ++ ++ if(status != MV_OK) { ++#ifdef CESA_OCF_POLLING ++ if(status == MV_BUSY) { /* Fragment */ ++ cesa_interrupt_polling(); ++ return; ++ } ++#endif ++ break; ++ } ++ res_idx++; ++ break; ++ } ++ ++ for(i = 0; i < res_idx; i++) { ++ ++ if(!result[i].pReqPrv) { ++ printk("%s,%d: warning private is NULL\n", __FILE__, __LINE__); ++ break; ++ } ++ ++ cesa_ocf_cmd = result[i].pReqPrv; ++ crp = cesa_ocf_cmd->crp; ++ ++ // ignore HMAC error. ++ //if(result->retCode) ++ // crp->crp_etype = EIO; ++ ++#if defined(CESA_OCF_POLLING) ++ if(!cesa_ocf_cmd->need_cb){ ++ cesa_interrupt_polling(); ++ } ++#endif ++ if(cesa_ocf_cmd->need_cb) { ++ if(debug) { ++ mvCesaDebugMbuf("DST BUFFER", cesa_ocf_cmd->cesa_cmd.pDst, 0, cesa_ocf_cmd->cesa_cmd.pDst->mbufSize); ++ } ++ crypto_done(crp); ++ } ++ kfree(cesa_ocf_cmd); ++ } ++#ifdef CESA_OCF_TASKLET ++ enable_irq(cesa_device.irq); ++#endif ++ ++ cesaTestTraceAdd(3); ++ ++ return; ++} ++ ++#ifdef CESA_OCF_POLLING ++static void ++cesa_interrupt_polling(void) ++{ ++ u32 cause; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Read cause register */ ++ do { ++ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ cause &= MV_CESA_CAUSE_ACC_DMA_ALL_MASK; ++ ++ } while (cause == 0); ++ ++ /* clear interrupts */ ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++ ++ cesa_callback(0); ++ ++ return; ++} ++ ++#endif ++ ++/* ++ * cesa Interrupt polling routine. ++ */ ++static irqreturn_t ++cesa_interrupt_handler(int irq, void *arg) ++{ ++ u32 cause; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ cesaTestTraceAdd(0); ++ ++ /* Read cause register */ ++ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ ++ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) ++ { ++ /* Empty interrupt */ ++ dprintk("%s,%d: cesaTestReadyIsr: cause=0x%x\n", __FILE__, __LINE__, cause); ++ return IRQ_HANDLED; ++ } ++ ++ /* clear interrupts */ ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++ ++ cesaTestTraceAdd(1); ++#ifdef CESA_OCF_TASKLET ++ tasklet_hi_schedule(&cesa_ocf_tasklet); ++#else ++ cesa_callback(0); ++#endif ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Open a session. ++ */ ++static int ++/*cesa_ocf_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri)*/ ++cesa_ocf_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ u32 status = 0, i; ++ u32 count = 0, auth = 0, encrypt =0; ++ struct cesa_ocf_data *cesa_ocf_cur_ses; ++ MV_CESA_OPEN_SESSION cesa_session; ++ MV_CESA_OPEN_SESSION *cesa_ses = &cesa_session; ++ ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* leave first empty like in other implementations */ ++ for (i = 1; i < CESA_OCF_MAX_SES; i++) { ++ if (cesa_ocf_sessions[i] == NULL) ++ break; ++ } ++ ++ if(i >= CESA_OCF_MAX_SES) { ++ printk("%s,%d: no more sessions \n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ cesa_ocf_sessions[i] = (struct cesa_ocf_data *) kmalloc(sizeof(struct cesa_ocf_data), GFP_ATOMIC); ++ if (cesa_ocf_sessions[i] == NULL) { ++ cesa_ocf_freesession(NULL, i); ++ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ dprintk("%s,%d: new session %d \n", __FILE__, __LINE__, i); ++ ++ *sid = i; ++ cesa_ocf_cur_ses = cesa_ocf_sessions[i]; ++ memset(cesa_ocf_cur_ses, 0, sizeof(struct cesa_ocf_data)); ++ cesa_ocf_cur_ses->sid_encrypt = -1; ++ cesa_ocf_cur_ses->sid_decrypt = -1; ++ cesa_ocf_cur_ses->frag_wa_encrypt = -1; ++ cesa_ocf_cur_ses->frag_wa_decrypt = -1; ++ cesa_ocf_cur_ses->frag_wa_auth = -1; ++ ++ /* init the session */ ++ memset(cesa_ses, 0, sizeof(MV_CESA_OPEN_SESSION)); ++ count = 1; ++ while (cri) { ++ if(count > 2) { ++ printk("%s,%d: don't support more then 2 operations\n", __FILE__, __LINE__); ++ goto error; ++ } ++ switch (cri->cri_alg) { ++ case CRYPTO_AES_CBC: ++ dprintk("%s,%d: (%d) AES CBC \n", __FILE__, __LINE__, count); ++ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->ivlen = MV_CESA_AES_BLOCK_SIZE; ++ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_AES; ++ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); ++ dprintk("%s,%d: key length %d \n", __FILE__, __LINE__, cri->cri_klen/8); ++ cesa_ses->cryptoKeyLength = cri->cri_klen/8; ++ encrypt += count; ++ break; ++ case CRYPTO_3DES_CBC: ++ dprintk("%s,%d: (%d) 3DES CBC \n", __FILE__, __LINE__, count); ++ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->ivlen = MV_CESA_3DES_BLOCK_SIZE; ++ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_3DES; ++ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->cryptoKeyLength = cri->cri_klen/8; ++ encrypt += count; ++ break; ++ case CRYPTO_DES_CBC: ++ dprintk("%s,%d: (%d) DES CBC \n", __FILE__, __LINE__, count); ++ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->ivlen = MV_CESA_DES_BLOCK_SIZE; ++ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_DES; ++ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->cryptoKeyLength = cri->cri_klen/8; ++ encrypt += count; ++ break; ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ dprintk("%s,%d: (%d) %sMD5 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_MD5)? "H-":" "); ++ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MD5_DIGEST_SIZE : 12; ++ cesa_ses->macMode = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MAC_MD5 : MV_CESA_MAC_HMAC_MD5; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); ++ goto error; ++ } ++ cesa_ses->macKeyLength = cri->cri_klen/8; ++ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; ++ auth += count; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ dprintk("%s,%d: (%d) %sSHA1 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_SHA1)? "H-":" "); ++ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_SHA1_DIGEST_SIZE : 12; ++ cesa_ses->macMode = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_MAC_SHA1 : MV_CESA_MAC_HMAC_SHA1; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); ++ goto error; ++ } ++ cesa_ses->macKeyLength = cri->cri_klen/8; ++ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; ++ auth += count; ++ break; ++ default: ++ printk("%s,%d: unknown algo 0x%x\n", __FILE__, __LINE__, cri->cri_alg); ++ goto error; ++ } ++ cri = cri->cri_next; ++ count++; ++ } ++ ++ if((encrypt > 2) || (auth > 2)) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ /* create new sessions in HAL */ ++ if(encrypt) { ++ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; ++ /* encrypt session */ ++ if(auth == 1) { ++ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; ++ } ++ else if(auth == 2) { ++ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; ++ cesa_ocf_cur_ses->encrypt_tn_auth = 1; ++ } ++ else { ++ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; ++ } ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ /* decrypt session */ ++ if( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) { ++ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; ++ } ++ else if( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC ) { ++ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; ++ } ++ cesa_ses->direction = MV_CESA_DIR_DECODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_decrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ ++ /* preapre one action sessions for case we will need to split an action */ ++#ifdef CESA_OCF_SPLIT ++ if(( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) || ++ ( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC )) { ++ /* open one session for encode and one for decode */ ++ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_encrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ ++ cesa_ses->direction = MV_CESA_DIR_DECODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_decrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ /* open one session for auth */ ++ cesa_ses->operation = MV_CESA_MAC_ONLY; ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_auth); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ } ++#endif ++ } ++ else { /* only auth */ ++ cesa_ses->operation = MV_CESA_MAC_ONLY; ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ } ++ ++ return 0; ++error: ++ cesa_ocf_freesession(NULL, *sid); ++ return EINVAL; ++ ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++cesa_ocf_freesession(device_t dev, u_int64_t tid) ++{ ++ struct cesa_ocf_data *cesa_ocf_cur_ses; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ //unsigned long flags; ++ ++ dprintk("%s() %d \n", __FUNCTION__, sid); ++ if ( (sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL) ) { ++ printk("%s,%d: EINVAL can't free session %d \n", __FILE__, __LINE__, sid); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ /* release session from HAL */ ++ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; ++ if (cesa_ocf_cur_ses->sid_encrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->sid_encrypt); ++ } ++ if (cesa_ocf_cur_ses->sid_decrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->sid_decrypt); ++ } ++ if (cesa_ocf_cur_ses->frag_wa_encrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_encrypt); ++ } ++ if (cesa_ocf_cur_ses->frag_wa_decrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_decrypt); ++ } ++ if (cesa_ocf_cur_ses->frag_wa_auth != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_auth); ++ } ++ ++ kfree(cesa_ocf_cur_ses); ++ cesa_ocf_sessions[sid] = NULL; ++ ++ return 0; ++} ++ ++ ++/* TDMA Window setup */ ++ ++static void __init ++setup_tdma_mbus_windows(struct cesa_dev *dev) ++{ ++ int i; ++ ++ for (i = 0; i < 4; i++) { ++ writel(0, dev->reg + WINDOW_BASE(i)); ++ writel(0, dev->reg + WINDOW_CTRL(i)); ++ } ++ ++ for (i = 0; i < dev->plat_data->dram->num_cs; i++) { ++ struct mbus_dram_window *cs = dev->plat_data->dram->cs + i; ++ writel( ++ ((cs->size - 1) & 0xffff0000) | ++ (cs->mbus_attr << 8) | ++ (dev->plat_data->dram->mbus_dram_target_id << 4) | 1, ++ dev->reg + WINDOW_CTRL(i) ++ ); ++ writel(cs->base, dev->reg + WINDOW_BASE(i)); ++ } ++} ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++static int ++mv_cesa_ocf_init(struct platform_device *pdev) ++{ ++#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X) ++ if (MV_FALSE == mvSocUnitIsMappedToThisCpu(CESA)) ++ { ++ dprintk("CESA is not mapped to this CPU\n"); ++ return -ENODEV; ++ } ++#endif ++ ++ dprintk("%s\n", __FUNCTION__); ++ memset(&mv_cesa_dev, 0, sizeof(mv_cesa_dev)); ++ softc_device_init(&mv_cesa_dev, "MV CESA", 0, mv_cesa_methods); ++ cesa_ocf_id = crypto_get_driverid(softc_get_device(&mv_cesa_dev),CRYPTOCAP_F_HARDWARE); ++ ++ if (cesa_ocf_id < 0) ++ panic("MV CESA crypto device cannot initialize!"); ++ ++ dprintk("%s,%d: cesa ocf device id is %d \n", __FILE__, __LINE__, cesa_ocf_id); ++ ++ /* CESA unit is auto power on off */ ++#if 0 ++ if (MV_FALSE == mvCtrlPwrClckGet(CESA_UNIT_ID,0)) ++ { ++ printk("\nWarning CESA %d is Powered Off\n",0); ++ return EINVAL; ++ } ++#endif ++ ++ memset(&cesa_device, 0, sizeof(struct cesa_dev)); ++ /* Get the IRQ, and crypto memory regions */ ++ { ++ struct resource *res; ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); ++ ++ if (!res) ++ return -ENXIO; ++ ++ cesa_device.sram = ioremap(res->start, res->end - res->start + 1); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); ++ ++ if (!res) { ++ iounmap(cesa_device.sram); ++ return -ENXIO; ++ } ++ cesa_device.reg = ioremap(res->start, res->end - res->start + 1); ++ cesa_device.irq = platform_get_irq(pdev, 0); ++ cesa_device.plat_data = pdev->dev.platform_data; ++ setup_tdma_mbus_windows(&cesa_device); ++ ++ } ++ ++ ++ if( MV_OK != mvCesaInit(CESA_OCF_MAX_SES*5, CESA_Q_SIZE, cesa_device.reg, ++ NULL) ) { ++ printk("%s,%d: mvCesaInit Failed. \n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* clear and unmask Int */ ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++#ifndef CESA_OCF_POLLING ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); ++#endif ++#ifdef CESA_OCF_TASKLET ++ tasklet_init(&cesa_ocf_tasklet, cesa_callback, (unsigned int) 0); ++#endif ++ /* register interrupt */ ++ if( request_irq( cesa_device.irq, cesa_interrupt_handler, ++ (IRQF_DISABLED) , "cesa", &cesa_ocf_id) < 0) { ++ printk("%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, cesa_device.reg); ++ return EINVAL; ++ } ++ ++ ++ memset(cesa_ocf_sessions, 0, sizeof(struct cesa_ocf_data *) * CESA_OCF_MAX_SES); ++ ++#define REGISTER(alg) \ ++ crypto_register(cesa_ocf_id, alg, 0,0) ++ REGISTER(CRYPTO_AES_CBC); ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++ return 0; ++} ++ ++static void ++mv_cesa_ocf_exit(struct platform_device *pdev) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ crypto_unregister_all(cesa_ocf_id); ++ cesa_ocf_id = -1; ++ iounmap(cesa_device.reg); ++ iounmap(cesa_device.sram); ++ free_irq(cesa_device.irq, NULL); ++ ++ /* mask and clear Int */ ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ ++ ++ if( MV_OK != mvCesaFinish() ) { ++ printk("%s,%d: mvCesaFinish Failed. \n", __FILE__, __LINE__); ++ return; ++ } ++} ++ ++ ++void cesa_ocf_debug(void) ++{ ++ ++#ifdef CESA_OCF_TRACE_DEBUG ++ { ++ int i, j; ++ j = cesaTestTraceIdx; ++ mvOsPrintf("No Type rCause iCause Proc Isr Res Time pReady pProc pEmpty\n"); ++ for(i=0; i= _1G) ++ { ++ mvOsOutput("%3dGB ", size / _1G); ++ size %= _1G; ++ if(size) ++ mvOsOutput("+"); ++ } ++ if(size >= _1M ) ++ { ++ mvOsOutput("%3dMB ", size / _1M); ++ size %= _1M; ++ if(size) ++ mvOsOutput("+"); ++ } ++ if(size >= _1K) ++ { ++ mvOsOutput("%3dKB ", size / _1K); ++ size %= _1K; ++ if(size) ++ mvOsOutput("+"); ++ } ++ if(size > 0) ++ { ++ mvOsOutput("%3dB ", size); ++ } ++} ++ ++/******************************************************************************* ++* mvHexToBin - Convert hex to binary ++* ++* DESCRIPTION: ++* This function Convert hex to binary. ++* ++* INPUT: ++* pHexStr - hex buffer pointer. ++* size - Size to convert. ++* ++* OUTPUT: ++* pBin - Binary buffer pointer. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size) ++{ ++ int j, i; ++ char tmp[3]; ++ MV_U8 byte; ++ ++ for(j=0, i=0; j> 1; ++ result++; ++ } ++ return result; ++} ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvCommon.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,308 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++ ++#ifndef __INCmvCommonh ++#define __INCmvCommonh ++ ++#include "mvTypes.h" ++ ++/* Swap tool */ ++ ++/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ ++#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ ++ ((X&0xf0) >> 4) | \ ++ ((X&0xf00) << 4) | \ ++ ((X&0xf000) >> 4)) ++ ++/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ ++#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ ++ ((X&0xf0) >> 4) | \ ++ ((X&0xf00) << 4) | \ ++ ((X&0xf000) >> 4) | \ ++ ((X&0xf0000) << 4) | \ ++ ((X&0xf00000) >> 4) | \ ++ ((X&0xf000000) << 4) | \ ++ ((X&0xf0000000) >> 4)) ++ ++/* 16bit byte swap. For example 0x1122 -> 0x2211 */ ++#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) ++ ++/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ ++#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ ++ (((X)&0xff00)<<8) | \ ++ (((X)&0xff0000)>>8) | \ ++ (((X)&0xff000000)>>24)) ++ ++/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ ++#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ ++ (((X)&0xff00ULL)<<40) | \ ++ (((X)&0xff0000ULL)<<24) | \ ++ (((X)&0xff000000ULL)<<8) | \ ++ (((X)&0xff00000000ULL)>>8) | \ ++ (((X)&0xff0000000000ULL)>>24) | \ ++ (((X)&0xff000000000000ULL)>>40) | \ ++ (((X)&0xff00000000000000ULL)>>56))) ++ ++/* Endianess macros. */ ++#if defined(MV_CPU_LE) ++ #define MV_16BIT_LE(X) (X) ++ #define MV_32BIT_LE(X) (X) ++ #define MV_64BIT_LE(X) (X) ++ #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) ++ #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) ++ #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) ++#elif defined(MV_CPU_BE) ++ #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) ++ #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) ++ #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) ++ #define MV_16BIT_BE(X) (X) ++ #define MV_32BIT_BE(X) (X) ++ #define MV_64BIT_BE(X) (X) ++#else ++ #error "CPU endianess isn't defined!\n" ++#endif ++ ++ ++/* Bit field definitions */ ++#define NO_BIT 0x00000000 ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++ ++/* Handy sizes */ ++#define _1K 0x00000400 ++#define _2K 0x00000800 ++#define _4K 0x00001000 ++#define _8K 0x00002000 ++#define _16K 0x00004000 ++#define _32K 0x00008000 ++#define _64K 0x00010000 ++#define _128K 0x00020000 ++#define _256K 0x00040000 ++#define _512K 0x00080000 ++ ++#define _1M 0x00100000 ++#define _2M 0x00200000 ++#define _4M 0x00400000 ++#define _8M 0x00800000 ++#define _16M 0x01000000 ++#define _32M 0x02000000 ++#define _64M 0x04000000 ++#define _128M 0x08000000 ++#define _256M 0x10000000 ++#define _512M 0x20000000 ++ ++#define _1G 0x40000000 ++#define _2G 0x80000000 ++ ++/* Tclock and Sys clock define */ ++#define _100MHz 100000000 ++#define _125MHz 125000000 ++#define _133MHz 133333334 ++#define _150MHz 150000000 ++#define _160MHz 160000000 ++#define _166MHz 166666667 ++#define _175MHz 175000000 ++#define _178MHz 178000000 ++#define _183MHz 183333334 ++#define _187MHz 187000000 ++#define _192MHz 192000000 ++#define _194MHz 194000000 ++#define _200MHz 200000000 ++#define _233MHz 233333334 ++#define _250MHz 250000000 ++#define _266MHz 266666667 ++#define _300MHz 300000000 ++ ++/* For better address window table readability */ ++#define EN MV_TRUE ++#define DIS MV_FALSE ++#define N_A -1 /* Not applicable */ ++ ++/* Cache configuration options for memory (DRAM, SRAM, ... ) */ ++ ++/* Memory uncached, HW or SW cache coherency is not needed */ ++#define MV_UNCACHED 0 ++/* Memory cached, HW cache coherency supported in WriteThrough mode */ ++#define MV_CACHE_COHER_HW_WT 1 ++/* Memory cached, HW cache coherency supported in WriteBack mode */ ++#define MV_CACHE_COHER_HW_WB 2 ++/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ ++#define MV_CACHE_COHER_SW 3 ++ ++ ++/* Macro for testing aligment. Positive if number is NOT aligned */ ++#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) ++ ++/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ ++#define MV_ALIGN_UP(number, align) \ ++(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) ++ ++/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ ++#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) ++ ++/* This macro returns absolute value */ ++#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) ++ ++ ++/* Bit fields manipulation macros */ ++ ++/* An integer word which its 'x' bit is set */ ++#define MV_BIT_MASK(bitNum) (1 << (bitNum) ) ++ ++/* Checks wheter bit 'x' in integer word is set */ ++#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) ) ++ ++/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ ++#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) ) ++ ++/* Set bit 'x' in integer word (RMW) */ ++#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) ) ++ ++/* Invert bit 'x' in integer word (RMW) */ ++#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) ) ++ ++/* Get the min between 'a' or 'b' */ ++#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b)) ++ ++/* Get the max between 'a' or 'b' */ ++#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a)) ++ ++/* Temporary */ ++#define mvOsDivide(num, div) \ ++({ \ ++ int i=0, rem=(num); \ ++ \ ++ while(rem >= (div)) \ ++ { \ ++ rem -= (div); \ ++ i++; \ ++ } \ ++ (i); \ ++}) ++ ++/* Temporary */ ++#define mvOsReminder(num, div) \ ++({ \ ++ int rem = (num); \ ++ \ ++ while(rem >= (div)) \ ++ rem -= (div); \ ++ (rem); \ ++}) ++ ++#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ ++ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) ++ ++#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) ++ ++#ifndef MV_ASMLANGUAGE ++/* mvCommon API list */ ++ ++MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size); ++void mvAsciiToHex(const char* asciiStr, char* hexStr); ++void mvBinToHex(const MV_U8* bin, char* hexStr, int size); ++void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size); ++ ++MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex); ++MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr); ++void mvSizePrint(MV_U32); ++ ++MV_U32 mvLog2(MV_U32 num); ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#endif /* __INCmvCommonh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvDebug.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,326 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++ ++/* includes */ ++#include "mvOs.h" ++#include "mv802_3.h" ++#include "mvCommon.h" ++#include "mvDebug.h" ++ ++/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros ++ * mvDebug - map of bits (one for each module) bit=1 means enable ++ * debug code and messages for this module ++ * mvModuleDebug - array of 32 bits varables one for each module ++ */ ++MV_U32 mvDebug = 0; ++MV_U32 mvDebugModules[MV_MODULE_MAX]; ++ ++/* Init mvModuleDebug array to default values */ ++void mvDebugInit(void) ++{ ++ int bit; ++ ++ mvDebug = 0; ++ for(bit=0; bit 0) ++ { ++ mvOsPrintf("%08x: ", memAddr); ++ i = 0; ++ /* 32 bytes in the line */ ++ while(i < 32) ++ { ++ if(memAddr >= (MV_U32)addr) ++ { ++ switch(access) ++ { ++ case 1: ++ if( memAddr == CPU_PHY_MEM(memAddr) ) ++ { ++ mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); ++ } ++ else ++ { ++ mvOsPrintf("%02x ", *((MV_U8*)memAddr)); ++ } ++ break; ++ ++ case 2: ++ if( memAddr == CPU_PHY_MEM(memAddr) ) ++ { ++ mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); ++ } ++ else ++ { ++ mvOsPrintf("%04x ", *((MV_U16*)memAddr)); ++ } ++ break; ++ ++ case 4: ++ if( memAddr == CPU_PHY_MEM(memAddr) ) ++ { ++ mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); ++ } ++ else ++ { ++ mvOsPrintf("%08x ", *((MV_U32*)memAddr)); ++ } ++ break; ++ } ++ } ++ else ++ { ++ for(j=0; j<(access*2+1); j++) ++ mvOsPrintf(" "); ++ } ++ i += access; ++ memAddr += access; ++ size -= access; ++ if(size <= 0) ++ break; ++ } ++ mvOsPrintf("\n"); ++ } ++} ++ ++void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access) ++{ ++ if(pBufInfo == NULL) ++ { ++ mvOsPrintf("\n!!! pBufInfo = NULL\n"); ++ return; ++ } ++ mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", ++ (unsigned int)pBufInfo, ++ (unsigned int)pBufInfo->cmdSts, ++ (unsigned int)pBufInfo->pBuff, ++ (unsigned int)pBufInfo->bufSize); ++ mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", ++ (unsigned int)pBufInfo->pData, ++ (unsigned int)pBufInfo->byteCnt, ++ (unsigned int)pBufInfo->pNextBufInfo, ++ (unsigned int)pBufInfo->userInfo1, ++ (unsigned int)pBufInfo->userInfo2); ++ if(pBufInfo->pData != NULL) ++ { ++ if(size > pBufInfo->byteCnt) ++ size = pBufInfo->byteCnt; ++ mvDebugMemDump(pBufInfo->pData, size, access); ++ } ++} ++ ++void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access) ++{ ++ int frag, len; ++ ++ if(pPktInfo == NULL) ++ { ++ mvOsPrintf("\n!!! pPktInfo = NULL\n"); ++ return; ++ } ++ mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", ++ pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, ++ pPktInfo->pFrags, pPktInfo->osInfo); ++ ++ for(frag=0; fragnumFrags; frag++) ++ { ++ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", ++ frag, pPktInfo->pFrags[frag].bufVirtPtr, ++ pPktInfo->pFrags[frag].bufSize); ++ if(size > 0) ++ { ++ len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); ++ mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); ++ size -= len; ++ } ++ } ++ ++} ++ ++void mvDebugPrintIpAddr(MV_U32 ipAddr) ++{ ++ mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), ++ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); ++} ++ ++void mvDebugPrintMacAddr(const MV_U8* pMacAddr) ++{ ++ int i; ++ ++ mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); ++ for(i=1; ibegin = 0; ++ pTimeEntry->count = count; ++ pTimeEntry->end = 0; ++ pTimeEntry->left = pTimeEntry->count; ++ pTimeEntry->total = 0; ++ pTimeEntry->min = 0xFFFFFFFF; ++ pTimeEntry->max = 0x0; ++ strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1); ++ pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0'; ++} ++ ++/* Print out MV_DEBUG_TIMES entry */ ++void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle) ++{ ++ int num; ++ ++ if(isTitle == MV_TRUE) ++ mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); ++ ++ num = pTimeEntry->count-pTimeEntry->left; ++ if(num > 0) ++ { ++ mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", ++ pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num, ++ pTimeEntry->min, pTimeEntry->max); ++ } ++} ++ ++/* Update MV_DEBUG_TIMES entry */ ++void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry) ++{ ++ MV_U32 delta; ++ ++ if(pTimeEntry->left > 0) ++ { ++ if(pTimeEntry->end <= pTimeEntry->begin) ++ { ++ delta = pTimeEntry->begin - pTimeEntry->end; ++ } ++ else ++ { ++ delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin; ++ } ++ pTimeEntry->total += delta; ++ ++ if(delta < pTimeEntry->min) ++ pTimeEntry->min = delta; ++ ++ if(delta > pTimeEntry->max) ++ pTimeEntry->max = delta; ++ ++ pTimeEntry->left--; ++ } ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvDebug.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,178 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++ ++#ifndef __INCmvDebugh ++#define __INCmvDebugh ++ ++/* includes */ ++#include "mvTypes.h" ++ ++typedef enum ++{ ++ MV_MODULE_INVALID = -1, ++ MV_MODULE_ETH = 0, ++ MV_MODULE_IDMA, ++ MV_MODULE_XOR, ++ MV_MODULE_TWASI, ++ MV_MODULE_MGI, ++ MV_MODULE_USB, ++ MV_MODULE_CESA, ++ ++ MV_MODULE_MAX ++}MV_MODULE_ID; ++ ++/* Define generic flags useful for most of modules */ ++#define MV_DEBUG_FLAG_ALL (0) ++#define MV_DEBUG_FLAG_INIT (1 << 0) ++#define MV_DEBUG_FLAG_RX (1 << 1) ++#define MV_DEBUG_FLAG_TX (1 << 2) ++#define MV_DEBUG_FLAG_ERR (1 << 3) ++#define MV_DEBUG_FLAG_TRACE (1 << 4) ++#define MV_DEBUG_FLAG_DUMP (1 << 5) ++#define MV_DEBUG_FLAG_CACHE (1 << 6) ++#define MV_DEBUG_FLAG_IOCTL (1 << 7) ++#define MV_DEBUG_FLAG_STATS (1 << 8) ++ ++extern MV_U32 mvDebug; ++extern MV_U32 mvDebugModules[MV_MODULE_MAX]; ++ ++#ifdef MV_DEBUG ++# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg ++# define MV_DEBUG_CODE(module, flags, code) code ++#elif defined(MV_RT_DEBUG) ++# define MV_DEBUG_PRINT(module, flags, msg) \ ++ if( (mvDebug & (1<<(module))) && \ ++ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ ++ mvOsPrintf msg ++# define MV_DEBUG_CODE(module, flags, code) \ ++ if( (mvDebug & (1<<(module))) && \ ++ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ ++ code ++#else ++# define MV_DEBUG_PRINT(module, flags, msg) ++# define MV_DEBUG_CODE(module, flags, code) ++#endif ++ ++ ++ ++/* typedefs */ ++ ++/* time measurement structure used to check how much time pass between ++ * two points ++ */ ++typedef struct { ++ char name[20]; /* name of the entry */ ++ unsigned long begin; /* time measured on begin point */ ++ unsigned long end; /* time measured on end point */ ++ unsigned long total; /* Accumulated time */ ++ unsigned long left; /* The rest measurement actions */ ++ unsigned long count; /* Maximum measurement actions */ ++ unsigned long min; /* Minimum time from begin to end */ ++ unsigned long max; /* Maximum time from begin to end */ ++} MV_DEBUG_TIMES; ++ ++ ++/* mvDebug.h API list */ ++ ++/****** Error Recording ******/ ++ ++/* Dump memory in specific format: ++ * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 ++ */ ++void mvDebugMemDump(void* addr, int size, int access); ++ ++void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access); ++ ++void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access); ++ ++void mvDebugPrintIpAddr(MV_U32 ipAddr); ++ ++void mvDebugPrintMacAddr(const MV_U8* pMacAddr); ++ ++/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ ++ ++/* Reset MV_DEBUG_TIMES entry */ ++void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name); ++ ++/* Update MV_DEBUG_TIMES entry */ ++void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry); ++ ++/* Print out MV_DEBUG_TIMES entry */ ++void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle); ++ ++ ++/******** General ***********/ ++ ++/* Change value of mvDebugPrint global variable */ ++ ++void mvDebugInit(void); ++void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); ++void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); ++void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); ++ ++ ++#endif /* __INCmvDebug.h */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,225 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDeviceIdh ++#define __INCmvDeviceIdh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* defines */ ++#define MARVELL_VEN_ID 0x11ab ++ ++/* Disco-3 */ ++#define MV64460_DEV_ID 0x6480 ++#define MV64460B_DEV_ID 0x6485 ++#define MV64430_DEV_ID 0x6420 ++ ++/* Disco-5 */ ++#define MV64560_DEV_ID 0x6450 ++ ++/* Disco-6 */ ++#define MV64660_DEV_ID 0x6460 ++ ++/* Orion */ ++#define MV_1181_DEV_ID 0x1181 ++#define MV_5181_DEV_ID 0x5181 ++#define MV_5281_DEV_ID 0x5281 ++#define MV_5182_DEV_ID 0x5182 ++#define MV_8660_DEV_ID 0x8660 ++#define MV_5180_DEV_ID 0x5180 ++#define MV_5082_DEV_ID 0x5082 ++#define MV_1281_DEV_ID 0x1281 ++#define MV_6082_DEV_ID 0x6082 ++#define MV_6183_DEV_ID 0x6183 ++#define MV_6183L_DEV_ID 0x6083 ++ ++#define MV_5281_D0_REV 0x4 ++#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) ++#define MV_5281_D0_NAME "88F5281 D0" ++ ++#define MV_5281_D1_REV 0x5 ++#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) ++#define MV_5281_D1_NAME "88F5281 D1" ++ ++#define MV_5281_D2_REV 0x6 ++#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) ++#define MV_5281_D2_NAME "88F5281 D2" ++ ++ ++#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ ++#define MV_5181_A1_REV 0x1 /* for USB Er ..*/ ++#define MV_5181_B0_REV 0x2 ++#define MV_5181_B1_REV 0x3 ++#define MV_5182_A1_REV 0x1 ++#define MV_5180N_B1_REV 0x3 ++#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) ++ ++ ++ ++/* kw */ ++#define MV_6281_DEV_ID 0x6281 ++#define MV_6192_DEV_ID 0x6192 ++#define MV_6190_DEV_ID 0x6190 ++#define MV_6180_DEV_ID 0x6180 ++ ++#define MV_6281_A0_REV 0x2 ++#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) ++#define MV_6281_A0_NAME "88F6281 A0" ++ ++#define MV_6192_A0_REV 0x2 ++#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) ++#define MV_6192_A0_NAME "88F6192 A0" ++ ++#define MV_6190_A0_REV 0x2 ++#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) ++#define MV_6190_A0_NAME "88F6190 A0" ++ ++#define MV_6180_A0_REV 0x2 ++#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) ++#define MV_6180_A0_NAME "88F6180 A0" ++ ++#define MV_6281_A1_REV 0x3 ++#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) ++#define MV_6281_A1_NAME "88F6281 A1" ++ ++#define MV_6192_A1_REV 0x3 ++#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) ++#define MV_6192_A1_NAME "88F6192 A1" ++ ++#define MV_6190_A1_REV 0x3 ++#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) ++#define MV_6190_A1_NAME "88F6190 A1" ++ ++#define MV_6180_A1_REV 0x3 ++#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) ++#define MV_6180_A1_NAME "88F6180 A1" ++ ++#define MV_88F6XXX_A0_REV 0x2 ++#define MV_88F6XXX_A1_REV 0x3 ++/* Disco-Duo */ ++#define MV_78XX0_ZY_DEV_ID 0x6381 ++#define MV_78XX0_ZY_NAME "MV78X00" ++ ++#define MV_78XX0_Z0_REV 0x1 ++#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) ++#define MV_78XX0_Z0_NAME "78X00 Z0" ++ ++#define MV_78XX0_Y0_REV 0x2 ++#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) ++#define MV_78XX0_Y0_NAME "78X00 Y0" ++ ++#define MV_78XX0_DEV_ID 0x7800 ++#define MV_78XX0_NAME "MV78X00" ++ ++#define MV_76100_DEV_ID 0x7610 ++#define MV_78200_DEV_ID 0x7820 ++#define MV_78100_DEV_ID 0x7810 ++#define MV_78XX0_A0_REV 0x1 ++#define MV_78XX0_A1_REV 0x2 ++ ++#define MV_76100_NAME "MV76100" ++#define MV_78100_NAME "MV78100" ++#define MV_78200_NAME "MV78200" ++ ++#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) ++#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) ++#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) ++ ++#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) ++#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) ++#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) ++ ++#define MV_76100_A0_NAME "MV76100 A0" ++#define MV_78100_A0_NAME "MV78100 A0" ++#define MV_78200_A0_NAME "MV78200 A0" ++#define MV_78XX0_A0_NAME "MV78XX0 A0" ++ ++#define MV_76100_A1_NAME "MV76100 A1" ++#define MV_78100_A1_NAME "MV78100 A1" ++#define MV_78200_A1_NAME "MV78200 A1" ++#define MV_78XX0_A1_NAME "MV78XX0 A1" ++ ++/*MV88F632X family*/ ++#define MV_6321_DEV_ID 0x6321 ++#define MV_6322_DEV_ID 0x6322 ++#define MV_6323_DEV_ID 0x6323 ++ ++#define MV_6321_NAME "88F6321" ++#define MV_6322_NAME "88F6322" ++#define MV_6323_NAME "88F6323" ++ ++#define MV_632X_A1_REV 0x2 ++ ++#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) ++#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) ++#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) ++ ++#define MV_6321_A1_NAME "88F6321 A1" ++#define MV_6322_A1_NAME "88F6322 A1" ++#define MV_6323_A1_NAME "88F6323 A1" ++ ++ ++#endif /* __INCmvDeviceIdh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,73 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvHalVerh ++#define __INCmvHalVerh ++ ++/* Defines */ ++#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7" ++#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4" ++ ++#endif /* __INCmvHalVerh */ +\ No newline at end of file +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvStack.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvStack.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,100 @@ ++/******************************************************************************* ++* Copyright 2003, Marvell Semiconductor Israel LTD. * ++* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * ++* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * ++* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * ++* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * ++* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * ++* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * ++* * ++* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * ++* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * ++* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * ++* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * ++******************************************************************************** ++* mvQueue.c ++* ++* FILENAME: $Workfile: mvStack.c $ ++* REVISION: $Revision: 1.1 $ ++* LAST UPDATE: $Modtime: $ ++* ++* DESCRIPTION: ++* This file implements simple Stack LIFO functionality. ++*******************************************************************************/ ++ ++/* includes */ ++#include "mvOs.h" ++#include "mvTypes.h" ++#include "mvDebug.h" ++#include "mvStack.h" ++ ++/* defines */ ++ ++ ++/* Public functions */ ++ ++ ++/* Purpose: Create new stack ++ * Inputs: ++ * - MV_U32 noOfElements - maximum number of elements in the stack. ++ * Each element 4 bytes size ++ * Return: void* - pointer to created stack. ++ */ ++void* mvStackCreate(int numOfElements) ++{ ++ MV_STACK* pStack; ++ MV_U32* pStackElements; ++ ++ pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK)); ++ pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32)); ++ if( (pStack == NULL) || (pStackElements == NULL) ) ++ { ++ mvOsPrintf("mvStack: Can't create new stack\n"); ++ return NULL; ++ } ++ memset(pStackElements, 0, numOfElements*sizeof(MV_U32)); ++ pStack->numOfElements = numOfElements; ++ pStack->stackIdx = 0; ++ pStack->stackElements = pStackElements; ++ ++ return pStack; ++} ++ ++/* Purpose: Delete existing stack ++ * Inputs: ++ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function ++ * ++ * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. ++ * MV_OK - Success. ++ */ ++MV_STATUS mvStackDelete(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ if( (pStack == NULL) || (pStack->stackElements == NULL) ) ++ return MV_NOT_FOUND; ++ ++ mvOsFree(pStack->stackElements); ++ mvOsFree(pStack); ++ ++ return MV_OK; ++} ++ ++ ++/* PrintOut status of the stack */ ++void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements) ++{ ++ int i; ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", ++ stackHndl, pStack->stackElements, pStack->numOfElements, ++ pStack->stackIdx); ++ if(isPrintElements == MV_TRUE) ++ { ++ for(i=0; istackIdx; i++) ++ { ++ mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); ++ } ++ } ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvStack.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvStack.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,140 @@ ++/******************************************************************************* ++* Copyright 2003, Marvell Semiconductor Israel LTD. * ++* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * ++* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * ++* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * ++* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * ++* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * ++* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * ++* * ++* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * ++* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * ++* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * ++* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * ++******************************************************************************** ++* mvStack.h - Header File for : ++* ++* FILENAME: $Workfile: mvStack.h $ ++* REVISION: $Revision: 1.1 $ ++* LAST UPDATE: $Modtime: $ ++* ++* DESCRIPTION: ++* This file defines simple Stack (LIFO) functionality. ++* ++*******************************************************************************/ ++ ++#ifndef __mvStack_h__ ++#define __mvStack_h__ ++ ++ ++/* includes */ ++#include "mvTypes.h" ++ ++ ++/* defines */ ++ ++ ++/* typedefs */ ++/* Data structure describes general purpose Stack */ ++typedef struct ++{ ++ int stackIdx; ++ int numOfElements; ++ MV_U32* stackElements; ++} MV_STACK; ++ ++static INLINE MV_BOOL mvStackIsFull(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ if(pStack->stackIdx == pStack->numOfElements) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ if(pStack->stackIdx == 0) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++/* Purpose: Push new element to stack ++ * Inputs: ++ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. ++ * - MV_U32 value - New element. ++ * ++ * Return: MV_STATUS MV_FULL - Failure. Stack is full. ++ * MV_OK - Success. Element is put to stack. ++ */ ++static INLINE void mvStackPush(void* stackHndl, MV_U32 value) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++#ifdef MV_RT_DEBUG ++ if(pStack->stackIdx == pStack->numOfElements) ++ { ++ mvOsPrintf("mvStackPush: Stack is FULL\n"); ++ return; ++ } ++#endif /* MV_RT_DEBUG */ ++ ++ pStack->stackElements[pStack->stackIdx] = value; ++ pStack->stackIdx++; ++} ++ ++/* Purpose: Pop element from the top of stack and copy it to "pValue" ++ * Inputs: ++ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. ++ * - MV_U32 value - Element in the top of stack. ++ * ++ * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. ++ * MV_OK - Success. Element is removed from the stack and ++ * copied to pValue argument ++ */ ++static INLINE MV_U32 mvStackPop(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++#ifdef MV_RT_DEBUG ++ if(pStack->stackIdx == 0) ++ { ++ mvOsPrintf("mvStackPop: Stack is EMPTY\n"); ++ return 0; ++ } ++#endif /* MV_RT_DEBUG */ ++ ++ pStack->stackIdx--; ++ return pStack->stackElements[pStack->stackIdx]; ++} ++ ++static INLINE int mvStackIndex(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ return pStack->stackIdx; ++} ++ ++static INLINE int mvStackFreeElements(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ return (pStack->numOfElements - pStack->stackIdx); ++} ++ ++/* mvStack.h API list */ ++ ++/* Create new Stack */ ++void* mvStackCreate(int numOfElements); ++ ++/* Delete existing stack */ ++MV_STATUS mvStackDelete(void* stackHndl); ++ ++/* Print status of the stack */ ++void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements); ++ ++#endif /* __mvStack_h__ */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvTypes.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,245 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvTypesh ++#define __INCmvTypesh ++ ++/* Defines */ ++ ++/* The following is a list of Marvell status */ ++#define MV_ERROR (-1) ++#define MV_OK (0x00) /* Operation succeeded */ ++#define MV_FAIL (0x01) /* Operation failed */ ++#define MV_BAD_VALUE (0x02) /* Illegal value (general) */ ++#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ ++#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ ++#define MV_BAD_PTR (0x05) /* Illegal pointer value */ ++#define MV_BAD_SIZE (0x06) /* Illegal size */ ++#define MV_BAD_STATE (0x07) /* Illegal state of state machine */ ++#define MV_SET_ERROR (0x08) /* Set operation failed */ ++#define MV_GET_ERROR (0x09) /* Get operation failed */ ++#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ ++#define MV_NOT_FOUND (0x0B) /* Item not found */ ++#define MV_NO_MORE (0x0C) /* No more items found */ ++#define MV_NO_SUCH (0x0D) /* No such item */ ++#define MV_TIMEOUT (0x0E) /* Time Out */ ++#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ ++#define MV_NOT_SUPPORTED (0x10) /* This request is not support */ ++#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */ ++#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ ++#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ ++#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ ++#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ ++#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ ++#define MV_HW_ERROR (0x17) /* Hardware error */ ++#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ ++#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ ++#define MV_NOT_READY (0x1A) /* The other side is not ready yet */ ++#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ ++#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ ++#define MV_NOT_STARTED (0x1D) /* Not started yet */ ++#define MV_BUSY (0x1E) /* Item is busy. */ ++#define MV_TERMINATE (0x1F) /* Item terminates it's work. */ ++#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ ++#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ ++#define MV_WRITE_PROTECT (0x22) /* Write protected */ ++ ++ ++#define MV_INVALID (int)(-1) ++ ++#define MV_FALSE 0 ++#define MV_TRUE (!(MV_FALSE)) ++ ++ ++#ifndef NULL ++#define NULL ((void*)0) ++#endif ++ ++ ++#ifndef MV_ASMLANGUAGE ++/* typedefs */ ++ ++typedef char MV_8; ++typedef unsigned char MV_U8; ++ ++typedef int MV_32; ++typedef unsigned int MV_U32; ++ ++typedef short MV_16; ++typedef unsigned short MV_U16; ++ ++#ifdef MV_PPC64 ++typedef long MV_64; ++typedef unsigned long MV_U64; ++#else ++typedef long long MV_64; ++typedef unsigned long long MV_U64; ++#endif ++ ++typedef long MV_LONG; /* 32/64 */ ++typedef unsigned long MV_ULONG; /* 32/64 */ ++ ++typedef int MV_STATUS; ++typedef int MV_BOOL; ++typedef void MV_VOID; ++typedef float MV_FLOAT; ++ ++typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ ++typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ ++typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/ ++typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ ++ ++typedef MV_U32 MV_KHZ; ++typedef MV_U32 MV_MHZ; ++typedef MV_U32 MV_HZ; ++ ++ ++/* This enumerator describes the set of commands that can be applied on */ ++/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ ++/* status (see MV_STATE enumerator) */ ++/* Start can be applied only when status is IDLE */ ++/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ ++/* Pause can be applied only when status is ACTIVE */ ++/* Restart can be applied only when status is PAUSED */ ++typedef enum _mvCommand ++{ ++ MV_START, /* Start */ ++ MV_STOP, /* Stop */ ++ MV_PAUSE, /* Pause */ ++ MV_RESTART /* Restart */ ++} MV_COMMAND; ++ ++/* This enumerator describes the set of state conditions. */ ++/* Moving from one state to other is stricted. */ ++typedef enum _mvState ++{ ++ MV_IDLE, ++ MV_ACTIVE, ++ MV_PAUSED, ++ MV_UNDEFINED_STATE ++} MV_STATE; ++ ++ ++/* This structure describes address space window. Window base can be */ ++/* 64 bit, window size up to 4GB */ ++typedef struct _mvAddrWin ++{ ++ MV_U32 baseLow; /* 32bit base low */ ++ MV_U32 baseHigh; /* 32bit base high */ ++ MV_U32 size; /* 32bit size */ ++}MV_ADDR_WIN; ++ ++/* This binary enumerator describes protection attribute status */ ++typedef enum _mvProtRight ++{ ++ ALLOWED, /* Protection attribute allowed */ ++ FORBIDDEN /* Protection attribute forbidden */ ++}MV_PROT_RIGHT; ++ ++/* Unified struct for Rx and Tx packet operations. The user is required to */ ++/* be familier only with Tx/Rx descriptor command status. */ ++typedef struct _bufInfo ++{ ++ MV_U32 cmdSts; /* Tx/Rx command status */ ++ MV_U16 byteCnt; /* Size of valid data in the buffer */ ++ MV_U16 bufSize; /* Total size of the buffer */ ++ MV_U8 *pBuff; /* Pointer to Buffer */ ++ MV_U8 *pData; /* Pointer to data in the Buffer */ ++ MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ ++ MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ ++ struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ ++} BUF_INFO; ++ ++/* This structure contains information describing one of buffers ++ * (fragments) they are built Ethernet packet. ++ */ ++typedef struct ++{ ++ MV_U8* bufVirtPtr; ++ MV_ULONG bufPhysAddr; ++ MV_U32 bufSize; ++ MV_U32 dataSize; ++ MV_U32 memHandle; ++ MV_32 bufAddrShift; ++} MV_BUF_INFO; ++ ++/* This structure contains information describing Ethernet packet. ++ * The packet can be divided for few buffers (fragments) ++ */ ++typedef struct ++{ ++ MV_ULONG osInfo; ++ MV_BUF_INFO *pFrags; ++ MV_U32 status; ++ MV_U16 pktSize; ++ MV_U16 numFrags; ++ MV_U32 ownerId; ++ MV_U32 fragIP; ++} MV_PKT_INFO; ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++#endif /* __INCmvTypesh */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/dbg-trace.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/dbg-trace.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,110 @@ ++#include ++#include ++#include ++#include "dbg-trace.h" ++ ++#define TRACE_ARR_LEN 800 ++#define STR_LEN 128 ++struct trace { ++ struct timeval tv; ++ char str[STR_LEN]; ++ unsigned int callback_val1; ++ unsigned int callback_val2; ++ char valid; ++}; ++static unsigned int (*trc_callback1) (unsigned char) = NULL; ++static unsigned int (*trc_callback2) (unsigned char) = NULL; ++static unsigned char trc_param1 = 0; ++static unsigned char trc_param2 = 0; ++struct trace *trc_arr; ++static int trc_index; ++static int trc_active = 0; ++ ++void TRC_START() ++{ ++ trc_active = 1; ++} ++ ++void TRC_STOP() ++{ ++ trc_active = 0; ++} ++ ++void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param) ++{ ++ printk("Marvell debug tracing is on\n"); ++ trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL); ++ if(trc_arr == NULL) ++ { ++ printk("Can't allocate Debug Trace buffer\n"); ++ return; ++ } ++ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); ++ trc_index = 0; ++ trc_callback1 = callback1; ++ trc_callback2 = callback2; ++ trc_param1 = callback1_param; ++ trc_param2 = callback2_param; ++} ++void TRC_REC(char *fmt,...) ++{ ++ va_list args; ++ struct trace *trc = &trc_arr[trc_index]; ++ ++ if(trc_active == 0) ++ return; ++ ++ do_gettimeofday(&trc->tv); ++ if(trc_callback1) ++ trc->callback_val1 = trc_callback1(trc_param1); ++ if(trc_callback2) ++ trc->callback_val2 = trc_callback2(trc_param2); ++ va_start(args, fmt); ++ vsprintf(trc->str,fmt,args); ++ va_end(args); ++ trc->valid = 1; ++ if((++trc_index) == TRACE_ARR_LEN) { ++ trc_index = 0; ++ } ++} ++void TRC_OUTPUT(void) ++{ ++ int i,j; ++ struct trace *p; ++ printk("\n\nTrace %d items\n",TRACE_ARR_LEN); ++ for(i=0,j=trc_index; ivalid) { ++ unsigned long uoffs; ++ struct trace *plast; ++ if(p == &trc_arr[0]) ++ plast = &trc_arr[TRACE_ARR_LEN-1]; ++ else ++ plast = p-1; ++ if(p->tv.tv_sec == ((plast)->tv.tv_sec)) ++ uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec)); ++ else ++ uoffs = (1000000 - ((plast)->tv.tv_usec)) + ++ ((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) + ++ p->tv.tv_usec; ++ printk("%03d: [+%ld usec]", j, (unsigned long)uoffs); ++ if(trc_callback1) ++ printk("[%u]",p->callback_val1); ++ if(trc_callback2) ++ printk("[%u]",p->callback_val2); ++ printk(": %s",p->str); ++ } ++ p->valid = 0; ++ } ++ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); ++ trc_index = 0; ++} ++void TRC_RELEASE(void) ++{ ++ kfree(trc_arr); ++ trc_index = 0; ++} ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/dbg-trace.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/dbg-trace.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,24 @@ ++ ++#ifndef _MV_DBG_TRCE_H_ ++#define _MV_DBG_TRCE_H_ ++ ++#ifdef CONFIG_MV_DBG_TRACE ++void TRC_INIT(void *callback1, void *callback2, ++ unsigned char callback1_param, unsigned char callback2_param); ++void TRC_REC(char *fmt,...); ++void TRC_OUTPUT(void); ++void TRC_RELEASE(void); ++void TRC_START(void); ++void TRC_STOP(void); ++ ++#else ++#define TRC_INIT(x1,x2,x3,x4) ++#define TRC_REC(X...) ++#define TRC_OUTPUT() ++#define TRC_RELEASE() ++#define TRC_START() ++#define TRC_STOP() ++#endif ++ ++ ++#endif +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,2513 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "boardEnv/mvBoardEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "cpu/mvCpu.h" ++#include "cntmr/mvCntmr.h" ++#include "gpp/mvGpp.h" ++#include "twsi/mvTwsi.h" ++#include "pex/mvPex.h" ++#include "device/mvDevice.h" ++#include "eth/gbe/mvEthRegs.h" ++ ++/* defines */ ++/* #define MV_DEBUG */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++extern MV_CPU_ARM_CLK _cpuARMDDRCLK[]; ++ ++#define CODE_IN_ROM MV_FALSE ++#define CODE_IN_RAM MV_TRUE ++ ++extern MV_BOARD_INFO* boardInfoTbl[]; ++#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] ++ ++/* Locals */ ++static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++ ++MV_U32 tClkRate = -1; ++ ++ ++/******************************************************************************* ++* mvBoardEnvInit - Init board ++* ++* DESCRIPTION: ++* In this function the board environment take care of device bank ++* initialization. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvBoardEnvInit(MV_VOID) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); ++ return; ++ ++ } ++ ++ /* Set GPP Out value */ ++ MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); ++ MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh); ++ ++ /* set GPP polarity */ ++ mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); ++ mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); ++ ++ /* Workaround for Erratum FE-MISC-70*/ ++ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV) ++ { ++ BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd; ++ BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002; ++ } /*End of WA*/ ++ ++ /* Set GPP Out Enable*/ ++ mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); ++ mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); ++ ++ /* Nand CE */ ++ MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT); ++} ++ ++/******************************************************************************* ++* mvBoardModelGet - Get Board model ++* ++* DESCRIPTION: ++* This function returns 16bit describing board model. ++* Board model is constructed of one byte major and minor numbers in the ++* following manner: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* String describing board model. ++* ++*******************************************************************************/ ++MV_U16 mvBoardModelGet(MV_VOID) ++{ ++ return (mvBoardIdGet() >> 16); ++} ++ ++/******************************************************************************* ++* mbBoardRevlGet - Get Board revision ++* ++* DESCRIPTION: ++* This function returns a 32bit describing the board revision. ++* Board revision is constructed of 4bytes. 2bytes describes major number ++* and the other 2bytes describes minor munber. ++* For example for board revision 3.4 the function will return ++* 0x00030004. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* String describing board model. ++* ++*******************************************************************************/ ++MV_U16 mvBoardRevGet(MV_VOID) ++{ ++ return (mvBoardIdGet() & 0xFFFF); ++} ++ ++/******************************************************************************* ++* mvBoardNameGet - Get Board name ++* ++* DESCRIPTION: ++* This function returns a string describing the board model and revision. ++* String is extracted from board I2C EEPROM. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. ++* ++* RETURN: ++* ++* MV_ERROR if informantion can not be read. ++*******************************************************************************/ ++MV_STATUS mvBoardNameGet(char *pNameBuff) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsSPrintf (pNameBuff, "Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardIsPortInSgmii - ++* ++* DESCRIPTION: ++* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE ++* For all other options. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE - port in SGMII. ++* MV_FALSE - other. ++* ++*******************************************************************************/ ++MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) ++{ ++ MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; ++ ++ if(ethPortNum >= BOARD_ETH_PORT_NUM) ++ { ++ mvOsPrintf ("Invalid portNo=%d\n", ethPortNum); ++ return MV_FALSE; ++ } ++ return ethPortSgmiiSupport[ethPortNum]; ++} ++ ++/******************************************************************************* ++* mvBoardIsPortInGmii - ++* ++* DESCRIPTION: ++* This routine returns MV_TRUE for port number works in GMII or MV_FALSE ++* For all other options. ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE - port in GMII. ++* MV_FALSE - other. ++* ++*******************************************************************************/ ++MV_BOOL mvBoardIsPortInGmii(MV_VOID) ++{ ++ MV_U32 devClassId, devClass = 0; ++ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) ++ { ++ /* Get MPP module ID */ ++ devClassId = mvBoarModuleTypeGet(devClass); ++ if (MV_BOARD_MODULE_GMII_ID == devClassId) ++ return MV_TRUE; ++ } ++ else if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++/******************************************************************************* ++* mvBoardPhyAddrGet - Get the phy address ++* ++* DESCRIPTION: ++* This routine returns the Phy address of a given ethernet port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing Phy address, -1 if the port number is wrong. ++* ++*******************************************************************************/ ++MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; ++} ++ ++/******************************************************************************* ++* mvBoardMacSpeedGet - Get the Mac speed ++* ++* DESCRIPTION: ++* This routine returns the Mac speed if pre define of a given ethernet port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. ++* ++*******************************************************************************/ ++MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; ++} ++ ++/******************************************************************************* ++* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication ++* ++* DESCRIPTION: ++* This routine returns the IRQ number for the link status indication. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the number of the IRQ for the link status indication, -1 if the port ++* number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq; ++} ++ ++/******************************************************************************* ++* mvBoardSwitchPortGet - Get the mapping between the board connector and the ++* Ethernet Switch port ++* ++* DESCRIPTION: ++* This routine returns the matching Switch port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* boardPortNum - logical number of the connector on the board ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the matching Switch port, -1 if the port number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) ++ { ++ mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum]; ++} ++ ++/******************************************************************************* ++* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port ++* ++* DESCRIPTION: ++* This routine returns the Switch CPU port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the Switch CPU port, -1 if the port number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort; ++} ++ ++/******************************************************************************* ++* mvBoardIsSwitchConnected - Get switch connection status ++* DESCRIPTION: ++* This routine returns port's connection status ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 1 - if ethPortNum is connected to switch, 0 otherwise ++* ++*******************************************************************************/ ++MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) ++ { ++ mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum); ++ return MV_ERROR; ++ } ++ ++ if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo)) ++ return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum); ++ else ++ return 0; ++} ++/******************************************************************************* ++* mvBoardSmiScanModeGet - Get Switch SMI scan mode ++* ++* DESCRIPTION: ++* This routine returns Switch SMI scan mode. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode; ++} ++/******************************************************************************* ++* mvBoardSpecInitGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, ++* otherwise return MV_FALSE. ++* ++* ++*******************************************************************************/ ++ ++MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) ++{ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvBoardTclkGet - Get the board Tclk (Controller clock) ++* ++* DESCRIPTION: ++* This routine extract the controller core clock. ++* This function uses the controller counters to make identification. ++* Note: In order to avoid interference, make sure task context switch ++* and interrupts will not occure during this function operation ++* ++* INPUT: ++* countNum - Counter number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit clock cycles in Hertz. ++* ++*******************************************************************************/ ++MV_U32 mvBoardTclkGet(MV_VOID) ++{ ++ if(mvCtrlModelGet()==MV_6281_DEV_ID) ++ { ++#if defined(TCLK_AUTO_DETECT) ++ MV_U32 tmpTClkRate = MV_BOARD_TCLK_166MHZ; ++ ++ tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ tmpTClkRate &= MSAR_TCLCK_MASK; ++ ++ switch (tmpTClkRate) ++ { ++ case MSAR_TCLCK_166: ++ return MV_BOARD_TCLK_166MHZ; ++ break; ++ case MSAR_TCLCK_200: ++ return MV_BOARD_TCLK_200MHZ; ++ break; ++ } ++#else ++ return MV_BOARD_TCLK_200MHZ; ++#endif ++ } ++ ++ return MV_BOARD_TCLK_166MHZ; ++ ++} ++/******************************************************************************* ++* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) ++* ++* DESCRIPTION: ++* This routine extract the CPU bus clock. ++* ++* INPUT: ++* countNum - Counter number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit clock cycles in Hertz. ++* ++*******************************************************************************/ ++static MV_U32 mvBoard6180SysClkGet(MV_VOID) ++{ ++ MV_U32 sysClkRate=0; ++ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; ++ ++ sysClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ sysClkRate = sysClkRate & MSAR_CPUCLCK_MASK_6180; ++ sysClkRate = sysClkRate >> MSAR_CPUCLCK_OFFS_6180; ++ ++ sysClkRate = _cpu6180_ddr_l2_CLK[sysClkRate].ddrClk; ++ ++ return sysClkRate; ++ ++} ++ ++MV_U32 mvBoardSysClkGet(MV_VOID) ++{ ++#ifdef SYSCLK_AUTO_DETECT ++ MV_U32 sysClkRate, tmp, pClkRate, indexDdrRtio; ++ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; ++ MV_U32 ddrRtio[][2] = MV_DDR_CLCK_RTIO_TBL; ++ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return mvBoard6180SysClkGet(); ++ ++ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ pClkRate = MSAR_CPUCLCK_EXTRACT(tmp); ++ pClkRate = cpuCLK[pClkRate]; ++ ++ indexDdrRtio = tmp & MSAR_DDRCLCK_RTIO_MASK; ++ indexDdrRtio = indexDdrRtio >> MSAR_DDRCLCK_RTIO_OFFS; ++ if(ddrRtio[indexDdrRtio][0] != 0) ++ sysClkRate = ((pClkRate * ddrRtio[indexDdrRtio][1]) / ddrRtio[indexDdrRtio][0]); ++ else ++ sysClkRate = 0; ++ return sysClkRate; ++#else ++ return MV_BOARD_DEFAULT_SYSCLK; ++#endif ++} ++ ++ ++/******************************************************************************* ++* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number ++* ++* DESCRIPTION: ++* Multi-ported PCI Express bridges that is implemented on the board ++* collapse interrupts across multiple conventional PCI/PCI-X buses. ++* A dual-headed PCI Express bridge would map (or "swizzle") the ++* interrupts per the following table (in accordance with the respective ++* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD# ++* signals from its two logical PCI/PCI-X bridges, collapse the ++* INTA#-INTD# signals from any internal sources, and convert the ++* signals to in-band PCI Express messages. 10 ++* This function returns the upstream interrupt as it was converted by ++* the bridge, according to board configuration and the following table: ++* PCI dev num ++* Interrupt pin 7, 8, 9 ++* A -> A D C ++* B -> B A D ++* C -> C B A ++* D -> D C B ++* ++* ++* INPUT: ++* devNum - PCI/PCIX device number. ++* intPin - PCI Int pin ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Int pin connected to the Interrupt controller ++* ++*******************************************************************************/ ++MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin) ++{ ++ MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 ); ++ ++ if (realIntPin == 0) return 4; ++ else return realIntPin; ++ ++} ++ ++/******************************************************************************* ++* mvBoardDebugLedNumGet - Get number of debug Leds ++* ++* DESCRIPTION: ++* INPUT: ++* boardId ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) ++{ ++ return BOARD_INFO(boardId)->activeLedsNumber; ++} ++ ++/******************************************************************************* ++* mvBoardDebugLeg - Set the board debug Leds ++* ++* DESCRIPTION: turn on/off status leds. ++* Note: assume MPP leds are part of group 0 only. ++* ++* INPUT: ++* hexNum - Number to be displied in hex by Leds. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvBoardDebugLed(MV_U32 hexNum) ++{ ++ MV_U32 val = 0,totalMask, currentBitMask = 1,i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (BOARD_INFO(boardId)->pLedGppPin == NULL) ++ return; ++ ++ totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1; ++ hexNum &= totalMask; ++ totalMask = 0; ++ ++ for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++) ++ { ++ if (hexNum & currentBitMask) ++ { ++ val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); ++ } ++ ++ totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); ++ ++ currentBitMask = (currentBitMask << 1); ++ } ++ ++ if (BOARD_INFO(boardId)->ledsPolarity) ++ { ++ mvGppValueSet(0, totalMask, val); ++ } ++ else ++ { ++ mvGppValueSet(0, totalMask, ~val); ++ } ++} ++ ++ ++/******************************************************************************* ++* mvBoarGpioPinGet - mvBoarGpioPinGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* class - MV_BOARD_GPP_CLASS enum. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index) ++{ ++ MV_U32 boardId, i; ++ MV_U32 indexFound = 0; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) ++ if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) { ++ if (indexFound == index) ++ return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; ++ else ++ indexFound++; ++ ++ } ++ ++ return MV_ERROR; ++} ++ ++ ++/******************************************************************************* ++* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardRTCGpioPinGet(MV_VOID) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_RTC, 0); ++} ++ ++ ++/******************************************************************************* ++* mvBoardReset - mvBoardReset ++* ++* DESCRIPTION: ++* Reset the board ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None ++* ++*******************************************************************************/ ++MV_VOID mvBoardReset(MV_VOID) ++{ ++ MV_32 resetPin; ++ ++ /* Get gpp reset pin if define */ ++ resetPin = mvBoardResetGpioPinGet(); ++ if (resetPin != MV_ERROR) ++ { ++ MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); ++ MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); ++ ++ } ++ else ++ { ++ /* No gpp reset pin was found, try to reset ussing ++ system reset out */ ++ MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2); ++ MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); ++ } ++} ++ ++/******************************************************************************* ++* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardResetGpioPinGet(MV_VOID) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); ++} ++/******************************************************************************* ++* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet ++* ++* DESCRIPTION: ++* used for hotswap detection ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardSDIOGpioPinGet(MV_VOID) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_SDIO_DETECT, 0); ++} ++ ++/******************************************************************************* ++* mvBoardUSBVbusGpioPinGet - return Vbus input GPP ++* ++* DESCRIPTION: ++* ++* INPUT: ++* int devNo. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); ++} ++ ++/******************************************************************************* ++* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP ++* ++* DESCRIPTION: ++* ++* INPUT: ++* int devNo. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); ++} ++ ++ ++/******************************************************************************* ++* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins ++* ++* DESCRIPTION: ++* This function returns a 32-bit mask of GPP pins that connected to ++* interrupt generating sources on board. ++* For example if UART channel A is hardwired to GPP pin 8 and ++* UART channel B is hardwired to GPP pin 4 the fuinction will return ++* the value 0x000000110 ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* See description. The function return -1 if board is not identified. ++* ++*******************************************************************************/ ++MV_32 mvBoardGpioIntMaskLowGet(MV_VOID) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return BOARD_INFO(boardId)->intsGppMaskLow; ++} ++MV_32 mvBoardGpioIntMaskHighGet(MV_VOID) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return BOARD_INFO(boardId)->intsGppMaskHigh; ++} ++ ++ ++/******************************************************************************* ++* mvBoardMppGet - Get board dependent MPP register value ++* ++* DESCRIPTION: ++* MPP settings are derived from board design. ++* MPP group consist of 8 MPPs. An MPP group represent MPP ++* control register. ++* This function retrieves board dependend MPP register value. ++* ++* INPUT: ++* mppGroupNum - MPP group number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit value describing MPP control register value. ++* ++*******************************************************************************/ ++MV_32 mvBoardMppGet(MV_U32 mppGroupNum) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum]; ++} ++ ++ ++/******************************************************************************* ++* mvBoardMppGroupId - If MPP group type is AUTO then identify it using twsi ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppGroupIdUpdate(MV_VOID) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MODULE_ID_CLASS devClassId; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U32 maxMppGrp = 1; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ /* If MPP group can be defined by the module connected to it */ ++ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) ++ { ++ /* Get MPP module ID */ ++ devClassId = mvBoarModuleTypeGet(devClass); ++ if (MV_ERROR != devClassId) ++ { ++ switch(devClassId) ++ { ++ case MV_BOARD_MODULE_TDM_ID: ++ case MV_BOARD_MODULE_TDM_5CHAN_ID: ++ mppGroupType = MV_BOARD_TDM; ++ break; ++ case MV_BOARD_MODULE_AUDIO_ID: ++ mppGroupType = MV_BOARD_AUDIO; ++ break; ++ case MV_BOARD_MODULE_RGMII_ID: ++ mppGroupType = MV_BOARD_RGMII; ++ break; ++ case MV_BOARD_MODULE_GMII_ID: ++ mppGroupType = MV_BOARD_GMII; ++ break; ++ case MV_BOARD_MODULE_TS_ID: ++ mppGroupType = MV_BOARD_TS; ++ break; ++ case MV_BOARD_MODULE_MII_ID: ++ mppGroupType = MV_BOARD_MII; ++ break; ++ default: ++ mppGroupType = MV_BOARD_OTHER; ++ break; ++ } ++ } ++ else ++ /* The module bay is empty */ ++ mppGroupType = MV_BOARD_OTHER; ++ ++ /* Update MPP group type */ ++ mvBoardMppGroupTypeSet(devClass, mppGroupType); ++ } ++ ++ /* Update MPP output voltage for RGMII 1.8V. Set port to GMII for GMII module */ ++ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_RGMII)) ++ MV_REG_BIT_SET(MPP_OUTPUT_DRIVE_REG,MPP_1_8_RGMII1_OUTPUT_DRIVE | MPP_1_8_RGMII0_OUTPUT_DRIVE); ++ else ++ { ++ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII)) ++ { ++ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); ++ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(0),BIT3); ++ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); ++ } ++ else if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_MII)) ++ { ++ /* Assumption that the MDC & MDIO should be 3.3V */ ++ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); ++ /* Assumption that only ETH1 can be MII when using modules on DB */ ++ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); ++ } ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvBoardMppGroupTypeGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) ++ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1; ++ else ++ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2; ++} ++ ++/******************************************************************************* ++* mvBoardMppGroupTypeSet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. ++* mppGroupType - MPP group type for MPP[35:20] or for MPP[49:36]. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); ++ } ++ ++ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) ++ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1 = mppGroupType; ++ else ++ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2 = mppGroupType; ++ ++} ++ ++/******************************************************************************* ++* mvBoardMppMuxSet - Update MPP mux ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppMuxSet(MV_VOID) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U8 muxVal = 0xf; ++ MV_U32 maxMppGrp = 1; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ mppGroupType = mvBoardMppGroupTypeGet(devClass); ++ ++ switch(mppGroupType) ++ { ++ case MV_BOARD_TDM: ++ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); ++ break; ++ case MV_BOARD_AUDIO: ++ muxVal &= ~(devClass ? 0x7 : 0x0); /*old Z0 value 0xd:0x0*/ ++ break; ++ case MV_BOARD_TS: ++ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); ++ break; ++ default: ++ muxVal |= (devClass ? 0xf : 0); ++ break; ++ } ++ } ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); ++ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 2; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 6; ++ muxVal = 0; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ ++} ++ ++/******************************************************************************* ++* mvBoardTdmMppSet - set MPPs in TDM module ++* ++* DESCRIPTION: ++* ++* INPUT: type of second telephony device ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardTdmMppSet(MV_32 chType) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U8 muxVal = 1; ++ MV_U8 muxValMask = 1; ++ MV_U8 twsiVal; ++ MV_U32 maxMppGrp = 1; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ mppGroupType = mvBoardMppGroupTypeGet(devClass); ++ if(mppGroupType == MV_BOARD_TDM) ++ break; ++ } ++ ++ if(devClass == maxMppGrp) ++ return; /* TDM module not found */ ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if(mvBoardIdGet() == RD_88F6281A_ID) ++ { ++ muxVal = 0xc; ++ muxValMask = 0xf3; ++ } ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxValMask) | muxVal; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp out val fail\n"); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ muxVal = 0xfe; ++ if(mvBoardIdGet() == RD_88F6281A_ID) ++ muxVal = 0xf3; ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxVal); ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp change to out fail\n"); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ /* reset the line to 0 */ ++ twsiSlave.offset = 3; ++ muxVal = 0; ++ muxValMask = 1; ++ ++ if(mvBoardIdGet() == RD_88F6281A_ID) { ++ muxVal = 0x0; ++ muxValMask = 0xf3; ++ } ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxValMask) | muxVal; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp out val fail\n"); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ mvOsDelay(20); ++ ++ /* set the line to 1 */ ++ twsiSlave.offset = 3; ++ muxVal = 1; ++ muxValMask = 1; ++ ++ if(mvBoardIdGet() == RD_88F6281A_ID) ++ { ++ muxVal = 0xc; ++ muxValMask = 0xf3; ++ if(chType) /* FXS - issue reset properly */ ++ { ++ MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), MV_GPP12); ++ mvOsDelay(50); ++ MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), MV_GPP12); ++ } ++ else /* FXO - issue reset via TDM_CODEC_RST*/ ++ { ++ /* change MPP44 type to TDM_CODEC_RST(0x2) */ ++ MV_REG_WRITE(MPP_CONTROL_REG5, ((MV_REG_READ(MPP_CONTROL_REG5) & 0xFFF0FFFF) | BIT17)); ++ } ++ } ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxValMask) | muxVal; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp out val fail\n"); ++ return; ++ } ++ ++ /* TBD - 5 channels */ ++#if defined(MV_TDM_5CHANNELS) ++ /* change MPP38 type to GPIO(0x0) & polarity for TDM_STROBE */ ++ MV_REG_WRITE(MPP_CONTROL_REG4, (MV_REG_READ(MPP_CONTROL_REG4) & 0xF0FFFFFF)); ++ mvGppPolaritySet(1, MV_GPP6, 0); ++ ++ twsiSlave.offset = 6; ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(2); ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & ~BIT2); ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp change to out fail\n"); ++ return; ++ } ++ ++ ++ twsiSlave.offset = 2; ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & ~BIT2); ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp change to out fail\n"); ++ return; ++ } ++#endif ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ ++} ++/******************************************************************************* ++* mvBoardVoiceConnModeGet - return SLIC/DAA connection & interrupt modes ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++ ++MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode) ++{ ++ switch(mvBoardIdGet()) ++ { ++ case RD_88F6281A_ID: ++ *connMode = DAISY_CHAIN_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ case DB_88F6281A_BP_ID: ++ *connMode = DUAL_CHIP_SELECT_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ case RD_88F6192A_ID: ++ *connMode = DUAL_CHIP_SELECT_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ case DB_88F6192A_BP_ID: ++ *connMode = DUAL_CHIP_SELECT_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ default: ++ *connMode = *irqMode = -1; ++ mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet()); ++ } ++ return; ++ ++} ++ ++/******************************************************************************* ++* mvBoardMppModuleTypePrint - print module detect ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppModuleTypePrint(MV_VOID) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U32 maxMppGrp = 1; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ mppGroupType = mvBoardMppGroupTypeGet(devClass); ++ ++ switch(mppGroupType) ++ { ++ case MV_BOARD_TDM: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is TDM\n", devClass); ++ break; ++ case MV_BOARD_AUDIO: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is AUDIO\n", devClass); ++ break; ++ case MV_BOARD_RGMII: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is RGMII\n", devClass); ++ break; ++ case MV_BOARD_GMII: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is GMII\n", devClass); ++ break; ++ case MV_BOARD_TS: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is TS\n", devClass); ++ break; ++ default: ++ break; ++ } ++ } ++} ++ ++/* Board devices API managments */ ++ ++/******************************************************************************* ++* mvBoardGetDeviceNumber - Get number of device of some type on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* number of those devices else the function returns 0 ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_U32 foundIndex=0,devNum; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); ++ return 0xFFFFFFFF; ++ ++ } ++ ++ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) ++ { ++ if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) ++ { ++ foundIndex++; ++ } ++ } ++ ++ return foundIndex; ++ ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* Base address else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ { ++ return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); ++ ++ } ++ ++ return 0xFFFFFFFF; ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* Bus width else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ { ++ return 8; ++ } ++ ++ return 0xFFFFFFFF; ++ ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceWidth - Get dev width of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* dev width else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("Board unknown.\n"); ++ return 0xFFFFFFFF; ++ } ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ return devEntry->devWidth; ++ ++ return MV_ERROR; ++ ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* window size else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("Board unknown.\n"); ++ return 0xFFFFFFFF; ++ } ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ { ++ return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); ++ } ++ ++ return 0xFFFFFFFF; ++} ++ ++ ++/******************************************************************************* ++* boardGetDevEntry - returns the entry pointer of a device on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* dev number else the function returns 0x0 ++* ++* ++*******************************************************************************/ ++static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_U32 foundIndex=0,devIndex; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("boardGetDevEntry: Board unknown.\n"); ++ return NULL; ++ ++ } ++ ++ for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) ++ { ++ /* TBR */ ++ /*if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX) ++ continue;*/ ++ ++ if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) ++ { ++ if (foundIndex == devNum) ++ { ++ return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); ++ } ++ foundIndex++; ++ } ++ } ++ ++ /* device not found */ ++ return NULL; ++} ++ ++/* Get device CS number */ ++ ++MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("Board unknown.\n"); ++ return 0xFFFFFFFF; ++ ++ } ++ ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ return devEntry->deviceCS; ++ ++ return 0xFFFFFFFF; ++ ++} ++ ++/******************************************************************************* ++* mvBoardRtcTwsiAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardRtcTwsiAddrTypeGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardRtcTwsiAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardRtcTwsiAddrGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ return (0xFF); ++} ++ ++/******************************************************************************* ++* mvBoardA2DTwsiAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardA2DTwsiAddrTypeGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardA2DTwsiAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardA2DTwsiAddrGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ return (0xFF); ++} ++ ++/******************************************************************************* ++* mvBoardTwsiExpAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ else ++ indexFound++; ++ } ++ ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardTwsiExpAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ else ++ indexFound++; ++ } ++ ++ return (0xFF); ++} ++ ++ ++/******************************************************************************* ++* mvBoardTwsiSatRAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ else ++ indexFound++; ++ } ++ ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardTwsiSatRAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ else ++ indexFound++; ++ } ++ ++ return (0xFF); ++} ++ ++/******************************************************************************* ++* mvBoardNandWidthGet - ++* ++* DESCRIPTION: Get the width of the first NAND device in byte. ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: 1, 2, 4 or MV_ERROR ++* ++* ++*******************************************************************************/ ++/* */ ++MV_32 mvBoardNandWidthGet(void) ++{ ++ MV_U32 devNum; ++ MV_U32 devWidth; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) ++ { ++ devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); ++ if (devWidth != MV_ERROR) ++ return (devWidth / 8); ++ } ++ ++ /* NAND wasn't found */ ++ return MV_ERROR; ++} ++ ++MV_U32 gBoardId = -1; ++ ++/******************************************************************************* ++* mvBoardIdGet - Get Board model ++* ++* DESCRIPTION: ++* This function returns board ID. ++* Board ID is 32bit word constructed of board model (16bit) and ++* board revision (16bit) in the following way: 0xMMMMRRRR. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit board ID number, '-1' if board is undefined. ++* ++*******************************************************************************/ ++MV_U32 mvBoardIdGet(MV_VOID) ++{ ++ MV_U32 tmpBoardId = -1; ++ ++ if(gBoardId == -1) ++ { ++ #if defined(DB_88F6281A) ++ tmpBoardId = DB_88F6281A_BP_ID; ++ #elif defined(RD_88F6281A) ++ tmpBoardId = RD_88F6281A_ID; ++ #elif defined(DB_88F6192A) ++ tmpBoardId = DB_88F6192A_BP_ID; ++ #elif defined(DB_88F6190A) ++ tmpBoardId = DB_88F6190A_BP_ID; ++ #elif defined(RD_88F6192A) ++ tmpBoardId = RD_88F6192A_ID; ++ #elif defined(RD_88F6190A) ++ tmpBoardId = RD_88F6190A_ID; ++ #elif defined(DB_88F6180A) ++ tmpBoardId = DB_88F6180A_BP_ID; ++ #elif defined(RD_88F6281A_PCAC) ++ tmpBoardId = RD_88F6281A_PCAC_ID; ++ #elif defined(RD_88F6281A_SHEEVA_PLUG) ++ tmpBoardId = SHEEVA_PLUG_ID; ++ #elif defined(DB_CUSTOMER) ++ tmpBoardId = DB_CUSTOMER_ID; ++ #endif ++ gBoardId = tmpBoardId; ++ } ++ ++ return gBoardId; ++} ++ ++ ++/******************************************************************************* ++* mvBoarModuleTypeGet - mvBoarModuleTypeGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group num - MV_BOARD_MPP_GROUP_CLASS enum ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* module num - MV_BOARD_MODULE_CLASS enum ++* ++*******************************************************************************/ ++MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass) ++{ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ MV_U8 data; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: Read MPP module ID\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); ++ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(devClass); ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ ++ ++ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) ++ { ++ DB(mvOsPrintf("Board: Read MPP module ID fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: Read MPP module ID succeded\n")); ++ ++ return data; ++} ++ ++/******************************************************************************* ++* mvBoarTwsiSatRGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* device num - one of three devices ++* reg num - 0 or 1 ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* reg value ++* ++*******************************************************************************/ ++MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) ++{ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ MV_U8 data; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: Read S@R device read\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); ++ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); ++ twsiSlave.validOffset = MV_TRUE; ++ /* Use offset as command */ ++ twsiSlave.offset = regNum; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) ++ { ++ DB(mvOsPrintf("Board: Read S@R fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: Read S@R succeded\n")); ++ ++ return data; ++} ++ ++/******************************************************************************* ++* mvBoarTwsiSatRSet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devNum - one of three devices ++* regNum - 0 or 1 ++* regVal - value ++* ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* reg value ++* ++*******************************************************************************/ ++MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) ++{ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); ++ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); ++ twsiSlave.validOffset = MV_TRUE; ++ DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", twsiSlave.slaveAddr.address,\ ++ twsiSlave.slaveAddr.type, regVal)); ++ /* Use offset as command */ ++ twsiSlave.offset = regNum; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, ®Val, 1) ) ++ { ++ DB(mvOsPrintf("Board: Write S@R fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: Write S@R succeded\n")); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardSlicGpioPinGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) ++{ ++ MV_U32 boardId; ++ boardId = mvBoardIdGet(); ++ ++ switch (boardId) ++ { ++ case DB_88F6281A_BP_ID: ++ case RD_88F6281A_ID: ++ default: ++ return MV_ERROR; ++ break; ++ ++ } ++} ++ ++/******************************************************************************* ++* mvBoardFanPowerControl - Turn on/off the fan power control on the RD-6281A ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mode - MV_TRUE = on ; MV_FALSE = off ++* ++* OUTPUT: ++* MV_STATUS - MV_OK , MV_ERROR. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvBoardFanPowerControl(MV_BOOL mode) ++{ ++ ++ MV_U8 val = 1, twsiVal; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ if(mvBoardIdGet() != RD_88F6281A_ID) ++ return MV_ERROR; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if(mode == MV_TRUE) ++ val = 0x1; ++ else ++ val = 0; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfe) | val; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfe); ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardHDDPowerControl - Turn on/off the HDD power control on the RD-6281A ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mode - MV_TRUE = on ; MV_FALSE = off ++* ++* OUTPUT: ++* MV_STATUS - MV_OK , MV_ERROR. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode) ++{ ++ ++ MV_U8 val = 1, twsiVal; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ if(mvBoardIdGet() != RD_88F6281A_ID) ++ return MV_ERROR; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if(mode == MV_TRUE) ++ val = 0x2; ++ else ++ val = 0; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfd) | val; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfd); ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardSDioWPControl - Turn on/off the SDIO WP on the RD-6281A ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mode - MV_TRUE = on ; MV_FALSE = off ++* ++* OUTPUT: ++* MV_STATUS - MV_OK , MV_ERROR. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvBoardSDioWPControl(MV_BOOL mode) ++{ ++ ++ MV_U8 val = 1, twsiVal; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ if(mvBoardIdGet() != RD_88F6281A_ID) ++ return MV_ERROR; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(0); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if(mode == MV_TRUE) ++ val = 0x10; ++ else ++ val = 0; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xef) | val; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xef); ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ return MV_OK; ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,376 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCmvBoardEnvLibh ++#define __INCmvBoardEnvLibh ++ ++/* defines */ ++/* The below constant macros defines the board I2C EEPROM data offsets */ ++ ++ ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "mvSysHwConfig.h" ++#include "boardEnv/mvBoardEnvSpec.h" ++ ++ ++/* DUART stuff for Tclk detection only */ ++#define DUART_BAUD_RATE 115200 ++#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ ++ ++/* Voice devices assembly modes */ ++#define DAISY_CHAIN_MODE 1 ++#define DUAL_CHIP_SELECT_MODE 0 ++#define INTERRUPT_TO_MPP 1 ++#define INTERRUPT_TO_TDM 0 ++ ++ ++#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS ++#define BOARD_ETH_SWITCH_PORT_NUM 5 ++ ++#define MV_BOARD_MAX_USB_IF 1 ++#define MV_BOARD_MAX_MPP 7 ++#define MV_BOARD_NAME_LEN 0x20 ++ ++typedef struct _boardData ++{ ++ MV_U32 magic; ++ MV_U16 boardId; ++ MV_U8 boardVer; ++ MV_U8 boardRev; ++ MV_U32 reserved1; ++ MV_U32 reserved2; ++ ++}BOARD_DATA; ++ ++typedef enum _devBoardMppGroupClass ++{ ++ MV_BOARD_MPP_GROUP_1, ++ MV_BOARD_MPP_GROUP_2, ++ MV_BOARD_MAX_MPP_GROUP ++}MV_BOARD_MPP_GROUP_CLASS; ++ ++typedef enum _devBoardMppTypeClass ++{ ++ MV_BOARD_AUTO, ++ MV_BOARD_TDM, ++ MV_BOARD_AUDIO, ++ MV_BOARD_RGMII, ++ MV_BOARD_GMII, ++ MV_BOARD_TS, ++ MV_BOARD_MII, ++ MV_BOARD_OTHER ++}MV_BOARD_MPP_TYPE_CLASS; ++ ++typedef enum _devBoardModuleIdClass ++{ ++ MV_BOARD_MODULE_TDM_ID = 1, ++ MV_BOARD_MODULE_AUDIO_ID, ++ MV_BOARD_MODULE_RGMII_ID, ++ MV_BOARD_MODULE_GMII_ID, ++ MV_BOARD_MODULE_TS_ID, ++ MV_BOARD_MODULE_MII_ID, ++ MV_BOARD_MODULE_TDM_5CHAN_ID, ++ MV_BOARD_MODULE_OTHER_ID ++}MV_BOARD_MODULE_ID_CLASS; ++ ++typedef struct _boardMppTypeInfo ++{ ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup1; ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2; ++ ++}MV_BOARD_MPP_TYPE_INFO; ++ ++ ++typedef enum _devBoardClass ++{ ++ BOARD_DEV_NOR_FLASH, ++ BOARD_DEV_NAND_FLASH, ++ BOARD_DEV_SEVEN_SEG, ++ BOARD_DEV_FPGA, ++ BOARD_DEV_SRAM, ++ BOARD_DEV_SPI_FLASH, ++ BOARD_DEV_OTHER, ++}MV_BOARD_DEV_CLASS; ++ ++typedef enum _devTwsiBoardClass ++{ ++ BOARD_TWSI_RTC, ++ BOARD_DEV_TWSI_EXP, ++ BOARD_DEV_TWSI_SATR, ++ BOARD_TWSI_AUDIO_DEC, ++ BOARD_TWSI_OTHER ++}MV_BOARD_TWSI_CLASS; ++ ++typedef enum _devGppBoardClass ++{ ++ BOARD_GPP_RTC, ++ BOARD_GPP_MV_SWITCH, ++ BOARD_GPP_USB_VBUS, ++ BOARD_GPP_USB_VBUS_EN, ++ BOARD_GPP_USB_OC, ++ BOARD_GPP_USB_HOST_DEVICE, ++ BOARD_GPP_REF_CLCK, ++ BOARD_GPP_VOIP_SLIC, ++ BOARD_GPP_LIFELINE, ++ BOARD_GPP_BUTTON, ++ BOARD_GPP_TS_BUTTON_C, ++ BOARD_GPP_TS_BUTTON_U, ++ BOARD_GPP_TS_BUTTON_D, ++ BOARD_GPP_TS_BUTTON_L, ++ BOARD_GPP_TS_BUTTON_R, ++ BOARD_GPP_POWER_BUTTON, ++ BOARD_GPP_RESTOR_BUTTON, ++ BOARD_GPP_WPS_BUTTON, ++ BOARD_GPP_HDD0_POWER, ++ BOARD_GPP_HDD1_POWER, ++ BOARD_GPP_FAN_POWER, ++ BOARD_GPP_RESET, ++ BOARD_GPP_POWER_ON_LED, ++ BOARD_GPP_HDD_POWER, ++ BOARD_GPP_SDIO_POWER, ++ BOARD_GPP_SDIO_DETECT, ++ BOARD_GPP_SDIO_WP, ++ BOARD_GPP_SWITCH_PHY_INT, ++ BOARD_GPP_TSU_DIRCTION, ++ BOARD_GPP_OTHER ++}MV_BOARD_GPP_CLASS; ++ ++ ++typedef struct _devCsInfo ++{ ++ MV_U8 deviceCS; ++ MV_U32 params; ++ MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ ++ MV_U8 devWidth; ++ ++}MV_DEV_CS_INFO; ++ ++ ++#define MV_BOARD_PHY_FORCE_10MB 0x0 ++#define MV_BOARD_PHY_FORCE_100MB 0x1 ++#define MV_BOARD_PHY_FORCE_1000MB 0x2 ++#define MV_BOARD_PHY_SPEED_AUTO 0x3 ++ ++typedef struct _boardSwitchInfo ++{ ++ MV_32 linkStatusIrq; ++ MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM]; ++ MV_32 qdCpuPort; ++ MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */ ++ MV_32 switchOnPort; ++ ++}MV_BOARD_SWITCH_INFO; ++ ++typedef struct _boardLedInfo ++{ ++ MV_U8 activeLedsNumber; ++ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ ++ MV_U8* gppPinNum; /* Pointer to GPP values */ ++ ++}MV_BOARD_LED_INFO; ++ ++typedef struct _boardGppInfo ++{ ++ MV_BOARD_GPP_CLASS devClass; ++ MV_U8 gppPinNum; ++ ++}MV_BOARD_GPP_INFO; ++ ++ ++typedef struct _boardTwsiInfo ++{ ++ MV_BOARD_TWSI_CLASS devClass; ++ MV_U8 twsiDevAddr; ++ MV_U8 twsiDevAddrType; ++ ++}MV_BOARD_TWSI_INFO; ++ ++ ++typedef enum _boardMacSpeed ++{ ++ BOARD_MAC_SPEED_10M, ++ BOARD_MAC_SPEED_100M, ++ BOARD_MAC_SPEED_1000M, ++ BOARD_MAC_SPEED_AUTO, ++ ++}MV_BOARD_MAC_SPEED; ++ ++typedef struct _boardMacInfo ++{ ++ MV_BOARD_MAC_SPEED boardMacSpeed; ++ MV_U8 boardEthSmiAddr; ++ ++}MV_BOARD_MAC_INFO; ++ ++typedef struct _boardMppInfo ++{ ++ MV_U32 mppGroup[MV_BOARD_MAX_MPP]; ++ ++}MV_BOARD_MPP_INFO; ++ ++typedef struct _boardInfo ++{ ++ char boardName[MV_BOARD_NAME_LEN]; ++ MV_U8 numBoardMppTypeValue; ++ MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue; ++ MV_U8 numBoardMppConfigValue; ++ MV_BOARD_MPP_INFO* pBoardMppConfigValue; ++ MV_U32 intsGppMaskLow; ++ MV_U32 intsGppMaskHigh; ++ MV_U8 numBoardDeviceIf; ++ MV_DEV_CS_INFO* pDevCsInfo; ++ MV_U8 numBoardTwsiDev; ++ MV_BOARD_TWSI_INFO* pBoardTwsiDev; ++ MV_U8 numBoardMacInfo; ++ MV_BOARD_MAC_INFO* pBoardMacInfo; ++ MV_U8 numBoardGppInfo; ++ MV_BOARD_GPP_INFO* pBoardGppInfo; ++ MV_U8 activeLedsNumber; ++ MV_U8* pLedGppPin; ++ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ ++ /* GPP values */ ++ MV_U32 gppOutEnValLow; ++ MV_U32 gppOutEnValHigh; ++ MV_U32 gppOutValLow; ++ MV_U32 gppOutValHigh; ++ MV_U32 gppPolarityValLow; ++ MV_U32 gppPolarityValHigh; ++ ++ /* Switch Configuration */ ++ MV_BOARD_SWITCH_INFO* pSwitchInfo; ++}MV_BOARD_INFO; ++ ++ ++ ++MV_VOID mvBoardEnvInit(MV_VOID); ++MV_U32 mvBoardIdGet(MV_VOID); ++MV_U16 mvBoardModelGet(MV_VOID); ++MV_U16 mvBoardRevGet(MV_VOID); ++MV_STATUS mvBoardNameGet(char *pNameBuff); ++MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); ++MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); ++MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum); ++MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum); ++MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum); ++MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum); ++MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum); ++MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); ++MV_BOOL mvBoardIsPortInGmii(MV_VOID); ++MV_U32 mvBoardTclkGet(MV_VOID); ++MV_U32 mvBoardSysClkGet(MV_VOID); ++MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); ++MV_VOID mvBoardDebugLed(MV_U32 hexNum); ++MV_32 mvBoardMppGet(MV_U32 mppGroupNum); ++ ++MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); ++MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); ++ ++MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID); ++MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID); ++ ++MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index); ++MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index); ++MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index); ++MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index); ++MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass); ++MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass); ++MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType); ++MV_VOID mvBoardMppGroupIdUpdate(MV_VOID); ++MV_VOID mvBoardMppMuxSet(MV_VOID); ++MV_VOID mvBoardTdmMppSet(MV_32 chType); ++MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode); ++ ++MV_VOID mvBoardMppModuleTypePrint(MV_VOID); ++MV_VOID mvBoardReset(MV_VOID); ++MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); ++MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); ++MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); ++/* Board devices API managments */ ++MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++ ++/* Gpio Pin Connections API */ ++MV_32 mvBoardUSBVbusGpioPinGet(int devId); ++MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); ++MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin); ++ ++MV_32 mvBoardResetGpioPinGet(MV_VOID); ++MV_32 mvBoardRTCGpioPinGet(MV_VOID); ++MV_32 mvBoardGpioIntMaskLowGet(MV_VOID); ++MV_32 mvBoardGpioIntMaskHighGet(MV_VOID); ++MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); ++ ++MV_32 mvBoardSDIOGpioPinGet(MV_VOID); ++MV_STATUS mvBoardSDioWPControl(MV_BOOL mode); ++MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); ++ ++MV_32 mvBoardNandWidthGet(void); ++MV_STATUS mvBoardFanPowerControl(MV_BOOL mode); ++MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode); ++#endif /* __INCmvBoardEnvLibh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,848 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "mvCommon.h" ++#include "mvBoardEnvLib.h" ++#include "mvBoardEnvSpec.h" ++#include "twsi/mvTwsi.h" ++ ++#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0 ++#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7 ++#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2 ++#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3 ++#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 ++#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0 ++ ++ ++MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, ++ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ { ++ {BOARD_MAC_SPEED_AUTO, 0x8}, ++ {BOARD_MAC_SPEED_AUTO, 0x9} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_AUTO, MV_BOARD_AUTO} ++ }; ++ ++MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ {BOARD_GPP_TSU_DIRCTION, 33} ++ /*muxed with TDM/Audio module via IOexpender ++ {BOARD_GPP_SDIO_DETECT, 38}, ++ {BOARD_GPP_USB_VBUS, 49}*/ ++ }; ++ ++MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] = ++ {{{ ++ DB_88F6281A_MPP0_7, ++ DB_88F6281A_MPP8_15, ++ DB_88F6281A_MPP16_23, ++ DB_88F6281A_MPP24_31, ++ DB_88F6281A_MPP32_39, ++ DB_88F6281A_MPP40_47, ++ DB_88F6281A_MPP48_55 ++ }}}; ++ ++ ++MV_BOARD_INFO db88f6281AInfo = { ++ "DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6281AInfoBoardMppTypeInfo, ++ DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6281AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6281AInfoBoardDeCsInfo, ++ DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6281AInfoBoardTwsiDev, ++ DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6281AInfoBoardMacInfo, ++ DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ db88f6281AInfoBoardGppInfo, ++ DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6281A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6281A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ BIT6, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++ ++#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0 ++#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2 ++#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2 ++#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5 ++#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_1000M, 0xa}, ++ {BOARD_MAC_SPEED_AUTO, 0xb} ++ }; ++ ++MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] = ++ /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, ++ MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */ ++ {{38, {0, 1, 2, 3, -1}, 5, 2, 0}, ++ {-1, {-1}, -1, -1, -1}}; ++ ++MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */ ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_RGMII, MV_BOARD_TDM} ++ }; ++ ++MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ {{BOARD_GPP_SDIO_DETECT, 28}, ++ {BOARD_GPP_USB_OC, 29}, ++ {BOARD_GPP_WPS_BUTTON, 35}, ++ {BOARD_GPP_MV_SWITCH, 38}, ++ {BOARD_GPP_USB_VBUS, 49} ++ }; ++ ++MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] = ++ {{{ ++ RD_88F6281A_MPP0_7, ++ RD_88F6281A_MPP8_15, ++ RD_88F6281A_MPP16_23, ++ RD_88F6281A_MPP24_31, ++ RD_88F6281A_MPP32_39, ++ RD_88F6281A_MPP40_47, ++ RD_88F6281A_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO rd88f6281AInfo = { ++ "RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6281AInfoBoardMppTypeInfo, ++ RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6281AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6281AInfoBoardDeCsInfo, ++ RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ rd88f6281AInfoBoardTwsiDev, ++ RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6281AInfoBoardMacInfo, ++ RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ rd88f6281AInfoBoardGppInfo, ++ RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ RD_88F6281A_OE_LOW, /* gppOutEnLow */ ++ RD_88F6281A_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ BIT6, /* gppPolarityValHigh */ ++ rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */ ++}; ++ ++ ++#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0 ++#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7 ++#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2 ++#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3 ++#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, ++ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ { ++ {BOARD_MAC_SPEED_AUTO, 0x8}, ++ {BOARD_MAC_SPEED_AUTO, 0x9} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_AUTO, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ {BOARD_GPP_SDIO_WP, 20}, ++ {BOARD_GPP_USB_VBUS, 22}, ++ {BOARD_GPP_SDIO_DETECT, 23}, ++ }; ++ ++MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] = ++ {{{ ++ DB_88F6192A_MPP0_7, ++ DB_88F6192A_MPP8_15, ++ DB_88F6192A_MPP16_23, ++ DB_88F6192A_MPP24_31, ++ DB_88F6192A_MPP32_35 ++ }}}; ++ ++MV_BOARD_INFO db88f6192AInfo = { ++ "DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6192AInfoBoardMppTypeInfo, ++ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6192AInfoBoardDeCsInfo, ++ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6192AInfoBoardTwsiDev, ++ DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6192AInfoBoardMacInfo, ++ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ db88f6192AInfoBoardGppInfo, ++ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6192A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1 ++ ++MV_BOARD_INFO db88f6190AInfo = { ++ "DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6192AInfoBoardMppTypeInfo, ++ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6192AInfoBoardDeCsInfo, ++ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6192AInfoBoardTwsiDev, ++ DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6192AInfoBoardMacInfo, ++ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ db88f6192AInfoBoardGppInfo, ++ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6192A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0 ++#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0 ++#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1 ++#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE ++#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 ++#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3 ++ ++MV_U8 rd88f6192AInfoBoardDebugLedIf[] = ++ {17, 28, 29}; ++ ++MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x8} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++ ++MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ {BOARD_GPP_USB_VBUS_EN, 10}, ++ {BOARD_GPP_USB_HOST_DEVICE, 11}, ++ {BOARD_GPP_RESET, 14}, ++ {BOARD_GPP_POWER_ON_LED, 15}, ++ {BOARD_GPP_HDD_POWER, 16}, ++ {BOARD_GPP_WPS_BUTTON, 24}, ++ {BOARD_GPP_TS_BUTTON_C, 25}, ++ {BOARD_GPP_USB_VBUS, 26}, ++ {BOARD_GPP_USB_OC, 27}, ++ {BOARD_GPP_TS_BUTTON_U, 30}, ++ {BOARD_GPP_TS_BUTTON_R, 31}, ++ {BOARD_GPP_TS_BUTTON_L, 32}, ++ {BOARD_GPP_TS_BUTTON_D, 34}, ++ {BOARD_GPP_FAN_POWER, 35} ++ }; ++ ++MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] = ++ {{{ ++ RD_88F6192A_MPP0_7, ++ RD_88F6192A_MPP8_15, ++ RD_88F6192A_MPP16_23, ++ RD_88F6192A_MPP24_31, ++ RD_88F6192A_MPP32_35 ++ }}}; ++ ++MV_BOARD_INFO rd88f6192AInfo = { ++ "RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6192AInfoBoardMppTypeInfo, ++ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6192AInfoBoardDeCsInfo, ++ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ NULL, ++ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6192AInfoBoardMacInfo, ++ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ rd88f6192AInfoBoardGppInfo, ++ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ rd88f6192AInfoBoardDebugLedIf, ++ 0, /* ledsPolarity */ ++ RD_88F6192A_OE_LOW, /* gppOutEnLow */ ++ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++MV_BOARD_INFO rd88f6190AInfo = { ++ "RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6192AInfoBoardMppTypeInfo, ++ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6192AInfoBoardDeCsInfo, ++ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ NULL, ++ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6192AInfoBoardMacInfo, ++ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ rd88f6192AInfoBoardGppInfo, ++ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ rd88f6192AInfoBoardDebugLedIf, ++ 0, /* ledsPolarity */ ++ RD_88F6192A_OE_LOW, /* gppOutEnLow */ ++ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0 ++#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5 ++#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1 ++#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0 ++#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2 ++#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1 ++#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, ++ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x8} ++ }; ++ ++MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ /* Muxed with TDM/Audio module via IOexpender ++ {BOARD_GPP_USB_VBUS, 6} */ ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_OTHER, MV_BOARD_AUTO} ++ }; ++ ++MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] = ++ {{{ ++ DB_88F6180A_MPP0_7, ++ DB_88F6180A_MPP8_15, ++ DB_88F6180A_MPP16_23, ++ DB_88F6180A_MPP24_31, ++ DB_88F6180A_MPP32_39, ++ DB_88F6180A_MPP40_44 ++ }}}; ++ ++MV_BOARD_INFO db88f6180AInfo = { ++ "DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6180AInfoBoardMppTypeInfo, ++ DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6180AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6180AInfoBoardDeCsInfo, ++ DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6180AInfoBoardTwsiDev, ++ DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6180AInfoBoardMacInfo, ++ DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ NULL, ++ DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6180A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6180A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++ ++#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0 ++#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1 ++#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1 ++#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0 ++#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4 ++ ++MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] = ++ {38, 39, 40, 41}; ++ ++MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x8} ++ }; ++ ++MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] = ++ {{{ ++ RD_88F6281A_PCAC_MPP0_7, ++ RD_88F6281A_PCAC_MPP8_15, ++ RD_88F6281A_PCAC_MPP16_23, ++ RD_88F6281A_PCAC_MPP24_31, ++ RD_88F6281A_PCAC_MPP32_39, ++ RD_88F6281A_PCAC_MPP40_47, ++ RD_88F6281A_PCAC_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO rd88f6281APcacInfo = { ++ "RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6281APcacInfoBoardMppTypeInfo, ++ RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6281APcacInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6281APcacInfoBoardDeCsInfo, ++ RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ rd88f6281APcacInfoBoardTwsiDev, ++ RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6281APcacInfoBoardMacInfo, ++ RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ 0, ++ RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */ ++ RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++ ++/* 6281 Sheeva Plug*/ ++ ++#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0 ++#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0 ++#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1 ++#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0 ++#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1 ++#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1 ++#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1 ++#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1 ++ ++MV_U8 sheevaPlugInfoBoardDebugLedIf[] = ++ {49}; ++ ++MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x0}}; ++ ++MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; ++ ++MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++ ++MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] = ++ {{{ ++ RD_SHEEVA_PLUG_MPP0_7, ++ RD_SHEEVA_PLUG_MPP8_15, ++ RD_SHEEVA_PLUG_MPP16_23, ++ RD_SHEEVA_PLUG_MPP24_31, ++ RD_SHEEVA_PLUG_MPP32_39, ++ RD_SHEEVA_PLUG_MPP40_47, ++ RD_SHEEVA_PLUG_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO sheevaPlugInfo = { ++ "SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */ ++ SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ ++ sheevaPlugInfoBoardMppTypeInfo, ++ SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ sheevaPlugInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ sheevaPlugInfoBoardDeCsInfo, ++ SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ sheevaPlugInfoBoardTwsiDev, ++ SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ sheevaPlugInfoBoardMacInfo, ++ SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ 0, ++ SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ sheevaPlugInfoBoardDebugLedIf, ++ 0, /* ledsPolarity */ ++ RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */ ++ RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */ ++ RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */ ++ RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++/* Customer specific board place holder*/ ++ ++#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0 ++#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0 ++#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0 ++#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0 ++#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0 ++#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 ++#else ++ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 ++#endif ++#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_U8 dbCustomerInfoBoardDebugLedIf[] = ++ {0}; ++ ++MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x0}}; ++ ++MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; ++ ++MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] = ++ {{{ ++ DB_CUSTOMER_MPP0_7, ++ DB_CUSTOMER_MPP8_15, ++ DB_CUSTOMER_MPP16_23, ++ DB_CUSTOMER_MPP24_31, ++ DB_CUSTOMER_MPP32_39, ++ DB_CUSTOMER_MPP40_47, ++ DB_CUSTOMER_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO dbCustomerInfo = { ++ "DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ ++ dbCustomerInfoBoardMppTypeInfo, ++ DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ dbCustomerInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ dbCustomerInfoBoardDeCsInfo, ++ DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ dbCustomerInfoBoardTwsiDev, ++ DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ dbCustomerInfoBoardMacInfo, ++ DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ 0, ++ DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_CUSTOMER_OE_LOW, /* gppOutEnLow */ ++ DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */ ++ DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */ ++ DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++MV_BOARD_INFO* boardInfoTbl[] = { ++ &db88f6281AInfo, ++ &rd88f6281AInfo, ++ &db88f6192AInfo, ++ &rd88f6192AInfo, ++ &db88f6180AInfo, ++ &db88f6190AInfo, ++ &rd88f6190AInfo, ++ &rd88f6281APcacInfo, ++ &dbCustomerInfo, ++ &sheevaPlugInfo ++ }; ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,262 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvBoardEnvSpech ++#define __INCmvBoardEnvSpech ++ ++#include "mvSysHwConfig.h" ++ ++ ++/* For future use */ ++#define BD_ID_DATA_START_OFFS 0x0 ++#define BD_DETECT_SEQ_OFFS 0x0 ++#define BD_SYS_NUM_OFFS 0x4 ++#define BD_NAME_OFFS 0x8 ++ ++/* I2C bus addresses */ ++#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ ++#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_DIMM0_I2C_ADDR 0x56 ++#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_DIMM1_I2C_ADDR 0x54 ++#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_EEPROM_I2C_ADDR 0x51 ++#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50 ++#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2 ++#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 ++ ++#define BOOT_FLASH_INDEX 0 ++#define MAIN_FLASH_INDEX 1 ++ ++#define BOARD_ETH_START_PORT_NUM 0 ++ ++/* Supported clocks */ ++#define MV_BOARD_TCLK_100MHZ 100000000 ++#define MV_BOARD_TCLK_125MHZ 125000000 ++#define MV_BOARD_TCLK_133MHZ 133333333 ++#define MV_BOARD_TCLK_150MHZ 150000000 ++#define MV_BOARD_TCLK_166MHZ 166666667 ++#define MV_BOARD_TCLK_200MHZ 200000000 ++ ++#define MV_BOARD_SYSCLK_100MHZ 100000000 ++#define MV_BOARD_SYSCLK_125MHZ 125000000 ++#define MV_BOARD_SYSCLK_133MHZ 133333333 ++#define MV_BOARD_SYSCLK_150MHZ 150000000 ++#define MV_BOARD_SYSCLK_166MHZ 166666667 ++#define MV_BOARD_SYSCLK_200MHZ 200000000 ++#define MV_BOARD_SYSCLK_233MHZ 233333333 ++#define MV_BOARD_SYSCLK_250MHZ 250000000 ++#define MV_BOARD_SYSCLK_267MHZ 266666667 ++#define MV_BOARD_SYSCLK_300MHZ 300000000 ++#define MV_BOARD_SYSCLK_333MHZ 333333334 ++#define MV_BOARD_SYSCLK_400MHZ 400000000 ++ ++#define MV_BOARD_REFCLK_25MHZ 25000000 ++ ++/* Board specific */ ++/* =============================== */ ++ ++/* boards ID numbers */ ++ ++#define BOARD_ID_BASE 0x0 ++ ++/* New board ID numbers */ ++#define DB_88F6281A_BP_ID (BOARD_ID_BASE) ++#define DB_88F6281_BP_MLL_ID 1680 ++#define RD_88F6281A_ID (BOARD_ID_BASE+0x1) ++#define RD_88F6281_MLL_ID 1682 ++#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2) ++#define RD_88F6192A_ID (BOARD_ID_BASE+0x3) ++#define RD_88F6192_MLL_ID 1681 ++#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4) ++#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5) ++#define RD_88F6190A_ID (BOARD_ID_BASE+0x6) ++#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7) ++#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8) ++#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9) ++#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1) ++ ++/* DB-88F6281A-BP */ ++#if defined(MV_NAND) ++ #define DB_88F6281A_MPP0_7 0x21111111 ++#else ++ #define DB_88F6281A_MPP0_7 0x21112220 ++#endif ++#define DB_88F6281A_MPP8_15 0x11113311 ++#define DB_88F6281A_MPP16_23 0x00551111 ++#define DB_88F6281A_MPP24_31 0x00000000 ++#define DB_88F6281A_MPP32_39 0x00000000 ++#define DB_88F6281A_MPP40_47 0x00000000 ++#define DB_88F6281A_MPP48_55 0x00000000 ++#define DB_88F6281A_OE_LOW 0x0 ++#if defined(MV_TDM_5CHANNELS) ++ #define DB_88F6281A_OE_HIGH (BIT6) ++#else ++#define DB_88F6281A_OE_HIGH 0x0 ++#endif ++#define DB_88F6281A_OE_VAL_LOW 0x0 ++#define DB_88F6281A_OE_VAL_HIGH 0x0 ++ ++/* RD-88F6281A */ ++#if defined(MV_NAND) ++ #define RD_88F6281A_MPP0_7 0x21111111 ++#else ++ #define RD_88F6281A_MPP0_7 0x21112220 ++#endif ++#define RD_88F6281A_MPP8_15 0x11113311 ++#define RD_88F6281A_MPP16_23 0x33331111 ++#define RD_88F6281A_MPP24_31 0x33003333 ++#define RD_88F6281A_MPP32_39 0x20440533 ++#define RD_88F6281A_MPP40_47 0x22202222 ++#define RD_88F6281A_MPP48_55 0x00000002 ++#define RD_88F6281A_OE_LOW (BIT28 | BIT29) ++#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17) ++#define RD_88F6281A_OE_VAL_LOW 0x0 ++#define RD_88F6281A_OE_VAL_HIGH 0x0 ++ ++/* DB-88F6192A-BP */ ++#if defined(MV_NAND) ++ #define DB_88F6192A_MPP0_7 0x21111111 ++#else ++ #define DB_88F6192A_MPP0_7 0x21112220 ++#endif ++#define DB_88F6192A_MPP8_15 0x11113311 ++#define DB_88F6192A_MPP16_23 0x00501111 ++#define DB_88F6192A_MPP24_31 0x00000000 ++#define DB_88F6192A_MPP32_35 0x00000000 ++#define DB_88F6192A_OE_LOW (BIT22 | BIT23) ++#define DB_88F6192A_OE_HIGH 0x0 ++#define DB_88F6192A_OE_VAL_LOW 0x0 ++#define DB_88F6192A_OE_VAL_HIGH 0x0 ++ ++/* RD-88F6192A */ ++#define RD_88F6192A_MPP0_7 0x01222222 ++#define RD_88F6192A_MPP8_15 0x00000011 ++#define RD_88F6192A_MPP16_23 0x05550000 ++#define RD_88F6192A_MPP24_31 0x0 ++#define RD_88F6192A_MPP32_35 0x0 ++#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31) ++#define RD_88F6192A_OE_HIGH (BIT0 | BIT2) ++#define RD_88F6192A_OE_VAL_LOW 0x18400 ++#define RD_88F6192A_OE_VAL_HIGH 0x8 ++ ++/* DB-88F6180A-BP */ ++#if defined(MV_NAND) ++ #define DB_88F6180A_MPP0_7 0x21111111 ++#else ++ #define DB_88F6180A_MPP0_7 0x01112222 ++#endif ++#define DB_88F6180A_MPP8_15 0x11113311 ++#define DB_88F6180A_MPP16_23 0x00001111 ++#define DB_88F6180A_MPP24_31 0x0 ++#define DB_88F6180A_MPP32_39 0x4444c000 ++#define DB_88F6180A_MPP40_44 0x00044444 ++#define DB_88F6180A_OE_LOW 0x0 ++#define DB_88F6180A_OE_HIGH 0x0 ++#define DB_88F6180A_OE_VAL_LOW 0x0 ++#define DB_88F6180A_OE_VAL_HIGH 0x0 ++ ++/* RD-88F6281A_PCAC */ ++#define RD_88F6281A_PCAC_MPP0_7 0x21111111 ++#define RD_88F6281A_PCAC_MPP8_15 0x00003311 ++#define RD_88F6281A_PCAC_MPP16_23 0x00001100 ++#define RD_88F6281A_PCAC_MPP24_31 0x00000000 ++#define RD_88F6281A_PCAC_MPP32_39 0x00000000 ++#define RD_88F6281A_PCAC_MPP40_47 0x00000000 ++#define RD_88F6281A_PCAC_MPP48_55 0x00000000 ++#define RD_88F6281A_PCAC_OE_LOW 0x0 ++#define RD_88F6281A_PCAC_OE_HIGH 0x0 ++#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0 ++#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0 ++ ++/* SHEEVA PLUG */ ++#define RD_SHEEVA_PLUG_MPP0_7 0x01111111 ++#define RD_SHEEVA_PLUG_MPP8_15 0x11113322 ++#define RD_SHEEVA_PLUG_MPP16_23 0x00001111 ++#define RD_SHEEVA_PLUG_MPP24_31 0x00100000 ++#define RD_SHEEVA_PLUG_MPP32_39 0x00000000 ++#define RD_SHEEVA_PLUG_MPP40_47 0x00000000 ++#define RD_SHEEVA_PLUG_MPP48_55 0x00000000 ++#define RD_SHEEVA_PLUG_OE_LOW 0x0 ++#define RD_SHEEVA_PLUG_OE_HIGH 0x0 ++#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29) ++#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14) ++ ++/* DB-CUSTOMER */ ++#define DB_CUSTOMER_MPP0_7 0x21111111 ++#define DB_CUSTOMER_MPP8_15 0x00003311 ++#define DB_CUSTOMER_MPP16_23 0x00001100 ++#define DB_CUSTOMER_MPP24_31 0x00000000 ++#define DB_CUSTOMER_MPP32_39 0x00000000 ++#define DB_CUSTOMER_MPP40_47 0x00000000 ++#define DB_CUSTOMER_MPP48_55 0x00000000 ++#define DB_CUSTOMER_OE_LOW 0x0 ++#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9))) ++#define DB_CUSTOMER_OE_VAL_LOW 0x0 ++#define DB_CUSTOMER_OE_VAL_HIGH 0x0 ++ ++#endif /* __INCmvBoardEnvSpech */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,320 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "cpu/mvCpu.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvRegs.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* locals */ ++ ++/******************************************************************************* ++* mvCpuPclkGet - Get the CPU pClk (pipe clock) ++* ++* DESCRIPTION: ++* This routine extract the CPU core clock. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit clock cycles in MHertz. ++* ++*******************************************************************************/ ++/* 6180 have different clk reset sampling */ ++ ++static MV_U32 mvCpu6180PclkGet(MV_VOID) ++{ ++ MV_U32 tmpPClkRate=0; ++ MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; ++ ++ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180; ++ tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180; ++ ++ tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk; ++ ++ return tmpPClkRate; ++} ++ ++ ++MV_U32 mvCpuPclkGet(MV_VOID) ++{ ++#if defined(PCLCK_AUTO_DETECT) ++ MV_U32 tmpPClkRate=0; ++ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; ++ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return mvCpu6180PclkGet(); ++ ++ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate); ++ tmpPClkRate = cpuCLK[tmpPClkRate]; ++ ++ return tmpPClkRate; ++#else ++ return MV_DEFAULT_PCLK ++#endif ++} ++ ++/******************************************************************************* ++* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) ++* ++* DESCRIPTION: ++* This routine extract the CPU L2 clock. ++* ++* RETURN: ++* 32bit clock cycles in Hertz. ++* ++*******************************************************************************/ ++static MV_U32 mvCpu6180L2ClkGet(MV_VOID) ++{ ++ MV_U32 L2ClkRate=0; ++ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; ++ ++ L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180; ++ L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180; ++ ++ L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk; ++ ++ return L2ClkRate; ++ ++} ++ ++MV_U32 mvCpuL2ClkGet(MV_VOID) ++{ ++#ifdef L2CLK_AUTO_DETECT ++ MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio; ++ MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL; ++ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return mvCpu6180L2ClkGet(); ++ ++ pClkRate = mvCpuPclkGet(); ++ ++ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp); ++ ++ L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]); ++ ++ return L2ClkRate; ++#else ++ return MV_BOARD_DEFAULT_L2CLK; ++#endif ++} ++ ++ ++/******************************************************************************* ++* mvCpuNameGet - Get CPU name ++* ++* DESCRIPTION: ++* This function returns a string describing the CPU model and revision. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. ++* ++* RETURN: ++* None. ++*******************************************************************************/ ++MV_VOID mvCpuNameGet(char *pNameBuff) ++{ ++ MV_U32 cpuModel; ++ ++ cpuModel = mvOsCpuPartGet(); ++ ++ /* The CPU module is indicated in the Processor Version Register (PVR) */ ++ switch(cpuModel) ++ { ++ case CPU_PART_MRVL131: ++ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet()); ++ break; ++ case CPU_PART_ARM926: ++ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); ++ break; ++ case CPU_PART_ARM946: ++ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); ++ break; ++ default: ++ mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); ++ break; ++ } /* switch */ ++ ++ return; ++} ++ ++ ++#define MV_PROC_STR_SIZE 50 ++ ++static void mvCpuIfGetL2EccMode(MV_8 *buf) ++{ ++ MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG); ++ if (regVal & BIT2) ++ mvOsSPrintf(buf, "L2 ECC Enabled"); ++ else ++ mvOsSPrintf(buf, "L2 ECC Disabled"); ++} ++ ++static void mvCpuIfGetL2Mode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT22) ++ mvOsSPrintf(buf, "L2 Enabled"); ++ else ++ mvOsSPrintf(buf, "L2 Disabled"); ++} ++ ++static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT24) ++ mvOsSPrintf(buf, "L2 Prefetch Disabled"); ++ else ++ mvOsSPrintf(buf, "L2 Prefetch Enabled"); ++} ++ ++static void mvCpuIfGetWriteAllocMode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT28) ++ mvOsSPrintf(buf, "Write Allocate Enabled"); ++ else ++ mvOsSPrintf(buf, "Write Allocate Disabled"); ++} ++ ++static void mvCpuIfGetCpuStreamMode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT29) ++ mvOsSPrintf(buf, "CPU Streaming Enabled"); ++ else ++ mvOsSPrintf(buf, "CPU Streaming Disabled"); ++} ++ ++static void mvCpuIfPrintCpuRegs(void) ++{ ++ MV_U32 regVal = 0; ++ ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); ++ ++ __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ ++ mvOsPrintf("Control Reg = 0x%x\n",regVal); ++ ++ __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ ++ mvOsPrintf("ID Code Reg = 0x%x\n",regVal); ++ ++ __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ ++ mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); ++ ++} ++ ++MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) ++{ ++ MV_U32 count = 0; ++ ++ MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; ++ MV_8 L2_En_str[MV_PROC_STR_SIZE]; ++ MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; ++ MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; ++ MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; ++ ++ mvCpuIfGetL2Mode(L2_En_str); ++ mvCpuIfGetL2EccMode(L2_ECC_str); ++ mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); ++ mvCpuIfGetWriteAllocMode(Write_Alloc_str); ++ mvCpuIfGetCpuStreamMode(Cpu_Stream_str); ++ mvCpuIfPrintCpuRegs(); ++ ++ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); ++ return count; ++} ++ ++MV_U32 whoAmI(MV_VOID) ++{ ++ return 0; ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,99 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCpuh ++#define __INCmvCpuh ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++/* defines */ ++#define CPU_PART_MRVL131 0x131 ++#define CPU_PART_ARM926 0x926 ++#define CPU_PART_ARM946 0x946 ++#define MV_CPU_ARM_CLK_ELM_SIZE 12 ++#define MV_CPU_ARM_CLK_RATIO_OFF 8 ++#define MV_CPU_ARM_CLK_DDR_OFF 4 ++ ++#ifndef MV_ASMLANGUAGE ++typedef struct _mvCpuArmClk ++{ ++ MV_U32 cpuClk; /* CPU clock in MHz */ ++ MV_U32 ddrClk; /* DDR clock in MHz */ ++ MV_U32 l2Clk; /* CPU DDR clock ratio */ ++ ++}MV_CPU_ARM_CLK; ++ ++MV_U32 mvCpuPclkGet(MV_VOID); ++MV_VOID mvCpuNameGet(char *pNameBuff); ++MV_U32 mvCpuL2ClkGet(MV_VOID); ++MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); ++MV_U32 whoAmI(MV_VOID); ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#endif /* __INCmvCpuh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,296 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvCtrlEnvAddrDec.h - Marvell controller address decode library ++* ++* DESCRIPTION: ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++#include "ctrlEnv/sys/mvAhbToMbusRegs.h" ++#include "ddr2/mvDramIfRegs.h" ++#include "pex/mvPexRegs.h" ++ ++#define MV_DEBUG ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* Default Attributes array */ ++MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; ++extern MV_TARGET *sampleAtResetTargetArray; ++/* Dram\AHBToMbus\PEX share regsiter */ ++ ++#define CTRL_DEC_BASE_OFFS 16 ++#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) ++#define CTRL_DEC_BASE_ALIGNMENT 0x10000 ++ ++#define CTRL_DEC_SIZE_OFFS 16 ++#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) ++#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 ++ ++#define CTRL_DEC_WIN_EN BIT0 ++ ++ ++ ++/******************************************************************************* ++* mvCtrlAddrDecToReg - Get address decode register format values ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) ++{ ++ ++ MV_U32 baseToReg=0 , sizeToReg=0; ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; ++ pAddrDecRegs->baseReg |= baseToReg; ++ ++ /* Get size register value according to window size */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ return MV_BAD_PARAM; ++ } ++ ++ /* set size */ ++ pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; ++ pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); ++ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCtrlRegToAddrDec - Extract address decode struct from registers. ++* ++* DESCRIPTION: ++* This function extract address decode struct from address decode ++* registers given as parameters. ++* ++* INPUT: ++* pAddrDecRegs - Address decode register struct. ++* ++* OUTPUT: ++* pAddrDecWin - Target window data structure. ++* ++* RETURN: ++* MV_BAD_PARAM if address decode registers data is invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) ++{ ++ MV_U32 sizeRegVal; ++ ++ sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> ++ CTRL_DEC_SIZE_OFFS; ++ ++ pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ ++ /* Extract base address */ ++ /* Base register [31:16] ==> baseLow[31:16] */ ++ pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; ++ ++ pAddrDecWin->baseHigh = 0; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCtrlAttribGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++ ++MV_STATUS mvCtrlAttribGet(MV_TARGET target, ++ MV_TARGET_ATTRIB *targetAttrib) ++{ ++ ++ targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; ++ targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCtrlGetAttrib - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) ++{ ++ MV_TARGET target; ++ MV_TARGET x; ++ for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) ++ { ++ x = MV_CHANGE_BOOT_CS(target); ++ if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && ++ (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) ++ { ++ /* found it */ ++ break; ++ } ++ } ++ ++ return target; ++} ++ ++MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, ++ MV_DEC_WIN_PARAMS *pWinParam) ++{ ++ MV_U32 baseToReg=0, sizeToReg=0; ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK; ++ pWinParam->baseAddr |= baseToReg; ++ ++ /* Get size register value according to window size */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n"); ++ return MV_BAD_PARAM; ++ } ++ pWinParam->size = sizeToReg; ++ ++ pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib; ++ pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId; ++ ++ return MV_OK; ++} ++ ++MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, ++ MV_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; ++ ++ /* Upper 32bit address base is supported under PCI High Address remap */ ++ pAddrDecWin->addrWin.baseHigh = 0; ++ ++ /* Prepare sizeReg to ctrlRegToSize function */ ++ pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); ++ return MV_BAD_PARAM; ++ } ++ targetAttrib.targetId = pWinParam->targetId; ++ targetAttrib.attrib = pWinParam->attrib; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ return MV_OK; ++} ++ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,203 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCtrlEnvAddrDech ++#define __INCmvCtrlEnvAddrDech ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvRegs.h" ++ ++ ++/* defines */ ++/* DUnit attributes */ ++#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 ++#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 ++#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) ++ ++#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 ++#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 ++#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) ++ ++#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 ++#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 ++#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) ++ ++#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 ++#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 ++#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) ++ ++/* RUnit (Device) attributes */ ++#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 ++#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 ++#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) ++ ++#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 ++#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 ++#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) ++ ++#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 ++#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 ++#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) ++ ++#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 ++#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 ++#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) ++ ++/* LMaster (PCI) attributes */ ++#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 ++#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 ++#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) ++#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) ++ ++ ++#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 ++#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 ++#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) ++#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) ++ ++#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 ++ ++#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 ++#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 ++#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) ++#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) ++ ++#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 ++#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 ++#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) ++ ++#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 ++#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 ++#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) ++ ++/* PEX Attributes */ ++#define ATMWCR_WIN_PEX_TYPE_OFFS 3 ++#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 ++#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) ++#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) ++ ++/* typedefs */ ++ ++/* Unsupported attributes for address decode: */ ++/* 2) PCI0/1_REQ64n control */ ++ ++typedef struct _mvDecRegs ++{ ++ MV_U32 baseReg; ++ MV_U32 baseRegHigh; ++ MV_U32 sizeReg; ++ ++}MV_DEC_REGS; ++ ++typedef struct _mvTargetAttrib ++{ ++ MV_U8 attrib; /* chip select attributes */ ++ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ ++ ++}MV_TARGET_ATTRIB; ++ ++ ++/* This structure describes address decode window */ ++typedef struct _mvDecWin ++{ ++ MV_TARGET target; /* Target for addr decode window */ ++ MV_ADDR_WIN addrWin; /* Address window of target */ ++ MV_BOOL enable; /* Window enable/disable */ ++}MV_DEC_WIN; ++ ++typedef struct _mvDecWinParams ++{ ++ MV_TARGET_ID targetId; /* Target ID field */ ++ MV_U8 attrib; /* Attribute field */ ++ MV_U32 baseAddr; /* Base address in register format */ ++ MV_U32 size; /* Size in register format */ ++}MV_DEC_WIN_PARAMS; ++ ++ ++/* mvCtrlEnvAddrDec API list */ ++ ++MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, ++ MV_DEC_REGS *pAddrDecRegs); ++ ++MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, ++ MV_ADDR_WIN *pAddrDecWin); ++ ++MV_STATUS mvCtrlAttribGet(MV_TARGET target, ++ MV_TARGET_ATTRIB *targetAttrib); ++ ++MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); ++ ++ ++MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, ++ MV_DEC_WIN_PARAMS *pWinParam); ++ ++MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, ++ MV_DEC_WIN *pAddrDecWin); ++ ++ ++ ++ ++#endif /* __INCmvCtrlEnvAddrDech */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,98 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCtrlEnvAsmh ++#define __INCmvCtrlEnvAsmh ++#include "pex/mvPexRegs.h" ++ ++#define CHIP_BOND_REG 0x10034 ++#define PCKG_OPT_MASK_AS #3 ++#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK ++ ++/* Read device ID into toReg bits 15:0 from 0xd0000000 */ ++/* defines */ ++#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ ++ MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ ++ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ ++ ++/* Read device ID into toReg bits 15:0 from 0xf1000000*/ ++#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ ++ MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ ++ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ ++ ++/* Read Revision into toReg bits 7:0 0xd0000000*/ ++#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ ++ /* Read device revision */ \ ++ MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ ++ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ ++ ++/* Read Revision into toReg bits 7:0 0xf1000000*/ ++#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ ++ /* Read device revision */ \ ++ MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ ++ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ ++ ++ ++#endif /* __INCmvCtrlEnvAsmh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,1825 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "mvCommon.h" ++#include "mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++#if defined(MV_INCLUDE_PEX) ++#include "pex/mvPex.h" ++#include "ctrlEnv/sys/mvSysPex.h" ++#endif ++ ++#if defined(MV_INCLUDE_GIG_ETH) ++#include "ctrlEnv/sys/mvSysGbe.h" ++#endif ++ ++#if defined(MV_INCLUDE_XOR) ++#include "ctrlEnv/sys/mvSysXor.h" ++#endif ++ ++#if defined(MV_INCLUDE_SATA) ++#include "ctrlEnv/sys/mvSysSata.h" ++#endif ++ ++#if defined(MV_INCLUDE_USB) ++#include "ctrlEnv/sys/mvSysUsb.h" ++#endif ++ ++#if defined(MV_INCLUDE_AUDIO) ++#include "ctrlEnv/sys/mvSysAudio.h" ++#endif ++ ++#if defined(MV_INCLUDE_CESA) ++#include "ctrlEnv/sys/mvSysCesa.h" ++#endif ++ ++#if defined(MV_INCLUDE_TS) ++#include "ctrlEnv/sys/mvSysTs.h" ++#endif ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/******************************************************************************* ++* mvCtrlEnvInit - Initialize Marvell controller environment. ++* ++* DESCRIPTION: ++* This function get environment information and initialize controller ++* internal/external environment. For example ++* 1) MPP settings according to board MPP macros. ++* NOTE: It is the user responsibility to shut down all DMA channels ++* in device and disable controller sub units interrupts during ++* boot process. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvCtrlEnvInit(MV_VOID) ++{ ++ MV_U32 mppGroup; ++ MV_U32 devId; ++ MV_U32 boardId; ++ MV_U32 i; ++ MV_U32 maxMppGrp = 1; ++ MV_U32 mppVal = 0; ++ MV_U32 bootVal = 0; ++ MV_U32 mppGroupType = 0; ++ MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE; ++ MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE; ++ ++ devId = mvCtrlModelGet(); ++ boardId= mvBoardIdGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_GROUP; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_GROUP; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_GROUP; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_GROUP; ++ break; ++ } ++ ++ /* MPP Init */ ++ /* We split mpp init to 3 phases: ++ * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write ++ * in phase 2. ++ * 2. We detect the mpp group type and according the mpp values [35:20]. ++ * 3. We detect the mpp group type and according the mpp values [49:36]. ++ */ ++ /* Mpp phase 1 mpp[19:0] */ ++ /* Read MPP group from board level and assign to MPP register */ ++ for (mppGroup = 0; mppGroup < 3; mppGroup++) ++ { ++ mppVal = mvBoardMppGet(mppGroup); ++ if (mppGroup == 0) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ if (mvCtrlIsBootFromSPI()) ++ { ++ mppVal &= ~0xffff; ++ bootVal &= 0xffff; ++ mppVal |= bootVal; ++ } ++ else if (mvCtrlIsBootFromSPIUseNAND()) ++ { ++ mppVal &= ~0xf0000000; ++ bootVal &= 0xf0000000; ++ mppVal |= bootVal; ++ } ++ else if (mvCtrlIsBootFromNAND()) ++ { ++ mppVal &= ~0xffffff; ++ bootVal &= 0xffffff; ++ mppVal |= bootVal; ++ } ++ } ++ ++ if (mppGroup == 2) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ if (mvCtrlIsBootFromNAND()) ++ { ++ mppVal &= ~0xff00; ++ bootVal &= 0xff00; ++ mppVal |= bootVal; ++ } ++ } ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); ++ } ++ ++ /* Identify MPPs group */ ++ mvBoardMppGroupIdUpdate(); ++ ++ /* Update MPPs mux relevent only on Marvell DB */ ++ if ((boardId == DB_88F6281A_BP_ID) || ++ (boardId == DB_88F6180A_BP_ID)) ++ mvBoardMppMuxSet(); ++ ++ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1); ++ ++ /* Mpp phase 2 */ ++ /* Read MPP group from board level and assign to MPP register */ ++ if (devId != MV_6180_DEV_ID) ++ { ++ i = 0; ++ for (mppGroup = 2; mppGroup < 5; mppGroup++) ++ { ++ if ((mppGroupType == MV_BOARD_OTHER) || ++ (boardId == RD_88F6281A_ID) || ++ (boardId == RD_88F6192A_ID) || ++ (boardId == RD_88F6190A_ID) || ++ (boardId == RD_88F6281A_PCAC_ID) || ++ (boardId == SHEEVA_PLUG_ID)) ++ mppVal = mvBoardMppGet(mppGroup); ++ else ++ { ++ mppVal = mppGroup1[mppGroupType][i]; ++ i++; ++ } ++ ++ /* Group 2 is shared mpp[23:16] */ ++ if (mppGroup == 2) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ mppVal &= ~0xffff; ++ bootVal &= 0xffff; ++ mppVal |= bootVal; ++ } ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); ++ } ++ } ++ ++ if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID)) ++ return MV_OK; ++ ++ /* Mpp phase 3 */ ++ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2); ++ /* Read MPP group from board level and assign to MPP register */ ++ i = 0; ++ for (mppGroup = 4; mppGroup < 7; mppGroup++) ++ { ++ if ((mppGroupType == MV_BOARD_OTHER) || ++ (boardId == RD_88F6281A_ID) || ++ (boardId == RD_88F6281A_PCAC_ID) || ++ (boardId == SHEEVA_PLUG_ID)) ++ mppVal = mvBoardMppGet(mppGroup); ++ else ++ { ++ mppVal = mppGroup2[mppGroupType][i]; ++ i++; ++ } ++ ++ /* Group 4 is shared mpp[35:32] */ ++ if (mppGroup == 4) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ mppVal &= ~0xffff; ++ bootVal &= 0xffff; ++ mppVal |= bootVal; ++ } ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); ++ } ++ /* Update SSCG configuration register*/ ++ if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6192A_BP_ID || ++ mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID) ++ MV_REG_WRITE(0x100d8, 0x53); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCtrlMppRegGet - return reg address of mpp group ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mppGroup - MPP group. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 - Register address. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) ++{ ++ MV_U32 ret; ++ ++ switch(mppGroup){ ++ case (0): ret = MPP_CONTROL_REG0; ++ break; ++ case (1): ret = MPP_CONTROL_REG1; ++ break; ++ case (2): ret = MPP_CONTROL_REG2; ++ break; ++ case (3): ret = MPP_CONTROL_REG3; ++ break; ++ case (4): ret = MPP_CONTROL_REG4; ++ break; ++ case (5): ret = MPP_CONTROL_REG5; ++ break; ++ case (6): ret = MPP_CONTROL_REG6; ++ break; ++ default: ret = MPP_CONTROL_REG0; ++ break; ++ } ++ return ret; ++} ++#if defined(MV_INCLUDE_PEX) ++/******************************************************************************* ++* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. ++* ++* DESCRIPTION: ++* This function returns Marvell controller number of PEX interfaces. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Marvell controller number of PEX interfaces. If controller ++* ID is undefined the function returns '0'. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlPexMaxIfGet(MV_VOID) ++{ ++ ++ return MV_PEX_MAX_IF; ++} ++#endif ++ ++#if defined(MV_INCLUDE_GIG_ETH) ++/******************************************************************************* ++* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. ++* ++* DESCRIPTION: ++* This function returns Marvell controller number of etherent port. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Marvell controller number of etherent port. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlEthMaxPortGet(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_ETH_MAX_PORTS; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_ETH_MAX_PORTS; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_ETH_MAX_PORTS; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_ETH_MAX_PORTS; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_XOR) ++/******************************************************************************* ++* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. ++* ++* DESCRIPTION: ++* This function returns Marvell controller number of XOR channels. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Marvell controller number of XOR channels. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlXorMaxChanGet(MV_VOID) ++{ ++ return MV_XOR_MAX_CHAN; ++} ++#endif ++ ++#if defined(MV_INCLUDE_USB) ++/******************************************************************************* ++* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* returns number of Marvell USB controllers. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlUsbMaxGet(void) ++{ ++ return MV_USB_MAX_PORTS; ++} ++#endif ++ ++ ++#if defined(MV_INCLUDE_NAND) ++/******************************************************************************* ++* mvCtrlNandSupport - Return if this controller has integrated NAND flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if NAND is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlNandSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_NAND; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_NAND; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_NAND; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_NAND; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_SDIO) ++/******************************************************************************* ++* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if SDIO is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlSdioSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_SDIO; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_SDIO; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_SDIO; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_SDIO; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_TS) ++/******************************************************************************* ++* mvCtrlTsSupport - Return if this controller has integrated TS flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if TS is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlTsSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_TS; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_TS; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_TS; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_TS; ++ break; ++ } ++ return 0; ++} ++#endif ++ ++#if defined(MV_INCLUDE_AUDIO) ++/******************************************************************************* ++* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if AUDIO is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlAudioSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_AUDIO; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_AUDIO; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_AUDIO; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_AUDIO; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_TDM) ++/******************************************************************************* ++* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if TDM is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlTdmSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_TDM; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_TDM; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_TDM; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_TDM; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++/******************************************************************************* ++* mvCtrlModelGet - Get Marvell controller device model (Id) ++* ++* DESCRIPTION: ++* This function returns 16bit describing the device model (ID) as defined ++* in PCI Device and Vendor ID configuration register offset 0x0. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 16bit desscribing Marvell controller ID ++* ++*******************************************************************************/ ++MV_U16 mvCtrlModelGet(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = MV_REG_READ(CHIP_BOND_REG); ++ devId &= PCKG_OPT_MASK; ++ ++ switch(devId){ ++ case 2: ++ return MV_6281_DEV_ID; ++ break; ++ case 1: ++ if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) ++ == MV_6190_DEV_ID) ++ return MV_6190_DEV_ID; ++ else ++ return MV_6192_DEV_ID; ++ break; ++ case 0: ++ return MV_6180_DEV_ID; ++ break; ++ } ++ ++ return 0; ++} ++/******************************************************************************* ++* mvCtrlRevGet - Get Marvell controller device revision number ++* ++* DESCRIPTION: ++* This function returns 8bit describing the device revision as defined ++* in PCI Express Class Code and Revision ID Register. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 8bit desscribing Marvell controller revision number ++* ++*******************************************************************************/ ++MV_U8 mvCtrlRevGet(MV_VOID) ++{ ++ MV_U8 revNum; ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++ /* Check pex power state */ ++ MV_U32 pexPower; ++ pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); ++ if (pexPower == MV_FALSE) ++ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); ++#endif ++ revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID)); ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++ /* Return to power off state */ ++ if (pexPower == MV_FALSE) ++ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); ++#endif ++ return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); ++} ++ ++/******************************************************************************* ++* mvCtrlNameGet - Get Marvell controller name ++* ++* DESCRIPTION: ++* This function returns a string describing the device model and revision. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. ++* ++* RETURN: ++* ++* MV_ERROR if informantion can not be read. ++*******************************************************************************/ ++MV_STATUS mvCtrlNameGet(char *pNameBuff) ++{ ++ mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, ++ mvCtrlModelGet(), mvCtrlRevGet()); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision ++* ++* DESCRIPTION: ++* This function returns 32bit value describing both Device ID and Revision ++* as defined in PCI Express Device and Vendor ID Register and device revision ++* as defined in PCI Express Class Code and Revision ID Register. ++ ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing both controller device ID and revision number ++* ++*******************************************************************************/ ++MV_U32 mvCtrlModelRevGet(MV_VOID) ++{ ++ return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); ++} ++ ++/******************************************************************************* ++* mvCtrlModelRevNameGet - Get Marvell controller name ++* ++* DESCRIPTION: ++* This function returns a string describing the device model and revision. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. ++* ++* RETURN: ++* ++* MV_ERROR if informantion can not be read. ++*******************************************************************************/ ++ ++MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) ++{ ++ ++ switch (mvCtrlModelRevGet()) ++ { ++ case MV_6281_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME); ++ break; ++ case MV_6192_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME); ++ break; ++ case MV_6180_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME); ++ break; ++ case MV_6190_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME); ++ break; ++ case MV_6281_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME); ++ break; ++ case MV_6192_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME); ++ break; ++ case MV_6180_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME); ++ break; ++ case MV_6190_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME); ++ break; ++ default: ++ mvCtrlNameGet(pNameBuff); ++ break; ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* ctrlWinOverlapTest - Test address windows for overlaping. ++* ++* DESCRIPTION: ++* This function checks the given two address windows for overlaping. ++* ++* INPUT: ++* pAddrWin1 - Address window 1. ++* pAddrWin2 - Address window 2. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* MV_TRUE if address window overlaps, MV_FALSE otherwise. ++*******************************************************************************/ ++MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) ++{ ++ MV_U32 winBase1, winBase2; ++ MV_U32 winTop1, winTop2; ++ ++ /* check if we have overflow than 4G*/ ++ if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)|| ++ ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1)) ++ { ++ return MV_TRUE; ++ } ++ ++ winBase1 = pAddrWin1->baseLow; ++ winBase2 = pAddrWin2->baseLow; ++ winTop1 = winBase1 + pAddrWin1->size-1; ++ winTop2 = winBase2 + pAddrWin2->size-1; ++ ++ ++ if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) || ++ ((winBase1 <= winBase2) && (winBase2 <= winTop1))) ++ { ++ return MV_TRUE; ++ } ++ else ++ { ++ return MV_FALSE; ++ } ++} ++ ++/******************************************************************************* ++* ctrlWinWithinWinTest - Test address windows for overlaping. ++* ++* DESCRIPTION: ++* This function checks the given win1 boundries is within ++* win2 boundries. ++* ++* INPUT: ++* pAddrWin1 - Address window 1. ++* pAddrWin2 - Address window 2. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. ++*******************************************************************************/ ++MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) ++{ ++ MV_U32 winBase1, winBase2; ++ MV_U32 winTop1, winTop2; ++ ++ winBase1 = pAddrWin1->baseLow; ++ winBase2 = pAddrWin2->baseLow; ++ winTop1 = winBase1 + pAddrWin1->size -1; ++ winTop2 = winBase2 + pAddrWin2->size -1; ++ ++ if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || ++ ((winTop1 >= winBase2) && (winTop1 <= winTop2))) ++ { ++ return MV_TRUE; ++ } ++ else ++ { ++ return MV_FALSE; ++ } ++} ++ ++static const char* cntrlName[] = TARGETS_NAME_ARRAY; ++ ++/******************************************************************************* ++* mvCtrlTargetNameGet - Get Marvell controller target name ++* ++* DESCRIPTION: ++* This function convert the trget enumeration to string. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Target name (const MV_8 *) ++*******************************************************************************/ ++const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) ++{ ++ ++ if (target >= MAX_TARGETS) ++ { ++ return "target unknown"; ++ } ++ ++ return cntrlName[target]; ++} ++ ++/******************************************************************************* ++* mvCtrlAddrDecShow - Print the Controller units address decode map. ++* ++* DESCRIPTION: ++* This function the Controller units address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvCtrlAddrDecShow(MV_VOID) ++{ ++ mvCpuIfAddDecShow(); ++ mvAhbToMbusAddDecShow(); ++#if defined(MV_INCLUDE_PEX) ++ mvPexAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_USB) ++ mvUsbAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ mvEthAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_XOR) ++ mvXorAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_SATA) ++ mvSataAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ mvAudioAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_TS) ++ mvTsuAddrDecShow(); ++#endif ++} ++ ++/******************************************************************************* ++* ctrlSizeToReg - Extract size value for register assignment. ++* ++* DESCRIPTION: ++* Address decode size parameter must be programed from LSB to MSB as ++* sequence of 1's followed by sequence of 0's. The number of 1's ++* specifies the size of the window in 64 KB granularity (e.g. a ++* value of 0x00ff specifies 256x64k = 16 MB). ++* This function extract the size value from the size parameter according ++* to given aligment paramter. For example for size 0x1000000 (16MB) and ++* aligment 0x10000 (64KB) the function will return 0x00FF. ++* ++* INPUT: ++* size - Size. ++* alignment - Size alignment. Note that alignment must be power of 2! ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing size register value correspond to size parameter. ++* If value is '-1' size parameter or aligment are invalid. ++*******************************************************************************/ ++MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) ++{ ++ MV_U32 retVal; ++ ++ /* Check size parameter alignment */ ++ if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); ++ return -1; ++ } ++ ++ /* Take out the "alignment" portion out of the size parameter */ ++ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ ++ /* and size is 0x1000000 (16MB) for example */ ++ while(alignment & 1) /* Check that alignmet LSB is set */ ++ { ++ size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ ++ alignment = (alignment >> 1); ++ } ++ ++ /* If after the alignment first '0' was met we still have '1' in */ ++ /* it then aligment is invalid (not power of 2) */ ++ if (alignment) ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", ++ (MV_U32)alignment)); ++ return -1; ++ } ++ ++ /* Now the size is shifted right according to aligment: 0x0100 */ ++ size--; /* Now the size is a sequance of '1': 0x00ff */ ++ ++ retVal = size ; ++ ++ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ ++ while(size & 1) /* Check that LSB is set */ ++ { ++ size = (size >> 1); /* If LSB is set, move one bit to the right */ ++ } ++ ++ if (size) /* Sequance of 1's is over. Check that we have no other 1's */ ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", ++ size)); ++ return -1; ++ } ++ ++ return retVal; ++ ++} ++ ++/******************************************************************************* ++* ctrlRegToSize - Extract size value from register value. ++* ++* DESCRIPTION: ++* This function extract a size value from the register size parameter ++* according to given aligment paramter. For example for register size ++* value 0xff and aligment 0x10000 the function will return 0x01000000. ++* ++* INPUT: ++* regSize - Size as in register format. See ctrlSizeToReg. ++* alignment - Size alignment. Note that alignment must be power of 2! ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing size. ++* If value is '-1' size parameter or aligment are invalid. ++*******************************************************************************/ ++MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) ++{ ++ MV_U32 temp; ++ ++ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ ++ temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ ++ ++ while(temp & 1) /* Check that LSB is set */ ++ { ++ temp = (temp >> 1); /* If LSB is set, move one bit to the right */ ++ } ++ ++ if (temp) /* Sequance of 1's is over. Check that we have no other 1's */ ++ { ++ DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", ++ regSize)); ++ return -1; ++ } ++ ++ ++ /* Check that aligment is a power of two */ ++ temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ ++ ++ while(temp & 1) /* Check that alignmet LSB is set */ ++ { ++ temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ ++ } ++ ++ /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ ++ /* then 'temp' is invalid (not power of 2) */ ++ if (temp) ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", ++ alignment)); ++ return -1; ++ } ++ ++ regSize++; /* Now the size is 0x0100 */ ++ ++ /* Add in the "alignment" portion to the register size parameter */ ++ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ ++ ++ while(alignment & 1) /* Check that alignmet LSB is set */ ++ { ++ regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ ++ alignment = (alignment >> 1); ++ } ++ ++ return regSize; ++} ++ ++ ++/******************************************************************************* ++* ctrlSizeRegRoundUp - Round up given size ++* ++* DESCRIPTION: ++* This function round up a given size to a size that fits the ++* restrictions of size format given an aligment parameter. ++* to given aligment paramter. For example for size parameter 0xa1000 and ++* aligment 0x1000 the function will return 0xFF000. ++* ++* INPUT: ++* size - Size. ++* alignment - Size alignment. Note that alignment must be power of 2! ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing size value correspond to size in register. ++*******************************************************************************/ ++MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) ++{ ++ MV_U32 msbBit = 0; ++ MV_U32 retSize; ++ ++ /* Check if size parameter is already comply with restriction */ ++ if (!(-1 == ctrlSizeToReg(size, alignment))) ++ { ++ return size; ++ } ++ ++ while(size) ++ { ++ size = (size >> 1); ++ msbBit++; ++ } ++ ++ retSize = (1 << msbBit); ++ ++ if (retSize < alignment) ++ { ++ return alignment; ++ } ++ else ++ { ++ return retSize; ++ } ++} ++/******************************************************************************* ++* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button ++* was pressed and clear counter ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: number of milliseconds the reset button was pressed ++*******************************************************************************/ ++MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID) ++{ ++ static volatile MV_U32 Count = 0; ++ ++ if(!Count) { ++ Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK); ++ Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000)); ++ /* clear counter for next boot */ ++ MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK); ++ } ++ ++ DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count)); ++ ++ return Count; ++} ++ ++MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) ++{ ++ MV_U32 satr = 0; ++ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ { ++ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++ } ++ satr = satr & MSAR_BOOT_MODE_MASK; ++ if (satr == MSAR_BOOT_SPI_WITH_BOOTROM) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++} ++ ++MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID) ++{ ++ MV_U32 satr = 0; ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return MV_FALSE; ++ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ satr = satr & MSAR_BOOT_MODE_MASK; ++ ++ if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++} ++ ++MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) ++{ ++ MV_U32 satr = 0; ++ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ { ++ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++ } ++ satr = satr & MSAR_BOOT_MODE_MASK; ++ if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM)) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++} ++ ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++/******************************************************************************* ++* mvCtrlPwrSaveOn - Set Power save mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrSaveOn(MV_VOID) ++{ ++ unsigned long old,temp; ++ /* Disable int */ ++ __asm__ __volatile__("mrs %0, cpsr\n" ++ "orr %1, %0, #0xc0\n" ++ "msr cpsr_c, %1" ++ : "=r" (old), "=r" (temp) ++ : ++ : "memory"); ++ ++ /* Set SoC in power save */ ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11); ++ /* Wait for int */ ++ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); ++ ++ /* Enabled int */ ++ __asm__ __volatile__("msr cpsr_c, %0" ++ : ++ : "r" (old) ++ : "memory"); ++} ++ ++ ++ ++/******************************************************************************* ++* mvCtrlPwrSaveOff - Go out of power save mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrSaveOff(MV_VOID) ++{ ++ unsigned long old,temp; ++ /* Disable int */ ++ __asm__ __volatile__("mrs %0, cpsr\n" ++ "orr %1, %0, #0xc0\n" ++ "msr cpsr_c, %1" ++ : "=r" (old), "=r" (temp) ++ : ++ : "memory"); ++ ++ /* Set SoC in power save */ ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11); ++ /* Wait for int */ ++ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); ++ ++ /* Enabled int */ ++ __asm__ __volatile__("msr cpsr_c, %0" ++ : ++ : "r" (old) ++ : "memory"); ++} ++ ++/******************************************************************************* ++* mvCtrlPwrClckSet - Set Power State for specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) ++{ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_INTEG_SATA) ++ case SATA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_TS) ++ case TS_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_SDIO) ++ case SDIO_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_TDM) ++ case TDM_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++ ++ default: ++ ++ break; ++ ++ } ++} ++ ++/******************************************************************************* ++* mvCtrlPwrClckGet - Get Power State of specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) ++{ ++ MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); ++ MV_BOOL state = MV_TRUE; ++ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_SATA) ++ case SATA_UNIT_ID: ++ if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_TS) ++ case TS_UNIT_ID: ++ if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_SDIO) ++ case SDIO_UNIT_ID: ++ if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_TDM) ++ case TDM_UNIT_ID: ++ if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++ ++ default: ++ state = MV_TRUE; ++ break; ++ } ++ ++ ++ return state; ++} ++/******************************************************************************* ++* mvCtrlPwrMemSet - Set Power State for memory on specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) ++{ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_INTEG_SATA) ++ case SATA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_XOR) ++ case XOR_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); ++ } ++ break; ++#endif ++ default: ++ ++ break; ++ ++ } ++} ++ ++/******************************************************************************* ++* mvCtrlPwrMemGet - Get Power State of memory on specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) ++{ ++ MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG); ++ MV_BOOL state = MV_TRUE; ++ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if ((reg & PMC_PEXSTOPMEM_MASK) == PMC_PEXSTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_SATA) ++ case SATA_UNIT_ID: ++ if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_XOR) ++ case XOR_UNIT_ID: ++ if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++ ++ default: ++ state = MV_TRUE; ++ break; ++ } ++ ++ ++ return state; ++} ++#else ++MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} ++MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} ++#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ ++ ++ ++/******************************************************************************* ++* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_VOID mvMPPConfigToSPI(MV_VOID) ++{ ++ MV_U32 mppVal = 0; ++ MV_U32 bootVal = 0; ++ ++ if(!mvCtrlIsBootFromSPIUseNAND()) ++ return; ++ mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */ ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); ++ bootVal &= 0xffff000f; ++ mppVal |= bootVal; ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); ++} ++ ++ ++/******************************************************************************* ++* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_VOID mvMPPConfigToDefault(MV_VOID) ++{ ++ MV_U32 mppVal = 0; ++ MV_U32 bootVal = 0; ++ ++ if(!mvCtrlIsBootFromSPIUseNAND()) ++ return; ++ mppVal = mvBoardMppGet(0); ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); ++ mppVal &= ~0xffff000f; ++ bootVal &= 0xffff000f; ++ mppVal |= bootVal; ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); ++} ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,185 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCtrlEnvLibh ++#define __INCmvCtrlEnvLibh ++ ++/* includes */ ++#include "mvSysHwConfig.h" ++#include "mvCommon.h" ++#include "mvTypes.h" ++#include "mvOs.h" ++#include "boardEnv/mvBoardEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/mvCtrlEnvRegs.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++ ++/* typedefs */ ++ ++/* This enumerator describes the possible HW cache coherency policies the */ ++/* controllers supports. */ ++typedef enum _mvCachePolicy ++{ ++ NO_COHERENCY, /* No HW cache coherency support */ ++ WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ ++ WB_COHERENCY /* HW cache coherency supported in Write Back policy */ ++}MV_CACHE_POLICY; ++ ++ ++/* The swapping is referred to a 64-bit words (as this is the controller */ ++/* internal data path width). This enumerator describes the possible */ ++/* data swap types. Below is an example of the data 0x0011223344556677 */ ++typedef enum _mvSwapType ++{ ++ MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ ++ MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ ++ MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ ++ MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ ++ SWAP_TYPE_MAX /* Delimiter for this enumerator */ ++}MV_SWAP_TYPE; ++ ++/* This structure describes access rights for Access protection windows */ ++/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ ++/* Note that the permission enumerator coresponds to its register format. */ ++/* For example, Read only premission is presented as "1" in register field. */ ++typedef enum _mvAccessRights ++{ ++ NO_ACCESS_ALLOWED = 0, /* No access allowed */ ++ READ_ONLY = 1, /* Read only permission */ ++ ACC_RESERVED = 2, /* Reserved access right */ ++ FULL_ACCESS = 3, /* Read and Write permission */ ++ MAX_ACC_RIGHTS ++}MV_ACCESS_RIGHTS; ++ ++ ++/* mcspLib.h API list */ ++ ++MV_STATUS mvCtrlEnvInit(MV_VOID); ++MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); ++ ++#if defined(MV_INCLUDE_PEX) ++MV_U32 mvCtrlPexMaxIfGet(MV_VOID); ++#else ++#define mvCtrlPexMaxIfGet() (0) ++#endif ++ ++#define mvCtrlPciIfMaxIfGet() (0) ++ ++#if defined(MV_INCLUDE_GIG_ETH) ++MV_U32 mvCtrlEthMaxPortGet(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_XOR) ++MV_U32 mvCtrlXorMaxChanGet(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_USB) ++MV_U32 mvCtrlUsbMaxGet(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_NAND) ++MV_U32 mvCtrlNandSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_SDIO) ++MV_U32 mvCtrlSdioSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_TS) ++MV_U32 mvCtrlTsSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++MV_U32 mvCtrlAudioSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_TDM) ++MV_U32 mvCtrlTdmSupport(MV_VOID); ++#endif ++ ++MV_U16 mvCtrlModelGet(MV_VOID); ++MV_U8 mvCtrlRevGet(MV_VOID); ++MV_STATUS mvCtrlNameGet(char *pNameBuff); ++MV_U32 mvCtrlModelRevGet(MV_VOID); ++MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); ++MV_VOID mvCtrlAddrDecShow(MV_VOID); ++const MV_8* mvCtrlTargetNameGet(MV_TARGET target); ++MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); ++MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); ++MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); ++MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); ++MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); ++MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); ++ ++MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); ++MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); ++MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); ++MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); ++MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID); ++MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++MV_VOID mvCtrlPwrSaveOn(MV_VOID); ++MV_VOID mvCtrlPwrSaveOff(MV_VOID); ++#endif ++MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); ++MV_VOID mvMPPConfigToSPI(MV_VOID); ++MV_VOID mvMPPConfigToDefault(MV_VOID); ++ ++ ++#endif /* __INCmvCtrlEnvLibh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,419 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvCtrlEnvRegsh ++#define __INCmvCtrlEnvRegsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* CV Support */ ++#define PEX0_MEM0 PEX0_MEM ++#define PCI0_MEM0 PEX0_MEM ++ ++/* Controller revision info */ ++#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 ++#define PCCRIR_REVID_OFFS 0 /* Revision ID */ ++#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) ++ ++/* Controler environment registers offsets */ ++ ++/* Power Managment Control */ ++#define POWER_MNG_MEM_CTRL_REG 0x20118 ++ ++#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0) ++#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port)) ++#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) ++#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) ++ ++#define PMC_PEXSTOPMEM_OFFS 1 ++#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS) ++#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS) ++#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS) ++ ++#define PMC_USBSTOPMEM_OFFS 2 ++#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS) ++#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS) ++#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS) ++ ++#define PMC_DUNITSTOPMEM_OFFS 3 ++#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS) ++#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) ++#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) ++ ++#define PMC_RUNITSTOPMEM_OFFS 4 ++#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS) ++#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS) ++#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS) ++ ++#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2)) ++#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port)) ++#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) ++#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) ++ ++#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5)) ++#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port)) ++#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) ++#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port)) ++ ++#define PMC_SESTOPMEM_OFFS 8 ++#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS) ++#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS) ++#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS) ++ ++#define PMC_AUDIOSTOPMEM_OFFS 9 ++#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS) ++#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS) ++#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS) ++ ++#define POWER_MNG_CTRL_REG 0x2011C ++ ++#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0) ++#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) ++#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) ++#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) ++ ++#define PMC_PEXPHYSTOPCLOCK_OFFS 1 ++#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS) ++#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS) ++#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS) ++ ++#define PMC_PEXSTOPCLOCK_OFFS 2 ++#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) ++#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS) ++#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS) ++ ++#define PMC_USBSTOPCLOCK_OFFS 3 ++#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) ++#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS) ++#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS) ++ ++#define PMC_SDIOSTOPCLOCK_OFFS 4 ++#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) ++#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) ++#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) ++ ++#define PMC_TSSTOPCLOCK_OFFS 5 ++#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS) ++#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS) ++#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS) ++ ++#define PMC_AUDIOSTOPCLOCK_OFFS 9 ++#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS) ++#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS) ++#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS) ++ ++#define PMC_POWERSAVE_OFFS 11 ++#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS) ++#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS) ++#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS) ++ ++ ++ ++ ++#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port)) ++#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) ++#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) ++#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port)) ++ ++#define PMC_SESTOPCLOCK_OFFS 17 ++#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) ++#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS) ++#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS) ++ ++#define PMC_TDMSTOPCLOCK_OFFS 20 ++#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) ++#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) ++#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) ++ ++ ++/* Controler environment registers offsets */ ++#define MPP_CONTROL_REG0 0x10000 ++#define MPP_CONTROL_REG1 0x10004 ++#define MPP_CONTROL_REG2 0x10008 ++#define MPP_CONTROL_REG3 0x1000C ++#define MPP_CONTROL_REG4 0x10010 ++#define MPP_CONTROL_REG5 0x10014 ++#define MPP_CONTROL_REG6 0x10018 ++#define MPP_SAMPLE_AT_RESET 0x10030 ++#define CHIP_BOND_REG 0x10034 ++#define SYSRST_LENGTH_COUNTER_REG 0x10050 ++#define SLCR_COUNT_OFFS 0 ++#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) ++#define SLCR_CLR_OFFS 31 ++#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) ++#define PCKG_OPT_MASK 0x3 ++#define MPP_OUTPUT_DRIVE_REG 0x100E0 ++#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7 ++#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) ++#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) ++#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15 ++#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) ++#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) ++ ++#define MSAR_BOOT_MODE_OFFS 12 ++#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS) ++#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS) ++#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS) ++#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS) ++ ++#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \ ++ ((X & 0x2) << 1)) ++#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1 ++#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5 ++ ++#define MSAR_TCLCK_OFFS 21 ++#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) ++#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) ++#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS) ++ ++ ++#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \ ++ ((X & 0x18) >> 1)) ++ ++#define MSAR_CPUCLCK_OFFS_6180 2 ++#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180) ++ ++#define MSAR_DDRCLCK_RTIO_OFFS 5 ++#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS) ++ ++#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17)) ++ ++#ifndef MV_ASMLANGUAGE ++/* CPU clock for 6281,6192 0->Resereved */ ++#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \ ++ 600000000, 0, 800000000, 1000000000, \ ++ 0, 1200000000, 0, 0, \ ++ 1500000000, 0, 0, 0} ++ ++/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */ ++#define MV_DDR_CLCK_RTIO_TBL {\ ++ {0, 0}, {0, 0}, {2, 1}, {0, 0}, \ ++ {3, 1}, {0, 0}, {4, 1}, {9, 2}, \ ++ {5, 1}, {6, 1}, {0, 0}, {0, 0}, \ ++ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ ++} ++ ++/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */ ++#define MV_L2_CLCK_RTIO_TBL {\ ++ {0, 0}, {2, 1}, {0, 0}, {3, 1}, \ ++ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ ++} ++ ++/* 6180 have different clk reset sampling */ ++/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */ ++#define MV_CPU6180_DDR_L2_CLCK_TBL { \ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {600000000, 200000000, 300000000 },\ ++ {800000000, 200000000, 400000000 },\ ++ {0, 0, 0 }\ ++} ++ ++ ++ ++/* These macros help units to identify a target Mbus Arbiter group */ ++#define MV_TARGET_IS_DRAM(target) \ ++ ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) ++ ++#define MV_TARGET_IS_PEX0(target) \ ++ ((target >= PEX0_MEM) && (target <= PEX0_IO)) ++ ++#define MV_TARGET_IS_PEX1(target) 0 ++ ++#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) ++ ++#define MV_TARGET_IS_DEVICE(target) \ ++ ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) ++ ++#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 ++ ++#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \ ++ (mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \ ++ (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ ++ & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) ++ ++ ++#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\ ++ sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \ ++ MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \ ++ ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\ ++ >> MSAR_BOOT_MODE_OFFS)]:(target)) ++ ++#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ ++ ++#define BOOT_TARGETS_NAME_ARRAY { \ ++ TBL_TERM, \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ TBL_TERM \ ++} ++ ++#define BOOT_TARGETS_NAME_ARRAY_6180 { \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ TBL_TERM, \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ TBL_TERM \ ++} ++ ++ ++/* For old competability */ ++#define DEVICE_CS0 NFLASH_CS ++#define DEVICE_CS1 SPI_CS ++#define DEVICE_CS2 BOOT_ROM_CS ++#define DEVICE_CS3 DEV_BOOCS ++#define MV_BOOTDEVICE_INDEX 0 ++ ++#define START_DEV_CS DEV_CS0 ++#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) ++ ++#define PCI_IF0_MEM0 PEX0_MEM ++#define PCI_IF0_IO PEX0_IO ++ ++ ++/* This enumerator defines the Marvell controller target ID */ ++typedef enum _mvTargetId ++{ ++ DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ ++ DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */ ++ PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ ++ CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */ ++ SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */ ++ MAX_TARGETS_ID ++}MV_TARGET_ID; ++ ++ ++/* This enumerator described the possible Controller paripheral targets. */ ++/* Controller peripherals are designated memory/IO address spaces that the */ ++/* controller can access. They are also refered as "targets" */ ++typedef enum _mvTarget ++{ ++ TBL_TERM = -1, /* none valid target, used as targets list terminator*/ ++ SDRAM_CS0, /* SDRAM chip select 0 */ ++ SDRAM_CS1, /* SDRAM chip select 1 */ ++ SDRAM_CS2, /* SDRAM chip select 2 */ ++ SDRAM_CS3, /* SDRAM chip select 3 */ ++ PEX0_MEM, /* PCI Express 0 Memory */ ++ PEX0_IO, /* PCI Express 0 IO */ ++ INTER_REGS, /* Internal registers */ ++ NFLASH_CS, /* NFLASH_CS */ ++ SPI_CS, /* SPI_CS */ ++ BOOT_ROM_CS, /* BOOT_ROM_CS */ ++ DEV_BOOCS, /* DEV_BOOCS */ ++ CRYPT_ENG, /* Crypto Engine */ ++#ifdef MV_INCLUDE_SAGE ++ SAGE_UNIT, /* SAGE Unit */ ++#endif ++ MAX_TARGETS ++ ++}MV_TARGET; ++ ++#define TARGETS_DEF_ARRAY { \ ++ {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ ++ {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ ++ {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ ++ {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ ++ {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \ ++ {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \ ++ {0xFF, 0xFF }, /* INTER_REGS */ \ ++ {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \ ++ {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \ ++ {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ ++ {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \ ++ {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \ ++ {0x00, SAGE_TARGET_ID } \ ++} ++ ++ ++#define TARGETS_NAME_ARRAY { \ ++ "SDRAM_CS0", /* SDRAM_CS0 */ \ ++ "SDRAM_CS1", /* SDRAM_CS1 */ \ ++ "SDRAM_CS2", /* SDRAM_CS2 */ \ ++ "SDRAM_CS3", /* SDRAM_CS3 */ \ ++ "PEX0_MEM", /* PEX0_MEM */ \ ++ "PEX0_IO", /* PEX0_IO */ \ ++ "INTER_REGS", /* INTER_REGS */ \ ++ "NFLASH_CS", /* NFLASH_CS */ \ ++ "SPI_CS", /* SPI_CS */ \ ++ "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ ++ "DEV_BOOTCS", /* DEV_BOOCS */ \ ++ "CRYPT_ENG", /* CRYPT_ENG */ \ ++ "SAGE_UNIT" /* SAGE_UNIT */ \ ++} ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#endif +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,257 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvCtrlEnvSpech ++#define __INCmvCtrlEnvSpech ++ ++#include "mvDeviceId.h" ++#include "mvSysHwConfig.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#define MV_ARM_SOC ++#define SOC_NAME_PREFIX "MV88F" ++ ++ ++/* units base and port numbers */ ++#ifdef MV_ASMLANGUAGE ++#define XOR_UNIT_BASE(unit) 0x60800 ++#else ++#define MV_XOR_REG_BASE 0x60000 ++#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800) ++#endif ++ ++#define TDM_REG_BASE 0xD0000 ++#define USB_REG_BASE(dev) 0x50000 ++#define AUDIO_REG_BASE 0xA0000 ++#define SATA_REG_BASE 0x80000 ++#define MV_CESA_REG_BASE 0x3D000 ++#define MV_CESA_TDMA_REG_BASE 0x30000 ++#define MV_SDIO_REG_BASE 0x90000 ++#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000) ++#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) ++#define DRAM_BASE 0x0 ++#define CNTMR_BASE 0x20300 ++#define TWSI_SLAVE_BASE(chanNum) 0x11000 ++#define PEX_IF_BASE(pexIf) 0x40000 ++#define MPP_REG_BASE 0x10000 ++#define TSU_GLOBAL_REG_BASE 0xB4000 ++#define MAX_AHB_TO_MBUS_REG_BASE 0x20000 ++ ++#define INTER_REGS_SIZE _1M ++/* This define describes the TWSI interrupt bit and location */ ++#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200 ++#define TWSI0_CPU_MAIN_INT_BIT (1<<29) ++#define TWSI_SPEED 100000 ++ ++#define MV_GPP_MAX_GROUP 2 ++#define MV_CNTMR_MAX_COUNTER 2 ++#define MV_UART_MAX_CHAN 2 ++#define MV_XOR_MAX_UNIT 2 ++#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ ++#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ ++#define MV_SATA_MAX_CHAN 2 ++ ++#define MV_6281_MPP_MAX_MODULE 2 ++#define MV_6192_MPP_MAX_MODULE 1 ++#define MV_6190_MPP_MAX_MODULE 1 ++#define MV_6180_MPP_MAX_MODULE 2 ++#define MV_6281_MPP_MAX_GROUP 7 ++#define MV_6192_MPP_MAX_GROUP 4 ++#define MV_6190_MPP_MAX_GROUP 4 ++#define MV_6180_MPP_MAX_GROUP 3 ++ ++#define MV_DRAM_MAX_CS 4 ++ ++/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ ++#define MV_PCI_MAX_IF 0 ++#define MV_PCI_START_IF 0 ++ ++/* This define describes the maximum number of supported PEX Interfaces */ ++#define MV_INCLUDE_PEX0 ++#define MV_DISABLE_PEX_DEVICE_BAR ++#define MV_PEX_MAX_IF 1 ++#define MV_PEX_START_IF MV_PCI_MAX_IF ++ ++/* This define describes the maximum number of supported PCI Interfaces */ ++#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) ++ ++#define MV_ETH_MAX_PORTS 2 ++#define MV_6281_ETH_MAX_PORTS 2 ++#define MV_6192_ETH_MAX_PORTS 2 ++#define MV_6190_ETH_MAX_PORTS 1 ++#define MV_6180_ETH_MAX_PORTS 1 ++ ++#define MV_IDMA_MAX_CHAN 0 ++ ++#define MV_USB_MAX_PORTS 1 ++ ++#define MV_USB_VERSION 1 ++ ++ ++#define MV_6281_NAND 1 ++#define MV_6192_NAND 1 ++#define MV_6190_NAND 1 ++#define MV_6180_NAND 0 ++ ++#define MV_6281_SDIO 1 ++#define MV_6192_SDIO 1 ++#define MV_6190_SDIO 1 ++#define MV_6180_SDIO 1 ++ ++#define MV_6281_TS 1 ++#define MV_6192_TS 1 ++#define MV_6190_TS 0 ++#define MV_6180_TS 0 ++ ++#define MV_6281_AUDIO 1 ++#define MV_6192_AUDIO 1 ++#define MV_6190_AUDIO 0 ++#define MV_6180_AUDIO 1 ++ ++#define MV_6281_TDM 1 ++#define MV_6192_TDM 1 ++#define MV_6190_TDM 0 ++#define MV_6180_TDM 0 ++ ++#define MV_DEVICE_MAX_CS 4 ++ ++/* Others */ ++#define PEX_HOST_BUS_NUM(pciIf) (pciIf) ++#define PEX_HOST_DEV_NUM(pciIf) 0 ++ ++#define PCI_IO(pciIf) (PEX0_IO) ++#define PCI_MEM(pciIf, memNum) (PEX0_MEM0) ++/* CESA version #2: One channel, 2KB SRAM, TDMA */ ++#if defined(MV_CESA_CHAIN_MODE_SUPPORT) ++ #define MV_CESA_VERSION 3 ++#else ++#define MV_CESA_VERSION 2 ++#endif ++#define MV_CESA_SRAM_SIZE 2*1024 ++/* This define describes the maximum number of supported Ethernet ports */ ++#define MV_ETH_VERSION 4 ++#define MV_ETH_MAX_RXQ 8 ++#define MV_ETH_MAX_TXQ 8 ++#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE } ++/* This define describes the the support of USB */ ++#define MV_USB_VERSION 1 ++ ++#define MV_INCLUDE_SDRAM_CS0 ++#define MV_INCLUDE_SDRAM_CS1 ++#define MV_INCLUDE_SDRAM_CS2 ++#define MV_INCLUDE_SDRAM_CS3 ++ ++#define MV_INCLUDE_DEVICE_CS0 ++#define MV_INCLUDE_DEVICE_CS1 ++#define MV_INCLUDE_DEVICE_CS2 ++#define MV_INCLUDE_DEVICE_CS3 ++ ++#define MPP_GROUP_1_TYPE {\ ++ {0, 0, 0}, /* Reserved for AUTO */ \ ++ {0x22220000, 0x22222222, 0x2222}, /* TDM */ \ ++ {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \ ++ {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \ ++ {0x33330000, 0x03333333, 0x0033}, /* GMII */ \ ++ {0x11110000, 0x11111111, 0x0001}, /* TS */ \ ++ {0x33330000, 0x33333333, 0x3333} /* MII */ \ ++} ++ ++#define MPP_GROUP_2_TYPE {\ ++ {0, 0, 0}, /* Reserved for AUTO */ \ ++ {0x22220000, 0x22222222, 0x22}, /* TDM */ \ ++ {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \ ++ {0, 0, 0}, /* N_A */ \ ++ {0, 0, 0}, /* N_A */ \ ++ {0x11110000, 0x11111111, 0x01} /* TS */ \ ++} ++ ++#ifndef MV_ASMLANGUAGE ++ ++/* This enumerator defines the Marvell Units ID */ ++typedef enum _mvUnitId ++{ ++ DRAM_UNIT_ID, ++ PEX_UNIT_ID, ++ ETH_GIG_UNIT_ID, ++ USB_UNIT_ID, ++ IDMA_UNIT_ID, ++ XOR_UNIT_ID, ++ SATA_UNIT_ID, ++ TDM_UNIT_ID, ++ UART_UNIT_ID, ++ CESA_UNIT_ID, ++ SPI_UNIT_ID, ++ AUDIO_UNIT_ID, ++ SDIO_UNIT_ID, ++ TS_UNIT_ID, ++ MAX_UNITS_ID ++ ++}MV_UNIT_ID; ++ ++#endif ++ ++#endif /* __INCmvCtrlEnvSpech */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,1048 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "ctrlEnv/sys/mvAhbToMbus.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++#undef MV_DEBUG ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* typedefs */ ++ ++ ++/* CPU address remap registers offsets are inconsecutive. This struct */ ++/* describes address remap register offsets */ ++typedef struct _ahbToMbusRemapRegOffs ++{ ++ MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ ++ MV_U32 highRegOffs; /* High 32 bit remap register offset */ ++}AHB_TO_MBUS_REMAP_REG_OFFS; ++ ++/* locals */ ++static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum, ++ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); ++ ++/******************************************************************************* ++* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK laways. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusInit(void) ++{ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window ++* ++* DESCRIPTION: ++* This function sets ++* address window, also known as address decode window. ++* A new address decode window is set for specified winNum address window. ++* If address decode window parameter structure enables the window, ++* the routine will also enable the winNum window, allowing CPU to access ++* the winNum window. ++* ++* INPUT: ++* winNum - Windows number. ++* pAddrDecWin - CPU winNum window data structure. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of ++* address window overlapps with other active CPU winNum window or ++* trying to assign 36bit base address while CPU does not support that. ++* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttribs; ++ MV_DEC_REGS decRegs; ++ ++ /* Parameter checking */ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ ++ /* read base register*/ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); ++ } ++ else ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ /* read control register*/ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); ++ } ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* enable\Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ decRegs.sizeReg |= ATMWCR_WIN_ENABLE; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; ++ decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; ++ /* set target ID */ ++ decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; ++ decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; ++ ++#if !defined(MV_RUN_FROM_FLASH) ++ /* To be on the safe side we disable the window before writing the */ ++ /* new values. */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ mvAhbToMbusWinEnable(winNum,MV_FALSE); ++ } ++#endif ++ ++ /* 3) Write to address decode Base Address Register */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); ++ } ++ else ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); ++ } ++ ++ ++ /* Internal register space have no size */ ++ /* register. Do not perform size register assigment for those targets */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window ++* ++* DESCRIPTION: ++* Get the CPU peripheral winNum address window. ++* ++* INPUT: ++* winNum - Peripheral winNum enumerator ++* ++* OUTPUT: ++* pAddrDecWin - CPU winNum window information data structure. ++* ++* RETURN: ++* MV_OK if winNum exist, MV_ERROR otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ ++ /* Parameter checking */ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ ++ /* Internal register space size have no size register*/ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); ++ } ++ else ++ { ++ decRegs.sizeReg = 0; ++ } ++ ++ ++ /* Read base and size */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); ++ } ++ else ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); ++ } ++ ++ ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ pAddrDecWin->addrWin.size = INTER_REGS_SIZE; ++ pAddrDecWin->target = INTER_REGS; ++ pAddrDecWin->enable = MV_TRUE; ++ ++ return MV_OK; ++ } ++ ++ ++ if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ ++ } ++ ++ ++ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> ++ ATMWCR_WIN_ATTR_OFFS; ++ targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> ++ ATMWCR_WIN_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinTargetGet - Get Window number associated with target ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ if (INTER_REGS == target) ++ { ++ return MV_AHB_TO_MBUS_INTREG_WIN; ++ } ++ ++ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) ++ { ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ continue; ++ ++ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); ++ return 0xffffffff; ++ ++ } ++ ++ if (decWin.enable == MV_TRUE) ++ { ++ if (decWin.target == target) ++ { ++ return winNum; ++ } ++ ++ } ++ ++ } ++ ++ return 0xFFFFFFFF; ++ ++ ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinAvailGet - Get First Available window number. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) ++ { ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ continue; ++ ++ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); ++ return 0xffffffff; ++ ++ } ++ ++ if (decWin.enable == MV_FALSE) ++ { ++ return winNum; ++ } ++ ++ } ++ ++ return 0xFFFFFFFF; ++} ++ ++ ++/******************************************************************************* ++* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window ++* ++* DESCRIPTION: ++* This function enable/disable a CPU address decode window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling CPU accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - Peripheral winNum enumerator. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if protection window number was wrong, or the window ++* overlapps other winNum window. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) ++{ ++ ++ /* Parameter checking */ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ /* Internal registers bar can't be disable or enabled */ ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ return (enable ? MV_OK : MV_ERROR); ++ } ++ ++ if (enable == MV_TRUE) ++ { ++ /* enable the window */ ++ MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); ++ } ++ else ++ { /* Disable address decode winNum window */ ++ MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvAhbToMbusWinRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* After a CPU address hits one of PCI address decode windows there is an ++* option to remap the address to a different one. For example, CPU ++* executes a read from PCI winNum window address 0x1200.0000. This ++* can be modified so the address on the PCI bus would be 0x1400.0000 ++* Using the PCI address remap mechanism. ++* ++* INPUT: ++* winNum - Peripheral winNum enumerator. Must be a PCI winNum. ++* pAddrDecWin - CPU winNum window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 baseAddr; ++ AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; ++ ++ MV_U32 effectiveBaseAddress=0, ++ baseAddrValue=0,windowSizeValue=0; ++ ++ ++ /* Get registers offsets of given winNum */ ++ if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) ++ { ++ return 0xffffffff; ++ } ++ ++ /* 1) Set address remap low */ ++ baseAddr = pAddrWin->baseLow; ++ ++ /* Check base address aligment */ ++ /* ++ if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) ++ { ++ mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", ++ baseAddr); ++ return MV_ERROR; ++ } ++ */ ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; ++ ++ MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); ++ ++ MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); ++ ++ ++ baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); ++ windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); ++ ++ baseAddrValue &= ATMWBR_BASE_MASK; ++ windowSizeValue &=ATMWCR_WIN_SIZE_MASK; ++ ++ /* Start calculating the effective Base Address */ ++ effectiveBaseAddress = baseAddrValue ; ++ ++ /* The effective base address will be combined from the chopped (if any) ++ remap value (according to the size value and remap mechanism) and the ++ window's base address */ ++ effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); ++ /* If the effectiveBaseAddress exceed the window boundaries return an ++ invalid value. */ ++ ++ if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) ++ { ++ mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); ++ return 0xffffffff; ++ } ++ ++ return effectiveBaseAddress; ++ ++ ++} ++/******************************************************************************* ++* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets ++* ++* DESCRIPTION: ++* ++* INPUT: ++* target1 - CPU Interface target 1 ++* target2 - CPU Interface target 2 ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if targets are illigal, or if one of the targets is not ++* associated to a valid window . ++* MV_OK otherwise. ++* ++*******************************************************************************/ ++ ++ ++MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2) ++{ ++ MV_U32 winNum1,winNum2; ++ MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; ++ AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; ++ MV_U32 remapBaseLow1=0,remapBaseLow2=0; ++ MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; ++ ++ ++ /* Check parameters */ ++ if (target1 >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); ++ return MV_ERROR; ++ } ++ ++ if (target2 >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); ++ return MV_ERROR; ++ } ++ ++ ++ /* get window associated with this target */ ++ winNum1 = mvAhbToMbusWinTargetGet(target1); ++ ++ if (winNum1 == 0xffffffff) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", ++ target1,winNum1); ++ return MV_ERROR; ++ ++ } ++ ++ /* get window associated with this target */ ++ winNum2 = mvAhbToMbusWinTargetGet(target2); ++ ++ if (winNum2 == 0xffffffff) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", ++ target2,winNum2); ++ return MV_ERROR; ++ ++ } ++ ++ /* now Get original values of both Windows */ ++ if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", ++ winNum1); ++ return MV_ERROR; ++ ++ } ++ if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", ++ winNum2); ++ return MV_ERROR; ++ ++ } ++ ++ ++ /* disable both windows */ ++ if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", ++ winNum1); ++ return MV_ERROR; ++ ++ } ++ if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", ++ winNum2); ++ return MV_ERROR; ++ ++ } ++ ++ ++ /* now swap targets */ ++ ++ /* first save winDec2 values */ ++ winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; ++ winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; ++ winDecTemp.addrWin.size = winDec2.addrWin.size; ++ winDecTemp.enable = winDec2.enable; ++ winDecTemp.target = winDec2.target; ++ ++ /* winDec2 = winDec1 */ ++ winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; ++ winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; ++ winDec2.addrWin.size = winDec1.addrWin.size; ++ winDec2.enable = winDec1.enable; ++ winDec2.target = winDec1.target; ++ ++ ++ /* winDec1 = winDecTemp */ ++ winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; ++ winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; ++ winDec1.addrWin.size = winDecTemp.addrWin.size; ++ winDec1.enable = winDecTemp.enable; ++ winDec1.target = winDecTemp.target; ++ ++ ++ /* now set the new values */ ++ ++ ++ mvAhbToMbusWinSet(winNum1,&winDec1); ++ mvAhbToMbusWinSet(winNum2,&winDec2); ++ ++ ++ ++ ++ ++ /* now we will treat the remap windows if exist */ ++ ++ ++ /* now check if one or both windows has a remap window ++ as well after the swap ! */ ++ ++ /* if a window had a remap value differnt than the base value ++ before the swap , then after the swap the remap value will be ++ equal to the base value unless both windows has a remap windows*/ ++ ++ /* first get old values */ ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) ++ { ++ remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); ++ remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); ++ ++ } ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) ++ { ++ remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); ++ remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); ++ ++ ++ } ++ ++ /* now do the swap */ ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) ++ { ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) ++ { ++ /* Two windows has a remap !!! so swap */ ++ ++ MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); ++ MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); ++ ++ MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); ++ MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); ++ ++ ++ ++ } ++ else ++ { ++ /* remap == base */ ++ MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); ++ MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); ++ ++ } ++ ++ } ++ else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) ++ { ++ /* remap == base */ ++ MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); ++ MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); ++ ++ } ++ ++ ++ ++ return MV_OK; ++ ++ ++} ++ ++ ++ ++#if defined(MV_88F1181) ++ ++/******************************************************************************* ++* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration. ++* ++* DESCRIPTION: ++* This function sets CPU Mbus Arbiter ++* ++* INPUT: ++* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At ++* each clock cycle, the crossbar arbiter samples all ++* requests and gives the bus to the next agent according ++* to the "pizza". ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if paramers to function invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray) ++{ ++ MV_U32 sliceNum; ++ MV_U32 xbarCtrl = 0; ++ MV_MBUS_ARB_TARGET xbarTarget; ++ ++ /* 1) Set crossbar control low register */ ++ for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++) ++ { ++ xbarTarget = pPizzaArbArray[sliceNum]; ++ ++ /* sliceNum parameter check */ ++ if (xbarTarget > MAX_MBUS_ARB_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", ++ xbarTarget); ++ return MV_ERROR; ++ } ++ xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum)); ++ } ++ /* Write to crossbar control low register */ ++ MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl); ++ ++ xbarCtrl = 0; ++ ++ /* 2) Set crossbar control high register */ ++ for (sliceNum = MRLR_SLICE_NUM; ++ sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM; ++ sliceNum++) ++ { ++ ++ xbarTarget = pPizzaArbArray[sliceNum]; ++ ++ /* sliceNum parameter check */ ++ if (xbarTarget > MAX_MBUS_ARB_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", ++ xbarTarget); ++ return MV_ERROR; ++ } ++ xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum)); ++ } ++ /* Write to crossbar control high register */ ++ MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvMbusArbCtrlSet - Set MBus Arbiter control register ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ctrl - pointer to MV_MBUS_ARB_CTRL register ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if paramers to function invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl) ++{ ++ ++ if (ctrl->highPrio == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); ++ } ++ else ++ { ++ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); ++ } ++ ++ if (ctrl->fixedRoundRobin == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); ++ } ++ else ++ { ++ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); ++ } ++ ++ if (ctrl->starvEn == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); ++ } ++ else ++ { ++ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvMbusArbCtrlGet - Get MBus Arbiter control register ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ctrl - pointer to MV_MBUS_ARB_CTRL register ++* ++* OUTPUT: ++* ctrl - pointer to MV_MBUS_ARB_CTRL register ++* ++* RETURN: ++* MV_ERROR if paramers to function invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl) ++{ ++ ++ MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG); ++ ++ if (ctrlReg & MACR_ARB_ARM_TOP) ++ { ++ ctrl->highPrio = MV_TRUE; ++ } ++ else ++ { ++ ctrl->highPrio = MV_FALSE; ++ } ++ ++ if (ctrlReg & MACR_ARB_TARGET_FIXED) ++ { ++ ctrl->fixedRoundRobin = MV_TRUE; ++ } ++ else ++ { ++ ctrl->fixedRoundRobin = MV_FALSE; ++ } ++ ++ if (ctrlReg & MACR_ARB_REQ_CTRL_EN) ++ { ++ ctrl->starvEn = MV_TRUE; ++ } ++ else ++ { ++ ctrl->starvEn = MV_FALSE; ++ } ++ ++ ++ return MV_OK; ++} ++ ++#endif /* #if defined(MV_88F1181) */ ++ ++ ++ ++/******************************************************************************* ++* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets ++* ++* DESCRIPTION: ++* CPU to PCI address remap registers offsets are inconsecutive. ++* This function returns PCI address remap registers offsets. ++* ++* INPUT: ++* winNum - Address decode window number. See MV_U32 enumerator. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if winNum is not a PCI one. ++* ++*******************************************************************************/ ++static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, ++ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) ++{ ++ switch (winNum) ++ { ++ case 0: ++ case 1: ++ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); ++ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); ++ break; ++ case 2: ++ case 3: ++ if((mvCtrlModelGet() == MV_5281_DEV_ID) || ++ (mvCtrlModelGet() == MV_1281_DEV_ID) || ++ (mvCtrlModelGet() == MV_6183_DEV_ID) || ++ (mvCtrlModelGet() == MV_6183L_DEV_ID)) ++ { ++ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); ++ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); ++ break; ++ } ++ else ++ { ++ pRemapRegs->lowRegOffs = 0; ++ pRemapRegs->highRegOffs = 0; ++ ++ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", ++ winNum)); ++ return MV_NO_SUCH; ++ } ++ default: ++ { ++ pRemapRegs->lowRegOffs = 0; ++ pRemapRegs->highRegOffs = 0; ++ ++ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", ++ winNum)); ++ return MV_NO_SUCH; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. ++* ++* DESCRIPTION: ++* This function print the CPU address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvAhbToMbusAddDecShow(MV_VOID) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN win; ++ MV_U32 winNum; ++ mvOsOutput( "\n" ); ++ mvOsOutput( "AHB To MBUS Bridge:\n" ); ++ mvOsOutput( "-------------------\n" ); ++ ++ for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) ++ { ++ memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", winNum ); ++ ++ if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,130 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvAhbToMbush ++#define __INCmvAhbToMbush ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvAhbToMbusRegs.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++/* defines */ ++ ++#if defined(MV_88F1181) ++/* This enumerator defines the Marvell controller possible MBUS arbiter */ ++/* target ports. It is used to define crossbar priority scheame (pizza) */ ++typedef enum _mvMBusArbTargetId ++{ ++ DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */ ++ TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */ ++ ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */ ++ PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */ ++ PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */ ++ MAX_MBUS_ARB_TARGETS ++}MV_MBUS_ARB_TARGET; ++ ++typedef struct _mvMBusArbCtrl ++{ ++ MV_BOOL starvEn; ++ MV_BOOL highPrio; ++ MV_BOOL fixedRoundRobin; ++ ++}MV_MBUS_ARB_CTRL; ++ ++#endif /* #if defined(MV_88F1181) */ ++ ++typedef struct _mvAhbtoMbusDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_AHB_TO_MBUS_DEC_WIN; ++ ++/* mvAhbToMbus.h API list */ ++ ++MV_STATUS mvAhbToMbusInit(MV_VOID); ++MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); ++MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); ++MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable); ++MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); ++MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); ++MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); ++MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2); ++ ++#if defined(MV_88F1181) ++ ++MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray); ++MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl); ++MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl); ++ ++#endif /* #if defined(MV_88F1181) */ ++ ++ ++MV_VOID mvAhbToMbusAddDecShow(MV_VOID); ++ ++ ++#endif /* __INCmvAhbToMbush */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,143 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvAhbToMbusRegsh ++#define __INCmvAhbToMbusRegsh ++ ++/******************************/ ++/* ARM Address Map Registers */ ++/******************************/ ++ ++#define MAX_AHB_TO_MBUS_WINS 9 ++#define MV_AHB_TO_MBUS_INTREG_WIN 8 ++ ++ ++#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080 ++ ++/* Window Control Register */ ++/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ ++#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ ++ ++#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated ++ with this window*/ ++#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) ++ ++#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes ++ Associated with this window */ ++#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) ++ ++ ++/* ++Used with the Base register to set the address window size and location ++Must be programed from LSB to MSB as sequence of 1’s followed ++by sequence of 0’s. The number of 1’s specifies the size of the window ++in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). ++ ++NOTE: A value of 0x0 specifies 64KB size. ++*/ ++#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ ++#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) ++#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 ++ ++/* Window Base Register */ ++/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ ++ ++/* ++Used with the size field to set the address window size and location. ++Corresponds to transaction address[31:16] ++*/ ++#define ATMWBR_BASE_OFFS 16 /* Base Address */ ++#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) ++#define ATMWBR_BASE_ALIGNMENT 0x10000 ++ ++/* Window Remap Low Register */ ++/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ ++ ++/* ++Used with the size field to specifies address bits[31:0] to be driven to ++the target interface.: ++target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) ++*/ ++#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ ++#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) ++#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 ++ ++/* Window Remap High Register */ ++/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ ++ ++/* ++Specifies address bits[63:32] to be driven to the target interface. ++target_addr[63:32] = (RemapHigh[31:0] ++*/ ++#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ ++#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) ++ ++ ++#endif /* __INCmvAhbToMbusRegsh */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,1036 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/sys/mvAhbToMbusRegs.h" ++#include "cpu/mvCpu.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "mvSysHwConfig.h" ++#include "mvSysDram.h" ++ ++/*#define MV_DEBUG*/ ++/* defines */ ++ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* locals */ ++/* static functions */ ++static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); ++ ++MV_TARGET * sampleAtResetTargetArray; ++MV_TARGET sampleAtResetTargetArrayP[] = BOOT_TARGETS_NAME_ARRAY; ++MV_TARGET sampleAtResetTargetArray6180P[] = BOOT_TARGETS_NAME_ARRAY_6180; ++/******************************************************************************* ++* mvCpuIfInit - Initialize Controller CPU interface ++* ++* DESCRIPTION: ++* This function initialize Controller CPU interface: ++* 1. Set CPU interface configuration registers. ++* 2. Set CPU master Pizza arbiter control according to static ++* configuration described in configuration file. ++* 3. Opens CPU address decode windows. DRAM windows are assumed to be ++* already set (auto detection). ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) ++{ ++ MV_U32 regVal; ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; ++ ++ if (cpuAddrWinMap == NULL) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); ++ return MV_ERROR; ++ } ++ ++ /*Initialize the boot target array according to device type*/ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ sampleAtResetTargetArray = sampleAtResetTargetArray6180P; ++ else ++ sampleAtResetTargetArray = sampleAtResetTargetArrayP; ++ ++ /* Set ARM Configuration register */ ++ regVal = MV_REG_READ(CPU_CONFIG_REG); ++ regVal &= ~CPU_CONFIG_DEFAULT_MASK; ++ regVal |= CPU_CONFIG_DEFAULT; ++ MV_REG_WRITE(CPU_CONFIG_REG,regVal); ++ ++ /* First disable all CPU target windows */ ++ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) ++ { ++ if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) ++ { ++ continue; ++ } ++ ++#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PCI(target)) ++ { ++ continue; ++ } ++#endif ++ ++#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PEX(target)) ++ { ++ continue; ++ } ++#endif ++#if defined(MV_RUN_FROM_FLASH) ++ /* Don't disable the boot device. */ ++ if (target == DEV_BOOCS) ++ { ++ continue; ++ } ++#endif /* MV_RUN_FROM_FLASH */ ++ mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE); ++ } ++ ++#if defined(MV_RUN_FROM_FLASH) ++ /* Resize the bootcs windows before other windows, because this */ ++ /* window is enabled and will cause an overlap if not resized. */ ++ target = DEV_BOOCS; ++ ++ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); ++ return MV_ERROR; ++ } ++ ++ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; ++ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; ++ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", ++ cpuAddrWinMap[target].winNum)); ++ } ++ ++#endif /* MV_RUN_FROM_FLASH */ ++ ++ /* Go through all targets in user table until table terminator */ ++ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) ++ { ++ ++#if defined(MV_RUN_FROM_FLASH) ++ if (target == DEV_BOOCS) ++ { ++ continue; ++ } ++#endif /* MV_RUN_FROM_FLASH */ ++ ++ /* if DRAM auto sizing is used do not initialized DRAM target windows, */ ++ /* assuming this already has been done earlier. */ ++#ifdef MV_DRAM_AUTO_SIZE ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ continue; ++ } ++#endif ++ ++#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PCI(target)) ++ { ++ continue; ++ } ++#endif ++ ++#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PEX(target)) ++ { ++ continue; ++ } ++#endif ++ /* If the target attribute is the same as the boot device attribute */ ++ /* then it's stays disable */ ++ if (MV_TARGET_IS_AS_BOOT(target)) ++ { ++ continue; ++ } ++ ++ if((0 == cpuAddrWinMap[target].addrWin.size) || ++ (DIS == cpuAddrWinMap[target].enable)) ++ ++ { ++ if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); ++ return MV_ERROR; ++ } ++ ++ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; ++ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; ++ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", ++ cpuAddrWinMap[target].winNum)); ++ } ++ ++ ++ } ++ } ++ ++ return MV_OK; ++ ++ ++} ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window ++* ++* DESCRIPTION: ++* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) ++* address window, also known as address decode window. ++* A new address decode window is set for specified target address window. ++* If address decode window parameter structure enables the window, ++* the routine will also enable the target window, allowing CPU to access ++* the target window. ++* ++* INPUT: ++* target - Peripheral target enumerator. ++* pAddrDecWin - CPU target window data structure. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_OK if CPU target window was set correctly, MV_ERROR in case of ++* address window overlapps with other active CPU target window or ++* trying to assign 36bit base address while CPU does not support that. ++* The function returns MV_NOT_SUPPORTED, if the target is unsupported. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_U32 existingWinNum; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* 2) Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ /* copy relevant data to MV_DRAM_DEC_WIN structure */ ++ addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; ++ addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; ++ addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; ++ addrDecWin.enable = pAddrDecWin->enable; ++ ++ ++ if (mvDramIfWinSet(target,&addrDecWin) != MV_OK); ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ ++ decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; ++ decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; ++ decWin.addrWin.size = pAddrDecWin->addrWin.size; ++ decWin.enable = pAddrDecWin->enable; ++ decWin.target = target; ++ ++ existingWinNum = mvAhbToMbusWinTargetGet(target); ++ ++ /* check if there is already another Window configured ++ for this target */ ++ if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&& ++ (existingWinNum != pAddrDecWin->winNum)) ++ { ++ /* if we want to enable the new winow number ++ passed by the user , then the old one should ++ be disabled */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ /* be sure it is disabled */ ++ mvAhbToMbusWinEnable(existingWinNum , MV_FALSE); ++ } ++ } ++ ++ if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); ++ return MV_ERROR; ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window ++* ++* DESCRIPTION: ++* Get the CPU peripheral target address window. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* pAddrDecWin - CPU target window information data structure. ++* ++* RETURN: ++* MV_OK if target exist, MV_ERROR otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) ++{ ++ ++ MV_U32 winNum=0xffffffff; ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ if (mvDramIfWinGet(target,&addrDecWin) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", ++ target); ++ return MV_ERROR; ++ } ++ ++ /* copy relevant data to MV_CPU_DEC_WIN structure */ ++ pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; ++ pAddrDecWin->enable = addrDecWin.enable; ++ pAddrDecWin->winNum = 0xffffffff; ++ ++ } ++ else ++ { ++ /* get the Window number associated with this target */ ++ ++ winNum = mvAhbToMbusWinTargetGet(target); ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ return MV_NO_SUCH; ++ ++ } ++ ++ if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK) ++ { ++ mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", ++ __FUNCTION__, winNum); ++ return MV_ERROR; ++ ++ } ++ ++ /* copy relevant data to MV_CPU_DEC_WIN structure */ ++ pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; ++ pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; ++ pAddrDecWin->addrWin.size = decWin.addrWin.size; ++ pAddrDecWin->enable = decWin.enable; ++ pAddrDecWin->winNum = winNum; ++ ++ } ++ ++ ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window ++* ++* DESCRIPTION: ++* This function enable/disable a CPU address decode window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling CPU accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* target - Peripheral target enumerator. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if protection window number was wrong, or the window ++* overlapps other target window. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable) ++{ ++ MV_U32 winNum, temp; ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* get the window and check if it exist */ ++ temp = mvCpuIfTargetWinGet(target, &addrDecWin); ++ if (MV_NO_SUCH == temp) ++ { ++ return (enable? MV_ERROR: MV_OK); ++ } ++ else if( MV_OK != temp) ++ { ++ mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); ++ return MV_ERROR; ++ } ++ ++ ++ /* check overlap */ ++ ++ if (MV_TRUE == enable) ++ { ++ if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); ++ return MV_ERROR; ++ } ++ ++ } ++ ++ ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ if (mvDramIfWinEnable(target , enable) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); ++ return MV_ERROR; ++ ++ } ++ ++ } ++ else ++ { ++ /* get the Window number associated with this target */ ++ ++ winNum = mvAhbToMbusWinTargetGet(target); ++ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ return (enable? MV_ERROR: MV_OK); ++ } ++ ++ if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", ++ winNum); ++ return MV_ERROR; ++ ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetWinSizeGet - Get CPU target address window size ++* ++* DESCRIPTION: ++* Get the size of CPU-to-peripheral target window. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit size. Function also returns '0' if window is closed. ++* Function returns 0xFFFFFFFF in case of an error. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) ++{ ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); ++ return 0; ++ } ++ ++ /* Get the winNum window */ ++ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", ++ target); ++ return 0; ++ } ++ ++ /* Check if window is enabled */ ++ if (addrDecWin.enable == MV_TRUE) ++ { ++ return (addrDecWin.addrWin.size); ++ } ++ else ++ { ++ return 0; /* Window disabled. return 0 */ ++ } ++} ++ ++/******************************************************************************* ++* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low ++* ++* DESCRIPTION: ++* CPU-to-peripheral target address window base is constructed of ++* two parts: Low and high. ++* This function gets the CPU peripheral target low base address. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit low base address. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) ++{ ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ /* Get the target window */ ++ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", ++ target); ++ return 0xffffffff; ++ } ++ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ return 0xffffffff; ++ } ++ return (addrDecWin.addrWin.baseLow); ++} ++ ++/******************************************************************************* ++* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high ++* ++* DESCRIPTION: ++* CPU-to-peripheral target address window base is constructed of ++* two parts: Low and high. ++* This function gets the CPU peripheral target high base address. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit high base address. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) ++{ ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ /* Get the target window */ ++ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", ++ target); ++ return 0xffffffff; ++ } ++ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ return 0; ++ } ++ ++ return (addrDecWin.addrWin.baseHigh); ++} ++ ++#if defined(MV_INCLUDE_PEX) ++/******************************************************************************* ++* mvCpuIfPexRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* pexTarget - Peripheral target enumerator. Must be a PEX target. ++* pAddrDecWin - CPU target window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if target is not a PEX one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) ++{ ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ ++ if (mvCtrlPexMaxIfGet() > 1) ++ { ++ if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget))) ++ { ++ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); ++ return 0xffffffff; ++ } ++ ++ } ++ else ++ { ++ if (!MV_TARGET_IS_PEX0(pexTarget)) ++ { ++ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); ++ return 0xffffffff; ++ } ++ ++ } ++ ++ /* get the Window number associated with this target */ ++ winNum = mvAhbToMbusWinTargetGet(pexTarget); ++ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); ++ return 0xffffffff; ++ ++ } ++ ++ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); ++} ++ ++#endif ++ ++#if defined(MV_INCLUDE_PCI) ++/******************************************************************************* ++* mvCpuIfPciRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* pciTarget - Peripheral target enumerator. Must be a PCI target. ++* pAddrDecWin - CPU target window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if target is not a PCI one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin) ++{ ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_PCI(pciTarget)) ++ { ++ mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget); ++ return 0xffffffff; ++ } ++ ++ /* get the Window number associated with this target */ ++ winNum = mvAhbToMbusWinTargetGet(pciTarget); ++ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n"); ++ return 0xffffffff; ++ ++ } ++ ++ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); ++} ++#endif /* MV_INCLUDE_PCI */ ++ ++ ++/******************************************************************************* ++* mvCpuIfPciIfRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* pciTarget - Peripheral target enumerator. Must be a PCI target. ++* pAddrDecWin - CPU target window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if target is not a PCI one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) ++{ ++#if defined(MV_INCLUDE_PEX) ++ if (MV_TARGET_IS_PEX(pciIfTarget)) ++ { ++ return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); ++ } ++#endif ++#if defined(MV_INCLUDE_PCI) ++ ++ if (MV_TARGET_IS_PCI(pciIfTarget)) ++ { ++ return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin); ++ } ++#endif ++ return 0; ++} ++ ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address ++* ++* DESCRIPTION: ++* ++* INPUT: ++* baseAddress - base address to be checked ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the target number that baseAddress belongs to or MAX_TARGETS is not ++* found ++* ++*******************************************************************************/ ++ ++MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) ++{ ++ MV_CPU_DEC_WIN win; ++ MV_U32 target; ++ ++ for( target = 0; target < MAX_TARGETS; target++ ) ++ { ++ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ if ((baseAddress >= win.addrWin.baseLow) && ++ (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break; ++ } ++ } ++ else return MAX_TARGETS; ++ ++ } ++ ++ return target; ++} ++/******************************************************************************* ++* cpuTargetWinOverlap - Detect CPU address decode windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case CPU address decode ++* windows overlapps. ++* This function detects CPU address decode windows overlapping of a ++* specified target. The function does not check the target itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* target - Peripheral target enumerator. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlaps current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 targetNum; ++ MV_CPU_DEC_WIN addrDecWin; ++ MV_STATUS status; ++ ++ ++ for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) ++ { ++#if defined(MV_RUN_FROM_FLASH) ++ if(MV_TARGET_IS_AS_BOOT(target)) ++ { ++ if (MV_CHANGE_BOOT_CS(targetNum) == target) ++ continue; ++ } ++#endif /* MV_RUN_FROM_FLASH */ ++ ++ /* don't check our target or illegal targets */ ++ if (targetNum == target) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); ++ if(MV_NO_SUCH == status) ++ { ++ continue; ++ } ++ if(MV_OK != status) ++ { ++ DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); ++ return MV_TRUE; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ DB(mvOsPrintf( ++ "cpuTargetWinOverlap: Required target %d overlap current %d\n", ++ target, targetNum)); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++ ++} ++ ++/******************************************************************************* ++* mvCpuIfAddDecShow - Print the CPU address decode map. ++* ++* DESCRIPTION: ++* This function print the CPU address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvCpuIfAddDecShow(MV_VOID) ++{ ++ MV_CPU_DEC_WIN win; ++ MV_U32 target; ++ mvOsOutput( "\n" ); ++ mvOsOutput( "CPU Interface\n" ); ++ mvOsOutput( "-------------\n" ); ++ ++ for( target = 0; target < MAX_TARGETS; target++ ) ++ { ++ ++ memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); ++ ++ mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); ++ mvOsOutput( "...." ); ++ ++ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "base %08x, ", win.addrWin.baseLow ); ++ mvSizePrint( win.addrWin.size ); ++ mvOsOutput( "\n" ); ++ ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH ) ++ { ++ mvOsOutput( "no such\n" ); ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvCpuIfEnablePex - Enable PCI Express. ++* ++* DESCRIPTION: ++* This function Enable PCI Express. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* pexType - MV_PEX_ROOT_COMPLEX - root complex device ++* MV_PEX_END_POINT - end point device ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++#if defined(MV_INCLUDE_PEX) ++MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType) ++{ ++ /* Set pex mode incase S@R not exist */ ++ if( pexType == MV_PEX_END_POINT) ++ { ++ MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); ++ /* Change pex mode in capability reg */ ++ MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22); ++ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20); ++ ++ } ++ else ++ { ++ MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); ++ } ++ ++ /* CPU config register Pex enable */ ++ MV_REG_BIT_SET(CPU_CTRL_STAT_REG,CCSR_PCI_ACCESS_MASK); ++} ++#endif ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,120 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCpuIfh ++#define __INCmvCpuIfh ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++#include "ctrlEnv/sys/mvAhbToMbus.h" ++#include "ddr2/mvDramIf.h" ++#include "ctrlEnv/sys/mvSysDram.h" ++#if defined(MV_INCLUDE_PEX) ++#include "pex/mvPex.h" ++#endif ++ ++/* defines */ ++ ++/* typedefs */ ++/* This structure describes CPU interface address decode window */ ++typedef struct _mvCpuIfDecWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_CPU_DEC_WIN; ++ ++ ++ ++/* mvCpuIfLib.h API list */ ++ ++/* mvCpuIfLib.h API list */ ++ ++MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); ++MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); ++MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); ++MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); ++MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); ++MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); ++MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); ++MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); ++#if defined(MV_INCLUDE_PEX) ++MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); ++MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType); ++#endif ++#if defined(MV_INCLUDE_PCI) ++MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); ++#endif ++MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); ++ ++MV_VOID mvCpuIfAddDecShow(MV_VOID); ++ ++#if defined(MV88F6281) ++MV_STATUS mvCpuIfBridgeReorderWAInit(void); ++#endif ++ ++#endif /* __INCmvCpuIfh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,304 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCpuIfRegsh ++#define __INCmvCpuIfRegsh ++ ++/****************************************/ ++/* ARM Control and Status Registers Map */ ++/****************************************/ ++ ++#define CPU_CONFIG_REG 0x20100 ++#define CPU_CTRL_STAT_REG 0x20104 ++#define CPU_RSTOUTN_MASK_REG 0x20108 ++#define CPU_SYS_SOFT_RST_REG 0x2010C ++#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110 ++#define CPU_AHB_MBUS_MASK_INT_REG 0x20114 ++#define CPU_FTDLL_CONFIG_REG 0x20120 ++#define CPU_L2_CONFIG_REG 0x20128 ++ ++ ++ ++/* ARM Configuration register */ ++/* CPU_CONFIG_REG (CCR) */ ++ ++ ++/* Reset vector location */ ++#define CCR_VEC_INIT_LOC_OFFS 1 ++#define CCR_VEC_INIT_LOC_MASK BIT1 ++/* reset at 0x00000000 */ ++#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) ++/* reset at 0xFFFF0000 */ ++#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) ++ ++ ++#define CCR_AHB_ERROR_PROP_OFFS 2 ++#define CCR_AHB_ERROR_PROP_MASK BIT2 ++/* Erros are not propogated to AHB */ ++#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) ++/* Erros are propogated to AHB */ ++#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) ++ ++ ++#define CCR_ENDIAN_INIT_OFFS 3 ++#define CCR_ENDIAN_INIT_MASK BIT3 ++#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) ++#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) ++ ++ ++#define CCR_INCR_EN_OFFS 4 ++#define CCR_INCR_EN_MASK BIT4 ++#define CCR_INCR_EN BIT4 ++ ++ ++#define CCR_NCB_BLOCKING_OFFS 5 ++#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS) ++#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS) ++#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS) ++ ++#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8 ++#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) ++#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12 ++#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS) ++#define CCR_ICACH_PREF_BUF_ENABLE BIT16 ++#define CCR_DCACH_PREF_BUF_ENABLE BIT17 ++ ++/* Ratio options for CPU to DDR for 6281/6192/6190 */ ++#define CPU_2_DDR_CLK_1x3 4 ++#define CPU_2_DDR_CLK_1x4 6 ++ ++/* Ratio options for CPU to DDR for 6281 only */ ++#define CPU_2_DDR_CLK_2x9 7 ++#define CPU_2_DDR_CLK_1x5 8 ++#define CPU_2_DDR_CLK_1x6 9 ++ ++/* Ratio options for CPU to DDR for 6180 only */ ++#define CPU_2_DDR_CLK_1x3_1 0x5 ++#define CPU_2_DDR_CLK_1x4_1 0x6 ++ ++/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ ++/* CPU to Mbus-L Tick Sample fields in CPU config register */ ++ ++#define TICK_DRV_1x1 0 ++#define TICK_DRV_1x2 0 ++#define TICK_DRV_1x3 1 ++#define TICK_DRV_1x4 2 ++#define TICK_SMPL_1x1 0 ++#define TICK_SMPL_1x2 1 ++#define TICK_SMPL_1x3 0 ++#define TICK_SMPL_1x4 0 ++ ++#define CPU_2_MBUSL_DDR_CLK_1x2 \ ++ ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ ++ (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) ++#define CPU_2_MBUSL_DDR_CLK_1x3 \ ++ ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ ++ (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) ++#define CPU_2_MBUSL_DDR_CLK_1x4 \ ++ ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ ++ (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) ++ ++/* ARM Control and Status register */ ++/* CPU_CTRL_STAT_REG (CCSR) */ ++ ++ ++/* ++This is used to block PCI express\PCI from access Socrates/Feroceon GP ++while ARM boot is still in progress ++*/ ++ ++#define CCSR_PCI_ACCESS_OFFS 0 ++#define CCSR_PCI_ACCESS_MASK BIT0 ++#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS) ++#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS) ++ ++#define CCSR_ARM_RESET BIT1 ++#define CCSR_SELF_INT BIT2 ++#define CCSR_BIG_ENDIAN BIT15 ++ ++ ++/* RSTOUTn Mask Register */ ++/* CPU_RSTOUTN_MASK_REG (CRMR) */ ++ ++#define CRMR_PEX_RST_OUT_OFFS 0 ++#define CRMR_PEX_RST_OUT_MASK BIT0 ++#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS) ++#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS) ++ ++#define CRMR_WD_RST_OUT_OFFS 1 ++#define CRMR_WD_RST_OUT_MASK BIT1 ++#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS) ++#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS) ++ ++#define CRMR_SOFT_RST_OUT_OFFS 2 ++#define CRMR_SOFT_RST_OUT_MASK BIT2 ++#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) ++#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS) ++ ++/* System Software Reset Register */ ++/* CPU_SYS_SOFT_RST_REG (CSSRR) */ ++ ++#define CSSRR_SYSTEM_SOFT_RST BIT0 ++ ++/* AHB to Mbus Bridge Interrupt Cause Register*/ ++/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ ++ ++#define CAMCIR_ARM_SELF_INT BIT0 ++#define CAMCIR_ARM_TIMER0_INT_REQ BIT1 ++#define CAMCIR_ARM_TIMER1_INT_REQ BIT2 ++#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3 ++ ++ ++/* AHB to Mbus Bridge Interrupt Mask Register*/ ++/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ ++ ++#define CAMCIR_ARM_SELF_INT_OFFS 0 ++#define CAMCIR_ARM_SELF_INT_MASK BIT0 ++#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS) ++#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS) ++ ++ ++#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1 ++#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 ++#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) ++#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) ++ ++#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2 ++#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 ++#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) ++#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) ++ ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) ++ ++/* CPU FTDLL Config register (CFCR) fields */ ++#define CFCR_FTDLL_ICACHE_TAG_OFFS 0 ++#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS) ++#define CFCR_FTDLL_DCACHE_TAG_OFFS 8 ++#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS) ++#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15) ++/* For Orion 2 D2 only */ ++#define CFCR_MRVL_CPU_ID_OFFS 16 ++#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS) ++#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS) ++#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS) ++#define CFCR_VFP_SUB_ARC_NUM_OFFS 7 ++#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) ++#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS) ++#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) ++ ++/* CPU_L2_CONFIG_REG fields */ ++#ifdef MV_CPU_LE ++#define CL2CR_L2_ECC_EN_OFFS 2 ++#define CL2CR_L2_WT_MODE_OFFS 4 ++#else ++#define CL2CR_L2_ECC_EN_OFFS 26 ++#define CL2CR_L2_WT_MODE_OFFS 28 ++#endif ++ ++#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS) ++#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS) ++ ++/*******************************************/ ++/* Main Interrupt Controller Registers Map */ ++/*******************************************/ ++ ++#define CPU_MAIN_INT_CAUSE_REG 0x20200 ++#define CPU_MAIN_IRQ_MASK_REG 0x20204 ++#define CPU_MAIN_FIQ_MASK_REG 0x20208 ++#define CPU_ENPOINT_MASK_REG 0x2020C ++#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210 ++#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214 ++#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218 ++#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C ++ ++ ++/*******************************************/ ++/* ARM Doorbell Registers Map */ ++/*******************************************/ ++ ++#define CPU_HOST_TO_ARM_DRBL_REG 0x20400 ++#define CPU_HOST_TO_ARM_MASK_REG 0x20404 ++#define CPU_ARM_TO_HOST_DRBL_REG 0x20408 ++#define CPU_ARM_TO_HOST_MASK_REG 0x2040C ++ ++ ++ ++/* CPU control register map */ ++/* Set bits means value is about to change according to new value */ ++#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK) ++ ++#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) ++ ++/* CPU Control and status defaults */ ++#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) ++ ++ ++#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) ++ ++#endif /* __INCmvCpuIfRegsh */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,324 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "mvSysAudio.h" ++ ++/******************************************************************************* ++* mvAudioWinSet - Set AUDIO target address window ++* ++* DESCRIPTION: ++* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0) ++* address window, also known as address decode window. ++* After setting this target window, the AUDIO will be able to access the ++* target within the address window. ++* ++* INPUT: ++* winNum - AUDIO target address decode window number. ++* pAddrDecWin - AUDIO target window data structure. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if address window overlapps with other address decode windows. ++* MV_BAD_PARAM if base address is invalid parameter or target is ++* unknown. ++* ++*******************************************************************************/ ++MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttribs; ++ MV_DEC_REGS decRegs; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = 0; ++ decRegs.sizeReg = 0; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK; ++ decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET); ++ ++ /* set target ID */ ++ decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK; ++ decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET); ++ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg); ++ MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAudioWinGet - Get AUDIO peripheral target address window. ++* ++* DESCRIPTION: ++* Get AUDIO peripheral target address window. ++* ++* INPUT: ++* winNum - AUDIO target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - AUDIO target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s : ERR. Invalid winNum %d\n", ++ __FUNCTION__, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) ); ++ decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) ); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) ++ { ++ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >> ++ MV_AUDIO_WIN_ATTR_OFFSET; ++ targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >> ++ MV_AUDIO_WIN_TARGET_OFFSET; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++/******************************************************************************* ++* mvAudioAddrDecShow - Print the AUDIO address decode map. ++* ++* DESCRIPTION: ++* This function print the AUDIO address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvAudioAddrDecShow(MV_VOID) ++{ ++ ++ MV_AUDIO_DEC_WIN win; ++ int i; ++ ++ if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) ++ return; ++ ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "AUDIO:\n" ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvAudioWinGet( i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ ++ ++/******************************************************************************* ++* mvAudioWinInit - Initialize the integrated AUDIO target address window. ++* ++* DESCRIPTION: ++* Initialize the AUDIO peripheral target address window. ++* ++* INPUT: ++* ++* ++* OUTPUT: ++* ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvAudioInit(MV_VOID) ++{ ++ int winNum; ++ MV_AUDIO_DEC_WIN audioWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_U32 status; ++ ++ mvAudioHalInit(); ++ ++ /* Initiate Audio address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum)); ++ regVal &= ~MV_AUDIO_WIN_ENABLE_MASK; ++ MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal); ++ } ++ ++ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ ++ /* We will set the Window to DRAM_CS0 in default */ ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(SDRAM_CS0, ++ &cpuAddrDecWin); ++ ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ audioWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ audioWin.enable = MV_TRUE; ++ audioWin.target = SDRAM_CS0; ++ ++ if(MV_OK != mvAudioWinSet(winNum, &audioWin)) ++ { ++ return MV_ERROR; ++ } ++ } ++ } ++ ++ return MV_OK; ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,123 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCMVSysAudioH ++#define __INCMVSysAudioH ++ ++#include "mvCommon.h" ++#include "audio/mvAudio.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++/***********************************/ ++/* Audio Address Decoding registers*/ ++/***********************************/ ++ ++#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2 ++#define MV_AUDIO_RECORD_WIN_NUM 0 ++#define MV_AUDIO_PLAYBACK_WIN_NUM 1 ++ ++#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3)) ++#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3)) ++ ++#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM) ++#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM) ++#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM) ++#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM) ++ ++ ++/* BITs in Windows 0-3 Control and Base Registers */ ++#define MV_AUDIO_WIN_ENABLE_BIT 0 ++#define MV_AUDIO_WIN_ENABLE_MASK (1<= 2) ++MV_TARGET tdmaAddrDecPrioTable[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_MEM, ++#endif ++ ++ TBL_TERM ++}; ++ ++/******************************************************************************* ++* mvCesaWinGet - Get TDMA target address window. ++* ++* DESCRIPTION: ++* Get TDMA target address window. ++* ++* INPUT: ++* winNum - TDMA target address decode window number. ++* ++* OUTPUT: ++* pDecWin - TDMA target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) ++{ ++ MV_DEC_WIN_PARAMS winParam; ++ MV_U32 sizeReg, baseReg; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) ++ { ++ mvOsPrintf("%s : ERR. Invalid winNum %d\n", ++ __FUNCTION__, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); ++ sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); ++ ++ /* Check if window is enabled */ ++ if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) ++ { ++ pDecWin->enable = MV_TRUE; ++ ++ /* Extract window parameters from registers */ ++ winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; ++ winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; ++ winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; ++ winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); ++ ++ /* Translate the decode window parameters to address decode struct */ ++ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) ++ { ++ mvOsPrintf("Failed to translate register parameters to CESA address" \ ++ " decode window structure\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ pDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case TDMA address decode ++* windows overlapps. ++* This function detects TDMA address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE - if the given address window overlap current address ++* decode map, ++* MV_FALSE - otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_DEC_WIN addrDecWin; ++ ++ for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) ++ { ++ mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pDecWin->target), ++ pDecWin->addrWin.baseLow, ++ pDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* set Size, Attributes and TargetID */ ++ sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | ++ ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | ++ ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); ++ ++ if (pDecWin->enable == MV_TRUE) ++ { ++ sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; ++ } ++ ++ /* Update Base value */ ++ baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); ++ ++ MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); ++ MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); ++ ++ return MV_OK; ++} ++ ++ ++static MV_STATUS mvCesaTdmaAddrDecInit (void) ++{ ++ MV_U32 winNum; ++ MV_STATUS status; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_DEC_WIN cesaWin; ++ MV_U32 winPrioIndex = 0; ++ ++ /* First disable all address decode windows */ ++ for(winNum=0; winNum= 2 */ ++ ++ ++ ++ ++MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) ++{ ++ MV_U32 cesaCryptEngBase; ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) ++ { ++ mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n", ++ sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); ++ return MV_FAIL; ++ } ++#if 0 ++ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) ++ cesaCryptEngBase = addrDecWin.addrWin.baseLow; ++ else ++ { ++ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++#else ++ cesaCryptEngBase = (MV_U32)pSramBase; ++#endif ++ ++#if 0 /* Already done in the platform init */ ++#if (MV_CESA_VERSION >= 2) ++ mvCesaTdmaAddrDecInit(); ++#endif /* MV_CESA_VERSION >= 2 */ ++#endif ++ return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, ++ osHandle); ++ ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,100 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvSysCesa_h__ ++#define __mvSysCesa_h__ ++ ++ ++#include "mvCommon.h" ++#include "cesa/mvCesa.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++/***************************** TDMA Registers *************************************/ ++ ++#define MV_CESA_TDMA_ADDR_DEC_WIN 4 ++ ++#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) ++ ++#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) ++ ++#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 ++#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) ++ ++#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 ++#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) ++ ++#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 ++#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) ++ ++#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 ++#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) ++ ++#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 ++#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) ++ ++ ++MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); ++ ++#endif +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,348 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++ ++#include "ddr2/mvDramIf.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/sys/mvSysDram.h" ++ ++/* #define MV_DEBUG */ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); ++ ++/******************************************************************************* ++* mvDramIfWinSet - Set DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function sets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* pAddrDecWin - SDRAM address window structure. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg=0,sizeReg=0; ++ MV_U32 baseToReg=0 , sizeToReg=0; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlaps with current enabled windows */ ++ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ ++ "\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ target, ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ /* read base register*/ ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); ++ ++ /* read size register */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ baseReg &= ~SCBAR_BASE_MASK; ++ baseReg |= baseToReg; ++ ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* set size */ ++ sizeReg &= ~SCSR_SIZE_MASK; ++ /* Size is located at upper 16 bits */ ++ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); ++ ++ /* enable/Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ sizeReg |= SCSR_WIN_EN; ++ } ++ else ++ { ++ sizeReg &= ~SCSR_WIN_EN; ++ } ++ ++ /* 3) Write to address decode Base Address Register */ ++ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinGet - Get DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function gets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* pAddrDecWin - SDRAM address window structure. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg,sizeReg; ++ MV_U32 sizeRegVal; ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Read base and size registers */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); ++ ++ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; ++ ++ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, ++ SCSR_SIZE_ALIGNMENT); ++ ++ /* Check if ctrlRegToSize returned OK */ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Extract base address */ ++ /* Base register [31:16] ==> baseLow[31:16] */ ++ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; ++ ++ pAddrDecWin->addrWin.baseHigh = 0; ++ ++ ++ if (sizeReg & SCSR_WIN_EN) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinEnable - Enable/Disable SDRAM address decode window ++* ++* DESCRIPTION: ++* This function enable/Disable SDRAM address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR in case function parameter are invalid, MV_OK otherewise. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { /* First check for overlap with other enabled windows */ ++ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", ++ target); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode winNum window */ ++ MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", ++ target); ++ return MV_ERROR; ++ } ++ } ++ else ++ { /* Disable address decode winNum window */ ++ MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window ++* ++* DESCRIPTION: ++* This function scan each SDRAM address decode window to test if it ++* overlapps the given address windoow ++* ++* INPUT: ++* target - SDRAM target where the function skips checking. ++* pAddrDecWin - The tested address window for overlapping with ++* SDRAM windows. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlaps any enabled address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_TARGET targetNum; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) ++ { ++ /* don't check our winNum or illegal targets */ ++ if (targetNum == target) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf( ++ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", ++ target, targetNum); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,80 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __sysDram ++#define __sysDram ++ ++/* This structure describes CPU interface address decode window */ ++typedef struct _mvDramIfDecWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++}MV_DRAM_DEC_WIN; ++ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); ++ ++#endif +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,658 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "ctrlEnv/sys/mvSysGbe.h" ++ ++ ++ ++typedef struct _mvEthDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_ETH_DEC_WIN; ++ ++MV_TARGET ethAddrDecPrioTap[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS0) ++ DEVICE_CS0, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS1) ++ DEVICE_CS1, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS2) ++ DEVICE_CS2, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS3) ++ DEVICE_CS3, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_IO, ++#endif ++ TBL_TERM ++}; ++ ++static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); ++static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); ++static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); ++ ++ ++/******************************************************************************* ++* mvEthWinInit - Initialize ETH address decode windows ++* ++* DESCRIPTION: ++* This function initialize ETH window decode unit. It set the ++* default address decode windows of the unit. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if setting fail. ++*******************************************************************************/ ++/* Configure EthDrv memory map registes. */ ++MV_STATUS mvEthWinInit (int port) ++{ ++ MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; ++ MV_ETH_DEC_WIN ethWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ static MV_U32 accessProtReg = 0; ++ ++#if (MV_ETH_VERSION <= 1) ++ static MV_BOOL isFirst = MV_TRUE; ++ ++ if(isFirst == MV_FALSE) ++ { ++ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); ++ return MV_OK; ++ } ++ isFirst = MV_FALSE; ++#endif /* MV_GIGA_ETH_VERSION */ ++ ++ /* Initiate Ethernet address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum=0; winNum= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ ++ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); ++ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; ++ decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; ++ /* set target ID */ ++ decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; ++ decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; ++ ++ /* for the safe side we disable the window before writing the new ++ values */ ++ mvEthWinEnable(port, winNum, MV_FALSE); ++ MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); ++ ++ /* Enable address decode target window */ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ mvEthWinEnable(port, winNum, MV_TRUE); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvETHWinGet - Get dma peripheral target address window. ++* ++* DESCRIPTION: ++* Get ETH peripheral target address window. ++* ++* INPUT: ++* winNum - ETH to target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - ETH target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); ++ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; ++ targetAttrib.targetId = ++ (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthWinEnable - Enable/disable a ETH to target address window ++* ++* DESCRIPTION: ++* This function enable/disable a ETH to target address window. ++* According to parameter 'enable' the routine will enable the ++* window, thus enabling ETH accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - ETH to target address decode window number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if decode window number was wrong or enabled window overlapps. ++* ++*******************************************************************************/ ++MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) ++{ ++ MV_ETH_DEC_WIN addrDecWin; ++ ++ /* Parameter checking */ ++ if (winNum >= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { /* First check for overlap with other enabled windows */ ++ /* Get current window */ ++ if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) ++ { ++ mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode target window */ ++ MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { /* Disable address decode target window */ ++ MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthWinTargetGet - Get Window number associated with target ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* window number ++* ++*******************************************************************************/ ++MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) ++{ ++ MV_ETH_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ for (winNum=0; winNum= mvCtrlEthMaxPortGet()) ++ { ++ mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); ++ return MV_ERROR; ++ } ++ ++ if (winNum >= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) ++ { ++ mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); ++ return MV_ERROR; ++ } ++ /* Read current protection register */ ++ protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); ++ ++ /* Clear protection window field */ ++ protReg &= ~(ETH_PROT_WIN_MASK(winNum)); ++ ++ /* Set new protection field value */ ++ protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); ++ ++ /* Write protection register back */ ++ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* ethWinOverlapDetect - Detect ETH address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case ETH address decode ++* windows overlapps. ++* This function detects ETH address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 baseAddrEnableReg; ++ MV_U32 winNumIndex; ++ MV_ETH_DEC_WIN addrDecWin; ++ ++ /* Read base address enable register. Do not check disabled windows */ ++ baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); ++ ++ for (winNumIndex=0; winNumIndex= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Enabled CPU access to PCI-Express */ ++ mvCpuIfEnablePex(pexIf, pexType); ++ ++ /* Start with bars */ ++ /* First disable all PEX bars*/ ++ for (bar = 0; bar < PEX_MAX_BARS; bar++) ++ { ++ if (PEX_INTER_REGS_BAR != bar) ++ { ++ if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) ++ { ++ mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar); ++ return MV_ERROR; ++ } ++ ++ } ++ ++ } ++ ++ /* and disable all PEX target windows */ ++ for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) ++ { ++ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) ++ { ++ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", ++ winNum); ++ return MV_ERROR; ++ ++ } ++ } ++ ++ /* Now, go through all bars*/ ++ ++ ++ ++/******************************************************************************/ ++/* Internal registers bar */ ++/******************************************************************************/ ++ bar = PEX_INTER_REGS_BAR; ++ ++ /* we only open the bar , no need to open windows for this bar */ ++ ++ /* first get the CS attribute from the CPU Interface */ ++ if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); ++ return MV_ERROR; ++ } ++ ++ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pexBar.addrWin.size = addrDecWin.addrWin.size; ++ pexBar.enable = MV_TRUE; ++ ++ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); ++ return MV_ERROR; ++ } ++ ++/******************************************************************************/ ++/* DRAM bar */ ++/******************************************************************************/ ++ ++ bar = PEX_DRAM_BAR; ++ ++ pexBar.addrWin.size = 0; ++ ++ for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ ) ++ { ++ ++ status = mvCpuIfTargetWinGet(target,&addrDecWin); ++ ++ if((MV_NO_SUCH == status)&&(target != SDRAM_CS0)) ++ { ++ continue; ++ } ++ ++ /* first get attributes from CPU If */ ++ if (MV_OK != status) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); ++ return MV_ERROR; ++ } ++ if (addrDecWin.enable == MV_TRUE) ++ { ++ /* the base is the base of DRAM CS0 always */ ++ if (SDRAM_CS0 == target ) ++ { ++ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ ++ } ++ ++ /* increment the bar size to be the sum of the size of all ++ DRAM chips selecs */ ++ pexBar.addrWin.size += addrDecWin.addrWin.size; ++ ++ /* set a Pex window for this target ! ++ DRAM CS always will have a Pex Window , and is not a ++ part of the priority table */ ++ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pexWin.addrWin.size = addrDecWin.addrWin.size; ++ ++ /* we disable the windows at first because we are not ++ sure that it is witihin bar boundries */ ++ pexWin.enable =MV_FALSE; ++ pexWin.target = target; ++ pexWin.targetBar = bar; ++ ++ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); ++ return MV_ERROR; ++ } ++ } ++ } ++ ++ /* check if the size of the bar is illeggal */ ++ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) ++ { ++ /* try to get a good size */ ++ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, ++ PXBCR_BAR_SIZE_ALIGNMENT); ++ } ++ ++ /* check if the size and base are valid */ ++ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) ++ { ++ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); ++ mvOsPrintf("it will be disabled\n"); ++ mvOsPrintf("please check Pex and CPU windows configuration\n"); ++ } ++ else ++ { ++ pexBar.enable = MV_TRUE; ++ ++ /* configure the bar */ ++ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); ++ return MV_ERROR; ++ } ++ ++ /* after the bar was configured then we enable the Pex windows*/ ++ for (winNum = 0;winNum < pexCurrWin ;winNum++) ++ { ++ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) ++ { ++ mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ } ++ } ++ ++/******************************************************************************/ ++/* DEVICE bar */ ++/******************************************************************************/ ++ ++/* Open the Device BAR for non linux only */ ++#ifndef MV_DISABLE_PEX_DEVICE_BAR ++ ++ /* then device bar*/ ++ bar = PEX_DEVICE_BAR; ++ ++ /* save the starting window */ ++ pexStartWindow = pexCurrWin; ++ pexBar.addrWin.size = 0; ++ pexBar.addrWin.baseLow = 0xffffffff; ++ pexBar.addrWin.baseHigh = 0; ++ maxBase = 0; ++ ++ for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ ) ++ { ++ status = mvCpuIfTargetWinGet(target,&addrDecWin); ++ ++ if (MV_NO_SUCH == status) ++ { ++ continue; ++ } ++ ++ if (MV_OK != status) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); ++ return MV_ERROR; ++ } ++ ++ if (addrDecWin.enable == MV_TRUE) ++ { ++ /* get the minimum base */ ++ if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) ++ { ++ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ } ++ ++ /* get the maximum base */ ++ if (addrDecWin.addrWin.baseLow > maxBase) ++ { ++ maxBase = addrDecWin.addrWin.baseLow; ++ sizeOfMaxBase = addrDecWin.addrWin.size; ++ } ++ ++ /* search in the priority table for this target */ ++ for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; ++ winIndex++) ++ { ++ if (pexDevBarPrioTable[winIndex] != target) ++ { ++ continue; ++ } ++ else if (pexDevBarPrioTable[winIndex] == target) ++ { ++ /*found it */ ++ ++ /* if the index of this target in the prio table is valid ++ then we set the Pex window for this target, a valid index is ++ an index that is lower than the number of the windows that ++ was not configured yet */ ++ ++ /* we subtract 2 always because the default and expantion ++ rom windows are always configured */ ++ if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2) ++ { ++ /* set a Pex window for this target ! */ ++ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pexWin.addrWin.size = addrDecWin.addrWin.size; ++ ++ /* we disable the windows at first because we are not ++ sure that it is witihin bar boundries */ ++ pexWin.enable = MV_FALSE; ++ pexWin.target = target; ++ pexWin.targetBar = bar; ++ ++ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, ++ &pexWin)) ++ { ++ mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); ++ return MV_ERROR; ++ } ++ } ++ } ++ } ++ } ++ } ++ ++ pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; ++ pexBar.enable = MV_TRUE; ++ ++ /* check if the size of the bar is illegal */ ++ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) ++ { ++ /* try to get a good size */ ++ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, ++ PXBCR_BAR_SIZE_ALIGNMENT); ++ } ++ ++ /* check if the size and base are valid */ ++ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) ++ { ++ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); ++ mvOsPrintf("it will be disabled\n"); ++ mvOsPrintf("please check Pex and CPU windows configuration\n"); ++ } ++ else ++ { ++ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); ++ return MV_ERROR; ++ } ++ ++ /* now enable the windows */ ++ for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) ++ { ++ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) ++ { ++ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", ++ winNum); ++ return MV_ERROR; ++ } ++ } ++ } ++ ++#endif ++ ++ return mvPexHalInit(pexIf, pexType); ++ ++} ++ ++/******************************************************************************* ++* mvPexTargetWinSet - Set PEX to peripheral target address window BAR ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_OK if PEX BAR target window was set correctly, ++* MV_BAD_PARAM on bad params ++* MV_ERROR otherwise ++* (e.g. address window overlapps with other active PEX target window). ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin) ++{ ++ ++ MV_DEC_REGS decRegs; ++ PEX_WIN_REG_INFO winRegInfo; ++ MV_TARGET_ATTRIB targetAttribs; ++ ++ /* Parameter checking */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (winNum >= PEX_MAX_TARGET_WIN) ++ { ++ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* get the pex Window registers offsets */ ++ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); ++ ++ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ ++ /* 2) Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* 2) Check if the requested window overlaps with current windows */ ++ if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", ++ winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ } ++ ++ ++ ++ /* read base register*/ ++ ++ if (winRegInfo.baseLowRegOffs) ++ { ++ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); ++ } ++ else ++ { ++ decRegs.baseReg = 0; ++ } ++ ++ if (winRegInfo.sizeRegOffs) ++ { ++ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); ++ } ++ else ++ { ++ decRegs.sizeReg =0; ++ } ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* enable\Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ decRegs.sizeReg |= PXWCR_WIN_EN; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~PXWCR_WIN_EN; ++ } ++ ++ ++ /* clear bit location */ ++ decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; ++ ++ /* set bar Mapping */ ++ if (pAddrDecWin->targetBar == 1) ++ { ++ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; ++ } ++ else if (pAddrDecWin->targetBar == 2) ++ { ++ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK; ++ decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS; ++ /* set target ID */ ++ decRegs.sizeReg &= ~PXWCR_TARGET_MASK; ++ decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS; ++ ++ ++ /* 3) Write to address decode Base Address Register */ ++ ++ if (winRegInfo.baseLowRegOffs) ++ { ++ MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg); ++ } ++ ++ /* write size reg */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ if ((MV_PEX_WIN_DEFAULT == winNum)|| ++ (MV_PEX_WIN_EXP_ROM == winNum)) ++ { ++ /* clear size because there is no size field*/ ++ decRegs.sizeReg &= ~PXWCR_SIZE_MASK; ++ ++ /* clear enable because there is no enable field*/ ++ decRegs.sizeReg &= ~PXWCR_WIN_EN; ++ ++ } ++ ++ MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg); ++ } ++ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexTargetWinGet - Get PEX to peripheral target address window ++* ++* DESCRIPTION: ++* Get the PEX to peripheral target address window BAR. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - BAR to be accessed by slave. ++* ++* OUTPUT: ++* pAddrBarWin - PEX target window information data structure. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttrib; ++ MV_DEC_REGS decRegs; ++ ++ PEX_WIN_REG_INFO winRegInfo; ++ ++ /* Parameter checking */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (winNum >= PEX_MAX_TARGET_WIN) ++ { ++ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* get the pex Window registers offsets */ ++ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); ++ ++ /* read base register*/ ++ if (winRegInfo.baseLowRegOffs) ++ { ++ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); ++ } ++ else ++ { ++ decRegs.baseReg = 0; ++ } ++ ++ /* read size reg */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); ++ } ++ else ++ { ++ decRegs.sizeReg =0; ++ } ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ ++ } ++ ++ if (decRegs.sizeReg & PXWCR_WIN_EN) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ ++ } ++ ++ ++ #if 0 ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ return MV_ERROR; ++ } ++ #endif ++ ++ ++ /* get target bar */ ++ if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 ) ++ { ++ pAddrDecWin->targetBar = 1; ++ } ++ else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == ++ PXWCR_WIN_BAR_MAP_BAR2 ) ++ { ++ pAddrDecWin->targetBar = 2; ++ } ++ ++ /* attrib and targetId */ ++ pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >> ++ PXWCR_ATTRIB_OFFS; ++ pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >> ++ PXWCR_TARGET_OFFS; ++ ++ targetAttrib.attrib = pAddrDecWin->attrib; ++ targetAttrib.targetId = pAddrDecWin->targetId; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ return MV_OK; ++ ++} ++ ++ ++/******************************************************************************* ++* mvPexTargetWinEnable - Enable/disable a PEX BAR window ++* ++* DESCRIPTION: ++* This function enable/disable a PEX BAR window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling PEX accesses for that BAR (before enabling the ++* window it is tested for overlapping). Otherwise, the window will ++* be disabled. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - BAR to be accessed by slave. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) ++{ ++ PEX_WIN_REG_INFO winRegInfo; ++ MV_PEX_DEC_WIN addrDecWin; ++ ++ /* Parameter checking */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (winNum >= PEX_MAX_TARGET_WIN) ++ { ++ mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ ++ /* get the pex Window registers offsets */ ++ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); ++ ++ ++ /* if the address windows is disabled , we only disable the appropriare ++ pex window and ignore other settings */ ++ ++ if (MV_FALSE == enable) ++ { ++ ++ /* this is not relevant to default and expantion rom ++ windows */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ if ((MV_PEX_WIN_DEFAULT != winNum)&& ++ (MV_PEX_WIN_EXP_ROM != winNum)) ++ { ++ MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); ++ } ++ } ++ ++ } ++ else ++ { ++ if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", ++ winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ /* this is not relevant to default and expantion rom ++ windows */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ if ((MV_PEX_WIN_DEFAULT != winNum)&& ++ (MV_PEX_WIN_EXP_ROM != winNum)) ++ { ++ MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); ++ } ++ } ++ ++ ++ } ++ ++ return MV_OK; ++ ++} ++ ++ ++ ++/******************************************************************************* ++* mvPexTargetWinRemap - Set PEX to target address window remap. ++* ++* DESCRIPTION: ++* The PEX interface supports remap of the BAR original address window. ++* For each BAR it is possible to define a remap address. For example ++* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified ++* according to remap register but will also be targeted to the ++* SDRAM CS[0]. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - Peripheral target enumerator accessed by slave. ++* pAddrWin - Address window to be checked. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_REMAP_WIN *pAddrWin) ++{ ++ ++ PEX_WIN_REG_INFO winRegInfo; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", ++ pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (MV_PEX_WIN_DEFAULT == winNum) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", ++ winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ ++ "\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ pexIf, ++ winNum, ++ pAddrWin->addrWin.baseLow, ++ pAddrWin->addrWin.size); ++ ++ return MV_ERROR; ++ } ++ ++ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); ++ ++ /* Set remap low register value */ ++ MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); ++ ++ /* Skip base high settings if the BAR has only base low (32-bit) */ ++ if (0 != winRegInfo.remapHighRegOffs) ++ { ++ MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); ++ } ++ ++ ++ if (pAddrWin->enable == MV_TRUE) ++ { ++ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPexTargetWinRemapEnable - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, ++ MV_BOOL enable) ++{ ++ PEX_WIN_REG_INFO winRegInfo; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", ++ pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (MV_PEX_WIN_DEFAULT == winNum) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", ++ winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ ++ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); ++ ++ if (enable == MV_TRUE) ++ { ++ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexBarSet - Set PEX bar address and size ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexBarSet(MV_U32 pexIf, ++ MV_U32 barNum, ++ MV_PEX_BAR *pAddrWin) ++{ ++ MV_U32 regBaseLow; ++ MV_U32 regSize,sizeToReg; ++ ++ ++ /* check parameters */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if(barNum >= PEX_MAX_BARS) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ if (pAddrWin->addrWin.size == 0) ++ { ++ mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" ); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ /* Check if the window complies with PEX spec */ ++ if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, ++ pAddrWin->addrWin.size)) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* 2) Check if the requested bar overlaps with current bars */ ++ if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Get size register value according to window size */ ++ sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); ++ ++ /* Read bar size */ ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ ++ { ++ regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ regSize &= ~PXBCR_BAR_SIZE_MASK; ++ regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; ++ ++ MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); ++ ++ } ++ ++ /* set size */ ++ ++ ++ ++ /* Read base address low */ ++ regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, ++ PEX_MV_BAR_BASE(barNum))); ++ ++ /* clear current base */ ++ if (PEX_INTER_REGS_BAR == barNum) ++ { ++ regBaseLow &= ~PXBIR_BASE_MASK; ++ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); ++ } ++ else ++ { ++ regBaseLow &= ~PXBR_BASE_MASK; ++ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); ++ } ++ ++ /* if we had a previous value that contain the bar type (MeM\IO), we want to ++ restore it */ ++ regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; ++ ++ ++ ++ /* write base low */ ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), ++ regBaseLow); ++ ++ if (pAddrWin->addrWin.baseHigh != 0) ++ { ++ /* Read base address high */ ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), ++ pAddrWin->addrWin.baseHigh); ++ ++ } ++ ++ /* lastly enable the Bar */ ++ if (pAddrWin->enable == MV_TRUE) ++ { ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers ++ are enabled always */ ++ { ++ MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); ++ } ++ } ++ else if (MV_FALSE == pAddrWin->enable) ++ { ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers ++ are enabled always */ ++ { ++ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); ++ } ++ ++ } ++ ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexBarGet - Get PEX bar address and size ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++MV_STATUS mvPexBarGet(MV_U32 pexIf, ++ MV_U32 barNum, ++ MV_PEX_BAR *pAddrWin) ++{ ++ /* check parameters */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if(barNum >= PEX_MAX_BARS) ++ { ++ mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* read base low */ ++ pAddrWin->addrWin.baseLow = ++ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); ++ ++ ++ if (PEX_INTER_REGS_BAR == barNum) ++ { ++ pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; ++ } ++ else ++ { ++ pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; ++ } ++ ++ ++ /* read base high */ ++ pAddrWin->addrWin.baseHigh = ++ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); ++ ++ ++ /* Read bar size */ ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ ++ { ++ pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); ++ ++ /* check if enable or not */ ++ if (pAddrWin->addrWin.size & PXBCR_BAR_EN) ++ { ++ pAddrWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrWin->enable = MV_FALSE; ++ } ++ ++ /* now get the size */ ++ pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; ++ pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; ++ ++ pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, ++ PXBCR_BAR_SIZE_ALIGNMENT); ++ ++ } ++ else /* PEX_INTER_REGS_BAR */ ++ { ++ pAddrWin->addrWin.size = INTER_REGS_SIZE; ++ pAddrWin->enable = MV_TRUE; ++ } ++ ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPexBarEnable - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++ ++MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) ++{ ++ ++ MV_PEX_BAR pexBar; ++ ++ /* check parameters */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ if(barNum >= PEX_MAX_BARS) ++ { ++ mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ if (PEX_INTER_REGS_BAR == barNum) ++ { ++ if (MV_TRUE == enable) ++ { ++ return MV_OK; ++ } ++ else ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ ++ if (MV_FALSE == enable) ++ { ++ /* disable bar and quit */ ++ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); ++ return MV_OK; ++ } ++ ++ /* else */ ++ ++ if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) ++ { ++ mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); ++ return MV_ERROR; ++ ++ } ++ ++ if (MV_TRUE == pexBar.enable) ++ { ++ /* it is already enabled !!! */ ++ return MV_OK; ++ } ++ ++ /* else enable the bar*/ ++ ++ pexBar.enable = MV_TRUE; ++ ++ if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) ++ { ++ mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* pexWinOverlapDetect - Detect address windows overlapping ++* ++* DESCRIPTION: ++* This function detects address window overlapping of a given address ++* window in PEX BARs. ++* ++* INPUT: ++* pAddrWin - Address window to be checked. ++* bar - BAR to be accessed by slave. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, ++ MV_U32 winNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 win; ++ MV_PEX_DEC_WIN addrDecWin; ++ ++ ++ for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++) ++ { ++ /* don't check our target or illegal targets */ ++ if (winNum == win) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) ++ { ++ mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", ++ win); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", ++ winNum, win); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* pexIsWinWithinBar - Detect if address is within PEX bar boundries ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 bar; ++ MV_PEX_BAR addrDecWin; ++ ++ for(bar = 0; bar < PEX_MAX_BARS; bar++) ++ { ++ ++ /* Get window parameters */ ++ if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) ++ { ++ mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled bars */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ ++ if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++ ++} ++ ++/******************************************************************************* ++* pexBarOverlapDetect - Detect address windows overlapping ++* ++* DESCRIPTION: ++* This function detects address window overlapping of a given address ++* window in PEX BARs. ++* ++* INPUT: ++* pAddrWin - Address window to be checked. ++* bar - BAR to be accessed by slave. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, ++ MV_U32 barNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 bar; ++ MV_PEX_BAR barDecWin; ++ ++ ++ for(bar = 0; bar < PEX_MAX_BARS; bar++) ++ { ++ /* don't check our target or illegal targets */ ++ if (barNum == bar) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) ++ { ++ mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* don'nt check disabled bars */ ++ if (barDecWin.enable == MV_FALSE) ++ { ++ continue; ++ } ++ ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) ++ { ++ mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", ++ barNum, bar); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* pexBarIsValid - Check if the given address window is valid ++* ++* DESCRIPTION: ++* PEX spec restrict BAR base to be aligned to BAR size. ++* This function checks if the given address window is valid. ++* ++* INPUT: ++* baseLow - 32bit low base address. ++* size - Window size. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the address window is valid, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) ++{ ++ ++ /* PCI spec restrict BAR base to be aligned to BAR size */ ++ if(MV_IS_NOT_ALIGN(baseLow, size)) ++ { ++ return MV_ERROR; ++ } ++ else ++ { ++ return MV_TRUE; ++ } ++ ++ return MV_TRUE; ++} ++ ++/******************************************************************************* ++* pexBarRegInfoGet - Get BAR register information ++* ++* DESCRIPTION: ++* PEX BARs registers offsets are inconsecutive. ++* This function gets a PEX BAR register information like register offsets ++* and function location of the BAR. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - The PEX BAR in question. ++* ++* OUTPUT: ++* pBarRegInfo - BAR register info struct. ++* ++* RETURN: ++* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK ++* ++*******************************************************************************/ ++static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, ++ MV_U32 winNum, ++ PEX_WIN_REG_INFO *pWinRegInfo) ++{ ++ ++ if ((winNum >= 0)&&(winNum <=3)) ++ { ++ pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum); ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum); ++ pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum); ++ pWinRegInfo->remapHighRegOffs = 0; ++ } ++ else if ((winNum >= 4)&&(winNum <=5)) ++ { ++ pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum); ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum); ++ pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum); ++ pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum); ++ ++ } ++ else if (MV_PEX_WIN_DEFAULT == winNum) ++ { ++ pWinRegInfo->baseLowRegOffs = 0; ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); ++ pWinRegInfo->remapLowRegOffs = 0; ++ pWinRegInfo->remapHighRegOffs = 0; ++ } ++ else if (MV_PEX_WIN_EXP_ROM == winNum) ++ { ++ pWinRegInfo->baseLowRegOffs = 0; ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); ++ pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); ++ pWinRegInfo->remapHighRegOffs = 0; ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* pexBarNameGet - Get the string name of PEX BAR. ++* ++* DESCRIPTION: ++* This function get the string name of PEX BAR. ++* ++* INPUT: ++* bar - PEX bar number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* pointer to the string name of PEX BAR. ++* ++*******************************************************************************/ ++const MV_8* pexBarNameGet( MV_U32 bar ) ++{ ++ switch( bar ) ++ { ++ case PEX_INTER_REGS_BAR: ++ return "Internal Regs Bar0...."; ++ case PEX_DRAM_BAR: ++ return "DRAM Bar1............."; ++ case PEX_DEVICE_BAR: ++ return "Devices Bar2.........."; ++ default: ++ return "Bar unknown"; ++ } ++} ++/******************************************************************************* ++* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). ++* ++* DESCRIPTION: ++* This function print the PEX address decode map (BARs and windows). ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvPexAddrDecShow(MV_VOID) ++{ ++ MV_PEX_BAR pexBar; ++ MV_PEX_DEC_WIN win; ++ MV_U32 pexIf; ++ MV_U32 bar,winNum; ++ ++ for( pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++ ) ++ { ++ if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue; ++ mvOsOutput( "\n" ); ++ mvOsOutput( "PEX%d:\n", pexIf ); ++ mvOsOutput( "-----\n" ); ++ ++ mvOsOutput( "\nPex Bars \n\n"); ++ ++ for( bar = 0; bar < PEX_MAX_BARS; bar++ ) ++ { ++ memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); ++ ++ mvOsOutput( "%s ", pexBarNameGet(bar) ); ++ ++ if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) ++ { ++ if( pexBar.enable ) ++ { ++ mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow ); ++ mvSizePrint( pexBar.addrWin.size ); ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ mvOsOutput( "\nPex Decode Windows\n\n"); ++ ++ for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) ++ { ++ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", winNum ); ++ ++ if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) ++ { ++ if (win.enable) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ ++ ++ } ++ } ++ ++ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); ++ ++ mvOsOutput( "default win - " ); ++ ++ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) ++ { ++ mvOsOutput( "%s ", ++ mvCtrlTargetNameGet(win.target) ); ++ mvOsOutput( "\n" ); ++ } ++ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); ++ ++ mvOsOutput( "Expansion ROM - " ); ++ ++ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) ++ { ++ mvOsOutput( "%s ", ++ mvCtrlTargetNameGet(win.target) ); ++ mvOsOutput( "\n" ); ++ } ++ ++ } ++} ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,348 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCSysPEXH ++#define __INCSysPEXH ++ ++#include "mvCommon.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++/* 4KB granularity */ ++#define MINIMUM_WINDOW_SIZE 0x1000 ++#define MINIMUM_BAR_SIZE 0x1000 ++#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 ++#define BAR_SIZE_OFFS 12 ++#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) ++ ++ ++ ++#define MV_PEX_WIN_DEFAULT 6 ++#define MV_PEX_WIN_EXP_ROM 7 ++#define PEX_MAX_TARGET_WIN 8 ++ ++ ++#define PEX_MAX_BARS 3 ++#define PEX_INTER_REGS_BAR 0 ++#define PEX_DRAM_BAR 1 ++#define PEX_DEVICE_BAR 2 ++ ++/*************************************/ ++/* PCI Express BAR Control Registers */ ++/*************************************/ ++#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000) ++#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000) ++ ++ ++/* PCI Express BAR Control Register */ ++/* PEX_BAR_CTRL_REG (PXBCR) */ ++ ++#define PXBCR_BAR_EN BIT0 ++#define PXBCR_BAR_SIZE_OFFS 16 ++#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) ++#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 ++ ++ ++ ++/* PCI Express Expansion ROM BAR Control Register */ ++/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ ++ ++#define PXERBCR_EXPROM_EN BIT0 ++#define PXERBCR_EXPROMSZ_OFFS 19 ++#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) ++ ++/************************************************/ ++/* PCI Express Address Window Control Registers */ ++/************************************************/ ++#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \ ++ (0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000) ++#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \ ++ (0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000) ++#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \ ++ (0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \ ++ (0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \ ++ (0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \ ++ (0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \ ++ (0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++ ++#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000) ++#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000) ++#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000) ++ ++/* PCI Express Window Control Register */ ++/* PEX_WIN_CTRL_REG (PXWCR) */ ++ ++#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ ++ ++#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ ++#define PXWCR_WIN_BAR_MAP_MASK BIT1 ++#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) ++#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) ++ ++#define PXWCR_TARGET_OFFS 4 /*Unit ID */ ++#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) ++ ++#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ ++#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) ++ ++#define PXWCR_SIZE_OFFS 16 /* size */ ++#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) ++#define PXWCR_SIZE_ALIGNMENT 0x10000 ++ ++/* PCI Express Window Base Register */ ++/* PEX_WIN_BASE_REG (PXWBR)*/ ++ ++#define PXWBR_BASE_OFFS 16 /* address[31:16] */ ++#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) ++#define PXWBR_BASE_ALIGNMENT 0x10000 ++ ++/* PCI Express Window Remap Register */ ++/* PEX_WIN_REMAP_REG (PXWRR)*/ ++ ++#define PXWRR_REMAP_EN BIT0 ++#define PXWRR_REMAP_OFFS 16 ++#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) ++#define PXWRR_REMAP_ALIGNMENT 0x10000 ++ ++/* PCI Express Window Remap (High) Register */ ++/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ ++ ++#define PXWRHR_REMAP_HIGH_OFFS 0 ++#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) ++ ++/* PCI Express Default Window Control Register */ ++/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ ++ ++#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ ++#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) ++#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ ++#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) ++ ++/* PCI Express Expansion ROM Window Control Register */ ++/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ ++ ++#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ ++#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) ++#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ ++#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) ++ ++/* PCI Express Expansion ROM Window Remap Register */ ++/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ ++ ++#define PXWERRR_REMAP_EN BIT0 ++#define PXWERRR_REMAP_OFFS 16 ++#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) ++#define PXWERRR_REMAP_ALIGNMENT 0x10000 ++ ++ ++ ++/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/ ++/* PCI Express BAR0 Internal Register*/ ++/*PEX BAR0_INTER_REG (PXBIR)*/ ++ ++#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ ++ ++#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ ++#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) ++#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) ++#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) ++ ++#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ ++ ++#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ ++#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) ++#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) ++ ++ ++/* PCI Express BAR0 Internal (High) Register*/ ++/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/ ++ ++#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ ++#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) ++ ++ ++#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ ++#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB ++#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB ++#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB ++ ++ ++/* PCI Express BAR1 Register */ ++/* PCI Express BAR2 Register*/ ++/*PEX BAR1_REG (PXBR)*/ ++/*PEX BAR2_REG (PXBR)*/ ++ ++#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ ++ ++#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ ++#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) ++#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) ++#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) ++ ++#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ ++ ++#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ ++#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) ++#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) ++ ++ ++/* PCI Express BAR1 (High) Register*/ ++/* PCI Express BAR2 (High) Register*/ ++/*PEX BAR1_REG_HIGH (PXBRH)*/ ++/*PEX BAR2_REG_HIGH (PXBRH)*/ ++ ++#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ ++#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) ++ ++/* PCI Express Expansion ROM BAR Register*/ ++/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/ ++ ++#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ ++ ++#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) ++ ++#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) ++ ++#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) ++ ++#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) ++ ++/* PEX Bar attributes */ ++typedef struct _mvPexBar ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_PEX_BAR; ++ ++/* PEX Remap Window attributes */ ++typedef struct _mvPexRemapWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_PEX_REMAP_WIN; ++ ++/* PEX Remap Window attributes */ ++typedef struct _mvPexDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_U32 targetBar; ++ MV_U8 attrib; /* chip select attributes */ ++ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_PEX_DEC_WIN; ++ ++/* Global Functions prototypes */ ++/* mvPexHalInit - Initialize PEX interfaces*/ ++MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); ++ ++ ++/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ ++MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin); ++ ++/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ ++MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin); ++ ++/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ ++MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable); ++ ++/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ ++MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_REMAP_WIN *pAddrWin); ++ ++/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ ++MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, ++ MV_BOOL enable); ++ ++/* mvPexBarSet - Set PEX bar address and size */ ++MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); ++ ++/* mvPexBarGet - Get PEX bar address and size */ ++MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); ++ ++/* mvPexBarEnable - enable\disable a PEX bar*/ ++MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); ++ ++/* mvPexAddrDecShow - Display address decode windows attributes */ ++MV_VOID mvPexAddrDecShow(MV_VOID); ++ ++#endif +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,430 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "mvTypes.h" ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "cpu/mvCpu.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "sata/CoreDriver/mvRegs.h" ++#include "ctrlEnv/sys/mvSysSata.h" ++ ++MV_TARGET sataAddrDecPrioTab[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_MEM, ++#endif ++ TBL_TERM ++}; ++ ++ ++/******************************************************************************* ++* sataWinOverlapDetect - Detect SATA address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case SATA address decode ++* windows overlapps. ++* This function detects SATA address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_SATA_DEC_WIN addrDecWin; ++ ++ for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = 0; ++ decRegs.sizeReg = 0; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; ++ decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); ++ ++ /* set target ID */ ++ decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; ++ decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); ++ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); ++ MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSataWinGet - Get SATA peripheral target address window. ++* ++* DESCRIPTION: ++* Get SATA peripheral target address window. ++* ++* INPUT: ++* winNum - SATA target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - SATA target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", ++ __FUNCTION__, dev, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); ++ decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) ++ { ++ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> ++ MV_SATA_WIN_ATTR_OFFSET; ++ targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> ++ MV_SATA_WIN_TARGET_OFFSET; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++/******************************************************************************* ++* mvSataAddrDecShow - Print the SATA address decode map. ++* ++* DESCRIPTION: ++* This function print the SATA address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvSataAddrDecShow(MV_VOID) ++{ ++ ++ MV_SATA_DEC_WIN win; ++ int i,j; ++ ++ ++ ++ for( j = 0; j < MV_SATA_MAX_CHAN; j++ ) ++ { ++ if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j)) ++ return; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "SATA %d:\n", j ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvSataWinGet(j, i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ } ++} ++ ++ ++/******************************************************************************* ++* mvSataWinInit - Initialize the integrated SATA target address window. ++* ++* DESCRIPTION: ++* Initialize the SATA peripheral target address window. ++* ++* INPUT: ++* ++* ++* OUTPUT: ++* ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSataWinInit(MV_VOID) ++{ ++ int winNum; ++ MV_SATA_DEC_WIN sataWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_U32 status, winPrioIndex = 0; ++ ++ /* Initiate Sata address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); ++ regVal &= ~MV_SATA_WIN_ENABLE_MASK; ++ MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); ++ } ++ ++ winNum = 0; ++ while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && ++ (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) ++ { ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], ++ &cpuAddrDecWin); ++ ++ if(MV_NO_SUCH == status) ++ { ++ winPrioIndex++; ++ continue; ++ } ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ sataWin.enable = MV_TRUE; ++ sataWin.target = sataAddrDecPrioTab[winPrioIndex]; ++ ++ if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) ++ { ++ return MV_ERROR; ++ } ++ winNum++; ++ } ++ winPrioIndex++; ++ } ++ return MV_OK; ++} ++ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,128 @@ ++ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCMVSysSataAddrDech ++#define __INCMVSysSataAddrDech ++ ++#include "mvCommon.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++typedef struct _mvSataDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++} MV_SATA_DEC_WIN; ++ ++ ++#define MV_SATA_MAX_ADDR_DECODE_WIN 4 ++ ++#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) ++#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) ++ ++/* BITs in Bridge Interrupt Cause and Mask registers */ ++#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 ++#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= MV_SDMMC_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = 0; ++ decRegs.sizeReg = 0; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK; ++ decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET); ++ ++ /* set target ID */ ++ decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK; ++ decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET); ++ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); ++ MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSdmmcWinGet - Get SDMMC peripheral target address window. ++* ++* DESCRIPTION: ++* Get SDMMC peripheral target address window. ++* ++* INPUT: ++* winNum - SDMMC target address decode window number. ++*d ++* OUTPUT: ++* pAddrDecWin - SDMMC target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", ++ __FUNCTION__, dev, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) ); ++ decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) ); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) ++ { ++ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >> ++ MV_SDMMC_WIN_ATTR_OFFSET; ++ targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >> ++ MV_SDMMC_WIN_TARGET_OFFSET; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++/******************************************************************************* ++* mvSdmmcAddrDecShow - Print the SDMMC address decode map. ++* ++* DESCRIPTION: ++* This function print the SDMMC address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvSdmmcAddrDecShow(MV_VOID) ++{ ++ ++ MV_SDMMC_DEC_WIN win; ++ int i,j=0; ++ ++ ++ ++ if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0)) ++ return; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "SDMMC %d:\n", j ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvSdmmcWinGet(j, i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ ++ ++/******************************************************************************* ++* mvSdmmcWinInit - Initialize the integrated SDMMC target address window. ++* ++* DESCRIPTION: ++* Initialize the SDMMC peripheral target address window. ++* ++* INPUT: ++* ++* ++* OUTPUT: ++* ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSdmmcWinInit(MV_VOID) ++{ ++ int winNum; ++ MV_SDMMC_DEC_WIN sdmmcWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_U32 status, winPrioIndex = 0; ++ ++ /* Initiate Sdmmc address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum)); ++ regVal &= ~MV_SDMMC_WIN_ENABLE_MASK; ++ MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal); ++ } ++ ++ winNum = 0; ++ while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) && ++ (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) ) ++ { ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex], ++ &cpuAddrDecWin); ++ ++ if(MV_NO_SUCH == status) ++ { ++ winPrioIndex++; ++ continue; ++ } ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ sdmmcWin.enable = MV_TRUE; ++ sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex]; ++ ++ if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin)) ++ { ++ return MV_ERROR; ++ } ++ winNum++; ++ } ++ winPrioIndex++; ++ } ++ return MV_OK; ++} ++ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,125 @@ ++ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCMVSysSdmmcAddrDech ++#define __INCMVSysSdmmcAddrDech ++ ++#include "mvCommon.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++typedef struct _mvSdmmcDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++} MV_SDMMC_DEC_WIN; ++ ++ ++#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4 ++ ++#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3)) ++#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3)) ++ ++ ++/* BITs in Windows 0-3 Control and Base Registers */ ++#define MV_SDMMC_WIN_ENABLE_BIT 0 ++#define MV_SDMMC_WIN_ENABLE_MASK (1<= TDM_MBUS_MAX_WIN) ++ { ++ mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* for the safe side we disable the window before writing the new ++ values */ ++ mvTdmWinEnable(winNum, MV_FALSE); ++ ++ ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); ++ ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); ++ ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK); ++ ++ /* Write to address base and control registers */ ++ MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); ++ MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); ++ /* Enable address decode target window */ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ mvTdmWinEnable(winNum, MV_TRUE); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTdmWinGet - Get peripheral target address window. ++* ++* DESCRIPTION: ++* Get TDM peripheral target address window. ++* ++* INPUT: ++* winNum - TDM to target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - TDM target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++ ++MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) ++{ ++ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= TDM_MBUS_MAX_WIN) ++ { ++ mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; ++ targetAttrib.targetId = ++ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTdmWinEnable - Enable/disable a TDM to target address window ++* ++* DESCRIPTION: ++* This function enable/disable a TDM to target address window. ++* According to parameter 'enable' the routine will enable the ++* window, thus enabling TDM accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - TDM to target address decode window number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if decode window number was wrong or enabled window overlapps. ++* ++*******************************************************************************/ ++MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) ++{ ++ MV_TDM_DEC_WIN addrDecWin; ++ ++ if (MV_TRUE == enable) ++ { ++ if (winNum >= TDM_MBUS_MAX_WIN) ++ { ++ mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ /* First check for overlap with other enabled windows */ ++ /* Get current window */ ++ if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) ++ { ++ mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode target window */ ++ MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); ++ } ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* tdmWinOverlapDetect - Detect TDM address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviour is expected in case TDM address decode ++* windows overlapps. ++* This function detects TDM address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_TDM_DEC_WIN addrDecWin; ++ ++ for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) ++ { ++ /* Do not check window itself */ ++ if (winNumIndex == winNum) ++ { ++ continue; ++ } ++ /* Do not check disabled windows */ ++ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) ++ { ++ /* Get window parameters */ ++ if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) ++ { ++ DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); ++ return MV_ERROR; ++ } ++ ++ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) ++ { ++ return MV_TRUE; ++ } ++ } ++ } ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvTdmAddrDecShow - Print the TDM address decode map. ++* ++* DESCRIPTION: ++* This function print the TDM address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvTdmAddrDecShow(MV_VOID) ++{ ++ MV_TDM_DEC_WIN win; ++ int i; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "TDM:\n" ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if (mvTdmWinGet(i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); ++ mvOsOutput( "...." ); ++ mvSizePrint( win.addrWin.size ); ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,106 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSysTdmh ++#define __INCmvSysTdmh ++ ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++typedef struct _mvTdmDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++} MV_TDM_DEC_WIN; ++ ++MV_STATUS mvTdmWinInit(MV_VOID); ++MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable); ++MV_VOID mvTdmAddrDecShow(MV_VOID); ++ ++ ++#define TDM_MBUS_MAX_WIN 4 ++#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4)) ++#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) ++ ++/* TDM_WIN_CTRL_REG bits */ ++#define TDM_WIN_ENABLE_OFFS 0 ++#define TDM_WIN_ENABLE_MASK (1<= TSU_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target " ++ "%s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); ++ ++ if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK; ++ decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS; ++ /* set target ID */ ++ decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK; ++ decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS; ++ ++ /* for the safe side we disable the window before writing the new */ ++ /* values */ ++ mvTsuWinEnable(winNum, MV_FALSE); ++ MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg); ++ ++ /* Enable address decode target window */ ++ if(pAddrDecWin->enable == MV_TRUE) ++ { ++ mvTsuWinEnable(winNum,MV_TRUE); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvTsuWinGet ++* ++* DESCRIPTION: ++* Get TSU peripheral target address window. ++* ++* INPUT: ++* winNum - TSU to target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - TSU target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if(winNum >= TSU_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); ++ ++ if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS; ++ targetAttrib.targetId = ++ (decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK)) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvTsuWinEnable ++* ++* DESCRIPTION: ++* This function enable/disable a TSU to target address window. ++* According to parameter 'enable' the routine will enable the ++* window, thus enabling TSU accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - TSU to target address decode window number. ++* enable - Enable / disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if decode window number was wrong or enabled window overlapps. ++* ++*******************************************************************************/ ++MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable) ++{ ++ MV_TSU_DEC_WIN addrDecWin; ++ ++ /* Parameter checking */ ++ if(winNum >= TSU_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ if(enable == MV_TRUE) ++ { ++ /* First check for overlap with other enabled windows */ ++ /* Get current window. */ ++ if(MV_OK != mvTsuWinGet(winNum,&addrDecWin)) ++ { ++ mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n"); ++ return MV_ERROR; ++ } ++ /* Check for overlapping. */ ++ if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode target window */ ++ MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum), ++ TSU_WIN_CTRL_EN_MASK); ++ } ++ else ++ { ++ /* Overlap detected */ ++ mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ /* Disable address decode target window */ ++ MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum), ++ TSU_WIN_CTRL_EN_MASK); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTsuWinTargetGet ++* ++* DESCRIPTION: ++* Get Window number associated with target ++* ++* INPUT: ++* target - Target ID to get the window number for. ++* OUTPUT: ++* ++* RETURN: ++* window number or 0xFFFFFFFF on error. ++* ++*******************************************************************************/ ++MV_U32 mvTsuWinTargetGet(MV_TARGET target) ++{ ++ MV_TSU_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if(target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++) ++ { ++ if(mvTsuWinGet(winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvTsuWinGet: window returned error\n"); ++ return 0xffffffff; ++ } ++ ++ if (decWin.enable == MV_TRUE) ++ { ++ if(decWin.target == target) ++ { ++ return winNum; ++ } ++ } ++ } ++ return 0xFFFFFFFF; ++} ++ ++ ++/******************************************************************************* ++* tsuWinOverlapDetect ++* ++* DESCRIPTION: ++* Detect TSU address windows overlapping ++* An unpredicted behaviur is expected in case TSU address decode ++* windows overlapps. ++* This function detects TSU address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 ctrlReg; ++ MV_U32 winNumIndex; ++ MV_TSU_DEC_WIN addrDecWin; ++ ++ for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++) ++ { ++ /* Do not check window itself */ ++ if(winNumIndex == winNum) ++ { ++ continue; ++ } ++ ++ /* Do not check disabled windows */ ++ ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex)); ++ if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin)) ++ { ++ mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) ++ { ++ return MV_TRUE; ++ } ++ } ++ return MV_FALSE; ++} ++ ++ ++/******************************************************************************* ++* mvTsuAddrDecShow ++* ++* DESCRIPTION: ++* Print the TSU address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++void mvTsuAddrDecShow(void) ++{ ++ MV_TSU_DEC_WIN win; ++ int i; ++ ++ if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0)) ++ return; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "TSU:\n"); ++ mvOsOutput( "----\n" ); ++ ++ for(i = 0; i < TSU_MAX_DECODE_WIN; i++) ++ { ++ memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN)); ++ mvOsOutput( "win%d - ", i ); ++ ++ if(mvTsuWinGet(i, &win ) == MV_OK ) ++ { ++ if(win.enable == MV_TRUE) ++ { ++ mvOsOutput("%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), ++ win.addrWin.baseLow); ++ mvOsOutput( "...." ); ++ mvSizePrint(win.addrWin.size ); ++ mvOsOutput( "\n" ); ++ } ++ else ++ { ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ } ++ return; ++} ++ ++ ++/******************************************************************************* ++* mvTsuInit ++* ++* DESCRIPTION: ++* Initialize the TSU unit, and get unit out of reset. ++* ++* INPUT: ++* coreClock - The core clock at which the TSU should operate. ++* mode - The mode on configure the unit into (serial/parallel). ++* memHandle - Memory handle used for memory allocations. ++* OUTPUT: ++* None. ++* RETURN: ++* MV_OK - on success, ++* ++*******************************************************************************/ ++MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, ++ void *osHandle) ++{ ++ MV_STATUS status; ++ ++ status = mvTsuWinInit(); ++ if(status == MV_OK) ++ status = mvTsuHalInit(coreClock,mode,osHandle); ++ ++ return status; ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,110 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSysTsh ++#define __INCmvSysTsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* includes */ ++#include "ts/mvTsu.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++#define TSU_MAX_DECODE_WIN 4 ++ ++ ++/*******************************************/ ++/* TSU Windows Registers */ ++/*******************************************/ ++#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win) ++#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win) ++ ++/* TSU windows control register. */ ++#define TSU_WIN_CTRL_EN_MASK (0x1 << 0) ++#define TSU_WIN_CTRL_TARGET_OFFS 4 ++#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS) ++#define TSU_WIN_CTRL_ATTR_OFFS 8 ++#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS) ++#define TSU_WIN_CTRL_SIZE_OFFS 16 ++#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS) ++ ++/* TSU windows base register. */ ++#define TSU_WIN_BASE_OFFS 16 ++#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS) ++ ++MV_STATUS mvTsuWinInit(void); ++ ++void mvTsuAddrDecShow(void); ++MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, ++ void *osHandle); ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvTsh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,497 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "ctrlEnv/sys/mvSysUsb.h" ++ ++MV_TARGET usbAddrDecPrioTab[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA) ++ CRYPT_ENG, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_MEM, ++#endif ++ TBL_TERM ++}; ++ ++ ++ ++MV_STATUS mvUsbInit(int dev, MV_BOOL isHost) ++{ ++ MV_STATUS status; ++ ++ status = mvUsbWinInit(dev); ++ if(status != MV_OK) ++ return status; ++ ++ return mvUsbHalInit(dev, isHost); ++} ++ ++ ++/******************************************************************************* ++* usbWinOverlapDetect - Detect USB address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case USB address decode ++* windows overlapps. ++* This function detects USB address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_DEC_WIN addrDecWin; ++ ++ for(winNumIndex=0; winNumIndex= MV_USB_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pDecWin->target), ++ pDecWin->addrWin.baseLow, ++ pDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* set Size, Attributes and TargetID */ ++ sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | ++ ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | ++ ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); ++ ++#if defined(MV645xx) || defined(MV646xx) ++ /* If window is DRAM with HW cache coherency, make sure bit2 is set */ ++ sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; ++ ++ if((MV_TARGET_IS_DRAM(pDecWin->target)) && ++ (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) ++ { ++ sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; ++ } ++ else ++ { ++ sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; ++ } ++#endif /* MV645xx || MV646xx */ ++ ++ if (pDecWin->enable == MV_TRUE) ++ { ++ sizeReg |= MV_USB_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ sizeReg &= ~MV_USB_WIN_ENABLE_MASK; ++ } ++ ++ /* Update Base value */ ++ baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); ++ ++ MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); ++ MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvUsbWinGet - Get USB peripheral target address window. ++* ++* DESCRIPTION: ++* Get USB peripheral target address window. ++* ++* INPUT: ++* winNum - USB target address decode window number. ++* ++* OUTPUT: ++* pDecWin - USB target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) ++{ ++ MV_DEC_WIN_PARAMS winParam; ++ MV_U32 sizeReg, baseReg; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", ++ __FUNCTION__, dev, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); ++ sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); ++ ++ /* Check if window is enabled */ ++ if(sizeReg & MV_USB_WIN_ENABLE_MASK) ++ { ++ pDecWin->enable = MV_TRUE; ++ ++ /* Extract window parameters from registers */ ++ winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; ++ winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; ++ winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; ++ winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); ++ ++ /* Translate the decode window parameters to address decode struct */ ++ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) ++ { ++ mvOsPrintf("Failed to translate register parameters to USB address" \ ++ " decode window structure\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ pDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvUsbWinInit - ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvUsbWinInit(int dev) ++{ ++ MV_STATUS status; ++ MV_DEC_WIN usbWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ int winNum; ++ MV_U32 winPrioIndex = 0; ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); ++ } ++ ++ /* Go through all windows in user table until table terminator */ ++ winNum = 0; ++ while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && ++ (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) ++ { ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], ++ &cpuAddrDecWin); ++ ++ if(MV_NO_SUCH == status) ++ { ++ winPrioIndex++; ++ continue; ++ } ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ usbWin.enable = MV_TRUE; ++ usbWin.target = usbAddrDecPrioTab[winPrioIndex]; ++ ++#if defined(MV645xx) || defined(MV646xx) ++ /* Get the default attributes for that target window */ ++ mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); ++#endif /* MV645xx || MV646xx */ ++ ++ if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) ++ { ++ return MV_ERROR; ++ } ++ winNum++; ++ } ++ winPrioIndex++; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvUsbAddrDecShow - Print the USB address decode map. ++* ++* DESCRIPTION: ++* This function print the USB address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvUsbAddrDecShow(MV_VOID) ++{ ++ MV_DEC_WIN addrDecWin; ++ int i, winNum; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "USB:\n" ); ++ mvOsOutput( "----\n" ); ++ ++ for(i=0; i= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); ++ return MV_BAD_PARAM; ++ } ++ if (pAddrDecWin == NULL) ++ { ++ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); ++ return MV_BAD_PTR; ++ } ++ /* Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); ++ return MV_ERROR; ++ } ++ ++ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); ++ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); ++ ++ /* Get Base Address and size registers values */ ++ if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; ++ xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; ++ /* set target ID */ ++ xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; ++ xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; ++ ++ ++ /* Write to address decode Base Address Register */ ++ MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); ++ ++ /* Write to Size Register */ ++ MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ if (pAddrDecWin->enable) ++ { ++ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorTargetWinGet - Get xor peripheral target address window. ++* ++* DESCRIPTION: ++* Get xor peripheral target address window. ++* ++* INPUT: ++* winNum - One of the possible XOR memory decode windows. ++* ++* OUTPUT: ++* base - Window base address. ++* size - Window size. ++* enable - window enable/disable. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS xorDecRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ MV_U32 chan=0,chanWinEn; ++ ++ /* Parameter checking */ ++ if (winNum >= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); ++ return MV_ERROR; ++ } ++ ++ if (NULL == pAddrDecWin) ++ { ++ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); ++ return MV_BAD_PTR; ++ } ++ ++ chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */ ++ { ++ /* Check if enable bit is equal for all channels */ ++ if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & ++ XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) ++ { ++ mvOsPrintf("%s: ERR. Window enable field must be equal in " ++ "all channels(chan=%d)\n",__FUNCTION__, chan); ++ return MV_ERROR; ++ } ++ } ++ ++ ++ ++ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); ++ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; ++ targetAttrib.targetId = ++ (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; ++ ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ if(chanWinEn) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else pAddrDecWin->enable = MV_FALSE; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorTargetWinEnable - Enable/disable a Xor address decode window ++* ++* DESCRIPTION: ++* This function enable/disable a XOR address decode window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling XOR accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - Decode window number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) ++{ ++ MV_XOR_DEC_WIN addrDecWin; ++ MV_U32 chan; ++ ++ /* Parameter checking */ ++ if (winNum >= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { ++ /* Get current window */ ++ if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); ++ return MV_ERROR; ++ } ++ ++ /* Check for overlapping */ ++ if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) ++ { ++ /* Overlap detected */ ++ DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); ++ return MV_ERROR; ++ } ++ ++ /* No Overlap. Enable address decode target window */ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ ++ } ++ else ++ { ++ /* Disable address decode target window */ ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorSetProtWinSet - Configure access attributes of a XOR engine ++* to one of the XOR memory windows. ++* ++* DESCRIPTION: ++* Each engine can be configured with access attributes for each of the ++* memory spaces. This function sets access attributes ++* to a given window for the given engine ++* ++* INPUTS: ++* chan - One of the possible engines. ++* winNum - One of the possible XOR memory spaces. ++* access - Protection access rights. ++* write - Write rights. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, ++ MV_BOOL write) ++{ ++ MV_U32 temp; ++ ++ /* Parameter checking */ ++ if (chan >= MV_XOR_MAX_CHAN_PER_UNIT) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); ++ return MV_BAD_PARAM; ++ } ++ if (winNum >= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); ++ return MV_BAD_PARAM; ++ } ++ ++ temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & ++ (~XEXWCR_WIN_ACC_MASK(winNum)); ++ ++ /* if access is disable */ ++ if (!access) ++ { ++ /* disable access */ ++ temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); ++ } ++ /* if access is enable */ ++ else ++ { ++ /* if write is enable */ ++ if (write) ++ { ++ /* enable write */ ++ temp |= XEXWCR_WIN_ACC_RW(winNum); ++ } ++ /* if write is disable */ ++ else ++ { ++ /* disable write */ ++ temp |= XEXWCR_WIN_ACC_RO(winNum); ++ } ++ } ++ MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorPciRemap - Set XOR remap register for PCI address windows. ++* ++* DESCRIPTION: ++* only Windows 0-3 can be remapped. ++* ++* INPUT: ++* winNum - window number ++* pAddrDecWin - pointer to address space window structure ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) ++{ ++ /* Parameter checking */ ++ if (winNum >= XOR_MAX_REMAP_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); ++ return MV_BAD_PARAM; ++ } ++ ++ MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* xorWinOverlapDetect - Detect XOR address windows overlaping ++* ++* DESCRIPTION: ++* An unpredicted behaviour is expected in case XOR address decode ++* windows overlaps. ++* This function detects XOR address decode windows overlaping of a ++* specified window. The function does not check the window itself for ++* overlaping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 baseAddrEnableReg; ++ MV_U32 winNumIndex,chan; ++ MV_XOR_DEC_WIN addrDecWin; ++ ++ if (pAddrWin == NULL) ++ { ++ DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); ++ return MV_BAD_PTR; ++ } ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ /* Read base address enable register. Do not check disabled windows */ ++ baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); ++ ++ for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) ++ { ++ /* Do not check window itself */ ++ if (winNumIndex == winNum) ++ { ++ continue; ++ } ++ ++ /* Do not check disabled windows */ ++ if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); ++ return MV_ERROR; ++ } ++ ++ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) ++ { ++ return MV_TRUE; ++ } ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) ++{ ++ MV_XOR_DEC_WIN win; ++ int i; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "XOR %d:\n", unit ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvXorAddrDecShow - Print the XOR address decode map. ++* ++* DESCRIPTION: ++* This function print the XOR address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvXorAddrDecShow(MV_VOID) ++{ ++ int i; ++ ++ for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) ++ mvXorAddrDecShowUnit(i); ++ ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,140 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCMVSysXorh ++#define __INCMVSysXorh ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ ++#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ ++ ++/* XOR Engine Address Decoding Register Map */ ++#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) ++#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) ++#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) ++#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) ++ ++/* XOR Engine [0..1] Window Control Registers (XExWCR) */ ++#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) ++#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) ++#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) ++#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) ++ ++#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) ++#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++ ++/* XOR Engine Base Address Registers (XEBARx) */ ++#define XEBARX_TARGET_OFFS (0) ++#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) ++#define XEBARX_ATTR_OFFS (8) ++#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) ++#define XEBARX_BASE_OFFS (16) ++#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) ++ ++/* XOR Engine Size Mask Registers (XESMRx) */ ++#define XESMRX_SIZE_MASK_OFFS (16) ++#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) ++ ++/* XOR Engine High Address Remap Register (XEHARRx1) */ ++#define XEHARRX_REMAP_OFFS (0) ++#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) ++ ++typedef struct _mvXorDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_XOR_DEC_WIN; ++ ++MV_STATUS mvXorInit (MV_VOID); ++MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, ++ MV_XOR_DEC_WIN *pAddrDecWin); ++MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, ++ MV_XOR_DEC_WIN *pAddrDecWin); ++MV_STATUS mvXorTargetWinEnable(MV_U32 unit, ++ MV_U32 winNum, MV_BOOL enable); ++MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, ++ MV_BOOL write); ++MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); ++ ++MV_VOID mvXorAddrDecShow(MV_VOID); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,75 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "device/mvDevice.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,74 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDeviceH ++#define __INCmvDeviceH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "device/mvDeviceRegs.h" ++ ++ ++#endif /* #ifndef __INCmvDeviceH */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,101 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDeviceRegsH ++#define __INCmvDeviceRegsH ++ ++#ifndef MV_ASMLANGUAGE ++#include "ctrlEnv/mvCtrlEnvLib.h" ++/* This enumerator describes the Marvell controller possible devices that */ ++/* can be connected to its device interface. */ ++typedef enum _mvDevice ++{ ++#if defined(MV_INCLUDE_DEVICE_CS0) ++ DEV_CS0 = 0, /* Device connected to dev CS[0] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS1) ++ DEV_CS1 = 1, /* Device connected to dev CS[1] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS2) ++ DEV_CS2 = 2, /* Device connected to dev CS[2] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS3) ++ DEV_CS3 = 3, /* Device connected to dev CS[2] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS4) ++ DEV_CS4 = 4, /* Device connected to BOOT dev */ ++#endif ++ MV_DEV_MAX_CS = MV_DEVICE_MAX_CS ++}MV_DEVICE; ++ ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#define NAND_CTRL_REG 0x10470 ++ ++#define NAND_ACTCEBOOT_BIT BIT1 ++ ++ ++#endif /* #ifndef __INCmvDeviceRegsH */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,211 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++/******************************************************************************* ++* mvOsCpuArchLib.c - Marvell CPU architecture library ++* ++* DESCRIPTION: ++* This library introduce Marvell API for OS dependent CPU architecture ++* APIs. This library introduce single CPU architecture services APKI ++* cross OS. ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#include ++#include "mvOs.h" ++ ++static MV_U32 read_p15_c0 (void); ++ ++/* defines */ ++#define ARM_ID_REVISION_OFFS 0 ++#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS) ++ ++#define ARM_ID_PART_NUM_OFFS 4 ++#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS) ++ ++#define ARM_ID_ARCH_OFFS 16 ++#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS) ++ ++#define ARM_ID_VAR_OFFS 20 ++#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS) ++ ++#define ARM_ID_ASCII_OFFS 24 ++#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS) ++ ++ ++ ++void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, ++ MV_U32 *memHandle) ++{ ++ void *p = kmalloc( size, GFP_KERNEL ); ++ *pPhyAddr = pci_map_single( osHandle, p, 0, PCI_DMA_BIDIRECTIONAL ); ++ return p; ++} ++void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, ++ MV_U32 *memHandle) ++{ ++ return pci_alloc_consistent( osHandle, size, (dma_addr_t *)pPhyAddr ); ++} ++ ++void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, ++ MV_U32 memHandle) ++{ ++ return pci_free_consistent( osHandle, size, pVirtAddr, (dma_addr_t)phyAddr ); ++} ++ ++void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, ++ MV_U32 memHandle ) ++{ ++ return kfree( pVirtAddr ); ++} ++ ++int mvOsRand(void) ++{ ++ int rand; ++ get_random_bytes(&rand, sizeof(rand) ); ++ return rand; ++} ++ ++/******************************************************************************* ++* mvOsCpuVerGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Revision ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuRevGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuPartGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Part number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuPartGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuArchGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Architicture number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuArchGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuVarGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Variant number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuVarGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuAsciiGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Variant number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuAsciiGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS); ++} ++ ++ ++ ++/* ++static unsigned long read_p15_c0 (void) ++*/ ++/* read co-processor 15, register #0 (ID register) */ ++static MV_U32 read_p15_c0 (void) ++{ ++ MV_U32 value; ++ ++ __asm__ __volatile__( ++ "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" ++ : "=r" (value) ++ : ++ : "memory"); ++ ++ return value; ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,423 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++#ifndef _MV_OS_LNX_H_ ++#define _MV_OS_LNX_H_ ++ ++ ++#ifdef __KERNEL__ ++/* for kernel space */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "dbg-trace.h" ++ ++extern void mv_early_printk(char *fmt,...); ++ ++#define MV_ASM __asm__ __volatile__ ++#define INLINE inline ++#define MV_TRC_REC TRC_REC ++#define mvOsPrintf printk ++#define mvOsEarlyPrintf mv_early_printk ++#define mvOsOutput printk ++#define mvOsSPrintf sprintf ++#define mvOsMalloc(_size_) kmalloc(_size_,GFP_ATOMIC) ++#define mvOsFree kfree ++#define mvOsMemcpy memcpy ++#define mvOsSleep(_mils_) mdelay(_mils_) ++#define mvOsTaskLock() ++#define mvOsTaskUnlock() ++#define strtol simple_strtoul ++#define mvOsDelay(x) mdelay(x) ++#define mvOsUDelay(x) udelay(x) ++#define mvCopyFromOs copy_from_user ++#define mvCopyToOs copy_to_user ++ ++ ++#include "mvTypes.h" ++#include "mvCommon.h" ++ ++#ifdef MV_NDEBUG ++#define mvOsAssert(cond) ++#else ++#define mvOsAssert(cond) { do { if(!(cond)) { BUG(); } }while(0); } ++#endif /* MV_NDEBUG */ ++ ++#else /* __KERNEL__ */ ++ ++/* for user space applications */ ++#include ++#include ++#include ++#include ++ ++#define INLINE inline ++#define mvOsPrintf printf ++#define mvOsOutput printf ++#define mvOsMalloc(_size_) malloc(_size_) ++#define mvOsFree free ++#define mvOsAssert(cond) assert(cond) ++ ++#endif /* __KERNEL__ */ ++#define mvOsIoVirtToPhy(pDev, pVirtAddr) \ ++ pci_map_single( (pDev), (pVirtAddr), 0, PCI_DMA_BIDIRECTIONAL ) ++ ++#define mvOsCacheClear(pDev, p, size ) \ ++ pci_map_single( (pDev), (p), (size), PCI_DMA_BIDIRECTIONAL) ++ ++#define mvOsCacheFlush(pDev, p, size ) \ ++ pci_map_single( (pDev), (p), (size), PCI_DMA_TODEVICE) ++ ++#define mvOsCacheInvalidate(pDev, p, size) \ ++ pci_map_single( (pDev), (p), (size), PCI_DMA_FROMDEVICE ) ++ ++#define mvOsCacheUnmap(pDev, phys, size) \ ++ pci_unmap_single( (pDev), (dma_addr_t)(phys), (size), PCI_DMA_FROMDEVICE ) ++ ++ ++#define CPU_PHY_MEM(x) (MV_U32)x ++#define CPU_MEMIO_CACHED_ADDR(x) (void*)x ++#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x ++ ++ ++/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */ ++#define MV_MEMIO32_WRITE(addr, data) \ ++ ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data))) ++ ++#define MV_MEMIO32_READ(addr) \ ++ ((*((volatile unsigned int*)(addr)))) ++ ++#define MV_MEMIO16_WRITE(addr, data) \ ++ ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data))) ++ ++#define MV_MEMIO16_READ(addr) \ ++ ((*((volatile unsigned short*)(addr)))) ++ ++#define MV_MEMIO8_WRITE(addr, data) \ ++ ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data))) ++ ++#define MV_MEMIO8_READ(addr) \ ++ ((*((volatile unsigned char*)(addr)))) ++ ++ ++/* No Fast Swap implementation (in assembler) for ARM */ ++#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val) ++#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val) ++#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val) ++#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val) ++ ++/* 32 and 16 bit read/write in big/little endian mode */ ++ ++/* 16bit write in little endian mode */ ++#define MV_MEMIO_LE16_WRITE(addr, data) \ ++ MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data)) ++ ++/* 16bit read in little endian mode */ ++static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr) ++{ ++ MV_U16 data; ++ ++ data= (MV_U16)MV_MEMIO16_READ(addr); ++ ++ return (MV_U16)MV_16BIT_LE_FAST(data); ++} ++ ++/* 32bit write in little endian mode */ ++#define MV_MEMIO_LE32_WRITE(addr, data) \ ++ MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data)) ++ ++/* 32bit read in little endian mode */ ++static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr) ++{ ++ MV_U32 data; ++ ++ data= (MV_U32)MV_MEMIO32_READ(addr); ++ ++ return (MV_U32)MV_32BIT_LE_FAST(data); ++} ++ ++static __inline void mvOsBCopy(char* srcAddr, char* dstAddr, int byteCount) ++{ ++ while(byteCount != 0) ++ { ++ *dstAddr = *srcAddr; ++ dstAddr++; ++ srcAddr++; ++ byteCount--; ++ } ++} ++ ++static INLINE MV_U64 mvOsDivMod64(MV_U64 divided, MV_U64 divisor, MV_U64* modulu) ++{ ++ MV_U64 division = 0; ++ ++ if(divisor == 1) ++ return divided; ++ ++ while(divided >= divisor) ++ { ++ division++; ++ divided -= divisor; ++ } ++ if (modulu != NULL) ++ *modulu = divided; ++ ++ return division; ++} ++ ++#if defined(MV_BRIDGE_SYNC_REORDER) ++extern MV_U32 *mvUncachedParam; ++ ++static __inline void mvOsBridgeReorderWA(void) ++{ ++ volatile MV_U32 val = 0; ++ ++ val = mvUncachedParam[0]; ++} ++#endif ++ ++ ++/* Flash APIs */ ++#define MV_FL_8_READ MV_MEMIO8_READ ++#define MV_FL_16_READ MV_MEMIO_LE16_READ ++#define MV_FL_32_READ MV_MEMIO_LE32_READ ++#define MV_FL_8_DATA_READ MV_MEMIO8_READ ++#define MV_FL_16_DATA_READ MV_MEMIO16_READ ++#define MV_FL_32_DATA_READ MV_MEMIO32_READ ++#define MV_FL_8_WRITE MV_MEMIO8_WRITE ++#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE ++#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE ++#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE ++#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE ++#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE ++ ++ ++/* CPU cache information */ ++#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ ++#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ ++ ++#ifdef CONFIG_L2_CACHE_ENABLE ++/* Data cache flush one line */ ++#define mvOsCacheLineFlushInv(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c10, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ ++} ++ ++#else ++ ++/* Data cache flush one line */ ++#define mvOsCacheLineFlushInv(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ ++} ++#endif ++ ++#ifdef CONFIG_L2_CACHE_ENABLE ++#define mvOsCacheLineInv(handle,addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ ++ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c11, 1" : : "r" (addr)); \ ++} ++#else ++#define mvOsCacheLineInv(handle,addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ ++} ++#endif ++ ++#ifdef CONFIG_L2_CACHE_ENABLE ++/* Data cache flush one line */ ++#define mvOsCacheLineFlush(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c9, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ ++} ++ ++#else ++/* Data cache flush one line */ ++#define mvOsCacheLineFlush(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ ++} ++#endif ++ ++static __inline void mvOsPrefetch(const void *ptr) ++{ ++#ifdef CONFIG_USE_DSP ++ __asm__ __volatile__( ++ "pld\t%0" ++ : ++ : "o" (*(char *)ptr) ++ : "cc"); ++#else ++ return; ++#endif ++} ++ ++ ++/* Flush CPU pipe */ ++#define CPU_PIPE_FLUSH ++ ++ ++ ++ ++ ++/* register manipulations */ ++ ++/****************************************************************************** ++* This debug function enable the write of each register that u-boot access to ++* to an array in the DRAM, the function record only MV_REG_WRITE access. ++* The function could not be operate when booting from flash. ++* In order to print the array we use the printreg command. ++******************************************************************************/ ++/* #define REG_DEBUG */ ++#if defined(REG_DEBUG) ++extern int reg_arry[2048][2]; ++extern int reg_arry_index; ++#endif ++ ++/* Marvell controller register read/write macros */ ++#define MV_REG_VALUE(offset) \ ++ (MV_MEMIO32_READ((INTER_REGS_BASE | (offset)))) ++ ++#define MV_REG_READ(offset) \ ++ (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset))) ++ ++#if defined(REG_DEBUG) ++#define MV_REG_WRITE(offset, val) \ ++ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (val);\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_WRITE(offset, val) \ ++ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); ++#endif ++ ++#define MV_REG_BYTE_READ(offset) \ ++ (MV_MEMIO8_READ((INTER_REGS_BASE | (offset)))) ++ ++#if defined(REG_DEBUG) ++#define MV_REG_BYTE_WRITE(offset, val) \ ++ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (val);\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_BYTE_WRITE(offset, val) \ ++ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)) ++#endif ++ ++#if defined(REG_DEBUG) ++#define MV_REG_BIT_SET(offset, bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ ++ MV_32BIT_LE_FAST(bitMask)))); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_BIT_SET(offset, bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ ++ MV_32BIT_LE_FAST(bitMask)))) ++#endif ++ ++#if defined(REG_DEBUG) ++#define MV_REG_BIT_RESET(offset,bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ ++ MV_32BIT_LE_FAST(~bitMask)))); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_BIT_RESET(offset,bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ ++ MV_32BIT_LE_FAST(~bitMask)))) ++#endif ++ ++ ++ ++/* ARM architecture APIs */ ++MV_U32 mvOsCpuRevGet (MV_VOID); ++MV_U32 mvOsCpuPartGet (MV_VOID); ++MV_U32 mvOsCpuArchGet (MV_VOID); ++MV_U32 mvOsCpuVarGet (MV_VOID); ++MV_U32 mvOsCpuAsciiGet (MV_VOID); ++ ++/* Other APIs */ ++void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle); ++void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle ); ++void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); ++void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); ++int mvOsRand(void); ++ ++#endif /* _MV_OS_LNX_H_ */ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,158 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++/******************************************************************************* ++* mvOsLinux.h - O.S. interface header file for Linux ++* ++* DESCRIPTION: ++* This header file contains OS dependent definition under Linux ++* ++* DEPENDENCIES: ++* Linux kernel header files. ++* ++* FILE REVISION NUMBER: ++* $Revision: 1.1 $ ++*******************************************************************************/ ++ ++#ifndef __INCmvOsLinuxh ++#define __INCmvOsLinuxh ++ ++/* Includes */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include "mvOs.h" ++ ++ ++/* Definitions */ ++#define MV_DEFAULT_QUEUE_DEPTH 2 ++#define MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION ++#define MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN ++ ++#ifdef CONFIG_MV88F6082 ++ #define MV_SATA_OVERRIDE_SW_QUEUE_SIZE ++ #define MV_SATA_REQUESTED_SW_QUEUE_SIZE 2 ++ #undef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN ++#endif ++ ++/* System dependent macro for flushing CPU write cache */ ++#if defined (MV_BRIDGE_SYNC_REORDER) ++#define MV_CPU_WRITE_BUFFER_FLUSH() do { \ ++ wmb(); \ ++ mvOsBridgeReorderWA(); \ ++ } while (0) ++#else ++#define MV_CPU_WRITE_BUFFER_FLUSH() wmb() ++#endif /* CONFIG_MV78XX0 */ ++ ++/* System dependent little endian from / to CPU conversions */ ++#define MV_CPU_TO_LE16(x) cpu_to_le16(x) ++#define MV_CPU_TO_LE32(x) cpu_to_le32(x) ++ ++#define MV_LE16_TO_CPU(x) le16_to_cpu(x) ++#define MV_LE32_TO_CPU(x) le32_to_cpu(x) ++ ++#ifdef __BIG_ENDIAN_BITFIELD ++#define MV_BIG_ENDIAN_BITFIELD ++#endif ++ ++/* System dependent register read / write in byte/word/dword variants */ ++#define MV_REG_WRITE_BYTE(base, offset, val) writeb(val, base + offset) ++#define MV_REG_WRITE_WORD(base, offset, val) writew(val, base + offset) ++#define MV_REG_WRITE_DWORD(base, offset, val) writel(val, base + offset) ++#define MV_REG_READ_BYTE(base, offset) readb(base + offset) ++#define MV_REG_READ_WORD(base, offset) readw(base + offset) ++#define MV_REG_READ_DWORD(base, offset) readl(base + offset) ++ ++ ++/* Typedefs */ ++ ++/* System dependant typedefs */ ++typedef void *MV_VOID_PTR; ++typedef u32 *MV_U32_PTR; ++typedef u16 *MV_U16_PTR; ++typedef u8 *MV_U8_PTR; ++typedef char *MV_CHAR_PTR; ++typedef void *MV_BUS_ADDR_T; ++typedef unsigned long MV_CPU_FLAGS; ++ ++ ++/* Structures */ ++/* System dependent structure */ ++typedef struct mvOsSemaphore ++{ ++ int notUsed; ++} MV_OS_SEMAPHORE; ++ ++ ++/* Functions (User implemented)*/ ++ ++/* Semaphore init, take and release */ ++#define mvOsSemInit(x) MV_TRUE ++#define mvOsSemTake(x) ++#define mvOsSemRelease(x) ++ ++/* Interrupt masking and unmasking functions */ ++MV_CPU_FLAGS mvOsSaveFlagsAndMaskCPUInterrupts(MV_VOID); ++MV_VOID mvOsRestoreFlags(MV_CPU_FLAGS); ++ ++/* Delay function in micro seconds resolution */ ++void mvMicroSecondsDelay(MV_VOID_PTR, MV_U32); ++ ++/* Typedefs */ ++typedef enum mvBoolean ++{ ++ MV_SFALSE, MV_STRUE ++} MV_BOOLEAN; ++ ++/* System logging function */ ++#include "mvLog.h" ++/* Enable READ/WRITE Long SCSI command only when driver is compiled for debugging */ ++#ifdef MV_LOGGER ++#define MV_SATA_SUPPORT_READ_WRITE_LONG ++#endif ++ ++#define MV_IAL_LOG_ID 3 ++ ++#endif /* __INCmvOsLinuxh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,375 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++ ++*******************************************************************************/ ++/******************************************************************************* ++* mvSysHwCfg.h - Marvell system HW configuration file ++* ++* DESCRIPTION: ++* None. ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++#ifndef __INCmvSysHwConfigh ++#define __INCmvSysHwConfigh ++ ++#include "../../../../include/linux/autoconf.h" ++ ++#define CONFIG_MARVELL 1 ++ ++/* includes */ ++#define _1K 0x00000400 ++#define _4K 0x00001000 ++#define _8K 0x00002000 ++#define _16K 0x00004000 ++#define _32K 0x00008000 ++#define _64K 0x00010000 ++#define _128K 0x00020000 ++#define _256K 0x00040000 ++#define _512K 0x00080000 ++ ++#define _1M 0x00100000 ++#define _2M 0x00200000 ++#define _4M 0x00400000 ++#define _8M 0x00800000 ++#define _16M 0x01000000 ++#define _32M 0x02000000 ++#define _64M 0x04000000 ++#define _128M 0x08000000 ++#define _256M 0x10000000 ++#define _512M 0x20000000 ++ ++#define _1G 0x40000000 ++#define _2G 0x80000000 ++ ++/****************************************/ ++/* Soc supporeted Units definitions */ ++/****************************************/ ++ ++#ifdef CONFIG_MV_INCLUDE_PEX ++#define MV_INCLUDE_PEX ++#endif ++#ifdef CONFIG_MV_INCLUDE_TWSI ++#define MV_INCLUDE_TWSI ++#endif ++#ifdef CONFIG_MV_INCLUDE_CESA ++#define MV_INCLUDE_CESA ++#endif ++#ifdef CONFIG_MV_INCLUDE_GIG_ETH ++#define MV_INCLUDE_GIG_ETH ++#endif ++#ifdef CONFIG_MV_INCLUDE_INTEG_SATA ++#define MV_INCLUDE_INTEG_SATA ++#define MV_INCLUDE_SATA ++#endif ++#ifdef CONFIG_MV_INCLUDE_USB ++#define MV_INCLUDE_USB ++#define MV_USB_VOLTAGE_FIX ++#endif ++#ifdef CONFIG_MV_INCLUDE_NAND ++#define MV_INCLUDE_NAND ++#endif ++#ifdef CONFIG_MV_INCLUDE_TDM ++#define MV_INCLUDE_TDM ++#endif ++#ifdef CONFIG_MV_INCLUDE_XOR ++#define MV_INCLUDE_XOR ++#endif ++#ifdef CONFIG_MV_INCLUDE_TWSI ++#define MV_INCLUDE_TWSI ++#endif ++#ifdef CONFIG_MV_INCLUDE_UART ++#define MV_INCLUDE_UART ++#endif ++#ifdef CONFIG_MV_INCLUDE_SPI ++#define MV_INCLUDE_SPI ++#endif ++#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD ++#define MV_INCLUDE_SFLASH_MTD ++#endif ++#ifdef CONFIG_MV_INCLUDE_AUDIO ++#define MV_INCLUDE_AUDIO ++#endif ++#ifdef CONFIG_MV_INCLUDE_TS ++#define MV_INCLUDE_TS ++#endif ++#ifdef CONFIG_MV_INCLUDE_SDIO ++#define MV_INCLUDE_SDIO ++#endif ++ ++ ++/* NAND flash stuff */ ++#ifdef CONFIG_MV_NAND_BOOT ++#define MV_NAND_BOOT ++#endif ++#ifdef CONFIG_MV_NAND ++#define MV_NAND ++#endif ++ ++/* SPI flash stuff */ ++#ifdef CONFIG_MV_SPI_BOOT ++#define MV_SPI_BOOT ++#endif ++ ++ ++/****************************************************************/ ++/************* General configuration ********************/ ++/****************************************************************/ ++ ++/* Enable Clock Power Control */ ++#define MV_INCLUDE_CLK_PWR_CNTRL ++ ++/* Disable the DEVICE BAR in the PEX */ ++#define MV_DISABLE_PEX_DEVICE_BAR ++ ++/* Allow the usage of early printings during initialization */ ++#define MV_INCLUDE_EARLY_PRINTK ++ ++/****************************************************************/ ++/************* NFP configuration ********************************/ ++/****************************************************************/ ++#define MV_NFP_SEC_Q_SIZE 64 ++#define MV_NFP_SEC_REQ_Q_SIZE 1000 ++ ++ ++ ++/****************************************************************/ ++/************* CESA configuration ********************/ ++/****************************************************************/ ++ ++#ifdef MV_INCLUDE_CESA ++ ++#define MV_CESA_MAX_CHAN 4 ++ ++/* Use 2K of SRAM */ ++#define MV_CESA_MAX_BUF_SIZE 1600 ++ ++#endif /* MV_INCLUDE_CESA */ ++ ++#if defined(CONFIG_MV_INCLUDE_GIG_ETH) ++ ++#ifdef CONFIG_MV_NFP_STATS ++#define MV_FP_STATISTICS ++#else ++#undef MV_FP_STATISTICS ++#endif ++/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */ ++#define MV_ETH_SKB_REUSE_DEFAULT 1 ++/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ ++#define MV_ETH_TX_EN_DEFAULT 0 ++ ++/* un-comment if you want to perform tx_done from within the poll function */ ++/* #define ETH_TX_DONE_ISR */ ++ ++/* put descriptors in uncached memory */ ++/* #define ETH_DESCR_UNCACHED */ ++ ++/* Descriptors location: DRAM/internal-SRAM */ ++#define ETH_DESCR_IN_SDRAM ++#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ ++ ++#if defined(ETH_DESCR_IN_SRAM) ++#if defined(ETH_DESCR_UNCACHED) ++ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" ++#else ++ #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" ++#endif ++#elif defined(ETH_DESCR_IN_SDRAM) ++#if defined(ETH_DESCR_UNCACHED) ++ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" ++#else ++ #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" ++#endif ++#else ++ #error "Ethernet descriptors location undefined" ++#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ ++ ++/* SW Sync-Barrier: not relevant for 88fxx81*/ ++/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ ++/* In RX the CPU theoretically might see himself as the descriptor owner, */ ++/* although the buffer hadn't been written to DRAM yet. Performance cost. */ ++/* #define INCLUDE_SYNC_BARR */ ++ ++/* Buffers cache coherency method (buffers in DRAM) */ ++#ifndef MV_CACHE_COHER_SW ++/* Taken from mvCommon.h */ ++/* Memory uncached, HW or SW cache coherency is not needed */ ++#define MV_UNCACHED 0 ++/* Memory cached, HW cache coherency supported in WriteThrough mode */ ++#define MV_CACHE_COHER_HW_WT 1 ++/* Memory cached, HW cache coherency supported in WriteBack mode */ ++#define MV_CACHE_COHER_HW_WB 2 ++/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ ++#define MV_CACHE_COHER_SW 3 ++ ++#endif ++ ++/* DRAM cache coherency configuration */ ++#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW ++ ++ ++#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ ++ ++#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) ++ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" ++#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ++ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" ++#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) ++ #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" ++#elif (ETHER_DRAM_COHER == MV_UNCACHED) ++# define ETH_SDRAM_CONFIG_STR "DRAM uncached" ++#else ++ #error "Ethernet-DRAM undefined" ++#endif /* ETHER_DRAM_COHER */ ++ ++ ++/****************************************************************/ ++/************* Ethernet driver configuration ********************/ ++/****************************************************************/ ++ ++/* port's default queueus */ ++#define ETH_DEF_TXQ 0 ++#define ETH_DEF_RXQ 0 ++ ++#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM ++#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM ++ ++/* interrupt coalescing setting */ ++#define ETH_TX_COAL 200 ++#define ETH_RX_COAL 200 ++ ++/* Checksum offloading */ ++#define TX_CSUM_OFFLOAD ++#define RX_CSUM_OFFLOAD ++ ++#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ ++ ++/****************************************************************/ ++/*************** Telephony configuration ************************/ ++/****************************************************************/ ++#if defined(CONFIG_MV_TDM_LINEAR_MODE) ++ #define MV_TDM_LINEAR_MODE ++#elif defined(CONFIG_MV_TDM_ULAW_MODE) ++ #define MV_TDM_ULAW_MODE ++#endif ++ ++#if defined(CONFIG_MV_TDM_5CHANNELS) ++ #define MV_TDM_5CHANNELS ++#endif ++ ++#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) ++ #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE ++#endif ++ ++/* We use the following registers to store DRAM interface pre configuration */ ++/* auto-detection results */ ++/* IMPORTANT: We are using mask register for that purpose. Before writing */ ++/* to units mask register, make sure main maks register is set to disable */ ++/* all interrupts. */ ++#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ ++#define DRAM_BUF_REG1 0x30820 /* sdram config */ ++#define DRAM_BUF_REG2 0x30830 /* sdram mode */ ++#define DRAM_BUF_REG3 0x308c4 /* dunit control low */ ++#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ ++#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ ++#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ ++#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ ++#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ ++#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ ++#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ ++#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ ++#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */ ++#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */ ++#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */ ++ ++/* Following the pre-configuration registers default values restored after */ ++/* auto-detection is done */ ++#define DRAM_BUF_REG_DV 0 ++ ++/* System Mapping */ ++#define SDRAM_CS0_BASE 0x00000000 ++#define SDRAM_CS0_SIZE _256M ++ ++#define SDRAM_CS1_BASE 0x10000000 ++#define SDRAM_CS1_SIZE _256M ++ ++#define SDRAM_CS2_BASE 0x20000000 ++#define SDRAM_CS2_SIZE _256M ++ ++#define SDRAM_CS3_BASE 0x30000000 ++#define SDRAM_CS3_SIZE _256M ++ ++/* PEX */ ++#define PEX0_MEM_BASE 0xe8000000 ++#define PEX0_MEM_SIZE _128M ++ ++#define PEX0_IO_BASE 0xf2000000 ++#define PEX0_IO_SIZE _1M ++ ++/* Device Chip Selects */ ++#define NFLASH_CS_BASE 0xfa000000 ++#define NFLASH_CS_SIZE _2M ++ ++#define SPI_CS_BASE 0xf4000000 ++#define SPI_CS_SIZE _16M ++ ++#define CRYPT_ENG_BASE 0xf0000000 ++#define CRYPT_ENG_SIZE _2M ++ ++#define BOOTDEV_CS_BASE 0xff800000 ++#define BOOTDEV_CS_SIZE _8M ++ ++/* CS2 - BOOTROM */ ++#define DEVICE_CS2_BASE 0xff900000 ++#define DEVICE_CS2_SIZE _1M ++ ++/* PEX Work arround */ ++/* the target we will use for the workarround */ ++#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM ++/*a flag that indicates if we are going to use the ++size and base of the target we using for the workarround ++window */ ++#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 ++/* if the above flag is 0 then the following values ++will be used for the workarround window base and size, ++otherwise the following defines will be ignored */ ++#define PEX_CONFIG_RW_WA_BASE 0xF3000000 ++#define PEX_CONFIG_RW_WA_SIZE _16M ++ ++/* Internal registers: size is defined in Controllerenvironment */ ++#define INTER_REGS_BASE 0xFEE00000 ++ ++/* DRAM detection stuff */ ++#define MV_DRAM_AUTO_SIZE ++ ++/* Board clock detection */ ++#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ ++#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ ++#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ ++#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */ ++ ++/* PEX-PCI\PCI-PCI Bridge*/ ++#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/ ++ ++ ++ ++#endif /* __INCmvSysHwConfigh */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,376 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvCntmr.h" ++#include "cpu/mvCpu.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++extern unsigned int whoAmI(void); ++ ++/******************************************************************************* ++* mvCntmrLoad - ++* ++* DESCRIPTION: ++* Load an init Value to a given counter/timer ++* ++* INPUT: ++* countNum - counter number ++* value - value to be loaded ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value) ++{ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ mvOsPrintf(("mvCntmrLoad: Err. Illigal counter number \n")); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ MV_REG_WRITE(CNTMR_RELOAD_REG(countNum),value); ++ MV_REG_WRITE(CNTMR_VAL_REG(countNum),value); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrRead - ++* ++* DESCRIPTION: ++* Returns the value of the given Counter/Timer ++* ++* INPUT: ++* countNum - counter number ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 counter value ++*******************************************************************************/ ++MV_U32 mvCntmrRead(MV_U32 countNum) ++{ ++ return MV_REG_READ(CNTMR_VAL_REG(countNum)); ++} ++ ++/******************************************************************************* ++* mvCntmrWrite - ++* ++* DESCRIPTION: ++* Returns the value of the given Counter/Timer ++* ++* INPUT: ++* countNum - counter number ++* countVal - value to write ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None ++*******************************************************************************/ ++void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal) ++{ ++ MV_REG_WRITE(CNTMR_VAL_REG(countNum),countVal); ++} ++ ++/******************************************************************************* ++* mvCntmrCtrlSet - ++* ++* DESCRIPTION: ++* Set the Control to a given counter/timer ++* ++* INPUT: ++* countNum - counter number ++* pCtrl - pointer to MV_CNTMR_CTRL structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ DB(mvOsPrintf(("mvCntmrCtrlSet: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ ++ if (pCtrl->enable) /* enable counter\timer */ ++ { ++ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); ++ } ++ else /* disable counter\timer */ ++ { ++ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); ++ } ++ ++ if ( pCtrl->autoEnable ) /* Auto mode */ ++ { ++ cntmrCtrl |= CTCR_ARM_TIMER_AUTO_EN(countNum); ++ ++ } ++ else /* no auto mode */ ++ { ++ cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(countNum); ++ } ++ ++ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCntmrCtrlGet - ++* ++* DESCRIPTION: ++* Get the Control value of a given counter/timer ++* ++* INPUT: ++* countNum - counter number ++* pCtrl - pointer to MV_CNTMR_CTRL structure ++* ++* OUTPUT: ++* Counter\Timer control value ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ DB(mvOsPrintf(("mvCntmrCtrlGet: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ /* enable counter\timer */ ++ if (cntmrCtrl & CTCR_ARM_TIMER_EN(countNum)) ++ { ++ pCtrl->enable = MV_TRUE; ++ } ++ else ++ { ++ pCtrl->enable = MV_FALSE; ++ } ++ ++ /* counter mode */ ++ if (cntmrCtrl & CTCR_ARM_TIMER_AUTO_EN(countNum)) ++ { ++ pCtrl->autoEnable = MV_TRUE; ++ } ++ else ++ { ++ pCtrl->autoEnable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrEnable - ++* ++* DESCRIPTION: ++* Set the Enable-Bit to logic '1' ==> starting the counter ++* ++* INPUT: ++* countNum - counter number ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrEnable(MV_U32 countNum) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ DB(mvOsPrintf(("mvCntmrEnable: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ /* enable counter\timer */ ++ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); ++ ++ ++ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrDisable - ++* ++* DESCRIPTION: ++* Stop the counter/timer running, and returns its Value ++* ++* INPUT: ++* countNum - counter number ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 counter\timer value ++*******************************************************************************/ ++MV_STATUS mvCntmrDisable(MV_U32 countNum) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ DB(mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ /* disable counter\timer */ ++ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); ++ ++ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrStart - ++* ++* DESCRIPTION: ++* Combined all the sub-operations above to one function: Load,setMode,Enable ++* ++* INPUT: ++* countNum - counter number ++* value - value of the counter\timer to be set ++* pCtrl - pointer to MV_CNTMR_CTRL structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, ++ MV_CNTMR_CTRL *pCtrl) ++{ ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n")); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* load value onto counter\timer */ ++ mvCntmrLoad(countNum,value); ++ ++ /* set the counter to load in the first time */ ++ mvCntmrWrite(countNum,value); ++ ++ /* set control for timer \ cunter and enable */ ++ mvCntmrCtrlSet(countNum,pCtrl); ++ ++ return MV_OK; ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,121 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvTmrWtdgh ++#define __INCmvTmrWtdgh ++ ++/* includes */ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "cntmr/mvCntmrRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++ ++/* This enumerator describe counters\watchdog numbers */ ++typedef enum _mvCntmrID ++{ ++ TIMER0 = 0, ++ TIMER1, ++ WATCHDOG, ++ TIMER2, ++ TIMER3, ++}MV_CNTMR_ID; ++ ++ ++/* Counter / Timer control structure */ ++typedef struct _mvCntmrCtrl ++{ ++ MV_BOOL enable; /* enable */ ++ MV_BOOL autoEnable; /* counter/Timer */ ++}MV_CNTMR_CTRL; ++ ++ ++/* Functions */ ++ ++/* Load an init Value to a given counter/timer */ ++MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value); ++ ++/* Returns the value of the given Counter/Timer */ ++MV_U32 mvCntmrRead(MV_U32 countNum); ++ ++/* Write a value of the given Counter/Timer */ ++void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal); ++ ++/* Set the Control to a given counter/timer */ ++MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); ++ ++/* Get the value of a given counter/timer */ ++MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); ++ ++/* Set the Enable-Bit to logic '1' ==> starting the counter. */ ++MV_STATUS mvCntmrEnable(MV_U32 countNum); ++ ++/* Stop the counter/timer running, and returns its Value. */ ++MV_STATUS mvCntmrDisable(MV_U32 countNum); ++ ++/* Combined all the sub-operations above to one function: Load,setMode,Enable */ ++MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, ++ MV_CNTMR_CTRL *pCtrl); ++ ++#endif /* __INCmvTmrWtdgh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,121 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvTmrwtdgRegsh ++#define __INCmvTmrwtdgRegsh ++ ++/*******************************************/ ++/* ARM Timers Registers Map */ ++/*******************************************/ ++ ++#define CNTMR_RELOAD_REG(tmrNum) (CNTMR_BASE + 0x10 + (tmrNum)*8 + \ ++ (((tmrNum) <= 3)?0:8)) ++#define CNTMR_VAL_REG(tmrNum) (CNTMR_BASE + 0x14 + (tmrNum)*8 + \ ++ (((tmrNum) <= 3)?0:8)) ++#define CNTMR_CTRL_REG (CNTMR_BASE) ++ ++/*For MV78XX0*/ ++#define CNTMR_CAUSE_REG (CPU_AHB_MBUS_CAUSE_INT_REG(whoAmI())) ++#define CNTMR_MASK_REG (CPU_AHB_MBUS_MASK_INT_REG(whoAmI())) ++ ++/* ARM Timers Registers Map */ ++/*******************************************/ ++ ++ ++/* ARM Timers Control Register */ ++/* CPU_TIMERS_CTRL_REG (CTCR) */ ++ ++#define TIMER0_NUM 0 ++#define TIMER1_NUM 1 ++#define WATCHDOG_NUM 2 ++#define TIMER2_NUM 3 ++#define TIMER3_NUM 4 ++ ++#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) ++#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) ++#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) ++#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) ++ ++#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) ++#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1 ++#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) ++#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) ++ ++ ++/* ARM Timer\Watchdog Reload Register */ ++/* CNTMR_RELOAD_REG (TRR) */ ++ ++#define TRG_ARM_TIMER_REL_OFFS 0 ++#define TRG_ARM_TIMER_REL_MASK 0xffffffff ++ ++/* ARM Timer\Watchdog Register */ ++/* CNTMR_VAL_REG (TVRG) */ ++ ++#define TVR_ARM_TIMER_OFFS 0 ++#define TVR_ARM_TIMER_MASK 0xffffffff ++#define TVR_ARM_TIMER_MAX 0xffffffff ++ ++ ++ ++#endif /* __INCmvTmrwtdgRegsh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,207 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include "mvOs.h" ++#include "mvCpuCntrs.h" ++ ++ ++const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] = ++{ ++ /*0*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS, ++ MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY, ++ MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, ++ }, ++ /*1*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS, ++ MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, ++ }, ++ /*2*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS, ++ MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, ++ }, ++ /*3*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS, ++ MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS, ++ MV_CPU_CNTRS_INVALID, ++ } ++}; ++ ++MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; ++ ++MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128]; ++ ++void mvCpuCntrsReset(void) ++{ ++ MV_U32 reg = 0; ++ ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg)); ++} ++ ++void program_counter(int counter, int op) ++{ ++ MV_U32 reg = (1 << op) | 0x1; /*enable*/ ++ ++ switch(counter) ++ { ++ case 0: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg)); ++ return; ++ ++ case 1: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg)); ++ return; ++ ++ case 2: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg)); ++ return; ++ ++ case 3: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg)); ++ return; ++ ++ default: ++ mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); ++ } ++ return; ++} ++ ++void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++ for(i=0; icounters_sum[i] = 0; ++ } ++ pEvent->num_of_measurements = 0; ++} ++ ++ ++MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold) ++{ ++ int i; ++ MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT)); ++ ++ if(event) ++ { ++ strncpy(event->name, name, sizeof(event->name)); ++ event->num_of_measurements = 0; ++ event->avg_sample_count = print_threshold; ++ for(i=0; icounters_before[i] = 0; ++ event->counters_after[i] = 0; ++ event->counters_sum[i] = 0; ++ } ++ } ++ return event; ++} ++ ++void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event) ++{ ++ if(event != NULL) ++ mvOsFree(event); ++} ++ ++ ++MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, ++ char* name, MV_U32 overhead) ++{ ++ int i; ++ ++ /* Find required operations */ ++ for(i=0; inum_of_measurements < pEvent->avg_sample_count) ++ return; ++ ++ mvOsPrintf("%16s: ", pEvent->name); ++ for(i=0; icounters_sum[i], ++ pEvent->num_of_measurements, NULL); ++ if(counters_avg >= mvCpuCntrsTbl[i].overhead) ++ counters_avg -= mvCpuCntrsTbl[i].overhead; ++ else ++ counters_avg = 0; ++ ++ mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg); ++ } ++ mvOsPrintf("\n"); ++ mvCpuCntrsEventClear(pEvent); ++ mvCpuCntrsReset(); ++} ++ ++void mvCpuCntrsStatus(void) ++{ ++ int i; ++ ++ for(i=0; icounters_before[i] = mvCpuCntrsRead(i); ++#else ++ pEvent->counters_before[1] = mvCpuCntrsRead(1); ++ pEvent->counters_before[3] = mvCpuCntrsRead(3); ++ pEvent->counters_before[0] = mvCpuCntrsRead(0); ++ pEvent->counters_before[2] = mvCpuCntrsRead(2); ++#endif ++} ++ ++static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++#if 0 ++ /* order is important - we want to measure the cycle count first here! */ ++ for(i=0; icounters_after[i] = mvCpuCntrsRead(i); ++#else ++ pEvent->counters_after[2] = mvCpuCntrsRead(2); ++ pEvent->counters_after[0] = mvCpuCntrsRead(0); ++ pEvent->counters_after[3] = mvCpuCntrsRead(3); ++ pEvent->counters_after[1] = mvCpuCntrsRead(1); ++#endif ++ ++ for(i=0; icounters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); ++ } ++ pEvent->num_of_measurements++; ++} ++ ++ ++#ifdef CONFIG_MV_CPU_PERF_CNTRS ++ ++#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter) ++ ++#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event) ++ ++#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event) ++ ++#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event) ++ ++#else ++ ++#define MV_CPU_CNTRS_READ(counter) ++#define MV_CPU_CNTRS_START(event) ++#define MV_CPU_CNTRS_STOP(event) ++#define MV_CPU_CNTRS_SHOW(event) ++ ++#endif /* CONFIG_MV_CPU_PERF_CNTRS */ ++ ++ ++#endif /* __mvCpuCntrs_h__ */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,143 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include "mvOs.h" ++#include "mvCpuL2Cntrs.h" ++ ++ ++ ++MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM]; ++ ++MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128]; ++ ++void mvCpuL2CntrsReset(void) ++{ ++ MV_U32 reg = 0; ++ ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg)); ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg)); ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg)); ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg)); ++} ++ ++static void mvCpuL2CntrConfig(int counter, int op) ++{ ++ MV_U32 reg = (1 << op) | 0x1; /*enable*/ ++ ++ switch(counter) ++ { ++ case 0: ++ MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg)); ++ return; ++ ++ case 1: ++ MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg)); ++ return; ++ ++ default: ++ mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter); ++ } ++ return; ++} ++ ++void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++ for(i=0; icounters_sum[i] = 0; ++ } ++ pEvent->num_of_measurements = 0; ++} ++ ++ ++MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold) ++{ ++ int i; ++ MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT)); ++ ++ if(event) ++ { ++ strncpy(event->name, name, sizeof(event->name)); ++ event->num_of_measurements = 0; ++ event->avg_sample_count = print_threshold; ++ for(i=0; icounters_before[i] = 0; ++ event->counters_after[i] = 0; ++ event->counters_sum[i] = 0; ++ } ++ } ++ return event; ++} ++ ++void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event) ++{ ++ if(event != NULL) ++ mvOsFree(event); ++} ++ ++ ++MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, ++ char* name, MV_U32 overhead) ++{ ++ strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name)); ++ mvCpuL2CntrsTbl[counter].operation = op; ++ mvCpuL2CntrsTbl[counter].opIdx = op; ++ mvCpuL2CntrsTbl[counter].overhead = overhead; ++ mvCpuL2CntrConfig(counter, op); ++ mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n", ++ counter, op, overhead); ++ return MV_OK; ++} ++ ++void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ MV_U64 counters_avg; ++ ++ if(pEvent->num_of_measurements < pEvent->avg_sample_count) ++ return; ++ ++ mvOsPrintf("%16s: ", pEvent->name); ++ for(i=0; icounters_sum[i], ++ pEvent->num_of_measurements, NULL); ++ ++ if(counters_avg >= mvCpuL2CntrsTbl[i].overhead) ++ counters_avg -= mvCpuL2CntrsTbl[i].overhead; ++ else ++ counters_avg = 0; ++ ++ mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg); ++ } ++ mvOsPrintf("\n"); ++ mvCpuL2CntrsEventClear(pEvent); ++ mvCpuL2CntrsReset(); ++} ++ ++void mvCpuL2CntrsStatus(void) ++{ ++ int i; ++ ++ for(i=0; icounters_before[i] = mvCpuL2CntrsRead(i); ++} ++ ++static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++ for(i=0; icounters_after[i] = mvCpuL2CntrsRead(i); ++ pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); ++ } ++ pEvent->num_of_measurements++; ++} ++ ++ ++#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS ++ ++#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter) ++ ++#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event) ++ ++#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event) ++ ++#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event) ++ ++#else ++ ++#define MV_CPU_L2_CNTRS_READ(counter) ++#define MV_CPU_L2_CNTRS_START(event) ++#define MV_CPU_L2_CNTRS_STOP(event) ++#define MV_CPU_L2_CNTRS_SHOW(event) ++ ++#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */ ++ ++ ++#endif /* __mvCpuL2Cntrs_h__ */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,1479 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "ddr1_2/mvDram.h" ++#include "boardEnv/mvBoardEnvLib.h" ++ ++#undef MV_DEBUG ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, ++ MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 cas2ps(MV_U8 spd_byte); ++/******************************************************************************* ++* mvDramBankGet - Get the DRAM bank paramters. ++* ++* DESCRIPTION: ++* This function retrieves DRAM bank parameters as described in ++* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board ++* has its DRAM on DIMMs it will use its EEPROM to extract SPD data ++* from it. Otherwise, if the DRAM is soldered on board, the function ++* should insert its bank information into MV_DRAM_BANK_INFO struct. ++* ++* INPUT: ++* bankNum - Board DRAM bank number. ++* ++* OUTPUT: ++* pBankInfo - DRAM bank information struct. ++* ++* RETURN: ++* MV_FAIL - Bank parameters could not be read. ++* ++*******************************************************************************/ ++MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_DIMM_INFO dimmInfo; ++ ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); ++ /* zero pBankInfo structure */ ++ memset(pBankInfo, 0, sizeof(*pBankInfo)); ++ ++ if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); ++ return MV_FAIL; ++ } ++ if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); ++ return MV_FAIL; ++ } ++ ++ /* convert Dimm info to Bank info */ ++ cpyDimm2BankInfo(&dimmInfo, pBankInfo); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. ++* ++* DESCRIPTION: ++* Convert a Dimm info struct into a bank info struct. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* pBankInfo - DRAM bank information struct. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, ++ MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ pBankInfo->memoryType = pDimmInfo->memoryType; ++ ++ /* DIMM dimensions */ ++ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; ++ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; ++ pBankInfo->dataWidth = pDimmInfo->dataWidth; ++ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; ++ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; ++ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; ++ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; ++ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; ++ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; ++ ++ /* DIMM timing parameters */ ++ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; ++ ++ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; ++ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; ++ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; ++ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; ++ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; ++ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; ++ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; ++ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; ++ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; ++ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / ++ pDimmInfo->numOfModuleBanks; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ ++ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || ++ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) ++ { ++ if (pDimmInfo->dimmAttributes & BIT1) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ ++ { ++ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ ++ return; ++} ++ ++/******************************************************************************* ++* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdCpy(MV_VOID) ++{ ++ MV_U32 i; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, ++ &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the DIMM 1 SPD */ ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ twsiSlave.offset = i; ++ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, ++ &twsiSlave, &data[i], 1) ) ++ { ++ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); ++ return MV_FAIL; ++ } ++ mvOsDelay(5); ++ } ++ ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdGet - Get the SPD parameters. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters into given struct parameter. ++* ++* INPUT: ++* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. ++* ++* OUTPUT: ++* pDimmInfo - DIMM information structure. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) ++{ ++ MV_U32 i; ++ MV_U32 density = 1; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = (dimmNum == 0) ? ++ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, ++ &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the dimmInfo structure*/ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ pDimmInfo->spdRawData[i] = data[i]; ++ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); ++ } ++ ++ DB(mvOsPrintf("DRAM SPD Information:\n")); ++ ++ /* Memory type (DDR / SDRAM) */ ++ switch (data[DIMM_MEM_TYPE]) ++ { ++ case (DIMM_MEM_TYPE_SDRAM): ++ pDimmInfo->memoryType = MEM_TYPE_SDRAM; ++ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR1): ++ pDimmInfo->memoryType = MEM_TYPE_DDR1; ++ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR2): ++ pDimmInfo->memoryType = MEM_TYPE_DDR2; ++ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); ++ break; ++ default: ++ mvOsPrintf("ERROR: Undefined memory type!\n"); ++ return MV_ERROR; ++ } ++ ++ ++ /* Number Of Row Addresses */ ++ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; ++ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); ++ ++ /* Number Of Column Addresses */ ++ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; ++ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); ++ ++ /* Number Of Module Banks */ ++ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", ++ pDimmInfo->numOfModuleBanks)); ++ ++ /* Number of module banks encoded differently for DDR2 */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; ++ ++ /* Data Width */ ++ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); ++ ++ /* Minimum Cycle Time At Max CasLatancy */ ++ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); ++ ++ /* Error Check Type */ ++ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; ++ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", ++ pDimmInfo->errorCheckType)); ++ ++ /* Refresh Interval */ ++ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; ++ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", ++ pDimmInfo->refreshInterval)); ++ ++ /* Sdram Width */ ++ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; ++ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); ++ ++ /* Error Check Data Width */ ++ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", ++ pDimmInfo->errorCheckDataWidth)); ++ ++ /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; ++ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", ++ pDimmInfo->burstLengthSupported)); ++ ++ /* Number Of Banks On Each Device */ ++ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", ++ pDimmInfo->numOfBanksOnEachDevice)); ++ ++ /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; ++ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", ++ pDimmInfo->suportedCasLatencies)); ++ ++ /* For DDR2 only, get the DIMM type information */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ { ++ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; ++ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", ++ pDimmInfo->dimmTypeInfo)); ++ } ++ ++ /* SDRAM Modules Attributes */ ++ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; ++ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", ++ pDimmInfo->dimmAttributes)); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); ++ ++ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; ++ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", ++ pDimmInfo->minRowPrechargeTime)); ++ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; ++ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", ++ pDimmInfo->minRowActiveToRowActive)); ++ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; ++ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", ++ pDimmInfo->minRasToCasDelay)); ++ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; ++ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", ++ pDimmInfo->minRasPulseWidth)); ++ ++ /* DIMM Bank Density */ ++ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; ++ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", ++ pDimmInfo->dimmBankDensity)); ++ ++ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ ++ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; ++ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", ++ pDimmInfo->minWriteRecoveryTime)); ++ ++ /* Only DDR2 includes Internal Write To Read Command Delay field. */ ++ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", ++ pDimmInfo->minWriteToReadCmdDelay)); ++ ++ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ ++ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", ++ pDimmInfo->minReadToPrechCmdDelay)); ++ ++ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ ++ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; ++ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", ++ pDimmInfo->minRefreshToActiveCmd)); ++ ++ /* calculating the sdram density. Representing device density from */ ++ /* bit 20 to allow representation of 4GB and above. */ ++ /* For example, if density is 512Mbit 0x20000000, will be represent in */ ++ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ ++ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ ++ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); ++ pDimmInfo->deviceDensity = density * ++ pDimmInfo->numOfBanksOnEachDevice * ++ pDimmInfo->sdramWidth; ++ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); ++ ++ /* Number of devices includeing Error correction */ ++ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * ++ pDimmInfo->numOfModuleBanks; ++ DB(mvOsPrintf("DRAM numberOfDevices %d\n", ++ pDimmInfo->numberOfDevices)); ++ ++ pDimmInfo->size = 0; ++ ++ /* Note that pDimmInfo->size is in MB units */ ++ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 8; /* Equal to 8MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 4096; /* Equal to 4GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 8192; /* Equal to 8GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 16384; /* Equal to 16GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ ++ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; ++ ++ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdPrint - Print the SPD parameters. ++* ++* DESCRIPTION: ++* Print the Dimm SPD parameters. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID dimmSpdPrint(MV_U32 dimmNum) ++{ ++ MV_DIMM_INFO dimmInfo; ++ MV_U32 i, temp = 0; ++ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; ++ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; ++ MV_U32 busClkPs; ++ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, ++ temp_buf[40], *spdRawData; ++ ++ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ ++ ++ spdRawData = dimmInfo.spdRawData; ++ ++ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) ++ { ++ mvOsOutput("ERROR: Could not read SPD information!\n"); ++ return; ++ } ++ ++ /* find Manufactura of Dimm Module */ ++ mvOsOutput("\nManufacturer's JEDEC ID Code: "); ++ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) ++ { ++ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); ++ } ++ mvOsOutput("\n"); ++ ++ /* Manufacturer's Specific Data */ ++ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; ++ } ++ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); ++ ++ /* Module Part Number */ ++ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; ++ } ++ mvOsOutput("Module Part Number: %s\n", temp_buf); ++ ++ /* Module Serial Number */ ++ for(i = 0; i < sizeof(MV_U32); i++) ++ { ++ temp |= spdRawData[95+i] << 8*i; ++ } ++ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, ++ (long)temp); ++ ++ /* find Manufac-Data of Dimm Module */ ++ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", ++ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), ++ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); ++ /* find modul_revision of Dimm Module */ ++ mvOsOutput("Module Revision: %d.%d\n", ++ spdRawData[91], spdRawData[92]); ++ ++ /* find manufac_place of Dimm Module */ ++ mvOsOutput("manufac_place: %d\n", spdRawData[72]); ++ ++ /* go over the first 35 I2C data bytes */ ++ for(i = 2 ; i <= 35 ; i++) ++ switch(i) ++ { ++ case 2: /* Memory type (DDR1/2 / SDRAM) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ mvOsOutput("Dram Type is: SDRAM\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ mvOsOutput("Dram Type is: SDRAM DDR1\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ mvOsOutput("Dram Type is: SDRAM DDR2\n"); ++ else ++ mvOsOutput("Dram Type unknown\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 3: /* Number Of Row Addresses */ ++ mvOsOutput("Module Number of row addresses: %d\n", ++ dimmInfo.numOfRowAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 4: /* Number Of Column Addresses */ ++ mvOsOutput("Module Number of col addresses: %d\n", ++ dimmInfo.numOfColAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 5: /* Number Of Module Banks */ ++ mvOsOutput("Number of Banks on Mod.: %d\n", ++ dimmInfo.numOfModuleBanks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 6: /* Data Width */ ++ mvOsOutput("Module Data Width: %d bit\n", ++ dimmInfo.dataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 8: /* Voltage Interface */ ++ switch(spdRawData[i]) ++ { ++ case 0x0: ++ mvOsOutput("Module is TTL_5V_TOLERANT\n"); ++ break; ++ case 0x1: ++ mvOsOutput("Module is LVTTL\n"); ++ break; ++ case 0x2: ++ mvOsOutput("Module is HSTL_1_5V\n"); ++ break; ++ case 0x3: ++ mvOsOutput("Module is SSTL_3_3V\n"); ++ break; ++ case 0x4: ++ mvOsOutput("Module is SSTL_2_5V\n"); ++ break; ++ case 0x5: ++ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) ++ { ++ mvOsOutput("Module is SSTL_1_8V\n"); ++ break; ++ } ++ default: ++ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); ++ break; ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 9: /* Minimum Cycle Time At Max CasLatancy */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 10: /* Clock To Data Out */ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 11: /* Error Check Type */ ++ mvOsOutput("Error Check Type (0=NONE): %d\n", ++ dimmInfo.errorCheckType); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 12: /* Refresh Interval */ ++ mvOsOutput("Refresh Rate: %x\n", ++ dimmInfo.refreshInterval); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 13: /* Sdram Width */ ++ mvOsOutput("Sdram Width: %d bits\n", ++ dimmInfo.sdramWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 14: /* Error Check Data Width */ ++ mvOsOutput("Error Check Data Width: %d bits\n", ++ dimmInfo.errorCheckDataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 15: /* Minimum Clock Delay is unsupported */ ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ mvOsOutput("Minimum Clk Delay back to back: %d\n", ++ spdRawData[i]); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 16: /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ mvOsOutput("Burst Length Supported: "); ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ if (dimmInfo.burstLengthSupported & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.burstLengthSupported & BIT1) ++ mvOsOutput("2, "); ++ } ++ if (dimmInfo.burstLengthSupported & BIT2) ++ mvOsOutput("4, "); ++ if (dimmInfo.burstLengthSupported & BIT3) ++ mvOsOutput("8, "); ++ ++ mvOsOutput(" Bit \n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 17: /* Number Of Banks On Each Device */ ++ mvOsOutput("Number Of Banks On Each Chip: %d\n", ++ dimmInfo.numOfBanksOnEachDevice); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 18: /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ mvOsOutput("Suported Cas Latencies: (CL) "); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ for (k = 0; k <=7; k++) ++ { ++ if (dimmInfo.suportedCasLatencies & (1 << k)) ++ mvOsOutput("%d, ", k+1); ++ } ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.suportedCasLatencies & BIT1) ++ mvOsOutput("1.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("2.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("3.5, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("4, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("5, "); ++ } ++ else ++ mvOsOutput("?.?, "); ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 20: /* DDR2 DIMM type info */ ++ if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) ++ mvOsOutput("Registered DIMM (RDIMM)\n"); ++ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) ++ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); ++ else ++ mvOsOutput("Unknown DIMM type.\n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 21: /* SDRAM Modules Attributes */ ++ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" Bufferd DQMB Input: Yes \n"); ++ else ++ mvOsOutput(" Bufferd DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" Registered DQMB Inputs: Yes \n"); ++ else ++ mvOsOutput(" Registered DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" redundant Row Addressing: Yes \n"); ++ else ++ mvOsOutput(" redundant Row Addressing: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch On-Card Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", ++ (dimmInfo.dimmAttributes & 0x3) + 1); ++ ++ mvOsOutput(" Number of PLLs on the DIMM: %d\n", ++ ((dimmInfo.dimmAttributes) >> 2) & 0x3); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" Analysis probe installed: Yes \n"); ++ else ++ mvOsOutput(" Analysis probe installed: No \n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 22: /* Suported AutoPreCharge */ ++ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Early Ras Precharge: Yes \n"); ++ else ++ mvOsOutput(" Early Ras Precharge: No \n"); ++ ++ if ( spdRawData[i] & BIT1 ) ++ mvOsOutput(" AutoPreCharge: Yes \n"); ++ else ++ mvOsOutput(" AutoPreCharge: No \n"); ++ ++ if ( spdRawData[i] & BIT2 ) ++ mvOsOutput(" Precharge All: Yes \n"); ++ else ++ mvOsOutput(" Precharge All: No \n"); ++ ++ if ( spdRawData[i] & BIT3 ) ++ mvOsOutput(" Write 1/ReadBurst: Yes \n"); ++ else ++ mvOsOutput(" Write 1/ReadBurst: No \n"); ++ ++ if ( spdRawData[i] & BIT4 ) ++ mvOsOutput(" lower VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" lower VCC tolerance: 10%%\n"); ++ ++ if ( spdRawData[i] & BIT5 ) ++ mvOsOutput(" upper VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" upper VCC tolerance: 10%%\n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ ++ if ( !(spdRawData[i] & BIT4) ) ++ mvOsOutput(" lower VCC tolerance: 0.2V\n"); ++ ++ if ( !(spdRawData[i] & BIT5) ) ++ mvOsOutput(" upper VCC tolerance: 0.2V\n"); ++ ++ if ( spdRawData[i] & BIT6 ) ++ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); ++ else ++ mvOsOutput(" Concurrent Auto Preharge: No \n"); ++ ++ if ( spdRawData[i] & BIT7 ) ++ mvOsOutput(" Supports Fast AP: Yes \n"); ++ else ++ mvOsOutput(" Supports Fast AP: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 23: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ ++ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 25: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ } ++ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = 0; ++ rightOfPoint = time_tmp; ++ } ++ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 27: /* Minimum Row Precharge Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ ++ trp_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 28: /* Minimum Row Active to Row Active Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " ++ "%d.%d = in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 29: /* Minimum Ras-To-Cas Delay */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; ++ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 30: /* Minimum Ras Pulse Width */ ++ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " ++ "in Clk cycles %d\n", spdRawData[i], tras_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 31: /* Module Bank Density */ ++ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("8MB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("4GB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("8GB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("16GB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 32: /* Address And Command Setup Time (measured in ns/1000) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 33: /* Address And Command Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 34: /* Data Input Setup Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 35: /* Data Input Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 36: /* Relevant for DDR2 only: Write Recovery Time */ ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; ++ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ } ++ ++} ++ ++ ++/* ++ * translate ns.ns/10 coding of SPD timing values ++ * into ps unit values ++ */ ++/******************************************************************************* ++* cas2ps - Translate x.y ns parameter to pico-seconds values ++* ++* DESCRIPTION: ++* This function translates x.y nano seconds to its value in pico seconds. ++* For example 3.75ns will return 3750. ++* ++* INPUT: ++* spd_byte - DIMM SPD byte. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* value in pico seconds. ++* ++*******************************************************************************/ ++static MV_U32 cas2ps(MV_U8 spd_byte) ++{ ++ MV_U32 ns, ns10; ++ ++ /* isolate upper nibble */ ++ ns = (spd_byte >> 4) & 0x0F; ++ /* isolate lower nibble */ ++ ns10 = (spd_byte & 0x0F); ++ ++ if( ns10 < 10 ) { ++ ns10 *= 10; ++ } ++ else if( ns10 == 10 ) ++ ns10 = 25; ++ else if( ns10 == 11 ) ++ ns10 = 33; ++ else if( ns10 == 12 ) ++ ns10 = 66; ++ else if( ns10 == 13 ) ++ ns10 = 75; ++ else ++ { ++ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); ++ } ++ ++ return (ns*1000 + ns10*10); ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,191 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDram ++#define __INCmvDram ++ ++#include "ddr1_2/mvDramIf.h" ++#include "twsi/mvTwsi.h" ++ ++#define MAX_DIMM_NUM 2 ++#define SPD_SIZE 128 ++ ++/* Dimm spd offsets */ ++#define DIMM_MEM_TYPE 2 ++#define DIMM_ROW_NUM 3 ++#define DIMM_COL_NUM 4 ++#define DIMM_MODULE_BANK_NUM 5 ++#define DIMM_DATA_WIDTH 6 ++#define DIMM_VOLT_IF 8 ++#define DIMM_MIN_CC_AT_MAX_CAS 9 ++#define DIMM_ERR_CHECK_TYPE 11 ++#define DIMM_REFRESH_INTERVAL 12 ++#define DIMM_SDRAM_WIDTH 13 ++#define DIMM_ERR_CHECK_DATA_WIDTH 14 ++#define DIMM_MIN_CLK_DEL 15 ++#define DIMM_BURST_LEN_SUP 16 ++#define DIMM_DEV_BANK_NUM 17 ++#define DIMM_SUP_CAL 18 ++#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ ++#define DIMM_BUF_ADDR_CONT_IN 21 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 ++#define DIMM_MIN_ROW_PRECHARGE_TIME 27 ++#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 ++#define DIMM_MIN_RAS_TO_CAS_DELAY 29 ++#define DIMM_MIN_RAS_PULSE_WIDTH 30 ++#define DIMM_BANK_DENSITY 31 ++#define DIMM_MIN_WRITE_RECOVERY_TIME 36 ++#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 ++#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 ++#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 ++ ++/* Dimm Memory Type values */ ++#define DIMM_MEM_TYPE_SDRAM 0x4 ++#define DIMM_MEM_TYPE_DDR1 0x7 ++#define DIMM_MEM_TYPE_DDR2 0x8 ++ ++#define DIMM_MODULE_MANU_OFFS 64 ++#define DIMM_MODULE_MANU_SIZE 8 ++#define DIMM_MODULE_VEN_OFFS 73 ++#define DIMM_MODULE_VEN_SIZE 25 ++#define DIMM_MODULE_ID_OFFS 99 ++#define DIMM_MODULE_ID_SIZE 18 ++ ++/* enumeration for voltage levels. */ ++typedef enum _mvDimmVoltageIf ++{ ++ TTL_5V_TOLERANT, ++ LVTTL, ++ HSTL_1_5V, ++ SSTL_3_3V, ++ SSTL_2_5V, ++ VOLTAGE_UNKNOWN, ++} MV_DIMM_VOLTAGE_IF; ++ ++ ++/* enumaration for SDRAM CAS Latencies. */ ++typedef enum _mvDimmSdramCas ++{ ++ SD_CL_1 =1, ++ SD_CL_2, ++ SD_CL_3, ++ SD_CL_4, ++ SD_CL_5, ++ SD_CL_6, ++ SD_CL_7, ++ SD_FAULT ++}MV_DIMM_SDRAM_CAS; ++ ++ ++/* DIMM information structure */ ++typedef struct _mvDimmInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ ++ ++ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 numOfModuleBanks; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ MV_U32 dimmBankDensity; ++ MV_U32 dimmTypeInfo; /* DDR2 only */ ++ MV_U32 dimmAttributes; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ ++ MV_U32 numberOfDevices; ++ ++} MV_DIMM_INFO; ++ ++ ++MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); ++MV_VOID dimmSpdPrint(MV_U32 dimmNum); ++MV_STATUS dimmSpdCpy(MV_VOID); ++ ++#endif /* __INCmvDram */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,1599 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "ddr1_2/mvDramIf.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++ ++ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++/* DRAM bank presence encoding */ ++#define BANK_PRESENT_CS0 0x1 ++#define BANK_PRESENT_CS0_CS1 0x3 ++#define BANK_PRESENT_CS0_CS2 0x5 ++#define BANK_PRESENT_CS0_CS1_CS2 0x7 ++#define BANK_PRESENT_CS0_CS2_CS3 0xd ++#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf ++ ++/* locals */ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); ++#if defined(MV_INC_BOARD_DDIM) ++static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas); ++static MV_U32 sdramModeRegCalc(MV_U32 minCas); ++static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); ++static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, ++ MV_U32 forcedCl); ++static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 minCas, MV_U32 busClk); ++static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 busClk); ++ ++/******************************************************************************* ++* mvDramIfDetect - Prepare DRAM interface configuration values. ++* ++* DESCRIPTION: ++* This function implements the full DRAM detection and timing ++* configuration for best system performance. ++* Since this routine runs from a ROM device (Boot Flash), its stack ++* resides on RAM, that might be the system DRAM. Changing DRAM ++* configuration values while keeping vital data in DRAM is risky. That ++* is why the function does not preform the configuration setting but ++* prepare those in predefined 32bit registers (in this case IDMA ++* registers are used) for other routine to perform the settings. ++* The function will call for board DRAM SPD information for each DRAM ++* chip select. The function will then analyze those SPD parameters of ++* all DRAM banks in order to decide on DRAM configuration compatible ++* for all DRAM banks. ++* The function will set the CPU DRAM address decode registers. ++* Note: This routine prepares values that will overide configuration of ++* mvDramBasicAsmInit(). ++* ++* INPUT: ++* forcedCl - Forced CAL Latency. If equal to zero, do not force. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfDetect(MV_U32 forcedCl) ++{ ++ MV_U32 retVal = MV_OK; /* return value */ ++ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; ++ MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW; ++ MV_U8 minCas; ++ MV_DRAM_DEC_WIN dramDecWin; ++ ++ dramDecWin.addrWin.baseHigh = 0; ++ ++ busClk = mvBoardSysClkGet(); ++ ++ if (0 == busClk) ++ { ++ mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); ++ return MV_ERROR; ++ } ++ ++ /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */ ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++) ++ mvCpuIfTargetWinEnable(i, MV_FALSE); ++#endif ++ ++ /* we will use bank 0 as the representative of the all the DRAM banks, */ ++ /* since bank 0 must exist. */ ++ for(i = 0; i < MV_DRAM_MAX_CS; i++) ++ { ++ /* if Bank exist */ ++ if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) ++ { ++ /* check it isn't SDRAM */ ++ if(bankInfo[i].memoryType == MEM_TYPE_SDRAM) ++ { ++ mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n"); ++ return MV_ERROR; ++ } ++ /* All banks must support registry in order to activate it */ ++ if(bankInfo[i].registeredAddrAndControlInputs != ++ bankInfo[0].registeredAddrAndControlInputs) ++ { ++ mvOsPrintf("Dram: ERR. different Registered settings !!!\n"); ++ return MV_ERROR; ++ } ++ ++ /* Init the CPU window decode */ ++ /* Note that the size in Bank info is in MB units */ ++ /* Note that the Dimm width might be different then the device DRAM width */ ++ temp = MV_REG_READ(SDRAM_CONFIG_REG); ++ ++ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32; ++ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); ++ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); ++ ++ /* We can not change DRAM window settings while excecuting */ ++ /* code from it. That is why we skip the DRAM CS[0], saving */ ++ /* it to the ROM configuration routine */ ++ if(i == SDRAM_CS0) ++ { ++ MV_U32 sizeToReg; ++ ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" ++ ,i); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Size is located at upper 16 bits */ ++ sizeToReg <<= SCSR_SIZE_OFFS; ++ ++ /* enable it */ ++ sizeToReg |= SCSR_WIN_EN; ++ ++ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); ++ } ++ else ++ { ++ dramDecWin.addrWin.baseLow = base; ++ dramDecWin.addrWin.size = size; ++ dramDecWin.enable = MV_TRUE; ++ ++ if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin)) ++ { ++ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", ++ SDRAM_CS0 + i); ++ return MV_ERROR; ++ } ++ } ++ ++ base += size; ++ ++ /* update the suportedCasLatencies mask */ ++ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; ++ ++ } ++ else ++ { ++ if( i == 0 ) /* bank 0 doesn't exist */ ++ { ++ mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n"); ++ return MV_ERROR; ++ } ++ else ++ { ++ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); ++ bankInfo[i].size = 0; /* Mark this bank as non exist */ ++ } ++ } ++ } ++ ++ /* calculate minimum CAS */ ++ minCas = minCasCalc(&bankInfo[0], busClk, forcedCl); ++ if (0 == minCas) ++ { ++ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", ++ (busClk / 1000000)); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ minCas = DDR2_CL_4; /* Continue with this CAS */ ++ mvOsPrintf("Set default CAS latency 4\n"); ++ } ++ else ++ { ++ minCas = DDR1_CL_3; /* Continue with this CAS */ ++ mvOsPrintf("Set default CAS latency 3\n"); ++ } ++ } ++ ++ /* calc SDRAM_CONFIG_REG and save it to temp register */ ++ temp = sdramConfigRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG1, temp); ++ ++ /* calc SDRAM_MODE_REG and save it to temp register */ ++ temp = sdramModeRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG2, temp); ++ ++ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ ++ temp = sdramExtModeRegCalc(&bankInfo[0]); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG10, temp); ++ ++ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ ++ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG3, temp); ++ ++ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ ++ temp = sdramAddrCtrlRegCalc(&bankInfo[0]); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG4, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ ++ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG5, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ ++ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG6, temp); ++ ++ /* Config DDR2 On Die Termination (ODT) registers */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ sdramDDr2OdtConfig(bankInfo); ++ } ++ ++ /* Note that DDR SDRAM Address/Control and Data pad calibration */ ++ /* settings is done in mvSdramIfConfig.s */ ++ ++ return retVal; ++} ++ ++/******************************************************************************* ++* minCasCalc - Calculate the Minimum CAS latency which can be used. ++* ++* DESCRIPTION: ++* Calculate the minimum CAS latency that can be used, base on the DRAM ++* parameters and the SDRAM bus Clock freq. ++* ++* INPUT: ++* busClk - the DRAM bus Clock. ++* pBankInfo - bank info parameters. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* The minimum CAS Latency. The function returns 0 if max CAS latency ++* supported by banks is incompatible with system bus clock frequancy. ++* ++*******************************************************************************/ ++static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, ++ MV_U32 forcedCl) ++{ ++ MV_U32 count = 1, j; ++ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ ++ MV_U32 startBit, stopBit; ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ ++ /* If we are asked to use the forced CAL */ ++ if (forcedCl) ++ { ++ mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), ++ (forcedCl % 10)); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ if (forcedCl == 30) ++ pBankInfo->suportedCasLatencies = 0x08; ++ else if (forcedCl == 40) ++ pBankInfo->suportedCasLatencies = 0x10; ++ else ++ { ++ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", ++ (forcedCl / 10), (forcedCl % 10)); ++ pBankInfo->suportedCasLatencies = 0x10; ++ } ++ } ++ else ++ { ++ if (forcedCl == 15) ++ pBankInfo->suportedCasLatencies = 0x02; ++ else if (forcedCl == 20) ++ pBankInfo->suportedCasLatencies = 0x04; ++ else if (forcedCl == 25) ++ pBankInfo->suportedCasLatencies = 0x08; ++ else if (forcedCl == 30) ++ pBankInfo->suportedCasLatencies = 0x10; ++ else if (forcedCl == 40) ++ pBankInfo->suportedCasLatencies = 0x40; ++ else ++ { ++ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n", ++ (forcedCl / 10), (forcedCl % 10)); ++ pBankInfo->suportedCasLatencies = 0x10; ++ } ++ } ++ ++ return pBankInfo->suportedCasLatencies; ++ } ++ ++ /* go over the supported cas mask from Max Cas down and check if the */ ++ /* SysClk stands in its time requirments. */ ++ ++ ++ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", ++ pBankInfo->suportedCasLatencies,busClkPs )); ++ for(j = 7; j > 0; j--) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ /* Reset the bits for CL incompatible for the sysClk */ ++ switch (count) ++ { ++ case 1: ++ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 2: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 3: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ default: ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ break; ++ } ++ } ++ } ++ ++ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", ++ pBankInfo->suportedCasLatencies )); ++ ++ /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */ ++ /* SDRAM DDR2 controller supports CL 3 to 5 */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ ++ stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */ ++ } ++ else ++ { ++ startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */ ++ stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */ ++ } ++ ++ for(j = startBit; j <= stopBit ; j++) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); ++ return (BIT0 << j); ++ } ++ } ++ ++ return 0; ++} ++ ++/******************************************************************************* ++* sdramConfigRegCalc - Calculate sdram config register ++* ++* DESCRIPTION: Calculate sdram config register optimized value based ++* on the bank info parameters. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram config reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 sdramConfig = 0; ++ MV_U32 refreshPeriod; ++ ++ busClk /= 1000000; /* we work with busClk in MHz */ ++ ++ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); ++ ++ /* figure out the memory refresh internal */ ++ switch (pBankInfo->refreshInterval & 0xf) ++ { ++ case 0x0: /* refresh period is 15.625 usec */ ++ refreshPeriod = 15625; ++ break; ++ case 0x1: /* refresh period is 3.9 usec */ ++ refreshPeriod = 3900; ++ break; ++ case 0x2: /* refresh period is 7.8 usec */ ++ refreshPeriod = 7800; ++ break; ++ case 0x3: /* refresh period is 31.3 usec */ ++ refreshPeriod = 31300; ++ break; ++ case 0x4: /* refresh period is 62.5 usec */ ++ refreshPeriod = 62500; ++ break; ++ case 0x5: /* refresh period is 125 usec */ ++ refreshPeriod = 125000; ++ break; ++ default: /* refresh period undefined */ ++ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); ++ return -1; ++ } ++ ++ /* Now the refreshPeriod is in register format value */ ++ refreshPeriod = (busClk * refreshPeriod) / 1000; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", ++ refreshPeriod)); ++ ++ /* make sure the refresh value is only 14 bits */ ++ if(refreshPeriod > SDRAM_REFRESH_MAX) ++ { ++ refreshPeriod = SDRAM_REFRESH_MAX; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", ++ refreshPeriod)); ++ } ++ ++ /* Clear the refresh field */ ++ sdramConfig &= ~SDRAM_REFRESH_MASK; ++ ++ /* Set new value to refresh field */ ++ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); ++ ++ /* registered DRAM ? */ ++ if ( pBankInfo->registeredAddrAndControlInputs ) ++ { ++ /* it's registered DRAM, so set the reg. DRAM bit */ ++ sdramConfig |= SDRAM_REGISTERED; ++ mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); ++ } ++ ++ /* set DDR SDRAM devices configuration */ ++ sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */ ++ ++ switch (pBankInfo->sdramWidth) ++ { ++ case 8: /* memory is x8 */ ++ sdramConfig |= SDRAM_DCFG_X8_DEV; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n")); ++ break; ++ case 16: ++ sdramConfig |= SDRAM_DCFG_X16_DEV; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n")); ++ break; ++ default: /* memory width unsupported */ ++ mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n"); ++ return -1; ++ } ++ ++ /* Set static default settings */ ++ sdramConfig |= SDRAM_CONFIG_DV; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", ++ sdramConfig)); ++ ++ return sdramConfig; ++} ++ ++/******************************************************************************* ++* sdramModeRegCalc - Calculate sdram mode register ++* ++* DESCRIPTION: Calculate sdram mode register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramModeRegCalc(MV_U32 minCas) ++{ ++ MV_U32 sdramMode; ++ ++ sdramMode = MV_REG_READ(SDRAM_MODE_REG); ++ ++ /* Clear CAS Latency field */ ++ sdramMode &= ~SDRAM_CL_MASK; ++ ++ mvOsPrintf("DRAM CAS Latency "); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ switch (minCas) ++ { ++ case DDR2_CL_3: ++ sdramMode |= SDRAM_DDR2_CL_3; ++ mvOsPrintf("3.\n"); ++ break; ++ case DDR2_CL_4: ++ sdramMode |= SDRAM_DDR2_CL_4; ++ mvOsPrintf("4.\n"); ++ break; ++ case DDR2_CL_5: ++ sdramMode |= SDRAM_DDR2_CL_5; ++ mvOsPrintf("5.\n"); ++ break; ++ default: ++ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); ++ return -1; ++ } ++ sdramMode |= DDR2_MODE_REG_DV; ++ } ++ else /* DDR1 */ ++ { ++ switch (minCas) ++ { ++ case DDR1_CL_1_5: ++ sdramMode |= SDRAM_DDR1_CL_1_5; ++ mvOsPrintf("1.5\n"); ++ break; ++ case DDR1_CL_2: ++ sdramMode |= SDRAM_DDR1_CL_2; ++ mvOsPrintf("2\n"); ++ break; ++ case DDR1_CL_2_5: ++ sdramMode |= SDRAM_DDR1_CL_2_5; ++ mvOsPrintf("2.5\n"); ++ break; ++ case DDR1_CL_3: ++ sdramMode |= SDRAM_DDR1_CL_3; ++ mvOsPrintf("3\n"); ++ break; ++ case DDR1_CL_4: ++ sdramMode |= SDRAM_DDR1_CL_4; ++ mvOsPrintf("4\n"); ++ break; ++ default: ++ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); ++ return -1; ++ } ++ sdramMode |= DDR1_MODE_REG_DV; ++ } ++ ++ DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode )); ++ ++ return sdramMode; ++} ++ ++/******************************************************************************* ++* sdramExtModeRegCalc - Calculate sdram Extended mode register ++* ++* DESCRIPTION: ++* Return sdram Extended mode register value based ++* on the bank info parameters and bank presence. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram Extended mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 populateBanks = 0; ++ int bankNum; ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ return DDR_SDRAM_EXT_MODE_CS0_DV; ++ ++ case(BANK_PRESENT_CS0_CS1): ++ return DDR_SDRAM_EXT_MODE_CS0_DV; ++ ++ case(BANK_PRESENT_CS0_CS2): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ default: ++ mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++/******************************************************************************* ++* dunitCtrlLowRegCalc - Calculate sdram dunit control low register ++* ++* DESCRIPTION: Calculate sdram dunit control low register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram dunit control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas) ++{ ++ MV_U32 dunitCtrlLow; ++ ++ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); ++ ++ /* Clear StBurstDel field */ ++ dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK; ++ ++#ifdef MV_88W8660 ++ /* Clear address/control output timing field */ ++ dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE; ++#endif /* MV_88W8660 */ ++ ++ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); ++ ++ /* For proper sample of read data set the Dunit Control register's */ ++ /* stBurstDel bits [27:24] */ ++ /********-********-********-********-********-********* ++ * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 * ++ *********-********-********-********-********-********* ++Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD * ++ *********-********-********-********-********-********* ++Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD * ++ *********-********-********-********-********-*********/ ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ switch (minCas) ++ { ++ case DDR2_CL_3: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR2_CL_4: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ default: ++ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", ++ minCas); ++ return -1; ++ } ++ } ++ else /* DDR1 */ ++ { ++ switch (minCas) ++ { ++ case DDR1_CL_1_5: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_2: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_2_5: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_3: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_4: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ default: ++ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", ++ minCas); ++ return -1; ++ } ++ ++ } ++ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); ++ ++ return dunitCtrlLow; ++} ++ ++/******************************************************************************* ++* sdramAddrCtrlRegCalc - Calculate sdram address control register ++* ++* DESCRIPTION: Calculate sdram address control register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram address control reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 addrCtrl = 0; ++ ++ /* Set Address Control register static configuration bits */ ++ addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG); ++ ++ /* Set address control default value */ ++ addrCtrl |= SDRAM_ADDR_CTRL_DV; ++ ++ /* Clear DSize field */ ++ addrCtrl &= ~SDRAM_DSIZE_MASK; ++ ++ /* Note that density is in MB units */ ++ switch (pBankInfo->deviceDensity) ++ { ++ case 128: /* 128 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 128Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_128Mb; ++ break; ++ case 256: /* 256 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_256Mb; ++ break; ++ case 512: /* 512 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_512Mb; ++ break; ++ default: ++ mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", ++ pBankInfo->deviceDensity); ++ return -1; ++ } ++ ++ /* SDRAM address control */ ++ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); ++ ++ return addrCtrl; ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control low register ++* optimized value based on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timinf control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 minCas, MV_U32 busClk) ++{ ++ MV_U32 tRp = 0; ++ MV_U32 tRrd = 0; ++ MV_U32 tRcd = 0; ++ MV_U32 tRas = 0; ++ MV_U32 tWr = 0; ++ MV_U32 tWtr = 0; ++ MV_U32 tRtp = 0; ++ ++ MV_U32 bankNum; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); ++ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); ++ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); ++ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ ++ /* by shifting the data two bits right. */ ++ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ ++ tRrd = tRrd >> 2; ++ tRcd = tRcd >> 2; ++ ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); ++ /* Micron work around for 133MHz */ ++ if (busClk == 133) ++ tRp += 1; ++ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); ++ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRrd = 2 */ ++ if (tRrd < 2) ++ tRrd = 2; ++ DB(mvOsPrintf("tRrd = %d ", tRrd)); ++ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRcd = %d ", tRcd)); ++ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRas = %d ", tRas)); ++ ++ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); ++ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); ++ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ ++ /* part by shifting the data two bits right. */ ++ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ ++ tWtr = tWtr >> 2; ++ tRtp = tRtp >> 2; ++ ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tWr = %d ", tWr)); ++ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tWtr = 2 */ ++ if (tWtr < 2) ++ tWtr = 2; ++ DB(mvOsPrintf("tWtr = %d ", tWtr)); ++ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRtp = 2 */ ++ if (tRtp < 2) ++ tRtp = 2; ++ DB(mvOsPrintf("tRtp = %d ", tRtp)); ++ } ++ else ++ { ++ tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0); ++ ++ if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas))) ++ { ++ tWtr = 2; ++ } ++ else ++ { ++ tWtr = 1; ++ } ++ ++ tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */ ++ } ++ ++ DB(mvOsPrintf("tWtr = %d\n", tWtr)); ++ ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ return (((tRp - 1) << SDRAM_TRP_OFFS) | ++ ((tRrd - 1) << SDRAM_TRRD_OFFS) | ++ ((tRcd - 1) << SDRAM_TRCD_OFFS) | ++ ((tRas - 1) << SDRAM_TRAS_OFFS) | ++ ((tWr - 1) << SDRAM_TWR_OFFS) | ++ ((tWtr - 1) << SDRAM_TWTR_OFFS) | ++ ((tRtp - 1) << SDRAM_TRTP_OFFS)); ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control high register ++* optimized value based on the bank info parameters and the bus clock. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timinf control high reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 busClk) ++{ ++ MV_U32 tRfc; ++ MV_U32 timeNs = 0; ++ int bankNum; ++ MV_U32 sdramTw2wCyc = 0; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* tRfc is different for DDR1 and DDR2. */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ MV_U32 bankNum; ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); ++ } ++ else ++ { ++ if (pBankInfo[0].deviceDensity == _1G) ++ { ++ timeNs = SDRAM_TRFC_1G; ++ } ++ else ++ { ++ if (200 == busClk) ++ { ++ timeNs = SDRAM_TRFC_64_512M_AT_200MHZ; ++ } ++ else ++ { ++ timeNs = SDRAM_TRFC_64_512M; ++ } ++ } ++ } ++ ++ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); ++ ++ DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc)); ++ ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ sdramTw2wCyc++; ++ } ++ ++ /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */ ++ if (sdramTw2wCyc > 1) ++ sdramTw2wCyc = 1; ++ else ++ sdramTw2wCyc = 0; ++ ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) | ++ ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) | ++ ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) | ++ (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) | ++ (sdramTw2wCyc << SDRAM_TW2W_OFFS)); ++ ++} ++ ++/******************************************************************************* ++* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. ++* ++* DESCRIPTION: ++* This function config DDR2 On Die Termination (ODT) registers. ++* ODT configuration is done according to DIMM presence: ++* ++* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode ++* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 ++* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 ++* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* ++* INPUT: ++* pBankInfo - bank info parameters. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* None ++*******************************************************************************/ ++static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 populateBanks = 0; ++ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; ++ int bankNum; ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS1): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ default: ++ mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"); ++ return; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); ++ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); ++ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); ++ return; ++} ++#endif /* defined(MV_INC_BOARD_DDIM) */ ++ ++/******************************************************************************* ++* mvDramIfWinSet - Set DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function sets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* pAddrDecWin - SDRAM address window structure. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg=0,sizeReg=0; ++ MV_U32 baseToReg=0 , sizeToReg=0; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlaps with current enabled windows */ ++ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ ++ "\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ target, ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ /* read base register*/ ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); ++ ++ /* read size register */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ baseReg &= ~SCBAR_BASE_MASK; ++ baseReg |= baseToReg; ++ ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* set size */ ++ sizeReg &= ~SCSR_SIZE_MASK; ++ /* Size is located at upper 16 bits */ ++ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); ++ ++ /* enable/Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ sizeReg |= SCSR_WIN_EN; ++ } ++ else ++ { ++ sizeReg &= ~SCSR_WIN_EN; ++ } ++ ++ /* 3) Write to address decode Base Address Register */ ++ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg); ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinGet - Get DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function gets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* pAddrDecWin - SDRAM address window structure. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg,sizeReg; ++ MV_U32 sizeRegVal; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Read base and size registers */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); ++ ++ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; ++ ++ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, ++ SCSR_SIZE_ALIGNMENT); ++ ++ /* Check if ctrlRegToSize returned OK */ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Extract base address */ ++ /* Base register [31:16] ==> baseLow[31:16] */ ++ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; ++ ++ pAddrDecWin->addrWin.baseHigh = 0; ++ ++ ++ if (sizeReg & SCSR_WIN_EN) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinEnable - Enable/Disable SDRAM address decode window ++* ++* DESCRIPTION: ++* This function enable/Disable SDRAM address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR in case function parameter are invalid, MV_OK otherewise. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { /* First check for overlap with other enabled windows */ ++ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", ++ target); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode winNum window */ ++ MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", ++ target); ++ return MV_ERROR; ++ } ++ } ++ else ++ { /* Disable address decode winNum window */ ++ MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window ++* ++* DESCRIPTION: ++* This function scan each SDRAM address decode window to test if it ++* overlapps the given address windoow ++* ++* INPUT: ++* target - SDRAM target where the function skips checking. ++* pAddrDecWin - The tested address window for overlapping with ++* SDRAM windows. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlaps any enabled address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_TARGET targetNum; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) ++ { ++ /* don't check our winNum or illegal targets */ ++ if (targetNum == target) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf( ++ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", ++ target, targetNum); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvDramIfBankSizeGet - Get DRAM interface bank size. ++* ++* DESCRIPTION: ++* This function returns the size of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled the function return '0'. In case ++* or paramter is invalid, the function returns -1. ++* ++*******************************************************************************/ ++MV_32 mvDramIfBankSizeGet(MV_U32 bankNum) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(bankNum)) ++ { ++ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); ++ return -1; ++ } ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return -1; ++ } ++ ++ if (MV_TRUE == addrDecWin.enable) ++ { ++ return addrDecWin.addrWin.size; ++ } ++ else ++ { ++ return 0; ++ } ++} ++ ++ ++/******************************************************************************* ++* mvDramIfSizeGet - Get DRAM interface total size. ++* ++* DESCRIPTION: ++* This function get the DRAM total size. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM total size. In case or paramter is invalid, the function ++* returns -1. ++* ++*******************************************************************************/ ++MV_32 mvDramIfSizeGet(MV_VOID) ++{ ++ MV_U32 totalSize = 0, bankSize = 0, bankNum; ++ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ bankSize = mvDramIfBankSizeGet(bankNum); ++ ++ if (-1 == bankSize) ++ { ++ mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum); ++ return -1; ++ } ++ else ++ { ++ totalSize += bankSize; ++ } ++ } ++ ++ DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize)); ++ ++ return totalSize; ++} ++ ++/******************************************************************************* ++* mvDramIfBankBaseGet - Get DRAM interface bank base. ++* ++* DESCRIPTION: ++* This function returns the 32 bit base address of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled or paramter is invalid, the ++* function returns -1. ++* ++*******************************************************************************/ ++MV_32 mvDramIfBankBaseGet(MV_U32 bankNum) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(bankNum)) ++ { ++ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); ++ return -1; ++ } ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return -1; ++ } ++ ++ if (MV_TRUE == addrDecWin.enable) ++ { ++ return addrDecWin.addrWin.baseLow; ++ } ++ else ++ { ++ return -1; ++ } ++} ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,179 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfh ++#define __INCmvDramIfh ++ ++/* includes */ ++#include "ddr1_2/mvDramIfRegs.h" ++#include "ddr1_2/mvDramIfConfig.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* defines */ ++/* DRAM Timing parameters */ ++#define SDRAM_TWR 15 /* ns tWr */ ++#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ ++#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ ++#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ ++#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ ++#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */ ++ ++/* typedefs */ ++ ++/* enumeration for memory types */ ++typedef enum _mvMemoryType ++{ ++ MEM_TYPE_SDRAM, ++ MEM_TYPE_DDR1, ++ MEM_TYPE_DDR2 ++}MV_MEMORY_TYPE; ++ ++/* enumeration for DDR1 supported CAS Latencies */ ++typedef enum _mvDimmDdr1Cas ++{ ++ DDR1_CL_1_5 = 0x02, ++ DDR1_CL_2 = 0x04, ++ DDR1_CL_2_5 = 0x08, ++ DDR1_CL_3 = 0x10, ++ DDR1_CL_4 = 0x40, ++ DDR1_CL_FAULT ++} MV_DIMM_DDR1_CAS; ++ ++/* enumeration for DDR2 supported CAS Latencies */ ++typedef enum _mvDimmDdr2Cas ++{ ++ DDR2_CL_3 = 0x08, ++ DDR2_CL_4 = 0x10, ++ DDR2_CL_5 = 0x20, ++ DDR2_CL_FAULT ++} MV_DIMM_DDR2_CAS; ++ ++ ++typedef struct _mvDramBankInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ ++ MV_U32 numberOfDevices; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ MV_BOOL registeredAddrAndControlInputs; ++ ++}MV_DRAM_BANK_INFO; ++ ++/* This structure describes CPU interface address decode window */ ++typedef struct _mvDramIfDecWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++}MV_DRAM_DEC_WIN; ++ ++#include "ddr1_2/mvDram.h" ++ ++/* mvDramIf.h API list */ ++MV_VOID mvDramIfBasicAsmInit(MV_VOID); ++MV_STATUS mvDramIfDetect(MV_U32 forcedCl); ++MV_VOID _mvDramIfConfig(MV_VOID); ++ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); ++MV_32 mvDramIfBankSizeGet(MV_U32 bankNum); ++MV_32 mvDramIfBankBaseGet(MV_U32 bankNum); ++MV_32 mvDramIfSizeGet(MV_VOID); ++ ++#if 0 ++MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray); ++MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable); ++#endif ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,192 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfConfigh ++#define __INCmvDramIfConfigh ++ ++/* includes */ ++ ++/* defines */ ++ ++/* registers defaults values */ ++ ++#define SDRAM_CONFIG_DV \ ++ (SDRAM_PERR_WRITE | \ ++ SDRAM_SRMODE | \ ++ SDRAM_SRCLK_GATED) ++ ++#define SDRAM_DUNIT_CTRL_LOW_DV \ ++ (SDRAM_CTRL_POS_RISE | \ ++ SDRAM_CLK1DRV_NORMAL | \ ++ SDRAM_LOCKEN_ENABLE) ++ ++#define SDRAM_ADDR_CTRL_DV 0 ++ ++#define SDRAM_TIMING_CTRL_LOW_REG_DV \ ++ ((0x2 << SDRAM_TRCD_OFFS) | \ ++ (0x2 << SDRAM_TRP_OFFS) | \ ++ (0x1 << SDRAM_TWR_OFFS) | \ ++ (0x0 << SDRAM_TWTR_OFFS) | \ ++ (0x5 << SDRAM_TRAS_OFFS) | \ ++ (0x1 << SDRAM_TRRD_OFFS)) ++/* TRFC 0x27, TW2W 0x1 */ ++#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\ ++ ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\ ++ ( 0x1 << SDRAM_TW2W_OFFS)) ++ ++#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN ++ ++/* DDR2 ODT default register values */ ++ ++/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ ++/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++ ++#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000 ++#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F ++#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440 ++ ++#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C ++#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F ++#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404 ++ ++ ++/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ ++#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ ++ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++ ++#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \ ++ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++/* DDR SDRAM Mode Register default value */ ++#define DDR1_MODE_REG_DV 0x00000000 ++#define DDR2_MODE_REG_DV 0x00000400 ++ ++/* DDR SDRAM Timing parameter default values */ ++#define DDR1_TIMING_LOW_DV 0x11602220 ++#define DDR1_TIMING_HIGH_DV 0x0000000d ++ ++#define DDR2_TIMING_LOW_DV 0x11812220 ++#define DDR2_TIMING_HIGH_DV 0x0000030f ++ ++/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */ ++#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \ ++ (0x7F<< 12) | \ ++ (0x1 << 22)) ++ ++#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ ++ ++#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \ ++ (0x1 << 12) | \ ++ (0x3 << 14) | \ ++ (0x1 << 18) | \ ++ (0x1 << 22)) ++ ++ ++#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \ ++ (0x1 << 12) | \ ++ (0x1 << 14) | \ ++ (0x1 << 16) | \ ++ (0x1 << 19) | \ ++ (0xF << 20)) ++ ++#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ ++ ++#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \ ++ (0x1 << 12) | \ ++ (0x1 << 14) | \ ++ (0x1 << 16) | \ ++ (0x1 << 19) | \ ++ (0xF << 20)) ++ ++#define FTDLL_DDR2_250MHZ 0x445001 ++ ++/* Orion 1 B1 and above */ ++#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001 ++ ++/* Orion nas */ ++#define FTDLL_DDR2_166MHZ_5182 0x597001 ++ ++/* Orion 2 D0 and above */ ++#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001 ++#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001 ++#define FTDLL_DDR2_166MHZ_5281_D0 0x485001 ++#define FTDLL_DDR2_200MHZ_5281_D0 0x485001 ++#define FTDLL_DDR2_250MHZ_5281_D0 0x445001 ++#define FTDLL_DDR2_200MHZ_5281_D1 0x995001 ++#define FTDLL_DDR2_250MHZ_5281_D1 0x984801 ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,306 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDramIfRegsh ++#define __INCmvDramIfRegsh ++ ++ ++/* DDR SDRAM Controller Address Decode Registers */ ++/* SDRAM CSn Base Address Register (SCBAR) */ ++#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) ++#define SCBAR_BASE_OFFS 16 ++#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) ++#define SCBAR_BASE_ALIGNMENT 0x10000 ++ ++/* SDRAM CSn Size Register (SCSR) */ ++#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) ++#define SCSR_WIN_EN BIT0 ++#define SCSR_SIZE_OFFS 16 ++#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) ++#define SCSR_SIZE_ALIGNMENT 0x10000 ++ ++/* configuration register */ ++#define SDRAM_CONFIG_REG 0x1400 ++#define SDRAM_REFRESH_OFFS 0 ++#define SDRAM_REFRESH_MAX 0x3000 ++#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) ++#define SDRAM_DWIDTH_OFFS 14 ++#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DTYPE_OFFS 16 ++#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) ++#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) ++#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) ++#define SDRAM_REGISTERED (1 << 17) ++#define SDRAM_PERR_OFFS 18 ++#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) ++#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) ++#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) ++#define SDRAM_DCFG_OFFS 20 ++#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) ++#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) ++#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) ++#define SDRAM_SRMODE (1 << 24) ++#define SDRAM_SRCLK_OFFS 25 ++#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_CATTH_OFFS 26 ++#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) ++ ++ ++/* dunit control register */ ++#define SDRAM_DUNIT_CTRL_REG 0x1404 ++#define SDRAM_CTRL_POS_OFFS 6 ++#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CLK1DRV_OFFS 12 ++#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_LOCKEN_OFFS 18 ++#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) ++#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) ++#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) ++#define SDRAM_ST_BURST_DEL_OFFS 24 ++#define SDRAM_ST_BURST_DEL_MAX 0xf ++#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX< busClkPs) ++ { ++ mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); ++ return MV_ERROR; ++ } ++ ++ /* All banks must support registry in order to activate it */ ++ if(bankInfo[i].registeredAddrAndControlInputs != ++ bankInfo[0].registeredAddrAndControlInputs) ++ { ++ mvOsOutput("Dram: ERR. different Registered settings !!!\n"); ++ return MV_ERROR; ++ } ++ ++ /* All banks must support same ECC mode */ ++ if(bankInfo[i].errorCheckType != ++ bankInfo[0].errorCheckType) ++ { ++ mvOsOutput("Dram: ERR. different ECC settings !!!\n"); ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ if( i == 0 ) /* bank 0 doesn't exist */ ++ { ++ mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); ++ return MV_ERROR; ++ } ++ else ++ { ++ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); ++ bankInfo[i].size = 0; /* Mark this bank as non exist */ ++ } ++ } ++ } ++ ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) ++ { ++ MV_DRAM_CS_order[0] = SDRAM_CS2; ++ MV_DRAM_CS_order[1] = SDRAM_CS3; ++ MV_DRAM_CS_order[2] = SDRAM_CS0; ++ MV_DRAM_CS_order[3] = SDRAM_CS1; ++ DRAM_CS_Order[0] = SDRAM_CS2; ++ DRAM_CS_Order[1] = SDRAM_CS3; ++ DRAM_CS_Order[2] = SDRAM_CS0; ++ DRAM_CS_Order[3] = SDRAM_CS1; ++ ++ } ++ else ++#endif ++ { ++ MV_DRAM_CS_order[0] = SDRAM_CS0; ++ MV_DRAM_CS_order[1] = SDRAM_CS1; ++ DRAM_CS_Order[0] = SDRAM_CS0; ++ DRAM_CS_Order[1] = SDRAM_CS1; ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ MV_DRAM_CS_order[2] = SDRAM_CS2; ++ MV_DRAM_CS_order[3] = SDRAM_CS3; ++ DRAM_CS_Order[2] = SDRAM_CS2; ++ DRAM_CS_Order[3] = SDRAM_CS3; ++#endif ++ } ++ ++ for(j = 0; j < MV_DRAM_MAX_CS; j++) ++ { ++ i = MV_DRAM_CS_order[j]; ++ ++ if (0 == bankInfo[i].size) ++ continue; ++ ++ /* Init the CPU window decode */ ++ /* Note that the Dimm width might be different then the device DRAM width */ ++#ifdef MV78XX0 ++ temp = MV_REG_READ(SDRAM_CONFIG_REG); ++ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; ++#else ++ deviceW = 16 /* KW family */; ++#endif ++ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); ++ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); ++ ++ /* We can not change DRAM window settings while excecuting */ ++ /* code from it. That is why we skip the DRAM CS[0], saving */ ++ /* it to the ROM configuration routine */ ++ ++ numOfAllDevices += bankInfo[i].numberOfDevices; ++ if (i == MV_DRAM_CS_order[0]) ++ { ++ MV_U32 sizeToReg; ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" ++ ,i); ++ return MV_BAD_PARAM; ++ } ++ ++ DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) ++ sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); ++ sizeToReg |= SCSR_WIN_EN; ++ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); ++ } ++ else ++ { ++ dramDecWin.addrWin.baseLow = base; ++ dramDecWin.addrWin.size = size; ++ dramDecWin.enable = MV_TRUE; ++ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); ++ ++ /* Check if the DRAM size is more then 3GByte */ ++ if (base < 0xC0000000) ++ { ++ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); ++ if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin)) ++ { ++ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); ++ return MV_ERROR; ++ } ++ } ++ } ++ ++ base += size; ++ ++ /* update the suportedCasLatencies mask */ ++ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; ++ } ++ ++ /* calculate minimum CAS */ ++ minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); ++ if (0 == minCas) ++ { ++ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", ++ (busClk / 1000000)); ++ ++ minCas = DDR2_CL_4; /* Continue with this CAS */ ++ mvOsOutput("Set default CAS latency 4\n"); ++ } ++ ++ /* calc SDRAM_CONFIG_REG and save it to temp register */ ++ temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ ++ /* check if ECC is enabled by the user */ ++ if(eccDisable) ++ { ++ /* turn off ECC*/ ++ temp &= ~BIT18; ++ } ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG1, temp); ++ ++ /* calc SDRAM_MODE_REG and save it to temp register */ ++ temp = sdramModeRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG2, temp); ++ ++ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ ++ temp = sdramExtModeRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG10, temp); ++ ++ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ ++ TTMode = MV_FALSE; ++ DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) ++ if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) ++ { ++ if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || ++ (numOfAllDevices > 18) ) ++ { ++ mvOsOutput("Enable 2T "); ++ TTMode = MV_TRUE; ++ } ++ } ++ ++ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG3, temp); ++ ++ /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ ++ temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) ++ /* check if ECC is enabled by the user */ ++ if(eccDisable) ++ { ++ /* turn off sample stage if no ecc */ ++ temp &= ~SDRAM__D2P_EN;; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG13, temp); ++ ++ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ ++ temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG4, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ ++ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG5, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ ++ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG6, temp); ++ ++ sdramDDr2OdtConfig(bankInfo); ++ ++ /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ ++ temp = sdramDdr2TimeLoRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG11, temp); ++ ++ /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ ++ temp = sdramDdr2TimeHiRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG12, temp); ++#endif ++ ++ /* Note that DDR SDRAM Address/Control and Data pad calibration */ ++ /* settings is done in mvSdramIfConfig.s */ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvDramIfBankBaseGet - Get DRAM interface bank base. ++* ++* DESCRIPTION: ++* This function returns the 32 bit base address of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled or paramter is invalid, the ++* function returns -1. ++* ++*******************************************************************************/ ++MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) ++{ ++ DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", ++ bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum))); ++ return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum); ++} ++ ++/******************************************************************************* ++* mvDramIfBankSizeGet - Get DRAM interface bank size. ++* ++* DESCRIPTION: ++* This function returns the size of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled the function return '0'. In case ++* or paramter is invalid, the function returns -1. ++* ++*******************************************************************************/ ++MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) ++{ ++ DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", ++ bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum))); ++ return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum); ++} ++ ++ ++/******************************************************************************* ++* mvDramIfSizeGet - Get DRAM interface total size. ++* ++* DESCRIPTION: ++* This function get the DRAM total size. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM total size. In case or paramter is invalid, the function ++* returns -1. ++* ++*******************************************************************************/ ++MV_U32 mvDramIfSizeGet(MV_VOID) ++{ ++ MV_U32 size = 0, i; ++ ++ for(i = 0; i < MV_DRAM_MAX_CS; i++) ++ size += mvDramIfBankSizeGet(i); ++ ++ DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); ++ return size; ++} ++ ++/******************************************************************************* ++* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. ++* ++* DESCRIPTION: ++* The ECC single bit error threshold is the number of single bit ++* errors to happen before the Dunit generates an interrupt. ++* This function set single bit ECC threshold. ++* ++* INPUT: ++* threshold - threshold. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) ++{ ++ MV_U32 regVal; ++ ++ if (threshold > SECR_THRECC_MAX) ++ { ++ return MV_BAD_PARAM; ++ } ++ ++ regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); ++ regVal &= ~SECR_THRECC_MASK; ++ regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); ++ MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); ++ ++ return MV_OK; ++} ++ ++#ifndef MV_STATIC_DRAM_ON_BOARD ++/******************************************************************************* ++* minCasCalc - Calculate the Minimum CAS latency which can be used. ++* ++* DESCRIPTION: ++* Calculate the minimum CAS latency that can be used, base on the DRAM ++* parameters and the SDRAM bus Clock freq. ++* ++* INPUT: ++* busClk - the DRAM bus Clock. ++* pBankInfo - bank info parameters. ++* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* The minimum CAS Latency. The function returns 0 if max CAS latency ++* supported by banks is incompatible with system bus clock frequancy. ++* ++*******************************************************************************/ ++ ++static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) ++{ ++ MV_U32 count = 1, j; ++ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ ++ MV_U32 startBit, stopBit; ++ MV_U32 minCas0 = 0, minCas2 = 0; ++ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * ++ Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * ++ *********************************************************/ ++ ++ ++ /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ ++ if (forcedCl) ++ { ++ mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); ++ ++ if (forcedCl == 30) ++ pBankInfo->suportedCasLatencies = 0x08; ++ else if (forcedCl == 40) ++ pBankInfo->suportedCasLatencies = 0x10; ++ else if (forcedCl == 50) ++ pBankInfo->suportedCasLatencies = 0x20; ++ else if (forcedCl == 60) ++ pBankInfo->suportedCasLatencies = 0x40; ++ else ++ { ++ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", ++ (forcedCl / 10), (forcedCl % 10)); ++ pBankInfo->suportedCasLatencies = 0x10; ++ } ++ ++ return pBankInfo->suportedCasLatencies; ++ } ++ ++ /* go over the supported cas mask from Max Cas down and check if the */ ++ /* SysClk stands in its time requirments. */ ++ ++ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", ++ pBankInfo->suportedCasLatencies,busClkPs )); ++ count = 1; ++ for(j = 7; j > 0; j--) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ /* Reset the bits for CL incompatible for the sysClk */ ++ switch (count) ++ { ++ case 1: ++ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 2: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 3: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ default: ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ break; ++ } ++ } ++ } ++ ++ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", ++ pBankInfo->suportedCasLatencies )); ++ ++ count = 1; ++ DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", ++ pBankInfo2->suportedCasLatencies,busClkPs )); ++ for(j = 7; j > 0; j--) ++ { ++ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) ++ { ++ /* Reset the bits for CL incompatible for the sysClk */ ++ switch (count) ++ { ++ case 1: ++ if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 2: ++ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 3: ++ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ default: ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ break; ++ } ++ } ++ } ++ ++ DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", ++ pBankInfo2->suportedCasLatencies )); ++ ++ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ ++ stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ ++ ++ for(j = startBit; j <= stopBit ; j++) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); ++ minCas0 = (BIT0 << j); ++ break; ++ } ++ } ++ ++ for(j = startBit; j <= stopBit ; j++) ++ { ++ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) ++ { ++ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); ++ minCas2 = (BIT0 << j); ++ break; ++ } ++ } ++ ++ if (minCas2 > minCas0) ++ return minCas2; ++ else ++ return minCas0; ++ ++ return 0; ++} ++ ++/******************************************************************************* ++* sdramConfigRegCalc - Calculate sdram config register ++* ++* DESCRIPTION: Calculate sdram config register optimized value based ++* on the bank info parameters. ++* ++* INPUT: ++* busClk - the DRAM bus Clock. ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram config reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) ++{ ++ MV_U32 sdramConfig = 0; ++ MV_U32 refreshPeriod; ++ ++ busClk /= 1000000; /* we work with busClk in MHz */ ++ ++ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); ++ ++ /* figure out the memory refresh internal */ ++ switch (pBankInfo->refreshInterval & 0xf) ++ { ++ case 0x0: /* refresh period is 15.625 usec */ ++ refreshPeriod = 15625; ++ break; ++ case 0x1: /* refresh period is 3.9 usec */ ++ refreshPeriod = 3900; ++ break; ++ case 0x2: /* refresh period is 7.8 usec */ ++ refreshPeriod = 7800; ++ break; ++ case 0x3: /* refresh period is 31.3 usec */ ++ refreshPeriod = 31300; ++ break; ++ case 0x4: /* refresh period is 62.5 usec */ ++ refreshPeriod = 62500; ++ break; ++ case 0x5: /* refresh period is 125 usec */ ++ refreshPeriod = 125000; ++ break; ++ default: /* refresh period undefined */ ++ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); ++ return -1; ++ } ++ ++ /* Now the refreshPeriod is in register format value */ ++ refreshPeriod = (busClk * refreshPeriod) / 1000; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", ++ refreshPeriod)); ++ ++ /* make sure the refresh value is only 14 bits */ ++ if(refreshPeriod > SDRAM_REFRESH_MAX) ++ { ++ refreshPeriod = SDRAM_REFRESH_MAX; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", ++ refreshPeriod)); ++ } ++ ++ /* Clear the refresh field */ ++ sdramConfig &= ~SDRAM_REFRESH_MASK; ++ ++ /* Set new value to refresh field */ ++ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); ++ ++ /* registered DRAM ? */ ++ if ( pBankInfo->registeredAddrAndControlInputs ) ++ { ++ /* it's registered DRAM, so set the reg. DRAM bit */ ++ sdramConfig |= SDRAM_REGISTERED; ++ DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) ++ } ++ ++ /* ECC and IERR support */ ++ sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ ++ sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ ++ ++ if ( pBankInfo->errorCheckType ) ++ { ++ sdramConfig |= SDRAM_ECC_EN; ++ sdramConfig |= SDRAM_IERR_REPORTE; ++ DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); ++ } ++ else ++ { ++ sdramConfig |= SDRAM_ECC_DIS; ++ sdramConfig |= SDRAM_IERR_IGNORE; ++ DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); ++ } ++ /* Set static default settings */ ++ sdramConfig |= SDRAM_CONFIG_DV; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", ++ sdramConfig)); ++ ++ return sdramConfig; ++} ++ ++/******************************************************************************* ++* sdramModeRegCalc - Calculate sdram mode register ++* ++* DESCRIPTION: Calculate sdram mode register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramModeRegCalc(MV_U32 minCas) ++{ ++ MV_U32 sdramMode; ++ ++ sdramMode = MV_REG_READ(SDRAM_MODE_REG); ++ ++ /* Clear CAS Latency field */ ++ sdramMode &= ~SDRAM_CL_MASK; ++ ++ DB(mvOsPrintf("DRAM CAS Latency ");) ++ ++ switch (minCas) ++ { ++ case DDR2_CL_3: ++ sdramMode |= SDRAM_DDR2_CL_3; ++ DB(mvOsPrintf("3.\n");) ++ break; ++ case DDR2_CL_4: ++ sdramMode |= SDRAM_DDR2_CL_4; ++ DB(mvOsPrintf("4.\n");) ++ break; ++ case DDR2_CL_5: ++ sdramMode |= SDRAM_DDR2_CL_5; ++ DB(mvOsPrintf("5.\n");) ++ break; ++ case DDR2_CL_6: ++ sdramMode |= SDRAM_DDR2_CL_6; ++ DB(mvOsPrintf("6.\n");) ++ break; ++ default: ++ mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); ++ return -1; ++ } ++ ++ DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); ++ ++ return sdramMode; ++} ++/******************************************************************************* ++* sdramExtModeRegCalc - Calculate sdram Extended mode register ++* ++* DESCRIPTION: ++* Return sdram Extended mode register value based ++* on the bank info parameters and bank presence. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - DRAM frequency ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram Extended mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 populateBanks = 0; ++ int bankNum; ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ case(BANK_PRESENT_CS0_CS1): ++ return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; ++ ++ case(BANK_PRESENT_CS0_CS2): ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ if (busClk >= MV_BOARD_SYSCLK_267MHZ) ++ return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; ++ else ++ return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; ++ ++ default: ++ mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++/******************************************************************************* ++* dunitCtrlLowRegCalc - Calculate sdram dunit control low register ++* ++* DESCRIPTION: Calculate sdram dunit control low register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram dunit control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) ++{ ++ MV_U32 dunitCtrlLow, cl; ++ MV_U32 sbOutR[4]={3,5,7,9} ; ++ MV_U32 sbOutU[4]={1,3,5,7} ; ++ ++ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); ++ ++ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); ++ ++ /* Clear StBurstOutDel field */ ++ dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; ++ ++ /* Clear StBurstInDel field */ ++ dunitCtrlLow &= ~SDRAM_SB_IN_MASK; ++ ++ /* Clear CtrlPos field */ ++ dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; ++ ++ /* Clear 2T field */ ++ dunitCtrlLow &= ~SDRAM_2T_MASK; ++ if (TTMode == MV_TRUE) ++ { ++ dunitCtrlLow |= SDRAM_2T_MODE; ++ } ++ ++ /* For proper sample of read data set the Dunit Control register's */ ++ /* stBurstInDel bits [27:24] */ ++ /* 200MHz - 267MHz None reg = CL + 1 */ ++ /* 200MHz - 267MHz reg = CL + 2 */ ++ /* > 267MHz None reg = CL + 2 */ ++ /* > 267MHz reg = CL + 3 */ ++ ++ /* For proper sample of read data set the Dunit Control register's */ ++ /* stBurstOutDel bits [23:20] */ ++ /********-********-********-********- ++ * CL=3 | CL=4 | CL=5 | CL=6 | ++ *********-********-********-********- ++ Not Reg. * 0001 | 0011 | 0101 | 0111 | ++ *********-********-********-********- ++ Registered * 0011 | 0101 | 0111 | 1001 | ++ *********-********-********-********/ ++ ++ /* Set Dunit Control low default value */ ++ dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; ++ ++ switch (minCas) ++ { ++ case DDR2_CL_3: cl = 3; break; ++ case DDR2_CL_4: cl = 4; break; ++ case DDR2_CL_5: cl = 5; break; ++ case DDR2_CL_6: cl = 6; break; ++ default: ++ mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); ++ return -1; ++ } ++ ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ { ++ dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; ++ } ++ else ++ { ++ dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; ++ } ++ ++ DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); ++ ++ if (busClk <= MV_BOARD_SYSCLK_267MHZ) ++ { ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ cl = cl + 2; ++ else ++ cl = cl + 1; ++ } ++ else ++ { ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ cl = cl + 3; ++ else ++ cl = cl + 2; ++ } ++ ++ DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); ++ dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; ++ ++ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); ++ ++ return dunitCtrlLow; ++} ++ ++/******************************************************************************* ++* dunitCtrlHighRegCalc - Calculate sdram dunit control high register ++* ++* DESCRIPTION: Calculate sdram dunit control high register optimized value based ++* on the bus clock. ++* ++* INPUT: ++* busClk - DRAM frequency. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram dunit control high reg value. ++* ++*******************************************************************************/ ++static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 dunitCtrlHigh; ++ dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); ++ if(busClk > MV_BOARD_SYSCLK_300MHZ) ++ dunitCtrlHigh |= SDRAM__P2D_EN; ++ else ++ dunitCtrlHigh &= ~SDRAM__P2D_EN; ++ ++ if(busClk > MV_BOARD_SYSCLK_267MHZ) ++ dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); ++ ++ /* If ECC support we turn on D2P sample */ ++ dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ ++ if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) ++ dunitCtrlHigh |= SDRAM__D2P_EN; ++ ++ return dunitCtrlHigh; ++} ++ ++/******************************************************************************* ++* sdramAddrCtrlRegCalc - Calculate sdram address control register ++* ++* DESCRIPTION: Calculate sdram address control register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram address control reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) ++{ ++ MV_U32 addrCtrl = 0; ++ ++ if (pBankInfoDIMM1->size) ++ { ++ switch (pBankInfoDIMM1->sdramWidth) ++ { ++ case 4: /* memory is x4 */ ++ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); ++ return -1; ++ break; ++ case 8: /* memory is x8 */ ++ addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); ++ break; ++ case 16: ++ addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); ++ break; ++ default: /* memory width unsupported */ ++ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); ++ return -1; ++ } ++ } ++ ++ switch (pBankInfo->sdramWidth) ++ { ++ case 4: /* memory is x4 */ ++ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); ++ return -1; ++ break; ++ case 8: /* memory is x8 */ ++ addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); ++ break; ++ case 16: ++ addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); ++ break; ++ default: /* memory width unsupported */ ++ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); ++ return -1; ++ } ++ ++ /* Note that density is in MB units */ ++ switch (pBankInfo->deviceDensity) ++ { ++ case 256: /* 256 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); ++ break; ++ case 512: /* 512 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); ++ break; ++ case 1024: /* 1 Gbit */ ++ DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); ++ break; ++ case 2048: /* 2 Gbit */ ++ DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); ++ break; ++ default: ++ mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", ++ pBankInfo->deviceDensity); ++ return -1; ++ } ++ ++ if (pBankInfoDIMM1->size) ++ { ++ switch (pBankInfoDIMM1->deviceDensity) ++ { ++ case 256: /* 256 Mbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); ++ break; ++ case 512: /* 512 Mbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); ++ break; ++ case 1024: /* 1 Gbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); ++ break; ++ case 2048: /* 2 Gbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); ++ break; ++ default: ++ mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", ++ pBankInfoDIMM1->deviceDensity); ++ return -1; ++ } ++ } ++ /* SDRAM address control */ ++ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); ++ ++ return addrCtrl; ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control low register ++* optimized value based on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* minCas - minimum CAS supported. ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timing control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) ++{ ++ MV_U32 tRp = 0; ++ MV_U32 tRrd = 0; ++ MV_U32 tRcd = 0; ++ MV_U32 tRas = 0; ++ MV_U32 tWr = 0; ++ MV_U32 tWtr = 0; ++ MV_U32 tRtp = 0; ++ MV_U32 timeCtrlLow = 0; ++ ++ MV_U32 bankNum; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); ++ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); ++ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); ++ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ ++ /* by shifting the data two bits right. */ ++ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ ++ tRrd = tRrd >> 2; ++ tRcd = tRcd >> 2; ++ ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); ++ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRrd = 2 */ ++ if (tRrd < 2) ++ tRrd = 2; ++ DB(mvOsPrintf("tRrd = %d ", tRrd)); ++ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRcd = %d ", tRcd)); ++ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRas = %d ", tRas)); ++ ++ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); ++ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); ++ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ ++ /* part by shifting the data two bits right. */ ++ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ ++ tWtr = tWtr >> 2; ++ tRtp = tRtp >> 2; ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tWr = %d ", tWr)); ++ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tWtr = 2 */ ++ if (tWtr < 2) ++ tWtr = 2; ++ DB(mvOsPrintf("tWtr = %d ", tWtr)); ++ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRtp = 2 */ ++ if (tRtp < 2) ++ tRtp = 2; ++ DB(mvOsPrintf("tRtp = %d ", tRtp)); ++ ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | ++ ((tRrd - 1) << SDRAM_TRRD_OFFS) | ++ ((tRcd - 1) << SDRAM_TRCD_OFFS) | ++ (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| ++ ((tWr - 1) << SDRAM_TWR_OFFS) | ++ ((tWtr - 1) << SDRAM_TWTR_OFFS) | ++ ((tRtp - 1) << SDRAM_TRTP_OFFS)); ++ ++ /* Check extended tRas bit */ ++ if ((tRas - 1) & BIT4) ++ timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); ++ ++ return timeCtrlLow; ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control high register ++* optimized value based on the bank info parameters and the bus clock. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timing control high reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 tRfc; ++ MV_U32 timingHigh; ++ MV_U32 timeNs = 0; ++ MV_U32 bankNum; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* Set DDR timing high register static configuration bits */ ++ timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); ++ ++ /* Set DDR timing high register default value */ ++ timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; ++ ++ /* Clear tRfc field */ ++ timingHigh &= ~SDRAM_TRFC_MASK; ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); ++ DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", ++ pBankInfo[bankNum].minRefreshToActiveCmd)); ++ } ++ if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) ++ { ++ timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; ++ } ++ ++ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); ++ timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); ++ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); ++ ++ /* SDRAM timing high */ ++ DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); ++ ++ return timingHigh; ++} ++/******************************************************************************* ++* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. ++* ++* DESCRIPTION: ++* This function config DDR2 On Die Termination (ODT) registers. ++* ++* INPUT: ++* pBankInfo - bank info parameters. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* None ++*******************************************************************************/ ++static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 populateBanks = 0; ++ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; ++ int bankNum; ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ case(BANK_PRESENT_CS0_CS1): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2): ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; ++ break; ++ default: ++ DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); ++ return; ++ } ++ /* DDR2 SDRAM ODT ctrl low */ ++ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); ++ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); ++ ++ /* DDR2 SDRAM ODT ctrl high */ ++ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); ++ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); ++ ++ /* DDR2 DUNIT ODT ctrl */ ++ if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || ++ (mvCtrlModelGet() == MV_76100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78200_DEV_ID) ) ++ dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ ++ ++ DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); ++ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); ++ return; ++} ++/******************************************************************************* ++* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. ++* ++* DESCRIPTION: ++* This function config DDR2 DRAM Timing low registers. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* DDR2 sdram timing low reg value. ++*******************************************************************************/ ++static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) ++{ ++ MV_U8 cl = -1; ++ MV_U32 ddr2TimeLoReg; ++ ++ /* read and clear the feilds we are going to set */ ++ ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); ++ ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | ++ SD2TLR_TODT_OFF_RD_MASK | ++ SD2TLR_TODT_ON_CTRL_RD_MASK | ++ SD2TLR_TODT_OFF_CTRL_RD_MASK); ++ ++ if( minCas == DDR2_CL_3 ) ++ { ++ cl = 3; ++ } ++ else if( minCas == DDR2_CL_4 ) ++ { ++ cl = 4; ++ } ++ else if( minCas == DDR2_CL_5 ) ++ { ++ cl = 5; ++ } ++ else if( minCas == DDR2_CL_6 ) ++ { ++ cl = 6; ++ } ++ else ++ { ++ DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", ++ minCas)); ++ cl = 4; ++ } ++ ++ ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); ++ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); ++ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); ++ ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); ++ ++ /* DDR2 SDRAM timing low */ ++ DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); ++ ++ return ddr2TimeLoReg; ++} ++ ++/******************************************************************************* ++* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. ++* ++* DESCRIPTION: ++* This function config DDR2 DRAM Timing high registers. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* DDR2 sdram timing high reg value. ++*******************************************************************************/ ++static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) ++{ ++ MV_U8 cl = -1; ++ MV_U32 ddr2TimeHiReg; ++ ++ /* read and clear the feilds we are going to set */ ++ ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); ++ ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | ++ SD2THR_TODT_OFF_WR_MASK | ++ SD2THR_TODT_ON_CTRL_WR_MASK | ++ SD2THR_TODT_OFF_CTRL_WR_MASK); ++ ++ if( minCas == DDR2_CL_3 ) ++ { ++ cl = 3; ++ } ++ else if( minCas == DDR2_CL_4 ) ++ { ++ cl = 4; ++ } ++ else if( minCas == DDR2_CL_5 ) ++ { ++ cl = 5; ++ } ++ else if( minCas == DDR2_CL_6 ) ++ { ++ cl = 6; ++ } ++ else ++ { ++ mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", ++ minCas); ++ cl = 4; ++ } ++ ++ ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); ++ ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); ++ ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); ++ ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); ++ ++ /* DDR2 SDRAM timin high */ ++ DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); ++ ++ return ddr2TimeHiReg; ++} ++#endif ++ ++/******************************************************************************* ++* mvDramIfCalGet - Get CAS Latency ++* ++* DESCRIPTION: ++* This function get the CAS Latency. ++* ++* INPUT: ++* None ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* CAS latency times 10 (to avoid using floating point). ++* ++*******************************************************************************/ ++MV_U32 mvDramIfCalGet(void) ++{ ++ MV_U32 sdramCasLat, casLatMask; ++ ++ casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); ++ ++ switch (casLatMask) ++ { ++ case SDRAM_DDR2_CL_3: ++ sdramCasLat = 30; ++ break; ++ case SDRAM_DDR2_CL_4: ++ sdramCasLat = 40; ++ break; ++ case SDRAM_DDR2_CL_5: ++ sdramCasLat = 50; ++ break; ++ case SDRAM_DDR2_CL_6: ++ sdramCasLat = 60; ++ break; ++ default: ++ mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); ++ return -1; ++ } ++ ++ return sdramCasLat; ++} ++ ++ ++/******************************************************************************* ++* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - ++* ++* DESCRIPTION: ++* add support in power management. ++* ++* ++* INPUT: ++* None ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* None ++* ++*******************************************************************************/ ++ ++MV_VOID mvDramIfSelfRefreshSet() ++{ ++ MV_U32 operReg; ++ ++ operReg = MV_REG_READ(SDRAM_OPERATION_REG); ++ MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); ++ /* Read until register is reset to 0 */ ++ while(MV_REG_READ(SDRAM_OPERATION_REG)); ++} ++/******************************************************************************* ++* mvDramIfDimGetSPDversion - return DIMM SPD version. ++* ++* DESCRIPTION: ++* This function prints the DRAM controller information. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) ++{ ++ MV_DIMM_INFO dimmInfo; ++ if (bankNum >= MV_DRAM_MAX_CS ) ++ { ++ DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); ++ return ; ++ } ++ memset(&dimmInfo,0,sizeof(dimmInfo)); ++ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); ++ return ; ++ } ++ *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; ++ *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; ++} ++/******************************************************************************* ++* mvDramIfShow - Show DRAM controller information. ++* ++* DESCRIPTION: ++* This function prints the DRAM controller information. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++void mvDramIfShow(void) ++{ ++ int i, sdramCasLat, sdramCsSize; ++ MV_U32 Major=0, Minor=0; ++ ++ mvOsOutput("DRAM Controller info:\n"); ++ ++ mvOsOutput("Total DRAM "); ++ mvSizePrint(mvDramIfSizeGet()); ++ mvOsOutput("\n"); ++ ++ for(i = 0; i < MV_DRAM_MAX_CS; i++) ++ { ++ sdramCsSize = mvDramIfBankSizeGet(i); ++ if (sdramCsSize) ++ { ++ if (0 == (i & 1)) ++ { ++ mvDramIfDimGetSPDversion(&Major, &Minor,i); ++ mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); ++ } ++ mvOsOutput("\tDRAM CS[%d] ", i); ++ mvSizePrint(sdramCsSize); ++ mvOsOutput("\n"); ++ } ++ } ++ sdramCasLat = mvDramIfCalGet(); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) ++ { ++ mvOsOutput("ECC enabled, "); ++ } ++ else ++ { ++ mvOsOutput("ECC Disabled, "); ++ } ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) ++ { ++ mvOsOutput("Registered DIMM\n"); ++ } ++ else ++ { ++ mvOsOutput("Non registered DIMM\n"); ++ } ++ ++ mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); ++} ++/******************************************************************************* ++* mvDramIfGetFirstCS - find the DRAM bank on the lower address ++* ++* ++* DESCRIPTION: ++* This function return the fisrt CS on address 0 ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* SDRAM_CS0 or SDRAM_CS2 ++* ++*******************************************************************************/ ++MV_U32 mvDramIfGetFirstCS(void) ++{ ++ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; ++ ++ if (DRAM_CS_Order[0] == N_A) ++ { ++ mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); ++#endif ++ ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) ++ { ++ DRAM_CS_Order[0] = SDRAM_CS2; ++ DRAM_CS_Order[1] = SDRAM_CS3; ++ DRAM_CS_Order[2] = SDRAM_CS0; ++ DRAM_CS_Order[3] = SDRAM_CS1; ++ ++ return SDRAM_CS2; ++ } ++#endif ++ DRAM_CS_Order[0] = SDRAM_CS0; ++ DRAM_CS_Order[1] = SDRAM_CS1; ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ DRAM_CS_Order[2] = SDRAM_CS2; ++ DRAM_CS_Order[3] = SDRAM_CS3; ++#endif ++ return SDRAM_CS0; ++ } ++ return DRAM_CS_Order[0]; ++} ++/******************************************************************************* ++* mvDramIfGetCSorder - ++* ++* ++* DESCRIPTION: ++* This function return the fisrt CS on address 0 ++* ++* INPUT: ++* CS number. ++* ++* OUTPUT: ++* CS order. ++* ++* RETURN: ++* SDRAM_CS0 or SDRAM_CS2 ++* ++* NOTE: mvDramIfGetFirstCS must be caled before this subroutine ++*******************************************************************************/ ++MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) ++{ ++ return DRAM_CS_Order[csOrder]; ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,172 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfh ++#define __INCmvDramIfh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* includes */ ++#include "ddr2/mvDramIfRegs.h" ++#include "ddr2/mvDramIfConfig.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* defines */ ++/* DRAM Timing parameters */ ++#define SDRAM_TWR 15 /* ns tWr */ ++#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ ++#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ ++#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ ++#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ ++ ++#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ ++#define ECC_DISABLE 1 /* Force ECC to Disable */ ++#define ECC_ENABLE 0 /* Force ECC to ENABLE */ ++/* typedefs */ ++ ++/* enumeration for memory types */ ++typedef enum _mvMemoryType ++{ ++ MEM_TYPE_SDRAM, ++ MEM_TYPE_DDR1, ++ MEM_TYPE_DDR2 ++}MV_MEMORY_TYPE; ++ ++/* enumeration for DDR2 supported CAS Latencies */ ++typedef enum _mvDimmDdr2Cas ++{ ++ DDR2_CL_3 = 0x08, ++ DDR2_CL_4 = 0x10, ++ DDR2_CL_5 = 0x20, ++ DDR2_CL_6 = 0x40, ++ DDR2_CL_FAULT ++} MV_DIMM_DDR2_CAS; ++ ++ ++typedef struct _mvDramBankInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ ++ MV_U32 numberOfDevices; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ MV_BOOL registeredAddrAndControlInputs; ++ MV_BOOL registeredDQMBinputs; ++ ++}MV_DRAM_BANK_INFO; ++ ++#include "ddr2/spd/mvSpd.h" ++ ++/* mvDramIf.h API list */ ++MV_VOID mvDramIfBasicAsmInit(MV_VOID); ++MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); ++MV_VOID _mvDramIfConfig(int entryNum); ++ ++MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); ++MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); ++MV_U32 mvDramIfSizeGet(MV_VOID); ++MV_U32 mvDramIfCalGet(void); ++MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); ++MV_VOID mvDramIfSelfRefreshSet(void); ++void mvDramIfShow(void); ++MV_U32 mvDramIfGetFirstCS(void); ++MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); ++MV_U32 mvDramCsSizeGet(MV_U32 csNum); ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,157 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfConfigh ++#define __INCmvDramIfConfigh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* includes */ ++ ++/* defines */ ++ ++/* registers defaults values */ ++ ++#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) ++ ++#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ ++ (SDRAM_SRCLK_KEPT | \ ++ SDRAM_CLK1DRV_NORMAL | \ ++ (BIT28 | BIT29)) ++ ++#define SDRAM_ADDR_CTRL_DV 2 ++ ++#define SDRAM_TIMING_CTRL_LOW_REG_DV \ ++ ((0x2 << SDRAM_TRCD_OFFS) | \ ++ (0x2 << SDRAM_TRP_OFFS) | \ ++ (0x1 << SDRAM_TWR_OFFS) | \ ++ (0x0 << SDRAM_TWTR_OFFS) | \ ++ (0x5 << SDRAM_TRAS_OFFS) | \ ++ (0x1 << SDRAM_TRRD_OFFS)) ++ ++/* Note: value of 0 in register means one cycle, 1 means two and so on */ ++#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ ++ ((0x0 << SDRAM_TR2R_OFFS) | \ ++ (0x0 << SDRAM_TR2W_W2R_OFFS) | \ ++ (0x1 << SDRAM_TW2W_OFFS)) ++ ++#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN ++ ++/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ ++/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++ ++#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 ++#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F ++#ifdef MV78XX0 ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 ++#else ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 ++#endif ++ ++#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C ++#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F ++#ifdef MV78XX0 ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 ++#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 ++#else ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 ++#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 ++#endif ++ ++/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ ++#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++/* DDR SDRAM Mode Register default value */ ++#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) ++/* DDR SDRAM Timing parameter default values */ ++#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 ++#define SDRAM_TRFC_DEFAULT_VALUE 0x34 ++#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE ++#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) ++ ++#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) ++ ++#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 ++#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 ++#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,423 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDramIfRegsh ++#define __INCmvDramIfRegsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* DDR SDRAM Controller Address Decode Registers */ ++ /* SDRAM CSn Base Address Register (SCBAR) */ ++#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) ++#define SCBAR_BASE_OFFS 16 ++#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) ++#define SCBAR_BASE_ALIGNMENT 0x10000 ++ ++/* SDRAM CSn Size Register (SCSR) */ ++#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) ++#define SCSR_SIZE_OFFS 24 ++#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) ++#define SCSR_SIZE_ALIGNMENT 0x1000000 ++#define SCSR_WIN_EN BIT0 ++ ++/* configuration register */ ++#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400) ++#define SDRAM_REFRESH_OFFS 0 ++#define SDRAM_REFRESH_MAX 0x3FFF ++#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) ++#define SDRAM_DWIDTH_OFFS 15 ++#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_REGISTERED (1 << 17) ++#define SDRAM_ECC_OFFS 18 ++#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) ++#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) ++#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) ++#define SDRAM_IERR_OFFS 19 ++#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) ++#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) ++#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) ++#define SDRAM_SRMODE_OFFS 24 ++#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) ++#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) ++#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) ++ ++/* dunit control low register */ ++#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404) ++#define SDRAM_2T_OFFS 4 ++#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) ++#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) ++ ++#define SDRAM_SRCLK_OFFS 5 ++#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_CTRL_POS_OFFS 6 ++#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CLK1DRV_OFFS 12 ++#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK2DRV_OFFS 13 ++#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) ++#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) ++#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) ++#define SDRAM_SB_OUT_DEL_OFFS 20 ++#define SDRAM_SB_OUT_DEL_MAX 0xf ++#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS )) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ memset(pBankInfo, 0, sizeof(*pBankInfo)); ++ ++ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); ++ return MV_FAIL; ++ } ++ if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); ++ return MV_FAIL; ++ } ++ /* convert Dimm info to Bank info */ ++ cpyDimm2BankInfo(&dimmInfo, pBankInfo); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. ++* ++* DESCRIPTION: ++* Convert a Dimm info struct into a bank info struct. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* pBankInfo - DRAM bank information struct. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, ++ MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ pBankInfo->memoryType = pDimmInfo->memoryType; ++ ++ /* DIMM dimensions */ ++ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; ++ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; ++ pBankInfo->dataWidth = pDimmInfo->dataWidth; ++ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; ++ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; ++ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; ++ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; ++ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; ++ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; ++ ++ /* DIMM timing parameters */ ++ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; ++ ++ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; ++ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; ++ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; ++ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; ++ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; ++ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; ++ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; ++ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; ++ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; ++ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / ++ pDimmInfo->numOfModuleBanks; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ ++ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || ++ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) ++ { ++ if (pDimmInfo->dimmAttributes & BIT1) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ ++ { ++ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ ++ return; ++} ++/******************************************************************************* ++* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdCpy(MV_VOID) ++{ ++ MV_U32 i; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the DIMM 1 SPD */ ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ twsiSlave.offset = i; ++ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) ) ++ { ++ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); ++ return MV_FAIL; ++ } ++ mvOsDelay(5); ++ } ++ ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdGet - Get the SPD parameters. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters into given struct parameter. ++* ++* INPUT: ++* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. ++* ++* OUTPUT: ++* pDimmInfo - DIMM information structure. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) ++{ ++ MV_U32 i; ++ MV_U32 density = 1; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = (dimmNum == 0) ? ++ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the dimmInfo structure*/ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ pDimmInfo->spdRawData[i] = data[i]; ++ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); ++ } ++ ++ DB(mvOsPrintf("DRAM SPD Information:\n")); ++ ++ /* Memory type (DDR / SDRAM) */ ++ switch (data[DIMM_MEM_TYPE]) ++ { ++ case (DIMM_MEM_TYPE_SDRAM): ++ pDimmInfo->memoryType = MEM_TYPE_SDRAM; ++ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR1): ++ pDimmInfo->memoryType = MEM_TYPE_DDR1; ++ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR2): ++ pDimmInfo->memoryType = MEM_TYPE_DDR2; ++ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); ++ break; ++ default: ++ mvOsPrintf("ERROR: Undefined memory type!\n"); ++ return MV_ERROR; ++ } ++ ++ ++ /* Number Of Row Addresses */ ++ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; ++ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); ++ ++ /* Number Of Column Addresses */ ++ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; ++ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); ++ ++ /* Number Of Module Banks */ ++ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", ++ pDimmInfo->numOfModuleBanks)); ++ ++ /* Number of module banks encoded differently for DDR2 */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; ++ ++ /* Data Width */ ++ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); ++ ++ /* Minimum Cycle Time At Max CasLatancy */ ++ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); ++ ++ /* Error Check Type */ ++ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; ++ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", ++ pDimmInfo->errorCheckType)); ++ ++ /* Refresh Interval */ ++ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; ++ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", ++ pDimmInfo->refreshInterval)); ++ ++ /* Sdram Width */ ++ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; ++ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); ++ ++ /* Error Check Data Width */ ++ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", ++ pDimmInfo->errorCheckDataWidth)); ++ ++ /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; ++ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", ++ pDimmInfo->burstLengthSupported)); ++ ++ /* Number Of Banks On Each Device */ ++ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", ++ pDimmInfo->numOfBanksOnEachDevice)); ++ ++ /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; ++ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", ++ pDimmInfo->suportedCasLatencies)); ++ ++ /* For DDR2 only, get the DIMM type information */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ { ++ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; ++ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", ++ pDimmInfo->dimmTypeInfo)); ++ } ++ ++ /* SDRAM Modules Attributes */ ++ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; ++ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", ++ pDimmInfo->dimmAttributes)); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); ++ ++ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; ++ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", ++ pDimmInfo->minRowPrechargeTime)); ++ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; ++ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", ++ pDimmInfo->minRowActiveToRowActive)); ++ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; ++ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", ++ pDimmInfo->minRasToCasDelay)); ++ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; ++ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", ++ pDimmInfo->minRasPulseWidth)); ++ ++ /* DIMM Bank Density */ ++ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; ++ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", ++ pDimmInfo->dimmBankDensity)); ++ ++ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ ++ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; ++ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", ++ pDimmInfo->minWriteRecoveryTime)); ++ ++ /* Only DDR2 includes Internal Write To Read Command Delay field. */ ++ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", ++ pDimmInfo->minWriteToReadCmdDelay)); ++ ++ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ ++ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", ++ pDimmInfo->minReadToPrechCmdDelay)); ++ ++ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ ++ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; ++ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", ++ pDimmInfo->minRefreshToActiveCmd)); ++ ++ /* calculating the sdram density. Representing device density from */ ++ /* bit 20 to allow representation of 4GB and above. */ ++ /* For example, if density is 512Mbit 0x20000000, will be represent in */ ++ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ ++ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ ++ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); ++ pDimmInfo->deviceDensity = density * ++ pDimmInfo->numOfBanksOnEachDevice * ++ pDimmInfo->sdramWidth; ++ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); ++ ++ /* Number of devices includeing Error correction */ ++ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * ++ pDimmInfo->numOfModuleBanks; ++ DB(mvOsPrintf("DRAM numberOfDevices %d\n", ++ pDimmInfo->numberOfDevices)); ++ ++ pDimmInfo->size = 0; ++ ++ /* Note that pDimmInfo->size is in MB units */ ++ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 8; /* Equal to 8MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 4096; /* Equal to 4GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 8192; /* Equal to 8GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 16384; /* Equal to 16GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ ++ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; ++ ++ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdPrint - Print the SPD parameters. ++* ++* DESCRIPTION: ++* Print the Dimm SPD parameters. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID dimmSpdPrint(MV_U32 dimmNum) ++{ ++ MV_DIMM_INFO dimmInfo; ++ MV_U32 i, temp = 0; ++ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; ++ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; ++ MV_U32 busClkPs; ++ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, ++ temp_buf[40], *spdRawData; ++ ++ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ ++ ++ spdRawData = dimmInfo.spdRawData; ++ ++ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) ++ { ++ mvOsOutput("ERROR: Could not read SPD information!\n"); ++ return; ++ } ++ ++ /* find Manufactura of Dimm Module */ ++ mvOsOutput("\nManufacturer's JEDEC ID Code: "); ++ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) ++ { ++ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); ++ } ++ mvOsOutput("\n"); ++ ++ /* Manufacturer's Specific Data */ ++ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; ++ } ++ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); ++ ++ /* Module Part Number */ ++ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; ++ } ++ mvOsOutput("Module Part Number: %s\n", temp_buf); ++ ++ /* Module Serial Number */ ++ for(i = 0; i < sizeof(MV_U32); i++) ++ { ++ temp |= spdRawData[95+i] << 8*i; ++ } ++ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, ++ (long)temp); ++ ++ /* find Manufac-Data of Dimm Module */ ++ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", ++ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), ++ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); ++ /* find modul_revision of Dimm Module */ ++ mvOsOutput("Module Revision: %d.%d\n", ++ spdRawData[62]/10, spdRawData[62]%10); ++ ++ /* find manufac_place of Dimm Module */ ++ mvOsOutput("manufac_place: %d\n", spdRawData[72]); ++ ++ /* go over the first 35 I2C data bytes */ ++ for(i = 2 ; i <= 35 ; i++) ++ switch(i) ++ { ++ case 2: /* Memory type (DDR1/2 / SDRAM) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ mvOsOutput("Dram Type is: SDRAM\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ mvOsOutput("Dram Type is: SDRAM DDR1\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ mvOsOutput("Dram Type is: SDRAM DDR2\n"); ++ else ++ mvOsOutput("Dram Type unknown\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 3: /* Number Of Row Addresses */ ++ mvOsOutput("Module Number of row addresses: %d\n", ++ dimmInfo.numOfRowAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 4: /* Number Of Column Addresses */ ++ mvOsOutput("Module Number of col addresses: %d\n", ++ dimmInfo.numOfColAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 5: /* Number Of Module Banks */ ++ mvOsOutput("Number of Banks on Mod.: %d\n", ++ dimmInfo.numOfModuleBanks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 6: /* Data Width */ ++ mvOsOutput("Module Data Width: %d bit\n", ++ dimmInfo.dataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 8: /* Voltage Interface */ ++ switch(spdRawData[i]) ++ { ++ case 0x0: ++ mvOsOutput("Module is TTL_5V_TOLERANT\n"); ++ break; ++ case 0x1: ++ mvOsOutput("Module is LVTTL\n"); ++ break; ++ case 0x2: ++ mvOsOutput("Module is HSTL_1_5V\n"); ++ break; ++ case 0x3: ++ mvOsOutput("Module is SSTL_3_3V\n"); ++ break; ++ case 0x4: ++ mvOsOutput("Module is SSTL_2_5V\n"); ++ break; ++ case 0x5: ++ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) ++ { ++ mvOsOutput("Module is SSTL_1_8V\n"); ++ break; ++ } ++ default: ++ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); ++ break; ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 9: /* Minimum Cycle Time At Max CasLatancy */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 10: /* Clock To Data Out */ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 11: /* Error Check Type */ ++ mvOsOutput("Error Check Type (0=NONE): %d\n", ++ dimmInfo.errorCheckType); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 12: /* Refresh Interval */ ++ mvOsOutput("Refresh Rate: %x\n", ++ dimmInfo.refreshInterval); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 13: /* Sdram Width */ ++ mvOsOutput("Sdram Width: %d bits\n", ++ dimmInfo.sdramWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 14: /* Error Check Data Width */ ++ mvOsOutput("Error Check Data Width: %d bits\n", ++ dimmInfo.errorCheckDataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 15: /* Minimum Clock Delay is unsupported */ ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ mvOsOutput("Minimum Clk Delay back to back: %d\n", ++ spdRawData[i]); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 16: /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ mvOsOutput("Burst Length Supported: "); ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ if (dimmInfo.burstLengthSupported & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.burstLengthSupported & BIT1) ++ mvOsOutput("2, "); ++ } ++ if (dimmInfo.burstLengthSupported & BIT2) ++ mvOsOutput("4, "); ++ if (dimmInfo.burstLengthSupported & BIT3) ++ mvOsOutput("8, "); ++ ++ mvOsOutput(" Bit \n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 17: /* Number Of Banks On Each Device */ ++ mvOsOutput("Number Of Banks On Each Chip: %d\n", ++ dimmInfo.numOfBanksOnEachDevice); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 18: /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ mvOsOutput("Suported Cas Latencies: (CL) "); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ for (k = 0; k <=7; k++) ++ { ++ if (dimmInfo.suportedCasLatencies & (1 << k)) ++ mvOsOutput("%d, ", k+1); ++ } ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.suportedCasLatencies & BIT1) ++ mvOsOutput("1.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("2.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("3.5, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("4, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("5, "); ++ } ++ else ++ mvOsOutput("?.?, "); ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 20: /* DDR2 DIMM type info */ ++ if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) ++ mvOsOutput("Registered DIMM (RDIMM)\n"); ++ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) ++ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); ++ else ++ mvOsOutput("Unknown DIMM type.\n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 21: /* SDRAM Modules Attributes */ ++ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" Bufferd DQMB Input: Yes \n"); ++ else ++ mvOsOutput(" Bufferd DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" Registered DQMB Inputs: Yes \n"); ++ else ++ mvOsOutput(" Registered DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" redundant Row Addressing: Yes \n"); ++ else ++ mvOsOutput(" redundant Row Addressing: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch On-Card Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", ++ (dimmInfo.dimmAttributes & 0x3) + 1); ++ ++ mvOsOutput(" Number of PLLs on the DIMM: %d\n", ++ ((dimmInfo.dimmAttributes) >> 2) & 0x3); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" Analysis probe installed: Yes \n"); ++ else ++ mvOsOutput(" Analysis probe installed: No \n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 22: /* Suported AutoPreCharge */ ++ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Early Ras Precharge: Yes \n"); ++ else ++ mvOsOutput(" Early Ras Precharge: No \n"); ++ ++ if ( spdRawData[i] & BIT1 ) ++ mvOsOutput(" AutoPreCharge: Yes \n"); ++ else ++ mvOsOutput(" AutoPreCharge: No \n"); ++ ++ if ( spdRawData[i] & BIT2 ) ++ mvOsOutput(" Precharge All: Yes \n"); ++ else ++ mvOsOutput(" Precharge All: No \n"); ++ ++ if ( spdRawData[i] & BIT3 ) ++ mvOsOutput(" Write 1/ReadBurst: Yes \n"); ++ else ++ mvOsOutput(" Write 1/ReadBurst: No \n"); ++ ++ if ( spdRawData[i] & BIT4 ) ++ mvOsOutput(" lower VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" lower VCC tolerance: 10%%\n"); ++ ++ if ( spdRawData[i] & BIT5 ) ++ mvOsOutput(" upper VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" upper VCC tolerance: 10%%\n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ ++ if ( !(spdRawData[i] & BIT4) ) ++ mvOsOutput(" lower VCC tolerance: 0.2V\n"); ++ ++ if ( !(spdRawData[i] & BIT5) ) ++ mvOsOutput(" upper VCC tolerance: 0.2V\n"); ++ ++ if ( spdRawData[i] & BIT6 ) ++ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); ++ else ++ mvOsOutput(" Concurrent Auto Preharge: No \n"); ++ ++ if ( spdRawData[i] & BIT7 ) ++ mvOsOutput(" Supports Fast AP: Yes \n"); ++ else ++ mvOsOutput(" Supports Fast AP: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 23: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ ++ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 25: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ } ++ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = 0; ++ rightOfPoint = time_tmp; ++ } ++ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 27: /* Minimum Row Precharge Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ ++ trp_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 28: /* Minimum Row Active to Row Active Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " ++ "%d.%d = in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 29: /* Minimum Ras-To-Cas Delay */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; ++ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 30: /* Minimum Ras Pulse Width */ ++ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " ++ "in Clk cycles %d\n", spdRawData[i], tras_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 31: /* Module Bank Density */ ++ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("8MB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("4GB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("8GB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("16GB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 32: /* Address And Command Setup Time (measured in ns/1000) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 33: /* Address And Command Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 34: /* Data Input Setup Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 35: /* Data Input Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 36: /* Relevant for DDR2 only: Write Recovery Time */ ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; ++ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ } ++ ++} ++ ++ ++/* ++ * translate ns.ns/10 coding of SPD timing values ++ * into ps unit values ++ */ ++/******************************************************************************* ++* cas2ps - Translate x.y ns parameter to pico-seconds values ++* ++* DESCRIPTION: ++* This function translates x.y nano seconds to its value in pico seconds. ++* For example 3.75ns will return 3750. ++* ++* INPUT: ++* spd_byte - DIMM SPD byte. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* value in pico seconds. ++* ++*******************************************************************************/ ++static MV_U32 cas2ps(MV_U8 spd_byte) ++{ ++ MV_U32 ns, ns10; ++ ++ /* isolate upper nibble */ ++ ns = (spd_byte >> 4) & 0x0F; ++ /* isolate lower nibble */ ++ ns10 = (spd_byte & 0x0F); ++ ++ if( ns10 < 10 ) { ++ ns10 *= 10; ++ } ++ else if( ns10 == 10 ) ++ ns10 = 25; ++ else if( ns10 == 11 ) ++ ns10 = 33; ++ else if( ns10 == 12 ) ++ ns10 = 66; ++ else if( ns10 == 13 ) ++ ns10 = 75; ++ else ++ { ++ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); ++ } ++ ++ return (ns*1000 + ns10*10); ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,192 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDram ++#define __INCmvDram ++ ++#include "ddr2/mvDramIf.h" ++#include "twsi/mvTwsi.h" ++ ++#define MAX_DIMM_NUM 2 ++#define SPD_SIZE 128 ++ ++/* Dimm spd offsets */ ++#define DIMM_MEM_TYPE 2 ++#define DIMM_ROW_NUM 3 ++#define DIMM_COL_NUM 4 ++#define DIMM_MODULE_BANK_NUM 5 ++#define DIMM_DATA_WIDTH 6 ++#define DIMM_VOLT_IF 8 ++#define DIMM_MIN_CC_AT_MAX_CAS 9 ++#define DIMM_ERR_CHECK_TYPE 11 ++#define DIMM_REFRESH_INTERVAL 12 ++#define DIMM_SDRAM_WIDTH 13 ++#define DIMM_ERR_CHECK_DATA_WIDTH 14 ++#define DIMM_MIN_CLK_DEL 15 ++#define DIMM_BURST_LEN_SUP 16 ++#define DIMM_DEV_BANK_NUM 17 ++#define DIMM_SUP_CAL 18 ++#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ ++#define DIMM_BUF_ADDR_CONT_IN 21 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 ++#define DIMM_MIN_ROW_PRECHARGE_TIME 27 ++#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 ++#define DIMM_MIN_RAS_TO_CAS_DELAY 29 ++#define DIMM_MIN_RAS_PULSE_WIDTH 30 ++#define DIMM_BANK_DENSITY 31 ++#define DIMM_MIN_WRITE_RECOVERY_TIME 36 ++#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 ++#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 ++#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 ++#define DIMM_SPD_VERSION 62 ++ ++/* Dimm Memory Type values */ ++#define DIMM_MEM_TYPE_SDRAM 0x4 ++#define DIMM_MEM_TYPE_DDR1 0x7 ++#define DIMM_MEM_TYPE_DDR2 0x8 ++ ++#define DIMM_MODULE_MANU_OFFS 64 ++#define DIMM_MODULE_MANU_SIZE 8 ++#define DIMM_MODULE_VEN_OFFS 73 ++#define DIMM_MODULE_VEN_SIZE 25 ++#define DIMM_MODULE_ID_OFFS 99 ++#define DIMM_MODULE_ID_SIZE 18 ++ ++/* enumeration for voltage levels. */ ++typedef enum _mvDimmVoltageIf ++{ ++ TTL_5V_TOLERANT, ++ LVTTL, ++ HSTL_1_5V, ++ SSTL_3_3V, ++ SSTL_2_5V, ++ VOLTAGE_UNKNOWN, ++} MV_DIMM_VOLTAGE_IF; ++ ++ ++/* enumaration for SDRAM CAS Latencies. */ ++typedef enum _mvDimmSdramCas ++{ ++ SD_CL_1 =1, ++ SD_CL_2, ++ SD_CL_3, ++ SD_CL_4, ++ SD_CL_5, ++ SD_CL_6, ++ SD_CL_7, ++ SD_FAULT ++}MV_DIMM_SDRAM_CAS; ++ ++ ++/* DIMM information structure */ ++typedef struct _mvDimmInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ ++ ++ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 numOfModuleBanks; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ MV_U32 dimmBankDensity; ++ MV_U32 dimmTypeInfo; /* DDR2 only */ ++ MV_U32 dimmAttributes; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ ++ MV_U32 numberOfDevices; ++ ++} MV_DIMM_INFO; ++ ++ ++MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); ++MV_VOID dimmSpdPrint(MV_U32 dimmNum); ++MV_STATUS dimmSpdCpy(MV_VOID); ++ ++#endif /* __INCmvDram */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,2952 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvEth.c - Marvell's Gigabit Ethernet controller low level driver ++* ++* DESCRIPTION: ++* This file introduce OS independent APIs to Marvell's Gigabit Ethernet ++* controller. This Gigabit Ethernet Controller driver API controls ++* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). ++* 2) Data flow (i.e. port Send, Receive etc'). ++* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) ++* 4) MIB counters support (ethReadMibCounter) ++* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) ++* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. ++* This struct includes configuration information as well as driver ++* internal data needed for its operations. ++* ++* Supported Features: ++* - OS independent. All required OS services are implemented via external ++* OS dependent components (like osLayer or ethOsg) ++* - The user is free from Rx/Tx queue managing. ++* - Simple Gigabit Ethernet port operation API. ++* - Simple Gigabit Ethernet port data flow API. ++* - Data flow and operation API support per queue functionality. ++* - Support cached descriptors for better performance. ++* - PHY access and control API. ++* - Port Configuration API. ++* - Full control over Special and Other Multicast MAC tables. ++* ++*******************************************************************************/ ++/* includes */ ++#include "mvTypes.h" ++#include "mv802_3.h" ++#include "mvDebug.h" ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "eth-phy/mvEthPhy.h" ++#include "eth/mvEth.h" ++#include "eth/gbe/mvEthGbe.h" ++#include "cpu/mvCpu.h" ++ ++#ifdef INCLUDE_SYNC_BARR ++#include "sys/mvCpuIf.h" ++#endif ++ ++#ifdef MV_RT_DEBUG ++# define ETH_DEBUG ++#endif ++ ++ ++/* locals */ ++MV_BOOL ethDescInSram; ++MV_BOOL ethDescSwCoher; ++ ++/* This array holds the control structure of each port */ ++ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS]; ++ ++/* Ethernet Port Local routines */ ++ ++static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); ++ ++static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); ++ ++static void ethSetUcastTable(int portNo, int queue); ++ ++static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue); ++static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); ++static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); ++ ++static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf); ++static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size, ++ MV_ULONG* pPhysAddr, MV_U32 *memHandle); ++ ++static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); ++ ++static void mvEthPortSgmiiConfig(int port); ++ ++ ++ ++/******************************************************************************/ ++/* EthDrv Initialization functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthHalInit - Initialize the Giga Ethernet unit ++* ++* DESCRIPTION: ++* This function initialize the Giga Ethernet unit. ++* 1) Configure Address decode windows of the unit ++* 2) Set registers to HW default values. ++* 3) Clear and Disable interrupts ++* ++* INPUT: NONE ++* ++* RETURN: NONE ++* ++* NOTE: this function is called once in the boot process. ++*******************************************************************************/ ++void mvEthHalInit(void) ++{ ++ int port; ++ ++ /* Init static data structures */ ++ for (port=0; port 0) ++ { ++ isSram = MV_TRUE; ++ #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) ++ isSwCoher = MV_TRUE; ++ #else ++ isSwCoher = MV_FALSE; ++ #endif ++ } ++#endif /* ETH_DESCR_IN_SRAM */ ++ ++ if(pIsSram != NULL) ++ *pIsSram = isSram; ++ ++ if(pIsSwCoher != NULL) ++ *pIsSwCoher = isSwCoher; ++} ++ ++ ++ ++/******************************************************************************/ ++/* Port Initialization functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthPortInit - Initialize the Ethernet port driver ++* ++* DESCRIPTION: ++* This function initialize the ethernet port. ++* 1) Allocate and initialize internal port Control structure. ++* 2) Create RX and TX descriptor rings for default RX and TX queues ++* 3) Disable RX and TX operations, clear cause registers and ++* mask all interrupts. ++* 4) Set all registers to default values and clean all MAC tables. ++* ++* INPUT: ++* int portNo - Ethernet port number ++* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure ++* ++* RETURN: ++* void* - ethernet port handler, that should be passed to the most other ++* functions dealing with this port. ++* ++* NOTE: This function is called once per port when loading the eth module. ++*******************************************************************************/ ++void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit) ++{ ++ int queue, descSize; ++ ETH_PORT_CTRL* pPortCtrl; ++ ++ /* Check validity of parameters */ ++ if( (portNo >= (int)mvCtrlEthMaxPortGet()) || ++ (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) || ++ (pEthPortInit->maxRxPktSize < 1518) ) ++ { ++ mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); ++ return NULL; ++ } ++ if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) ++ { ++ mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", ++ portNo, pEthPortInit->rxDefQ); ++ return NULL; ++ } ++ ++ pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) ); ++ if(pPortCtrl == NULL) ++ { ++ mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", ++ (int)sizeof(ETH_PORT_CTRL), portNo); ++ return NULL; ++ } ++ ++ memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) ); ++ ethPortCtrl[portNo] = pPortCtrl; ++ ++ pPortCtrl->portState = MV_UNDEFINED_STATE; ++ ++ pPortCtrl->portNo = portNo; ++ ++ pPortCtrl->osHandle = pEthPortInit->osHandle; ++ ++ /* Copy Configuration parameters */ ++ pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; ++ pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; ++ pPortCtrl->portConfig.ejpMode = 0; ++ ++ for( queue=0; queuerxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; ++ } ++ for( queue=0; queuetxQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; ++ } ++ ++ mvEthPortDisable(pPortCtrl); ++ ++ /* Set the board information regarding PHY address */ ++ mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) ); ++ ++ /* Create all requested RX queues */ ++ for(queue=0; queuerxQueueConfig[queue].descrNum == 0) ++ continue; ++ ++ /* Allocate memory for RX descriptors */ ++ descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = ++ ethAllocDescrMemory(pPortCtrl, descSize, ++ &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, ++ &pPortCtrl->rxQueue[queue].descBuf.memHandle); ++ pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; ++ if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", ++ pPortCtrl->portNo, queue, descSize, ++ ethDescInSram ? "SRAM" : "DRAM", ++ pPortCtrl->rxQueueConfig[queue].descrNum); ++ return NULL; ++ } ++ ++ ethInitRxDescRing(pPortCtrl, queue); ++ } ++ /* Create TX queues */ ++ for(queue=0; queuetxQueueConfig[queue].descrNum == 0) ++ continue; ++ ++ /* Allocate memory for TX descriptors */ ++ descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = ++ ethAllocDescrMemory(pPortCtrl, descSize, ++ &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, ++ &pPortCtrl->txQueue[queue].descBuf.memHandle); ++ pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; ++ if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", ++ pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", ++ pPortCtrl->txQueueConfig[queue].descrNum); ++ return NULL; ++ } ++ ++ ethInitTxDescRing(pPortCtrl, queue); ++ } ++ mvEthDefaultsSet(pPortCtrl); ++ ++ pPortCtrl->portState = MV_IDLE; ++ return pPortCtrl; ++} ++ ++/******************************************************************************* ++* ethPortFinish - Finish the Ethernet port driver ++* ++* DESCRIPTION: ++* This function finish the ethernet port. ++* 1) Down ethernet port if needed. ++* 2) Delete RX and TX descriptor rings for all created RX and TX queues ++* 3) Free internal port Control structure. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: NONE. ++* ++*******************************************************************************/ ++void mvEthPortFinish(void* pPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ int queue, portNo = pPortCtrl->portNo; ++ ++ if(pPortCtrl->portState == MV_ACTIVE) ++ { ++ mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", ++ portNo); ++ mvEthPortDisable(pPortHndl); ++ } ++ ++ /* Free all allocated RX queues */ ++ for(queue=0; queuerxQueue[queue].descBuf); ++ } ++ ++ /* Free all allocated TX queues */ ++ for(queue=0; queuetxQueue[queue].descBuf); ++ } ++ ++ /* Free port control structure */ ++ mvOsFree(pPortCtrl); ++ ++ ethPortCtrl[portNo] = NULL; ++} ++ ++/******************************************************************************* ++* mvEthDefaultsSet - Set defaults to the ethernet port ++* ++* DESCRIPTION: ++* This function set default values to the ethernet port. ++* 1) Clear Cause registers and Mask all interrupts ++* 2) Clear all MAC tables ++* 3) Set defaults to all registers ++* 4) Reset all created RX and TX descriptors ring ++* 5) Reset PHY ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure ++* NOTE: ++* This function update all the port configuration except those set ++* Initialy by the OsGlue by MV_ETH_PORT_INIT. ++* This function can be called after portDown to return the port setting ++* to defaults. ++*******************************************************************************/ ++MV_STATUS mvEthDefaultsSet(void* pPortHndl) ++{ ++ int ethPortNo, queue; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ MV_U32 txPrio; ++ MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; ++ MV_BOARD_MAC_SPEED boardMacCfg; ++ ++ ethPortNo = pPortCtrl->portNo; ++ ++ /* Clear Cause registers */ ++ MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0); ++ MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0); ++ ++ /* Mask all interrupts */ ++ MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0); ++ MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0); ++ ++ portCfgReg = PORT_CONFIG_VALUE; ++ portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; ++ ++ boardMacCfg = mvBoardMacSpeedGet(ethPortNo); ++ ++ if(boardMacCfg == BOARD_MAC_SPEED_100M) ++ { ++ portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; ++ } ++ else if(boardMacCfg == BOARD_MAC_SPEED_1000M) ++ { ++ portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; ++ } ++ else ++ { ++ portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; ++ } ++ ++ /* build PORT_SDMA_CONFIG_REG */ ++ portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); ++ portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); ++ ++#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \ ++ (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ) ++ /* some devices have restricted RX burst size when using HW coherency */ ++ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); ++#else ++ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); ++#endif ++ ++#if defined(MV_CPU_BE) ++ /* big endian */ ++# if defined(MV_ARM) ++ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | ++ ETH_TX_NO_DATA_SWAP_MASK | ++ ETH_DESC_SWAP_MASK); ++# elif defined(MV_PPC) ++ portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | ++ ETH_TX_DATA_SWAP_MASK | ++ ETH_NO_DESC_SWAP_MASK); ++# else ++# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" ++# endif /* MV_ARM / MV_PPC */ ++ ++#else /* MV_CPU_LE */ ++ /* little endian */ ++ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | ++ ETH_TX_NO_DATA_SWAP_MASK | ++ ETH_NO_DESC_SWAP_MASK); ++#endif /* MV_CPU_BE / MV_CPU_LE */ ++ ++ pPortCtrl->portRxQueueCmdReg = 0; ++ pPortCtrl->portTxQueueCmdReg = 0; ++ ++#if (MV_ETH_VERSION >= 4) ++ if(pPortCtrl->portConfig.ejpMode == MV_TRUE) ++ { ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK); ++ } ++ else ++ { ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0) ++ } ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++ ethSetUcastTable(ethPortNo, -1); ++ mvEthSetSpecialMcastTable(ethPortNo, -1); ++ mvEthSetOtherMcastTable(ethPortNo, -1); ++ ++ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; ++ ++ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); ++ ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); ++ ++ /* Update value of PortConfig register accordingly with all RxQueue types */ ++ pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; ++ pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; ++ pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; ++ pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; ++ ++ portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); ++ ++ /* Assignment of Tx CTRP of given queue */ ++ txPrio = 0; ++ ++ for(queue=0; queuetxQueue[queue]; ++ ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ ethResetTxDescRing(pPortCtrl, queue); ++ ++ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), ++ 0x3fffffff); ++ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), ++ 0x03ffffff); ++ } ++ else ++ { ++ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); ++ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); ++ } ++ } ++ ++ /* Assignment of Rx CRDP of given queue */ ++ for(queue=0; queueportNo; ++ ++ if( (pPortCtrl->portState != MV_ACTIVE) && ++ (pPortCtrl->portState != MV_PAUSED) ) ++ { ++ mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", ++ ethPortNo, pPortCtrl->portState); ++ return MV_BAD_STATE; ++ } ++ ++ ethPortNo = pPortCtrl->portNo; ++ ++ /* Enable port RX. */ ++ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); ++ ++ /* Enable port TX. */ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; ++ ++ pPortCtrl->portState = MV_ACTIVE; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* ethPortDown - Stop the Ethernet port activity. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure. ++* ++* NOTE : used for port link down. ++*******************************************************************************/ ++MV_STATUS mvEthPortDown(void* pEthPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ int ethPortNum = pPortCtrl->portNo; ++ unsigned int regData; ++ volatile int uDelay, mDelay; ++ ++ /* Stop Rx port activity. Check port Rx activity. */ ++ regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; ++ if(regData != 0) ++ { ++ /* Issue stop command for active channels only */ ++ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); ++ } ++ ++ /* Stop Tx port activity. Check port Tx activity. */ ++ regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; ++ if(regData != 0) ++ { ++ /* Issue stop command for active channels only */ ++ MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), ++ (regData << ETH_TXQ_DISABLE_OFFSET) ); ++ } ++ ++ /* Force link down */ ++/* ++ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); ++ regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); ++*/ ++ /* Wait for all Rx activity to terminate. */ ++ mDelay = 0; ++ do ++ { ++ if(mDelay >= RX_DISABLE_TIMEOUT_MSEC) ++ { ++ mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", ++ ethPortNum, regData); ++ break; ++ } ++ mvOsDelay(1); ++ mDelay++; ++ ++ /* Check port RX Command register that all Rx queues are stopped */ ++ regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); ++ } ++ while(regData & 0xFF); ++ ++ /* Wait for all Tx activity to terminate. */ ++ mDelay = 0; ++ do ++ { ++ if(mDelay >= TX_DISABLE_TIMEOUT_MSEC) ++ { ++ mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", ++ ethPortNum, regData); ++ break; ++ } ++ mvOsDelay(1); ++ mDelay++; ++ ++ /* Check port TX Command register that all Tx queues are stopped */ ++ regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); ++ } ++ while(regData & 0xFF); ++ ++ /* Double check to Verify that TX FIFO is Empty */ ++ mDelay = 0; ++ while(MV_TRUE) ++ { ++ do ++ { ++ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) ++ { ++ mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", ++ ethPortNum, regData); ++ break; ++ } ++ mvOsDelay(1); ++ mDelay++; ++ ++ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); ++ } ++ while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || ++ ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) ); ++ ++ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) ++ break; ++ ++ /* Double check */ ++ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); ++ if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && ++ ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) ) ++ { ++ break; ++ } ++ else ++ mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", ++ ethPortNum, mDelay, regData); ++ } ++ ++ /* Do NOT force link down */ ++/* ++ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); ++ regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); ++*/ ++ /* Wait about 2500 tclk cycles */ ++ uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000)); ++ mvOsUDelay(uDelay); ++ ++ pPortCtrl->portState = MV_PAUSED; ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* ethPortEnable - Enable the Ethernet port and Start RX and TX. ++* ++* DESCRIPTION: ++* This routine enable the Ethernet port and Rx and Tx activity: ++* ++* Note: Each Rx and Tx queue descriptor's list must be initialized prior ++* to calling this function (use etherInitTxDescRing for Tx queues and ++* etherInitRxDescRing for Rx queues). ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure. ++* ++* NOTE: main usage is to enable the port after ifconfig up. ++*******************************************************************************/ ++MV_STATUS mvEthPortEnable(void* pEthPortHndl) ++{ ++ int ethPortNo; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ MV_U32 portSerialCtrlReg; ++ ++ ethPortNo = pPortCtrl->portNo; ++ ++ /* Enable port */ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); ++ portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); ++ ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); ++ ++ mvEthMibCountersClear(pEthPortHndl); ++ ++ pPortCtrl->portState = MV_PAUSED; ++ ++ /* If Link is UP, Start RX and TX traffic */ ++ if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK) ++ return( mvEthPortUp(pEthPortHndl) ); ++ ++ return MV_NOT_READY; ++} ++ ++ ++/******************************************************************************* ++* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure. ++* ++* NOTE: main usage is to disable the port after ifconfig down. ++*******************************************************************************/ ++MV_STATUS mvEthPortDisable(void* pEthPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ int ethPortNum = pPortCtrl->portNo; ++ unsigned int regData; ++ volatile int mvDelay; ++ ++ if(pPortCtrl->portState == MV_ACTIVE) ++ { ++ /* Stop RX and TX activities */ ++ mvEthPortDown(pEthPortHndl); ++ } ++ ++ /* Reset the Enable bit in the Serial Control Register */ ++ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); ++ regData &= ~(ETH_PORT_ENABLE_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); ++ ++ /* Wait about 2500 tclk cycles */ ++ mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet())); ++ for(mvDelay; mvDelay>0; mvDelay--); ++ ++ pPortCtrl->portState = MV_IDLE; ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. ++* ++* DESCRIPTION: ++* This routine used to free buffers attached to the Tx ring and should ++* be called only when Giga Ethernet port is Down ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of TX queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. ++* ++* RETURN: ++* MV_EMPTY - There is no more buffers in this queue. ++* MV_OK - Buffer detached from the queue and pPktInfo structure ++* filled with relevant information. ++* ++*******************************************************************************/ ++MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ MV_PKT_INFO* pPktInfo; ++ ETH_TX_DESC* pTxDesc; ++ int port = pPortCtrl->portNo; ++ ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || ++ (pQueueCtrl->resource == 0) ) ++ { ++ /* Free next descriptor */ ++ pQueueCtrl->resource++; ++ pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr; ++ ++ /* pPktInfo is available only in descriptors which are last descriptors */ ++ pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo; ++ if (pPktInfo) ++ pPktInfo->status = pTxDesc->cmdSts; ++ ++ pTxDesc->cmdSts = 0x0; ++ pTxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); ++ ++ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); ++ ++ if (pPktInfo) ++ if (pPktInfo->status & ETH_TX_LAST_DESC_MASK) ++ return pPktInfo; ++ } ++ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ return NULL; ++} ++ ++ ++ ++/******************************************************************************* ++* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. ++* ++* DESCRIPTION: ++* This routine used to free buffers attached to the Rx ring and should ++* be called only when Giga Ethernet port is Down ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int rxQueue - Number of Rx queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to received packet. ++* ++* RETURN: ++* MV_EMPTY - There is no more buffers in this queue. ++* MV_OK - Buffer detached from the queue and pBufInfo structure ++* filled with relevant information. ++* ++*******************************************************************************/ ++MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_RX_DESC* pRxDesc; ++ MV_PKT_INFO* pPktInfo; ++ int port = pPortCtrl->portNo; ++ ++ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; ++ ++ if(pQueueCtrl->resource == 0) ++ { ++ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ ++ return NULL; ++ } ++ /* Free next descriptor */ ++ pQueueCtrl->resource--; ++ pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr; ++ pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo; ++ ++ pPktInfo->status = pRxDesc->cmdSts; ++ pRxDesc->cmdSts = 0x0; ++ pRxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); ++ ++ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); ++ return pPktInfo; ++} ++ ++ ++/******************************************************************************/ ++/* Port Configuration functions */ ++/******************************************************************************/ ++/******************************************************************************* ++* mvEthMruGet - Get MRU configuration for Max Rx packet size. ++* ++* INPUT: ++* MV_U32 maxRxPktSize - max packet size. ++* ++* RETURN: MV_U32 - MRU configuration. ++* ++*******************************************************************************/ ++static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) ++{ ++ MV_U32 portSerialCtrlReg = 0; ++ ++ if(maxRxPktSize > 9192) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; ++ else if(maxRxPktSize > 9022) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; ++ else if(maxRxPktSize > 1552) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; ++ else if(maxRxPktSize > 1522) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; ++ else if(maxRxPktSize > 1518) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; ++ else ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; ++ ++ return portSerialCtrlReg; ++} ++ ++/******************************************************************************* ++* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path ++* ++* DESCRIPTION: ++* This routine sets the RX coalescing interrupt mechanism parameter. ++* This parameter is a timeout counter, that counts in 64 tClk ++* chunks, that when timeout event occurs a maskable interrupt occurs. ++* The parameter is calculated using the tCLK frequency of the ++* MV-64xxx chip, and the required number is in micro seconds. ++* ++* INPUT: ++* void* pPortHndl - Ethernet Port handler. ++* MV_U32 uSec - Number of micro seconds between ++* RX interrupts ++* ++* RETURN: ++* None. ++* ++* COMMENT: ++* 1 sec - TCLK_RATE clocks ++* 1 uSec - TCLK_RATE / 1,000,000 clocks ++* ++* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); ++ MV_U32 portSdmaCfgReg; ++ ++ portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); ++ portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; ++ ++ portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); ++ ++#if (MV_ETH_VERSION >= 2) ++ /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ ++ if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) ++ portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; ++#endif /* MV_ETH_VERSION >= 2 */ ++ ++ MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); ++ return coal; ++} ++ ++/******************************************************************************* ++* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path ++* ++* DESCRIPTION: ++* This routine sets the TX coalescing interrupt mechanism parameter. ++* This parameter is a timeout counter, that counts in 64 tClk ++* chunks, that when timeout event occurs a maskable interrupt ++* occurs. ++* The parameter is calculated using the tCLK frequency of the ++* MV-64xxx chip, and the required number is in micro seconds. ++* ++* INPUT: ++* void* pPortHndl - Ethernet Port handler. ++* MV_U32 uSec - Number of micro seconds between ++* RX interrupts ++* ++* RETURN: ++* None. ++* ++* COMMENT: ++* 1 sec - TCLK_RATE clocks ++* 1 uSec - TCLK_RATE / 1,000,000 clocks ++* ++* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) ++* ++*******************************************************************************/ ++MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); ++ MV_U32 regVal; ++ ++ regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); ++ regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; ++ regVal |= ETH_TX_INTR_COAL_MASK(coal); ++ ++ /* Set TX Coalescing mechanism */ ++ MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); ++ return coal; ++} ++ ++/******************************************************************************* ++* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds ++* ++* DESCRIPTION: ++* This routine gets the RX and TX coalescing interrupt values. ++* The parameter is calculated using the tCLK frequency of the ++* MV-64xxx chip, and the returned numbers are in micro seconds. ++* ++* INPUTs: ++* void* pPortHndl - Ethernet Port handler. ++* ++* OUTPUTs: ++* MV_U32* pRxCoal - Number of micro seconds between RX interrupts ++* MV_U32* pTxCoal - Number of micro seconds between TX interrupts ++* ++* RETURN: ++* MV_STATUS MV_OK - success ++* Others - failure. ++* ++* COMMENT: ++* 1 sec - TCLK_RATE clocks ++* 1 uSec - TCLK_RATE / 1,000,000 clocks ++* ++* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) ++* ++*******************************************************************************/ ++MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal) ++{ ++ MV_U32 regVal, coal, usec; ++ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ /* get TX Coalescing */ ++ regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); ++ coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); ++ ++ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); ++ if(pTxCoal != NULL) ++ *pTxCoal = usec; ++ ++ /* Get RX Coalescing */ ++ regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); ++ coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); ++ ++#if (MV_ETH_VERSION >= 2) ++ if(regVal & ETH_RX_INTR_COAL_MSB_MASK) ++ { ++ /* Add MSB */ ++ coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); ++ } ++#endif /* MV_ETH_VERSION >= 2 */ ++ ++ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); ++ if(pRxCoal != NULL) ++ *pRxCoal = usec; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMaxRxSizeSet - ++* ++* DESCRIPTION: ++* Change maximum receive size of the port. This configuration will take place ++* after next call of ethPortSetDefaults() function. ++* ++* INPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ MV_U32 portSerialCtrlReg; ++ ++ if((maxRxSize < 1518) || (maxRxSize & ~ETH_RX_BUFFER_MASK)) ++ return MV_BAD_PARAM; ++ ++ pPortCtrl->portConfig.maxRxPktSize = maxRxSize; ++ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); ++ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; ++ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************/ ++/* MAC Filtering functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port ++* ++* DESCRIPTION: ++* This routine used to free buffers attached to the Rx ring and should ++* be called only when Giga Ethernet port is Down ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* MV_BOOL isPromisc - Promiscous mode ++* MV_TRUE - accept all Broadcast, Multicast ++* and Unicast packets ++* MV_FALSE - accept all Broadcast, ++* specially added Multicast and ++* single Unicast packets ++* ++* RETURN: MV_STATUS MV_OK - Success, Other - Failure ++* ++*******************************************************************************/ ++MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ int queue; ++ MV_U32 portCfgReg; ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ /* Set / Clear UPM bit in port configuration register */ ++ if(isPromisc) ++ { ++ /* Accept all multicast packets to RX default queue */ ++ queue = pPortCtrl->portConfig.rxDefQ; ++ portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; ++ memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); ++ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF); ++ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF); ++ } ++ else ++ { ++ /* Reject all Multicast addresses */ ++ queue = -1; ++ portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; ++ /* Clear all mcastCount */ ++ memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); ++ } ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ /* Set Special Multicast and Other Multicast tables */ ++ mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); ++ mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); ++ ethSetUcastTable(pPortCtrl->portNo, queue); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMacAddrSet - This function Set the port Unicast address. ++* ++* DESCRIPTION: ++* This function Set the port Ethernet MAC address. This address ++* will be used to send Pause frames if enabled. Packets with this ++* address will be accepted and dispatched to default RX queue ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler. ++* char* pAddr - Address to be set ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Other - Faulure ++* ++*******************************************************************************/ ++MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ unsigned int macH; ++ unsigned int macL; ++ ++ if(queue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); ++ return MV_BAD_PARAM; ++ } ++ ++ if(queue != -1) ++ { ++ macL = (pAddr[4] << 8) | (pAddr[5]); ++ macH = (pAddr[0] << 24)| (pAddr[1] << 16) | ++ (pAddr[2] << 8) | (pAddr[3] << 0); ++ ++ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); ++ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); ++ } ++ ++ /* Accept frames of this address */ ++ ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMacAddrGet - This function returns the port Unicast address. ++* ++* DESCRIPTION: ++* This function returns the port Ethernet MAC address. ++* ++* INPUT: ++* int portNo - Ethernet port number. ++* char* pAddr - Pointer where address will be written to ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Other - Faulure ++* ++*******************************************************************************/ ++MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) ++{ ++ unsigned int macH; ++ unsigned int macL; ++ ++ if(pAddr == NULL) ++ { ++ mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); ++ return MV_BAD_PARAM; ++ } ++ ++ macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); ++ macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); ++ pAddr[0] = (macH >> 24) & 0xff; ++ pAddr[1] = (macH >> 16) & 0xff; ++ pAddr[2] = (macH >> 8) & 0xff; ++ pAddr[3] = macH & 0xff; ++ pAddr[4] = (macL >> 8) & 0xff; ++ pAddr[5] = macL & 0xff; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* MV_U8* pAddr - Address to calculate CRC-8 ++* ++* RETURN: MV_U8 - CRC-8 of this MAC address ++* ++*******************************************************************************/ ++MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr) ++{ ++ unsigned int macH; ++ unsigned int macL; ++ int macArray[48]; ++ int crc[8]; ++ int i; ++ unsigned char crcResult = 0; ++ ++ /* Calculate CRC-8 out of the given address */ ++ macH = (pAddr[0] << 8) | (pAddr[1]); ++ macL = (pAddr[2] << 24)| (pAddr[3] << 16) | ++ (pAddr[4] << 8) | (pAddr[5] << 0); ++ ++ for(i=0; i<32; i++) ++ macArray[i] = (macL >> i) & 0x1; ++ ++ for(i=32; i<48; i++) ++ macArray[i] = (macH >> (i - 32)) & 0x1; ++ ++ crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ ++ macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ ++ macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ ++ macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ ++ macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; ++ ++ crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ ++ macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ ++ macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ ++ macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ ++ macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ ++ macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ ++ macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; ++ ++ crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ ++ macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ ++ macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ ++ macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ ++ macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ ++ macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; ++ ++ crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ ++ macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ ++ macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ ++ macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ ++ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ ++ macArray[3] ^ macArray[2] ^ macArray[1]; ++ ++ crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ ++ macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ ++ macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ ++ macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ ++ macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ ++ macArray[3] ^ macArray[2]; ++ ++ crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ ++ macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ ++ macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ ++ macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ ++ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ ++ macArray[4] ^ macArray[3]; ++ ++ crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ ++ macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ ++ macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ ++ macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ ++ macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ ++ macArray[4]; ++ ++ crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ ++ macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ ++ macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ ++ macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ ++ macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; ++ ++ for(i=0; i<8; i++) ++ crcResult = crcResult | (crc[i] << i); ++ ++ return crcResult; ++} ++/******************************************************************************* ++* mvEthMcastAddrSet - Multicast address settings. ++* ++* DESCRIPTION: ++* This API controls the MV device MAC multicast support. ++* The MV device supports multicast using two tables: ++* 1) Special Multicast Table for MAC addresses of the form ++* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). ++* The MAC DA[7:0] bits are used as a pointer to the Special Multicast ++* Table entries in the DA-Filter table. ++* In this case, the function calls ethPortSmcAddr() routine to set the ++* Special Multicast Table. ++* 2) Other Multicast Table for multicast of another type. A CRC-8bit ++* is used as an index to the Other Multicast Table entries in the ++* DA-Filter table. ++* In this case, the function calculates the CRC-8bit value and calls ++* ethPortOmcAddr() routine to set the Other Multicast Table. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler. ++* MV_U8* pAddr - Address to be set ++* int queue - RX queue to capture all packets with this ++* Multicast MAC address. ++* -1 means delete this Multicast address. ++* ++* RETURN: MV_STATUS ++* MV_TRUE - Success, Other - Failure ++* ++*******************************************************************************/ ++MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ unsigned char crcResult = 0; ++ ++ if(queue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", ++ pPortCtrl->portNo, queue); ++ return MV_BAD_PARAM; ++ } ++ ++ if((pAddr[0] == 0x01) && ++ (pAddr[1] == 0x00) && ++ (pAddr[2] == 0x5E) && ++ (pAddr[3] == 0x00) && ++ (pAddr[4] == 0x00)) ++ { ++ ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); ++ } ++ else ++ { ++ crcResult = mvEthMcastCrc8Get(pAddr); ++ ++ /* Check Add counter for this CRC value */ ++ if(queue == -1) ++ { ++ if(pPortCtrl->mcastCount[crcResult] == 0) ++ { ++ mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", ++ pPortCtrl->portNo, (unsigned)crcResult); ++ return MV_NO_SUCH; ++ } ++ ++ pPortCtrl->mcastCount[crcResult]--; ++ if(pPortCtrl->mcastCount[crcResult] != 0) ++ { ++ mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", ++ pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], ++ (unsigned)crcResult); ++ return MV_NO_CHANGE; ++ } ++ } ++ else ++ { ++ pPortCtrl->mcastCount[crcResult]++; ++ if(pPortCtrl->mcastCount[crcResult] > 1) ++ { ++ mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", ++ pPortCtrl->portNo, (unsigned)crcResult); ++ return MV_NO_CHANGE; ++ } ++ } ++ ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* ethSetUcastTable - Unicast address settings. ++* ++* DESCRIPTION: ++* Set all entries in the Unicast MAC Table queue==-1 means reject all ++* INPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++static void ethSetUcastTable(int portNo, int queue) ++{ ++ int offset; ++ MV_U32 regValue; ++ ++ if(queue == -1) ++ { ++ regValue = 0; ++ } ++ else ++ { ++ regValue = (((0x01 | (queue<<1)) << 0) | ++ ((0x01 | (queue<<1)) << 8) | ++ ((0x01 | (queue<<1)) << 16) | ++ ((0x01 | (queue<<1)) << 24)); ++ } ++ ++ for (offset=0; offset<=0xC; offset+=4) ++ MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); ++} ++ ++/******************************************************************************* ++* mvEthSetSpecialMcastTable - Special Multicast address settings. ++* ++* DESCRIPTION: ++* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all ++* INPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) ++{ ++ int offset; ++ MV_U32 regValue; ++ ++ if(queue == -1) ++ { ++ regValue = 0; ++ } ++ else ++ { ++ regValue = (((0x01 | (queue<<1)) << 0) | ++ ((0x01 | (queue<<1)) << 8) | ++ ((0x01 | (queue<<1)) << 16) | ++ ((0x01 | (queue<<1)) << 24)); ++ } ++ ++ for (offset=0; offset<=0xFC; offset+=4) ++ { ++ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + ++ offset), regValue); ++ } ++} ++ ++/******************************************************************************* ++* mvEthSetOtherMcastTable - Other Multicast address settings. ++* ++* DESCRIPTION: ++* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all ++* INPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) ++{ ++ int offset; ++ MV_U32 regValue; ++ ++ if(queue == -1) ++ { ++ regValue = 0; ++ } ++ else ++ { ++ regValue = (((0x01 | (queue<<1)) << 0) | ++ ((0x01 | (queue<<1)) << 8) | ++ ((0x01 | (queue<<1)) << 16) | ++ ((0x01 | (queue<<1)) << 24)); ++ } ++ ++ for (offset=0; offset<=0xFC; offset+=4) ++ { ++ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + ++ offset), regValue); ++ } ++} ++ ++/******************************************************************************* ++* ethSetUcastAddr - This function Set the port unicast address table ++* ++* DESCRIPTION: ++* This function locates the proper entry in the Unicast table for the ++* specified MAC nibble and sets its properties according to function ++* parameters. ++* ++* INPUT: ++* int ethPortNum - Port number. ++* MV_U8 lastNibble - Unicast MAC Address last nibble. ++* int queue - Rx queue number for this MAC address. ++* value "-1" means remove address ++* ++* OUTPUT: ++* This function add/removes MAC addresses from the port unicast address ++* table. ++* ++* RETURN: ++* MV_TRUE is output succeeded. ++* MV_FALSE if option parameter is invalid. ++* ++*******************************************************************************/ ++static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) ++{ ++ unsigned int unicastReg; ++ unsigned int tblOffset; ++ unsigned int regOffset; ++ ++ /* Locate the Unicast table entry */ ++ lastNibble = (0xf & lastNibble); ++ tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/ ++ regOffset = lastNibble % 4; /* Entry offset within the above register */ ++ ++ ++ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) + ++ tblOffset)); ++ ++ ++ if(queue == -1) ++ { ++ /* Clear accepts frame bit at specified unicast DA table entry */ ++ unicastReg &= ~(0xFF << (8*regOffset)); ++ } ++ else ++ { ++ unicastReg &= ~(0xFF << (8*regOffset)); ++ unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset)); ++ } ++ MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), ++ unicastReg); ++ ++ return MV_TRUE; ++} ++ ++/******************************************************************************* ++* ethSetSpecialMcastAddr - Special Multicast address settings. ++* ++* DESCRIPTION: ++* This routine controls the MV device special MAC multicast support. ++* The Special Multicast Table for MAC addresses supports MAC of the form ++* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). ++* The MAC DA[7:0] bits are used as a pointer to the Special Multicast ++* Table entries in the DA-Filter table. ++* This function set the Special Multicast Table appropriate entry ++* according to the argument given. ++* ++* INPUT: ++* int ethPortNum Port number. ++* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). ++* int queue Rx queue number for this MAC address. ++* int option 0 = Add, 1 = remove address. ++* ++* OUTPUT: ++* See description. ++* ++* RETURN: ++* MV_TRUE is output succeeded. ++* MV_FALSE if option parameter is invalid. ++* ++*******************************************************************************/ ++static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) ++{ ++ unsigned int smcTableReg; ++ unsigned int tblOffset; ++ unsigned int regOffset; ++ ++ /* Locate the SMC table entry */ ++ tblOffset = (lastByte / 4); /* Register offset from SMC table base */ ++ regOffset = lastByte % 4; /* Entry offset within the above register */ ++ ++ smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4)); ++ ++ if(queue == -1) ++ { ++ /* Clear accepts frame bit at specified Special DA table entry */ ++ smcTableReg &= ~(0xFF << (8 * regOffset)); ++ } ++ else ++ { ++ smcTableReg &= ~(0xFF << (8 * regOffset)); ++ smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); ++ } ++ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + ++ tblOffset*4), smcTableReg); ++ ++ return MV_TRUE; ++} ++ ++/******************************************************************************* ++* ethSetOtherMcastAddr - Multicast address settings. ++* ++* DESCRIPTION: ++* This routine controls the MV device Other MAC multicast support. ++* The Other Multicast Table is used for multicast of another type. ++* A CRC-8bit is used as an index to the Other Multicast Table entries ++* in the DA-Filter table. ++* The function gets the CRC-8bit value from the calling routine and ++* set the Other Multicast Table appropriate entry according to the ++* CRC-8 argument given. ++* ++* INPUT: ++* int ethPortNum Port number. ++* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). ++* int queue Rx queue number for this MAC address. ++* ++* OUTPUT: ++* See description. ++* ++* RETURN: ++* MV_TRUE is output succeeded. ++* MV_FALSE if option parameter is invalid. ++* ++*******************************************************************************/ ++static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) ++{ ++ unsigned int omcTableReg; ++ unsigned int tblOffset; ++ unsigned int regOffset; ++ ++ /* Locate the OMC table entry */ ++ tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ ++ regOffset = crc8 % 4; /* Entry offset within the above register */ ++ ++ omcTableReg = MV_REG_READ( ++ (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); ++ ++ if(queue == -1) ++ { ++ /* Clear accepts frame bit at specified Other DA table entry */ ++ omcTableReg &= ~(0xFF << (8 * regOffset)); ++ } ++ else ++ { ++ omcTableReg &= ~(0xFF << (8 * regOffset)); ++ omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); ++ } ++ ++ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), ++ omcTableReg); ++ ++ return MV_TRUE; ++} ++ ++ ++/******************************************************************************/ ++/* MIB Counters functions */ ++/******************************************************************************/ ++ ++ ++/******************************************************************************* ++* mvEthMibCounterRead - Read a MIB counter ++* ++* DESCRIPTION: ++* This function reads a MIB counter of a specific ethernet port. ++* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or ++* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, ++* so pHigh32 pointer should not be NULL in this case. ++* ++* INPUT: ++* int ethPortNum - Ethernet Port number. ++* unsigned int mibOffset - MIB counter offset. ++* ++* OUTPUT: ++* MV_U32* pHigh32 - pointer to place where 32 most significant bits ++* of the counter will be stored. ++* ++* RETURN: ++* 32 low sgnificant bits of MIB counter value. ++* ++*******************************************************************************/ ++MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset, ++ MV_U32* pHigh32) ++{ ++ int portNo; ++ MV_U32 valLow32, valHigh32; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ ++ portNo = pPortCtrl->portNo; ++ ++ valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); ++ ++ /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ ++ /* of a 64-bit MIB Counter. */ ++ if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || ++ (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) ) ++ { ++ valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); ++ if(pHigh32 != NULL) ++ *pHigh32 = valHigh32; ++ } ++ return valLow32; ++} ++ ++/******************************************************************************* ++* mvEthMibCountersClear - Clear all MIB counters ++* ++* DESCRIPTION: ++* This function clears all MIB counters ++* ++* INPUT: ++* int ethPortNum - Ethernet Port number. ++* ++* ++* RETURN: void ++* ++*******************************************************************************/ ++void mvEthMibCountersClear(void* pPortHandle) ++{ ++ int i, portNo; ++ unsigned int dummy; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ ++ portNo = pPortCtrl->portNo; ++ ++ /* Perform dummy reads from MIB counters */ ++ for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i 0xFF) ++ { ++ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); ++ return -1; ++ } ++ regIdx = mvOsDivide(tos>>2, 10); ++ regOffs = mvOsReminder(tos>>2, 10); ++ ++ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); ++ rxq = (regValue >> (regOffs*3)); ++ rxq &= 0x7; ++ ++ return rxq; ++} ++ ++/******************************************************************************* ++* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int tos - TOS value in the IP header of the packet ++* int rxq - RX Queue for packets with the configured TOS value ++* Negative value (-1) means no special processing for these packets, ++* so they will be processed as regular packets. ++* ++* RETURN: MV_STATUS ++*******************************************************************************/ ++MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq) ++{ ++ MV_U32 regValue; ++ int regIdx, regOffs; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ ++ if( (rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM) ) ++ { ++ mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq); ++ return MV_BAD_PARAM; ++ } ++ if(tos > 0xFF) ++ { ++ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); ++ return MV_BAD_PARAM; ++ } ++ regIdx = mvOsDivide(tos>>2, 10); ++ regOffs = mvOsReminder(tos>>2, 10); ++ ++ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); ++ regValue &= ~(0x7 << (regOffs*3)); ++ regValue |= (rxq << (regOffs*3)); ++ ++ MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with ++* special priority bits [0-2] ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int bpduQueue - Special queue to capture VLAN tagged packets with special ++* priority. ++* Negative value (-1) means no special processing for these packets, ++* so they will be processed as regular packets. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 vlanPrioReg; ++ ++ if(vlanPrioQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); ++ return MV_BAD_PARAM; ++ } ++ if(vlanPrio >= 8) ++ { ++ mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); ++ return MV_BAD_PARAM; ++ } ++ ++ vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); ++ vlanPrioReg &= ~(0x7 << (vlanPrio*3)); ++ vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3)); ++ MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. ++* ++* DESCRIPTION: ++* This function defines processing of BPDU packets. ++* BPDU packets can be accepted and captured to one of RX queues ++* or can be processing as regular Multicast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int bpduQueue - Special queue to capture BPDU packets (DA is equal to ++* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, ++* except for the Flow-Control Pause packets). ++* Negative value (-1) means no special processing for BPDU, ++* packets so they will be processed as regular Multicast packets. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ MV_U32 portCfgExtReg; ++ ++ if(bpduQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); ++ return MV_BAD_PARAM; ++ } ++ ++ portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ if(bpduQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxBpduQ = bpduQueue; ++ ++ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxBpduQ = -1; ++ /* no special processing for BPDU packets */ ++ portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthArpRxQueue - Configure RX queue to capture ARP packets. ++* ++* DESCRIPTION: ++* This function defines processing of ARP (type=0x0806) packets. ++* ARP packets can be accepted and captured to one of RX queues ++* or can be processed as other Broadcast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int arpQueue - Special queue to capture ARP packets (type=0x806). ++* Negative value (-1) means discard ARP packets ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ ++ if(arpQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); ++ return MV_BAD_PARAM; ++ } ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ ++ if(arpQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxArpQ = arpQueue; ++ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); ++ ++ portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxArpQ = -1; ++ portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. ++* ++* DESCRIPTION: ++* This function defines processing of TCP packets. ++* TCP packets can be accepted and captured to one of RX queues ++* or can be processed as regular Unicast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int tcpQueue - Special queue to capture TCP packets. Value "-1" ++* means no special processing for TCP packets, ++* so they will be processed as regular ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ ++ if(tcpQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); ++ return MV_BAD_PARAM; ++ } ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ ++ if(tcpQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxTcpQ = tcpQueue; ++ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); ++ ++ portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxTcpQ = -1; ++ portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. ++* ++* DESCRIPTION: ++* This function defines processing of UDP packets. ++* TCP packets can be accepted and captured to one of RX queues ++* or can be processed as regular Unicast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int udpQueue - Special queue to capture UDP packets. Value "-1" ++* means no special processing for UDP packets, ++* so they will be processed as regular ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ ++ if(udpQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); ++ return MV_BAD_PARAM; ++ } ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ ++ if(udpQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxUdpQ = udpQueue; ++ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); ++ ++ portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxUdpQ = -1; ++ portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************/ ++/* Speed, Duplex, FlowControl routines */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. ++* ++* DESCRIPTION: ++* This function configure the port to work with desirable Duplex and Speed. ++* Changing of these parameters are allowed only when port is disabled. ++* This function disable the port if was enabled, change duplex and speed ++* and, enable the port back if needed. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* ETH_PORT_SPEED speed - Speed of the port. ++* ETH_PORT_SPEED duplex - Duplex of the port. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_OUT_OF_RANGE - Failed. Port is out of valid range ++* MV_NOT_FOUND - Failed. Port is not initialized. ++* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. ++* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) ++* is not valid ++* ++*******************************************************************************/ ++MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed, ++ MV_ETH_PORT_DUPLEX duplex) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ MV_U32 portSerialCtrlReg; ++ ++ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) ) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ /* Check validity */ ++ if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) ) ++ return MV_BAD_PARAM; ++ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); ++ /* Set Speed */ ++ switch(speed) ++ { ++ case MV_ETH_SPEED_AN: ++ portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ break; ++ ++ case MV_ETH_SPEED_10: ++ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; ++ portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; ++ break; ++ ++ case MV_ETH_SPEED_100: ++ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; ++ portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; ++ break; ++ ++ case MV_ETH_SPEED_1000: ++ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; ++ break; ++ ++ default: ++ mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); ++ return MV_BAD_VALUE; ++ } ++ /* Set duplex */ ++ switch(duplex) ++ { ++ case MV_ETH_DUPLEX_AN: ++ portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; ++ break; ++ ++ case MV_ETH_DUPLEX_HALF: ++ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; ++ break; ++ ++ case MV_ETH_DUPLEX_FULL: ++ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; ++ break; ++ ++ default: ++ mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); ++ return MV_BAD_VALUE; ++ } ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthFlowCtrlSet - Set Flow Control of the port. ++* ++* DESCRIPTION: ++* This function configure the port to work with desirable Duplex and ++* Speed. Changing of these parameters are allowed only when port is ++* disabled. This function disable the port if was enabled, change ++* duplex and speed and, enable the port back if needed. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* MV_ETH_PORT_FC flowControl - Flow control of the port. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_OUT_OF_RANGE - Failed. Port is out of valid range ++* MV_NOT_FOUND - Failed. Port is not initialized. ++* MV_BAD_VALUE - Value flowControl parameters is not valid ++* ++*******************************************************************************/ ++MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ MV_U32 portSerialCtrlReg; ++ ++ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) ) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); ++ switch(flowControl) ++ { ++ case MV_ETH_FC_AN_ADV_DIS: ++ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; ++ break; ++ ++ case MV_ETH_FC_AN_ADV_SYM: ++ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; ++ break; ++ ++ case MV_ETH_FC_DISABLE: ++ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; ++ break; ++ ++ case MV_ETH_FC_ENABLE: ++ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; ++ break; ++ ++ default: ++ mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); ++ return MV_BAD_VALUE; ++ } ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthHeaderModeSet - Set port header mode. ++* ++* DESCRIPTION: ++* This function configures the port to work in Marvell-Header mode. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_NOT_SUPPORTED- Feature not supported. ++* MV_OUT_OF_RANGE - Failed. Port is out of valid range ++* MV_NOT_FOUND - Failed. Port is not initialized. ++* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. ++* ++*******************************************************************************/ ++MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ MV_U32 mvHeaderReg; ++ MV_U32 numRxQ = MV_ETH_RX_Q_NUM; ++ ++ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); ++ /* Disable header mode. */ ++ mvHeaderReg &= ~ETH_MVHDR_EN_MASK; ++ ++ if(headerMode != MV_ETH_DISABLE_HEADER_MODE) ++ { ++ /* Enable Header mode. */ ++ mvHeaderReg |= ETH_MVHDR_EN_MASK; ++ ++ /* Clear DA-Prefix & MHMask fields.*/ ++ mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); ++ ++ if(numRxQ > 1) ++ { ++ switch (headerMode) ++ { ++ case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): ++ mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; ++ break; ++ case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): ++ mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; ++ break; ++ case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): ++ mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; ++ break; ++ default: ++ break; ++ } ++ ++ switch (numRxQ) ++ { ++ case (4): ++ mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; ++ break; ++ case (8): ++ mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; ++ break; ++ default: ++ break; ++ } ++ } ++ } ++ ++ MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); ++ ++ return MV_OK; ++} ++ ++#if (MV_ETH_VERSION >= 4) ++/******************************************************************************* ++* mvEthEjpModeSet - Enable / Disable EJP policy for TX. ++* ++* DESCRIPTION: ++* This function ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* MV_BOOL TRUE - enable EJP mode ++* FALSE - disable EJP mode ++* ++* OUTPUT: MV_STATUS ++* MV_OK - Success ++* Other - Failure ++* ++* RETURN: None. ++* ++*******************************************************************************/ ++MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ ++ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ pPortCtrl->portConfig.ejpMode = mode; ++ if(mode) ++ { ++ /* EJP enabled */ ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK); ++ } ++ else ++ { ++ /* EJP disabled */ ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0); ++ } ++ mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n", ++ port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port), ++ MV_REG_READ(ETH_TXQ_CMD_1_REG(port))); ++ ++ return MV_OK; ++} ++#endif /* MV_ETH_VERSION >= 4 */ ++ ++/******************************************************************************* ++* mvEthStatusGet - Get major properties of the port . ++* ++* DESCRIPTION: ++* This function get major properties of the port (link, speed, duplex, ++* flowControl, etc) and return them using the single structure. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* ++* OUTPUT: ++* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status ++* will be placed. ++* ++* RETURN: None. ++* ++*******************************************************************************/ ++void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ ++ MV_U32 regValue; ++ ++ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); ++ ++ if(regValue & ETH_GMII_SPEED_1000_MASK) ++ pStatus->speed = MV_ETH_SPEED_1000; ++ else if(regValue & ETH_MII_SPEED_100_MASK) ++ pStatus->speed = MV_ETH_SPEED_100; ++ else ++ pStatus->speed = MV_ETH_SPEED_10; ++ ++ if(regValue & ETH_LINK_UP_MASK) ++ pStatus->isLinkUp = MV_TRUE; ++ else ++ pStatus->isLinkUp = MV_FALSE; ++ ++ if(regValue & ETH_FULL_DUPLEX_MASK) ++ pStatus->duplex = MV_ETH_DUPLEX_FULL; ++ else ++ pStatus->duplex = MV_ETH_DUPLEX_HALF; ++ ++ ++ if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ++ pStatus->flowControl = MV_ETH_FC_ENABLE; ++ else ++ pStatus->flowControl = MV_ETH_FC_DISABLE; ++} ++ ++ ++/******************************************************************************/ ++/* PHY Control Functions */ ++/******************************************************************************/ ++ ++ ++/******************************************************************************* ++* mvEthPhyAddrSet - Set the ethernet port PHY address. ++* ++* DESCRIPTION: ++* This routine set the ethernet port PHY address according to given ++* parameter. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int phyAddr - PHY address ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++void mvEthPhyAddrSet(void* pPortHandle, int phyAddr) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ unsigned int regData; ++ ++ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); ++ ++ regData &= ~ETH_PHY_ADDR_MASK; ++ regData |= phyAddr; ++ ++ MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); ++ ++ return; ++} ++ ++/******************************************************************************* ++* mvEthPhyAddrGet - Get the ethernet port PHY address. ++* ++* DESCRIPTION: ++* This routine returns the given ethernet port PHY address. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* ++* ++* RETURN: int - PHY address. ++* ++*******************************************************************************/ ++int mvEthPhyAddrGet(void* pPortHandle) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ unsigned int regData; ++ ++ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); ++ ++ return ((regData >> (5 * port)) & 0x1f); ++} ++ ++/******************************************************************************/ ++/* Descriptor handling Functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. ++* ++* DESCRIPTION: ++* This function prepares a Rx chained list of descriptors and packet ++* buffers in a form of a ring. The routine must be called after port ++* initialization routine and before port start routine. ++* The Ethernet SDMA engine uses CPU bus addresses to access the various ++* devices in the system (i.e. DRAM). This function uses the ethernet ++* struct 'virtual to physical' routine (set by the user) to set the ring ++* with physical addresses. ++* ++* INPUT: ++* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. ++* int rxQueue Number of Rx queue. ++* int rxDescNum Number of Rx descriptors ++* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. ++* ++* OUTPUT: ++* The routine updates the Ethernet port control struct with information ++* regarding the Rx descriptors and buffers. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) ++{ ++ ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; ++ int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; ++ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; ++ ++ /* Make sure descriptor address is cache line size aligned */ ++ pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pRxDesc = (ETH_RX_DESC*)pRxDescBase; ++ pRxPrevDesc = pRxDesc; ++ ++ /* initialize the Rx descriptors ring */ ++ for (ix=0; ixbufSize = 0x0; ++ pRxDesc->byteCnt = 0x0; ++ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pRxDesc->bufPtr = 0x0; ++ pRxDesc->returnInfo = 0x0; ++ pRxPrevDesc = pRxDesc; ++ if(ix == (rxDescNum-1)) ++ { ++ /* Closing Rx descriptors ring */ ++ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase); ++ } ++ else ++ { ++ pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); ++ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc); ++ } ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); ++ } ++ ++ pQueueCtrl->pCurrentDescr = pRxDescBase; ++ pQueueCtrl->pUsedDescr = pRxDescBase; ++ ++ pQueueCtrl->pFirstDescr = pRxDescBase; ++ pQueueCtrl->pLastDescr = pRxDesc; ++ pQueueCtrl->resource = 0; ++} ++ ++void ethResetRxDescRing(void* pPortHndl, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue]; ++ ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; ++ ++ pQueueCtrl->resource = 0; ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ while(MV_TRUE) ++ { ++ pRxDesc->bufSize = 0x0; ++ pRxDesc->byteCnt = 0x0; ++ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pRxDesc->bufPtr = 0x0; ++ pRxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); ++ if( (void*)pRxDesc == pQueueCtrl->pLastDescr) ++ break; ++ pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); ++ } ++ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; ++ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; ++ ++ /* Update RX Command register */ ++ pPortCtrl->portRxQueueCmdReg |= (1 << queue); ++ ++ /* update HW */ ++ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ } ++ else ++ { ++ /* Update RX Command register */ ++ pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); ++ ++ /* update HW */ ++ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); ++ } ++} ++ ++/******************************************************************************* ++* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. ++* ++* DESCRIPTION: ++* This function prepares a Tx chained list of descriptors and packet ++* buffers in a form of a ring. The routine must be called after port ++* initialization routine and before port start routine. ++* The Ethernet SDMA engine uses CPU bus addresses to access the various ++* devices in the system (i.e. DRAM). This function uses the ethernet ++* struct 'virtual to physical' routine (set by the user) to set the ring ++* with physical addresses. ++* ++* INPUT: ++* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. ++* int txQueue Number of Tx queue. ++* int txDescNum Number of Tx descriptors ++* int txBuffSize Size of Tx buffer ++* MV_U8* pTxDescBase Tx descriptors memory area base addr. ++* ++* OUTPUT: ++* The routine updates the Ethernet port control struct with information ++* regarding the Tx descriptors and buffers. ++* ++* RETURN: None. ++* ++*******************************************************************************/ ++static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) ++{ ++ ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; ++ int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; ++ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; ++ ++ /* Make sure descriptor address is cache line size aligned */ ++ pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pTxDesc = (ETH_TX_DESC*)pTxDescBase; ++ pTxPrevDesc = pTxDesc; ++ ++ /* initialize the Tx descriptors ring */ ++ for (ix=0; ixbyteCnt = 0x0000; ++ pTxDesc->L4iChk = 0x0000; ++ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pTxDesc->bufPtr = 0x0; ++ pTxDesc->returnInfo = 0x0; ++ ++ pTxPrevDesc = pTxDesc; ++ ++ if(ix == (txDescNum-1)) ++ { ++ /* Closing Tx descriptors ring */ ++ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase); ++ } ++ else ++ { ++ pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); ++ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc); ++ } ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); ++ } ++ ++ pQueueCtrl->pCurrentDescr = pTxDescBase; ++ pQueueCtrl->pUsedDescr = pTxDescBase; ++ ++ pQueueCtrl->pFirstDescr = pTxDescBase; ++ pQueueCtrl->pLastDescr = pTxDesc; ++ /* Leave one TX descriptor out of use */ ++ pQueueCtrl->resource = txDescNum - 1; ++} ++ ++void ethResetTxDescRing(void* pPortHndl, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue]; ++ ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; ++ ++ pQueueCtrl->resource = 0; ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ while(MV_TRUE) ++ { ++ pTxDesc->byteCnt = 0x0000; ++ pTxDesc->L4iChk = 0x0000; ++ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pTxDesc->bufPtr = 0x0; ++ pTxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); ++ pQueueCtrl->resource++; ++ if( (void*)pTxDesc == pQueueCtrl->pLastDescr) ++ break; ++ pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); ++ } ++ /* Leave one TX descriptor out of use */ ++ pQueueCtrl->resource--; ++ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; ++ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; ++ ++ /* Update TX Command register */ ++ pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); ++ /* update HW */ ++ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ } ++ else ++ { ++ /* Update TX Command register */ ++ pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); ++ /* update HW */ ++ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 ); ++ } ++} ++ ++/******************************************************************************* ++* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. ++* ++* DESCRIPTION: ++* This function allocates memory for RX and TX descriptors. ++* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. ++* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. ++* ++* INPUT: ++* int size - size of memory should be allocated. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize, ++ MV_ULONG* pPhysAddr, MV_U32 *memHandle) ++{ ++ MV_U8* pVirt; ++ ++#if defined(ETH_DESCR_IN_SRAM) ++ if(ethDescInSram == MV_TRUE) ++ pVirt = (char*)mvSramMalloc(descSize, pPhysAddr); ++ else ++#endif /* ETH_DESCR_IN_SRAM */ ++ { ++#ifdef ETH_DESCR_UNCACHED ++ pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, ++ pPhysAddr,memHandle); ++#else ++ pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, ++ pPhysAddr, memHandle); ++#endif /* ETH_DESCR_UNCACHED */ ++ } ++ memset(pVirt, 0, descSize); ++ ++ return pVirt; ++} ++ ++/******************************************************************************* ++* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. ++* ++* DESCRIPTION: ++* This function frees memory allocated for RX and TX descriptors. ++* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. ++* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. ++* ++* INPUT: ++* void* pVirtAddr - virtual pointer to memory allocated for RX and TX ++* desriptors. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf) ++{ ++ if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) ) ++ return; ++ ++#if defined(ETH_DESCR_IN_SRAM) ++ if( ethDescInSram ) ++ { ++ mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); ++ return; ++ } ++#endif /* ETH_DESCR_IN_SRAM */ ++ ++#ifdef ETH_DESCR_UNCACHED ++ mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, ++ pDescBuf->bufVirtPtr,pDescBuf->memHandle); ++#else ++ mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, ++ pDescBuf->bufVirtPtr,pDescBuf->memHandle); ++#endif /* ETH_DESCR_UNCACHED */ ++} ++ ++/******************************************************************************/ ++/* Other Functions */ ++/******************************************************************************/ ++ ++void mvEthPortPowerUp(int port) ++{ ++ MV_U32 regVal; ++ ++ /* MAC Cause register should be cleared */ ++ MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); ++ ++ if (mvBoardIsPortInSgmii(port)) ++ mvEthPortSgmiiConfig(port); ++ ++ /* Cancel Port Reset */ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); ++ regVal &= (~ETH_PORT_RESET_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); ++ while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0); ++} ++ ++void mvEthPortPowerDown(int port) ++{ ++ MV_U32 regVal; ++ ++ /* Port must be DISABLED */ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); ++ if( (regVal & ETH_PORT_ENABLE_MASK) != 0) ++ { ++ mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", ++ port, regVal); ++ return; ++ } ++ ++ /* Port Reset (Read after write the register as a precaution) */ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); ++ while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0); ++} ++ ++static void mvEthPortSgmiiConfig(int port) ++{ ++ MV_U32 regVal; ++ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); ++ ++ regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); ++ regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); ++ ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); ++} ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,748 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthDebug.c - Source file for user friendly debug functions ++* ++* DESCRIPTION: ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvCommon.h" ++#include "mvTypes.h" ++#include "mv802_3.h" ++#include "mvDebug.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "eth-phy/mvEthPhy.h" ++#include "eth/mvEth.h" ++#include "eth/gbe/mvEthDebug.h" ++ ++/* #define mvOsPrintf printf */ ++ ++void mvEthPortShow(void* pHndl); ++void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); ++ ++/******************************************************************************/ ++/* Debug functions */ ++/******************************************************************************/ ++void ethRxCoal(int port, int usec) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthRxCoalSet(pHndl, usec); ++ } ++} ++ ++void ethTxCoal(int port, int usec) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthTxCoalSet(pHndl, usec); ++ } ++} ++ ++#if (MV_ETH_VERSION >= 4) ++void ethEjpModeSet(int port, int mode) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthEjpModeSet(pHndl, mode); ++ } ++} ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++void ethBpduRxQ(int port, int bpduQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthBpduRxQueue(pHndl, bpduQueue); ++ } ++} ++ ++void ethArpRxQ(int port, int arpQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthArpRxQueue(pHndl, arpQueue); ++ } ++} ++ ++void ethTcpRxQ(int port, int tcpQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthTcpRxQueue(pHndl, tcpQueue); ++ } ++} ++ ++void ethUdpRxQ(int port, int udpQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthUdpRxQueue(pHndl, udpQueue); ++ } ++} ++ ++void ethTxPolicyRegs(int port) ++{ ++ int queue; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); ++ ++ if(pPortCtrl == NULL) ++ { ++ return; ++ } ++ mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", ++ port, pPortCtrl->portConfig.ejpMode); ++ for(queue=0; queuetxQueueConfig[queue].descrNum > 0) ++ mvOsPrintf("%d, ", queue); ++ } ++ mvOsPrintf("\n"); ++ ++ mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); ++ ++ mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", ++ ETH_TX_QUEUE_COMMAND_REG(port), ++ MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", ++ ETH_TX_FIXED_PRIO_CFG_REG(port), ++ MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", ++ ETH_TX_TOKEN_RATE_CFG_REG(port), ++ MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) ); ++ ++ mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", ++ ETH_MAX_TRANSMIT_UNIT_REG(port), ++ MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", ++ ETH_TX_TOKEN_BUCKET_SIZE_REG(port), ++ MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", ++ ETH_TX_TOKEN_BUCKET_COUNT_REG(port), ++ MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) ); ++ ++ for(queue=0; queue> 24) & 0xff), ((macH >> 16) & 0xff), ++ ((macH >> 8) & 0xff), (macH & 0xff), ++ ((macL >> 8) & 0xff), (macL & 0xff) ); ++ ++ for (i=0; i<4; i++) ++ { ++ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4)); ++ for(j=0; j<4; j++) ++ { ++ MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF; ++ ++ mvOsPrintf("%X: %8s, Q = %d\n", i*4+j, ++ (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); ++ } ++ } ++} ++ ++void ethMcastAdd(int port, char* macStr, int queue) ++{ ++ void* pHndl; ++ MV_U8 macAddr[MV_MAC_ADDR_SIZE]; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvMacStrToHex(macStr, macAddr); ++ mvEthMcastAddrSet(pHndl, macAddr, queue); ++ } ++} ++ ++void ethPortMcast(int port) ++{ ++ int tblIdx, regIdx; ++ MV_U32 regVal; ++ ++ mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", ++ port); ++ ++ for(tblIdx=0; tblIdx<(256/4); tblIdx++) ++ { ++ regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4)); ++ for(regIdx=0; regIdx<4; regIdx++) ++ { ++ if((regVal & (0x01 << (regIdx*8))) != 0) ++ { ++ mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", ++ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); ++ } ++ } ++ } ++ mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); ++ for(tblIdx=0; tblIdx<(256/4); tblIdx++) ++ { ++ regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4)); ++ for(regIdx=0; regIdx<4; regIdx++) ++ { ++ if((regVal & (0x01 << (regIdx*8))) != 0) ++ { ++ mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", ++ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); ++ } ++ } ++ } ++} ++ ++ ++/* Print status of Ethernet port */ ++void mvEthPortShow(void* pHndl) ++{ ++ MV_U32 regValue, rxCoal, txCoal; ++ int speed, queue, port; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl; ++ ++ port = pPortCtrl->portNo; ++ ++ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); ++ ++ mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", ++ port, ETH_PORT_STATUS_REG(port), regValue); ++ ++ mvOsPrintf("descInSram=%d, descSwCoher=%d\n", ++ ethDescInSram, ethDescSwCoher); ++ ++ if(regValue & ETH_GMII_SPEED_1000_MASK) ++ speed = 1000; ++ else if(regValue & ETH_MII_SPEED_100_MASK) ++ speed = 100; ++ else ++ speed = 10; ++ ++ mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); ++ ++ /* Link, Speed, Duplex, FlowControl */ ++ mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", ++ (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", ++ speed, ++ (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", ++ (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); ++ ++ mvOsPrintf("\n"); ++ ++ mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", ++ rxCoal, txCoal); ++ ++ mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", ++ pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, ++ pPortCtrl->portConfig.rxBpduQ, ++ pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); ++ ++ /* Print all RX and TX queues */ ++ for(queue=0; queuerxQueue[queue].pFirstDescr, ++ mvEthRxResourceGet(pPortCtrl, queue) ); ++ } ++ mvOsPrintf("\n"); ++ for(queue=0; queuetxQueue[queue].pFirstDescr, ++ mvEthTxResourceGet(pPortCtrl, queue) ); ++ } ++} ++ ++/* Print RX and TX queue of the Ethernet port */ ++void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode) ++{ ++ ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl; ++ ETH_QUEUE_CTRL *pQueueCtrl; ++ MV_U32 regValue; ++ ETH_RX_DESC *pRxDescr; ++ ETH_TX_DESC *pTxDescr; ++ int i, port = pPortCtrl->portNo; ++ ++ if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) ) ++ { ++ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); ++ mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); ++ ++ mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", ++ ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), ++ MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); ++ ++ ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", ++ (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr, ++ pQueueCtrl->resource); ++ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", ++ (MV_ULONG)pQueueCtrl->pCurrentDescr, ++ (MV_ULONG)pQueueCtrl->pUsedDescr); ++ ++ if(mode == 1) ++ { ++ pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; ++ i = 0; ++ do ++ { ++ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", ++ i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr), ++ pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize, ++ (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo, ++ ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo); ++ ++ ETH_DESCR_INV(pPortCtrl, pRxDescr); ++ pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); ++ i++; ++ } while (pRxDescr != pQueueCtrl->pFirstDescr); ++ } ++ } ++ else ++ mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); ++ } ++ ++ if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) ) ++ { ++ pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); ++ mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); ++ ++ regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); ++ mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", ++ ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); ++ ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", ++ (MV_ULONG)pQueueCtrl->pFirstDescr, ++ (MV_ULONG)pQueueCtrl->pLastDescr, ++ pQueueCtrl->resource); ++ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", ++ (MV_ULONG)pQueueCtrl->pCurrentDescr, ++ (MV_ULONG)pQueueCtrl->pUsedDescr); ++ ++ if(mode == 1) ++ { ++ pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; ++ i = 0; ++ do ++ { ++ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", ++ i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr), ++ pTxDescr->cmdSts, pTxDescr->byteCnt, ++ (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo, ++ pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0); ++ ++ ETH_DESCR_INV(pPortCtrl, pTxDescr); ++ pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); ++ i++; ++ } while (pTxDescr != pQueueCtrl->pFirstDescr); ++ } ++ } ++ else ++ mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); ++ } ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,146 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __MV_ETH_DEBUG_H__ ++#define __MV_ETH_DEBUG_H__ ++ ++#if 0 ++/* ++ ** Externs ++ */ ++void ethBpduRxQ(int port, int bpduQueue); ++void ethArpRxQ(int port, int bpduQueue); ++void ethTcpRxQ(int port, int bpduQueue); ++void ethUdpRxQ(int port, int bpduQueue); ++void ethMcastAdd(int port, char* macStr, int queue); ++ ++#ifdef INCLUDE_MULTI_QUEUE ++void ethRxPolicy( int port); ++void ethTxPolicy( int port); ++void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); ++void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); ++void ethRxPolQ(int port, int rxQueue, int rxQuota); ++#endif /* INCLUDE_MULTI_QUEUE */ ++ ++void print_egiga_stat(void *sc, unsigned int port); ++void ethPortStatus (int port); ++void ethPortQueues( int port, int rxQueue, int txQueue, int mode); ++void ethPortMcast(int port); ++void ethPortRegs(int port); ++void ethPortCounters(int port); ++void ethPortRmonCounters(int port); ++void ethRxCoal(int port, int usec); ++void ethTxCoal(int port, int usec); ++ ++void ethRegs(int port); ++void ethClearCounters(int port); ++void ethUcastSet(int port, char* macStr, int queue); ++void ethPortUcastShow(int port); ++ ++#ifdef CONFIG_MV_ETH_HEADER ++void run_com_header(const char *buffer); ++#endif ++ ++#ifdef INCLUDE_MULTI_QUEUE ++void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); ++void ethRxPolQ(int port, int queue, int quota); ++void ethRxPolicy(int port); ++void ethTxPolDef(int port, int txQ, char* headerHexStr); ++void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); ++void ethTxPolicy(int port); ++#endif /* INCLUDE_MULTI_QUEUE */ ++ ++#if (MV_ETH_VERSION >= 4) ++void ethEjpModeSet(int port, int mode) ++#endif ++#endif /* 0 */ ++ ++ ++ ++ ++void ethRxCoal(int port, int usec); ++void ethTxCoal(int port, int usec); ++#if (MV_ETH_VERSION >= 4) ++void ethEjpModeSet(int port, int mode); ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++void ethBpduRxQ(int port, int bpduQueue); ++void ethArpRxQ(int port, int arpQueue); ++void ethTcpRxQ(int port, int tcpQueue); ++void ethUdpRxQ(int port, int udpQueue); ++void ethTxPolicyRegs(int port); ++void ethPortRegs(int port); ++void ethRegs(int port); ++void ethClearCounters(int port); ++void ethPortCounters(int port); ++void ethPortRmonCounters(int port); ++void ethPortStatus(int port); ++void ethPortQueues(int port, int rxQueue, int txQueue, int mode); ++void ethUcastSet(int port, char* macStr, int queue); ++void ethPortUcastShow(int port); ++void ethMcastAdd(int port, char* macStr, int queue); ++void ethPortMcast(int port); ++void mvEthPortShow(void* pHndl); ++void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); ++ ++#endif +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,751 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller ++* ++* DESCRIPTION: ++* This header file contains macros typedefs and function declaration specific to ++* the Marvell Gigabit Ethernet Controller. ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++#ifndef __mvEthGbe_h__ ++#define __mvEthGbe_h__ ++ ++extern MV_BOOL ethDescInSram; ++extern MV_BOOL ethDescSwCoher; ++extern ETH_PORT_CTRL* ethPortCtrl[]; ++ ++static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc) ++{ ++#if defined (ETH_DESCR_IN_SRAM) ++ if( ethDescInSram ) ++ return mvSramVirtToPhy(pDesc); ++ else ++#endif /* ETH_DESCR_IN_SRAM */ ++ return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); ++} ++/* Return port handler */ ++#define mvEthPortHndlGet(port) ethPortCtrl[port] ++ ++/* Used as WA for HW/SW race on TX */ ++static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep) ++{ ++ int deep = 0; ++ MV_U32 txCurrReg, txEnReg; ++ ETH_TX_DESC* pTxLastDesc; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); ++ if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) ++ { ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; ++ return 0; ++ } ++ ++ pQueueCtrl = &pPortCtrl->txQueue[queue]; ++ pTxLastDesc = pQueueCtrl->pCurrentDescr; ++ txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); ++ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) ++ { ++ /* All descriptors are processed, no chance for race */ ++ return 0; ++ } ++ ++ /* Check distance betwee HW and SW location: */ ++ /* If distance between HW and SW pointers is less than max_deep descriptors */ ++ /* Race condition is possible, so wait end of TX and restart TXQ */ ++ while(deep < max_deep) ++ { ++ pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); ++ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) ++ { ++ int count = 0; ++ ++ while( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0) ++ { ++ count++; ++ if(count > 10000) ++ { ++ mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", ++ MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) ); ++ break; ++ } ++ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); ++ } ++ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; ++ return count; ++ } ++ deep++; ++ } ++ /* Distance between HW and SW pointers is more than max_deep descriptors, */ ++ /* So NO race condition - do nothing */ ++ return -1; ++} ++ ++ ++/* defines */ ++#define ETH_CSUM_MIN_BYTE_COUNT 72 ++ ++/* Tailgate and Kirwood have only 2K TX FIFO */ ++#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) ++#define ETH_CSUM_MAX_BYTE_COUNT 1600 ++#else ++#define ETH_CSUM_MAX_BYTE_COUNT 9*1024 ++#endif /* MV_ETH_VERSION */ ++ ++#define ETH_MV_HEADER_SIZE 2 ++#define ETH_MV_TX_EN ++ ++/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ ++#define MIN_TX_BUFF_LOAD 8 ++#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) ++ ++/* Default port configuration value */ ++#define PORT_CONFIG_VALUE \ ++ ETH_DEF_RX_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ ++ ETH_RX_CHECKSUM_WITH_PSEUDO_HDR ++ ++/* Default port extend configuration value */ ++#define PORT_CONFIG_EXTEND_VALUE 0 ++ ++#define PORT_SERIAL_CONTROL_VALUE \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE | \ ++ ETH_SET_FULL_DUPLEX_MASK ++ ++#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ ++ ETH_FORCE_LINK_PASS_MASK | \ ++ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ ++ ETH_SET_FULL_DUPLEX_MASK | \ ++ ETH_SET_MII_SPEED_100_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE ++ ++ ++#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ ++ ETH_FORCE_LINK_PASS_MASK | \ ++ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ ++ ETH_SET_FULL_DUPLEX_MASK | \ ++ ETH_SET_GMII_SPEED_1000_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE ++ ++#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_IN_BAND_AN_EN_MASK | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE ++ ++/* Function headers: */ ++MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); ++MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue); ++MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue); ++MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue); ++MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); ++MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); ++MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); ++/* Interrupt Coalesting functions */ ++MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec); ++MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec); ++MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal); ++ ++/******************************************************************************/ ++/* Data Flow functions */ ++/******************************************************************************/ ++static INLINE void mvEthPortTxRestart(void* pPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; ++} ++ ++/* Get number of Free resources in specific TX queue */ ++static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ return (pPortCtrl->txQueue[txQueue].resource); ++} ++ ++/* Get number of Free resources in specific RX queue */ ++static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ return (pPortCtrl->rxQueue[rxQueue].resource); ++} ++ ++static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ if(pPortCtrl->txQueue[txQueue].resource == 0) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++/* Get number of Free resources in specific RX queue */ ++static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; ++ ++ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && ++ (pQueueCtrl->resource != 0) ) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && ++ (pQueueCtrl->resource != 0) ) ++ { ++ return MV_TRUE; ++ } ++ return MV_FALSE; ++} ++ ++/* Get number of Free resources in specific RX queue */ ++static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ if(pPortCtrl->rxQueue[rxQueue].resource == 0) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvEthPortTx - Send an Ethernet packet ++* ++* DESCRIPTION: ++* This routine send a given packet described by pPktInfo parameter. ++* Single buffer only. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of Tx queue. ++* MV_PKT_INFO *pPktInfo - User packet to send. ++* ++* RETURN: ++* MV_NO_RESOURCE - No enough resources to send this packet. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - Packet send successfully. ++* ++*******************************************************************************/ ++static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) ++{ ++ ETH_TX_DESC* pTxCurrDesc; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ int portNo; ++ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; ++ ++#ifdef ETH_DEBUG ++ if(pPortCtrl->portState != MV_ACTIVE) ++ return MV_BAD_STATE; ++#endif /* ETH_DEBUG */ ++ ++ portNo = pPortCtrl->portNo; ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ /* Get the Tx Desc ring indexes */ ++ pTxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ /* Check if there is enough resources to send the packet */ ++ if(pQueueCtrl->resource == 0) ++ return MV_NO_RESOURCE; ++ ++ pTxCurrDesc->byteCnt = pBufInfo->dataSize; ++ ++ /* Flash Buffer */ ++ if(pPktInfo->pktSize != 0) ++ { ++#ifdef MV_NETBSD ++ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; ++ ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); ++#else ++ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); ++#endif ++ pPktInfo->pktSize = 0; ++ } ++ else ++ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; ++ ++ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; ++ ++ /* There is only one buffer in the packet */ ++ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ ++ pTxCurrDesc->cmdSts = pPktInfo->status | ++ ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_GENERATE_CRC_MASK | ++ ETH_TX_ENABLE_INTERRUPT_MASK | ++ ETH_TX_ZERO_PADDING_MASK | ++ ETH_TX_FIRST_DESC_MASK | ++ ETH_TX_LAST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ ++ pQueueCtrl->resource--; ++ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); ++ ++ /* Apply send command */ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthPortSgTx - Send an Ethernet packet ++* ++* DESCRIPTION: ++* This routine send a given packet described by pBufInfo parameter. It ++* supports transmitting of a packet spaned over multiple buffers. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of Tx queue. ++* MV_PKT_INFO *pPktInfo - User packet to send. ++* ++* RETURN: ++* MV_NO_RESOURCE - No enough resources to send this packet. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - Packet send successfully. ++* ++*******************************************************************************/ ++static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) ++{ ++ ETH_TX_DESC* pTxFirstDesc; ++ ETH_TX_DESC* pTxCurrDesc; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ int portNo, bufCount; ++ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; ++ MV_U8* pTxBuf; ++ ++#ifdef ETH_DEBUG ++ if(pPortCtrl->portState != MV_ACTIVE) ++ return MV_BAD_STATE; ++#endif /* ETH_DEBUG */ ++ ++ portNo = pPortCtrl->portNo; ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ /* Get the Tx Desc ring indexes */ ++ pTxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ /* Check if there is enough resources to send the packet */ ++ if(pQueueCtrl->resource < pPktInfo->numFrags) ++ return MV_NO_RESOURCE; ++ ++ /* Remember first desc */ ++ pTxFirstDesc = pTxCurrDesc; ++ ++ bufCount = 0; ++ while(MV_TRUE) ++ { ++ if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) ++ { ++ /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ ++ /* to 64-bit boundary. Two options here: */ ++ /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ ++ /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ ++ /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ ++ pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC; ++ mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); ++ pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); ++ } ++ else ++ { ++ /* Flash Buffer */ ++#ifdef MV_NETBSD ++ pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr; ++ ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); ++#else ++ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); ++#endif ++ } ++ ++ pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; ++ bufCount++; ++ ++ if(bufCount >= pPktInfo->numFrags) ++ break; ++ ++ if(bufCount > 1) ++ { ++ /* There is middle buffer of the packet Not First and Not Last */ ++ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ } ++ /* Go to next descriptor and next buffer */ ++ pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); ++ } ++ /* Set last desc with DMA ownership and interrupt enable. */ ++ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; ++ if(bufCount == 1) ++ { ++ /* There is only one buffer in the packet */ ++ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ ++ pTxCurrDesc->cmdSts = pPktInfo->status | ++ ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_GENERATE_CRC_MASK | ++ ETH_TX_ENABLE_INTERRUPT_MASK | ++ ETH_TX_ZERO_PADDING_MASK | ++ ETH_TX_FIRST_DESC_MASK | ++ ETH_TX_LAST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ } ++ else ++ { ++ /* Last but not First */ ++ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_ENABLE_INTERRUPT_MASK | ++ ETH_TX_ZERO_PADDING_MASK | ++ ETH_TX_LAST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ ++ /* Update First when more than one buffer in the packet */ ++ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ ++ pTxFirstDesc->cmdSts = pPktInfo->status | ++ ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_GENERATE_CRC_MASK | ++ ETH_TX_FIRST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); ++ } ++ /* Update txQueue state */ ++ pQueueCtrl->resource -= bufCount; ++ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); ++ ++ /* Apply send command */ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthPortTxDone - Free all used Tx descriptors and mBlks. ++* ++* DESCRIPTION: ++* This routine returns the transmitted packet information to the caller. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of Tx queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. ++* ++* RETURN: ++* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. ++* MV_EMPTY - No transmitted packets to return. TX Queue is empty. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - There is transmitted packet in the queue, ++* 'pPktInfo' filled with relevant information. ++* ++*******************************************************************************/ ++static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue) ++{ ++ ETH_TX_DESC* pTxCurrDesc; ++ ETH_TX_DESC* pTxUsedDesc; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ MV_PKT_INFO* pPktInfo; ++ MV_U32 commandStatus; ++ ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ pTxUsedDesc = pQueueCtrl->pUsedDescr; ++ pTxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ while(MV_TRUE) ++ { ++ /* No more used descriptors */ ++ commandStatus = pTxUsedDesc->cmdSts; ++ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) ++ { ++ ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); ++ return NULL; ++ } ++ if( (pTxUsedDesc == pTxCurrDesc) && ++ (pQueueCtrl->resource != 0) ) ++ { ++ return NULL; ++ } ++ pQueueCtrl->resource++; ++ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); ++ if(commandStatus & (ETH_TX_LAST_DESC_MASK)) ++ { ++ pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo; ++ pPktInfo->status = commandStatus; ++ return pPktInfo; ++ } ++ pTxUsedDesc = pQueueCtrl->pUsedDescr; ++ } ++} ++ ++/******************************************************************************* ++* mvEthPortRx - Get new received packets from Rx queue. ++* ++* DESCRIPTION: ++* This routine returns the received data to the caller. There is no ++* data copying during routine operation. All information is returned ++* using pointer to packet information struct passed from the caller. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int rxQueue - Number of Rx queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to received packet. ++* ++* RETURN: ++* MV_NO_RESOURCE - No free resources in RX queue. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - New packet received and 'pBufInfo' structure filled ++* with relevant information. ++* ++*******************************************************************************/ ++static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue) ++{ ++ ETH_RX_DESC *pRxCurrDesc; ++ MV_U32 commandStatus; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ MV_PKT_INFO* pPktInfo; ++ ++ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); ++ ++ /* Check resources */ ++ if(pQueueCtrl->resource == 0) ++ { ++ mvOsPrintf("ethPortRx: no more resources\n"); ++ return NULL; ++ } ++ while(MV_TRUE) ++ { ++ /* Get the Rx Desc ring 'curr and 'used' indexes */ ++ pRxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ commandStatus = pRxCurrDesc->cmdSts; ++ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) ++ { ++ /* Nothing to receive... */ ++ ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); ++ return NULL; ++ } ++ ++ /* Valid RX only if FIRST and LAST bits are set */ ++ if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == ++ (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) ) ++ { ++ pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo; ++ pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; ++ pPktInfo->status = commandStatus; ++ pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; ++ ++ pQueueCtrl->resource--; ++ /* Update 'curr' in data structure */ ++ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); ++ ++#ifdef INCLUDE_SYNC_BARR ++ mvCpuIfSyncBarr(DRAM_TARGET); ++#endif ++ return pPktInfo; ++ } ++ else ++ { ++ ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr; ++ ++#ifdef ETH_DEBUG ++ mvOsPrintf("ethDrv: Unexpected Jumbo frame: " ++ "status=0x%08x, byteCnt=%d, pData=0x%x\n", ++ commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); ++#endif /* ETH_DEBUG */ ++ ++ /* move buffer from pCurrentDescr position to pUsedDescr position */ ++ pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; ++ pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; ++ pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; ++ ++ /* Return the descriptor to DMA ownership */ ++ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ++ ETH_RX_ENABLE_INTERRUPT_MASK; ++ ++ /* Flush descriptor and CPU pipe */ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); ++ ++ /* Move the used descriptor pointer to the next descriptor */ ++ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); ++ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. ++* ++* DESCRIPTION: ++* This routine returns a Rx buffer back to the Rx ring. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int rxQueue - Number of Rx queue. ++* MV_PKT_INFO *pPktInfo - Pointer to received packet. ++* ++* RETURN: ++* MV_ERROR - Unexpected Fatal error. ++* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be ++* returned to this queue. ++* MV_FULL - Buffer returned successfully and RX queue became full. ++* More buffers should not be returned at the time. ++* MV_OK - Buffer returned successfully and there are more free ++* places in the queue. ++* ++*******************************************************************************/ ++static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo) ++{ ++ ETH_RX_DESC* pRxUsedDesc; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ++ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; ++ ++ /* Get 'used' Rx descriptor */ ++ pRxUsedDesc = pQueueCtrl->pUsedDescr; ++ ++ /* Check that ring is not FULL */ ++ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && ++ (pQueueCtrl->resource != 0) ) ++ { ++ mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", ++ __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource, ++ pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; ++ pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo; ++ pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; ++ ++ /* Invalidate data buffer accordingly with pktSize */ ++ if(pPktInfo->pktSize != 0) ++ { ++ ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); ++ pPktInfo->pktSize = 0; ++ } ++ ++ /* Return the descriptor to DMA ownership */ ++ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; ++ ++ /* Flush descriptor and CPU pipe */ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); ++ ++ pQueueCtrl->resource++; ++ ++ /* Move the used descriptor pointer to the next descriptor */ ++ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); ++ ++ /* If ring became Full return MV_FULL */ ++ if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) ++ return MV_FULL; ++ ++ return MV_OK; ++} ++ ++ ++#endif /* __mvEthGbe_h__ */ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,700 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvEthRegsh ++#define __INCmvEthRegsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++/****************************************/ ++/* Ethernet Unit Registers */ ++/****************************************/ ++#define ETH_REG_BASE MV_ETH_REG_BASE ++ ++#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000) ++#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004) ++#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008) ++#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c) ++#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014) ++#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080) ++#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084) ++ ++ ++#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094) ++#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098) ++#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0) ++ ++#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400) ++#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404) ++#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408) ++#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c) ++#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410) ++#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414) ++#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418) ++#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c) ++#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2)) ++#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c) ++#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440) ++#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444) ++ ++#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680) ++#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448) ++ ++#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c) ++#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450) ++#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454) ++#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458) ++#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c) ++#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460) ++#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464) ++#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468) ++#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c) ++#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474) ++#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c) ++#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484) ++#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488) ++#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494) ++#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc) ++#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0) ++#define ETH_TX_QUEUE_COMMAND1_REG(port) (ETH_REG_BASE(port) + 0x4e4) ++#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8) ++#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec) ++#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780) ++#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4)) ++#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4)) ++#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4)) ++#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4)) ++#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2)) ++ ++#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4)) ++#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4)) ++#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4)) ++ ++#if (MV_ETH_VERSION >= 4) ++#define ETH_TXQ_CMD_1_REG(port) (ETH_REG_BASE(port) + 0x4E4) ++#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8) ++#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8) ++#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0) ++#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4) ++#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8) ++#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0) ++#endif /* MV_ETH_VERSION >= 4 */ ++ ++#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000) ++#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400) ++#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500) ++#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600) ++ ++/* Phy address register definitions */ ++#define ETH_PHY_ADDR_OFFS 0 ++#define ETH_PHY_ADDR_MASK (0x1f <= 4) ++#define ETH_TX_EJP_RESET_BIT 0 ++#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT) ++ ++#define ETH_TX_EJP_ENABLE_BIT 2 ++#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) ++ ++#define ETH_TX_LEGACY_WRR_BIT 3 ++#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++/***** BITs of Ethernet Port Status reg (PSR) *****/ ++#define ETH_LINK_UP_BIT 1 ++#define ETH_LINK_UP_MASK (1<= 4) ++MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode); ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus); ++ ++/* Marvell Header control */ ++MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); ++ ++/* PHY routines */ ++void mvEthPhyAddrSet(void* pPortHandle, int phyAddr); ++int mvEthPhyAddrGet(void* pPortHandle); ++ ++/* Power management routines */ ++void mvEthPortPowerDown(int port); ++void mvEthPortPowerUp(int port); ++ ++/******************** ETH PRIVATE ************************/ ++ ++/*#define UNCACHED_TX_BUFFERS*/ ++/*#define UNCACHED_RX_BUFFERS*/ ++ ++ ++/* Port attributes */ ++/* Size of a Tx/Rx descriptor used in chain list data structure */ ++#define ETH_RX_DESC_ALIGNED_SIZE 32 ++#define ETH_TX_DESC_ALIGNED_SIZE 32 ++ ++#define TX_DISABLE_TIMEOUT_MSEC 1000 ++#define RX_DISABLE_TIMEOUT_MSEC 1000 ++#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 ++#define PORT_DISABLE_WAIT_TCLOCKS 5000 ++ ++/* Macros that save access to desc in order to find next desc pointer */ ++#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \ ++ ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \ ++ (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \ ++ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) ++ ++#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ ++ ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ ++ (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \ ++ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) ++ ++#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ ++ ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ ++ (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \ ++ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) ++ ++#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ ++ ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ ++ (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \ ++ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) ++ ++ ++/* Queue specific information */ ++typedef struct ++{ ++ void* pFirstDescr; ++ void* pLastDescr; ++ void* pCurrentDescr; ++ void* pUsedDescr; ++ int resource; ++ MV_BUF_INFO descBuf; ++} ETH_QUEUE_CTRL; ++ ++ ++/* Ethernet port specific infomation */ ++typedef struct _ethPortCtrl ++{ ++ int portNo; ++ ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ ++ ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ ++ ++ MV_ETH_PORT_CFG portConfig; ++ MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; ++ MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; ++ ++ /* Register images - For DP */ ++ MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ ++ MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ ++ ++ MV_STATE portState; ++ ++ MV_U8 mcastCount[256]; ++ MV_U32* hashPtr; ++ void *osHandle; ++} ETH_PORT_CTRL; ++ ++/************** MACROs ****************/ ++ ++/* MACROs to Flush / Invalidate TX / RX Buffers */ ++#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) ++# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ ++ mvOsCacheClear(NULL, (pAddr), (size)); \ ++ /*CPU_PIPE_FLUSH;*/ ++#else ++# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ ++ mvOsIoVirtToPhy(NULL, (pAddr)); ++#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ ++ ++#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) ) ++# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ ++ mvOsCacheInvalidate (NULL, (pAddr), (size)); \ ++ /*CPU_PIPE_FLUSH;*/ ++#else ++# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) ++#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ ++ ++#ifdef ETH_DESCR_UNCACHED ++ ++#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) ++#define ETH_DESCR_INV(pPortCtrl, pDescr) ++ ++#else ++ ++#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ ++ mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) ++ ++#define ETH_DESCR_INV(pPortCtrl, pDescr) \ ++ mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) ++ ++#endif /* ETH_DESCR_UNCACHED */ ++ ++#include "eth/gbe/mvEthGbe.h" ++ ++#endif /* __mvEth_h__ */ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,362 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "gpp/mvGpp.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value); ++ ++/******************************************************************************* ++* mvGppTypeSet - Enable a GPP (OUT) pin ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the type ++* of corresponding GPP will be set. Other GPPs are ignored. ++* value - 32bit value that describes GPP type per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 to input and GPP15 to output. ++* mvGppTypeSet(0, (GPP8 | GPP15), ++* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value); ++ ++ /* Workaround for Erratum FE-MISC-70*/ ++ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) ++ { ++ mask &= 0x2; ++ gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value); ++ } /*End of WA*/ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the type ++* of corresponding GPP will be set. Other GPPs are ignored. ++* value - 32bit value that describes GPP blink per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 to be static and GPP15 to be blinking. ++* mvGppBlinkEn(0, (GPP8 | GPP15), ++* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value); ++ ++ return MV_OK; ++ ++} ++/******************************************************************************* ++* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the type ++* of corresponding GPP will be set. Other GPPs are ignored. ++* value - 32bit value that describes GPP polarity per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 to the actual pin value and GPP15 to be inverted. ++* mvGppPolaritySet(0, (GPP8 | GPP15), ++* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* returned value is valid for it. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Get GPP8 and GPP15 value. ++* mvGppPolarityGet(0, (GPP8 | GPP15)); ++* ++* RETURN: ++* 32bit value that describes GPP polatity mode per pin. ++* ++*******************************************************************************/ ++MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask) ++{ ++ MV_U32 regVal; ++ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n")); ++ return MV_ERROR; ++ } ++ regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group)); ++ ++ return (regVal & mask); ++} ++ ++/******************************************************************************* ++* mvGppValueGet - Get a GPP Pin list value. ++* ++* DESCRIPTION: ++* This function get GPP value. ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* returned value is valid for it. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Get GPP8 and GPP15 value. ++* mvGppValueGet(0, (GPP8 | GPP15)); ++* ++* RETURN: ++* 32bit value that describes GPP activity mode per pin. ++* ++*******************************************************************************/ ++MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask) ++{ ++ MV_U32 gppData; ++ ++ gppData = MV_REG_READ(GPP_DATA_IN_REG(group)); ++ ++ gppData &= mask; ++ ++ return gppData; ++ ++} ++ ++/******************************************************************************* ++* mvGppValueSet - Set a GPP Pin list value. ++* ++* DESCRIPTION: ++* This function set value for given GPP pin list. ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* value of corresponding GPP will be set accordingly. Other GPP ++* are not affected. ++* value - 32bit value that describes GPP value per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 value of '0' and GPP15 value of '1'. ++* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ MV_U32 outEnable, tmp; ++ MV_U32 i; ++ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ /* verify that the gpp pin is configured as output */ ++ /* Note that in the register out enabled -> bit = '0'. */ ++ outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group)); ++ ++ /* Workaround for Erratum FE-MISC-70*/ ++ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) ++ { ++ tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0)); ++ outEnable &= 0xfffffffd; ++ outEnable |= (tmp & 0x2); ++ } /*End of WA*/ ++ ++ for (i = 0 ; i < 32 ;i++) ++ { ++ if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i))) ++ { ++ mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\ ++ "value to GPP %d in input mode.\n", i); ++ return MV_ERROR; ++ } ++ } ++ ++ gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value); ++ ++ return MV_OK; ++ ++} ++/******************************************************************************* ++* gppRegSet - Set a specific GPP pin on a specific GPP register ++* ++* DESCRIPTION: ++* This function set a specific GPP pin on a specific GPP register ++* ++* INPUT: ++* regOffs - GPP Register offset ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* value of corresponding GPP will be set accordingly. Other GPP ++* are not affected. ++* value - 32bit value that describes GPP value per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 value of '0' and GPP15 value of '1'. ++* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value) ++{ ++ MV_U32 gppData; ++ ++ gppData = MV_REG_READ(regOffs); ++ ++ gppData &= ~mask; ++ ++ gppData |= (value & mask); ++ ++ MV_REG_WRITE(regOffs, gppData); ++} ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,118 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvGppH ++#define __INCmvGppH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "gpp/mvGppRegs.h" ++ ++/* These macros describes the GPP type. Each of the GPPs pins can */ ++/* be assigned to act as a general purpose input or output pin. */ ++#define MV_GPP_IN 0xFFFFFFFF /* GPP input */ ++#define MV_GPP_OUT 0 /* GPP output */ ++ ++ ++/* These macros describes the GPP Out Enable. */ ++#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled*/ ++#define MV_GPP_OUT_EN 0 /* Out pin enabled*/ ++ ++/* These macros describes the GPP Out Blinking. */ ++/* When set and the corresponding bit in GPIO Data Out Enable Control */ ++/* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */ ++/* 2^24 TCLK clocks). */ ++#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking*/ ++#define MV_GPP_OUT_STATIC 0 /* Out pin static*/ ++ ++ ++/* These macros describes the GPP Polarity. */ ++/* When set to 1 GPIO Data In Register reflects the inverted value of the */ ++/* corresponding pin. */ ++ ++#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got*/ ++#define MV_GPP_IN_ORIGIN 0 /* original value is got*/ ++ ++/* mvGppTypeSet - Set PP pin mode (IN or OUT) */ ++MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++/* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */ ++MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++/* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */ ++MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++/* mvGppPolarityGet - Get the Polarity of a GPP Pin */ ++MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask); ++ ++/* mvGppValueGet - Get a GPP Pin list value.*/ ++MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); ++ ++ ++/* mvGppValueSet - Set a GPP Pin list value. */ ++MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++#endif /* #ifndef __INCmvGppH */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,116 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvGppRegsH ++#define __INCmvGppRegsH ++ ++#define MV_GPP0 BIT0 ++#define MV_GPP1 BIT1 ++#define MV_GPP2 BIT2 ++#define MV_GPP3 BIT3 ++#define MV_GPP4 BIT4 ++#define MV_GPP5 BIT5 ++#define MV_GPP6 BIT6 ++#define MV_GPP7 BIT7 ++#define MV_GPP8 BIT8 ++#define MV_GPP9 BIT9 ++#define MV_GPP10 BIT10 ++#define MV_GPP11 BIT11 ++#define MV_GPP12 BIT12 ++#define MV_GPP13 BIT13 ++#define MV_GPP14 BIT14 ++#define MV_GPP15 BIT15 ++#define MV_GPP16 BIT16 ++#define MV_GPP17 BIT17 ++#define MV_GPP18 BIT18 ++#define MV_GPP19 BIT19 ++#define MV_GPP20 BIT20 ++#define MV_GPP21 BIT21 ++#define MV_GPP22 BIT22 ++#define MV_GPP23 BIT23 ++#define MV_GPP24 BIT24 ++#define MV_GPP25 BIT25 ++#define MV_GPP26 BIT26 ++#define MV_GPP27 BIT27 ++#define MV_GPP28 BIT28 ++#define MV_GPP29 BIT29 ++#define MV_GPP30 BIT30 ++#define MV_GPP31 BIT31 ++ ++ ++/* registers offsets */ ++ ++#define GPP_DATA_OUT_REG(grp) ((grp == 0) ? 0x10100 : 0x10140) ++#define GPP_DATA_OUT_EN_REG(grp) ((grp == 0) ? 0x10104 : 0x10144) ++#define GPP_BLINK_EN_REG(grp) ((grp == 0) ? 0x10108 : 0x10148) ++#define GPP_DATA_IN_POL_REG(grp) ((grp == 0) ? 0x1010C : 0x1014c) ++#define GPP_DATA_IN_REG(grp) ((grp == 0) ? 0x10110 : 0x10150) ++#define GPP_INT_CAUSE_REG(grp) ((grp == 0) ? 0x10114 : 0x10154) ++#define GPP_INT_MASK_REG(grp) ((grp == 0) ? 0x10118 : 0x10158) ++#define GPP_INT_LVL_REG(grp) ((grp == 0) ? 0x1011c : 0x1015c) ++ ++#define GPP_DATA_OUT_SET_REG 0x10120 ++#define GPP_DATA_OUT_CLEAR_REG 0x10124 ++ ++#endif /* #ifndef __INCmvGppRegsH */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,1047 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "pci/mvPci.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++ ++ ++MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod) ++{ ++ if (MV_PCI_MOD_HOST == pciIfmod) ++ { ++ ++ mvPciLocalBusNumSet(pciIf, PCI_HOST_BUS_NUM(pciIf)); ++ mvPciLocalDevNumSet(pciIf, PCI_HOST_DEV_NUM(pciIf)); ++ ++ /* Local device master Enable */ ++ mvPciMasterEnable(pciIf, MV_TRUE); ++ ++ /* Local device slave Enable */ ++ mvPciSlaveEnable(pciIf, mvPciLocalBusNumGet(pciIf), ++ mvPciLocalDevNumGet(pciIf), MV_TRUE); ++ } ++ /* enable CPU-2-PCI ordering */ ++ MV_REG_BIT_SET(PCI_CMD_REG(0), PCR_CPU_TO_PCI_ORDER_EN); ++} ++ ++/******************************************************************************* ++* mvPciCommandSet - Set PCI comman register value. ++* ++* DESCRIPTION: ++* This function sets a given PCI interface with its command register ++* value. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* command - 32bit value to be written to comamnd register. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if pciIf is not in range otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command) ++{ ++ MV_U32 locBusNum, locDevNum, regVal; ++ ++ locBusNum = mvPciLocalBusNumGet(pciIf); ++ locDevNum = mvPciLocalDevNumGet(pciIf); ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Set command register */ ++ MV_REG_WRITE(PCI_CMD_REG(pciIf), command); ++ ++ /* Upodate device max outstanding split tarnsaction */ ++ if ((command & PCR_CPU_TO_PCI_ORDER_EN) && ++ (command & PCR_PCI_TO_CPU_ORDER_EN)) ++ { ++ /* Read PCI-X command register */ ++ regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND); ++ ++ /* clear bits 22:20 */ ++ regVal &= 0xff8fffff; ++ ++ /* set reset value */ ++ regVal |= (0x3 << 20); ++ ++ /* Write back the value */ ++ mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal); ++ } ++ ++ return MV_OK; ++ ++ ++} ++ ++ ++/******************************************************************************* ++* mvPciModeGet - Get PCI interface mode. ++* ++* DESCRIPTION: ++* This function returns the given PCI interface mode. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* ++* OUTPUT: ++* pPciMode - Pointer to PCI mode structure. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode) ++{ ++ MV_U32 pciMode; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (NULL == pPciMode) ++ { ++ mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n"); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Read pci mode register */ ++ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); ++ ++ switch (pciMode & PMR_PCI_MODE_MASK) ++ { ++ case PMR_PCI_MODE_CONV: ++ pPciMode->pciType = MV_PCI_CONV; ++ ++ if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN) ++ { ++ pPciMode->pciSpeed = 66000000; /* 66MHZ */ ++ } ++ else ++ { ++ pPciMode->pciSpeed = 33000000; /* 33MHZ */ ++ } ++ ++ break; ++ ++ case PMR_PCI_MODE_PCIX_66MHZ: ++ pPciMode->pciType = MV_PCIX; ++ pPciMode->pciSpeed = 66000000; /* 66MHZ */ ++ break; ++ ++ case PMR_PCI_MODE_PCIX_100MHZ: ++ pPciMode->pciType = MV_PCIX; ++ pPciMode->pciSpeed = 100000000; /* 100MHZ */ ++ break; ++ ++ case PMR_PCI_MODE_PCIX_133MHZ: ++ pPciMode->pciType = MV_PCIX; ++ pPciMode->pciSpeed = 133000000; /* 133MHZ */ ++ break; ++ ++ default: ++ { ++ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); ++ return MV_ERROR; ++ } ++ } ++ ++ switch (pciMode & PMR_PCI_64_MASK) ++ { ++ case PMR_PCI_64_64BIT: ++ pPciMode->pciWidth = MV_PCI_64; ++ break; ++ ++ case PMR_PCI_64_32BIT: ++ pPciMode->pciWidth = MV_PCI_32; ++ break; ++ ++ default: ++ { ++ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); ++ return MV_ERROR; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciRetrySet - Set PCI retry counters ++* ++* DESCRIPTION: ++* This function specifies the number of times the PCI controller ++* retries a transaction before it quits. ++* Applies to the PCI Master when acting as a requester. ++* Applies to the PCI slave when acting as a completer (PCI-X mode). ++* A 0x00 value means a "retry forever". ++* ++* INPUT: ++* pciIf - PCI interface number. ++* counter - Number of times PCI controller retry. Use counter value ++* up to PRR_RETRY_CNTR_MAX. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter) ++{ ++ MV_U32 pciRetry; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (counter >= PRR_RETRY_CNTR_MAX) ++ { ++ mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* Reading PCI retry register */ ++ pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf)); ++ ++ pciRetry &= ~PRR_RETRY_CNTR_MASK; ++ ++ pciRetry |= (counter << PRR_RETRY_CNTR_OFFS); ++ ++ /* write new value */ ++ MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciDiscardTimerSet - Set PCI discard timer ++* ++* DESCRIPTION: ++* This function set PCI discard timer. ++* In conventional PCI mode: ++* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed ++* read buffers (non-completed delayed read) before invalidate the buffer. ++* Set to '0' to disable the timer. The PCI slave waits for delayed ++* read completion forever. ++* In PCI-X mode: ++* Specifies the number of PCLK cycles the PCI master waits for split ++* completion transaction, before it invalidates the pre-allocated read ++* buffer. ++* Set to '0' to disable the timer. The PCI master waits for split ++* completion forever. ++* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK, ++* unless using the "wait for ever" setting 0x0. ++* NOTE: Must not be updated while there are pending read requests. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* pClkCycles - Number of PCI clock cycles. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles) ++{ ++ MV_U32 pciDiscardTimer; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (pClkCycles >= PDTR_TIMER_MIN) ++ { ++ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n", ++ pClkCycles); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* Read PCI Discard Timer */ ++ pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf)); ++ ++ pciDiscardTimer &= ~PDTR_TIMER_MASK; ++ ++ pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS); ++ ++ /* Write new value */ ++ MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer); ++ ++ return MV_OK; ++ ++} ++ ++/* PCI Arbiter routines */ ++ ++/******************************************************************************* ++* mvPciArbEnable - PCI arbiter enable/disable ++* ++* DESCRIPTION: ++* This fuction enable/disables a given PCI interface arbiter. ++* NOTE: Arbiter setting can not be changed while in work. It should only ++* be set once. ++* INPUT: ++* pciIf - PCI interface number. ++* enable - Enable/disable parameter. If enable = MV_TRUE then enable. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable) ++{ ++ MV_U32 regVal; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_ERROR; ++ } ++ ++ /* Set PCI Arbiter Control register according to default configuration */ ++ regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); ++ ++ /* Make sure arbiter disabled before changing its values */ ++ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); ++ ++ regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK; ++ ++ regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */ ++ ++ if (MV_TRUE == enable) ++ { ++ regVal |= PACR_ARB_ENABLE; ++ } ++ else ++ { ++ regVal &= ~PACR_ARB_ENABLE; ++ } ++ ++ /* Write to register */ ++ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciArbParkDis - Disable arbiter parking on agent ++* ++* DESCRIPTION: ++* This function disables the PCI arbiter from parking on the given agent ++* list. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* pciAgentMask - When a bit in the mask is set to '1', parking on ++* the associated PCI master is disabled. Mask bit ++* refers to bit 0 - 6. For example disable parking on PCI ++* agent 3 set pciAgentMask 0x4 (bit 3 is set). ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask) ++{ ++ MV_U32 pciArbiterCtrl; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_ERROR; ++ } ++ ++ /* Reading Arbiter Control register */ ++ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); ++ ++ /* Arbiter must be disabled before changing parking */ ++ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); ++ ++ /* do the change */ ++ pciArbiterCtrl &= ~PACR_PARK_DIS_MASK; ++ pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS); ++ ++ /* writing new value ( if th earbiter was enabled before the change */ ++ /* here it will be reenabled */ ++ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciArbBrokDetectSet - Set PCI arbiter broken detection ++* ++* DESCRIPTION: ++* This function sets the maximum number of cycles that the arbiter ++* waits for a PCI master to respond to its grant assertion. If a ++* PCI agent fails to respond within this time, the PCI arbiter aborts ++* the transaction and performs a new arbitration cycle. ++* NOTE: Value must be greater than '1' for conventional PCI and ++* greater than '5' for PCI-X. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken ++* master detection is disabled. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles) ++{ ++ MV_U32 pciArbiterCtrl; ++ MV_U32 pciMode; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Checking PCI mode and if pClkCycles is legal value */ ++ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); ++ pciMode &= PMR_PCI_MODE_MASK; ++ ++ if (PMR_PCI_MODE_CONV == pciMode) ++ { ++ if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN) ++ return MV_ERROR; ++ } ++ else ++ { ++ if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN) ++ return MV_ERROR; ++ } ++ ++ pClkCycles <<= PACR_BROKEN_VAL_OFFS; ++ ++ /* Reading Arbiter Control register */ ++ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); ++ pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK; ++ pciArbiterCtrl |= pClkCycles; ++ ++ /* Arbiter must be disabled before changing broken detection */ ++ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); ++ ++ /* writing new value ( if th earbiter was enabled before the change */ ++ /* here it will be reenabled */ ++ ++ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); ++ ++ return MV_OK; ++} ++ ++/* PCI configuration space read write */ ++ ++/******************************************************************************* ++* mvPciConfigRead - Read from configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit read from PCI configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to read from local bus segment, use ++* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pciIf - PCI interface number. ++* bus - PCI segment bus number. ++* dev - PCI device number. ++* func - Function number. ++* regOffs - Register offset. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit register data, 0xffffffff on error ++* ++*******************************************************************************/ ++MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++ MV_U32 pciData = 0; ++ ++ /* Parameter checking */ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ if (dev >= MAX_PCI_DEVICES) ++ { ++ DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (func >= MAX_PCI_FUNCS) ++ { ++ DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (bus >= MAX_PCI_BUSSES) ++ { ++ DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus)); ++ return MV_ERROR; ++ } ++ ++ ++ /* Creating PCI address to be passed */ ++ pciData |= (bus << PCAR_BUS_NUM_OFFS); ++ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); ++ pciData |= (func << PCAR_FUNC_NUM_OFFS); ++ pciData |= (regOff & PCAR_REG_NUM_MASK); ++ ++ pciData |= PCAR_CONFIG_EN; ++ ++ /* Write the address to the PCI configuration address register */ ++ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); ++ ++ /* In order to let the PCI controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) ++ { ++ return MV_ERROR; ++ } ++ /* Read the Data returned in the PCI Data register */ ++ pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf)); ++ ++ return pciData; ++} ++ ++/******************************************************************************* ++* mvPciConfigWrite - Write to configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit write to PCI configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to write to local bus segment, use ++* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pciIf - PCI interface number. ++* bus - PCI segment bus number. ++* dev - PCI device number. ++* func - Function number. ++* regOffs - Register offset. ++* data - 32bit data. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++ MV_U32 pciData = 0; ++ ++ /* Parameter checking */ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ if (dev >= MAX_PCI_DEVICES) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev); ++ return MV_BAD_PARAM; ++ } ++ ++ if (func >= MAX_PCI_FUNCS) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func); ++ return MV_ERROR; ++ } ++ ++ if (bus >= MAX_PCI_BUSSES) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus); ++ return MV_ERROR; ++ } ++ ++ /* Creating PCI address to be passed */ ++ pciData |= (bus << PCAR_BUS_NUM_OFFS); ++ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); ++ pciData |= (func << PCAR_FUNC_NUM_OFFS); ++ pciData |= (regOff & PCAR_REG_NUM_MASK); ++ ++ pciData |= PCAR_CONFIG_EN; ++ ++ /* Write the address to the PCI configuration address register */ ++ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); ++ ++ /* In order to let the PCI controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) ++ { ++ return MV_ERROR; ++ } ++ ++ /* Write the Data passed to the PCI Data register */ ++ MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciMasterEnable - Enable/disale PCI interface master transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PCI command status ++* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI ++* master is allowed to gain ownership on the bus, otherwise it is ++* incapable to do so. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable) ++{ ++ MV_U32 pciCommandStatus; ++ MV_U32 RegOffs; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_ERROR; ++ } ++ ++ localBus = mvPciLocalBusNumGet(pciIf); ++ localDev = mvPciLocalDevNumGet(pciIf); ++ ++ RegOffs = PCI_STATUS_AND_COMMAND; ++ ++ pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs); ++ ++ if (MV_TRUE == enable) ++ { ++ pciCommandStatus |= PSCR_MASTER_EN; ++ } ++ else ++ { ++ pciCommandStatus &= ~PSCR_MASTER_EN; ++ } ++ ++ mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PCI command status ++* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, ++* the PCI slave is allowed to respond to PCI IO space access (bit 0) ++* and PCI memory space access (bit 1). ++* ++* INPUT: ++* pciIf - PCI interface number. ++* dev - PCI device number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) ++{ ++ MV_U32 pciCommandStatus; ++ MV_U32 RegOffs; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (dev >= MAX_PCI_DEVICES) ++ { ++ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ RegOffs = PCI_STATUS_AND_COMMAND; ++ ++ pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs); ++ ++ if (MV_TRUE == enable) ++ { ++ pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN); ++ } ++ else ++ { ++ pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN); ++ } ++ ++ mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciLocalBusNumSet - Set PCI interface local bus number. ++* ++* DESCRIPTION: ++* This function sets given PCI interface its local bus number. ++* Note: In case the PCI interface is PCI-X, the information is read-only. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* busNum - Bus number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PCI interface is PCI-X. ++* MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) ++{ ++ MV_U32 pciP2PConfig; ++ MV_PCI_MODE pciMode; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (busNum >= MAX_PCI_BUSSES) ++ { ++ mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum); ++ return MV_ERROR; ++ ++ } ++ ++ localBus = mvPciLocalBusNumGet(pciIf); ++ localDev = mvPciLocalDevNumGet(pciIf); ++ ++ ++ /* PCI interface mode */ ++ mvPciModeGet(pciIf, &pciMode); ++ ++ /* if PCI type is PCI-X then it is not allowed to change the dev number */ ++ if (MV_PCIX == pciMode.pciType) ++ { ++ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); ++ ++ pciP2PConfig &= ~PXS_BN_MASK; ++ ++ pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK; ++ ++ mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); ++ ++ } ++ else ++ { ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ ++ pciP2PConfig &= ~PPCR_BUS_NUM_MASK; ++ ++ pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK; ++ ++ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); ++ ++ } ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciLocalBusNumGet - Get PCI interface local bus number. ++* ++* DESCRIPTION: ++* This function gets the local bus number of a given PCI interface. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local bus number.0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf) ++{ ++ MV_U32 pciP2PConfig; ++ ++ /* Parameter checking */ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ pciP2PConfig &= PPCR_BUS_NUM_MASK; ++ return (pciP2PConfig >> PPCR_BUS_NUM_OFFS); ++} ++ ++ ++/******************************************************************************* ++* mvPciLocalDevNumSet - Set PCI interface local device number. ++* ++* DESCRIPTION: ++* This function sets given PCI interface its local device number. ++* Note: In case the PCI interface is PCI-X, the information is read-only. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* devNum - Device number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) ++{ ++ MV_U32 pciP2PConfig; ++ MV_PCI_MODE pciMode; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (devNum >= MAX_PCI_DEVICES) ++ { ++ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", ++ devNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ localBus = mvPciLocalBusNumGet(pciIf); ++ localDev = mvPciLocalDevNumGet(pciIf); ++ ++ /* PCI interface mode */ ++ mvPciModeGet(pciIf, &pciMode); ++ ++ /* if PCI type is PCIX then it is not allowed to change the dev number */ ++ if (MV_PCIX == pciMode.pciType) ++ { ++ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); ++ ++ pciP2PConfig &= ~PXS_DN_MASK; ++ ++ pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK; ++ ++ mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); ++ } ++ else ++ { ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ ++ pciP2PConfig &= ~PPCR_DEV_NUM_MASK; ++ ++ pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK; ++ ++ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciLocalDevNumGet - Get PCI interface local device number. ++* ++* DESCRIPTION: ++* This function gets the local device number of a given PCI interface. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local device number. 0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf) ++{ ++ MV_U32 pciP2PConfig; ++ ++ /* Parameter checking */ ++ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ ++ pciP2PConfig &= PPCR_DEV_NUM_MASK; ++ ++ return (pciP2PConfig >> PPCR_DEV_NUM_OFFS); ++} ++ ++ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,185 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCPCIH ++#define __INCPCIH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "pci/mvPciRegs.h" ++ ++ ++/* NOTE not supported in this driver: ++ ++ Built In Self Test (BIST) ++ Vital Product Data (VPD) ++ Message Signaled Interrupt (MSI) ++ Power Management ++ Compact PCI Hot Swap ++ Header retarget ++ ++Registers not supported: ++1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0) ++2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C) ++*/ ++ ++/* defines */ ++/* The number of supported PCI interfaces depend on Marvell controller */ ++/* device number. This device number ID is located on the PCI unit */ ++/* configuration header. This creates a loop where calling PCI */ ++/* configuration read/write routine results a call to get PCI configuration */ ++/* information etc. This macro defines a default PCI interface. This PCI */ ++/* interface is sure to exist. */ ++#define PCI_DEFAULT_IF 0 ++ ++ ++/* typedefs */ ++/* The Marvell controller supports both conventional PCI and PCI-X. */ ++/* This enumeration describes the PCI type. */ ++typedef enum _mvPciType ++{ ++ MV_PCI_CONV, /* Conventional PCI */ ++ MV_PCIX /* PCI-X */ ++}MV_PCI_TYPE; ++ ++typedef enum _mvPciMod ++{ ++ MV_PCI_MOD_HOST, ++ MV_PCI_MOD_DEVICE ++}MV_PCI_MOD; ++ ++ ++/* The Marvell controller supports both PCI width of 32 and 64 bit. */ ++/* This enumerator describes PCI width */ ++typedef enum _mvPciWidth ++{ ++ MV_PCI_32, /* PCI width 32bit */ ++ MV_PCI_64 /* PCI width 64bit */ ++}MV_PCI_WIDTH; ++ ++/* This structure describes the PCI unit configured type, speed and width. */ ++typedef struct _mvPciMode ++{ ++ MV_PCI_TYPE pciType; /* PCI type */ ++ MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */ ++ MV_PCI_WIDTH pciWidth; /* PCI bus width */ ++}MV_PCI_MODE; ++ ++/* mvPciInit - Initialize PCI interfaces*/ ++MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); ++ ++/* mvPciCommandSet - Set PCI comman register value.*/ ++MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command); ++ ++/* mvPciModeGet - Get PCI interface mode.*/ ++MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode); ++ ++/* mvPciRetrySet - Set PCI retry counters*/ ++MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter); ++ ++/* mvPciDiscardTimerSet - Set PCI discard timer*/ ++MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles); ++ ++/* mvPciArbEnable - PCI arbiter enable/disable*/ ++MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable); ++ ++/* mvPciArbParkDis - Disable arbiter parking on agent */ ++MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask); ++ ++/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */ ++MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles); ++ ++/* mvPciConfigRead - Read from configuration space */ ++MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPciConfigWrite - Write to configuration space */ ++MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/ ++MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable); ++ ++/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/ ++MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable); ++ ++/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/ ++MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); ++ ++/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/ ++MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf); ++ ++/* mvPciLocalDevNumSet - Set PCI interface local device number.*/ ++MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); ++ ++/* mvPciLocalDevNumGet - Get PCI interface local device number.*/ ++MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf); ++ ++ ++#endif /* #ifndef __INCPCIH */ ++ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,411 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPCIREGSH ++#define __INCPCIREGSH ++ ++ ++#include "pci-if/mvPciIfRegs.h" ++/* defines */ ++#define MAX_PCI_DEVICES 32 ++#define MAX_PCI_FUNCS 8 ++#define MAX_PCI_BUSSES 128 ++ ++/* enumerators */ ++ ++/* This enumerator described the possible PCI slave targets. */ ++/* PCI slave targets are designated memory/IO address spaces that the */ ++/* PCI slave targets can access. They are also refered as "targets" */ ++/* this enumeratoe order is determined by the content of : ++ PCI_BASE_ADDR_ENABLE_REG */ ++ ++ ++/* registers offsetes defines */ ++ ++ ++ ++/*************************/ ++/* PCI control registers */ ++/*************************/ ++/* maen : should add new registers */ ++#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) ++#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) ++#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) ++#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) ++#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) ++#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) ++#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ ++ (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) ++#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ ++ (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) ++#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ ++ (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) ++ ++#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) ++ ++/* PCI Dll Control (PDC)*/ ++#define PDC_DLL_EN BIT0 ++ ++ ++/* PCI Command Register (PCR) */ ++#define PCR_MASTER_BYTE_SWAP_EN BIT0 ++#define PCR_MASTER_WR_COMBINE_EN BIT4 ++#define PCR_MASTER_RD_COMBINE_EN BIT5 ++#define PCR_MASTER_WR_TRIG_WHOLE BIT6 ++#define PCR_MASTER_RD_TRIG_WHOLE BIT7 ++#define PCR_MASTER_MEM_RD_LINE_EN BIT8 ++#define PCR_MASTER_MEM_RD_MULT_EN BIT9 ++#define PCR_MASTER_WORD_SWAP_EN BIT10 ++#define PCR_SLAVE_WORD_SWAP_EN BIT11 ++#define PCR_NS_ACCORDING_RCV_TRANS BIT14 ++#define PCR_MASTER_PCIX_REQ64N_EN BIT15 ++#define PCR_SLAVE_BYTE_SWAP_EN BIT16 ++#define PCR_MASTER_DAC_EN BIT17 ++#define PCR_MASTER_M64_ALLIGN BIT18 ++#define PCR_ERRORS_PROPAGATION_EN BIT19 ++#define PCR_SLAVE_SWAP_ENABLE BIT20 ++#define PCR_MASTER_SWAP_ENABLE BIT21 ++#define PCR_MASTER_INT_SWAP_EN BIT22 ++#define PCR_LOOP_BACK_ENABLE BIT23 ++#define PCR_SLAVE_INTREG_SWAP_OFFS 24 ++#define PCR_SLAVE_INTREG_SWAP_MASK 0x3 ++#define PCR_SLAVE_INTREG_BYTE_SWAP \ ++ (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_SLAVE_INTREG_NO_SWAP \ ++ (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_SLAVE_INTREG_BYTE_WORD \ ++ (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_SLAVE_INTREG_WORD_SWAP \ ++ (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_RESET_REASSERTION_EN BIT26 ++#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 ++#define PCR_CPU_TO_PCI_ORDER_EN BIT29 ++#define PCR_PCI_TO_CPU_ORDER_EN BIT30 ++ ++/* PCI Mode Register (PMR) */ ++#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ ++#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) ++#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) ++ ++#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ ++#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) ++#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) ++#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) ++ ++#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ ++#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) ++ ++#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ ++ ++#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ ++#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) ++#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) ++ ++ ++/* PCI Retry Register (PRR) */ ++#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ ++#define PRR_RETRY_CNTR_MAX 0xff ++#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) ++ ++ ++/* PCI Discard Timer Register (PDTR) */ ++#define PDTR_TIMER_OFFS 0 /* Timer */ ++#define PDTR_TIMER_MAX 0xffff ++#define PDTR_TIMER_MIN 0x7F ++#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) ++ ++ ++/* PCI Arbiter Control Register (PACR) */ ++#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ ++ ++#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ ++#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) ++#define PACR_BROKEN_VAL_CONV_MIN 0x2 ++#define PACR_BROKEN_VAL_PCIX_MIN 0x6 ++ ++#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ ++#define PACR_PARK_DIS_MAX_AGENT 0x3f ++#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<= MV_PCI_START_IF)&&(pciIf < MV_PCI_MAX_IF + MV_PCI_START_IF)) ++ { ++ return PCI_IF_TYPE_CONVEN_PCIX; ++ } ++ else if ((pciIf >= MV_PEX_START_IF) && ++ (pciIf < MV_PEX_MAX_IF + MV_PEX_START_IF)) ++ { ++ return PCI_IF_TYPE_PEX; ++ ++ } ++ else ++ { ++ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); ++ } ++ ++ return 0xffffffff; ++ ++} ++ ++/******************************************************************************* ++* mvPciIfTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++ ++MV_U32 mvPciRealIfNumGet(MV_U32 pciIf) ++{ ++ ++ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); ++ ++ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) ++ { ++ return (pciIf - MV_PCI_START_IF); ++ } ++ else if (PCI_IF_TYPE_PEX == pciIfType) ++ { ++ return (pciIf - MV_PEX_START_IF); ++ ++ } ++ else ++ { ++ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); ++ } ++ ++ return 0xffffffff; ++ ++} ++ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,134 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPCIIFH ++#define __INCPCIIFH ++ ++#include "mvSysHwConfig.h" ++#include "pci-if/mvPciIfRegs.h" ++#if defined(MV_INCLUDE_PEX) ++#include "pex/mvPex.h" ++#endif ++#if defined(MV_INCLUDE_PCI) ++#include "pci/mvPci.h" ++#endif ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++typedef enum _mvPCIIfType ++{ ++ PCI_IF_TYPE_CONVEN_PCIX, ++ PCI_IF_TYPE_PEX ++ ++}PCI_IF_TYPE; ++ ++typedef enum _mvPCIIfMode ++{ ++ PCI_IF_MODE_HOST, ++ PCI_IF_MODE_DEVICE ++}PCI_IF_MODE; ++ ++ ++/* Global Functions prototypes */ ++ ++/* mvPciIfInit - Initialize PCI interfaces*/ ++MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode); ++ ++/* mvPciIfConfigRead - Read from configuration space */ ++MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPciIfConfigWrite - Write to configuration space */ ++MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/ ++MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable); ++ ++/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/ ++MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, ++ MV_BOOL enable); ++ ++/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/ ++MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); ++ ++/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/ ++MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf); ++ ++/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/ ++MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); ++ ++/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/ ++MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf); ++ ++/* mvPciIfTypeGet - Get PCI If type*/ ++PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf); ++ ++MV_U32 mvPciRealIfNumGet(MV_U32 pciIf); ++ ++/* mvPciIfAddrDecShow - Display address decode windows attributes */ ++MV_VOID mvPciIfAddrDecShow(MV_VOID); ++ ++#endif /* #ifndef __INCPCIIFH */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,245 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPCIIFREGSH ++#define __INCPCIIFREGSH ++ ++ ++/* defines */ ++#define MAX_PCI_DEVICES 32 ++#define MAX_PCI_FUNCS 8 ++#define MAX_PCI_BUSSES 128 ++ ++/***************************************/ ++/* PCI Configuration registers */ ++/***************************************/ ++ ++/*********************************************/ ++/* PCI Configuration, Function 0, Registers */ ++/*********************************************/ ++ ++ ++/* Standard registers */ ++#define PCI_DEVICE_AND_VENDOR_ID 0x000 ++#define PCI_STATUS_AND_COMMAND 0x004 ++#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 ++#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C ++#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) ++#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C ++#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 ++#define PCI_CAPABILTY_LIST_POINTER 0x034 ++#define PCI_INTERRUPT_PIN_AND_LINE 0x03C ++ ++ ++/* PCI Device and Vendor ID Register (PDVIR) */ ++#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */ ++#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS) ++ ++#define PDVIR_DEV_ID_OFFS 16 /* Device ID */ ++#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS) ++ ++/* PCI Status and Command Register (PSCR) */ ++#define PSCR_IO_EN BIT0 /* IO Enable */ ++#define PSCR_MEM_EN BIT1 /* Memory Enable */ ++#define PSCR_MASTER_EN BIT2 /* Master Enable */ ++#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */ ++#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */ ++#define PSCR_VGA BIT5 /* VGA Palette Snoops */ ++#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */ ++#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En)*/ ++#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */ ++#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions*/ ++#define PSCR_CAP_LIST BIT20 /* Capability List Support */ ++#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */ ++#define PSCR_UDF_EN BIT22 /* User definable features */ ++#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */ ++#define PSCR_DATA_PERR BIT24 /* Data Parity reported */ ++ ++#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */ ++#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS) ++#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS) ++#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS) ++#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS) ++ ++#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */ ++#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */ ++#define PSCR_MABORT BIT29 /* Recieved Master Abort */ ++#define PSCR_SYSERR BIT30 /* Signalled system error */ ++#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */ ++ ++/* PCI configuration register offset=0x08 fields ++ (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */ ++ ++#define PCCRIR_REVID_OFFS 0 /* Revision ID */ ++#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) ++ ++#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */ ++#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS) ++ ++#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F*/ ++#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS) ++ ++#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class*/ ++#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS) ++ ++#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class*/ ++#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS) ++ ++/* PCI configuration register offset=0x0C fields ++ (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */ ++ ++#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */ ++#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS) ++ ++#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */ ++#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS) ++ ++#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ ++#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS) ++ ++#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */ ++ ++#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */ ++#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS) ++#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS) ++#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS) ++ ++ ++#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */ ++#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS) ++ ++#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */ ++#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */ ++ ++ ++/* PCI Bar Base Low Register (PBBLR) */ ++#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */ ++ ++#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */ ++#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS) ++#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS) ++#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS) ++ ++#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */ ++ ++ ++#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to ++ address bits [31:4] */ ++#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS) ++ ++#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to ++ address bits [31:2] */ ++#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS) ++ ++ ++#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */ ++#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS) ++#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS) ++ ++ ++/* PCI Bar Base High Fegister (PBBHR) */ ++#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */ ++#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) ++ ++ ++/* PCI configuration register offset=0x2C fields ++ (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */ ++ ++#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ ++#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS) ++ ++#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */ ++#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS) ++ ++/* PCI configuration register offset=0x30 fields ++ (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */ ++ ++#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ ++ ++#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */ ++#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS) ++ ++/* PCI configuration register offset=0x34 fields ++ (PCI_CAPABILTY_LIST_POINTER)(PCLP) */ ++ ++#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */ ++#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS) ++ ++/* PCI configuration register offset=0x3C fields ++ (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */ ++ ++#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ ++#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS) ++ ++#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ ++#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS) ++ ++#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */ ++#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS) ++ ++#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */ ++#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS) ++ ++#endif /* #ifndef __INCPCIIFREGSH */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,1006 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/* includes */ ++#include "mvPciUtils.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* #define MV_DEBUG */ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++ #define mvOsPrintf printf ++#else ++ #define DB(x) ++#endif ++ ++/* ++This module only support scanning of Header type 00h of pci devices ++There is no suppotr for Header type 01h of pci devices ( PCI bridges ) ++*/ ++ ++ ++static MV_STATUS pciDetectDevice(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent); ++ ++static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent); ++ ++ ++ ++ ++ ++ ++/******************************************************************************* ++* mvPciScan - Scan a PCI interface bus ++* ++* DESCRIPTION: ++* Performs a full scan on a PCI interface and returns all possible details ++* on the agents found on the bus. ++* ++* INPUT: ++* pciIf - PCI Interface ++* pPciAgents - Pointer to an Array of the pci agents to be detected ++* pPciAgentsNum - pPciAgents array maximum number of elements ++* ++* OUTPUT: ++* pPciAgents - Array of the pci agents detected on the bus ++* pPciAgentsNum - Number of pci agents detected on the bus ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++MV_STATUS mvPciScan(MV_U32 pciIf, ++ MV_PCI_DEVICE *pPciAgents, ++ MV_U32 *pPciAgentsNum) ++{ ++ ++ MV_U32 devIndex,funcIndex=0,busIndex=0,detectedDevNum=0; ++ MV_U32 localBus=mvPciIfLocalBusNumGet(pciIf); ++ MV_PCI_DEVICE *pPciDevice; ++ MV_PCI_DEVICE *pMainDevice; ++ ++ DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf)); ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPexMaxIfGet()) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf)); ++ return MV_BAD_PARAM; ++ } ++ if (NULL == pPciAgents) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n")); ++ return MV_BAD_PARAM; ++ } ++ if (NULL == pPciAgentsNum) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf)); ++ /* Master enable the MV PCI master */ ++ if (MV_OK != mvPciIfMasterEnable(pciIf,MV_TRUE)) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n")); ++ return MV_ERROR; ++ ++ } ++ ++ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf)); ++ ++ /* go through all busses */ ++ for (busIndex=localBus ; busIndex < MAX_PCI_BUSSES ; busIndex++) ++ { ++ /* go through all possible devices on the local bus */ ++ for (devIndex=0 ; devIndex < MAX_PCI_DEVICES ; devIndex++) ++ { ++ /* always start with function equal to zero */ ++ funcIndex=0; ++ ++ pPciDevice=&pPciAgents[detectedDevNum]; ++ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex)); ++ ++ if (MV_ERROR == pciDetectDevice(pciIf, ++ busIndex, ++ devIndex, ++ funcIndex, ++ pPciDevice)) ++ { ++ /* no device detected , try the next address */ ++ continue; ++ } ++ ++ /* We are here ! means we have detected a device*/ ++ /* always we start with only one function per device */ ++ pMainDevice = pPciDevice; ++ pPciDevice->funtionsNum = 1; ++ ++ ++ /* move on */ ++ detectedDevNum++; ++ ++ ++ /* check if we have no more room for a new device */ ++ if (detectedDevNum == *pPciAgentsNum) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n")); ++ return MV_ERROR; ++ } ++ ++ /* check the detected device if it is a multi functional device then ++ scan all device functions*/ ++ if (pPciDevice->isMultiFunction == MV_TRUE) ++ { ++ /* start with function number 1 because we have already detected ++ function 0 */ ++ for (funcIndex=1; funcIndexfuntionsNum++; ++ detectedDevNum++; ++ ++ /* check if we have no more room for a new device */ ++ if (detectedDevNum == *pPciAgentsNum) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. Array too small\n")); ++ return MV_ERROR; ++ } ++ ++ ++ } ++ } ++ ++ } ++ ++ } ++ ++ /* return the number of devices actually detected on the bus ! */ ++ *pPciAgentsNum = detectedDevNum; ++ ++ return MV_OK; ++ ++} ++ ++ ++/******************************************************************************* ++* pciDetectDevice - Detect a pci device parameters ++* ++* DESCRIPTION: ++* This function detect if a pci agent exist on certain address ! ++* and if exists then it fills all possible information on the ++* agent ++* ++* INPUT: ++* pciIf - PCI Interface ++* bus - Bus number ++* dev - Device number ++* func - Function number ++* ++* ++* ++* OUTPUT: ++* pPciAgent - pointer to the pci agent filled with its information ++* ++* RETURN: ++* MV_ERROR if no device , MV_OK otherwise ++* ++*******************************************************************************/ ++ ++static MV_STATUS pciDetectDevice(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent) ++{ ++ MV_U32 pciData; ++ ++ /* no Parameters checking ! because it is static function and it is assumed ++ that all parameters were checked in the calling function */ ++ ++ ++ /* Try read the PCI Vendor ID and Device ID */ ++ ++ /* We will scan only ourselves and the PCI slots that exist on the ++ board, because we may have a case that we have one slot that has ++ a Cardbus connector, and because CardBus answers all IDsels we want ++ to scan only this slot and ourseleves. ++ ++ */ ++ #if defined(MV_INCLUDE_PCI) ++ if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) && ++ (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && ++ (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) && ++ (DB_88F5181_DDR1_MNG != mvBoardIdGet())) ++ { ++ ++ if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE) ++ { ++ return MV_ERROR; ++ } ++ } ++ #endif /* defined(MV_INCLUDE_PCI) */ ++ ++ pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID); ++ ++ if (PCI_ERROR_CODE == pciData) ++ { ++ /* no device exist */ ++ return MV_ERROR; ++ } ++ ++ /* we are here ! means a device is detected */ ++ ++ /* fill basic information */ ++ pPciAgent->busNumber=bus; ++ pPciAgent->deviceNum=dev; ++ pPciAgent->function=func; ++ ++ /* Fill the PCI Vendor ID and Device ID */ ++ ++ pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS; ++ pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS; ++ ++ /* Read Status and command */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_STATUS_AND_COMMAND); ++ ++ ++ /* Fill related Status and Command information*/ ++ ++ if (pciData & PSCR_TAR_FAST_BB) ++ { ++ pPciAgent->isFastB2BCapable = MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isFastB2BCapable = MV_FALSE; ++ } ++ ++ if (pciData & PSCR_CAP_LIST) ++ { ++ pPciAgent->isCapListSupport=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isCapListSupport=MV_FALSE; ++ } ++ ++ if (pciData & PSCR_66MHZ_EN) ++ { ++ pPciAgent->is66MHZCapable=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->is66MHZCapable=MV_FALSE; ++ } ++ ++ /* Read Class Code and Revision */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_CLASS_CODE_AND_REVISION_ID); ++ ++ ++ pPciAgent->baseClassCode = ++ (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; ++ ++ pPciAgent->subClassCode = ++ (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; ++ ++ pPciAgent->progIf = ++ (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS; ++ ++ pPciAgent->revisionID = ++ (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; ++ ++ /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE); ++ ++ ++ ++ pPciAgent->pciCacheLine= ++ (pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS; ++ pPciAgent->pciLatencyTimer= ++ (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS; ++ ++ switch (pciData & PBHTLTCLR_HEADER_MASK) ++ { ++ case PBHTLTCLR_HEADER_STANDARD: ++ ++ pPciAgent->pciHeader=MV_PCI_STANDARD; ++ break; ++ case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE: ++ ++ pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE; ++ break; ++ ++ } ++ ++ if (pciData & PBHTLTCLR_MULTI_FUNC) ++ { ++ pPciAgent->isMultiFunction=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isMultiFunction=MV_FALSE; ++ } ++ ++ if (pciData & PBHTLTCLR_BISTCAP) ++ { ++ pPciAgent->isBISTCapable=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isBISTCapable=MV_FALSE; ++ } ++ ++ ++ /* read this device pci bars */ ++ ++ pciDetectDeviceBars(pciIf, ++ bus,dev,func, ++ pPciAgent); ++ ++ ++ /* check if we are bridge*/ ++ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& ++ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) ++ { ++ ++ /* Read P2P_BUSSES_NUM */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_BUSSES_NUM); ++ ++ pPciAgent->p2pPrimBusNum = ++ (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS; ++ ++ pPciAgent->p2pSecBusNum = ++ (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS; ++ ++ pPciAgent->p2pSubBusNum = ++ (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS; ++ ++ pPciAgent->p2pSecLatencyTimer = ++ (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS; ++ ++ /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_IO_BASE_LIMIT_SEC_STATUS); ++ ++ pPciAgent->p2pSecStatus = ++ (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS; ++ ++ ++ pPciAgent->p2pIObase = ++ (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS; ++ ++ /* clear low address (should be zero)*/ ++ pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK; ++ ++ pPciAgent->p2pIOLimit = ++ (pciData & PIBLSS_IO_LIMIT_MASK); ++ ++ /* fill low address with 0xfff */ ++ pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK; ++ ++ ++ switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS) ++ { ++ case PIBLSS_ADD_CAP_16BIT: ++ ++ pPciAgent->bIO32 = MV_FALSE; ++ ++ break; ++ case PIBLSS_ADD_CAP_32BIT: ++ ++ pPciAgent->bIO32 = MV_TRUE; ++ ++ /* Read P2P_IO_BASE_LIMIT_UPPER_16 */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_IO_BASE_LIMIT_UPPER_16); ++ ++ pPciAgent->p2pIObase |= ++ (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS; ++ ++ ++ pPciAgent->p2pIOLimit |= ++ (pciData & PRBU_IO_UPP_LIMIT_MASK); ++ ++ break; ++ ++ } ++ ++ ++ /* Read P2P_MEM_BASE_LIMIT */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_MEM_BASE_LIMIT); ++ ++ pPciAgent->p2pMemBase = ++ (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS; ++ ++ /* clear low address */ ++ pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK; ++ ++ pPciAgent->p2pMemLimit = ++ (pciData & PMBL_MEM_LIMIT_MASK); ++ ++ /* add 0xfffff */ ++ pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK; ++ ++ ++ /* Read P2P_PREF_MEM_BASE_LIMIT */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_PREF_MEM_BASE_LIMIT); ++ ++ ++ pPciAgent->p2pPrefMemBase = ++ (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS; ++ ++ /* get high address only */ ++ pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK; ++ ++ ++ ++ pPciAgent->p2pPrefMemLimit = ++ (pciData & PRMBL_PREF_MEM_LIMIT_MASK); ++ ++ /* add 0xfffff */ ++ pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK; ++ ++ switch (pciData & PRMBL_ADD_CAP_MASK) ++ { ++ case PRMBL_ADD_CAP_32BIT: ++ ++ pPciAgent->bPrefMem64 = MV_FALSE; ++ ++ /* Read P2P_PREF_BASE_UPPER_32 */ ++ pPciAgent->p2pPrefBaseUpper32Bits = 0; ++ ++ /* Read P2P_PREF_LIMIT_UPPER_32 */ ++ pPciAgent->p2pPrefLimitUpper32Bits = 0; ++ ++ break; ++ case PRMBL_ADD_CAP_64BIT: ++ ++ pPciAgent->bPrefMem64 = MV_TRUE; ++ ++ /* Read P2P_PREF_BASE_UPPER_32 */ ++ pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_PREF_BASE_UPPER_32); ++ ++ /* Read P2P_PREF_LIMIT_UPPER_32 */ ++ pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_PREF_LIMIT_UPPER_32); ++ ++ break; ++ ++ } ++ ++ } ++ else /* no bridge */ ++ { ++ /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID); ++ ++ ++ pPciAgent->subSysVenID = ++ (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS; ++ pPciAgent->subSysID = ++ (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS; ++ ++ ++ /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_EXPANSION_ROM_BASE_ADDR_REG); ++ ++ ++ if (pciData & PERBAR_EXPROMEN) ++ { ++ pPciAgent->isExpRom = MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isExpRom = MV_FALSE; ++ } ++ ++ pPciAgent->expRomAddr = ++ (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS; ++ ++ } ++ ++ ++ if (MV_TRUE == pPciAgent->isCapListSupport) ++ { ++ /* Read PCI_CAPABILTY_LIST_POINTER */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_CAPABILTY_LIST_POINTER); ++ ++ pPciAgent->capListPointer = ++ (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS; ++ ++ } ++ ++ /* Read PCI_INTERRUPT_PIN_AND_LINE */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_INTERRUPT_PIN_AND_LINE); ++ ++ ++ pPciAgent->irqLine= ++ (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS; ++ ++ pPciAgent->intPin= ++ (MV_PCI_INT_PIN)(pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS; ++ ++ pPciAgent->minGrant= ++ (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS; ++ pPciAgent->maxLatency= ++ (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS; ++ ++ mvPciClassNameGet(pPciAgent->baseClassCode, ++ (MV_8 *)pPciAgent->type); ++ ++ return MV_OK; ++ ++ ++} ++ ++/******************************************************************************* ++* pciDetectDeviceBars - Detect a pci device bars ++* ++* DESCRIPTION: ++* This function detects all pci agent bars ++* ++* INPUT: ++* pciIf - PCI Interface ++* bus - Bus number ++* dev - Device number ++* func - Function number ++* ++* ++* ++* OUTPUT: ++* pPciAgent - pointer to the pci agent filled with its information ++* ++* RETURN: ++* detected bars number ++* ++*******************************************************************************/ ++static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent) ++{ ++ MV_U32 pciData,barIndex,detectedBar=0; ++ MV_U32 tmpBaseHigh=0,tmpBaseLow=0; ++ MV_U32 pciMaxBars=0; ++ ++ pPciAgent->barsNum=0; ++ ++ /* check if we are bridge*/ ++ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& ++ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) ++ { ++ pciMaxBars = 2; ++ } ++ else /* no bridge */ ++ { ++ pciMaxBars = 6; ++ } ++ ++ /* read this device pci bars */ ++ for (barIndex = 0 ; barIndex < pciMaxBars ; barIndex++ ) ++ { ++ /* Read PCI_MEMORY_BAR_BASE_ADDR */ ++ tmpBaseLow = pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ pPciAgent->pciBar[detectedBar].barOffset = ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex); ++ ++ /* check if the bar is 32bit or 64bit bar */ ++ switch (pciData & PBBLR_TYPE_MASK) ++ { ++ case PBBLR_TYPE_32BIT_ADDR: ++ pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR; ++ break; ++ case PBBLR_TYPE_64BIT_ADDR: ++ pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR; ++ break; ++ ++ } ++ ++ /* check if it is memory or IO bar */ ++ if (pciData & PBBLR_IOSPACE) ++ { ++ pPciAgent->pciBar[detectedBar].barMapping=PCI_IO_BAR; ++ } ++ else ++ { ++ pPciAgent->pciBar[detectedBar].barMapping=PCI_MEMORY_BAR; ++ } ++ ++ /* if it is memory bar then check if it is prefetchable */ ++ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) ++ { ++ if (pciData & PBBLR_PREFETCH_EN) ++ { ++ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE; ++ } ++ ++ pPciAgent->pciBar[detectedBar].barBaseLow = ++ pciData & PBBLR_MEM_BASE_MASK; ++ ++ ++ } ++ else /* IO Bar */ ++ { ++ pPciAgent->pciBar[detectedBar].barBaseLow = ++ pciData & PBBLR_IO_BASE_MASK; ++ ++ } ++ ++ pPciAgent->pciBar[detectedBar].barBaseHigh=0; ++ ++ if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) ++ { ++ barIndex++; ++ ++ tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ ++ } ++ ++ /* calculating full base address (64bit) */ ++ pPciAgent->pciBar[detectedBar].barBaseAddr = ++ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseHigh; ++ ++ pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32; ++ ++ pPciAgent->pciBar[detectedBar].barBaseAddr |= ++ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseLow; ++ ++ ++ ++ /* get the sizes of the the bar */ ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh=0; ++ ++ if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) && ++ (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)) ++ ++ { ++ /* write oxffffffff to the bar to get the size */ ++ /* start with sizelow ( original value was saved in tmpBaseLow ) */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), ++ 0xffffffff); ++ ++ /* read size */ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1)); ++ ++ ++ ++ /* restore original value */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), ++ tmpBaseLow); ++ ++ ++ /* now do the same for BaseHigh */ ++ ++ /* write oxffffffff to the bar to get the size */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ 0xffffffff); ++ ++ /* read size */ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ /* restore original value */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ tmpBaseHigh); ++ ++ if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow)&& ++ (0 == pPciAgent->pciBar[detectedBar].barSizeHigh)) ++ { ++ /* this bar is not applicable for this device, ++ ignore all previous settings and check the next bar*/ ++ ++ /* we though this was a 64bit bar , and it seems this ++ was wrong ! so decrement barIndex */ ++ barIndex--; ++ continue; ++ } ++ ++ /* calculate the full 64 bit size */ ++ ++ if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh) ++ { ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; ++ ++ } ++ else ++ { ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; ++ ++ } ++ ++ ++ ++ } ++ else /* 32bit bar */ ++ { ++ /* write oxffffffff to the bar to get the size */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ 0xffffffff); ++ ++ /* read size */ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ if (0 == pPciAgent->pciBar[detectedBar].barSizeLow) ++ { ++ /* this bar is not applicable for this device, ++ ignore all previous settings and check the next bar*/ ++ continue; ++ } ++ ++ ++ /* restore original value */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ tmpBaseLow); ++ ++ /* calculate size low */ ++ ++ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) ++ { ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; ++ } ++ else ++ { ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK; ++ } ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; ++ pPciAgent->pciBar[detectedBar].barSize = ++ (MV_U64)pPciAgent->pciBar[detectedBar].barSizeLow; ++ ++ ++ } ++ ++ /* we are here ! this means we have already detected a bar for ++ this device , now move on */ ++ ++ detectedBar++; ++ pPciAgent->barsNum++; ++ } ++ ++ return detectedBar; ++} ++ ++ ++/******************************************************************************* ++* mvPciClassNameGet - get PCI class name ++* ++* DESCRIPTION: ++* This function returns the PCI class name ++* ++* INPUT: ++* baseClassCode - Base Class Code. ++* ++* OUTPUT: ++* pType - the class name ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType) ++{ ++ ++ switch(baseClassCode) ++ { ++ case 0x0: ++ strcpy(pType,"Old generation device"); ++ break; ++ case 0x1: ++ strcpy(pType,"Mass storage controller"); ++ break; ++ case 0x2: ++ strcpy(pType,"Network controller"); ++ break; ++ case 0x3: ++ strcpy(pType,"Display controller"); ++ break; ++ case 0x4: ++ strcpy(pType,"Multimedia device"); ++ break; ++ case 0x5: ++ strcpy(pType,"Memory controller"); ++ break; ++ case 0x6: ++ strcpy(pType,"Bridge Device"); ++ break; ++ case 0x7: ++ strcpy(pType,"Simple Communication controllers"); ++ break; ++ case 0x8: ++ strcpy(pType,"Base system peripherals"); ++ break; ++ case 0x9: ++ strcpy(pType,"Input Devices"); ++ break; ++ case 0xa: ++ strcpy(pType,"Docking stations"); ++ break; ++ case 0xb: ++ strcpy(pType,"Processors"); ++ break; ++ case 0xc: ++ strcpy(pType,"Serial bus controllers"); ++ break; ++ case 0xd: ++ strcpy(pType,"Wireless controllers"); ++ break; ++ case 0xe: ++ strcpy(pType,"Intelligent I/O controllers"); ++ break; ++ case 0xf: ++ strcpy(pType,"Satellite communication controllers"); ++ break; ++ case 0x10: ++ strcpy(pType,"Encryption/Decryption controllers"); ++ break; ++ case 0x11: ++ strcpy(pType,"Data acquisition and signal processing controllers"); ++ break; ++ default: ++ strcpy(pType,"Unknown device"); ++ break; ++ } ++ ++ return MV_OK; ++ ++} ++ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,323 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvPciUtilsh ++#define __INCmvPciUtilsh ++ ++/* ++This module only support scanning of Header type 00h of pci devices ++There is no suppotr for Header type 01h of pci devices ( PCI bridges ) ++*/ ++ ++/* includes */ ++#include "mvSysHwConfig.h" ++#include "pci-if/mvPciIf.h" ++#include "pci/mvPciRegs.h" ++ ++ ++ ++/* PCI base address low bar mask */ ++#define PCI_ERROR_CODE 0xffffffff ++ ++#define PCI_BRIDGE_CLASS 0x6 ++#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 ++ ++ ++#define P2P_BUSSES_NUM 0x18 ++#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C ++#define P2P_MEM_BASE_LIMIT 0x20 ++#define P2P_PREF_MEM_BASE_LIMIT 0x24 ++#define P2P_PREF_BASE_UPPER_32 0x28 ++#define P2P_PREF_LIMIT_UPPER_32 0x2C ++#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 ++#define P2P_EXP_ROM 0x38 ++ ++/* P2P_BUSSES_NUM (PBM) */ ++ ++#define PBM_PRIME_BUS_NUM_OFFS 0 ++#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) ++ ++#define PBM_SEC_BUS_NUM_OFFS 8 ++#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) ++ ++#define PBM_SUB_BUS_NUM_OFFS 16 ++#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) ++ ++#define PBM_SEC_LAT_TMR_OFFS 24 ++#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) ++ ++/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ ++ ++#define PIBLSS_IO_BASE_OFFS 0 ++#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) ++ ++#define PIBLSS_ADD_CAP_OFFS 0 ++#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) ++#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) ++#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) ++ ++#define PIBLSS_LOW_ADDR_OFFS 0 ++#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) ++ ++#define PIBLSS_HIGH_ADDR_OFFS 12 ++#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) ++ ++#define PIBLSS_IO_LIMIT_OFFS 8 ++#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) ++ ++#define PIBLSS_SEC_STATUS_OFFS 16 ++#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) ++ ++ ++/* P2P_MEM_BASE_LIMIT (PMBL)*/ ++ ++#define PMBL_MEM_BASE_OFFS 0 ++#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) ++ ++#define PMBL_MEM_LIMIT_OFFS 16 ++#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) ++ ++ ++#define PMBL_LOW_ADDR_OFFS 0 ++#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) ++ ++#define PMBL_HIGH_ADDR_OFFS 20 ++#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) ++ ++ ++/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ ++ ++#define PRMBL_PREF_MEM_BASE_OFFS 0 ++#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) ++ ++#define PRMBL_PREF_MEM_LIMIT_OFFS 16 ++#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf); ++ return MV_ERROR; ++ } ++ } ++ ++ pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); ++ ++ switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) ++ { ++ case PXCR_DEV_TYPE_CTRL_CMPLX: ++ pexMode->pexType = MV_PEX_ROOT_COMPLEX; ++ break; ++ case PXCR_DEV_TYPE_CTRL_POINT: ++ pexMode->pexType = MV_PEX_END_POINT; ++ break; ++ ++ } ++ ++ /* Check if we have link */ ++ if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) ++ { ++ pexMode->pexLinkUp = MV_FALSE; ++ ++ /* If there is no link, the auto negotiation data is worthless */ ++ pexMode->pexWidth = MV_PEX_WITDH_INVALID; ++ } ++ else ++ { ++ pexMode->pexLinkUp = MV_TRUE; ++ ++ /* We have link. The link width is now valid */ ++ pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); ++ pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> ++ PXLCSR_NEG_LNK_WDTH_OFFS); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/* PEX configuration space read write */ ++ ++/******************************************************************************* ++* mvPexConfigRead - Read from configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit read from PEX configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to read from local bus segment, use ++* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bus - PEX segment bus number. ++* dev - PEX device number. ++* func - Function number. ++* regOffs - Register offset. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit register data, 0xffffffff on error ++* ++*******************************************************************************/ ++MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) ++ return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff); ++} ++ ++MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++#endif ++ MV_U32 pexData = 0; ++ MV_U32 localDev,localBus; ++ ++ /* Parameter checking */ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ if (dev >= MAX_PEX_DEVICES) ++ { ++ DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (func >= MAX_PEX_FUNCS) ++ { ++ DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (bus >= MAX_PEX_BUSSES) ++ { ++ DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); ++ return MV_ERROR; ++ } ++ ++ DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", ++ pexIf, bus, dev, func, regOff)); ++ ++ localDev = mvPexLocalDevNumGet(pexIf); ++ localBus = mvPexLocalBusNumGet(pexIf); ++ ++ /* Speed up the process. In case on no link, return MV_ERROR */ ++ if ((dev != localDev) || (bus != localBus)) ++ { ++ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ if ((pexData & PXSR_DL_DOWN)) ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ /* in PCI Express we have only one device number */ ++ /* and this number is the first number we encounter ++ else that the localDev*/ ++ /* spec pex define return on config read/write on any device */ ++ if (bus == localBus) ++ { ++ if (localDev == 0) ++ { ++ /* if local dev is 0 then the first number we encounter ++ after 0 is 1 */ ++ if ((dev != 1)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ /* if local dev is not 0 then the first number we encounter ++ is 0 */ ++ ++ if ((dev != 0)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ } ++ if(func != 0 ) /* i.e bridge */ ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ ++ /* Creating PEX address to be passed */ ++ pexData = (bus << PXCAR_BUS_NUM_OFFS); ++ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); ++ pexData |= (func << PXCAR_FUNC_NUM_OFFS); ++ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ ++ /* extended register space */ ++ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> ++ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); ++ ++ pexData |= PXCAR_CONFIG_EN; ++ ++ /* Write the address to the PEX configuration address register */ ++ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); ++ ++ DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData)); ++ ++ ++ /* In order to let the PEX controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) ++ { ++ return MV_ERROR; ++ } ++ ++ /* cleaning Master Abort */ ++ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), ++ PXSAC_MABORT); ++#if 0 ++ /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ ++ /* This guideline is relevant for all devices except of the following devices: ++ 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above ++ 88F6183 A0 and above, 88F6183L */ ++ if ( ( (dev != localDev) || (bus != localBus) ) && ++ ( ++ !(MV_5281_DEV_ID == mvCtrlModelGet())&& ++ !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&& ++ !(MV_1281_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6183_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6183L_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6281_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6192_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6190_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6180_DEV_ID == mvCtrlModelGet())&& ++ !(MV_78XX0_DEV_ID == mvCtrlModelGet()) ++ )) ++ { ++ ++ /* PCI-Express configuration read work-around */ ++ ++ /* we will use one of the Punit (AHBToMbus) windows to access the xbar ++ and read the data from there */ ++ /* ++ Need to configure the 2 free Punit (AHB to MBus bridge) ++ address decoding windows: ++ Configure the flash Window to handle Configuration space requests ++ for PEX0/1: ++ 1. write 0x7931/0x7941 to the flash window and the size, ++ 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn ++ 2. write base to flash window ++ ++ Configuration transactions from the CPU should write/read the data ++ to/from address of the form: ++ addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) ++ addr[27:24] = extended register number ++ addr[23:16] = bus number ++ addr[15:11] = device number ++ addr[10:8] = function number ++ addr[7:0] = register number ++ */ ++ ++ #include "ctrlEnv/sys/mvAhbToMbus.h" ++ { ++ MV_U32 winNum; ++ MV_AHB_TO_MBUS_DEC_WIN originWin; ++ MV_U32 pciAddr=0; ++ MV_U32 remapLow=0,remapHigh=0; ++ ++ /* ++ We will use DEV_CS2\Flash window for this workarround ++ */ ++ ++ winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); ++ ++ /* save remap values if exist */ ++ if ((1 == winNum)||(0 == winNum)) ++ { ++ remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); ++ remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); ++ ++ } ++ ++ ++ /* save the original window values */ ++ mvAhbToMbusWinGet(winNum,&originWin); ++ ++ if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) ++ { ++ /* set the window as xbar window */ ++ if (pexIf) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16)); ++ } ++ else ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16)); ++ } ++ ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), ++ originWin.addrWin.baseLow); ++ ++ /*pciAddr = originWin.addrWin.baseLow;*/ ++ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR( ++ (MV_U32)originWin.addrWin.baseLow); ++ ++ } ++ else ++ { ++ /* set the window as xbar window */ ++ if (pexIf) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); ++ } ++ else ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); ++ } ++ ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), ++ PEX_CONFIG_RW_WA_BASE); ++ ++ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); ++ } ++ ++ ++ /* remap should be as base */ ++ if ((1 == winNum)||(0 == winNum)) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr); ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0); ++ ++ } ++ ++ /* extended register space */ ++ pciAddr |= (bus << 16); ++ pciAddr |= (dev << 11); ++ pciAddr |= (func << 8); ++ pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ ++ ++ pexData = *(MV_U32*)pciAddr; ++ pexData = MV_32BIT_LE(pexData); /* Data always in LE */ ++ ++ /* restore the original window values */ ++ mvAhbToMbusWinSet(winNum,&originWin); ++ ++ /* restore original remap values*/ ++ if ((1 == winNum)||(0 == winNum)) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow); ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh); ++ ++ } ++ } ++ } ++ else ++#endif ++ { ++ /* Read the Data returned in the PEX Data register */ ++ pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); ++ ++ } ++ ++ DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData)); ++ ++ return pexData; ++ ++} ++ ++/******************************************************************************* ++* mvPexConfigWrite - Write to configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit write to PEX configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to write to local bus segment, use ++* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bus - PEX segment bus number. ++* dev - PEX device number. ++* func - Function number. ++* regOffs - Register offset. ++* data - 32bit data. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) ++ return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data); ++} ++ ++MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++#endif ++ MV_U32 pexData = 0; ++ MV_U32 localDev,localBus; ++ ++ /* Parameter checking */ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", ++ pexIf); ++ return MV_ERROR; ++ } ++ } ++ ++ if (dev >= MAX_PEX_DEVICES) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev); ++ return MV_BAD_PARAM; ++ } ++ ++ if (func >= MAX_PEX_FUNCS) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); ++ return MV_ERROR; ++ } ++ ++ if (bus >= MAX_PEX_BUSSES) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); ++ return MV_ERROR; ++ } ++ ++ ++ ++ localDev = mvPexLocalDevNumGet(pexIf); ++ localBus = mvPexLocalBusNumGet(pexIf); ++ ++ ++ /* in PCI Express we have only one device number other than ourselves*/ ++ /* and this number is the first number we encounter ++ else than the localDev that can be any valid dev number*/ ++ /* pex spec define return on config read/write on any device */ ++ if (bus == localBus) ++ { ++ ++ if (localDev == 0) ++ { ++ /* if local dev is 0 then the first number we encounter ++ after 0 is 1 */ ++ if ((dev != 1)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ /* if local dev is not 0 then the first number we encounter ++ is 0 */ ++ ++ if ((dev != 0)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ ++ } ++ ++ /* if we are not accessing ourselves , then check the link */ ++ if ((dev != localDev) || (bus != localBus) ) ++ { ++ /* workarround */ ++ /* when no link return MV_ERROR */ ++ ++ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ if ((pexData & PXSR_DL_DOWN)) ++ { ++ return MV_ERROR; ++ } ++ ++ } ++ ++ pexData =0; ++ ++ /* Creating PEX address to be passed */ ++ pexData |= (bus << PXCAR_BUS_NUM_OFFS); ++ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); ++ pexData |= (func << PXCAR_FUNC_NUM_OFFS); ++ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ ++ /* extended register space */ ++ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> ++ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); ++ pexData |= PXCAR_CONFIG_EN; ++ ++ DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", ++ pexIf,bus,func,dev,regOff,data,pexData) ); ++ ++ /* Write the address to the PEX configuration address register */ ++ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); ++ ++ /* Clear CPU pipe. Important where CPU can perform OOO execution */ ++ CPU_PIPE_FLUSH; ++ ++ /* In order to let the PEX controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) ++ { ++ return MV_ERROR; ++ } ++ ++ /* Write the Data passed to the PEX Data register */ ++ MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexMasterEnable - Enable/disale PEX interface master transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PEX command status ++* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX ++* master is allowed to gain ownership on the bus, otherwise it is ++* incapable to do so. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) ++{ ++ MV_U32 pexCommandStatus; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_ERROR; ++ } ++ ++ localBus = mvPexLocalBusNumGet(pexIf); ++ localDev = mvPexLocalDevNumGet(pexIf); ++ ++ pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, ++ PEX_STATUS_AND_COMMAND)); ++ ++ ++ if (MV_TRUE == enable) ++ { ++ pexCommandStatus |= PXSAC_MASTER_EN; ++ } ++ else ++ { ++ pexCommandStatus &= ~PXSAC_MASTER_EN; ++ } ++ ++ ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), ++ pexCommandStatus); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PEX command status ++* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, ++* the PEX slave is allowed to respond to PEX IO space access (bit 0) ++* and PEX memory space access (bit 1). ++* ++* INPUT: ++* pexIf - PEX interface number. ++* dev - PEX device number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable) ++{ ++ MV_U32 pexCommandStatus; ++ MV_U32 RegOffs; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (dev >= MAX_PEX_DEVICES) ++ { ++ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ ++ RegOffs = PEX_STATUS_AND_COMMAND; ++ ++ pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); ++ ++ if (MV_TRUE == enable) ++ { ++ pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); ++ } ++ else ++ { ++ pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); ++ } ++ ++ mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexLocalBusNumSet - Set PEX interface local bus number. ++* ++* DESCRIPTION: ++* This function sets given PEX interface its local bus number. ++* Note: In case the PEX interface is PEX-X, the information is read-only. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* busNum - Bus number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PEX interface is PEX-X. ++* MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) ++{ ++ MV_U32 pexStatus; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (busNum >= MAX_PEX_BUSSES) ++ { ++ mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); ++ return MV_ERROR; ++ ++ } ++ ++ localBus = mvPexLocalBusNumGet(pexIf); ++ localDev = mvPexLocalDevNumGet(pexIf); ++ ++ ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; ++ ++ pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; ++ ++ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexLocalBusNumGet - Get PEX interface local bus number. ++* ++* DESCRIPTION: ++* This function gets the local bus number of a given PEX interface. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local bus number.0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) ++{ ++ MV_U32 pexStatus; ++ ++ /* Parameter checking */ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= PXSR_PEX_BUS_NUM_MASK; ++ ++ return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); ++ ++} ++ ++ ++/******************************************************************************* ++* mvPexLocalDevNumSet - Set PEX interface local device number. ++* ++* DESCRIPTION: ++* This function sets given PEX interface its local device number. ++* Note: In case the PEX interface is PEX-X, the information is read-only. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* devNum - Device number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PEX interface is PEX-X. ++* MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) ++{ ++ MV_U32 pexStatus; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (devNum >= MAX_PEX_DEVICES) ++ { ++ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", ++ devNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ localBus = mvPexLocalBusNumGet(pexIf); ++ localDev = mvPexLocalDevNumGet(pexIf); ++ ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; ++ ++ pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; ++ ++ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); ++ ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPexLocalDevNumGet - Get PEX interface local device number. ++* ++* DESCRIPTION: ++* This function gets the local device number of a given PEX interface. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local device number. 0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) ++{ ++ MV_U32 pexStatus; ++ ++ /* Parameter checking */ ++ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", ++ pexIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= PXSR_PEX_DEV_NUM_MASK; ++ ++ return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); ++} ++ ++MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) ++{ ++ ++ MV_U32 regAddr; ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); ++ return; ++ } ++ regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); ++ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); ++ *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); ++} ++ ++ ++MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) ++{ ++ ++ MV_U32 regAddr; ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); ++ return; ++ } ++ regAddr = (((regOffset & 0x3fff) << 16) | value); ++ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); ++} ++ ++/******************************************************************************* ++* mvPexActiveStateLinkPMEnable ++* ++* DESCRIPTION: ++* Enable Active Link State Power Management ++* ++* INPUT: ++* pexIf - PEX interface number. ++* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_OK on success , MV_ERROR otherwise ++* ++*******************************************************************************/ ++MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) ++{ ++ MV_U32 reg; ++ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_ERROR; ++ } ++ ++ reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; ++ if(enable == MV_TRUE) ++ reg |= PXPMER_L1_ASPM_EN_MASK; ++ MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); ++ ++ /* Enable / Disable L0/1 entry */ ++ reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) ++ & ~PXLCSR_ASPM_CNT_MASK; ++ if(enable == MV_TRUE) ++ reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexForceX1 ++* ++* DESCRIPTION: ++* shut down lanes 1-3 if recognize that attached to an x1 end-point ++* INPUT: ++* pexIf - PEX interface number. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_OK on success , MV_ERROR otherwise ++* ++*******************************************************************************/ ++MV_U32 mvPexForceX1(MV_U32 pexIf) ++{ ++ MV_U32 regData = 0; ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ; ++ regData |= PXCR_CONF_LINK_X1; ++ ++ MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); ++ return MV_OK; ++} ++ ++MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) ++{ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_FALSE; ++ } ++ return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); ++} ++ ++ ++MV_VOID mvPexPowerDown(MV_U32 pexIf) ++{ ++ if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) || ++ (mvCtrlModelGet() == MV_76100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78200_DEV_ID) ) ++ { ++ mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); ++ } ++ else ++ { ++ MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087); ++ } ++} ++ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,168 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPEXH ++#define __INCPEXH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "pex/mvPexRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++ ++ ++/* NOTE not supported in this driver:*/ ++ ++ ++/* defines */ ++/* The number of supported PEX interfaces depend on Marvell controller */ ++/* device number. This device number ID is located on the PEX unit */ ++/* configuration header. This creates a loop where calling PEX */ ++/* configuration read/write routine results a call to get PEX configuration */ ++/* information etc. This macro defines a default PEX interface. This PEX */ ++/* interface is sure to exist. */ ++#define PEX_DEFAULT_IF 0 ++ ++ ++/* typedefs */ ++/* The Marvell controller supports both root complex and end point devices */ ++/* This enumeration describes the PEX type. */ ++typedef enum _mvPexType ++{ ++ MV_PEX_ROOT_COMPLEX, /* root complex device */ ++ MV_PEX_END_POINT /* end point device */ ++}MV_PEX_TYPE; ++ ++typedef enum _mvPexWidth ++{ ++ MV_PEX_WITDH_X1 = 1, ++ MV_PEX_WITDH_X2, ++ MV_PEX_WITDH_X3, ++ MV_PEX_WITDH_X4, ++ MV_PEX_WITDH_INVALID ++}MV_PEX_WIDTH; ++ ++/* PEX Bar attributes */ ++typedef struct _mvPexMode ++{ ++ MV_PEX_TYPE pexType; ++ MV_PEX_WIDTH pexWidth; ++ MV_BOOL pexLinkUp; ++}MV_PEX_MODE; ++ ++ ++ ++/* Global Functions prototypes */ ++/* mvPexInit - Initialize PEX interfaces*/ ++MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType); ++ ++/* mvPexModeGet - Get Pex If mode */ ++MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode); ++ ++/* mvPexConfigRead - Read from configuration space */ ++MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPexConfigWrite - Write to configuration space */ ++MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/ ++MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); ++ ++/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/ ++MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable); ++ ++/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/ ++MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); ++ ++/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/ ++MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); ++ ++/* mvPexLocalDevNumSet - Set PEX interface local device number.*/ ++MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); ++ ++/* mvPexLocalDevNumGet - Get PEX interface local device number.*/ ++MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); ++/* mvPexForceX1 - Force PEX interface to X1 mode. */ ++MV_U32 mvPexForceX1(MV_U32 pexIf); ++ ++/* mvPexIsPowerUp - Is PEX interface Power up? */ ++MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); ++ ++/* mvPexPowerDown - Power Down */ ++MV_VOID mvPexPowerDown(MV_U32 pexIf); ++ ++/* mvPexPowerUp - Power Up */ ++MV_VOID mvPexPowerUp(MV_U32 pexIf); ++ ++/* mvPexPhyRegRead - Pex phy read */ ++MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); ++ ++/* mvPexPhyRegWrite - Pex phy write */ ++MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); ++ ++MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); ++ ++#endif /* #ifndef __INCPEXH */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,751 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPEXREGSH ++#define __INCPEXREGSH ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* defines */ ++#define MAX_PEX_DEVICES 32 ++#define MAX_PEX_FUNCS 8 ++#define MAX_PEX_BUSSES 256 ++ ++ ++ ++/*********************************************************/ ++/* PCI Express Configuration Cycles Generation Registers */ ++/*********************************************************/ ++ ++#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8) ++#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC) ++#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00) ++/* PCI Express Configuration Address Register */ ++/* PEX_CFG_ADDR_REG (PXCAR)*/ ++ ++#define PXCAR_REG_NUM_OFFS 2 ++#define PXCAR_REG_NUM_MAX 0x3F ++#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) ++#define PXCAR_FUNC_NUM_OFFS 8 ++#define PXCAR_FUNC_NUM_MAX 0x7 ++#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) ++#define PXCAR_DEVICE_NUM_OFFS 11 ++#define PXCAR_DEVICE_NUM_MAX 0x1F ++#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) ++#define PXCAR_BUS_NUM_OFFS 16 ++#define PXCAR_BUS_NUM_MAX 0xFF ++#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) ++#define PXCAR_EXT_REG_NUM_OFFS 24 ++#define PXCAR_EXT_REG_NUM_MAX 0xF ++ ++/* in pci express register address is now the legacy register address (8 bits) ++with the new extended register address (more 4 bits) , below is the mask of ++the upper 4 bits of the full register address */ ++ ++#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 ++#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) ++#define PXCAR_CONFIG_EN BIT31 ++ ++#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 ++#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) ++ ++/* The traditional PCI spec defined 6-bit field to describe register offset.*/ ++/* The new PCI Express extend the register offset by an extra 4-bits. */ ++/* The below macro assign 10-bit register offset into the apprpreate */ ++/* fields in the CFG_ADDR_REG */ ++#define PXCAR_REG_OFFS_SET(regOffs) \ ++ ( (regOff & PXCAR_REG_NUM_MASK) | \ ++ ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) ) ++ ++/***********************************/ ++/* PCI Express Interrupt registers */ ++/***********************************/ ++#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900) ++#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910) ++ ++#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ ++ /* of the PCI Express */ ++/* PCI Express Interrupt Cause */ ++/* PEX_INT_CAUSE_REG (PXICR)*/ ++/* PEX_INT_MASK_REG*/ ++/* ++NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets ++upon an error event occurrence. A write of 0 clears the bit. A write of 1 has ++no affect. Bits[24:27} are set and cleared upon reception of interrupt ++emulation messages. ++ ++Mask bit per cause bit. If a bit is set to 1, the corresponding event is ++enabled. Mask does not affect setting of the Interrupt Cause register bits; ++it only affects the assertion of the interrupt .*/ ++ ++ ++#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction ++ while master is disabled */ ++#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to ++ PCI Express internal register*/ ++#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ ++#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ ++#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ ++#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/ ++#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/ ++#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/ ++#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/ ++#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/ ++#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ ++ ++#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ ++#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/ ++#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/ ++#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/ ++#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/ ++#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/ ++#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/ ++#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/ ++#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/ ++#define PXICR_RCV_INTA BIT24 /* IntA status.*/ ++#define PXICR_RCV_INTB BIT25 /* IntB status.*/ ++#define PXICR_RCV_INTC BIT26 /* IntC status.*/ ++#define PXICR_RCV_INTD BIT27 /* IntD status.*/ ++#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ ++ ++ ++/********************************************/ ++/* PCI Express Control and Status Registers */ ++/********************************************/ ++#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00) ++#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04) ++#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10) ++#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18) ++#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20) ++#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30) ++#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40) ++#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0) ++ ++ ++#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50) ++/* PCI Express Control Register */ ++/* PEX_CTRL_REG (PXCR) */ ++ ++#define PXCR_CONF_LINK_OFFS 0 ++#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) ++#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) ++#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) ++#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/ ++#define PXCR_DEV_TYPE_CTRL_MASK BIT1 ++#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) ++#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) ++#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping ++ to Memory Space Enable */ ++ ++#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping ++ to Memory Space Enable*/ ++ ++#define PXCR_RSRV1_OFFS 5 ++#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) ++#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) ++ ++#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/ ++#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) ++ ++ ++#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/ ++#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) ++ ++#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/ ++#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ ++#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/ ++#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/ ++ ++/* PCI Express Status Register */ ++/* PEX_STATUS_REG (PXSR) */ ++ ++#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/ ++ ++#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ ++#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) ++ ++#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ ++#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) ++ ++#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/ ++#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/ ++#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/ ++#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/ ++ ++ ++/* PCI Express Completion Timeout Register */ ++/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/ ++ ++#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ ++#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) ++ ++/* PCI Express Power Management Extended Register */ ++/* PEX_PWR_MNG_EXT_REG (PXPMER) */ ++ ++#define PXPMER_L1_ASPM_EN_OFFS 1 ++#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) ++ ++/* PCI Express Flow Control Register */ ++/* PEX_FLOW_CTRL_REG (PXFCR)*/ ++ ++#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit ++ Initial Value.*/ ++#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) ++ ++ ++#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers ++ Flow Control Credit Initial Value*/ ++#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) ++ ++#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control ++ Credit Initial Value Infinite*/ ++ ++#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) ++ ++#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ ++#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) ++ ++/* PCI Express Acknowledge Timers (4X) Register */ ++/* PEX_ACK_TMR_4X_REG (PXAT4R) */ ++#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ ++#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) ++#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ ++#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) ++ ++/* PCI Express Acknowledge Timers (1X) Register */ ++/* PEX_ACK_TMR_1X_REG (PXAT1R) */ ++ ++#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout ++ Value for 1X Link*/ ++#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) ++ ++#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout ++ Value for 1X*/ ++#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) ++ ++ ++/* PCI Express TL Control Register */ ++/* PEX_TL_CTRL_REG (PXTCR) */ ++ ++#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/ ++#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) ++ ++/* PCI Express Debug MAC Control Register */ ++/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ ++ ++#define PXDMCR_LINKUP BIT4 ++ ++ ++ ++/**********************************************/ ++/* PCI Express Configuration Header Registers */ ++/**********************************************/ ++#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg)) ++ ++#define PEX_DEVICE_AND_VENDOR_ID 0x000 ++#define PEX_STATUS_AND_COMMAND 0x004 ++#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 ++#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C ++#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) ++#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) ++#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) ++#define PEX_BAR0_INTER_REG 0x010 ++#define PEX_BAR0_INTER_REG_HIGH 0x014 ++#define PEX_BAR1_REG 0x018 ++#define PEX_BAR1_REG_HIGH 0x01C ++#define PEX_BAR2_REG 0x020 ++#define PEX_BAR2_REG_HIGH 0x024 ++ ++#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C ++#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 ++#define PEX_CAPABILTY_LIST_POINTER 0x034 ++#define PEX_INTERRUPT_PIN_AND_LINE 0x03C ++ ++/* capability list */ ++#define PEX_POWER_MNG_CAPABILITY 0x040 ++#define PEX_POWER_MNG_STATUS_CONTROL 0x044 ++ ++#define PEX_MSI_MESSAGE_CONTROL 0x050 ++#define PEX_MSI_MESSAGE_ADDR 0x054 ++#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 ++#define PEX_MSI_MESSAGE_DATA 0x05C ++ ++#define PEX_CAPABILITY_REG 0x60 ++#define PEX_DEV_CAPABILITY_REG 0x64 ++#define PEX_DEV_CTRL_STAT_REG 0x68 ++#define PEX_LINK_CAPABILITY_REG 0x6C ++#define PEX_LINK_CTRL_STAT_REG 0x70 ++ ++#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 ++#define PEX_UNCORRECT_ERR_STAT_REG 0x104 ++#define PEX_UNCORRECT_ERR_MASK_REG 0x108 ++#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C ++#define PEX_CORRECT_ERR_STAT_REG 0x110 ++#define PEX_CORRECT_ERR_MASK_REG 0x114 ++#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 ++#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C ++#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 ++#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 ++#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 ++ ++ ++ ++/* PCI Express Device and Vendor ID Register*/ ++/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/ ++ ++#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ ++#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) ++ ++#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ ++#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) ++ ++ ++/* PCI Express Command and Status Register*/ ++/*PEX_STATUS_AND_COMMAND (PXSAC)*/ ++ ++#define PXSAC_IO_EN BIT0 /* IO Enable */ ++#define PXSAC_MEM_EN BIT1 /* Memory Enable */ ++#define PXSAC_MASTER_EN BIT2 /* Master Enable */ ++#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ ++#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ ++#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ ++#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ ++#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ ++#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ ++#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ ++#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ ++#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ ++#define PXSAC_SYSERR BIT30 /* Signalled system error */ ++#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ ++ ++ ++/* PCI Express Class Code and Revision ID Register*/ ++/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/ ++ ++#define PXCCARI_REVID_OFFS 0 /* Revision ID */ ++#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) ++ ++#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ ++#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) ++ ++#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/ ++#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) ++ ++#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/ ++#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) ++ ++#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/ ++#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) ++ ++ ++/* PCI Express BIST, Header Type and Cache Line Size Register*/ ++/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/ ++ ++#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ ++#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) ++ ++#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ ++#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) ++ ++#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ ++ ++#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ ++#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) ++#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) ++#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) ++ ++ ++#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ ++#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) ++ ++#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ ++#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ ++#define PXBHTLTCL_BISTCAP_OFFS 31 ++#define PXBHTLTCL_BISTCAP_MASK BIT31 ++#define PXBHTLTCL_BISTCAP_VAL 0 ++ ++ ++/* PCI Express Subsystem Device and Vendor ID */ ++/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/ ++ ++#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ ++#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) ++ ++#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ ++#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) ++ ++ ++/* PCI Express Capability List Pointer Register*/ ++/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/ ++ ++#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ ++#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) ++ ++/* PCI Express Interrupt Pin and Line Register */ ++/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/ ++ ++#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ ++#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) ++ ++#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ ++#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) ++ ++ ++/* PCI Express Power Management Capability Header Register*/ ++/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/ ++ ++#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ ++#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) ++ ++#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ ++#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) ++ ++#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/ ++#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) ++ ++#define PXPMC_DSI BIT21/* Device Specific Initialization */ ++ ++#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ ++#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) ++ ++#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/ ++ ++#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/ ++ ++#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/ ++#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) ++ ++/* PCI Express Power Management Control and Status Register*/ ++/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/ ++ ++#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ ++#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) ++ ++#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */ ++ ++#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/ ++#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) ++ ++#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ ++#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) ++ ++#define PXPMSC_PME_STAT BIT15/* PME Status */ ++ ++#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ ++#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) ++ ++ ++/* PCI Express MSI Message Control Register*/ ++/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/ ++ ++#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ ++#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) ++ ++#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ ++#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) ++ ++#define PXMMC_MSI_EN BIT18 /* MSI Enable */ ++ ++#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ ++#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) ++ ++#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ ++#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) ++ ++#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ ++ ++ ++/* PCI Express MSI Message Address Register*/ ++/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/ ++ ++#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to ++ Address[31:2] of the MSI MWr TLP*/ ++#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) ++ ++ ++/* PCI Express MSI Message Address (High) Register */ ++/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/ ++ ++#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to ++ Address[63:32] of the MSI MWr TLP*/ ++#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS ) ++ ++ ++/* PCI Express MSI Message Data Register*/ ++/*PEX_MSI_MESSAGE_DATA (PXMMD)*/ ++ ++#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ ++#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS ) ++ ++ ++/* PCI Express Capability Register*/ ++/*PEX_CAPABILITY_REG (PXCR)*/ ++ ++#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/ ++#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) ++ ++#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/ ++#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) ++ ++#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/ ++#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) ++ ++#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/ ++#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) ++ ++#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/ ++ ++#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/ ++#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) ++ ++ ++/* PCI Express Device Capabilities Register */ ++/*PEX_DEV_CAPABILITY_REG (PXDCR)*/ ++ ++#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/ ++#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) ++ ++#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/ ++#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++ ++#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/ ++#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) ++ ++ ++#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/ ++#define PXDCR_ATT_BUT_PRS_MASK BIT12 ++#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 ++ ++#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/ ++#define PXDCR_ATT_IND_PRS_MASK BIT13 ++#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 ++ ++#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/ ++#define PXDCR_PWR_IND_PRS_MASK BIT14 ++#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 ++ ++#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit ++ Value*/ ++#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) ++ ++#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit ++ Scale */ ++#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) ++ ++/* PCI Express Device Control Status Register */ ++/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/ ++ ++#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/ ++#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/ ++#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/ ++#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) ++ Reporting Enable*/ ++#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/ ++ ++#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/ ++#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) ++#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) ++#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/ ++ ++#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/ ++#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++ ++#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/ ++#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/ ++#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/ ++#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ ++#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/ ++ ++#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/ ++#define PXDCSR_TRANS_PEND_MASK BIT21 ++#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) ++ ++ ++/* PCI Express Link Capabilities Register*/ ++/*PEX_LINK_CAPABILITY_REG (PXLCR)*/ ++ ++#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/ ++#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) ++ ++#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/ ++#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) ++ ++#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/ ++#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) ++ ++#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/ ++#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) ++ ++#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ ++#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) ++ ++/* PCI Express Link Control Status Register */ ++/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/ ++ ++#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ ++#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) ++ ++#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ ++#define PXLCSR_RCB_MASK BIT3 ++#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) ++#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) ++ ++#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ ++#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ ++#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ ++#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ ++ ++#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ ++#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) ++ ++#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ ++#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) ++#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) ++ ++#define PXLCSR_LNK_TRN BIT27 /* Link Training */ ++ ++#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ ++#define PXLCSR_SLT_CLK_CFG_MASK BIT28 ++#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) ++#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) ++ ++/* PCI Express Advanced Error Report Header Register */ ++/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/ ++ ++/* PCI Express Uncorrectable Error Status Register*/ ++/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/ ++ ++/* PCI Express Uncorrectable Error Mask Register */ ++/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/ ++ ++/* PCI Express Uncorrectable Error Severity Register */ ++/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/ ++ ++/* PCI Express Correctable Error Status Register */ ++/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/ ++ ++/* PCI Express Correctable Error Mask Register */ ++/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/ ++ ++/* PCI Express Advanced Error Capability and Control Register*/ ++/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/ ++ ++/* PCI Express Header Log First DWORD Register*/ ++/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/ ++ ++/* PCI Express Header Log Second DWORD Register*/ ++/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/ ++ ++/* PCI Express Header Log Third DWORD Register*/ ++/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/ ++ ++/* PCI Express Header Log Fourth DWORD Register*/ ++/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* #ifndef __INCPEXREGSH */ ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,313 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvPex.h" ++ ++//#define MV_DEBUG ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* locals */ ++typedef struct ++{ ++ MV_U32 data; ++ MV_U32 mask; ++}PEX_HEADER_DATA; ++ ++/* local function forwad decleration */ ++MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff); ++MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev); ++ ++ ++PEX_HEADER_DATA configHdr[16] = ++{ ++{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */ ++{0x00100007, 0x0000ffff}, /*[status register, command register] */ ++{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */ ++{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */ ++{0x00000000, 0x00000000}, /*[base address 0] */ ++{0x00000000, 0x00000000}, /*[base address 1] */ ++{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */ ++{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */ ++{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ ++{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ ++{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ ++{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */ ++{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ ++{0x00000000, 0x00000000}, /*[reserved, capability pointer] */ ++{0x00000000, 0x00000000}, /*[expansion ROM base address] */ ++{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ ++}; ++ ++ ++#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \ ++ (data & configHdr[offset/4].mask)) ++#define HEADER_READ(offset) configHdr[offset/4].data ++ ++/******************************************************************************* ++* mvVrtBrgPexInit - Initialize PEX interfaces ++* ++* DESCRIPTION: ++* ++* This function is responsible of intialization of the Pex Interface , It ++* configure the Pex Bars and Windows in the following manner: ++* ++* Assumptions : ++* Bar0 is always internal registers bar ++* Bar1 is always the DRAM bar ++* Bar2 is always the Device bar ++* ++* 1) Sets the Internal registers bar base by obtaining the base from ++* the CPU Interface ++* 2) Sets the DRAM bar base and size by getting the base and size from ++* the CPU Interface when the size is the sum of all enabled DRAM ++* chip selects and the base is the base of CS0 . ++* 3) Sets the Device bar base and size by getting these values from the ++* CPU Interface when the base is the base of the lowest base of the ++* Device chip selects, and the ++* ++* ++* INPUT: ++* ++* pexIf - PEX interface number. ++* ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM ++* ++*******************************************************************************/ ++MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf) ++{ ++ /* reset PEX tree to recover previous U-boot/Boot configurations */ ++ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); ++ ++ ++ resetPexConfig(pexIf, localBus, 1); ++ return MV_OK; ++} ++ ++ ++MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++ ++ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); ++ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); ++ MV_U32 val; ++ if(bus == localBus) ++ { ++ if(dev > 1) ++ { ++/* on the local device allow only device #0 & #1 */ ++ return 0xffffffff; ++ } ++ else ++ if (dev == localDev) ++ { ++ /* read the memory controller registers */ ++ return mvPexHwConfigRead (pexIf, bus, dev, func, regOff); ++ } ++ else ++ { ++ /* access the virtual brg header */ ++ return HEADER_READ(regOff); ++ } ++ } ++ else ++ if(bus == (localBus + 1)) ++ { ++ /* access the device behind the virtual bridge */ ++ if((dev == localDev) || (dev > 1)) ++ { ++ return 0xffffffff; ++ } ++ else ++ { ++ /* access the device behind the virtual bridge, in this case ++ * change the bus number to the local bus number in order to ++ * generate type 0 config cycle ++ */ ++ mvPexLocalBusNumSet(pexIf, bus); ++ mvPexLocalDevNumSet(pexIf, 1); ++ val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff); ++ mvPexLocalBusNumSet(pexIf, localBus); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return val; ++ } ++ } ++ /* for all other devices use the HW function to get the ++ * requested registers ++ */ ++ mvPexLocalDevNumSet(pexIf, 1); ++ val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return val; ++} ++ ++ ++MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); ++ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); ++ MV_STATUS status; ++ ++ if(bus == localBus) ++ { ++ if(dev > 1) ++ { ++ /* on the local device allow only device #0 & #1 */ ++ return MV_ERROR; ++ } ++ else ++ if (dev == localDev) ++ { ++ /* read the memory controller registers */ ++ return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); ++ } ++ else ++ { ++ /* access the virtual brg header */ ++ HEADER_WRITE(data, regOff); ++ return MV_OK; ++ } ++ } ++ else ++ if(bus == (localBus + 1)) ++ { ++ /* access the device behind the virtual bridge */ ++ if((dev == localDev) || (dev > 1)) ++ { ++ return MV_ERROR; ++ } ++ else ++ { ++ /* access the device behind the virtual bridge, in this case ++ * change the bus number to the local bus number in order to ++ * generate type 0 config cycle ++ */ ++ //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data); ++ mvPexLocalBusNumSet(pexIf, bus); ++ mvPexLocalDevNumSet(pexIf, 1); ++ status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data); ++ mvPexLocalBusNumSet(pexIf, localBus); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return status; ++ ++ } ++ } ++ /* for all other devices use the HW function to get the ++ * requested registers ++ */ ++ mvPexLocalDevNumSet(pexIf, 1); ++ status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return status; ++} ++ ++ ++ ++ ++void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev) ++{ ++ MV_U32 tData; ++ MV_U32 i; ++ ++ /* restore the PEX configuration to initialization state */ ++ /* in case PEX P2P call recursive and reset config */ ++ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0); ++ if(tData != 0xffffffff) ++ { ++ /* agent had been found - check whether P2P */ ++ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8); ++ if((tData & 0xffff0000) == 0x06040000) ++ {/* P2P */ ++ /* get the sec bus and the subordinate */ ++ MV_U32 secBus; ++ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18); ++ secBus = ((tData >> 8) & 0xff); ++ /* now scan on sec bus */ ++ for(i = 0;i < 0xff;i++) ++ { ++ resetPexConfig(pexIf, secBus, i); ++ } ++ /* now reset this device */ ++ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); ++ mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); ++ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); ++ } ++ } ++} ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,82 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCVRTBRGPEXH ++#define __INCVRTBRGPEXH ++ ++ ++/* Global Functions prototypes */ ++/* mvPexInit - Initialize PEX interfaces*/ ++MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf); ++ ++/* mvPexConfigRead - Read from configuration space */ ++MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPexConfigWrite - Write to configuration space */ ++MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++ ++#endif /* #ifndef __INCPEXH */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,1522 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "mvOs.h" ++#include "sflash/mvSFlash.h" ++#include "sflash/mvSFlashSpec.h" ++#include "spi/mvSpi.h" ++#include "spi/mvSpiCmnd.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/*#define MV_DEBUG*/ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++/* Globals */ ++static MV_SFLASH_DEVICE_PARAMS sflash[] = { ++ /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ ++ { ++ MV_M25P_WREN_CMND_OPCD, ++ MV_M25P_WRDI_CMND_OPCD, ++ MV_M25P_RDID_CMND_OPCD, ++ MV_M25P_RDSR_CMND_OPCD, ++ MV_M25P_WRSR_CMND_OPCD, ++ MV_M25P_READ_CMND_OPCD, ++ MV_M25P_FAST_RD_CMND_OPCD, ++ MV_M25P_PP_CMND_OPCD, ++ MV_M25P_SE_CMND_OPCD, ++ MV_M25P_BE_CMND_OPCD, ++ MV_M25P_RES_CMND_OPCD, ++ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ ++ MV_M25P32_SECTOR_SIZE, ++ MV_M25P32_SECTOR_NUMBER, ++ MV_M25P_PAGE_SIZE, ++ "ST M25P32", ++ MV_M25PXXX_ST_MANF_ID, ++ MV_M25P32_DEVICE_ID, ++ MV_M25P32_MAX_SPI_FREQ, ++ MV_M25P32_MAX_FAST_SPI_FREQ, ++ MV_M25P32_FAST_READ_DUMMY_BYTES ++ }, ++ /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ ++ { ++ MV_M25P_WREN_CMND_OPCD, ++ MV_M25P_WRDI_CMND_OPCD, ++ MV_M25P_RDID_CMND_OPCD, ++ MV_M25P_RDSR_CMND_OPCD, ++ MV_M25P_WRSR_CMND_OPCD, ++ MV_M25P_READ_CMND_OPCD, ++ MV_M25P_FAST_RD_CMND_OPCD, ++ MV_M25P_PP_CMND_OPCD, ++ MV_M25P_SE_CMND_OPCD, ++ MV_M25P_BE_CMND_OPCD, ++ MV_M25P_RES_CMND_OPCD, ++ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ ++ MV_M25P64_SECTOR_SIZE, ++ MV_M25P64_SECTOR_NUMBER, ++ MV_M25P_PAGE_SIZE, ++ "ST M25P64", ++ MV_M25PXXX_ST_MANF_ID, ++ MV_M25P64_DEVICE_ID, ++ MV_M25P64_MAX_SPI_FREQ, ++ MV_M25P64_MAX_FAST_SPI_FREQ, ++ MV_M25P64_FAST_READ_DUMMY_BYTES ++ }, ++ /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ ++ { ++ MV_M25P_WREN_CMND_OPCD, ++ MV_M25P_WRDI_CMND_OPCD, ++ MV_M25P_RDID_CMND_OPCD, ++ MV_M25P_RDSR_CMND_OPCD, ++ MV_M25P_WRSR_CMND_OPCD, ++ MV_M25P_READ_CMND_OPCD, ++ MV_M25P_FAST_RD_CMND_OPCD, ++ MV_M25P_PP_CMND_OPCD, ++ MV_M25P_SE_CMND_OPCD, ++ MV_M25P_BE_CMND_OPCD, ++ MV_M25P_RES_CMND_OPCD, ++ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ ++ MV_M25P128_SECTOR_SIZE, ++ MV_M25P128_SECTOR_NUMBER, ++ MV_M25P_PAGE_SIZE, ++ "ST M25P128", ++ MV_M25PXXX_ST_MANF_ID, ++ MV_M25P128_DEVICE_ID, ++ MV_M25P128_MAX_SPI_FREQ, ++ MV_M25P128_MAX_FAST_SPI_FREQ, ++ MV_M25P128_FAST_READ_DUMMY_BYTES ++ }, ++ /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ ++ { ++ MV_MX25L_WREN_CMND_OPCD, ++ MV_MX25L_WRDI_CMND_OPCD, ++ MV_MX25L_RDID_CMND_OPCD, ++ MV_MX25L_RDSR_CMND_OPCD, ++ MV_MX25L_WRSR_CMND_OPCD, ++ MV_MX25L_READ_CMND_OPCD, ++ MV_MX25L_FAST_RD_CMND_OPCD, ++ MV_MX25L_PP_CMND_OPCD, ++ MV_MX25L_SE_CMND_OPCD, ++ MV_MX25L_BE_CMND_OPCD, ++ MV_MX25L_RES_CMND_OPCD, ++ MV_MX25L_DP_CMND_OPCD, ++ MV_MX25L6405_SECTOR_SIZE, ++ MV_MX25L6405_SECTOR_NUMBER, ++ MV_MXIC_PAGE_SIZE, ++ "MXIC MX25L6405", ++ MV_MXIC_MANF_ID, ++ MV_MX25L6405_DEVICE_ID, ++ MV_MX25L6405_MAX_SPI_FREQ, ++ MV_MX25L6405_MAX_FAST_SPI_FREQ, ++ MV_MX25L6405_FAST_READ_DUMMY_BYTES ++ }, ++ /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ ++ { ++ MV_S25FL_WREN_CMND_OPCD, ++ MV_S25FL_WRDI_CMND_OPCD, ++ MV_S25FL_RDID_CMND_OPCD, ++ MV_S25FL_RDSR_CMND_OPCD, ++ MV_S25FL_WRSR_CMND_OPCD, ++ MV_S25FL_READ_CMND_OPCD, ++ MV_S25FL_FAST_RD_CMND_OPCD, ++ MV_S25FL_PP_CMND_OPCD, ++ MV_S25FL_SE_CMND_OPCD, ++ MV_S25FL_BE_CMND_OPCD, ++ MV_S25FL_RES_CMND_OPCD, ++ MV_S25FL_DP_CMND_OPCD, ++ MV_S25FL128_SECTOR_SIZE, ++ MV_S25FL128_SECTOR_NUMBER, ++ MV_S25FL_PAGE_SIZE, ++ "SPANSION S25FL128", ++ MV_SPANSION_MANF_ID, ++ MV_S25FL128_DEVICE_ID, ++ MV_S25FL128_MAX_SPI_FREQ, ++ MV_M25P128_MAX_FAST_SPI_FREQ, ++ MV_M25P128_FAST_READ_DUMMY_BYTES ++ } ++}; ++ ++/* Static Functions */ ++static MV_STATUS mvWriteEnable (MV_SFLASH_INFO * pFlinfo); ++static MV_STATUS mvStatusRegGet (MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg); ++static MV_STATUS mvStatusRegSet (MV_SFLASH_INFO * pFlinfo, MV_U8 sr); ++static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo); ++static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, \ ++ MV_U8* pPageBuff, MV_U32 buffSize); ++static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, \ ++ MV_U8* manId, MV_U16* devId); ++ ++/******************************************************************************* ++* mvWriteEnable - serialize the write enable sequence ++* ++* DESCRIPTION: ++* transmit the sequence for write enable ++* ++********************************************************************************/ ++static MV_STATUS mvWriteEnable(MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_U8 cmd[MV_SFLASH_WREN_CMND_LENGTH]; ++ ++ ++ cmd[0] = sflash[pFlinfo->index].opcdWREN; ++ ++ return mvSpiWriteThenRead(cmd, MV_SFLASH_WREN_CMND_LENGTH, NULL, 0, 0); ++} ++ ++/******************************************************************************* ++* mvStatusRegGet - Retrieve the value of the status register ++* ++* DESCRIPTION: ++* perform the RDSR sequence to get the 8bit status register ++* ++********************************************************************************/ ++static MV_STATUS mvStatusRegGet(MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_RDSR_CMND_LENGTH]; ++ MV_U8 sr[MV_SFLASH_RDSR_REPLY_LENGTH]; ++ ++ ++ ++ ++ cmd[0] = sflash[pFlinfo->index].opcdRDSR; ++ ++ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDSR_CMND_LENGTH, sr, ++ MV_SFLASH_RDSR_REPLY_LENGTH,0)) != MV_OK) ++ return ret; ++ ++ *pStatReg = sr[0]; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared ++* ++* DESCRIPTION: ++* Block waiting for the WIP (write in progress) to be cleared ++* ++********************************************************************************/ ++static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U32 i; ++ MV_U8 stat; ++ ++ for (i=0; iindex].opcdWRSR; ++ cmd[1] = sr; ++ ++ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_WRSR_CMND_LENGTH, NULL, 0, 0)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) ++ return ret; ++ ++ mvOsDelay(1); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashPageWr - Write up to 256 Bytes in the same page ++* ++* DESCRIPTION: ++* Write a buffer up to the page size in length provided that the whole address ++* range is within the same page (alligned to page bounderies) ++* ++*******************************************************************************/ ++static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pPageBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_PP_CMND_LENGTH]; ++ ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invalid parameter device index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that we do not cross the page bounderies */ ++ if (((offset & (sflash[pFlinfo->index].pageSize - 1)) + buffSize) > ++ sflash[pFlinfo->index].pageSize) ++ { ++ DB(mvOsPrintf("%s WARNING: Page allignment problem!\n", __FUNCTION__);) ++ return MV_OUT_OF_RANGE; ++ } ++ ++ /* Issue the Write enable command prior the page program command */ ++ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) ++ return ret; ++ ++ cmd[0] = sflash[pFlinfo->index].opcdPP; ++ cmd[1] = ((offset >> 16) & 0xFF); ++ cmd[2] = ((offset >> 8) & 0xFF); ++ cmd[3] = (offset & 0xFF); ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_PP_CMND_LENGTH, pPageBuff, buffSize)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashWithDefaultsIdGet - Try to read the manufacturer and Device IDs from ++* the device using the default RDID opcode and the default WREN opcode. ++* ++* DESCRIPTION: ++* This is used to detect a generic device that uses the default opcodes ++* for the WREN and RDID. ++* ++********************************************************************************/ ++static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* manId, MV_U16* devId) ++{ ++ MV_STATUS ret; ++ MV_U8 cmdRDID[MV_SFLASH_RDID_CMND_LENGTH]; ++ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; ++ ++ ++ ++ /* Use the default RDID opcode to read the IDs */ ++ cmdRDID[0] = MV_SFLASH_DEFAULT_RDID_OPCD; /* unknown model try default */ ++ if ((ret = mvSpiWriteThenRead(cmdRDID, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) ++ return ret; ++ ++ *manId = id[0]; ++ *devId = 0; ++ *devId |= (id[1] << 8); ++ *devId |= id[2]; ++ ++ return MV_OK; ++} ++ ++/* ++##################################################################################### ++##################################################################################### ++*/ ++ ++/******************************************************************************* ++* mvSFlashInit - Initialize the serial flash device ++* ++* DESCRIPTION: ++* Perform the neccessary initialization and configuration ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* pFlinfo->baseAddr: base address in fast mode. ++* pFlinfo->index: Index of the flash in the sflash tabel. If the SPI ++* flash device does not support read Id command with ++* the standard opcode, then the user should supply this ++* as an input to skip the autodetection process!!!! ++* ++* OUTPUT: ++* pFlinfo: pointer to the Flash information structure after detection ++* pFlinfo->manufacturerId: Manufacturer ID ++* pFlinfo->deviceId: Device ID ++* pFlinfo->sectorSize: size of the sector (all sectors are the same). ++* pFlinfo->sectorNumber: number of sectors. ++* pFlinfo->pageSize: size of the page. ++* pFlinfo->index: Index of the detected flash in the sflash tabel ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 manf; ++ MV_U16 dev; ++ MV_U32 indx; ++ MV_BOOL detectFlag = MV_FALSE; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Initialize the SPI interface with low frequency to make sure that the read ID succeeds */ ++ if ((ret = mvSpiInit(MV_SFLASH_BASIC_SPI_FREQ)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to initialize the SPI interface!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ /* First try to read the Manufacturer and Device IDs */ ++ if ((ret = mvSFlashIdGet(pFlinfo, &manf, &dev)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to get the SFlash ID!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ /* loop over the whole table and look for the appropriate SFLASH */ ++ for (indx=0; indxmanufacturerId = manf; ++ pFlinfo->deviceId = dev; ++ pFlinfo->index = indx; ++ detectFlag = MV_TRUE; ++ } ++ } ++ ++ if(!detectFlag) ++ { ++ mvOsPrintf("%s ERROR: Unknown SPI flash device!\n", __FUNCTION__); ++ return MV_FAIL; ++ } ++ ++ /* fill the info based on the model detected */ ++ pFlinfo->sectorSize = sflash[pFlinfo->index].sectorSize; ++ pFlinfo->sectorNumber = sflash[pFlinfo->index].sectorNumber; ++ pFlinfo->pageSize = sflash[pFlinfo->index].pageSize; ++ ++ /* Set the SPI frequency to the MAX allowed for the device for best performance */ ++ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ /* As default lock the SR */ ++ if ((ret = mvSFlashStatRegLock(pFlinfo, MV_TRUE)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashSectorErase - Erasse a single sector of the serial flash ++* ++* DESCRIPTION: ++* Issue the erase sector command and address ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* secNumber: sector Number to erase (0 -> (sectorNumber-1)) ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_SE_CMND_LENGTH]; ++ ++ MV_U32 secAddr = (secNumber * pFlinfo->sectorSize); ++#if 0 ++ MV_U32 i; ++ MV_U32 * pW = (MV_U32*) (secAddr + pFlinfo->baseAddr); ++ MV_U32 erasedWord = 0xFFFFFFFF; ++ MV_U32 wordsPerSector = (pFlinfo->sectorSize / sizeof(MV_U32)); ++ MV_BOOL eraseNeeded = MV_FALSE; ++#endif ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that the sector number is valid */ ++ if (secNumber >= pFlinfo->sectorNumber) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter sector number!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* we don't want to access SPI in direct mode from in-direct API, ++ becasue of timing issue between CS asserts. */ ++#if 0 ++ /* First compare to FF and check if erase is needed */ ++ for (i=0; iindex].opcdSE; ++ cmd[1] = ((secAddr >> 16) & 0xFF); ++ cmd[2] = ((secAddr >> 8) & 0xFF); ++ cmd[3] = (secAddr & 0xFF); ++ ++ /* Issue the Write enable command prior the sector erase command */ ++ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_SE_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashChipErase - Erasse the whole serial flash ++* ++* DESCRIPTION: ++* Issue the bulk (chip) erase command ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_BE_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdBE; ++ ++ /* Issue the Write enable command prior the Bulk erase command */ ++ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_BE_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnChipEraseDone(pFlinfo)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashBlockRd - Read from the serial flash ++* ++* DESCRIPTION: ++* Issue the read command and address then perfom the needed read ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* offset: byte offset with the flash to start reading from ++* pReadBuff: pointer to the buffer to read the data in ++* buffSize: size of the buffer to read. ++* ++* OUTPUT: ++* pReadBuff: pointer to the buffer containing the read data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize) ++{ ++ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pReadBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdREAD; ++ cmd[1] = ((offset >> 16) & 0xFF); ++ cmd[2] = ((offset >> 8) & 0xFF); ++ cmd[3] = (offset & 0xFF); ++ ++ return mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, 0); ++} ++ ++/******************************************************************************* ++* mvSFlashFastBlockRd - Fast read from the serial flash ++* ++* DESCRIPTION: ++* Issue the fast read command and address then perfom the needed read ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* offset: byte offset with the flash to start reading from ++* pReadBuff: pointer to the buffer to read the data in ++* buffSize: size of the buffer to read. ++* ++* OUTPUT: ++* pReadBuff: pointer to the buffer containing the read data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize) ++{ ++ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; ++ MV_STATUS ret; ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pReadBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* Set the SPI frequency to the MAX allowed for fast-read operations */ ++ mvOsPrintf("Setting freq to %d.\n",sflash[pFlinfo->index].spiMaxFastFreq); ++ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFastFreq)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to set the SPI fast frequency!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdFSTRD; ++ cmd[1] = ((offset >> 16) & 0xFF); ++ cmd[2] = ((offset >> 8) & 0xFF); ++ cmd[3] = (offset & 0xFF); ++ ++ ++ ret = mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, ++ sflash[pFlinfo->index].spiFastRdDummyBytes); ++ ++ /* Reset the SPI frequency to the MAX allowed for the device for best performance */ ++ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++ ++/******************************************************************************* ++* mvSFlashBlockWr - Write a buffer with any size ++* ++* DESCRIPTION: ++* write regardless of the page boundaries and size limit per Page ++* program command ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* offset: byte offset within the flash region ++* pWriteBuff: pointer to the buffer holding the data to program ++* buffSize: size of the buffer to write ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pWriteBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 data2write = buffSize; ++ MV_U32 preAllOffset = (offset & MV_SFLASH_PAGE_ALLIGN_MASK(MV_M25P_PAGE_SIZE)); ++ MV_U32 preAllSz = (preAllOffset ? (MV_M25P_PAGE_SIZE - preAllOffset) : 0); ++ MV_U32 writeOffset = offset; ++ ++ /* check for NULL pointer */ ++#ifndef CONFIG_MARVELL ++ if(NULL == pWriteBuff) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++#endif ++ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that the buffer size does not exceed the flash size */ ++ if ((offset + buffSize) > mvSFlashSizeGet(pFlinfo)) ++ { ++ DB(mvOsPrintf("%s WARNING: Write exceeds flash size!\n", __FUNCTION__);) ++ return MV_OUT_OF_RANGE; ++ } ++ ++ /* check if the total block size is less than the first chunk remainder */ ++ if (data2write < preAllSz) ++ preAllSz = data2write; ++ ++ /* check if programing does not start at a 64byte alligned offset */ ++ if (preAllSz) ++ { ++ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, preAllSz)) != MV_OK) ++ return ret; ++ ++ /* increment pointers and counters */ ++ writeOffset += preAllSz; ++ data2write -= preAllSz; ++ pWriteBuff += preAllSz; ++ } ++ ++ /* program the data that fits in complete page chunks */ ++ while (data2write >= sflash[pFlinfo->index].pageSize) ++ { ++ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, sflash[pFlinfo->index].pageSize)) != MV_OK) ++ return ret; ++ ++ /* increment pointers and counters */ ++ writeOffset += sflash[pFlinfo->index].pageSize; ++ data2write -= sflash[pFlinfo->index].pageSize; ++ pWriteBuff += sflash[pFlinfo->index].pageSize; ++ } ++ ++ /* program the last partial chunk */ ++ if (data2write) ++ { ++ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, data2write)) != MV_OK) ++ return ret; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashIdGet - Get the manufacturer and device IDs. ++* ++* DESCRIPTION: ++* Get the Manufacturer and device IDs from the serial flash through ++* writing the RDID command then reading 3 bytes of data. In case that ++* this command was called for the first time in order to detect the ++* manufacturer and device IDs, then the default RDID opcode will be used ++* unless the device index is indicated by the user (in case the SPI flash ++* does not use the default RDID opcode). ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* pManId: pointer to the 8bit variable to hold the manufacturing ID ++* pDevId: pointer to the 16bit variable to hold the device ID ++* ++* OUTPUT: ++* pManId: pointer to the 8bit variable holding the manufacturing ID ++* pDevId: pointer to the 16bit variable holding the device ID ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_RDID_CMND_LENGTH]; ++ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; ++ ++ ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pManId == NULL) || (pDevId == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ return mvSFlashWithDefaultsIdGet(pFlinfo, pManId, pDevId); ++ else ++ cmd[0] = sflash[pFlinfo->index].opcdRDID; ++ ++ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) ++ return ret; ++ ++ *pManId = id[0]; ++ *pDevId = 0; ++ *pDevId |= (id[1] << 8); ++ *pDevId |= id[2]; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashWpRegionSet - Set the Write-Protected region ++* ++* DESCRIPTION: ++* Set the Write-Protected region ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* wpRegion: which region will be protected ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion) ++{ ++ MV_U8 wpMask; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the chip is an ST flash; then WP supports only 3 bits */ ++ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) ++ { ++ switch (wpRegion) ++ { ++ case MV_WP_NONE: ++ wpMask = MV_M25P_STATUS_BP_NONE; ++ break; ++ ++ case MV_WP_UPR_1OF128: ++ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ ++ case MV_WP_UPR_1OF64: ++ wpMask = MV_M25P_STATUS_BP_1_OF_64; ++ break; ++ ++ case MV_WP_UPR_1OF32: ++ wpMask = MV_M25P_STATUS_BP_1_OF_32; ++ break; ++ ++ case MV_WP_UPR_1OF16: ++ wpMask = MV_M25P_STATUS_BP_1_OF_16; ++ break; ++ ++ case MV_WP_UPR_1OF8: ++ wpMask = MV_M25P_STATUS_BP_1_OF_8; ++ break; ++ ++ case MV_WP_UPR_1OF4: ++ wpMask = MV_M25P_STATUS_BP_1_OF_4; ++ break; ++ ++ case MV_WP_UPR_1OF2: ++ wpMask = MV_M25P_STATUS_BP_1_OF_2; ++ break; ++ ++ case MV_WP_ALL: ++ wpMask = MV_M25P_STATUS_BP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ } ++ /* check if the manufacturer is MXIC then the WP is 4bits */ ++ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) ++ { ++ switch (wpRegion) ++ { ++ case MV_WP_NONE: ++ wpMask = MV_MX25L_STATUS_BP_NONE; ++ break; ++ ++ case MV_WP_UPR_1OF128: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_128; ++ break; ++ ++ case MV_WP_UPR_1OF64: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_64; ++ break; ++ ++ case MV_WP_UPR_1OF32: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_32; ++ break; ++ ++ case MV_WP_UPR_1OF16: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_16; ++ break; ++ ++ case MV_WP_UPR_1OF8: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_8; ++ break; ++ ++ case MV_WP_UPR_1OF4: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_4; ++ break; ++ ++ case MV_WP_UPR_1OF2: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_2; ++ break; ++ ++ case MV_WP_ALL: ++ wpMask = MV_MX25L_STATUS_BP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ } ++ /* check if the manufacturer is SPANSION then the WP is 4bits */ ++ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) ++ { ++ switch (wpRegion) ++ { ++ case MV_WP_NONE: ++ wpMask = MV_S25FL_STATUS_BP_NONE; ++ break; ++ ++ case MV_WP_UPR_1OF128: ++ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ ++ case MV_WP_UPR_1OF64: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_64; ++ break; ++ ++ case MV_WP_UPR_1OF32: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_32; ++ break; ++ ++ case MV_WP_UPR_1OF16: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_16; ++ break; ++ ++ case MV_WP_UPR_1OF8: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_8; ++ break; ++ ++ case MV_WP_UPR_1OF4: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_4; ++ break; ++ ++ case MV_WP_UPR_1OF2: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_2; ++ break; ++ ++ case MV_WP_ALL: ++ wpMask = MV_S25FL_STATUS_BP_ALL; ++ break; ++ ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ } ++ else ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* Verify that the SRWD bit is always set - register is s/w locked */ ++ wpMask |= MV_SFLASH_STATUS_REG_SRWD_MASK; ++ ++ return mvStatusRegSet(pFlinfo, wpMask); ++} ++ ++/******************************************************************************* ++* mvSFlashWpRegionGet - Get the Write-Protected region configured ++* ++* DESCRIPTION: ++* Get from the chip the Write-Protected region configured ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* pWpRegion: pointer to the variable to return the WP region in ++* ++* OUTPUT: ++* wpRegion: pointer to the variable holding the WP region configured ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion) ++{ ++ MV_STATUS ret; ++ MV_U8 reg; ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pWpRegion == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) ++ return ret; ++ ++ /* Check if the chip is an ST flash; then WP supports only 3 bits */ ++ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) ++ { ++ switch ((reg & MV_M25P_STATUS_REG_WP_MASK)) ++ { ++ case MV_M25P_STATUS_BP_NONE: ++ *pWpRegion = MV_WP_NONE; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_64: ++ *pWpRegion = MV_WP_UPR_1OF64; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_32: ++ *pWpRegion = MV_WP_UPR_1OF32; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_16: ++ *pWpRegion = MV_WP_UPR_1OF16; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_8: ++ *pWpRegion = MV_WP_UPR_1OF8; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_4: ++ *pWpRegion = MV_WP_UPR_1OF4; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_2: ++ *pWpRegion = MV_WP_UPR_1OF2; ++ break; ++ ++ case MV_M25P_STATUS_BP_ALL: ++ *pWpRegion = MV_WP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) ++ return MV_BAD_VALUE; ++ } ++ } ++ /* check if the manufacturer is MXIC then the WP is 4bits */ ++ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) ++ { ++ switch ((reg & MV_MX25L_STATUS_REG_WP_MASK)) ++ { ++ case MV_MX25L_STATUS_BP_NONE: ++ *pWpRegion = MV_WP_NONE; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_128: ++ *pWpRegion = MV_WP_UPR_1OF128; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_64: ++ *pWpRegion = MV_WP_UPR_1OF64; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_32: ++ *pWpRegion = MV_WP_UPR_1OF32; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_16: ++ *pWpRegion = MV_WP_UPR_1OF16; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_8: ++ *pWpRegion = MV_WP_UPR_1OF8; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_4: ++ *pWpRegion = MV_WP_UPR_1OF4; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_2: ++ *pWpRegion = MV_WP_UPR_1OF2; ++ break; ++ ++ case MV_MX25L_STATUS_BP_ALL: ++ *pWpRegion = MV_WP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) ++ return MV_BAD_VALUE; ++ } ++ } ++ /* Check if the chip is an SPANSION flash; then WP supports only 3 bits */ ++ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) ++ { ++ switch ((reg & MV_S25FL_STATUS_REG_WP_MASK)) ++ { ++ case MV_S25FL_STATUS_BP_NONE: ++ *pWpRegion = MV_WP_NONE; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_64: ++ *pWpRegion = MV_WP_UPR_1OF64; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_32: ++ *pWpRegion = MV_WP_UPR_1OF32; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_16: ++ *pWpRegion = MV_WP_UPR_1OF16; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_8: ++ *pWpRegion = MV_WP_UPR_1OF8; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_4: ++ *pWpRegion = MV_WP_UPR_1OF4; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_2: ++ *pWpRegion = MV_WP_UPR_1OF2; ++ break; ++ ++ case MV_S25FL_STATUS_BP_ALL: ++ *pWpRegion = MV_WP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) ++ return MV_BAD_VALUE; ++ } ++ } ++ else ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashStatRegLock - Lock the status register for writing - W/Vpp ++* pin should be low to take effect ++* ++* DESCRIPTION: ++* Lock the access to the Status Register for writing. This will ++* cause the flash to enter the hardware protection mode if the W/Vpp ++* is low. If the W/Vpp is hi, the chip will be in soft protection mode, but ++* the register will continue to be writable if WREN sequence was used. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* srLock: enable/disable (MV_TRUE/MV_FALSE) status registor lock mechanism ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock) ++{ ++ MV_STATUS ret; ++ MV_U8 reg; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) ++ return ret; ++ ++ if (srLock) ++ reg |= MV_SFLASH_STATUS_REG_SRWD_MASK; ++ else ++ reg &= ~MV_SFLASH_STATUS_REG_SRWD_MASK; ++ ++ return mvStatusRegSet(pFlinfo, reg); ++} ++ ++/******************************************************************************* ++* mvSFlashSizeGet - Get the size of the SPI flash ++* ++* DESCRIPTION: ++* based on the sector number and size of each sector calculate the total ++* size of the flash memory. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Size of the flash in bytes. ++* ++* ++*******************************************************************************/ ++MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo) ++{ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ return (pFlinfo->sectorSize * pFlinfo->sectorNumber); ++} ++ ++/******************************************************************************* ++* mvSFlashPowerSaveEnter - Cause the falsh device to go into power save mode ++* ++* DESCRIPTION: ++* Enter a special power save mode. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Size of the flash in bytes. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_DP_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that power save mode is supported in the specific device */ ++ if (sflash[pFlinfo->index].opcdPwrSave == MV_SFLASH_NO_SPECIFIC_OPCD) ++ { ++ DB(mvOsPrintf("%s WARNING: Power save not supported for this device!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdPwrSave; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_DP_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvSFlashPowerSaveExit - Cause the falsh device to exit the power save mode ++* ++* DESCRIPTION: ++* Exit the deep power save mode. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Size of the flash in bytes. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_RES_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that power save mode is supported in the specific device */ ++ if (sflash[pFlinfo->index].opcdRES == MV_SFLASH_NO_SPECIFIC_OPCD) ++ { ++ DB(mvOsPrintf("%s WARNING: Read Electronic Signature not supported for this device!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdRES; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_RES_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ /* add the delay needed for the device to wake up */ ++ mvOsDelay(MV_MXIC_DP_EXIT_DELAY); /* 30 ms */ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvSFlashModelGet - Retreive the string with the device manufacturer and model ++* ++* DESCRIPTION: ++* Retreive the string with the device manufacturer and model ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* pointer to the string indicating the device manufacturer and model ++* ++* ++*******************************************************************************/ ++const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo) ++{ ++ static const MV_8 * unknModel = (const MV_8 *)"Unknown"; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return unknModel; ++ } ++ ++ return sflash[pFlinfo->index].deviceModel; ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,166 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSFlashH ++#define __INCmvSFlashH ++ ++#include "mvTypes.h" ++ ++/* MCAROS */ ++#define MV_SFLASH_PAGE_ALLIGN_MASK(pgSz) (pgSz-1) ++#define MV_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) ++ ++/* Constants */ ++#define MV_INVALID_DEVICE_NUMBER 0xFFFFFFFF ++/* 10 MHz is the minimum possible SPI frequency when tclk is set 200MHz*/ ++#define MV_SFLASH_BASIC_SPI_FREQ 10000000 ++/* enumerations */ ++typedef enum ++{ ++ MV_WP_NONE, /* Unprotect the whole chip */ ++ MV_WP_UPR_1OF128, /* Write protect the upper 1/128 part */ ++ MV_WP_UPR_1OF64, /* Write protect the upper 1/64 part */ ++ MV_WP_UPR_1OF32, /* Write protect the upper 1/32 part */ ++ MV_WP_UPR_1OF16, /* Write protect the upper 1/16 part */ ++ MV_WP_UPR_1OF8, /* Write protect the upper 1/8 part */ ++ MV_WP_UPR_1OF4, /* Write protect the upper 1/4 part */ ++ MV_WP_UPR_1OF2, /* Write protect the upper 1/2 part */ ++ MV_WP_ALL /* Write protect the whole chip */ ++} MV_SFLASH_WP_REGION; ++ ++/* Type Definitions */ ++typedef struct ++{ ++ MV_U8 opcdWREN; /* Write enable opcode */ ++ MV_U8 opcdWRDI; /* Write disable opcode */ ++ MV_U8 opcdRDID; /* Read ID opcode */ ++ MV_U8 opcdRDSR; /* Read Status Register opcode */ ++ MV_U8 opcdWRSR; /* Write Status register opcode */ ++ MV_U8 opcdREAD; /* Read opcode */ ++ MV_U8 opcdFSTRD; /* Fast Read opcode */ ++ MV_U8 opcdPP; /* Page program opcode */ ++ MV_U8 opcdSE; /* Sector erase opcode */ ++ MV_U8 opcdBE; /* Bulk erase opcode */ ++ MV_U8 opcdRES; /* Read electronic signature */ ++ MV_U8 opcdPwrSave; /* Go into power save mode */ ++ MV_U32 sectorSize; /* Size of each sector */ ++ MV_U32 sectorNumber; /* Number of sectors */ ++ MV_U32 pageSize; /* size of each page */ ++ const char * deviceModel; /* string with the device model */ ++ MV_U32 manufacturerId; /* The manufacturer ID */ ++ MV_U32 deviceId; /* Device ID */ ++ MV_U32 spiMaxFreq; /* The MAX frequency that can be used with the device */ ++ MV_U32 spiMaxFastFreq; /* The MAX frequency that can be used with the device for fast reads */ ++ MV_U32 spiFastRdDummyBytes; /* Number of dumy bytes to read before real data when working in fast read mode. */ ++} MV_SFLASH_DEVICE_PARAMS; ++ ++typedef struct ++{ ++ MV_U32 baseAddr; /* Flash Base Address used in fast mode */ ++ MV_U8 manufacturerId; /* Manufacturer ID */ ++ MV_U16 deviceId; /* Device ID */ ++ MV_U32 sectorSize; /* Size of each sector - all the same */ ++ MV_U32 sectorNumber; /* Number of sectors */ ++ MV_U32 pageSize; /* Page size - affect allignment */ ++ MV_U32 index; /* index of the device in the sflash table (internal parameter) */ ++} MV_SFLASH_INFO; ++ ++/* Function Prototypes */ ++/* Init */ ++MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo); ++ ++/* erase */ ++MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber); ++MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo); ++ ++/* Read */ ++MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize); ++MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize); ++ ++/* write regardless of the page boundaries and size limit per Page program command */ ++MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pWriteBuff, MV_U32 buffSize); ++/* Get IDs */ ++MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId); ++ ++/* Set and Get the Write Protection region - if the Status register is not locked */ ++MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion); ++MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion); ++ ++/* Lock the status register for writing - W/Vpp pin should be low to take effect */ ++MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock); ++ ++/* Get the regions sizes */ ++MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo); ++ ++/* Cause the falsh device to go into power save mode */ ++MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo); ++MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo); ++ ++/* Retreive the string with the device manufacturer and model */ ++const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo); ++ ++#endif /* __INCmvSFlashH */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,233 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSFlashSpecH ++#define __INCmvSFlashSpecH ++ ++/* Constants */ ++#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ ++#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ ++#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ ++#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */ ++#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ ++#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */ ++#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ ++ ++/* Status Register Bit Masks */ ++#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */ ++#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */ ++#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */ ++#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET) ++#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET) ++ ++#define MV_SFLASH_MAX_WAIT_LOOP 1000000 ++#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 ++ ++#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ ++#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ ++#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00 ++ ++/********************************/ ++/* ST M25Pxxx Device Specific */ ++/********************************/ ++ ++/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ ++#define MV_M25PXXX_ST_MANF_ID 0x20 ++#define MV_M25P32_DEVICE_ID 0x2016 ++#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_M25P32_FAST_READ_DUMMY_BYTES 1 ++#define MV_M25P64_DEVICE_ID 0x2017 ++#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_M25P64_FAST_READ_DUMMY_BYTES 1 ++#define MV_M25P128_DEVICE_ID 0x2018 ++#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_M25P128_FAST_READ_DUMMY_BYTES 1 ++ ++ ++/* Sector Sizes and population per device model*/ ++#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */ ++#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */ ++#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */ ++#define MV_M25P32_SECTOR_NUMBER 64 ++#define MV_M25P64_SECTOR_NUMBER 128 ++#define MV_M25P128_SECTOR_NUMBER 64 ++#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */ ++ ++#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ ++#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ ++#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ ++#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */ ++#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */ ++#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ ++#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ ++#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */ ++#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ ++#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ ++#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ ++ ++/* Status Register Write Protect Bit Masks - 3bits */ ++#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++ ++/************************************/ ++/* MXIC MX25L6405 Device Specific */ ++/************************************/ ++ ++/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ ++#define MV_MXIC_MANF_ID 0xC2 ++#define MV_MX25L6405_DEVICE_ID 0x2017 ++#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1 ++#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ ++ ++/* Sector Sizes and population per device model*/ ++#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ ++#define MV_MX25L6405_SECTOR_NUMBER 128 ++#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */ ++ ++#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ ++#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ ++#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ ++#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */ ++#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */ ++#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ ++#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ ++#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ ++#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ ++#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ ++#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ ++#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ ++ ++/* Status Register Write Protect Bit Masks - 4bits */ ++#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++ ++/************************************/ ++/* SPANSION S25FL128P Device Specific */ ++/************************************/ ++ ++/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ ++#define MV_SPANSION_MANF_ID 0x01 ++#define MV_S25FL128_DEVICE_ID 0x2018 ++#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ ++#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ ++#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1 ++ ++/* Sector Sizes and population per device model*/ ++#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */ ++#define MV_S25FL128_SECTOR_NUMBER 64 ++#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */ ++ ++#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ ++#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ ++#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ ++#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */ ++#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */ ++#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ ++#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ ++#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ ++#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ ++#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ ++#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ ++#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ ++ ++/* Status Register Write Protect Bit Masks - 4bits */ ++#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++ ++#endif /* __INCmvSFlashSpecH */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,576 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "spi/mvSpi.h" ++#include "spi/mvSpiSpec.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* #define MV_DEBUG */ ++#ifdef MV_DEBUG ++#define DB(x) x ++#define mvOsPrintf printf ++#else ++#define DB(x) ++#endif ++ ++ ++/******************************************************************************* ++* mvSpi16bitDataTxRx - Transmt and receive data ++* ++* DESCRIPTION: ++* Tx data and block waiting for data to be transmitted ++* ++********************************************************************************/ ++static MV_STATUS mvSpi16bitDataTxRx (MV_U16 txData, MV_U16 * pRxData) ++{ ++ MV_U32 i; ++ MV_BOOL ready = MV_FALSE; ++ ++ /* First clear the bit in the interrupt cause register */ ++ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); ++ ++ /* Transmit data */ ++ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, MV_16BIT_LE(txData)); ++ ++ /* wait with timeout for memory ready */ ++ for (i=0; i> 8) & 0xFF); ++ ++#elif defined(MV_CPU_BE) ++ ++ /* perform the data write to the buffer in two stages with 8bit each */ ++ MV_U8 * bptr = (MV_U8 *)pRxData; ++ MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); ++ *bptr = ((data >> 8) & 0xFF); ++ ++bptr; ++ *bptr = (data & 0xFF); ++ ++#else ++ #error "CPU endianess isn't defined!\n" ++#endif ++ ++ } ++ else ++ *pRxData = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvSpi8bitDataTxRx - Transmt and receive data (8bits) ++* ++* DESCRIPTION: ++* Tx data and block waiting for data to be transmitted ++* ++********************************************************************************/ ++static MV_STATUS mvSpi8bitDataTxRx (MV_U8 txData, MV_U8 * pRxData) ++{ ++ MV_U32 i; ++ MV_BOOL ready = MV_FALSE; ++ ++ /* First clear the bit in the interrupt cause register */ ++ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); ++ ++ /* Transmit data */ ++ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, txData); ++ ++ /* wait with timeout for memory ready */ ++ for (i=0; i serialBaudRate) ++ continue; ++ ++ /* check for exact fit */ ++ if ((cpuClk / preScale[i]) == serialBaudRate) ++ { ++ bestPrescaleIndx = i; ++ break; ++ } ++ ++ /* check if this is better than the previous one */ ++ if ((serialBaudRate - (cpuClk / preScale[i])) < minBaudOffset) ++ { ++ minBaudOffset = (serialBaudRate - (cpuClk / preScale[i])); ++ bestPrescaleIndx = i; ++ } ++ } ++ ++ if (bestPrescaleIndx > 14) ++ { ++ mvOsPrintf("%s ERROR: SPI baud rate prescale error!\n", __FUNCTION__); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ /* configure the Prescale */ ++ tempReg = MV_REG_READ(MV_SPI_IF_CONFIG_REG); ++ tempReg = ((tempReg & ~MV_SPI_CLK_PRESCALE_MASK) | (bestPrescaleIndx + 0x12)); ++ MV_REG_WRITE(MV_SPI_IF_CONFIG_REG, tempReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSpiCsAssert - Assert the Chip Select pin indicating a new transfer ++* ++* DESCRIPTION: ++* Assert The chip select - used to select an external SPI device ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++********************************************************************************/ ++MV_VOID mvSpiCsAssert(MV_VOID) ++{ ++ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ ++ mvMPPConfigToSPI(); ++ mvOsUDelay(1); ++ MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); ++} ++ ++/******************************************************************************* ++* mvSpiCsDeassert - DeAssert the Chip Select pin indicating the end of a ++* SPI transfer sequence ++* ++* DESCRIPTION: ++* DeAssert the chip select pin ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++********************************************************************************/ ++MV_VOID mvSpiCsDeassert(MV_VOID) ++{ ++ MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); ++ ++ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ ++ mvMPPConfigToDefault(); ++} ++ ++/******************************************************************************* ++* mvSpiRead - Read a buffer over the SPI interface ++* ++* DESCRIPTION: ++* Receive (read) a buffer over the SPI interface in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. Chip select is not ++* handled at this level. ++* ++* INPUT: ++* pRxBuff: Pointer to the buffer to hold the received data ++* buffSize: length of the pRxBuff ++* ++* OUTPUT: ++* pRxBuff: Pointer to the buffer with the received data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 bytesLeft = buffSize; ++ MV_U16* rxPtr = (MV_U16*)pRxBuff; ++ ++ /* check for null parameters */ ++ if (pRxBuff == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check that the buffer pointer and the buffer size are 16bit aligned */ ++ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) ++ { ++ /* Verify that the SPI mode is in 16bit mode */ ++ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX as long we have complete 16bit chunks */ ++ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi16bitDataTxRx(MV_SPI_DUMMY_WRITE_16BITS, rxPtr)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ rxPtr++; ++ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; ++ } ++ ++ } ++ else ++ { ++ /* Verify that the SPI mode is in 8bit mode */ ++ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX in 8bit chanks */ ++ while (bytesLeft > 0) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi8bitDataTxRx(MV_SPI_DUMMY_WRITE_8BITS, pRxBuff)) != MV_OK) ++ return ret; ++ /* increment the pointers */ ++ pRxBuff++; ++ bytesLeft--; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSpiWrite - Transmit a buffer over the SPI interface ++* ++* DESCRIPTION: ++* Transmit a buffer over the SPI interface in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. No chip select ++* action is taken. ++* ++* INPUT: ++* pTxBuff: Pointer to the buffer holding the TX data ++* buffSize: length of the pTxBuff ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiWrite(MV_U8* pTxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 bytesLeft = buffSize; ++ MV_U16* txPtr = (MV_U16*)pTxBuff; ++ ++ /* check for null parameters */ ++ if (pTxBuff == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check that the buffer pointer and the buffer size are 16bit aligned */ ++ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0)) ++ { ++ /* Verify that the SPI mode is in 16bit mode */ ++ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX as long we have complete 16bit chunks */ ++ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi16bitDataTxRx(*txPtr, NULL)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ txPtr++; ++ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; ++ } ++ } ++ else ++ { ++ ++ /* Verify that the SPI mode is in 8bit mode */ ++ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX in 8bit chanks */ ++ while (bytesLeft > 0) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi8bitDataTxRx(*pTxBuff, NULL)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ pTxBuff++; ++ bytesLeft--; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvSpiReadWrite - Read and Write a buffer simultanuosely ++* ++* DESCRIPTION: ++* Transmit and receive a buffer over the SPI in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. The SPI chip ++* select is not handled implicitely. ++* ++* INPUT: ++* pRxBuff: Pointer to the buffer to write the RX info in ++* pTxBuff: Pointer to the buffer holding the TX info ++* buffSize: length of both the pTxBuff and pRxBuff ++* ++* OUTPUT: ++* pRxBuff: Pointer of the buffer holding the RX data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiReadWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 bytesLeft = buffSize; ++ MV_U16* txPtr = (MV_U16*)pTxBuff; ++ MV_U16* rxPtr = (MV_U16*)pRxBuff; ++ ++ /* check for null parameters */ ++ if ((pRxBuff == NULL) || (pTxBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check that the buffer pointer and the buffer size are 16bit aligned */ ++ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) ++ { ++ /* Verify that the SPI mode is in 16bit mode */ ++ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX as long we have complete 16bit chunks */ ++ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi16bitDataTxRx(*txPtr, rxPtr)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ txPtr++; ++ rxPtr++; ++ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; ++ } ++ } ++ else ++ { ++ /* Verify that the SPI mode is in 8bit mode */ ++ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX in 8bit chanks */ ++ while (bytesLeft > 0) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ( (ret = mvSpi8bitDataTxRx(*pTxBuff, pRxBuff) ) != MV_OK) ++ return ret; ++ pRxBuff++; ++ pTxBuff++; ++ bytesLeft--; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,94 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSpihH ++#define __INCmvSpihH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++/* Function Prototypes */ ++/* Init */ ++MV_STATUS mvSpiInit (MV_U32 serialBaudRate); ++ ++/* Set the Frequency of the Spi clock */ ++MV_STATUS mvSpiBaudRateSet(MV_U32 serialBaudRate); ++ ++/* Assert the SPI chip select */ ++MV_VOID mvSpiCsAssert (MV_VOID); ++ ++/* De-assert the SPI chip select */ ++MV_VOID mvSpiCsDeassert (MV_VOID); ++ ++/* Simultanuous Read and write */ ++MV_STATUS mvSpiReadWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); ++ ++/* serialize a buffer on the TX line - Rx is ignored */ ++MV_STATUS mvSpiWrite (MV_U8* pTxBuff, MV_U32 buffSize); ++ ++/* read from the RX line by writing dummy values to the TX line */ ++MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize); ++ ++#endif /* __INCmvSpihH */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,249 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "spi/mvSpi.h" ++#include "spi/mvSpiSpec.h" ++ ++/*#define MV_DEBUG*/ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++ ++/******************************************************************************* ++* mvSpiReadAndWrite - Read and Write a buffer simultanuousely ++* ++* DESCRIPTION: ++* Transmit and receive a buffer over the SPI in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. ++* ++* INPUT: ++* pRxBuff: Pointer to the buffer to write the RX info in ++* pTxBuff: Pointer to the buffer holding the TX info ++* buffSize: length of both the pTxBuff and pRxBuff ++* ++* OUTPUT: ++* pRxBuff: Pointer of the buffer holding the RX data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiReadAndWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ ++ /* check for null parameters */ ++ if ((pRxBuff == NULL) || (pTxBuff == NULL) || (buffSize == 0)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* First assert the chip select */ ++ mvSpiCsAssert(); ++ ++ ret = mvSpiReadWrite(pRxBuff, pTxBuff, buffSize); ++ ++ /* Finally deassert the chip select */ ++ mvSpiCsDeassert(); ++ ++ return ret; ++} ++ ++/******************************************************************************* ++* mvSpiWriteThenWrite - Serialize a command followed by the data over the TX line ++* ++* DESCRIPTION: ++* Assert the chip select line. Transmit the command buffer followed by ++* the data buffer. Then deassert the CS line. ++* ++* INPUT: ++* pCmndBuff: Pointer to the command buffer to transmit ++* cmndSize: length of the command size ++* pTxDataBuff: Pointer to the data buffer to transmit ++* txDataSize: length of the data buffer ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, ++ MV_U32 txDataSize) ++{ ++ MV_STATUS ret = MV_OK, tempRet; ++ ++ /* check for null parameters */ ++#ifndef CONFIG_MARVELL ++ if(NULL == pTxDataBuff) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++#endif ++ ++ if (pCmndBuff == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* First assert the chip select */ ++ mvSpiCsAssert(); ++ ++ /* first write the command */ ++ if ((cmndSize) && (pCmndBuff != NULL)) ++ { ++ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Then write the data buffer */ ++#ifndef CONFIG_MARVELL ++ if (txDataSize) ++#else ++ if ((txDataSize) && (pTxDataBuff != NULL)) ++#endif ++ { ++ if ((tempRet = mvSpiWrite(pTxDataBuff, txDataSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Finally deassert the chip select */ ++ mvSpiCsDeassert(); ++ ++ return ret; ++} ++ ++/******************************************************************************* ++* mvSpiWriteThenRead - Serialize a command then read a data buffer ++* ++* DESCRIPTION: ++* Assert the chip select line. Transmit the command buffer then read ++* the data buffer. Then deassert the CS line. ++* ++* INPUT: ++* pCmndBuff: Pointer to the command buffer to transmit ++* cmndSize: length of the command size ++* pRxDataBuff: Pointer to the buffer to read the data in ++* txDataSize: length of the data buffer ++* ++* OUTPUT: ++* pRxDataBuff: Pointer to the buffer holding the data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, ++ MV_U32 rxDataSize,MV_U32 dummyBytesToRead) ++{ ++ MV_STATUS ret = MV_OK, tempRet; ++ MV_U8 dummyByte; ++ ++ /* check for null parameters */ ++ if ((pCmndBuff == NULL) && (pRxDataBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* First assert the chip select */ ++ mvSpiCsAssert(); ++ ++ /* first write the command */ ++ if ((cmndSize) && (pCmndBuff != NULL)) ++ { ++ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Read dummy bytes before real data. */ ++ while(dummyBytesToRead) ++ { ++ mvSpiRead(&dummyByte,1); ++ dummyBytesToRead--; ++ } ++ ++ /* Then write the data buffer */ ++ if ((rxDataSize) && (pRxDataBuff != NULL)) ++ { ++ if ((tempRet = mvSpiRead(pRxDataBuff, rxDataSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Finally deassert the chip select */ ++ mvSpiCsDeassert(); ++ ++ return ret; ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,82 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSpiCmndhH ++#define __INCmvSpiCmndhH ++ ++#include "mvTypes.h" ++ ++/* Function Prototypes */ ++ ++/* Simultanuous Read and write */ ++MV_STATUS mvSpiReadAndWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); ++ ++/* write command - write a command and then write data */ ++MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, MV_U32 txDataSize); ++ ++/* read command - write a command and then read data by writing dummy data */ ++MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, ++ MV_U32 rxDataSize,MV_U32 dummyBytesToRead); ++ ++#endif /* __INCmvSpiCmndhH */ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,98 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSpiSpecH ++#define __INCmvSpiSpecH ++ ++/* Constants */ ++#define MV_SPI_WAIT_RDY_MAX_LOOP 100000 ++#define MV_SPI_16_BIT_CHUNK_SIZE 2 ++#define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF ++#define MV_SPI_DUMMY_WRITE_8BITS 0xFF ++ ++/* Marvell Flash Device Controller Registers */ ++#define MV_SPI_CTRLR_OFST 0x10600 ++#define MV_SPI_IF_CTRL_REG (MV_SPI_CTRLR_OFST + 0x00) ++#define MV_SPI_IF_CONFIG_REG (MV_SPI_CTRLR_OFST + 0x04) ++#define MV_SPI_DATA_OUT_REG (MV_SPI_CTRLR_OFST + 0x08) ++#define MV_SPI_DATA_IN_REG (MV_SPI_CTRLR_OFST + 0x0c) ++#define MV_SPI_INT_CAUSE_REG (MV_SPI_CTRLR_OFST + 0x10) ++#define MV_SPI_INT_CAUSE_MASK_REG (MV_SPI_CTRLR_OFST + 0x14) ++ ++/* Serial Memory Interface Control Register Masks */ ++#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */ ++#define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */ ++#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET) ++#define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET) ++ ++/* Serial Memory Interface Configuration Register Masks */ ++#define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */ ++#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */ ++#define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */ ++#define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET) ++#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET) ++#define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET) ++ ++#endif /* __INCmvSpiSpecH */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,1023 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "mvTwsi.h" ++#include "mvTwsiSpec.h" ++#include "cpu/mvCpu.h" ++ ++ ++/*#define MV_DEBUG*/ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++static MV_VOID twsiIntFlgClr(MV_U8 chanNum); ++static MV_BOOL twsiMainIntGet(MV_U8 chanNum); ++static MV_VOID twsiAckBitSet(MV_U8 chanNum); ++static MV_U32 twsiStsGet(MV_U8 chanNum); ++static MV_VOID twsiReset(MV_U8 chanNum); ++static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); ++static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); ++static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); ++static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); ++static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset,MV_BOOL moreThen256); ++ ++ ++static MV_BOOL twsiTimeoutChk(MV_U32 timeout, const MV_8 *pString) ++{ ++ if(timeout >= TWSI_TIMEOUT_VALUE) ++ { ++ DB(mvOsPrintf("%s",pString)); ++ return MV_TRUE; ++ } ++ return MV_FALSE; ++ ++} ++/******************************************************************************* ++* mvTwsiStartBitSet - Set start bit on the bus ++* ++* DESCRIPTION: ++* This routine sets the start bit on the TWSI bus. ++* The routine first checks for interrupt flag condition, then it sets ++* the start bit in the TWSI Control register. ++* If the interrupt flag condition check previously was set, the function ++* will clear it. ++* The function then wait for the start bit to be cleared by the HW. ++* Then it waits for the interrupt flag to be set and eventually, the ++* TWSI status is checked to be 0x8 or 0x10(repeated start bit). ++* ++* INPUT: ++* chanNum - TWSI channel. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK is start bit was set successfuly on the bus. ++* MV_FAIL if interrupt flag was set before setting start bit. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum) ++{ ++ MV_BOOL isIntFlag = MV_FALSE; ++ MV_U32 timeout, temp; ++ ++ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet \n")); ++ /* check Int flag */ ++ if(twsiMainIntGet(chanNum)) ++ isIntFlag = MV_TRUE; ++ /* set start Bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT); ++ ++ /* in case that the int flag was set before i.e. repeated start bit */ ++ if(isIntFlag){ ++ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet repeated start Bit\n")); ++ twsiIntFlgClr(chanNum); ++ } ++ ++ /* wait for interrupt */ ++ timeout = 0; ++ while(!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n")) ++ return MV_TIMEOUT; ++ ++ ++ /* check that start bit went down */ ++ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0) ++ { ++ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - start bit didn't went down\n"); ++ return MV_FAIL; ++ } ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if(( temp != TWSI_START_CON_TRA ) && ( temp != TWSI_REPEATED_START_CON_TRA )) ++ { ++ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - status %x after Set Start Bit. \n",temp); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvTwsiStopBitSet - Set stop bit on the bus ++* ++* DESCRIPTION: ++* This routine set the stop bit on the TWSI bus. ++* The function then wait for the stop bit to be cleared by the HW. ++* Finally the function checks for status of 0xF8. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE is stop bit was set successfuly on the bus. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum) ++{ ++ MV_U32 timeout, temp; ++ ++ /* Generate stop bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_STOP_BIT); ++ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for stop bit to come down */ ++ timeout = 0; ++ while( ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStopBitSet ERROR - Stop bit TimeOut .\n")) ++ return MV_TIMEOUT; ++ ++ /* check that the stop bit went down */ ++ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) ++ { ++ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - stop bit didn't went down. \n"); ++ return MV_FAIL; ++ } ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if( temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0){ ++ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - status %x after Stop Bit. \n", temp); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiMainIntGet - Get twsi bit from main Interrupt cause. ++* ++* DESCRIPTION: ++* This routine returns the twsi interrupt flag value. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE is interrupt flag is set, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL twsiMainIntGet(MV_U8 chanNum) ++{ ++ MV_U32 temp; ++ ++ /* get the int flag bit */ ++ ++ temp = MV_REG_READ(TWSI_CPU_MAIN_INT_CAUSE_REG); ++ if (temp & (TWSI0_CPU_MAIN_INT_BIT << chanNum)) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++/******************************************************************************* ++* twsiIntFlgClr - Clear Interrupt flag. ++* ++* DESCRIPTION: ++* This routine clears the interrupt flag. It does NOT poll the interrupt ++* to make sure the clear. After clearing the interrupt, it waits for at ++* least 1 miliseconds. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID twsiIntFlgClr(MV_U8 chanNum) ++{ ++ MV_U32 temp; ++ ++ /* wait for 1 mili to prevent TWSI register write after write problems */ ++ mvOsDelay(1); ++ /* clear the int flag bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET)); ++ ++ /* wait for 1 mili sec for the clear to take effect */ ++ mvOsDelay(1); ++ ++ return; ++} ++ ++ ++/******************************************************************************* ++* twsiAckBitSet - Set acknowledge bit on the bus ++* ++* DESCRIPTION: ++* This routine set the acknowledge bit on the TWSI bus. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID twsiAckBitSet(MV_U8 chanNum) ++{ ++ MV_U32 temp; ++ ++ /*Set the Ack bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK); ++ ++ /* Add delay of 1ms */ ++ mvOsDelay(1); ++ return; ++} ++ ++ ++/******************************************************************************* ++* twsiInit - Initialize TWSI interface ++* ++* DESCRIPTION: ++* This routine: ++* -Reset the TWSI. ++* -Initialize the TWSI clock baud rate according to given frequancy ++* parameter based on Tclk frequancy and enables TWSI slave. ++* -Set the ack bit. ++* -Assign the TWSI slave address according to the TWSI address Type. ++* ++* ++* INPUT: ++* chanNum - TWSI channel ++* frequancy - TWSI frequancy in KHz. (up to 100KHZ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Actual frequancy. ++* ++*******************************************************************************/ ++MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable) ++{ ++ MV_U32 n,m,freq,margin,minMargin = 0xffffffff; ++ MV_U32 power; ++ MV_U32 actualFreq = 0,actualN = 0,actualM = 0,val; ++ ++ if(frequancy > 100000) ++ { ++ mvOsPrintf("Warning TWSI frequancy is too high, please use up tp 100Khz. \n"); ++ } ++ ++ DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n",Tclk,frequancy)); ++ /* Calucalte N and M for the TWSI clock baud rate */ ++ for(n = 0 ; n < 8 ; n++) ++ { ++ for(m = 0 ; m < 16 ; m++) ++ { ++ power = 2 << n; /* power = 2^(n+1) */ ++ freq = Tclk/(10*(m+1)*power); ++ margin = MV_ABS(frequancy - freq); ++ if(margin < minMargin) ++ { ++ minMargin = margin; ++ actualFreq = freq; ++ actualN = n; ++ actualM = m; ++ } ++ } ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiInit - actN %d actM %d actFreq %d\n",actualN , actualM, actualFreq)); ++ /* Reset the TWSI logic */ ++ twsiReset(chanNum); ++ ++ /* Set the baud rate */ ++ val = ((actualM<< TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS); ++ MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum),val); ++ ++ /* Enable the TWSI and slave */ ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK); ++ ++ /* set the TWSI slave address */ ++ if( pTwsiAddr->type == ADDR10_BIT )/* 10 Bit deviceAddress */ ++ { ++ /* writing the 2 most significant bits of the 10 bit address*/ ++ val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS ); ++ /* bits 7:3 must be 0x11110 */ ++ val |= TWSI_SLAVE_ADDR_10BIT_CONST; ++ /* set GCE bit */ ++ if(generalCallEnable) ++ val |= TWSI_SLAVE_ADDR_GCE_ENA; ++ /* write slave address */ ++ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum),val); ++ ++ /* writing the 8 least significant bits of the 10 bit address*/ ++ val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK; ++ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val); ++ } ++ else /*7 bit address*/ ++ { ++ /* set the 7 Bits address */ ++ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum),0x0); ++ val = (pTwsiAddr->address << TWSI_SLAVE_ADDR_7BIT_OFFS) & TWSI_SLAVE_ADDR_7BIT_MASK; ++ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val); ++ } ++ ++ /* unmask twsi int */ ++ val = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), val | TWSI_CONTROL_INT_ENA); ++ /* Add delay of 1ms */ ++ mvOsDelay(1); ++ ++ return actualFreq; ++} ++ ++ ++/******************************************************************************* ++* twsiStsGet - Get the TWSI status value. ++* ++* DESCRIPTION: ++* This routine returns the TWSI status value. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 - the TWSI status. ++* ++*******************************************************************************/ ++static MV_U32 twsiStsGet(MV_U8 chanNum) ++{ ++ return MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum)); ++ ++} ++ ++/******************************************************************************* ++* twsiReset - Reset the TWSI. ++* ++* DESCRIPTION: ++* Resets the TWSI logic and sets all TWSI registers to their reset values. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None ++* ++*******************************************************************************/ ++static MV_VOID twsiReset(MV_U8 chanNum) ++{ ++ /* Reset the TWSI logic */ ++ MV_REG_WRITE(TWSI_SOFT_RESET_REG(chanNum),0); ++ ++ /* wait for 2 mili sec */ ++ mvOsDelay(2); ++ ++ return; ++} ++ ++ ++ ++ ++/******************************* POLICY ****************************************/ ++ ++ ++ ++/******************************************************************************* ++* mvTwsiAddrSet - Set address on TWSI bus. ++* ++* DESCRIPTION: ++* This function Set address (7 or 10 Bit address) on the Twsi Bus. ++* ++* INPUT: ++* chanNum - TWSI channel ++* pTwsiAddr - twsi address. ++* command - read / write . ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the address completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *pTwsiAddr, MV_TWSI_CMD command) ++{ ++ DB(mvOsPrintf("TWSI: mvTwsiAddr7BitSet addr %x , type %d, cmd is %s\n",pTwsiAddr->address,\ ++ pTwsiAddr->type, ((command==MV_TWSI_WRITE)?"Write":"Read") )); ++ /* 10 Bit address */ ++ if(pTwsiAddr->type == ADDR10_BIT) ++ { ++ return twsiAddr10BitSet(chanNum, pTwsiAddr->address,command); ++ } ++ /* 7 Bit address */ ++ else ++ { ++ return twsiAddr7BitSet(chanNum, pTwsiAddr->address,command); ++ } ++ ++} ++ ++/******************************************************************************* ++* twsiAddr10BitSet - Set 10 Bit address on TWSI bus. ++* ++* DESCRIPTION: ++* There are two address phases: ++* 1) Write '11110' to data register bits [7:3] and 10-bit address MSB ++* (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1) bit ++* to the Data register. Then it clears interrupt flag which drive ++* the address on the TWSI bus. The function then waits for interrupt ++* flag to be active and status 0x18 (write) or 0x40 (read) to be set. ++* 2) write the rest of 10-bit address to data register and clears ++* interrupt flag which drive the address on the TWSI bus. The ++* function then waits for interrupt flag to be active and status ++* 0xD0 (write) or 0xE0 (read) to be set. ++* ++* INPUT: ++* chanNum - TWSI channel ++* deviceAddress - twsi address. ++* command - read / write . ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the address completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) ++{ ++ MV_U32 val,timeout; ++ ++ /* writing the 2 most significant bits of the 10 bit address*/ ++ val = ((deviceAddress & TWSI_DATA_ADDR_10BIT_MASK) >> TWSI_DATA_ADDR_10BIT_OFFS ); ++ /* bits 7:3 must be 0x11110 */ ++ val |= TWSI_DATA_ADDR_10BIT_CONST; ++ /* set command */ ++ val |= command; ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); ++ /* WA add a delay */ ++ mvOsDelay(1); ++ ++ /* clear Int flag */ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 1st addr (10Bit) Int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ val = twsiStsGet(chanNum); ++ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || ++ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) ++ { ++ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 1st addr (10 Bit) in %s mode.\n"\ ++ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); ++ return MV_FAIL; ++ } ++ ++ /* set 8 LSB of the address */ ++ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); ++ ++ /* clear Int flag */ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 2nd (10 Bit) Int TimOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ val = twsiStsGet(chanNum); ++ if(( (val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || ++ ( (val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) ++ { ++ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 2nd addr(10 Bit) in %s mode.\n"\ ++ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiAddr7BitSet - Set 7 Bit address on TWSI bus. ++* ++* DESCRIPTION: ++* This function writes 7 bit address plus a write or read bit to the ++* Data register. Then it clears interrupt flag which drive the address on ++* the TWSI bus. The function then waits for interrupt flag to be active ++* and status 0x18 (write) or 0x40 (read) to be set. ++* ++* INPUT: ++* chanNum - TWSI channel ++* deviceAddress - twsi address. ++* command - read / write . ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the address completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) ++{ ++ MV_U32 val,timeout; ++ ++ /* set the address */ ++ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; ++ /* set command */ ++ val |= command; ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); ++ /* WA add a delay */ ++ mvOsDelay(1); ++ ++ /* clear Int flag */ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr7BitSet ERROR - Addr (7 Bit) int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ val = twsiStsGet(chanNum); ++ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || ++ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) ++ { ++ /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't ++ want error messeges in case DIMM doesn't exist. */ ++ DB(mvOsPrintf("TWSI: twsiAddr7BitSet ERROR - status %x addr (7 Bit) in %s mode.\n"\ ++ ,val,((command==MV_TWSI_WRITE)?"Write":"Read") )); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiDataWrite - Trnasmit a data block over TWSI bus. ++* ++* DESCRIPTION: ++* This function writes a given data block to TWSI bus in 8 bit granularity. ++* first The function waits for interrupt flag to be active then ++* For each 8-bit data: ++* The function writes data to data register. It then clears ++* interrupt flag which drives the data on the TWSI bus. ++* The function then waits for interrupt flag to be active and status ++* 0x28 to be set. ++* ++* ++* INPUT: ++* chanNum - TWSI channel ++* pBlock - Data block. ++* blockSize - number of chars in pBlock. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if transmiting the block completed succesfully, ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ MV_U32 timeout, temp, blockSizeWr = blockSize; ++ ++ if(NULL == pBlock) ++ return MV_BAD_PARAM; ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ while(blockSizeWr) ++ { ++ /* write the data*/ ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum),(MV_U32)*pBlock); ++ DB(mvOsPrintf("TWSI: twsiDataTransmit place = %d write %x \n",\ ++ blockSize - blockSizeWr, *pBlock)); ++ pBlock++; ++ blockSizeWr--; ++ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if(temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC) ++ { ++ mvOsPrintf("TWSI: twsiDataTransmit ERROR - status %x in write trans\n",temp); ++ return MV_FAIL; ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiDataReceive - Receive data block from TWSI bus. ++* ++* DESCRIPTION: ++* This function receive data block from TWSI bus in 8bit granularity ++* into pBlock buffer. ++* first The function waits for interrupt flag to be active then ++* For each 8-bit data: ++* It clears the interrupt flag which allows the next data to be ++* received from TWSI bus. ++* The function waits for interrupt flag to be active, ++* and status reg is 0x50. ++* Then the function reads data from data register, and copies it to ++* the given buffer. ++* ++* INPUT: ++* chanNum - TWSI channel ++* blockSize - number of bytes to read. ++* ++* OUTPUT: ++* pBlock - Data block. ++* ++* RETURN: ++* MV_OK - if receive transaction completed succesfully, ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ MV_U32 timeout, temp, blockSizeRd = blockSize; ++ if(NULL == pBlock) ++ return MV_BAD_PARAM; ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data int Time out .\n")) ++ return MV_TIMEOUT; ++ ++ while(blockSizeRd) ++ { ++ if(blockSizeRd == 1) ++ { ++ /* clear ack and Int flag */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ temp &= ~(TWSI_CONTROL_ACK); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp); ++ } ++ twsiIntFlgClr(chanNum); ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( (!twsiMainIntGet(chanNum)) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data Int Time out .\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if((temp != TWSI_M_REC_RD_DATA_ACK_TRA) && (blockSizeRd !=1)) ++ { ++ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in read trans \n",temp); ++ return MV_FAIL; ++ } ++ else if((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) && (blockSizeRd ==1)) ++ { ++ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in Rd Terminate\n",temp); ++ return MV_FAIL; ++ } ++ ++ /* read the data*/ ++ *pBlock = (MV_U8)MV_REG_READ(TWSI_DATA_REG(chanNum)); ++ DB(mvOsPrintf("TWSI: twsiDataReceive place %d read %x \n",\ ++ blockSize - blockSizeRd,*pBlock)); ++ pBlock++; ++ blockSizeRd--; ++ } ++ ++ return MV_OK; ++} ++ ++ ++ ++/******************************************************************************* ++* twsiTargetOffsSet - Set TWST target offset on TWSI bus. ++* ++* DESCRIPTION: ++* The function support TWSI targets that have inside address space (for ++* example EEPROMs). The function: ++* 1) Convert the given offset into pBlock and size. ++* in case the offset should be set to a TWSI slave which support ++* more then 256 bytes offset, the offset setting will be done ++* in 2 transactions. ++* 2) Use twsiDataTransmit to place those on the bus. ++* ++* INPUT: ++* chanNum - TWSI channel ++* offset - offset to be set on the EEPROM device. ++* moreThen256 - whether the EEPROM device support more then 256 byte offset. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the offset completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset, MV_BOOL moreThen256) ++{ ++ MV_U8 offBlock[2]; ++ MV_U32 offSize; ++ ++ if(moreThen256 == MV_TRUE) ++ { ++ offBlock[0] = (offset >> 8) & 0xff; ++ offBlock[1] = offset & 0xff; ++ offSize = 2; ++ } ++ else ++ { ++ offBlock[0] = offset & 0xff; ++ offSize = 1; ++ } ++ DB(mvOsPrintf("TWSI: twsiTargetOffsSet offSize = %x addr1 = %x addr2 = %x\n",\ ++ offSize,offBlock[0],offBlock[1])); ++ return twsiDataTransmit(chanNum, offBlock, offSize); ++ ++} ++ ++/******************************************************************************* ++* mvTwsiRead - Read data block from a TWSI Slave. ++* ++* DESCRIPTION: ++* The function calls the following functions: ++* -) mvTwsiStartBitSet(); ++* if(EEPROM device) ++* -) mvTwsiAddrSet(w); ++* -) twsiTargetOffsSet(); ++* -) mvTwsiStartBitSet(); ++* -) mvTwsiAddrSet(r); ++* -) twsiDataReceive(); ++* -) mvTwsiStopBitSet(); ++* ++* INPUT: ++* chanNum - TWSI channel ++* pTwsiSlave - Twsi Slave structure. ++* blockSize - number of bytes to read. ++* ++* OUTPUT: ++* pBlock - Data block. ++* ++* RETURN: ++* MV_OK - if EEPROM read transaction completed succesfully, ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiRead(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ if((NULL == pBlock) || (NULL == pTwsiSlave)) ++ return MV_BAD_PARAM; ++ if(MV_OK != mvTwsiStartBitSet(chanNum)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); ++ ++ /* in case offset exsist (i.e. eeprom ) */ ++ if(MV_TRUE == pTwsiSlave->validOffset) ++ { ++ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); ++ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiTargetOffsSet\n")); ++ if(MV_OK != mvTwsiStartBitSet(chanNum)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); ++ } ++ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_READ)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); ++ if(MV_OK != twsiDataReceive(chanNum, pBlock, blockSize)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiDataReceive\n")); ++ ++ if(MV_OK != mvTwsiStopBitSet(chanNum)) ++ { ++ return MV_FAIL; ++ } ++ ++ twsiAckBitSet(chanNum); ++ ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStopBitSet\n")); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTwsiWrite - Write data block to a TWSI Slave. ++* ++* DESCRIPTION: ++* The function calls the following functions: ++* -) mvTwsiStartBitSet(); ++* -) mvTwsiAddrSet(); ++* -)if(EEPROM device) ++* -) twsiTargetOffsSet(); ++* -) twsiDataTransmit(); ++* -) mvTwsiStopBitSet(); ++* ++* INPUT: ++* chanNum - TWSI channel ++* eepromAddress - eeprom address. ++* blockSize - number of bytes to write. ++* pBlock - Data block. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_OK - if EEPROM read transaction completed succesfully. ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++* NOTE: Part of the EEPROM, required that the offset will be aligned to the ++* max write burst supported. ++*******************************************************************************/ ++MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ if((NULL == pBlock) || (NULL == pTwsiSlave)) ++ return MV_BAD_PARAM; ++ ++ if(MV_OK != mvTwsiStartBitSet(chanNum)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStartBitSet\n")); ++ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI :mvTwsiEepromWrite after mvTwsiAddrSet\n")); ++ ++ /* in case offset exsist (i.e. eeprom ) */ ++ if(MV_TRUE == pTwsiSlave->validOffset) ++ { ++ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiTargetOffsSet\n")); ++ } ++ if(MV_OK != twsiDataTransmit(chanNum, pBlock, blockSize)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiDataTransmit\n")); ++ if(MV_OK != mvTwsiStopBitSet(chanNum)) ++ { ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStopBitSet\n")); ++ ++ return MV_OK; ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,121 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCmvTwsiH ++#define __INCmvTwsiH ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* need to update this includes */ ++#include "twsi/mvTwsiSpec.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++ ++/* The TWSI interface supports both 7-bit and 10-bit addressing. */ ++/* This enumerator describes addressing type. */ ++typedef enum _mvTwsiAddrType ++{ ++ ADDR7_BIT, /* 7 bit address */ ++ ADDR10_BIT /* 10 bit address */ ++}MV_TWSI_ADDR_TYPE; ++ ++/* This structure describes TWSI address. */ ++typedef struct _mvTwsiAddr ++{ ++ MV_U32 address; /* address */ ++ MV_TWSI_ADDR_TYPE type; /* Address type */ ++}MV_TWSI_ADDR; ++ ++/* This structure describes a TWSI slave. */ ++typedef struct _mvTwsiSlave ++{ ++ MV_TWSI_ADDR slaveAddr; ++ MV_BOOL validOffset; /* whether the slave has offset (i.e. Eeprom etc.) */ ++ MV_U32 offset; /* offset in the slave. */ ++ MV_BOOL moreThen256; /* whether the ofset is bigger then 256 */ ++}MV_TWSI_SLAVE; ++ ++/* This enumerator describes TWSI protocol commands. */ ++typedef enum _mvTwsiCmd ++{ ++ MV_TWSI_WRITE, /* TWSI write command - 0 according to spec */ ++ MV_TWSI_READ /* TWSI read command - 1 according to spec */ ++}MV_TWSI_CMD; ++ ++MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum); ++MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum); ++MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *twsiAddr, MV_TWSI_CMD command); ++ ++MV_U32 mvTwsiInit(MV_U8 chanNum, MV_KHZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *twsiAddr, MV_BOOL generalCallEnable); ++MV_STATUS mvTwsiRead (MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); ++MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); ++ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvTwsiH */ ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h +--- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,160 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++/****************************************/ ++/* TWSI Registers */ ++/****************************************/ ++#ifndef __INCmvTwsiSpech ++#define __INCmvTwsiSpech ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* defines */ ++#define TWSI_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum)+ 0x00) ++ ++#define TWSI_SLAVE_ADDR_GCE_ENA BIT0 ++#define TWSI_SLAVE_ADDR_7BIT_OFFS 0x1 ++#define TWSI_SLAVE_ADDR_7BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7BIT_OFFS) ++#define TWSI_SLAVE_ADDR_10BIT_OFFS 0x7 ++#define TWSI_SLAVE_ADDR_10BIT_MASK 0x300 ++#define TWSI_SLAVE_ADDR_10BIT_CONST 0xF0 ++ ++ ++#define TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x10) ++#define TWSI_EXTENDED_SLAVE_OFFS 0 ++#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS) ++ ++ ++#define TWSI_DATA_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x04) ++#define TWSI_DATA_COMMAND_OFFS 0x0 ++#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS) ++#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS) ++#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS) ++#define TWSI_DATA_ADDR_7BIT_OFFS 0x1 ++#define TWSI_DATA_ADDR_7BIT_MASK (0xFF << TWSI_DATA_ADDR_7BIT_OFFS) ++#define TWSI_DATA_ADDR_10BIT_OFFS 0x7 ++#define TWSI_DATA_ADDR_10BIT_MASK 0x300 ++#define TWSI_DATA_ADDR_10BIT_CONST 0xF0 ++ ++ ++#define TWSI_CONTROL_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x08) ++#define TWSI_CONTROL_ACK BIT2 ++#define TWSI_CONTROL_INT_FLAG_SET BIT3 ++#define TWSI_CONTROL_STOP_BIT BIT4 ++#define TWSI_CONTROL_START_BIT BIT5 ++#define TWSI_CONTROL_ENA BIT6 ++#define TWSI_CONTROL_INT_ENA BIT7 ++ ++ ++#define TWSI_STATUS_BAUDE_RATE_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x0c) ++#define TWSI_BAUD_RATE_N_OFFS 0 ++#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS) ++#define TWSI_BAUD_RATE_M_OFFS 3 ++#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS) ++ ++#define TWSI_SOFT_RESET_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x1c) ++ ++/* defines */ ++#define TWSI_TIMEOUT_VALUE 0x500 ++ ++/* TWSI status codes */ ++#define TWSI_BUS_ERROR 0x00 ++#define TWSI_START_CON_TRA 0x08 ++#define TWSI_REPEATED_START_CON_TRA 0x10 ++#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18 ++#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20 ++#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28 ++#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30 ++#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38 ++#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40 ++#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48 ++#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50 ++#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58 ++#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60 ++#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68 ++#define TWSI_GNL_CALL_REC_ACK_TRA 0x70 ++#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98 ++#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0 ++#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8 ++#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0 ++#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8 ++#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0 ++#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8 ++#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0 ++#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8 ++#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0 ++#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8 ++#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8 ++ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvTwsiSpech */ +diff -Nur linux-2.6.39.orig/crypto/ocf/ocf-bench.c linux-2.6.39/crypto/ocf/ocf-bench.c +--- linux-2.6.39.orig/crypto/ocf/ocf-bench.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/ocf-bench.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,436 @@ ++/* ++ * A loadable module that benchmarks the OCF crypto speed from kernel space. ++ * ++ * Copyright (C) 2004-2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef I_HAVE_AN_XSCALE_WITH_INTEL_SDK ++#define BENCH_IXP_ACCESS_LIB 1 ++#endif ++#ifdef BENCH_IXP_ACCESS_LIB ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++/* ++ * support for access lib version 1.4 ++ */ ++#ifndef IX_MBUF_PRIV ++#define IX_MBUF_PRIV(x) ((x)->priv) ++#endif ++ ++/* ++ * the number of simultaneously active requests ++ */ ++static int request_q_len = 20; ++module_param(request_q_len, int, 0); ++MODULE_PARM_DESC(request_q_len, "Number of outstanding requests"); ++/* ++ * how many requests we want to have processed ++ */ ++static int request_num = 1024; ++module_param(request_num, int, 0); ++MODULE_PARM_DESC(request_num, "run for at least this many requests"); ++/* ++ * the size of each request ++ */ ++static int request_size = 1500; ++module_param(request_size, int, 0); ++MODULE_PARM_DESC(request_size, "size of each request"); ++ ++/* ++ * a structure for each request ++ */ ++typedef struct { ++ struct work_struct work; ++#ifdef BENCH_IXP_ACCESS_LIB ++ IX_MBUF mbuf; ++#endif ++ unsigned char *buffer; ++} request_t; ++ ++static request_t *requests; ++ ++static int outstanding; ++static int total; ++ ++/*************************************************************************/ ++/* ++ * OCF benchmark routines ++ */ ++ ++static uint64_t ocf_cryptoid; ++static int ocf_init(void); ++static int ocf_cb(struct cryptop *crp); ++static void ocf_request(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ocf_request_wq(struct work_struct *work); ++#endif ++ ++static int ++ocf_init(void) ++{ ++ int error; ++ struct cryptoini crie, cria; ++ struct cryptodesc crda, crde; ++ ++ memset(&crie, 0, sizeof(crie)); ++ memset(&cria, 0, sizeof(cria)); ++ memset(&crde, 0, sizeof(crde)); ++ memset(&crda, 0, sizeof(crda)); ++ ++ cria.cri_alg = CRYPTO_SHA1_HMAC; ++ cria.cri_klen = 20 * 8; ++ cria.cri_key = "0123456789abcdefghij"; ++ ++ crie.cri_alg = CRYPTO_3DES_CBC; ++ crie.cri_klen = 24 * 8; ++ crie.cri_key = "0123456789abcdefghijklmn"; ++ ++ crie.cri_next = &cria; ++ ++ error = crypto_newsession(&ocf_cryptoid, &crie, 0); ++ if (error) { ++ printk("crypto_newsession failed %d\n", error); ++ return -1; ++ } ++ return 0; ++} ++ ++static int ++ocf_cb(struct cryptop *crp) ++{ ++ request_t *r = (request_t *) crp->crp_opaque; ++ ++ if (crp->crp_etype) ++ printk("Error in OCF processing: %d\n", crp->crp_etype); ++ total++; ++ crypto_freereq(crp); ++ crp = NULL; ++ ++ if (total > request_num) { ++ outstanding--; ++ return 0; ++ } ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&r->work, ocf_request_wq); ++#else ++ INIT_WORK(&r->work, ocf_request, r); ++#endif ++ schedule_work(&r->work); ++ return 0; ++} ++ ++ ++static void ++ocf_request(void *arg) ++{ ++ request_t *r = arg; ++ struct cryptop *crp = crypto_getreq(2); ++ struct cryptodesc *crde, *crda; ++ ++ if (!crp) { ++ outstanding--; ++ return; ++ } ++ ++ crde = crp->crp_desc; ++ crda = crde->crd_next; ++ ++ crda->crd_skip = 0; ++ crda->crd_flags = 0; ++ crda->crd_len = request_size; ++ crda->crd_inject = request_size; ++ crda->crd_alg = CRYPTO_SHA1_HMAC; ++ crda->crd_key = "0123456789abcdefghij"; ++ crda->crd_klen = 20 * 8; ++ ++ crde->crd_skip = 0; ++ crde->crd_flags = CRD_F_IV_EXPLICIT | CRD_F_ENCRYPT; ++ crde->crd_len = request_size; ++ crde->crd_inject = request_size; ++ crde->crd_alg = CRYPTO_3DES_CBC; ++ crde->crd_key = "0123456789abcdefghijklmn"; ++ crde->crd_klen = 24 * 8; ++ ++ crp->crp_ilen = request_size + 64; ++ crp->crp_flags = CRYPTO_F_CBIMM; ++ crp->crp_buf = (caddr_t) r->buffer; ++ crp->crp_callback = ocf_cb; ++ crp->crp_sid = ocf_cryptoid; ++ crp->crp_opaque = (caddr_t) r; ++ crypto_dispatch(crp); ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ocf_request_wq(struct work_struct *work) ++{ ++ request_t *r = container_of(work, request_t, work); ++ ocf_request(r); ++} ++#endif ++ ++/*************************************************************************/ ++#ifdef BENCH_IXP_ACCESS_LIB ++/*************************************************************************/ ++/* ++ * CryptoAcc benchmark routines ++ */ ++ ++static IxCryptoAccCtx ixp_ctx; ++static UINT32 ixp_ctx_id; ++static IX_MBUF ixp_pri; ++static IX_MBUF ixp_sec; ++static int ixp_registered = 0; ++ ++static void ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, ++ IxCryptoAccStatus status); ++static void ixp_perform_cb(UINT32 ctx_id, IX_MBUF *sbufp, IX_MBUF *dbufp, ++ IxCryptoAccStatus status); ++static void ixp_request(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ixp_request_wq(struct work_struct *work); ++#endif ++ ++static int ++ixp_init(void) ++{ ++ IxCryptoAccStatus status; ++ ++ ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; ++ ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp_ctx.cipherCtx.cipherKeyLen = 24; ++ ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp_ctx.cipherCtx.cipherInitialVectorLen = IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp_ctx.cipherCtx.key.cipherKey, "0123456789abcdefghijklmn", 24); ++ ++ ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; ++ ixp_ctx.authCtx.authDigestLen = 12; ++ ixp_ctx.authCtx.aadLen = 0; ++ ixp_ctx.authCtx.authKeyLen = 20; ++ memcpy(ixp_ctx.authCtx.key.authKey, "0123456789abcdefghij", 20); ++ ++ ixp_ctx.useDifferentSrcAndDestMbufs = 0; ++ ixp_ctx.operation = IX_CRYPTO_ACC_OP_ENCRYPT_AUTH ; ++ ++ IX_MBUF_MLEN(&ixp_pri) = IX_MBUF_PKT_LEN(&ixp_pri) = 128; ++ IX_MBUF_MDATA(&ixp_pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ IX_MBUF_MLEN(&ixp_sec) = IX_MBUF_PKT_LEN(&ixp_sec) = 128; ++ IX_MBUF_MDATA(&ixp_sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ ++ status = ixCryptoAccCtxRegister(&ixp_ctx, &ixp_pri, &ixp_sec, ++ ixp_register_cb, ixp_perform_cb, &ixp_ctx_id); ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) { ++ while (!ixp_registered) ++ schedule(); ++ return ixp_registered < 0 ? -1 : 0; ++ } ++ ++ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); ++ return -1; ++} ++ ++static void ++ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) ++{ ++ if (bufp) { ++ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; ++ kfree(IX_MBUF_MDATA(bufp)); ++ IX_MBUF_MDATA(bufp) = NULL; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_WAIT == status) ++ return; ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ ixp_registered = 1; ++ else ++ ixp_registered = -1; ++} ++ ++static void ++ixp_perform_cb( ++ UINT32 ctx_id, ++ IX_MBUF *sbufp, ++ IX_MBUF *dbufp, ++ IxCryptoAccStatus status) ++{ ++ request_t *r = NULL; ++ ++ total++; ++ if (total > request_num) { ++ outstanding--; ++ return; ++ } ++ ++ if (!sbufp || !(r = IX_MBUF_PRIV(sbufp))) { ++ printk("crappo %p %p\n", sbufp, r); ++ outstanding--; ++ return; ++ } ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&r->work, ixp_request_wq); ++#else ++ INIT_WORK(&r->work, ixp_request, r); ++#endif ++ schedule_work(&r->work); ++} ++ ++static void ++ixp_request(void *arg) ++{ ++ request_t *r = arg; ++ IxCryptoAccStatus status; ++ ++ memset(&r->mbuf, 0, sizeof(r->mbuf)); ++ IX_MBUF_MLEN(&r->mbuf) = IX_MBUF_PKT_LEN(&r->mbuf) = request_size + 64; ++ IX_MBUF_MDATA(&r->mbuf) = r->buffer; ++ IX_MBUF_PRIV(&r->mbuf) = r; ++ status = ixCryptoAccAuthCryptPerform(ixp_ctx_id, &r->mbuf, NULL, ++ 0, request_size, 0, request_size, request_size, r->buffer); ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("status1 = %d\n", status); ++ outstanding--; ++ return; ++ } ++ return; ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_request_wq(struct work_struct *work) ++{ ++ request_t *r = container_of(work, request_t, work); ++ ixp_request(r); ++} ++#endif ++ ++/*************************************************************************/ ++#endif /* BENCH_IXP_ACCESS_LIB */ ++/*************************************************************************/ ++ ++int ++ocfbench_init(void) ++{ ++ int i, jstart, jstop; ++ ++ printk("Crypto Speed tests\n"); ++ ++ requests = kmalloc(sizeof(request_t) * request_q_len, GFP_KERNEL); ++ if (!requests) { ++ printk("malloc failed\n"); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < request_q_len; i++) { ++ /* +64 for return data */ ++ requests[i].buffer = kmalloc(request_size + 128, GFP_DMA); ++ if (!requests[i].buffer) { ++ printk("malloc failed\n"); ++ return -EINVAL; ++ } ++ memset(requests[i].buffer, '0' + i, request_size + 128); ++ } ++ ++ /* ++ * OCF benchmark ++ */ ++ printk("OCF: testing ...\n"); ++ ocf_init(); ++ total = outstanding = 0; ++ jstart = jiffies; ++ for (i = 0; i < request_q_len; i++) { ++ outstanding++; ++ ocf_request(&requests[i]); ++ } ++ while (outstanding > 0) ++ schedule(); ++ jstop = jiffies; ++ ++ printk("OCF: %d requests of %d bytes in %d jiffies\n", total, request_size, ++ jstop - jstart); ++ ++#ifdef BENCH_IXP_ACCESS_LIB ++ /* ++ * IXP benchmark ++ */ ++ printk("IXP: testing ...\n"); ++ ixp_init(); ++ total = outstanding = 0; ++ jstart = jiffies; ++ for (i = 0; i < request_q_len; i++) { ++ outstanding++; ++ ixp_request(&requests[i]); ++ } ++ while (outstanding > 0) ++ schedule(); ++ jstop = jiffies; ++ ++ printk("IXP: %d requests of %d bytes in %d jiffies\n", total, request_size, ++ jstop - jstart); ++#endif /* BENCH_IXP_ACCESS_LIB */ ++ ++ for (i = 0; i < request_q_len; i++) ++ kfree(requests[i].buffer); ++ kfree(requests); ++ return -EINVAL; /* always fail to load so it can be re-run quickly ;-) */ ++} ++ ++static void __exit ocfbench_exit(void) ++{ ++} ++ ++module_init(ocfbench_init); ++module_exit(ocfbench_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Benchmark various in-kernel crypto speeds"); +diff -Nur linux-2.6.39.orig/crypto/ocf/ocf-compat.h linux-2.6.39/crypto/ocf/ocf-compat.h +--- linux-2.6.39.orig/crypto/ocf/ocf-compat.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/ocf-compat.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,294 @@ ++#ifndef _BSD_COMPAT_H_ ++#define _BSD_COMPAT_H_ 1 ++/****************************************************************************/ ++/* ++ * Provide compat routines for older linux kernels and BSD kernels ++ * ++ * Written by David McCullough ++ * Copyright (C) 2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this file ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++/****************************************************************************/ ++#ifdef __KERNEL__ ++/* ++ * fake some BSD driver interface stuff specifically for OCF use ++ */ ++ ++typedef struct ocf_device *device_t; ++ ++typedef struct { ++ int (*cryptodev_newsession)(device_t dev, u_int32_t *sidp, struct cryptoini *cri); ++ int (*cryptodev_freesession)(device_t dev, u_int64_t tid); ++ int (*cryptodev_process)(device_t dev, struct cryptop *crp, int hint); ++ int (*cryptodev_kprocess)(device_t dev, struct cryptkop *krp, int hint); ++} device_method_t; ++#define DEVMETHOD(id, func) id: func ++ ++struct ocf_device { ++ char name[32]; /* the driver name */ ++ char nameunit[32]; /* the driver name + HW instance */ ++ int unit; ++ device_method_t methods; ++ void *softc; ++}; ++ ++#define CRYPTODEV_NEWSESSION(dev, sid, cri) \ ++ ((*(dev)->methods.cryptodev_newsession)(dev,sid,cri)) ++#define CRYPTODEV_FREESESSION(dev, sid) \ ++ ((*(dev)->methods.cryptodev_freesession)(dev, sid)) ++#define CRYPTODEV_PROCESS(dev, crp, hint) \ ++ ((*(dev)->methods.cryptodev_process)(dev, crp, hint)) ++#define CRYPTODEV_KPROCESS(dev, krp, hint) \ ++ ((*(dev)->methods.cryptodev_kprocess)(dev, krp, hint)) ++ ++#define device_get_name(dev) ((dev)->name) ++#define device_get_nameunit(dev) ((dev)->nameunit) ++#define device_get_unit(dev) ((dev)->unit) ++#define device_get_softc(dev) ((dev)->softc) ++ ++#define softc_device_decl \ ++ struct ocf_device _device; \ ++ device_t ++ ++#define softc_device_init(_sc, _name, _unit, _methods) \ ++ if (1) {\ ++ strncpy((_sc)->_device.name, _name, sizeof((_sc)->_device.name) - 1); \ ++ snprintf((_sc)->_device.nameunit, sizeof((_sc)->_device.name), "%s%d", _name, _unit); \ ++ (_sc)->_device.unit = _unit; \ ++ (_sc)->_device.methods = _methods; \ ++ (_sc)->_device.softc = (void *) _sc; \ ++ *(device_t *)((softc_get_device(_sc))+1) = &(_sc)->_device; \ ++ } else ++ ++#define softc_get_device(_sc) (&(_sc)->_device) ++ ++/* ++ * iomem support for 2.4 and 2.6 kernels ++ */ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#define ocf_iomem_t unsigned long ++ ++/* ++ * implement simple workqueue like support for older kernels ++ */ ++ ++#include ++ ++#define work_struct tq_struct ++ ++#define INIT_WORK(wp, fp, ap) \ ++ do { \ ++ (wp)->sync = 0; \ ++ (wp)->routine = (fp); \ ++ (wp)->data = (ap); \ ++ } while (0) ++ ++#define schedule_work(wp) \ ++ do { \ ++ queue_task((wp), &tq_immediate); \ ++ mark_bh(IMMEDIATE_BH); \ ++ } while (0) ++ ++#define flush_scheduled_work() run_task_queue(&tq_immediate) ++ ++#else ++#define ocf_iomem_t void __iomem * ++ ++#include ++ ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) ++#include ++#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) ++#define files_fdtable(files) (files) ++#endif ++ ++#ifdef MODULE_PARM ++#undef module_param /* just in case */ ++#define module_param(a,b,c) MODULE_PARM(a,"i") ++#endif ++ ++#define bzero(s,l) memset(s,0,l) ++#define bcopy(s,d,l) memcpy(d,s,l) ++#define bcmp(x, y, l) memcmp(x,y,l) ++ ++#define MIN(x,y) ((x) < (y) ? (x) : (y)) ++ ++#define device_printf(dev, a...) ({ \ ++ printk("%s: ", device_get_nameunit(dev)); printk(a); \ ++ }) ++ ++#undef printf ++#define printf(fmt...) printk(fmt) ++ ++#define KASSERT(c,p) if (!(c)) { printk p ; } else ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#define ocf_daemonize(str) \ ++ daemonize(); \ ++ spin_lock_irq(¤t->sigmask_lock); \ ++ sigemptyset(¤t->blocked); \ ++ recalc_sigpending(current); \ ++ spin_unlock_irq(¤t->sigmask_lock); \ ++ sprintf(current->comm, str); ++#else ++#define ocf_daemonize(str) daemonize(str); ++#endif ++ ++#define TAILQ_INSERT_TAIL(q,d,m) list_add_tail(&(d)->m, (q)) ++#define TAILQ_EMPTY(q) list_empty(q) ++#define TAILQ_FOREACH(v, q, m) list_for_each_entry(v, q, m) ++ ++#define read_random(p,l) get_random_bytes(p,l) ++ ++#define DELAY(x) ((x) > 2000 ? mdelay((x)/1000) : udelay(x)) ++#define strtoul simple_strtoul ++ ++#define pci_get_vendor(dev) ((dev)->vendor) ++#define pci_get_device(dev) ((dev)->device) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#define pci_set_consistent_dma_mask(dev, mask) (0) ++#endif ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ++#define pci_dma_sync_single_for_cpu pci_dma_sync_single ++#endif ++ ++#ifndef DMA_32BIT_MASK ++#define DMA_32BIT_MASK 0x00000000ffffffffULL ++#endif ++ ++#ifndef htole32 ++#define htole32(x) cpu_to_le32(x) ++#endif ++#ifndef htobe32 ++#define htobe32(x) cpu_to_be32(x) ++#endif ++#ifndef htole16 ++#define htole16(x) cpu_to_le16(x) ++#endif ++#ifndef htobe16 ++#define htobe16(x) cpu_to_be16(x) ++#endif ++ ++/* older kernels don't have these */ ++ ++#include ++#if !defined(IRQ_NONE) && !defined(IRQ_RETVAL) ++#define IRQ_NONE ++#define IRQ_HANDLED ++#define IRQ_WAKE_THREAD ++#define IRQ_RETVAL ++#define irqreturn_t void ++typedef irqreturn_t (*irq_handler_t)(int irq, void *arg, struct pt_regs *regs); ++#endif ++#ifndef IRQF_SHARED ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++# define strlcpy(dest,src,len) \ ++ ({strncpy(dest,src,(len)-1); ((char *)dest)[(len)-1] = '\0'; }) ++#endif ++ ++#ifndef MAX_ERRNO ++#define MAX_ERRNO 4095 ++#endif ++#ifndef IS_ERR_VALUE ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,5) ++#include ++#endif ++#ifndef IS_ERR_VALUE ++#define IS_ERR_VALUE(x) ((unsigned long)(x) >= (unsigned long)-MAX_ERRNO) ++#endif ++#endif ++ ++/* ++ * common debug for all ++ */ ++#if 1 ++#define dprintk(a...) do { if (debug) printk(a); } while(0) ++#else ++#define dprintk(a...) ++#endif ++ ++#ifndef SLAB_ATOMIC ++/* Changed in 2.6.20, must use GFP_ATOMIC now */ ++#define SLAB_ATOMIC GFP_ATOMIC ++#endif ++ ++/* ++ * need some additional support for older kernels */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,2) ++#define pci_register_driver_compat(driver, rc) \ ++ do { \ ++ if ((rc) > 0) { \ ++ (rc) = 0; \ ++ } else if (rc == 0) { \ ++ (rc) = -ENODEV; \ ++ } else { \ ++ pci_unregister_driver(driver); \ ++ } \ ++ } while (0) ++#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ++#define pci_register_driver_compat(driver,rc) ((rc) = (rc) < 0 ? (rc) : 0) ++#else ++#define pci_register_driver_compat(driver,rc) ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ++ ++#include ++#include ++ ++static inline void sg_set_page(struct scatterlist *sg, struct page *page, ++ unsigned int len, unsigned int offset) ++{ ++ sg->page = page; ++ sg->offset = offset; ++ sg->length = len; ++} ++ ++static inline void *sg_virt(struct scatterlist *sg) ++{ ++ return page_address(sg->page) + sg->offset; ++} ++ ++#define sg_init_table(sg, n) ++ ++#endif ++ ++#ifndef late_initcall ++#define late_initcall(init) module_init(init) ++#endif ++ ++#endif /* __KERNEL__ */ ++ ++/****************************************************************************/ ++#endif /* _BSD_COMPAT_H_ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/ocfnull/Makefile linux-2.6.39/crypto/ocf/ocfnull/Makefile +--- linux-2.6.39.orig/crypto/ocf/ocfnull/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/ocfnull/Makefile 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_OCFNULL) += ocfnull.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/ocfnull/ocfnull.c linux-2.6.39/crypto/ocf/ocfnull/ocfnull.c +--- linux-2.6.39.orig/crypto/ocf/ocfnull/ocfnull.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/ocfnull/ocfnull.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,203 @@ ++/* ++ * An OCF module for determining the cost of crypto versus the cost of ++ * IPSec processing outside of OCF. This modules gives us the effect of ++ * zero cost encryption, of course you will need to run it at both ends ++ * since it does no crypto at all. ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++static int32_t null_id = -1; ++static u_int32_t null_sesnum = 0; ++ ++static int null_process(device_t, struct cryptop *, int); ++static int null_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int null_freesession(device_t, u_int64_t); ++ ++#define debug ocfnull_debug ++int ocfnull_debug = 0; ++module_param(ocfnull_debug, int, 0644); ++MODULE_PARM_DESC(ocfnull_debug, "Enable debug"); ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} nulldev; ++ ++static device_method_t null_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, null_newsession), ++ DEVMETHOD(cryptodev_freesession,null_freesession), ++ DEVMETHOD(cryptodev_process, null_process), ++}; ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++null_newsession(device_t arg, u_int32_t *sid, struct cryptoini *cri) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (null_sesnum == 0) ++ null_sesnum++; ++ *sid = null_sesnum++; ++ return 0; ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++null_freesession(device_t arg, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > null_sesnum) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return 0; ++ return 0; ++} ++ ++ ++/* ++ * Process a request. ++ */ ++static int ++null_process(device_t arg, struct cryptop *crp, int hint) ++{ ++ unsigned int lid; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ /* ++ * find the session we are using ++ */ ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= null_sesnum || lid == 0) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++done: ++ crypto_done(crp); ++ return 0; ++} ++ ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++ ++static int ++null_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, null_init); ++ ++ memset(&nulldev, 0, sizeof(nulldev)); ++ softc_device_init(&nulldev, "ocfnull", 0, null_methods); ++ ++ null_id = crypto_get_driverid(softc_get_device(&nulldev), ++ CRYPTOCAP_F_HARDWARE); ++ if (null_id < 0) ++ panic("ocfnull: crypto device cannot initialize!"); ++ ++#define REGISTER(alg) \ ++ crypto_register(null_id,alg,0,0) ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_RIJNDAEL128_CBC); ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_SHA1); ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++ return 0; ++} ++ ++static void ++null_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(null_id); ++ null_id = -1; ++} ++ ++module_init(null_init); ++module_exit(null_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("ocfnull - claims a lot but does nothing"); +diff -Nur linux-2.6.39.orig/crypto/ocf/pasemi/Makefile linux-2.6.39/crypto/ocf/pasemi/Makefile +--- linux-2.6.39.orig/crypto/ocf/pasemi/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/pasemi/Makefile 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_PASEMI) += pasemi.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/pasemi/pasemi.c linux-2.6.39/crypto/ocf/pasemi/pasemi.c +--- linux-2.6.39.orig/crypto/ocf/pasemi/pasemi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/pasemi/pasemi.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,1009 @@ ++/* ++ * Copyright (C) 2007 PA Semi, Inc ++ * ++ * Driver for the PA Semi PWRficient DMA Crypto Engine ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "pasemi_fnu.h" ++ ++#define DRV_NAME "pasemi" ++ ++#define TIMER_INTERVAL 1000 ++ ++static void __devexit pasemi_dma_remove(struct pci_dev *pdev); ++static struct pasdma_status volatile * dma_status; ++ ++static int debug; ++module_param(debug, int, 0644); ++MODULE_PARM_DESC(debug, "Enable debug"); ++ ++static void pasemi_desc_start(struct pasemi_desc *desc, u64 hdr) ++{ ++ desc->postop = 0; ++ desc->quad[0] = hdr; ++ desc->quad_cnt = 1; ++ desc->size = 1; ++} ++ ++static void pasemi_desc_build(struct pasemi_desc *desc, u64 val) ++{ ++ desc->quad[desc->quad_cnt++] = val; ++ desc->size = (desc->quad_cnt + 1) / 2; ++} ++ ++static void pasemi_desc_hdr(struct pasemi_desc *desc, u64 hdr) ++{ ++ desc->quad[0] |= hdr; ++} ++ ++static int pasemi_desc_size(struct pasemi_desc *desc) ++{ ++ return desc->size; ++} ++ ++static void pasemi_ring_add_desc( ++ struct pasemi_fnu_txring *ring, ++ struct pasemi_desc *desc, ++ struct cryptop *crp) { ++ int i; ++ int ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); ++ ++ TX_DESC_INFO(ring, ring->next_to_fill).desc_size = desc->size; ++ TX_DESC_INFO(ring, ring->next_to_fill).desc_postop = desc->postop; ++ TX_DESC_INFO(ring, ring->next_to_fill).cf_crp = crp; ++ ++ for (i = 0; i < desc->quad_cnt; i += 2) { ++ ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); ++ ring->desc[ring_index] = desc->quad[i]; ++ ring->desc[ring_index + 1] = desc->quad[i + 1]; ++ ring->next_to_fill++; ++ } ++ ++ if (desc->quad_cnt & 1) ++ ring->desc[ring_index + 1] = 0; ++} ++ ++static void pasemi_ring_incr(struct pasemi_softc *sc, int chan_index, int incr) ++{ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_INCR(sc->base_chan + chan_index), ++ incr); ++} ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++pasemi_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct pasemi_softc *sc = device_get_softc(dev); ++ struct pasemi_session *ses = NULL, **sespp; ++ int sesn, blksz = 0; ++ u64 ccmd = 0; ++ unsigned long flags; ++ struct pasemi_desc init_desc; ++ struct pasemi_fnu_txring *txring; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ if (sidp == NULL || cri == NULL || sc == NULL) { ++ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return -EINVAL; ++ } ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (ALG_IS_SIG(c->cri_alg)) { ++ if (macini) ++ return -EINVAL; ++ macini = c; ++ } else if (ALG_IS_CIPHER(c->cri_alg)) { ++ if (encini) ++ return -EINVAL; ++ encini = c; ++ } else { ++ DPRINTF("UNKNOWN c->cri_alg %d\n", c->cri_alg); ++ return -EINVAL; ++ } ++ } ++ if (encini == NULL && macini == NULL) ++ return -EINVAL; ++ if (encini) { ++ /* validate key length */ ++ switch (encini->cri_alg) { ++ case CRYPTO_DES_CBC: ++ if (encini->cri_klen != 64) ++ return -EINVAL; ++ ccmd = DMA_CALGO_DES; ++ break; ++ case CRYPTO_3DES_CBC: ++ if (encini->cri_klen != 192) ++ return -EINVAL; ++ ccmd = DMA_CALGO_3DES; ++ break; ++ case CRYPTO_AES_CBC: ++ if (encini->cri_klen != 128 && ++ encini->cri_klen != 192 && ++ encini->cri_klen != 256) ++ return -EINVAL; ++ ccmd = DMA_CALGO_AES; ++ break; ++ case CRYPTO_ARC4: ++ if (encini->cri_klen != 128) ++ return -EINVAL; ++ ccmd = DMA_CALGO_ARC; ++ break; ++ default: ++ DPRINTF("UNKNOWN encini->cri_alg %d\n", ++ encini->cri_alg); ++ return -EINVAL; ++ } ++ } ++ ++ if (macini) { ++ switch (macini->cri_alg) { ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ blksz = 16; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ blksz = 20; ++ break; ++ default: ++ DPRINTF("UNKNOWN macini->cri_alg %d\n", ++ macini->cri_alg); ++ return -EINVAL; ++ } ++ if (((macini->cri_klen + 7) / 8) > blksz) { ++ DPRINTF("key length %d bigger than blksize %d not supported\n", ++ ((macini->cri_klen + 7) / 8), blksz); ++ return -EINVAL; ++ } ++ } ++ ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn] == NULL) { ++ sc->sc_sessions[sesn] = (struct pasemi_session *) ++ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); ++ ses = sc->sc_sessions[sesn]; ++ break; ++ } else if (sc->sc_sessions[sesn]->used == 0) { ++ ses = sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sespp = (struct pasemi_session **) ++ kzalloc(sc->sc_nsessions * 2 * ++ sizeof(struct pasemi_session *), GFP_ATOMIC); ++ if (sespp == NULL) ++ return -ENOMEM; ++ memcpy(sespp, sc->sc_sessions, ++ sc->sc_nsessions * sizeof(struct pasemi_session *)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = sespp; ++ sesn = sc->sc_nsessions; ++ ses = sc->sc_sessions[sesn] = (struct pasemi_session *) ++ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); ++ if (ses == NULL) ++ return -ENOMEM; ++ sc->sc_nsessions *= 2; ++ } ++ ++ ses->used = 1; ++ ++ ses->dma_addr = pci_map_single(sc->dma_pdev, (void *) ses->civ, ++ sizeof(struct pasemi_session), DMA_TO_DEVICE); ++ ++ /* enter the channel scheduler */ ++ spin_lock_irqsave(&sc->sc_chnlock, flags); ++ ++ /* ARC4 has to be processed by the even channel */ ++ if (encini && (encini->cri_alg == CRYPTO_ARC4)) ++ ses->chan = sc->sc_lastchn & ~1; ++ else ++ ses->chan = sc->sc_lastchn; ++ sc->sc_lastchn = (sc->sc_lastchn + 1) % sc->sc_num_channels; ++ ++ spin_unlock_irqrestore(&sc->sc_chnlock, flags); ++ ++ txring = &sc->tx[ses->chan]; ++ ++ if (encini) { ++ ses->ccmd = ccmd; ++ ++ /* get an IV */ ++ /* XXX may read fewer than requested */ ++ get_random_bytes(ses->civ, sizeof(ses->civ)); ++ ++ ses->keysz = (encini->cri_klen - 63) / 64; ++ memcpy(ses->key, encini->cri_key, (ses->keysz + 1) * 8); ++ ++ pasemi_desc_start(&init_desc, ++ XCT_CTRL_HDR(ses->chan, (encini && macini) ? 0x68 : 0x40, DMA_FN_CIV0)); ++ pasemi_desc_build(&init_desc, ++ XCT_FUN_SRC_PTR((encini && macini) ? 0x68 : 0x40, ses->dma_addr)); ++ } ++ if (macini) { ++ if (macini->cri_alg == CRYPTO_MD5_HMAC || ++ macini->cri_alg == CRYPTO_SHA1_HMAC) ++ memcpy(ses->hkey, macini->cri_key, blksz); ++ else { ++ /* Load initialization constants(RFC 1321, 3174) */ ++ ses->hiv[0] = 0x67452301efcdab89ULL; ++ ses->hiv[1] = 0x98badcfe10325476ULL; ++ ses->hiv[2] = 0xc3d2e1f000000000ULL; ++ } ++ ses->hseq = 0ULL; ++ } ++ ++ spin_lock_irqsave(&txring->fill_lock, flags); ++ ++ if (((txring->next_to_fill + pasemi_desc_size(&init_desc)) - ++ txring->next_to_clean) > TX_RING_SIZE) { ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ return ERESTART; ++ } ++ ++ if (encini) { ++ pasemi_ring_add_desc(txring, &init_desc, NULL); ++ pasemi_ring_incr(sc, ses->chan, ++ pasemi_desc_size(&init_desc)); ++ } ++ ++ txring->sesn = sesn; ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ ++ *sidp = PASEMI_SID(sesn); ++ return 0; ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++pasemi_freesession(device_t dev, u_int64_t tid) ++{ ++ struct pasemi_softc *sc = device_get_softc(dev); ++ int session; ++ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (sc == NULL) ++ return -EINVAL; ++ session = PASEMI_SESSION(sid); ++ if (session >= sc->sc_nsessions || !sc->sc_sessions[session]) ++ return -EINVAL; ++ ++ pci_unmap_single(sc->dma_pdev, ++ sc->sc_sessions[session]->dma_addr, ++ sizeof(struct pasemi_session), DMA_TO_DEVICE); ++ memset(sc->sc_sessions[session], 0, ++ sizeof(struct pasemi_session)); ++ ++ return 0; ++} ++ ++static int ++pasemi_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ ++ int err = 0, ivsize, srclen = 0, reinit = 0, reinit_size = 0, chsel; ++ struct pasemi_softc *sc = device_get_softc(dev); ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ caddr_t ivp; ++ struct pasemi_desc init_desc, work_desc; ++ struct pasemi_session *ses; ++ struct sk_buff *skb; ++ struct uio *uiop; ++ unsigned long flags; ++ struct pasemi_fnu_txring *txring; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) ++ return -EINVAL; ++ ++ crp->crp_etype = 0; ++ if (PASEMI_SESSION(crp->crp_sid) >= sc->sc_nsessions) ++ return -EINVAL; ++ ++ ses = sc->sc_sessions[PASEMI_SESSION(crp->crp_sid)]; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ err = -EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ if (ALG_IS_SIG(crd1->crd_alg)) { ++ maccrd = crd1; ++ if (crd2 == NULL) ++ enccrd = NULL; ++ else if (ALG_IS_CIPHER(crd2->crd_alg) && ++ (crd2->crd_flags & CRD_F_ENCRYPT) == 0) ++ enccrd = crd2; ++ else ++ goto erralg; ++ } else if (ALG_IS_CIPHER(crd1->crd_alg)) { ++ enccrd = crd1; ++ if (crd2 == NULL) ++ maccrd = NULL; ++ else if (ALG_IS_SIG(crd2->crd_alg) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) ++ maccrd = crd2; ++ else ++ goto erralg; ++ } else ++ goto erralg; ++ ++ chsel = ses->chan; ++ ++ txring = &sc->tx[chsel]; ++ ++ if (enccrd && !maccrd) { ++ if (enccrd->crd_alg == CRYPTO_ARC4) ++ reinit = 1; ++ reinit_size = 0x40; ++ srclen = crp->crp_ilen; ++ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I ++ | XCT_FUN_FUN(chsel)); ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) ++ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_ENC); ++ else ++ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_DEC); ++ } else if (enccrd && maccrd) { ++ if (enccrd->crd_alg == CRYPTO_ARC4) ++ reinit = 1; ++ reinit_size = 0x68; ++ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ /* Encrypt -> Authenticate */ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_ENC_SIG ++ | XCT_FUN_A | XCT_FUN_FUN(chsel)); ++ srclen = maccrd->crd_skip + maccrd->crd_len; ++ } else { ++ /* Authenticate -> Decrypt */ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG_DEC ++ | XCT_FUN_24BRES | XCT_FUN_FUN(chsel)); ++ pasemi_desc_build(&work_desc, 0); ++ pasemi_desc_build(&work_desc, 0); ++ pasemi_desc_build(&work_desc, 0); ++ work_desc.postop = PASEMI_CHECK_SIG; ++ srclen = crp->crp_ilen; ++ } ++ ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SHL(maccrd->crd_skip / 4)); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_CHL(enccrd->crd_skip - maccrd->crd_skip)); ++ } else if (!enccrd && maccrd) { ++ srclen = maccrd->crd_len; ++ ++ pasemi_desc_start(&init_desc, ++ XCT_CTRL_HDR(chsel, 0x58, DMA_FN_HKEY0)); ++ pasemi_desc_build(&init_desc, ++ XCT_FUN_SRC_PTR(0x58, ((struct pasemi_session *)ses->dma_addr)->hkey)); ++ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG ++ | XCT_FUN_A | XCT_FUN_FUN(chsel)); ++ } ++ ++ if (enccrd) { ++ switch (enccrd->crd_alg) { ++ case CRYPTO_3DES_CBC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_3DES | ++ XCT_FUN_BCM_CBC); ++ ivsize = sizeof(u64); ++ break; ++ case CRYPTO_DES_CBC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_DES | ++ XCT_FUN_BCM_CBC); ++ ivsize = sizeof(u64); ++ break; ++ case CRYPTO_AES_CBC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_AES | ++ XCT_FUN_BCM_CBC); ++ ivsize = 2 * sizeof(u64); ++ break; ++ case CRYPTO_ARC4: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_ARC); ++ ivsize = 0; ++ break; ++ default: ++ printk(DRV_NAME ": unimplemented enccrd->crd_alg %d\n", ++ enccrd->crd_alg); ++ err = -EINVAL; ++ goto errout; ++ } ++ ++ ivp = (ivsize == sizeof(u64)) ? (caddr_t) &ses->civ[1] : (caddr_t) &ses->civ[0]; ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ memcpy(ivp, enccrd->crd_iv, ivsize); ++ /* If IV is not present in the buffer already, it has to be copied there */ ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, ivp); ++ } else { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ /* IV is provided expicitly in descriptor */ ++ memcpy(ivp, enccrd->crd_iv, ivsize); ++ else ++ /* IV is provided in the packet */ ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, ++ ivp); ++ } ++ } ++ ++ if (maccrd) { ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_MD5 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ case CRYPTO_SHA1: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_SHA1 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ case CRYPTO_MD5_HMAC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_MD5 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_SHA1 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ default: ++ printk(DRV_NAME ": unimplemented maccrd->crd_alg %d\n", ++ maccrd->crd_alg); ++ err = -EINVAL; ++ goto errout; ++ } ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ /* using SKB buffers */ ++ skb = (struct sk_buff *)crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ printk(DRV_NAME ": skb frags unimplemented\n"); ++ err = -EINVAL; ++ goto errout; ++ } ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_DST_PTR(skb->len, pci_map_single( ++ sc->dma_pdev, skb->data, ++ skb->len, DMA_TO_DEVICE))); ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_SRC_PTR( ++ srclen, pci_map_single( ++ sc->dma_pdev, skb->data, ++ srclen, DMA_TO_DEVICE))); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ /* using IOV buffers */ ++ uiop = (struct uio *)crp->crp_buf; ++ if (uiop->uio_iovcnt > 1) { ++ printk(DRV_NAME ": iov frags unimplemented\n"); ++ err = -EINVAL; ++ goto errout; ++ } ++ ++ /* crp_olen is never set; always use crp_ilen */ ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( ++ sc->dma_pdev, ++ uiop->uio_iov->iov_base, ++ crp->crp_ilen, DMA_TO_DEVICE))); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); ++ ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_SRC_PTR(srclen, pci_map_single( ++ sc->dma_pdev, ++ uiop->uio_iov->iov_base, ++ srclen, DMA_TO_DEVICE))); ++ } else { ++ /* using contig buffers */ ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( ++ sc->dma_pdev, ++ crp->crp_buf, ++ crp->crp_ilen, DMA_TO_DEVICE))); ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_SRC_PTR(srclen, pci_map_single( ++ sc->dma_pdev, ++ crp->crp_buf, srclen, ++ DMA_TO_DEVICE))); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); ++ } ++ ++ spin_lock_irqsave(&txring->fill_lock, flags); ++ ++ if (txring->sesn != PASEMI_SESSION(crp->crp_sid)) { ++ txring->sesn = PASEMI_SESSION(crp->crp_sid); ++ reinit = 1; ++ } ++ ++ if (enccrd) { ++ pasemi_desc_start(&init_desc, ++ XCT_CTRL_HDR(chsel, reinit ? reinit_size : 0x10, DMA_FN_CIV0)); ++ pasemi_desc_build(&init_desc, ++ XCT_FUN_SRC_PTR(reinit ? reinit_size : 0x10, ses->dma_addr)); ++ } ++ ++ if (((txring->next_to_fill + pasemi_desc_size(&init_desc) + ++ pasemi_desc_size(&work_desc)) - ++ txring->next_to_clean) > TX_RING_SIZE) { ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ err = ERESTART; ++ goto errout; ++ } ++ ++ pasemi_ring_add_desc(txring, &init_desc, NULL); ++ pasemi_ring_add_desc(txring, &work_desc, crp); ++ ++ pasemi_ring_incr(sc, chsel, ++ pasemi_desc_size(&init_desc) + ++ pasemi_desc_size(&work_desc)); ++ ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ ++ mod_timer(&txring->crypto_timer, jiffies + TIMER_INTERVAL); ++ ++ return 0; ++ ++erralg: ++ printk(DRV_NAME ": unsupported algorithm or algorithm order alg1 %d alg2 %d\n", ++ crd1->crd_alg, crd2->crd_alg); ++ err = -EINVAL; ++ ++errout: ++ if (err != ERESTART) { ++ crp->crp_etype = err; ++ crypto_done(crp); ++ } ++ return err; ++} ++ ++static int pasemi_clean_tx(struct pasemi_softc *sc, int chan) ++{ ++ int i, j, ring_idx; ++ struct pasemi_fnu_txring *ring = &sc->tx[chan]; ++ u16 delta_cnt; ++ int flags, loops = 10; ++ int desc_size; ++ struct cryptop *crp; ++ ++ spin_lock_irqsave(&ring->clean_lock, flags); ++ ++ while ((delta_cnt = (dma_status->tx_sta[sc->base_chan + chan] ++ & PAS_STATUS_PCNT_M) - ring->total_pktcnt) ++ && loops--) { ++ ++ for (i = 0; i < delta_cnt; i++) { ++ desc_size = TX_DESC_INFO(ring, ring->next_to_clean).desc_size; ++ crp = TX_DESC_INFO(ring, ring->next_to_clean).cf_crp; ++ if (crp) { ++ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); ++ if (TX_DESC_INFO(ring, ring->next_to_clean).desc_postop & PASEMI_CHECK_SIG) { ++ /* Need to make sure signature matched, ++ * if not - return error */ ++ if (!(ring->desc[ring_idx + 1] & (1ULL << 63))) ++ crp->crp_etype = -EINVAL; ++ } ++ crypto_done(TX_DESC_INFO(ring, ++ ring->next_to_clean).cf_crp); ++ TX_DESC_INFO(ring, ring->next_to_clean).cf_crp = NULL; ++ pci_unmap_single( ++ sc->dma_pdev, ++ XCT_PTR_ADDR_LEN(ring->desc[ring_idx + 1]), ++ PCI_DMA_TODEVICE); ++ ++ ring->desc[ring_idx] = ring->desc[ring_idx + 1] = 0; ++ ++ ring->next_to_clean++; ++ for (j = 1; j < desc_size; j++) { ++ ring_idx = 2 * ++ (ring->next_to_clean & ++ (TX_RING_SIZE-1)); ++ pci_unmap_single( ++ sc->dma_pdev, ++ XCT_PTR_ADDR_LEN(ring->desc[ring_idx]), ++ PCI_DMA_TODEVICE); ++ if (ring->desc[ring_idx + 1]) ++ pci_unmap_single( ++ sc->dma_pdev, ++ XCT_PTR_ADDR_LEN( ++ ring->desc[ ++ ring_idx + 1]), ++ PCI_DMA_TODEVICE); ++ ring->desc[ring_idx] = ++ ring->desc[ring_idx + 1] = 0; ++ ring->next_to_clean++; ++ } ++ } else { ++ for (j = 0; j < desc_size; j++) { ++ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); ++ ring->desc[ring_idx] = ++ ring->desc[ring_idx + 1] = 0; ++ ring->next_to_clean++; ++ } ++ } ++ } ++ ++ ring->total_pktcnt += delta_cnt; ++ } ++ spin_unlock_irqrestore(&ring->clean_lock, flags); ++ ++ return 0; ++} ++ ++static void sweepup_tx(struct pasemi_softc *sc) ++{ ++ int i; ++ ++ for (i = 0; i < sc->sc_num_channels; i++) ++ pasemi_clean_tx(sc, i); ++} ++ ++static irqreturn_t pasemi_intr(int irq, void *arg, struct pt_regs *regs) ++{ ++ struct pasemi_softc *sc = arg; ++ unsigned int reg; ++ int chan = irq - sc->base_irq; ++ int chan_index = sc->base_chan + chan; ++ u64 stat = dma_status->tx_sta[chan_index]; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (!(stat & PAS_STATUS_CAUSE_M)) ++ return IRQ_NONE; ++ ++ pasemi_clean_tx(sc, chan); ++ ++ stat = dma_status->tx_sta[chan_index]; ++ ++ reg = PAS_IOB_DMA_TXCH_RESET_PINTC | ++ PAS_IOB_DMA_TXCH_RESET_PCNT(sc->tx[chan].total_pktcnt); ++ ++ if (stat & PAS_STATUS_SOFT) ++ reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; ++ ++ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), reg); ++ ++ ++ return IRQ_HANDLED; ++} ++ ++static int pasemi_dma_setup_tx_resources(struct pasemi_softc *sc, int chan) ++{ ++ u32 val; ++ int chan_index = chan + sc->base_chan; ++ int ret; ++ struct pasemi_fnu_txring *ring; ++ ++ ring = &sc->tx[chan]; ++ ++ spin_lock_init(&ring->fill_lock); ++ spin_lock_init(&ring->clean_lock); ++ ++ ring->desc_info = kzalloc(sizeof(struct pasemi_desc_info) * ++ TX_RING_SIZE, GFP_KERNEL); ++ if (!ring->desc_info) ++ return -ENOMEM; ++ ++ /* Allocate descriptors */ ++ ring->desc = dma_alloc_coherent(&sc->dma_pdev->dev, ++ TX_RING_SIZE * ++ 2 * sizeof(u64), ++ &ring->dma, GFP_KERNEL); ++ if (!ring->desc) ++ return -ENOMEM; ++ ++ memset((void *) ring->desc, 0, TX_RING_SIZE * 2 * sizeof(u64)); ++ ++ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), 0x30); ++ ++ ring->total_pktcnt = 0; ++ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEL(chan_index), ++ PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); ++ ++ val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); ++ val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); ++ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEU(chan_index), val); ++ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_CFG(chan_index), ++ PAS_DMA_TXCHAN_CFG_TY_FUNC | ++ PAS_DMA_TXCHAN_CFG_TATTR(chan) | ++ PAS_DMA_TXCHAN_CFG_WT(2)); ++ ++ /* enable tx channel */ ++ out_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index), ++ PAS_DMA_TXCHAN_TCMDSTA_EN); ++ ++ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_CFG(chan_index), ++ PAS_IOB_DMA_TXCH_CFG_CNTTH(1000)); ++ ++ ring->next_to_fill = 0; ++ ring->next_to_clean = 0; ++ ++ snprintf(ring->irq_name, sizeof(ring->irq_name), ++ "%s%d", "crypto", chan); ++ ++ ring->irq = irq_create_mapping(NULL, sc->base_irq + chan); ++ ret = request_irq(ring->irq, (irq_handler_t) ++ pasemi_intr, IRQF_DISABLED, ring->irq_name, sc); ++ if (ret) { ++ printk(KERN_ERR DRV_NAME ": failed to hook irq %d ret %d\n", ++ ring->irq, ret); ++ ring->irq = -1; ++ return ret; ++ } ++ ++ setup_timer(&ring->crypto_timer, (void *) sweepup_tx, (unsigned long) sc); ++ ++ return 0; ++} ++ ++static device_method_t pasemi_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, pasemi_newsession), ++ DEVMETHOD(cryptodev_freesession, pasemi_freesession), ++ DEVMETHOD(cryptodev_process, pasemi_process), ++}; ++ ++/* Set up the crypto device structure, private data, ++ * and anything else we need before we start */ ++ ++static int __devinit ++pasemi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *ent) ++{ ++ struct pasemi_softc *sc; ++ int ret, i; ++ ++ DPRINTF(KERN_ERR "%s()\n", __FUNCTION__); ++ ++ sc = kzalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return -ENOMEM; ++ ++ softc_device_init(sc, DRV_NAME, 1, pasemi_methods); ++ ++ pci_set_drvdata(pdev, sc); ++ ++ spin_lock_init(&sc->sc_chnlock); ++ ++ sc->sc_sessions = (struct pasemi_session **) ++ kzalloc(PASEMI_INITIAL_SESSIONS * ++ sizeof(struct pasemi_session *), GFP_ATOMIC); ++ if (sc->sc_sessions == NULL) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ sc->sc_nsessions = PASEMI_INITIAL_SESSIONS; ++ sc->sc_lastchn = 0; ++ sc->base_irq = pdev->irq + 6; ++ sc->base_chan = 6; ++ sc->sc_cid = -1; ++ sc->dma_pdev = pdev; ++ ++ sc->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); ++ if (!sc->iob_pdev) { ++ dev_err(&pdev->dev, "Can't find I/O Bridge\n"); ++ ret = -ENODEV; ++ goto out; ++ } ++ ++ /* This is hardcoded and ugly, but we have some firmware versions ++ * who don't provide the register space in the device tree. Luckily ++ * they are at well-known locations so we can just do the math here. ++ */ ++ sc->dma_regs = ++ ioremap(0xe0000000 + (sc->dma_pdev->devfn << 12), 0x2000); ++ sc->iob_regs = ++ ioremap(0xe0000000 + (sc->iob_pdev->devfn << 12), 0x2000); ++ if (!sc->dma_regs || !sc->iob_regs) { ++ dev_err(&pdev->dev, "Can't map registers\n"); ++ ret = -ENODEV; ++ goto out; ++ } ++ ++ dma_status = __ioremap(0xfd800000, 0x1000, 0); ++ if (!dma_status) { ++ ret = -ENODEV; ++ dev_err(&pdev->dev, "Can't map dmastatus space\n"); ++ goto out; ++ } ++ ++ sc->tx = (struct pasemi_fnu_txring *) ++ kzalloc(sizeof(struct pasemi_fnu_txring) ++ * 8, GFP_KERNEL); ++ if (!sc->tx) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ /* Initialize the h/w */ ++ out_le32(sc->dma_regs + PAS_DMA_COM_CFG, ++ (in_le32(sc->dma_regs + PAS_DMA_COM_CFG) | ++ PAS_DMA_COM_CFG_FWF)); ++ out_le32(sc->dma_regs + PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); ++ ++ for (i = 0; i < PASEMI_FNU_CHANNELS; i++) { ++ sc->sc_num_channels++; ++ ret = pasemi_dma_setup_tx_resources(sc, i); ++ if (ret) ++ goto out; ++ } ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), ++ CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ printk(KERN_ERR DRV_NAME ": could not get crypto driver id\n"); ++ ret = -ENXIO; ++ goto out; ++ } ++ ++ /* register algorithms with the framework */ ++ printk(DRV_NAME ":"); ++ ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ ++ return 0; ++ ++out: ++ pasemi_dma_remove(pdev); ++ return ret; ++} ++ ++#define MAX_RETRIES 5000 ++ ++static void pasemi_free_tx_resources(struct pasemi_softc *sc, int chan) ++{ ++ struct pasemi_fnu_txring *ring = &sc->tx[chan]; ++ int chan_index = chan + sc->base_chan; ++ int retries; ++ u32 stat; ++ ++ /* Stop the channel */ ++ out_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index), ++ PAS_DMA_TXCHAN_TCMDSTA_ST); ++ ++ for (retries = 0; retries < MAX_RETRIES; retries++) { ++ stat = in_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index)); ++ if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) ++ break; ++ cond_resched(); ++ } ++ ++ if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT) ++ dev_err(&sc->dma_pdev->dev, "Failed to stop tx channel %d\n", ++ chan_index); ++ ++ /* Disable the channel */ ++ out_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index), ++ 0); ++ ++ if (ring->desc_info) ++ kfree((void *) ring->desc_info); ++ if (ring->desc) ++ dma_free_coherent(&sc->dma_pdev->dev, ++ TX_RING_SIZE * ++ 2 * sizeof(u64), ++ (void *) ring->desc, ring->dma); ++ if (ring->irq != -1) ++ free_irq(ring->irq, sc); ++ ++ del_timer(&ring->crypto_timer); ++} ++ ++static void __devexit pasemi_dma_remove(struct pci_dev *pdev) ++{ ++ struct pasemi_softc *sc = pci_get_drvdata(pdev); ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (sc->sc_cid >= 0) { ++ crypto_unregister_all(sc->sc_cid); ++ } ++ ++ if (sc->tx) { ++ for (i = 0; i < sc->sc_num_channels; i++) ++ pasemi_free_tx_resources(sc, i); ++ ++ kfree(sc->tx); ++ } ++ if (sc->sc_sessions) { ++ for (i = 0; i < sc->sc_nsessions; i++) ++ kfree(sc->sc_sessions[i]); ++ kfree(sc->sc_sessions); ++ } ++ if (sc->iob_pdev) ++ pci_dev_put(sc->iob_pdev); ++ if (sc->dma_regs) ++ iounmap(sc->dma_regs); ++ if (sc->iob_regs) ++ iounmap(sc->iob_regs); ++ kfree(sc); ++} ++ ++static struct pci_device_id pasemi_dma_pci_tbl[] = { ++ { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa007) }, ++}; ++ ++MODULE_DEVICE_TABLE(pci, pasemi_dma_pci_tbl); ++ ++static struct pci_driver pasemi_dma_driver = { ++ .name = "pasemi_dma", ++ .id_table = pasemi_dma_pci_tbl, ++ .probe = pasemi_dma_probe, ++ .remove = __devexit_p(pasemi_dma_remove), ++}; ++ ++static void __exit pasemi_dma_cleanup_module(void) ++{ ++ pci_unregister_driver(&pasemi_dma_driver); ++ __iounmap(dma_status); ++ dma_status = NULL; ++} ++ ++int pasemi_dma_init_module(void) ++{ ++ return pci_register_driver(&pasemi_dma_driver); ++} ++ ++module_init(pasemi_dma_init_module); ++module_exit(pasemi_dma_cleanup_module); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("Egor Martovetsky egor@pasemi.com"); ++MODULE_DESCRIPTION("OCF driver for PA Semi PWRficient DMA Crypto Engine"); +diff -Nur linux-2.6.39.orig/crypto/ocf/pasemi/pasemi_fnu.h linux-2.6.39/crypto/ocf/pasemi/pasemi_fnu.h +--- linux-2.6.39.orig/crypto/ocf/pasemi/pasemi_fnu.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/pasemi/pasemi_fnu.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,410 @@ ++/* ++ * Copyright (C) 2007 PA Semi, Inc ++ * ++ * Driver for the PA Semi PWRficient DMA Crypto Engine, soft state and ++ * hardware register layouts. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef PASEMI_FNU_H ++#define PASEMI_FNU_H ++ ++#include ++ ++#define PASEMI_SESSION(sid) ((sid) & 0xffffffff) ++#define PASEMI_SID(sesn) ((sesn) & 0xffffffff) ++#define DPRINTF(a...) if (debug) { printk(DRV_NAME ": " a); } ++ ++/* Must be a power of two */ ++#define RX_RING_SIZE 512 ++#define TX_RING_SIZE 512 ++#define TX_DESC(ring, num) ((ring)->desc[2 * (num & (TX_RING_SIZE-1))]) ++#define TX_DESC_INFO(ring, num) ((ring)->desc_info[(num) & (TX_RING_SIZE-1)]) ++#define MAX_DESC_SIZE 8 ++#define PASEMI_INITIAL_SESSIONS 10 ++#define PASEMI_FNU_CHANNELS 8 ++ ++/* DMA descriptor */ ++struct pasemi_desc { ++ u64 quad[2*MAX_DESC_SIZE]; ++ int quad_cnt; ++ int size; ++ int postop; ++}; ++ ++/* ++ * Holds per descriptor data ++ */ ++struct pasemi_desc_info { ++ int desc_size; ++ int desc_postop; ++#define PASEMI_CHECK_SIG 0x1 ++ ++ struct cryptop *cf_crp; ++}; ++ ++/* ++ * Holds per channel data ++ */ ++struct pasemi_fnu_txring { ++ volatile u64 *desc; ++ volatile struct ++ pasemi_desc_info *desc_info; ++ dma_addr_t dma; ++ struct timer_list crypto_timer; ++ spinlock_t fill_lock; ++ spinlock_t clean_lock; ++ unsigned int next_to_fill; ++ unsigned int next_to_clean; ++ u16 total_pktcnt; ++ int irq; ++ int sesn; ++ char irq_name[10]; ++}; ++ ++/* ++ * Holds data specific to a single pasemi device. ++ */ ++struct pasemi_softc { ++ softc_device_decl sc_cdev; ++ struct pci_dev *dma_pdev; /* device backpointer */ ++ struct pci_dev *iob_pdev; /* device backpointer */ ++ void __iomem *dma_regs; ++ void __iomem *iob_regs; ++ int base_irq; ++ int base_chan; ++ int32_t sc_cid; /* crypto tag */ ++ int sc_nsessions; ++ struct pasemi_session **sc_sessions; ++ int sc_num_channels;/* number of crypto channels */ ++ ++ /* pointer to the array of txring datastructures, one txring per channel */ ++ struct pasemi_fnu_txring *tx; ++ ++ /* ++ * mutual exclusion for the channel scheduler ++ */ ++ spinlock_t sc_chnlock; ++ /* last channel used, for now use round-robin to allocate channels */ ++ int sc_lastchn; ++}; ++ ++struct pasemi_session { ++ u64 civ[2]; ++ u64 keysz; ++ u64 key[4]; ++ u64 ccmd; ++ u64 hkey[4]; ++ u64 hseq; ++ u64 giv[2]; ++ u64 hiv[4]; ++ ++ int used; ++ dma_addr_t dma_addr; ++ int chan; ++}; ++ ++/* status register layout in IOB region, at 0xfd800000 */ ++struct pasdma_status { ++ u64 rx_sta[64]; ++ u64 tx_sta[20]; ++}; ++ ++#define ALG_IS_CIPHER(alg) ((alg == CRYPTO_DES_CBC) || \ ++ (alg == CRYPTO_3DES_CBC) || \ ++ (alg == CRYPTO_AES_CBC) || \ ++ (alg == CRYPTO_ARC4) || \ ++ (alg == CRYPTO_NULL_CBC)) ++ ++#define ALG_IS_SIG(alg) ((alg == CRYPTO_MD5) || \ ++ (alg == CRYPTO_MD5_HMAC) || \ ++ (alg == CRYPTO_SHA1) || \ ++ (alg == CRYPTO_SHA1_HMAC) || \ ++ (alg == CRYPTO_NULL_HMAC)) ++ ++enum { ++ PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ ++ PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ ++ PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ ++ PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ ++ PAS_DMA_COM_CFG = 0x114, /* DMA Configuration Register */ ++}; ++ ++/* All these registers live in the PCI configuration space for the DMA PCI ++ * device. Use the normal PCI config access functions for them. ++ */ ++ ++#define PAS_DMA_COM_CFG_FWF 0x18000000 ++ ++#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ ++#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ ++#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ ++#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ ++ ++#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ ++#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ ++#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ ++#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ ++#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ ++#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ ++#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ ++#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ ++#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ ++#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ ++#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ ++#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = interface */ ++#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ ++#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c ++#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 ++#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ ++ PAS_DMA_TXCHAN_CFG_TATTR_M) ++#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 ++#define PAS_DMA_TXCHAN_CFG_WT_S 6 ++#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ ++ PAS_DMA_TXCHAN_CFG_WT_M) ++#define PAS_DMA_TXCHAN_CFG_LPSQ_FAST 0x00000400 ++#define PAS_DMA_TXCHAN_CFG_LPDQ_FAST 0x00000800 ++#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ ++#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ ++#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ ++#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 ++#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 ++#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ ++ PAS_DMA_TXCHAN_BASEL_BRBL_M) ++#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff ++#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 ++#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ ++ PAS_DMA_TXCHAN_BASEU_BRBH_M) ++/* # of cache lines worth of buffer ring */ ++#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 ++#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ ++#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ ++ PAS_DMA_TXCHAN_BASEU_SIZ_M) ++ ++#define PAS_STATUS_PCNT_M 0x000000000000ffffull ++#define PAS_STATUS_PCNT_S 0 ++#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull ++#define PAS_STATUS_DCNT_S 16 ++#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull ++#define PAS_STATUS_BPCNT_S 32 ++#define PAS_STATUS_CAUSE_M 0xf000000000000000ull ++#define PAS_STATUS_TIMER 0x1000000000000000ull ++#define PAS_STATUS_ERROR 0x2000000000000000ull ++#define PAS_STATUS_SOFT 0x4000000000000000ull ++#define PAS_STATUS_INT 0x8000000000000000ull ++ ++#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) ++#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff ++#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 ++#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ ++ PAS_IOB_DMA_RXCH_CFG_CNTTH_M) ++#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) ++#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff ++#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 ++#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ ++ PAS_IOB_DMA_TXCH_CFG_CNTTH_M) ++#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) ++#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 ++#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff ++#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 ++#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ ++ PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) ++#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) ++#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 ++#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff ++#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 ++#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ ++ PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) ++#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) ++#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 ++#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 ++#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ ++ PAS_IOB_DMA_RXCH_RESET_PCNT_M) ++#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 ++#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 ++#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 ++#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 ++#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 ++#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 ++#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) ++#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 ++#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 ++#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ ++ PAS_IOB_DMA_TXCH_RESET_PCNT_M) ++#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 ++#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 ++#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 ++#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 ++#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 ++#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 ++ ++#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 ++#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff ++#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 ++#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ ++ PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) ++ ++/* Transmit descriptor fields */ ++#define XCT_MACTX_T 0x8000000000000000ull ++#define XCT_MACTX_ST 0x4000000000000000ull ++#define XCT_MACTX_NORES 0x0000000000000000ull ++#define XCT_MACTX_8BRES 0x1000000000000000ull ++#define XCT_MACTX_24BRES 0x2000000000000000ull ++#define XCT_MACTX_40BRES 0x3000000000000000ull ++#define XCT_MACTX_I 0x0800000000000000ull ++#define XCT_MACTX_O 0x0400000000000000ull ++#define XCT_MACTX_E 0x0200000000000000ull ++#define XCT_MACTX_VLAN_M 0x0180000000000000ull ++#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull ++#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull ++#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull ++#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull ++#define XCT_MACTX_CRC_M 0x0060000000000000ull ++#define XCT_MACTX_CRC_NOP 0x0000000000000000ull ++#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull ++#define XCT_MACTX_CRC_PAD 0x0040000000000000ull ++#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull ++#define XCT_MACTX_SS 0x0010000000000000ull ++#define XCT_MACTX_LLEN_M 0x00007fff00000000ull ++#define XCT_MACTX_LLEN_S 32ull ++#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ ++ XCT_MACTX_LLEN_M) ++#define XCT_MACTX_IPH_M 0x00000000f8000000ull ++#define XCT_MACTX_IPH_S 27ull ++#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ ++ XCT_MACTX_IPH_M) ++#define XCT_MACTX_IPO_M 0x0000000007c00000ull ++#define XCT_MACTX_IPO_S 22ull ++#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ ++ XCT_MACTX_IPO_M) ++#define XCT_MACTX_CSUM_M 0x0000000000000060ull ++#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull ++#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull ++#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull ++#define XCT_MACTX_V6 0x0000000000000010ull ++#define XCT_MACTX_C 0x0000000000000004ull ++#define XCT_MACTX_AL2 0x0000000000000002ull ++ ++#define XCT_PTR_T 0x8000000000000000ull ++#define XCT_PTR_LEN_M 0x7ffff00000000000ull ++#define XCT_PTR_LEN_S 44 ++#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ ++ XCT_PTR_LEN_M) ++#define XCT_PTR_ADDR_M 0x00000fffffffffffull ++#define XCT_PTR_ADDR_S 0 ++#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ ++ XCT_PTR_ADDR_M) ++ ++/* Function descriptor fields */ ++#define XCT_FUN_T 0x8000000000000000ull ++#define XCT_FUN_ST 0x4000000000000000ull ++#define XCT_FUN_NORES 0x0000000000000000ull ++#define XCT_FUN_8BRES 0x1000000000000000ull ++#define XCT_FUN_24BRES 0x2000000000000000ull ++#define XCT_FUN_40BRES 0x3000000000000000ull ++#define XCT_FUN_I 0x0800000000000000ull ++#define XCT_FUN_O 0x0400000000000000ull ++#define XCT_FUN_E 0x0200000000000000ull ++#define XCT_FUN_FUN_S 54 ++#define XCT_FUN_FUN_M 0x01c0000000000000ull ++#define XCT_FUN_FUN(num) ((((long)(num)) << XCT_FUN_FUN_S) & \ ++ XCT_FUN_FUN_M) ++#define XCT_FUN_CRM_NOP 0x0000000000000000ull ++#define XCT_FUN_CRM_SIG 0x0008000000000000ull ++#define XCT_FUN_CRM_ENC 0x0010000000000000ull ++#define XCT_FUN_CRM_DEC 0x0018000000000000ull ++#define XCT_FUN_CRM_SIG_ENC 0x0020000000000000ull ++#define XCT_FUN_CRM_ENC_SIG 0x0028000000000000ull ++#define XCT_FUN_CRM_SIG_DEC 0x0030000000000000ull ++#define XCT_FUN_CRM_DEC_SIG 0x0038000000000000ull ++#define XCT_FUN_LLEN_M 0x0007ffff00000000ull ++#define XCT_FUN_LLEN_S 32ULL ++#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & \ ++ XCT_FUN_LLEN_M) ++#define XCT_FUN_SHL_M 0x00000000f8000000ull ++#define XCT_FUN_SHL_S 27ull ++#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & \ ++ XCT_FUN_SHL_M) ++#define XCT_FUN_CHL_M 0x0000000007c00000ull ++#define XCT_FUN_CHL_S 22ull ++#define XCT_FUN_CHL(x) ((((long)(x)) << XCT_FUN_CHL_S) & \ ++ XCT_FUN_CHL_M) ++#define XCT_FUN_HSZ_M 0x00000000003c0000ull ++#define XCT_FUN_HSZ_S 18ull ++#define XCT_FUN_HSZ(x) ((((long)(x)) << XCT_FUN_HSZ_S) & \ ++ XCT_FUN_HSZ_M) ++#define XCT_FUN_ALG_DES 0x0000000000000000ull ++#define XCT_FUN_ALG_3DES 0x0000000000008000ull ++#define XCT_FUN_ALG_AES 0x0000000000010000ull ++#define XCT_FUN_ALG_ARC 0x0000000000018000ull ++#define XCT_FUN_ALG_KASUMI 0x0000000000020000ull ++#define XCT_FUN_BCM_ECB 0x0000000000000000ull ++#define XCT_FUN_BCM_CBC 0x0000000000001000ull ++#define XCT_FUN_BCM_CFB 0x0000000000002000ull ++#define XCT_FUN_BCM_OFB 0x0000000000003000ull ++#define XCT_FUN_BCM_CNT 0x0000000000003800ull ++#define XCT_FUN_BCM_KAS_F8 0x0000000000002800ull ++#define XCT_FUN_BCM_KAS_F9 0x0000000000001800ull ++#define XCT_FUN_BCP_NO_PAD 0x0000000000000000ull ++#define XCT_FUN_BCP_ZRO 0x0000000000000200ull ++#define XCT_FUN_BCP_PL 0x0000000000000400ull ++#define XCT_FUN_BCP_INCR 0x0000000000000600ull ++#define XCT_FUN_SIG_MD5 (0ull << 4) ++#define XCT_FUN_SIG_SHA1 (2ull << 4) ++#define XCT_FUN_SIG_HMAC_MD5 (8ull << 4) ++#define XCT_FUN_SIG_HMAC_SHA1 (10ull << 4) ++#define XCT_FUN_A 0x0000000000000008ull ++#define XCT_FUN_C 0x0000000000000004ull ++#define XCT_FUN_AL2 0x0000000000000002ull ++#define XCT_FUN_SE 0x0000000000000001ull ++ ++#define XCT_FUN_SRC_PTR(len, addr) (XCT_PTR_LEN(len) | XCT_PTR_ADDR(addr)) ++#define XCT_FUN_DST_PTR(len, addr) (XCT_FUN_SRC_PTR(len, addr) | \ ++ 0x8000000000000000ull) ++ ++#define XCT_CTRL_HDR_FUN_NUM_M 0x01c0000000000000ull ++#define XCT_CTRL_HDR_FUN_NUM_S 54 ++#define XCT_CTRL_HDR_LEN_M 0x0007ffff00000000ull ++#define XCT_CTRL_HDR_LEN_S 32 ++#define XCT_CTRL_HDR_REG_M 0x00000000000000ffull ++#define XCT_CTRL_HDR_REG_S 0 ++ ++#define XCT_CTRL_HDR(funcN,len,reg) (0x9400000000000000ull | \ ++ ((((long)(funcN)) << XCT_CTRL_HDR_FUN_NUM_S) \ ++ & XCT_CTRL_HDR_FUN_NUM_M) | \ ++ ((((long)(len)) << \ ++ XCT_CTRL_HDR_LEN_S) & XCT_CTRL_HDR_LEN_M) | \ ++ ((((long)(reg)) << \ ++ XCT_CTRL_HDR_REG_S) & XCT_CTRL_HDR_REG_M)) ++ ++/* Function config command options */ ++#define DMA_CALGO_DES 0x00 ++#define DMA_CALGO_3DES 0x01 ++#define DMA_CALGO_AES 0x02 ++#define DMA_CALGO_ARC 0x03 ++ ++#define DMA_FN_CIV0 0x02 ++#define DMA_FN_CIV1 0x03 ++#define DMA_FN_HKEY0 0x0a ++ ++#define XCT_PTR_ADDR_LEN(ptr) ((ptr) & XCT_PTR_ADDR_M), \ ++ (((ptr) & XCT_PTR_LEN_M) >> XCT_PTR_LEN_S) ++ ++#endif /* PASEMI_FNU_H */ +diff -Nur linux-2.6.39.orig/crypto/ocf/random.c linux-2.6.39/crypto/ocf/random.c +--- linux-2.6.39.orig/crypto/ocf/random.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/random.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,322 @@ ++/* ++ * A system independant way of adding entropy to the kernels pool ++ * this way the drivers can focus on the real work and we can take ++ * care of pushing it to the appropriate place in the kernel. ++ * ++ * This should be fast and callable from timers/interrupts ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_OCF_FIPS ++#include "rndtest.h" ++#endif ++ ++#ifndef HAS_RANDOM_INPUT_WAIT ++#error "Please do not enable OCF_RANDOMHARVEST unless you have applied patches" ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++#include ++#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) ++#endif ++ ++/* ++ * a hack to access the debug levels from the crypto driver ++ */ ++extern int crypto_debug; ++#define debug crypto_debug ++ ++/* ++ * a list of all registered random providers ++ */ ++static LIST_HEAD(random_ops); ++static int started = 0; ++static int initted = 0; ++ ++struct random_op { ++ struct list_head random_list; ++ u_int32_t driverid; ++ int (*read_random)(void *arg, u_int32_t *buf, int len); ++ void *arg; ++}; ++ ++static int random_proc(void *arg); ++ ++static pid_t randomproc = (pid_t) -1; ++static spinlock_t random_lock; ++ ++/* ++ * just init the spin locks ++ */ ++static int ++crypto_random_init(void) ++{ ++ spin_lock_init(&random_lock); ++ initted = 1; ++ return(0); ++} ++ ++/* ++ * Add the given random reader to our list (if not present) ++ * and start the thread (if not already started) ++ * ++ * we have to assume that driver id is ok for now ++ */ ++int ++crypto_rregister( ++ u_int32_t driverid, ++ int (*read_random)(void *arg, u_int32_t *buf, int len), ++ void *arg) ++{ ++ unsigned long flags; ++ int ret = 0; ++ struct random_op *rops, *tmp; ++ ++ dprintk("%s,%d: %s(0x%x, %p, %p)\n", __FILE__, __LINE__, ++ __FUNCTION__, driverid, read_random, arg); ++ ++ if (!initted) ++ crypto_random_init(); ++ ++#if 0 ++ struct cryptocap *cap; ++ ++ cap = crypto_checkdriver(driverid); ++ if (!cap) ++ return EINVAL; ++#endif ++ ++ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { ++ if (rops->driverid == driverid && rops->read_random == read_random) ++ return EEXIST; ++ } ++ ++ rops = (struct random_op *) kmalloc(sizeof(*rops), GFP_KERNEL); ++ if (!rops) ++ return ENOMEM; ++ ++ rops->driverid = driverid; ++ rops->read_random = read_random; ++ rops->arg = arg; ++ ++ spin_lock_irqsave(&random_lock, flags); ++ list_add_tail(&rops->random_list, &random_ops); ++ if (!started) { ++ randomproc = kernel_thread(random_proc, NULL, CLONE_FS|CLONE_FILES); ++ if (randomproc < 0) { ++ ret = randomproc; ++ printk("crypto: crypto_rregister cannot start random thread; " ++ "error %d", ret); ++ } else ++ started = 1; ++ } ++ spin_unlock_irqrestore(&random_lock, flags); ++ ++ return ret; ++} ++EXPORT_SYMBOL(crypto_rregister); ++ ++int ++crypto_runregister_all(u_int32_t driverid) ++{ ++ struct random_op *rops, *tmp; ++ unsigned long flags; ++ ++ dprintk("%s,%d: %s(0x%x)\n", __FILE__, __LINE__, __FUNCTION__, driverid); ++ ++ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { ++ if (rops->driverid == driverid) { ++ list_del(&rops->random_list); ++ kfree(rops); ++ } ++ } ++ ++ spin_lock_irqsave(&random_lock, flags); ++ if (list_empty(&random_ops) && started) ++ kill_proc(randomproc, SIGKILL, 1); ++ spin_unlock_irqrestore(&random_lock, flags); ++ return(0); ++} ++EXPORT_SYMBOL(crypto_runregister_all); ++ ++/* ++ * while we can add entropy to random.c continue to read random data from ++ * the drivers and push it to random. ++ */ ++static int ++random_proc(void *arg) ++{ ++ int n; ++ int wantcnt; ++ int bufcnt = 0; ++ int retval = 0; ++ int *buf = NULL; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ daemonize(); ++ spin_lock_irq(¤t->sigmask_lock); ++ sigemptyset(¤t->blocked); ++ recalc_sigpending(current); ++ spin_unlock_irq(¤t->sigmask_lock); ++ sprintf(current->comm, "ocf-random"); ++#else ++ daemonize("ocf-random"); ++ allow_signal(SIGKILL); ++#endif ++ ++ (void) get_fs(); ++ set_fs(get_ds()); ++ ++#ifdef CONFIG_OCF_FIPS ++#define NUM_INT (RNDTEST_NBYTES/sizeof(int)) ++#else ++#define NUM_INT 32 ++#endif ++ ++ /* ++ * some devices can transferr their RNG data direct into memory, ++ * so make sure it is device friendly ++ */ ++ buf = kmalloc(NUM_INT * sizeof(int), GFP_DMA); ++ if (NULL == buf) { ++ printk("crypto: RNG could not allocate memory\n"); ++ retval = -ENOMEM; ++ goto bad_alloc; ++ } ++ ++ wantcnt = NUM_INT; /* start by adding some entropy */ ++ ++ /* ++ * its possible due to errors or driver removal that we no longer ++ * have anything to do, if so exit or we will consume all the CPU ++ * doing nothing ++ */ ++ while (!list_empty(&random_ops)) { ++ struct random_op *rops, *tmp; ++ ++#ifdef CONFIG_OCF_FIPS ++ if (wantcnt) ++ wantcnt = NUM_INT; /* FIPs mode can do 20000 bits or none */ ++#endif ++ ++ /* see if we can get enough entropy to make the world ++ * a better place. ++ */ ++ while (bufcnt < wantcnt && bufcnt < NUM_INT) { ++ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { ++ ++ n = (*rops->read_random)(rops->arg, &buf[bufcnt], ++ NUM_INT - bufcnt); ++ ++ /* on failure remove the random number generator */ ++ if (n == -1) { ++ list_del(&rops->random_list); ++ printk("crypto: RNG (driverid=0x%x) failed, disabling\n", ++ rops->driverid); ++ kfree(rops); ++ } else if (n > 0) ++ bufcnt += n; ++ } ++ /* give up CPU for a bit, just in case as this is a loop */ ++ schedule(); ++ } ++ ++ ++#ifdef CONFIG_OCF_FIPS ++ if (bufcnt > 0 && rndtest_buf((unsigned char *) &buf[0])) { ++ dprintk("crypto: buffer had fips errors, discarding\n"); ++ bufcnt = 0; ++ } ++#endif ++ ++ /* ++ * if we have a certified buffer, we can send some data ++ * to /dev/random and move along ++ */ ++ if (bufcnt > 0) { ++ /* add what we have */ ++ random_input_words(buf, bufcnt, bufcnt*sizeof(int)*8); ++ bufcnt = 0; ++ } ++ ++ /* give up CPU for a bit so we don't hog while filling */ ++ schedule(); ++ ++ /* wait for needing more */ ++ wantcnt = random_input_wait(); ++ ++ if (wantcnt <= 0) ++ wantcnt = 0; /* try to get some info again */ ++ else ++ /* round up to one word or we can loop forever */ ++ wantcnt = (wantcnt + (sizeof(int)*8)) / (sizeof(int)*8); ++ if (wantcnt > NUM_INT) { ++ wantcnt = NUM_INT; ++ } ++ ++ if (signal_pending(current)) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_lock_irq(¤t->sigmask_lock); ++#endif ++ flush_signals(current); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_unlock_irq(¤t->sigmask_lock); ++#endif ++ } ++ } ++ ++ kfree(buf); ++ ++bad_alloc: ++ spin_lock_irq(&random_lock); ++ randomproc = (pid_t) -1; ++ started = 0; ++ spin_unlock_irq(&random_lock); ++ ++ return retval; ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/rndtest.c linux-2.6.39/crypto/ocf/rndtest.c +--- linux-2.6.39.orig/crypto/ocf/rndtest.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/rndtest.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,300 @@ ++/* $OpenBSD$ */ ++ ++/* ++ * OCF/Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by Jason L. Wright ++ * 4. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, ++ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ++ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "rndtest.h" ++ ++static struct rndtest_stats rndstats; ++ ++static void rndtest_test(struct rndtest_state *); ++ ++/* The tests themselves */ ++static int rndtest_monobit(struct rndtest_state *); ++static int rndtest_runs(struct rndtest_state *); ++static int rndtest_longruns(struct rndtest_state *); ++static int rndtest_chi_4(struct rndtest_state *); ++ ++static int rndtest_runs_check(struct rndtest_state *, int, int *); ++static void rndtest_runs_record(struct rndtest_state *, int, int *); ++ ++static const struct rndtest_testfunc { ++ int (*test)(struct rndtest_state *); ++} rndtest_funcs[] = { ++ { rndtest_monobit }, ++ { rndtest_runs }, ++ { rndtest_chi_4 }, ++ { rndtest_longruns }, ++}; ++ ++#define RNDTEST_NTESTS (sizeof(rndtest_funcs)/sizeof(rndtest_funcs[0])) ++ ++static void ++rndtest_test(struct rndtest_state *rsp) ++{ ++ int i, rv = 0; ++ ++ rndstats.rst_tests++; ++ for (i = 0; i < RNDTEST_NTESTS; i++) ++ rv |= (*rndtest_funcs[i].test)(rsp); ++ rsp->rs_discard = (rv != 0); ++} ++ ++ ++extern int crypto_debug; ++#define rndtest_verbose 2 ++#define rndtest_report(rsp, failure, fmt, a...) \ ++ { if (failure || crypto_debug) { printk("rng_test: " fmt "\n", a); } else; } ++ ++#define RNDTEST_MONOBIT_MINONES 9725 ++#define RNDTEST_MONOBIT_MAXONES 10275 ++ ++static int ++rndtest_monobit(struct rndtest_state *rsp) ++{ ++ int i, ones = 0, j; ++ u_int8_t r; ++ ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ r = rsp->rs_buf[i]; ++ for (j = 0; j < 8; j++, r <<= 1) ++ if (r & 0x80) ++ ones++; ++ } ++ if (ones > RNDTEST_MONOBIT_MINONES && ++ ones < RNDTEST_MONOBIT_MAXONES) { ++ if (rndtest_verbose > 1) ++ rndtest_report(rsp, 0, "monobit pass (%d < %d < %d)", ++ RNDTEST_MONOBIT_MINONES, ones, ++ RNDTEST_MONOBIT_MAXONES); ++ return (0); ++ } else { ++ if (rndtest_verbose) ++ rndtest_report(rsp, 1, ++ "monobit failed (%d ones)", ones); ++ rndstats.rst_monobit++; ++ return (-1); ++ } ++} ++ ++#define RNDTEST_RUNS_NINTERVAL 6 ++ ++static const struct rndtest_runs_tabs { ++ u_int16_t min, max; ++} rndtest_runs_tab[] = { ++ { 2343, 2657 }, ++ { 1135, 1365 }, ++ { 542, 708 }, ++ { 251, 373 }, ++ { 111, 201 }, ++ { 111, 201 }, ++}; ++ ++static int ++rndtest_runs(struct rndtest_state *rsp) ++{ ++ int i, j, ones, zeros, rv = 0; ++ int onei[RNDTEST_RUNS_NINTERVAL], zeroi[RNDTEST_RUNS_NINTERVAL]; ++ u_int8_t c; ++ ++ bzero(onei, sizeof(onei)); ++ bzero(zeroi, sizeof(zeroi)); ++ ones = zeros = 0; ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ c = rsp->rs_buf[i]; ++ for (j = 0; j < 8; j++, c <<= 1) { ++ if (c & 0x80) { ++ ones++; ++ rndtest_runs_record(rsp, zeros, zeroi); ++ zeros = 0; ++ } else { ++ zeros++; ++ rndtest_runs_record(rsp, ones, onei); ++ ones = 0; ++ } ++ } ++ } ++ rndtest_runs_record(rsp, ones, onei); ++ rndtest_runs_record(rsp, zeros, zeroi); ++ ++ rv |= rndtest_runs_check(rsp, 0, zeroi); ++ rv |= rndtest_runs_check(rsp, 1, onei); ++ ++ if (rv) ++ rndstats.rst_runs++; ++ ++ return (rv); ++} ++ ++static void ++rndtest_runs_record(struct rndtest_state *rsp, int len, int *intrv) ++{ ++ if (len == 0) ++ return; ++ if (len > RNDTEST_RUNS_NINTERVAL) ++ len = RNDTEST_RUNS_NINTERVAL; ++ len -= 1; ++ intrv[len]++; ++} ++ ++static int ++rndtest_runs_check(struct rndtest_state *rsp, int val, int *src) ++{ ++ int i, rv = 0; ++ ++ for (i = 0; i < RNDTEST_RUNS_NINTERVAL; i++) { ++ if (src[i] < rndtest_runs_tab[i].min || ++ src[i] > rndtest_runs_tab[i].max) { ++ rndtest_report(rsp, 1, ++ "%s interval %d failed (%d, %d-%d)", ++ val ? "ones" : "zeros", ++ i + 1, src[i], rndtest_runs_tab[i].min, ++ rndtest_runs_tab[i].max); ++ rv = -1; ++ } else { ++ rndtest_report(rsp, 0, ++ "runs pass %s interval %d (%d < %d < %d)", ++ val ? "ones" : "zeros", ++ i + 1, rndtest_runs_tab[i].min, src[i], ++ rndtest_runs_tab[i].max); ++ } ++ } ++ return (rv); ++} ++ ++static int ++rndtest_longruns(struct rndtest_state *rsp) ++{ ++ int i, j, ones = 0, zeros = 0, maxones = 0, maxzeros = 0; ++ u_int8_t c; ++ ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ c = rsp->rs_buf[i]; ++ for (j = 0; j < 8; j++, c <<= 1) { ++ if (c & 0x80) { ++ zeros = 0; ++ ones++; ++ if (ones > maxones) ++ maxones = ones; ++ } else { ++ ones = 0; ++ zeros++; ++ if (zeros > maxzeros) ++ maxzeros = zeros; ++ } ++ } ++ } ++ ++ if (maxones < 26 && maxzeros < 26) { ++ rndtest_report(rsp, 0, "longruns pass (%d ones, %d zeros)", ++ maxones, maxzeros); ++ return (0); ++ } else { ++ rndtest_report(rsp, 1, "longruns fail (%d ones, %d zeros)", ++ maxones, maxzeros); ++ rndstats.rst_longruns++; ++ return (-1); ++ } ++} ++ ++/* ++ * chi^2 test over 4 bits: (this is called the poker test in FIPS 140-2, ++ * but it is really the chi^2 test over 4 bits (the poker test as described ++ * by Knuth vol 2 is something different, and I take him as authoritative ++ * on nomenclature over NIST). ++ */ ++#define RNDTEST_CHI4_K 16 ++#define RNDTEST_CHI4_K_MASK (RNDTEST_CHI4_K - 1) ++ ++/* ++ * The unnormalized values are used so that we don't have to worry about ++ * fractional precision. The "real" value is found by: ++ * (V - 1562500) * (16 / 5000) = Vn (where V is the unnormalized value) ++ */ ++#define RNDTEST_CHI4_VMIN 1563181 /* 2.1792 */ ++#define RNDTEST_CHI4_VMAX 1576929 /* 46.1728 */ ++ ++static int ++rndtest_chi_4(struct rndtest_state *rsp) ++{ ++ unsigned int freq[RNDTEST_CHI4_K], i, sum; ++ ++ for (i = 0; i < RNDTEST_CHI4_K; i++) ++ freq[i] = 0; ++ ++ /* Get number of occurances of each 4 bit pattern */ ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ freq[(rsp->rs_buf[i] >> 4) & RNDTEST_CHI4_K_MASK]++; ++ freq[(rsp->rs_buf[i] >> 0) & RNDTEST_CHI4_K_MASK]++; ++ } ++ ++ for (i = 0, sum = 0; i < RNDTEST_CHI4_K; i++) ++ sum += freq[i] * freq[i]; ++ ++ if (sum >= 1563181 && sum <= 1576929) { ++ rndtest_report(rsp, 0, "chi^2(4): pass (sum %u)", sum); ++ return (0); ++ } else { ++ rndtest_report(rsp, 1, "chi^2(4): failed (sum %u)", sum); ++ rndstats.rst_chi++; ++ return (-1); ++ } ++} ++ ++int ++rndtest_buf(unsigned char *buf) ++{ ++ struct rndtest_state rsp; ++ ++ memset(&rsp, 0, sizeof(rsp)); ++ rsp.rs_buf = buf; ++ rndtest_test(&rsp); ++ return(rsp.rs_discard); ++} ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/rndtest.h linux-2.6.39/crypto/ocf/rndtest.h +--- linux-2.6.39.orig/crypto/ocf/rndtest.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/rndtest.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,54 @@ ++/* $FreeBSD: src/sys/dev/rndtest/rndtest.h,v 1.1 2003/03/11 22:54:44 sam Exp $ */ ++/* $OpenBSD$ */ ++ ++/* ++ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by Jason L. Wright ++ * 4. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, ++ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ++ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++/* Some of the tests depend on these values */ ++#define RNDTEST_NBYTES 2500 ++#define RNDTEST_NBITS (8 * RNDTEST_NBYTES) ++ ++struct rndtest_state { ++ int rs_discard; /* discard/accept random data */ ++ u_int8_t *rs_buf; ++}; ++ ++struct rndtest_stats { ++ u_int32_t rst_discard; /* number of bytes discarded */ ++ u_int32_t rst_tests; /* number of test runs */ ++ u_int32_t rst_monobit; /* monobit test failures */ ++ u_int32_t rst_runs; /* 0/1 runs failures */ ++ u_int32_t rst_longruns; /* longruns failures */ ++ u_int32_t rst_chi; /* chi^2 failures */ ++}; ++ ++extern int rndtest_buf(unsigned char *buf); +diff -Nur linux-2.6.39.orig/crypto/ocf/safe/Makefile linux-2.6.39/crypto/ocf/safe/Makefile +--- linux-2.6.39.orig/crypto/ocf/safe/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/safe/Makefile 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_SAFE) += safe.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/safe/md5.c linux-2.6.39/crypto/ocf/safe/md5.c +--- linux-2.6.39.orig/crypto/ocf/safe/md5.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/safe/md5.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,308 @@ ++/* $KAME: md5.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++#if 0 ++#include ++__FBSDID("$FreeBSD: src/sys/crypto/md5.c,v 1.9 2004/01/27 19:49:19 des Exp $"); ++ ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++#define SHIFT(X, s) (((X) << (s)) | ((X) >> (32 - (s)))) ++ ++#define F(X, Y, Z) (((X) & (Y)) | ((~X) & (Z))) ++#define G(X, Y, Z) (((X) & (Z)) | ((Y) & (~Z))) ++#define H(X, Y, Z) ((X) ^ (Y) ^ (Z)) ++#define I(X, Y, Z) ((Y) ^ ((X) | (~Z))) ++ ++#define ROUND1(a, b, c, d, k, s, i) { \ ++ (a) = (a) + F((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define ROUND2(a, b, c, d, k, s, i) { \ ++ (a) = (a) + G((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define ROUND3(a, b, c, d, k, s, i) { \ ++ (a) = (a) + H((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define ROUND4(a, b, c, d, k, s, i) { \ ++ (a) = (a) + I((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define Sa 7 ++#define Sb 12 ++#define Sc 17 ++#define Sd 22 ++ ++#define Se 5 ++#define Sf 9 ++#define Sg 14 ++#define Sh 20 ++ ++#define Si 4 ++#define Sj 11 ++#define Sk 16 ++#define Sl 23 ++ ++#define Sm 6 ++#define Sn 10 ++#define So 15 ++#define Sp 21 ++ ++#define MD5_A0 0x67452301 ++#define MD5_B0 0xefcdab89 ++#define MD5_C0 0x98badcfe ++#define MD5_D0 0x10325476 ++ ++/* Integer part of 4294967296 times abs(sin(i)), where i is in radians. */ ++static const u_int32_t T[65] = { ++ 0, ++ 0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee, ++ 0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501, ++ 0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be, ++ 0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821, ++ ++ 0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa, ++ 0xd62f105d, 0x2441453, 0xd8a1e681, 0xe7d3fbc8, ++ 0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed, ++ 0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a, ++ ++ 0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c, ++ 0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70, ++ 0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x4881d05, ++ 0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665, ++ ++ 0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039, ++ 0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1, ++ 0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1, ++ 0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391, ++}; ++ ++static const u_int8_t md5_paddat[MD5_BUFLEN] = { ++ 0x80, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++}; ++ ++static void md5_calc(u_int8_t *, md5_ctxt *); ++ ++void md5_init(ctxt) ++ md5_ctxt *ctxt; ++{ ++ ctxt->md5_n = 0; ++ ctxt->md5_i = 0; ++ ctxt->md5_sta = MD5_A0; ++ ctxt->md5_stb = MD5_B0; ++ ctxt->md5_stc = MD5_C0; ++ ctxt->md5_std = MD5_D0; ++ bzero(ctxt->md5_buf, sizeof(ctxt->md5_buf)); ++} ++ ++void md5_loop(ctxt, input, len) ++ md5_ctxt *ctxt; ++ u_int8_t *input; ++ u_int len; /* number of bytes */ ++{ ++ u_int gap, i; ++ ++ ctxt->md5_n += len * 8; /* byte to bit */ ++ gap = MD5_BUFLEN - ctxt->md5_i; ++ ++ if (len >= gap) { ++ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), ++ gap); ++ md5_calc(ctxt->md5_buf, ctxt); ++ ++ for (i = gap; i + MD5_BUFLEN <= len; i += MD5_BUFLEN) { ++ md5_calc((u_int8_t *)(input + i), ctxt); ++ } ++ ++ ctxt->md5_i = len - i; ++ bcopy((void *)(input + i), (void *)ctxt->md5_buf, ctxt->md5_i); ++ } else { ++ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), ++ len); ++ ctxt->md5_i += len; ++ } ++} ++ ++void md5_pad(ctxt) ++ md5_ctxt *ctxt; ++{ ++ u_int gap; ++ ++ /* Don't count up padding. Keep md5_n. */ ++ gap = MD5_BUFLEN - ctxt->md5_i; ++ if (gap > 8) { ++ bcopy(md5_paddat, ++ (void *)(ctxt->md5_buf + ctxt->md5_i), ++ gap - sizeof(ctxt->md5_n)); ++ } else { ++ /* including gap == 8 */ ++ bcopy(md5_paddat, (void *)(ctxt->md5_buf + ctxt->md5_i), ++ gap); ++ md5_calc(ctxt->md5_buf, ctxt); ++ bcopy((md5_paddat + gap), ++ (void *)ctxt->md5_buf, ++ MD5_BUFLEN - sizeof(ctxt->md5_n)); ++ } ++ ++ /* 8 byte word */ ++#if BYTE_ORDER == LITTLE_ENDIAN ++ bcopy(&ctxt->md5_n8[0], &ctxt->md5_buf[56], 8); ++#endif ++#if BYTE_ORDER == BIG_ENDIAN ++ ctxt->md5_buf[56] = ctxt->md5_n8[7]; ++ ctxt->md5_buf[57] = ctxt->md5_n8[6]; ++ ctxt->md5_buf[58] = ctxt->md5_n8[5]; ++ ctxt->md5_buf[59] = ctxt->md5_n8[4]; ++ ctxt->md5_buf[60] = ctxt->md5_n8[3]; ++ ctxt->md5_buf[61] = ctxt->md5_n8[2]; ++ ctxt->md5_buf[62] = ctxt->md5_n8[1]; ++ ctxt->md5_buf[63] = ctxt->md5_n8[0]; ++#endif ++ ++ md5_calc(ctxt->md5_buf, ctxt); ++} ++ ++void md5_result(digest, ctxt) ++ u_int8_t *digest; ++ md5_ctxt *ctxt; ++{ ++ /* 4 byte words */ ++#if BYTE_ORDER == LITTLE_ENDIAN ++ bcopy(&ctxt->md5_st8[0], digest, 16); ++#endif ++#if BYTE_ORDER == BIG_ENDIAN ++ digest[ 0] = ctxt->md5_st8[ 3]; digest[ 1] = ctxt->md5_st8[ 2]; ++ digest[ 2] = ctxt->md5_st8[ 1]; digest[ 3] = ctxt->md5_st8[ 0]; ++ digest[ 4] = ctxt->md5_st8[ 7]; digest[ 5] = ctxt->md5_st8[ 6]; ++ digest[ 6] = ctxt->md5_st8[ 5]; digest[ 7] = ctxt->md5_st8[ 4]; ++ digest[ 8] = ctxt->md5_st8[11]; digest[ 9] = ctxt->md5_st8[10]; ++ digest[10] = ctxt->md5_st8[ 9]; digest[11] = ctxt->md5_st8[ 8]; ++ digest[12] = ctxt->md5_st8[15]; digest[13] = ctxt->md5_st8[14]; ++ digest[14] = ctxt->md5_st8[13]; digest[15] = ctxt->md5_st8[12]; ++#endif ++} ++ ++static void md5_calc(b64, ctxt) ++ u_int8_t *b64; ++ md5_ctxt *ctxt; ++{ ++ u_int32_t A = ctxt->md5_sta; ++ u_int32_t B = ctxt->md5_stb; ++ u_int32_t C = ctxt->md5_stc; ++ u_int32_t D = ctxt->md5_std; ++#if BYTE_ORDER == LITTLE_ENDIAN ++ u_int32_t *X = (u_int32_t *)b64; ++#endif ++#if BYTE_ORDER == BIG_ENDIAN ++ /* 4 byte words */ ++ /* what a brute force but fast! */ ++ u_int32_t X[16]; ++ u_int8_t *y = (u_int8_t *)X; ++ y[ 0] = b64[ 3]; y[ 1] = b64[ 2]; y[ 2] = b64[ 1]; y[ 3] = b64[ 0]; ++ y[ 4] = b64[ 7]; y[ 5] = b64[ 6]; y[ 6] = b64[ 5]; y[ 7] = b64[ 4]; ++ y[ 8] = b64[11]; y[ 9] = b64[10]; y[10] = b64[ 9]; y[11] = b64[ 8]; ++ y[12] = b64[15]; y[13] = b64[14]; y[14] = b64[13]; y[15] = b64[12]; ++ y[16] = b64[19]; y[17] = b64[18]; y[18] = b64[17]; y[19] = b64[16]; ++ y[20] = b64[23]; y[21] = b64[22]; y[22] = b64[21]; y[23] = b64[20]; ++ y[24] = b64[27]; y[25] = b64[26]; y[26] = b64[25]; y[27] = b64[24]; ++ y[28] = b64[31]; y[29] = b64[30]; y[30] = b64[29]; y[31] = b64[28]; ++ y[32] = b64[35]; y[33] = b64[34]; y[34] = b64[33]; y[35] = b64[32]; ++ y[36] = b64[39]; y[37] = b64[38]; y[38] = b64[37]; y[39] = b64[36]; ++ y[40] = b64[43]; y[41] = b64[42]; y[42] = b64[41]; y[43] = b64[40]; ++ y[44] = b64[47]; y[45] = b64[46]; y[46] = b64[45]; y[47] = b64[44]; ++ y[48] = b64[51]; y[49] = b64[50]; y[50] = b64[49]; y[51] = b64[48]; ++ y[52] = b64[55]; y[53] = b64[54]; y[54] = b64[53]; y[55] = b64[52]; ++ y[56] = b64[59]; y[57] = b64[58]; y[58] = b64[57]; y[59] = b64[56]; ++ y[60] = b64[63]; y[61] = b64[62]; y[62] = b64[61]; y[63] = b64[60]; ++#endif ++ ++ ROUND1(A, B, C, D, 0, Sa, 1); ROUND1(D, A, B, C, 1, Sb, 2); ++ ROUND1(C, D, A, B, 2, Sc, 3); ROUND1(B, C, D, A, 3, Sd, 4); ++ ROUND1(A, B, C, D, 4, Sa, 5); ROUND1(D, A, B, C, 5, Sb, 6); ++ ROUND1(C, D, A, B, 6, Sc, 7); ROUND1(B, C, D, A, 7, Sd, 8); ++ ROUND1(A, B, C, D, 8, Sa, 9); ROUND1(D, A, B, C, 9, Sb, 10); ++ ROUND1(C, D, A, B, 10, Sc, 11); ROUND1(B, C, D, A, 11, Sd, 12); ++ ROUND1(A, B, C, D, 12, Sa, 13); ROUND1(D, A, B, C, 13, Sb, 14); ++ ROUND1(C, D, A, B, 14, Sc, 15); ROUND1(B, C, D, A, 15, Sd, 16); ++ ++ ROUND2(A, B, C, D, 1, Se, 17); ROUND2(D, A, B, C, 6, Sf, 18); ++ ROUND2(C, D, A, B, 11, Sg, 19); ROUND2(B, C, D, A, 0, Sh, 20); ++ ROUND2(A, B, C, D, 5, Se, 21); ROUND2(D, A, B, C, 10, Sf, 22); ++ ROUND2(C, D, A, B, 15, Sg, 23); ROUND2(B, C, D, A, 4, Sh, 24); ++ ROUND2(A, B, C, D, 9, Se, 25); ROUND2(D, A, B, C, 14, Sf, 26); ++ ROUND2(C, D, A, B, 3, Sg, 27); ROUND2(B, C, D, A, 8, Sh, 28); ++ ROUND2(A, B, C, D, 13, Se, 29); ROUND2(D, A, B, C, 2, Sf, 30); ++ ROUND2(C, D, A, B, 7, Sg, 31); ROUND2(B, C, D, A, 12, Sh, 32); ++ ++ ROUND3(A, B, C, D, 5, Si, 33); ROUND3(D, A, B, C, 8, Sj, 34); ++ ROUND3(C, D, A, B, 11, Sk, 35); ROUND3(B, C, D, A, 14, Sl, 36); ++ ROUND3(A, B, C, D, 1, Si, 37); ROUND3(D, A, B, C, 4, Sj, 38); ++ ROUND3(C, D, A, B, 7, Sk, 39); ROUND3(B, C, D, A, 10, Sl, 40); ++ ROUND3(A, B, C, D, 13, Si, 41); ROUND3(D, A, B, C, 0, Sj, 42); ++ ROUND3(C, D, A, B, 3, Sk, 43); ROUND3(B, C, D, A, 6, Sl, 44); ++ ROUND3(A, B, C, D, 9, Si, 45); ROUND3(D, A, B, C, 12, Sj, 46); ++ ROUND3(C, D, A, B, 15, Sk, 47); ROUND3(B, C, D, A, 2, Sl, 48); ++ ++ ROUND4(A, B, C, D, 0, Sm, 49); ROUND4(D, A, B, C, 7, Sn, 50); ++ ROUND4(C, D, A, B, 14, So, 51); ROUND4(B, C, D, A, 5, Sp, 52); ++ ROUND4(A, B, C, D, 12, Sm, 53); ROUND4(D, A, B, C, 3, Sn, 54); ++ ROUND4(C, D, A, B, 10, So, 55); ROUND4(B, C, D, A, 1, Sp, 56); ++ ROUND4(A, B, C, D, 8, Sm, 57); ROUND4(D, A, B, C, 15, Sn, 58); ++ ROUND4(C, D, A, B, 6, So, 59); ROUND4(B, C, D, A, 13, Sp, 60); ++ ROUND4(A, B, C, D, 4, Sm, 61); ROUND4(D, A, B, C, 11, Sn, 62); ++ ROUND4(C, D, A, B, 2, So, 63); ROUND4(B, C, D, A, 9, Sp, 64); ++ ++ ctxt->md5_sta += A; ++ ctxt->md5_stb += B; ++ ctxt->md5_stc += C; ++ ctxt->md5_std += D; ++} +diff -Nur linux-2.6.39.orig/crypto/ocf/safe/md5.h linux-2.6.39/crypto/ocf/safe/md5.h +--- linux-2.6.39.orig/crypto/ocf/safe/md5.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/safe/md5.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,76 @@ ++/* $FreeBSD: src/sys/crypto/md5.h,v 1.4 2002/03/20 05:13:50 alfred Exp $ */ ++/* $KAME: md5.h,v 1.4 2000/03/27 04:36:22 sumikawa Exp $ */ ++ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++#ifndef _NETINET6_MD5_H_ ++#define _NETINET6_MD5_H_ ++ ++#define MD5_BUFLEN 64 ++ ++typedef struct { ++ union { ++ u_int32_t md5_state32[4]; ++ u_int8_t md5_state8[16]; ++ } md5_st; ++ ++#define md5_sta md5_st.md5_state32[0] ++#define md5_stb md5_st.md5_state32[1] ++#define md5_stc md5_st.md5_state32[2] ++#define md5_std md5_st.md5_state32[3] ++#define md5_st8 md5_st.md5_state8 ++ ++ union { ++ u_int64_t md5_count64; ++ u_int8_t md5_count8[8]; ++ } md5_count; ++#define md5_n md5_count.md5_count64 ++#define md5_n8 md5_count.md5_count8 ++ ++ u_int md5_i; ++ u_int8_t md5_buf[MD5_BUFLEN]; ++} md5_ctxt; ++ ++extern void md5_init(md5_ctxt *); ++extern void md5_loop(md5_ctxt *, u_int8_t *, u_int); ++extern void md5_pad(md5_ctxt *); ++extern void md5_result(u_int8_t *, md5_ctxt *); ++ ++/* compatibility */ ++#define MD5_CTX md5_ctxt ++#define MD5Init(x) md5_init((x)) ++#define MD5Update(x, y, z) md5_loop((x), (y), (z)) ++#define MD5Final(x, y) \ ++do { \ ++ md5_pad((y)); \ ++ md5_result((x), (y)); \ ++} while (0) ++ ++#endif /* ! _NETINET6_MD5_H_*/ +diff -Nur linux-2.6.39.orig/crypto/ocf/safe/safe.c linux-2.6.39/crypto/ocf/safe/safe.c +--- linux-2.6.39.orig/crypto/ocf/safe/safe.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/safe/safe.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,2288 @@ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2004-2010 David McCullough ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2003 Sam Leffler, Errno Consulting ++ * Copyright (c) 2003 Global Technology Associates, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++__FBSDID("$FreeBSD: src/sys/dev/safe/safe.c,v 1.18 2007/03/21 03:42:50 sam Exp $"); ++ */ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * SafeNet SafeXcel-1141 hardware crypto accelerator ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#if 1 ++#define DPRINTF(a) do { \ ++ if (debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_dev) : "safe"); \ ++ printk a; \ ++ } \ ++ } while (0) ++#else ++#define DPRINTF(a) ++#endif ++ ++/* ++ * until we find a cleaner way, include the BSD md5/sha1 code ++ * here ++ */ ++#define HMAC_HACK 1 ++#ifdef HMAC_HACK ++#define LITTLE_ENDIAN 1234 ++#define BIG_ENDIAN 4321 ++#ifdef __LITTLE_ENDIAN ++#define BYTE_ORDER LITTLE_ENDIAN ++#endif ++#ifdef __BIG_ENDIAN ++#define BYTE_ORDER BIG_ENDIAN ++#endif ++#include ++#include ++#include ++#include ++ ++u_int8_t hmac_ipad_buffer[64] = { ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36 ++}; ++ ++u_int8_t hmac_opad_buffer[64] = { ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C ++}; ++#endif /* HMAC_HACK */ ++ ++/* add proc entry for this */ ++struct safe_stats safestats; ++ ++#define debug safe_debug ++int safe_debug = 0; ++module_param(safe_debug, int, 0644); ++MODULE_PARM_DESC(safe_debug, "Enable debug"); ++ ++static void safe_callback(struct safe_softc *, struct safe_ringentry *); ++static void safe_feed(struct safe_softc *, struct safe_ringentry *); ++#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) ++static void safe_rng_init(struct safe_softc *); ++int safe_rngbufsize = 8; /* 32 bytes each read */ ++module_param(safe_rngbufsize, int, 0644); ++MODULE_PARM_DESC(safe_rngbufsize, "RNG polling buffer size (32-bit words)"); ++int safe_rngmaxalarm = 8; /* max alarms before reset */ ++module_param(safe_rngmaxalarm, int, 0644); ++MODULE_PARM_DESC(safe_rngmaxalarm, "RNG max alarms before reset"); ++#endif /* SAFE_NO_RNG */ ++ ++static void safe_totalreset(struct safe_softc *sc); ++static int safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op); ++static int safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op); ++static int safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re); ++static int safe_kprocess(device_t dev, struct cryptkop *krp, int hint); ++static int safe_kstart(struct safe_softc *sc); ++static int safe_ksigbits(struct safe_softc *sc, struct crparam *cr); ++static void safe_kfeed(struct safe_softc *sc); ++static void safe_kpoll(unsigned long arg); ++static void safe_kload_reg(struct safe_softc *sc, u_int32_t off, ++ u_int32_t len, struct crparam *n); ++ ++static int safe_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int safe_freesession(device_t, u_int64_t); ++static int safe_process(device_t, struct cryptop *, int); ++ ++static device_method_t safe_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, safe_newsession), ++ DEVMETHOD(cryptodev_freesession,safe_freesession), ++ DEVMETHOD(cryptodev_process, safe_process), ++ DEVMETHOD(cryptodev_kprocess, safe_kprocess), ++}; ++ ++#define READ_REG(sc,r) readl((sc)->sc_base_addr + (r)) ++#define WRITE_REG(sc,r,val) writel((val), (sc)->sc_base_addr + (r)) ++ ++#define SAFE_MAX_CHIPS 8 ++static struct safe_softc *safe_chip_idx[SAFE_MAX_CHIPS]; ++ ++/* ++ * split our buffers up into safe DMAable byte fragments to avoid lockup ++ * bug in 1141 HW on rev 1.0. ++ */ ++ ++static int ++pci_map_linear( ++ struct safe_softc *sc, ++ struct safe_operand *buf, ++ void *addr, ++ int len) ++{ ++ dma_addr_t tmp; ++ int chunk, tlen = len; ++ ++ tmp = pci_map_single(sc->sc_pcidev, addr, len, PCI_DMA_BIDIRECTIONAL); ++ ++ buf->mapsize += len; ++ while (len > 0) { ++ chunk = (len > sc->sc_max_dsize) ? sc->sc_max_dsize : len; ++ buf->segs[buf->nsegs].ds_addr = tmp; ++ buf->segs[buf->nsegs].ds_len = chunk; ++ buf->segs[buf->nsegs].ds_tlen = tlen; ++ buf->nsegs++; ++ tmp += chunk; ++ len -= chunk; ++ tlen = 0; ++ } ++ return 0; ++} ++ ++/* ++ * map in a given uio buffer (great on some arches :-) ++ */ ++ ++static int ++pci_map_uio(struct safe_softc *sc, struct safe_operand *buf, struct uio *uio) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int n; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ buf->mapsize = 0; ++ buf->nsegs = 0; ++ ++ for (n = 0; n < uio->uio_iovcnt; n++) { ++ pci_map_linear(sc, buf, iov->iov_base, iov->iov_len); ++ iov++; ++ } ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++/* ++ * map in a given sk_buff ++ */ ++ ++static int ++pci_map_skb(struct safe_softc *sc,struct safe_operand *buf,struct sk_buff *skb) ++{ ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ buf->mapsize = 0; ++ buf->nsegs = 0; ++ ++ pci_map_linear(sc, buf, skb->data, skb_headlen(skb)); ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { ++ pci_map_linear(sc, buf, ++ page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ skb_shinfo(skb)->frags[i].size); ++ } ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++ ++#if 0 /* not needed at this time */ ++static void ++pci_sync_operand(struct safe_softc *sc, struct safe_operand *buf) ++{ ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ for (i = 0; i < buf->nsegs; i++) ++ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); ++} ++#endif ++ ++static void ++pci_unmap_operand(struct safe_softc *sc, struct safe_operand *buf) ++{ ++ int i; ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ for (i = 0; i < buf->nsegs; i++) { ++ if (buf->segs[i].ds_tlen) { ++ DPRINTF(("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); ++ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_tlen, PCI_DMA_BIDIRECTIONAL); ++ DPRINTF(("%s - unmap %d 0x%x %d done\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); ++ } ++ buf->segs[i].ds_addr = 0; ++ buf->segs[i].ds_len = 0; ++ buf->segs[i].ds_tlen = 0; ++ } ++ buf->nsegs = 0; ++ buf->mapsize = 0; ++ buf->map = 0; ++} ++ ++ ++/* ++ * SafeXcel Interrupt routine ++ */ ++static irqreturn_t ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++safe_intr(int irq, void *arg) ++#else ++safe_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct safe_softc *sc = arg; ++ int stat; ++ unsigned long flags; ++ ++ stat = READ_REG(sc, SAFE_HM_STAT); ++ ++ DPRINTF(("%s(stat=0x%x)\n", __FUNCTION__, stat)); ++ ++ if (stat == 0) /* shared irq, not for us */ ++ return IRQ_NONE; ++ ++ WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ ++ ++ if ((stat & SAFE_INT_PE_DDONE)) { ++ /* ++ * Descriptor(s) done; scan the ring and ++ * process completed operations. ++ */ ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ while (sc->sc_back != sc->sc_front) { ++ struct safe_ringentry *re = sc->sc_back; ++ ++#ifdef SAFE_DEBUG ++ if (debug) { ++ safe_dump_ringstate(sc, __func__); ++ safe_dump_request(sc, __func__, re); ++ } ++#endif ++ /* ++ * safe_process marks ring entries that were allocated ++ * but not used with a csr of zero. This insures the ++ * ring front pointer never needs to be set backwards ++ * in the event that an entry is allocated but not used ++ * because of a setup error. ++ */ ++ DPRINTF(("%s re->re_desc.d_csr=0x%x\n", __FUNCTION__, re->re_desc.d_csr)); ++ if (re->re_desc.d_csr != 0) { ++ if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) { ++ DPRINTF(("%s !CSR_IS_DONE\n", __FUNCTION__)); ++ break; ++ } ++ if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) { ++ DPRINTF(("%s !LEN_IS_DONE\n", __FUNCTION__)); ++ break; ++ } ++ sc->sc_nqchip--; ++ safe_callback(sc, re); ++ } ++ if (++(sc->sc_back) == sc->sc_ringtop) ++ sc->sc_back = sc->sc_ring; ++ } ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ } ++ ++ /* ++ * Check to see if we got any DMA Error ++ */ ++ if (stat & SAFE_INT_PE_ERROR) { ++ printk("%s: dmaerr dmastat %08x\n", device_get_nameunit(sc->sc_dev), ++ (int)READ_REG(sc, SAFE_PE_DMASTAT)); ++ safestats.st_dmaerr++; ++ safe_totalreset(sc); ++#if 0 ++ safe_feed(sc); ++#endif ++ } ++ ++ if (sc->sc_needwakeup) { /* XXX check high watermark */ ++ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); ++ DPRINTF(("%s: wakeup crypto %x\n", __func__, ++ sc->sc_needwakeup)); ++ sc->sc_needwakeup &= ~wakeup; ++ crypto_unblock(sc->sc_cid, wakeup); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * safe_feed() - post a request to chip ++ */ ++static void ++safe_feed(struct safe_softc *sc, struct safe_ringentry *re) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++#ifdef SAFE_DEBUG ++ if (debug) { ++ safe_dump_ringstate(sc, __func__); ++ safe_dump_request(sc, __func__, re); ++ } ++#endif ++ sc->sc_nqchip++; ++ if (sc->sc_nqchip > safestats.st_maxqchip) ++ safestats.st_maxqchip = sc->sc_nqchip; ++ /* poke h/w to check descriptor ring, any value can be written */ ++ WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); ++} ++ ++#define N(a) (sizeof(a) / sizeof (a[0])) ++static void ++safe_setup_enckey(struct safe_session *ses, caddr_t key) ++{ ++ int i; ++ ++ bcopy(key, ses->ses_key, ses->ses_klen / 8); ++ ++ /* PE is little-endian, insure proper byte order */ ++ for (i = 0; i < N(ses->ses_key); i++) ++ ses->ses_key[i] = htole32(ses->ses_key[i]); ++} ++ ++static void ++safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) ++{ ++#ifdef HMAC_HACK ++ MD5_CTX md5ctx; ++ SHA1_CTX sha1ctx; ++ int i; ++ ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_IPAD_VAL; ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_ipad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_opad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_OPAD_VAL; ++ ++#if 0 ++ /* ++ * this code prevents SHA working on a BE host, ++ * so it is obviously wrong. I think the byte ++ * swap setup we do with the chip fixes this for us ++ */ ++ ++ /* PE is little-endian, insure proper byte order */ ++ for (i = 0; i < N(ses->ses_hminner); i++) { ++ ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); ++ ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); ++ } ++#endif ++#else /* HMAC_HACK */ ++ printk("safe: md5/sha not implemented\n"); ++#endif /* HMAC_HACK */ ++} ++#undef N ++ ++/* ++ * Allocate a new 'session' and return an encoded session id. 'sidp' ++ * contains our registration id, and should contain an encoded session ++ * id on successful allocation. ++ */ ++static int ++safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct safe_session *ses = NULL; ++ int sesn; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sidp == NULL || cri == NULL || sc == NULL) ++ return (EINVAL); ++ ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1_HMAC || ++ c->cri_alg == CRYPTO_NULL_HMAC) { ++ if (macini) ++ return (EINVAL); ++ macini = c; ++ } else if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC || ++ c->cri_alg == CRYPTO_NULL_CBC) { ++ if (encini) ++ return (EINVAL); ++ encini = c; ++ } else ++ return (EINVAL); ++ } ++ if (encini == NULL && macini == NULL) ++ return (EINVAL); ++ if (encini) { /* validate key length */ ++ switch (encini->cri_alg) { ++ case CRYPTO_DES_CBC: ++ if (encini->cri_klen != 64) ++ return (EINVAL); ++ break; ++ case CRYPTO_3DES_CBC: ++ if (encini->cri_klen != 192) ++ return (EINVAL); ++ break; ++ case CRYPTO_AES_CBC: ++ if (encini->cri_klen != 128 && ++ encini->cri_klen != 192 && ++ encini->cri_klen != 256) ++ return (EINVAL); ++ break; ++ } ++ } ++ ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct safe_session *) ++ kmalloc(sizeof(struct safe_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, sizeof(struct safe_session)); ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn].ses_used == 0) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sesn = sc->sc_nsessions; ++ ses = (struct safe_session *) ++ kmalloc((sesn + 1) * sizeof(struct safe_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, (sesn + 1) * sizeof(struct safe_session)); ++ bcopy(sc->sc_sessions, ses, sesn * ++ sizeof(struct safe_session)); ++ bzero(sc->sc_sessions, sesn * ++ sizeof(struct safe_session)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ ++ bzero(ses, sizeof(struct safe_session)); ++ ses->ses_used = 1; ++ ++ if (encini) { ++ /* get an IV */ ++ /* XXX may read fewer than requested */ ++ read_random(ses->ses_iv, sizeof(ses->ses_iv)); ++ ++ ses->ses_klen = encini->cri_klen; ++ if (encini->cri_key != NULL) ++ safe_setup_enckey(ses, encini->cri_key); ++ } ++ ++ if (macini) { ++ ses->ses_mlen = macini->cri_mlen; ++ if (ses->ses_mlen == 0) { ++ if (macini->cri_alg == CRYPTO_MD5_HMAC) ++ ses->ses_mlen = MD5_HASH_LEN; ++ else ++ ses->ses_mlen = SHA1_HASH_LEN; ++ } ++ ++ if (macini->cri_key != NULL) { ++ safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, ++ macini->cri_klen / 8); ++ } ++ } ++ ++ *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); ++ return (0); ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++safe_freesession(device_t dev, u_int64_t tid) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ int session, ret; ++ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sc == NULL) ++ return (EINVAL); ++ ++ session = SAFE_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); ++ ret = 0; ++ } else ++ ret = EINVAL; ++ return (ret); ++} ++ ++ ++static int ++safe_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ int err = 0, i, nicealign, uniform; ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ int bypass, oplen, ivsize; ++ caddr_t iv; ++ int16_t coffset; ++ struct safe_session *ses; ++ struct safe_ringentry *re; ++ struct safe_sarec *sa; ++ struct safe_pdesc *pd; ++ u_int32_t cmd0, cmd1, staterec; ++ unsigned long flags; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { ++ safestats.st_invalid++; ++ return (EINVAL); ++ } ++ if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { ++ safestats.st_badsession++; ++ return (EINVAL); ++ } ++ ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { ++ safestats.st_ringfull++; ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ return (ERESTART); ++ } ++ re = sc->sc_front; ++ ++ staterec = re->re_sa.sa_staterec; /* save */ ++ /* NB: zero everything but the PE descriptor */ ++ bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); ++ re->re_sa.sa_staterec = staterec; /* restore */ ++ ++ re->re_crp = crp; ++ re->re_sesn = SAFE_SESSION(crp->crp_sid); ++ ++ re->re_src.nsegs = 0; ++ re->re_dst.nsegs = 0; ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ re->re_src_skb = (struct sk_buff *)crp->crp_buf; ++ re->re_dst_skb = (struct sk_buff *)crp->crp_buf; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ re->re_src_io = (struct uio *)crp->crp_buf; ++ re->re_dst_io = (struct uio *)crp->crp_buf; ++ } else { ++ safestats.st_badflags++; ++ err = EINVAL; ++ goto errout; /* XXX we don't handle contiguous blocks! */ ++ } ++ ++ sa = &re->re_sa; ++ ses = &sc->sc_sessions[re->re_sesn]; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ safestats.st_nodesc++; ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ ++ cmd1 = 0; ++ if (crd2 == NULL) { ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_NULL_HMAC) { ++ maccrd = crd1; ++ enccrd = NULL; ++ cmd0 |= SAFE_SA_CMD0_OP_HASH; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_NULL_CBC) { ++ maccrd = NULL; ++ enccrd = crd1; ++ cmd0 |= SAFE_SA_CMD0_OP_CRYPT; ++ } else { ++ safestats.st_badalg++; ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_NULL_HMAC) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC || ++ crd2->crd_alg == CRYPTO_NULL_CBC) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_NULL_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC || ++ crd2->crd_alg == CRYPTO_NULL_HMAC) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ safestats.st_badalg++; ++ err = EINVAL; ++ goto errout; ++ } ++ cmd0 |= SAFE_SA_CMD0_OP_BOTH; ++ } ++ ++ if (enccrd) { ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) ++ safe_setup_enckey(ses, enccrd->crd_key); ++ ++ if (enccrd->crd_alg == CRYPTO_DES_CBC) { ++ cmd0 |= SAFE_SA_CMD0_DES; ++ cmd1 |= SAFE_SA_CMD1_CBC; ++ ivsize = 2*sizeof(u_int32_t); ++ } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { ++ cmd0 |= SAFE_SA_CMD0_3DES; ++ cmd1 |= SAFE_SA_CMD1_CBC; ++ ivsize = 2*sizeof(u_int32_t); ++ } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { ++ cmd0 |= SAFE_SA_CMD0_AES; ++ cmd1 |= SAFE_SA_CMD1_CBC; ++ if (ses->ses_klen == 128) ++ cmd1 |= SAFE_SA_CMD1_AES128; ++ else if (ses->ses_klen == 192) ++ cmd1 |= SAFE_SA_CMD1_AES192; ++ else ++ cmd1 |= SAFE_SA_CMD1_AES256; ++ ivsize = 4*sizeof(u_int32_t); ++ } else { ++ cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; ++ ivsize = 0; ++ } ++ ++ /* ++ * Setup encrypt/decrypt state. When using basic ops ++ * we can't use an inline IV because hash/crypt offset ++ * must be from the end of the IV to the start of the ++ * crypt data and this leaves out the preceding header ++ * from the hash calculation. Instead we place the IV ++ * in the state record and set the hash/crypt offset to ++ * copy both the header+IV. ++ */ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ cmd0 |= SAFE_SA_CMD0_OUTBOUND; ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ iv = enccrd->crd_iv; ++ else ++ iv = (caddr_t) ses->ses_iv; ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, iv); ++ } ++ bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); ++ /* make iv LE */ ++ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) ++ re->re_sastate.sa_saved_iv[i] = ++ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); ++ cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; ++ re->re_flags |= SAFE_QFLAGS_COPYOUTIV; ++ } else { ++ cmd0 |= SAFE_SA_CMD0_INBOUND; ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ bcopy(enccrd->crd_iv, ++ re->re_sastate.sa_saved_iv, ivsize); ++ } else { ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, ++ (caddr_t)re->re_sastate.sa_saved_iv); ++ } ++ /* make iv LE */ ++ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) ++ re->re_sastate.sa_saved_iv[i] = ++ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); ++ cmd0 |= SAFE_SA_CMD0_IVLD_STATE; ++ } ++ /* ++ * For basic encryption use the zero pad algorithm. ++ * This pads results to an 8-byte boundary and ++ * suppresses padding verification for inbound (i.e. ++ * decrypt) operations. ++ * ++ * NB: Not sure if the 8-byte pad boundary is a problem. ++ */ ++ cmd0 |= SAFE_SA_CMD0_PAD_ZERO; ++ ++ /* XXX assert key bufs have the same size */ ++ bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); ++ } ++ ++ if (maccrd) { ++ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ safe_setup_mackey(ses, maccrd->crd_alg, ++ maccrd->crd_key, maccrd->crd_klen / 8); ++ } ++ ++ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { ++ cmd0 |= SAFE_SA_CMD0_MD5; ++ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ ++ } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { ++ cmd0 |= SAFE_SA_CMD0_SHA1; ++ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ ++ } else { ++ cmd0 |= SAFE_SA_CMD0_HASH_NULL; ++ } ++ /* ++ * Digest data is loaded from the SA and the hash ++ * result is saved to the state block where we ++ * retrieve it for return to the caller. ++ */ ++ /* XXX assert digest bufs have the same size */ ++ bcopy(ses->ses_hminner, sa->sa_indigest, ++ sizeof(sa->sa_indigest)); ++ bcopy(ses->ses_hmouter, sa->sa_outdigest, ++ sizeof(sa->sa_outdigest)); ++ ++ cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; ++ re->re_flags |= SAFE_QFLAGS_COPYOUTICV; ++ } ++ ++ if (enccrd && maccrd) { ++ /* ++ * The offset from hash data to the start of ++ * crypt data is the difference in the skips. ++ */ ++ bypass = maccrd->crd_skip; ++ coffset = enccrd->crd_skip - maccrd->crd_skip; ++ if (coffset < 0) { ++ DPRINTF(("%s: hash does not precede crypt; " ++ "mac skip %u enc skip %u\n", ++ __func__, maccrd->crd_skip, enccrd->crd_skip)); ++ safestats.st_skipmismatch++; ++ err = EINVAL; ++ goto errout; ++ } ++ oplen = enccrd->crd_skip + enccrd->crd_len; ++ if (maccrd->crd_skip + maccrd->crd_len != oplen) { ++ DPRINTF(("%s: hash amount %u != crypt amount %u\n", ++ __func__, maccrd->crd_skip + maccrd->crd_len, ++ oplen)); ++ safestats.st_lenmismatch++; ++ err = EINVAL; ++ goto errout; ++ } ++#ifdef SAFE_DEBUG ++ if (debug) { ++ printf("mac: skip %d, len %d, inject %d\n", ++ maccrd->crd_skip, maccrd->crd_len, ++ maccrd->crd_inject); ++ printf("enc: skip %d, len %d, inject %d\n", ++ enccrd->crd_skip, enccrd->crd_len, ++ enccrd->crd_inject); ++ printf("bypass %d coffset %d oplen %d\n", ++ bypass, coffset, oplen); ++ } ++#endif ++ if (coffset & 3) { /* offset must be 32-bit aligned */ ++ DPRINTF(("%s: coffset %u misaligned\n", ++ __func__, coffset)); ++ safestats.st_coffmisaligned++; ++ err = EINVAL; ++ goto errout; ++ } ++ coffset >>= 2; ++ if (coffset > 255) { /* offset must be <256 dwords */ ++ DPRINTF(("%s: coffset %u too big\n", ++ __func__, coffset)); ++ safestats.st_cofftoobig++; ++ err = EINVAL; ++ goto errout; ++ } ++ /* ++ * Tell the hardware to copy the header to the output. ++ * The header is defined as the data from the end of ++ * the bypass to the start of data to be encrypted. ++ * Typically this is the inline IV. Note that you need ++ * to do this even if src+dst are the same; it appears ++ * that w/o this bit the crypted data is written ++ * immediately after the bypass data. ++ */ ++ cmd1 |= SAFE_SA_CMD1_HDRCOPY; ++ /* ++ * Disable IP header mutable bit handling. This is ++ * needed to get correct HMAC calculations. ++ */ ++ cmd1 |= SAFE_SA_CMD1_MUTABLE; ++ } else { ++ if (enccrd) { ++ bypass = enccrd->crd_skip; ++ oplen = bypass + enccrd->crd_len; ++ } else { ++ bypass = maccrd->crd_skip; ++ oplen = bypass + maccrd->crd_len; ++ } ++ coffset = 0; ++ } ++ /* XXX verify multiple of 4 when using s/g */ ++ if (bypass > 96) { /* bypass offset must be <= 96 bytes */ ++ DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); ++ safestats.st_bypasstoobig++; ++ err = EINVAL; ++ goto errout; ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (pci_map_skb(sc, &re->re_src, re->re_src_skb)) { ++ safestats.st_noload++; ++ err = ENOMEM; ++ goto errout; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (pci_map_uio(sc, &re->re_src, re->re_src_io)) { ++ safestats.st_noload++; ++ err = ENOMEM; ++ goto errout; ++ } ++ } ++ nicealign = safe_dmamap_aligned(sc, &re->re_src); ++ uniform = safe_dmamap_uniform(sc, &re->re_src); ++ ++ DPRINTF(("src nicealign %u uniform %u nsegs %u\n", ++ nicealign, uniform, re->re_src.nsegs)); ++ if (re->re_src.nsegs > 1) { ++ re->re_desc.d_src = sc->sc_spalloc.dma_paddr + ++ ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); ++ for (i = 0; i < re->re_src_nsegs; i++) { ++ /* NB: no need to check if there's space */ ++ pd = sc->sc_spfree; ++ if (++(sc->sc_spfree) == sc->sc_springtop) ++ sc->sc_spfree = sc->sc_spring; ++ ++ KASSERT((pd->pd_flags&3) == 0 || ++ (pd->pd_flags&3) == SAFE_PD_DONE, ++ ("bogus source particle descriptor; flags %x", ++ pd->pd_flags)); ++ pd->pd_addr = re->re_src_segs[i].ds_addr; ++ pd->pd_size = re->re_src_segs[i].ds_len; ++ pd->pd_flags = SAFE_PD_READY; ++ } ++ cmd0 |= SAFE_SA_CMD0_IGATHER; ++ } else { ++ /* ++ * No need for gather, reference the operand directly. ++ */ ++ re->re_desc.d_src = re->re_src_segs[0].ds_addr; ++ } ++ ++ if (enccrd == NULL && maccrd != NULL) { ++ /* ++ * Hash op; no destination needed. ++ */ ++ } else { ++ if (crp->crp_flags & (CRYPTO_F_IOV|CRYPTO_F_SKBUF)) { ++ if (!nicealign) { ++ safestats.st_iovmisaligned++; ++ err = EINVAL; ++ goto errout; ++ } ++ if (uniform != 1) { ++ device_printf(sc->sc_dev, "!uniform source\n"); ++ if (!uniform) { ++ /* ++ * There's no way to handle the DMA ++ * requirements with this uio. We ++ * could create a separate DMA area for ++ * the result and then copy it back, ++ * but for now we just bail and return ++ * an error. Note that uio requests ++ * > SAFE_MAX_DSIZE are handled because ++ * the DMA map and segment list for the ++ * destination wil result in a ++ * destination particle list that does ++ * the necessary scatter DMA. ++ */ ++ safestats.st_iovnotuniform++; ++ err = EINVAL; ++ goto errout; ++ } ++ } else ++ re->re_dst = re->re_src; ++ } else { ++ safestats.st_badflags++; ++ err = EINVAL; ++ goto errout; ++ } ++ ++ if (re->re_dst.nsegs > 1) { ++ re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + ++ ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); ++ for (i = 0; i < re->re_dst_nsegs; i++) { ++ pd = sc->sc_dpfree; ++ KASSERT((pd->pd_flags&3) == 0 || ++ (pd->pd_flags&3) == SAFE_PD_DONE, ++ ("bogus dest particle descriptor; flags %x", ++ pd->pd_flags)); ++ if (++(sc->sc_dpfree) == sc->sc_dpringtop) ++ sc->sc_dpfree = sc->sc_dpring; ++ pd->pd_addr = re->re_dst_segs[i].ds_addr; ++ pd->pd_flags = SAFE_PD_READY; ++ } ++ cmd0 |= SAFE_SA_CMD0_OSCATTER; ++ } else { ++ /* ++ * No need for scatter, reference the operand directly. ++ */ ++ re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; ++ } ++ } ++ ++ /* ++ * All done with setup; fillin the SA command words ++ * and the packet engine descriptor. The operation ++ * is now ready for submission to the hardware. ++ */ ++ sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; ++ sa->sa_cmd1 = cmd1 ++ | (coffset << SAFE_SA_CMD1_OFFSET_S) ++ | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ ++ | SAFE_SA_CMD1_SRPCI ++ ; ++ /* ++ * NB: the order of writes is important here. In case the ++ * chip is scanning the ring because of an outstanding request ++ * it might nab this one too. In that case we need to make ++ * sure the setup is complete before we write the length ++ * field of the descriptor as it signals the descriptor is ++ * ready for processing. ++ */ ++ re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; ++ if (maccrd) ++ re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; ++ wmb(); ++ re->re_desc.d_len = oplen ++ | SAFE_PE_LEN_READY ++ | (bypass << SAFE_PE_LEN_BYPASS_S) ++ ; ++ ++ safestats.st_ipackets++; ++ safestats.st_ibytes += oplen; ++ ++ if (++(sc->sc_front) == sc->sc_ringtop) ++ sc->sc_front = sc->sc_ring; ++ ++ /* XXX honor batching */ ++ safe_feed(sc, re); ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ return (0); ++ ++errout: ++ if (re->re_src.map != re->re_dst.map) ++ pci_unmap_operand(sc, &re->re_dst); ++ if (re->re_src.map) ++ pci_unmap_operand(sc, &re->re_src); ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ if (err != ERESTART) { ++ crp->crp_etype = err; ++ crypto_done(crp); ++ } else { ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ } ++ return (err); ++} ++ ++static void ++safe_callback(struct safe_softc *sc, struct safe_ringentry *re) ++{ ++ struct cryptop *crp = (struct cryptop *)re->re_crp; ++ struct cryptodesc *crd; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ safestats.st_opackets++; ++ safestats.st_obytes += re->re_dst.mapsize; ++ ++ if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { ++ device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", ++ re->re_desc.d_csr, ++ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); ++ safestats.st_peoperr++; ++ crp->crp_etype = EIO; /* something more meaningful? */ ++ } ++ ++ if (re->re_dst.map != NULL && re->re_dst.map != re->re_src.map) ++ pci_unmap_operand(sc, &re->re_dst); ++ pci_unmap_operand(sc, &re->re_src); ++ ++ /* ++ * If result was written to a differet mbuf chain, swap ++ * it in as the return value and reclaim the original. ++ */ ++ if ((crp->crp_flags & CRYPTO_F_SKBUF) && re->re_src_skb != re->re_dst_skb) { ++ device_printf(sc->sc_dev, "no CRYPTO_F_SKBUF swapping support\n"); ++ /* kfree_skb(skb) */ ++ /* crp->crp_buf = (caddr_t)re->re_dst_skb */ ++ return; ++ } ++ ++ if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { ++ /* copy out IV for future use */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ int i; ++ int ivsize; ++ ++ if (crd->crd_alg == CRYPTO_DES_CBC || ++ crd->crd_alg == CRYPTO_3DES_CBC) { ++ ivsize = 2*sizeof(u_int32_t); ++ } else if (crd->crd_alg == CRYPTO_AES_CBC) { ++ ivsize = 4*sizeof(u_int32_t); ++ } else ++ continue; ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ crd->crd_skip + crd->crd_len - ivsize, ivsize, ++ (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); ++ for (i = 0; ++ i < ivsize/sizeof(sc->sc_sessions[re->re_sesn].ses_iv[0]); ++ i++) ++ sc->sc_sessions[re->re_sesn].ses_iv[i] = ++ cpu_to_le32(sc->sc_sessions[re->re_sesn].ses_iv[i]); ++ break; ++ } ++ } ++ ++ if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { ++ /* copy out ICV result */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ if (!(crd->crd_alg == CRYPTO_MD5_HMAC || ++ crd->crd_alg == CRYPTO_SHA1_HMAC || ++ crd->crd_alg == CRYPTO_NULL_HMAC)) ++ continue; ++ if (crd->crd_alg == CRYPTO_SHA1_HMAC) { ++ /* ++ * SHA-1 ICV's are byte-swapped; fix 'em up ++ * before copy them to their destination. ++ */ ++ re->re_sastate.sa_saved_indigest[0] = ++ cpu_to_be32(re->re_sastate.sa_saved_indigest[0]); ++ re->re_sastate.sa_saved_indigest[1] = ++ cpu_to_be32(re->re_sastate.sa_saved_indigest[1]); ++ re->re_sastate.sa_saved_indigest[2] = ++ cpu_to_be32(re->re_sastate.sa_saved_indigest[2]); ++ } else { ++ re->re_sastate.sa_saved_indigest[0] = ++ cpu_to_le32(re->re_sastate.sa_saved_indigest[0]); ++ re->re_sastate.sa_saved_indigest[1] = ++ cpu_to_le32(re->re_sastate.sa_saved_indigest[1]); ++ re->re_sastate.sa_saved_indigest[2] = ++ cpu_to_le32(re->re_sastate.sa_saved_indigest[2]); ++ } ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ++ sc->sc_sessions[re->re_sesn].ses_mlen, ++ (caddr_t)re->re_sastate.sa_saved_indigest); ++ break; ++ } ++ } ++ crypto_done(crp); ++} ++ ++ ++#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) ++#define SAFE_RNG_MAXWAIT 1000 ++ ++static void ++safe_rng_init(struct safe_softc *sc) ++{ ++ u_int32_t w, v; ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ WRITE_REG(sc, SAFE_RNG_CTRL, 0); ++ /* use default value according to the manual */ ++ WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ ++ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); ++ ++ /* ++ * There is a bug in rev 1.0 of the 1140 that when the RNG ++ * is brought out of reset the ready status flag does not ++ * work until the RNG has finished its internal initialization. ++ * ++ * So in order to determine the device is through its ++ * initialization we must read the data register, using the ++ * status reg in the read in case it is initialized. Then read ++ * the data register until it changes from the first read. ++ * Once it changes read the data register until it changes ++ * again. At this time the RNG is considered initialized. ++ * This could take between 750ms - 1000ms in time. ++ */ ++ i = 0; ++ w = READ_REG(sc, SAFE_RNG_OUT); ++ do { ++ v = READ_REG(sc, SAFE_RNG_OUT); ++ if (v != w) { ++ w = v; ++ break; ++ } ++ DELAY(10); ++ } while (++i < SAFE_RNG_MAXWAIT); ++ ++ /* Wait Until data changes again */ ++ i = 0; ++ do { ++ v = READ_REG(sc, SAFE_RNG_OUT); ++ if (v != w) ++ break; ++ DELAY(10); ++ } while (++i < SAFE_RNG_MAXWAIT); ++} ++ ++static __inline void ++safe_rng_disable_short_cycle(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ WRITE_REG(sc, SAFE_RNG_CTRL, ++ READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); ++} ++ ++static __inline void ++safe_rng_enable_short_cycle(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ WRITE_REG(sc, SAFE_RNG_CTRL, ++ READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); ++} ++ ++static __inline u_int32_t ++safe_rng_read(struct safe_softc *sc) ++{ ++ int i; ++ ++ i = 0; ++ while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) ++ ; ++ return READ_REG(sc, SAFE_RNG_OUT); ++} ++ ++static int ++safe_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ struct safe_softc *sc = (struct safe_softc *) arg; ++ int i, rc; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ safestats.st_rng++; ++ /* ++ * Fetch the next block of data. ++ */ ++ if (maxwords > safe_rngbufsize) ++ maxwords = safe_rngbufsize; ++ if (maxwords > SAFE_RNG_MAXBUFSIZ) ++ maxwords = SAFE_RNG_MAXBUFSIZ; ++retry: ++ /* read as much as we can */ ++ for (rc = 0; rc < maxwords; rc++) { ++ if (READ_REG(sc, SAFE_RNG_STAT) != 0) ++ break; ++ buf[rc] = READ_REG(sc, SAFE_RNG_OUT); ++ } ++ if (rc == 0) ++ return 0; ++ /* ++ * Check the comparator alarm count and reset the h/w if ++ * it exceeds our threshold. This guards against the ++ * hardware oscillators resonating with external signals. ++ */ ++ if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { ++ u_int32_t freq_inc, w; ++ ++ DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, ++ (unsigned)READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); ++ safestats.st_rngalarm++; ++ safe_rng_enable_short_cycle(sc); ++ freq_inc = 18; ++ for (i = 0; i < 64; i++) { ++ w = READ_REG(sc, SAFE_RNG_CNFG); ++ freq_inc = ((w + freq_inc) & 0x3fL); ++ w = ((w & ~0x3fL) | freq_inc); ++ WRITE_REG(sc, SAFE_RNG_CNFG, w); ++ ++ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); ++ ++ (void) safe_rng_read(sc); ++ DELAY(25); ++ ++ if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { ++ safe_rng_disable_short_cycle(sc); ++ goto retry; ++ } ++ freq_inc = 1; ++ } ++ safe_rng_disable_short_cycle(sc); ++ } else ++ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); ++ ++ return(rc); ++} ++#endif /* defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) */ ++ ++ ++/* ++ * Resets the board. Values in the regesters are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++static void ++safe_reset_board(struct safe_softc *sc) ++{ ++ u_int32_t v; ++ /* ++ * Reset the device. The manual says no delay ++ * is needed between marking and clearing reset. ++ */ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ v = READ_REG(sc, SAFE_PE_DMACFG) &~ ++ (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | ++ SAFE_PE_DMACFG_SGRESET); ++ WRITE_REG(sc, SAFE_PE_DMACFG, v ++ | SAFE_PE_DMACFG_PERESET ++ | SAFE_PE_DMACFG_PDRRESET ++ | SAFE_PE_DMACFG_SGRESET); ++ WRITE_REG(sc, SAFE_PE_DMACFG, v); ++} ++ ++/* ++ * Initialize registers we need to touch only once. ++ */ ++static void ++safe_init_board(struct safe_softc *sc) ++{ ++ u_int32_t v, dwords; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ v = READ_REG(sc, SAFE_PE_DMACFG); ++ v &=~ ( SAFE_PE_DMACFG_PEMODE ++ | SAFE_PE_DMACFG_FSENA /* failsafe enable */ ++ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ ++ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ ++ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ ++ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ ++ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ ++ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ ++ ); ++ v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ ++ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ ++ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ ++ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ ++ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ ++ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ ++#if 0 ++ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ ++#endif ++ ; ++ WRITE_REG(sc, SAFE_PE_DMACFG, v); ++ ++#ifdef __BIG_ENDIAN ++ /* tell the safenet that we are 4321 and not 1234 */ ++ WRITE_REG(sc, SAFE_ENDIAN, 0xe4e41b1b); ++#endif ++ ++ if (sc->sc_chiprev == SAFE_REV(1,0)) { ++ /* ++ * Avoid large PCI DMA transfers. Rev 1.0 has a bug where ++ * "target mode transfers" done while the chip is DMA'ing ++ * >1020 bytes cause the hardware to lockup. To avoid this ++ * we reduce the max PCI transfer size and use small source ++ * particle descriptors (<= 256 bytes). ++ */ ++ WRITE_REG(sc, SAFE_DMA_CFG, 256); ++ device_printf(sc->sc_dev, ++ "Reduce max DMA size to %u words for rev %u.%u WAR\n", ++ (unsigned) ((READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff), ++ (unsigned) SAFE_REV_MAJ(sc->sc_chiprev), ++ (unsigned) SAFE_REV_MIN(sc->sc_chiprev)); ++ sc->sc_max_dsize = 256; ++ } else { ++ sc->sc_max_dsize = SAFE_MAX_DSIZE; ++ } ++ ++ /* NB: operands+results are overlaid */ ++ WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); ++ WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); ++ /* ++ * Configure ring entry size and number of items in the ring. ++ */ ++ KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, ++ ("PE ring entry not 32-bit aligned!")); ++ dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); ++ WRITE_REG(sc, SAFE_PE_RINGCFG, ++ (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); ++ WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ ++ ++ WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); ++ WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); ++ WRITE_REG(sc, SAFE_PE_PARTSIZE, ++ (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); ++ /* ++ * NB: destination particles are fixed size. We use ++ * an mbuf cluster and require all results go to ++ * clusters or smaller. ++ */ ++ WRITE_REG(sc, SAFE_PE_PARTCFG, sc->sc_max_dsize); ++ ++ /* it's now safe to enable PE mode, do it */ ++ WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); ++ ++ /* ++ * Configure hardware to use level-triggered interrupts and ++ * to interrupt after each descriptor is processed. ++ */ ++ WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); ++ WRITE_REG(sc, SAFE_HI_CLR, 0xffffffff); ++ WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); ++ WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); ++} ++ ++ ++/* ++ * Clean up after a chip crash. ++ * It is assumed that the caller in splimp() ++ */ ++static void ++safe_cleanchip(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sc->sc_nqchip != 0) { ++ struct safe_ringentry *re = sc->sc_back; ++ ++ while (re != sc->sc_front) { ++ if (re->re_desc.d_csr != 0) ++ safe_free_entry(sc, re); ++ if (++re == sc->sc_ringtop) ++ re = sc->sc_ring; ++ } ++ sc->sc_back = re; ++ sc->sc_nqchip = 0; ++ } ++} ++ ++/* ++ * free a safe_q ++ * It is assumed that the caller is within splimp(). ++ */ ++static int ++safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) ++{ ++ struct cryptop *crp; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ /* ++ * Free header MCR ++ */ ++ if ((re->re_dst_skb != NULL) && (re->re_src_skb != re->re_dst_skb)) ++#ifdef NOTYET ++ m_freem(re->re_dst_m); ++#else ++ printk("%s,%d: SKB not supported\n", __FILE__, __LINE__); ++#endif ++ ++ crp = (struct cryptop *)re->re_crp; ++ ++ re->re_desc.d_csr = 0; ++ ++ crp->crp_etype = EFAULT; ++ crypto_done(crp); ++ return(0); ++} ++ ++/* ++ * Routine to reset the chip and clean up. ++ * It is assumed that the caller is in splimp() ++ */ ++static void ++safe_totalreset(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ safe_reset_board(sc); ++ safe_init_board(sc); ++ safe_cleanchip(sc); ++} ++ ++/* ++ * Is the operand suitable aligned for direct DMA. Each ++ * segment must be aligned on a 32-bit boundary and all ++ * but the last segment must be a multiple of 4 bytes. ++ */ ++static int ++safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op) ++{ ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ for (i = 0; i < op->nsegs; i++) { ++ if (op->segs[i].ds_addr & 3) ++ return (0); ++ if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) ++ return (0); ++ } ++ return (1); ++} ++ ++/* ++ * Is the operand suitable for direct DMA as the destination ++ * of an operation. The hardware requires that each ``particle'' ++ * but the last in an operation result have the same size. We ++ * fix that size at SAFE_MAX_DSIZE bytes. This routine returns ++ * 0 if some segment is not a multiple of of this size, 1 if all ++ * segments are exactly this size, or 2 if segments are at worst ++ * a multple of this size. ++ */ ++static int ++safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op) ++{ ++ int result = 1; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (op->nsegs > 0) { ++ int i; ++ ++ for (i = 0; i < op->nsegs-1; i++) { ++ if (op->segs[i].ds_len % sc->sc_max_dsize) ++ return (0); ++ if (op->segs[i].ds_len != sc->sc_max_dsize) ++ result = 2; ++ } ++ } ++ return (result); ++} ++ ++static int ++safe_kprocess(device_t dev, struct cryptkop *krp, int hint) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ struct safe_pkq *q; ++ unsigned long flags; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sc == NULL) { ++ krp->krp_status = EINVAL; ++ goto err; ++ } ++ ++ if (krp->krp_op != CRK_MOD_EXP) { ++ krp->krp_status = EOPNOTSUPP; ++ goto err; ++ } ++ ++ q = (struct safe_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); ++ if (q == NULL) { ++ krp->krp_status = ENOMEM; ++ goto err; ++ } ++ memset(q, 0, sizeof(*q)); ++ q->pkq_krp = krp; ++ INIT_LIST_HEAD(&q->pkq_list); ++ ++ spin_lock_irqsave(&sc->sc_pkmtx, flags); ++ list_add_tail(&q->pkq_list, &sc->sc_pkq); ++ safe_kfeed(sc); ++ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); ++ return (0); ++ ++err: ++ crypto_kdone(krp); ++ return (0); ++} ++ ++#define SAFE_CRK_PARAM_BASE 0 ++#define SAFE_CRK_PARAM_EXP 1 ++#define SAFE_CRK_PARAM_MOD 2 ++ ++static int ++safe_kstart(struct safe_softc *sc) ++{ ++ struct cryptkop *krp = sc->sc_pkq_cur->pkq_krp; ++ int exp_bits, mod_bits, base_bits; ++ u_int32_t op, a_off, b_off, c_off, d_off; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (krp->krp_iparams < 3 || krp->krp_oparams != 1) { ++ krp->krp_status = EINVAL; ++ return (1); ++ } ++ ++ base_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_BASE]); ++ if (base_bits > 2048) ++ goto too_big; ++ if (base_bits <= 0) /* 5. base not zero */ ++ goto too_small; ++ ++ exp_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_EXP]); ++ if (exp_bits > 2048) ++ goto too_big; ++ if (exp_bits <= 0) /* 1. exponent word length > 0 */ ++ goto too_small; /* 4. exponent not zero */ ++ ++ mod_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_MOD]); ++ if (mod_bits > 2048) ++ goto too_big; ++ if (mod_bits <= 32) /* 2. modulus word length > 1 */ ++ goto too_small; /* 8. MSW of modulus != zero */ ++ if (mod_bits < exp_bits) /* 3 modulus len >= exponent len */ ++ goto too_small; ++ if ((krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p[0] & 1) == 0) ++ goto bad_domain; /* 6. modulus is odd */ ++ if (mod_bits > krp->krp_param[krp->krp_iparams].crp_nbits) ++ goto too_small; /* make sure result will fit */ ++ ++ /* 7. modulus > base */ ++ if (mod_bits < base_bits) ++ goto too_small; ++ if (mod_bits == base_bits) { ++ u_int8_t *basep, *modp; ++ int i; ++ ++ basep = krp->krp_param[SAFE_CRK_PARAM_BASE].crp_p + ++ ((base_bits + 7) / 8) - 1; ++ modp = krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p + ++ ((mod_bits + 7) / 8) - 1; ++ ++ for (i = 0; i < (mod_bits + 7) / 8; i++, basep--, modp--) { ++ if (*modp < *basep) ++ goto too_small; ++ if (*modp > *basep) ++ break; ++ } ++ } ++ ++ /* And on the 9th step, he rested. */ ++ ++ WRITE_REG(sc, SAFE_PK_A_LEN, (exp_bits + 31) / 32); ++ WRITE_REG(sc, SAFE_PK_B_LEN, (mod_bits + 31) / 32); ++ if (mod_bits > 1024) { ++ op = SAFE_PK_FUNC_EXP4; ++ a_off = 0x000; ++ b_off = 0x100; ++ c_off = 0x200; ++ d_off = 0x300; ++ } else { ++ op = SAFE_PK_FUNC_EXP16; ++ a_off = 0x000; ++ b_off = 0x080; ++ c_off = 0x100; ++ d_off = 0x180; ++ } ++ sc->sc_pk_reslen = b_off - a_off; ++ sc->sc_pk_resoff = d_off; ++ ++ /* A is exponent, B is modulus, C is base, D is result */ ++ safe_kload_reg(sc, a_off, b_off - a_off, ++ &krp->krp_param[SAFE_CRK_PARAM_EXP]); ++ WRITE_REG(sc, SAFE_PK_A_ADDR, a_off >> 2); ++ safe_kload_reg(sc, b_off, b_off - a_off, ++ &krp->krp_param[SAFE_CRK_PARAM_MOD]); ++ WRITE_REG(sc, SAFE_PK_B_ADDR, b_off >> 2); ++ safe_kload_reg(sc, c_off, b_off - a_off, ++ &krp->krp_param[SAFE_CRK_PARAM_BASE]); ++ WRITE_REG(sc, SAFE_PK_C_ADDR, c_off >> 2); ++ WRITE_REG(sc, SAFE_PK_D_ADDR, d_off >> 2); ++ ++ WRITE_REG(sc, SAFE_PK_FUNC, op | SAFE_PK_FUNC_RUN); ++ ++ return (0); ++ ++too_big: ++ krp->krp_status = E2BIG; ++ return (1); ++too_small: ++ krp->krp_status = ERANGE; ++ return (1); ++bad_domain: ++ krp->krp_status = EDOM; ++ return (1); ++} ++ ++static int ++safe_ksigbits(struct safe_softc *sc, struct crparam *cr) ++{ ++ u_int plen = (cr->crp_nbits + 7) / 8; ++ int i, sig = plen * 8; ++ u_int8_t c, *p = cr->crp_p; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ for (i = plen - 1; i >= 0; i--) { ++ c = p[i]; ++ if (c != 0) { ++ while ((c & 0x80) == 0) { ++ sig--; ++ c <<= 1; ++ } ++ break; ++ } ++ sig -= 8; ++ } ++ return (sig); ++} ++ ++static void ++safe_kfeed(struct safe_softc *sc) ++{ ++ struct safe_pkq *q, *tmp; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (list_empty(&sc->sc_pkq) && sc->sc_pkq_cur == NULL) ++ return; ++ if (sc->sc_pkq_cur != NULL) ++ return; ++ list_for_each_entry_safe(q, tmp, &sc->sc_pkq, pkq_list) { ++ sc->sc_pkq_cur = q; ++ list_del(&q->pkq_list); ++ if (safe_kstart(sc) != 0) { ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ sc->sc_pkq_cur = NULL; ++ } else { ++ /* op started, start polling */ ++ mod_timer(&sc->sc_pkto, jiffies + 1); ++ break; ++ } ++ } ++} ++ ++static void ++safe_kpoll(unsigned long arg) ++{ ++ struct safe_softc *sc = NULL; ++ struct safe_pkq *q; ++ struct crparam *res; ++ int i; ++ u_int32_t buf[64]; ++ unsigned long flags; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (arg >= SAFE_MAX_CHIPS) ++ return; ++ sc = safe_chip_idx[arg]; ++ if (!sc) { ++ DPRINTF(("%s() - bad callback\n", __FUNCTION__)); ++ return; ++ } ++ ++ spin_lock_irqsave(&sc->sc_pkmtx, flags); ++ if (sc->sc_pkq_cur == NULL) ++ goto out; ++ if (READ_REG(sc, SAFE_PK_FUNC) & SAFE_PK_FUNC_RUN) { ++ /* still running, check back later */ ++ mod_timer(&sc->sc_pkto, jiffies + 1); ++ goto out; ++ } ++ ++ q = sc->sc_pkq_cur; ++ res = &q->pkq_krp->krp_param[q->pkq_krp->krp_iparams]; ++ bzero(buf, sizeof(buf)); ++ bzero(res->crp_p, (res->crp_nbits + 7) / 8); ++ for (i = 0; i < sc->sc_pk_reslen >> 2; i++) ++ buf[i] = le32_to_cpu(READ_REG(sc, SAFE_PK_RAM_START + ++ sc->sc_pk_resoff + (i << 2))); ++ bcopy(buf, res->crp_p, (res->crp_nbits + 7) / 8); ++ /* ++ * reduce the bits that need copying if possible ++ */ ++ res->crp_nbits = min(res->crp_nbits,sc->sc_pk_reslen * 8); ++ res->crp_nbits = safe_ksigbits(sc, res); ++ ++ for (i = SAFE_PK_RAM_START; i < SAFE_PK_RAM_END; i += 4) ++ WRITE_REG(sc, i, 0); ++ ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ sc->sc_pkq_cur = NULL; ++ ++ safe_kfeed(sc); ++out: ++ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); ++} ++ ++static void ++safe_kload_reg(struct safe_softc *sc, u_int32_t off, u_int32_t len, ++ struct crparam *n) ++{ ++ u_int32_t buf[64], i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ bzero(buf, sizeof(buf)); ++ bcopy(n->crp_p, buf, (n->crp_nbits + 7) / 8); ++ ++ for (i = 0; i < len >> 2; i++) ++ WRITE_REG(sc, SAFE_PK_RAM_START + off + (i << 2), ++ cpu_to_le32(buf[i])); ++} ++ ++#ifdef SAFE_DEBUG ++static void ++safe_dump_dmastatus(struct safe_softc *sc, const char *tag) ++{ ++ printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" ++ , tag ++ , READ_REG(sc, SAFE_DMA_ENDIAN) ++ , READ_REG(sc, SAFE_DMA_SRCADDR) ++ , READ_REG(sc, SAFE_DMA_DSTADDR) ++ , READ_REG(sc, SAFE_DMA_STAT) ++ ); ++} ++ ++static void ++safe_dump_intrstate(struct safe_softc *sc, const char *tag) ++{ ++ printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" ++ , tag ++ , READ_REG(sc, SAFE_HI_CFG) ++ , READ_REG(sc, SAFE_HI_MASK) ++ , READ_REG(sc, SAFE_HI_DESC_CNT) ++ , READ_REG(sc, SAFE_HU_STAT) ++ , READ_REG(sc, SAFE_HM_STAT) ++ ); ++} ++ ++static void ++safe_dump_ringstate(struct safe_softc *sc, const char *tag) ++{ ++ u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); ++ ++ /* NB: assume caller has lock on ring */ ++ printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", ++ tag, ++ estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), ++ (unsigned long)(sc->sc_back - sc->sc_ring), ++ (unsigned long)(sc->sc_front - sc->sc_ring)); ++} ++ ++static void ++safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) ++{ ++ int ix, nsegs; ++ ++ ix = re - sc->sc_ring; ++ printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" ++ , tag ++ , re, ix ++ , re->re_desc.d_csr ++ , re->re_desc.d_src ++ , re->re_desc.d_dst ++ , re->re_desc.d_sa ++ , re->re_desc.d_len ++ ); ++ if (re->re_src.nsegs > 1) { ++ ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / ++ sizeof(struct safe_pdesc); ++ for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { ++ printf(" spd[%u] %p: %p size %u flags %x" ++ , ix, &sc->sc_spring[ix] ++ , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr ++ , sc->sc_spring[ix].pd_size ++ , sc->sc_spring[ix].pd_flags ++ ); ++ if (sc->sc_spring[ix].pd_size == 0) ++ printf(" (zero!)"); ++ printf("\n"); ++ if (++ix == SAFE_TOTAL_SPART) ++ ix = 0; ++ } ++ } ++ if (re->re_dst.nsegs > 1) { ++ ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / ++ sizeof(struct safe_pdesc); ++ for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { ++ printf(" dpd[%u] %p: %p flags %x\n" ++ , ix, &sc->sc_dpring[ix] ++ , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr ++ , sc->sc_dpring[ix].pd_flags ++ ); ++ if (++ix == SAFE_TOTAL_DPART) ++ ix = 0; ++ } ++ } ++ printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", ++ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); ++ printf("sa: key %x %x %x %x %x %x %x %x\n" ++ , re->re_sa.sa_key[0] ++ , re->re_sa.sa_key[1] ++ , re->re_sa.sa_key[2] ++ , re->re_sa.sa_key[3] ++ , re->re_sa.sa_key[4] ++ , re->re_sa.sa_key[5] ++ , re->re_sa.sa_key[6] ++ , re->re_sa.sa_key[7] ++ ); ++ printf("sa: indigest %x %x %x %x %x\n" ++ , re->re_sa.sa_indigest[0] ++ , re->re_sa.sa_indigest[1] ++ , re->re_sa.sa_indigest[2] ++ , re->re_sa.sa_indigest[3] ++ , re->re_sa.sa_indigest[4] ++ ); ++ printf("sa: outdigest %x %x %x %x %x\n" ++ , re->re_sa.sa_outdigest[0] ++ , re->re_sa.sa_outdigest[1] ++ , re->re_sa.sa_outdigest[2] ++ , re->re_sa.sa_outdigest[3] ++ , re->re_sa.sa_outdigest[4] ++ ); ++ printf("sr: iv %x %x %x %x\n" ++ , re->re_sastate.sa_saved_iv[0] ++ , re->re_sastate.sa_saved_iv[1] ++ , re->re_sastate.sa_saved_iv[2] ++ , re->re_sastate.sa_saved_iv[3] ++ ); ++ printf("sr: hashbc %u indigest %x %x %x %x %x\n" ++ , re->re_sastate.sa_saved_hashbc ++ , re->re_sastate.sa_saved_indigest[0] ++ , re->re_sastate.sa_saved_indigest[1] ++ , re->re_sastate.sa_saved_indigest[2] ++ , re->re_sastate.sa_saved_indigest[3] ++ , re->re_sastate.sa_saved_indigest[4] ++ ); ++} ++ ++static void ++safe_dump_ring(struct safe_softc *sc, const char *tag) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ printf("\nSafeNet Ring State:\n"); ++ safe_dump_intrstate(sc, tag); ++ safe_dump_dmastatus(sc, tag); ++ safe_dump_ringstate(sc, tag); ++ if (sc->sc_nqchip) { ++ struct safe_ringentry *re = sc->sc_back; ++ do { ++ safe_dump_request(sc, tag, re); ++ if (++re == sc->sc_ringtop) ++ re = sc->sc_ring; ++ } while (re != sc->sc_front); ++ } ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++} ++#endif /* SAFE_DEBUG */ ++ ++ ++static int safe_probe(struct pci_dev *dev, const struct pci_device_id *ent) ++{ ++ struct safe_softc *sc = NULL; ++ u32 mem_start, mem_len, cmd; ++ int i, rc, devinfo; ++ dma_addr_t raddr; ++ static int num_chips = 0; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (pci_enable_device(dev) < 0) ++ return(-ENODEV); ++ ++ if (!dev->irq) { ++ printk("safe: found device with no IRQ assigned. check BIOS settings!"); ++ pci_disable_device(dev); ++ return(-ENODEV); ++ } ++ ++ if (pci_set_mwi(dev)) { ++ printk("safe: pci_set_mwi failed!"); ++ return(-ENODEV); ++ } ++ ++ sc = (struct safe_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, "safe", num_chips, safe_methods); ++ ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++ sc->sc_pcidev = dev; ++ if (num_chips < SAFE_MAX_CHIPS) { ++ safe_chip_idx[device_get_unit(sc->sc_dev)] = sc; ++ num_chips++; ++ } ++ ++ INIT_LIST_HEAD(&sc->sc_pkq); ++ spin_lock_init(&sc->sc_pkmtx); ++ ++ pci_set_drvdata(sc->sc_pcidev, sc); ++ ++ /* we read its hardware registers as memory */ ++ mem_start = pci_resource_start(sc->sc_pcidev, 0); ++ mem_len = pci_resource_len(sc->sc_pcidev, 0); ++ ++ sc->sc_base_addr = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_base_addr) { ++ device_printf(sc->sc_dev, "failed to ioremap 0x%x-0x%x\n", ++ mem_start, mem_start + mem_len - 1); ++ goto out; ++ } ++ ++ /* fix up the bus size */ ++ if (pci_set_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); ++ goto out; ++ } ++ if (pci_set_consistent_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, "No usable consistent DMA configuration, aborting.\n"); ++ goto out; ++ } ++ ++ pci_set_master(sc->sc_pcidev); ++ ++ pci_read_config_dword(sc->sc_pcidev, PCI_COMMAND, &cmd); ++ ++ if (!(cmd & PCI_COMMAND_MEMORY)) { ++ device_printf(sc->sc_dev, "failed to enable memory mapping\n"); ++ goto out; ++ } ++ ++ if (!(cmd & PCI_COMMAND_MASTER)) { ++ device_printf(sc->sc_dev, "failed to enable bus mastering\n"); ++ goto out; ++ } ++ ++ rc = request_irq(dev->irq, safe_intr, IRQF_SHARED, "safe", sc); ++ if (rc) { ++ device_printf(sc->sc_dev, "failed to hook irq %d\n", sc->sc_irq); ++ goto out; ++ } ++ sc->sc_irq = dev->irq; ++ ++ sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & ++ (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); ++ ++ /* ++ * Allocate packet engine descriptors. ++ */ ++ sc->sc_ringalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, ++ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), ++ &sc->sc_ringalloc.dma_paddr); ++ if (!sc->sc_ringalloc.dma_vaddr) { ++ device_printf(sc->sc_dev, "cannot allocate PE descriptor ring\n"); ++ goto out; ++ } ++ ++ /* ++ * Hookup the static portion of all our data structures. ++ */ ++ sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; ++ sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; ++ sc->sc_front = sc->sc_ring; ++ sc->sc_back = sc->sc_ring; ++ raddr = sc->sc_ringalloc.dma_paddr; ++ bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); ++ for (i = 0; i < SAFE_MAX_NQUEUE; i++) { ++ struct safe_ringentry *re = &sc->sc_ring[i]; ++ ++ re->re_desc.d_sa = raddr + ++ offsetof(struct safe_ringentry, re_sa); ++ re->re_sa.sa_staterec = raddr + ++ offsetof(struct safe_ringentry, re_sastate); ++ ++ raddr += sizeof (struct safe_ringentry); ++ } ++ spin_lock_init(&sc->sc_ringmtx); ++ ++ /* ++ * Allocate scatter and gather particle descriptors. ++ */ ++ sc->sc_spalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), ++ &sc->sc_spalloc.dma_paddr); ++ if (!sc->sc_spalloc.dma_vaddr) { ++ device_printf(sc->sc_dev, "cannot allocate source particle descriptor ring\n"); ++ goto out; ++ } ++ sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; ++ sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; ++ sc->sc_spfree = sc->sc_spring; ++ bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); ++ ++ sc->sc_dpalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ &sc->sc_dpalloc.dma_paddr); ++ if (!sc->sc_dpalloc.dma_vaddr) { ++ device_printf(sc->sc_dev, "cannot allocate destination particle descriptor ring\n"); ++ goto out; ++ } ++ sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; ++ sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; ++ sc->sc_dpfree = sc->sc_dpring; ++ bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ goto out; ++ } ++ ++ printf("%s:", device_get_nameunit(sc->sc_dev)); ++ ++ devinfo = READ_REG(sc, SAFE_DEVINFO); ++ if (devinfo & SAFE_DEVINFO_RNG) { ++ sc->sc_flags |= SAFE_FLAGS_RNG; ++ printf(" rng"); ++ } ++ if (devinfo & SAFE_DEVINFO_PKEY) { ++ printf(" key"); ++ sc->sc_flags |= SAFE_FLAGS_KEY; ++ crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); ++#if 0 ++ crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); ++#endif ++ init_timer(&sc->sc_pkto); ++ sc->sc_pkto.function = safe_kpoll; ++ sc->sc_pkto.data = (unsigned long) device_get_unit(sc->sc_dev); ++ } ++ if (devinfo & SAFE_DEVINFO_DES) { ++ printf(" des/3des"); ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ } ++ if (devinfo & SAFE_DEVINFO_AES) { ++ printf(" aes"); ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ } ++ if (devinfo & SAFE_DEVINFO_MD5) { ++ printf(" md5"); ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ } ++ if (devinfo & SAFE_DEVINFO_SHA1) { ++ printf(" sha1"); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ } ++ printf(" null"); ++ crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); ++ /* XXX other supported algorithms */ ++ printf("\n"); ++ ++ safe_reset_board(sc); /* reset h/w */ ++ safe_init_board(sc); /* init h/w */ ++ ++#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) ++ if (sc->sc_flags & SAFE_FLAGS_RNG) { ++ safe_rng_init(sc); ++ crypto_rregister(sc->sc_cid, safe_read_random, sc); ++ } ++#endif /* SAFE_NO_RNG */ ++ ++ return (0); ++ ++out: ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_ringalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), ++ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); ++ if (sc->sc_spalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); ++ if (sc->sc_dpalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); ++ kfree(sc); ++ return(-ENODEV); ++} ++ ++static void safe_remove(struct pci_dev *dev) ++{ ++ struct safe_softc *sc = pci_get_drvdata(dev); ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ /* XXX wait/abort active ops */ ++ ++ WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ ++ ++ del_timer_sync(&sc->sc_pkto); ++ ++ crypto_unregister_all(sc->sc_cid); ++ ++ safe_cleanchip(sc); ++ ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_ringalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), ++ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); ++ if (sc->sc_spalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); ++ if (sc->sc_dpalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); ++ sc->sc_irq = -1; ++ sc->sc_ringalloc.dma_vaddr = NULL; ++ sc->sc_spalloc.dma_vaddr = NULL; ++ sc->sc_dpalloc.dma_vaddr = NULL; ++} ++ ++static struct pci_device_id safe_pci_tbl[] = { ++ { PCI_VENDOR_SAFENET, PCI_PRODUCT_SAFEXCEL, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(pci, safe_pci_tbl); ++ ++static struct pci_driver safe_driver = { ++ .name = "safe", ++ .id_table = safe_pci_tbl, ++ .probe = safe_probe, ++ .remove = safe_remove, ++ /* add PM stuff here one day */ ++}; ++ ++static int __init safe_init (void) ++{ ++ struct safe_softc *sc = NULL; ++ int rc; ++ ++ DPRINTF(("%s(%p)\n", __FUNCTION__, safe_init)); ++ ++ rc = pci_register_driver(&safe_driver); ++ pci_register_driver_compat(&safe_driver, rc); ++ ++ return rc; ++} ++ ++static void __exit safe_exit (void) ++{ ++ pci_unregister_driver(&safe_driver); ++} ++ ++module_init(safe_init); ++module_exit(safe_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("OCF driver for safenet PCI crypto devices"); +diff -Nur linux-2.6.39.orig/crypto/ocf/safe/safereg.h linux-2.6.39/crypto/ocf/safe/safereg.h +--- linux-2.6.39.orig/crypto/ocf/safe/safereg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/safe/safereg.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,421 @@ ++/*- ++ * Copyright (c) 2003 Sam Leffler, Errno Consulting ++ * Copyright (c) 2003 Global Technology Associates, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++ * $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $ ++ */ ++#ifndef _SAFE_SAFEREG_H_ ++#define _SAFE_SAFEREG_H_ ++ ++/* ++ * Register definitions for SafeNet SafeXcel-1141 crypto device. ++ * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual. ++ */ ++ ++#define BS_BAR 0x10 /* DMA base address register */ ++#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ ++#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ ++ ++#define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */ ++ ++/* SafeNet */ ++#define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */ ++ ++#define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */ ++#define SAFE_PE_SRC 0x0004 /* Packet Engine Source */ ++#define SAFE_PE_DST 0x0008 /* Packet Engine Destination */ ++#define SAFE_PE_SA 0x000c /* Packet Engine SA */ ++#define SAFE_PE_LEN 0x0010 /* Packet Engine Length */ ++#define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */ ++#define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */ ++#define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */ ++#define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */ ++#define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */ ++#define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */ ++#define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */ ++#define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */ ++#define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */ ++#define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */ ++#define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */ ++#define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */ ++#define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */ ++#define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */ ++#define SAFE_DEVID 0x0084 /* Device ID */ ++#define SAFE_DEVINFO 0x0088 /* Device Info */ ++#define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */ ++#define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */ ++#define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */ ++#define SAFE_HI_MASK 0x00a8 /* Host Mask Control */ ++#define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */ ++#define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */ ++#define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */ ++#define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */ ++#define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */ ++#define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */ ++#define SAFE_DMA_STAT 0x00cc /* DMA Current Status */ ++#define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */ ++#define SAFE_ENDIAN 0x00e0 /* Endian Configuration */ ++#define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */ ++#define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */ ++#define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */ ++#define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */ ++#define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */ ++#define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */ ++#define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */ ++#define SAFE_PK_FUNC 0x081c /* Public Key Function */ ++#define SAFE_PK_RAM_START 0x1000 /* Public Key RAM start address */ ++#define SAFE_PK_RAM_END 0x1fff /* Public Key RAM end address */ ++ ++#define SAFE_RNG_OUT 0x0100 /* RNG Output */ ++#define SAFE_RNG_STAT 0x0104 /* RNG Status */ ++#define SAFE_RNG_CTRL 0x0108 /* RNG Control */ ++#define SAFE_RNG_A 0x010c /* RNG A */ ++#define SAFE_RNG_B 0x0110 /* RNG B */ ++#define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */ ++#define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */ ++#define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */ ++#define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */ ++#define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */ ++#define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */ ++#define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */ ++#define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */ ++#define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */ ++#define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */ ++ ++#define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */ ++#define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */ ++#define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */ ++#define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */ ++#define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */ ++#define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */ ++#define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */ ++#define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */ ++#define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */ ++#define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */ ++#define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */ ++#define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */ ++#define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */ ++#define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */ ++#define SAFE_PE_CSR_XECODE_S 20 ++#define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */ ++#define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */ ++#define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */ ++#define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */ ++#define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */ ++#define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */ ++#define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */ ++#define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */ ++#define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */ ++#define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */ ++#define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */ ++#define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */ ++#define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */ ++#define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */ ++#define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */ ++ ++/* ++ * Check the CSR to see if the PE has returned ownership to ++ * the host. Note that before processing a descriptor this ++ * must be done followed by a check of the SAFE_PE_LEN register ++ * status bits to avoid premature processing of a descriptor ++ * on its way back to the host. ++ */ ++#define SAFE_PE_CSR_IS_DONE(_csr) \ ++ (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE) ++ ++#define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */ ++#define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */ ++#define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */ ++#define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */ ++#define SAFE_PE_LEN_BYPASS_S 24 ++ ++#define SAFE_PE_LEN_IS_DONE(_len) \ ++ (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE) ++ ++/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */ ++#define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */ ++#define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */ ++#define SAFE_INT_PE_ERROR 0x00000010 /* PE error */ ++#define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */ ++ ++#define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */ ++#define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */ ++#define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */ ++ ++#define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */ ++#define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */ ++ ++#define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */ ++#define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */ ++#define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */ ++#define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */ ++#define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */ ++#define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */ ++#define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */ ++#define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */ ++#define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */ ++#define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */ ++#define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */ ++#define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */ ++#define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */ ++#define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */ ++#define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */ ++#define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */ ++#define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */ ++ ++#define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */ ++#define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */ ++#define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */ ++#define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */ ++#define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */ ++#define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */ ++#define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */ ++#define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */ ++#define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */ ++#define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */ ++#define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */ ++#define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */ ++#define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */ ++#define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */ ++ ++#define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */ ++#define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */ ++#define SAFE_PE_RINGCFG_OFFSET_S 16 ++ ++#define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */ ++#define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */ ++#define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */ ++ ++#define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */ ++ ++#define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */ ++#define SAFE_PE_ERNGSTAT_NEXT_S 16 ++ ++#define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */ ++#define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */ ++ ++#define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */ ++#define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */ ++#define SAFE_PE_PARTCFG_GBURST_2 0x00000000 ++#define SAFE_PE_PARTCFG_GBURST_4 0x00010000 ++#define SAFE_PE_PARTCFG_GBURST_8 0x00020000 ++#define SAFE_PE_PARTCFG_GBURST_16 0x00030000 ++#define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */ ++#define SAFE_PE_PARTCFG_SBURST_2 0x00000000 ++#define SAFE_PE_PARTCFG_SBURST_4 0x00040000 ++#define SAFE_PE_PARTCFG_SBURST_8 0x00080000 ++#define SAFE_PE_PARTCFG_SBURST_16 0x000c0000 ++ ++#define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */ ++#define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */ ++ ++#define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */ ++#define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */ ++#define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */ ++ ++#define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */ ++#define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */ ++#define SAFE_DEVINFO_REV_MAJ_S 4 ++#define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */ ++#define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */ ++#define SAFE_DEVINFO_AES 0x00000400 /* AES support present */ ++#define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */ ++#define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */ ++#define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */ ++#define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */ ++#define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */ ++#define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */ ++#define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */ ++#define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */ ++ ++#define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min)) ++#define SAFE_REV_MAJ(_chiprev) \ ++ (((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S) ++#define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN) ++ ++#define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */ ++#define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */ ++#define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */ ++#define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */ ++#define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */ ++#define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */ ++#define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */ ++#define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */ ++#define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */ ++#define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */ ++#define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */ ++#define SAFE_PK_FUNC_RUN 0x00008000 /* start/status */ ++ ++#define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */ ++ ++#define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */ ++#define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */ ++#define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */ ++#define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */ ++#define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */ ++#define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */ ++#define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */ ++#define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */ ++#define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */ ++#define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */ ++ ++/* ++ * Packet engine descriptor. Note that d_csr is a copy of the ++ * SAFE_PE_CSR register and all definitions apply, and d_len ++ * is a copy of the SAFE_PE_LEN register and all definitions apply. ++ * d_src and d_len may point directly to contiguous data or to a ++ * list of ``particle descriptors'' when using scatter/gather i/o. ++ */ ++struct safe_desc { ++ u_int32_t d_csr; /* per-packet control/status */ ++ u_int32_t d_src; /* source address */ ++ u_int32_t d_dst; /* destination address */ ++ u_int32_t d_sa; /* SA address */ ++ u_int32_t d_len; /* length, bypass, status */ ++}; ++ ++/* ++ * Scatter/Gather particle descriptor. ++ * ++ * NB: scatter descriptors do not specify a size; this is fixed ++ * by the setting of the SAFE_PE_PARTCFG register. ++ */ ++struct safe_pdesc { ++ u_int32_t pd_addr; /* particle address */ ++#ifdef __BIG_ENDIAN ++ u_int16_t pd_flags; /* control word */ ++ u_int16_t pd_size; /* particle size (bytes) */ ++#else ++ u_int16_t pd_flags; /* control word */ ++ u_int16_t pd_size; /* particle size (bytes) */ ++#endif ++}; ++ ++#define SAFE_PD_READY 0x0001 /* ready for processing */ ++#define SAFE_PD_DONE 0x0002 /* h/w completed processing */ ++ ++/* ++ * Security Association (SA) Record (Rev 1). One of these is ++ * required for each operation processed by the packet engine. ++ */ ++struct safe_sarec { ++ u_int32_t sa_cmd0; ++ u_int32_t sa_cmd1; ++ u_int32_t sa_resv0; ++ u_int32_t sa_resv1; ++ u_int32_t sa_key[8]; /* DES/3DES/AES key */ ++ u_int32_t sa_indigest[5]; /* inner digest */ ++ u_int32_t sa_outdigest[5]; /* outer digest */ ++ u_int32_t sa_spi; /* SPI */ ++ u_int32_t sa_seqnum; /* sequence number */ ++ u_int32_t sa_seqmask[2]; /* sequence number mask */ ++ u_int32_t sa_resv2; ++ u_int32_t sa_staterec; /* address of state record */ ++ u_int32_t sa_resv3[2]; ++ u_int32_t sa_samgmt0; /* SA management field 0 */ ++ u_int32_t sa_samgmt1; /* SA management field 0 */ ++}; ++ ++#define SAFE_SA_CMD0_OP 0x00000007 /* operation code */ ++#define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */ ++#define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */ ++#define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */ ++#define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */ ++#define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */ ++#define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */ ++#define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */ ++#define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */ ++#define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */ ++#define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */ ++#define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */ ++#define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */ ++#define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */ ++#define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */ ++#define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */ ++#define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */ ++#define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */ ++#define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */ ++#define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */ ++#define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */ ++#define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */ ++#define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */ ++#define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */ ++#define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */ ++#define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */ ++#define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */ ++#define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */ ++#define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */ ++#define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */ ++#define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */ ++#define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */ ++#define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */ ++#define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */ ++#define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */ ++#define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */ ++#define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */ ++#define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */ ++#define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */ ++#define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */ ++#define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */ ++#define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */ ++#define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */ ++ ++#define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */ ++#define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */ ++#define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */ ++#define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */ ++#define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */ ++#define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */ ++#define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */ ++#define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */ ++#define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */ ++#define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */ ++#define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */ ++#define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */ ++#define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */ ++#define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */ ++#define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */ ++#define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */ ++#define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */ ++#define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */ ++#define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */ ++#define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS ++#define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */ ++#define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */ ++#define SAFE_SA_CMD1_OFFSET_S 16 ++#define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */ ++#define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */ ++#define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */ ++#define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */ ++ ++/* ++ * Security Associate State Record (Rev 1). ++ */ ++struct safe_sastate { ++ u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */ ++ u_int32_t sa_saved_hashbc; /* saved hash byte count */ ++ u_int32_t sa_saved_indigest[5]; /* saved inner digest */ ++}; ++#endif /* _SAFE_SAFEREG_H_ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/safe/safevar.h linux-2.6.39/crypto/ocf/safe/safevar.h +--- linux-2.6.39.orig/crypto/ocf/safe/safevar.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/safe/safevar.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,230 @@ ++/*- ++ * The linux port of this code done by David McCullough ++ * Copyright (C) 2004-2010 David McCullough ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2003 Sam Leffler, Errno Consulting ++ * Copyright (c) 2003 Global Technology Associates, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++ * $FreeBSD: src/sys/dev/safe/safevar.h,v 1.2 2006/05/17 18:34:26 pjd Exp $ ++ */ ++#ifndef _SAFE_SAFEVAR_H_ ++#define _SAFE_SAFEVAR_H_ ++ ++/* Maximum queue length */ ++#ifndef SAFE_MAX_NQUEUE ++#define SAFE_MAX_NQUEUE 60 ++#endif ++ ++#define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ ++#define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ ++#define SAFE_MAX_DSIZE 2048 /* MCLBYTES Fixed scatter particle size */ ++#define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ ++#define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ ++/* total src+dst particle descriptors */ ++#define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) ++#define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) ++ ++#define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ ++ ++#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) ++#define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) ++#define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) ++ ++#define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ ++#define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ ++#define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ ++ ++#ifdef __KERNEL__ ++/* ++ * State associated with the allocation of each chunk ++ * of memory setup for DMA. ++ */ ++struct safe_dma_alloc { ++ dma_addr_t dma_paddr; ++ void *dma_vaddr; ++}; ++ ++/* ++ * Cryptographic operand state. One of these exists for each ++ * source and destination operand passed in from the crypto ++ * subsystem. When possible source and destination operands ++ * refer to the same memory. More often they are distinct. ++ * We track the virtual address of each operand as well as ++ * where each is mapped for DMA. ++ */ ++struct safe_operand { ++ union { ++ struct sk_buff *skb; ++ struct uio *io; ++ } u; ++ void *map; ++ int mapsize; /* total number of bytes in segs */ ++ struct { ++ dma_addr_t ds_addr; ++ int ds_len; ++ int ds_tlen; ++ } segs[SAFE_MAX_PART]; ++ int nsegs; ++}; ++ ++/* ++ * Packet engine ring entry and cryptographic operation state. ++ * The packet engine requires a ring of descriptors that contain ++ * pointers to various cryptographic state. However the ring ++ * configuration register allows you to specify an arbitrary size ++ * for ring entries. We use this feature to collect most of the ++ * state for each cryptographic request into one spot. Other than ++ * ring entries only the ``particle descriptors'' (scatter/gather ++ * lists) and the actual operand data are kept separate. The ++ * particle descriptors must also be organized in rings. The ++ * operand data can be located aribtrarily (modulo alignment constraints). ++ * ++ * Note that the descriptor ring is mapped onto the PCI bus so ++ * the hardware can DMA data. This means the entire ring must be ++ * contiguous. ++ */ ++struct safe_ringentry { ++ struct safe_desc re_desc; /* command descriptor */ ++ struct safe_sarec re_sa; /* SA record */ ++ struct safe_sastate re_sastate; /* SA state record */ ++ ++ struct cryptop *re_crp; /* crypto operation */ ++ ++ struct safe_operand re_src; /* source operand */ ++ struct safe_operand re_dst; /* destination operand */ ++ ++ int re_sesn; /* crypto session ID */ ++ int re_flags; ++#define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ ++#define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ ++}; ++ ++#define re_src_skb re_src.u.skb ++#define re_src_io re_src.u.io ++#define re_src_map re_src.map ++#define re_src_nsegs re_src.nsegs ++#define re_src_segs re_src.segs ++#define re_src_mapsize re_src.mapsize ++ ++#define re_dst_skb re_dst.u.skb ++#define re_dst_io re_dst.u.io ++#define re_dst_map re_dst.map ++#define re_dst_nsegs re_dst.nsegs ++#define re_dst_segs re_dst.segs ++#define re_dst_mapsize re_dst.mapsize ++ ++struct rndstate_test; ++ ++struct safe_session { ++ u_int32_t ses_used; ++ u_int32_t ses_klen; /* key length in bits */ ++ u_int32_t ses_key[8]; /* DES/3DES/AES key */ ++ u_int32_t ses_mlen; /* hmac length in bytes */ ++ u_int32_t ses_hminner[5]; /* hmac inner state */ ++ u_int32_t ses_hmouter[5]; /* hmac outer state */ ++ u_int32_t ses_iv[4]; /* DES/3DES/AES iv */ ++}; ++ ++struct safe_pkq { ++ struct list_head pkq_list; ++ struct cryptkop *pkq_krp; ++}; ++ ++struct safe_softc { ++ softc_device_decl sc_dev; ++ u32 sc_irq; ++ ++ struct pci_dev *sc_pcidev; ++ ocf_iomem_t sc_base_addr; ++ ++ u_int sc_chiprev; /* major/minor chip revision */ ++ int sc_flags; /* device specific flags */ ++#define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ ++#define SAFE_FLAGS_RNG 0x02 /* hardware rng */ ++ int sc_suspended; ++ int sc_needwakeup; /* notify crypto layer */ ++ int32_t sc_cid; /* crypto tag */ ++ ++ struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ ++ struct safe_ringentry *sc_ring; /* PE ring */ ++ struct safe_ringentry *sc_ringtop; /* PE ring top */ ++ struct safe_ringentry *sc_front; /* next free entry */ ++ struct safe_ringentry *sc_back; /* next pending entry */ ++ int sc_nqchip; /* # passed to chip */ ++ spinlock_t sc_ringmtx; /* PE ring lock */ ++ struct safe_pdesc *sc_spring; /* src particle ring */ ++ struct safe_pdesc *sc_springtop; /* src particle ring top */ ++ struct safe_pdesc *sc_spfree; /* next free src particle */ ++ struct safe_dma_alloc sc_spalloc; /* src particle ring state */ ++ struct safe_pdesc *sc_dpring; /* dest particle ring */ ++ struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ ++ struct safe_pdesc *sc_dpfree; /* next free dest particle */ ++ struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ ++ int sc_nsessions; /* # of sessions */ ++ struct safe_session *sc_sessions; /* sessions */ ++ ++ struct timer_list sc_pkto; /* PK polling */ ++ spinlock_t sc_pkmtx; /* PK lock */ ++ struct list_head sc_pkq; /* queue of PK requests */ ++ struct safe_pkq *sc_pkq_cur; /* current processing request */ ++ u_int32_t sc_pk_reslen, sc_pk_resoff; ++ ++ int sc_max_dsize; /* maximum safe DMA size */ ++}; ++#endif /* __KERNEL__ */ ++ ++struct safe_stats { ++ u_int64_t st_ibytes; ++ u_int64_t st_obytes; ++ u_int32_t st_ipackets; ++ u_int32_t st_opackets; ++ u_int32_t st_invalid; /* invalid argument */ ++ u_int32_t st_badsession; /* invalid session id */ ++ u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ ++ u_int32_t st_nodesc; /* op submitted w/o descriptors */ ++ u_int32_t st_badalg; /* unsupported algorithm */ ++ u_int32_t st_ringfull; /* PE descriptor ring full */ ++ u_int32_t st_peoperr; /* PE marked error */ ++ u_int32_t st_dmaerr; /* PE DMA error */ ++ u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ ++ u_int32_t st_skipmismatch; /* enc part begins before auth part */ ++ u_int32_t st_lenmismatch; /* enc length different auth length */ ++ u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ ++ u_int32_t st_cofftoobig; /* crypto offset > 255 words */ ++ u_int32_t st_iovmisaligned; /* iov op not aligned */ ++ u_int32_t st_iovnotuniform; /* iov op not suitable */ ++ u_int32_t st_unaligned; /* unaligned src caused copy */ ++ u_int32_t st_notuniform; /* non-uniform src caused copy */ ++ u_int32_t st_nomap; /* bus_dmamap_create failed */ ++ u_int32_t st_noload; /* bus_dmamap_load_* failed */ ++ u_int32_t st_nombuf; /* MGET* failed */ ++ u_int32_t st_nomcl; /* MCLGET* failed */ ++ u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ ++ u_int32_t st_rng; /* RNG requests */ ++ u_int32_t st_rngalarm; /* RNG alarm requests */ ++ u_int32_t st_noicvcopy; /* ICV data copies suppressed */ ++}; ++#endif /* _SAFE_SAFEVAR_H_ */ +diff -Nur linux-2.6.39.orig/crypto/ocf/safe/sha1.c linux-2.6.39/crypto/ocf/safe/sha1.c +--- linux-2.6.39.orig/crypto/ocf/safe/sha1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/safe/sha1.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,279 @@ ++/* $KAME: sha1.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++/* ++ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) ++ * based on: http://csrc.nist.gov/fips/fip180-1.txt ++ * implemented by Jun-ichiro itojun Itoh ++ */ ++ ++#if 0 ++#include ++__FBSDID("$FreeBSD: src/sys/crypto/sha1.c,v 1.9 2003/06/10 21:36:57 obrien Exp $"); ++ ++#include ++#include ++#include ++#include ++ ++#include ++#endif ++ ++/* sanity check */ ++#if BYTE_ORDER != BIG_ENDIAN ++# if BYTE_ORDER != LITTLE_ENDIAN ++# define unsupported 1 ++# endif ++#endif ++ ++#ifndef unsupported ++ ++/* constant table */ ++static u_int32_t _K[] = { 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 }; ++#define K(t) _K[(t) / 20] ++ ++#define F0(b, c, d) (((b) & (c)) | ((~(b)) & (d))) ++#define F1(b, c, d) (((b) ^ (c)) ^ (d)) ++#define F2(b, c, d) (((b) & (c)) | ((b) & (d)) | ((c) & (d))) ++#define F3(b, c, d) (((b) ^ (c)) ^ (d)) ++ ++#define S(n, x) (((x) << (n)) | ((x) >> (32 - n))) ++ ++#undef H ++#define H(n) (ctxt->h.b32[(n)]) ++#define COUNT (ctxt->count) ++#define BCOUNT (ctxt->c.b64[0] / 8) ++#define W(n) (ctxt->m.b32[(n)]) ++ ++#define PUTBYTE(x) { \ ++ ctxt->m.b8[(COUNT % 64)] = (x); \ ++ COUNT++; \ ++ COUNT %= 64; \ ++ ctxt->c.b64[0] += 8; \ ++ if (COUNT % 64 == 0) \ ++ sha1_step(ctxt); \ ++ } ++ ++#define PUTPAD(x) { \ ++ ctxt->m.b8[(COUNT % 64)] = (x); \ ++ COUNT++; \ ++ COUNT %= 64; \ ++ if (COUNT % 64 == 0) \ ++ sha1_step(ctxt); \ ++ } ++ ++static void sha1_step(struct sha1_ctxt *); ++ ++static void ++sha1_step(ctxt) ++ struct sha1_ctxt *ctxt; ++{ ++ u_int32_t a, b, c, d, e; ++ size_t t, s; ++ u_int32_t tmp; ++ ++#if BYTE_ORDER == LITTLE_ENDIAN ++ struct sha1_ctxt tctxt; ++ bcopy(&ctxt->m.b8[0], &tctxt.m.b8[0], 64); ++ ctxt->m.b8[0] = tctxt.m.b8[3]; ctxt->m.b8[1] = tctxt.m.b8[2]; ++ ctxt->m.b8[2] = tctxt.m.b8[1]; ctxt->m.b8[3] = tctxt.m.b8[0]; ++ ctxt->m.b8[4] = tctxt.m.b8[7]; ctxt->m.b8[5] = tctxt.m.b8[6]; ++ ctxt->m.b8[6] = tctxt.m.b8[5]; ctxt->m.b8[7] = tctxt.m.b8[4]; ++ ctxt->m.b8[8] = tctxt.m.b8[11]; ctxt->m.b8[9] = tctxt.m.b8[10]; ++ ctxt->m.b8[10] = tctxt.m.b8[9]; ctxt->m.b8[11] = tctxt.m.b8[8]; ++ ctxt->m.b8[12] = tctxt.m.b8[15]; ctxt->m.b8[13] = tctxt.m.b8[14]; ++ ctxt->m.b8[14] = tctxt.m.b8[13]; ctxt->m.b8[15] = tctxt.m.b8[12]; ++ ctxt->m.b8[16] = tctxt.m.b8[19]; ctxt->m.b8[17] = tctxt.m.b8[18]; ++ ctxt->m.b8[18] = tctxt.m.b8[17]; ctxt->m.b8[19] = tctxt.m.b8[16]; ++ ctxt->m.b8[20] = tctxt.m.b8[23]; ctxt->m.b8[21] = tctxt.m.b8[22]; ++ ctxt->m.b8[22] = tctxt.m.b8[21]; ctxt->m.b8[23] = tctxt.m.b8[20]; ++ ctxt->m.b8[24] = tctxt.m.b8[27]; ctxt->m.b8[25] = tctxt.m.b8[26]; ++ ctxt->m.b8[26] = tctxt.m.b8[25]; ctxt->m.b8[27] = tctxt.m.b8[24]; ++ ctxt->m.b8[28] = tctxt.m.b8[31]; ctxt->m.b8[29] = tctxt.m.b8[30]; ++ ctxt->m.b8[30] = tctxt.m.b8[29]; ctxt->m.b8[31] = tctxt.m.b8[28]; ++ ctxt->m.b8[32] = tctxt.m.b8[35]; ctxt->m.b8[33] = tctxt.m.b8[34]; ++ ctxt->m.b8[34] = tctxt.m.b8[33]; ctxt->m.b8[35] = tctxt.m.b8[32]; ++ ctxt->m.b8[36] = tctxt.m.b8[39]; ctxt->m.b8[37] = tctxt.m.b8[38]; ++ ctxt->m.b8[38] = tctxt.m.b8[37]; ctxt->m.b8[39] = tctxt.m.b8[36]; ++ ctxt->m.b8[40] = tctxt.m.b8[43]; ctxt->m.b8[41] = tctxt.m.b8[42]; ++ ctxt->m.b8[42] = tctxt.m.b8[41]; ctxt->m.b8[43] = tctxt.m.b8[40]; ++ ctxt->m.b8[44] = tctxt.m.b8[47]; ctxt->m.b8[45] = tctxt.m.b8[46]; ++ ctxt->m.b8[46] = tctxt.m.b8[45]; ctxt->m.b8[47] = tctxt.m.b8[44]; ++ ctxt->m.b8[48] = tctxt.m.b8[51]; ctxt->m.b8[49] = tctxt.m.b8[50]; ++ ctxt->m.b8[50] = tctxt.m.b8[49]; ctxt->m.b8[51] = tctxt.m.b8[48]; ++ ctxt->m.b8[52] = tctxt.m.b8[55]; ctxt->m.b8[53] = tctxt.m.b8[54]; ++ ctxt->m.b8[54] = tctxt.m.b8[53]; ctxt->m.b8[55] = tctxt.m.b8[52]; ++ ctxt->m.b8[56] = tctxt.m.b8[59]; ctxt->m.b8[57] = tctxt.m.b8[58]; ++ ctxt->m.b8[58] = tctxt.m.b8[57]; ctxt->m.b8[59] = tctxt.m.b8[56]; ++ ctxt->m.b8[60] = tctxt.m.b8[63]; ctxt->m.b8[61] = tctxt.m.b8[62]; ++ ctxt->m.b8[62] = tctxt.m.b8[61]; ctxt->m.b8[63] = tctxt.m.b8[60]; ++#endif ++ ++ a = H(0); b = H(1); c = H(2); d = H(3); e = H(4); ++ ++ for (t = 0; t < 20; t++) { ++ s = t & 0x0f; ++ if (t >= 16) { ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ } ++ tmp = S(5, a) + F0(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ for (t = 20; t < 40; t++) { ++ s = t & 0x0f; ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ tmp = S(5, a) + F1(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ for (t = 40; t < 60; t++) { ++ s = t & 0x0f; ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ tmp = S(5, a) + F2(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ for (t = 60; t < 80; t++) { ++ s = t & 0x0f; ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ tmp = S(5, a) + F3(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ ++ H(0) = H(0) + a; ++ H(1) = H(1) + b; ++ H(2) = H(2) + c; ++ H(3) = H(3) + d; ++ H(4) = H(4) + e; ++ ++ bzero(&ctxt->m.b8[0], 64); ++} ++ ++/*------------------------------------------------------------*/ ++ ++void ++sha1_init(ctxt) ++ struct sha1_ctxt *ctxt; ++{ ++ bzero(ctxt, sizeof(struct sha1_ctxt)); ++ H(0) = 0x67452301; ++ H(1) = 0xefcdab89; ++ H(2) = 0x98badcfe; ++ H(3) = 0x10325476; ++ H(4) = 0xc3d2e1f0; ++} ++ ++void ++sha1_pad(ctxt) ++ struct sha1_ctxt *ctxt; ++{ ++ size_t padlen; /*pad length in bytes*/ ++ size_t padstart; ++ ++ PUTPAD(0x80); ++ ++ padstart = COUNT % 64; ++ padlen = 64 - padstart; ++ if (padlen < 8) { ++ bzero(&ctxt->m.b8[padstart], padlen); ++ COUNT += padlen; ++ COUNT %= 64; ++ sha1_step(ctxt); ++ padstart = COUNT % 64; /* should be 0 */ ++ padlen = 64 - padstart; /* should be 64 */ ++ } ++ bzero(&ctxt->m.b8[padstart], padlen - 8); ++ COUNT += (padlen - 8); ++ COUNT %= 64; ++#if BYTE_ORDER == BIG_ENDIAN ++ PUTPAD(ctxt->c.b8[0]); PUTPAD(ctxt->c.b8[1]); ++ PUTPAD(ctxt->c.b8[2]); PUTPAD(ctxt->c.b8[3]); ++ PUTPAD(ctxt->c.b8[4]); PUTPAD(ctxt->c.b8[5]); ++ PUTPAD(ctxt->c.b8[6]); PUTPAD(ctxt->c.b8[7]); ++#else ++ PUTPAD(ctxt->c.b8[7]); PUTPAD(ctxt->c.b8[6]); ++ PUTPAD(ctxt->c.b8[5]); PUTPAD(ctxt->c.b8[4]); ++ PUTPAD(ctxt->c.b8[3]); PUTPAD(ctxt->c.b8[2]); ++ PUTPAD(ctxt->c.b8[1]); PUTPAD(ctxt->c.b8[0]); ++#endif ++} ++ ++void ++sha1_loop(ctxt, input, len) ++ struct sha1_ctxt *ctxt; ++ const u_int8_t *input; ++ size_t len; ++{ ++ size_t gaplen; ++ size_t gapstart; ++ size_t off; ++ size_t copysiz; ++ ++ off = 0; ++ ++ while (off < len) { ++ gapstart = COUNT % 64; ++ gaplen = 64 - gapstart; ++ ++ copysiz = (gaplen < len - off) ? gaplen : len - off; ++ bcopy(&input[off], &ctxt->m.b8[gapstart], copysiz); ++ COUNT += copysiz; ++ COUNT %= 64; ++ ctxt->c.b64[0] += copysiz * 8; ++ if (COUNT % 64 == 0) ++ sha1_step(ctxt); ++ off += copysiz; ++ } ++} ++ ++void ++sha1_result(ctxt, digest0) ++ struct sha1_ctxt *ctxt; ++ caddr_t digest0; ++{ ++ u_int8_t *digest; ++ ++ digest = (u_int8_t *)digest0; ++ sha1_pad(ctxt); ++#if BYTE_ORDER == BIG_ENDIAN ++ bcopy(&ctxt->h.b8[0], digest, 20); ++#else ++ digest[0] = ctxt->h.b8[3]; digest[1] = ctxt->h.b8[2]; ++ digest[2] = ctxt->h.b8[1]; digest[3] = ctxt->h.b8[0]; ++ digest[4] = ctxt->h.b8[7]; digest[5] = ctxt->h.b8[6]; ++ digest[6] = ctxt->h.b8[5]; digest[7] = ctxt->h.b8[4]; ++ digest[8] = ctxt->h.b8[11]; digest[9] = ctxt->h.b8[10]; ++ digest[10] = ctxt->h.b8[9]; digest[11] = ctxt->h.b8[8]; ++ digest[12] = ctxt->h.b8[15]; digest[13] = ctxt->h.b8[14]; ++ digest[14] = ctxt->h.b8[13]; digest[15] = ctxt->h.b8[12]; ++ digest[16] = ctxt->h.b8[19]; digest[17] = ctxt->h.b8[18]; ++ digest[18] = ctxt->h.b8[17]; digest[19] = ctxt->h.b8[16]; ++#endif ++} ++ ++#endif /*unsupported*/ +diff -Nur linux-2.6.39.orig/crypto/ocf/safe/sha1.h linux-2.6.39/crypto/ocf/safe/sha1.h +--- linux-2.6.39.orig/crypto/ocf/safe/sha1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/safe/sha1.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,72 @@ ++/* $FreeBSD: src/sys/crypto/sha1.h,v 1.8 2002/03/20 05:13:50 alfred Exp $ */ ++/* $KAME: sha1.h,v 1.5 2000/03/27 04:36:23 sumikawa Exp $ */ ++ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++/* ++ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) ++ * based on: http://csrc.nist.gov/fips/fip180-1.txt ++ * implemented by Jun-ichiro itojun Itoh ++ */ ++ ++#ifndef _NETINET6_SHA1_H_ ++#define _NETINET6_SHA1_H_ ++ ++struct sha1_ctxt { ++ union { ++ u_int8_t b8[20]; ++ u_int32_t b32[5]; ++ } h; ++ union { ++ u_int8_t b8[8]; ++ u_int64_t b64[1]; ++ } c; ++ union { ++ u_int8_t b8[64]; ++ u_int32_t b32[16]; ++ } m; ++ u_int8_t count; ++}; ++ ++#ifdef __KERNEL__ ++extern void sha1_init(struct sha1_ctxt *); ++extern void sha1_pad(struct sha1_ctxt *); ++extern void sha1_loop(struct sha1_ctxt *, const u_int8_t *, size_t); ++extern void sha1_result(struct sha1_ctxt *, caddr_t); ++ ++/* compatibilty with other SHA1 source codes */ ++typedef struct sha1_ctxt SHA1_CTX; ++#define SHA1Init(x) sha1_init((x)) ++#define SHA1Update(x, y, z) sha1_loop((x), (y), (z)) ++#define SHA1Final(x, y) sha1_result((y), (x)) ++#endif /* __KERNEL__ */ ++ ++#define SHA1_RESULTLEN (160/8) ++ ++#endif /*_NETINET6_SHA1_H_*/ +diff -Nur linux-2.6.39.orig/crypto/ocf/talitos/Makefile linux-2.6.39/crypto/ocf/talitos/Makefile +--- linux-2.6.39.orig/crypto/ocf/talitos/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/talitos/Makefile 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_TALITOS) += talitos.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-2.6.39.orig/crypto/ocf/talitos/talitos.c linux-2.6.39/crypto/ocf/talitos/talitos.c +--- linux-2.6.39.orig/crypto/ocf/talitos/talitos.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/talitos/talitos.c 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,1359 @@ ++/* ++ * crypto/ocf/talitos/talitos.c ++ * ++ * An OCF-Linux module that uses Freescale's SEC to do the crypto. ++ * Based on crypto/ocf/hifn and crypto/ocf/safe OCF drivers ++ * ++ * Copyright (c) 2006 Freescale Semiconductor, Inc. ++ * ++ * This code written by Kim A. B. Phillips ++ * some code copied from files with the following: ++ * Copyright (C) 2004-2007 David McCullough ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * --------------------------------------------------------------------------- ++ * ++ * NOTES: ++ * ++ * The Freescale SEC (also known as 'talitos') resides on the ++ * internal bus, and runs asynchronous to the processor core. It has ++ * a wide gamut of cryptographic acceleration features, including single- ++ * pass IPsec (also known as algorithm chaining). To properly utilize ++ * all of the SEC's performance enhancing features, further reworking ++ * of higher level code (framework, applications) will be necessary. ++ * ++ * The following table shows which SEC version is present in which devices: ++ * ++ * Devices SEC version ++ * ++ * 8272, 8248 SEC 1.0 ++ * 885, 875 SEC 1.2 ++ * 8555E, 8541E SEC 2.0 ++ * 8349E SEC 2.01 ++ * 8548E SEC 2.1 ++ * ++ * The following table shows the features offered by each SEC version: ++ * ++ * Max. chan- ++ * version Bus I/F Clock nels DEU AESU AFEU MDEU PKEU RNG KEU ++ * ++ * SEC 1.0 internal 64b 100MHz 4 1 1 1 1 1 1 0 ++ * SEC 1.2 internal 32b 66MHz 1 1 1 0 1 0 0 0 ++ * SEC 2.0 internal 64b 166MHz 4 1 1 1 1 1 1 0 ++ * SEC 2.01 internal 64b 166MHz 4 1 1 1 1 1 1 0 ++ * SEC 2.1 internal 64b 333MHz 4 1 1 1 1 1 1 1 ++ * ++ * Each execution unit in the SEC has two modes of execution; channel and ++ * slave/debug. This driver employs the channel infrastructure in the ++ * device for convenience. Only the RNG is directly accessed due to the ++ * convenience of its random fifo pool. The relationship between the ++ * channels and execution units is depicted in the following diagram: ++ * ++ * ------- ------------ ++ * ---| ch0 |---| | ++ * ------- | | ++ * | |------+-------+-------+-------+------------ ++ * ------- | | | | | | | ++ * ---| ch1 |---| | | | | | | ++ * ------- | | ------ ------ ------ ------ ------ ++ * |controller| |DEU | |AESU| |MDEU| |PKEU| ... |RNG | ++ * ------- | | ------ ------ ------ ------ ------ ++ * ---| ch2 |---| | | | | | | ++ * ------- | | | | | | | ++ * | |------+-------+-------+-------+------------ ++ * ------- | | ++ * ---| ch3 |---| | ++ * ------- ------------ ++ * ++ * Channel ch0 may drive an aes operation to the aes unit (AESU), ++ * and, at the same time, ch1 may drive a message digest operation ++ * to the mdeu. Each channel has an input descriptor FIFO, and the ++ * FIFO can contain, e.g. on the 8541E, up to 24 entries, before a ++ * a buffer overrun error is triggered. The controller is responsible ++ * for fetching the data from descriptor pointers, and passing the ++ * data to the appropriate EUs. The controller also writes the ++ * cryptographic operation's result to memory. The SEC notifies ++ * completion by triggering an interrupt and/or setting the 1st byte ++ * of the hdr field to 0xff. ++ * ++ * TODO: ++ * o support more algorithms ++ * o support more versions of the SEC ++ * o add support for linux 2.4 ++ * o scatter-gather (sg) support ++ * o add support for public key ops (PKEU) ++ * o add statistics ++ */ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* dma_map_single() */ ++#include ++ ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) ++#include ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++#include ++#endif ++ ++#include ++#include ++ ++#define DRV_NAME "talitos" ++ ++#include "talitos_dev.h" ++#include "talitos_soft.h" ++ ++#define read_random(p,l) get_random_bytes(p,l) ++ ++const char talitos_driver_name[] = "Talitos OCF"; ++const char talitos_driver_version[] = "0.2"; ++ ++static int talitos_newsession(device_t dev, u_int32_t *sidp, ++ struct cryptoini *cri); ++static int talitos_freesession(device_t dev, u_int64_t tid); ++static int talitos_process(device_t dev, struct cryptop *crp, int hint); ++static void dump_talitos_status(struct talitos_softc *sc); ++static int talitos_submit(struct talitos_softc *sc, struct talitos_desc *td, ++ int chsel); ++static void talitos_doneprocessing(struct talitos_softc *sc); ++static void talitos_init_device(struct talitos_softc *sc); ++static void talitos_reset_device_master(struct talitos_softc *sc); ++static void talitos_reset_device(struct talitos_softc *sc); ++static void talitos_errorprocessing(struct talitos_softc *sc); ++#ifdef CONFIG_PPC_MERGE ++static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match); ++static int talitos_remove(struct of_device *ofdev); ++#else ++static int talitos_probe(struct platform_device *pdev); ++static int talitos_remove(struct platform_device *pdev); ++#endif ++#ifdef CONFIG_OCF_RANDOMHARVEST ++static int talitos_read_random(void *arg, u_int32_t *buf, int maxwords); ++static void talitos_rng_init(struct talitos_softc *sc); ++#endif ++ ++static device_method_t talitos_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, talitos_newsession), ++ DEVMETHOD(cryptodev_freesession,talitos_freesession), ++ DEVMETHOD(cryptodev_process, talitos_process), ++}; ++ ++#define debug talitos_debug ++int talitos_debug = 0; ++module_param(talitos_debug, int, 0644); ++MODULE_PARM_DESC(talitos_debug, "Enable debug"); ++ ++static inline void talitos_write(volatile unsigned *addr, u32 val) ++{ ++ out_be32(addr, val); ++} ++ ++static inline u32 talitos_read(volatile unsigned *addr) ++{ ++ u32 val; ++ val = in_be32(addr); ++ return val; ++} ++ ++static void dump_talitos_status(struct talitos_softc *sc) ++{ ++ unsigned int v, v_hi, i, *ptr; ++ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_MCR_HI); ++ printk(KERN_INFO "%s: MCR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); ++ printk(KERN_INFO "%s: IMR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); ++ printk(KERN_INFO "%s: ISR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CDPR); ++ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CDPR_HI); ++ printk(KERN_INFO "%s: CDPR ch%d 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), i, v, v_hi); ++ } ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCPSR); ++ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCPSR_HI); ++ printk(KERN_INFO "%s: CCPSR ch%d 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), i, v, v_hi); ++ } ++ ptr = sc->sc_base_addr + TALITOS_CH_DESCBUF; ++ for (i = 0; i < 16; i++) { ++ v = talitos_read(ptr++); v_hi = talitos_read(ptr++); ++ printk(KERN_INFO "%s: DESCBUF ch0 0x%08x_%08x (tdp%02d)\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi, i); ++ } ++ return; ++} ++ ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++/* ++ * pull random numbers off the RNG FIFO, not exceeding amount available ++ */ ++static int ++talitos_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ struct talitos_softc *sc = (struct talitos_softc *) arg; ++ int rc; ++ u_int32_t v; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* check for things like FIFO underflow */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); ++ if (unlikely(v)) { ++ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", ++ device_get_nameunit(sc->sc_cdev), v); ++ return 0; ++ } ++ /* ++ * OFL is number of available 64-bit words, ++ * shift and convert to a 32-bit word count ++ */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI); ++ v = (v & TALITOS_RNGSR_HI_OFL) >> (16 - 1); ++ if (maxwords > v) ++ maxwords = v; ++ for (rc = 0; rc < maxwords; rc++) { ++ buf[rc] = talitos_read(sc->sc_base_addr + ++ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); ++ } ++ if (maxwords & 1) { ++ /* ++ * RNG will complain with an AE in the RNGISR ++ * if we don't complete the pairs of 32-bit reads ++ * to its 64-bit register based FIFO ++ */ ++ v = talitos_read(sc->sc_base_addr + ++ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); ++ } ++ ++ return rc; ++} ++ ++static void ++talitos_rng_init(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ /* reset RNG EU */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGRCR_HI); ++ v |= TALITOS_RNGRCR_HI_SR; ++ talitos_write(sc->sc_base_addr + TALITOS_RNGRCR_HI, v); ++ while ((talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI) ++ & TALITOS_RNGSR_HI_RD) == 0) ++ cpu_relax(); ++ /* ++ * we tell the RNG to start filling the RNG FIFO ++ * by writing the RNGDSR ++ */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGDSR_HI); ++ talitos_write(sc->sc_base_addr + TALITOS_RNGDSR_HI, v); ++ /* ++ * 64 bits of data will be pushed onto the FIFO every ++ * 256 SEC cycles until the FIFO is full. The RNG then ++ * attempts to keep the FIFO full. ++ */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); ++ if (v) { ++ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", ++ device_get_nameunit(sc->sc_cdev), v); ++ return; ++ } ++ /* ++ * n.b. we need to add a FIPS test here - if the RNG is going ++ * to fail, it's going to fail at reset time ++ */ ++ return; ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++talitos_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct talitos_softc *sc = device_get_softc(dev); ++ struct talitos_session *ses = NULL; ++ int sesn; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ if (sidp == NULL || cri == NULL || sc == NULL) { ++ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (c->cri_alg == CRYPTO_MD5 || ++ c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1 || ++ c->cri_alg == CRYPTO_SHA1_HMAC || ++ c->cri_alg == CRYPTO_NULL_HMAC) { ++ if (macini) ++ return EINVAL; ++ macini = c; ++ } else if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC || ++ c->cri_alg == CRYPTO_NULL_CBC) { ++ if (encini) ++ return EINVAL; ++ encini = c; ++ } else { ++ DPRINTF("UNKNOWN c->cri_alg %d\n", encini->cri_alg); ++ return EINVAL; ++ } ++ } ++ if (encini == NULL && macini == NULL) ++ return EINVAL; ++ if (encini) { ++ /* validate key length */ ++ switch (encini->cri_alg) { ++ case CRYPTO_DES_CBC: ++ if (encini->cri_klen != 64) ++ return EINVAL; ++ break; ++ case CRYPTO_3DES_CBC: ++ if (encini->cri_klen != 192) { ++ return EINVAL; ++ } ++ break; ++ case CRYPTO_AES_CBC: ++ if (encini->cri_klen != 128 && ++ encini->cri_klen != 192 && ++ encini->cri_klen != 256) ++ return EINVAL; ++ break; ++ default: ++ DPRINTF("UNKNOWN encini->cri_alg %d\n", ++ encini->cri_alg); ++ return EINVAL; ++ } ++ } ++ ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct talitos_session *) ++ kmalloc(sizeof(struct talitos_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return ENOMEM; ++ memset(ses, 0, sizeof(struct talitos_session)); ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn].ses_used == 0) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ /* allocating session */ ++ sesn = sc->sc_nsessions; ++ ses = (struct talitos_session *) kmalloc( ++ (sesn + 1) * sizeof(struct talitos_session), ++ SLAB_ATOMIC); ++ if (ses == NULL) ++ return ENOMEM; ++ memset(ses, 0, ++ (sesn + 1) * sizeof(struct talitos_session)); ++ memcpy(ses, sc->sc_sessions, ++ sesn * sizeof(struct talitos_session)); ++ memset(sc->sc_sessions, 0, ++ sesn * sizeof(struct talitos_session)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ ++ ses->ses_used = 1; ++ ++ if (encini) { ++ /* get an IV */ ++ /* XXX may read fewer than requested */ ++ read_random(ses->ses_iv, sizeof(ses->ses_iv)); ++ ++ ses->ses_klen = (encini->cri_klen + 7) / 8; ++ memcpy(ses->ses_key, encini->cri_key, ses->ses_klen); ++ if (macini) { ++ /* doing hash on top of cipher */ ++ ses->ses_hmac_len = (macini->cri_klen + 7) / 8; ++ memcpy(ses->ses_hmac, macini->cri_key, ++ ses->ses_hmac_len); ++ } ++ } else if (macini) { ++ /* doing hash */ ++ ses->ses_klen = (macini->cri_klen + 7) / 8; ++ memcpy(ses->ses_key, macini->cri_key, ses->ses_klen); ++ } ++ ++ /* back compat way of determining MSC result len */ ++ if (macini) { ++ ses->ses_mlen = macini->cri_mlen; ++ if (ses->ses_mlen == 0) { ++ if (macini->cri_alg == CRYPTO_MD5_HMAC) ++ ses->ses_mlen = MD5_HASH_LEN; ++ else ++ ses->ses_mlen = SHA1_HASH_LEN; ++ } ++ } ++ ++ /* really should make up a template td here, ++ * and only fill things like i/o and direction in process() */ ++ ++ /* assign session ID */ ++ *sidp = TALITOS_SID(sc->sc_num, sesn); ++ return 0; ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++talitos_freesession(device_t dev, u_int64_t tid) ++{ ++ struct talitos_softc *sc = device_get_softc(dev); ++ int session, ret; ++ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; ++ ++ if (sc == NULL) ++ return EINVAL; ++ session = TALITOS_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ memset(&sc->sc_sessions[session], 0, ++ sizeof(sc->sc_sessions[session])); ++ ret = 0; ++ } else ++ ret = EINVAL; ++ return ret; ++} ++ ++/* ++ * launch device processing - it will come back with done notification ++ * in the form of an interrupt and/or HDR_DONE_BITS in header ++ */ ++static int ++talitos_submit( ++ struct talitos_softc *sc, ++ struct talitos_desc *td, ++ int chsel) ++{ ++ u_int32_t v; ++ ++ v = dma_map_single(NULL, td, sizeof(*td), DMA_TO_DEVICE); ++ talitos_write(sc->sc_base_addr + ++ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF, 0); ++ talitos_write(sc->sc_base_addr + ++ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF_HI, v); ++ return 0; ++} ++ ++static int ++talitos_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ int i, err = 0, ivsize; ++ struct talitos_softc *sc = device_get_softc(dev); ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ caddr_t iv; ++ struct talitos_session *ses; ++ struct talitos_desc *td; ++ unsigned long flags; ++ /* descriptor mappings */ ++ int hmac_key, hmac_data, cipher_iv, cipher_key, ++ in_fifo, out_fifo, cipher_iv_out; ++ static int chsel = -1; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { ++ return EINVAL; ++ } ++ crp->crp_etype = 0; ++ if (TALITOS_SESSION(crp->crp_sid) >= sc->sc_nsessions) { ++ return EINVAL; ++ } ++ ++ ses = &sc->sc_sessions[TALITOS_SESSION(crp->crp_sid)]; ++ ++ /* enter the channel scheduler */ ++ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ /* reuse channel that already had/has requests for the required EU */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ if (sc->sc_chnlastalg[i] == crp->crp_desc->crd_alg) ++ break; ++ } ++ if (i == sc->sc_num_channels) { ++ /* ++ * haven't seen this algo the last sc_num_channels or more ++ * use round robin in this case ++ * nb: sc->sc_num_channels must be power of 2 ++ */ ++ chsel = (chsel + 1) & (sc->sc_num_channels - 1); ++ } else { ++ /* ++ * matches channel with same target execution unit; ++ * use same channel in this case ++ */ ++ chsel = i; ++ } ++ sc->sc_chnlastalg[chsel] = crp->crp_desc->crd_alg; ++ ++ /* release the channel scheduler lock */ ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ /* acquire the selected channel fifo lock */ ++ spin_lock_irqsave(&sc->sc_chnfifolock[chsel], flags); ++ ++ /* find and reserve next available descriptor-cryptop pair */ ++ for (i = 0; i < sc->sc_chfifo_len; i++) { ++ if (sc->sc_chnfifo[chsel][i].cf_desc.hdr == 0) { ++ /* ++ * ensure correct descriptor formation by ++ * avoiding inadvertently setting "optional" entries ++ * e.g. not using "optional" dptr2 for MD/HMAC descs ++ */ ++ memset(&sc->sc_chnfifo[chsel][i].cf_desc, ++ 0, sizeof(*td)); ++ /* reserve it with done notification request bit */ ++ sc->sc_chnfifo[chsel][i].cf_desc.hdr |= ++ TALITOS_DONE_NOTIFY; ++ break; ++ } ++ } ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[chsel], flags); ++ ++ if (i == sc->sc_chfifo_len) { ++ /* fifo full */ ++ err = ERESTART; ++ goto errout; ++ } ++ ++ td = &sc->sc_chnfifo[chsel][i].cf_desc; ++ sc->sc_chnfifo[chsel][i].cf_crp = crp; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ /* prevent compiler warning */ ++ hmac_key = 0; ++ hmac_data = 0; ++ if (crd2 == NULL) { ++ td->hdr |= TD_TYPE_COMMON_NONSNOOP_NO_AFEU; ++ /* assign descriptor dword ptr mappings for this desc. type */ ++ cipher_iv = 1; ++ cipher_key = 2; ++ in_fifo = 3; ++ cipher_iv_out = 5; ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1 || ++ crd1->crd_alg == CRYPTO_MD5) { ++ out_fifo = 5; ++ maccrd = crd1; ++ enccrd = NULL; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4) { ++ out_fifo = 4; ++ maccrd = NULL; ++ enccrd = crd1; ++ } else { ++ DPRINTF("UNKNOWN crd1->crd_alg %d\n", crd1->crd_alg); ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if (sc->sc_desc_types & TALITOS_HAS_DT_IPSEC_ESP) { ++ td->hdr |= TD_TYPE_IPSEC_ESP; ++ } else { ++ DPRINTF("unimplemented: multiple descriptor ipsec\n"); ++ err = EINVAL; ++ goto errout; ++ } ++ /* assign descriptor dword ptr mappings for this desc. type */ ++ hmac_key = 0; ++ hmac_data = 1; ++ cipher_iv = 2; ++ cipher_key = 3; ++ in_fifo = 4; ++ out_fifo = 5; ++ cipher_iv_out = 6; ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_MD5 || ++ crd1->crd_alg == CRYPTO_SHA1) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC || ++ crd2->crd_alg == CRYPTO_ARC4) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4 || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC || ++ crd2->crd_alg == CRYPTO_MD5 || ++ crd2->crd_alg == CRYPTO_SHA1) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ /* We cannot order the SEC as requested */ ++ printk("%s: cannot do the order\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ /* assign in_fifo and out_fifo based on input/output struct type */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ /* using SKB buffers */ ++ struct sk_buff *skb = (struct sk_buff *)crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ printk("%s: skb frags unimplemented\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ td->ptr[in_fifo].ptr = dma_map_single(NULL, skb->data, ++ skb->len, DMA_TO_DEVICE); ++ td->ptr[in_fifo].len = skb->len; ++ td->ptr[out_fifo].ptr = dma_map_single(NULL, skb->data, ++ skb->len, DMA_TO_DEVICE); ++ td->ptr[out_fifo].len = skb->len; ++ td->ptr[hmac_data].ptr = dma_map_single(NULL, skb->data, ++ skb->len, DMA_TO_DEVICE); ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ /* using IOV buffers */ ++ struct uio *uiop = (struct uio *)crp->crp_buf; ++ if (uiop->uio_iovcnt > 1) { ++ printk("%s: iov frags unimplemented\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ td->ptr[in_fifo].ptr = dma_map_single(NULL, ++ uiop->uio_iov->iov_base, crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[in_fifo].len = crp->crp_ilen; ++ /* crp_olen is never set; always use crp_ilen */ ++ td->ptr[out_fifo].ptr = dma_map_single(NULL, ++ uiop->uio_iov->iov_base, ++ crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[out_fifo].len = crp->crp_ilen; ++ } else { ++ /* using contig buffers */ ++ td->ptr[in_fifo].ptr = dma_map_single(NULL, ++ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[in_fifo].len = crp->crp_ilen; ++ td->ptr[out_fifo].ptr = dma_map_single(NULL, ++ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[out_fifo].len = crp->crp_ilen; ++ } ++ if (enccrd) { ++ switch (enccrd->crd_alg) { ++ case CRYPTO_3DES_CBC: ++ td->hdr |= TALITOS_MODE0_DEU_3DES; ++ /* FALLTHROUGH */ ++ case CRYPTO_DES_CBC: ++ td->hdr |= TALITOS_SEL0_DEU ++ | TALITOS_MODE0_DEU_CBC; ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) ++ td->hdr |= TALITOS_MODE0_DEU_ENC; ++ ivsize = 2*sizeof(u_int32_t); ++ DPRINTF("%cDES ses %d ch %d len %d\n", ++ (td->hdr & TALITOS_MODE0_DEU_3DES)?'3':'1', ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ case CRYPTO_AES_CBC: ++ td->hdr |= TALITOS_SEL0_AESU ++ | TALITOS_MODE0_AESU_CBC; ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) ++ td->hdr |= TALITOS_MODE0_AESU_ENC; ++ ivsize = 4*sizeof(u_int32_t); ++ DPRINTF("AES ses %d ch %d len %d\n", ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ default: ++ printk("%s: unimplemented enccrd->crd_alg %d\n", ++ device_get_nameunit(sc->sc_cdev), enccrd->crd_alg); ++ err = EINVAL; ++ goto errout; ++ } ++ /* ++ * Setup encrypt/decrypt state. When using basic ops ++ * we can't use an inline IV because hash/crypt offset ++ * must be from the end of the IV to the start of the ++ * crypt data and this leaves out the preceding header ++ * from the hash calculation. Instead we place the IV ++ * in the state record and set the hash/crypt offset to ++ * copy both the header+IV. ++ */ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ td->hdr |= TALITOS_DIR_OUTBOUND; ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ iv = enccrd->crd_iv; ++ else ++ iv = (caddr_t) ses->ses_iv; ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, iv); ++ } ++ } else { ++ td->hdr |= TALITOS_DIR_INBOUND; ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ iv = enccrd->crd_iv; ++ bcopy(enccrd->crd_iv, iv, ivsize); ++ } else { ++ iv = (caddr_t) ses->ses_iv; ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, iv); ++ } ++ } ++ td->ptr[cipher_iv].ptr = dma_map_single(NULL, iv, ivsize, ++ DMA_TO_DEVICE); ++ td->ptr[cipher_iv].len = ivsize; ++ /* ++ * we don't need the cipher iv out length/pointer ++ * field to do ESP IPsec. Therefore we set the len field as 0, ++ * which tells the SEC not to do anything with this len/ptr ++ * field. Previously, when length/pointer as pointing to iv, ++ * it gave us corruption of packets. ++ */ ++ td->ptr[cipher_iv_out].len = 0; ++ } ++ if (enccrd && maccrd) { ++ /* this is ipsec only for now */ ++ td->hdr |= TALITOS_SEL1_MDEU ++ | TALITOS_MODE1_MDEU_INIT ++ | TALITOS_MODE1_MDEU_PAD; ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ td->hdr |= TALITOS_MODE1_MDEU_MD5; ++ break; ++ case CRYPTO_MD5_HMAC: ++ td->hdr |= TALITOS_MODE1_MDEU_MD5_HMAC; ++ break; ++ case CRYPTO_SHA1: ++ td->hdr |= TALITOS_MODE1_MDEU_SHA1; ++ break; ++ case CRYPTO_SHA1_HMAC: ++ td->hdr |= TALITOS_MODE1_MDEU_SHA1_HMAC; ++ break; ++ default: ++ /* We cannot order the SEC as requested */ ++ printk("%s: cannot do the order\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || ++ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { ++ /* ++ * The offset from hash data to the start of ++ * crypt data is the difference in the skips. ++ */ ++ /* ipsec only for now */ ++ td->ptr[hmac_key].ptr = dma_map_single(NULL, ++ ses->ses_hmac, ses->ses_hmac_len, DMA_TO_DEVICE); ++ td->ptr[hmac_key].len = ses->ses_hmac_len; ++ td->ptr[in_fifo].ptr += enccrd->crd_skip; ++ td->ptr[in_fifo].len = enccrd->crd_len; ++ td->ptr[out_fifo].ptr += enccrd->crd_skip; ++ td->ptr[out_fifo].len = enccrd->crd_len; ++ /* bytes of HMAC to postpend to ciphertext */ ++ td->ptr[out_fifo].extent = ses->ses_mlen; ++ td->ptr[hmac_data].ptr += maccrd->crd_skip; ++ td->ptr[hmac_data].len = enccrd->crd_skip - maccrd->crd_skip; ++ } ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ printk("%s: CRD_F_KEY_EXPLICIT unimplemented\n", ++ device_get_nameunit(sc->sc_cdev)); ++ } ++ } ++ if (!enccrd && maccrd) { ++ /* single MD5 or SHA */ ++ td->hdr |= TALITOS_SEL0_MDEU ++ | TALITOS_MODE0_MDEU_INIT ++ | TALITOS_MODE0_MDEU_PAD; ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ td->hdr |= TALITOS_MODE0_MDEU_MD5; ++ DPRINTF("MD5 ses %d ch %d len %d\n", ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ case CRYPTO_MD5_HMAC: ++ td->hdr |= TALITOS_MODE0_MDEU_MD5_HMAC; ++ break; ++ case CRYPTO_SHA1: ++ td->hdr |= TALITOS_MODE0_MDEU_SHA1; ++ DPRINTF("SHA1 ses %d ch %d len %d\n", ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ td->hdr |= TALITOS_MODE0_MDEU_SHA1_HMAC; ++ break; ++ default: ++ /* We cannot order the SEC as requested */ ++ DPRINTF("cannot do the order\n"); ++ err = EINVAL; ++ goto errout; ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_IOV) ++ td->ptr[out_fifo].ptr += maccrd->crd_inject; ++ ++ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || ++ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { ++ td->ptr[hmac_key].ptr = dma_map_single(NULL, ++ ses->ses_hmac, ses->ses_hmac_len, ++ DMA_TO_DEVICE); ++ td->ptr[hmac_key].len = ses->ses_hmac_len; ++ } ++ } ++ else { ++ /* using process key (session data has duplicate) */ ++ td->ptr[cipher_key].ptr = dma_map_single(NULL, ++ enccrd->crd_key, (enccrd->crd_klen + 7) / 8, ++ DMA_TO_DEVICE); ++ td->ptr[cipher_key].len = (enccrd->crd_klen + 7) / 8; ++ } ++ /* descriptor complete - GO! */ ++ return talitos_submit(sc, td, chsel); ++ ++errout: ++ if (err != ERESTART) { ++ crp->crp_etype = err; ++ crypto_done(crp); ++ } ++ return err; ++} ++ ++/* go through all channels descriptors, notifying OCF what has ++ * _and_hasn't_ successfully completed and reset the device ++ * (otherwise it's up to decoding desc hdrs!) ++ */ ++static void talitos_errorprocessing(struct talitos_softc *sc) ++{ ++ unsigned long flags; ++ int i, j; ++ ++ /* disable further scheduling until under control */ ++ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ if (debug) dump_talitos_status(sc); ++ /* go through descriptors, try and salvage those successfully done, ++ * and EIO those that weren't ++ */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); ++ for (j = 0; j < sc->sc_chfifo_len; j++) { ++ if (sc->sc_chnfifo[i][j].cf_desc.hdr) { ++ if ((sc->sc_chnfifo[i][j].cf_desc.hdr ++ & TALITOS_HDR_DONE_BITS) ++ != TALITOS_HDR_DONE_BITS) { ++ /* this one didn't finish */ ++ /* signify in crp->etype */ ++ sc->sc_chnfifo[i][j].cf_crp->crp_etype ++ = EIO; ++ } ++ } else ++ continue; /* free entry */ ++ /* either way, notify ocf */ ++ crypto_done(sc->sc_chnfifo[i][j].cf_crp); ++ /* and tag it available again ++ * ++ * memset to ensure correct descriptor formation by ++ * avoiding inadvertently setting "optional" entries ++ * e.g. not using "optional" dptr2 MD/HMAC processing ++ */ ++ memset(&sc->sc_chnfifo[i][j].cf_desc, ++ 0, sizeof(struct talitos_desc)); ++ } ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); ++ } ++ /* reset and initialize the SEC h/w device */ ++ talitos_reset_device(sc); ++ talitos_init_device(sc); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) ++ talitos_rng_init(sc); ++#endif ++ ++ /* Okay. Stand by. */ ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ return; ++} ++ ++/* go through all channels descriptors, notifying OCF what's been done */ ++static void talitos_doneprocessing(struct talitos_softc *sc) ++{ ++ unsigned long flags; ++ int i, j; ++ ++ /* go through descriptors looking for done bits */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); ++ for (j = 0; j < sc->sc_chfifo_len; j++) { ++ /* descriptor has done bits set? */ ++ if ((sc->sc_chnfifo[i][j].cf_desc.hdr ++ & TALITOS_HDR_DONE_BITS) ++ == TALITOS_HDR_DONE_BITS) { ++ /* notify ocf */ ++ crypto_done(sc->sc_chnfifo[i][j].cf_crp); ++ /* and tag it available again ++ * ++ * memset to ensure correct descriptor formation by ++ * avoiding inadvertently setting "optional" entries ++ * e.g. not using "optional" dptr2 MD/HMAC processing ++ */ ++ memset(&sc->sc_chnfifo[i][j].cf_desc, ++ 0, sizeof(struct talitos_desc)); ++ } ++ } ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); ++ } ++ return; ++} ++ ++static irqreturn_t ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++talitos_intr(int irq, void *arg) ++#else ++talitos_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct talitos_softc *sc = arg; ++ u_int32_t v, v_hi; ++ ++ /* ack */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); ++ talitos_write(sc->sc_base_addr + TALITOS_ICR, v); ++ talitos_write(sc->sc_base_addr + TALITOS_ICR_HI, v_hi); ++ ++ if (unlikely(v & TALITOS_ISR_ERROR)) { ++ /* Okay, Houston, we've had a problem here. */ ++ printk(KERN_DEBUG "%s: got error interrupt - ISR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ talitos_errorprocessing(sc); ++ } else ++ if (likely(v & TALITOS_ISR_DONE)) { ++ talitos_doneprocessing(sc); ++ } ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Initialize registers we need to touch only once. ++ */ ++static void ++talitos_init_device(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* init all channels */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + ++ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI); ++ v |= TALITOS_CH_CCCR_HI_CDWE ++ | TALITOS_CH_CCCR_HI_CDIE; /* invoke interrupt if done */ ++ talitos_write(sc->sc_base_addr + ++ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI, v); ++ } ++ /* enable all interrupts */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); ++ v |= TALITOS_IMR_ALL; ++ talitos_write(sc->sc_base_addr + TALITOS_IMR, v); ++ v = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); ++ v |= TALITOS_IMR_HI_ERRONLY; ++ talitos_write(sc->sc_base_addr + TALITOS_IMR_HI, v); ++ return; ++} ++ ++/* ++ * set the master reset bit on the device. ++ */ ++static void ++talitos_reset_device_master(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ ++ /* Reset the device by writing 1 to MCR:SWR and waiting 'til cleared */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); ++ talitos_write(sc->sc_base_addr + TALITOS_MCR, v | TALITOS_MCR_SWR); ++ ++ while (talitos_read(sc->sc_base_addr + TALITOS_MCR) & TALITOS_MCR_SWR) ++ cpu_relax(); ++ ++ return; ++} ++ ++/* ++ * Resets the device. Values in the registers are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++static void ++talitos_reset_device(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* ++ * Master reset ++ * errata documentation: warning: certain SEC interrupts ++ * are not fully cleared by writing the MCR:SWR bit, ++ * set bit twice to completely reset ++ */ ++ talitos_reset_device_master(sc); /* once */ ++ talitos_reset_device_master(sc); /* and once again */ ++ ++ /* reset all channels */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCCR); ++ talitos_write(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCCR, v | TALITOS_CH_CCCR_RESET); ++ } ++} ++ ++/* Set up the crypto device structure, private data, ++ * and anything else we need before we start */ ++#ifdef CONFIG_PPC_MERGE ++static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match) ++#else ++static int talitos_probe(struct platform_device *pdev) ++#endif ++{ ++ struct talitos_softc *sc = NULL; ++ struct resource *r; ++#ifdef CONFIG_PPC_MERGE ++ struct device *device = &ofdev->dev; ++ struct device_node *np = ofdev->node; ++ const unsigned int *prop; ++ int err; ++ struct resource res; ++#endif ++ static int num_chips = 0; ++ int rc; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ sc = (struct talitos_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return -ENOMEM; ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, DRV_NAME, num_chips, talitos_methods); ++ ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++#ifndef CONFIG_PPC_MERGE ++ sc->sc_dev = pdev; ++#endif ++ sc->sc_num = num_chips++; ++ ++#ifdef CONFIG_PPC_MERGE ++ dev_set_drvdata(device, sc); ++#else ++ platform_set_drvdata(sc->sc_dev, sc); ++#endif ++ ++ /* get the irq line */ ++#ifdef CONFIG_PPC_MERGE ++ err = of_address_to_resource(np, 0, &res); ++ if (err) ++ return -EINVAL; ++ r = &res; ++ ++ sc->sc_irq = irq_of_parse_and_map(np, 0); ++#else ++ /* get a pointer to the register memory */ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ sc->sc_irq = platform_get_irq(pdev, 0); ++#endif ++ rc = request_irq(sc->sc_irq, talitos_intr, 0, ++ device_get_nameunit(sc->sc_cdev), sc); ++ if (rc) { ++ printk(KERN_ERR "%s: failed to hook irq %d\n", ++ device_get_nameunit(sc->sc_cdev), sc->sc_irq); ++ sc->sc_irq = -1; ++ goto out; ++ } ++ ++ sc->sc_base_addr = (ocf_iomem_t) ioremap(r->start, (r->end - r->start)); ++ if (!sc->sc_base_addr) { ++ printk(KERN_ERR "%s: failed to ioremap\n", ++ device_get_nameunit(sc->sc_cdev)); ++ goto out; ++ } ++ ++ /* figure out our SEC's properties and capabilities */ ++ sc->sc_chiprev = (u64)talitos_read(sc->sc_base_addr + TALITOS_ID) << 32 ++ | talitos_read(sc->sc_base_addr + TALITOS_ID_HI); ++ DPRINTF("sec id 0x%llx\n", sc->sc_chiprev); ++ ++#ifdef CONFIG_PPC_MERGE ++ /* get SEC properties from device tree, defaulting to SEC 2.0 */ ++ ++ prop = of_get_property(np, "num-channels", NULL); ++ sc->sc_num_channels = prop ? *prop : TALITOS_NCHANNELS_SEC_2_0; ++ ++ prop = of_get_property(np, "channel-fifo-len", NULL); ++ sc->sc_chfifo_len = prop ? *prop : TALITOS_CHFIFOLEN_SEC_2_0; ++ ++ prop = of_get_property(np, "exec-units-mask", NULL); ++ sc->sc_exec_units = prop ? *prop : TALITOS_HAS_EUS_SEC_2_0; ++ ++ prop = of_get_property(np, "descriptor-types-mask", NULL); ++ sc->sc_desc_types = prop ? *prop : TALITOS_HAS_DESCTYPES_SEC_2_0; ++#else ++ /* bulk should go away with openfirmware flat device tree support */ ++ if (sc->sc_chiprev & TALITOS_ID_SEC_2_0) { ++ sc->sc_num_channels = TALITOS_NCHANNELS_SEC_2_0; ++ sc->sc_chfifo_len = TALITOS_CHFIFOLEN_SEC_2_0; ++ sc->sc_exec_units = TALITOS_HAS_EUS_SEC_2_0; ++ sc->sc_desc_types = TALITOS_HAS_DESCTYPES_SEC_2_0; ++ } else { ++ printk(KERN_ERR "%s: failed to id device\n", ++ device_get_nameunit(sc->sc_cdev)); ++ goto out; ++ } ++#endif ++ ++ /* + 1 is for the meta-channel lock used by the channel scheduler */ ++ sc->sc_chnfifolock = (spinlock_t *) kmalloc( ++ (sc->sc_num_channels + 1) * sizeof(spinlock_t), GFP_KERNEL); ++ if (!sc->sc_chnfifolock) ++ goto out; ++ for (i = 0; i < sc->sc_num_channels + 1; i++) { ++ spin_lock_init(&sc->sc_chnfifolock[i]); ++ } ++ ++ sc->sc_chnlastalg = (int *) kmalloc( ++ sc->sc_num_channels * sizeof(int), GFP_KERNEL); ++ if (!sc->sc_chnlastalg) ++ goto out; ++ memset(sc->sc_chnlastalg, 0, sc->sc_num_channels * sizeof(int)); ++ ++ sc->sc_chnfifo = (struct desc_cryptop_pair **) kmalloc( ++ sc->sc_num_channels * sizeof(struct desc_cryptop_pair *), ++ GFP_KERNEL); ++ if (!sc->sc_chnfifo) ++ goto out; ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ sc->sc_chnfifo[i] = (struct desc_cryptop_pair *) kmalloc( ++ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair), ++ GFP_KERNEL); ++ if (!sc->sc_chnfifo[i]) ++ goto out; ++ memset(sc->sc_chnfifo[i], 0, ++ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair)); ++ } ++ ++ /* reset and initialize the SEC h/w device */ ++ talitos_reset_device(sc); ++ talitos_init_device(sc); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ printk(KERN_ERR "%s: could not get crypto driver id\n", ++ device_get_nameunit(sc->sc_cdev)); ++ goto out; ++ } ++ ++ /* register algorithms with the framework */ ++ printk("%s:", device_get_nameunit(sc->sc_cdev)); ++ ++ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) { ++ printk(" rng"); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ talitos_rng_init(sc); ++ crypto_rregister(sc->sc_cid, talitos_read_random, sc); ++#endif ++ } ++ if (sc->sc_exec_units & TALITOS_HAS_EU_DEU) { ++ printk(" des/3des"); ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ } ++ if (sc->sc_exec_units & TALITOS_HAS_EU_AESU) { ++ printk(" aes"); ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ } ++ if (sc->sc_exec_units & TALITOS_HAS_EU_MDEU) { ++ printk(" md5"); ++ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); ++ /* HMAC support only with IPsec for now */ ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ printk(" sha1"); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); ++ /* HMAC support only with IPsec for now */ ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ } ++ printk("\n"); ++ return 0; ++ ++out: ++#ifndef CONFIG_PPC_MERGE ++ talitos_remove(pdev); ++#endif ++ return -ENOMEM; ++} ++ ++#ifdef CONFIG_PPC_MERGE ++static int talitos_remove(struct of_device *ofdev) ++#else ++static int talitos_remove(struct platform_device *pdev) ++#endif ++{ ++#ifdef CONFIG_PPC_MERGE ++ struct talitos_softc *sc = dev_get_drvdata(&ofdev->dev); ++#else ++ struct talitos_softc *sc = platform_get_drvdata(pdev); ++#endif ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_chnfifo) { ++ for (i = 0; i < sc->sc_num_channels; i++) ++ if (sc->sc_chnfifo[i]) ++ kfree(sc->sc_chnfifo[i]); ++ kfree(sc->sc_chnfifo); ++ } ++ if (sc->sc_chnlastalg) ++ kfree(sc->sc_chnlastalg); ++ if (sc->sc_chnfifolock) ++ kfree(sc->sc_chnfifolock); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_base_addr) ++ iounmap((void *) sc->sc_base_addr); ++ kfree(sc); ++ return 0; ++} ++ ++#ifdef CONFIG_PPC_MERGE ++static struct of_device_id talitos_match[] = { ++ { ++ .type = "crypto", ++ .compatible = "talitos", ++ }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, talitos_match); ++ ++static struct of_platform_driver talitos_driver = { ++ .name = DRV_NAME, ++ .match_table = talitos_match, ++ .probe = talitos_probe, ++ .remove = talitos_remove, ++}; ++ ++static int __init talitos_init(void) ++{ ++ return of_register_platform_driver(&talitos_driver); ++} ++ ++static void __exit talitos_exit(void) ++{ ++ of_unregister_platform_driver(&talitos_driver); ++} ++#else ++/* Structure for a platform device driver */ ++static struct platform_driver talitos_driver = { ++ .probe = talitos_probe, ++ .remove = talitos_remove, ++ .driver = { ++ .name = "fsl-sec2", ++ } ++}; ++ ++static int __init talitos_init(void) ++{ ++ return platform_driver_register(&talitos_driver); ++} ++ ++static void __exit talitos_exit(void) ++{ ++ platform_driver_unregister(&talitos_driver); ++} ++#endif ++ ++module_init(talitos_init); ++module_exit(talitos_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("kim.phillips@freescale.com"); ++MODULE_DESCRIPTION("OCF driver for Freescale SEC (talitos)"); +diff -Nur linux-2.6.39.orig/crypto/ocf/talitos/talitos_dev.h linux-2.6.39/crypto/ocf/talitos/talitos_dev.h +--- linux-2.6.39.orig/crypto/ocf/talitos/talitos_dev.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/talitos/talitos_dev.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,277 @@ ++/* ++ * Freescale SEC (talitos) device dependent data structures ++ * ++ * Copyright (c) 2006 Freescale Semiconductor, Inc. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ */ ++ ++/* device ID register values */ ++#define TALITOS_ID_SEC_2_0 0x40 ++#define TALITOS_ID_SEC_2_1 0x40 /* cross ref with IP block revision reg */ ++ ++/* ++ * following num_channels, channel-fifo-depth, exec-unit-mask, and ++ * descriptor-types-mask are for forward-compatibility with openfirmware ++ * flat device trees ++ */ ++ ++/* ++ * num_channels : the number of channels available in each SEC version. ++ */ ++ ++/* n.b. this driver requires these values be a power of 2 */ ++#define TALITOS_NCHANNELS_SEC_1_0 4 ++#define TALITOS_NCHANNELS_SEC_1_2 1 ++#define TALITOS_NCHANNELS_SEC_2_0 4 ++#define TALITOS_NCHANNELS_SEC_2_01 4 ++#define TALITOS_NCHANNELS_SEC_2_1 4 ++#define TALITOS_NCHANNELS_SEC_2_4 4 ++ ++/* ++ * channel-fifo-depth : The number of descriptor ++ * pointers a channel fetch fifo can hold. ++ */ ++#define TALITOS_CHFIFOLEN_SEC_1_0 1 ++#define TALITOS_CHFIFOLEN_SEC_1_2 1 ++#define TALITOS_CHFIFOLEN_SEC_2_0 24 ++#define TALITOS_CHFIFOLEN_SEC_2_01 24 ++#define TALITOS_CHFIFOLEN_SEC_2_1 24 ++#define TALITOS_CHFIFOLEN_SEC_2_4 24 ++ ++/* ++ * exec-unit-mask : The bitmask representing what Execution Units (EUs) ++ * are available. EU information should be encoded following the SEC's ++ * EU_SEL0 bitfield documentation, i.e. as follows: ++ * ++ * bit 31 = set if SEC permits no-EU selection (should be always set) ++ * bit 30 = set if SEC has the ARC4 EU (AFEU) ++ * bit 29 = set if SEC has the des/3des EU (DEU) ++ * bit 28 = set if SEC has the message digest EU (MDEU) ++ * bit 27 = set if SEC has the random number generator EU (RNG) ++ * bit 26 = set if SEC has the public key EU (PKEU) ++ * bit 25 = set if SEC has the aes EU (AESU) ++ * bit 24 = set if SEC has the Kasumi EU (KEU) ++ * ++ */ ++#define TALITOS_HAS_EU_NONE (1<<0) ++#define TALITOS_HAS_EU_AFEU (1<<1) ++#define TALITOS_HAS_EU_DEU (1<<2) ++#define TALITOS_HAS_EU_MDEU (1<<3) ++#define TALITOS_HAS_EU_RNG (1<<4) ++#define TALITOS_HAS_EU_PKEU (1<<5) ++#define TALITOS_HAS_EU_AESU (1<<6) ++#define TALITOS_HAS_EU_KEU (1<<7) ++ ++/* the corresponding masks for each SEC version */ ++#define TALITOS_HAS_EUS_SEC_1_0 0x7f ++#define TALITOS_HAS_EUS_SEC_1_2 0x4d ++#define TALITOS_HAS_EUS_SEC_2_0 0x7f ++#define TALITOS_HAS_EUS_SEC_2_01 0x7f ++#define TALITOS_HAS_EUS_SEC_2_1 0xff ++#define TALITOS_HAS_EUS_SEC_2_4 0x7f ++ ++/* ++ * descriptor-types-mask : The bitmask representing what descriptors ++ * are available. Descriptor type information should be encoded ++ * following the SEC's Descriptor Header Dword DESC_TYPE field ++ * documentation, i.e. as follows: ++ * ++ * bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type ++ * bit 1 = set if SEC supports the ipsec_esp descriptor type ++ * bit 2 = set if SEC supports the common_nonsnoop desc. type ++ * bit 3 = set if SEC supports the 802.11i AES ccmp desc. type ++ * bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type ++ * bit 5 = set if SEC supports the srtp descriptor type ++ * bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type ++ * bit 7 = set if SEC supports the pkeu_assemble descriptor type ++ * bit 8 = set if SEC supports the aesu_key_expand_output desc.type ++ * bit 9 = set if SEC supports the pkeu_ptmul descriptor type ++ * bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type ++ * bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type ++ * ++ * ..and so on and so forth. ++ */ ++#define TALITOS_HAS_DT_AESU_CTR_NONSNOOP (1<<0) ++#define TALITOS_HAS_DT_IPSEC_ESP (1<<1) ++#define TALITOS_HAS_DT_COMMON_NONSNOOP (1<<2) ++ ++/* the corresponding masks for each SEC version */ ++#define TALITOS_HAS_DESCTYPES_SEC_2_0 0x01010ebf ++#define TALITOS_HAS_DESCTYPES_SEC_2_1 0x012b0ebf ++ ++/* ++ * a TALITOS_xxx_HI address points to the low data bits (32-63) of the register ++ */ ++ ++/* global register offset addresses */ ++#define TALITOS_ID 0x1020 ++#define TALITOS_ID_HI 0x1024 ++#define TALITOS_MCR 0x1030 /* master control register */ ++#define TALITOS_MCR_HI 0x1038 /* master control register */ ++#define TALITOS_MCR_SWR 0x1 ++#define TALITOS_IMR 0x1008 /* interrupt mask register */ ++#define TALITOS_IMR_ALL 0x00010fff /* enable all interrupts mask */ ++#define TALITOS_IMR_ERRONLY 0x00010aaa /* enable error interrupts */ ++#define TALITOS_IMR_HI 0x100C /* interrupt mask register */ ++#define TALITOS_IMR_HI_ALL 0x00323333 /* enable all interrupts mask */ ++#define TALITOS_IMR_HI_ERRONLY 0x00222222 /* enable error interrupts */ ++#define TALITOS_ISR 0x1010 /* interrupt status register */ ++#define TALITOS_ISR_ERROR 0x00010faa /* errors mask */ ++#define TALITOS_ISR_DONE 0x00000055 /* channel(s) done mask */ ++#define TALITOS_ISR_HI 0x1014 /* interrupt status register */ ++#define TALITOS_ICR 0x1018 /* interrupt clear register */ ++#define TALITOS_ICR_HI 0x101C /* interrupt clear register */ ++ ++/* channel register address stride */ ++#define TALITOS_CH_OFFSET 0x100 ++ ++/* channel register offset addresses and bits */ ++#define TALITOS_CH_CCCR 0x1108 /* Crypto-Channel Config Register */ ++#define TALITOS_CH_CCCR_RESET 0x1 /* Channel Reset bit */ ++#define TALITOS_CH_CCCR_HI 0x110c /* Crypto-Channel Config Register */ ++#define TALITOS_CH_CCCR_HI_CDWE 0x10 /* Channel done writeback enable bit */ ++#define TALITOS_CH_CCCR_HI_NT 0x4 /* Notification type bit */ ++#define TALITOS_CH_CCCR_HI_CDIE 0x2 /* Channel Done Interrupt Enable bit */ ++#define TALITOS_CH_CCPSR 0x1110 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_CCPSR_HI 0x1114 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_FF 0x1148 /* Fetch FIFO */ ++#define TALITOS_CH_FF_HI 0x114c /* Fetch FIFO's FETCH_ADRS */ ++#define TALITOS_CH_CDPR 0x1140 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_CDPR_HI 0x1144 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_DESCBUF 0x1180 /* (thru 11bf) Crypto-Channel ++ * Descriptor Buffer (debug) */ ++ ++/* execution unit register offset addresses and bits */ ++#define TALITOS_DEUSR 0x2028 /* DEU status register */ ++#define TALITOS_DEUSR_HI 0x202c /* DEU status register */ ++#define TALITOS_DEUISR 0x2030 /* DEU interrupt status register */ ++#define TALITOS_DEUISR_HI 0x2034 /* DEU interrupt status register */ ++#define TALITOS_DEUICR 0x2038 /* DEU interrupt control register */ ++#define TALITOS_DEUICR_HI 0x203c /* DEU interrupt control register */ ++#define TALITOS_AESUISR 0x4030 /* AESU interrupt status register */ ++#define TALITOS_AESUISR_HI 0x4034 /* AESU interrupt status register */ ++#define TALITOS_AESUICR 0x4038 /* AESU interrupt control register */ ++#define TALITOS_AESUICR_HI 0x403c /* AESU interrupt control register */ ++#define TALITOS_MDEUISR 0x6030 /* MDEU interrupt status register */ ++#define TALITOS_MDEUISR_HI 0x6034 /* MDEU interrupt status register */ ++#define TALITOS_RNGSR 0xa028 /* RNG status register */ ++#define TALITOS_RNGSR_HI 0xa02c /* RNG status register */ ++#define TALITOS_RNGSR_HI_RD 0x1 /* RNG Reset done */ ++#define TALITOS_RNGSR_HI_OFL 0xff0000/* number of dwords in RNG output FIFO*/ ++#define TALITOS_RNGDSR 0xa010 /* RNG data size register */ ++#define TALITOS_RNGDSR_HI 0xa014 /* RNG data size register */ ++#define TALITOS_RNG_FIFO 0xa800 /* RNG FIFO - pool of random numbers */ ++#define TALITOS_RNGISR 0xa030 /* RNG Interrupt status register */ ++#define TALITOS_RNGISR_HI 0xa034 /* RNG Interrupt status register */ ++#define TALITOS_RNGRCR 0xa018 /* RNG Reset control register */ ++#define TALITOS_RNGRCR_HI 0xa01c /* RNG Reset control register */ ++#define TALITOS_RNGRCR_HI_SR 0x1 /* RNG RNGRCR:Software Reset */ ++ ++/* descriptor pointer entry */ ++struct talitos_desc_ptr { ++ u16 len; /* length */ ++ u8 extent; /* jump (to s/g link table) and extent */ ++ u8 res; /* reserved */ ++ u32 ptr; /* pointer */ ++}; ++ ++/* descriptor */ ++struct talitos_desc { ++ u32 hdr; /* header */ ++ u32 res; /* reserved */ ++ struct talitos_desc_ptr ptr[7]; /* ptr/len pair array */ ++}; ++ ++/* talitos descriptor header (hdr) bits */ ++ ++/* primary execution unit select */ ++#define TALITOS_SEL0_AFEU 0x10000000 ++#define TALITOS_SEL0_DEU 0x20000000 ++#define TALITOS_SEL0_MDEU 0x30000000 ++#define TALITOS_SEL0_RNG 0x40000000 ++#define TALITOS_SEL0_PKEU 0x50000000 ++#define TALITOS_SEL0_AESU 0x60000000 ++ ++/* primary execution unit mode (MODE0) and derivatives */ ++#define TALITOS_MODE0_AESU_CBC 0x00200000 ++#define TALITOS_MODE0_AESU_ENC 0x00100000 ++#define TALITOS_MODE0_DEU_CBC 0x00400000 ++#define TALITOS_MODE0_DEU_3DES 0x00200000 ++#define TALITOS_MODE0_DEU_ENC 0x00100000 ++#define TALITOS_MODE0_MDEU_INIT 0x01000000 /* init starting regs */ ++#define TALITOS_MODE0_MDEU_HMAC 0x00800000 ++#define TALITOS_MODE0_MDEU_PAD 0x00400000 /* PD */ ++#define TALITOS_MODE0_MDEU_MD5 0x00200000 ++#define TALITOS_MODE0_MDEU_SHA256 0x00100000 ++#define TALITOS_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */ ++#define TALITOS_MODE0_MDEU_MD5_HMAC \ ++ (TALITOS_MODE0_MDEU_MD5 | TALITOS_MODE0_MDEU_HMAC) ++#define TALITOS_MODE0_MDEU_SHA256_HMAC \ ++ (TALITOS_MODE0_MDEU_SHA256 | TALITOS_MODE0_MDEU_HMAC) ++#define TALITOS_MODE0_MDEU_SHA1_HMAC \ ++ (TALITOS_MODE0_MDEU_SHA1 | TALITOS_MODE0_MDEU_HMAC) ++ ++/* secondary execution unit select (SEL1) */ ++/* it's MDEU or nothing */ ++#define TALITOS_SEL1_MDEU 0x00030000 ++ ++/* secondary execution unit mode (MODE1) and derivatives */ ++#define TALITOS_MODE1_MDEU_INIT 0x00001000 /* init starting regs */ ++#define TALITOS_MODE1_MDEU_HMAC 0x00000800 ++#define TALITOS_MODE1_MDEU_PAD 0x00000400 /* PD */ ++#define TALITOS_MODE1_MDEU_MD5 0x00000200 ++#define TALITOS_MODE1_MDEU_SHA256 0x00000100 ++#define TALITOS_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */ ++#define TALITOS_MODE1_MDEU_MD5_HMAC \ ++ (TALITOS_MODE1_MDEU_MD5 | TALITOS_MODE1_MDEU_HMAC) ++#define TALITOS_MODE1_MDEU_SHA256_HMAC \ ++ (TALITOS_MODE1_MDEU_SHA256 | TALITOS_MODE1_MDEU_HMAC) ++#define TALITOS_MODE1_MDEU_SHA1_HMAC \ ++ (TALITOS_MODE1_MDEU_SHA1 | TALITOS_MODE1_MDEU_HMAC) ++ ++/* direction of overall data flow (DIR) */ ++#define TALITOS_DIR_OUTBOUND 0x00000000 ++#define TALITOS_DIR_INBOUND 0x00000002 ++ ++/* done notification (DN) */ ++#define TALITOS_DONE_NOTIFY 0x00000001 ++ ++/* descriptor types */ ++/* odd numbers here are valid on SEC2 and greater only (e.g. ipsec_esp) */ ++#define TD_TYPE_AESU_CTR_NONSNOOP (0 << 3) ++#define TD_TYPE_IPSEC_ESP (1 << 3) ++#define TD_TYPE_COMMON_NONSNOOP_NO_AFEU (2 << 3) ++#define TD_TYPE_HMAC_SNOOP_NO_AFEU (4 << 3) ++ ++#define TALITOS_HDR_DONE_BITS 0xff000000 ++ ++#define DPRINTF(a...) do { \ ++ if (debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_cdev) : "talitos"); \ ++ printk(a); \ ++ } \ ++ } while (0) +diff -Nur linux-2.6.39.orig/crypto/ocf/talitos/talitos_soft.h linux-2.6.39/crypto/ocf/talitos/talitos_soft.h +--- linux-2.6.39.orig/crypto/ocf/talitos/talitos_soft.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/talitos/talitos_soft.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,77 @@ ++/* ++ * Freescale SEC data structures for integration with ocf-linux ++ * ++ * Copyright (c) 2006 Freescale Semiconductor, Inc. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/* ++ * paired descriptor and associated crypto operation ++ */ ++struct desc_cryptop_pair { ++ struct talitos_desc cf_desc; /* descriptor ptr */ ++ struct cryptop *cf_crp; /* cryptop ptr */ ++}; ++ ++/* ++ * Holds data specific to a single talitos device. ++ */ ++struct talitos_softc { ++ softc_device_decl sc_cdev; ++ struct platform_device *sc_dev; /* device backpointer */ ++ ocf_iomem_t sc_base_addr; ++ int sc_irq; ++ int sc_num; /* if we have multiple chips */ ++ int32_t sc_cid; /* crypto tag */ ++ u64 sc_chiprev; /* major/minor chip revision */ ++ int sc_nsessions; ++ struct talitos_session *sc_sessions; ++ int sc_num_channels;/* number of crypto channels */ ++ int sc_chfifo_len; /* channel fetch fifo len */ ++ int sc_exec_units; /* execution units mask */ ++ int sc_desc_types; /* descriptor types mask */ ++ /* ++ * mutual exclusion for intra-channel resources, e.g. fetch fifos ++ * the last entry is a meta-channel lock used by the channel scheduler ++ */ ++ spinlock_t *sc_chnfifolock; ++ /* sc_chnlastalgo contains last algorithm for that channel */ ++ int *sc_chnlastalg; ++ /* sc_chnfifo holds pending descriptor--crypto operation pairs */ ++ struct desc_cryptop_pair **sc_chnfifo; ++}; ++ ++struct talitos_session { ++ u_int32_t ses_used; ++ u_int32_t ses_klen; /* key length in bits */ ++ u_int32_t ses_key[8]; /* DES/3DES/AES key */ ++ u_int32_t ses_hmac[5]; /* hmac inner state */ ++ u_int32_t ses_hmac_len; /* hmac length */ ++ u_int32_t ses_iv[4]; /* DES/3DES/AES iv */ ++ u_int32_t ses_mlen; /* desired hash result len (12=ipsec or 16) */ ++}; ++ ++#define TALITOS_SESSION(sid) ((sid) & 0x0fffffff) ++#define TALITOS_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) +diff -Nur linux-2.6.39.orig/crypto/ocf/uio.h linux-2.6.39/crypto/ocf/uio.h +--- linux-2.6.39.orig/crypto/ocf/uio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/crypto/ocf/uio.h 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,54 @@ ++#ifndef _OCF_UIO_H_ ++#define _OCF_UIO_H_ ++ ++#include ++ ++/* ++ * The linux uio.h doesn't have all we need. To be fully api compatible ++ * with the BSD cryptodev, we need to keep this around. Perhaps this can ++ * be moved back into the linux/uio.h ++ * ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ * --------------------------------------------------------------------------- ++ */ ++ ++struct uio { ++ struct iovec *uio_iov; ++ int uio_iovcnt; ++ off_t uio_offset; ++ int uio_resid; ++#if 0 ++ enum uio_seg uio_segflg; ++ enum uio_rw uio_rw; ++ struct thread *uio_td; ++#endif ++}; ++ ++#endif +diff -Nur linux-2.6.39.orig/drivers/char/random.c linux-2.6.39/drivers/char/random.c +--- linux-2.6.39.orig/drivers/char/random.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/char/random.c 2011-08-01 14:38:19.000000000 +0200 +@@ -130,6 +130,9 @@ + * void add_interrupt_randomness(int irq); + * void add_disk_randomness(struct gendisk *disk); + * ++ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++ * int random_input_wait(void); ++ * + * add_input_randomness() uses the input layer interrupt timing, as well as + * the event type information from the hardware. + * +@@ -147,6 +150,13 @@ + * seek times do not make for good sources of entropy, as their seek + * times are usually fairly consistent. + * ++ * random_input_words() just provides a raw block of entropy to the input ++ * pool, such as from a hardware entropy generator. ++ * ++ * random_input_wait() suspends the caller until such time as the ++ * entropy pool falls below the write threshold, and returns a count of how ++ * much entropy (in bits) is needed to sustain the pool. ++ * + * All of these routines try to estimate how many bits of randomness a + * particular randomness source. They do this by keeping track of the + * first and second order deltas of the event timings. +@@ -266,6 +276,7 @@ + #define SEC_XFER_SIZE 512 + #define EXTRACT_SIZE 10 + ++ + /* + * The minimum number of bits of entropy before we wake up a read on + * /dev/random. Should be enough to do a significant reseed. +@@ -559,6 +570,60 @@ + spin_unlock_irqrestore(&r->lock, flags); + } + ++/* ++ * random_input_words - add bulk entropy to pool ++ * ++ * @buf: buffer to add ++ * @wordcount: number of __u32 words to add ++ * @ent_count: total amount of entropy (in bits) to credit ++ * ++ * this provides bulk input of entropy to the input pool ++ * ++ */ ++void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++{ ++ mix_pool_bytes(&input_pool, buf, wordcount*4); ++ ++ credit_entropy_bits(&input_pool, ent_count); ++ ++ DEBUG_ENT("crediting %d bits => %d\n", ++ ent_count, input_pool.entropy_count); ++ /* ++ * Wake up waiting processes if we have enough ++ * entropy. ++ */ ++ if (input_pool.entropy_count >= random_read_wakeup_thresh) ++ wake_up_interruptible(&random_read_wait); ++} ++EXPORT_SYMBOL(random_input_words); ++ ++/* ++ * random_input_wait - wait until random needs entropy ++ * ++ * this function sleeps until the /dev/random subsystem actually ++ * needs more entropy, and then return the amount of entropy ++ * that it would be nice to have added to the system. ++ */ ++int random_input_wait(void) ++{ ++ int count; ++ ++ wait_event_interruptible(random_write_wait, ++ input_pool.entropy_count < random_write_wakeup_thresh); ++ ++ count = random_write_wakeup_thresh - input_pool.entropy_count; ++ ++ /* likely we got woken up due to a signal */ ++ if (count <= 0) count = random_read_wakeup_thresh; ++ ++ DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n", ++ count, ++ input_pool.entropy_count, random_write_wakeup_thresh); ++ ++ return count; ++} ++EXPORT_SYMBOL(random_input_wait); ++ + /********************************************************************* + * + * Entropy input management +diff -Nur linux-2.6.39.orig/drivers/char/random.c.orig linux-2.6.39/drivers/char/random.c.orig +--- linux-2.6.39.orig/drivers/char/random.c.orig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/char/random.c.orig 2011-08-01 14:38:19.000000000 +0200 +@@ -0,0 +1,1667 @@ ++/* ++ * random.c -- A strong random number generator ++ * ++ * Copyright Matt Mackall , 2003, 2004, 2005 ++ * ++ * Copyright Theodore Ts'o, 1994, 1995, 1996, 1997, 1998, 1999. All ++ * rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, and the entire permission notice in its entirety, ++ * including the disclaimer of warranties. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote ++ * products derived from this software without specific prior ++ * written permission. ++ * ++ * ALTERNATIVELY, this product may be distributed under the terms of ++ * the GNU General Public License, in which case the provisions of the GPL are ++ * required INSTEAD OF the above restrictions. (This clause is ++ * necessary due to a potential bad interaction between the GPL and ++ * the restrictions contained in a BSD-style copyright.) ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ALL OF ++ * WHICH ARE HEREBY DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ++ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ++ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF NOT ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ */ ++ ++/* ++ * (now, with legal B.S. out of the way.....) ++ * ++ * This routine gathers environmental noise from device drivers, etc., ++ * and returns good random numbers, suitable for cryptographic use. ++ * Besides the obvious cryptographic uses, these numbers are also good ++ * for seeding TCP sequence numbers, and other places where it is ++ * desirable to have numbers which are not only random, but hard to ++ * predict by an attacker. ++ * ++ * Theory of operation ++ * =================== ++ * ++ * Computers are very predictable devices. Hence it is extremely hard ++ * to produce truly random numbers on a computer --- as opposed to ++ * pseudo-random numbers, which can easily generated by using a ++ * algorithm. Unfortunately, it is very easy for attackers to guess ++ * the sequence of pseudo-random number generators, and for some ++ * applications this is not acceptable. So instead, we must try to ++ * gather "environmental noise" from the computer's environment, which ++ * must be hard for outside attackers to observe, and use that to ++ * generate random numbers. In a Unix environment, this is best done ++ * from inside the kernel. ++ * ++ * Sources of randomness from the environment include inter-keyboard ++ * timings, inter-interrupt timings from some interrupts, and other ++ * events which are both (a) non-deterministic and (b) hard for an ++ * outside observer to measure. Randomness from these sources are ++ * added to an "entropy pool", which is mixed using a CRC-like function. ++ * This is not cryptographically strong, but it is adequate assuming ++ * the randomness is not chosen maliciously, and it is fast enough that ++ * the overhead of doing it on every interrupt is very reasonable. ++ * As random bytes are mixed into the entropy pool, the routines keep ++ * an *estimate* of how many bits of randomness have been stored into ++ * the random number generator's internal state. ++ * ++ * When random bytes are desired, they are obtained by taking the SHA ++ * hash of the contents of the "entropy pool". The SHA hash avoids ++ * exposing the internal state of the entropy pool. It is believed to ++ * be computationally infeasible to derive any useful information ++ * about the input of SHA from its output. Even if it is possible to ++ * analyze SHA in some clever way, as long as the amount of data ++ * returned from the generator is less than the inherent entropy in ++ * the pool, the output data is totally unpredictable. For this ++ * reason, the routine decreases its internal estimate of how many ++ * bits of "true randomness" are contained in the entropy pool as it ++ * outputs random numbers. ++ * ++ * If this estimate goes to zero, the routine can still generate ++ * random numbers; however, an attacker may (at least in theory) be ++ * able to infer the future output of the generator from prior ++ * outputs. This requires successful cryptanalysis of SHA, which is ++ * not believed to be feasible, but there is a remote possibility. ++ * Nonetheless, these numbers should be useful for the vast majority ++ * of purposes. ++ * ++ * Exported interfaces ---- output ++ * =============================== ++ * ++ * There are three exported interfaces; the first is one designed to ++ * be used from within the kernel: ++ * ++ * void get_random_bytes(void *buf, int nbytes); ++ * ++ * This interface will return the requested number of random bytes, ++ * and place it in the requested buffer. ++ * ++ * The two other interfaces are two character devices /dev/random and ++ * /dev/urandom. /dev/random is suitable for use when very high ++ * quality randomness is desired (for example, for key generation or ++ * one-time pads), as it will only return a maximum of the number of ++ * bits of randomness (as estimated by the random number generator) ++ * contained in the entropy pool. ++ * ++ * The /dev/urandom device does not have this limit, and will return ++ * as many bytes as are requested. As more and more random bytes are ++ * requested without giving time for the entropy pool to recharge, ++ * this will result in random numbers that are merely cryptographically ++ * strong. For many applications, however, this is acceptable. ++ * ++ * Exported interfaces ---- input ++ * ============================== ++ * ++ * The current exported interfaces for gathering environmental noise ++ * from the devices are: ++ * ++ * void add_input_randomness(unsigned int type, unsigned int code, ++ * unsigned int value); ++ * void add_interrupt_randomness(int irq); ++ * void add_disk_randomness(struct gendisk *disk); ++ * ++ * add_input_randomness() uses the input layer interrupt timing, as well as ++ * the event type information from the hardware. ++ * ++ * add_interrupt_randomness() uses the inter-interrupt timing as random ++ * inputs to the entropy pool. Note that not all interrupts are good ++ * sources of randomness! For example, the timer interrupts is not a ++ * good choice, because the periodicity of the interrupts is too ++ * regular, and hence predictable to an attacker. Network Interface ++ * Controller interrupts are a better measure, since the timing of the ++ * NIC interrupts are more unpredictable. ++ * ++ * add_disk_randomness() uses what amounts to the seek time of block ++ * layer request events, on a per-disk_devt basis, as input to the ++ * entropy pool. Note that high-speed solid state drives with very low ++ * seek times do not make for good sources of entropy, as their seek ++ * times are usually fairly consistent. ++ * ++ * All of these routines try to estimate how many bits of randomness a ++ * particular randomness source. They do this by keeping track of the ++ * first and second order deltas of the event timings. ++ * ++ * Ensuring unpredictability at system startup ++ * ============================================ ++ * ++ * When any operating system starts up, it will go through a sequence ++ * of actions that are fairly predictable by an adversary, especially ++ * if the start-up does not involve interaction with a human operator. ++ * This reduces the actual number of bits of unpredictability in the ++ * entropy pool below the value in entropy_count. In order to ++ * counteract this effect, it helps to carry information in the ++ * entropy pool across shut-downs and start-ups. To do this, put the ++ * following lines an appropriate script which is run during the boot ++ * sequence: ++ * ++ * echo "Initializing random number generator..." ++ * random_seed=/var/run/random-seed ++ * # Carry a random seed from start-up to start-up ++ * # Load and then save the whole entropy pool ++ * if [ -f $random_seed ]; then ++ * cat $random_seed >/dev/urandom ++ * else ++ * touch $random_seed ++ * fi ++ * chmod 600 $random_seed ++ * dd if=/dev/urandom of=$random_seed count=1 bs=512 ++ * ++ * and the following lines in an appropriate script which is run as ++ * the system is shutdown: ++ * ++ * # Carry a random seed from shut-down to start-up ++ * # Save the whole entropy pool ++ * echo "Saving random seed..." ++ * random_seed=/var/run/random-seed ++ * touch $random_seed ++ * chmod 600 $random_seed ++ * dd if=/dev/urandom of=$random_seed count=1 bs=512 ++ * ++ * For example, on most modern systems using the System V init ++ * scripts, such code fragments would be found in ++ * /etc/rc.d/init.d/random. On older Linux systems, the correct script ++ * location might be in /etc/rcb.d/rc.local or /etc/rc.d/rc.0. ++ * ++ * Effectively, these commands cause the contents of the entropy pool ++ * to be saved at shut-down time and reloaded into the entropy pool at ++ * start-up. (The 'dd' in the addition to the bootup script is to ++ * make sure that /etc/random-seed is different for every start-up, ++ * even if the system crashes without executing rc.0.) Even with ++ * complete knowledge of the start-up activities, predicting the state ++ * of the entropy pool requires knowledge of the previous history of ++ * the system. ++ * ++ * Configuring the /dev/random driver under Linux ++ * ============================================== ++ * ++ * The /dev/random driver under Linux uses minor numbers 8 and 9 of ++ * the /dev/mem major number (#1). So if your system does not have ++ * /dev/random and /dev/urandom created already, they can be created ++ * by using the commands: ++ * ++ * mknod /dev/random c 1 8 ++ * mknod /dev/urandom c 1 9 ++ * ++ * Acknowledgements: ++ * ================= ++ * ++ * Ideas for constructing this random number generator were derived ++ * from Pretty Good Privacy's random number generator, and from private ++ * discussions with Phil Karn. Colin Plumb provided a faster random ++ * number generator, which speed up the mixing function of the entropy ++ * pool, taken from PGPfone. Dale Worley has also contributed many ++ * useful ideas and suggestions to improve this driver. ++ * ++ * Any flaws in the design are solely my responsibility, and should ++ * not be attributed to the Phil, Colin, or any of authors of PGP. ++ * ++ * Further background information on this topic may be obtained from ++ * RFC 1750, "Randomness Recommendations for Security", by Donald ++ * Eastlake, Steve Crocker, and Jeff Schiller. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_GENERIC_HARDIRQS ++# include ++#endif ++ ++#include ++#include ++#include ++#include ++ ++/* ++ * Configuration information ++ */ ++#define INPUT_POOL_WORDS 128 ++#define OUTPUT_POOL_WORDS 32 ++#define SEC_XFER_SIZE 512 ++#define EXTRACT_SIZE 10 ++ ++/* ++ * The minimum number of bits of entropy before we wake up a read on ++ * /dev/random. Should be enough to do a significant reseed. ++ */ ++static int random_read_wakeup_thresh = 64; ++ ++/* ++ * If the entropy count falls under this number of bits, then we ++ * should wake up processes which are selecting or polling on write ++ * access to /dev/random. ++ */ ++static int random_write_wakeup_thresh = 128; ++ ++/* ++ * When the input pool goes over trickle_thresh, start dropping most ++ * samples to avoid wasting CPU time and reduce lock contention. ++ */ ++ ++static int trickle_thresh __read_mostly = INPUT_POOL_WORDS * 28; ++ ++static DEFINE_PER_CPU(int, trickle_count); ++ ++/* ++ * A pool of size .poolwords is stirred with a primitive polynomial ++ * of degree .poolwords over GF(2). The taps for various sizes are ++ * defined below. They are chosen to be evenly spaced (minimum RMS ++ * distance from evenly spaced; the numbers in the comments are a ++ * scaled squared error sum) except for the last tap, which is 1 to ++ * get the twisting happening as fast as possible. ++ */ ++static struct poolinfo { ++ int poolwords; ++ int tap1, tap2, tap3, tap4, tap5; ++} poolinfo_table[] = { ++ /* x^128 + x^103 + x^76 + x^51 +x^25 + x + 1 -- 105 */ ++ { 128, 103, 76, 51, 25, 1 }, ++ /* x^32 + x^26 + x^20 + x^14 + x^7 + x + 1 -- 15 */ ++ { 32, 26, 20, 14, 7, 1 }, ++#if 0 ++ /* x^2048 + x^1638 + x^1231 + x^819 + x^411 + x + 1 -- 115 */ ++ { 2048, 1638, 1231, 819, 411, 1 }, ++ ++ /* x^1024 + x^817 + x^615 + x^412 + x^204 + x + 1 -- 290 */ ++ { 1024, 817, 615, 412, 204, 1 }, ++ ++ /* x^1024 + x^819 + x^616 + x^410 + x^207 + x^2 + 1 -- 115 */ ++ { 1024, 819, 616, 410, 207, 2 }, ++ ++ /* x^512 + x^411 + x^308 + x^208 + x^104 + x + 1 -- 225 */ ++ { 512, 411, 308, 208, 104, 1 }, ++ ++ /* x^512 + x^409 + x^307 + x^206 + x^102 + x^2 + 1 -- 95 */ ++ { 512, 409, 307, 206, 102, 2 }, ++ /* x^512 + x^409 + x^309 + x^205 + x^103 + x^2 + 1 -- 95 */ ++ { 512, 409, 309, 205, 103, 2 }, ++ ++ /* x^256 + x^205 + x^155 + x^101 + x^52 + x + 1 -- 125 */ ++ { 256, 205, 155, 101, 52, 1 }, ++ ++ /* x^128 + x^103 + x^78 + x^51 + x^27 + x^2 + 1 -- 70 */ ++ { 128, 103, 78, 51, 27, 2 }, ++ ++ /* x^64 + x^52 + x^39 + x^26 + x^14 + x + 1 -- 15 */ ++ { 64, 52, 39, 26, 14, 1 }, ++#endif ++}; ++ ++#define POOLBITS poolwords*32 ++#define POOLBYTES poolwords*4 ++ ++/* ++ * For the purposes of better mixing, we use the CRC-32 polynomial as ++ * well to make a twisted Generalized Feedback Shift Reigster ++ * ++ * (See M. Matsumoto & Y. Kurita, 1992. Twisted GFSR generators. ACM ++ * Transactions on Modeling and Computer Simulation 2(3):179-194. ++ * Also see M. Matsumoto & Y. Kurita, 1994. Twisted GFSR generators ++ * II. ACM Transactions on Mdeling and Computer Simulation 4:254-266) ++ * ++ * Thanks to Colin Plumb for suggesting this. ++ * ++ * We have not analyzed the resultant polynomial to prove it primitive; ++ * in fact it almost certainly isn't. Nonetheless, the irreducible factors ++ * of a random large-degree polynomial over GF(2) are more than large enough ++ * that periodicity is not a concern. ++ * ++ * The input hash is much less sensitive than the output hash. All ++ * that we want of it is that it be a good non-cryptographic hash; ++ * i.e. it not produce collisions when fed "random" data of the sort ++ * we expect to see. As long as the pool state differs for different ++ * inputs, we have preserved the input entropy and done a good job. ++ * The fact that an intelligent attacker can construct inputs that ++ * will produce controlled alterations to the pool's state is not ++ * important because we don't consider such inputs to contribute any ++ * randomness. The only property we need with respect to them is that ++ * the attacker can't increase his/her knowledge of the pool's state. ++ * Since all additions are reversible (knowing the final state and the ++ * input, you can reconstruct the initial state), if an attacker has ++ * any uncertainty about the initial state, he/she can only shuffle ++ * that uncertainty about, but never cause any collisions (which would ++ * decrease the uncertainty). ++ * ++ * The chosen system lets the state of the pool be (essentially) the input ++ * modulo the generator polymnomial. Now, for random primitive polynomials, ++ * this is a universal class of hash functions, meaning that the chance ++ * of a collision is limited by the attacker's knowledge of the generator ++ * polynomail, so if it is chosen at random, an attacker can never force ++ * a collision. Here, we use a fixed polynomial, but we *can* assume that ++ * ###--> it is unknown to the processes generating the input entropy. <-### ++ * Because of this important property, this is a good, collision-resistant ++ * hash; hash collisions will occur no more often than chance. ++ */ ++ ++/* ++ * Static global variables ++ */ ++static DECLARE_WAIT_QUEUE_HEAD(random_read_wait); ++static DECLARE_WAIT_QUEUE_HEAD(random_write_wait); ++static struct fasync_struct *fasync; ++ ++#if 0 ++static int debug; ++module_param(debug, bool, 0644); ++#define DEBUG_ENT(fmt, arg...) do { \ ++ if (debug) \ ++ printk(KERN_DEBUG "random %04d %04d %04d: " \ ++ fmt,\ ++ input_pool.entropy_count,\ ++ blocking_pool.entropy_count,\ ++ nonblocking_pool.entropy_count,\ ++ ## arg); } while (0) ++#else ++#define DEBUG_ENT(fmt, arg...) do {} while (0) ++#endif ++ ++/********************************************************************** ++ * ++ * OS independent entropy store. Here are the functions which handle ++ * storing entropy in an entropy pool. ++ * ++ **********************************************************************/ ++ ++struct entropy_store; ++struct entropy_store { ++ /* read-only data: */ ++ struct poolinfo *poolinfo; ++ __u32 *pool; ++ const char *name; ++ struct entropy_store *pull; ++ int limit; ++ ++ /* read-write data: */ ++ spinlock_t lock; ++ unsigned add_ptr; ++ int entropy_count; ++ int input_rotate; ++ __u8 last_data[EXTRACT_SIZE]; ++}; ++ ++static __u32 input_pool_data[INPUT_POOL_WORDS]; ++static __u32 blocking_pool_data[OUTPUT_POOL_WORDS]; ++static __u32 nonblocking_pool_data[OUTPUT_POOL_WORDS]; ++ ++static struct entropy_store input_pool = { ++ .poolinfo = &poolinfo_table[0], ++ .name = "input", ++ .limit = 1, ++ .lock = __SPIN_LOCK_UNLOCKED(&input_pool.lock), ++ .pool = input_pool_data ++}; ++ ++static struct entropy_store blocking_pool = { ++ .poolinfo = &poolinfo_table[1], ++ .name = "blocking", ++ .limit = 1, ++ .pull = &input_pool, ++ .lock = __SPIN_LOCK_UNLOCKED(&blocking_pool.lock), ++ .pool = blocking_pool_data ++}; ++ ++static struct entropy_store nonblocking_pool = { ++ .poolinfo = &poolinfo_table[1], ++ .name = "nonblocking", ++ .pull = &input_pool, ++ .lock = __SPIN_LOCK_UNLOCKED(&nonblocking_pool.lock), ++ .pool = nonblocking_pool_data ++}; ++ ++/* ++ * This function adds bytes into the entropy "pool". It does not ++ * update the entropy estimate. The caller should call ++ * credit_entropy_bits if this is appropriate. ++ * ++ * The pool is stirred with a primitive polynomial of the appropriate ++ * degree, and then twisted. We twist by three bits at a time because ++ * it's cheap to do so and helps slightly in the expected case where ++ * the entropy is concentrated in the low-order bits. ++ */ ++static void mix_pool_bytes_extract(struct entropy_store *r, const void *in, ++ int nbytes, __u8 out[64]) ++{ ++ static __u32 const twist_table[8] = { ++ 0x00000000, 0x3b6e20c8, 0x76dc4190, 0x4db26158, ++ 0xedb88320, 0xd6d6a3e8, 0x9b64c2b0, 0xa00ae278 }; ++ unsigned long i, j, tap1, tap2, tap3, tap4, tap5; ++ int input_rotate; ++ int wordmask = r->poolinfo->poolwords - 1; ++ const char *bytes = in; ++ __u32 w; ++ unsigned long flags; ++ ++ /* Taps are constant, so we can load them without holding r->lock. */ ++ tap1 = r->poolinfo->tap1; ++ tap2 = r->poolinfo->tap2; ++ tap3 = r->poolinfo->tap3; ++ tap4 = r->poolinfo->tap4; ++ tap5 = r->poolinfo->tap5; ++ ++ spin_lock_irqsave(&r->lock, flags); ++ input_rotate = r->input_rotate; ++ i = r->add_ptr; ++ ++ /* mix one byte at a time to simplify size handling and churn faster */ ++ while (nbytes--) { ++ w = rol32(*bytes++, input_rotate & 31); ++ i = (i - 1) & wordmask; ++ ++ /* XOR in the various taps */ ++ w ^= r->pool[i]; ++ w ^= r->pool[(i + tap1) & wordmask]; ++ w ^= r->pool[(i + tap2) & wordmask]; ++ w ^= r->pool[(i + tap3) & wordmask]; ++ w ^= r->pool[(i + tap4) & wordmask]; ++ w ^= r->pool[(i + tap5) & wordmask]; ++ ++ /* Mix the result back in with a twist */ ++ r->pool[i] = (w >> 3) ^ twist_table[w & 7]; ++ ++ /* ++ * Normally, we add 7 bits of rotation to the pool. ++ * At the beginning of the pool, add an extra 7 bits ++ * rotation, so that successive passes spread the ++ * input bits across the pool evenly. ++ */ ++ input_rotate += i ? 7 : 14; ++ } ++ ++ r->input_rotate = input_rotate; ++ r->add_ptr = i; ++ ++ if (out) ++ for (j = 0; j < 16; j++) ++ ((__u32 *)out)[j] = r->pool[(i - j) & wordmask]; ++ ++ spin_unlock_irqrestore(&r->lock, flags); ++} ++ ++static void mix_pool_bytes(struct entropy_store *r, const void *in, int bytes) ++{ ++ mix_pool_bytes_extract(r, in, bytes, NULL); ++} ++ ++/* ++ * Credit (or debit) the entropy store with n bits of entropy ++ */ ++static void credit_entropy_bits(struct entropy_store *r, int nbits) ++{ ++ unsigned long flags; ++ int entropy_count; ++ ++ if (!nbits) ++ return; ++ ++ spin_lock_irqsave(&r->lock, flags); ++ ++ DEBUG_ENT("added %d entropy credits to %s\n", nbits, r->name); ++ entropy_count = r->entropy_count; ++ entropy_count += nbits; ++ if (entropy_count < 0) { ++ DEBUG_ENT("negative entropy/overflow\n"); ++ entropy_count = 0; ++ } else if (entropy_count > r->poolinfo->POOLBITS) ++ entropy_count = r->poolinfo->POOLBITS; ++ r->entropy_count = entropy_count; ++ ++ /* should we wake readers? */ ++ if (r == &input_pool && entropy_count >= random_read_wakeup_thresh) { ++ wake_up_interruptible(&random_read_wait); ++ kill_fasync(&fasync, SIGIO, POLL_IN); ++ } ++ spin_unlock_irqrestore(&r->lock, flags); ++} ++ ++/********************************************************************* ++ * ++ * Entropy input management ++ * ++ *********************************************************************/ ++ ++/* There is one of these per entropy source */ ++struct timer_rand_state { ++ cycles_t last_time; ++ long last_delta, last_delta2; ++ unsigned dont_count_entropy:1; ++}; ++ ++#ifndef CONFIG_GENERIC_HARDIRQS ++ ++static struct timer_rand_state *irq_timer_state[NR_IRQS]; ++ ++static struct timer_rand_state *get_timer_rand_state(unsigned int irq) ++{ ++ return irq_timer_state[irq]; ++} ++ ++static void set_timer_rand_state(unsigned int irq, ++ struct timer_rand_state *state) ++{ ++ irq_timer_state[irq] = state; ++} ++ ++#else ++ ++static struct timer_rand_state *get_timer_rand_state(unsigned int irq) ++{ ++ struct irq_desc *desc; ++ ++ desc = irq_to_desc(irq); ++ ++ return desc->timer_rand_state; ++} ++ ++static void set_timer_rand_state(unsigned int irq, ++ struct timer_rand_state *state) ++{ ++ struct irq_desc *desc; ++ ++ desc = irq_to_desc(irq); ++ ++ desc->timer_rand_state = state; ++} ++#endif ++ ++static struct timer_rand_state input_timer_state; ++ ++/* ++ * This function adds entropy to the entropy "pool" by using timing ++ * delays. It uses the timer_rand_state structure to make an estimate ++ * of how many bits of entropy this call has added to the pool. ++ * ++ * The number "num" is also added to the pool - it should somehow describe ++ * the type of event which just happened. This is currently 0-255 for ++ * keyboard scan codes, and 256 upwards for interrupts. ++ * ++ */ ++static void add_timer_randomness(struct timer_rand_state *state, unsigned num) ++{ ++ struct { ++ cycles_t cycles; ++ long jiffies; ++ unsigned num; ++ } sample; ++ long delta, delta2, delta3; ++ ++ preempt_disable(); ++ /* if over the trickle threshold, use only 1 in 4096 samples */ ++ if (input_pool.entropy_count > trickle_thresh && ++ ((__this_cpu_inc_return(trickle_count) - 1) & 0xfff)) ++ goto out; ++ ++ sample.jiffies = jiffies; ++ sample.cycles = get_cycles(); ++ sample.num = num; ++ mix_pool_bytes(&input_pool, &sample, sizeof(sample)); ++ ++ /* ++ * Calculate number of bits of randomness we probably added. ++ * We take into account the first, second and third-order deltas ++ * in order to make our estimate. ++ */ ++ ++ if (!state->dont_count_entropy) { ++ delta = sample.jiffies - state->last_time; ++ state->last_time = sample.jiffies; ++ ++ delta2 = delta - state->last_delta; ++ state->last_delta = delta; ++ ++ delta3 = delta2 - state->last_delta2; ++ state->last_delta2 = delta2; ++ ++ if (delta < 0) ++ delta = -delta; ++ if (delta2 < 0) ++ delta2 = -delta2; ++ if (delta3 < 0) ++ delta3 = -delta3; ++ if (delta > delta2) ++ delta = delta2; ++ if (delta > delta3) ++ delta = delta3; ++ ++ /* ++ * delta is now minimum absolute delta. ++ * Round down by 1 bit on general principles, ++ * and limit entropy entimate to 12 bits. ++ */ ++ credit_entropy_bits(&input_pool, ++ min_t(int, fls(delta>>1), 11)); ++ } ++out: ++ preempt_enable(); ++} ++ ++void add_input_randomness(unsigned int type, unsigned int code, ++ unsigned int value) ++{ ++ static unsigned char last_value; ++ ++ /* ignore autorepeat and the like */ ++ if (value == last_value) ++ return; ++ ++ DEBUG_ENT("input event\n"); ++ last_value = value; ++ add_timer_randomness(&input_timer_state, ++ (type << 4) ^ code ^ (code >> 4) ^ value); ++} ++EXPORT_SYMBOL_GPL(add_input_randomness); ++ ++void add_interrupt_randomness(int irq) ++{ ++ struct timer_rand_state *state; ++ ++ state = get_timer_rand_state(irq); ++ ++ if (state == NULL) ++ return; ++ ++ DEBUG_ENT("irq event %d\n", irq); ++ add_timer_randomness(state, 0x100 + irq); ++} ++ ++#ifdef CONFIG_BLOCK ++void add_disk_randomness(struct gendisk *disk) ++{ ++ if (!disk || !disk->random) ++ return; ++ /* first major is 1, so we get >= 0x200 here */ ++ DEBUG_ENT("disk event %d:%d\n", ++ MAJOR(disk_devt(disk)), MINOR(disk_devt(disk))); ++ ++ add_timer_randomness(disk->random, 0x100 + disk_devt(disk)); ++} ++#endif ++ ++/********************************************************************* ++ * ++ * Entropy extraction routines ++ * ++ *********************************************************************/ ++ ++static ssize_t extract_entropy(struct entropy_store *r, void *buf, ++ size_t nbytes, int min, int rsvd); ++ ++/* ++ * This utility inline function is responsible for transferring entropy ++ * from the primary pool to the secondary extraction pool. We make ++ * sure we pull enough for a 'catastrophic reseed'. ++ */ ++static void xfer_secondary_pool(struct entropy_store *r, size_t nbytes) ++{ ++ __u32 tmp[OUTPUT_POOL_WORDS]; ++ ++ if (r->pull && r->entropy_count < nbytes * 8 && ++ r->entropy_count < r->poolinfo->POOLBITS) { ++ /* If we're limited, always leave two wakeup worth's BITS */ ++ int rsvd = r->limit ? 0 : random_read_wakeup_thresh/4; ++ int bytes = nbytes; ++ ++ /* pull at least as many as BYTES as wakeup BITS */ ++ bytes = max_t(int, bytes, random_read_wakeup_thresh / 8); ++ /* but never more than the buffer size */ ++ bytes = min_t(int, bytes, sizeof(tmp)); ++ ++ DEBUG_ENT("going to reseed %s with %d bits " ++ "(%d of %d requested)\n", ++ r->name, bytes * 8, nbytes * 8, r->entropy_count); ++ ++ bytes = extract_entropy(r->pull, tmp, bytes, ++ random_read_wakeup_thresh / 8, rsvd); ++ mix_pool_bytes(r, tmp, bytes); ++ credit_entropy_bits(r, bytes*8); ++ } ++} ++ ++/* ++ * These functions extracts randomness from the "entropy pool", and ++ * returns it in a buffer. ++ * ++ * The min parameter specifies the minimum amount we can pull before ++ * failing to avoid races that defeat catastrophic reseeding while the ++ * reserved parameter indicates how much entropy we must leave in the ++ * pool after each pull to avoid starving other readers. ++ * ++ * Note: extract_entropy() assumes that .poolwords is a multiple of 16 words. ++ */ ++ ++static size_t account(struct entropy_store *r, size_t nbytes, int min, ++ int reserved) ++{ ++ unsigned long flags; ++ ++ /* Hold lock while accounting */ ++ spin_lock_irqsave(&r->lock, flags); ++ ++ BUG_ON(r->entropy_count > r->poolinfo->POOLBITS); ++ DEBUG_ENT("trying to extract %d bits from %s\n", ++ nbytes * 8, r->name); ++ ++ /* Can we pull enough? */ ++ if (r->entropy_count / 8 < min + reserved) { ++ nbytes = 0; ++ } else { ++ /* If limited, never pull more than available */ ++ if (r->limit && nbytes + reserved >= r->entropy_count / 8) ++ nbytes = r->entropy_count/8 - reserved; ++ ++ if (r->entropy_count / 8 >= nbytes + reserved) ++ r->entropy_count -= nbytes*8; ++ else ++ r->entropy_count = reserved; ++ ++ if (r->entropy_count < random_write_wakeup_thresh) { ++ wake_up_interruptible(&random_write_wait); ++ kill_fasync(&fasync, SIGIO, POLL_OUT); ++ } ++ } ++ ++ DEBUG_ENT("debiting %d entropy credits from %s%s\n", ++ nbytes * 8, r->name, r->limit ? "" : " (unlimited)"); ++ ++ spin_unlock_irqrestore(&r->lock, flags); ++ ++ return nbytes; ++} ++ ++static void extract_buf(struct entropy_store *r, __u8 *out) ++{ ++ int i; ++ __u32 hash[5], workspace[SHA_WORKSPACE_WORDS]; ++ __u8 extract[64]; ++ ++ /* Generate a hash across the pool, 16 words (512 bits) at a time */ ++ sha_init(hash); ++ for (i = 0; i < r->poolinfo->poolwords; i += 16) ++ sha_transform(hash, (__u8 *)(r->pool + i), workspace); ++ ++ /* ++ * We mix the hash back into the pool to prevent backtracking ++ * attacks (where the attacker knows the state of the pool ++ * plus the current outputs, and attempts to find previous ++ * ouputs), unless the hash function can be inverted. By ++ * mixing at least a SHA1 worth of hash data back, we make ++ * brute-forcing the feedback as hard as brute-forcing the ++ * hash. ++ */ ++ mix_pool_bytes_extract(r, hash, sizeof(hash), extract); ++ ++ /* ++ * To avoid duplicates, we atomically extract a portion of the ++ * pool while mixing, and hash one final time. ++ */ ++ sha_transform(hash, extract, workspace); ++ memset(extract, 0, sizeof(extract)); ++ memset(workspace, 0, sizeof(workspace)); ++ ++ /* ++ * In case the hash function has some recognizable output ++ * pattern, we fold it in half. Thus, we always feed back ++ * twice as much data as we output. ++ */ ++ hash[0] ^= hash[3]; ++ hash[1] ^= hash[4]; ++ hash[2] ^= rol32(hash[2], 16); ++ memcpy(out, hash, EXTRACT_SIZE); ++ memset(hash, 0, sizeof(hash)); ++} ++ ++static ssize_t extract_entropy(struct entropy_store *r, void *buf, ++ size_t nbytes, int min, int reserved) ++{ ++ ssize_t ret = 0, i; ++ __u8 tmp[EXTRACT_SIZE]; ++ unsigned long flags; ++ ++ xfer_secondary_pool(r, nbytes); ++ nbytes = account(r, nbytes, min, reserved); ++ ++ while (nbytes) { ++ extract_buf(r, tmp); ++ ++ if (fips_enabled) { ++ spin_lock_irqsave(&r->lock, flags); ++ if (!memcmp(tmp, r->last_data, EXTRACT_SIZE)) ++ panic("Hardware RNG duplicated output!\n"); ++ memcpy(r->last_data, tmp, EXTRACT_SIZE); ++ spin_unlock_irqrestore(&r->lock, flags); ++ } ++ i = min_t(int, nbytes, EXTRACT_SIZE); ++ memcpy(buf, tmp, i); ++ nbytes -= i; ++ buf += i; ++ ret += i; ++ } ++ ++ /* Wipe data just returned from memory */ ++ memset(tmp, 0, sizeof(tmp)); ++ ++ return ret; ++} ++ ++static ssize_t extract_entropy_user(struct entropy_store *r, void __user *buf, ++ size_t nbytes) ++{ ++ ssize_t ret = 0, i; ++ __u8 tmp[EXTRACT_SIZE]; ++ ++ xfer_secondary_pool(r, nbytes); ++ nbytes = account(r, nbytes, 0, 0); ++ ++ while (nbytes) { ++ if (need_resched()) { ++ if (signal_pending(current)) { ++ if (ret == 0) ++ ret = -ERESTARTSYS; ++ break; ++ } ++ schedule(); ++ } ++ ++ extract_buf(r, tmp); ++ i = min_t(int, nbytes, EXTRACT_SIZE); ++ if (copy_to_user(buf, tmp, i)) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ nbytes -= i; ++ buf += i; ++ ret += i; ++ } ++ ++ /* Wipe data just returned from memory */ ++ memset(tmp, 0, sizeof(tmp)); ++ ++ return ret; ++} ++ ++/* ++ * This function is the exported kernel interface. It returns some ++ * number of good random numbers, suitable for seeding TCP sequence ++ * numbers, etc. ++ */ ++void get_random_bytes(void *buf, int nbytes) ++{ ++ extract_entropy(&nonblocking_pool, buf, nbytes, 0, 0); ++} ++EXPORT_SYMBOL(get_random_bytes); ++ ++/* ++ * init_std_data - initialize pool with system data ++ * ++ * @r: pool to initialize ++ * ++ * This function clears the pool's entropy count and mixes some system ++ * data into the pool to prepare it for use. The pool is not cleared ++ * as that can only decrease the entropy in the pool. ++ */ ++static void init_std_data(struct entropy_store *r) ++{ ++ ktime_t now; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&r->lock, flags); ++ r->entropy_count = 0; ++ spin_unlock_irqrestore(&r->lock, flags); ++ ++ now = ktime_get_real(); ++ mix_pool_bytes(r, &now, sizeof(now)); ++ mix_pool_bytes(r, utsname(), sizeof(*(utsname()))); ++} ++ ++static int rand_initialize(void) ++{ ++ init_std_data(&input_pool); ++ init_std_data(&blocking_pool); ++ init_std_data(&nonblocking_pool); ++ return 0; ++} ++module_init(rand_initialize); ++ ++void rand_initialize_irq(int irq) ++{ ++ struct timer_rand_state *state; ++ ++ state = get_timer_rand_state(irq); ++ ++ if (state) ++ return; ++ ++ /* ++ * If kzalloc returns null, we just won't use that entropy ++ * source. ++ */ ++ state = kzalloc(sizeof(struct timer_rand_state), GFP_KERNEL); ++ if (state) ++ set_timer_rand_state(irq, state); ++} ++ ++#ifdef CONFIG_BLOCK ++void rand_initialize_disk(struct gendisk *disk) ++{ ++ struct timer_rand_state *state; ++ ++ /* ++ * If kzalloc returns null, we just won't use that entropy ++ * source. ++ */ ++ state = kzalloc(sizeof(struct timer_rand_state), GFP_KERNEL); ++ if (state) ++ disk->random = state; ++} ++#endif ++ ++static ssize_t ++random_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) ++{ ++ ssize_t n, retval = 0, count = 0; ++ ++ if (nbytes == 0) ++ return 0; ++ ++ while (nbytes > 0) { ++ n = nbytes; ++ if (n > SEC_XFER_SIZE) ++ n = SEC_XFER_SIZE; ++ ++ DEBUG_ENT("reading %d bits\n", n*8); ++ ++ n = extract_entropy_user(&blocking_pool, buf, n); ++ ++ DEBUG_ENT("read got %d bits (%d still needed)\n", ++ n*8, (nbytes-n)*8); ++ ++ if (n == 0) { ++ if (file->f_flags & O_NONBLOCK) { ++ retval = -EAGAIN; ++ break; ++ } ++ ++ DEBUG_ENT("sleeping?\n"); ++ ++ wait_event_interruptible(random_read_wait, ++ input_pool.entropy_count >= ++ random_read_wakeup_thresh); ++ ++ DEBUG_ENT("awake\n"); ++ ++ if (signal_pending(current)) { ++ retval = -ERESTARTSYS; ++ break; ++ } ++ ++ continue; ++ } ++ ++ if (n < 0) { ++ retval = n; ++ break; ++ } ++ count += n; ++ buf += n; ++ nbytes -= n; ++ break; /* This break makes the device work */ ++ /* like a named pipe */ ++ } ++ ++ return (count ? count : retval); ++} ++ ++static ssize_t ++urandom_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) ++{ ++ return extract_entropy_user(&nonblocking_pool, buf, nbytes); ++} ++ ++static unsigned int ++random_poll(struct file *file, poll_table * wait) ++{ ++ unsigned int mask; ++ ++ poll_wait(file, &random_read_wait, wait); ++ poll_wait(file, &random_write_wait, wait); ++ mask = 0; ++ if (input_pool.entropy_count >= random_read_wakeup_thresh) ++ mask |= POLLIN | POLLRDNORM; ++ if (input_pool.entropy_count < random_write_wakeup_thresh) ++ mask |= POLLOUT | POLLWRNORM; ++ return mask; ++} ++ ++static int ++write_pool(struct entropy_store *r, const char __user *buffer, size_t count) ++{ ++ size_t bytes; ++ __u32 buf[16]; ++ const char __user *p = buffer; ++ ++ while (count > 0) { ++ bytes = min(count, sizeof(buf)); ++ if (copy_from_user(&buf, p, bytes)) ++ return -EFAULT; ++ ++ count -= bytes; ++ p += bytes; ++ ++ mix_pool_bytes(r, buf, bytes); ++ cond_resched(); ++ } ++ ++ return 0; ++} ++ ++static ssize_t random_write(struct file *file, const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ size_t ret; ++ ++ ret = write_pool(&blocking_pool, buffer, count); ++ if (ret) ++ return ret; ++ ret = write_pool(&nonblocking_pool, buffer, count); ++ if (ret) ++ return ret; ++ ++ return (ssize_t)count; ++} ++ ++static long random_ioctl(struct file *f, unsigned int cmd, unsigned long arg) ++{ ++ int size, ent_count; ++ int __user *p = (int __user *)arg; ++ int retval; ++ ++ switch (cmd) { ++ case RNDGETENTCNT: ++ /* inherently racy, no point locking */ ++ if (put_user(input_pool.entropy_count, p)) ++ return -EFAULT; ++ return 0; ++ case RNDADDTOENTCNT: ++ if (!capable(CAP_SYS_ADMIN)) ++ return -EPERM; ++ if (get_user(ent_count, p)) ++ return -EFAULT; ++ credit_entropy_bits(&input_pool, ent_count); ++ return 0; ++ case RNDADDENTROPY: ++ if (!capable(CAP_SYS_ADMIN)) ++ return -EPERM; ++ if (get_user(ent_count, p++)) ++ return -EFAULT; ++ if (ent_count < 0) ++ return -EINVAL; ++ if (get_user(size, p++)) ++ return -EFAULT; ++ retval = write_pool(&input_pool, (const char __user *)p, ++ size); ++ if (retval < 0) ++ return retval; ++ credit_entropy_bits(&input_pool, ent_count); ++ return 0; ++ case RNDZAPENTCNT: ++ case RNDCLEARPOOL: ++ /* Clear the entropy pool counters. */ ++ if (!capable(CAP_SYS_ADMIN)) ++ return -EPERM; ++ rand_initialize(); ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static int random_fasync(int fd, struct file *filp, int on) ++{ ++ return fasync_helper(fd, filp, on, &fasync); ++} ++ ++const struct file_operations random_fops = { ++ .read = random_read, ++ .write = random_write, ++ .poll = random_poll, ++ .unlocked_ioctl = random_ioctl, ++ .fasync = random_fasync, ++ .llseek = noop_llseek, ++}; ++ ++const struct file_operations urandom_fops = { ++ .read = urandom_read, ++ .write = random_write, ++ .unlocked_ioctl = random_ioctl, ++ .fasync = random_fasync, ++ .llseek = noop_llseek, ++}; ++ ++/*************************************************************** ++ * Random UUID interface ++ * ++ * Used here for a Boot ID, but can be useful for other kernel ++ * drivers. ++ ***************************************************************/ ++ ++/* ++ * Generate random UUID ++ */ ++void generate_random_uuid(unsigned char uuid_out[16]) ++{ ++ get_random_bytes(uuid_out, 16); ++ /* Set UUID version to 4 --- truly random generation */ ++ uuid_out[6] = (uuid_out[6] & 0x0F) | 0x40; ++ /* Set the UUID variant to DCE */ ++ uuid_out[8] = (uuid_out[8] & 0x3F) | 0x80; ++} ++EXPORT_SYMBOL(generate_random_uuid); ++ ++/******************************************************************** ++ * ++ * Sysctl interface ++ * ++ ********************************************************************/ ++ ++#ifdef CONFIG_SYSCTL ++ ++#include ++ ++static int min_read_thresh = 8, min_write_thresh; ++static int max_read_thresh = INPUT_POOL_WORDS * 32; ++static int max_write_thresh = INPUT_POOL_WORDS * 32; ++static char sysctl_bootid[16]; ++ ++/* ++ * These functions is used to return both the bootid UUID, and random ++ * UUID. The difference is in whether table->data is NULL; if it is, ++ * then a new UUID is generated and returned to the user. ++ * ++ * If the user accesses this via the proc interface, it will be returned ++ * as an ASCII string in the standard UUID format. If accesses via the ++ * sysctl system call, it is returned as 16 bytes of binary data. ++ */ ++static int proc_do_uuid(ctl_table *table, int write, ++ void __user *buffer, size_t *lenp, loff_t *ppos) ++{ ++ ctl_table fake_table; ++ unsigned char buf[64], tmp_uuid[16], *uuid; ++ ++ uuid = table->data; ++ if (!uuid) { ++ uuid = tmp_uuid; ++ uuid[8] = 0; ++ } ++ if (uuid[8] == 0) ++ generate_random_uuid(uuid); ++ ++ sprintf(buf, "%pU", uuid); ++ ++ fake_table.data = buf; ++ fake_table.maxlen = sizeof(buf); ++ ++ return proc_dostring(&fake_table, write, buffer, lenp, ppos); ++} ++ ++static int sysctl_poolsize = INPUT_POOL_WORDS * 32; ++ctl_table random_table[] = { ++ { ++ .procname = "poolsize", ++ .data = &sysctl_poolsize, ++ .maxlen = sizeof(int), ++ .mode = 0444, ++ .proc_handler = proc_dointvec, ++ }, ++ { ++ .procname = "entropy_avail", ++ .maxlen = sizeof(int), ++ .mode = 0444, ++ .proc_handler = proc_dointvec, ++ .data = &input_pool.entropy_count, ++ }, ++ { ++ .procname = "read_wakeup_threshold", ++ .data = &random_read_wakeup_thresh, ++ .maxlen = sizeof(int), ++ .mode = 0644, ++ .proc_handler = proc_dointvec_minmax, ++ .extra1 = &min_read_thresh, ++ .extra2 = &max_read_thresh, ++ }, ++ { ++ .procname = "write_wakeup_threshold", ++ .data = &random_write_wakeup_thresh, ++ .maxlen = sizeof(int), ++ .mode = 0644, ++ .proc_handler = proc_dointvec_minmax, ++ .extra1 = &min_write_thresh, ++ .extra2 = &max_write_thresh, ++ }, ++ { ++ .procname = "boot_id", ++ .data = &sysctl_bootid, ++ .maxlen = 16, ++ .mode = 0444, ++ .proc_handler = proc_do_uuid, ++ }, ++ { ++ .procname = "uuid", ++ .maxlen = 16, ++ .mode = 0444, ++ .proc_handler = proc_do_uuid, ++ }, ++ { } ++}; ++#endif /* CONFIG_SYSCTL */ ++ ++/******************************************************************** ++ * ++ * Random functions for networking ++ * ++ ********************************************************************/ ++ ++/* ++ * TCP initial sequence number picking. This uses the random number ++ * generator to pick an initial secret value. This value is hashed ++ * along with the TCP endpoint information to provide a unique ++ * starting point for each pair of TCP endpoints. This defeats ++ * attacks which rely on guessing the initial TCP sequence number. ++ * This algorithm was suggested by Steve Bellovin. ++ * ++ * Using a very strong hash was taking an appreciable amount of the total ++ * TCP connection establishment time, so this is a weaker hash, ++ * compensated for by changing the secret periodically. ++ */ ++ ++/* F, G and H are basic MD4 functions: selection, majority, parity */ ++#define F(x, y, z) ((z) ^ ((x) & ((y) ^ (z)))) ++#define G(x, y, z) (((x) & (y)) + (((x) ^ (y)) & (z))) ++#define H(x, y, z) ((x) ^ (y) ^ (z)) ++ ++/* ++ * The generic round function. The application is so specific that ++ * we don't bother protecting all the arguments with parens, as is generally ++ * good macro practice, in favor of extra legibility. ++ * Rotation is separate from addition to prevent recomputation ++ */ ++#define ROUND(f, a, b, c, d, x, s) \ ++ (a += f(b, c, d) + x, a = (a << s) | (a >> (32 - s))) ++#define K1 0 ++#define K2 013240474631UL ++#define K3 015666365641UL ++ ++#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) ++ ++static __u32 twothirdsMD4Transform(__u32 const buf[4], __u32 const in[12]) ++{ ++ __u32 a = buf[0], b = buf[1], c = buf[2], d = buf[3]; ++ ++ /* Round 1 */ ++ ROUND(F, a, b, c, d, in[ 0] + K1, 3); ++ ROUND(F, d, a, b, c, in[ 1] + K1, 7); ++ ROUND(F, c, d, a, b, in[ 2] + K1, 11); ++ ROUND(F, b, c, d, a, in[ 3] + K1, 19); ++ ROUND(F, a, b, c, d, in[ 4] + K1, 3); ++ ROUND(F, d, a, b, c, in[ 5] + K1, 7); ++ ROUND(F, c, d, a, b, in[ 6] + K1, 11); ++ ROUND(F, b, c, d, a, in[ 7] + K1, 19); ++ ROUND(F, a, b, c, d, in[ 8] + K1, 3); ++ ROUND(F, d, a, b, c, in[ 9] + K1, 7); ++ ROUND(F, c, d, a, b, in[10] + K1, 11); ++ ROUND(F, b, c, d, a, in[11] + K1, 19); ++ ++ /* Round 2 */ ++ ROUND(G, a, b, c, d, in[ 1] + K2, 3); ++ ROUND(G, d, a, b, c, in[ 3] + K2, 5); ++ ROUND(G, c, d, a, b, in[ 5] + K2, 9); ++ ROUND(G, b, c, d, a, in[ 7] + K2, 13); ++ ROUND(G, a, b, c, d, in[ 9] + K2, 3); ++ ROUND(G, d, a, b, c, in[11] + K2, 5); ++ ROUND(G, c, d, a, b, in[ 0] + K2, 9); ++ ROUND(G, b, c, d, a, in[ 2] + K2, 13); ++ ROUND(G, a, b, c, d, in[ 4] + K2, 3); ++ ROUND(G, d, a, b, c, in[ 6] + K2, 5); ++ ROUND(G, c, d, a, b, in[ 8] + K2, 9); ++ ROUND(G, b, c, d, a, in[10] + K2, 13); ++ ++ /* Round 3 */ ++ ROUND(H, a, b, c, d, in[ 3] + K3, 3); ++ ROUND(H, d, a, b, c, in[ 7] + K3, 9); ++ ROUND(H, c, d, a, b, in[11] + K3, 11); ++ ROUND(H, b, c, d, a, in[ 2] + K3, 15); ++ ROUND(H, a, b, c, d, in[ 6] + K3, 3); ++ ROUND(H, d, a, b, c, in[10] + K3, 9); ++ ROUND(H, c, d, a, b, in[ 1] + K3, 11); ++ ROUND(H, b, c, d, a, in[ 5] + K3, 15); ++ ROUND(H, a, b, c, d, in[ 9] + K3, 3); ++ ROUND(H, d, a, b, c, in[ 0] + K3, 9); ++ ROUND(H, c, d, a, b, in[ 4] + K3, 11); ++ ROUND(H, b, c, d, a, in[ 8] + K3, 15); ++ ++ return buf[1] + b; /* "most hashed" word */ ++ /* Alternative: return sum of all words? */ ++} ++#endif ++ ++#undef ROUND ++#undef F ++#undef G ++#undef H ++#undef K1 ++#undef K2 ++#undef K3 ++ ++/* This should not be decreased so low that ISNs wrap too fast. */ ++#define REKEY_INTERVAL (300 * HZ) ++/* ++ * Bit layout of the tcp sequence numbers (before adding current time): ++ * bit 24-31: increased after every key exchange ++ * bit 0-23: hash(source,dest) ++ * ++ * The implementation is similar to the algorithm described ++ * in the Appendix of RFC 1185, except that ++ * - it uses a 1 MHz clock instead of a 250 kHz clock ++ * - it performs a rekey every 5 minutes, which is equivalent ++ * to a (source,dest) tulple dependent forward jump of the ++ * clock by 0..2^(HASH_BITS+1) ++ * ++ * Thus the average ISN wraparound time is 68 minutes instead of ++ * 4.55 hours. ++ * ++ * SMP cleanup and lock avoidance with poor man's RCU. ++ * Manfred Spraul ++ * ++ */ ++#define COUNT_BITS 8 ++#define COUNT_MASK ((1 << COUNT_BITS) - 1) ++#define HASH_BITS 24 ++#define HASH_MASK ((1 << HASH_BITS) - 1) ++ ++static struct keydata { ++ __u32 count; /* already shifted to the final position */ ++ __u32 secret[12]; ++} ____cacheline_aligned ip_keydata[2]; ++ ++static unsigned int ip_cnt; ++ ++static void rekey_seq_generator(struct work_struct *work); ++ ++static DECLARE_DELAYED_WORK(rekey_work, rekey_seq_generator); ++ ++/* ++ * Lock avoidance: ++ * The ISN generation runs lockless - it's just a hash over random data. ++ * State changes happen every 5 minutes when the random key is replaced. ++ * Synchronization is performed by having two copies of the hash function ++ * state and rekey_seq_generator always updates the inactive copy. ++ * The copy is then activated by updating ip_cnt. ++ * The implementation breaks down if someone blocks the thread ++ * that processes SYN requests for more than 5 minutes. Should never ++ * happen, and even if that happens only a not perfectly compliant ++ * ISN is generated, nothing fatal. ++ */ ++static void rekey_seq_generator(struct work_struct *work) ++{ ++ struct keydata *keyptr = &ip_keydata[1 ^ (ip_cnt & 1)]; ++ ++ get_random_bytes(keyptr->secret, sizeof(keyptr->secret)); ++ keyptr->count = (ip_cnt & COUNT_MASK) << HASH_BITS; ++ smp_wmb(); ++ ip_cnt++; ++ schedule_delayed_work(&rekey_work, ++ round_jiffies_relative(REKEY_INTERVAL)); ++} ++ ++static inline struct keydata *get_keyptr(void) ++{ ++ struct keydata *keyptr = &ip_keydata[ip_cnt & 1]; ++ ++ smp_rmb(); ++ ++ return keyptr; ++} ++ ++static __init int seqgen_init(void) ++{ ++ rekey_seq_generator(NULL); ++ return 0; ++} ++late_initcall(seqgen_init); ++ ++#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) ++__u32 secure_tcpv6_sequence_number(__be32 *saddr, __be32 *daddr, ++ __be16 sport, __be16 dport) ++{ ++ __u32 seq; ++ __u32 hash[12]; ++ struct keydata *keyptr = get_keyptr(); ++ ++ /* The procedure is the same as for IPv4, but addresses are longer. ++ * Thus we must use twothirdsMD4Transform. ++ */ ++ ++ memcpy(hash, saddr, 16); ++ hash[4] = ((__force u16)sport << 16) + (__force u16)dport; ++ memcpy(&hash[5], keyptr->secret, sizeof(__u32) * 7); ++ ++ seq = twothirdsMD4Transform((const __u32 *)daddr, hash) & HASH_MASK; ++ seq += keyptr->count; ++ ++ seq += ktime_to_ns(ktime_get_real()); ++ ++ return seq; ++} ++EXPORT_SYMBOL(secure_tcpv6_sequence_number); ++#endif ++ ++/* The code below is shamelessly stolen from secure_tcp_sequence_number(). ++ * All blames to Andrey V. Savochkin . ++ */ ++__u32 secure_ip_id(__be32 daddr) ++{ ++ struct keydata *keyptr; ++ __u32 hash[4]; ++ ++ keyptr = get_keyptr(); ++ ++ /* ++ * Pick a unique starting offset for each IP destination. ++ * The dest ip address is placed in the starting vector, ++ * which is then hashed with random data. ++ */ ++ hash[0] = (__force __u32)daddr; ++ hash[1] = keyptr->secret[9]; ++ hash[2] = keyptr->secret[10]; ++ hash[3] = keyptr->secret[11]; ++ ++ return half_md4_transform(hash, keyptr->secret); ++} ++ ++#ifdef CONFIG_INET ++ ++__u32 secure_tcp_sequence_number(__be32 saddr, __be32 daddr, ++ __be16 sport, __be16 dport) ++{ ++ __u32 seq; ++ __u32 hash[4]; ++ struct keydata *keyptr = get_keyptr(); ++ ++ /* ++ * Pick a unique starting offset for each TCP connection endpoints ++ * (saddr, daddr, sport, dport). ++ * Note that the words are placed into the starting vector, which is ++ * then mixed with a partial MD4 over random data. ++ */ ++ hash[0] = (__force u32)saddr; ++ hash[1] = (__force u32)daddr; ++ hash[2] = ((__force u16)sport << 16) + (__force u16)dport; ++ hash[3] = keyptr->secret[11]; ++ ++ seq = half_md4_transform(hash, keyptr->secret) & HASH_MASK; ++ seq += keyptr->count; ++ /* ++ * As close as possible to RFC 793, which ++ * suggests using a 250 kHz clock. ++ * Further reading shows this assumes 2 Mb/s networks. ++ * For 10 Mb/s Ethernet, a 1 MHz clock is appropriate. ++ * For 10 Gb/s Ethernet, a 1 GHz clock should be ok, but ++ * we also need to limit the resolution so that the u32 seq ++ * overlaps less than one time per MSL (2 minutes). ++ * Choosing a clock of 64 ns period is OK. (period of 274 s) ++ */ ++ seq += ktime_to_ns(ktime_get_real()) >> 6; ++ ++ return seq; ++} ++ ++/* Generate secure starting point for ephemeral IPV4 transport port search */ ++u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport) ++{ ++ struct keydata *keyptr = get_keyptr(); ++ u32 hash[4]; ++ ++ /* ++ * Pick a unique starting offset for each ephemeral port search ++ * (saddr, daddr, dport) and 48bits of random data. ++ */ ++ hash[0] = (__force u32)saddr; ++ hash[1] = (__force u32)daddr; ++ hash[2] = (__force u32)dport ^ keyptr->secret[10]; ++ hash[3] = keyptr->secret[11]; ++ ++ return half_md4_transform(hash, keyptr->secret); ++} ++EXPORT_SYMBOL_GPL(secure_ipv4_port_ephemeral); ++ ++#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) ++u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, ++ __be16 dport) ++{ ++ struct keydata *keyptr = get_keyptr(); ++ u32 hash[12]; ++ ++ memcpy(hash, saddr, 16); ++ hash[4] = (__force u32)dport; ++ memcpy(&hash[5], keyptr->secret, sizeof(__u32) * 7); ++ ++ return twothirdsMD4Transform((const __u32 *)daddr, hash); ++} ++#endif ++ ++#if defined(CONFIG_IP_DCCP) || defined(CONFIG_IP_DCCP_MODULE) ++/* Similar to secure_tcp_sequence_number but generate a 48 bit value ++ * bit's 32-47 increase every key exchange ++ * 0-31 hash(source, dest) ++ */ ++u64 secure_dccp_sequence_number(__be32 saddr, __be32 daddr, ++ __be16 sport, __be16 dport) ++{ ++ u64 seq; ++ __u32 hash[4]; ++ struct keydata *keyptr = get_keyptr(); ++ ++ hash[0] = (__force u32)saddr; ++ hash[1] = (__force u32)daddr; ++ hash[2] = ((__force u16)sport << 16) + (__force u16)dport; ++ hash[3] = keyptr->secret[11]; ++ ++ seq = half_md4_transform(hash, keyptr->secret); ++ seq |= ((u64)keyptr->count) << (32 - HASH_BITS); ++ ++ seq += ktime_to_ns(ktime_get_real()); ++ seq &= (1ull << 48) - 1; ++ ++ return seq; ++} ++EXPORT_SYMBOL(secure_dccp_sequence_number); ++#endif ++ ++#endif /* CONFIG_INET */ ++ ++ ++/* ++ * Get a random word for internal kernel use only. Similar to urandom but ++ * with the goal of minimal entropy pool depletion. As a result, the random ++ * value is not cryptographically secure but for several uses the cost of ++ * depleting entropy is too high ++ */ ++DEFINE_PER_CPU(__u32 [4], get_random_int_hash); ++unsigned int get_random_int(void) ++{ ++ struct keydata *keyptr; ++ __u32 *hash = get_cpu_var(get_random_int_hash); ++ int ret; ++ ++ keyptr = get_keyptr(); ++ hash[0] += current->pid + jiffies + get_cycles(); ++ ++ ret = half_md4_transform(hash, keyptr->secret); ++ put_cpu_var(get_random_int_hash); ++ ++ return ret; ++} ++ ++/* ++ * randomize_range() returns a start address such that ++ * ++ * [...... .....] ++ * start end ++ * ++ * a with size "len" starting at the return value is inside in the ++ * area defined by [start, end], but is otherwise randomized. ++ */ ++unsigned long ++randomize_range(unsigned long start, unsigned long end, unsigned long len) ++{ ++ unsigned long range = end - len - start; ++ ++ if (end <= start + len) ++ return 0; ++ return PAGE_ALIGN(get_random_int() % range + start); ++} +diff -Nur linux-2.6.39.orig/fs/fcntl.c linux-2.6.39/fs/fcntl.c +--- linux-2.6.39.orig/fs/fcntl.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/fs/fcntl.c 2011-08-01 14:38:19.000000000 +0200 +@@ -142,6 +142,7 @@ + } + return ret; + } ++EXPORT_SYMBOL(sys_dup); + + #define SETFL_MASK (O_APPEND | O_NONBLOCK | O_NDELAY | O_DIRECT | O_NOATIME) + +diff -Nur linux-2.6.39.orig/include/linux/miscdevice.h linux-2.6.39/include/linux/miscdevice.h +--- linux-2.6.39.orig/include/linux/miscdevice.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/include/linux/miscdevice.h 2011-08-01 14:38:19.000000000 +0200 +@@ -18,6 +18,7 @@ + #define APOLLO_MOUSE_MINOR 7 + #define PC110PAD_MINOR 9 + /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ ++#define CRYPTODEV_MINOR 70 /* /dev/crypto */ + #define WATCHDOG_MINOR 130 /* Watchdog timer */ + #define TEMP_MINOR 131 /* Temperature Sensor */ + #define RTC_MINOR 135 +diff -Nur linux-2.6.39.orig/include/linux/random.h linux-2.6.39/include/linux/random.h +--- linux-2.6.39.orig/include/linux/random.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/include/linux/random.h 2011-08-01 14:38:19.000000000 +0200 +@@ -9,6 +9,7 @@ + + #include + #include ++#include /* for __u32 in user space */ + #include + + /* ioctl()'s for the random number generator */ +@@ -34,6 +35,30 @@ + /* Clear the entropy pool and associated counters. (Superuser only.) */ + #define RNDCLEARPOOL _IO( 'R', 0x06 ) + ++#ifdef CONFIG_FIPS_RNG ++ ++/* Size of seed value - equal to AES blocksize */ ++#define AES_BLOCK_SIZE_BYTES 16 ++#define SEED_SIZE_BYTES AES_BLOCK_SIZE_BYTES ++/* Size of AES key */ ++#define KEY_SIZE_BYTES 16 ++ ++/* ioctl() structure used by FIPS 140-2 Tests */ ++struct rand_fips_test { ++ unsigned char key[KEY_SIZE_BYTES]; /* Input */ ++ unsigned char datetime[SEED_SIZE_BYTES]; /* Input */ ++ unsigned char seed[SEED_SIZE_BYTES]; /* Input */ ++ unsigned char result[SEED_SIZE_BYTES]; /* Output */ ++}; ++ ++/* FIPS 140-2 RNG Variable Seed Test. (Superuser only.) */ ++#define RNDFIPSVST _IOWR('R', 0x10, struct rand_fips_test) ++ ++/* FIPS 140-2 RNG Monte Carlo Test. (Superuser only.) */ ++#define RNDFIPSMCT _IOWR('R', 0x11, struct rand_fips_test) ++ ++#endif /* #ifdef CONFIG_FIPS_RNG */ ++ + struct rand_pool_info { + int entropy_count; + int buf_size; +@@ -54,6 +79,10 @@ + unsigned int value); + extern void add_interrupt_randomness(int irq); + ++extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); ++extern int random_input_wait(void); ++#define HAS_RANDOM_INPUT_WAIT 1 ++ + extern void get_random_bytes(void *buf, int nbytes); + void generate_random_uuid(unsigned char uuid_out[16]); + diff --git a/target/linux/patches/2.6.39.4/rb4xx.patch b/target/linux/patches/2.6.39.4/rb4xx.patch new file mode 100644 index 000000000..4f2e1cd84 --- /dev/null +++ b/target/linux/patches/2.6.39.4/rb4xx.patch @@ -0,0 +1,25253 @@ +diff -Nur linux-2.6.39.orig/arch/mips/Kconfig linux-2.6.39/arch/mips/Kconfig +--- linux-2.6.39.orig/arch/mips/Kconfig 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/Kconfig 2011-08-24 18:17:24.000000000 +0200 +@@ -84,6 +84,23 @@ + help + Support for the Atheros AR71XX/AR724X/AR913X SoCs. + ++config ATHEROS_AR71XX ++ bool "Atheros AR71xx based boards" ++ select CEVT_R4K ++ select CSRC_R4K ++ select DMA_NONCOHERENT ++ select HW_HAS_PCI ++ select IRQ_CPU ++ select ARCH_REQUIRE_GPIOLIB ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_HAS_CPU_MIPS32_R2 ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select SYS_HAS_EARLY_PRINTK ++ select MIPS_MACHINE ++ help ++ Support for Atheros AR71xx based boards. ++ + config BCM47XX + bool "Broadcom BCM47XX based boards" + select CEVT_R4K +@@ -739,6 +756,7 @@ + endchoice + + source "arch/mips/alchemy/Kconfig" ++source "arch/mips/ar71xx/Kconfig" + source "arch/mips/ath79/Kconfig" + source "arch/mips/bcm63xx/Kconfig" + source "arch/mips/jazz/Kconfig" +@@ -907,6 +925,9 @@ + config MIPS_DISABLE_OBSOLETE_IDE + bool + ++config MYLOADER ++ bool ++ + config SYNC_R4K + bool + +diff -Nur linux-2.6.39.orig/arch/mips/Makefile linux-2.6.39/arch/mips/Makefile +--- linux-2.6.39.orig/arch/mips/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/Makefile 2011-08-24 18:17:24.000000000 +0200 +@@ -158,6 +158,13 @@ + endif + cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 + ++# ++# Atheros AR71xx ++# ++core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/ ++cflags-$(CONFIG_ATHEROS_AR71XX) += -I$(srctree)/arch/mips/include/asm/mach-ar71xx ++load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000 ++ + cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) + cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) + cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) +@@ -174,6 +181,7 @@ + # + libs-$(CONFIG_ARC) += arch/mips/fw/arc/ + libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ ++libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/ + libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/ + libs-y += arch/mips/fw/lib/ + +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/Kconfig linux-2.6.39/arch/mips/ar71xx/Kconfig +--- linux-2.6.39.orig/arch/mips/ar71xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/Kconfig 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,420 @@ ++if ATHEROS_AR71XX ++ ++menu "Atheros AR71xx machine selection" ++ ++config AR71XX_MACH_AP81 ++ bool "Atheros AP81 board support" ++ select SOC_AR913X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_AP83 ++ bool "Atheros AP83 board support" ++ select SOC_AR913X ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_AP96 ++ bool "Atheros AP96 board support" ++ select SOC_AR71XX ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AP94_PCI if PCI ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_AP121 ++ bool "Atheros AP121 board support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ select AR71XX_DEV_AR9XXX_WMAC ++ select SOC_AR933X ++ default n ++ ++config AR71XX_MACH_DB120 ++ bool "Atheros DB120 board support" ++ select SOC_AR934X ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_DB120_PCI if PCI ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_DIR_600_A1 ++ bool "D-Link DIR-600 rev. A1 support" ++ select SOC_AR724X ++ select AR71XX_DEV_AP91_PCI if PCI ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_NVRAM ++ default n ++ ++config AR71XX_MACH_DIR_615_C1 ++ bool "D-Link DIR-615 rev. C1 support" ++ select SOC_AR913X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_NVRAM ++ default n ++ ++config AR71XX_MACH_DIR_825_B1 ++ bool "D-Link DIR-825 rev. B1 board support" ++ select SOC_AR71XX ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AP94_PCI if PCI ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_JA76PF ++ bool "jjPlus JA76PF board support" ++ select SOC_AR71XX ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_PB42_PCI if PCI ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_JWAP003 ++ bool "jjPlus JWAP003 board support" ++ select SOC_AR71XX ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_PB42_PCI if PCI ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_PB42 ++ bool "Atheros PB42 board support" ++ select SOC_AR71XX ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_PB42_PCI if PCI ++ default n ++ ++config AR71XX_MACH_PB44 ++ bool "Atheros PB44 board support" ++ select SOC_AR71XX ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_PB42_PCI if PCI ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_PB92 ++ bool "Atheros PB92 board support" ++ select SOC_AR724X ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_PB9X_PCI if PCI ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_AW_NR580 ++ bool "AzureWave AW-NR580 board support" ++ select SOC_AR71XX ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_PB42_PCI if PCI ++ select AR71XX_DEV_LEDS_GPIO ++ default n ++ ++config AR71XX_MACH_WZR_HP_AG300H ++ bool "Buffalo WZR-HP-AG300H board support" ++ select SOC_AR71XX ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_WZR_HP_G300NH ++ bool "Buffalo WZR-HP-G300NH board support" ++ select SOC_AR913X ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ select RTL8366_SMI ++ default n ++ ++config AR71XX_MACH_WP543 ++ bool "Compex WP543/WPJ543 board support" ++ select SOC_AR71XX ++ select MYLOADER ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_PB42_PCI if PCI ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_WRT160NL ++ bool "Linksys WRT160NL board support" ++ select SOC_AR913X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ select AR71XX_NVRAM ++ default n ++ ++config AR71XX_MACH_WRT400N ++ bool "Linksys WRT400N board support" ++ select SOC_AR71XX ++ select AR71XX_DEV_AP94_PCI if PCI ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n ++ ++config AR71XX_MACH_RB4XX ++ bool "MikroTik RouterBOARD 4xx series support" ++ select SOC_AR71XX ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_RB750 ++ bool "MikroTik RouterBOARD 750 support" ++ select SOC_AR724X ++ default n ++ ++config AR71XX_MACH_WNDR3700 ++ bool "NETGEAR WNDR3700 board support" ++ select SOC_AR71XX ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AP94_PCI if PCI ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_WNR2000 ++ bool "NETGEAR WNR2000 board support" ++ select SOC_AR913X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n ++ ++config AR71XX_MACH_MZK_W04NU ++ bool "Planex MZK-W04NU board support" ++ select SOC_AR913X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_MZK_W300NH ++ bool "Planex MZK-W300NH board support" ++ select SOC_AR913X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n ++ ++config AR71XX_MACH_NBG460N ++ bool "Zyxel NBG460N/550N/550NH board support" ++ select SOC_AR913X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n ++ ++config AR71XX_MACH_TL_MR3X20 ++ bool "TP-LINK TL-MR3220/3420 support" ++ select SOC_AR724X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AP91_PCI if PCI ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_TL_WA901ND ++ bool "TP-LINK TL-WA901ND support" ++ select SOC_AR724X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AP91_PCI if PCI ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n ++ ++config AR71XX_MACH_TL_WA901ND_V2 ++ bool "TP-LINK TL-WA901ND v2 support" ++ select SOC_AR913X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n ++ ++config AR71XX_MACH_TL_WR741ND ++ bool "TP-LINK TL-WR741ND support" ++ select SOC_AR724X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AP91_PCI if PCI ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n ++ ++config AR71XX_MACH_TL_WR841N_V1 ++ bool "TP-LINK TL-WR841N v1 support" ++ select SOC_AR71XX ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_PB42_PCI if PCI ++ select AR71XX_DEV_DSA ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n ++ ++config AR71XX_MACH_TL_WR941ND ++ bool "TP-LINK TL-WR941ND support" ++ select SOC_AR913X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_DSA ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n ++ ++config AR71XX_MACH_TL_WR1043ND ++ bool "TP-LINK TL-WR1043ND support" ++ select SOC_AR913X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_TEW_632BRP ++ bool "TRENDnet TEW-632BRP support" ++ select SOC_AR913X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR9XXX_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_NVRAM ++ default n ++ ++config AR71XX_MACH_UBNT ++ bool "Ubiquiti AR71xx based boards support" ++ select SOC_AR71XX ++ select SOC_AR724X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AP91_PCI if PCI ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_PB42_PCI if PCI ++ select AR71XX_DEV_USB ++ default n ++ ++config AR71XX_MACH_EAP7660D ++ bool "Senao EAP7660D support" ++ select SOC_AR71XX ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n ++ ++config AR71XX_MACH_ZCN_1523H ++ bool "Zcomax ZCN-1523H support" ++ select SOC_AR724X ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AP91_PCI if PCI ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n ++ ++endmenu ++ ++config SOC_AR71XX ++ bool ++ select USB_ARCH_HAS_EHCI ++ select USB_ARCH_HAS_OHCI ++ ++config SOC_AR724X ++ bool ++ select USB_ARCH_HAS_EHCI ++ select USB_ARCH_HAS_OHCI ++ ++config SOC_AR913X ++ bool ++ select USB_ARCH_HAS_EHCI ++ ++config SOC_AR934X ++ bool ++ select USB_ARCH_HAS_EHCI ++ ++config AR71XX_DEV_M25P80 ++ def_bool n ++ ++config AR71XX_DEV_AP91_PCI ++ select AR71XX_PCI_ATH9K_FIXUP ++ def_bool n ++ ++config AR71XX_DEV_AP94_PCI ++ select AR71XX_PCI_ATH9K_FIXUP ++ def_bool n ++ ++config AR71XX_DEV_AR9XXX_WMAC ++ def_bool n ++ ++config AR71XX_DEV_DB120_PCI ++ select AR71XX_PCI_ATH9K_FIXUP ++ def_bool n ++ ++config AR71XX_DEV_DSA ++ def_bool n ++ ++config AR71XX_DEV_GPIO_BUTTONS ++ def_bool n ++ ++config AR71XX_DEV_LEDS_GPIO ++ def_bool n ++ ++config AR71XX_DEV_PB42_PCI ++ def_bool n ++ ++config AR71XX_DEV_PB9X_PCI ++ def_bool n ++ ++config AR71XX_DEV_USB ++ def_bool n ++ ++config AR71XX_NVRAM ++ def_bool n ++ ++config AR71XX_PCI_ATH9K_FIXUP ++ def_bool n ++ ++config SOC_AR933X ++ bool ++ select USB_ARCH_HAS_EHCI ++ ++endif +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/Makefile linux-2.6.39/arch/mips/ar71xx/Makefile +--- linux-2.6.39.orig/arch/mips/ar71xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/Makefile 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,67 @@ ++# ++# Makefile for the Atheros AR71xx SoC specific parts of the kernel ++# ++# Copyright (C) 2008-2009 Gabor Juhos ++# Copyright (C) 2008 Imre Kaloz ++# ++# This program is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License version 2 as published ++# by the Free Software Foundation. ++ ++obj-y := prom.o irq.o setup.o devices.o gpio.o ar71xx.o ++ ++obj-$(CONFIG_EARLY_PRINTK) += early_printk.o ++obj-$(CONFIG_PCI) += pci.o ++ ++obj-$(CONFIG_AR71XX_DEV_AP91_PCI) += dev-ap91-pci.o ++obj-$(CONFIG_AR71XX_DEV_AP94_PCI) += dev-ap94-pci.o ++obj-$(CONFIG_AR71XX_DEV_AR9XXX_WMAC) += dev-ar9xxx-wmac.o ++obj-$(CONFIG_AR71XX_DEV_DB120_PCI) += dev-db120-pci.o ++obj-$(CONFIG_AR71XX_DEV_DSA) += dev-dsa.o ++obj-$(CONFIG_AR71XX_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o ++obj-$(CONFIG_AR71XX_DEV_LEDS_GPIO) += dev-leds-gpio.o ++obj-$(CONFIG_AR71XX_DEV_M25P80) += dev-m25p80.o ++obj-$(CONFIG_AR71XX_DEV_PB42_PCI) += dev-pb42-pci.o ++obj-$(CONFIG_AR71XX_DEV_PB9X_PCI) += dev-pb9x-pci.o ++obj-$(CONFIG_AR71XX_DEV_USB) += dev-usb.o ++ ++obj-$(CONFIG_AR71XX_NVRAM) += nvram.o ++obj-$(CONFIG_AR71XX_PCI_ATH9K_FIXUP) += pci-ath9k-fixup.o ++ ++obj-$(CONFIG_AR71XX_MACH_AP121) += mach-ap121.o ++obj-$(CONFIG_AR71XX_MACH_AP81) += mach-ap81.o ++obj-$(CONFIG_AR71XX_MACH_AP83) += mach-ap83.o ++obj-$(CONFIG_AR71XX_MACH_AP96) += mach-ap96.o ++obj-$(CONFIG_AR71XX_MACH_AW_NR580) += mach-aw-nr580.o ++obj-$(CONFIG_AR71XX_MACH_DB120) += mach-db120.o ++obj-$(CONFIG_AR71XX_MACH_DIR_600_A1) += mach-dir-600-a1.o ++obj-$(CONFIG_AR71XX_MACH_DIR_615_C1) += mach-dir-615-c1.o ++obj-$(CONFIG_AR71XX_MACH_DIR_825_B1) += mach-dir-825-b1.o ++obj-$(CONFIG_AR71XX_MACH_EAP7660D) += mach-eap7660d.o ++obj-$(CONFIG_AR71XX_MACH_JA76PF) += mach-ja76pf.o ++obj-$(CONFIG_AR71XX_MACH_JWAP003) += mach-jwap003.o ++obj-$(CONFIG_AR71XX_MACH_MZK_W04NU) += mach-mzk-w04nu.o ++obj-$(CONFIG_AR71XX_MACH_MZK_W300NH) += mach-mzk-w300nh.o ++obj-$(CONFIG_AR71XX_MACH_NBG460N) += mach-nbg460n.o ++obj-$(CONFIG_AR71XX_MACH_PB42) += mach-pb42.o ++obj-$(CONFIG_AR71XX_MACH_PB44) += mach-pb44.o ++obj-$(CONFIG_AR71XX_MACH_PB92) += mach-pb92.o ++obj-$(CONFIG_AR71XX_MACH_RB4XX) += mach-rb4xx.o ++obj-$(CONFIG_AR71XX_MACH_RB750) += mach-rb750.o ++obj-$(CONFIG_AR71XX_MACH_TEW_632BRP) += mach-tew-632brp.o ++obj-$(CONFIG_AR71XX_MACH_TL_MR3X20) += mach-tl-mr3x20.o ++obj-$(CONFIG_AR71XX_MACH_TL_WA901ND) += mach-tl-wa901nd.o ++obj-$(CONFIG_AR71XX_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o ++obj-$(CONFIG_AR71XX_MACH_TL_WR741ND) += mach-tl-wr741nd.o ++obj-$(CONFIG_AR71XX_MACH_TL_WR841N_V1) += mach-tl-wr841n.o ++obj-$(CONFIG_AR71XX_MACH_TL_WR941ND) += mach-tl-wr941nd.o ++obj-$(CONFIG_AR71XX_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o ++obj-$(CONFIG_AR71XX_MACH_UBNT) += mach-ubnt.o ++obj-$(CONFIG_AR71XX_MACH_WNDR3700) += mach-wndr3700.o ++obj-$(CONFIG_AR71XX_MACH_WNR2000) += mach-wnr2000.o ++obj-$(CONFIG_AR71XX_MACH_WP543) += mach-wp543.o ++obj-$(CONFIG_AR71XX_MACH_WRT160NL) += mach-wrt160nl.o ++obj-$(CONFIG_AR71XX_MACH_WRT400N) += mach-wrt400n.o ++obj-$(CONFIG_AR71XX_MACH_WZR_HP_G300NH) += mach-wzr-hp-g300nh.o ++obj-$(CONFIG_AR71XX_MACH_WZR_HP_AG300H) += mach-wzr-hp-ag300h.o ++obj-$(CONFIG_AR71XX_MACH_ZCN_1523H) += mach-zcn-1523h.o +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/ar71xx.c linux-2.6.39/arch/mips/ar71xx/ar71xx.c +--- linux-2.6.39.orig/arch/mips/ar71xx/ar71xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/ar71xx.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,230 @@ ++/* ++ * AR71xx SoC routines ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++static DEFINE_MUTEX(ar71xx_flash_mutex); ++static DEFINE_SPINLOCK(ar71xx_device_lock); ++ ++void __iomem *ar71xx_ddr_base; ++EXPORT_SYMBOL_GPL(ar71xx_ddr_base); ++ ++void __iomem *ar71xx_pll_base; ++EXPORT_SYMBOL_GPL(ar71xx_pll_base); ++ ++void __iomem *ar71xx_reset_base; ++EXPORT_SYMBOL_GPL(ar71xx_reset_base); ++ ++void __iomem *ar71xx_gpio_base; ++EXPORT_SYMBOL_GPL(ar71xx_gpio_base); ++ ++void __iomem *ar71xx_usb_ctrl_base; ++EXPORT_SYMBOL_GPL(ar71xx_usb_ctrl_base); ++ ++void ar71xx_device_stop(u32 mask) ++{ ++ unsigned long flags; ++ u32 mask_inv; ++ u32 t; ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t | mask); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); ++ t |= mask; ++ t &= ~mask_inv; ++ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t | mask); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR933X_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR933X_RESET_REG_RESET_MODULE, t | mask); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ case AR71XX_SOC_AR9341: ++ case AR71XX_SOC_AR9342: ++ case AR71XX_SOC_AR9344: ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR934X_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR934X_RESET_REG_RESET_MODULE, t | mask); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ default: ++ BUG(); ++ } ++} ++EXPORT_SYMBOL_GPL(ar71xx_device_stop); ++ ++void ar71xx_device_start(u32 mask) ++{ ++ unsigned long flags; ++ u32 mask_inv; ++ u32 t; ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t & ~mask); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); ++ t &= ~mask; ++ t |= mask_inv; ++ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t & ~mask); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR933X_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR933X_RESET_REG_RESET_MODULE, t & ~mask); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ case AR71XX_SOC_AR9341: ++ case AR71XX_SOC_AR9342: ++ case AR71XX_SOC_AR9344: ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR934X_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR934X_RESET_REG_RESET_MODULE, t & ~mask); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ default: ++ BUG(); ++ } ++} ++EXPORT_SYMBOL_GPL(ar71xx_device_start); ++ ++int ar71xx_device_stopped(u32 mask) ++{ ++ unsigned long flags; ++ u32 t; ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR933X_RESET_REG_RESET_MODULE); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ case AR71XX_SOC_AR9341: ++ case AR71XX_SOC_AR9342: ++ case AR71XX_SOC_AR9344: ++ spin_lock_irqsave(&ar71xx_device_lock, flags); ++ t = ar71xx_reset_rr(AR934X_RESET_REG_RESET_MODULE); ++ spin_unlock_irqrestore(&ar71xx_device_lock, flags); ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ return ((t & mask) == mask); ++} ++EXPORT_SYMBOL_GPL(ar71xx_device_stopped); ++ ++void ar71xx_ddr_flush(u32 reg) ++{ ++ ar71xx_ddr_wr(reg, 1); ++ while ((ar71xx_ddr_rr(reg) & 0x1)) ++ ; ++ ++ ar71xx_ddr_wr(reg, 1); ++ while ((ar71xx_ddr_rr(reg) & 0x1)) ++ ; ++} ++EXPORT_SYMBOL_GPL(ar71xx_ddr_flush); ++ ++void ar71xx_flash_acquire(void) ++{ ++ mutex_lock(&ar71xx_flash_mutex); ++} ++EXPORT_SYMBOL_GPL(ar71xx_flash_acquire); ++ ++void ar71xx_flash_release(void) ++{ ++ mutex_unlock(&ar71xx_flash_mutex); ++} ++EXPORT_SYMBOL_GPL(ar71xx_flash_release); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-ap91-pci.c linux-2.6.39/arch/mips/ar71xx/dev-ap91-pci.c +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-ap91-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-ap91-pci.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,71 @@ ++/* ++ * Atheros AP91 reference board PCI initialization ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "dev-ap91-pci.h" ++#include "pci-ath9k-fixup.h" ++ ++static struct ath9k_platform_data ap91_wmac_data = { ++ .led_pin = -1, ++}; ++static char ap91_wmac_mac[6]; ++ ++static struct ar71xx_pci_irq ap91_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ } ++}; ++ ++static int ap91_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ switch (PCI_SLOT(dev->devfn)) { ++ case 0: ++ dev->dev.platform_data = &ap91_wmac_data; ++ break; ++ } ++ ++ return 0; ++} ++ ++__init void ap91_pci_setup_wmac_led_pin(int pin) ++{ ++ ap91_wmac_data.led_pin = pin; ++} ++ ++__init void ap91_pci_setup_wmac_gpio(u32 mask, u32 val) ++{ ++ ap91_wmac_data.gpio_mask = mask; ++ ap91_wmac_data.gpio_val = val; ++} ++ ++void __init ap91_pci_init(u8 *cal_data, u8 *mac_addr) ++{ ++ if (cal_data) ++ memcpy(ap91_wmac_data.eeprom_data, cal_data, ++ sizeof(ap91_wmac_data.eeprom_data)); ++ ++ if (mac_addr) { ++ memcpy(ap91_wmac_mac, mac_addr, sizeof(ap91_wmac_mac)); ++ ap91_wmac_data.macaddr = ap91_wmac_mac; ++ } ++ ++ ar71xx_pci_plat_dev_init = ap91_pci_plat_dev_init; ++ ar71xx_pci_init(ARRAY_SIZE(ap91_pci_irqs), ap91_pci_irqs); ++ ++ pci_enable_ath9k_fixup(0, ap91_wmac_data.eeprom_data); ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-ap91-pci.h linux-2.6.39/arch/mips/ar71xx/dev-ap91-pci.h +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-ap91-pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-ap91-pci.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,25 @@ ++/* ++ * Atheros AP91 reference board PCI initialization ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_AP91_PCI_H ++#define _AR71XX_DEV_AP91_PCI_H ++ ++#if defined(CONFIG_AR71XX_DEV_AP91_PCI) ++void ap91_pci_init(u8 *cal_data, u8 *mac_addr) __init; ++void ap91_pci_setup_wmac_led_pin(int pin) __init; ++void ap91_pci_setup_wmac_gpio(u32 mask, u32 val) __init; ++#else ++static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) { } ++static inline void ap91_pci_setup_wmac_led_pin(int pin) { } ++static inline void ap91_pci_setup_wmac_gpio(u32 mask, u32 gpio) { } ++#endif ++ ++#endif /* _AR71XX_DEV_AP91_PCI_H */ ++ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-ap94-pci.c linux-2.6.39/arch/mips/ar71xx/dev-ap94-pci.c +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-ap94-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-ap94-pci.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,109 @@ ++/* ++ * Atheros AP94 reference board PCI initialization ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "dev-ap94-pci.h" ++#include "pci-ath9k-fixup.h" ++ ++static struct ath9k_platform_data ap94_wmac0_data = { ++ .led_pin = -1, ++}; ++static struct ath9k_platform_data ap94_wmac1_data = { ++ .led_pin = -1, ++}; ++static char ap94_wmac0_mac[6]; ++static char ap94_wmac1_mac[6]; ++ ++static struct ar71xx_pci_irq ap94_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ }, { ++ .slot = 1, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV1, ++ } ++}; ++ ++static int ap94_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ switch (PCI_SLOT(dev->devfn)) { ++ case 17: ++ dev->dev.platform_data = &ap94_wmac0_data; ++ break; ++ ++ case 18: ++ dev->dev.platform_data = &ap94_wmac1_data; ++ break; ++ } ++ ++ return 0; ++} ++ ++__init void ap94_pci_setup_wmac_led_pin(unsigned wmac, int pin) ++{ ++ switch (wmac) { ++ case 0: ++ ap94_wmac0_data.led_pin = pin; ++ break; ++ case 1: ++ ap94_wmac1_data.led_pin = pin; ++ break; ++ } ++} ++ ++__init void ap94_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val) ++{ ++ switch (wmac) { ++ case 0: ++ ap94_wmac0_data.gpio_mask = mask; ++ ap94_wmac0_data.gpio_val = val; ++ break; ++ case 1: ++ ap94_wmac1_data.gpio_mask = mask; ++ ap94_wmac1_data.gpio_val = val; ++ break; ++ } ++} ++ ++void __init ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, ++ u8 *cal_data1, u8 *mac_addr1) ++{ ++ if (cal_data0) ++ memcpy(ap94_wmac0_data.eeprom_data, cal_data0, ++ sizeof(ap94_wmac0_data.eeprom_data)); ++ ++ if (cal_data1) ++ memcpy(ap94_wmac1_data.eeprom_data, cal_data1, ++ sizeof(ap94_wmac1_data.eeprom_data)); ++ ++ if (mac_addr0) { ++ memcpy(ap94_wmac0_mac, mac_addr0, sizeof(ap94_wmac0_mac)); ++ ap94_wmac0_data.macaddr = ap94_wmac0_mac; ++ } ++ ++ if (mac_addr1) { ++ memcpy(ap94_wmac1_mac, mac_addr1, sizeof(ap94_wmac1_mac)); ++ ap94_wmac1_data.macaddr = ap94_wmac1_mac; ++ } ++ ++ ar71xx_pci_plat_dev_init = ap94_pci_plat_dev_init; ++ ar71xx_pci_init(ARRAY_SIZE(ap94_pci_irqs), ap94_pci_irqs); ++ ++ pci_enable_ath9k_fixup(17, ap94_wmac0_data.eeprom_data); ++ pci_enable_ath9k_fixup(18, ap94_wmac1_data.eeprom_data); ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-ap94-pci.h linux-2.6.39/arch/mips/ar71xx/dev-ap94-pci.h +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-ap94-pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-ap94-pci.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,31 @@ ++/* ++ * Atheros AP94 reference board PCI initialization ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_AP94_PCI_H ++#define _AR71XX_DEV_AP94_PCI_H ++ ++#if defined(CONFIG_AR71XX_DEV_AP94_PCI) ++void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, ++ u8 *cal_data1, u8 *mac_addr1) __init; ++ ++void ap94_pci_setup_wmac_led_pin(unsigned wmac, int pin) __init; ++void ap94_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val) __init; ++ ++#else ++static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, ++ u8 *cal_data1, u8 *mac_addr1) {} ++ ++static inline void ap94_pci_setup_wmac_led_pin(unsigned wmac, int pin) {} ++static inline void ap94_pci_setup_wmac_gpio(unsigned wmac, ++ u32 mask, u32 val) {} ++#endif ++ ++#endif /* _AR71XX_DEV_AP94_PCI_H */ ++ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-ar9xxx-wmac.c linux-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.c +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-ar9xxx-wmac.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,154 @@ ++/* ++ * Atheros AR9XXX SoCs built-in WMAC device support ++ * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "dev-ar9xxx-wmac.h" ++ ++#define MHZ_25 (25 * 1000 * 1000) ++ ++static struct ath9k_platform_data ar9xxx_wmac_data = { ++ .led_pin = -1, ++}; ++static char ar9xxx_wmac_mac[6]; ++ ++static struct resource ar9xxx_wmac_resources[] = { ++ { ++ /* .start and .end fields are filled dynamically */ ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = AR71XX_CPU_IRQ_IP2, ++ .end = AR71XX_CPU_IRQ_IP2, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device ar9xxx_wmac_device = { ++ .name = "ath9k", ++ .id = -1, ++ .resource = ar9xxx_wmac_resources, ++ .num_resources = ARRAY_SIZE(ar9xxx_wmac_resources), ++ .dev = { ++ .platform_data = &ar9xxx_wmac_data, ++ }, ++}; ++ ++static void ar913x_wmac_init(void) ++{ ++ ar71xx_device_stop(RESET_MODULE_AMBA2WMAC); ++ mdelay(10); ++ ++ ar71xx_device_start(RESET_MODULE_AMBA2WMAC); ++ mdelay(10); ++ ++ ar9xxx_wmac_resources[0].start = AR91XX_WMAC_BASE; ++ ar9xxx_wmac_resources[0].end = AR91XX_WMAC_BASE + AR91XX_WMAC_SIZE - 1; ++} ++ ++static int ar933x_r1_get_wmac_revision(void) ++{ ++ return ar71xx_soc_rev; ++} ++ ++static int ar933x_wmac_reset(void) ++{ ++ unsigned retries = 0; ++ ++ ar71xx_device_stop(AR933X_RESET_WMAC); ++ ar71xx_device_start(AR933X_RESET_WMAC); ++ ++ while (1) { ++ u32 bootstrap; ++ ++ bootstrap = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP); ++ if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0) ++ return 0; ++ ++ if (retries > 20) ++ break; ++ ++ udelay(10000); ++ retries++; ++ } ++ ++ pr_err("ar93xx: WMAC reset timed out"); ++ return -ETIMEDOUT; ++} ++ ++static void ar933x_wmac_init(void) ++{ ++ ar9xxx_wmac_device.name = "ar933x_wmac"; ++ ar9xxx_wmac_resources[0].start = AR933X_WMAC_BASE; ++ ar9xxx_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; ++ if (ar71xx_ref_freq == MHZ_25) ++ ar9xxx_wmac_data.is_clk_25mhz = true; ++ ++ if (ar71xx_soc_rev == 1) ++ ar9xxx_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision; ++ ++ ar9xxx_wmac_data.external_reset = ar933x_wmac_reset; ++ ++ ar933x_wmac_reset(); ++} ++ ++static void ar934x_wmac_init(void) ++{ ++ ar9xxx_wmac_device.name = "ar934x_wmac"; ++ ar9xxx_wmac_resources[0].start = AR934X_WMAC_BASE; ++ ar9xxx_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1; ++ if (ar71xx_ref_freq == MHZ_25) ++ ar9xxx_wmac_data.is_clk_25mhz = true; ++} ++ ++void __init ar9xxx_add_device_wmac(u8 *cal_data, u8 *mac_addr) ++{ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ ar913x_wmac_init(); ++ break; ++ ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ ar933x_wmac_init(); ++ break; ++ ++ case AR71XX_SOC_AR9341: ++ case AR71XX_SOC_AR9342: ++ case AR71XX_SOC_AR9344: ++ ar934x_wmac_init(); ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ if (cal_data) ++ memcpy(ar9xxx_wmac_data.eeprom_data, cal_data, ++ sizeof(ar9xxx_wmac_data.eeprom_data)); ++ ++ if (mac_addr) { ++ memcpy(ar9xxx_wmac_mac, mac_addr, sizeof(ar9xxx_wmac_mac)); ++ ar9xxx_wmac_data.macaddr = ar9xxx_wmac_mac; ++ } ++ ++ platform_device_register(&ar9xxx_wmac_device); ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-ar9xxx-wmac.h linux-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.h +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-ar9xxx-wmac.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,20 @@ ++/* ++ * Atheros AR9XXX SoCs built-in WMAC device support ++ * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_AR9XXX_WMAC_H ++#define _AR71XX_DEV_AR9XXX_WMAC_H ++ ++void ar9xxx_add_device_wmac(u8 *cal_data, u8 *mac_addr) __init; ++ ++#endif /* _AR71XX_DEV_AR9XXX_WMAC_H */ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-db120-pci.c linux-2.6.39/arch/mips/ar71xx/dev-db120-pci.c +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-db120-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-db120-pci.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,31 @@ ++/* ++ * Atheros db120 reference board PCI initialization ++ * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan ++ * ++ * Parts of this file are based on Atheros linux 2.6.31 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++ ++#include ++#include ++ ++#include "dev-db120-pci.h" ++ ++static struct ar71xx_pci_irq db120_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ } ++}; ++ ++void __init db120_pci_init(void) ++{ ++ ar71xx_pci_init(ARRAY_SIZE(db120_pci_irqs), db120_pci_irqs); ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-db120-pci.h linux-2.6.39/arch/mips/ar71xx/dev-db120-pci.h +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-db120-pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-db120-pci.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,22 @@ ++/* ++ * Atheros DB120 reference board PCI initialization ++ * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan ++ * ++ * Parts of this file are based on Atheros linux 2.6.31 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_DB120_PCI_H ++#define _AR71XX_DEV_DB120_PCI_H ++ ++#if defined(CONFIG_AR71XX_DEV_DB120_PCI) ++void db120_pci_init(void); ++#else ++static inline void db120_pci_init(void) { } ++#endif ++ ++#endif /* _AR71XX_DEV_DB120_PCI_H */ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-dsa.c linux-2.6.39/arch/mips/ar71xx/dev-dsa.c +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-dsa.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-dsa.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,50 @@ ++/* ++ * Atheros AR71xx DSA switch device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "devices.h" ++#include "dev-dsa.h" ++ ++static struct platform_device ar71xx_dsa_switch_device = { ++ .name = "dsa", ++ .id = 0, ++}; ++ ++void __init ar71xx_add_device_dsa(unsigned int id, ++ struct dsa_platform_data *d) ++{ ++ int i; ++ ++ switch (id) { ++ case 0: ++ d->netdev = &ar71xx_eth0_device.dev; ++ break; ++ case 1: ++ d->netdev = &ar71xx_eth1_device.dev; ++ break; ++ default: ++ printk(KERN_ERR ++ "ar71xx: invalid ethernet id %d for DSA switch\n", ++ id); ++ return; ++ } ++ ++ for (i = 0; i < d->nr_chips; i++) ++ d->chip[i].mii_bus = &ar71xx_mdio_device.dev; ++ ++ ar71xx_dsa_switch_device.dev.platform_data = d; ++ ++ platform_device_register(&ar71xx_dsa_switch_device); ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-dsa.h linux-2.6.39/arch/mips/ar71xx/dev-dsa.h +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-dsa.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-dsa.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,20 @@ ++/* ++ * Atheros AR71xx DSA switch device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_DSA_H ++#define _AR71XX_DEV_DSA_H ++ ++#include ++ ++void ar71xx_add_device_dsa(unsigned int id, ++ struct dsa_platform_data *d) __init; ++ ++#endif /* _AR71XX_DEV_DSA_H */ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-gpio-buttons.c linux-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.c +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-gpio-buttons.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,58 @@ ++/* ++ * Atheros AR71xx GPIO button support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include "linux/init.h" ++#include "linux/slab.h" ++#include ++ ++#include "dev-gpio-buttons.h" ++ ++void __init ar71xx_register_gpio_keys_polled(int id, ++ unsigned poll_interval, ++ unsigned nbuttons, ++ struct gpio_keys_button *buttons) ++{ ++ struct platform_device *pdev; ++ struct gpio_keys_platform_data pdata; ++ struct gpio_keys_button *p; ++ int err; ++ ++ p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); ++ if (!p) ++ return; ++ ++ memcpy(p, buttons, nbuttons * sizeof(*p)); ++ ++ pdev = platform_device_alloc("gpio-keys-polled", id); ++ if (!pdev) ++ goto err_free_buttons; ++ ++ memset(&pdata, 0, sizeof(pdata)); ++ pdata.poll_interval = poll_interval; ++ pdata.nbuttons = nbuttons; ++ pdata.buttons = p; ++ ++ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); ++ if (err) ++ goto err_put_pdev; ++ ++ err = platform_device_add(pdev); ++ if (err) ++ goto err_put_pdev; ++ ++ return; ++ ++err_put_pdev: ++ platform_device_put(pdev); ++ ++err_free_buttons: ++ kfree(p); ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-gpio-buttons.h linux-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.h +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-gpio-buttons.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,23 @@ ++/* ++ * Atheros AR71xx GPIO button support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_GPIO_BUTTONS_H ++#define _AR71XX_DEV_GPIO_BUTTONS_H ++ ++#include ++#include ++ ++void ar71xx_register_gpio_keys_polled(int id, ++ unsigned poll_interval, ++ unsigned nbuttons, ++ struct gpio_keys_button *buttons); ++ ++#endif /* _AR71XX_DEV_GPIO_BUTTONS_H */ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-leds-gpio.c linux-2.6.39/arch/mips/ar71xx/dev-leds-gpio.c +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-leds-gpio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-leds-gpio.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,57 @@ ++/* ++ * Atheros AR71xx GPIO LED device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include "dev-leds-gpio.h" ++ ++void __init ar71xx_add_device_leds_gpio(int id, unsigned num_leds, ++ struct gpio_led *leds) ++{ ++ struct platform_device *pdev; ++ struct gpio_led_platform_data pdata; ++ struct gpio_led *p; ++ int err; ++ ++ p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); ++ if (!p) ++ return; ++ ++ memcpy(p, leds, num_leds * sizeof(*p)); ++ ++ pdev = platform_device_alloc("leds-gpio", id); ++ if (!pdev) ++ goto err_free_leds; ++ ++ memset(&pdata, 0, sizeof(pdata)); ++ pdata.num_leds = num_leds; ++ pdata.leds = p; ++ ++ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); ++ if (err) ++ goto err_put_pdev; ++ ++ err = platform_device_add(pdev); ++ if (err) ++ goto err_put_pdev; ++ ++ return; ++ ++err_put_pdev: ++ platform_device_put(pdev); ++ ++err_free_leds: ++ kfree(p); ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-leds-gpio.h linux-2.6.39/arch/mips/ar71xx/dev-leds-gpio.h +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-leds-gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-leds-gpio.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,21 @@ ++/* ++ * Atheros AR71xx GPIO LED device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_LEDS_GPIO_H ++#define _AR71XX_DEV_LEDS_GPIO_H ++ ++#include ++ ++void ar71xx_add_device_leds_gpio(int id, ++ unsigned num_leds, ++ struct gpio_led *leds) __init; ++ ++#endif /* _AR71XX_DEV_LEDS_GPIO_H */ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-m25p80.c linux-2.6.39/arch/mips/ar71xx/dev-m25p80.c +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-m25p80.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-m25p80.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,30 @@ ++/* ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include "devices.h" ++#include "dev-m25p80.h" ++ ++static struct spi_board_info ar71xx_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "m25p80", ++ } ++}; ++ ++void __init ar71xx_add_device_m25p80(struct flash_platform_data *pdata) ++{ ++ ar71xx_spi_info[0].platform_data = pdata; ++ ar71xx_add_device_spi(NULL, ar71xx_spi_info, ++ ARRAY_SIZE(ar71xx_spi_info)); ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-m25p80.h linux-2.6.39/arch/mips/ar71xx/dev-m25p80.h +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-m25p80.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-m25p80.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,16 @@ ++/* ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_M25P80_H ++#define _AR71XX_DEV_M25P80_H ++ ++#include ++ ++void ar71xx_add_device_m25p80(struct flash_platform_data *pdata) __init; ++ ++#endif /* _AR71XX_DEV_M25P80_H */ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-pb42-pci.c linux-2.6.39/arch/mips/ar71xx/dev-pb42-pci.c +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-pb42-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-pb42-pci.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,40 @@ ++/* ++ * Atheros PB42 reference board PCI initialization ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++ ++#include ++#include ++ ++#include "dev-pb42-pci.h" ++ ++static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ }, { ++ .slot = 1, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV1, ++ }, { ++ .slot = 2, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV2, ++ } ++}; ++ ++void __init pb42_pci_init(void) ++{ ++ ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs); ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-pb42-pci.h linux-2.6.39/arch/mips/ar71xx/dev-pb42-pci.h +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-pb42-pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-pb42-pci.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,21 @@ ++/* ++ * Atheros PB42 reference board PCI initialization ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_PB42_PCI_H ++#define _AR71XX_DEV_PB42_PCI_H ++ ++#if defined(CONFIG_AR71XX_DEV_PB42_PCI) ++void pb42_pci_init(void) __init; ++#else ++static inline void pb42_pci_init(void) { } ++#endif ++ ++#endif /* _AR71XX_DEV_PB42_PCI_H */ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-pb9x-pci.c linux-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.c +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-pb9x-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,33 @@ ++/* ++ * Atheros PB9x reference board PCI initialization ++ * ++ * Copyright (C) 2010 Felix Fietkau ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++ ++#include ++#include ++ ++#include "dev-pb9x-pci.h" ++ ++static struct ar71xx_pci_irq pb9x_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ } ++}; ++ ++void __init pb9x_pci_init(void) ++{ ++ ar71xx_pci_init(ARRAY_SIZE(pb9x_pci_irqs), pb9x_pci_irqs); ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-pb9x-pci.h linux-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.h +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-pb9x-pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,22 @@ ++/* ++ * Atheros PB9x reference board PCI initialization ++ * ++ * Copyright (C) 2010 Felix Fietkau ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_PB9X_PCI_H ++#define _AR71XX_DEV_PB9X_PCI_H ++ ++#if defined(CONFIG_AR71XX_DEV_PB9X_PCI) ++void pb9x_pci_init(void) __init; ++#else ++static inline void pb9x_pci_init(void) { } ++#endif ++ ++#endif /* _AR71XX_DEV_PB9X_PCI_H */ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-usb.c linux-2.6.39/arch/mips/ar71xx/dev-usb.c +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-usb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-usb.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,199 @@ ++/* ++ * Atheros AR71xx USB host device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "dev-usb.h" ++ ++/* ++ * OHCI (USB full speed host controller) ++ */ ++static struct resource ar71xx_ohci_resources[] = { ++ [0] = { ++ .start = AR71XX_OHCI_BASE, ++ .end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = AR71XX_MISC_IRQ_OHCI, ++ .end = AR71XX_MISC_IRQ_OHCI, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource ar7240_ohci_resources[] = { ++ [0] = { ++ .start = AR7240_OHCI_BASE, ++ .end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = AR71XX_CPU_IRQ_USB, ++ .end = AR71XX_CPU_IRQ_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 ar71xx_ohci_dmamask = DMA_BIT_MASK(32); ++static struct platform_device ar71xx_ohci_device = { ++ .name = "ar71xx-ohci", ++ .id = -1, ++ .resource = ar71xx_ohci_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_ohci_resources), ++ .dev = { ++ .dma_mask = &ar71xx_ohci_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++}; ++ ++/* ++ * EHCI (USB high/full speed host controller) ++ */ ++static struct resource ar71xx_ehci_resources[] = { ++ [0] = { ++ .start = AR71XX_EHCI_BASE, ++ .end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = AR71XX_CPU_IRQ_USB, ++ .end = AR71XX_CPU_IRQ_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 ar71xx_ehci_dmamask = DMA_BIT_MASK(32); ++static struct ar71xx_ehci_platform_data ar71xx_ehci_data; ++ ++static struct platform_device ar71xx_ehci_device = { ++ .name = "ar71xx-ehci", ++ .id = -1, ++ .resource = ar71xx_ehci_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_ehci_resources), ++ .dev = { ++ .dma_mask = &ar71xx_ehci_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ .platform_data = &ar71xx_ehci_data, ++ }, ++}; ++ ++#define AR71XX_USB_RESET_MASK \ ++ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_PHY \ ++ | RESET_MODULE_USB_OHCI_DLL) ++ ++#define AR7240_USB_RESET_MASK \ ++ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_OHCI_DLL_7240) ++ ++static void __init ar71xx_usb_setup(void) ++{ ++ ar71xx_device_stop(AR71XX_USB_RESET_MASK); ++ mdelay(1000); ++ ar71xx_device_start(AR71XX_USB_RESET_MASK); ++ ++ /* Turning on the Buff and Desc swap bits */ ++ ar71xx_usb_ctrl_wr(USB_CTRL_REG_CONFIG, 0xf0000); ++ ++ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ ++ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x20c00); ++ ++ mdelay(900); ++ ++ platform_device_register(&ar71xx_ohci_device); ++ platform_device_register(&ar71xx_ehci_device); ++} ++ ++static void __init ar7240_usb_setup(void) ++{ ++ ar71xx_device_stop(AR7240_USB_RESET_MASK); ++ mdelay(1000); ++ ar71xx_device_start(AR7240_USB_RESET_MASK); ++ ++ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ ++ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x3); ++ ++ ar71xx_ohci_device.resource = ar7240_ohci_resources; ++ ar71xx_ohci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); ++ platform_device_register(&ar71xx_ohci_device); ++} ++ ++static void __init ar7241_usb_setup(void) ++{ ++ ar71xx_device_start(AR724X_RESET_USBSUS_OVERRIDE); ++ mdelay(10); ++ ++ ar71xx_device_start(AR724X_RESET_USB_HOST); ++ mdelay(10); ++ ++ ar71xx_device_start(AR724X_RESET_USB_PHY); ++ mdelay(10); ++ ++ ar71xx_ehci_data.is_ar91xx = 1; ++ ar71xx_ehci_device.resource = ar7240_ohci_resources; ++ ar71xx_ehci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); ++ platform_device_register(&ar71xx_ehci_device); ++} ++ ++static void __init ar91xx_usb_setup(void) ++{ ++ ar71xx_device_stop(RESET_MODULE_USBSUS_OVERRIDE); ++ mdelay(10); ++ ++ ar71xx_device_start(RESET_MODULE_USB_HOST); ++ mdelay(10); ++ ++ ar71xx_device_start(RESET_MODULE_USB_PHY); ++ mdelay(10); ++ ++ ar71xx_ehci_data.is_ar91xx = 1; ++ platform_device_register(&ar71xx_ehci_device); ++} ++ ++void __init ar71xx_add_device_usb(void) ++{ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7240: ++ ar7240_usb_setup(); ++ break; ++ ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ar7241_usb_setup(); ++ break; ++ ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ ar71xx_usb_setup(); ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ case AR71XX_SOC_AR9341: ++ case AR71XX_SOC_AR9342: ++ case AR71XX_SOC_AR9344: ++ ar91xx_usb_setup(); ++ break; ++ ++ default: ++ BUG(); ++ } ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-usb.h linux-2.6.39/arch/mips/ar71xx/dev-usb.h +--- linux-2.6.39.orig/arch/mips/ar71xx/dev-usb.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/dev-usb.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,17 @@ ++/* ++ * Atheros AR71xx USB host device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_DEV_USB_H ++#define _AR71XX_DEV_USB_H ++ ++void ar71xx_add_device_usb(void) __init; ++ ++#endif /* _AR71XX_DEV_USB_H */ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/devices.c linux-2.6.39/arch/mips/ar71xx/devices.c +--- linux-2.6.39.orig/arch/mips/ar71xx/devices.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/devices.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,765 @@ ++/* ++ * Atheros AR71xx SoC platform devices ++ * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros 2.6.15 BSP ++ * Parts of this file are based on Atheros 2.6.31 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "devices.h" ++ ++unsigned char ar71xx_mac_base[ETH_ALEN] __initdata; ++ ++static struct resource ar71xx_uart_resources[] = { ++ { ++ .start = AR71XX_UART_BASE, ++ .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) ++static struct plat_serial8250_port ar71xx_uart_data[] = { ++ { ++ .mapbase = AR71XX_UART_BASE, ++ .irq = AR71XX_MISC_IRQ_UART, ++ .flags = AR71XX_UART_FLAGS, ++ .iotype = UPIO_MEM32, ++ .regshift = 2, ++ }, { ++ /* terminating entry */ ++ } ++}; ++ ++static struct platform_device ar71xx_uart_device = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .resource = ar71xx_uart_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_uart_resources), ++ .dev = { ++ .platform_data = ar71xx_uart_data ++ }, ++}; ++ ++static struct resource ar933x_uart_resources[] = { ++ { ++ .start = AR933X_UART_BASE, ++ .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = AR71XX_MISC_IRQ_UART, ++ .end = AR71XX_MISC_IRQ_UART, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct ar933x_uart_platform_data ar933x_uart_data; ++static struct platform_device ar933x_uart_device = { ++ .name = "ar933x-uart", ++ .id = -1, ++ .resource = ar933x_uart_resources, ++ .num_resources = ARRAY_SIZE(ar933x_uart_resources), ++ .dev = { ++ .platform_data = &ar933x_uart_data, ++ }, ++}; ++ ++void __init ar71xx_add_device_uart(void) ++{ ++ struct platform_device *pdev; ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ pdev = &ar71xx_uart_device; ++ ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq; ++ break; ++ ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ pdev = &ar933x_uart_device; ++ ar933x_uart_data.uartclk = ar71xx_ref_freq; ++ break; ++ ++ case AR71XX_SOC_AR9341: ++ case AR71XX_SOC_AR9342: ++ case AR71XX_SOC_AR9344: ++ pdev = &ar71xx_uart_device; ++ ar71xx_uart_data[0].uartclk = ar71xx_ref_freq; ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ platform_device_register(pdev); ++} ++ ++static struct resource ar71xx_mdio_resources[] = { ++ { ++ .name = "mdio_base", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_GE0_BASE, ++ .end = AR71XX_GE0_BASE + 0x200 - 1, ++ } ++}; ++ ++static struct ag71xx_mdio_platform_data ar71xx_mdio_data; ++ ++struct platform_device ar71xx_mdio_device = { ++ .name = "ag71xx-mdio", ++ .id = -1, ++ .resource = ar71xx_mdio_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_mdio_resources), ++ .dev = { ++ .platform_data = &ar71xx_mdio_data, ++ }, ++}; ++ ++static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift) ++{ ++ void __iomem *base; ++ u32 t; ++ ++ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); ++ ++ t = __raw_readl(base + cfg_reg); ++ t &= ~(3 << shift); ++ t |= (2 << shift); ++ __raw_writel(t, base + cfg_reg); ++ udelay(100); ++ ++ __raw_writel(pll_val, base + pll_reg); ++ ++ t |= (3 << shift); ++ __raw_writel(t, base + cfg_reg); ++ udelay(100); ++ ++ t &= ~(3 << shift); ++ __raw_writel(t, base + cfg_reg); ++ udelay(100); ++ ++ printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n", ++ (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg)); ++ ++ iounmap(base); ++} ++ ++void __init ar71xx_add_device_mdio(u32 phy_mask) ++{ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7240: ++ ar71xx_mdio_data.is_ar7240 = 1; ++ break; ++ case AR71XX_SOC_AR7241: ++ ar71xx_mdio_data.is_ar7240 = 1; ++ ar71xx_mdio_resources[0].start = AR71XX_GE1_BASE; ++ ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1; ++ break; ++ case AR71XX_SOC_AR7242: ++ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, ++ AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000, ++ AR71XX_ETH0_PLL_SHIFT); ++ break; ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ ar71xx_mdio_data.is_ar7240 = 1; ++ ar71xx_mdio_resources[0].start = AR71XX_GE1_BASE; ++ ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1; ++ break; ++ default: ++ break; ++ } ++ ++ ar71xx_mdio_data.phy_mask = phy_mask; ++ ++ platform_device_register(&ar71xx_mdio_device); ++} ++ ++struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; ++struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; ++ ++static u32 ar71xx_get_eth_pll(unsigned int mac, int speed) ++{ ++ struct ar71xx_eth_pll_data *pll_data; ++ u32 pll_val; ++ ++ switch (mac) { ++ case 0: ++ pll_data = &ar71xx_eth0_pll_data; ++ break; ++ case 1: ++ pll_data = &ar71xx_eth1_pll_data; ++ break; ++ default: ++ BUG(); ++ } ++ ++ switch (speed) { ++ case SPEED_10: ++ pll_val = pll_data->pll_10; ++ break; ++ case SPEED_100: ++ pll_val = pll_data->pll_100; ++ break; ++ case SPEED_1000: ++ pll_val = pll_data->pll_1000; ++ break; ++ default: ++ BUG(); ++ } ++ ++ return pll_val; ++} ++ ++static void ar71xx_set_pll_ge0(int speed) ++{ ++ u32 val = ar71xx_get_eth_pll(0, speed); ++ ++ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK, ++ val, AR71XX_ETH0_PLL_SHIFT); ++} ++ ++static void ar71xx_set_pll_ge1(int speed) ++{ ++ u32 val = ar71xx_get_eth_pll(1, speed); ++ ++ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK, ++ val, AR71XX_ETH1_PLL_SHIFT); ++} ++ ++static void ar724x_set_pll_ge0(int speed) ++{ ++ /* TODO */ ++} ++ ++static void ar724x_set_pll_ge1(int speed) ++{ ++ /* TODO */ ++} ++ ++static void ar7242_set_pll_ge0(int speed) ++{ ++ u32 val = ar71xx_get_eth_pll(0, speed); ++ ++ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR7242_PLL_REG_ETH0_INT_CLOCK, ++ val, AR71XX_ETH0_PLL_SHIFT); ++} ++ ++static void ar91xx_set_pll_ge0(int speed) ++{ ++ u32 val = ar71xx_get_eth_pll(0, speed); ++ ++ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK, ++ val, AR91XX_ETH0_PLL_SHIFT); ++} ++ ++static void ar91xx_set_pll_ge1(int speed) ++{ ++ u32 val = ar71xx_get_eth_pll(1, speed); ++ ++ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK, ++ val, AR91XX_ETH1_PLL_SHIFT); ++} ++ ++static void ar933x_set_pll_ge0(int speed) ++{ ++ /* TODO */ ++} ++ ++static void ar933x_set_pll_ge1(int speed) ++{ ++ /* TODO */ ++} ++ ++static void ar71xx_ddr_flush_ge0(void) ++{ ++ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0); ++} ++ ++static void ar71xx_ddr_flush_ge1(void) ++{ ++ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1); ++} ++ ++static void ar724x_ddr_flush_ge0(void) ++{ ++ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0); ++} ++ ++static void ar724x_ddr_flush_ge1(void) ++{ ++ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1); ++} ++ ++static void ar91xx_ddr_flush_ge0(void) ++{ ++ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0); ++} ++ ++static void ar91xx_ddr_flush_ge1(void) ++{ ++ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1); ++} ++ ++static void ar933x_ddr_flush_ge0(void) ++{ ++ ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0); ++} ++ ++static void ar933x_ddr_flush_ge1(void) ++{ ++ ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1); ++} ++ ++static struct resource ar71xx_eth0_resources[] = { ++ { ++ .name = "mac_base", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_GE0_BASE, ++ .end = AR71XX_GE0_BASE + 0x200 - 1, ++ }, { ++ .name = "mii_ctrl", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL, ++ .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3, ++ }, { ++ .name = "mac_irq", ++ .flags = IORESOURCE_IRQ, ++ .start = AR71XX_CPU_IRQ_GE0, ++ .end = AR71XX_CPU_IRQ_GE0, ++ }, ++}; ++ ++struct ag71xx_platform_data ar71xx_eth0_data = { ++ .reset_bit = RESET_MODULE_GE0_MAC, ++}; ++ ++struct platform_device ar71xx_eth0_device = { ++ .name = "ag71xx", ++ .id = 0, ++ .resource = ar71xx_eth0_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_eth0_resources), ++ .dev = { ++ .platform_data = &ar71xx_eth0_data, ++ }, ++}; ++ ++static struct resource ar71xx_eth1_resources[] = { ++ { ++ .name = "mac_base", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_GE1_BASE, ++ .end = AR71XX_GE1_BASE + 0x200 - 1, ++ }, { ++ .name = "mii_ctrl", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL, ++ .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3, ++ }, { ++ .name = "mac_irq", ++ .flags = IORESOURCE_IRQ, ++ .start = AR71XX_CPU_IRQ_GE1, ++ .end = AR71XX_CPU_IRQ_GE1, ++ }, ++}; ++ ++struct ag71xx_platform_data ar71xx_eth1_data = { ++ .reset_bit = RESET_MODULE_GE1_MAC, ++}; ++ ++struct platform_device ar71xx_eth1_device = { ++ .name = "ag71xx", ++ .id = 1, ++ .resource = ar71xx_eth1_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_eth1_resources), ++ .dev = { ++ .platform_data = &ar71xx_eth1_data, ++ }, ++}; ++ ++#define AR71XX_PLL_VAL_1000 0x00110000 ++#define AR71XX_PLL_VAL_100 0x00001099 ++#define AR71XX_PLL_VAL_10 0x00991099 ++ ++#define AR724X_PLL_VAL_1000 0x00110000 ++#define AR724X_PLL_VAL_100 0x00001099 ++#define AR724X_PLL_VAL_10 0x00991099 ++ ++#define AR7242_PLL_VAL_1000 0x1c000000 ++#define AR7242_PLL_VAL_100 0x00000101 ++#define AR7242_PLL_VAL_10 0x00001616 ++ ++#define AR91XX_PLL_VAL_1000 0x1a000000 ++#define AR91XX_PLL_VAL_100 0x13000a44 ++#define AR91XX_PLL_VAL_10 0x00441099 ++ ++#define AR933X_PLL_VAL_1000 0x00110000 ++#define AR933X_PLL_VAL_100 0x00001099 ++#define AR933X_PLL_VAL_10 0x00991099 ++ ++static void __init ar71xx_init_eth_pll_data(unsigned int id) ++{ ++ struct ar71xx_eth_pll_data *pll_data; ++ u32 pll_10, pll_100, pll_1000; ++ ++ switch (id) { ++ case 0: ++ pll_data = &ar71xx_eth0_pll_data; ++ break; ++ case 1: ++ pll_data = &ar71xx_eth1_pll_data; ++ break; ++ default: ++ BUG(); ++ } ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ pll_10 = AR71XX_PLL_VAL_10; ++ pll_100 = AR71XX_PLL_VAL_100; ++ pll_1000 = AR71XX_PLL_VAL_1000; ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ pll_10 = AR724X_PLL_VAL_10; ++ pll_100 = AR724X_PLL_VAL_100; ++ pll_1000 = AR724X_PLL_VAL_1000; ++ break; ++ ++ case AR71XX_SOC_AR7242: ++ pll_10 = AR7242_PLL_VAL_10; ++ pll_100 = AR7242_PLL_VAL_100; ++ pll_1000 = AR7242_PLL_VAL_1000; ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ pll_10 = AR91XX_PLL_VAL_10; ++ pll_100 = AR91XX_PLL_VAL_100; ++ pll_1000 = AR91XX_PLL_VAL_1000; ++ break; ++ ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ pll_10 = AR933X_PLL_VAL_10; ++ pll_100 = AR933X_PLL_VAL_100; ++ pll_1000 = AR933X_PLL_VAL_1000; ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ if (!pll_data->pll_10) ++ pll_data->pll_10 = pll_10; ++ ++ if (!pll_data->pll_100) ++ pll_data->pll_100 = pll_100; ++ ++ if (!pll_data->pll_1000) ++ pll_data->pll_1000 = pll_1000; ++} ++ ++static int ar71xx_eth_instance __initdata; ++void __init ar71xx_add_device_eth(unsigned int id) ++{ ++ struct platform_device *pdev; ++ struct ag71xx_platform_data *pdata; ++ ++ ar71xx_init_eth_pll_data(id); ++ ++ switch (id) { ++ case 0: ++ switch (ar71xx_eth0_data.phy_if_mode) { ++ case PHY_INTERFACE_MODE_MII: ++ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII; ++ break; ++ case PHY_INTERFACE_MODE_GMII: ++ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII; ++ break; ++ case PHY_INTERFACE_MODE_RMII: ++ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII; ++ break; ++ default: ++ printk(KERN_ERR "ar71xx: invalid PHY interface mode " ++ "for eth0\n"); ++ return; ++ } ++ pdev = &ar71xx_eth0_device; ++ break; ++ case 1: ++ switch (ar71xx_eth1_data.phy_if_mode) { ++ case PHY_INTERFACE_MODE_RMII: ++ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII; ++ break; ++ default: ++ printk(KERN_ERR "ar71xx: invalid PHY interface mode " ++ "for eth1\n"); ++ return; ++ } ++ pdev = &ar71xx_eth1_device; ++ break; ++ default: ++ printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id); ++ return; ++ } ++ ++ pdata = pdev->dev.platform_data; ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 ++ : ar71xx_ddr_flush_ge0; ++ pdata->set_pll = id ? ar71xx_set_pll_ge1 ++ : ar71xx_set_pll_ge0; ++ break; ++ ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 ++ : ar71xx_ddr_flush_ge0; ++ pdata->set_pll = id ? ar71xx_set_pll_ge1 ++ : ar71xx_set_pll_ge0; ++ pdata->has_gbit = 1; ++ break; ++ ++ case AR71XX_SOC_AR7242: ++ ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO | ++ RESET_MODULE_GE0_PHY; ++ ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO | ++ RESET_MODULE_GE1_PHY; ++ pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 ++ : ar724x_ddr_flush_ge0; ++ pdata->set_pll = id ? ar724x_set_pll_ge1 ++ : ar7242_set_pll_ge0; ++ pdata->has_gbit = 1; ++ pdata->is_ar724x = 1; ++ ++ if (!pdata->fifo_cfg1) ++ pdata->fifo_cfg1 = 0x0010ffff; ++ if (!pdata->fifo_cfg2) ++ pdata->fifo_cfg2 = 0x015500aa; ++ if (!pdata->fifo_cfg3) ++ pdata->fifo_cfg3 = 0x01f00140; ++ break; ++ ++ case AR71XX_SOC_AR7241: ++ ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO; ++ ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO; ++ /* fall through */ ++ case AR71XX_SOC_AR7240: ++ ar71xx_eth0_data.reset_bit |= RESET_MODULE_GE0_PHY; ++ ar71xx_eth1_data.reset_bit |= RESET_MODULE_GE1_PHY; ++ pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 ++ : ar724x_ddr_flush_ge0; ++ pdata->set_pll = id ? ar724x_set_pll_ge1 ++ : ar724x_set_pll_ge0; ++ pdata->is_ar724x = 1; ++ if (ar71xx_soc == AR71XX_SOC_AR7240) ++ pdata->is_ar7240 = 1; ++ ++ if (!pdata->fifo_cfg1) ++ pdata->fifo_cfg1 = 0x0010ffff; ++ if (!pdata->fifo_cfg2) ++ pdata->fifo_cfg2 = 0x015500aa; ++ if (!pdata->fifo_cfg3) ++ pdata->fifo_cfg3 = 0x01f00140; ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 ++ : ar91xx_ddr_flush_ge0; ++ pdata->set_pll = id ? ar91xx_set_pll_ge1 ++ : ar91xx_set_pll_ge0; ++ pdata->is_ar91xx = 1; ++ break; ++ ++ case AR71XX_SOC_AR9132: ++ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 ++ : ar91xx_ddr_flush_ge0; ++ pdata->set_pll = id ? ar91xx_set_pll_ge1 ++ : ar91xx_set_pll_ge0; ++ pdata->is_ar91xx = 1; ++ pdata->has_gbit = 1; ++ break; ++ ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ ar71xx_eth0_data.reset_bit = AR933X_RESET_GE0_MAC | ++ AR933X_RESET_GE0_MDIO; ++ ar71xx_eth1_data.reset_bit = AR933X_RESET_GE1_MAC | ++ AR933X_RESET_GE1_MDIO; ++ pdata->ddr_flush = id ? ar933x_ddr_flush_ge1 ++ : ar933x_ddr_flush_ge0; ++ pdata->set_pll = id ? ar933x_set_pll_ge1 ++ : ar933x_set_pll_ge0; ++ pdata->has_gbit = 1; ++ pdata->is_ar724x = 1; ++ ++ if (!pdata->fifo_cfg1) ++ pdata->fifo_cfg1 = 0x0010ffff; ++ if (!pdata->fifo_cfg2) ++ pdata->fifo_cfg2 = 0x015500aa; ++ if (!pdata->fifo_cfg3) ++ pdata->fifo_cfg3 = 0x01f00140; ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ switch (pdata->phy_if_mode) { ++ case PHY_INTERFACE_MODE_GMII: ++ case PHY_INTERFACE_MODE_RGMII: ++ if (!pdata->has_gbit) { ++ printk(KERN_ERR "ar71xx: no gbit available on eth%d\n", ++ id); ++ return; ++ } ++ /* fallthrough */ ++ default: ++ break; ++ } ++ ++ if (!is_valid_ether_addr(pdata->mac_addr)) { ++ random_ether_addr(pdata->mac_addr); ++ printk(KERN_DEBUG ++ "ar71xx: using random MAC address for eth%d\n", ++ ar71xx_eth_instance); ++ } ++ ++ if (pdata->mii_bus_dev == NULL) ++ pdata->mii_bus_dev = &ar71xx_mdio_device.dev; ++ ++ /* Reset the device */ ++ ar71xx_device_stop(pdata->reset_bit); ++ mdelay(100); ++ ++ ar71xx_device_start(pdata->reset_bit); ++ mdelay(100); ++ ++ platform_device_register(pdev); ++ ar71xx_eth_instance++; ++} ++ ++static struct resource ar71xx_spi_resources[] = { ++ [0] = { ++ .start = AR71XX_SPI_BASE, ++ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static struct platform_device ar71xx_spi_device = { ++ .name = "ar71xx-spi", ++ .id = -1, ++ .resource = ar71xx_spi_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_spi_resources), ++}; ++ ++void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, ++ struct spi_board_info const *info, ++ unsigned n) ++{ ++ spi_register_board_info(info, n); ++ ar71xx_spi_device.dev.platform_data = pdata; ++ platform_device_register(&ar71xx_spi_device); ++} ++ ++void __init ar71xx_add_device_wdt(void) ++{ ++ platform_device_register_simple("ar71xx-wdt", -1, NULL, 0); ++} ++ ++void __init ar71xx_set_mac_base(unsigned char *mac) ++{ ++ memcpy(ar71xx_mac_base, mac, ETH_ALEN); ++} ++ ++void __init ar71xx_parse_mac_addr(char *mac_str) ++{ ++ u8 tmp[ETH_ALEN]; ++ int t; ++ ++ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", ++ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); ++ ++ if (t != ETH_ALEN) ++ t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx", ++ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); ++ ++ if (t == ETH_ALEN) ++ ar71xx_set_mac_base(tmp); ++ else ++ printk(KERN_DEBUG "ar71xx: failed to parse mac address " ++ "\"%s\"\n", mac_str); ++} ++ ++static int __init ar71xx_ethaddr_setup(char *str) ++{ ++ ar71xx_parse_mac_addr(str); ++ return 1; ++} ++__setup("ethaddr=", ar71xx_ethaddr_setup); ++ ++static int __init ar71xx_kmac_setup(char *str) ++{ ++ ar71xx_parse_mac_addr(str); ++ return 1; ++} ++__setup("kmac=", ar71xx_kmac_setup); ++ ++void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src, ++ unsigned offset) ++{ ++ u32 t; ++ ++ if (!is_valid_ether_addr(src)) { ++ memset(dst, '\0', ETH_ALEN); ++ return; ++ } ++ ++ t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]); ++ t += offset; ++ ++ dst[0] = src[0]; ++ dst[1] = src[1]; ++ dst[2] = src[2]; ++ dst[3] = (t >> 16) & 0xff; ++ dst[4] = (t >> 8) & 0xff; ++ dst[5] = t & 0xff; ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/devices.h linux-2.6.39/arch/mips/ar71xx/devices.h +--- linux-2.6.39.orig/arch/mips/ar71xx/devices.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/devices.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,50 @@ ++/* ++ * Atheros AR71xx SoC device definitions ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __AR71XX_DEVICES_H ++#define __AR71XX_DEVICES_H ++ ++#include ++ ++struct platform_device; ++ ++void ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, ++ struct spi_board_info const *info, ++ unsigned n) __init; ++ ++extern unsigned char ar71xx_mac_base[] __initdata; ++void ar71xx_parse_mac_addr(char *mac_str) __init; ++void ar71xx_init_mac(unsigned char *dst, const unsigned char *src, ++ unsigned offset) __init; ++ ++struct ar71xx_eth_pll_data { ++ u32 pll_10; ++ u32 pll_100; ++ u32 pll_1000; ++}; ++ ++extern struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; ++extern struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; ++ ++extern struct ag71xx_platform_data ar71xx_eth0_data; ++extern struct ag71xx_platform_data ar71xx_eth1_data; ++extern struct platform_device ar71xx_eth0_device; ++extern struct platform_device ar71xx_eth1_device; ++void ar71xx_add_device_eth(unsigned int id) __init; ++ ++extern struct platform_device ar71xx_mdio_device; ++void ar71xx_add_device_mdio(u32 phy_mask) __init; ++ ++void ar71xx_add_device_uart(void) __init; ++ ++void ar71xx_add_device_wdt(void) __init; ++ ++#endif /* __AR71XX_DEVICES_H */ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/early_printk.c linux-2.6.39/arch/mips/ar71xx/early_printk.c +--- linux-2.6.39.orig/arch/mips/ar71xx/early_printk.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/early_printk.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,96 @@ ++/* ++ * Atheros AR7xxx/AR9xxx SoC early printk support ++ * ++ * Copyright (C) 2008-2011 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++static void (*_prom_putchar) (unsigned char); ++ ++static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val) ++{ ++ u32 t; ++ ++ do { ++ t = __raw_readl(reg); ++ if ((t & mask) == val) ++ break; ++ } while (1); ++} ++ ++static void prom_putchar_ar71xx(unsigned char ch) ++{ ++ void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); ++ ++ prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE); ++ __raw_writel(ch, base + UART_TX * 4); ++ prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE); ++} ++ ++static void prom_putchar_ar933x(unsigned char ch) ++{ ++ void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE)); ++ ++ prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, ++ AR933X_UART_DATA_TX_CSR); ++ __raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG); ++ prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, ++ AR933X_UART_DATA_TX_CSR); ++} ++ ++static void prom_putchar_dummy(unsigned char ch) ++{ ++ /* nothing to do */ ++} ++ ++static void prom_putchar_init(void) ++{ ++ void __iomem *base; ++ u32 id; ++ ++ base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE)); ++ id = __raw_readl(base + AR71XX_RESET_REG_REV_ID); ++ id &= REV_ID_MAJOR_MASK; ++ ++ switch (id) { ++ case REV_ID_MAJOR_AR71XX: ++ case REV_ID_MAJOR_AR7240: ++ case REV_ID_MAJOR_AR7241: ++ case REV_ID_MAJOR_AR7242: ++ case REV_ID_MAJOR_AR913X: ++ case REV_ID_MAJOR_AR9341: ++ case REV_ID_MAJOR_AR9342: ++ case REV_ID_MAJOR_AR9344: ++ _prom_putchar = prom_putchar_ar71xx; ++ break; ++ ++ case REV_ID_MAJOR_AR9330: ++ case REV_ID_MAJOR_AR9331: ++ _prom_putchar = prom_putchar_ar933x; ++ break; ++ ++ default: ++ _prom_putchar = prom_putchar_dummy; ++ break; ++ } ++} ++ ++void prom_putchar(unsigned char ch) ++{ ++ if (!_prom_putchar) ++ prom_putchar_init(); ++ ++ _prom_putchar(ch); ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/gpio.c linux-2.6.39/arch/mips/ar71xx/gpio.c +--- linux-2.6.39.orig/arch/mips/ar71xx/gpio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/gpio.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,193 @@ ++/* ++ * Atheros AR7XXX/AR9XXX SoC GPIO API support ++ * ++ * Copyright (C) 2008-2011 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++static DEFINE_SPINLOCK(ar71xx_gpio_lock); ++ ++unsigned long ar71xx_gpio_count; ++EXPORT_SYMBOL(ar71xx_gpio_count); ++ ++void __ar71xx_gpio_set_value(unsigned gpio, int value) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ ++ if (value) ++ __raw_writel(1 << gpio, base + GPIO_REG_SET); ++ else ++ __raw_writel(1 << gpio, base + GPIO_REG_CLEAR); ++} ++EXPORT_SYMBOL(__ar71xx_gpio_set_value); ++ ++int __ar71xx_gpio_get_value(unsigned gpio) ++{ ++ return (__raw_readl(ar71xx_gpio_base + GPIO_REG_IN) >> gpio) & 1; ++} ++EXPORT_SYMBOL(__ar71xx_gpio_get_value); ++ ++static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset) ++{ ++ return __ar71xx_gpio_get_value(offset); ++} ++ ++static void ar71xx_gpio_set_value(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ __ar71xx_gpio_set_value(offset, value); ++} ++ ++static int ar71xx_gpio_direction_input(struct gpio_chip *chip, ++ unsigned offset) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); ++ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(1 << offset), ++ base + GPIO_REG_OE); ++ ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); ++ ++ return 0; ++} ++ ++static int ar71xx_gpio_direction_output(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); ++ ++ if (value) ++ __raw_writel(1 << offset, base + GPIO_REG_SET); ++ else ++ __raw_writel(1 << offset, base + GPIO_REG_CLEAR); ++ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) | (1 << offset), ++ base + GPIO_REG_OE); ++ ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); ++ ++ return 0; ++} ++ ++static struct gpio_chip ar71xx_gpio_chip = { ++ .label = "ar71xx", ++ .get = ar71xx_gpio_get_value, ++ .set = ar71xx_gpio_set_value, ++ .direction_input = ar71xx_gpio_direction_input, ++ .direction_output = ar71xx_gpio_direction_output, ++ .base = 0, ++ .ngpio = AR71XX_GPIO_COUNT, ++}; ++ ++void ar71xx_gpio_function_enable(u32 mask) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); ++ ++ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) | mask, ++ base + GPIO_REG_FUNC); ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_FUNC); ++ ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); ++} ++ ++void ar71xx_gpio_function_disable(u32 mask) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); ++ ++ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) & ~mask, ++ base + GPIO_REG_FUNC); ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_FUNC); ++ ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); ++} ++ ++void ar71xx_gpio_function_setup(u32 set, u32 clear) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); ++ ++ __raw_writel((__raw_readl(base + GPIO_REG_FUNC) & ~clear) | set, ++ base + GPIO_REG_FUNC); ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_FUNC); ++ ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); ++} ++EXPORT_SYMBOL(ar71xx_gpio_function_setup); ++ ++void __init ar71xx_gpio_init(void) ++{ ++ int err; ++ ++ if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, ++ "AR71xx GPIO controller")) ++ panic("cannot allocate AR71xx GPIO registers page"); ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT; ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT; ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT; ++ break; ++ ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ ar71xx_gpio_chip.ngpio = AR933X_GPIO_COUNT; ++ break; ++ ++ case AR71XX_SOC_AR9341: ++ case AR71XX_SOC_AR9342: ++ case AR71XX_SOC_AR9344: ++ ar71xx_gpio_chip.ngpio = AR934X_GPIO_COUNT; ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ err = gpiochip_add(&ar71xx_gpio_chip); ++ if (err) ++ panic("cannot add AR71xx GPIO chip, error=%d", err); ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/irq.c linux-2.6.39/arch/mips/ar71xx/irq.c +--- linux-2.6.39.orig/arch/mips/ar71xx/irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/irq.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,377 @@ ++/* ++ * Atheros AR71xx SoC specific interrupt handling ++ * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros 2.6.15 BSP ++ * Parts of this file are based on Atheros 2.6.31 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++static void ar71xx_gpio_irq_dispatch(void) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ u32 pending; ++ ++ pending = __raw_readl(base + GPIO_REG_INT_PENDING) & ++ __raw_readl(base + GPIO_REG_INT_ENABLE); ++ ++ if (pending) ++ do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1); ++ else ++ spurious_interrupt(); ++} ++ ++static void ar71xx_gpio_irq_unmask(struct irq_data *d) ++{ ++ unsigned int irq = d->irq - AR71XX_GPIO_IRQ_BASE; ++ void __iomem *base = ar71xx_gpio_base; ++ u32 t; ++ ++ t = __raw_readl(base + GPIO_REG_INT_ENABLE); ++ __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE); ++ ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_INT_ENABLE); ++} ++ ++static void ar71xx_gpio_irq_mask(struct irq_data *d) ++{ ++ unsigned int irq = d->irq - AR71XX_GPIO_IRQ_BASE; ++ void __iomem *base = ar71xx_gpio_base; ++ u32 t; ++ ++ t = __raw_readl(base + GPIO_REG_INT_ENABLE); ++ __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE); ++ ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_INT_ENABLE); ++} ++ ++static struct irq_chip ar71xx_gpio_irq_chip = { ++ .name = "AR71XX GPIO", ++ .irq_unmask = ar71xx_gpio_irq_unmask, ++ .irq_mask = ar71xx_gpio_irq_mask, ++ .irq_mask_ack = ar71xx_gpio_irq_mask, ++}; ++ ++static struct irqaction ar71xx_gpio_irqaction = { ++ .handler = no_action, ++ .name = "cascade [AR71XX GPIO]", ++}; ++ ++#define GPIO_INT_ALL 0xffff ++ ++static void __init ar71xx_gpio_irq_init(void) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ int i; ++ ++ __raw_writel(0, base + GPIO_REG_INT_ENABLE); ++ __raw_writel(0, base + GPIO_REG_INT_PENDING); ++ ++ /* setup type of all GPIO interrupts to level sensitive */ ++ __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE); ++ ++ /* setup polarity of all GPIO interrupts to active high */ ++ __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY); ++ ++ for (i = AR71XX_GPIO_IRQ_BASE; ++ i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &ar71xx_gpio_irq_chip, ++ handle_level_irq); ++ ++ setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction); ++} ++ ++static void ar71xx_misc_irq_dispatch(void) ++{ ++ u32 pending; ++ ++ pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) ++ & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); ++ ++ if (pending & MISC_INT_UART) ++ do_IRQ(AR71XX_MISC_IRQ_UART); ++ ++ else if (pending & MISC_INT_DMA) ++ do_IRQ(AR71XX_MISC_IRQ_DMA); ++ ++ else if (pending & MISC_INT_PERFC) ++ do_IRQ(AR71XX_MISC_IRQ_PERFC); ++ ++ else if (pending & MISC_INT_TIMER) ++ do_IRQ(AR71XX_MISC_IRQ_TIMER); ++ ++ else if (pending & MISC_INT_OHCI) ++ do_IRQ(AR71XX_MISC_IRQ_OHCI); ++ ++ else if (pending & MISC_INT_ERROR) ++ do_IRQ(AR71XX_MISC_IRQ_ERROR); ++ ++ else if (pending & MISC_INT_GPIO) ++ ar71xx_gpio_irq_dispatch(); ++ ++ else if (pending & MISC_INT_WDOG) ++ do_IRQ(AR71XX_MISC_IRQ_WDOG); ++ ++ else if (pending & MISC_INT_TIMER2) ++ do_IRQ(AR71XX_MISC_IRQ_TIMER2); ++ ++ else if (pending & MISC_INT_TIMER3) ++ do_IRQ(AR71XX_MISC_IRQ_TIMER3); ++ ++ else if (pending & MISC_INT_TIMER4) ++ do_IRQ(AR71XX_MISC_IRQ_TIMER4); ++ ++ else if (pending & MISC_INT_DDR_PERF) ++ do_IRQ(AR71XX_MISC_IRQ_DDR_PERF); ++ ++ else if (pending & MISC_INT_ENET_LINK) ++ do_IRQ(AR71XX_MISC_IRQ_ENET_LINK); ++ ++ else ++ spurious_interrupt(); ++} ++ ++static void ar71xx_misc_irq_unmask(struct irq_data *d) ++{ ++ unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE; ++ void __iomem *base = ar71xx_reset_base; ++ u32 t; ++ ++ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); ++ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); ++ ++ /* flush write */ ++ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); ++} ++ ++static void ar71xx_misc_irq_mask(struct irq_data *d) ++{ ++ unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE; ++ void __iomem *base = ar71xx_reset_base; ++ u32 t; ++ ++ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); ++ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); ++ ++ /* flush write */ ++ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); ++} ++ ++static void ar724x_misc_irq_ack(struct irq_data *d) ++{ ++ unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE; ++ void __iomem *base = ar71xx_reset_base; ++ u32 t; ++ ++ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); ++ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); ++ ++ /* flush write */ ++ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); ++} ++ ++static struct irq_chip ar71xx_misc_irq_chip = { ++ .name = "AR71XX MISC", ++ .irq_unmask = ar71xx_misc_irq_unmask, ++ .irq_mask = ar71xx_misc_irq_mask, ++}; ++ ++static struct irqaction ar71xx_misc_irqaction = { ++ .handler = no_action, ++ .name = "cascade [AR71XX MISC]", ++}; ++ ++static void __init ar71xx_misc_irq_init(void) ++{ ++ void __iomem *base = ar71xx_reset_base; ++ int i; ++ ++ __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); ++ __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ case AR71XX_SOC_AR9341: ++ case AR71XX_SOC_AR9342: ++ case AR71XX_SOC_AR9344: ++ ar71xx_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; ++ break; ++ default: ++ ar71xx_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; ++ break; ++ } ++ ++ for (i = AR71XX_MISC_IRQ_BASE; ++ i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &ar71xx_misc_irq_chip, ++ handle_level_irq); ++ ++ setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction); ++} ++ ++/* ++ * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for ++ * these devices typically allocate coherent DMA memory, however the ++ * DMA controller may still have some unsynchronized data in the FIFO. ++ * Issue a flush in the handlers to ensure that the driver sees ++ * the update. ++ */ ++static void ar71xx_ip2_handler(void) ++{ ++ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_PCI); ++ do_IRQ(AR71XX_CPU_IRQ_IP2); ++} ++ ++static void ar724x_ip2_handler(void) ++{ ++ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE); ++ do_IRQ(AR71XX_CPU_IRQ_IP2); ++} ++ ++static void ar913x_ip2_handler(void) ++{ ++ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC); ++ do_IRQ(AR71XX_CPU_IRQ_IP2); ++} ++ ++static void ar933x_ip2_handler(void) ++{ ++ ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC); ++ do_IRQ(AR71XX_CPU_IRQ_IP2); ++} ++ ++static void ar934x_ip2_handler(void) ++{ ++ ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_PCIE); ++ do_IRQ(AR71XX_CPU_IRQ_IP2); ++} ++ ++static void ar71xx_ip3_handler(void) ++{ ++ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_USB); ++ do_IRQ(AR71XX_CPU_IRQ_USB); ++} ++ ++static void ar724x_ip3_handler(void) ++{ ++ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_USB); ++ do_IRQ(AR71XX_CPU_IRQ_USB); ++} ++ ++static void ar913x_ip3_handler(void) ++{ ++ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_USB); ++ do_IRQ(AR71XX_CPU_IRQ_USB); ++} ++ ++static void ar933x_ip3_handler(void) ++{ ++ ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_USB); ++ do_IRQ(AR71XX_CPU_IRQ_USB); ++} ++ ++static void ar934x_ip3_handler(void) ++{ ++ do_IRQ(AR71XX_CPU_IRQ_USB); ++} ++ ++static void (*ip2_handler)(void); ++static void (*ip3_handler)(void); ++ ++asmlinkage void plat_irq_dispatch(void) ++{ ++ unsigned long pending; ++ ++ pending = read_c0_status() & read_c0_cause() & ST0_IM; ++ ++ if (pending & STATUSF_IP7) ++ do_IRQ(AR71XX_CPU_IRQ_TIMER); ++ ++ else if (pending & STATUSF_IP2) ++ ip2_handler(); ++ ++ else if (pending & STATUSF_IP4) ++ do_IRQ(AR71XX_CPU_IRQ_GE0); ++ ++ else if (pending & STATUSF_IP5) ++ do_IRQ(AR71XX_CPU_IRQ_GE1); ++ ++ else if (pending & STATUSF_IP3) ++ ip3_handler(); ++ ++ else if (pending & STATUSF_IP6) ++ ar71xx_misc_irq_dispatch(); ++ ++ spurious_interrupt(); ++} ++ ++void __init arch_init_irq(void) ++{ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ ip2_handler = ar71xx_ip2_handler; ++ ip3_handler = ar71xx_ip3_handler; ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ip2_handler = ar724x_ip2_handler; ++ ip3_handler = ar724x_ip3_handler; ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ ip2_handler = ar913x_ip2_handler; ++ ip3_handler = ar913x_ip3_handler; ++ break; ++ ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ ip2_handler = ar933x_ip2_handler; ++ ip3_handler = ar933x_ip3_handler; ++ break; ++ ++ case AR71XX_SOC_AR9341: ++ case AR71XX_SOC_AR9342: ++ case AR71XX_SOC_AR9344: ++ ip2_handler = ar934x_ip2_handler; ++ ip3_handler = ar934x_ip3_handler; ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ mips_cpu_irq_init(); ++ ++ ar71xx_misc_irq_init(); ++ ++ cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC; ++ ++ ar71xx_gpio_irq_init(); ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-ap121.c linux-2.6.39/arch/mips/ar71xx/mach-ap121.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-ap121.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-ap121.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,245 @@ ++/* ++ * Atheros AP121 board support ++ * ++ * Copyright (C) 2011 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-m25p80.h" ++#include "dev-usb.h" ++ ++#define AP121_GPIO_LED_WLAN 0 ++#define AP121_GPIO_LED_USB 1 ++ ++#define AP121_GPIO_BTN_JUMPSTART 11 ++#define AP121_GPIO_BTN_RESET 12 ++ ++#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL) ++ ++#define AP121_MAC0_OFFSET 0x0000 ++#define AP121_MAC1_OFFSET 0x0006 ++#define AP121_CALDATA_OFFSET 0x1000 ++#define AP121_WMAC_MAC_OFFSET 0x1002 ++ ++#define AP121_MINI_GPIO_LED_WLAN 0 ++#define AP121_MINI_GPIO_BTN_JUMPSTART 12 ++#define AP121_MINI_GPIO_BTN_RESET 11 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition ap121_parts[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, ++ { ++ .name = "rootfs", ++ .offset = 0x010000, ++ .size = 0x130000, ++ }, ++ { ++ .name = "uImage", ++ .offset = 0x140000, ++ .size = 0x0a0000, ++ }, ++ { ++ .name = "NVRAM", ++ .offset = 0x1e0000, ++ .size = 0x010000, ++ }, ++ { ++ .name = "ART", ++ .offset = 0x1f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, ++}; ++#define ap121_nr_parts ARRAY_SIZE(ap121_parts) ++ ++static struct mtd_partition ap121_mini_parts[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, ++ { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, ++ { ++ .name = "rootfs", ++ .offset = 0x050000, ++ .size = 0x2b0000, ++ }, ++ { ++ .name = "uImage", ++ .offset = 0x300000, ++ .size = 0x0e0000, ++ }, ++ { ++ .name = "NVRAM", ++ .offset = 0x3e0000, ++ .size = 0x010000, ++ }, ++ { ++ .name = "ART", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, ++}; ++ ++#define ap121_mini_nr_parts ARRAY_SIZE(ap121_parts) ++ ++#else ++#define ap121_parts NULL ++#define ap121_nr_parts 0 ++#define ap121_mini_parts NULL ++#define ap121_mini_nr_parts 0 ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data ap121_flash_data = { ++ .parts = ap121_parts, ++ .nr_parts = ap121_nr_parts, ++}; ++ ++static struct gpio_led ap121_leds_gpio[] __initdata = { ++ { ++ .name = "ap121:green:usb", ++ .gpio = AP121_GPIO_LED_USB, ++ .active_low = 0, ++ }, ++ { ++ .name = "ap121:green:wlan", ++ .gpio = AP121_GPIO_LED_WLAN, ++ .active_low = 0, ++ }, ++}; ++ ++static struct gpio_keys_button ap121_gpio_keys[] __initdata = { ++ { ++ .desc = "jumpstart button", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP121_GPIO_BTN_JUMPSTART, ++ .active_low = 1, ++ }, ++ { ++ .desc = "reset button", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP121_GPIO_BTN_RESET, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_led ap121_mini_leds_gpio[] __initdata = { ++ { ++ .name = "ap121:green:wlan", ++ .gpio = AP121_MINI_GPIO_LED_WLAN, ++ .active_low = 0, ++ }, ++}; ++ ++static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = { ++ { ++ .desc = "jumpstart button", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP121_MINI_GPIO_BTN_JUMPSTART, ++ .active_low = 1, ++ }, ++ { ++ .desc = "reset button", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP121_MINI_GPIO_BTN_RESET, ++ .active_low = 1, ++ } ++}; ++ ++static void __init ap121_common_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ar71xx_add_device_m25p80(&ap121_flash_data); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0); ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0); ++ ++ /* WAN port */ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.phy_mask = BIT(4); ++ ++ /* LAN ports */ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ar71xx_eth1_data.has_ar7240_switch = 1; ++ ++ ar71xx_add_device_mdio(0x0); ++ ar71xx_add_device_eth(1); ++ ar71xx_add_device_eth(0); ++ ++ ar9xxx_add_device_wmac(art + AP121_CALDATA_OFFSET, ++ art + AP121_WMAC_MAC_OFFSET); ++} ++ ++static void __init ap121_setup(void) ++{ ++ ap121_flash_data.parts = ap121_parts; ++ ap121_flash_data.nr_parts = ap121_nr_parts; ++ ++ ap121_common_setup(); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio), ++ ap121_leds_gpio); ++ ar71xx_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ap121_gpio_keys), ++ ap121_gpio_keys); ++ ++ ar71xx_add_device_usb(); ++} ++ ++static void __init ap121_mini_setup(void) ++{ ++ ap121_flash_data.parts = ap121_mini_parts; ++ ap121_flash_data.nr_parts = ap121_mini_nr_parts; ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio), ++ ap121_mini_leds_gpio); ++ ar71xx_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ap121_mini_gpio_keys), ++ ap121_mini_gpio_keys); ++ ++ ap121_common_setup(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_AP121, "AP121", "Atheros AP121", ++ ap121_setup); ++ ++MIPS_MACHINE(AR71XX_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI", ++ ap121_mini_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-ap81.c linux-2.6.39/arch/mips/ar71xx/mach-ap81.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-ap81.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-ap81.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,142 @@ ++/* ++ * Atheros AP81 board support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * Copyright (C) 2009 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++ ++#define AP81_GPIO_LED_STATUS 1 ++#define AP81_GPIO_LED_AOSS 3 ++#define AP81_GPIO_LED_WLAN 6 ++#define AP81_GPIO_LED_POWER 14 ++ ++#define AP81_GPIO_BTN_SW4 12 ++#define AP81_GPIO_BTN_SW1 21 ++ ++#define AP81_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define AP81_KEYS_DEBOUNCE_INTERVAL (3 * AP81_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition ap81_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x050000, ++ .size = 0x500000, ++ }, { ++ .name = "uImage", ++ .offset = 0x550000, ++ .size = 0x100000, ++ }, { ++ .name = "ART", ++ .offset = 0x650000, ++ .size = 0x1b0000, ++ .mask_flags = MTD_WRITEABLE, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data ap81_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = ap81_partitions, ++ .nr_parts = ARRAY_SIZE(ap81_partitions), ++#endif ++}; ++ ++static struct gpio_led ap81_leds_gpio[] __initdata = { ++ { ++ .name = "ap81:green:status", ++ .gpio = AP81_GPIO_LED_STATUS, ++ .active_low = 1, ++ }, { ++ .name = "ap81:amber:aoss", ++ .gpio = AP81_GPIO_LED_AOSS, ++ .active_low = 1, ++ }, { ++ .name = "ap81:green:wlan", ++ .gpio = AP81_GPIO_LED_WLAN, ++ .active_low = 1, ++ }, { ++ .name = "ap81:green:power", ++ .gpio = AP81_GPIO_LED_POWER, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button ap81_gpio_keys[] __initdata = { ++ { ++ .desc = "sw1", ++ .type = EV_KEY, ++ .code = BTN_0, ++ .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP81_GPIO_BTN_SW1, ++ .active_low = 1, ++ }, { ++ .desc = "sw4", ++ .type = EV_KEY, ++ .code = BTN_1, ++ .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP81_GPIO_BTN_SW4, ++ .active_low = 1, ++ } ++}; ++ ++static void __init ap81_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ar71xx_add_device_mdio(0x0); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.has_ar8216 = 1; ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = 0x10; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_usb(); ++ ++ ar71xx_add_device_m25p80(&ap81_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), ++ ap81_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ap81_gpio_keys), ++ ap81_gpio_keys); ++ ++ ar9xxx_add_device_wmac(eeprom, NULL); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_AP81, "AP81", "Atheros AP81", ap81_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-ap83.c linux-2.6.39/arch/mips/ar71xx/mach-ap83.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-ap83.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-ap83.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,267 @@ ++/* ++ * Atheros AP83 board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++ ++#define AP83_GPIO_LED_WLAN 6 ++#define AP83_GPIO_LED_POWER 14 ++#define AP83_GPIO_LED_JUMPSTART 15 ++#define AP83_GPIO_BTN_JUMPSTART 12 ++#define AP83_GPIO_BTN_RESET 21 ++ ++#define AP83_050_GPIO_VSC7385_CS 1 ++#define AP83_050_GPIO_VSC7385_MISO 3 ++#define AP83_050_GPIO_VSC7385_MOSI 16 ++#define AP83_050_GPIO_VSC7385_SCK 17 ++ ++#define AP83_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define AP83_KEYS_DEBOUNCE_INTERVAL (3 * AP83_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition ap83_flash_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = 0x060000, ++ .size = 0x140000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x1a0000, ++ .size = 0x650000, ++ }, { ++ .name = "art", ++ .offset = 0x7f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x060000, ++ .size = 0x790000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct ar91xx_flash_platform_data ap83_flash_data = { ++ .width = 2, ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = ap83_flash_partitions, ++ .nr_parts = ARRAY_SIZE(ap83_flash_partitions), ++#endif ++}; ++ ++static struct resource ap83_flash_resources[] = { ++ [0] = { ++ .start = AR71XX_SPI_BASE, ++ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static struct platform_device ap83_flash_device = { ++ .name = "ar91xx-flash", ++ .id = -1, ++ .resource = ap83_flash_resources, ++ .num_resources = ARRAY_SIZE(ap83_flash_resources), ++ .dev = { ++ .platform_data = &ap83_flash_data, ++ } ++}; ++ ++static struct gpio_led ap83_leds_gpio[] __initdata = { ++ { ++ .name = "ap83:green:jumpstart", ++ .gpio = AP83_GPIO_LED_JUMPSTART, ++ .active_low = 0, ++ }, { ++ .name = "ap83:green:power", ++ .gpio = AP83_GPIO_LED_POWER, ++ .active_low = 0, ++ }, { ++ .name = "ap83:green:wlan", ++ .gpio = AP83_GPIO_LED_WLAN, ++ .active_low = 0, ++ }, ++}; ++ ++static struct gpio_keys_button ap83_gpio_keys[] __initdata = { ++ { ++ .desc = "soft_reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP83_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "jumpstart", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP83_GPIO_BTN_JUMPSTART, ++ .active_low = 1, ++ } ++}; ++ ++static struct resource ap83_040_spi_resources[] = { ++ [0] = { ++ .start = AR71XX_SPI_BASE, ++ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static struct platform_device ap83_040_spi_device = { ++ .name = "ap83-spi", ++ .id = 0, ++ .resource = ap83_040_spi_resources, ++ .num_resources = ARRAY_SIZE(ap83_040_spi_resources), ++}; ++ ++static struct spi_gpio_platform_data ap83_050_spi_data = { ++ .miso = AP83_050_GPIO_VSC7385_MISO, ++ .mosi = AP83_050_GPIO_VSC7385_MOSI, ++ .sck = AP83_050_GPIO_VSC7385_SCK, ++ .num_chipselect = 1, ++}; ++ ++static struct platform_device ap83_050_spi_device = { ++ .name = "spi_gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &ap83_050_spi_data, ++ } ++}; ++ ++static void ap83_vsc7385_reset(void) ++{ ++ ar71xx_device_stop(RESET_MODULE_GE1_PHY); ++ udelay(10); ++ ar71xx_device_start(RESET_MODULE_GE1_PHY); ++ mdelay(50); ++} ++ ++static struct vsc7385_platform_data ap83_vsc7385_data = { ++ .reset = ap83_vsc7385_reset, ++ .ucode_name = "vsc7385_ucode_ap83.bin", ++ .mac_cfg = { ++ .tx_ipg = 6, ++ .bit2 = 0, ++ .clk_sel = 3, ++ }, ++}; ++ ++static struct spi_board_info ap83_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "spi-vsc7385", ++ .platform_data = &ap83_vsc7385_data, ++ .controller_data = (void *) AP83_050_GPIO_VSC7385_CS, ++ } ++}; ++ ++static void __init ap83_generic_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ar71xx_add_device_mdio(0xfffffffe); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.phy_mask = 0x1; ++ ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_eth1_pll_data.pll_1000 = 0x1f000000; ++ ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio), ++ ap83_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, AP83_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ap83_gpio_keys), ++ ap83_gpio_keys); ++ ++ ar71xx_add_device_usb(); ++ ++ ar9xxx_add_device_wmac(eeprom, NULL); ++ ++ platform_device_register(&ap83_flash_device); ++ ++ spi_register_board_info(ap83_spi_info, ARRAY_SIZE(ap83_spi_info)); ++} ++ ++static void __init ap83_040_setup(void) ++{ ++ ap83_flash_data.is_shared = 1; ++ ap83_generic_setup(); ++ platform_device_register(&ap83_040_spi_device); ++} ++ ++static void __init ap83_050_setup(void) ++{ ++ ap83_generic_setup(); ++ platform_device_register(&ap83_050_spi_device); ++} ++ ++static void __init ap83_setup(void) ++{ ++ u8 *board_id = (u8 *) KSEG1ADDR(0x1fff1244); ++ unsigned int board_version; ++ ++ board_version = (unsigned int)(board_id[0] - '0'); ++ board_version += ((unsigned int)(board_id[1] - '0')) * 10; ++ ++ switch (board_version) { ++ case 40: ++ ap83_040_setup(); ++ break; ++ case 50: ++ ap83_050_setup(); ++ break; ++ default: ++ printk(KERN_WARNING "AP83-%03u board is not yet supported\n", ++ board_version); ++ } ++} ++ ++MIPS_MACHINE(AR71XX_MACH_AP83, "AP83", "Atheros AP83", ap83_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-ap96.c linux-2.6.39/arch/mips/ar71xx/mach-ap96.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-ap96.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-ap96.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,180 @@ ++/* ++ * Atheros AP96 board support ++ * ++ * Copyright (C) 2009 Marco Porsch ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * Copyright (C) 2010 Atheros Communications ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap94-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++ ++#define AP96_GPIO_LED_12_GREEN 0 ++#define AP96_GPIO_LED_3_GREEN 1 ++#define AP96_GPIO_LED_2_GREEN 2 ++#define AP96_GPIO_LED_WPS_GREEN 4 ++#define AP96_GPIO_LED_5_GREEN 5 ++#define AP96_GPIO_LED_4_ORANGE 6 ++ ++/* Reset button - next to the power connector */ ++#define AP96_GPIO_BTN_RESET 3 ++/* WPS button - next to a led on right */ ++#define AP96_GPIO_BTN_WPS 8 ++ ++#define AP96_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define AP96_KEYS_DEBOUNCE_INTERVAL (3 * AP96_KEYS_POLL_INTERVAL) ++ ++#define AP96_WMAC0_MAC_OFFSET 0x120c ++#define AP96_WMAC1_MAC_OFFSET 0x520c ++#define AP96_CALDATA0_OFFSET 0x1000 ++#define AP96_CALDATA1_OFFSET 0x5000 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition ap96_partitions[] = { ++ { ++ .name = "uboot", ++ .offset = 0, ++ .size = 0x030000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "env", ++ .offset = 0x030000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "rootfs", ++ .offset = 0x040000, ++ .size = 0x600000, ++ }, { ++ .name = "uImage", ++ .offset = 0x640000, ++ .size = 0x1b0000, ++ }, { ++ .name = "caldata", ++ .offset = 0x7f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data ap96_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = ap96_partitions, ++ .nr_parts = ARRAY_SIZE(ap96_partitions), ++#endif ++}; ++ ++/* ++ * AP96 has 12 unlabeled leds in the front; these are numbered from 1 to 12 ++ * below (from left to right on the board). Led 1 seems to be on whenever the ++ * board is powered. Led 11 shows LAN link activity actity. Led 3 is orange; ++ * others are green. ++ * ++ * In addition, there is one led next to a button on the right side for WPS. ++ */ ++static struct gpio_led ap96_leds_gpio[] __initdata = { ++ { ++ .name = "ap96:green:led2", ++ .gpio = AP96_GPIO_LED_2_GREEN, ++ .active_low = 1, ++ }, { ++ .name = "ap96:green:led3", ++ .gpio = AP96_GPIO_LED_3_GREEN, ++ .active_low = 1, ++ }, { ++ .name = "ap96:orange:led4", ++ .gpio = AP96_GPIO_LED_4_ORANGE, ++ .active_low = 1, ++ }, { ++ .name = "ap96:green:led5", ++ .gpio = AP96_GPIO_LED_5_GREEN, ++ .active_low = 1, ++ }, { ++ .name = "ap96:green:led12", ++ .gpio = AP96_GPIO_LED_12_GREEN, ++ .active_low = 1, ++ }, { /* next to a button on right */ ++ .name = "ap96:green:wps", ++ .gpio = AP96_GPIO_LED_WPS_GREEN, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button ap96_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP96_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP96_GPIO_BTN_WPS, ++ .active_low = 1, ++ } ++}; ++ ++#define AP96_WAN_PHYMASK 0x10 ++#define AP96_LAN_PHYMASK 0x0f ++ ++static void __init ap96_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ar71xx_add_device_mdio(~(AP96_WAN_PHYMASK | AP96_LAN_PHYMASK)); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, art, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.phy_mask = AP96_LAN_PHYMASK; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, art, 1); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.phy_mask = AP96_WAN_PHYMASK; ++ ++ ar71xx_eth1_pll_data.pll_1000 = 0x1f000000; ++ ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_usb(); ++ ++ ar71xx_add_device_m25p80(&ap96_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap96_leds_gpio), ++ ap96_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, AP96_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ap96_gpio_keys), ++ ap96_gpio_keys); ++ ++ ap94_pci_init(art + AP96_CALDATA0_OFFSET, ++ art + AP96_WMAC0_MAC_OFFSET, ++ art + AP96_CALDATA1_OFFSET, ++ art + AP96_WMAC1_MAC_OFFSET); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_AP96, "AP96", "Atheros AP96", ap96_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-aw-nr580.c linux-2.6.39/arch/mips/ar71xx/mach-aw-nr580.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-aw-nr580.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-aw-nr580.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,102 @@ ++/* ++ * AzureWave AW-NR580 board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-pb42-pci.h" ++#include "dev-leds-gpio.h" ++ ++#define AW_NR580_GPIO_LED_READY_RED 0 ++#define AW_NR580_GPIO_LED_WLAN 1 ++#define AW_NR580_GPIO_LED_READY_GREEN 2 ++#define AW_NR580_GPIO_LED_WPS_GREEN 4 ++#define AW_NR580_GPIO_LED_WPS_AMBER 5 ++ ++#define AW_NR580_GPIO_BTN_WPS 3 ++#define AW_NR580_GPIO_BTN_RESET 11 ++ ++#define AW_NR580_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define AW_NR580_KEYS_DEBOUNCE_INTERVAL (3 * AW_NR580_KEYS_POLL_INTERVAL) ++ ++static struct gpio_led aw_nr580_leds_gpio[] __initdata = { ++ { ++ .name = "aw-nr580:red:ready", ++ .gpio = AW_NR580_GPIO_LED_READY_RED, ++ .active_low = 0, ++ }, { ++ .name = "aw-nr580:green:ready", ++ .gpio = AW_NR580_GPIO_LED_READY_GREEN, ++ .active_low = 0, ++ }, { ++ .name = "aw-nr580:green:wps", ++ .gpio = AW_NR580_GPIO_LED_WPS_GREEN, ++ .active_low = 0, ++ }, { ++ .name = "aw-nr580:amber:wps", ++ .gpio = AW_NR580_GPIO_LED_WPS_AMBER, ++ .active_low = 0, ++ }, { ++ .name = "aw-nr580:green:wlan", ++ .gpio = AW_NR580_GPIO_LED_WLAN, ++ .active_low = 0, ++ } ++}; ++ ++static struct gpio_keys_button aw_nr580_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AW_NR580_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AW_NR580_GPIO_BTN_WPS, ++ .active_low = 1, ++ } ++}; ++ ++static void __init aw_nr580_setup(void) ++{ ++ ar71xx_add_device_mdio(0x0); ++ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_eth(0); ++ ++ pb42_pci_init(); ++ ++ ar71xx_add_device_m25p80(NULL); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(aw_nr580_leds_gpio), ++ aw_nr580_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, AW_NR580_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(aw_nr580_gpio_keys), ++ aw_nr580_gpio_keys); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_AW_NR580, "AW-NR580", "AzureWave AW-NR580", ++ aw_nr580_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-db120.c linux-2.6.39/arch/mips/ar71xx/mach-db120.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-db120.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-db120.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,134 @@ ++/* ++ * Atheros DB120 board (WASP SoC) support ++ * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-db120-pci.h" ++ ++#define DB120_GPIO_LED_USB 11 ++#define DB120_GPIO_LED_WLAN_5G 12 ++#define DB120_GPIO_LED_WLAN_2G 13 ++#define DB120_GPIO_LED_STATUS 14 ++#define DB120_GPIO_LED_WPS 15 ++ ++#define DB120_GPIO_BTN_SW1 16 ++ ++#define DB120_CALDATA_OFFSET 0x1000 ++#define DB120_WMAC_MAC_OFFSET 0x1002 ++ ++#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition db120_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x050000, ++ .size = 0x630000, ++ }, { ++ .name = "uImage", ++ .offset = 0x680000, ++ .size = 0x160000, ++ }, { ++ .name = "NVRAM", ++ .offset = 0x7E0000, ++ .size = 0x010000, ++ }, { ++ .name = "ART", ++ .offset = 0x7F0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data db120_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = db120_partitions, ++ .nr_parts = ARRAY_SIZE(db120_partitions), ++#endif ++}; ++ ++static struct gpio_led db120_leds_gpio[] __initdata = { ++ { ++ .name = "db120:green:status", ++ .gpio = DB120_GPIO_LED_STATUS, ++ .active_low = 1, ++ }, { ++ .name = "db120:green:wps", ++ .gpio = DB120_GPIO_LED_WPS, ++ .active_low = 1, ++ }, { ++ .name = "db120:green:wlan-5g", ++ .gpio = DB120_GPIO_LED_WLAN_5G, ++ .active_low = 1, ++ }, { ++ .name = "db120:green:wlan-2g", ++ .gpio = DB120_GPIO_LED_WLAN_2G, ++ .active_low = 1, ++ }, { ++ .name = "db120:green:usb", ++ .gpio = DB120_GPIO_LED_USB, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button db120_gpio_keys[] __initdata = { ++ { ++ .desc = "sw1", ++ .type = EV_KEY, ++ .code = BTN_0, ++ .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = DB120_GPIO_BTN_SW1, ++ .active_low = 1, ++ } ++}; ++ ++static void __init db120_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ar71xx_add_device_usb(); ++ ++ ar71xx_add_device_m25p80(&db120_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), ++ db120_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(db120_gpio_keys), ++ db120_gpio_keys); ++ ++ ar9xxx_add_device_wmac(art + DB120_CALDATA_OFFSET, ++ art + DB120_WMAC_MAC_OFFSET); ++ ++ db120_pci_init(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_DB120, "DB120", "Atheros DB120", db120_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-dir-600-a1.c linux-2.6.39/arch/mips/ar71xx/mach-dir-600-a1.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-dir-600-a1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-dir-600-a1.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,159 @@ ++/* ++ * D-Link DIR-600 rev. A1 board support ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap91-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "nvram.h" ++ ++#define DIR_600_A1_GPIO_LED_WPS 0 ++#define DIR_600_A1_GPIO_LED_POWER_AMBER 1 ++#define DIR_600_A1_GPIO_LED_POWER_GREEN 6 ++ ++#define DIR_600_A1_GPIO_BTN_RESET 8 ++#define DIR_600_A1_GPIO_BTN_WPS 12 ++ ++#define DIR_600_A1_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define DIR_600_A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_600_A1_KEYS_POLL_INTERVAL) ++ ++#define DIR_600_A1_NVRAM_ADDR 0x1f030000 ++#define DIR_600_A1_NVRAM_SIZE 0x10000 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition dir_600_a1_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x030000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "nvram", ++ .offset = 0x030000, ++ .size = 0x010000, ++ }, { ++ .name = "kernel", ++ .offset = 0x040000, ++ .size = 0x0e0000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x120000, ++ .size = 0x2c0000, ++ }, { ++ .name = "mac", ++ .offset = 0x3e0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x040000, ++ .size = 0x3a0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data dir_600_a1_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = dir_600_a1_partitions, ++ .nr_parts = ARRAY_SIZE(dir_600_a1_partitions), ++#endif ++}; ++ ++static struct gpio_led dir_600_a1_leds_gpio[] __initdata = { ++ { ++ .name = "dir-600-a1:green:power", ++ .gpio = DIR_600_A1_GPIO_LED_POWER_GREEN, ++ }, { ++ .name = "dir-600-a1:amber:power", ++ .gpio = DIR_600_A1_GPIO_LED_POWER_AMBER, ++ }, { ++ .name = "dir-600-a1:blue:wps", ++ .gpio = DIR_600_A1_GPIO_LED_WPS, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button dir_600_a1_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = DIR_600_A1_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = DIR_600_A1_GPIO_BTN_WPS, ++ .active_low = 1, ++ } ++}; ++ ++static void __init dir_600_a1_setup(void) ++{ ++ const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ u8 mac_buff[6]; ++ u8 *mac = NULL; ++ ++ if (nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE, ++ "lan_mac=", mac_buff) == 0) { ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac_buff, 0); ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac_buff, 1); ++ mac = mac_buff; ++ } ++ ++ ar71xx_add_device_m25p80(&dir_600_a1_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio), ++ dir_600_a1_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, DIR_600_A1_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(dir_600_a1_gpio_keys), ++ dir_600_a1_gpio_keys); ++ ++ ar71xx_eth1_data.has_ar7240_switch = 1; ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); ++ ++ /* WAN port */ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.phy_mask = BIT(4); ++ ++ /* LAN ports */ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_mdio(0x0); ++ ar71xx_add_device_eth(1); ++ ar71xx_add_device_eth(0); ++ ++ ap91_pci_init(ee, mac); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_DIR_600_A1, "DIR-600-A1", "D-Link DIR-600 rev. A1", ++ dir_600_a1_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-dir-615-c1.c linux-2.6.39/arch/mips/ar71xx/mach-dir-615-c1.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-dir-615-c1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-dir-615-c1.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,175 @@ ++/* ++ * D-Link DIR-615 rev C1 board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "nvram.h" ++ ++#define DIR_615C1_GPIO_LED_ORANGE_STATUS 1 /* ORANGE:STATUS:TRICOLOR */ ++#define DIR_615C1_GPIO_LED_BLUE_WPS 3 /* BLUE:WPS */ ++#define DIR_615C1_GPIO_LED_GREEN_WAN 4 /* GREEN:WAN:TRICOLOR */ ++#define DIR_615C1_GPIO_LED_GREEN_WANCPU 5 /* GREEN:WAN:CPU:TRICOLOR */ ++#define DIR_615C1_GPIO_LED_GREEN_WLAN 6 /* GREEN:WLAN */ ++#define DIR_615C1_GPIO_LED_GREEN_STATUS 14 /* GREEN:STATUS:TRICOLOR */ ++#define DIR_615C1_GPIO_LED_ORANGE_WAN 15 /* ORANGE:WAN:TRICOLOR */ ++ ++/* buttons may need refinement */ ++ ++#define DIR_615C1_GPIO_BTN_WPS 12 ++#define DIR_615C1_GPIO_BTN_RESET 21 ++ ++#define DIR_615C1_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define DIR_615C1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615C1_KEYS_POLL_INTERVAL) ++ ++#define DIR_615C1_CONFIG_ADDR 0x1f020000 ++#define DIR_615C1_CONFIG_SIZE 0x10000 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition dir_615c1_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "config", ++ .offset = 0x020000, ++ .size = 0x010000, ++ }, { ++ .name = "kernel", ++ .offset = 0x030000, ++ .size = 0x0e0000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x110000, ++ .size = 0x2e0000, ++ }, { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x030000, ++ .size = 0x3c0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data dir_615c1_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = dir_615c1_partitions, ++ .nr_parts = ARRAY_SIZE(dir_615c1_partitions), ++#endif ++}; ++ ++static struct gpio_led dir_615c1_leds_gpio[] __initdata = { ++ { ++ .name = "dir-615c1:orange:status", ++ .gpio = DIR_615C1_GPIO_LED_ORANGE_STATUS, ++ .active_low = 1, ++ }, { ++ .name = "dir-615c1:blue:wps", ++ .gpio = DIR_615C1_GPIO_LED_BLUE_WPS, ++ .active_low = 1, ++ }, { ++ .name = "dir-615c1:green:wan", ++ .gpio = DIR_615C1_GPIO_LED_GREEN_WAN, ++ .active_low = 1, ++ }, { ++ .name = "dir-615c1:green:wancpu", ++ .gpio = DIR_615C1_GPIO_LED_GREEN_WANCPU, ++ .active_low = 1, ++ }, { ++ .name = "dir-615c1:green:wlan", ++ .gpio = DIR_615C1_GPIO_LED_GREEN_WLAN, ++ .active_low = 1, ++ }, { ++ .name = "dir-615c1:green:status", ++ .gpio = DIR_615C1_GPIO_LED_GREEN_STATUS, ++ .active_low = 1, ++ }, { ++ .name = "dir-615c1:orange:wan", ++ .gpio = DIR_615C1_GPIO_LED_ORANGE_WAN, ++ .active_low = 1, ++ } ++ ++}; ++ ++static struct gpio_keys_button dir_615c1_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = DIR_615C1_GPIO_BTN_RESET, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = DIR_615C1_GPIO_BTN_WPS, ++ } ++}; ++ ++#define DIR_615C1_LAN_PHYMASK BIT(0) ++#define DIR_615C1_WAN_PHYMASK BIT(4) ++#define DIR_615C1_MDIO_MASK (~(DIR_615C1_LAN_PHYMASK | \ ++ DIR_615C1_WAN_PHYMASK)) ++ ++static void __init dir_615c1_setup(void) ++{ ++ const char *config = (char *) KSEG1ADDR(DIR_615C1_CONFIG_ADDR); ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ u8 mac[6]; ++ u8 *wlan_mac = NULL; ++ ++ if (nvram_parse_mac_addr(config, DIR_615C1_CONFIG_SIZE, ++ "lan_mac=", mac) == 0) { ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); ++ wlan_mac = mac; ++ } ++ ++ ar71xx_add_device_mdio(DIR_615C1_MDIO_MASK); ++ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.phy_mask = DIR_615C1_LAN_PHYMASK; ++ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = DIR_615C1_WAN_PHYMASK; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_m25p80(&dir_615c1_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_615c1_leds_gpio), ++ dir_615c1_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, DIR_615C1_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(dir_615c1_gpio_keys), ++ dir_615c1_gpio_keys); ++ ++ ar9xxx_add_device_wmac(eeprom, wlan_mac); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_DIR_615_C1, "DIR-615-C1", "D-Link DIR-615 rev. C1", ++ dir_615c1_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-dir-825-b1.c linux-2.6.39/arch/mips/ar71xx/mach-dir-825-b1.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-dir-825-b1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-dir-825-b1.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,198 @@ ++/* ++ * D-Link DIR-825 rev. B1 board support ++ * ++ * Copyright (C) 2009 Lukas Kuna, Evkanet, s.r.o. ++ * ++ * based on mach-wndr3700.c ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap94-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++ ++#define DIR825B1_GPIO_LED_BLUE_USB 0 ++#define DIR825B1_GPIO_LED_ORANGE_POWER 1 ++#define DIR825B1_GPIO_LED_BLUE_POWER 2 ++#define DIR825B1_GPIO_LED_BLUE_WPS 4 ++#define DIR825B1_GPIO_LED_ORANGE_PLANET 6 ++#define DIR825B1_GPIO_LED_BLUE_PLANET 11 ++ ++#define DIR825B1_GPIO_BTN_RESET 3 ++#define DIR825B1_GPIO_BTN_WPS 8 ++ ++#define DIR825B1_GPIO_RTL8366_SDA 5 ++#define DIR825B1_GPIO_RTL8366_SCK 7 ++ ++#define DIR825B1_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define DIR825B1_KEYS_DEBOUNCE_INTERVAL (3 * DIR825B1_KEYS_POLL_INTERVAL) ++ ++#define DIR825B1_CAL_LOCATION_0 0x1f661000 ++#define DIR825B1_CAL_LOCATION_1 0x1f665000 ++ ++#define DIR825B1_MAC_LOCATION_0 0x2ffa81b8 ++#define DIR825B1_MAC_LOCATION_1 0x2ffa8370 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition dir825b1_partitions[] = { ++ { ++ .name = "uboot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "config", ++ .offset = 0x040000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x050000, ++ .size = 0x610000, ++ }, { ++ .name = "caldata", ++ .offset = 0x660000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "unknown", ++ .offset = 0x670000, ++ .size = 0x190000, ++ .mask_flags = MTD_WRITEABLE, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data dir825b1_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = dir825b1_partitions, ++ .nr_parts = ARRAY_SIZE(dir825b1_partitions), ++#endif ++}; ++ ++static struct gpio_led dir825b1_leds_gpio[] __initdata = { ++ { ++ .name = "dir825b1:blue:usb", ++ .gpio = DIR825B1_GPIO_LED_BLUE_USB, ++ .active_low = 1, ++ }, { ++ .name = "dir825b1:orange:power", ++ .gpio = DIR825B1_GPIO_LED_ORANGE_POWER, ++ .active_low = 1, ++ }, { ++ .name = "dir825b1:blue:power", ++ .gpio = DIR825B1_GPIO_LED_BLUE_POWER, ++ .active_low = 1, ++ }, { ++ .name = "dir825b1:blue:wps", ++ .gpio = DIR825B1_GPIO_LED_BLUE_WPS, ++ .active_low = 1, ++ }, { ++ .name = "dir825b1:orange:planet", ++ .gpio = DIR825B1_GPIO_LED_ORANGE_PLANET, ++ .active_low = 1, ++ }, { ++ .name = "dir825b1:blue:planet", ++ .gpio = DIR825B1_GPIO_LED_BLUE_PLANET, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button dir825b1_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = DIR825B1_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = DIR825B1_GPIO_BTN_WPS, ++ .active_low = 1, ++ } ++}; ++ ++static struct rtl8366_initval dir825b1_rtl8366s_initvals[] = { ++ { .reg = 0x06, .val = 0x0108 }, ++}; ++ ++static struct rtl8366_platform_data dir825b1_rtl8366s_data = { ++ .gpio_sda = DIR825B1_GPIO_RTL8366_SDA, ++ .gpio_sck = DIR825B1_GPIO_RTL8366_SCK, ++ .num_initvals = ARRAY_SIZE(dir825b1_rtl8366s_initvals), ++ .initvals = dir825b1_rtl8366s_initvals, ++}; ++ ++static struct platform_device dir825b1_rtl8366s_device = { ++ .name = RTL8366S_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &dir825b1_rtl8366s_data, ++ } ++}; ++ ++static void __init dir825b1_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_1); ++ ++ ar71xx_add_device_mdio(0x0); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 1); ++ ar71xx_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_pll_data.pll_1000 = 0x11110000; ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 2); ++ ar71xx_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.phy_mask = 0x10; ++ ar71xx_eth1_pll_data.pll_1000 = 0x11110000; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_m25p80(&dir825b1_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio), ++ dir825b1_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, DIR825B1_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(dir825b1_gpio_keys), ++ dir825b1_gpio_keys); ++ ++ ar71xx_add_device_usb(); ++ ++ platform_device_register(&dir825b1_rtl8366s_device); ++ ++ ap94_pci_setup_wmac_led_pin(0, 5); ++ ap94_pci_setup_wmac_led_pin(1, 5); ++ ++ ap94_pci_init((u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0), ++ (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_0), ++ (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1), ++ (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_1)); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_DIR_825_B1, "DIR-825-B1", "D-Link DIR-825 rev. B1", ++ dir825b1_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-eap7660d.c linux-2.6.39/arch/mips/ar71xx/mach-eap7660d.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-eap7660d.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-eap7660d.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,180 @@ ++/* ++ * Senao EAP7660D board support ++ * ++ * Copyright (C) 2010 Daniel Golle ++ * Copyright (C) 2008 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-m25p80.h" ++ ++#define EAP7660D_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define EAP7660D_KEYS_DEBOUNCE_INTERVAL (3 * EAP7660D_KEYS_POLL_INTERVAL) ++ ++#define EAP7660D_GPIO_DS4 7 ++#define EAP7660D_GPIO_DS5 2 ++#define EAP7660D_GPIO_DS7 0 ++#define EAP7660D_GPIO_DS8 4 ++#define EAP7660D_GPIO_SW1 3 ++#define EAP7660D_GPIO_SW3 8 ++#define EAP7660D_PHYMASK BIT(20) ++#define EAP7660D_BOARDCONFIG 0x1F7F0000 ++#define EAP7660D_GBIC_MAC_OFFSET 0x1000 ++#define EAP7660D_WMAC0_MAC_OFFSET 0x1010 ++#define EAP7660D_WMAC1_MAC_OFFSET 0x1016 ++#define EAP7660D_WMAC0_CALDATA_OFFSET 0x2000 ++#define EAP7660D_WMAC1_CALDATA_OFFSET 0x3000 ++ ++static struct ath5k_platform_data eap7660d_wmac0_data; ++static struct ath5k_platform_data eap7660d_wmac1_data; ++static char eap7660d_wmac0_mac[6]; ++static char eap7660d_wmac1_mac[6]; ++static u16 eap7660d_wmac0_eeprom[ATH5K_PLAT_EEP_MAX_WORDS]; ++static u16 eap7660d_wmac1_eeprom[ATH5K_PLAT_EEP_MAX_WORDS]; ++ ++#ifdef CONFIG_PCI ++static struct ar71xx_pci_irq eap7660d_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ }, { ++ .slot = 1, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV1, ++ } ++}; ++ ++static int eap7660d_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ switch (PCI_SLOT(dev->devfn)) { ++ case 17: ++ dev->dev.platform_data = &eap7660d_wmac0_data; ++ break; ++ ++ case 18: ++ dev->dev.platform_data = &eap7660d_wmac1_data; ++ break; ++ } ++ ++ return 0; ++} ++ ++void __init eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0, ++ u8 *cal_data1, u8 *mac_addr1) ++{ ++ if (cal_data0 && *cal_data0 == 0xa55a) { ++ memcpy(eap7660d_wmac0_eeprom, cal_data0, ++ ATH5K_PLAT_EEP_MAX_WORDS); ++ eap7660d_wmac0_data.eeprom_data = eap7660d_wmac0_eeprom; ++ } ++ ++ if (cal_data1 && *cal_data1 == 0xa55a) { ++ memcpy(eap7660d_wmac1_eeprom, cal_data1, ++ ATH5K_PLAT_EEP_MAX_WORDS); ++ eap7660d_wmac1_data.eeprom_data = eap7660d_wmac1_eeprom; ++ } ++ ++ if (mac_addr0) { ++ memcpy(eap7660d_wmac0_mac, mac_addr0, ++ sizeof(eap7660d_wmac0_mac)); ++ eap7660d_wmac0_data.macaddr = eap7660d_wmac0_mac; ++ } ++ ++ if (mac_addr1) { ++ memcpy(eap7660d_wmac1_mac, mac_addr1, ++ sizeof(eap7660d_wmac1_mac)); ++ eap7660d_wmac1_data.macaddr = eap7660d_wmac1_mac; ++ } ++ ++ ar71xx_pci_plat_dev_init = eap7660d_pci_plat_dev_init; ++ ar71xx_pci_init(ARRAY_SIZE(eap7660d_pci_irqs), eap7660d_pci_irqs); ++} ++#else ++static inline void eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0, ++ u8 *cal_data1, u8 *mac_addr1) ++{ ++} ++#endif /* CONFIG_PCI */ ++ ++static struct gpio_led eap7660d_leds_gpio[] __initdata = { ++ { ++ .name = "eap7660d:green:ds8", ++ .gpio = EAP7660D_GPIO_DS8, ++ .active_low = 0, ++ }, ++ { ++ .name = "eap7660d:green:ds5", ++ .gpio = EAP7660D_GPIO_DS5, ++ .active_low = 0, ++ }, ++ { ++ .name = "eap7660d:green:ds7", ++ .gpio = EAP7660D_GPIO_DS7, ++ .active_low = 0, ++ }, ++ { ++ .name = "eap7660d:green:ds4", ++ .gpio = EAP7660D_GPIO_DS4, ++ .active_low = 0, ++ } ++}; ++ ++static struct gpio_keys_button eap7660d_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = EAP7660D_GPIO_SW1, ++ .active_low = 1, ++ }, ++ { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = EAP7660D_GPIO_SW3, ++ .active_low = 1, ++ } ++}; ++ ++static void __init eap7660d_setup(void) ++{ ++ u8 *boardconfig = (u8 *) KSEG1ADDR(EAP7660D_BOARDCONFIG); ++ ++ ar71xx_add_device_mdio(~EAP7660D_PHYMASK); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ++ boardconfig + EAP7660D_GBIC_MAC_OFFSET, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.phy_mask = EAP7660D_PHYMASK; ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_m25p80(NULL); ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(eap7660d_leds_gpio), ++ eap7660d_leds_gpio); ++ ar71xx_register_gpio_keys_polled(-1, EAP7660D_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(eap7660d_gpio_keys), ++ eap7660d_gpio_keys); ++ eap7660d_pci_init(boardconfig + EAP7660D_WMAC0_CALDATA_OFFSET, ++ boardconfig + EAP7660D_WMAC0_MAC_OFFSET, ++ boardconfig + EAP7660D_WMAC1_CALDATA_OFFSET, ++ boardconfig + EAP7660D_WMAC1_MAC_OFFSET); ++}; ++ ++MIPS_MACHINE(AR71XX_MACH_EAP7660D, "EAP7660D", "Senao EAP7660D", ++ eap7660d_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-ja76pf.c linux-2.6.39/arch/mips/ar71xx/mach-ja76pf.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-ja76pf.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-ja76pf.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,102 @@ ++/* ++ * jjPlus JA76PF board support ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-pb42-pci.h" ++#include "dev-usb.h" ++#include "dev-leds-gpio.h" ++ ++#define JA76PF_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define JA76PF_KEYS_DEBOUNCE_INTERVAL (3 * JA76PF_KEYS_POLL_INTERVAL) ++ ++#define JA76PF_GPIO_I2C_SCL 0 ++#define JA76PF_GPIO_I2C_SDA 1 ++#define JA76PF_GPIO_LED_1 5 ++#define JA76PF_GPIO_LED_2 4 ++#define JA76PF_GPIO_LED_3 3 ++#define JA76PF_GPIO_BTN_RESET 11 ++ ++static struct gpio_led ja76pf_leds_gpio[] __initdata = { ++ { ++ .name = "ja76pf:green:led1", ++ .gpio = JA76PF_GPIO_LED_1, ++ .active_low = 1, ++ }, { ++ .name = "ja76pf:green:led2", ++ .gpio = JA76PF_GPIO_LED_2, ++ .active_low = 1, ++ }, { ++ .name = "ja76pf:green:led3", ++ .gpio = JA76PF_GPIO_LED_3, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button ja76pf_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = JA76PF_GPIO_BTN_RESET, ++ .active_low = 1, ++ } ++}; ++ ++static struct i2c_gpio_platform_data ja76pf_i2c_gpio_data = { ++ .sda_pin = JA76PF_GPIO_I2C_SDA, ++ .scl_pin = JA76PF_GPIO_I2C_SCL, ++}; ++ ++static struct platform_device ja76pf_i2c_gpio_device = { ++ .name = "i2c-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &ja76pf_i2c_gpio_data, ++ } ++}; ++ ++#define JA76PF_WAN_PHYMASK (1 << 4) ++#define JA76PF_LAN_PHYMASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 < 3)) ++#define JA76PF_MDIO_PHYMASK (JA76PF_LAN_PHYMASK | JA76PF_WAN_PHYMASK) ++ ++static void __init ja76pf_init(void) ++{ ++ ar71xx_add_device_m25p80(NULL); ++ ++ ar71xx_add_device_mdio(~JA76PF_MDIO_PHYMASK); ++ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.phy_mask = JA76PF_LAN_PHYMASK; ++ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.phy_mask = JA76PF_WAN_PHYMASK; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ platform_device_register(&ja76pf_i2c_gpio_device); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ja76pf_leds_gpio), ++ ja76pf_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ja76pf_gpio_keys), ++ ja76pf_gpio_keys); ++ ++ ar71xx_add_device_usb(); ++ pb42_pci_init(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_JA76PF, "JA76PF", "jjPlus JA76PF", ja76pf_init); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-jwap003.c linux-2.6.39/arch/mips/ar71xx/mach-jwap003.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-jwap003.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-jwap003.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,83 @@ ++/* ++ * jjPlus JWAP003 board support ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-pb42-pci.h" ++#include "dev-usb.h" ++ ++#define JWAP003_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define JWAP003_KEYS_DEBOUNCE_INTERVAL (3 * JWAP003_KEYS_POLL_INTERVAL) ++ ++#define JWAP003_GPIO_WPS 11 ++#define JWAP003_GPIO_I2C_SCL 0 ++#define JWAP003_GPIO_I2C_SDA 1 ++ ++static struct gpio_keys_button jwap003_gpio_keys[] __initdata = { ++ { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = JWAP003_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = JWAP003_GPIO_WPS, ++ .active_low = 1, ++ } ++}; ++ ++static struct i2c_gpio_platform_data jwap003_i2c_gpio_data = { ++ .sda_pin = JWAP003_GPIO_I2C_SDA, ++ .scl_pin = JWAP003_GPIO_I2C_SCL, ++}; ++ ++static struct platform_device jwap003_i2c_gpio_device = { ++ .name = "i2c-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &jwap003_i2c_gpio_data, ++ } ++}; ++ ++#define JWAP003_WAN_PHYMASK BIT(0) ++#define JWAP003_LAN_PHYMASK BIT(4) ++ ++static void __init jwap003_init(void) ++{ ++ ar71xx_add_device_m25p80(NULL); ++ ++ ar71xx_add_device_mdio(0x0); ++ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.phy_mask = JWAP003_WAN_PHYMASK; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.has_ar8216 = 1; ++ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = JWAP003_LAN_PHYMASK; ++ ar71xx_eth1_data.speed = SPEED_100; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ platform_device_register(&jwap003_i2c_gpio_device); ++ ++ ar71xx_add_device_usb(); ++ ++ ar71xx_register_gpio_keys_polled(-1, JWAP003_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(jwap003_gpio_keys), ++ jwap003_gpio_keys); ++ ++ pb42_pci_init(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_JWAP003, "JWAP003", "jjPlus JWAP003", jwap003_init); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-mzk-w04nu.c linux-2.6.39/arch/mips/ar71xx/mach-mzk-w04nu.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-mzk-w04nu.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-mzk-w04nu.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,166 @@ ++/* ++ * Planex MZK-W04NU board support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-m25p80.h" ++#include "dev-usb.h" ++ ++#define MZK_W04NU_GPIO_LED_USB 0 ++#define MZK_W04NU_GPIO_LED_STATUS 1 ++#define MZK_W04NU_GPIO_LED_WPS 3 ++#define MZK_W04NU_GPIO_LED_WLAN 6 ++#define MZK_W04NU_GPIO_LED_AP 15 ++#define MZK_W04NU_GPIO_LED_ROUTER 16 ++ ++#define MZK_W04NU_GPIO_BTN_APROUTER 5 ++#define MZK_W04NU_GPIO_BTN_WPS 12 ++#define MZK_W04NU_GPIO_BTN_RESET 21 ++ ++#define MZK_W04NU_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define MZK_W04NU_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W04NU_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition mzk_w04nu_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ }, { ++ .name = "kernel", ++ .offset = 0x050000, ++ .size = 0x160000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x1b0000, ++ .size = 0x630000, ++ }, { ++ .name = "art", ++ .offset = 0x7e0000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x050000, ++ .size = 0x790000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data mzk_w04nu_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = mzk_w04nu_partitions, ++ .nr_parts = ARRAY_SIZE(mzk_w04nu_partitions), ++#endif ++}; ++ ++static struct gpio_led mzk_w04nu_leds_gpio[] __initdata = { ++ { ++ .name = "mzk-w04nu:green:status", ++ .gpio = MZK_W04NU_GPIO_LED_STATUS, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w04nu:blue:wps", ++ .gpio = MZK_W04NU_GPIO_LED_WPS, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w04nu:green:wlan", ++ .gpio = MZK_W04NU_GPIO_LED_WLAN, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w04nu:green:usb", ++ .gpio = MZK_W04NU_GPIO_LED_USB, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w04nu:green:ap", ++ .gpio = MZK_W04NU_GPIO_LED_AP, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w04nu:green:router", ++ .gpio = MZK_W04NU_GPIO_LED_ROUTER, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button mzk_w04nu_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = MZK_W04NU_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = MZK_W04NU_GPIO_BTN_WPS, ++ .active_low = 1, ++ }, { ++ .desc = "aprouter", ++ .type = EV_KEY, ++ .code = BTN_2, ++ .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = MZK_W04NU_GPIO_BTN_APROUTER, ++ .active_low = 0, ++ } ++}; ++ ++#define MZK_W04NU_WAN_PHYMASK BIT(4) ++#define MZK_W04NU_MDIO_MASK (~MZK_W04NU_WAN_PHYMASK) ++ ++static void __init mzk_w04nu_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ar71xx_add_device_mdio(MZK_W04NU_MDIO_MASK); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.has_ar8216 = 1; ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = MZK_W04NU_WAN_PHYMASK; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_m25p80(&mzk_w04nu_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w04nu_leds_gpio), ++ mzk_w04nu_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, MZK_W04NU_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(mzk_w04nu_gpio_keys), ++ mzk_w04nu_gpio_keys); ++ ar71xx_add_device_usb(); ++ ++ ar9xxx_add_device_wmac(eeprom, NULL); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_MZK_W04NU, "MZK-W04NU", "Planex MZK-W04NU", ++ mzk_w04nu_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-mzk-w300nh.c linux-2.6.39/arch/mips/ar71xx/mach-mzk-w300nh.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-mzk-w300nh.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-mzk-w300nh.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,159 @@ ++/* ++ * Planex MZK-W300NH board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++ ++#define MZK_W300NH_GPIO_LED_STATUS 1 ++#define MZK_W300NH_GPIO_LED_WPS 3 ++#define MZK_W300NH_GPIO_LED_WLAN 6 ++#define MZK_W300NH_GPIO_LED_AP 15 ++#define MZK_W300NH_GPIO_LED_ROUTER 16 ++ ++#define MZK_W300NH_GPIO_BTN_APROUTER 5 ++#define MZK_W300NH_GPIO_BTN_WPS 12 ++#define MZK_W300NH_GPIO_BTN_RESET 21 ++ ++#define MZK_W300NH_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define MZK_W300NH_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W300NH_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition mzk_w300nh_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ }, { ++ .name = "kernel", ++ .offset = 0x050000, ++ .size = 0x160000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x1b0000, ++ .size = 0x630000, ++ }, { ++ .name = "art", ++ .offset = 0x7e0000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x050000, ++ .size = 0x790000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data mzk_w300nh_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = mzk_w300nh_partitions, ++ .nr_parts = ARRAY_SIZE(mzk_w300nh_partitions), ++#endif ++}; ++ ++static struct gpio_led mzk_w300nh_leds_gpio[] __initdata = { ++ { ++ .name = "mzk-w300nh:green:status", ++ .gpio = MZK_W300NH_GPIO_LED_STATUS, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w300nh:blue:wps", ++ .gpio = MZK_W300NH_GPIO_LED_WPS, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w300nh:green:wlan", ++ .gpio = MZK_W300NH_GPIO_LED_WLAN, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w300nh:green:ap", ++ .gpio = MZK_W300NH_GPIO_LED_AP, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w300nh:green:router", ++ .gpio = MZK_W300NH_GPIO_LED_ROUTER, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button mzk_w300nh_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = MZK_W300NH_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = MZK_W300NH_GPIO_BTN_WPS, ++ .active_low = 1, ++ }, { ++ .desc = "aprouter", ++ .type = EV_KEY, ++ .code = BTN_2, ++ .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = MZK_W300NH_GPIO_BTN_APROUTER, ++ .active_low = 0, ++ } ++}; ++ ++#define MZK_W300NH_WAN_PHYMASK BIT(4) ++#define MZK_W300NH_MDIO_MASK (~MZK_W300NH_WAN_PHYMASK) ++ ++static void __init mzk_w300nh_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ar71xx_add_device_mdio(MZK_W300NH_MDIO_MASK); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.has_ar8216 = 1; ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = MZK_W300NH_WAN_PHYMASK; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_m25p80(&mzk_w300nh_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w300nh_leds_gpio), ++ mzk_w300nh_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, MZK_W300NH_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(mzk_w300nh_gpio_keys), ++ mzk_w300nh_gpio_keys); ++ ar9xxx_add_device_wmac(eeprom, NULL); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_MZK_W300NH, "MZK-W300NH", "Planex MZK-W300NH", ++ mzk_w300nh_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-nbg460n.c linux-2.6.39/arch/mips/ar71xx/mach-nbg460n.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-nbg460n.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-nbg460n.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,225 @@ ++/* ++ * Zyxel NBG 460N/550N/550NH board support ++ * ++ * Copyright (C) 2010 Michael Kurz ++ * ++ * based on mach-tl-wr1043nd.c ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++ ++/* LEDs */ ++#define NBG460N_GPIO_LED_WPS 3 ++#define NBG460N_GPIO_LED_WAN 6 ++#define NBG460N_GPIO_LED_POWER 14 ++#define NBG460N_GPIO_LED_WLAN 15 ++ ++/* Buttons */ ++#define NBG460N_GPIO_BTN_WPS 12 ++#define NBG460N_GPIO_BTN_RESET 21 ++ ++#define NBG460N_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define NBG460N_KEYS_DEBOUNCE_INTERVAL (3 * NBG460N_KEYS_POLL_INTERVAL) ++ ++/* RTC chip PCF8563 I2C interface */ ++#define NBG460N_GPIO_PCF8563_SDA 8 ++#define NBG460N_GPIO_PCF8563_SCK 7 ++ ++/* Switch configuration I2C interface */ ++#define NBG460N_GPIO_RTL8366_SDA 16 ++#define NBG460N_GPIO_RTL8366_SCK 18 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition nbg460n_partitions[] = { ++ { ++ .name = "Bootbase", ++ .offset = 0, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "U-Boot Config", ++ .offset = 0x010000, ++ .size = 0x030000, ++ }, { ++ .name = "U-Boot", ++ .offset = 0x040000, ++ .size = 0x030000, ++ }, { ++ .name = "linux", ++ .offset = 0x070000, ++ .size = 0x0e0000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x150000, ++ .size = 0x2a0000, ++ }, { ++ .name = "CalibData", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x070000, ++ .size = 0x380000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data nbg460n_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = nbg460n_partitions, ++ .nr_parts = ARRAY_SIZE(nbg460n_partitions), ++#endif ++}; ++ ++static struct gpio_led nbg460n_leds_gpio[] __initdata = { ++ { ++ .name = "nbg460n:green:power", ++ .gpio = NBG460N_GPIO_LED_POWER, ++ .active_low = 0, ++ .default_trigger = "default-on", ++ }, { ++ .name = "nbg460n:green:wps", ++ .gpio = NBG460N_GPIO_LED_WPS, ++ .active_low = 0, ++ }, { ++ .name = "nbg460n:green:wlan", ++ .gpio = NBG460N_GPIO_LED_WLAN, ++ .active_low = 0, ++ }, { ++ /* Not really for controlling the LED, ++ when set low the LED blinks uncontrollable */ ++ .name = "nbg460n:green:wan", ++ .gpio = NBG460N_GPIO_LED_WAN, ++ .active_low = 0, ++ } ++}; ++ ++static struct gpio_keys_button nbg460n_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = NBG460N_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = NBG460N_GPIO_BTN_WPS, ++ .active_low = 1, ++ } ++}; ++ ++static struct i2c_gpio_platform_data nbg460n_i2c_device_platdata = { ++ .sda_pin = NBG460N_GPIO_PCF8563_SDA, ++ .scl_pin = NBG460N_GPIO_PCF8563_SCK, ++ .udelay = 10, ++}; ++ ++static struct platform_device nbg460n_i2c_device = { ++ .name = "i2c-gpio", ++ .id = -1, ++ .num_resources = 0, ++ .resource = NULL, ++ .dev = { ++ .platform_data = &nbg460n_i2c_device_platdata, ++ }, ++}; ++ ++static struct i2c_board_info nbg460n_i2c_devs[] __initdata = { ++ { ++ I2C_BOARD_INFO("pcf8563", 0x51), ++ }, ++}; ++ ++static void __devinit nbg460n_i2c_init(void) ++{ ++ /* The gpio interface */ ++ platform_device_register(&nbg460n_i2c_device); ++ /* I2C devices */ ++ i2c_register_board_info(0, nbg460n_i2c_devs, ++ ARRAY_SIZE(nbg460n_i2c_devs)); ++} ++ ++ ++static struct rtl8366_platform_data nbg460n_rtl8366s_data = { ++ .gpio_sda = NBG460N_GPIO_RTL8366_SDA, ++ .gpio_sck = NBG460N_GPIO_RTL8366_SCK, ++}; ++ ++static struct platform_device nbg460n_rtl8366s_device = { ++ .name = RTL8366S_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &nbg460n_rtl8366s_data, ++ } ++}; ++ ++static void __init nbg460n_setup(void) ++{ ++ /* end of bootloader sector contains mac address */ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1fc0fff8); ++ /* last sector contains wlan calib data */ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ /* LAN Port */ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_eth0_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ++ /* WAN Port */ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); ++ ar71xx_eth1_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.phy_mask = 0x10; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ /* register the switch phy */ ++ platform_device_register(&nbg460n_rtl8366s_device); ++ ++ /* register flash */ ++ ar71xx_add_device_m25p80(&nbg460n_flash_data); ++ ++ ar9xxx_add_device_wmac(eeprom, mac); ++ ++ /* register RTC chip */ ++ nbg460n_i2c_init(); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(nbg460n_leds_gpio), ++ nbg460n_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, NBG460N_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(nbg460n_gpio_keys), ++ nbg460n_gpio_keys); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_NBG460N, "NBG460N", "Zyxel NBG460N/550N/550NH", ++ nbg460n_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-pb42.c linux-2.6.39/arch/mips/ar71xx/mach-pb42.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-pb42.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-pb42.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,74 @@ ++/* ++ * Atheros PB42 board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-pb42-pci.h" ++#include "dev-usb.h" ++ ++#define PB42_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define PB42_KEYS_DEBOUNCE_INTERVAL (3 * PB42_KEYS_POLL_INTERVAL) ++ ++#define PB42_GPIO_BTN_SW4 8 ++#define PB42_GPIO_BTN_SW5 3 ++ ++static struct gpio_keys_button pb42_gpio_keys[] __initdata = { ++ { ++ .desc = "sw4", ++ .type = EV_KEY, ++ .code = BTN_0, ++ .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = PB42_GPIO_BTN_SW4, ++ .active_low = 1, ++ }, { ++ .desc = "sw5", ++ .type = EV_KEY, ++ .code = BTN_1, ++ .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = PB42_GPIO_BTN_SW5, ++ .active_low = 1, ++ } ++}; ++ ++#define PB42_WAN_PHYMASK BIT(20) ++#define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) ++#define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK) ++ ++static void __init pb42_init(void) ++{ ++ ar71xx_add_device_m25p80(NULL); ++ ++ ar71xx_add_device_mdio(~PB42_MDIO_PHYMASK); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = PB42_WAN_PHYMASK; ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 1); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_100; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_register_gpio_keys_polled(-1, PB42_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(pb42_gpio_keys), ++ pb42_gpio_keys); ++ ++ pb42_pci_init(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_PB42, "PB42", "Atheros PB42", pb42_init); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-pb44.c linux-2.6.39/arch/mips/ar71xx/mach-pb44.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-pb44.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-pb44.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,213 @@ ++/* ++ * Atheros PB44 board support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-pb42-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++ ++#define PB44_PCF8757_VSC7395_CS 0 ++#define PB44_PCF8757_STEREO_CS 1 ++#define PB44_PCF8757_SLIC_CS0 2 ++#define PB44_PCF8757_SLIC_TEST 3 ++#define PB44_PCF8757_SLIC_INT0 4 ++#define PB44_PCF8757_SLIC_INT1 5 ++#define PB44_PCF8757_SW_RESET 6 ++#define PB44_PCF8757_SW_JUMP 8 ++#define PB44_PCF8757_LED_JUMP1 9 ++#define PB44_PCF8757_LED_JUMP2 10 ++#define PB44_PCF8757_TP24 11 ++#define PB44_PCF8757_TP25 12 ++#define PB44_PCF8757_TP26 13 ++#define PB44_PCF8757_TP27 14 ++#define PB44_PCF8757_TP28 15 ++ ++#define PB44_GPIO_I2C_SCL 0 ++#define PB44_GPIO_I2C_SDA 1 ++ ++#define PB44_GPIO_EXP_BASE 16 ++#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS) ++#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + PB44_PCF8757_SW_RESET) ++#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + PB44_PCF8757_SW_JUMP) ++#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + PB44_PCF8757_LED_JUMP1) ++#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + PB44_PCF8757_LED_JUMP2) ++ ++#define PB44_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define PB44_KEYS_DEBOUNCE_INTERVAL (3 * PB44_KEYS_POLL_INTERVAL) ++ ++static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { ++ .sda_pin = PB44_GPIO_I2C_SDA, ++ .scl_pin = PB44_GPIO_I2C_SCL, ++}; ++ ++static struct platform_device pb44_i2c_gpio_device = { ++ .name = "i2c-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &pb44_i2c_gpio_data, ++ } ++}; ++ ++static struct pcf857x_platform_data pb44_pcf857x_data = { ++ .gpio_base = PB44_GPIO_EXP_BASE, ++}; ++ ++static struct i2c_board_info pb44_i2c_board_info[] __initdata = { ++ { ++ I2C_BOARD_INFO("pcf8575", 0x20), ++ .platform_data = &pb44_pcf857x_data, ++ }, ++}; ++ ++static struct gpio_led pb44_leds_gpio[] __initdata = { ++ { ++ .name = "pb44:amber:jump1", ++ .gpio = PB44_GPIO_LED_JUMP1, ++ .active_low = 1, ++ }, { ++ .name = "pb44:green:jump2", ++ .gpio = PB44_GPIO_LED_JUMP2, ++ .active_low = 1, ++ }, ++}; ++ ++static struct gpio_keys_button pb44_gpio_keys[] __initdata = { ++ { ++ .desc = "soft_reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = PB44_GPIO_SW_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "jumpstart", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = PB44_GPIO_SW_JUMP, ++ .active_low = 1, ++ } ++}; ++ ++static void pb44_vsc7395_reset(void) ++{ ++ ar71xx_device_stop(RESET_MODULE_GE1_PHY); ++ udelay(10); ++ ar71xx_device_start(RESET_MODULE_GE1_PHY); ++ mdelay(50); ++} ++ ++static struct vsc7385_platform_data pb44_vsc7395_data = { ++ .reset = pb44_vsc7395_reset, ++ .ucode_name = "vsc7395_ucode_pb44.bin", ++ .mac_cfg = { ++ .tx_ipg = 6, ++ .bit2 = 1, ++ .clk_sel = 0, ++ }, ++}; ++ ++static struct spi_board_info pb44_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "m25p80", ++ }, { ++ .bus_num = 0, ++ .chip_select = 1, ++ .max_speed_hz = 25000000, ++ .modalias = "spi-vsc7385", ++ .platform_data = &pb44_vsc7395_data, ++ .controller_data = (void *) PB44_GPIO_VSC7395_CS, ++ }, ++}; ++ ++static struct resource pb44_spi_resources[] = { ++ [0] = { ++ .start = AR71XX_SPI_BASE, ++ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static struct ar71xx_spi_platform_data pb44_spi_data = { ++ .bus_num = 0, ++ .num_chipselect = 2, ++}; ++ ++static struct platform_device pb44_spi_device = { ++ .name = "pb44-spi", ++ .id = -1, ++ .resource = pb44_spi_resources, ++ .num_resources = ARRAY_SIZE(pb44_spi_resources), ++ .dev = { ++ .platform_data = &pb44_spi_data, ++ }, ++}; ++ ++#define PB44_WAN_PHYMASK BIT(0) ++#define PB44_LAN_PHYMASK 0 ++#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK) ++ ++static void __init pb44_init(void) ++{ ++ ar71xx_add_device_mdio(~PB44_MDIO_PHYMASK); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.phy_mask = PB44_WAN_PHYMASK; ++ ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 1); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ar71xx_eth1_pll_data.pll_1000 = 0x110000; ++ ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_usb(); ++ ++ pb42_pci_init(); ++ ++ i2c_register_board_info(0, pb44_i2c_board_info, ++ ARRAY_SIZE(pb44_i2c_board_info)); ++ ++ platform_device_register(&pb44_i2c_gpio_device); ++ ++ spi_register_board_info(pb44_spi_info, ARRAY_SIZE(pb44_spi_info)); ++ platform_device_register(&pb44_spi_device); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), ++ pb44_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(pb44_gpio_keys), ++ pb44_gpio_keys); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_PB44, "PB44", "Atheros PB44", pb44_init); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-pb92.c linux-2.6.39/arch/mips/ar71xx/mach-pb92.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-pb92.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-pb92.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,105 @@ ++/* ++ * Atheros PB92 board support ++ * ++ * Copyright (C) 2010 Felix Fietkau ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-pb9x-pci.h" ++#include "dev-usb.h" ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition pb92_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x050000, ++ .size = 0x2b0000, ++ }, { ++ .name = "uImage", ++ .offset = 0x300000, ++ .size = 0x0e0000, ++ }, { ++ .name = "ART", ++ .offset = 0x3e0000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data pb92_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = pb92_partitions, ++ .nr_parts = ARRAY_SIZE(pb92_partitions), ++#endif ++}; ++ ++#define PB92_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define PB92_KEYS_DEBOUNCE_INTERVAL (3 * PB92_KEYS_POLL_INTERVAL) ++ ++#define PB92_GPIO_BTN_SW4 8 ++#define PB92_GPIO_BTN_SW5 3 ++ ++static struct gpio_keys_button pb92_gpio_keys[] __initdata = { ++ { ++ .desc = "sw4", ++ .type = EV_KEY, ++ .code = BTN_0, ++ .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = PB92_GPIO_BTN_SW4, ++ .active_low = 1, ++ }, { ++ .desc = "sw5", ++ .type = EV_KEY, ++ .code = BTN_1, ++ .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = PB92_GPIO_BTN_SW5, ++ .active_low = 1, ++ } ++}; ++ ++static void __init pb92_init(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ar71xx_add_device_m25p80(&pb92_flash_data); ++ ++ ar71xx_add_device_mdio(~BIT(0)); ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.phy_mask = BIT(0); ++ ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_register_gpio_keys_polled(-1, PB92_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(pb92_gpio_keys), ++ pb92_gpio_keys); ++ ++ pb9x_pci_init(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_PB92, "PB92", "Atheros PB92", pb92_init); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-rb4xx.c linux-2.6.39/arch/mips/ar71xx/mach-rb4xx.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-rb4xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-rb4xx.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,344 @@ ++/* ++ * MikroTik RouterBOARD 4xx series support ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++ ++#define RB4XX_GPIO_USER_LED 4 ++#define RB4XX_GPIO_RESET_SWITCH 7 ++ ++#define RB4XX_GPIO_CPLD_BASE 32 ++#define RB4XX_GPIO_CPLD_LED1 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1) ++#define RB4XX_GPIO_CPLD_LED2 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2) ++#define RB4XX_GPIO_CPLD_LED3 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3) ++#define RB4XX_GPIO_CPLD_LED4 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4) ++#define RB4XX_GPIO_CPLD_LED5 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5) ++ ++#define RB4XX_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define RB4XX_KEYS_DEBOUNCE_INTERVAL (3 * RB4XX_KEYS_POLL_INTERVAL) ++ ++static struct gpio_led rb4xx_leds_gpio[] __initdata = { ++ { ++ .name = "rb4xx:yellow:user", ++ .gpio = RB4XX_GPIO_USER_LED, ++ .active_low = 0, ++ }, { ++ .name = "rb4xx:green:led1", ++ .gpio = RB4XX_GPIO_CPLD_LED1, ++ .active_low = 1, ++ }, { ++ .name = "rb4xx:green:led2", ++ .gpio = RB4XX_GPIO_CPLD_LED2, ++ .active_low = 1, ++ }, { ++ .name = "rb4xx:green:led3", ++ .gpio = RB4XX_GPIO_CPLD_LED3, ++ .active_low = 1, ++ }, { ++ .name = "rb4xx:green:led4", ++ .gpio = RB4XX_GPIO_CPLD_LED4, ++ .active_low = 1, ++ }, { ++ .name = "rb4xx:green:led5", ++ .gpio = RB4XX_GPIO_CPLD_LED5, ++ .active_low = 0, ++ }, ++}; ++ ++static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = { ++ { ++ .desc = "reset_switch", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = RB4XX_GPIO_RESET_SWITCH, ++ .active_low = 1, ++ } ++}; ++ ++static struct platform_device rb4xx_nand_device = { ++ .name = "rb4xx-nand", ++ .id = -1, ++}; ++ ++static struct ar71xx_pci_irq rb4xx_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV2, ++ }, { ++ .slot = 1, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ }, { ++ .slot = 1, ++ .pin = 2, ++ .irq = AR71XX_PCI_IRQ_DEV1, ++ }, { ++ .slot = 2, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV1, ++ }, { ++ .slot = 3, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV2, ++ } ++}; ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition rb4xx_partitions[] = { ++ { ++ .name = "routerboot", ++ .offset = 0, ++ .size = 0x0b000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "hard_config", ++ .offset = 0x0b000, ++ .size = 0x01000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "bios", ++ .offset = 0x0d000, ++ .size = 0x02000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "soft_config", ++ .offset = 0x0f000, ++ .size = 0x01000, ++ } ++}; ++#define rb4xx_num_partitions ARRAY_SIZE(rb4xx_partitions) ++#else /* CONFIG_MTD_PARTITIONS */ ++#define rb4xx_partitions NULL ++#define rb4xx_num_partitions 0 ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data rb4xx_flash_data = { ++ .type = "pm25lv512", ++ .parts = rb4xx_partitions, ++ .nr_parts = rb4xx_num_partitions, ++}; ++ ++static struct rb4xx_cpld_platform_data rb4xx_cpld_data = { ++ .gpio_base = RB4XX_GPIO_CPLD_BASE, ++}; ++ ++static struct mmc_spi_platform_data rb4xx_mmc_data = { ++ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, ++}; ++ ++static struct spi_board_info rb4xx_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "m25p80", ++ .platform_data = &rb4xx_flash_data, ++ }, { ++ .bus_num = 0, ++ .chip_select = 1, ++ .max_speed_hz = 25000000, ++ .modalias = "spi-rb4xx-cpld", ++ .platform_data = &rb4xx_cpld_data, ++ } ++}; ++ ++static struct spi_board_info rb4xx_microsd_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 2, ++ .max_speed_hz = 25000000, ++ .modalias = "mmc_spi", ++ .platform_data = &rb4xx_mmc_data, ++ } ++}; ++ ++ ++static struct resource rb4xx_spi_resources[] = { ++ { ++ .start = AR71XX_SPI_BASE, ++ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static struct platform_device rb4xx_spi_device = { ++ .name = "rb4xx-spi", ++ .id = -1, ++ .resource = rb4xx_spi_resources, ++ .num_resources = ARRAY_SIZE(rb4xx_spi_resources), ++}; ++ ++static void __init rb4xx_generic_setup(void) ++{ ++ ar71xx_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | ++ AR71XX_GPIO_FUNC_SPI_CS2_EN); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), ++ rb4xx_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(rb4xx_gpio_keys), ++ rb4xx_gpio_keys); ++ ++ spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); ++ platform_device_register(&rb4xx_spi_device); ++ platform_device_register(&rb4xx_nand_device); ++} ++ ++static void __init rb411_setup(void) ++{ ++ rb4xx_generic_setup(); ++ spi_register_board_info(rb4xx_microsd_info, ++ ARRAY_SIZE(rb4xx_microsd_info)); ++ ++ ar71xx_add_device_mdio(0xfffffffc); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = 0x00000003; ++ ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH", ++ rb411_setup); ++ ++static void __init rb411u_setup(void) ++{ ++ rb411_setup(); ++ ar71xx_add_device_usb(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U", ++ rb411u_setup); ++ ++#define RB433_LAN_PHYMASK BIT(0) ++#define RB433_WAN_PHYMASK BIT(4) ++#define RB433_MDIO_PHYMASK (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK) ++ ++static void __init rb433_setup(void) ++{ ++ rb4xx_generic_setup(); ++ spi_register_board_info(rb4xx_microsd_info, ++ ARRAY_SIZE(rb4xx_microsd_info)); ++ ++ ar71xx_add_device_mdio(~RB433_MDIO_PHYMASK); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 1); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = RB433_LAN_PHYMASK; ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 0); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = RB433_WAN_PHYMASK; ++ ++ ar71xx_add_device_eth(1); ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH", ++ rb433_setup); ++ ++static void __init rb433u_setup(void) ++{ ++ rb433_setup(); ++ ar71xx_add_device_usb(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH", ++ rb433u_setup); ++ ++#define RB450_LAN_PHYMASK BIT(0) ++#define RB450_WAN_PHYMASK BIT(4) ++#define RB450_MDIO_PHYMASK (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK) ++ ++static void __init rb450_generic_setup(int gige) ++{ ++ rb4xx_generic_setup(); ++ ar71xx_add_device_mdio(~RB450_MDIO_PHYMASK); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 1); ++ ar71xx_eth0_data.phy_if_mode = (gige) ? ++ PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = RB450_LAN_PHYMASK; ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 0); ++ ar71xx_eth1_data.phy_if_mode = (gige) ? ++ PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = RB450_WAN_PHYMASK; ++ ++ ar71xx_add_device_eth(1); ++ ar71xx_add_device_eth(0); ++} ++ ++static void __init rb450_setup(void) ++{ ++ rb450_generic_setup(0); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_RB_450, "450", "MikroTik RouterBOARD 450", ++ rb450_setup); ++ ++static void __init rb450g_setup(void) ++{ ++ rb450_generic_setup(1); ++ spi_register_board_info(rb4xx_microsd_info, ++ ARRAY_SIZE(rb4xx_microsd_info)); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G", ++ rb450g_setup); ++ ++static void __init rb493_setup(void) ++{ ++ rb4xx_generic_setup(); ++ ++ ar71xx_add_device_mdio(0x3fffff00); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 1); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = 0x00000001; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH", ++ rb493_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-rb750.c linux-2.6.39/arch/mips/ar71xx/mach-rb750.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-rb750.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-rb750.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,144 @@ ++/* ++ * MikroTik RouterBOARD 750 support ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++ ++static struct rb750_led_data rb750_leds[] = { ++ { ++ .name = "rb750:green:act", ++ .mask = RB750_LED_ACT, ++ .active_low = 1, ++ }, { ++ .name = "rb750:green:port1", ++ .mask = RB750_LED_PORT5, ++ .active_low = 1, ++ }, { ++ .name = "rb750:green:port2", ++ .mask = RB750_LED_PORT4, ++ .active_low = 1, ++ }, { ++ .name = "rb750:green:port3", ++ .mask = RB750_LED_PORT3, ++ .active_low = 1, ++ }, { ++ .name = "rb750:green:port4", ++ .mask = RB750_LED_PORT2, ++ .active_low = 1, ++ }, { ++ .name = "rb750:green:port5", ++ .mask = RB750_LED_PORT1, ++ .active_low = 1, ++ } ++}; ++ ++static struct rb750_led_platform_data rb750_leds_data = { ++ .num_leds = ARRAY_SIZE(rb750_leds), ++ .leds = rb750_leds, ++}; ++ ++static struct platform_device rb750_leds_device = { ++ .name = "leds-rb750", ++ .dev = { ++ .platform_data = &rb750_leds_data, ++ } ++}; ++ ++static struct platform_device rb750_nand_device = { ++ .name = "rb750-nand", ++ .id = -1, ++}; ++ ++int rb750_latch_change(u32 mask_clr, u32 mask_set) ++{ ++ static DEFINE_SPINLOCK(lock); ++ static u32 latch_set = RB750_LED_BITS | RB750_LVC573_LE; ++ static u32 latch_oe; ++ static u32 latch_clr; ++ unsigned long flags; ++ u32 t; ++ int ret = 0; ++ ++ spin_lock_irqsave(&lock, flags); ++ ++ if ((mask_clr & BIT(31)) != 0 && ++ (latch_set & RB750_LVC573_LE) == 0) { ++ goto unlock; ++ } ++ ++ latch_set = (latch_set | mask_set) & ~mask_clr; ++ latch_clr = (latch_clr | mask_clr) & ~mask_set; ++ ++ if (latch_oe == 0) ++ latch_oe = __raw_readl(ar71xx_gpio_base + GPIO_REG_OE); ++ ++ if (likely(latch_set & RB750_LVC573_LE)) { ++ void __iomem *base = ar71xx_gpio_base; ++ ++ t = __raw_readl(base + GPIO_REG_OE); ++ t |= mask_clr | latch_oe | mask_set; ++ ++ __raw_writel(t, base + GPIO_REG_OE); ++ __raw_writel(latch_clr, base + GPIO_REG_CLEAR); ++ __raw_writel(latch_set, base + GPIO_REG_SET); ++ } else if (mask_clr & RB750_LVC573_LE) { ++ void __iomem *base = ar71xx_gpio_base; ++ ++ latch_oe = __raw_readl(base + GPIO_REG_OE); ++ __raw_writel(RB750_LVC573_LE, base + GPIO_REG_CLEAR); ++ /* flush write */ ++ __raw_readl(base + GPIO_REG_CLEAR); ++ } ++ ++ ret = 1; ++ ++unlock: ++ spin_unlock_irqrestore(&lock, flags); ++ return ret; ++} ++EXPORT_SYMBOL_GPL(rb750_latch_change); ++ ++static void __init rb750_setup(void) ++{ ++ ar71xx_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | ++ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | ++ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | ++ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | ++ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 1); ++ ++ /* WAN port */ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.phy_mask = BIT(4); ++ ++ /* LAN ports */ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ar71xx_eth1_data.has_ar7240_switch = 1; ++ ++ ar71xx_add_device_mdio(0x0); ++ ar71xx_add_device_eth(1); ++ ar71xx_add_device_eth(0); ++ ++ platform_device_register(&rb750_leds_device); ++ platform_device_register(&rb750_nand_device); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_RB_750, "750i", "MikroTik RouterBOARD 750", ++ rb750_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tew-632brp.c linux-2.6.39/arch/mips/ar71xx/mach-tew-632brp.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-tew-632brp.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-tew-632brp.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,151 @@ ++/* ++ * TrendNET TEW-632BRP board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "nvram.h" ++ ++#define TEW_632BRP_GPIO_LED_STATUS 1 ++#define TEW_632BRP_GPIO_LED_WPS 3 ++#define TEW_632BRP_GPIO_LED_WLAN 6 ++#define TEW_632BRP_GPIO_BTN_WPS 12 ++#define TEW_632BRP_GPIO_BTN_RESET 21 ++ ++#define TEW_632BRP_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define TEW_632BRP_KEYS_DEBOUNCE_INTERVAL (3 * TEW_632BRP_KEYS_POLL_INTERVAL) ++ ++#define TEW_632BRP_CONFIG_ADDR 0x1f020000 ++#define TEW_632BRP_CONFIG_SIZE 0x10000 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition tew_632brp_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "config", ++ .offset = 0x020000, ++ .size = 0x010000, ++ }, { ++ .name = "kernel", ++ .offset = 0x030000, ++ .size = 0x0e0000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x110000, ++ .size = 0x2e0000, ++ }, { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x030000, ++ .size = 0x3c0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data tew_632brp_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = tew_632brp_partitions, ++ .nr_parts = ARRAY_SIZE(tew_632brp_partitions), ++#endif ++}; ++ ++static struct gpio_led tew_632brp_leds_gpio[] __initdata = { ++ { ++ .name = "tew-632brp:green:status", ++ .gpio = TEW_632BRP_GPIO_LED_STATUS, ++ .active_low = 1, ++ }, { ++ .name = "tew-632brp:blue:wps", ++ .gpio = TEW_632BRP_GPIO_LED_WPS, ++ .active_low = 1, ++ }, { ++ .name = "tew-632brp:green:wlan", ++ .gpio = TEW_632BRP_GPIO_LED_WLAN, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button tew_632brp_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TEW_632BRP_GPIO_BTN_RESET, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TEW_632BRP_GPIO_BTN_WPS, ++ } ++}; ++ ++#define TEW_632BRP_LAN_PHYMASK BIT(0) ++#define TEW_632BRP_WAN_PHYMASK BIT(4) ++#define TEW_632BRP_MDIO_MASK (~(TEW_632BRP_LAN_PHYMASK | \ ++ TEW_632BRP_WAN_PHYMASK)) ++ ++static void __init tew_632brp_setup(void) ++{ ++ const char *config = (char *) KSEG1ADDR(TEW_632BRP_CONFIG_ADDR); ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ u8 mac[6]; ++ u8 *wlan_mac = NULL; ++ ++ if (nvram_parse_mac_addr(config, TEW_632BRP_CONFIG_SIZE, ++ "lan_mac=", mac) == 0) { ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); ++ wlan_mac = mac; ++ } ++ ++ ar71xx_add_device_mdio(TEW_632BRP_MDIO_MASK); ++ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.phy_mask = TEW_632BRP_LAN_PHYMASK; ++ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = TEW_632BRP_WAN_PHYMASK; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_m25p80(&tew_632brp_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tew_632brp_leds_gpio), ++ tew_632brp_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, TEW_632BRP_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(tew_632brp_gpio_keys), ++ tew_632brp_gpio_keys); ++ ++ ar9xxx_add_device_wmac(eeprom, wlan_mac); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_TEW_632BRP, "TEW-632BRP", "TRENDnet TEW-632BRP", ++ tew_632brp_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-mr3x20.c linux-2.6.39/arch/mips/ar71xx/mach-tl-mr3x20.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-mr3x20.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-tl-mr3x20.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,166 @@ ++/* ++ * TP-LINK TL-MR3220/3420 board support ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap91-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++ ++#define TL_MR3X20_GPIO_LED_QSS 0 ++#define TL_MR3X20_GPIO_LED_SYSTEM 1 ++#define TL_MR3X20_GPIO_LED_3G 8 ++ ++#define TL_MR3X20_GPIO_BTN_RESET 11 ++#define TL_MR3X20_GPIO_BTN_QSS 12 ++ ++#define TL_MR3X20_GPIO_USB_POWER 6 ++ ++#define TL_MR3X20_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define TL_MR3X20_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR3X20_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition tl_mr3x20_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = 0x020000, ++ .size = 0x140000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x160000, ++ .size = 0x290000, ++ }, { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x020000, ++ .size = 0x3d0000, ++ } ++}; ++#define tl_mr3x20_num_partitions ARRAY_SIZE(tl_mr3x20_partitions) ++#else ++#define tl_mr3x20_partitions NULL ++#define tl_mr3x20_num_partitions 0 ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data tl_mr3x20_flash_data = { ++ .parts = tl_mr3x20_partitions, ++ .nr_parts = tl_mr3x20_num_partitions, ++}; ++ ++static struct gpio_led tl_mr3x20_leds_gpio[] __initdata = { ++ { ++ .name = "tl-mr3x20:green:system", ++ .gpio = TL_MR3X20_GPIO_LED_SYSTEM, ++ .active_low = 1, ++ }, { ++ .name = "tl-mr3x20:green:qss", ++ .gpio = TL_MR3X20_GPIO_LED_QSS, ++ .active_low = 1, ++ }, { ++ .name = "tl-mr3x20:green:3g", ++ .gpio = TL_MR3X20_GPIO_LED_3G, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button tl_mr3x20_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_MR3X20_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "qss", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_MR3X20_GPIO_BTN_QSS, ++ .active_low = 1, ++ } ++}; ++ ++static void __init tl_mr3x20_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ /* enable power for the USB port */ ++ gpio_request(TL_MR3X20_GPIO_USB_POWER, "USB power"); ++ gpio_direction_output(TL_MR3X20_GPIO_USB_POWER, 1); ++ ++ ar71xx_add_device_m25p80(&tl_mr3x20_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio), ++ tl_mr3x20_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, TL_MR3X20_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(tl_mr3x20_gpio_keys), ++ tl_mr3x20_gpio_keys); ++ ++ ar71xx_eth1_data.has_ar7240_switch = 1; ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); ++ ++ /* WAN port */ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.phy_mask = BIT(4); ++ ++ /* LAN ports */ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_mdio(0x0); ++ ar71xx_add_device_eth(1); ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_add_device_usb(); ++ ++ ap91_pci_init(ee, mac); ++} ++ ++static void __init tl_mr3220_setup(void) ++{ ++ tl_mr3x20_setup(); ++ ap91_pci_setup_wmac_led_pin(1); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_TL_MR3220, "TL-MR3220", "TP-LINK TL-MR3220", ++ tl_mr3220_setup); ++ ++static void __init tl_mr3420_setup(void) ++{ ++ tl_mr3x20_setup(); ++ ap91_pci_setup_wmac_led_pin(0); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_TL_MR3420, "TL-MR3420", "TP-LINK TL-MR3420", ++ tl_mr3420_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wa901nd-v2.c linux-2.6.39/arch/mips/ar71xx/mach-tl-wa901nd-v2.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wa901nd-v2.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-tl-wa901nd-v2.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,132 @@ ++/* ++ * TP-LINK TL-WA901ND v2 board support ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * Copyright (C) 2010 Pieter Hollants ++ * Copyright (C) 2011 Jonathan Bennett ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-ar9xxx-wmac.h" ++ ++#define TL_WA901ND_V2_GPIO_LED_QSS 4 ++#define TL_WA901ND_V2_GPIO_LED_SYSTEM 2 ++#define TL_WA901ND_V2_GPIO_LED_WLAN 9 ++ ++ ++#define TL_WA901ND_V2_GPIO_BTN_RESET 3 ++#define TL_WA901ND_V2_GPIO_BTN_QSS 7 ++ ++#define TL_WA901ND_V2_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL \ ++ (3 * TL_WA901ND_V2_KEYS_POLL_INTERVAL) ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition tl_wa901nd_v2_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = 0x020000, ++ .size = 0x140000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x160000, ++ .size = 0x290000, ++ }, { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x020000, ++ .size = 0x3d0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data tl_wa901nd_v2_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = tl_wa901nd_v2_partitions, ++ .nr_parts = ARRAY_SIZE(tl_wa901nd_v2_partitions), ++#endif ++}; ++ ++static struct gpio_led tl_wa901nd_v2_leds_gpio[] __initdata = { ++ { ++ .name = "tl-wa901nd-v2:green:system", ++ .gpio = TL_WA901ND_V2_GPIO_LED_SYSTEM, ++ .active_low = 1, ++ }, { ++ .name = "tl-wa901nd-v2:green:qss", ++ .gpio = TL_WA901ND_V2_GPIO_LED_QSS, ++ }, { ++ .name = "tl-wa901nd-v2:green:wlan", ++ .gpio = TL_WA901ND_V2_GPIO_LED_WLAN, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button tl_wa901nd_v2_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_WA901ND_V2_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "qss", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_WA901ND_V2_GPIO_BTN_QSS, ++ .active_low = 1, ++ } ++}; ++ ++static void __init tl_wa901nd_v2_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = 0x00001000; ++ ar71xx_add_device_mdio(0x0); ++ ++ ar71xx_eth0_data.reset_bit = RESET_MODULE_GE0_MAC | ++ RESET_MODULE_GE0_PHY; ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_add_device_m25p80(&tl_wa901nd_v2_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_v2_leds_gpio), ++ tl_wa901nd_v2_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, TL_WA901ND_V2_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(tl_wa901nd_v2_gpio_keys), ++ tl_wa901nd_v2_gpio_keys); ++ ++ ar9xxx_add_device_wmac(eeprom, mac); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_TL_WA901ND_V2, "TL-WA901ND-v2", ++ "TP-LINK TL-WA901ND v2", tl_wa901nd_v2_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wa901nd.c linux-2.6.39/arch/mips/ar71xx/mach-tl-wa901nd.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wa901nd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-tl-wa901nd.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,130 @@ ++/* ++ * TP-LINK TL-WA901ND board support ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * Copyright (C) 2010 Pieter Hollants ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap91-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++ ++#define TL_WA901ND_GPIO_LED_QSS 0 ++#define TL_WA901ND_GPIO_LED_SYSTEM 1 ++ ++#define TL_WA901ND_GPIO_BTN_RESET 11 ++#define TL_WA901ND_GPIO_BTN_QSS 12 ++ ++#define TL_WA901ND_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define TL_WA901ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WA901ND_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition tl_wa901nd_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = 0x020000, ++ .size = 0x140000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x160000, ++ .size = 0x290000, ++ }, { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x020000, ++ .size = 0x3d0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data tl_wa901nd_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = tl_wa901nd_partitions, ++ .nr_parts = ARRAY_SIZE(tl_wa901nd_partitions), ++#endif ++}; ++ ++static struct gpio_led tl_wa901nd_leds_gpio[] __initdata = { ++ { ++ .name = "tl-wa901nd:green:system", ++ .gpio = TL_WA901ND_GPIO_LED_SYSTEM, ++ .active_low = 1, ++ }, { ++ .name = "tl-wa901nd:green:qss", ++ .gpio = TL_WA901ND_GPIO_LED_QSS, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button tl_wa901nd_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = BTN_0, ++ .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_WA901ND_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "qss", ++ .type = EV_KEY, ++ .code = BTN_1, ++ .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_WA901ND_GPIO_BTN_QSS, ++ .active_low = 1, ++ } ++}; ++ ++static void __init tl_wa901nd_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ /* ++ * ar71xx_eth0 would be the WAN port, but is not connected on ++ * the TL-WA901ND. ar71xx_eth1 connects to the internal switch chip, ++ * however we have a single LAN port only. ++ */ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 0); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ar71xx_eth1_data.has_ar7240_switch = 1; ++ ++ ar71xx_add_device_mdio(0x0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_m25p80(&tl_wa901nd_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_leds_gpio), ++ tl_wa901nd_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, TL_WA901ND_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(tl_wa901nd_gpio_keys), ++ tl_wa901nd_gpio_keys); ++ ++ ap91_pci_init(ee, mac); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_TL_WA901ND, "TL-WA901ND", "TP-LINK TL-WA901ND", ++ tl_wa901nd_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr1043nd.c linux-2.6.39/arch/mips/ar71xx/mach-tl-wr1043nd.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr1043nd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-tl-wr1043nd.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,156 @@ ++/* ++ * TP-LINK TL-WR1043ND board support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++ ++#define TL_WR1043ND_GPIO_LED_USB 1 ++#define TL_WR1043ND_GPIO_LED_SYSTEM 2 ++#define TL_WR1043ND_GPIO_LED_QSS 5 ++#define TL_WR1043ND_GPIO_LED_WLAN 9 ++ ++#define TL_WR1043ND_GPIO_BTN_RESET 3 ++#define TL_WR1043ND_GPIO_BTN_QSS 7 ++ ++#define TL_WR1043ND_GPIO_RTL8366_SDA 18 ++#define TL_WR1043ND_GPIO_RTL8366_SCK 19 ++ ++#define TL_WR1043ND_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1043ND_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition tl_wr1043nd_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = 0x020000, ++ .size = 0x140000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x160000, ++ .size = 0x690000, ++ }, { ++ .name = "art", ++ .offset = 0x7f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x020000, ++ .size = 0x7d0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data tl_wr1043nd_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = tl_wr1043nd_partitions, ++ .nr_parts = ARRAY_SIZE(tl_wr1043nd_partitions), ++#endif ++}; ++ ++static struct gpio_led tl_wr1043nd_leds_gpio[] __initdata = { ++ { ++ .name = "tl-wr1043nd:green:usb", ++ .gpio = TL_WR1043ND_GPIO_LED_USB, ++ .active_low = 1, ++ }, { ++ .name = "tl-wr1043nd:green:system", ++ .gpio = TL_WR1043ND_GPIO_LED_SYSTEM, ++ .active_low = 1, ++ }, { ++ .name = "tl-wr1043nd:green:qss", ++ .gpio = TL_WR1043ND_GPIO_LED_QSS, ++ .active_low = 0, ++ }, { ++ .name = "tl-wr1043nd:green:wlan", ++ .gpio = TL_WR1043ND_GPIO_LED_WLAN, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button tl_wr1043nd_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_WR1043ND_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "qss", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_WR1043ND_GPIO_BTN_QSS, ++ .active_low = 1, ++ } ++}; ++ ++static struct rtl8366_platform_data tl_wr1043nd_rtl8366rb_data = { ++ .gpio_sda = TL_WR1043ND_GPIO_RTL8366_SDA, ++ .gpio_sck = TL_WR1043ND_GPIO_RTL8366_SCK, ++}; ++ ++static struct platform_device tl_wr1043nd_rtl8366rb_device = { ++ .name = RTL8366RB_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &tl_wr1043nd_rtl8366rb_data, ++ } ++}; ++ ++static void __init tl_wr1043nd_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_eth0_data.mii_bus_dev = &tl_wr1043nd_rtl8366rb_device.dev; ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_pll_data.pll_1000 = 0x1a000000; ++ ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_add_device_usb(); ++ ++ ar71xx_add_device_m25p80(&tl_wr1043nd_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr1043nd_leds_gpio), ++ tl_wr1043nd_leds_gpio); ++ ++ platform_device_register(&tl_wr1043nd_rtl8366rb_device); ++ ++ ar71xx_register_gpio_keys_polled(-1, TL_WR1043ND_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(tl_wr1043nd_gpio_keys), ++ tl_wr1043nd_gpio_keys); ++ ++ ar9xxx_add_device_wmac(eeprom, mac); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_TL_WR1043ND, "TL-WR1043ND", "TP-LINK TL-WR1043ND", ++ tl_wr1043nd_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr741nd.c linux-2.6.39/arch/mips/ar71xx/mach-tl-wr741nd.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr741nd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-tl-wr741nd.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,135 @@ ++/* ++ * TP-LINK TL-WR741ND board support ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap91-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++ ++#define TL_WR741ND_GPIO_LED_QSS 0 ++#define TL_WR741ND_GPIO_LED_SYSTEM 1 ++ ++#define TL_WR741ND_GPIO_BTN_RESET 11 ++#define TL_WR741ND_GPIO_BTN_QSS 12 ++ ++#define TL_WR741ND_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define TL_WR741ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR741ND_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition tl_wr741nd_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = 0x020000, ++ .size = 0x140000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x160000, ++ .size = 0x290000, ++ }, { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x020000, ++ .size = 0x3d0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data tl_wr741nd_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = tl_wr741nd_partitions, ++ .nr_parts = ARRAY_SIZE(tl_wr741nd_partitions), ++#endif ++}; ++ ++static struct gpio_led tl_wr741nd_leds_gpio[] __initdata = { ++ { ++ .name = "tl-wr741nd:green:system", ++ .gpio = TL_WR741ND_GPIO_LED_SYSTEM, ++ .active_low = 1, ++ }, { ++ .name = "tl-wr741nd:green:qss", ++ .gpio = TL_WR741ND_GPIO_LED_QSS, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button tl_wr741nd_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_WR741ND_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "qss", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_WR741ND_GPIO_BTN_QSS, ++ .active_low = 1, ++ } ++}; ++ ++static void __init tl_wr741nd_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ar71xx_add_device_m25p80(&tl_wr741nd_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr741nd_leds_gpio), ++ tl_wr741nd_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, TL_WR741ND_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(tl_wr741nd_gpio_keys), ++ tl_wr741nd_gpio_keys); ++ ++ ar71xx_eth1_data.has_ar7240_switch = 1; ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); ++ ++ /* WAN port */ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.phy_mask = BIT(4); ++ ++ /* LAN ports */ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_mdio(0x0); ++ ar71xx_add_device_eth(1); ++ ar71xx_add_device_eth(0); ++ ++ ap91_pci_setup_wmac_led_pin(1); ++ ++ ap91_pci_init(ee, mac); ++} ++MIPS_MACHINE(AR71XX_MACH_TL_WR741ND, "TL-WR741ND", "TP-LINK TL-WR741ND", ++ tl_wr741nd_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr841n.c linux-2.6.39/arch/mips/ar71xx/mach-tl-wr841n.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr841n.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-tl-wr841n.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,144 @@ ++/* ++ * TP-LINK TL-WR841N board support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-dsa.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-pb42-pci.h" ++#include "dev-leds-gpio.h" ++ ++#define TL_WR841ND_V1_GPIO_LED_SYSTEM 2 ++#define TL_WR841ND_V1_GPIO_LED_QSS_GREEN 4 ++#define TL_WR841ND_V1_GPIO_LED_QSS_RED 5 ++ ++#define TL_WR841ND_V1_GPIO_BTN_RESET 3 ++#define TL_WR841ND_V1_GPIO_BTN_QSS 7 ++ ++#define TL_WR841ND_V1_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL \ ++ (3 * TL_WR841ND_V1_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition tl_wr841n_v1_partitions[] = { ++ { ++ .name = "redboot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = 0x020000, ++ .size = 0x140000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x160000, ++ .size = 0x280000, ++ }, { ++ .name = "config", ++ .offset = 0x3e0000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x020000, ++ .size = 0x3c0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data tl_wr841n_v1_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = tl_wr841n_v1_partitions, ++ .nr_parts = ARRAY_SIZE(tl_wr841n_v1_partitions), ++#endif ++}; ++ ++static struct gpio_led tl_wr841n_v1_leds_gpio[] __initdata = { ++ { ++ .name = "tl-wr841n:green:system", ++ .gpio = TL_WR841ND_V1_GPIO_LED_SYSTEM, ++ .active_low = 1, ++ }, { ++ .name = "tl-wr841n:red:qss", ++ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_RED, ++ }, { ++ .name = "tl-wr841n:green:qss", ++ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_GREEN, ++ } ++}; ++ ++static struct gpio_keys_button tl_wr841n_v1_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_WR841ND_V1_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "qss", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_WR841ND_V1_GPIO_BTN_QSS, ++ .active_low = 1, ++ } ++}; ++ ++static struct dsa_chip_data tl_wr841n_v1_dsa_chip = { ++ .port_names[0] = "wan", ++ .port_names[1] = "lan1", ++ .port_names[2] = "lan2", ++ .port_names[3] = "lan3", ++ .port_names[4] = "lan4", ++ .port_names[5] = "cpu", ++}; ++ ++static struct dsa_platform_data tl_wr841n_v1_dsa_data = { ++ .nr_chips = 1, ++ .chip = &tl_wr841n_v1_dsa_chip, ++}; ++ ++static void __init tl_wr841n_v1_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); ++ ++ ar71xx_add_device_mdio(0x0); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_add_device_dsa(0, &tl_wr841n_v1_dsa_data); ++ ++ ar71xx_add_device_m25p80(&tl_wr841n_v1_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v1_leds_gpio), ++ tl_wr841n_v1_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, TL_WR841ND_V1_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(tl_wr841n_v1_gpio_keys), ++ tl_wr841n_v1_gpio_keys); ++ ++ pb42_pci_init(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_TL_WR841N_V1, "TL-WR841N-v1.5", "TP-LINK TL-WR841N v1", ++ tl_wr841n_v1_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr941nd.c linux-2.6.39/arch/mips/ar71xx/mach-tl-wr941nd.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr941nd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-tl-wr941nd.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,147 @@ ++/* ++ * TP-LINK TL-WR941ND board support ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-dsa.h" ++#include "dev-m25p80.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++ ++#define TL_WR941ND_GPIO_LED_SYSTEM 2 ++#define TL_WR941ND_GPIO_LED_QSS_RED 4 ++#define TL_WR941ND_GPIO_LED_QSS_GREEN 5 ++#define TL_WR941ND_GPIO_LED_WLAN 9 ++ ++#define TL_WR941ND_GPIO_BTN_RESET 3 ++#define TL_WR941ND_GPIO_BTN_QSS 7 ++ ++#define TL_WR941ND_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define TL_WR941ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR941ND_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition tl_wr941nd_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = 0x020000, ++ .size = 0x140000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x160000, ++ .size = 0x290000, ++ }, { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x020000, ++ .size = 0x3d0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data tl_wr941nd_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = tl_wr941nd_partitions, ++ .nr_parts = ARRAY_SIZE(tl_wr941nd_partitions), ++#endif ++}; ++ ++static struct gpio_led tl_wr941nd_leds_gpio[] __initdata = { ++ { ++ .name = "tl-wr941nd:green:system", ++ .gpio = TL_WR941ND_GPIO_LED_SYSTEM, ++ .active_low = 1, ++ }, { ++ .name = "tl-wr941nd:red:qss", ++ .gpio = TL_WR941ND_GPIO_LED_QSS_RED, ++ }, { ++ .name = "tl-wr941nd:green:qss", ++ .gpio = TL_WR941ND_GPIO_LED_QSS_GREEN, ++ }, { ++ .name = "tl-wr941nd:green:wlan", ++ .gpio = TL_WR941ND_GPIO_LED_WLAN, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button tl_wr941nd_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_WR941ND_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "qss", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = TL_WR941ND_GPIO_BTN_QSS, ++ .active_low = 1, ++ } ++}; ++ ++static struct dsa_chip_data tl_wr941nd_dsa_chip = { ++ .port_names[0] = "wan", ++ .port_names[1] = "lan1", ++ .port_names[2] = "lan2", ++ .port_names[3] = "lan3", ++ .port_names[4] = "lan4", ++ .port_names[5] = "cpu", ++}; ++ ++static struct dsa_platform_data tl_wr941nd_dsa_data = { ++ .nr_chips = 1, ++ .chip = &tl_wr941nd_dsa_chip, ++}; ++ ++static void __init tl_wr941nd_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ar71xx_add_device_mdio(0x0); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_dsa(0, &tl_wr941nd_dsa_data); ++ ++ ar71xx_add_device_m25p80(&tl_wr941nd_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_leds_gpio), ++ tl_wr941nd_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, TL_WR941ND_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(tl_wr941nd_gpio_keys), ++ tl_wr941nd_gpio_keys); ++ ar9xxx_add_device_wmac(eeprom, mac); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_TL_WR941ND, "TL-WR941ND", "TP-LINK TL-WR941ND", ++ tl_wr941nd_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-ubnt.c linux-2.6.39/arch/mips/ar71xx/mach-ubnt.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-ubnt.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-ubnt.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,333 @@ ++/* ++ * Ubiquiti RouterStation support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * Copyright (C) 2008 Ubiquiti ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap91-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-pb42-pci.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++ ++#define UBNT_RS_GPIO_LED_RF 2 ++#define UBNT_RS_GPIO_SW4 8 ++ ++#define UBNT_LS_SR71_GPIO_LED_D25 0 ++#define UBNT_LS_SR71_GPIO_LED_D26 1 ++#define UBNT_LS_SR71_GPIO_LED_D24 2 ++#define UBNT_LS_SR71_GPIO_LED_D23 4 ++#define UBNT_LS_SR71_GPIO_LED_D22 5 ++#define UBNT_LS_SR71_GPIO_LED_D27 6 ++#define UBNT_LS_SR71_GPIO_LED_D28 7 ++ ++#define UBNT_M_GPIO_LED_L1 0 ++#define UBNT_M_GPIO_LED_L2 1 ++#define UBNT_M_GPIO_LED_L3 11 ++#define UBNT_M_GPIO_LED_L4 7 ++#define UBNT_M_GPIO_BTN_RESET 12 ++ ++#define UBNT_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define UBNT_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_KEYS_POLL_INTERVAL) ++ ++static struct gpio_led ubnt_rs_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:green:rf", ++ .gpio = UBNT_RS_GPIO_LED_RF, ++ .active_low = 0, ++ } ++}; ++ ++static struct gpio_led ubnt_ls_sr71_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:green:d22", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D22, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:d23", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D23, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:d24", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D24, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:red:d25", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D25, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:red:d26", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D26, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:d27", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D27, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:d28", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D28, ++ .active_low = 0, ++ } ++}; ++ ++static struct gpio_led ubnt_m_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:red:link1", ++ .gpio = UBNT_M_GPIO_LED_L1, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:orange:link2", ++ .gpio = UBNT_M_GPIO_LED_L2, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:link3", ++ .gpio = UBNT_M_GPIO_LED_L3, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:link4", ++ .gpio = UBNT_M_GPIO_LED_L4, ++ .active_low = 0, ++ } ++}; ++ ++static struct gpio_keys_button ubnt_gpio_keys[] __initdata = { ++ { ++ .desc = "sw4", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = UBNT_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = UBNT_RS_GPIO_SW4, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button ubnt_m_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = UBNT_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = UBNT_M_GPIO_BTN_RESET, ++ .active_low = 1, ++ } ++}; ++ ++static void __init ubnt_generic_setup(void) ++{ ++ ar71xx_add_device_m25p80(NULL); ++ ++ ar71xx_register_gpio_keys_polled(-1, UBNT_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_gpio_keys), ++ ubnt_gpio_keys); ++ ++ pb42_pci_init(); ++} ++ ++/* ++ * There is Secondary MAC address duplicate problem with some UBNT HW batches. ++ * Do not increase Secondary MAC address by 1 but do workaround ++ * with 'Locally Administrated' bit. ++ */ ++static void __init ubnt_init_secondary_mac(unsigned char *mac_base) ++{ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac_base, 0); ++ ar71xx_eth1_data.mac_addr[0] |= 0x02; ++} ++ ++#define UBNT_RS_WAN_PHYMASK BIT(20) ++#define UBNT_RS_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) ++ ++static void __init ubnt_rs_setup(void) ++{ ++ ubnt_generic_setup(); ++ ++ ar71xx_add_device_mdio(~(UBNT_RS_WAN_PHYMASK | UBNT_RS_LAN_PHYMASK)); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = UBNT_RS_WAN_PHYMASK; ++ ++ ubnt_init_secondary_mac(ar71xx_mac_base); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_100; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_usb(); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), ++ ubnt_rs_leds_gpio); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_UBNT_RS, "UBNT-RS", "Ubiquiti RouterStation", ++ ubnt_rs_setup); ++ ++#define UBNT_RSPRO_WAN_PHYMASK BIT(4) ++#define UBNT_RSPRO_LAN_PHYMASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) ++ ++static void __init ubnt_rspro_setup(void) ++{ ++ ubnt_generic_setup(); ++ ++ ar71xx_add_device_mdio(~(UBNT_RSPRO_WAN_PHYMASK | ++ UBNT_RSPRO_LAN_PHYMASK)); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.phy_mask = UBNT_RSPRO_WAN_PHYMASK; ++ ++ ubnt_init_secondary_mac(ar71xx_mac_base); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.phy_mask = UBNT_RSPRO_LAN_PHYMASK; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_usb(); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), ++ ubnt_rs_leds_gpio); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_UBNT_RSPRO, "UBNT-RSPRO", "Ubiquiti RouterStation Pro", ++ ubnt_rspro_setup); ++ ++static void __init ubnt_lsx_setup(void) ++{ ++ ubnt_generic_setup(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_UBNT_LSX, "UBNT-LSX", "Ubiquiti LSX", ubnt_lsx_setup); ++ ++#define UBNT_LSSR71_PHY_MASK BIT(1) ++ ++static void __init ubnt_lssr71_setup(void) ++{ ++ ubnt_generic_setup(); ++ ++ ar71xx_add_device_mdio(~UBNT_LSSR71_PHY_MASK); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = UBNT_LSSR71_PHY_MASK; ++ ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_ls_sr71_leds_gpio), ++ ubnt_ls_sr71_leds_gpio); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_UBNT_LSSR71, "UBNT-LS-SR71", "Ubiquiti LS-SR71", ++ ubnt_lssr71_setup); ++ ++#define UBNT_M_WAN_PHYMASK BIT(4) ++ ++static void __init ubnt_m_setup(void) ++{ ++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ar71xx_add_device_m25p80(NULL); ++ ++ ar71xx_add_device_mdio(~UBNT_M_WAN_PHYMASK); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac1, 0); ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac2, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.phy_mask = UBNT_M_WAN_PHYMASK; ++ ++ ar71xx_add_device_eth(0); ++ ++ ap91_pci_init(ee, NULL); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_m_leds_gpio), ++ ubnt_m_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, UBNT_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_m_gpio_keys), ++ ubnt_m_gpio_keys); ++} ++ ++static void __init ubnt_rocket_m_setup(void) ++{ ++ ubnt_m_setup(); ++ ar71xx_add_device_usb(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M", ++ ubnt_m_setup); ++MIPS_MACHINE(AR71XX_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M", ++ ubnt_rocket_m_setup); ++ ++/* TODO detect the second ethernet port and use one ++ init function for all Ubiquiti MIMO series products */ ++static void __init ubnt_nano_m_setup(void) ++{ ++ ubnt_m_setup(); ++ ++ ar71xx_eth1_data.has_ar7240_switch = 1; ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_eth(1); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M", ++ ubnt_nano_m_setup); ++ ++static struct gpio_led ubnt_unifi_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:orange:dome", ++ .gpio = 1, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:dome", ++ .gpio = 0, ++ .active_low = 0, ++ } ++}; ++ ++static void __init ubnt_unifi_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ar71xx_add_device_m25p80(NULL); ++ ++ ar71xx_add_device_mdio(~UBNT_M_WAN_PHYMASK); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.phy_mask = UBNT_M_WAN_PHYMASK; ++ ++ ar71xx_add_device_eth(0); ++ ++ ap91_pci_init(ee, NULL); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_leds_gpio), ++ ubnt_unifi_leds_gpio); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_UBNT_UNIFI, "UBNT-XM", "Ubiquiti UniFi", ++ ubnt_unifi_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wndr3700.c linux-2.6.39/arch/mips/ar71xx/mach-wndr3700.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-wndr3700.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-wndr3700.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,290 @@ ++/* ++ * Netgear WNDR3700 board support ++ * ++ * Copyright (C) 2009 Marco Porsch ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap94-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++ ++#define WNDR3700_GPIO_LED_WPS_ORANGE 0 ++#define WNDR3700_GPIO_LED_POWER_ORANGE 1 ++#define WNDR3700_GPIO_LED_POWER_GREEN 2 ++#define WNDR3700_GPIO_LED_WPS_GREEN 4 ++#define WNDR3700_GPIO_LED_WAN_GREEN 6 ++ ++#define WNDR3700_GPIO_BTN_WPS 3 ++#define WNDR3700_GPIO_BTN_RESET 8 ++#define WNDR3700_GPIO_BTN_WIFI 11 ++ ++#define WNDR3700_GPIO_RTL8366_SDA 5 ++#define WNDR3700_GPIO_RTL8366_SCK 7 ++ ++#define WNDR3700_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define WNDR3700_KEYS_DEBOUNCE_INTERVAL (3 * WNDR3700_KEYS_POLL_INTERVAL) ++ ++#define WNDR3700_ETH0_MAC_OFFSET 0 ++#define WNDR3700_ETH1_MAC_OFFSET 0x6 ++ ++#define WNDR3700_WMAC0_MAC_OFFSET 0 ++#define WNDR3700_WMAC1_MAC_OFFSET 0xc ++#define WNDR3700_CALDATA0_OFFSET 0x1000 ++#define WNDR3700_CALDATA1_OFFSET 0x5000 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition wndr3700_partitions[] = { ++ { ++ .name = "uboot", ++ .offset = 0, ++ .size = 0x050000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "env", ++ .offset = 0x050000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "rootfs", ++ .offset = 0x070000, ++ .size = 0x720000, ++ }, { ++ .name = "config", ++ .offset = 0x790000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "config_bak", ++ .offset = 0x7a0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "pot", ++ .offset = 0x7b0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "traffic_meter", ++ .offset = 0x7c0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "language", ++ .offset = 0x7d0000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "caldata", ++ .offset = 0x7f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } ++}; ++ ++static struct mtd_partition wndr3700v2_partitions[] = { ++ { ++ .name = "uboot", ++ .offset = 0, ++ .size = 0x050000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "env", ++ .offset = 0x050000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "rootfs", ++ .offset = 0x070000, ++ .size = 0xe40000, ++ }, { ++ .name = "config", ++ .offset = 0xeb0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "config_bak", ++ .offset = 0xec0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "pot", ++ .offset = 0xed0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "traffic_meter", ++ .offset = 0xee0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "language", ++ .offset = 0xef0000, ++ .size = 0x100000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "caldata", ++ .offset = 0xff0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } ++}; ++#define wndr3700_num_partitions ARRAY_SIZE(wndr3700_partitions) ++#define wndr3700v2_num_partitions ARRAY_SIZE(wndr3700v2_partitions) ++#else ++#define wndr3700_partitions NULL ++#define wndr3700_num_partitions 0 ++#define wndr3700v2_partitions NULL ++#define wndr3700v2_num_partitions 0 ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data wndr3700_flash_data; ++ ++static struct gpio_led wndr3700_leds_gpio[] __initdata = { ++ { ++ .name = "wndr3700:green:power", ++ .gpio = WNDR3700_GPIO_LED_POWER_GREEN, ++ .active_low = 1, ++ }, { ++ .name = "wndr3700:orange:power", ++ .gpio = WNDR3700_GPIO_LED_POWER_ORANGE, ++ .active_low = 1, ++ }, { ++ .name = "wndr3700:green:wps", ++ .gpio = WNDR3700_GPIO_LED_WPS_GREEN, ++ .active_low = 1, ++ }, { ++ .name = "wndr3700:orange:wps", ++ .gpio = WNDR3700_GPIO_LED_WPS_ORANGE, ++ .active_low = 1, ++ }, { ++ .name = "wndr3700:green:wan", ++ .gpio = WNDR3700_GPIO_LED_WAN_GREEN, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button wndr3700_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WNDR3700_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WNDR3700_GPIO_BTN_WPS, ++ .active_low = 1, ++ }, { ++ .desc = "wifi", ++ .type = EV_KEY, ++ .code = BTN_2, ++ .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WNDR3700_GPIO_BTN_WIFI, ++ .active_low = 1, ++ } ++}; ++ ++static struct rtl8366_platform_data wndr3700_rtl8366s_data = { ++ .gpio_sda = WNDR3700_GPIO_RTL8366_SDA, ++ .gpio_sck = WNDR3700_GPIO_RTL8366_SCK, ++}; ++ ++static struct platform_device wndr3700_rtl8366s_device = { ++ .name = RTL8366S_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &wndr3700_rtl8366s_data, ++ } ++}; ++ ++static void __init wndr3700_common_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ++ art + WNDR3700_ETH0_MAC_OFFSET, 0); ++ ar71xx_eth0_pll_data.pll_1000 = 0x11110000; ++ ar71xx_eth0_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ++ art + WNDR3700_ETH1_MAC_OFFSET, 0); ++ ar71xx_eth1_pll_data.pll_1000 = 0x11110000; ++ ar71xx_eth1_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.phy_mask = 0x10; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_usb(); ++ ++ ar71xx_add_device_m25p80(&wndr3700_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wndr3700_leds_gpio), ++ wndr3700_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, WNDR3700_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(wndr3700_gpio_keys), ++ wndr3700_gpio_keys); ++ ++ platform_device_register(&wndr3700_rtl8366s_device); ++ platform_device_register_simple("wndr3700-led-usb", -1, NULL, 0); ++ ++ ap94_pci_setup_wmac_led_pin(0, 5); ++ ap94_pci_setup_wmac_led_pin(1, 5); ++ ++ /* 2.4 GHz uses the first fixed antenna group (1, 0, 1, 0) */ ++ ap94_pci_setup_wmac_gpio(0, (0xf << 6), (0xa << 6)); ++ ++ /* 5 GHz uses the second fixed antenna group (0, 1, 1, 0) */ ++ ap94_pci_setup_wmac_gpio(1, (0xf << 6), (0x6 << 6)); ++ ++ ap94_pci_init(art + WNDR3700_CALDATA0_OFFSET, ++ art + WNDR3700_WMAC0_MAC_OFFSET, ++ art + WNDR3700_CALDATA1_OFFSET, ++ art + WNDR3700_WMAC1_MAC_OFFSET); ++} ++ ++static void __init wndr3700_setup(void) ++{ ++ wndr3700_flash_data.parts = wndr3700_partitions, ++ wndr3700_flash_data.nr_parts = wndr3700_num_partitions, ++ wndr3700_common_setup(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_WNDR3700, "WNDR3700", "NETGEAR WNDR3700", ++ wndr3700_setup); ++ ++static void __init wndr3700v2_setup(void) ++{ ++ wndr3700_flash_data.parts = wndr3700v2_partitions, ++ wndr3700_flash_data.nr_parts = wndr3700v2_num_partitions, ++ wndr3700_common_setup(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_WNDR3700V2, "WNDR3700v2", "NETGEAR WNDR3700v2", ++ wndr3700v2_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wnr2000.c linux-2.6.39/arch/mips/ar71xx/mach-wnr2000.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-wnr2000.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-wnr2000.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,150 @@ ++/* ++ * NETGEAR WNR2000 board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * Copyright (C) 2008-2009 Andy Boyett ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++ ++#define WNR2000_GPIO_LED_PWR_GREEN 14 ++#define WNR2000_GPIO_LED_PWR_AMBER 7 ++#define WNR2000_GPIO_LED_WPS 4 ++#define WNR2000_GPIO_LED_WLAN 6 ++#define WNR2000_GPIO_BTN_RESET 21 ++#define WNR2000_GPIO_BTN_WPS 8 ++ ++#define WNR2000_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define WNR2000_KEYS_DEBOUNCE_INTERVAL (3 * WNR2000_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition wnr2000_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x050000, ++ .size = 0x240000, ++ }, { ++ .name = "user-config", ++ .offset = 0x290000, ++ .size = 0x010000, ++ }, { ++ .name = "uImage", ++ .offset = 0x2a0000, ++ .size = 0x120000, ++ }, { ++ .name = "language_table", ++ .offset = 0x3c0000, ++ .size = 0x020000, ++ }, { ++ .name = "rootfs_checksum", ++ .offset = 0x3e0000, ++ .size = 0x010000, ++ }, { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data wnr2000_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = wnr2000_partitions, ++ .nr_parts = ARRAY_SIZE(wnr2000_partitions), ++#endif ++}; ++ ++static struct gpio_led wnr2000_leds_gpio[] __initdata = { ++ { ++ .name = "wnr2000:green:power", ++ .gpio = WNR2000_GPIO_LED_PWR_GREEN, ++ .active_low = 1, ++ }, { ++ .name = "wnr2000:amber:power", ++ .gpio = WNR2000_GPIO_LED_PWR_AMBER, ++ .active_low = 1, ++ }, { ++ .name = "wnr2000:green:wps", ++ .gpio = WNR2000_GPIO_LED_WPS, ++ .active_low = 1, ++ }, { ++ .name = "wnr2000:blue:wlan", ++ .gpio = WNR2000_GPIO_LED_WLAN, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button wnr2000_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WNR2000_GPIO_BTN_RESET, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WNR2000_GPIO_BTN_WPS, ++ } ++}; ++ ++static void __init wnr2000_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ar71xx_add_device_mdio(0x0); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.has_ar8216 = 1; ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = 0x10; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_m25p80(&wnr2000_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wnr2000_leds_gpio), ++ wnr2000_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, WNR2000_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(wnr2000_gpio_keys), ++ wnr2000_gpio_keys); ++ ++ ++ ar9xxx_add_device_wmac(eeprom, NULL); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_WNR2000, "WNR2000", "NETGEAR WNR2000", wnr2000_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wp543.c linux-2.6.39/arch/mips/ar71xx/mach-wp543.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-wp543.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-wp543.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,101 @@ ++/* ++ * Compex WP543/WPJ543 board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-pb42-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++ ++#define WP543_GPIO_SW6 2 ++#define WP543_GPIO_LED_1 3 ++#define WP543_GPIO_LED_2 4 ++#define WP543_GPIO_LED_WLAN 5 ++#define WP543_GPIO_LED_CONN 6 ++#define WP543_GPIO_LED_DIAG 7 ++#define WP543_GPIO_SW4 8 ++ ++#define WP543_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define WP543_KEYS_DEBOUNCE_INTERVAL (3 * WP543_KEYS_POLL_INTERVAL) ++ ++static struct gpio_led wp543_leds_gpio[] __initdata = { ++ { ++ .name = "wp543:green:led1", ++ .gpio = WP543_GPIO_LED_1, ++ .active_low = 1, ++ }, { ++ .name = "wp543:green:led2", ++ .gpio = WP543_GPIO_LED_2, ++ .active_low = 1, ++ }, { ++ .name = "wp543:green:wlan", ++ .gpio = WP543_GPIO_LED_WLAN, ++ .active_low = 1, ++ }, { ++ .name = "wp543:green:conn", ++ .gpio = WP543_GPIO_LED_CONN, ++ .active_low = 1, ++ }, { ++ .name = "wp543:green:diag", ++ .gpio = WP543_GPIO_LED_DIAG, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button wp543_gpio_keys[] __initdata = { ++ { ++ .desc = "sw6", ++ .type = EV_KEY, ++ .code = BTN_0, ++ .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WP543_GPIO_SW6, ++ }, { ++ .desc = "sw4", ++ .type = EV_KEY, ++ .code = BTN_1, ++ .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WP543_GPIO_SW4, ++ } ++}; ++ ++static void __init wp543_setup(void) ++{ ++ ar71xx_add_device_m25p80(NULL); ++ ++ ar71xx_add_device_mdio(0xfffffff7); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = 0x08; ++ ar71xx_eth0_data.reset_bit = RESET_MODULE_GE0_MAC | ++ RESET_MODULE_GE0_PHY; ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_add_device_usb(); ++ ++ pb42_pci_init(); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wp543_leds_gpio), ++ wp543_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, WP543_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(wp543_gpio_keys), ++ wp543_gpio_keys); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_WP543, "WP543", "Compex WP543", wp543_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wrt160nl.c linux-2.6.39/arch/mips/ar71xx/mach-wrt160nl.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-wrt160nl.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-wrt160nl.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,161 @@ ++/* ++ * Linksys WRT160NL board support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++#include "nvram.h" ++ ++#define WRT160NL_GPIO_LED_POWER 14 ++#define WRT160NL_GPIO_LED_WPS_AMBER 9 ++#define WRT160NL_GPIO_LED_WPS_BLUE 8 ++#define WRT160NL_GPIO_LED_WLAN 6 ++ ++#define WRT160NL_GPIO_BTN_WPS 7 ++#define WRT160NL_GPIO_BTN_RESET 21 ++ ++#define WRT160NL_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define WRT160NL_KEYS_DEBOUNCE_INTERVAL (3 * WRT160NL_KEYS_POLL_INTERVAL) ++ ++#define WRT160NL_NVRAM_ADDR 0x1f7e0000 ++#define WRT160NL_NVRAM_SIZE 0x10000 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition wrt160nl_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = 0x040000, ++ .size = 0x0e0000, ++ }, { ++ .name = "filesytem", ++ .offset = 0x120000, ++ .size = 0x6c0000, ++ }, { ++ .name = "nvram", ++ .offset = 0x7e0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "ART", ++ .offset = 0x7f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x040000, ++ .size = 0x7a0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data wrt160nl_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = wrt160nl_partitions, ++ .nr_parts = ARRAY_SIZE(wrt160nl_partitions), ++#endif ++}; ++ ++static struct gpio_led wrt160nl_leds_gpio[] __initdata = { ++ { ++ .name = "wrt160nl:blue:power", ++ .gpio = WRT160NL_GPIO_LED_POWER, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, { ++ .name = "wrt160nl:amber:wps", ++ .gpio = WRT160NL_GPIO_LED_WPS_AMBER, ++ .active_low = 1, ++ }, { ++ .name = "wrt160nl:blue:wps", ++ .gpio = WRT160NL_GPIO_LED_WPS_BLUE, ++ .active_low = 1, ++ }, { ++ .name = "wrt160nl:blue:wlan", ++ .gpio = WRT160NL_GPIO_LED_WLAN, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button wrt160nl_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WRT160NL_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WRT160NL_GPIO_BTN_WPS, ++ .active_low = 1, ++ } ++}; ++ ++static void __init wrt160nl_setup(void) ++{ ++ const char *nvram = (char *) KSEG1ADDR(WRT160NL_NVRAM_ADDR); ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ u8 mac[6]; ++ ++ if (nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, ++ "lan_hwaddr=", mac) == 0) { ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); ++ } ++ ++ ar71xx_add_device_mdio(0x0); ++ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.phy_mask = 0x01; ++ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = 0x10; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_m25p80(&wrt160nl_flash_data); ++ ++ ar71xx_add_device_usb(); ++ ++ if (nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, ++ "wl0_hwaddr=", mac) == 0) ++ ar9xxx_add_device_wmac(eeprom, mac); ++ else ++ ar9xxx_add_device_wmac(eeprom, NULL); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wrt160nl_leds_gpio), ++ wrt160nl_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, WRT160NL_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(wrt160nl_gpio_keys), ++ wrt160nl_gpio_keys); ++ ++} ++ ++MIPS_MACHINE(AR71XX_MACH_WRT160NL, "WRT160NL", "Linksys WRT160NL", ++ wrt160nl_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wrt400n.c linux-2.6.39/arch/mips/ar71xx/mach-wrt400n.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-wrt400n.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-wrt400n.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,164 @@ ++/* ++ * Linksys WRT400N board support ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * Copyright (C) 2009 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-ap94-pci.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++ ++#define WRT400N_GPIO_LED_ORANGE 5 ++#define WRT400N_GPIO_LED_GREEN 4 ++#define WRT400N_GPIO_LED_POWER 1 ++#define WRT400N_GPIO_LED_WLAN 0 ++ ++#define WRT400N_GPIO_BTN_RESET 8 ++#define WRT400N_GPIO_BTN_WLSEC 3 ++ ++#define WRT400N_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define WRT400N_KEYS_DEBOUNE_INTERVAL (3 * WRT400N_KEYS_POLL_INTERVAL) ++ ++#define WRT400N_MAC_ADDR_OFFSET 0x120c ++#define WRT400N_CALDATA0_OFFSET 0x1000 ++#define WRT400N_CALDATA1_OFFSET 0x5000 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition wrt400n_partitions[] = { ++ { ++ .name = "uboot", ++ .offset = 0, ++ .size = 0x030000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "env", ++ .offset = 0x030000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "linux", ++ .offset = 0x040000, ++ .size = 0x140000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x180000, ++ .size = 0x630000, ++ }, { ++ .name = "nvram", ++ .offset = 0x7b0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "factory", ++ .offset = 0x7c0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "language", ++ .offset = 0x7d0000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "caldata", ++ .offset = 0x7f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x040000, ++ .size = 0x770000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data wrt400n_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = wrt400n_partitions, ++ .nr_parts = ARRAY_SIZE(wrt400n_partitions), ++#endif ++}; ++ ++static struct gpio_led wrt400n_leds_gpio[] __initdata = { ++ { ++ .name = "wrt400n:green:status", ++ .gpio = WRT400N_GPIO_LED_GREEN, ++ .active_low = 1, ++ }, { ++ .name = "wrt400n:amber:aoss", ++ .gpio = WRT400N_GPIO_LED_ORANGE, ++ .active_low = 1, ++ }, { ++ .name = "wrt400n:green:wlan", ++ .gpio = WRT400N_GPIO_LED_WLAN, ++ .active_low = 1, ++ }, { ++ .name = "wrt400n:green:power", ++ .gpio = WRT400N_GPIO_LED_POWER, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button wrt400n_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, ++ .gpio = WRT400N_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wlsec", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, ++ .gpio = WRT400N_GPIO_BTN_WLSEC, ++ .active_low = 1, ++ } ++}; ++ ++static void __init wrt400n_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *mac = art + WRT400N_MAC_ADDR_OFFSET; ++ ++ ar71xx_add_device_mdio(0x0); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 1); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 2); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = 0x10; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_m25p80(&wrt400n_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio), ++ wrt400n_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, WRT400N_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(wrt400n_gpio_keys), ++ wrt400n_gpio_keys); ++ ++ ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL, ++ art + WRT400N_CALDATA1_OFFSET, NULL); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wzr-hp-ag300h.c linux-2.6.39/arch/mips/ar71xx/mach-wzr-hp-ag300h.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-wzr-hp-ag300h.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-wzr-hp-ag300h.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,231 @@ ++/* ++ * Buffalo WZR-HP-AG300H board support ++ * ++ * Copyright (C) 2011 Felix Fietkau ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-ap94-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-m25p80.h" ++#include "dev-usb.h" ++ ++#define WZRHPAG300H_MAC_OFFSET 0x20c ++#define WZRHPAG300H_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPAG300H_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition wzrhpag300h_flash_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x0040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "u-boot-env", ++ .offset = 0x0040000, ++ .size = 0x0010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "art", ++ .offset = 0x0050000, ++ .size = 0x0010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = 0x0060000, ++ .size = 0x0100000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x0160000, ++ .size = 0x1e90000, ++ }, { ++ .name = "user_property", ++ .offset = 0x1ff0000, ++ .size = 0x0010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x0060000, ++ .size = 0x1f90000, ++ } ++}; ++ ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct mtd_info *concat_devs[2] = { NULL, NULL }; ++static struct work_struct mtd_concat_work; ++ ++static void mtd_concat_add_work(struct work_struct *work) ++{ ++ struct mtd_info *mtd; ++ ++ mtd = mtd_concat_create(concat_devs, ARRAY_SIZE(concat_devs), "flash"); ++ ++#ifdef CONFIG_MTD_PARTITIONS ++ add_mtd_partitions(mtd, wzrhpag300h_flash_partitions, ++ ARRAY_SIZE(wzrhpag300h_flash_partitions)); ++#else ++ add_mtd_device(mtd); ++#endif ++} ++ ++static void mtd_concat_add(struct mtd_info *mtd) ++{ ++ static bool registered = false; ++ ++ if (registered) ++ return; ++ ++ if (!strcmp(mtd->name, "spi0.0")) ++ concat_devs[0] = mtd; ++ else if (!strcmp(mtd->name, "spi0.1")) ++ concat_devs[1] = mtd; ++ else ++ return; ++ ++ if (!concat_devs[0] || !concat_devs[1]) ++ return; ++ ++ registered = true; ++ INIT_WORK(&mtd_concat_work, mtd_concat_add_work); ++ schedule_work(&mtd_concat_work); ++} ++ ++static void mtd_concat_remove(struct mtd_info *mtd) ++{ ++} ++ ++static void add_mtd_concat_notifier(void) ++{ ++ static struct mtd_notifier not = { ++ .add = mtd_concat_add, ++ .remove = mtd_concat_remove, ++ }; ++ ++ register_mtd_user(¬); ++} ++ ++static struct gpio_led wzrhpag300h_leds_gpio[] __initdata = { ++ { ++ .name = "wzr-hp-ag300h:red:diag", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++}; ++ ++ ++static struct gpio_keys_button wzrhpag300h_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = 11, ++ .active_low = 1, ++ }, { ++ .desc = "usb", ++ .type = EV_KEY, ++ .code = BTN_2, ++ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = 3, ++ .active_low = 1, ++ }, { ++ .desc = "aoss", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = 5, ++ .active_low = 1, ++ }, { ++ .desc = "router_auto", ++ .type = EV_KEY, ++ .code = BTN_6, ++ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = 6, ++ .active_low = 1, ++ }, { ++ .desc = "router_off", ++ .type = EV_KEY, ++ .code = BTN_5, ++ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = 7, ++ .active_low = 1, ++ } ++}; ++ ++static struct spi_board_info ar71xx_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "m25p80", ++ }, ++ { ++ .bus_num = 0, ++ .chip_select = 1, ++ .max_speed_hz = 25000000, ++ .modalias = "m25p80", ++ } ++}; ++ ++static void __init wzrhpag300h_setup(void) ++{ ++ u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1f051000); ++ u8 *eeprom2 = (u8 *) KSEG1ADDR(0x1f055000); ++ u8 *mac1 = eeprom1 + WZRHPAG300H_MAC_OFFSET; ++ u8 *mac2 = eeprom2 + WZRHPAG300H_MAC_OFFSET; ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac1, 0); ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac2, 1); ++ ++ ar71xx_add_device_mdio(~(BIT(0) | BIT(4))); ++ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.phy_mask = BIT(0); ++ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.phy_mask = BIT(4); ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_usb(); ++ gpio_request(2, "usb"); ++ gpio_direction_output(2, 1); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wzrhpag300h_leds_gpio), ++ wzrhpag300h_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, WZRHPAG300H_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(wzrhpag300h_gpio_keys), ++ wzrhpag300h_gpio_keys); ++ ++ ar71xx_add_device_spi(NULL, ar71xx_spi_info, ++ ARRAY_SIZE(ar71xx_spi_info)); ++ ++ add_mtd_concat_notifier(); ++ ++ ap94_pci_init(eeprom1, mac1, eeprom2, mac2); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_WZR_HP_AG300H, "WZR-HP-AG300H", ++ "Buffalo WZR-HP-AG300H", wzrhpag300h_setup); ++ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wzr-hp-g300nh.c linux-2.6.39/arch/mips/ar71xx/mach-wzr-hp-g300nh.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-wzr-hp-g300nh.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-wzr-hp-g300nh.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,292 @@ ++/* ++ * Buffalo WZR-HP-G300NH board support ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-ar9xxx-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++ ++#define WZRHPG300NH_GPIO_LED_USB 0 ++#define WZRHPG300NH_GPIO_LED_DIAG 1 ++#define WZRHPG300NH_GPIO_LED_WIRELESS 6 ++#define WZRHPG300NH_GPIO_LED_SECURITY 17 ++#define WZRHPG300NH_GPIO_LED_ROUTER 18 ++ ++#define WZRHPG300NH_GPIO_RTL8366_SDA 19 ++#define WZRHPG300NH_GPIO_RTL8366_SCK 20 ++ ++#define WZRHPG300NH_GPIO_74HC153_S0 9 ++#define WZRHPG300NH_GPIO_74HC153_S1 11 ++#define WZRHPG300NH_GPIO_74HC153_1Y 12 ++#define WZRHPG300NH_GPIO_74HC153_2Y 14 ++ ++#define WZRHPG300NH_GPIO_EXP_BASE 32 ++#define WZRHPG300NH_GPIO_BTN_AOSS (WZRHPG300NH_GPIO_EXP_BASE + 0) ++#define WZRHPG300NH_GPIO_BTN_RESET (WZRHPG300NH_GPIO_EXP_BASE + 1) ++#define WZRHPG300NH_GPIO_BTN_ROUTER_ON (WZRHPG300NH_GPIO_EXP_BASE + 2) ++#define WZRHPG300NH_GPIO_BTN_QOS_ON (WZRHPG300NH_GPIO_EXP_BASE + 3) ++#define WZRHPG300NH_GPIO_BTN_USB (WZRHPG300NH_GPIO_EXP_BASE + 5) ++#define WZRHPG300NH_GPIO_BTN_ROUTER_AUTO (WZRHPG300NH_GPIO_EXP_BASE + 6) ++#define WZRHPG300NH_GPIO_BTN_QOS_OFF (WZRHPG300NH_GPIO_EXP_BASE + 7) ++ ++#define WZRHPG300NH_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG300NH_KEYS_POLL_INTERVAL) ++ ++#define WZRHPG300NH_MAC_OFFSET 0x20c ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition wzrhpg300nh_flash_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x0040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "u-boot-env", ++ .offset = 0x0040000, ++ .size = 0x0020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = 0x0060000, ++ .size = 0x0100000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x0160000, ++ .size = 0x1e60000, ++ }, { ++ .name = "user_property", ++ .offset = 0x1fc0000, ++ .size = 0x0020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "art", ++ .offset = 0x1fe0000, ++ .size = 0x0020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x0060000, ++ .size = 0x1f60000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct ar91xx_flash_platform_data wzrhpg300nh_flash_data = { ++ .width = 2, ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = wzrhpg300nh_flash_partitions, ++ .nr_parts = ARRAY_SIZE(wzrhpg300nh_flash_partitions), ++#endif ++}; ++ ++#define WZRHPG300NH_FLASH_BASE 0x1e000000 ++#define WZRHPG300NH_FLASH_SIZE (32 * 1024 * 1024) ++ ++static struct resource wzrhpg300nh_flash_resources[] = { ++ [0] = { ++ .start = WZRHPG300NH_FLASH_BASE, ++ .end = WZRHPG300NH_FLASH_BASE + WZRHPG300NH_FLASH_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static struct platform_device wzrhpg300nh_flash_device = { ++ .name = "ar91xx-flash", ++ .id = -1, ++ .resource = wzrhpg300nh_flash_resources, ++ .num_resources = ARRAY_SIZE(wzrhpg300nh_flash_resources), ++ .dev = { ++ .platform_data = &wzrhpg300nh_flash_data, ++ } ++}; ++ ++static struct gpio_led wzrhpg300nh_leds_gpio[] __initdata = { ++ { ++ .name = "wzr-hp-g300nh:orange:security", ++ .gpio = WZRHPG300NH_GPIO_LED_SECURITY, ++ .active_low = 1, ++ }, { ++ .name = "wzr-hp-g300nh:green:wireless", ++ .gpio = WZRHPG300NH_GPIO_LED_WIRELESS, ++ .active_low = 1, ++ }, { ++ .name = "wzr-hp-g300nh:green:router", ++ .gpio = WZRHPG300NH_GPIO_LED_ROUTER, ++ .active_low = 1, ++ }, { ++ .name = "wzr-hp-g300nh:red:diag", ++ .gpio = WZRHPG300NH_GPIO_LED_DIAG, ++ .active_low = 1, ++ }, { ++ .name = "wzr-hp-g300nh:blue:usb", ++ .gpio = WZRHPG300NH_GPIO_LED_USB, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_keys_button wzrhpg300nh_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WZRHPG300NH_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "aoss", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WZRHPG300NH_GPIO_BTN_AOSS, ++ .active_low = 1, ++ }, { ++ .desc = "usb", ++ .type = EV_KEY, ++ .code = BTN_2, ++ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WZRHPG300NH_GPIO_BTN_USB, ++ .active_low = 1, ++ }, { ++ .desc = "qos_on", ++ .type = EV_KEY, ++ .code = BTN_3, ++ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WZRHPG300NH_GPIO_BTN_QOS_ON, ++ .active_low = 0, ++ }, { ++ .desc = "qos_off", ++ .type = EV_KEY, ++ .code = BTN_4, ++ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WZRHPG300NH_GPIO_BTN_QOS_OFF, ++ .active_low = 0, ++ }, { ++ .desc = "router_on", ++ .type = EV_KEY, ++ .code = BTN_5, ++ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_ON, ++ .active_low = 0, ++ }, { ++ .desc = "router_auto", ++ .type = EV_KEY, ++ .code = BTN_6, ++ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_AUTO, ++ .active_low = 0, ++ } ++}; ++ ++static struct nxp_74hc153_platform_data wzrhpg300nh_74hc153_data = { ++ .gpio_base = WZRHPG300NH_GPIO_EXP_BASE, ++ .gpio_pin_s0 = WZRHPG300NH_GPIO_74HC153_S0, ++ .gpio_pin_s1 = WZRHPG300NH_GPIO_74HC153_S1, ++ .gpio_pin_1y = WZRHPG300NH_GPIO_74HC153_1Y, ++ .gpio_pin_2y = WZRHPG300NH_GPIO_74HC153_2Y, ++}; ++ ++static struct platform_device wzrhpg300nh_74hc153_device = { ++ .name = NXP_74HC153_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &wzrhpg300nh_74hc153_data, ++ } ++}; ++ ++static struct rtl8366_platform_data wzrhpg300nh_rtl8366_data = { ++ .gpio_sda = WZRHPG300NH_GPIO_RTL8366_SDA, ++ .gpio_sck = WZRHPG300NH_GPIO_RTL8366_SCK, ++}; ++ ++static struct platform_device wzrhpg300nh_rtl8366s_device = { ++ .name = RTL8366S_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &wzrhpg300nh_rtl8366_data, ++ } ++}; ++ ++static struct platform_device wzrhpg300nh_rtl8366rb_device = { ++ .name = RTL8366RB_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &wzrhpg300nh_rtl8366_data, ++ } ++}; ++ ++static void __init wzrhpg300nh_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ u8 *mac = eeprom + WZRHPG300NH_MAC_OFFSET; ++ bool hasrtl8366rb = false; ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); ++ ++ if (rtl8366_smi_detect(&wzrhpg300nh_rtl8366_data) == RTL8366_TYPE_RB) ++ hasrtl8366rb = true; ++ ++ if (hasrtl8366rb) { ++ ar71xx_eth0_pll_data.pll_1000 = 0x1f000000; ++ ar71xx_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev; ++ ar71xx_eth1_pll_data.pll_1000 = 0x100; ++ ar71xx_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev; ++ } else { ++ ar71xx_eth0_pll_data.pll_1000 = 0x1e000100; ++ ar71xx_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; ++ ar71xx_eth1_pll_data.pll_1000 = 0x1e000100; ++ ar71xx_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; ++ } ++ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.phy_mask = 0x10; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); ++ ++ ar71xx_add_device_usb(); ++ ar9xxx_add_device_wmac(eeprom, NULL); ++ ++ platform_device_register(&wzrhpg300nh_74hc153_device); ++ platform_device_register(&wzrhpg300nh_flash_device); ++ ++ if (hasrtl8366rb) ++ platform_device_register(&wzrhpg300nh_rtl8366rb_device); ++ else ++ platform_device_register(&wzrhpg300nh_rtl8366s_device); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh_leds_gpio), ++ wzrhpg300nh_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, WZRHPG300NH_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(wzrhpg300nh_gpio_keys), ++ wzrhpg300nh_gpio_keys); ++ ++} ++ ++MIPS_MACHINE(AR71XX_MACH_WZR_HP_G300NH, "WZR-HP-G300NH", ++ "Buffalo WZR-HP-G300NH", wzrhpg300nh_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-zcn-1523h.c linux-2.6.39/arch/mips/ar71xx/mach-zcn-1523h.c +--- linux-2.6.39.orig/arch/mips/ar71xx/mach-zcn-1523h.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/mach-zcn-1523h.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,214 @@ ++/* ++ * Zcomax ZCN-1523H-2-8/5-16 board support ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap91-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++ ++#define ZCN_1523H_GPIO_BTN_RESET 0 ++#define ZCN_1523H_GPIO_LED_INIT 11 ++#define ZCN_1523H_GPIO_LED_LAN1 17 ++ ++#define ZCN_1523H_2_GPIO_LED_WEAK 13 ++#define ZCN_1523H_2_GPIO_LED_MEDIUM 14 ++#define ZCN_1523H_2_GPIO_LED_STRONG 15 ++ ++#define ZCN_1523H_5_GPIO_LED_UNKNOWN 1 ++#define ZCN_1523H_5_GPIO_LED_LAN2 13 ++#define ZCN_1523H_5_GPIO_LED_WEAK 14 ++#define ZCN_1523H_5_GPIO_LED_MEDIUM 15 ++#define ZCN_1523H_5_GPIO_LED_STRONG 16 ++ ++#define ZCN_1523H_KEYS_POLL_INTERVAL 20 /* msecs */ ++#define ZCN_1523H_KEYS_DEBOUNCE_INTERVAL (3 * ZCN_1523H_KEYS_POLL_INTERVAL) ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition zcn_1523h_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "rootfs", ++ .offset = 0x050000, ++ .size = 0x610000, ++ }, { ++ .name = "kernel", ++ .offset = 0x660000, ++ .size = 0x170000, ++ }, { ++ .name = "configure", ++ .offset = 0x7d0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "mfg", ++ .offset = 0x7e0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "eeprom", ++ .offset = 0x7f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x050000, ++ .size = 0x780000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data zcn_1523h_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = zcn_1523h_partitions, ++ .nr_parts = ARRAY_SIZE(zcn_1523h_partitions), ++#endif ++}; ++ ++static struct gpio_keys_button zcn_1523h_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = ZCN_1523H_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = ZCN_1523H_GPIO_BTN_RESET, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_led zcn_1523h_leds_gpio[] __initdata = { ++ { ++ .name = "zcn-1523h:amber:init", ++ .gpio = ZCN_1523H_GPIO_LED_INIT, ++ .active_low = 1, ++ }, { ++ .name = "zcn-1523h:green:lan1", ++ .gpio = ZCN_1523H_GPIO_LED_LAN1, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_led zcn_1523h_2_leds_gpio[] __initdata = { ++ { ++ .name = "zcn-1523h:red:weak", ++ .gpio = ZCN_1523H_2_GPIO_LED_WEAK, ++ .active_low = 1, ++ }, { ++ .name = "zcn-1523h:amber:medium", ++ .gpio = ZCN_1523H_2_GPIO_LED_MEDIUM, ++ .active_low = 1, ++ }, { ++ .name = "zcn-1523h:green:strong", ++ .gpio = ZCN_1523H_2_GPIO_LED_STRONG, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_led zcn_1523h_5_leds_gpio[] __initdata = { ++ { ++ .name = "zcn-1523h:red:weak", ++ .gpio = ZCN_1523H_5_GPIO_LED_WEAK, ++ .active_low = 1, ++ }, { ++ .name = "zcn-1523h:amber:medium", ++ .gpio = ZCN_1523H_5_GPIO_LED_MEDIUM, ++ .active_low = 1, ++ }, { ++ .name = "zcn-1523h:green:strong", ++ .gpio = ZCN_1523H_5_GPIO_LED_STRONG, ++ .active_low = 1, ++ }, { ++ .name = "zcn-1523h:green:lan2", ++ .gpio = ZCN_1523H_5_GPIO_LED_LAN2, ++ .active_low = 1, ++ }, { ++ .name = "zcn-1523h:amber:unknown", ++ .gpio = ZCN_1523H_5_GPIO_LED_UNKNOWN, ++ } ++}; ++ ++static void __init zcn_1523h_generic_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1f7e0004); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ar71xx_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | ++ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | ++ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | ++ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | ++ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); ++ ++ ar71xx_add_device_m25p80(&zcn_1523h_flash_data); ++ ++ ar71xx_add_device_leds_gpio(0, ARRAY_SIZE(zcn_1523h_leds_gpio), ++ zcn_1523h_leds_gpio); ++ ++ ar71xx_register_gpio_keys_polled(-1, ZCN_1523H_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(zcn_1523h_gpio_keys), ++ zcn_1523h_gpio_keys); ++ ++ ap91_pci_init(ee, mac); ++ ++ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); ++ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); ++ ++ /* LAN1 port */ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ++ /* LAN2 port */ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_mdio(0x0); ++ ar71xx_add_device_eth(0); ++} ++ ++static void __init zcn_1523h_2_setup(void) ++{ ++ zcn_1523h_generic_setup(); ++ ap91_pci_setup_wmac_gpio(BIT(9), 0); ++ ++ ar71xx_add_device_leds_gpio(1, ARRAY_SIZE(zcn_1523h_2_leds_gpio), ++ zcn_1523h_2_leds_gpio); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_ZCN_1523H_2, "ZCN-1523H-2", "Zcomax ZCN-1523H-2", ++ zcn_1523h_2_setup); ++ ++static void __init zcn_1523h_5_setup(void) ++{ ++ zcn_1523h_generic_setup(); ++ ap91_pci_setup_wmac_gpio(BIT(8), 0); ++ ++ ar71xx_add_device_leds_gpio(1, ARRAY_SIZE(zcn_1523h_5_leds_gpio), ++ zcn_1523h_5_leds_gpio); ++ ar71xx_add_device_eth(1); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_ZCN_1523H_5, "ZCN-1523H-5", "Zcomax ZCN-1523H-5", ++ zcn_1523h_5_setup); +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/machtype.h linux-2.6.39/arch/mips/ar71xx/machtype.h +--- linux-2.6.39.orig/arch/mips/ar71xx/machtype.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/machtype.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,75 @@ ++/* ++ * Atheros AR71xx machine type definitions ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_MACHTYPE_H ++#define _AR71XX_MACHTYPE_H ++ ++#include ++ ++enum ar71xx_mach_type { ++ AR71XX_MACH_GENERIC = 0, ++ AR71XX_MACH_AP121, /* Atheros AP121 */ ++ AR71XX_MACH_AP121_MINI, /* Atheros AP121-MINI */ ++ AR71XX_MACH_AP81, /* Atheros AP81 */ ++ AR71XX_MACH_AP83, /* Atheros AP83 */ ++ AR71XX_MACH_AW_NR580, /* AzureWave AW-NR580 */ ++ AR71XX_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */ ++ AR71XX_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */ ++ AR71XX_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */ ++ AR71XX_MACH_JA76PF, /* jjPlus JA76PF */ ++ AR71XX_MACH_JWAP003, /* jjPlus JWAP003 */ ++ AR71XX_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */ ++ AR71XX_MACH_RB_411U, /* MikroTik RouterBOARD 411U */ ++ AR71XX_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */ ++ AR71XX_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */ ++ AR71XX_MACH_RB_450, /* MikroTik RouterBOARD 450 */ ++ AR71XX_MACH_RB_450G, /* MikroTik RouterBOARD 450G */ ++ AR71XX_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */ ++ AR71XX_MACH_RB_750, /* MikroTik RouterBOARD 750 */ ++ AR71XX_MACH_PB42, /* Atheros PB42 */ ++ AR71XX_MACH_PB44, /* Atheros PB44 */ ++ AR71XX_MACH_PB92, /* Atheros PB92 */ ++ AR71XX_MACH_MZK_W04NU, /* Planex MZK-W04NU */ ++ AR71XX_MACH_MZK_W300NH, /* Planex MZK-W300NH */ ++ AR71XX_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */ ++ AR71XX_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */ ++ AR71XX_MACH_TL_MR3220, /* TP-LINK TL-MR3220 */ ++ AR71XX_MACH_TL_MR3420, /* TP-LINK TL-MR3420 */ ++ AR71XX_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */ ++ AR71XX_MACH_TL_WA901ND_V2, /* TP-LINK TL-WA901ND v2 */ ++ AR71XX_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */ ++ AR71XX_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */ ++ AR71XX_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ ++ AR71XX_MACH_TL_WR1043ND, /* TP-LINK TL-WR1041ND */ ++ AR71XX_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */ ++ AR71XX_MACH_UBNT_LSX, /* Ubiquiti LSX */ ++ AR71XX_MACH_UBNT_RS, /* Ubiquiti RouterStation */ ++ AR71XX_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */ ++ AR71XX_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ ++ AR71XX_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */ ++ AR71XX_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */ ++ AR71XX_MACH_WNDR3700, /* NETGEAR WNDR3700 */ ++ AR71XX_MACH_WNDR3700V2, /* NETGEAR WNDR3700v2 */ ++ AR71XX_MACH_WNR2000, /* NETGEAR WNR2000 */ ++ AR71XX_MACH_WP543, /* Compex WP543 */ ++ AR71XX_MACH_WRT160NL, /* Linksys WRT160NL */ ++ AR71XX_MACH_WRT400N, /* Linksys WRT400N */ ++ AR71XX_MACH_WZR_HP_AG300H, /* Buffalo WZR-HP-AG300H */ ++ AR71XX_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */ ++ AR71XX_MACH_EAP7660D, /* Senao EAP7660D */ ++ AR71XX_MACH_ZCN_1523H_2, /* Zcomax ZCN-1523H-2-xx */ ++ AR71XX_MACH_ZCN_1523H_5, /* Zcomax ZCN-1523H-5-xx */ ++ AR71XX_MACH_AP96, /* Atheros AP96 */ ++ AR71XX_MACH_UBNT_UNIFI, /* Unifi */ ++ AR71XX_MACH_DB120, /* Atheros DB120 (AR934x based) */ ++}; ++ ++#endif /* _AR71XX_MACHTYPE_H */ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/nvram.c linux-2.6.39/arch/mips/ar71xx/nvram.c +--- linux-2.6.39.orig/arch/mips/ar71xx/nvram.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/nvram.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,75 @@ ++/* ++ * Atheros AR71xx minimal nvram support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "nvram.h" ++ ++char *nvram_find_var(const char *name, const char *buf, unsigned buf_len) ++{ ++ unsigned len = strlen(name); ++ char *cur, *last; ++ ++ if (buf_len == 0 || len == 0) ++ return NULL; ++ ++ if (buf_len < len) ++ return NULL; ++ ++ if (len == 1) ++ return memchr(buf, (int) *name, buf_len); ++ ++ last = (char *) buf + buf_len - len; ++ for (cur = (char *) buf; cur <= last; cur++) ++ if (cur[0] == name[0] && memcmp(cur, name, len) == 0) ++ return cur + len; ++ ++ return NULL; ++} ++ ++int nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, ++ const char *name, char *mac) ++{ ++ char *buf; ++ char *mac_str; ++ int ret; ++ int t; ++ ++ buf = vmalloc(nvram_len); ++ if (!buf) ++ return -ENOMEM; ++ ++ memcpy(buf, nvram, nvram_len); ++ buf[nvram_len - 1] = '\0'; ++ ++ mac_str = nvram_find_var(name, buf, nvram_len); ++ if (!mac_str) { ++ ret = -EINVAL; ++ goto free; ++ } ++ ++ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", ++ &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); ++ ++ if (t != 6) { ++ ret = -EINVAL; ++ goto free; ++ } ++ ++ ret = 0; ++ ++free: ++ vfree(buf); ++ return ret; ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/nvram.h linux-2.6.39/arch/mips/ar71xx/nvram.h +--- linux-2.6.39.orig/arch/mips/ar71xx/nvram.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/nvram.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,19 @@ ++/* ++ * Atheros AR71xx minimal nvram support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR71XX_NVRAM_H ++#define _AR71XX_NVRAM_H ++ ++char *nvram_find_var(const char *name, const char *buf, ++ unsigned buf_len) __init; ++int nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, ++ const char *name, char *mac) __init; ++ ++#endif /* _AR71XX_NVRAM_H */ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/pci-ath9k-fixup.c linux-2.6.39/arch/mips/ar71xx/pci-ath9k-fixup.c +--- linux-2.6.39.orig/arch/mips/ar71xx/pci-ath9k-fixup.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/pci-ath9k-fixup.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,123 @@ ++/* ++ * Atheros AP94 reference board PCI initialization ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++ ++struct ath9k_fixup { ++ u16 *cal_data; ++ unsigned slot; ++}; ++ ++static int ath9k_num_fixups; ++static struct ath9k_fixup ath9k_fixups[2]; ++ ++static void ath9k_pci_fixup(struct pci_dev *dev) ++{ ++ void __iomem *mem; ++ u16 *cal_data = NULL; ++ u16 cmd; ++ u32 bar0; ++ u32 val; ++ unsigned i; ++ ++ for (i = 0; i < ath9k_num_fixups; i++) { ++ if (ath9k_fixups[i].cal_data == NULL) ++ continue; ++ ++ if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn)) ++ continue; ++ ++ cal_data = ath9k_fixups[i].cal_data; ++ break; ++ } ++ ++ if (cal_data == NULL) ++ return; ++ ++ if (*cal_data != 0xa55a) { ++ pr_err("pci %s: invalid calibration data\n", pci_name(dev)); ++ return; ++ } ++ ++ pr_info("pci %s: fixup device configuration\n", pci_name(dev)); ++ ++ mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); ++ if (!mem) { ++ pr_err("pci %s: ioremap error\n", pci_name(dev)); ++ return; ++ } ++ ++ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7161: ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, ++ AR71XX_PCI_MEM_BASE); ++ break; ++ case AR71XX_SOC_AR7240: ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff); ++ break; ++ ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff); ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ /* set pointer to first reg address */ ++ cal_data += 3; ++ while (*cal_data != 0xffff) { ++ u32 reg; ++ reg = *cal_data++; ++ val = *cal_data++; ++ val |= (*cal_data++) << 16; ++ ++ __raw_writel(val, mem + reg); ++ udelay(100); ++ } ++ ++ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); ++ dev->vendor = val & 0xffff; ++ dev->device = (val >> 16) & 0xffff; ++ ++ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); ++ dev->revision = val & 0xff; ++ dev->class = val >> 8; /* upper 3 bytes */ ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); ++ ++ iounmap(mem); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); ++ ++void __init pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data) ++{ ++ if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) ++ return; ++ ++ ath9k_fixups[ath9k_num_fixups].slot = slot; ++ ath9k_fixups[ath9k_num_fixups].cal_data = cal_data; ++ ath9k_num_fixups++; ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/pci-ath9k-fixup.h linux-2.6.39/arch/mips/ar71xx/pci-ath9k-fixup.h +--- linux-2.6.39.orig/arch/mips/ar71xx/pci-ath9k-fixup.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/pci-ath9k-fixup.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,6 @@ ++#ifndef _PCI_ATH9K_FIXUP ++#define _PCI_ATH9K_FIXUP ++ ++void pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data) __init; ++ ++#endif /* _PCI_ATH9K_FIXUP */ +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/pci.c linux-2.6.39/arch/mips/ar71xx/pci.c +--- linux-2.6.39.orig/arch/mips/ar71xx/pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/pci.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,97 @@ ++/* ++ * Atheros AR71xx PCI setup code ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++ ++#include ++ ++#include ++#include ++ ++unsigned ar71xx_pci_nr_irqs __initdata; ++struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata; ++ ++int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev); ++ ++static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup) ++{ ++ int err = 0; ++ ++ err = ar71xx_pci_be_handler(is_fixup); ++ ++ return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL; ++} ++ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++ if (ar71xx_pci_plat_dev_init) ++ return ar71xx_pci_plat_dev_init(dev); ++ ++ return 0; ++} ++ ++int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) ++{ ++ int ret = 0; ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ ret = ar71xx_pcibios_map_irq(dev, slot, pin); ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ case AR71XX_SOC_AR9342: ++ case AR71XX_SOC_AR9344: ++ ret = ar724x_pcibios_map_irq(dev, slot, pin); ++ break; ++ ++ default: ++ break; ++ } ++ ++ return ret; ++} ++ ++int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) ++{ ++ int ret = 0; ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ board_be_handler = ar71xx_be_handler; ++ ret = ar71xx_pcibios_init(); ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ case AR71XX_SOC_AR9342: ++ case AR71XX_SOC_AR9344: ++ ret = ar724x_pcibios_init(); ++ break; ++ ++ default: ++ return 0; ++ } ++ ++ ar71xx_pci_nr_irqs = nr_irqs; ++ ar71xx_pci_irq_map = map; ++ ++ return ret; ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/prom.c linux-2.6.39/arch/mips/ar71xx/prom.c +--- linux-2.6.39.orig/arch/mips/ar71xx/prom.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/prom.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,189 @@ ++/* ++ * Atheros AR71xx SoC specific prom routines ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++static inline int is_valid_ram_addr(void *addr) ++{ ++ if (((u32) addr > KSEG0) && ++ ((u32) addr < (KSEG0 + AR71XX_MEM_SIZE_MAX))) ++ return 1; ++ ++ if (((u32) addr > KSEG1) && ++ ((u32) addr < (KSEG1 + AR71XX_MEM_SIZE_MAX))) ++ return 1; ++ ++ return 0; ++} ++ ++static void __init ar71xx_prom_append_cmdline(const char *name, ++ const char *value) ++{ ++ char buf[COMMAND_LINE_SIZE]; ++ ++ snprintf(buf, sizeof(buf), " %s=%s", name, value); ++ strlcat(arcs_cmdline, buf, sizeof(arcs_cmdline)); ++} ++ ++static const char * __init ar71xx_prom_find_env(char **envp, const char *name) ++{ ++ const char *ret = NULL; ++ int len; ++ char **p; ++ ++ if (!is_valid_ram_addr(envp)) ++ return NULL; ++ ++ len = strlen(name); ++ for (p = envp; is_valid_ram_addr(*p); p++) { ++ if (strncmp(name, *p, len) == 0 && (*p)[len] == '=') { ++ ret = *p + len + 1; ++ break; ++ } ++ ++ /* RedBoot env comes in pointer pairs - key, value */ ++ if (strncmp(name, *p, len) == 0 && (*p)[len] == 0) ++ if (is_valid_ram_addr(*(++p))) { ++ ret = *p; ++ break; ++ } ++ } ++ ++ return ret; ++} ++ ++static int __init ar71xx_prom_init_myloader(void) ++{ ++ struct myloader_info *mylo; ++ char mac_buf[32]; ++ char *mac; ++ ++ mylo = myloader_get_info(); ++ if (!mylo) ++ return 0; ++ ++ switch (mylo->did) { ++ case DEVID_COMPEX_WP543: ++ ar71xx_prom_append_cmdline("board", "WP543"); ++ break; ++ default: ++ printk(KERN_WARNING "prom: unknown device id: %x\n", ++ mylo->did); ++ return 0; ++ } ++ ++ mac = mylo->macs[0]; ++ snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x", ++ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); ++ ++ ar71xx_prom_append_cmdline("ethaddr", mac_buf); ++ ++ return 1; ++} ++ ++#ifdef CONFIG_IMAGE_CMDLINE_HACK ++extern char __image_cmdline[]; ++ ++static int __init ar71xx_use__image_cmdline(void) ++{ ++ char *p = __image_cmdline; ++ int replace = 0; ++ ++ if (*p == '-') { ++ replace = 1; ++ p++; ++ } ++ ++ if (*p == '\0') ++ return 0; ++ ++ if (replace) { ++ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } else { ++ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); ++ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } ++ ++ return 1; ++} ++#else ++static inline int ar71xx_use__image_cmdline(void) { return 0; } ++#endif ++ ++static __init void ar71xx_prom_init_cmdline(int argc, char **argv) ++{ ++ int i; ++ ++ if (ar71xx_use__image_cmdline()) ++ return; ++ ++ if (!is_valid_ram_addr(argv)) ++ return; ++ ++ for (i = 0; i < argc; i++) ++ if (is_valid_ram_addr(argv[i])) { ++ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); ++ strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline)); ++ } ++} ++ ++void __init prom_init(void) ++{ ++ const char *env; ++ char **envp; ++ ++ printk(KERN_DEBUG "prom: fw_arg0=%08x, fw_arg1=%08x, " ++ "fw_arg2=%08x, fw_arg3=%08x\n", ++ (unsigned int)fw_arg0, (unsigned int)fw_arg1, ++ (unsigned int)fw_arg2, (unsigned int)fw_arg3); ++ ++ ++ if (ar71xx_prom_init_myloader()) ++ return; ++ ++ ar71xx_prom_init_cmdline(fw_arg0, (char **)fw_arg1); ++ ++ envp = (char **)fw_arg2; ++ if (!strstr(arcs_cmdline, "ethaddr=")) { ++ env = ar71xx_prom_find_env(envp, "ethaddr"); ++ if (env) ++ ar71xx_prom_append_cmdline("ethaddr", env); ++ } ++ ++ if (!strstr(arcs_cmdline, "board=")) { ++ env = ar71xx_prom_find_env(envp, "board"); ++ if (env) { ++ /* Workaround for buggy bootloaders */ ++ if (strcmp(env, "RouterStation") == 0 || ++ strcmp(env, "Ubiquiti AR71xx-based board") == 0) ++ env = "UBNT-RS"; ++ ++ if (strcmp(env, "RouterStation PRO") == 0) ++ env = "UBNT-RSPRO"; ++ ++ ar71xx_prom_append_cmdline("board", env); ++ } ++ } ++} ++ ++void __init prom_free_prom_memory(void) ++{ ++ /* We do not have to prom memory to free */ ++} +diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/setup.c linux-2.6.39/arch/mips/ar71xx/setup.c +--- linux-2.6.39.orig/arch/mips/ar71xx/setup.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/ar71xx/setup.c 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,446 @@ ++/* ++ * Atheros AR71xx SoC specific setup ++ * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros 2.6.15 BSP ++ * Parts of this file are based on Atheros 2.6.31 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include /* for mips_hpt_frequency */ ++#include /* for _machine_{restart,halt} */ ++#include ++ ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++ ++#define AR71XX_SYS_TYPE_LEN 64 ++ ++u32 ar71xx_cpu_freq; ++EXPORT_SYMBOL_GPL(ar71xx_cpu_freq); ++ ++u32 ar71xx_ahb_freq; ++EXPORT_SYMBOL_GPL(ar71xx_ahb_freq); ++ ++u32 ar71xx_ddr_freq; ++EXPORT_SYMBOL_GPL(ar71xx_ddr_freq); ++ ++u32 ar71xx_ref_freq; ++EXPORT_SYMBOL_GPL(ar71xx_ref_freq); ++ ++enum ar71xx_soc_type ar71xx_soc; ++EXPORT_SYMBOL_GPL(ar71xx_soc); ++ ++u32 ar71xx_soc_rev; ++EXPORT_SYMBOL_GPL(ar71xx_soc_rev); ++ ++static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN]; ++ ++static void ar71xx_restart(char *command) ++{ ++ ar71xx_device_stop(RESET_MODULE_FULL_CHIP); ++ for (;;) ++ if (cpu_wait) ++ cpu_wait(); ++} ++ ++static void ar71xx_halt(void) ++{ ++ while (1) ++ cpu_wait(); ++} ++ ++static void __init ar71xx_detect_mem_size(void) ++{ ++ unsigned long size; ++ ++ for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX; ++ size <<= 1) { ++ if (!memcmp(ar71xx_detect_mem_size, ++ ar71xx_detect_mem_size + size, 1024)) ++ break; ++ } ++ ++ add_memory_region(0, size, BOOT_MEM_RAM); ++} ++ ++static void __init ar71xx_detect_sys_type(void) ++{ ++ char *chip = "????"; ++ u32 id; ++ u32 major; ++ u32 minor; ++ u32 rev = 0; ++ ++ id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID); ++ major = id & REV_ID_MAJOR_MASK; ++ ++ switch (major) { ++ case REV_ID_MAJOR_AR71XX: ++ minor = id & AR71XX_REV_ID_MINOR_MASK; ++ rev = id >> AR71XX_REV_ID_REVISION_SHIFT; ++ rev &= AR71XX_REV_ID_REVISION_MASK; ++ switch (minor) { ++ case AR71XX_REV_ID_MINOR_AR7130: ++ ar71xx_soc = AR71XX_SOC_AR7130; ++ chip = "7130"; ++ break; ++ ++ case AR71XX_REV_ID_MINOR_AR7141: ++ ar71xx_soc = AR71XX_SOC_AR7141; ++ chip = "7141"; ++ break; ++ ++ case AR71XX_REV_ID_MINOR_AR7161: ++ ar71xx_soc = AR71XX_SOC_AR7161; ++ chip = "7161"; ++ break; ++ } ++ break; ++ ++ case REV_ID_MAJOR_AR7240: ++ ar71xx_soc = AR71XX_SOC_AR7240; ++ chip = "7240"; ++ rev = id & AR724X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_AR7241: ++ ar71xx_soc = AR71XX_SOC_AR7241; ++ chip = "7241"; ++ rev = id & AR724X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_AR7242: ++ ar71xx_soc = AR71XX_SOC_AR7242; ++ chip = "7242"; ++ rev = id & AR724X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_AR913X: ++ minor = id & AR91XX_REV_ID_MINOR_MASK; ++ rev = id >> AR91XX_REV_ID_REVISION_SHIFT; ++ rev &= AR91XX_REV_ID_REVISION_MASK; ++ switch (minor) { ++ case AR91XX_REV_ID_MINOR_AR9130: ++ ar71xx_soc = AR71XX_SOC_AR9130; ++ chip = "9130"; ++ break; ++ ++ case AR91XX_REV_ID_MINOR_AR9132: ++ ar71xx_soc = AR71XX_SOC_AR9132; ++ chip = "9132"; ++ break; ++ } ++ break; ++ ++ case REV_ID_MAJOR_AR9330: ++ ar71xx_soc = AR71XX_SOC_AR9330; ++ chip = "9330"; ++ rev = id & AR933X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_AR9331: ++ ar71xx_soc = AR71XX_SOC_AR9331; ++ chip = "9331"; ++ rev = id & AR933X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_AR9342: ++ ar71xx_soc = AR71XX_SOC_AR9342; ++ chip = "9342"; ++ rev = id & AR934X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_AR9344: ++ ar71xx_soc = AR71XX_SOC_AR9344; ++ chip = "9344"; ++ rev = id & AR934X_REV_ID_REVISION_MASK; ++ break; ++ ++ default: ++ panic("ar71xx: unknown chip id:0x%08x\n", id); ++ } ++ ++ ar71xx_soc_rev = rev; ++ ++ sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev); ++ pr_info("SoC: %s\n", ar71xx_sys_type); ++} ++ ++static void __init ar934x_detect_sys_frequency(void) ++{ ++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; ++ ++ if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40) ++ ar71xx_ref_freq = 40 * 1000 * 1000; ++ else ++ ar71xx_ref_freq = 25 * 1000 * 1000; ++ ++ clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK); ++ ++ pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG); ++ out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll); ++ ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll); ++ nint = AR934X_CPU_PLL_CFG_NINT_GET(pll); ++ frac = AR934X_CPU_PLL_CFG_NFRAC_GET(pll); ++ postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl); ++ ar71xx_cpu_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) / ++ (postdiv + 1); ++ ++ out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll); ++ ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll); ++ nint = AR934X_DDR_PLL_CFG_NINT_GET(pll); ++ frac = AR934X_DDR_PLL_CFG_NFRAC_GET(pll); ++ postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl); ++ ar71xx_ddr_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) / ++ (postdiv + 1); ++ ++ postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl); ++ ++ if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) { ++ ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1); ++ } else { ++ ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1); ++ } ++ ++} ++ ++static void __init ar91xx_detect_sys_frequency(void) ++{ ++ u32 pll; ++ u32 freq; ++ u32 div; ++ ++ ar71xx_ref_freq = 5 * 1000 * 1000; ++ ++ pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG); ++ ++ div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK); ++ freq = div * ar71xx_ref_freq; ++ ++ ar71xx_cpu_freq = freq; ++ ++ div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1; ++ ar71xx_ddr_freq = freq / div; ++ ++ div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2; ++ ar71xx_ahb_freq = ar71xx_cpu_freq / div; ++} ++ ++static void __init ar71xx_detect_sys_frequency(void) ++{ ++ u32 pll; ++ u32 freq; ++ u32 div; ++ ++ ar71xx_ref_freq = 40 * 1000 * 1000; ++ ++ pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); ++ ++ div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; ++ freq = div * ar71xx_ref_freq; ++ ++ div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; ++ ar71xx_cpu_freq = freq / div; ++ ++ div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; ++ ar71xx_ddr_freq = freq / div; ++ ++ div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; ++ ar71xx_ahb_freq = ar71xx_cpu_freq / div; ++} ++ ++static void __init ar724x_detect_sys_frequency(void) ++{ ++ u32 pll; ++ u32 freq; ++ u32 div; ++ ++ ar71xx_ref_freq = 5 * 1000 * 1000; ++ ++ pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG); ++ ++ div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); ++ freq = div * ar71xx_ref_freq; ++ ++ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); ++ freq *= div; ++ ++ ar71xx_cpu_freq = freq; ++ ++ div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; ++ ar71xx_ddr_freq = freq / div; ++ ++ div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; ++ ar71xx_ahb_freq = ar71xx_cpu_freq / div; ++} ++ ++static void __init ar933x_detect_sys_frequency(void) ++{ ++ u32 clock_ctrl; ++ u32 cpu_config; ++ u32 freq; ++ u32 t; ++ ++ t = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP); ++ if (t & AR933X_BOOTSTRAP_REF_CLK_40) ++ ar71xx_ref_freq = (40 * 1000 * 1000); ++ else ++ ar71xx_ref_freq = (25 * 1000 * 1000); ++ ++ clock_ctrl = ar71xx_pll_rr(AR933X_PLL_CLOCK_CTRL_REG); ++ if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { ++ ar71xx_cpu_freq = ar71xx_ref_freq; ++ ar71xx_ahb_freq = ar71xx_ref_freq; ++ ar71xx_ddr_freq = ar71xx_ref_freq; ++ } else { ++ cpu_config = ar71xx_pll_rr(AR933X_PLL_CPU_CONFIG_REG); ++ ++ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ++ AR933X_PLL_CPU_CONFIG_REFDIV_MASK; ++ freq = ar71xx_ref_freq / t; ++ ++ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & ++ AR933X_PLL_CPU_CONFIG_NINT_MASK; ++ freq *= t; ++ ++ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & ++ AR933X_PLL_CPU_CONFIG_OUTDIV_MASK; ++ if (t == 0) ++ t = 1; ++ ++ freq >>= t; ++ ++ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & ++ AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; ++ ar71xx_cpu_freq = freq / t; ++ ++ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & ++ AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; ++ ar71xx_ddr_freq = freq / t; ++ ++ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & ++ AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; ++ ar71xx_ahb_freq = freq / t; ++ } ++} ++ ++static void __init detect_sys_frequency(void) ++{ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ ar71xx_detect_sys_frequency(); ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ar724x_detect_sys_frequency(); ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ ar91xx_detect_sys_frequency(); ++ break; ++ ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ ar933x_detect_sys_frequency(); ++ break; ++ ++ case AR71XX_SOC_AR9341: ++ case AR71XX_SOC_AR9342: ++ case AR71XX_SOC_AR9344: ++ ar934x_detect_sys_frequency(); ++ break; ++ default: ++ BUG(); ++ } ++} ++ ++const char *get_system_type(void) ++{ ++ return ar71xx_sys_type; ++} ++ ++unsigned int __cpuinit get_c0_compare_irq(void) ++{ ++ return CP0_LEGACY_COMPARE_IRQ; ++} ++ ++void __init plat_mem_setup(void) ++{ ++ set_io_port_base(KSEG1); ++ ++ ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, ++ AR71XX_DDR_CTRL_SIZE); ++ ++ ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE, ++ AR71XX_PLL_SIZE); ++ ++ ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE, ++ AR71XX_RESET_SIZE); ++ ++ ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); ++ ++ ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE, ++ AR71XX_USB_CTRL_SIZE); ++ ++ ar71xx_detect_mem_size(); ++ ar71xx_detect_sys_type(); ++ detect_sys_frequency(); ++ ++ pr_info("Clocks: CPU:%u.%03uMHz, DDR:%u.%03uMHz, AHB:%u.%03uMHz, " ++ "Ref:%u.%03uMHz", ++ ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000, ++ ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000, ++ ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000, ++ ar71xx_ref_freq / 1000000, (ar71xx_ref_freq / 1000) % 1000); ++ ++ _machine_restart = ar71xx_restart; ++ _machine_halt = ar71xx_halt; ++ pm_power_off = ar71xx_halt; ++} ++ ++void __init plat_time_init(void) ++{ ++ mips_hpt_frequency = ar71xx_cpu_freq / 2; ++} ++ ++__setup("board=", mips_machtype_setup); ++ ++static int __init ar71xx_machine_setup(void) ++{ ++ ar71xx_gpio_init(); ++ ++ ar71xx_add_device_uart(); ++ ar71xx_add_device_wdt(); ++ ++ mips_machine_setup(); ++ return 0; ++} ++ ++arch_initcall(ar71xx_machine_setup); ++ ++static void __init ar71xx_generic_init(void) ++{ ++ /* Nothing to do */ ++} ++ ++MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board", ++ ar71xx_generic_init); +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/checksum.h linux-2.6.39/arch/mips/include/asm/checksum.h +--- linux-2.6.39.orig/arch/mips/include/asm/checksum.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/include/asm/checksum.h 2011-08-24 18:17:23.000000000 +0200 +@@ -12,6 +12,7 @@ + #define _ASM_CHECKSUM_H + + #include ++#include + + #include + +@@ -104,26 +105,30 @@ + const unsigned int *stop = word + ihl; + unsigned int csum; + int carry; ++ unsigned int w; + +- csum = word[0]; +- csum += word[1]; +- carry = (csum < word[1]); ++ csum = __get_unaligned_cpu32(word++); ++ ++ w = __get_unaligned_cpu32(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; + +- csum += word[2]; +- carry = (csum < word[2]); ++ w = __get_unaligned_cpu32(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; + +- csum += word[3]; +- carry = (csum < word[3]); ++ w = __get_unaligned_cpu32(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; + +- word += 4; + do { +- csum += *word; +- carry = (csum < *word); ++ w = __get_unaligned_cpu32(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; +- word++; + } while (word != stop); + + return csum_fold(csum); +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/fw/myloader/myloader.h linux-2.6.39/arch/mips/include/asm/fw/myloader/myloader.h +--- linux-2.6.39.orig/arch/mips/include/asm/fw/myloader/myloader.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/fw/myloader/myloader.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,34 @@ ++/* ++ * Compex's MyLoader specific definitions ++ * ++ * Copyright (C) 2006-2008 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++ ++#ifndef _ASM_MIPS_FW_MYLOADER_H ++#define _ASM_MIPS_FW_MYLOADER_H ++ ++#include ++ ++struct myloader_info { ++ uint32_t vid; ++ uint32_t did; ++ uint32_t svid; ++ uint32_t sdid; ++ uint8_t macs[MYLO_ETHADDR_COUNT][6]; ++}; ++ ++#ifdef CONFIG_MYLOADER ++extern struct myloader_info *myloader_get_info(void) __init; ++#else ++static inline struct myloader_info *myloader_get_info(void) ++{ ++ return NULL; ++} ++#endif /* CONFIG_MYLOADER */ ++ ++#endif /* _ASM_MIPS_FW_MYLOADER_H */ +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar71xx.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar71xx.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar71xx.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar71xx.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,769 @@ ++/* ++ * Atheros AR71xx SoC specific definitions ++ * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros 2.6.15 BSP ++ * Parts of this file are based on Atheros 2.6.31 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_MACH_AR71XX_H ++#define __ASM_MACH_AR71XX_H ++ ++#include ++#include ++#include ++#include ++ ++#ifndef __ASSEMBLER__ ++ ++#define AR71XX_PCI_MEM_BASE 0x10000000 ++#define AR71XX_PCI_MEM_SIZE 0x08000000 ++#define AR71XX_APB_BASE 0x18000000 ++#define AR71XX_GE0_BASE 0x19000000 ++#define AR71XX_GE0_SIZE 0x01000000 ++#define AR71XX_GE1_BASE 0x1a000000 ++#define AR71XX_GE1_SIZE 0x01000000 ++#define AR71XX_EHCI_BASE 0x1b000000 ++#define AR71XX_EHCI_SIZE 0x01000000 ++#define AR71XX_OHCI_BASE 0x1c000000 ++#define AR71XX_OHCI_SIZE 0x01000000 ++#define AR7240_OHCI_BASE 0x1b000000 ++#define AR7240_OHCI_SIZE 0x01000000 ++#define AR71XX_SPI_BASE 0x1f000000 ++#define AR71XX_SPI_SIZE 0x01000000 ++ ++#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) ++#define AR71XX_DDR_CTRL_SIZE 0x10000 ++#define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000) ++#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) ++#define AR71XX_UART_SIZE 0x10000 ++#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) ++#define AR71XX_USB_CTRL_SIZE 0x10000 ++#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) ++#define AR71XX_GPIO_SIZE 0x10000 ++#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) ++#define AR71XX_PLL_SIZE 0x10000 ++#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) ++#define AR71XX_RESET_SIZE 0x10000 ++#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) ++#define AR71XX_MII_SIZE 0x10000 ++#define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000) ++#define AR71XX_SLIC_SIZE 0x10000 ++#define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000) ++#define AR71XX_DMA_SIZE 0x10000 ++#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000) ++#define AR71XX_STEREO_SIZE 0x10000 ++ ++#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) ++#define AR724X_PCI_CRP_SIZE 0x100 ++ ++#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) ++#define AR724X_PCI_CTRL_SIZE 0x100 ++ ++#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) ++#define AR91XX_WMAC_SIZE 0x30000 ++ ++#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) ++#define AR933X_UART_SIZE 0x14 ++#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) ++#define AR933X_WMAC_SIZE 0x20000 ++ ++#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) ++#define AR934X_WMAC_SIZE 0x20000 ++ ++#define AR71XX_MEM_SIZE_MIN 0x0200000 ++#define AR71XX_MEM_SIZE_MAX 0x10000000 ++ ++#define AR71XX_CPU_IRQ_BASE 0 ++#define AR71XX_MISC_IRQ_BASE 8 ++#define AR71XX_MISC_IRQ_COUNT 32 ++#define AR71XX_GPIO_IRQ_BASE 40 ++#define AR71XX_GPIO_IRQ_COUNT 32 ++#define AR71XX_PCI_IRQ_BASE 72 ++#define AR71XX_PCI_IRQ_COUNT 8 ++ ++#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2) ++#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3) ++#define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4) ++#define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5) ++#define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6) ++#define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7) ++ ++#define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0) ++#define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1) ++#define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2) ++#define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3) ++#define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4) ++#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5) ++#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6) ++#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7) ++#define AR71XX_MISC_IRQ_TIMER2 (AR71XX_MISC_IRQ_BASE + 8) ++#define AR71XX_MISC_IRQ_TIMER3 (AR71XX_MISC_IRQ_BASE + 9) ++#define AR71XX_MISC_IRQ_TIMER4 (AR71XX_MISC_IRQ_BASE + 10) ++#define AR71XX_MISC_IRQ_DDR_PERF (AR71XX_MISC_IRQ_BASE + 11) ++#define AR71XX_MISC_IRQ_ENET_LINK (AR71XX_MISC_IRQ_BASE + 12) ++ ++#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x)) ++ ++#define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0) ++#define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1) ++#define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2) ++#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4) ++ ++extern u32 ar71xx_ahb_freq; ++extern u32 ar71xx_cpu_freq; ++extern u32 ar71xx_ddr_freq; ++extern u32 ar71xx_ref_freq; ++ ++enum ar71xx_soc_type { ++ AR71XX_SOC_UNKNOWN, ++ AR71XX_SOC_AR7130, ++ AR71XX_SOC_AR7141, ++ AR71XX_SOC_AR7161, ++ AR71XX_SOC_AR7240, ++ AR71XX_SOC_AR7241, ++ AR71XX_SOC_AR7242, ++ AR71XX_SOC_AR9130, ++ AR71XX_SOC_AR9132, ++ AR71XX_SOC_AR9330, ++ AR71XX_SOC_AR9331, ++ AR71XX_SOC_AR9341, ++ AR71XX_SOC_AR9342, ++ AR71XX_SOC_AR9344, ++}; ++extern u32 ar71xx_soc_rev; ++ ++extern enum ar71xx_soc_type ar71xx_soc; ++ ++/* ++ * PLL block ++ */ ++#define AR71XX_PLL_REG_CPU_CONFIG 0x00 ++#define AR71XX_PLL_REG_SEC_CONFIG 0x04 ++#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 ++#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 ++ ++#define AR71XX_PLL_DIV_SHIFT 3 ++#define AR71XX_PLL_DIV_MASK 0x1f ++#define AR71XX_CPU_DIV_SHIFT 16 ++#define AR71XX_CPU_DIV_MASK 0x3 ++#define AR71XX_DDR_DIV_SHIFT 18 ++#define AR71XX_DDR_DIV_MASK 0x3 ++#define AR71XX_AHB_DIV_SHIFT 20 ++#define AR71XX_AHB_DIV_MASK 0x7 ++ ++#define AR71XX_ETH0_PLL_SHIFT 17 ++#define AR71XX_ETH1_PLL_SHIFT 19 ++ ++#define AR724X_PLL_REG_CPU_CONFIG 0x00 ++#define AR724X_PLL_REG_PCIE_CONFIG 0x18 ++ ++#define AR724X_PLL_DIV_SHIFT 0 ++#define AR724X_PLL_DIV_MASK 0x3ff ++#define AR724X_PLL_REF_DIV_SHIFT 10 ++#define AR724X_PLL_REF_DIV_MASK 0xf ++#define AR724X_AHB_DIV_SHIFT 19 ++#define AR724X_AHB_DIV_MASK 0x1 ++#define AR724X_DDR_DIV_SHIFT 22 ++#define AR724X_DDR_DIV_MASK 0x3 ++ ++#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c ++ ++#define AR91XX_PLL_REG_CPU_CONFIG 0x00 ++#define AR91XX_PLL_REG_ETH_CONFIG 0x04 ++#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14 ++#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18 ++ ++#define AR91XX_PLL_DIV_SHIFT 0 ++#define AR91XX_PLL_DIV_MASK 0x3ff ++#define AR91XX_DDR_DIV_SHIFT 22 ++#define AR91XX_DDR_DIV_MASK 0x3 ++#define AR91XX_AHB_DIV_SHIFT 19 ++#define AR91XX_AHB_DIV_MASK 0x1 ++ ++#define AR91XX_ETH0_PLL_SHIFT 20 ++#define AR91XX_ETH1_PLL_SHIFT 22 ++ ++#define AR933X_PLL_CPU_CONFIG_REG 0x00 ++#define AR933X_PLL_CLOCK_CTRL_REG 0x08 ++ ++#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 ++#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f ++#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 ++#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f ++#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 ++#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 ++ ++#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) ++#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 ++#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 ++#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 ++#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 ++#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 ++#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 ++ ++#define AR934X_PLL_REG_CPU_CONFIG 0x00 ++#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8 ++ ++#define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21 ++#define AR934X_CPU_PLL_CFG_OUTDIV_LSB 19 ++#define AR934X_CPU_PLL_CFG_OUTDIV_MASK 0x00380000 ++ ++#define AR934X_CPU_PLL_CFG_OUTDIV_GET(x) \ ++ (((x) & AR934X_CPU_PLL_CFG_OUTDIV_MASK) >> \ ++ AR934X_CPU_PLL_CFG_OUTDIV_LSB) ++ ++#define AR934X_DDR_PLL_CFG_OUTDIV_MSB 25 ++#define AR934X_DDR_PLL_CFG_OUTDIV_LSB 23 ++#define AR934X_DDR_PLL_CFG_OUTDIV_MASK 0x03800000 ++ ++#define AR934X_DDR_PLL_CFG_OUTDIV_GET(x) \ ++ (((x) & AR934X_DDR_PLL_CFG_OUTDIV_MASK) >> \ ++ AR934X_DDR_PLL_CFG_OUTDIV_LSB) ++ ++#define AR934X_DDR_PLL_CFG_OUTDIV_SET(x) \ ++ (((x) << AR934X_DDR_PLL_CFG_OUTDIV_LSB) & \ ++ AR934X_DDR_PLL_CFG_OUTDIV_MASK) ++ ++#define AR934X_CPU_PLL_CFG_REFDIV_MSB 16 ++#define AR934X_CPU_PLL_CFG_REFDIV_LSB 12 ++#define AR934X_CPU_PLL_CFG_REFDIV_MASK 0x0001f000 ++ ++#define AR934X_CPU_PLL_CFG_REFDIV_GET(x) \ ++ (((x) & AR934X_CPU_PLL_CFG_REFDIV_MASK) >> \ ++ AR934X_CPU_PLL_CFG_REFDIV_LSB) ++ ++#define AR934X_CPU_PLL_CFG_REFDIV_SET(x) \ ++ (((x) << AR934X_CPU_PLL_CFG_REFDIV_LSB) & \ ++ AR934X_CPU_PLL_CFG_REFDIV_MASK) ++ ++#define AR934X_CPU_PLL_CFG_REFDIV_RESET 2 ++ ++#define AR934X_CPU_PLL_CFG_NINT_MSB 11 ++#define AR934X_CPU_PLL_CFG_NINT_LSB 6 ++#define AR934X_CPU_PLL_CFG_NINT_MASK 0x00000fc0 ++ ++#define AR934X_CPU_PLL_CFG_NINT_GET(x) \ ++ (((x) & AR934X_CPU_PLL_CFG_NINT_MASK) >> \ ++ AR934X_CPU_PLL_CFG_NINT_LSB) ++ ++#define AR934X_CPU_PLL_CFG_NINT_SET(x) \ ++ (((x) << AR934X_CPU_PLL_CFG_NINT_LSB) & \ ++ AR934X_CPU_PLL_CFG_NINT_MASK) ++ ++#define AR934X_CPU_PLL_CFG_NINT_RESET 20 ++ ++#define AR934X_CPU_PLL_CFG_NFRAC_MSB 5 ++#define AR934X_CPU_PLL_CFG_NFRAC_LSB 0 ++#define AR934X_CPU_PLL_CFG_NFRAC_MASK 0x0000003f ++ ++#define AR934X_CPU_PLL_CFG_NFRAC_GET(x) \ ++ (((x) & AR934X_CPU_PLL_CFG_NFRAC_MASK) >> \ ++ AR934X_CPU_PLL_CFG_NFRAC_LSB) ++ ++#define AR934X_CPU_PLL_CFG_NFRAC_SET(x) \ ++ (((x) << AR934X_CPU_PLL_CFG_NFRAC_LSB) & \ ++ AR934X_CPU_PLL_CFG_NFRAC_MASK) ++ ++#define AR934X_DDR_PLL_CFG_REFDIV_MSB 20 ++#define AR934X_DDR_PLL_CFG_REFDIV_LSB 16 ++#define AR934X_DDR_PLL_CFG_REFDIV_MASK 0x001f0000 ++ ++#define AR934X_DDR_PLL_CFG_REFDIV_GET(x) \ ++ (((x) & AR934X_DDR_PLL_CFG_REFDIV_MASK) >> \ ++ AR934X_DDR_PLL_CFG_REFDIV_LSB) ++ ++#define AR934X_DDR_PLL_CFG_REFDIV_SET(x) \ ++ (((x) << AR934X_DDR_PLL_CFG_REFDIV_LSB) & \ ++ AR934X_DDR_PLL_CFG_REFDIV_MASK) ++ ++#define AR934X_DDR_PLL_CFG_REFDIV_RESET 2 ++ ++#define AR934X_DDR_PLL_CFG_NINT_MSB 15 ++#define AR934X_DDR_PLL_CFG_NINT_LSB 10 ++#define AR934X_DDR_PLL_CFG_NINT_MASK 0x0000fc00 ++ ++#define AR934X_DDR_PLL_CFG_NINT_GET(x) \ ++ (((x) & AR934X_DDR_PLL_CFG_NINT_MASK) >> \ ++ AR934X_DDR_PLL_CFG_NINT_LSB) ++ ++#define AR934X_DDR_PLL_CFG_NINT_SET(x) \ ++ (((x) << AR934X_DDR_PLL_CFG_NINT_LSB) & \ ++ AR934X_DDR_PLL_CFG_NINT_MASK) ++ ++#define AR934X_DDR_PLL_CFG_NINT_RESET 20 ++ ++#define AR934X_DDR_PLL_CFG_NFRAC_MSB 9 ++#define AR934X_DDR_PLL_CFG_NFRAC_LSB 0 ++#define AR934X_DDR_PLL_CFG_NFRAC_MASK 0x000003ff ++ ++#define AR934X_DDR_PLL_CFG_NFRAC_GET(x) \ ++ (((x) & AR934X_DDR_PLL_CFG_NFRAC_MASK) >> \ ++ AR934X_DDR_PLL_CFG_NFRAC_LSB) ++ ++#define AR934X_DDR_PLL_CFG_NFRAC_SET(x) \ ++ (((x) << AR934X_DDR_PLL_CFG_NFRAC_LSB) & \ ++ AR934X_DDR_PLL_CFG_NFRAC_MASK) ++ ++#define AR934X_DDR_PLL_CFG_NFRAC_RESET 512 ++ ++#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MSB 19 ++#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB 15 ++#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x000f8000 ++ ++#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(x) \ ++ (((x) & AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) >> \ ++ AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) ++ ++#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SET(x) \ ++ (((x) << AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) & \ ++ AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) ++ ++#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_RESET 0 ++ ++#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MSB 14 ++#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB 10 ++#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x00007c00 ++ ++#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(x) \ ++ (((x) & AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) >> \ ++ AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) ++ ++#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SET(x) \ ++ (((x) << AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) & \ ++ AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) ++ ++#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_RESET 0 ++ ++#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MSB 9 ++#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB 5 ++#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x000003e0 ++ ++#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(x) \ ++ (((x) & AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) >> \ ++ AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) ++ ++#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SET(x) \ ++ (((x) << AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) & \ ++ AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) ++ ++#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_RESET 0 ++ ++#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MSB 24 ++#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB 24 ++#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK 0x01000000 ++ ++#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(x) \ ++ (((x) & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) >> \ ++ AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) ++ ++#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SET(x) \ ++ (((x) << AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) & \ ++ AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) ++ ++#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1 ++ ++extern void __iomem *ar71xx_pll_base; ++ ++static inline void ar71xx_pll_wr(unsigned reg, u32 val) ++{ ++ __raw_writel(val, ar71xx_pll_base + reg); ++} ++ ++static inline u32 ar71xx_pll_rr(unsigned reg) ++{ ++ return __raw_readl(ar71xx_pll_base + reg); ++} ++ ++/* ++ * USB_CONFIG block ++ */ ++#define USB_CTRL_REG_FLADJ 0x00 ++#define USB_CTRL_REG_CONFIG 0x04 ++ ++extern void __iomem *ar71xx_usb_ctrl_base; ++ ++static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val) ++{ ++ __raw_writel(val, ar71xx_usb_ctrl_base + reg); ++} ++ ++static inline u32 ar71xx_usb_ctrl_rr(unsigned reg) ++{ ++ return __raw_readl(ar71xx_usb_ctrl_base + reg); ++} ++ ++/* ++ * GPIO block ++ */ ++#define GPIO_REG_OE 0x00 ++#define GPIO_REG_IN 0x04 ++#define GPIO_REG_OUT 0x08 ++#define GPIO_REG_SET 0x0c ++#define GPIO_REG_CLEAR 0x10 ++#define GPIO_REG_INT_MODE 0x14 ++#define GPIO_REG_INT_TYPE 0x18 ++#define GPIO_REG_INT_POLARITY 0x1c ++#define GPIO_REG_INT_PENDING 0x20 ++#define GPIO_REG_INT_ENABLE 0x24 ++#define GPIO_REG_FUNC 0x28 ++ ++#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) ++#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) ++#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) ++#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) ++#define AR71XX_GPIO_FUNC_UART_EN BIT(8) ++#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) ++#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) ++ ++#define AR71XX_GPIO_COUNT 16 ++ ++#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) ++#define AR724X_GPIO_FUNC_SPI_EN BIT(18) ++#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) ++#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) ++#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) ++#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) ++#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) ++#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) ++#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) ++#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) ++#define AR724X_GPIO_FUNC_UART_EN BIT(1) ++#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) ++ ++#define AR724X_GPIO_COUNT 18 ++ ++#define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22) ++#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) ++#define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20) ++#define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19) ++#define AR91XX_GPIO_FUNC_I2S1_EN BIT(18) ++#define AR91XX_GPIO_FUNC_I2S0_EN BIT(17) ++#define AR91XX_GPIO_FUNC_SLIC_EN BIT(16) ++#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9) ++#define AR91XX_GPIO_FUNC_UART_EN BIT(8) ++#define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4) ++ ++#define AR91XX_GPIO_COUNT 22 ++ ++#define AR933X_GPIO_COUNT 30 ++ ++#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14) ++#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13) ++ ++#define AR934X_GPIO_COUNT 32 ++#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17) ++ ++extern void __iomem *ar71xx_gpio_base; ++ ++static inline void ar71xx_gpio_wr(unsigned reg, u32 value) ++{ ++ __raw_writel(value, ar71xx_gpio_base + reg); ++} ++ ++static inline u32 ar71xx_gpio_rr(unsigned reg) ++{ ++ return __raw_readl(ar71xx_gpio_base + reg); ++} ++ ++void ar71xx_gpio_init(void) __init; ++void ar71xx_gpio_function_enable(u32 mask); ++void ar71xx_gpio_function_disable(u32 mask); ++void ar71xx_gpio_function_setup(u32 set, u32 clear); ++ ++/* ++ * DDR_CTRL block ++ */ ++#define AR71XX_DDR_REG_PCI_WIN0 0x7c ++#define AR71XX_DDR_REG_PCI_WIN1 0x80 ++#define AR71XX_DDR_REG_PCI_WIN2 0x84 ++#define AR71XX_DDR_REG_PCI_WIN3 0x88 ++#define AR71XX_DDR_REG_PCI_WIN4 0x8c ++#define AR71XX_DDR_REG_PCI_WIN5 0x90 ++#define AR71XX_DDR_REG_PCI_WIN6 0x94 ++#define AR71XX_DDR_REG_PCI_WIN7 0x98 ++#define AR71XX_DDR_REG_FLUSH_GE0 0x9c ++#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 ++#define AR71XX_DDR_REG_FLUSH_USB 0xa4 ++#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 ++ ++#define AR724X_DDR_REG_FLUSH_GE0 0x7c ++#define AR724X_DDR_REG_FLUSH_GE1 0x80 ++#define AR724X_DDR_REG_FLUSH_USB 0x84 ++#define AR724X_DDR_REG_FLUSH_PCIE 0x88 ++ ++#define AR91XX_DDR_REG_FLUSH_GE0 0x7c ++#define AR91XX_DDR_REG_FLUSH_GE1 0x80 ++#define AR91XX_DDR_REG_FLUSH_USB 0x84 ++#define AR91XX_DDR_REG_FLUSH_WMAC 0x88 ++ ++#define AR933X_DDR_REG_FLUSH_GE0 0x7c ++#define AR933X_DDR_REG_FLUSH_GE1 0x80 ++#define AR933X_DDR_REG_FLUSH_USB 0x84 ++#define AR933X_DDR_REG_FLUSH_WMAC 0x88 ++ ++#define AR934X_DDR_REG_FLUSH_GE0 0x9c ++#define AR934X_DDR_REG_FLUSH_GE1 0xa0 ++#define AR934X_DDR_REG_FLUSH_USB 0xa4 ++#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 ++ ++ ++#define PCI_WIN0_OFFS 0x10000000 ++#define PCI_WIN1_OFFS 0x11000000 ++#define PCI_WIN2_OFFS 0x12000000 ++#define PCI_WIN3_OFFS 0x13000000 ++#define PCI_WIN4_OFFS 0x14000000 ++#define PCI_WIN5_OFFS 0x15000000 ++#define PCI_WIN6_OFFS 0x16000000 ++#define PCI_WIN7_OFFS 0x07000000 ++ ++extern void __iomem *ar71xx_ddr_base; ++ ++static inline void ar71xx_ddr_wr(unsigned reg, u32 val) ++{ ++ __raw_writel(val, ar71xx_ddr_base + reg); ++} ++ ++static inline u32 ar71xx_ddr_rr(unsigned reg) ++{ ++ return __raw_readl(ar71xx_ddr_base + reg); ++} ++ ++void ar71xx_ddr_flush(u32 reg); ++ ++/* ++ * PCI block ++ */ ++#define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000) ++#define AR71XX_PCI_CFG_SIZE 0x100 ++ ++#define PCI_REG_CRP_AD_CBE 0x00 ++#define PCI_REG_CRP_WRDATA 0x04 ++#define PCI_REG_CRP_RDDATA 0x08 ++#define PCI_REG_CFG_AD 0x0c ++#define PCI_REG_CFG_CBE 0x10 ++#define PCI_REG_CFG_WRDATA 0x14 ++#define PCI_REG_CFG_RDDATA 0x18 ++#define PCI_REG_PCI_ERR 0x1c ++#define PCI_REG_PCI_ERR_ADDR 0x20 ++#define PCI_REG_AHB_ERR 0x24 ++#define PCI_REG_AHB_ERR_ADDR 0x28 ++ ++#define PCI_CRP_CMD_WRITE 0x00010000 ++#define PCI_CRP_CMD_READ 0x00000000 ++#define PCI_CFG_CMD_READ 0x0000000a ++#define PCI_CFG_CMD_WRITE 0x0000000b ++ ++#define PCI_IDSEL_ADL_START 17 ++ ++#define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000) ++#define AR724X_PCI_CFG_SIZE 0x1000 ++ ++#define AR724X_PCI_REG_APP 0x00 ++#define AR724X_PCI_REG_RESET 0x18 ++#define AR724X_PCI_REG_INT_STATUS 0x4c ++#define AR724X_PCI_REG_INT_MASK 0x50 ++ ++#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) ++#define AR724X_PCI_RESET_LINK_UP BIT(0) ++ ++#define AR724X_PCI_INT_DEV0 BIT(14) ++ ++/* ++ * RESET block ++ */ ++#define AR71XX_RESET_REG_TIMER 0x00 ++#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 ++#define AR71XX_RESET_REG_WDOG_CTRL 0x08 ++#define AR71XX_RESET_REG_WDOG 0x0c ++#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 ++#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 ++#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 ++#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c ++#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 ++#define AR71XX_RESET_REG_RESET_MODULE 0x24 ++#define AR71XX_RESET_REG_PERFC_CTRL 0x2c ++#define AR71XX_RESET_REG_PERFC0 0x30 ++#define AR71XX_RESET_REG_PERFC1 0x34 ++#define AR71XX_RESET_REG_REV_ID 0x90 ++ ++#define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18 ++#define AR91XX_RESET_REG_RESET_MODULE 0x1c ++#define AR91XX_RESET_REG_PERF_CTRL 0x20 ++#define AR91XX_RESET_REG_PERFC0 0x24 ++#define AR91XX_RESET_REG_PERFC1 0x28 ++ ++#define AR724X_RESET_REG_RESET_MODULE 0x1c ++ ++#define AR933X_RESET_REG_RESET_MODULE 0x1c ++#define AR933X_RESET_REG_BOOTSTRAP 0xac ++#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) ++#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) ++ ++#define AR934X_RESET_REG_RESET_MODULE 0x1c ++#define AR934X_RESET_REG_BOOTSTRAP 0xb0 ++/* 0 - 25MHz 1 - 40 MHz */ ++#define AR934X_REF_CLK_40 (1 << 4) ++ ++#define WDOG_CTRL_LAST_RESET BIT(31) ++#define WDOG_CTRL_ACTION_MASK 3 ++#define WDOG_CTRL_ACTION_NONE 0 /* no action */ ++#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */ ++#define WDOG_CTRL_ACTION_NMI 2 /* NMI */ ++#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */ ++ ++#define MISC_INT_ENET_LINK BIT(12) ++#define MISC_INT_DDR_PERF BIT(11) ++#define MISC_INT_TIMER4 BIT(10) ++#define MISC_INT_TIMER3 BIT(9) ++#define MISC_INT_TIMER2 BIT(8) ++#define MISC_INT_DMA BIT(7) ++#define MISC_INT_OHCI BIT(6) ++#define MISC_INT_PERFC BIT(5) ++#define MISC_INT_WDOG BIT(4) ++#define MISC_INT_UART BIT(3) ++#define MISC_INT_GPIO BIT(2) ++#define MISC_INT_ERROR BIT(1) ++#define MISC_INT_TIMER BIT(0) ++ ++#define PCI_INT_CORE BIT(4) ++#define PCI_INT_DEV2 BIT(2) ++#define PCI_INT_DEV1 BIT(1) ++#define PCI_INT_DEV0 BIT(0) ++ ++#define RESET_MODULE_EXTERNAL BIT(28) ++#define RESET_MODULE_FULL_CHIP BIT(24) ++#define RESET_MODULE_AMBA2WMAC BIT(22) ++#define RESET_MODULE_CPU_NMI BIT(21) ++#define RESET_MODULE_CPU_COLD BIT(20) ++#define RESET_MODULE_DMA BIT(19) ++#define RESET_MODULE_SLIC BIT(18) ++#define RESET_MODULE_STEREO BIT(17) ++#define RESET_MODULE_DDR BIT(16) ++#define RESET_MODULE_GE1_MAC BIT(13) ++#define RESET_MODULE_GE1_PHY BIT(12) ++#define RESET_MODULE_USBSUS_OVERRIDE BIT(10) ++#define RESET_MODULE_GE0_MAC BIT(9) ++#define RESET_MODULE_GE0_PHY BIT(8) ++#define RESET_MODULE_USB_OHCI_DLL BIT(6) ++#define RESET_MODULE_USB_HOST BIT(5) ++#define RESET_MODULE_USB_PHY BIT(4) ++#define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3) ++#define RESET_MODULE_PCI_BUS BIT(1) ++#define RESET_MODULE_PCI_CORE BIT(0) ++ ++#define AR724X_RESET_GE1_MDIO BIT(23) ++#define AR724X_RESET_GE0_MDIO BIT(22) ++#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) ++#define AR724X_RESET_PCIE_PHY BIT(7) ++#define AR724X_RESET_PCIE BIT(6) ++#define AR724X_RESET_USB_HOST BIT(5) ++#define AR724X_RESET_USB_PHY BIT(4) ++#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) ++ ++#define AR933X_RESET_WMAC BIT(11) ++#define AR933X_RESET_GE1_MDIO BIT(23) ++#define AR933X_RESET_GE0_MDIO BIT(22) ++#define AR933X_RESET_GE1_MAC BIT(13) ++#define AR933X_RESET_GE0_MAC BIT(9) ++ ++#define REV_ID_MAJOR_MASK 0xfff0 ++#define REV_ID_MAJOR_AR71XX 0x00a0 ++#define REV_ID_MAJOR_AR913X 0x00b0 ++#define REV_ID_MAJOR_AR7240 0x00c0 ++#define REV_ID_MAJOR_AR7241 0x0100 ++#define REV_ID_MAJOR_AR7242 0x1100 ++#define REV_ID_MAJOR_AR9330 0x0110 ++#define REV_ID_MAJOR_AR9331 0x1110 ++#define REV_ID_MAJOR_AR9341 0x0120 ++#define REV_ID_MAJOR_AR9342 0x1120 ++#define REV_ID_MAJOR_AR9344 0x2120 ++ ++#define AR71XX_REV_ID_MINOR_MASK 0x3 ++#define AR71XX_REV_ID_MINOR_AR7130 0x0 ++#define AR71XX_REV_ID_MINOR_AR7141 0x1 ++#define AR71XX_REV_ID_MINOR_AR7161 0x2 ++#define AR71XX_REV_ID_REVISION_MASK 0x3 ++#define AR71XX_REV_ID_REVISION_SHIFT 2 ++ ++#define AR91XX_REV_ID_MINOR_MASK 0x3 ++#define AR91XX_REV_ID_MINOR_AR9130 0x0 ++#define AR91XX_REV_ID_MINOR_AR9132 0x1 ++#define AR91XX_REV_ID_REVISION_MASK 0x3 ++#define AR91XX_REV_ID_REVISION_SHIFT 2 ++ ++#define AR724X_REV_ID_REVISION_MASK 0x3 ++ ++#define AR933X_REV_ID_REVISION_MASK 0xf ++ ++#define AR934X_REV_ID_REVISION_MASK 0xf ++ ++extern void __iomem *ar71xx_reset_base; ++ ++static inline void ar71xx_reset_wr(unsigned reg, u32 val) ++{ ++ __raw_writel(val, ar71xx_reset_base + reg); ++} ++ ++static inline u32 ar71xx_reset_rr(unsigned reg) ++{ ++ return __raw_readl(ar71xx_reset_base + reg); ++} ++ ++void ar71xx_device_stop(u32 mask); ++void ar71xx_device_start(u32 mask); ++int ar71xx_device_stopped(u32 mask); ++ ++/* ++ * SPI block ++ */ ++#define SPI_REG_FS 0x00 /* Function Select */ ++#define SPI_REG_CTRL 0x04 /* SPI Control */ ++#define SPI_REG_IOC 0x08 /* SPI I/O Control */ ++#define SPI_REG_RDS 0x0c /* Read Data Shift */ ++ ++#define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ ++ ++#define SPI_CTRL_RD BIT(6) /* Remap Disable */ ++#define SPI_CTRL_DIV_MASK 0x3f ++ ++#define SPI_IOC_DO BIT(0) /* Data Out pin */ ++#define SPI_IOC_CLK BIT(8) /* CLK pin */ ++#define SPI_IOC_CS(n) BIT(16 + (n)) ++#define SPI_IOC_CS0 SPI_IOC_CS(0) ++#define SPI_IOC_CS1 SPI_IOC_CS(1) ++#define SPI_IOC_CS2 SPI_IOC_CS(2) ++#define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2) ++ ++void ar71xx_flash_acquire(void); ++void ar71xx_flash_release(void); ++ ++/* ++ * MII_CTRL block ++ */ ++#define MII_REG_MII0_CTRL 0x00 ++#define MII_REG_MII1_CTRL 0x04 ++ ++#define MII0_CTRL_IF_GMII 0 ++#define MII0_CTRL_IF_MII 1 ++#define MII0_CTRL_IF_RGMII 2 ++#define MII0_CTRL_IF_RMII 3 ++ ++#define MII1_CTRL_IF_RGMII 0 ++#define MII1_CTRL_IF_RMII 1 ++ ++#endif /* __ASSEMBLER__ */ ++ ++#endif /* __ASM_MACH_AR71XX_H */ +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,26 @@ ++/* ++ * AR91xx parallel flash driver platform data definitions ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __AR91XX_FLASH_H ++#define __AR91XX_FLASH_H ++ ++struct mtd_partition; ++ ++struct ar91xx_flash_platform_data { ++ unsigned int width; ++ u8 is_shared:1; ++#ifdef CONFIG_MTD_PARTITIONS ++ unsigned int nr_parts; ++ struct mtd_partition *parts; ++#endif ++}; ++ ++#endif /* __AR91XX_FLASH_H */ +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar933x_uart.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar933x_uart.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar933x_uart.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar933x_uart.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,67 @@ ++/* ++ * Atheros AR933X UART defines ++ * ++ * Copyright (C) 2011 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __AR933X_UART_H ++#define __AR933X_UART_H ++ ++#define AR933X_UART_REGS_SIZE 20 ++#define AR933X_UART_FIFO_SIZE 16 ++ ++#define AR933X_UART_DATA_REG 0x00 ++#define AR933X_UART_CS_REG 0x04 ++#define AR933X_UART_CLOCK_REG 0x08 ++#define AR933X_UART_INT_REG 0x0c ++#define AR933X_UART_INT_EN_REG 0x10 ++ ++#define AR933X_UART_DATA_TX_RX_MASK 0xff ++#define AR933X_UART_DATA_RX_CSR BIT(8) ++#define AR933X_UART_DATA_TX_CSR BIT(9) ++ ++#define AR933X_UART_CS_PARITY_S 0 ++#define AR933X_UART_CS_PARITY_M 0x3 ++#define AR933X_UART_CS_PARITY_NONE 0 ++#define AR933X_UART_CS_PARITY_ODD 1 ++#define AR933X_UART_CS_PARITY_EVEN 2 ++#define AR933X_UART_CS_IF_MODE_S 2 ++#define AR933X_UART_CS_IF_MODE_M 0x3 ++#define AR933X_UART_CS_IF_MODE_NONE 0 ++#define AR933X_UART_CS_IF_MODE_DTE 1 ++#define AR933X_UART_CS_IF_MODE_DCE 2 ++#define AR933X_UART_CS_FLOW_CTRL_S 4 ++#define AR933X_UART_CS_FLOW_CTRL_M 0x3 ++#define AR933X_UART_CS_DMA_EN BIT(6) ++#define AR933X_UART_CS_TX_READY_ORIDE BIT(7) ++#define AR933X_UART_CS_RX_READY_ORIDE BIT(8) ++#define AR933X_UART_CS_TX_READY BIT(9) ++#define AR933X_UART_CS_RX_BREAK BIT(10) ++#define AR933X_UART_CS_TX_BREAK BIT(11) ++#define AR933X_UART_CS_HOST_INT BIT(12) ++#define AR933X_UART_CS_HOST_INT_EN BIT(13) ++#define AR933X_UART_CS_TX_BUSY BIT(14) ++#define AR933X_UART_CS_RX_BUSY BIT(15) ++ ++#define AR933X_UART_CLOCK_STEP_M 0xffff ++#define AR933X_UART_CLOCK_SCALE_M 0xfff ++#define AR933X_UART_CLOCK_SCALE_S 16 ++#define AR933X_UART_CLOCK_STEP_M 0xffff ++ ++#define AR933X_UART_INT_RX_VALID BIT(0) ++#define AR933X_UART_INT_TX_READY BIT(1) ++#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2) ++#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3) ++#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4) ++#define AR933X_UART_INT_RX_PARITY_ERR BIT(5) ++#define AR933X_UART_INT_RX_BREAK_ON BIT(6) ++#define AR933X_UART_INT_RX_BREAK_OFF BIT(7) ++#define AR933X_UART_INT_RX_FULL BIT(8) ++#define AR933X_UART_INT_TX_EMPTY BIT(9) ++#define AR933X_UART_INT_ALLINTS 0x3ff ++ ++#endif /* __AR933X_UART_H */ +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar933x_uart_platform.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar933x_uart_platform.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar933x_uart_platform.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar933x_uart_platform.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,18 @@ ++/* ++ * Platform data definition for Atheros AR933X UART ++ * ++ * Copyright (C) 2011 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _AR933X_UART_PLATFORM_H ++#define _AR933X_UART_PLATFORM_H ++ ++struct ar933x_uart_platform_data { ++ unsigned uartclk; ++}; ++ ++#endif /* _AR933X_UART_PLATFORM_H */ +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,56 @@ ++/* ++ * Atheros AR71xx specific CPU feature overrides ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This file was derived from: include/asm-mips/cpu-features.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * Copyright (C) 2004 Maciej W. Rozycki ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++#ifndef __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H ++#define __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H ++ ++#define cpu_has_tlb 1 ++#define cpu_has_4kex 1 ++#define cpu_has_3k_cache 0 ++#define cpu_has_4k_cache 1 ++#define cpu_has_tx39_cache 0 ++#define cpu_has_sb1_cache 0 ++#define cpu_has_fpu 0 ++#define cpu_has_32fpr 0 ++#define cpu_has_counter 1 ++#define cpu_has_watch 1 ++#define cpu_has_divec 1 ++ ++#define cpu_has_prefetch 1 ++#define cpu_has_ejtag 1 ++#define cpu_has_llsc 1 ++ ++#define cpu_has_mips16 1 ++#define cpu_has_mdmx 0 ++#define cpu_has_mips3d 0 ++#define cpu_has_smartmips 0 ++ ++#define cpu_has_mips32r1 1 ++#define cpu_has_mips32r2 1 ++#define cpu_has_mips64r1 0 ++#define cpu_has_mips64r2 0 ++ ++#define cpu_has_dsp 0 ++#define cpu_has_mipsmt 0 ++ ++#define cpu_has_64bits 0 ++#define cpu_has_64bit_zero_reg 0 ++#define cpu_has_64bit_gp_regs 0 ++#define cpu_has_64bit_addresses 0 ++ ++#define cpu_dcache_line_size() 32 ++#define cpu_icache_line_size() 32 ++ ++#endif /* __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H */ +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/gpio.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/gpio.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/gpio.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,53 @@ ++/* ++ * Atheros AR71xx GPIO API definitions ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++ ++#ifndef __ASM_MACH_AR71XX_GPIO_H ++#define __ASM_MACH_AR71XX_GPIO_H ++ ++#define ARCH_NR_GPIOS 64 ++#include ++ ++#include ++ ++extern unsigned long ar71xx_gpio_count; ++extern void __ar71xx_gpio_set_value(unsigned gpio, int value); ++extern int __ar71xx_gpio_get_value(unsigned gpio); ++ ++static inline int gpio_to_irq(unsigned gpio) ++{ ++ return AR71XX_GPIO_IRQ(gpio); ++} ++ ++static inline int irq_to_gpio(unsigned irq) ++{ ++ return irq - AR71XX_GPIO_IRQ_BASE; ++} ++ ++static inline int gpio_get_value(unsigned gpio) ++{ ++ if (gpio < ar71xx_gpio_count) ++ return __ar71xx_gpio_get_value(gpio); ++ ++ return __gpio_get_value(gpio); ++} ++ ++static inline void gpio_set_value(unsigned gpio, int value) ++{ ++ if (gpio < ar71xx_gpio_count) ++ __ar71xx_gpio_set_value(gpio, value); ++ else ++ __gpio_set_value(gpio, value); ++} ++ ++#define gpio_cansleep __gpio_cansleep ++ ++#endif /* __ASM_MACH_AR71XX_GPIO_H */ +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/irq.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/irq.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/irq.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/irq.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,17 @@ ++/* ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++#ifndef __ASM_MACH_AR71XX_IRQ_H ++#define __ASM_MACH_AR71XX_IRQ_H ++ ++#define MIPS_CPU_IRQ_BASE 0 ++#define NR_IRQS 80 ++ ++#include_next ++ ++#endif /* __ASM_MACH_AR71XX_IRQ_H */ +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,32 @@ ++/* ++ * Atheros AR71xx specific kernel entry setup ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++#ifndef __ASM_MACH_AR71XX_KERNEL_ENTRY_H ++#define __ASM_MACH_AR71XX_KERNEL_ENTRY_H ++ ++ /* ++ * Some bootloaders set the 'Kseg0 coherency algorithm' to ++ * 'Cacheable, noncoherent, write-through, no write allocate' ++ * and this cause performance issues. Let's go and change it to ++ * 'Cacheable, noncoherent, write-back, write allocate' ++ */ ++ .macro kernel_entry_setup ++ mfc0 t0, CP0_CONFIG ++ li t1, ~CONF_CM_CMASK ++ and t0, t1 ++ ori t0, CONF_CM_CACHABLE_NONCOHERENT ++ mtc0 t0, CP0_CONFIG ++ nop ++ .endm ++ ++ .macro smp_slave_setup ++ .endm ++ ++#endif /* __ASM_MACH_AR71XX_KERNEL_ENTRY_H */ +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/mach-rb750.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/mach-rb750.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/mach-rb750.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/mach-rb750.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,66 @@ ++/* ++ * MikroTik RouterBOARD 750 definitions ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++#ifndef _MACH_RB750_H ++#define _MACH_RB750_H ++ ++#include ++ ++#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */ ++#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */ ++#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */ ++#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */ ++#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */ ++#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */ ++#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */ ++#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */ ++#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */ ++#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */ ++#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */ ++#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */ ++#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */ ++#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */ ++#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */ ++ ++#define RB750_GPIO_BTN_RESET 1 ++#define RB750_GPIO_SPI_CS0 2 ++#define RB750_GPIO_LED_ACT 12 ++#define RB750_GPIO_LED_PORT1 13 ++#define RB750_GPIO_LED_PORT2 14 ++#define RB750_GPIO_LED_PORT3 15 ++#define RB750_GPIO_LED_PORT4 16 ++#define RB750_GPIO_LED_PORT5 17 ++ ++#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT) ++#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1) ++#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2) ++#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3) ++#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4) ++#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5) ++ ++#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE) ++ ++#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \ ++ RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT) ++ ++struct rb750_led_data { ++ char *name; ++ char *default_trigger; ++ u32 mask; ++ int active_low; ++}; ++ ++struct rb750_led_platform_data { ++ int num_leds; ++ struct rb750_led_data *leds; ++}; ++ ++int rb750_latch_change(u32 mask_clr, u32 mask_set); ++ ++#endif /* _MACH_RB750_H */ +\ No newline at end of file +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/mangle-port.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/mangle-port.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/mangle-port.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/mangle-port.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,45 @@ ++/* ++ * Copyright (C) 2008 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_MACH_AR71XX_MANGLE_PORT_H ++#define __ASM_MACH_AR71XX_MANGLE_PORT_H ++ ++#define __swizzle_addr_b(port) ((port) ^ 3) ++#define __swizzle_addr_w(port) ((port) ^ 2) ++#define __swizzle_addr_l(port) (port) ++#define __swizzle_addr_q(port) (port) ++ ++#if defined(CONFIG_SWAP_IO_SPACE) ++ ++# define ioswabb(a, x) (x) ++# define __mem_ioswabb(a, x) (x) ++# define ioswabw(a, x) le16_to_cpu(x) ++# define __mem_ioswabw(a, x) (x) ++# define ioswabl(a, x) le32_to_cpu(x) ++# define __mem_ioswabl(a, x) (x) ++# define ioswabq(a, x) le64_to_cpu(x) ++# define __mem_ioswabq(a, x) (x) ++ ++#else ++ ++# define ioswabb(a, x) (x) ++# define __mem_ioswabb(a, x) (x) ++# define ioswabw(a, x) (x) ++# define __mem_ioswabw(a, x) cpu_to_le16(x) ++# define ioswabl(a, x) (x) ++# define __mem_ioswabl(a, x) cpu_to_le32(x) ++# define ioswabq(a, x) (x) ++# define __mem_ioswabq(a, x) cpu_to_le64(x) ++ ++#endif ++ ++#endif /* __ASM_MACH_AR71XX_MANGLE_PORT_H */ +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/pci.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/pci.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/pci.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,46 @@ ++/* ++ * Atheros AR71xx SoC specific PCI definitions ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_MACH_AR71XX_PCI_H ++#define __ASM_MACH_AR71XX_PCI_H ++ ++struct pci_dev; ++ ++struct ar71xx_pci_irq { ++ int irq; ++ u8 slot; ++ u8 pin; ++}; ++ ++#ifdef CONFIG_PCI ++extern int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev); ++extern unsigned ar71xx_pci_nr_irqs __initdata; ++extern struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata; ++ ++int ar71xx_pcibios_map_irq(const struct pci_dev *dev, ++ uint8_t slot, uint8_t pin) __init; ++int ar71xx_pcibios_init(void) __init; ++ ++int ar71xx_pci_be_handler(int is_fixup); ++ ++int ar724x_pcibios_map_irq(const struct pci_dev *dev, ++ uint8_t slot, uint8_t pin) __init; ++int ar724x_pcibios_init(void) __init; ++ ++int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) __init; ++#else ++static inline int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) ++{ ++ return 0; ++} ++#endif ++ ++#endif /* __ASM_MACH_AR71XX_PCI_H */ +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/platform.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/platform.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/platform.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/platform.h 2011-08-24 18:17:23.000000000 +0200 +@@ -0,0 +1,63 @@ ++/* ++ * Atheros AR71xx SoC specific platform data definitions ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_MACH_AR71XX_PLATFORM_H ++#define __ASM_MACH_AR71XX_PLATFORM_H ++ ++#include ++#include ++#include ++#include ++ ++struct ag71xx_platform_data { ++ phy_interface_t phy_if_mode; ++ u32 phy_mask; ++ int speed; ++ int duplex; ++ u32 reset_bit; ++ u32 mii_if; ++ u8 mac_addr[ETH_ALEN]; ++ struct device *mii_bus_dev; ++ ++ u8 has_gbit:1; ++ u8 is_ar91xx:1; ++ u8 is_ar7240:1; ++ u8 is_ar724x:1; ++ u8 has_ar8216:1; ++ u8 has_ar7240_switch:1; ++ ++ void (*ddr_flush)(void); ++ void (*set_pll)(int speed); ++ ++ u32 fifo_cfg1; ++ u32 fifo_cfg2; ++ u32 fifo_cfg3; ++}; ++ ++struct ag71xx_mdio_platform_data { ++ u32 phy_mask; ++ int is_ar7240; ++}; ++ ++struct ar71xx_ehci_platform_data { ++ u8 is_ar91xx; ++}; ++ ++struct ar71xx_spi_platform_data { ++ unsigned bus_num; ++ unsigned num_chipselect; ++ u32 (*get_ioc_base)(u8 chip_select, int cs_high, int is_on); ++}; ++ ++#define AR71XX_SPI_CS_INACTIVE 0 ++#define AR71XX_SPI_CS_ACTIVE 1 ++ ++#endif /* __ASM_MACH_AR71XX_PLATFORM_H */ +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,48 @@ ++/* ++ * SPI driver definitions for the CPLD chip on the Mikrotik RB4xx boards ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This file was based on the patches for Linux 2.6.27.39 published by ++ * MikroTik for their RouterBoard 4xx series devices. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#define CPLD_GPIO_nLED1 0 ++#define CPLD_GPIO_nLED2 1 ++#define CPLD_GPIO_nLED3 2 ++#define CPLD_GPIO_nLED4 3 ++#define CPLD_GPIO_FAN 4 ++#define CPLD_GPIO_ALE 5 ++#define CPLD_GPIO_CLE 6 ++#define CPLD_GPIO_nCE 7 ++#define CPLD_GPIO_nLED5 8 ++ ++#define CPLD_NUM_GPIOS 9 ++ ++#define CPLD_CFG_nLED1 BIT(CPLD_GPIO_nLED1) ++#define CPLD_CFG_nLED2 BIT(CPLD_GPIO_nLED2) ++#define CPLD_CFG_nLED3 BIT(CPLD_GPIO_nLED3) ++#define CPLD_CFG_nLED4 BIT(CPLD_GPIO_nLED4) ++#define CPLD_CFG_FAN BIT(CPLD_GPIO_FAN) ++#define CPLD_CFG_ALE BIT(CPLD_GPIO_ALE) ++#define CPLD_CFG_CLE BIT(CPLD_GPIO_CLE) ++#define CPLD_CFG_nCE BIT(CPLD_GPIO_nCE) ++#define CPLD_CFG_nLED5 BIT(CPLD_GPIO_nLED5) ++ ++struct rb4xx_cpld_platform_data { ++ unsigned gpio_base; ++}; ++ ++extern int rb4xx_cpld_change_cfg(unsigned mask, unsigned value); ++extern int rb4xx_cpld_read(unsigned char *rx_buf, ++ const unsigned char *verify_buf, ++ unsigned cnt); ++extern int rb4xx_cpld_read_from(unsigned addr, ++ unsigned char *rx_buf, ++ const unsigned char *verify_buf, ++ unsigned cnt); ++extern int rb4xx_cpld_write(const unsigned char *buf, unsigned count); +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/war.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/war.h +--- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/war.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/war.h 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,25 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle ++ */ ++#ifndef __ASM_MACH_AR71XX_WAR_H ++#define __ASM_MACH_AR71XX_WAR_H ++ ++#define R4600_V1_INDEX_ICACHEOP_WAR 0 ++#define R4600_V1_HIT_CACHEOP_WAR 0 ++#define R4600_V2_HIT_CACHEOP_WAR 0 ++#define R5432_CP0_INTERRUPT_WAR 0 ++#define BCM1250_M3_WAR 0 ++#define SIBYTE_1956_WAR 0 ++#define MIPS4K_ICACHE_REFILL_WAR 0 ++#define MIPS_CACHE_SYNC_WAR 0 ++#define TX49XX_ICACHE_INDEX_INV_WAR 0 ++#define RM9000_CDEX_SMP_WAR 0 ++#define ICACHE_REFILLS_WORKAROUND_WAR 0 ++#define R10000_LLSC_WAR 0 ++#define MIPS34K_MISSED_ITLB_WAR 0 ++ ++#endif /* __ASM_MACH_AR71XX_WAR_H */ +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/time.h linux-2.6.39/arch/mips/include/asm/time.h +--- linux-2.6.39.orig/arch/mips/include/asm/time.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/include/asm/time.h 2011-08-24 18:17:24.000000000 +0200 +@@ -52,6 +52,7 @@ + */ + #ifdef CONFIG_CEVT_R4K_LIB + extern unsigned int __weak get_c0_compare_int(void); ++extern unsigned int __weak get_c0_compare_irq(void); + extern int r4k_clockevent_init(void); + #endif + +diff -Nur linux-2.6.39.orig/arch/mips/kernel/traps.c linux-2.6.39/arch/mips/kernel/traps.c +--- linux-2.6.39.orig/arch/mips/kernel/traps.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/kernel/traps.c 2011-08-24 18:17:24.000000000 +0200 +@@ -54,6 +54,7 @@ + #include + #include + #include ++#include + + extern void check_wait(void); + extern asmlinkage void r4k_wait(void); +@@ -1576,6 +1577,8 @@ + if (cpu_has_mips_r2) { + cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; + cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; ++ if (get_c0_compare_irq) ++ cp0_compare_irq = get_c0_compare_irq(); + cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; + if (cp0_perfcount_irq == cp0_compare_irq) + cp0_perfcount_irq = -1; +diff -Nur linux-2.6.39.orig/arch/mips/pci/Makefile linux-2.6.39/arch/mips/pci/Makefile +--- linux-2.6.39.orig/arch/mips/pci/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/pci/Makefile 2011-08-24 18:17:24.000000000 +0200 +@@ -18,6 +18,7 @@ + obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o + obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ + ops-bcm63xx.o ++obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o pci-ar724x.o + + # + # These are still pretty much in the old state, watch, go blind. +diff -Nur linux-2.6.39.orig/arch/mips/pci/pci-ar71xx.c linux-2.6.39/arch/mips/pci/pci-ar71xx.c +--- linux-2.6.39.orig/arch/mips/pci/pci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/pci/pci-ar71xx.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,415 @@ ++/* ++ * Atheros AR71xx PCI host controller driver ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#undef DEBUG ++#ifdef DEBUG ++#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args) ++#else ++#define DBG(fmt, args...) ++#endif ++ ++#define AR71XX_PCI_DELAY 100 /* msecs */ ++ ++#if 0 ++#define PCI_IDSEL_BASE PCI_IDSEL_ADL_START ++#else ++#define PCI_IDSEL_BASE 0 ++#endif ++ ++static void __iomem *ar71xx_pcicfg_base; ++static DEFINE_SPINLOCK(ar71xx_pci_lock); ++static int ar71xx_pci_fixup_enable; ++ ++static inline void ar71xx_pci_delay(void) ++{ ++ mdelay(AR71XX_PCI_DELAY); ++} ++ ++/* Byte lane enable bits */ ++static u8 ble_table[4][4] = { ++ {0x0, 0xf, 0xf, 0xf}, ++ {0xe, 0xd, 0xb, 0x7}, ++ {0xc, 0xf, 0x3, 0xf}, ++ {0xf, 0xf, 0xf, 0xf}, ++}; ++ ++static inline u32 ar71xx_pci_get_ble(int where, int size, int local) ++{ ++ u32 t; ++ ++ t = ble_table[size & 3][where & 3]; ++ BUG_ON(t == 0xf); ++ t <<= (local) ? 20 : 4; ++ return t; ++} ++ ++static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, ++ int where) ++{ ++ u32 ret; ++ ++ if (!bus->number) { ++ /* type 0 */ ++ ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn))) ++ | (PCI_FUNC(devfn) << 8) | (where & ~3); ++ } else { ++ /* type 1 */ ++ ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) ++ | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1; ++ } ++ ++ return ret; ++} ++ ++int ar71xx_pci_be_handler(int is_fixup) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ u32 pci_err; ++ u32 ahb_err; ++ ++ pci_err = __raw_readl(base + PCI_REG_PCI_ERR) & 3; ++ if (pci_err) { ++ if (!is_fixup) ++ printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n", ++ pci_err, ++ __raw_readl(base + PCI_REG_PCI_ERR_ADDR)); ++ ++ __raw_writel(pci_err, base + PCI_REG_PCI_ERR); ++ } ++ ++ ahb_err = __raw_readl(base + PCI_REG_AHB_ERR) & 1; ++ if (ahb_err) { ++ if (!is_fixup) ++ printk(KERN_ALERT "AHB error at AHB address 0x%x\n", ++ __raw_readl(base + PCI_REG_AHB_ERR_ADDR)); ++ ++ __raw_writel(ahb_err, base + PCI_REG_AHB_ERR); ++ } ++ ++ return (ahb_err | pci_err) ? 1 : 0; ++} ++ ++static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, ++ unsigned int devfn, int where, int size, u32 cmd) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ u32 addr; ++ ++ addr = ar71xx_pci_bus_addr(bus, devfn, where); ++ ++ DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n", ++ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), ++ where, size, addr); ++ ++ __raw_writel(addr, base + PCI_REG_CFG_AD); ++ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), ++ base + PCI_REG_CFG_CBE); ++ ++ return ar71xx_pci_be_handler(1); ++} ++ ++static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 *value) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; ++ unsigned long flags; ++ u32 data; ++ int retry = 0; ++ int ret; ++ ++ ret = PCIBIOS_SUCCESSFUL; ++ ++ DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number, ++ PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); ++ ++retry: ++ spin_lock_irqsave(&ar71xx_pci_lock, flags); ++ ++ if (bus->number == 0 && devfn == 0) { ++ u32 t; ++ ++ t = PCI_CRP_CMD_READ | (where & ~3); ++ ++ __raw_writel(t, base + PCI_REG_CRP_AD_CBE); ++ data = __raw_readl(base + PCI_REG_CRP_RDDATA); ++ ++ DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data); ++ ++ } else { ++ int err; ++ ++ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, ++ PCI_CFG_CMD_READ); ++ ++ if (err == 0) { ++ data = __raw_readl(base + PCI_REG_CFG_RDDATA); ++ } else { ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ data = ~0; ++ } ++ } ++ ++ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); ++ ++ DBG("PCI: read config: data=%08x raw=%08x\n", ++ (data >> (8 * (where & 3))) & mask[size & 7], data); ++ ++ *value = (data >> (8 * (where & 3))) & mask[size & 7]; ++ ++ /* ++ * PCI controller bug: sometimes reads to the PCI_COMMAND register ++ * return 0xffff, even though the PCI trace shows the correct value. ++ * Work around this by retrying reads to this register ++ */ ++ if (where == PCI_COMMAND && (*value & 0xffff) == 0xffff && retry++ < 2) ++ goto retry; ++ ++ return ret; ++} ++ ++static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 value) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ unsigned long flags; ++ int ret; ++ ++ DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n", ++ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), ++ where, size, value); ++ ++ value = value << (8 * (where & 3)); ++ ret = PCIBIOS_SUCCESSFUL; ++ ++ spin_lock_irqsave(&ar71xx_pci_lock, flags); ++ if (bus->number == 0 && devfn == 0) { ++ u32 t; ++ ++ t = PCI_CRP_CMD_WRITE | (where & ~3); ++ t |= ar71xx_pci_get_ble(where, size, 1); ++ ++ DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value); ++ ++ __raw_writel(t, base + PCI_REG_CRP_AD_CBE); ++ __raw_writel(value, base + PCI_REG_CRP_WRDATA); ++ } else { ++ int err; ++ ++ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, ++ PCI_CFG_CMD_WRITE); ++ ++ if (err == 0) ++ __raw_writel(value, base + PCI_REG_CFG_WRDATA); ++ else ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ } ++ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); ++ ++ return ret; ++} ++ ++static void ar71xx_pci_fixup(struct pci_dev *dev) ++{ ++ u32 t; ++ ++ if (!ar71xx_pci_fixup_enable) ++ return; ++ ++ if (dev->bus->number != 0 || dev->devfn != 0) ++ return; ++ ++ DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev), ++ dev->vendor, dev->device); ++ ++ /* setup COMMAND register */ ++ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE ++ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; ++ ++ pci_write_config_word(dev, PCI_COMMAND, t); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup); ++ ++int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, ++ uint8_t pin) ++{ ++ int irq = -1; ++ int i; ++ ++ slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE; ++ ++ for (i = 0; i < ar71xx_pci_nr_irqs; i++) { ++ struct ar71xx_pci_irq *entry; ++ ++ entry = &ar71xx_pci_irq_map[i]; ++ if (entry->slot == slot && entry->pin == pin) { ++ irq = entry->irq; ++ break; ++ } ++ } ++ ++ if (irq < 0) { ++ printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n", ++ pin, pci_name((struct pci_dev *)dev)); ++ } else { ++ printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n", ++ irq, pin, pci_name((struct pci_dev *)dev)); ++ } ++ ++ return irq; ++} ++ ++static struct pci_ops ar71xx_pci_ops = { ++ .read = ar71xx_pci_read_config, ++ .write = ar71xx_pci_write_config, ++}; ++ ++static struct resource ar71xx_pci_io_resource = { ++ .name = "PCI IO space", ++ .start = 0, ++ .end = 0, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource ar71xx_pci_mem_resource = { ++ .name = "PCI memory space", ++ .start = AR71XX_PCI_MEM_BASE, ++ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, ++ .flags = IORESOURCE_MEM ++}; ++ ++static struct pci_controller ar71xx_pci_controller = { ++ .pci_ops = &ar71xx_pci_ops, ++ .mem_resource = &ar71xx_pci_mem_resource, ++ .io_resource = &ar71xx_pci_io_resource, ++}; ++ ++static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) ++{ ++ void __iomem *base = ar71xx_reset_base; ++ u32 pending; ++ ++ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & ++ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ ++ if (pending & PCI_INT_DEV0) ++ generic_handle_irq(AR71XX_PCI_IRQ_DEV0); ++ ++ else if (pending & PCI_INT_DEV1) ++ generic_handle_irq(AR71XX_PCI_IRQ_DEV1); ++ ++ else if (pending & PCI_INT_DEV2) ++ generic_handle_irq(AR71XX_PCI_IRQ_DEV2); ++ ++ else if (pending & PCI_INT_CORE) ++ generic_handle_irq(AR71XX_PCI_IRQ_CORE); ++ ++ else ++ spurious_interrupt(); ++} ++ ++static void ar71xx_pci_irq_unmask(struct irq_data *d) ++{ ++ unsigned int irq = d->irq - AR71XX_PCI_IRQ_BASE; ++ void __iomem *base = ar71xx_reset_base; ++ u32 t; ++ ++ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ ++ /* flush write */ ++ (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++} ++ ++static void ar71xx_pci_irq_mask(struct irq_data *d) ++{ ++ unsigned int irq = d->irq - AR71XX_PCI_IRQ_BASE; ++ void __iomem *base = ar71xx_reset_base; ++ u32 t; ++ ++ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ ++ /* flush write */ ++ (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++} ++ ++static struct irq_chip ar71xx_pci_irq_chip = { ++ .name = "AR71XX PCI ", ++ .irq_mask = ar71xx_pci_irq_mask, ++ .irq_unmask = ar71xx_pci_irq_unmask, ++ .irq_mask_ack = ar71xx_pci_irq_mask, ++}; ++ ++static void __init ar71xx_pci_irq_init(void) ++{ ++ void __iomem *base = ar71xx_reset_base; ++ int i; ++ ++ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); ++ ++ for (i = AR71XX_PCI_IRQ_BASE; ++ i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, ++ handle_level_irq); ++ ++ irq_set_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler); ++} ++ ++int __init ar71xx_pcibios_init(void) ++{ ++ void __iomem *ddr_base = ar71xx_ddr_base; ++ ++ ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); ++ ar71xx_pci_delay(); ++ ++ ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); ++ ar71xx_pci_delay(); ++ ++ ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE, ++ AR71XX_PCI_CFG_SIZE); ++ if (ar71xx_pcicfg_base == NULL) ++ return -ENOMEM; ++ ++ __raw_writel(PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0); ++ __raw_writel(PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1); ++ __raw_writel(PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2); ++ __raw_writel(PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3); ++ __raw_writel(PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4); ++ __raw_writel(PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5); ++ __raw_writel(PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6); ++ __raw_writel(PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7); ++ ++ ar71xx_pci_delay(); ++ ++ /* clear bus errors */ ++ (void)ar71xx_pci_be_handler(1); ++ ++ ar71xx_pci_fixup_enable = 1; ++ ar71xx_pci_irq_init(); ++ register_pci_controller(&ar71xx_pci_controller); ++ ++ return 0; ++} +diff -Nur linux-2.6.39.orig/arch/mips/pci/pci-ar724x.c linux-2.6.39/arch/mips/pci/pci-ar724x.c +--- linux-2.6.39.orig/arch/mips/pci/pci-ar724x.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/arch/mips/pci/pci-ar724x.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,389 @@ ++/* ++ * Atheros AR724x PCI host controller driver ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#undef DEBUG ++#ifdef DEBUG ++#define DBG(fmt, args...) printk(KERN_INFO fmt, ## args) ++#else ++#define DBG(fmt, args...) ++#endif ++ ++static void __iomem *ar724x_pci_localcfg_base; ++static void __iomem *ar724x_pci_devcfg_base; ++static void __iomem *ar724x_pci_ctrl_base; ++static int ar724x_pci_fixup_enable; ++ ++static DEFINE_SPINLOCK(ar724x_pci_lock); ++ ++static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value) ++{ ++ unsigned long flags; ++ u32 data; ++ ++ spin_lock_irqsave(&ar724x_pci_lock, flags); ++ data = __raw_readl(base + (where & ~3)); ++ ++ switch (size) { ++ case 1: ++ if (where & 1) ++ data >>= 8; ++ if (where & 2) ++ data >>= 16; ++ data &= 0xFF; ++ break; ++ case 2: ++ if (where & 2) ++ data >>= 16; ++ data &= 0xFFFF; ++ break; ++ } ++ ++ *value = data; ++ spin_unlock_irqrestore(&ar724x_pci_lock, flags); ++} ++ ++static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value) ++{ ++ unsigned long flags; ++ u32 data; ++ int s; ++ ++ spin_lock_irqsave(&ar724x_pci_lock, flags); ++ data = __raw_readl(base + (where & ~3)); ++ ++ switch (size) { ++ case 1: ++ s = ((where & 3) << 3); ++ data &= ~(0xFF << s); ++ data |= ((value & 0xFF) << s); ++ break; ++ case 2: ++ s = ((where & 2) << 3); ++ data &= ~(0xFFFF << s); ++ data |= ((value & 0xFFFF) << s); ++ break; ++ case 4: ++ data = value; ++ break; ++ } ++ ++ __raw_writel(data, base + (where & ~3)); ++ /* flush write */ ++ (void)__raw_readl(base + (where & ~3)); ++ spin_unlock_irqrestore(&ar724x_pci_lock, flags); ++} ++ ++static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 *value) ++{ ++ ++ if (bus->number != 0 || devfn != 0) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value); ++ ++ DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n", ++ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), ++ where, size, *value); ++ ++ /* ++ * WAR for BAR issue - We are unable to access the PCI device space ++ * if we set the BAR with proper base address ++ */ ++ if ((where == 0x10) && (size == 4)) { ++ u32 val; ++ val = (ar71xx_soc == AR71XX_SOC_AR7240) ? 0xffff : 0x1000ffff; ++ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, val); ++ } ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 value) ++{ ++ if (bus->number != 0 || devfn != 0) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n", ++ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), ++ where, size, value); ++ ++ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value); ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static void ar724x_pci_fixup(struct pci_dev *dev) ++{ ++ u16 cmd; ++ ++ if (!ar724x_pci_fixup_enable) ++ return; ++ ++ if (dev->bus->number != 0 || dev->devfn != 0) ++ return; ++ ++ /* setup COMMAND register */ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | ++ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | ++ PCI_COMMAND_FAST_BACK; ++ ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup); ++ ++int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, ++ uint8_t pin) ++{ ++ int irq = -1; ++ int i; ++ ++ for (i = 0; i < ar71xx_pci_nr_irqs; i++) { ++ struct ar71xx_pci_irq *entry; ++ entry = &ar71xx_pci_irq_map[i]; ++ ++ if (entry->slot == slot && entry->pin == pin) { ++ irq = entry->irq; ++ break; ++ } ++ } ++ ++ if (irq < 0) ++ printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n", ++ pin, pci_name((struct pci_dev *)dev)); ++ else ++ printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n", ++ irq, pin, pci_name((struct pci_dev *)dev)); ++ ++ return irq; ++} ++ ++static struct pci_ops ar724x_pci_ops = { ++ .read = ar724x_pci_read_config, ++ .write = ar724x_pci_write_config, ++}; ++ ++static struct resource ar724x_pci_io_resource = { ++ .name = "PCI IO space", ++ .start = 0, ++ .end = 0, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource ar724x_pci_mem_resource = { ++ .name = "PCI memory space", ++ .start = AR71XX_PCI_MEM_BASE, ++ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, ++ .flags = IORESOURCE_MEM ++}; ++ ++static struct pci_controller ar724x_pci_controller = { ++ .pci_ops = &ar724x_pci_ops, ++ .mem_resource = &ar724x_pci_mem_resource, ++ .io_resource = &ar724x_pci_io_resource, ++}; ++ ++static void __init ar724x_pci_reset(void) ++{ ++ ar71xx_device_stop(AR724X_RESET_PCIE); ++ ar71xx_device_stop(AR724X_RESET_PCIE_PHY); ++ ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL); ++ udelay(100); ++ ++ ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL); ++ udelay(100); ++ ar71xx_device_start(AR724X_RESET_PCIE_PHY); ++ ar71xx_device_start(AR724X_RESET_PCIE); ++} ++ ++static int __init ar724x_pci_setup(void) ++{ ++ void __iomem *base = ar724x_pci_ctrl_base; ++ u32 t; ++ ++ /* setup COMMAND register */ ++ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | ++ PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK; ++ ++ ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t); ++ ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000); ++ ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000); ++ ++ t = __raw_readl(base + AR724X_PCI_REG_RESET); ++ if (t != 0x7) { ++ udelay(100000); ++ __raw_writel(0, base + AR724X_PCI_REG_RESET); ++ udelay(100); ++ __raw_writel(4, base + AR724X_PCI_REG_RESET); ++ udelay(100000); ++ } ++ ++ if (ar71xx_soc == AR71XX_SOC_AR7240) ++ t = AR724X_PCI_APP_LTSSM_ENABLE; ++ else ++ t = 0x1ffc1; ++ __raw_writel(t, base + AR724X_PCI_REG_APP); ++ /* flush write */ ++ (void) __raw_readl(base + AR724X_PCI_REG_APP); ++ udelay(1000); ++ ++ t = __raw_readl(base + AR724X_PCI_REG_RESET); ++ if ((t & AR724X_PCI_RESET_LINK_UP) == 0x0) { ++ printk(KERN_WARNING "PCI: no PCIe module found\n"); ++ return -ENODEV; ++ } ++ ++ if (ar71xx_soc == AR71XX_SOC_AR7241 || ++ ar71xx_soc == AR71XX_SOC_AR7242) { ++ t = __raw_readl(base + AR724X_PCI_REG_APP); ++ t |= BIT(16); ++ __raw_writel(t, base + AR724X_PCI_REG_APP); ++ } ++ ++ return 0; ++} ++ ++static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) ++{ ++ void __iomem *base = ar724x_pci_ctrl_base; ++ u32 pending; ++ ++ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & ++ __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ ++ if (pending & AR724X_PCI_INT_DEV0) ++ generic_handle_irq(AR71XX_PCI_IRQ_DEV0); ++ ++ else ++ spurious_interrupt(); ++} ++ ++static void ar724x_pci_irq_unmask(struct irq_data *d) ++{ ++ void __iomem *base = ar724x_pci_ctrl_base; ++ u32 t; ++ ++ switch (d->irq) { ++ case AR71XX_PCI_IRQ_DEV0: ++ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ __raw_writel(t | AR724X_PCI_INT_DEV0, ++ base + AR724X_PCI_REG_INT_MASK); ++ /* flush write */ ++ (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ } ++} ++ ++static void ar724x_pci_irq_mask(struct irq_data *d) ++{ ++ void __iomem *base = ar724x_pci_ctrl_base; ++ u32 t; ++ ++ switch (d->irq) { ++ case AR71XX_PCI_IRQ_DEV0: ++ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ __raw_writel(t & ~AR724X_PCI_INT_DEV0, ++ base + AR724X_PCI_REG_INT_MASK); ++ ++ /* flush write */ ++ (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ ++ t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); ++ __raw_writel(t | AR724X_PCI_INT_DEV0, ++ base + AR724X_PCI_REG_INT_STATUS); ++ ++ /* flush write */ ++ (void) __raw_readl(base + AR724X_PCI_REG_INT_STATUS); ++ } ++} ++ ++static struct irq_chip ar724x_pci_irq_chip = { ++ .name = "AR724X PCI ", ++ .irq_mask = ar724x_pci_irq_mask, ++ .irq_unmask = ar724x_pci_irq_unmask, ++ .irq_mask_ack = ar724x_pci_irq_mask, ++}; ++ ++static void __init ar724x_pci_irq_init(void) ++{ ++ void __iomem *base = ar724x_pci_ctrl_base; ++ u32 t; ++ int i; ++ ++ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); ++ if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY | ++ AR724X_RESET_PCIE_PHY_SERIAL)) { ++ return; ++ } ++ ++ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); ++ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); ++ ++ for (i = AR71XX_PCI_IRQ_BASE; ++ i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, ++ handle_level_irq); ++ ++ irq_set_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler); ++} ++ ++int __init ar724x_pcibios_init(void) ++{ ++ int ret = -ENOMEM; ++ ++ ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE, ++ AR724X_PCI_CRP_SIZE); ++ if (ar724x_pci_localcfg_base == NULL) ++ goto err; ++ ++ ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE, ++ AR724X_PCI_CFG_SIZE); ++ if (ar724x_pci_devcfg_base == NULL) ++ goto err_unmap_localcfg; ++ ++ ar724x_pci_ctrl_base = ioremap_nocache(AR724X_PCI_CTRL_BASE, ++ AR724X_PCI_CTRL_SIZE); ++ if (ar724x_pci_ctrl_base == NULL) ++ goto err_unmap_devcfg; ++ ++ ar724x_pci_reset(); ++ ret = ar724x_pci_setup(); ++ if (ret) ++ goto err_unmap_ctrl; ++ ++ ar724x_pci_fixup_enable = 1; ++ ar724x_pci_irq_init(); ++ register_pci_controller(&ar724x_pci_controller); ++ ++ return 0; ++ ++err_unmap_ctrl: ++ iounmap(ar724x_pci_ctrl_base); ++err_unmap_devcfg: ++ iounmap(ar724x_pci_devcfg_base); ++err_unmap_localcfg: ++ iounmap(ar724x_pci_localcfg_base); ++err: ++ return ret; ++} +diff -Nur linux-2.6.39.orig/drivers/Makefile linux-2.6.39/drivers/Makefile +--- linux-2.6.39.orig/drivers/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/Makefile 2011-08-24 18:17:24.000000000 +0200 +@@ -46,8 +46,8 @@ + obj-$(CONFIG_SCSI) += scsi/ + obj-$(CONFIG_ATA) += ata/ + obj-$(CONFIG_TARGET_CORE) += target/ +-obj-$(CONFIG_MTD) += mtd/ + obj-$(CONFIG_SPI) += spi/ ++obj-$(CONFIG_MTD) += mtd/ + obj-y += net/ + obj-$(CONFIG_ATM) += atm/ + obj-$(CONFIG_FUSION) += message/ +diff -Nur linux-2.6.39.orig/drivers/gpio/nxp_74hc153.c linux-2.6.39/drivers/gpio/nxp_74hc153.c +--- linux-2.6.39.orig/drivers/gpio/nxp_74hc153.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/gpio/nxp_74hc153.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,247 @@ ++/* ++ * NXP 74HC153 - Dual 4-input multiplexer GPIO driver ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define NXP_74HC153_NUM_GPIOS 8 ++#define NXP_74HC153_S0_MASK 0x1 ++#define NXP_74HC153_S1_MASK 0x2 ++#define NXP_74HC153_BANK_MASK 0x4 ++ ++struct nxp_74hc153_chip { ++ struct device *parent; ++ struct gpio_chip gpio_chip; ++ struct mutex lock; ++}; ++ ++static struct nxp_74hc153_chip *gpio_to_nxp(struct gpio_chip *gc) ++{ ++ return container_of(gc, struct nxp_74hc153_chip, gpio_chip); ++} ++ ++static int nxp_74hc153_direction_input(struct gpio_chip *gc, unsigned offset) ++{ ++ return 0; ++} ++ ++static int nxp_74hc153_direction_output(struct gpio_chip *gc, ++ unsigned offset, int val) ++{ ++ return -EINVAL; ++} ++ ++static int nxp_74hc153_get_value(struct gpio_chip *gc, unsigned offset) ++{ ++ struct nxp_74hc153_chip *nxp; ++ struct nxp_74hc153_platform_data *pdata; ++ unsigned s0; ++ unsigned s1; ++ unsigned pin; ++ int ret; ++ ++ nxp = gpio_to_nxp(gc); ++ pdata = nxp->parent->platform_data; ++ ++ s0 = !!(offset & NXP_74HC153_S0_MASK); ++ s1 = !!(offset & NXP_74HC153_S1_MASK); ++ pin = (offset & NXP_74HC153_BANK_MASK) ? pdata->gpio_pin_2y ++ : pdata->gpio_pin_1y; ++ ++ mutex_lock(&nxp->lock); ++ gpio_set_value(pdata->gpio_pin_s0, s0); ++ gpio_set_value(pdata->gpio_pin_s1, s1); ++ ret = gpio_get_value(pin); ++ mutex_unlock(&nxp->lock); ++ ++ return ret; ++} ++ ++static void nxp_74hc153_set_value(struct gpio_chip *gc, ++ unsigned offset, int val) ++{ ++ /* not supported */ ++} ++ ++static int __devinit nxp_74hc153_probe(struct platform_device *pdev) ++{ ++ struct nxp_74hc153_platform_data *pdata; ++ struct nxp_74hc153_chip *nxp; ++ struct gpio_chip *gc; ++ int err; ++ ++ pdata = pdev->dev.platform_data; ++ if (pdata == NULL) { ++ dev_dbg(&pdev->dev, "no platform data specified\n"); ++ return -EINVAL; ++ } ++ ++ nxp = kzalloc(sizeof(struct nxp_74hc153_chip), GFP_KERNEL); ++ if (nxp == NULL) { ++ dev_err(&pdev->dev, "no memory for private data\n"); ++ return -ENOMEM; ++ } ++ ++ err = gpio_request(pdata->gpio_pin_s0, dev_name(&pdev->dev)); ++ if (err) { ++ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", ++ pdata->gpio_pin_s0, err); ++ goto err_free_nxp; ++ } ++ ++ err = gpio_request(pdata->gpio_pin_s1, dev_name(&pdev->dev)); ++ if (err) { ++ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", ++ pdata->gpio_pin_s1, err); ++ goto err_free_s0; ++ } ++ ++ err = gpio_request(pdata->gpio_pin_1y, dev_name(&pdev->dev)); ++ if (err) { ++ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", ++ pdata->gpio_pin_1y, err); ++ goto err_free_s1; ++ } ++ ++ err = gpio_request(pdata->gpio_pin_2y, dev_name(&pdev->dev)); ++ if (err) { ++ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", ++ pdata->gpio_pin_2y, err); ++ goto err_free_1y; ++ } ++ ++ err = gpio_direction_output(pdata->gpio_pin_s0, 0); ++ if (err) { ++ dev_err(&pdev->dev, ++ "unable to set direction of gpio %u, err=%d\n", ++ pdata->gpio_pin_s0, err); ++ goto err_free_2y; ++ } ++ ++ err = gpio_direction_output(pdata->gpio_pin_s1, 0); ++ if (err) { ++ dev_err(&pdev->dev, ++ "unable to set direction of gpio %u, err=%d\n", ++ pdata->gpio_pin_s1, err); ++ goto err_free_2y; ++ } ++ ++ err = gpio_direction_input(pdata->gpio_pin_1y); ++ if (err) { ++ dev_err(&pdev->dev, ++ "unable to set direction of gpio %u, err=%d\n", ++ pdata->gpio_pin_1y, err); ++ goto err_free_2y; ++ } ++ ++ err = gpio_direction_input(pdata->gpio_pin_2y); ++ if (err) { ++ dev_err(&pdev->dev, ++ "unable to set direction of gpio %u, err=%d\n", ++ pdata->gpio_pin_2y, err); ++ goto err_free_2y; ++ } ++ ++ nxp->parent = &pdev->dev; ++ mutex_init(&nxp->lock); ++ ++ gc = &nxp->gpio_chip; ++ ++ gc->direction_input = nxp_74hc153_direction_input; ++ gc->direction_output = nxp_74hc153_direction_output; ++ gc->get = nxp_74hc153_get_value; ++ gc->set = nxp_74hc153_set_value; ++ gc->can_sleep = 1; ++ ++ gc->base = pdata->gpio_base; ++ gc->ngpio = NXP_74HC153_NUM_GPIOS; ++ gc->label = dev_name(nxp->parent); ++ gc->dev = nxp->parent; ++ gc->owner = THIS_MODULE; ++ ++ err = gpiochip_add(&nxp->gpio_chip); ++ if (err) { ++ dev_err(&pdev->dev, "unable to add gpio chip, err=%d\n", err); ++ goto err_free_2y; ++ } ++ ++ platform_set_drvdata(pdev, nxp); ++ return 0; ++ ++err_free_2y: ++ gpio_free(pdata->gpio_pin_2y); ++err_free_1y: ++ gpio_free(pdata->gpio_pin_1y); ++err_free_s1: ++ gpio_free(pdata->gpio_pin_s1); ++err_free_s0: ++ gpio_free(pdata->gpio_pin_s0); ++err_free_nxp: ++ kfree(nxp); ++ return err; ++} ++ ++static int nxp_74hc153_remove(struct platform_device *pdev) ++{ ++ struct nxp_74hc153_chip *nxp = platform_get_drvdata(pdev); ++ struct nxp_74hc153_platform_data *pdata = pdev->dev.platform_data; ++ ++ if (nxp) { ++ int err; ++ ++ err = gpiochip_remove(&nxp->gpio_chip); ++ if (err) { ++ dev_err(&pdev->dev, ++ "unable to remove gpio chip, err=%d\n", ++ err); ++ return err; ++ } ++ ++ gpio_free(pdata->gpio_pin_2y); ++ gpio_free(pdata->gpio_pin_1y); ++ gpio_free(pdata->gpio_pin_s1); ++ gpio_free(pdata->gpio_pin_s0); ++ ++ kfree(nxp); ++ platform_set_drvdata(pdev, NULL); ++ } ++ ++ return 0; ++} ++ ++static struct platform_driver nxp_74hc153_driver = { ++ .probe = nxp_74hc153_probe, ++ .remove = __devexit_p(nxp_74hc153_remove), ++ .driver = { ++ .name = NXP_74HC153_DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init nxp_74hc153_init(void) ++{ ++ return platform_driver_register(&nxp_74hc153_driver); ++} ++subsys_initcall(nxp_74hc153_init); ++ ++static void __exit nxp_74hc153_exit(void) ++{ ++ platform_driver_unregister(&nxp_74hc153_driver); ++} ++module_exit(nxp_74hc153_exit); ++ ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_DESCRIPTION("GPIO expander driver for NXP 74HC153"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" NXP_74HC153_DRIVER_NAME); +diff -Nur linux-2.6.39.orig/drivers/leds/leds-rb750.c linux-2.6.39/drivers/leds/leds-rb750.c +--- linux-2.6.39.orig/drivers/leds/leds-rb750.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/leds/leds-rb750.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,141 @@ ++/* ++ * LED driver for the RouterBOARD 750 ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define DRV_NAME "leds-rb750" ++ ++struct rb750_led_dev { ++ struct led_classdev cdev; ++ u32 mask; ++ int active_low; ++}; ++ ++struct rb750_led_drvdata { ++ struct rb750_led_dev *led_devs; ++ int num_leds; ++}; ++ ++static inline struct rb750_led_dev *to_rbled(struct led_classdev *led_cdev) ++{ ++ return (struct rb750_led_dev *)container_of(led_cdev, ++ struct rb750_led_dev, cdev); ++} ++ ++static void rb750_led_brightness_set(struct led_classdev *led_cdev, ++ enum led_brightness value) ++{ ++ struct rb750_led_dev *rbled = to_rbled(led_cdev); ++ int level; ++ ++ level = (value == LED_OFF) ? 0 : 1; ++ level ^= rbled->active_low; ++ ++ if (level) ++ rb750_latch_change(0, rbled->mask); ++ else ++ rb750_latch_change(rbled->mask, 0); ++} ++ ++static int __devinit rb750_led_probe(struct platform_device *pdev) ++{ ++ struct rb750_led_platform_data *pdata; ++ struct rb750_led_drvdata *drvdata; ++ int ret = 0; ++ int i; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata) ++ return -EINVAL; ++ ++ drvdata = kzalloc(sizeof(struct rb750_led_drvdata) + ++ sizeof(struct rb750_led_dev) * pdata->num_leds, ++ GFP_KERNEL); ++ if (!drvdata) ++ return -ENOMEM; ++ ++ drvdata->num_leds = pdata->num_leds; ++ drvdata->led_devs = (struct rb750_led_dev *) &drvdata[1]; ++ ++ for (i = 0; i < drvdata->num_leds; i++) { ++ struct rb750_led_dev *rbled = &drvdata->led_devs[i]; ++ struct rb750_led_data *led_data = &pdata->leds[i]; ++ ++ rbled->cdev.name = led_data->name; ++ rbled->cdev.default_trigger = led_data->default_trigger; ++ rbled->cdev.brightness_set = rb750_led_brightness_set; ++ rbled->cdev.brightness = LED_OFF; ++ ++ rbled->mask = led_data->mask; ++ rbled->active_low = !!led_data->active_low; ++ ++ ret = led_classdev_register(&pdev->dev, &rbled->cdev); ++ if (ret) ++ goto err; ++ } ++ ++ platform_set_drvdata(pdev, drvdata); ++ return 0; ++ ++err: ++ for (i = i - 1; i >= 0; i--) ++ led_classdev_unregister(&drvdata->led_devs[i].cdev); ++ ++ kfree(drvdata); ++ return ret; ++} ++ ++static int __devexit rb750_led_remove(struct platform_device *pdev) ++{ ++ struct rb750_led_drvdata *drvdata; ++ int i; ++ ++ drvdata = platform_get_drvdata(pdev); ++ for (i = 0; i < drvdata->num_leds; i++) ++ led_classdev_unregister(&drvdata->led_devs[i].cdev); ++ ++ kfree(drvdata); ++ return 0; ++} ++ ++static struct platform_driver rb750_led_driver = { ++ .probe = rb750_led_probe, ++ .remove = __devexit_p(rb750_led_remove), ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++MODULE_ALIAS("platform:leds-rb750"); ++ ++static int __init rb750_led_init(void) ++{ ++ return platform_driver_register(&rb750_led_driver); ++} ++ ++static void __exit rb750_led_exit(void) ++{ ++ platform_driver_unregister(&rb750_led_driver); ++} ++ ++module_init(rb750_led_init); ++module_exit(rb750_led_exit); ++ ++MODULE_DESCRIPTION(DRV_NAME); ++MODULE_DESCRIPTION("LED driver for the RouterBOARD 750"); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.39.orig/drivers/leds/leds-wndr3700-usb.c linux-2.6.39/drivers/leds/leds-wndr3700-usb.c +--- linux-2.6.39.orig/drivers/leds/leds-wndr3700-usb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/leds/leds-wndr3700-usb.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,75 @@ ++/* ++ * USB LED driver for the NETGEAR WNDR3700 ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++ ++#define DRIVER_NAME "wndr3700-led-usb" ++ ++static void wndr3700_usb_led_set(struct led_classdev *cdev, ++ enum led_brightness brightness) ++{ ++ if (brightness) ++ ar71xx_device_start(RESET_MODULE_GE1_PHY); ++ else ++ ar71xx_device_stop(RESET_MODULE_GE1_PHY); ++} ++ ++static enum led_brightness wndr3700_usb_led_get(struct led_classdev *cdev) ++{ ++ return ar71xx_device_stopped(RESET_MODULE_GE1_PHY) ? LED_OFF : LED_FULL; ++} ++ ++static struct led_classdev wndr3700_usb_led = { ++ .name = "wndr3700:green:usb", ++ .brightness_set = wndr3700_usb_led_set, ++ .brightness_get = wndr3700_usb_led_get, ++}; ++ ++static int __devinit wndr3700_usb_led_probe(struct platform_device *pdev) ++{ ++ return led_classdev_register(&pdev->dev, &wndr3700_usb_led); ++} ++ ++static int __devexit wndr3700_usb_led_remove(struct platform_device *pdev) ++{ ++ led_classdev_unregister(&wndr3700_usb_led); ++ return 0; ++} ++ ++static struct platform_driver wndr3700_usb_led_driver = { ++ .probe = wndr3700_usb_led_probe, ++ .remove = __devexit_p(wndr3700_usb_led_remove), ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init wndr3700_usb_led_init(void) ++{ ++ return platform_driver_register(&wndr3700_usb_led_driver); ++} ++ ++static void __exit wndr3700_usb_led_exit(void) ++{ ++ platform_driver_unregister(&wndr3700_usb_led_driver); ++} ++ ++module_init(wndr3700_usb_led_init); ++module_exit(wndr3700_usb_led_exit); ++ ++MODULE_DESCRIPTION("USB LED driver for the NETGEAR WNDR3700"); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" DRIVER_NAME); +diff -Nur linux-2.6.39.orig/drivers/mtd/chips/cfi_cmdset_0002.c linux-2.6.39/drivers/mtd/chips/cfi_cmdset_0002.c +--- linux-2.6.39.orig/drivers/mtd/chips/cfi_cmdset_0002.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/mtd/chips/cfi_cmdset_0002.c 2011-08-24 18:17:24.000000000 +0200 +@@ -39,7 +39,7 @@ + #include + + #define AMD_BOOTLOC_BUG +-#define FORCE_WORD_WRITE 0 ++#define FORCE_WORD_WRITE 1 + + #define MAX_WORD_RETRIES 3 + +@@ -50,7 +50,9 @@ + + static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); + static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); ++#if !FORCE_WORD_WRITE + static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); ++#endif + static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); + static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); + static void cfi_amdstd_sync (struct mtd_info *); +@@ -186,6 +188,7 @@ + } + #endif + ++#if !FORCE_WORD_WRITE + static void fixup_use_write_buffers(struct mtd_info *mtd) + { + struct map_info *map = mtd->priv; +@@ -195,6 +198,7 @@ + mtd->write = cfi_amdstd_write_buffers; + } + } ++#endif /* !FORCE_WORD_WRITE */ + + /* Atmel chips don't use the same PRI format as AMD chips */ + static void fixup_convert_atmel_pri(struct mtd_info *mtd) +@@ -1377,6 +1381,7 @@ + /* + * FIXME: interleaved mode not tested, and probably not supported! + */ ++#if !FORCE_WORD_WRITE + static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, + unsigned long adr, const u_char *buf, + int len) +@@ -1487,7 +1492,6 @@ + return ret; + } + +- + static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf) + { +@@ -1566,6 +1570,7 @@ + + return 0; + } ++#endif /* !FORCE_WORD_WRITE */ + + + /* +diff -Nur linux-2.6.39.orig/drivers/mtd/maps/Kconfig linux-2.6.39/drivers/mtd/maps/Kconfig +--- linux-2.6.39.orig/drivers/mtd/maps/Kconfig 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/mtd/maps/Kconfig 2011-08-24 18:17:24.000000000 +0200 +@@ -260,6 +260,13 @@ + Support for parsing CFE image tag and creating MTD partitions on + Broadcom BCM63xx boards. + ++config MTD_AR91XX_FLASH ++ tristate "Atheros AR91xx parallel flash support" ++ depends on ATHEROS_AR71XX ++ select MTD_COMPLEX_MAPPINGS ++ help ++ Parallel flash driver for the Atheros AR91xx based boards. ++ + config MTD_DILNETPC + tristate "CFI Flash device mapped on DIL/Net PC" + depends on X86 && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN +diff -Nur linux-2.6.39.orig/drivers/mtd/maps/Makefile linux-2.6.39/drivers/mtd/maps/Makefile +--- linux-2.6.39.orig/drivers/mtd/maps/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/mtd/maps/Makefile 2011-08-24 18:17:24.000000000 +0200 +@@ -40,6 +40,7 @@ + obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.o + obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o + obj-$(CONFIG_MTD_PCI) += pci.o ++obj-$(CONFIG_MTD_AR91XX_FLASH) += ar91xx_flash.o + obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o + obj-$(CONFIG_MTD_EDB7312) += edb7312.o + obj-$(CONFIG_MTD_IMPA7) += impa7.o +diff -Nur linux-2.6.39.orig/drivers/mtd/maps/ar91xx_flash.c linux-2.6.39/drivers/mtd/maps/ar91xx_flash.c +--- linux-2.6.39.orig/drivers/mtd/maps/ar91xx_flash.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/mtd/maps/ar91xx_flash.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,310 @@ ++/* ++ * Parallel flash driver for the Atheros AR91xx SoC ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define DRV_NAME "ar91xx-flash" ++ ++struct ar91xx_flash_info { ++ struct mtd_info *mtd; ++ struct map_info map; ++#ifdef CONFIG_MTD_PARTITIONS ++ int nr_parts; ++ struct mtd_partition *parts; ++#endif ++}; ++ ++static map_word ar91xx_flash_read(struct map_info *map, unsigned long ofs) ++{ ++ map_word val; ++ ++ if (map_bankwidth_is_1(map)) ++ val.x[0] = __raw_readb(map->virt + (ofs ^ 3)); ++ else if (map_bankwidth_is_2(map)) ++ val.x[0] = __raw_readw(map->virt + (ofs ^ 2)); ++ else ++ val = map_word_ff(map); ++ ++ return val; ++} ++ ++static void ar91xx_flash_write(struct map_info *map, map_word d, ++ unsigned long ofs) ++{ ++ if (map_bankwidth_is_1(map)) ++ __raw_writeb(d.x[0], map->virt + (ofs ^ 3)); ++ else if (map_bankwidth_is_2(map)) ++ __raw_writew(d.x[0], map->virt + (ofs ^ 2)); ++ ++ mb(); ++} ++ ++static map_word ar91xx_flash_read_lock(struct map_info *map, unsigned long ofs) ++{ ++ map_word ret; ++ ++ ar71xx_flash_acquire(); ++ ret = ar91xx_flash_read(map, ofs); ++ ar71xx_flash_release(); ++ ++ return ret; ++} ++ ++static void ar91xx_flash_write_lock(struct map_info *map, map_word d, ++ unsigned long ofs) ++{ ++ ar71xx_flash_acquire(); ++ ar91xx_flash_write(map, d, ofs); ++ ar71xx_flash_release(); ++} ++ ++static void ar91xx_flash_copy_from_lock(struct map_info *map, void *to, ++ unsigned long from, ssize_t len) ++{ ++ ar71xx_flash_acquire(); ++ inline_map_copy_from(map, to, from, len); ++ ar71xx_flash_release(); ++} ++ ++static void ar91xx_flash_copy_to_lock(struct map_info *map, unsigned long to, ++ const void *from, ssize_t len) ++{ ++ ar71xx_flash_acquire(); ++ inline_map_copy_to(map, to, from, len); ++ ar71xx_flash_release(); ++} ++ ++static int ar91xx_flash_remove(struct platform_device *pdev) ++{ ++ struct ar91xx_flash_platform_data *pdata; ++ struct ar91xx_flash_info *info; ++ ++ info = platform_get_drvdata(pdev); ++ if (info == NULL) ++ return 0; ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ if (info->mtd == NULL) ++ return 0; ++ ++ pdata = pdev->dev.platform_data; ++#ifdef CONFIG_MTD_PARTITIONS ++ if (info->nr_parts) { ++ del_mtd_partitions(info->mtd); ++ kfree(info->parts); ++ } else if (pdata->nr_parts) { ++ del_mtd_partitions(info->mtd); ++ } else { ++ del_mtd_device(info->mtd); ++ } ++#else ++ del_mtd_device(info->mtd); ++#endif ++ map_destroy(info->mtd); ++ ++ return 0; ++} ++ ++static const char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL }; ++#ifdef CONFIG_MTD_PARTITIONS ++static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL }; ++#endif ++ ++static int ar91xx_flash_probe(struct platform_device *pdev) ++{ ++ struct ar91xx_flash_platform_data *pdata; ++ struct ar91xx_flash_info *info; ++ struct resource *res; ++ struct resource *region; ++ const char **probe_type; ++ int err = 0; ++ ++ pdata = pdev->dev.platform_data; ++ if (pdata == NULL) ++ return -EINVAL; ++ ++ info = devm_kzalloc(&pdev->dev, sizeof(struct ar91xx_flash_info), ++ GFP_KERNEL); ++ if (info == NULL) { ++ err = -ENOMEM; ++ goto err_out; ++ } ++ ++ platform_set_drvdata(pdev, info); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ err = -ENOENT; ++ goto err_out; ++ } ++ ++ dev_info(&pdev->dev, "%.8llx at %.8llx\n", ++ (unsigned long long)(res->end - res->start + 1), ++ (unsigned long long)res->start); ++ ++ region = devm_request_mem_region(&pdev->dev, ++ res->start, res->end - res->start + 1, ++ dev_name(&pdev->dev)); ++ if (region == NULL) { ++ dev_err(&pdev->dev, "could not reserve memory region\n"); ++ err = -ENOMEM; ++ goto err_out; ++ } ++ ++ info->map.name = dev_name(&pdev->dev); ++ info->map.phys = res->start; ++ info->map.size = res->end - res->start + 1; ++ info->map.bankwidth = pdata->width; ++ ++ info->map.virt = devm_ioremap(&pdev->dev, info->map.phys, ++ info->map.size); ++ if (info->map.virt == NULL) { ++ dev_err(&pdev->dev, "failed to ioremap flash region\n"); ++ err = -EIO; ++ goto err_out; ++ } ++ ++ simple_map_init(&info->map); ++ if (pdata->is_shared) { ++ info->map.read = ar91xx_flash_read_lock; ++ info->map.write = ar91xx_flash_write_lock; ++ info->map.copy_from = ar91xx_flash_copy_from_lock; ++ info->map.copy_to = ar91xx_flash_copy_to_lock; ++ } else { ++ info->map.read = ar91xx_flash_read; ++ info->map.write = ar91xx_flash_write; ++ } ++ ++ probe_type = rom_probe_types; ++ for (; info->mtd == NULL && *probe_type != NULL; probe_type++) ++ info->mtd = do_map_probe(*probe_type, &info->map); ++ ++ if (info->mtd == NULL) { ++ dev_err(&pdev->dev, "map_probe failed\n"); ++ err = -ENXIO; ++ goto err_out; ++ } ++ ++ info->mtd->owner = THIS_MODULE; ++ ++#ifdef CONFIG_MTD_PARTITIONS ++ if (pdata->nr_parts) { ++ dev_info(&pdev->dev, "using static partition mapping\n"); ++ add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts); ++ return 0; ++ } ++ ++ err = parse_mtd_partitions(info->mtd, part_probe_types, ++ &info->parts, 0); ++ if (err > 0) { ++ add_mtd_partitions(info->mtd, info->parts, err); ++ return 0; ++ } ++#endif ++ ++ add_mtd_device(info->mtd); ++ return 0; ++ ++err_out: ++ ar91xx_flash_remove(pdev); ++ return err; ++} ++ ++#ifdef CONFIG_PM ++static int ar91xx_flash_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct ar91xx_flash_info *info = platform_get_drvdata(dev); ++ int ret = 0; ++ ++ if (info->mtd->suspend) ++ ret = info->mtd->suspend(info->mtd); ++ ++ if (ret) ++ goto fail; ++ ++ return 0; ++ ++fail: ++ if (info->mtd->suspend) { ++ BUG_ON(!info->mtd->resume); ++ info->mtd->resume(info->mtd); ++ } ++ ++ return ret; ++} ++ ++static int ar91xx_flash_resume(struct platform_device *pdev) ++{ ++ struct ar91xx_flash_info *info = platform_get_drvdata(pdev); ++ ++ if (info->mtd->resume) ++ info->mtd->resume(info->mtd); ++ ++ return 0; ++} ++ ++static void ar91xx_flash_shutdown(struct platform_device *pdev) ++{ ++ struct ar91xx_flash_info *info = platform_get_drvdata(pdev); ++ ++ if (info->mtd->suspend && info->mtd->resume) ++ if (info->mtd->suspend(info->mtd) == 0) ++ info->mtd->resume(info->mtd); ++} ++#else ++#define ar91xx_flash_suspend NULL ++#define ar91xx_flash_resume NULL ++#define ar91xx_flash_shutdown NULL ++#endif ++ ++static struct platform_driver ar91xx_flash_driver = { ++ .probe = ar91xx_flash_probe, ++ .remove = ar91xx_flash_remove, ++ .suspend = ar91xx_flash_suspend, ++ .resume = ar91xx_flash_resume, ++ .shutdown = ar91xx_flash_shutdown, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init ar91xx_flash_init(void) ++{ ++ return platform_driver_register(&ar91xx_flash_driver); ++} ++ ++static void __exit ar91xx_flash_exit(void) ++{ ++ platform_driver_unregister(&ar91xx_flash_driver); ++} ++ ++module_init(ar91xx_flash_init); ++module_exit(ar91xx_flash_exit); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_DESCRIPTION("Parallel flash driver for the Atheros AR91xx SoC"); ++MODULE_ALIAS("platform:" DRV_NAME); +diff -Nur linux-2.6.39.orig/drivers/mtd/nand/Kconfig linux-2.6.39/drivers/mtd/nand/Kconfig +--- linux-2.6.39.orig/drivers/mtd/nand/Kconfig 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/mtd/nand/Kconfig 2011-08-24 18:17:24.000000000 +0200 +@@ -531,4 +531,9 @@ + Enables support for NAND Flash chips on the ST Microelectronics + Flexible Static Memory Controller (FSMC) + ++config MTD_NAND_RB4XX ++ tristate "NAND flash driver for RouterBoard 4xx series" ++ depends on MTD_NAND && AR71XX_MACH_RB4XX ++ select SPI_AR71XX ++ + endif # MTD_NAND +diff -Nur linux-2.6.39.orig/drivers/mtd/nand/Makefile linux-2.6.39/drivers/mtd/nand/Makefile +--- linux-2.6.39.orig/drivers/mtd/nand/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/mtd/nand/Makefile 2011-08-24 18:17:24.000000000 +0200 +@@ -34,6 +34,7 @@ + obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o + obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o + obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o ++obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o + obj-$(CONFIG_MTD_ALAUDA) += alauda.o + obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o + obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o +diff -Nur linux-2.6.39.orig/drivers/mtd/nand/rb4xx_nand.c linux-2.6.39/drivers/mtd/nand/rb4xx_nand.c +--- linux-2.6.39.orig/drivers/mtd/nand/rb4xx_nand.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/mtd/nand/rb4xx_nand.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,311 @@ ++/* ++ * NAND flash driver for the MikroTik RouterBoard 4xx series ++ * ++ * Copyright (C) 2008-2011 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This file was based on the driver for Linux 2.6.22 published by ++ * MikroTik for their RouterBoard 4xx series devices. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define DRV_NAME "rb4xx-nand" ++#define DRV_VERSION "0.2.0" ++#define DRV_DESC "NAND flash driver for RouterBoard 4xx series" ++ ++#define RB4XX_NAND_GPIO_READY 5 ++#define RB4XX_NAND_GPIO_ALE 37 ++#define RB4XX_NAND_GPIO_CLE 38 ++#define RB4XX_NAND_GPIO_NCE 39 ++ ++struct rb4xx_nand_info { ++ struct nand_chip chip; ++ struct mtd_info mtd; ++}; ++ ++/* ++ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader ++ * will not be able to find the kernel that we load. ++ */ ++static struct nand_ecclayout rb4xx_nand_ecclayout = { ++ .eccbytes = 6, ++ .eccpos = { 8, 9, 10, 13, 14, 15 }, ++ .oobavail = 9, ++ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } ++}; ++ ++static struct mtd_partition rb4xx_nand_partitions[] = { ++ { ++ .name = "booter", ++ .offset = 0, ++ .size = (256 * 1024), ++ .mask_flags = MTD_WRITEABLE, ++ }, ++ { ++ .name = "kernel", ++ .offset = (256 * 1024), ++ .size = (6 * 1024 * 1024) - (256 * 1024), ++ }, ++ { ++ .name = "rootfs", ++ .offset = MTDPART_OFS_NXTBLK, ++ .size = MTDPART_SIZ_FULL, ++ }, ++}; ++ ++static int rb4xx_nand_dev_ready(struct mtd_info *mtd) ++{ ++ return gpio_get_value_cansleep(RB4XX_NAND_GPIO_READY); ++} ++ ++static void rb4xx_nand_write_cmd(unsigned char cmd) ++{ ++ unsigned char data = cmd; ++ int err; ++ ++ err = rb4xx_cpld_write(&data, 1); ++ if (err) ++ pr_err("rb4xx_nand: write cmd failed, err=%d\n", err); ++} ++ ++static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, ++ unsigned int ctrl) ++{ ++ if (ctrl & NAND_CTRL_CHANGE) { ++ gpio_set_value_cansleep(RB4XX_NAND_GPIO_CLE, ++ (ctrl & NAND_CLE) ? 1 : 0); ++ gpio_set_value_cansleep(RB4XX_NAND_GPIO_ALE, ++ (ctrl & NAND_ALE) ? 1 : 0); ++ gpio_set_value_cansleep(RB4XX_NAND_GPIO_NCE, ++ (ctrl & NAND_NCE) ? 0 : 1); ++ } ++ ++ if (cmd != NAND_CMD_NONE) ++ rb4xx_nand_write_cmd(cmd); ++} ++ ++static unsigned char rb4xx_nand_read_byte(struct mtd_info *mtd) ++{ ++ unsigned char data = 0; ++ int err; ++ ++ err = rb4xx_cpld_read(&data, NULL, 1); ++ if (err) { ++ pr_err("rb4xx_nand: read data failed, err=%d\n", err); ++ data = 0xff; ++ } ++ ++ return data; ++} ++ ++static void rb4xx_nand_write_buf(struct mtd_info *mtd, const unsigned char *buf, ++ int len) ++{ ++ int err; ++ ++ err = rb4xx_cpld_write(buf, len); ++ if (err) ++ pr_err("rb4xx_nand: write buf failed, err=%d\n", err); ++} ++ ++static void rb4xx_nand_read_buf(struct mtd_info *mtd, unsigned char *buf, ++ int len) ++{ ++ int err; ++ ++ err = rb4xx_cpld_read(buf, NULL, len); ++ if (err) ++ pr_err("rb4xx_nand: read buf failed, err=%d\n", err); ++} ++ ++static int __init rb4xx_nand_probe(struct platform_device *pdev) ++{ ++ struct rb4xx_nand_info *info; ++ int ret; ++ ++ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); ++ ++ ret = gpio_request(RB4XX_NAND_GPIO_READY, "NAND RDY"); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to request gpio %d\n", ++ RB4XX_NAND_GPIO_READY); ++ goto err; ++ } ++ ++ ret = gpio_direction_input(RB4XX_NAND_GPIO_READY); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to set input mode on gpio %d\n", ++ RB4XX_NAND_GPIO_READY); ++ goto err_free_gpio_ready; ++ } ++ ++ ret = gpio_request(RB4XX_NAND_GPIO_ALE, "NAND ALE"); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to request gpio %d\n", ++ RB4XX_NAND_GPIO_ALE); ++ goto err_free_gpio_ready; ++ } ++ ++ ret = gpio_direction_output(RB4XX_NAND_GPIO_ALE, 0); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", ++ RB4XX_NAND_GPIO_ALE); ++ goto err_free_gpio_ale; ++ } ++ ++ ret = gpio_request(RB4XX_NAND_GPIO_CLE, "NAND CLE"); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to request gpio %d\n", ++ RB4XX_NAND_GPIO_CLE); ++ goto err_free_gpio_ale; ++ } ++ ++ ret = gpio_direction_output(RB4XX_NAND_GPIO_CLE, 0); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", ++ RB4XX_NAND_GPIO_CLE); ++ goto err_free_gpio_cle; ++ } ++ ++ ret = gpio_request(RB4XX_NAND_GPIO_NCE, "NAND NCE"); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to request gpio %d\n", ++ RB4XX_NAND_GPIO_NCE); ++ goto err_free_gpio_cle; ++ } ++ ++ ret = gpio_direction_output(RB4XX_NAND_GPIO_NCE, 1); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", ++ RB4XX_NAND_GPIO_ALE); ++ goto err_free_gpio_nce; ++ } ++ ++ info = kzalloc(sizeof(*info), GFP_KERNEL); ++ if (!info) { ++ dev_err(&pdev->dev, "rb4xx-nand: no memory for private data\n"); ++ ret = -ENOMEM; ++ goto err_free_gpio_nce; ++ } ++ ++ info->chip.priv = &info; ++ info->mtd.priv = &info->chip; ++ info->mtd.owner = THIS_MODULE; ++ ++ info->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl; ++ info->chip.dev_ready = rb4xx_nand_dev_ready; ++ info->chip.read_byte = rb4xx_nand_read_byte; ++ info->chip.write_buf = rb4xx_nand_write_buf; ++ info->chip.read_buf = rb4xx_nand_read_buf; ++#if 0 ++ info->chip.verify_buf = rb4xx_nand_verify_buf; ++#endif ++ ++ info->chip.chip_delay = 25; ++ info->chip.ecc.mode = NAND_ECC_SOFT; ++ info->chip.options |= NAND_NO_AUTOINCR; ++ ++ platform_set_drvdata(pdev, info); ++ ++ ret = nand_scan_ident(&info->mtd, 1, NULL); ++ if (ret) { ++ ret = -ENXIO; ++ goto err_free_info; ++ } ++ ++ if (info->mtd.writesize == 512) ++ info->chip.ecc.layout = &rb4xx_nand_ecclayout; ++ ++ ret = nand_scan_tail(&info->mtd); ++ if (ret) { ++ return -ENXIO; ++ goto err_set_drvdata; ++ } ++ ++#ifdef CONFIG_MTD_PARTITIONS ++ ret = add_mtd_partitions(&info->mtd, rb4xx_nand_partitions, ++ ARRAY_SIZE(rb4xx_nand_partitions)); ++#else ++ ret = add_mtd_device(&info->mtd); ++#endif ++ if (ret) ++ goto err_release_nand; ++ ++ return 0; ++ ++err_release_nand: ++ nand_release(&info->mtd); ++err_set_drvdata: ++ platform_set_drvdata(pdev, NULL); ++err_free_info: ++ kfree(info); ++err_free_gpio_nce: ++ gpio_free(RB4XX_NAND_GPIO_NCE); ++err_free_gpio_cle: ++ gpio_free(RB4XX_NAND_GPIO_CLE); ++err_free_gpio_ale: ++ gpio_free(RB4XX_NAND_GPIO_ALE); ++err_free_gpio_ready: ++ gpio_free(RB4XX_NAND_GPIO_READY); ++err: ++ return ret; ++} ++ ++static int __devexit rb4xx_nand_remove(struct platform_device *pdev) ++{ ++ struct rb4xx_nand_info *info = platform_get_drvdata(pdev); ++ ++ nand_release(&info->mtd); ++ platform_set_drvdata(pdev, NULL); ++ kfree(info); ++ gpio_free(RB4XX_NAND_GPIO_NCE); ++ gpio_free(RB4XX_NAND_GPIO_CLE); ++ gpio_free(RB4XX_NAND_GPIO_ALE); ++ gpio_free(RB4XX_NAND_GPIO_READY); ++ ++ return 0; ++} ++ ++static struct platform_driver rb4xx_nand_driver = { ++ .probe = rb4xx_nand_probe, ++ .remove = __devexit_p(rb4xx_nand_remove), ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init rb4xx_nand_init(void) ++{ ++ return platform_driver_register(&rb4xx_nand_driver); ++} ++ ++static void __exit rb4xx_nand_exit(void) ++{ ++ platform_driver_unregister(&rb4xx_nand_driver); ++} ++ ++module_init(rb4xx_nand_init); ++module_exit(rb4xx_nand_exit); ++ ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_AUTHOR("Imre Kaloz "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.39.orig/drivers/mtd/nand/rb750_nand.c linux-2.6.39/drivers/mtd/nand/rb750_nand.c +--- linux-2.6.39.orig/drivers/mtd/nand/rb750_nand.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/mtd/nand/rb750_nand.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,361 @@ ++/* ++ * NAND flash driver for the MikroTik RouterBOARD 750 ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define DRV_NAME "rb750-nand" ++#define DRV_VERSION "0.1.0" ++#define DRV_DESC "NAND flash driver for the RouterBOARD 750" ++ ++#define RB750_NAND_IO0 BIT(RB750_GPIO_NAND_IO0) ++#define RB750_NAND_ALE BIT(RB750_GPIO_NAND_ALE) ++#define RB750_NAND_CLE BIT(RB750_GPIO_NAND_CLE) ++#define RB750_NAND_NRE BIT(RB750_GPIO_NAND_NRE) ++#define RB750_NAND_NWE BIT(RB750_GPIO_NAND_NWE) ++#define RB750_NAND_RDY BIT(RB750_GPIO_NAND_RDY) ++#define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE) ++ ++#define RB750_NAND_DATA_SHIFT 1 ++#define RB750_NAND_DATA_BITS (0xff << RB750_NAND_DATA_SHIFT) ++#define RB750_NAND_INPUT_BITS (RB750_NAND_DATA_BITS | RB750_NAND_RDY) ++#define RB750_NAND_OUTPUT_BITS (RB750_NAND_ALE | RB750_NAND_CLE | \ ++ RB750_NAND_NRE | RB750_NAND_NWE | \ ++ RB750_NAND_NCE) ++ ++struct rb750_nand_info { ++ struct nand_chip chip; ++ struct mtd_info mtd; ++}; ++ ++/* ++ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader ++ * will not be able to find the kernel that we load. ++ */ ++static struct nand_ecclayout rb750_nand_ecclayout = { ++ .eccbytes = 6, ++ .eccpos = { 8, 9, 10, 13, 14, 15 }, ++ .oobavail = 9, ++ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } ++}; ++ ++static struct mtd_partition rb750_nand_partitions[] = { ++ { ++ .name = "booter", ++ .offset = 0, ++ .size = (256 * 1024), ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = (256 * 1024), ++ .size = (4 * 1024 * 1024) - (256 * 1024), ++ }, { ++ .name = "rootfs", ++ .offset = MTDPART_OFS_NXTBLK, ++ .size = MTDPART_SIZ_FULL, ++ }, ++}; ++ ++static void rb750_nand_write(const u8 *buf, unsigned len) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ u32 out; ++ unsigned i; ++ ++ /* set data lines to output mode */ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_DATA_BITS, ++ base + GPIO_REG_OE); ++ ++ out = __raw_readl(base + GPIO_REG_OUT); ++ out &= ~(RB750_NAND_DATA_BITS | RB750_NAND_NWE); ++ for (i = 0; i != len; i++) { ++ u32 data; ++ ++ data = buf[i]; ++ data <<= RB750_NAND_DATA_SHIFT; ++ data |= out; ++ __raw_writel(data, base + GPIO_REG_OUT); ++ ++ __raw_writel(data | RB750_NAND_NWE, base + GPIO_REG_OUT); ++ /* flush write */ ++ __raw_readl(base + GPIO_REG_OUT); ++ } ++ ++ /* set data lines to input mode */ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~RB750_NAND_DATA_BITS, ++ base + GPIO_REG_OE); ++ /* flush write */ ++ __raw_readl(base + GPIO_REG_OE); ++} ++ ++static int rb750_nand_read_verify(u8 *read_buf, unsigned len, ++ const u8 *verify_buf) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned i; ++ ++ for (i = 0; i < len; i++) { ++ u8 data; ++ ++ /* activate RE line */ ++ __raw_writel(RB750_NAND_NRE, base + GPIO_REG_CLEAR); ++ /* flush write */ ++ __raw_readl(base + GPIO_REG_CLEAR); ++ ++ /* read input lines */ ++ data = __raw_readl(base + GPIO_REG_IN) >> RB750_NAND_DATA_SHIFT; ++ ++ /* deactivate RE line */ ++ __raw_writel(RB750_NAND_NRE, base + GPIO_REG_SET); ++ ++ if (read_buf) ++ read_buf[i] = data; ++ else if (verify_buf && verify_buf[i] != data) ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++static void rb750_nand_select_chip(struct mtd_info *mtd, int chip) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ u32 func; ++ ++ func = __raw_readl(base + GPIO_REG_FUNC); ++ if (chip >= 0) { ++ /* disable latch */ ++ rb750_latch_change(RB750_LVC573_LE, 0); ++ ++ /* disable alternate functions */ ++ ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, ++ AR724X_GPIO_FUNC_SPI_EN); ++ ++ /* set input mode for data lines */ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ++ ~RB750_NAND_INPUT_BITS, ++ base + GPIO_REG_OE); ++ ++ /* deactivate RE and WE lines */ ++ __raw_writel(RB750_NAND_NRE | RB750_NAND_NWE, ++ base + GPIO_REG_SET); ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_SET); ++ ++ /* activate CE line */ ++ __raw_writel(RB750_NAND_NCE, base + GPIO_REG_CLEAR); ++ } else { ++ /* deactivate CE line */ ++ __raw_writel(RB750_NAND_NCE, base + GPIO_REG_SET); ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_SET); ++ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) | ++ RB750_NAND_IO0 | RB750_NAND_RDY, ++ base + GPIO_REG_OE); ++ ++ /* restore alternate functions */ ++ ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN, ++ AR724X_GPIO_FUNC_JTAG_DISABLE); ++ ++ /* enable latch */ ++ rb750_latch_change(0, RB750_LVC573_LE); ++ } ++} ++ ++static int rb750_nand_dev_ready(struct mtd_info *mtd) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ ++ return !!(__raw_readl(base + GPIO_REG_IN) & RB750_NAND_RDY); ++} ++ ++static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, ++ unsigned int ctrl) ++{ ++ if (ctrl & NAND_CTRL_CHANGE) { ++ void __iomem *base = ar71xx_gpio_base; ++ u32 t; ++ ++ t = __raw_readl(base + GPIO_REG_OUT); ++ ++ t &= ~(RB750_NAND_CLE | RB750_NAND_ALE); ++ t |= (ctrl & NAND_CLE) ? RB750_NAND_CLE : 0; ++ t |= (ctrl & NAND_ALE) ? RB750_NAND_ALE : 0; ++ ++ __raw_writel(t, base + GPIO_REG_OUT); ++ /* flush write */ ++ __raw_readl(base + GPIO_REG_OUT); ++ } ++ ++ if (cmd != NAND_CMD_NONE) { ++ u8 t = cmd; ++ rb750_nand_write(&t, 1); ++ } ++} ++ ++static u8 rb750_nand_read_byte(struct mtd_info *mtd) ++{ ++ u8 data = 0; ++ rb750_nand_read_verify(&data, 1, NULL); ++ return data; ++} ++ ++static void rb750_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) ++{ ++ rb750_nand_read_verify(buf, len, NULL); ++} ++ ++static void rb750_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) ++{ ++ rb750_nand_write(buf, len); ++} ++ ++static int rb750_nand_verify_buf(struct mtd_info *mtd, const u8 *buf, int len) ++{ ++ return rb750_nand_read_verify(NULL, len, buf); ++} ++ ++static void __init rb750_nand_gpio_init(void) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ u32 out; ++ ++ out = __raw_readl(base + GPIO_REG_OUT); ++ ++ /* setup output levels */ ++ __raw_writel(RB750_NAND_NCE | RB750_NAND_NRE | RB750_NAND_NWE, ++ base + GPIO_REG_SET); ++ ++ __raw_writel(RB750_NAND_ALE | RB750_NAND_CLE, ++ base + GPIO_REG_CLEAR); ++ ++ /* setup input lines */ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(RB750_NAND_INPUT_BITS), ++ base + GPIO_REG_OE); ++ ++ /* setup output lines */ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_OUTPUT_BITS, ++ base + GPIO_REG_OE); ++ ++ rb750_latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0); ++} ++ ++static int __init rb750_nand_probe(struct platform_device *pdev) ++{ ++ struct rb750_nand_info *info; ++ int ret; ++ ++ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); ++ ++ rb750_nand_gpio_init(); ++ ++ info = kzalloc(sizeof(*info), GFP_KERNEL); ++ if (!info) ++ return -ENOMEM; ++ ++ info->chip.priv = &info; ++ info->mtd.priv = &info->chip; ++ info->mtd.owner = THIS_MODULE; ++ ++ info->chip.select_chip = rb750_nand_select_chip; ++ info->chip.cmd_ctrl = rb750_nand_cmd_ctrl; ++ info->chip.dev_ready = rb750_nand_dev_ready; ++ info->chip.read_byte = rb750_nand_read_byte; ++ info->chip.write_buf = rb750_nand_write_buf; ++ info->chip.read_buf = rb750_nand_read_buf; ++ info->chip.verify_buf = rb750_nand_verify_buf; ++ ++ info->chip.chip_delay = 25; ++ info->chip.ecc.mode = NAND_ECC_SOFT; ++ info->chip.options |= NAND_NO_AUTOINCR; ++ ++ platform_set_drvdata(pdev, info); ++ ++ ret = nand_scan_ident(&info->mtd, 1); ++ if (ret) { ++ ret = -ENXIO; ++ goto err_free_info; ++ } ++ ++ if (info->mtd.writesize == 512) ++ info->chip.ecc.layout = &rb750_nand_ecclayout; ++ ++ ret = nand_scan_tail(&info->mtd); ++ if (ret) { ++ return -ENXIO; ++ goto err_set_drvdata; ++ } ++ ++#ifdef CONFIG_MTD_PARTITIONS ++ ret = add_mtd_partitions(&info->mtd, rb750_nand_partitions, ++ ARRAY_SIZE(rb750_nand_partitions)); ++#else ++ ret = add_mtd_device(&info->mtd); ++#endif ++ if (ret) ++ goto err_release_nand; ++ ++ return 0; ++ ++err_release_nand: ++ nand_release(&info->mtd); ++err_set_drvdata: ++ platform_set_drvdata(pdev, NULL); ++err_free_info: ++ kfree(info); ++ return ret; ++} ++ ++static int __devexit rb750_nand_remove(struct platform_device *pdev) ++{ ++ struct rb750_nand_info *info = platform_get_drvdata(pdev); ++ ++ nand_release(&info->mtd); ++ platform_set_drvdata(pdev, NULL); ++ kfree(info); ++ ++ return 0; ++} ++ ++static struct platform_driver rb750_nand_driver = { ++ .probe = rb750_nand_probe, ++ .remove = __devexit_p(rb750_nand_remove), ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init rb750_nand_init(void) ++{ ++ return platform_driver_register(&rb750_nand_driver); ++} ++ ++static void __exit rb750_nand_exit(void) ++{ ++ platform_driver_unregister(&rb750_nand_driver); ++} ++ ++module_init(rb750_nand_init); ++module_exit(rb750_nand_exit); ++ ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.39.orig/drivers/mtd/wrt160nl_part.c linux-2.6.39/drivers/mtd/wrt160nl_part.c +--- linux-2.6.39.orig/drivers/mtd/wrt160nl_part.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/mtd/wrt160nl_part.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,190 @@ ++/* ++ * Copyright (C) 2009 Christian Daniel ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ * ++ * TRX flash partition table. ++ * Based on ar7 map by Felix Fietkau ++ * ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++struct cybertan_header { ++ char magic[4]; ++ u8 res1[4]; ++ char fw_date[3]; ++ char fw_ver[3]; ++ char id[4]; ++ char hw_ver; ++ char unused; ++ u8 flags[2]; ++ u8 res2[10]; ++}; ++ ++#define TRX_PARTS 6 ++#define TRX_MAGIC 0x30524448 ++#define TRX_MAX_OFFSET 3 ++ ++struct trx_header { ++ uint32_t magic; /* "HDR0" */ ++ uint32_t len; /* Length of file including header */ ++ uint32_t crc32; /* 32-bit CRC from flag_version to end of file */ ++ uint32_t flag_version; /* 0:15 flags, 16:31 version */ ++ uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */ ++}; ++ ++#define IH_MAGIC 0x27051956 /* Image Magic Number */ ++#define IH_NMLEN 32 /* Image Name Length */ ++ ++struct uimage_header { ++ uint32_t ih_magic; /* Image Header Magic Number */ ++ uint32_t ih_hcrc; /* Image Header CRC Checksum */ ++ uint32_t ih_time; /* Image Creation Timestamp */ ++ uint32_t ih_size; /* Image Data Size */ ++ uint32_t ih_load; /* Data» Load Address */ ++ uint32_t ih_ep; /* Entry Point Address */ ++ uint32_t ih_dcrc; /* Image Data CRC Checksum */ ++ uint8_t ih_os; /* Operating System */ ++ uint8_t ih_arch; /* CPU architecture */ ++ uint8_t ih_type; /* Image Type */ ++ uint8_t ih_comp; /* Compression Type */ ++ uint8_t ih_name[IH_NMLEN]; /* Image Name */ ++}; ++ ++struct wrt160nl_header { ++ struct cybertan_header cybertan; ++ struct trx_header trx; ++ struct uimage_header uimage; ++} __attribute__ ((packed)); ++ ++static struct mtd_partition trx_parts[TRX_PARTS]; ++ ++#define WRT160NL_UBOOT_LEN 0x40000 ++#define WRT160NL_ART_LEN 0x10000 ++#define WRT160NL_NVRAM_LEN 0x10000 ++ ++static int wrt160nl_parse_partitions(struct mtd_info *master, ++ struct mtd_partition **pparts, ++ unsigned long origin) ++{ ++ struct wrt160nl_header *header; ++ struct trx_header *theader; ++ struct uimage_header *uheader; ++ size_t retlen; ++ unsigned int kernel_len; ++ unsigned int uboot_len = max(master->erasesize, WRT160NL_UBOOT_LEN); ++ unsigned int nvram_len = max(master->erasesize, WRT160NL_NVRAM_LEN); ++ unsigned int art_len = max(master->erasesize, WRT160NL_ART_LEN); ++ int ret; ++ ++ header = vmalloc(sizeof(*header)); ++ if (!header) { ++ return -ENOMEM; ++ goto out; ++ } ++ ++ ret = master->read(master, uboot_len, sizeof(*header), ++ &retlen, (void *) header); ++ if (ret) ++ goto free_hdr; ++ ++ if (retlen != sizeof(*header)) { ++ ret = -EIO; ++ goto free_hdr; ++ } ++ ++ if (strncmp(header->cybertan.magic, "NL16", 4) != 0) { ++ printk(KERN_NOTICE "%s: no WRT160NL signature found\n", ++ master->name); ++ goto free_hdr; ++ } ++ ++ theader = &header->trx; ++ if (le32_to_cpu(theader->magic) != TRX_MAGIC) { ++ printk(KERN_NOTICE "%s: no TRX header found\n", master->name); ++ goto free_hdr; ++ } ++ ++ uheader = &header->uimage; ++ if (uheader->ih_magic != IH_MAGIC) { ++ printk(KERN_NOTICE "%s: no uImage found\n", master->name); ++ goto free_hdr; ++ } ++ ++ kernel_len = le32_to_cpu(theader->offsets[1]) + ++ sizeof(struct cybertan_header); ++ ++ trx_parts[0].name = "u-boot"; ++ trx_parts[0].offset = 0; ++ trx_parts[0].size = uboot_len; ++ trx_parts[0].mask_flags = MTD_WRITEABLE; ++ ++ trx_parts[1].name = "kernel"; ++ trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size; ++ trx_parts[1].size = kernel_len; ++ trx_parts[1].mask_flags = 0; ++ ++ trx_parts[2].name = "rootfs"; ++ trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size; ++ trx_parts[2].size = master->size - uboot_len - nvram_len - art_len - ++ trx_parts[1].size; ++ trx_parts[2].mask_flags = 0; ++ ++ trx_parts[3].name = "nvram"; ++ trx_parts[3].offset = master->size - nvram_len - art_len; ++ trx_parts[3].size = nvram_len; ++ trx_parts[3].mask_flags = MTD_WRITEABLE; ++ ++ trx_parts[4].name = "art"; ++ trx_parts[4].offset = master->size - art_len; ++ trx_parts[4].size = art_len; ++ trx_parts[4].mask_flags = MTD_WRITEABLE; ++ ++ trx_parts[5].name = "firmware"; ++ trx_parts[5].offset = uboot_len; ++ trx_parts[5].size = master->size - uboot_len - nvram_len - art_len; ++ trx_parts[5].mask_flags = 0; ++ ++ *pparts = trx_parts; ++ ret = TRX_PARTS; ++ ++free_hdr: ++ vfree(header); ++out: ++ return ret; ++} ++ ++static struct mtd_part_parser wrt160nl_parser = { ++ .owner = THIS_MODULE, ++ .parse_fn = wrt160nl_parse_partitions, ++ .name = "wrt160nl", ++}; ++ ++static int __init wrt160nl_parser_init(void) ++{ ++ return register_mtd_parser(&wrt160nl_parser); ++} ++ ++module_init(wrt160nl_parser_init); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Christian Daniel "); +diff -Nur linux-2.6.39.orig/drivers/net/Kconfig linux-2.6.39/drivers/net/Kconfig +--- linux-2.6.39.orig/drivers/net/Kconfig 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/net/Kconfig 2011-08-24 18:17:24.000000000 +0200 +@@ -2071,6 +2071,8 @@ + + The safe and default value for this is N. + ++source drivers/net/ag71xx/Kconfig ++ + config DL2K + tristate "DL2000/TC902x-based Gigabit Ethernet support" + depends on PCI +diff -Nur linux-2.6.39.orig/drivers/net/Makefile linux-2.6.39/drivers/net/Makefile +--- linux-2.6.39.orig/drivers/net/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/net/Makefile 2011-08-24 18:17:24.000000000 +0200 +@@ -112,6 +112,7 @@ + # end link order section + # + ++obj-$(CONFIG_AG71XX) += ag71xx/ + obj-$(CONFIG_SUNDANCE) += sundance.o + obj-$(CONFIG_HAMACHI) += hamachi.o + obj-$(CONFIG_NET) += Space.o loopback.o +diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/Kconfig linux-2.6.39/drivers/net/ag71xx/Kconfig +--- linux-2.6.39.orig/drivers/net/ag71xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/net/ag71xx/Kconfig 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,33 @@ ++config AG71XX ++ tristate "Atheros AR71xx built-in ethernet mac support" ++ depends on ATHEROS_AR71XX ++ select PHYLIB ++ help ++ If you wish to compile a kernel for AR71xx/91xx and enable ++ ethernet support, then you should always answer Y to this. ++ ++if AG71XX ++ ++config AG71XX_DEBUG ++ bool "Atheros AR71xx built-in ethernet driver debugging" ++ default n ++ help ++ Atheros AR71xx built-in ethernet driver debugging messages. ++ ++config AG71XX_DEBUG_FS ++ bool "Atheros AR71xx built-in ethernet driver debugfs support" ++ depends on DEBUG_FS ++ default n ++ help ++ Say Y, if you need access to various statistics provided by ++ the ag71xx driver. ++ ++config AG71XX_AR8216_SUPPORT ++ bool "special support for the Atheros AR8216 switch" ++ default n ++ default y if AR71XX_MACH_WNR2000 || AR71XX_MACH_MZK_W04NU ++ help ++ Say 'y' here if you want to enable special support for the ++ Atheros AR8216 switch found on some boards. ++ ++endif +diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/Makefile linux-2.6.39/drivers/net/ag71xx/Makefile +--- linux-2.6.39.orig/drivers/net/ag71xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/net/ag71xx/Makefile 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,15 @@ ++# ++# Makefile for the Atheros AR71xx built-in ethernet macs ++# ++ ++ag71xx-y += ag71xx_main.o ++ag71xx-y += ag71xx_ethtool.o ++ag71xx-y += ag71xx_phy.o ++ag71xx-y += ag71xx_mdio.o ++ag71xx-y += ag71xx_ar7240.o ++ ++ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o ++ag71xx-$(CONFIG_AG71XX_AR8216_SUPPORT) += ag71xx_ar8216.o ++ ++obj-$(CONFIG_AG71XX) += ag71xx.o ++ +diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx.h linux-2.6.39/drivers/net/ag71xx/ag71xx.h +--- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/net/ag71xx/ag71xx.h 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,518 @@ ++/* ++ * Atheros AR71xx built-in ethernet mac driver ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Based on Atheros' AG7100 driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __AG71XX_H ++#define __AG71XX_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#define AG71XX_DRV_NAME "ag71xx" ++#define AG71XX_DRV_VERSION "0.5.35" ++ ++#define AG71XX_NAPI_WEIGHT 64 ++#define AG71XX_OOM_REFILL (1 + HZ/10) ++ ++#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) ++#define AG71XX_INT_TX (AG71XX_INT_TX_PS) ++#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) ++ ++#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) ++#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) ++ ++#define AG71XX_TX_MTU_LEN 1540 ++#define AG71XX_RX_PKT_RESERVE 64 ++#define AG71XX_RX_PKT_SIZE \ ++ (AG71XX_RX_PKT_RESERVE + ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) ++ ++#define AG71XX_TX_RING_SIZE_DEFAULT 64 ++#define AG71XX_RX_RING_SIZE_DEFAULT 128 ++ ++#define AG71XX_TX_RING_SIZE_MAX 256 ++#define AG71XX_RX_RING_SIZE_MAX 256 ++ ++#ifdef CONFIG_AG71XX_DEBUG ++#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args) ++#else ++#define DBG(fmt, args...) do {} while (0) ++#endif ++ ++#define ag71xx_assert(_cond) \ ++do { \ ++ if (_cond) \ ++ break; \ ++ printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \ ++ BUG(); \ ++} while (0) ++ ++struct ag71xx_desc { ++ u32 data; ++ u32 ctrl; ++#define DESC_EMPTY BIT(31) ++#define DESC_MORE BIT(24) ++#define DESC_PKTLEN_M 0xfff ++ u32 next; ++ u32 pad; ++} __attribute__((aligned(4))); ++ ++struct ag71xx_buf { ++ struct sk_buff *skb; ++ struct ag71xx_desc *desc; ++ dma_addr_t dma_addr; ++ unsigned long timestamp; ++}; ++ ++struct ag71xx_ring { ++ struct ag71xx_buf *buf; ++ u8 *descs_cpu; ++ dma_addr_t descs_dma; ++ unsigned int desc_size; ++ unsigned int curr; ++ unsigned int dirty; ++ unsigned int size; ++}; ++ ++struct ag71xx_mdio { ++ struct mii_bus *mii_bus; ++ int mii_irq[PHY_MAX_ADDR]; ++ void __iomem *mdio_base; ++ struct ag71xx_mdio_platform_data *pdata; ++}; ++ ++struct ag71xx_int_stats { ++ unsigned long rx_pr; ++ unsigned long rx_be; ++ unsigned long rx_of; ++ unsigned long tx_ps; ++ unsigned long tx_be; ++ unsigned long tx_ur; ++ unsigned long total; ++}; ++ ++struct ag71xx_napi_stats { ++ unsigned long napi_calls; ++ unsigned long rx_count; ++ unsigned long rx_packets; ++ unsigned long rx_packets_max; ++ unsigned long tx_count; ++ unsigned long tx_packets; ++ unsigned long tx_packets_max; ++ ++ unsigned long rx[AG71XX_NAPI_WEIGHT + 1]; ++ unsigned long tx[AG71XX_NAPI_WEIGHT + 1]; ++}; ++ ++struct ag71xx_debug { ++ struct dentry *debugfs_dir; ++ ++ struct ag71xx_int_stats int_stats; ++ struct ag71xx_napi_stats napi_stats; ++}; ++ ++struct ag71xx { ++ void __iomem *mac_base; ++ void __iomem *mii_ctrl; ++ ++ spinlock_t lock; ++ struct platform_device *pdev; ++ struct net_device *dev; ++ struct napi_struct napi; ++ u32 msg_enable; ++ ++ struct ag71xx_desc *stop_desc; ++ dma_addr_t stop_desc_dma; ++ ++ struct ag71xx_ring rx_ring; ++ struct ag71xx_ring tx_ring; ++ ++ struct mii_bus *mii_bus; ++ struct phy_device *phy_dev; ++ void *phy_priv; ++ ++ unsigned int link; ++ unsigned int speed; ++ int duplex; ++ ++ struct work_struct restart_work; ++ struct delayed_work link_work; ++ struct timer_list oom_timer; ++ ++#ifdef CONFIG_AG71XX_DEBUG_FS ++ struct ag71xx_debug debug; ++#endif ++}; ++ ++extern struct ethtool_ops ag71xx_ethtool_ops; ++void ag71xx_link_adjust(struct ag71xx *ag); ++ ++int ag71xx_mdio_driver_init(void) __init; ++void ag71xx_mdio_driver_exit(void); ++ ++int ag71xx_phy_connect(struct ag71xx *ag); ++void ag71xx_phy_disconnect(struct ag71xx *ag); ++void ag71xx_phy_start(struct ag71xx *ag); ++void ag71xx_phy_stop(struct ag71xx *ag); ++ ++static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag) ++{ ++ return ag->pdev->dev.platform_data; ++} ++ ++static inline int ag71xx_desc_empty(struct ag71xx_desc *desc) ++{ ++ return (desc->ctrl & DESC_EMPTY) != 0; ++} ++ ++static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc) ++{ ++ return desc->ctrl & DESC_PKTLEN_M; ++} ++ ++/* Register offsets */ ++#define AG71XX_REG_MAC_CFG1 0x0000 ++#define AG71XX_REG_MAC_CFG2 0x0004 ++#define AG71XX_REG_MAC_IPG 0x0008 ++#define AG71XX_REG_MAC_HDX 0x000c ++#define AG71XX_REG_MAC_MFL 0x0010 ++#define AG71XX_REG_MII_CFG 0x0020 ++#define AG71XX_REG_MII_CMD 0x0024 ++#define AG71XX_REG_MII_ADDR 0x0028 ++#define AG71XX_REG_MII_CTRL 0x002c ++#define AG71XX_REG_MII_STATUS 0x0030 ++#define AG71XX_REG_MII_IND 0x0034 ++#define AG71XX_REG_MAC_IFCTL 0x0038 ++#define AG71XX_REG_MAC_ADDR1 0x0040 ++#define AG71XX_REG_MAC_ADDR2 0x0044 ++#define AG71XX_REG_FIFO_CFG0 0x0048 ++#define AG71XX_REG_FIFO_CFG1 0x004c ++#define AG71XX_REG_FIFO_CFG2 0x0050 ++#define AG71XX_REG_FIFO_CFG3 0x0054 ++#define AG71XX_REG_FIFO_CFG4 0x0058 ++#define AG71XX_REG_FIFO_CFG5 0x005c ++#define AG71XX_REG_FIFO_RAM0 0x0060 ++#define AG71XX_REG_FIFO_RAM1 0x0064 ++#define AG71XX_REG_FIFO_RAM2 0x0068 ++#define AG71XX_REG_FIFO_RAM3 0x006c ++#define AG71XX_REG_FIFO_RAM4 0x0070 ++#define AG71XX_REG_FIFO_RAM5 0x0074 ++#define AG71XX_REG_FIFO_RAM6 0x0078 ++#define AG71XX_REG_FIFO_RAM7 0x007c ++ ++#define AG71XX_REG_TX_CTRL 0x0180 ++#define AG71XX_REG_TX_DESC 0x0184 ++#define AG71XX_REG_TX_STATUS 0x0188 ++#define AG71XX_REG_RX_CTRL 0x018c ++#define AG71XX_REG_RX_DESC 0x0190 ++#define AG71XX_REG_RX_STATUS 0x0194 ++#define AG71XX_REG_INT_ENABLE 0x0198 ++#define AG71XX_REG_INT_STATUS 0x019c ++ ++#define AG71XX_REG_FIFO_DEPTH 0x01a8 ++#define AG71XX_REG_RX_SM 0x01b0 ++#define AG71XX_REG_TX_SM 0x01b4 ++ ++#define MAC_CFG1_TXE BIT(0) /* Tx Enable */ ++#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ ++#define MAC_CFG1_RXE BIT(2) /* Rx Enable */ ++#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ ++#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ ++#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ ++#define MAC_CFG1_LB BIT(8) /* Loopback mode */ ++#define MAC_CFG1_SR BIT(31) /* Soft Reset */ ++ ++#define MAC_CFG2_FDX BIT(0) ++#define MAC_CFG2_CRC_EN BIT(1) ++#define MAC_CFG2_PAD_CRC_EN BIT(2) ++#define MAC_CFG2_LEN_CHECK BIT(4) ++#define MAC_CFG2_HUGE_FRAME_EN BIT(5) ++#define MAC_CFG2_IF_1000 BIT(9) ++#define MAC_CFG2_IF_10_100 BIT(8) ++ ++#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ ++#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ ++#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ ++#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ ++#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ ++#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ ++ | FIFO_CFG0_TXS | FIFO_CFG0_TXF) ++ ++#define FIFO_CFG0_ENABLE_SHIFT 8 ++ ++#define FIFO_CFG4_DE BIT(0) /* Drop Event */ ++#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ ++#define FIFO_CFG4_FC BIT(2) /* False Carrier */ ++#define FIFO_CFG4_CE BIT(3) /* Code Error */ ++#define FIFO_CFG4_CR BIT(4) /* CRC error */ ++#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ ++#define FIFO_CFG4_LO BIT(6) /* Length out of range */ ++#define FIFO_CFG4_OK BIT(7) /* Packet is OK */ ++#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ ++#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ ++#define FIFO_CFG4_DR BIT(10) /* Dribble */ ++#define FIFO_CFG4_LE BIT(11) /* Long Event */ ++#define FIFO_CFG4_CF BIT(12) /* Control Frame */ ++#define FIFO_CFG4_PF BIT(13) /* Pause Frame */ ++#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ ++#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ ++#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ ++#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ ++ ++#define FIFO_CFG5_DE BIT(0) /* Drop Event */ ++#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ ++#define FIFO_CFG5_FC BIT(2) /* False Carrier */ ++#define FIFO_CFG5_CE BIT(3) /* Code Error */ ++#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ ++#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ ++#define FIFO_CFG5_OK BIT(6) /* Packet is OK */ ++#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ ++#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ ++#define FIFO_CFG5_DR BIT(9) /* Dribble */ ++#define FIFO_CFG5_CF BIT(10) /* Control Frame */ ++#define FIFO_CFG5_PF BIT(11) /* Pause Frame */ ++#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ ++#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ ++#define FIFO_CFG5_LE BIT(14) /* Long Event */ ++#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ ++#define FIFO_CFG5_16 BIT(16) /* unknown */ ++#define FIFO_CFG5_17 BIT(17) /* unknown */ ++#define FIFO_CFG5_SF BIT(18) /* Short Frame */ ++#define FIFO_CFG5_BM BIT(19) /* Byte Mode */ ++ ++#define AG71XX_INT_TX_PS BIT(0) ++#define AG71XX_INT_TX_UR BIT(1) ++#define AG71XX_INT_TX_BE BIT(3) ++#define AG71XX_INT_RX_PR BIT(4) ++#define AG71XX_INT_RX_OF BIT(6) ++#define AG71XX_INT_RX_BE BIT(7) ++ ++#define MAC_IFCTL_SPEED BIT(16) ++ ++#define MII_CFG_CLK_DIV_4 0 ++#define MII_CFG_CLK_DIV_6 2 ++#define MII_CFG_CLK_DIV_8 3 ++#define MII_CFG_CLK_DIV_10 4 ++#define MII_CFG_CLK_DIV_14 5 ++#define MII_CFG_CLK_DIV_20 6 ++#define MII_CFG_CLK_DIV_28 7 ++#define MII_CFG_RESET BIT(31) ++ ++#define MII_CMD_WRITE 0x0 ++#define MII_CMD_READ 0x1 ++#define MII_ADDR_SHIFT 8 ++#define MII_IND_BUSY BIT(0) ++#define MII_IND_INVALID BIT(2) ++ ++#define TX_CTRL_TXE BIT(0) /* Tx Enable */ ++ ++#define TX_STATUS_PS BIT(0) /* Packet Sent */ ++#define TX_STATUS_UR BIT(1) /* Tx Underrun */ ++#define TX_STATUS_BE BIT(3) /* Bus Error */ ++ ++#define RX_CTRL_RXE BIT(0) /* Rx Enable */ ++ ++#define RX_STATUS_PR BIT(0) /* Packet Received */ ++#define RX_STATUS_OF BIT(2) /* Rx Overflow */ ++#define RX_STATUS_BE BIT(3) /* Bus Error */ ++ ++#define MII_CTRL_IF_MASK 3 ++#define MII_CTRL_SPEED_SHIFT 4 ++#define MII_CTRL_SPEED_MASK 3 ++#define MII_CTRL_SPEED_10 0 ++#define MII_CTRL_SPEED_100 1 ++#define MII_CTRL_SPEED_1000 2 ++ ++static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg) ++{ ++ switch (reg) { ++ case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: ++ case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: ++ case AG71XX_REG_MII_CFG: ++ break; ++ ++ default: ++ BUG(); ++ } ++} ++ ++static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) ++{ ++ ag71xx_check_reg_offset(ag, reg); ++ ++ __raw_writel(value, ag->mac_base + reg); ++ /* flush write */ ++ (void) __raw_readl(ag->mac_base + reg); ++} ++ ++static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg) ++{ ++ ag71xx_check_reg_offset(ag, reg); ++ ++ return __raw_readl(ag->mac_base + reg); ++} ++ ++static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask) ++{ ++ void __iomem *r; ++ ++ ag71xx_check_reg_offset(ag, reg); ++ ++ r = ag->mac_base + reg; ++ __raw_writel(__raw_readl(r) | mask, r); ++ /* flush write */ ++ (void)__raw_readl(r); ++} ++ ++static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask) ++{ ++ void __iomem *r; ++ ++ ag71xx_check_reg_offset(ag, reg); ++ ++ r = ag->mac_base + reg; ++ __raw_writel(__raw_readl(r) & ~mask, r); ++ /* flush write */ ++ (void) __raw_readl(r); ++} ++ ++static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints) ++{ ++ ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); ++} ++ ++static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints) ++{ ++ ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); ++} ++ ++static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value) ++{ ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ ++ if (pdata->is_ar724x) ++ return; ++ ++ __raw_writel(value, ag->mii_ctrl); ++ ++ /* flush write */ ++ __raw_readl(ag->mii_ctrl); ++} ++ ++static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag) ++{ ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ ++ if (pdata->is_ar724x) ++ return 0xffffffff; ++ ++ return __raw_readl(ag->mii_ctrl); ++} ++ ++static inline void ag71xx_mii_ctrl_set_if(struct ag71xx *ag, ++ unsigned int mii_if) ++{ ++ u32 t; ++ ++ t = ag71xx_mii_ctrl_rr(ag); ++ t &= ~(MII_CTRL_IF_MASK); ++ t |= (mii_if & MII_CTRL_IF_MASK); ++ ag71xx_mii_ctrl_wr(ag, t); ++} ++ ++static inline void ag71xx_mii_ctrl_set_speed(struct ag71xx *ag, ++ unsigned int speed) ++{ ++ u32 t; ++ ++ t = ag71xx_mii_ctrl_rr(ag); ++ t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT); ++ t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT; ++ ag71xx_mii_ctrl_wr(ag, t); ++} ++ ++#ifdef CONFIG_AG71XX_AR8216_SUPPORT ++void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb); ++int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, ++ int pktlen); ++static inline int ag71xx_has_ar8216(struct ag71xx *ag) ++{ ++ return ag71xx_get_pdata(ag)->has_ar8216; ++} ++#else ++static inline void ag71xx_add_ar8216_header(struct ag71xx *ag, ++ struct sk_buff *skb) ++{ ++} ++ ++static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag, ++ struct sk_buff *skb, ++ int pktlen) ++{ ++ return 0; ++} ++static inline int ag71xx_has_ar8216(struct ag71xx *ag) ++{ ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_AG71XX_DEBUG_FS ++int ag71xx_debugfs_root_init(void); ++void ag71xx_debugfs_root_exit(void); ++int ag71xx_debugfs_init(struct ag71xx *ag); ++void ag71xx_debugfs_exit(struct ag71xx *ag); ++void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status); ++void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx); ++#else ++static inline int ag71xx_debugfs_root_init(void) { return 0; } ++static inline void ag71xx_debugfs_root_exit(void) {} ++static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; } ++static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {} ++static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, ++ u32 status) {} ++static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, ++ int rx, int tx) {} ++#endif /* CONFIG_AG71XX_DEBUG_FS */ ++ ++void ag71xx_ar7240_start(struct ag71xx *ag); ++void ag71xx_ar7240_stop(struct ag71xx *ag); ++int ag71xx_ar7240_init(struct ag71xx *ag); ++void ag71xx_ar7240_cleanup(struct ag71xx *ag); ++ ++int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg); ++void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val); ++ ++u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr, ++ unsigned reg_addr); ++int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr, ++ unsigned reg_addr, u16 reg_val); ++ ++#endif /* _AG71XX_H */ +diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_ar7240.c linux-2.6.39/drivers/net/ag71xx/ag71xx_ar7240.c +--- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_ar7240.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/net/ag71xx/ag71xx_ar7240.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,913 @@ ++/* ++ * Driver for the built-in ethernet switch of the Atheros AR7240 SoC ++ * Copyright (c) 2010 Gabor Juhos ++ * Copyright (c) 2010 Felix Fietkau ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ag71xx.h" ++ ++#define BITM(_count) (BIT(_count) - 1) ++#define BITS(_shift, _count) (BITM(_count) << _shift) ++ ++#define AR7240_REG_MASK_CTRL 0x00 ++#define AR7240_MASK_CTRL_REVISION_M BITM(8) ++#define AR7240_MASK_CTRL_VERSION_M BITM(8) ++#define AR7240_MASK_CTRL_VERSION_S 8 ++#define AR7240_MASK_CTRL_SOFT_RESET BIT(31) ++ ++#define AR7240_REG_MAC_ADDR0 0x20 ++#define AR7240_REG_MAC_ADDR1 0x24 ++ ++#define AR7240_REG_FLOOD_MASK 0x2c ++#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26) ++ ++#define AR7240_REG_GLOBAL_CTRL 0x30 ++#define AR7240_GLOBAL_CTRL_MTU_M BITM(12) ++ ++#define AR7240_REG_VTU 0x0040 ++#define AR7240_VTU_OP BITM(3) ++#define AR7240_VTU_OP_NOOP 0x0 ++#define AR7240_VTU_OP_FLUSH 0x1 ++#define AR7240_VTU_OP_LOAD 0x2 ++#define AR7240_VTU_OP_PURGE 0x3 ++#define AR7240_VTU_OP_REMOVE_PORT 0x4 ++#define AR7240_VTU_ACTIVE BIT(3) ++#define AR7240_VTU_FULL BIT(4) ++#define AR7240_VTU_PORT BITS(8, 4) ++#define AR7240_VTU_PORT_S 8 ++#define AR7240_VTU_VID BITS(16, 12) ++#define AR7240_VTU_VID_S 16 ++#define AR7240_VTU_PRIO BITS(28, 3) ++#define AR7240_VTU_PRIO_S 28 ++#define AR7240_VTU_PRIO_EN BIT(31) ++ ++#define AR7240_REG_VTU_DATA 0x0044 ++#define AR7240_VTUDATA_MEMBER BITS(0, 10) ++#define AR7240_VTUDATA_VALID BIT(11) ++ ++#define AR7240_REG_ATU 0x50 ++#define AR7240_ATU_FLUSH_ALL 0x1 ++ ++#define AR7240_REG_AT_CTRL 0x5c ++#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15) ++#define AR7240_AT_CTRL_AGE_EN BIT(17) ++#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18) ++#define AR7240_AT_CTRL_ARP_EN BIT(20) ++ ++#define AR7240_REG_TAG_PRIORITY 0x70 ++ ++#define AR7240_REG_SERVICE_TAG 0x74 ++#define AR7240_SERVICE_TAG_M BITM(16) ++ ++#define AR7240_REG_CPU_PORT 0x78 ++#define AR7240_MIRROR_PORT_S 4 ++#define AR7240_CPU_PORT_EN BIT(8) ++ ++#define AR7240_REG_MIB_FUNCTION0 0x80 ++#define AR7240_MIB_TIMER_M BITM(16) ++#define AR7240_MIB_AT_HALF_EN BIT(16) ++#define AR7240_MIB_BUSY BIT(17) ++#define AR7240_MIB_FUNC_S 24 ++#define AR7240_MIB_FUNC_NO_OP 0x0 ++#define AR7240_MIB_FUNC_FLUSH 0x1 ++#define AR7240_MIB_FUNC_CAPTURE 0x3 ++ ++#define AR7240_REG_MDIO_CTRL 0x98 ++#define AR7240_MDIO_CTRL_DATA_M BITM(16) ++#define AR7240_MDIO_CTRL_REG_ADDR_S 16 ++#define AR7240_MDIO_CTRL_PHY_ADDR_S 21 ++#define AR7240_MDIO_CTRL_CMD_WRITE 0 ++#define AR7240_MDIO_CTRL_CMD_READ BIT(27) ++#define AR7240_MDIO_CTRL_MASTER_EN BIT(30) ++#define AR7240_MDIO_CTRL_BUSY BIT(31) ++ ++#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) ++ ++#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00) ++#define AR7240_PORT_STATUS_SPEED_M BITM(2) ++#define AR7240_PORT_STATUS_SPEED_10 0 ++#define AR7240_PORT_STATUS_SPEED_100 1 ++#define AR7240_PORT_STATUS_SPEED_1000 2 ++#define AR7240_PORT_STATUS_TXMAC BIT(2) ++#define AR7240_PORT_STATUS_RXMAC BIT(3) ++#define AR7240_PORT_STATUS_TXFLOW BIT(4) ++#define AR7240_PORT_STATUS_RXFLOW BIT(5) ++#define AR7240_PORT_STATUS_DUPLEX BIT(6) ++#define AR7240_PORT_STATUS_LINK_UP BIT(8) ++#define AR7240_PORT_STATUS_LINK_AUTO BIT(9) ++#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10) ++ ++#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04) ++#define AR7240_PORT_CTRL_STATE_M BITM(3) ++#define AR7240_PORT_CTRL_STATE_DISABLED 0 ++#define AR7240_PORT_CTRL_STATE_BLOCK 1 ++#define AR7240_PORT_CTRL_STATE_LISTEN 2 ++#define AR7240_PORT_CTRL_STATE_LEARN 3 ++#define AR7240_PORT_CTRL_STATE_FORWARD 4 ++#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7) ++#define AR7240_PORT_CTRL_VLAN_MODE_S 8 ++#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0 ++#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1 ++#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2 ++#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3 ++#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10) ++#define AR7240_PORT_CTRL_HEADER BIT(11) ++#define AR7240_PORT_CTRL_MAC_LOOP BIT(12) ++#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13) ++#define AR7240_PORT_CTRL_LEARN BIT(14) ++#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15) ++#define AR7240_PORT_CTRL_MIRROR_TX BIT(16) ++#define AR7240_PORT_CTRL_MIRROR_RX BIT(17) ++ ++#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08) ++ ++#define AR7240_PORT_VLAN_DEFAULT_ID_S 0 ++#define AR7240_PORT_VLAN_DEST_PORTS_S 16 ++#define AR7240_PORT_VLAN_MODE_S 30 ++#define AR7240_PORT_VLAN_MODE_PORT_ONLY 0 ++#define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1 ++#define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2 ++#define AR7240_PORT_VLAN_MODE_SECURE 3 ++ ++ ++#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100) ++ ++#define AR7240_STATS_RXBROAD 0x00 ++#define AR7240_STATS_RXPAUSE 0x04 ++#define AR7240_STATS_RXMULTI 0x08 ++#define AR7240_STATS_RXFCSERR 0x0c ++#define AR7240_STATS_RXALIGNERR 0x10 ++#define AR7240_STATS_RXRUNT 0x14 ++#define AR7240_STATS_RXFRAGMENT 0x18 ++#define AR7240_STATS_RX64BYTE 0x1c ++#define AR7240_STATS_RX128BYTE 0x20 ++#define AR7240_STATS_RX256BYTE 0x24 ++#define AR7240_STATS_RX512BYTE 0x28 ++#define AR7240_STATS_RX1024BYTE 0x2c ++#define AR7240_STATS_RX1518BYTE 0x30 ++#define AR7240_STATS_RXMAXBYTE 0x34 ++#define AR7240_STATS_RXTOOLONG 0x38 ++#define AR7240_STATS_RXGOODBYTE 0x3c ++#define AR7240_STATS_RXBADBYTE 0x44 ++#define AR7240_STATS_RXOVERFLOW 0x4c ++#define AR7240_STATS_FILTERED 0x50 ++#define AR7240_STATS_TXBROAD 0x54 ++#define AR7240_STATS_TXPAUSE 0x58 ++#define AR7240_STATS_TXMULTI 0x5c ++#define AR7240_STATS_TXUNDERRUN 0x60 ++#define AR7240_STATS_TX64BYTE 0x64 ++#define AR7240_STATS_TX128BYTE 0x68 ++#define AR7240_STATS_TX256BYTE 0x6c ++#define AR7240_STATS_TX512BYTE 0x70 ++#define AR7240_STATS_TX1024BYTE 0x74 ++#define AR7240_STATS_TX1518BYTE 0x78 ++#define AR7240_STATS_TXMAXBYTE 0x7c ++#define AR7240_STATS_TXOVERSIZE 0x80 ++#define AR7240_STATS_TXBYTE 0x84 ++#define AR7240_STATS_TXCOLLISION 0x8c ++#define AR7240_STATS_TXABORTCOL 0x90 ++#define AR7240_STATS_TXMULTICOL 0x94 ++#define AR7240_STATS_TXSINGLECOL 0x98 ++#define AR7240_STATS_TXEXCDEFER 0x9c ++#define AR7240_STATS_TXDEFER 0xa0 ++#define AR7240_STATS_TXLATECOL 0xa4 ++ ++#define AR7240_PORT_CPU 0 ++#define AR7240_NUM_PORTS 6 ++#define AR7240_NUM_PHYS 5 ++ ++#define AR7240_PHY_ID1 0x004d ++#define AR7240_PHY_ID2 0xd041 ++ ++#define AR7240_PORT_MASK(_port) BIT((_port)) ++#define AR7240_PORT_MASK_ALL BITM(AR7240_NUM_PORTS) ++#define AR7240_PORT_MASK_BUT(_port) (AR7240_PORT_MASK_ALL & ~BIT((_port))) ++ ++#define AR7240_MAX_VLANS 16 ++ ++#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev) ++ ++struct ar7240sw { ++ struct mii_bus *mii_bus; ++ struct switch_dev swdev; ++ bool vlan; ++ u16 vlan_id[AR7240_MAX_VLANS]; ++ u8 vlan_table[AR7240_MAX_VLANS]; ++ u8 vlan_tagged; ++ u16 pvid[AR7240_NUM_PORTS]; ++}; ++ ++struct ar7240sw_hw_stat { ++ char string[ETH_GSTRING_LEN]; ++ int sizeof_stat; ++ int reg; ++}; ++ ++static DEFINE_MUTEX(reg_mutex); ++ ++static inline void ar7240sw_init(struct ar7240sw *as, struct mii_bus *mii) ++{ ++ as->mii_bus = mii; ++} ++ ++static inline u16 mk_phy_addr(u32 reg) ++{ ++ return 0x17 & ((reg >> 4) | 0x10); ++} ++ ++static inline u16 mk_phy_reg(u32 reg) ++{ ++ return (reg << 1) & 0x1e; ++} ++ ++static inline u16 mk_high_addr(u32 reg) ++{ ++ return (reg >> 7) & 0x1ff; ++} ++ ++static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg) ++{ ++ unsigned long flags; ++ u16 phy_addr; ++ u16 phy_reg; ++ u32 hi, lo; ++ ++ reg = (reg & 0xfffffffc) >> 2; ++ phy_addr = mk_phy_addr(reg); ++ phy_reg = mk_phy_reg(reg); ++ ++ local_irq_save(flags); ++ ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg)); ++ lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg); ++ hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1); ++ local_irq_restore(flags); ++ ++ return (hi << 16) | lo; ++} ++ ++static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val) ++{ ++ unsigned long flags; ++ u16 phy_addr; ++ u16 phy_reg; ++ ++ reg = (reg & 0xfffffffc) >> 2; ++ phy_addr = mk_phy_addr(reg); ++ phy_reg = mk_phy_reg(reg); ++ ++ local_irq_save(flags); ++ ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg)); ++ ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16)); ++ ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff)); ++ local_irq_restore(flags); ++} ++ ++static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr) ++{ ++ u32 ret; ++ ++ mutex_lock(®_mutex); ++ ret = __ar7240sw_reg_read(mii, reg_addr); ++ mutex_unlock(®_mutex); ++ ++ return ret; ++} ++ ++static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val) ++{ ++ mutex_lock(®_mutex); ++ __ar7240sw_reg_write(mii, reg_addr, reg_val); ++ mutex_unlock(®_mutex); ++} ++ ++static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val) ++{ ++ u32 t; ++ ++ mutex_lock(®_mutex); ++ t = __ar7240sw_reg_read(mii, reg); ++ t &= ~mask; ++ t |= val; ++ __ar7240sw_reg_write(mii, reg, t); ++ mutex_unlock(®_mutex); ++ ++ return t; ++} ++ ++static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val) ++{ ++ u32 t; ++ ++ mutex_lock(®_mutex); ++ t = __ar7240sw_reg_read(mii, reg); ++ t |= val; ++ __ar7240sw_reg_write(mii, reg, t); ++ mutex_unlock(®_mutex); ++} ++ ++static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val, ++ unsigned timeout) ++{ ++ int i; ++ ++ for (i = 0; i < timeout; i++) { ++ u32 t; ++ ++ t = __ar7240sw_reg_read(mii, reg); ++ if ((t & mask) == val) ++ return 0; ++ ++ msleep(1); ++ } ++ ++ return -ETIMEDOUT; ++} ++ ++static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val, ++ unsigned timeout) ++{ ++ int ret; ++ ++ mutex_lock(®_mutex); ++ ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout); ++ mutex_unlock(®_mutex); ++ return ret; ++} ++ ++u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr, ++ unsigned reg_addr) ++{ ++ u32 t, val = 0xffff; ++ int err; ++ ++ if (phy_addr >= AR7240_NUM_PHYS) ++ return 0xffff; ++ ++ mutex_lock(®_mutex); ++ t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | ++ (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | ++ AR7240_MDIO_CTRL_MASTER_EN | ++ AR7240_MDIO_CTRL_BUSY | ++ AR7240_MDIO_CTRL_CMD_READ; ++ ++ __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t); ++ err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL, ++ AR7240_MDIO_CTRL_BUSY, 0, 5); ++ if (!err) ++ val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL); ++ mutex_unlock(®_mutex); ++ ++ return val & AR7240_MDIO_CTRL_DATA_M; ++} ++ ++int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr, ++ unsigned reg_addr, u16 reg_val) ++{ ++ u32 t; ++ int ret; ++ ++ if (phy_addr >= AR7240_NUM_PHYS) ++ return -EINVAL; ++ ++ mutex_lock(®_mutex); ++ t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | ++ (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | ++ AR7240_MDIO_CTRL_MASTER_EN | ++ AR7240_MDIO_CTRL_BUSY | ++ AR7240_MDIO_CTRL_CMD_WRITE | ++ reg_val; ++ ++ __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t); ++ ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL, ++ AR7240_MDIO_CTRL_BUSY, 0, 5); ++ mutex_unlock(®_mutex); ++ ++ return ret; ++} ++ ++static int ar7240sw_capture_stats(struct ar7240sw *as) ++{ ++ struct mii_bus *mii = as->mii_bus; ++ int ret; ++ ++ /* Capture the hardware statistics for all ports */ ++ ar7240sw_reg_write(mii, AR7240_REG_MIB_FUNCTION0, ++ (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S)); ++ ++ /* Wait for the capturing to complete. */ ++ ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0, ++ AR7240_MIB_BUSY, 0, 10); ++ return ret; ++} ++ ++static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port) ++{ ++ ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port), ++ AR7240_PORT_CTRL_STATE_DISABLED); ++} ++ ++static void ar7240sw_setup(struct ar7240sw *as) ++{ ++ struct mii_bus *mii = as->mii_bus; ++ ++ /* Enable CPU port, and disable mirror port */ ++ ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT, ++ AR7240_CPU_PORT_EN | ++ (15 << AR7240_MIRROR_PORT_S)); ++ ++ /* Setup TAG priority mapping */ ++ ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50); ++ ++ /* Enable ARP frame acknowledge, aging, MAC replacing */ ++ ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL, ++ 0x2b /* 5 min age time */ | ++ AR7240_AT_CTRL_AGE_EN | ++ AR7240_AT_CTRL_ARP_EN | ++ AR7240_AT_CTRL_LEARN_CHANGE); ++ ++ /* Enable Broadcast frames transmitted to the CPU */ ++ ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK, ++ AR7240_FLOOD_MASK_BROAD_TO_CPU); ++ ++ /* setup MTU */ ++ ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M, ++ 1536); ++ ++ /* setup Service TAG */ ++ ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0); ++} ++ ++static int ar7240sw_reset(struct ar7240sw *as) ++{ ++ struct mii_bus *mii = as->mii_bus; ++ int ret; ++ int i; ++ ++ /* Set all ports to disabled state. */ ++ for (i = 0; i < AR7240_NUM_PORTS; i++) ++ ar7240sw_disable_port(as, i); ++ ++ /* Wait for transmit queues to drain. */ ++ msleep(2); ++ ++ /* Reset the switch. */ ++ ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL, ++ AR7240_MASK_CTRL_SOFT_RESET); ++ ++ ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL, ++ AR7240_MASK_CTRL_SOFT_RESET, 0, 1000); ++ ++ ar7240sw_setup(as); ++ return ret; ++} ++ ++static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask) ++{ ++ struct mii_bus *mii = as->mii_bus; ++ u32 ctrl; ++ u32 dest_ports; ++ u32 vlan; ++ ++ ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN | ++ AR7240_PORT_CTRL_SINGLE_VLAN; ++ ++ if (port == AR7240_PORT_CPU) { ++ ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port), ++ AR7240_PORT_STATUS_SPEED_1000 | ++ AR7240_PORT_STATUS_TXFLOW | ++ AR7240_PORT_STATUS_RXFLOW | ++ AR7240_PORT_STATUS_TXMAC | ++ AR7240_PORT_STATUS_RXMAC | ++ AR7240_PORT_STATUS_DUPLEX); ++ } else { ++ ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port), ++ AR7240_PORT_STATUS_LINK_AUTO); ++ } ++ ++ /* Set the default VID for this port */ ++ if (as->vlan) { ++ vlan = as->vlan_id[as->pvid[port]]; ++ vlan |= AR7240_PORT_VLAN_MODE_SECURE << ++ AR7240_PORT_VLAN_MODE_S; ++ } else { ++ vlan = port; ++ vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY << ++ AR7240_PORT_VLAN_MODE_S; ++ } ++ ++ if (as->vlan && (as->vlan_tagged & BIT(port))) { ++ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD << ++ AR7240_PORT_CTRL_VLAN_MODE_S; ++ } else { ++ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP << ++ AR7240_PORT_CTRL_VLAN_MODE_S; ++ } ++ ++ if (!portmask) { ++ if (port == AR7240_PORT_CPU) ++ portmask = AR7240_PORT_MASK_BUT(AR7240_PORT_CPU); ++ else ++ portmask = AR7240_PORT_MASK(AR7240_PORT_CPU); ++ } ++ ++ /* allow the port to talk to all other ports, but exclude its ++ * own ID to prevent frames from being reflected back to the ++ * port that they came from */ ++ dest_ports = AR7240_PORT_MASK_BUT(port); ++ ++ /* set default VID and and destination ports for this VLAN */ ++ vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S); ++ ++ ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl); ++ ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan); ++} ++ ++static int ar7240_set_addr(struct ar7240sw *as, u8 *addr) ++{ ++ struct mii_bus *mii = as->mii_bus; ++ u32 t; ++ ++ t = (addr[4] << 8) | addr[5]; ++ ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t); ++ ++ t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; ++ ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t); ++ ++ return 0; ++} ++ ++static int ++ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ as->vlan_id[val->port_vlan] = val->value.i; ++ return 0; ++} ++ ++static int ++ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ val->value.i = as->vlan_id[val->port_vlan]; ++ return 0; ++} ++ ++static int ++ar7240_set_pvid(struct switch_dev *dev, int port, int vlan) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ ++ /* make sure no invalid PVIDs get set */ ++ ++ if (vlan >= dev->vlans) ++ return -EINVAL; ++ ++ as->pvid[port] = vlan; ++ return 0; ++} ++ ++static int ++ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ *vlan = as->pvid[port]; ++ return 0; ++} ++ ++static int ++ar7240_get_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ u8 ports = as->vlan_table[val->port_vlan]; ++ int i; ++ ++ val->len = 0; ++ for (i = 0; i < AR7240_NUM_PORTS; i++) { ++ struct switch_port *p; ++ ++ if (!(ports & (1 << i))) ++ continue; ++ ++ p = &val->value.ports[val->len++]; ++ p->id = i; ++ if (as->vlan_tagged & (1 << i)) ++ p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); ++ else ++ p->flags = 0; ++ } ++ return 0; ++} ++ ++static int ++ar7240_set_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ u8 *vt = &as->vlan_table[val->port_vlan]; ++ int i, j; ++ ++ *vt = 0; ++ for (i = 0; i < val->len; i++) { ++ struct switch_port *p = &val->value.ports[i]; ++ ++ if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) ++ as->vlan_tagged |= (1 << p->id); ++ else { ++ as->vlan_tagged &= ~(1 << p->id); ++ as->pvid[p->id] = val->port_vlan; ++ ++ /* make sure that an untagged port does not ++ * appear in other vlans */ ++ for (j = 0; j < AR7240_MAX_VLANS; j++) { ++ if (j == val->port_vlan) ++ continue; ++ as->vlan_table[j] &= ~(1 << p->id); ++ } ++ } ++ ++ *vt |= 1 << p->id; ++ } ++ return 0; ++} ++ ++static int ++ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ as->vlan = !!val->value.i; ++ return 0; ++} ++ ++static int ++ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ val->value.i = as->vlan; ++ return 0; ++} ++ ++ ++static void ++ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val) ++{ ++ struct mii_bus *mii = as->mii_bus; ++ ++ if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5)) ++ return; ++ ++ if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) { ++ val &= AR7240_VTUDATA_MEMBER; ++ val |= AR7240_VTUDATA_VALID; ++ ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val); ++ } ++ op |= AR7240_VTU_ACTIVE; ++ ar7240sw_reg_write(mii, AR7240_REG_VTU, op); ++} ++ ++static int ++ar7240_hw_apply(struct switch_dev *dev) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ u8 portmask[AR7240_NUM_PORTS]; ++ int i, j; ++ ++ /* flush all vlan translation unit entries */ ++ ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0); ++ ++ memset(portmask, 0, sizeof(portmask)); ++ if (as->vlan) { ++ /* calculate the port destination masks and load vlans ++ * into the vlan translation unit */ ++ for (j = 0; j < AR7240_MAX_VLANS; j++) { ++ u8 vp = as->vlan_table[j]; ++ ++ if (!vp) ++ continue; ++ ++ for (i = 0; i < AR7240_NUM_PORTS; i++) { ++ u8 mask = (1 << i); ++ if (vp & mask) ++ portmask[i] |= vp & ~mask; ++ } ++ ++ ar7240_vtu_op(as, ++ AR7240_VTU_OP_LOAD | ++ (as->vlan_id[j] << AR7240_VTU_VID_S), ++ as->vlan_table[j]); ++ } ++ } else { ++ /* vlan disabled: ++ * isolate all ports, but connect them to the cpu port */ ++ for (i = 0; i < AR7240_NUM_PORTS; i++) { ++ if (i == AR7240_PORT_CPU) ++ continue; ++ ++ portmask[i] = 1 << AR7240_PORT_CPU; ++ portmask[AR7240_PORT_CPU] |= (1 << i); ++ } ++ } ++ ++ /* update the port destination mask registers and tag settings */ ++ for (i = 0; i < AR7240_NUM_PORTS; i++) ++ ar7240sw_setup_port(as, i, portmask[i]); ++ ++ return 0; ++} ++ ++static int ++ar7240_reset_switch(struct switch_dev *dev) ++{ ++ struct ar7240sw *as = sw_to_ar7240(dev); ++ ar7240sw_reset(as); ++ return 0; ++} ++ ++static struct switch_attr ar7240_globals[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "enable_vlan", ++ .description = "Enable VLAN mode", ++ .set = ar7240_set_vlan, ++ .get = ar7240_get_vlan, ++ .max = 1 ++ }, ++}; ++ ++static struct switch_attr ar7240_port[] = { ++}; ++ ++static struct switch_attr ar7240_vlan[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "vid", ++ .description = "VLAN ID", ++ .set = ar7240_set_vid, ++ .get = ar7240_get_vid, ++ .max = 4094, ++ }, ++}; ++ ++static const struct switch_dev_ops ar7240_ops = { ++ .attr_global = { ++ .attr = ar7240_globals, ++ .n_attr = ARRAY_SIZE(ar7240_globals), ++ }, ++ .attr_port = { ++ .attr = ar7240_port, ++ .n_attr = ARRAY_SIZE(ar7240_port), ++ }, ++ .attr_vlan = { ++ .attr = ar7240_vlan, ++ .n_attr = ARRAY_SIZE(ar7240_vlan), ++ }, ++ .get_port_pvid = ar7240_get_pvid, ++ .set_port_pvid = ar7240_set_pvid, ++ .get_vlan_ports = ar7240_get_ports, ++ .set_vlan_ports = ar7240_set_ports, ++ .apply_config = ar7240_hw_apply, ++ .reset_switch = ar7240_reset_switch, ++}; ++ ++static struct ar7240sw *ar7240_probe(struct ag71xx *ag) ++{ ++ struct mii_bus *mii = ag->mii_bus; ++ struct ar7240sw *as; ++ struct switch_dev *swdev; ++ u32 ctrl; ++ u16 phy_id1; ++ u16 phy_id2; ++ u8 ver; ++ int i; ++ ++ as = kzalloc(sizeof(*as), GFP_KERNEL); ++ if (!as) ++ return NULL; ++ ++ ar7240sw_init(as, mii); ++ ++ ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL); ++ ++ ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M; ++ if (ver != 1) { ++ pr_err("%s: unsupported chip, ctrl=%08x\n", ++ ag->dev->name, ctrl); ++ return NULL; ++ } ++ ++ phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1); ++ phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2); ++ if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) { ++ pr_err("%s: unknown phy id '%04x:%04x'\n", ++ ag->dev->name, phy_id1, phy_id2); ++ return NULL; ++ } ++ ++ swdev = &as->swdev; ++ swdev->name = "AR7240 built-in switch"; ++ swdev->ports = AR7240_NUM_PORTS; ++ swdev->cpu_port = AR7240_PORT_CPU; ++ swdev->vlans = AR7240_MAX_VLANS; ++ swdev->ops = &ar7240_ops; ++ ++ if (register_switch(&as->swdev, ag->dev) < 0) { ++ kfree(as); ++ return NULL; ++ } ++ ++ pr_info("%s: Found an AR7240 built-in switch\n", ag->dev->name); ++ ++ /* initialize defaults */ ++ for (i = 0; i < AR7240_MAX_VLANS; i++) ++ as->vlan_id[i] = i; ++ ++ as->vlan_table[0] = AR7240_PORT_MASK_ALL; ++ ++ return as; ++} ++ ++static void link_function(struct work_struct *work) { ++ struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work); ++ unsigned long flags; ++ int i; ++ int status = 0; ++ ++ for (i = 0; i < 4; i++) { ++ int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR); ++ if(link & BMSR_LSTATUS) { ++ status = 1; ++ break; ++ } ++ } ++ ++ spin_lock_irqsave(&ag->lock, flags); ++ if(status != ag->link) { ++ ag->link = status; ++ ag71xx_link_adjust(ag); ++ } ++ spin_unlock_irqrestore(&ag->lock, flags); ++ ++ schedule_delayed_work(&ag->link_work, HZ / 2); ++} ++ ++void ag71xx_ar7240_start(struct ag71xx *ag) ++{ ++ struct ar7240sw *as = ag->phy_priv; ++ ++ ar7240sw_reset(as); ++ ++ ag->speed = SPEED_1000; ++ ag->duplex = 1; ++ ++ ar7240_set_addr(as, ag->dev->dev_addr); ++ ar7240_hw_apply(&as->swdev); ++ ++ schedule_delayed_work(&ag->link_work, HZ / 10); ++} ++ ++void ag71xx_ar7240_stop(struct ag71xx *ag) ++{ ++ cancel_delayed_work_sync(&ag->link_work); ++} ++ ++int __devinit ag71xx_ar7240_init(struct ag71xx *ag) ++{ ++ struct ar7240sw *as; ++ ++ as = ar7240_probe(ag); ++ if (!as) ++ return -ENODEV; ++ ++ ag->phy_priv = as; ++ ar7240sw_reset(as); ++ ++ INIT_DELAYED_WORK(&ag->link_work, link_function); ++ ++ return 0; ++} ++ ++void ag71xx_ar7240_cleanup(struct ag71xx *ag) ++{ ++ struct ar7240sw *as = ag->phy_priv; ++ ++ if (!as) ++ return; ++ ++ unregister_switch(&as->swdev); ++ kfree(as); ++ ag->phy_priv = NULL; ++} +diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_ar8216.c linux-2.6.39/drivers/net/ag71xx/ag71xx_ar8216.c +--- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_ar8216.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/net/ag71xx/ag71xx_ar8216.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* ++ * Atheros AR71xx built-in ethernet mac driver ++ * Special support for the Atheros ar8216 switch chip ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * Based on Atheros' AG7100 driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include "ag71xx.h" ++ ++#define AR8216_PACKET_TYPE_MASK 0xf ++#define AR8216_PACKET_TYPE_NORMAL 0 ++ ++#define AR8216_HEADER_LEN 2 ++ ++void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb) ++{ ++ skb_push(skb, AR8216_HEADER_LEN); ++ skb->data[0] = 0x10; ++ skb->data[1] = 0x80; ++} ++ ++int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, ++ int pktlen) ++{ ++ u8 type; ++ ++ type = skb->data[1] & AR8216_PACKET_TYPE_MASK; ++ switch (type) { ++ case AR8216_PACKET_TYPE_NORMAL: ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ skb_pull(skb, AR8216_HEADER_LEN); ++ return 0; ++} +diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_debugfs.c linux-2.6.39/drivers/net/ag71xx/ag71xx_debugfs.c +--- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_debugfs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/net/ag71xx/ag71xx_debugfs.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,280 @@ ++/* ++ * Atheros AR71xx built-in ethernet mac driver ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Based on Atheros' AG7100 driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++ ++#include "ag71xx.h" ++ ++static struct dentry *ag71xx_debugfs_root; ++ ++static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file) ++{ ++ file->private_data = inode->i_private; ++ return 0; ++} ++ ++void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status) ++{ ++ if (status) ++ ag->debug.int_stats.total++; ++ if (status & AG71XX_INT_TX_PS) ++ ag->debug.int_stats.tx_ps++; ++ if (status & AG71XX_INT_TX_UR) ++ ag->debug.int_stats.tx_ur++; ++ if (status & AG71XX_INT_TX_BE) ++ ag->debug.int_stats.tx_be++; ++ if (status & AG71XX_INT_RX_PR) ++ ag->debug.int_stats.rx_pr++; ++ if (status & AG71XX_INT_RX_OF) ++ ag->debug.int_stats.rx_of++; ++ if (status & AG71XX_INT_RX_BE) ++ ag->debug.int_stats.rx_be++; ++} ++ ++static ssize_t read_file_int_stats(struct file *file, char __user *user_buf, ++ size_t count, loff_t *ppos) ++{ ++#define PR_INT_STAT(_label, _field) \ ++ len += snprintf(buf + len, sizeof(buf) - len, \ ++ "%20s: %10lu\n", _label, ag->debug.int_stats._field); ++ ++ struct ag71xx *ag = file->private_data; ++ char buf[256]; ++ unsigned int len = 0; ++ ++ PR_INT_STAT("TX Packet Sent", tx_ps); ++ PR_INT_STAT("TX Underrun", tx_ur); ++ PR_INT_STAT("TX Bus Error", tx_be); ++ PR_INT_STAT("RX Packet Received", rx_pr); ++ PR_INT_STAT("RX Overflow", rx_of); ++ PR_INT_STAT("RX Bus Error", rx_be); ++ len += snprintf(buf + len, sizeof(buf) - len, "\n"); ++ PR_INT_STAT("Total", total); ++ ++ return simple_read_from_buffer(user_buf, count, ppos, buf, len); ++#undef PR_INT_STAT ++} ++ ++static const struct file_operations ag71xx_fops_int_stats = { ++ .open = ag71xx_debugfs_generic_open, ++ .read = read_file_int_stats, ++ .owner = THIS_MODULE ++}; ++ ++void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx) ++{ ++ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; ++ ++ if (rx) { ++ stats->rx_count++; ++ stats->rx_packets += rx; ++ if (rx <= AG71XX_NAPI_WEIGHT) ++ stats->rx[rx]++; ++ if (rx > stats->rx_packets_max) ++ stats->rx_packets_max = rx; ++ } ++ ++ if (tx) { ++ stats->tx_count++; ++ stats->tx_packets += tx; ++ if (tx <= AG71XX_NAPI_WEIGHT) ++ stats->tx[tx]++; ++ if (tx > stats->tx_packets_max) ++ stats->tx_packets_max = tx; ++ } ++} ++ ++static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf, ++ size_t count, loff_t *ppos) ++{ ++ struct ag71xx *ag = file->private_data; ++ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; ++ char *buf; ++ unsigned int buflen; ++ unsigned int len = 0; ++ unsigned long rx_avg = 0; ++ unsigned long tx_avg = 0; ++ int ret; ++ int i; ++ ++ buflen = 2048; ++ buf = kmalloc(buflen, GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ if (stats->rx_count) ++ rx_avg = stats->rx_packets / stats->rx_count; ++ ++ if (stats->tx_count) ++ tx_avg = stats->tx_packets / stats->tx_count; ++ ++ len += snprintf(buf + len, buflen - len, "%3s %10s %10s\n", ++ "len", "rx", "tx"); ++ ++ for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++) ++ len += snprintf(buf + len, buflen - len, ++ "%3d: %10lu %10lu\n", ++ i, stats->rx[i], stats->tx[i]); ++ ++ len += snprintf(buf + len, buflen - len, "\n"); ++ ++ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", ++ "sum", stats->rx_count, stats->tx_count); ++ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", ++ "avg", rx_avg, tx_avg); ++ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", ++ "max", stats->rx_packets_max, stats->tx_packets_max); ++ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", ++ "pkt", stats->rx_packets, stats->tx_packets); ++ ++ ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); ++ kfree(buf); ++ ++ return ret; ++} ++ ++static const struct file_operations ag71xx_fops_napi_stats = { ++ .open = ag71xx_debugfs_generic_open, ++ .read = read_file_napi_stats, ++ .owner = THIS_MODULE ++}; ++ ++#define DESC_PRINT_LEN 64 ++ ++static ssize_t read_file_ring(struct file *file, char __user *user_buf, ++ size_t count, loff_t *ppos, ++ struct ag71xx *ag, ++ struct ag71xx_ring *ring, ++ unsigned desc_reg) ++{ ++ char *buf; ++ unsigned int buflen; ++ unsigned int len = 0; ++ unsigned long flags; ++ ssize_t ret; ++ int curr; ++ int dirty; ++ u32 desc_hw; ++ int i; ++ ++ buflen = (ring->size * DESC_PRINT_LEN); ++ buf = kmalloc(buflen, GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ len += snprintf(buf + len, buflen - len, ++ "Idx ... %-8s %-8s %-8s %-8s . %-10s\n", ++ "desc", "next", "data", "ctrl", "timestamp"); ++ ++ spin_lock_irqsave(&ag->lock, flags); ++ ++ curr = (ring->curr % ring->size); ++ dirty = (ring->dirty % ring->size); ++ desc_hw = ag71xx_rr(ag, desc_reg); ++ for (i = 0; i < ring->size; i++) { ++ struct ag71xx_buf *ab = &ring->buf[i]; ++ u32 desc_dma = ((u32) ring->descs_dma) + i * ring->desc_size; ++ ++ len += snprintf(buf + len, buflen - len, ++ "%3d %c%c%c %08x %08x %08x %08x %c %10lu\n", ++ i, ++ (i == curr) ? 'C' : ' ', ++ (i == dirty) ? 'D' : ' ', ++ (desc_hw == desc_dma) ? 'H' : ' ', ++ desc_dma, ++ ab->desc->next, ++ ab->desc->data, ++ ab->desc->ctrl, ++ (ab->desc->ctrl & DESC_EMPTY) ? 'E' : '*', ++ ab->timestamp); ++ } ++ ++ spin_unlock_irqrestore(&ag->lock, flags); ++ ++ ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); ++ kfree(buf); ++ ++ return ret; ++} ++ ++static ssize_t read_file_tx_ring(struct file *file, char __user *user_buf, ++ size_t count, loff_t *ppos) ++{ ++ struct ag71xx *ag = file->private_data; ++ ++ return read_file_ring(file, user_buf, count, ppos, ag, &ag->tx_ring, ++ AG71XX_REG_TX_DESC); ++} ++ ++static const struct file_operations ag71xx_fops_tx_ring = { ++ .open = ag71xx_debugfs_generic_open, ++ .read = read_file_tx_ring, ++ .owner = THIS_MODULE ++}; ++ ++static ssize_t read_file_rx_ring(struct file *file, char __user *user_buf, ++ size_t count, loff_t *ppos) ++{ ++ struct ag71xx *ag = file->private_data; ++ ++ return read_file_ring(file, user_buf, count, ppos, ag, &ag->rx_ring, ++ AG71XX_REG_RX_DESC); ++} ++ ++static const struct file_operations ag71xx_fops_rx_ring = { ++ .open = ag71xx_debugfs_generic_open, ++ .read = read_file_rx_ring, ++ .owner = THIS_MODULE ++}; ++ ++void ag71xx_debugfs_exit(struct ag71xx *ag) ++{ ++ debugfs_remove_recursive(ag->debug.debugfs_dir); ++} ++ ++int ag71xx_debugfs_init(struct ag71xx *ag) ++{ ++ ag->debug.debugfs_dir = debugfs_create_dir(ag->dev->name, ++ ag71xx_debugfs_root); ++ if (!ag->debug.debugfs_dir) ++ return -ENOMEM; ++ ++ debugfs_create_file("int_stats", S_IRUGO, ag->debug.debugfs_dir, ++ ag, &ag71xx_fops_int_stats); ++ debugfs_create_file("napi_stats", S_IRUGO, ag->debug.debugfs_dir, ++ ag, &ag71xx_fops_napi_stats); ++ debugfs_create_file("tx_ring", S_IRUGO, ag->debug.debugfs_dir, ++ ag, &ag71xx_fops_tx_ring); ++ debugfs_create_file("rx_ring", S_IRUGO, ag->debug.debugfs_dir, ++ ag, &ag71xx_fops_rx_ring); ++ ++ return 0; ++} ++ ++int ag71xx_debugfs_root_init(void) ++{ ++ if (ag71xx_debugfs_root) ++ return -EBUSY; ++ ++ ag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); ++ if (!ag71xx_debugfs_root) ++ return -ENOENT; ++ ++ return 0; ++} ++ ++void ag71xx_debugfs_root_exit(void) ++{ ++ debugfs_remove(ag71xx_debugfs_root); ++ ag71xx_debugfs_root = NULL; ++} +diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_ethtool.c linux-2.6.39/drivers/net/ag71xx/ag71xx_ethtool.c +--- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_ethtool.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/net/ag71xx/ag71xx_ethtool.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,124 @@ ++/* ++ * Atheros AR71xx built-in ethernet mac driver ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Based on Atheros' AG7100 driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include "ag71xx.h" ++ ++static int ag71xx_ethtool_get_settings(struct net_device *dev, ++ struct ethtool_cmd *cmd) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ struct phy_device *phydev = ag->phy_dev; ++ ++ if (!phydev) ++ return -ENODEV; ++ ++ return phy_ethtool_gset(phydev, cmd); ++} ++ ++static int ag71xx_ethtool_set_settings(struct net_device *dev, ++ struct ethtool_cmd *cmd) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ struct phy_device *phydev = ag->phy_dev; ++ ++ if (!phydev) ++ return -ENODEV; ++ ++ return phy_ethtool_sset(phydev, cmd); ++} ++ ++static void ag71xx_ethtool_get_drvinfo(struct net_device *dev, ++ struct ethtool_drvinfo *info) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ ++ strcpy(info->driver, ag->pdev->dev.driver->name); ++ strcpy(info->version, AG71XX_DRV_VERSION); ++ strcpy(info->bus_info, dev_name(&ag->pdev->dev)); ++} ++ ++static u32 ag71xx_ethtool_get_msglevel(struct net_device *dev) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ ++ return ag->msg_enable; ++} ++ ++static void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ ++ ag->msg_enable = msg_level; ++} ++ ++static void ag71xx_ethtool_get_ringparam(struct net_device *dev, ++ struct ethtool_ringparam *er) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ ++ er->tx_max_pending = AG71XX_TX_RING_SIZE_MAX; ++ er->rx_max_pending = AG71XX_RX_RING_SIZE_MAX; ++ er->rx_mini_max_pending = 0; ++ er->rx_jumbo_max_pending = 0; ++ ++ er->tx_pending = ag->tx_ring.size; ++ er->rx_pending = ag->rx_ring.size; ++ er->rx_mini_pending = 0; ++ er->rx_jumbo_pending = 0; ++} ++ ++static int ag71xx_ethtool_set_ringparam(struct net_device *dev, ++ struct ethtool_ringparam *er) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ unsigned tx_size; ++ unsigned rx_size; ++ int err; ++ ++ if (er->rx_mini_pending != 0|| ++ er->rx_jumbo_pending != 0 || ++ er->rx_pending == 0 || ++ er->tx_pending == 0) ++ return -EINVAL; ++ ++ tx_size = er->tx_pending < AG71XX_TX_RING_SIZE_MAX ? ++ er->tx_pending : AG71XX_TX_RING_SIZE_MAX; ++ ++ rx_size = er->rx_pending < AG71XX_RX_RING_SIZE_MAX ? ++ er->rx_pending : AG71XX_RX_RING_SIZE_MAX; ++ ++ if (netif_running(dev)) { ++ err = dev->netdev_ops->ndo_stop(dev); ++ if (err) ++ return err; ++ } ++ ++ ag->tx_ring.size = tx_size; ++ ag->rx_ring.size = rx_size; ++ ++ if (netif_running(dev)) ++ err = dev->netdev_ops->ndo_open(dev); ++ ++ return err; ++} ++ ++struct ethtool_ops ag71xx_ethtool_ops = { ++ .set_settings = ag71xx_ethtool_set_settings, ++ .get_settings = ag71xx_ethtool_get_settings, ++ .get_drvinfo = ag71xx_ethtool_get_drvinfo, ++ .get_msglevel = ag71xx_ethtool_get_msglevel, ++ .set_msglevel = ag71xx_ethtool_set_msglevel, ++ .get_ringparam = ag71xx_ethtool_get_ringparam, ++ .set_ringparam = ag71xx_ethtool_set_ringparam, ++ .get_link = ethtool_op_get_link, ++}; +diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_main.c linux-2.6.39/drivers/net/ag71xx/ag71xx_main.c +--- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_main.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/net/ag71xx/ag71xx_main.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,1291 @@ ++/* ++ * Atheros AR71xx built-in ethernet mac driver ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Based on Atheros' AG7100 driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include "ag71xx.h" ++ ++#define AG71XX_DEFAULT_MSG_ENABLE \ ++ (NETIF_MSG_DRV \ ++ | NETIF_MSG_PROBE \ ++ | NETIF_MSG_LINK \ ++ | NETIF_MSG_TIMER \ ++ | NETIF_MSG_IFDOWN \ ++ | NETIF_MSG_IFUP \ ++ | NETIF_MSG_RX_ERR \ ++ | NETIF_MSG_TX_ERR) ++ ++static int ag71xx_msg_level = -1; ++ ++module_param_named(msg_level, ag71xx_msg_level, int, 0); ++MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); ++ ++static void ag71xx_dump_dma_regs(struct ag71xx *ag) ++{ ++ DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_TX_CTRL), ++ ag71xx_rr(ag, AG71XX_REG_TX_DESC), ++ ag71xx_rr(ag, AG71XX_REG_TX_STATUS)); ++ ++ DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_RX_CTRL), ++ ag71xx_rr(ag, AG71XX_REG_RX_DESC), ++ ag71xx_rr(ag, AG71XX_REG_RX_STATUS)); ++} ++ ++static void ag71xx_dump_regs(struct ag71xx *ag) ++{ ++ DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_MAC_CFG1), ++ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), ++ ag71xx_rr(ag, AG71XX_REG_MAC_IPG), ++ ag71xx_rr(ag, AG71XX_REG_MAC_HDX), ++ ag71xx_rr(ag, AG71XX_REG_MAC_MFL)); ++ DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), ++ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1), ++ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2)); ++ DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); ++ DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); ++} ++ ++static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr) ++{ ++ DBG("%s: %s intr=%08x %s%s%s%s%s%s\n", ++ ag->dev->name, label, intr, ++ (intr & AG71XX_INT_TX_PS) ? "TXPS " : "", ++ (intr & AG71XX_INT_TX_UR) ? "TXUR " : "", ++ (intr & AG71XX_INT_TX_BE) ? "TXBE " : "", ++ (intr & AG71XX_INT_RX_PR) ? "RXPR " : "", ++ (intr & AG71XX_INT_RX_OF) ? "RXOF " : "", ++ (intr & AG71XX_INT_RX_BE) ? "RXBE " : ""); ++} ++ ++static void ag71xx_ring_free(struct ag71xx_ring *ring) ++{ ++ kfree(ring->buf); ++ ++ if (ring->descs_cpu) ++ dma_free_coherent(NULL, ring->size * ring->desc_size, ++ ring->descs_cpu, ring->descs_dma); ++} ++ ++static int ag71xx_ring_alloc(struct ag71xx_ring *ring) ++{ ++ int err; ++ int i; ++ ++ ring->desc_size = sizeof(struct ag71xx_desc); ++ if (ring->desc_size % cache_line_size()) { ++ DBG("ag71xx: ring %p, desc size %u rounded to %u\n", ++ ring, ring->desc_size, ++ roundup(ring->desc_size, cache_line_size())); ++ ring->desc_size = roundup(ring->desc_size, cache_line_size()); ++ } ++ ++ ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size, ++ &ring->descs_dma, GFP_ATOMIC); ++ if (!ring->descs_cpu) { ++ err = -ENOMEM; ++ goto err; ++ } ++ ++ ++ ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL); ++ if (!ring->buf) { ++ err = -ENOMEM; ++ goto err; ++ } ++ ++ for (i = 0; i < ring->size; i++) { ++ int idx = i * ring->desc_size; ++ ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx]; ++ DBG("ag71xx: ring %p, desc %d at %p\n", ++ ring, i, ring->buf[i].desc); ++ } ++ ++ return 0; ++ ++err: ++ return err; ++} ++ ++static void ag71xx_ring_tx_clean(struct ag71xx *ag) ++{ ++ struct ag71xx_ring *ring = &ag->tx_ring; ++ struct net_device *dev = ag->dev; ++ ++ while (ring->curr != ring->dirty) { ++ u32 i = ring->dirty % ring->size; ++ ++ if (!ag71xx_desc_empty(ring->buf[i].desc)) { ++ ring->buf[i].desc->ctrl = 0; ++ dev->stats.tx_errors++; ++ } ++ ++ if (ring->buf[i].skb) ++ dev_kfree_skb_any(ring->buf[i].skb); ++ ++ ring->buf[i].skb = NULL; ++ ++ ring->dirty++; ++ } ++ ++ /* flush descriptors */ ++ wmb(); ++ ++} ++ ++static void ag71xx_ring_tx_init(struct ag71xx *ag) ++{ ++ struct ag71xx_ring *ring = &ag->tx_ring; ++ int i; ++ ++ for (i = 0; i < ring->size; i++) { ++ ring->buf[i].desc->next = (u32) (ring->descs_dma + ++ ring->desc_size * ((i + 1) % ring->size)); ++ ++ ring->buf[i].desc->ctrl = DESC_EMPTY; ++ ring->buf[i].skb = NULL; ++ } ++ ++ /* flush descriptors */ ++ wmb(); ++ ++ ring->curr = 0; ++ ring->dirty = 0; ++} ++ ++static void ag71xx_ring_rx_clean(struct ag71xx *ag) ++{ ++ struct ag71xx_ring *ring = &ag->rx_ring; ++ int i; ++ ++ if (!ring->buf) ++ return; ++ ++ for (i = 0; i < ring->size; i++) ++ if (ring->buf[i].skb) { ++ dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr, ++ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE); ++ kfree_skb(ring->buf[i].skb); ++ } ++} ++ ++static int ag71xx_rx_reserve(struct ag71xx *ag) ++{ ++ int reserve = 0; ++ ++ if (ag71xx_get_pdata(ag)->is_ar724x) { ++ if (!ag71xx_has_ar8216(ag)) ++ reserve = 2; ++ ++ if (ag->phy_dev) ++ reserve += 4 - (ag->phy_dev->pkt_align % 4); ++ ++ reserve %= 4; ++ } ++ ++ return reserve + AG71XX_RX_PKT_RESERVE; ++} ++ ++ ++static int ag71xx_ring_rx_init(struct ag71xx *ag) ++{ ++ struct ag71xx_ring *ring = &ag->rx_ring; ++ unsigned int reserve = ag71xx_rx_reserve(ag); ++ unsigned int i; ++ int ret; ++ ++ ret = 0; ++ for (i = 0; i < ring->size; i++) { ++ ring->buf[i].desc->next = (u32) (ring->descs_dma + ++ ring->desc_size * ((i + 1) % ring->size)); ++ ++ DBG("ag71xx: RX desc at %p, next is %08x\n", ++ ring->buf[i].desc, ++ ring->buf[i].desc->next); ++ } ++ ++ for (i = 0; i < ring->size; i++) { ++ struct sk_buff *skb; ++ dma_addr_t dma_addr; ++ ++ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve); ++ if (!skb) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ skb->dev = ag->dev; ++ skb_reserve(skb, reserve); ++ ++ dma_addr = dma_map_single(&ag->dev->dev, skb->data, ++ AG71XX_RX_PKT_SIZE, ++ DMA_FROM_DEVICE); ++ ring->buf[i].skb = skb; ++ ring->buf[i].dma_addr = dma_addr; ++ ring->buf[i].desc->data = (u32) dma_addr; ++ ring->buf[i].desc->ctrl = DESC_EMPTY; ++ } ++ ++ /* flush descriptors */ ++ wmb(); ++ ++ ring->curr = 0; ++ ring->dirty = 0; ++ ++ return ret; ++} ++ ++static int ag71xx_ring_rx_refill(struct ag71xx *ag) ++{ ++ struct ag71xx_ring *ring = &ag->rx_ring; ++ unsigned int reserve = ag71xx_rx_reserve(ag); ++ unsigned int count; ++ ++ count = 0; ++ for (; ring->curr - ring->dirty > 0; ring->dirty++) { ++ unsigned int i; ++ ++ i = ring->dirty % ring->size; ++ ++ if (ring->buf[i].skb == NULL) { ++ dma_addr_t dma_addr; ++ struct sk_buff *skb; ++ ++ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve); ++ if (skb == NULL) ++ break; ++ ++ skb_reserve(skb, reserve); ++ skb->dev = ag->dev; ++ ++ dma_addr = dma_map_single(&ag->dev->dev, skb->data, ++ AG71XX_RX_PKT_SIZE, ++ DMA_FROM_DEVICE); ++ ++ ring->buf[i].skb = skb; ++ ring->buf[i].dma_addr = dma_addr; ++ ring->buf[i].desc->data = (u32) dma_addr; ++ } ++ ++ ring->buf[i].desc->ctrl = DESC_EMPTY; ++ count++; ++ } ++ ++ /* flush descriptors */ ++ wmb(); ++ ++ DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count); ++ ++ return count; ++} ++ ++static int ag71xx_rings_init(struct ag71xx *ag) ++{ ++ int ret; ++ ++ ret = ag71xx_ring_alloc(&ag->tx_ring); ++ if (ret) ++ return ret; ++ ++ ag71xx_ring_tx_init(ag); ++ ++ ret = ag71xx_ring_alloc(&ag->rx_ring); ++ if (ret) ++ return ret; ++ ++ ret = ag71xx_ring_rx_init(ag); ++ return ret; ++} ++ ++static void ag71xx_rings_cleanup(struct ag71xx *ag) ++{ ++ ag71xx_ring_rx_clean(ag); ++ ag71xx_ring_free(&ag->rx_ring); ++ ++ ag71xx_ring_tx_clean(ag); ++ ag71xx_ring_free(&ag->tx_ring); ++} ++ ++static unsigned char *ag71xx_speed_str(struct ag71xx *ag) ++{ ++ switch (ag->speed) { ++ case SPEED_1000: ++ return "1000"; ++ case SPEED_100: ++ return "100"; ++ case SPEED_10: ++ return "10"; ++ } ++ ++ return "?"; ++} ++ ++static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) ++{ ++ u32 t; ++ ++ t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16) ++ | (((u32) mac[3]) << 8) | ((u32) mac[2]); ++ ++ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); ++ ++ t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16); ++ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); ++} ++ ++static void ag71xx_dma_reset(struct ag71xx *ag) ++{ ++ u32 val; ++ int i; ++ ++ ag71xx_dump_dma_regs(ag); ++ ++ /* stop RX and TX */ ++ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); ++ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); ++ ++ /* ++ * give the hardware some time to really stop all rx/tx activity ++ * clearing the descriptors too early causes random memory corruption ++ */ ++ mdelay(1); ++ ++ /* clear descriptor addresses */ ++ ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma); ++ ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma); ++ ++ /* clear pending RX/TX interrupts */ ++ for (i = 0; i < 256; i++) { ++ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); ++ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); ++ } ++ ++ /* clear pending errors */ ++ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); ++ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); ++ ++ val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); ++ if (val) ++ printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n", ++ ag->dev->name, val); ++ ++ val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); ++ ++ /* mask out reserved bits */ ++ val &= ~0xff000000; ++ ++ if (val) ++ printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n", ++ ag->dev->name, val); ++ ++ ag71xx_dump_dma_regs(ag); ++} ++ ++#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ ++ MAC_CFG1_SRX | MAC_CFG1_STX) ++ ++#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) ++ ++#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ ++ FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ ++ FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ ++ FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ ++ FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ ++ FIFO_CFG4_VT) ++ ++#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ ++ FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ ++ FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ ++ FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ ++ FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ ++ FIFO_CFG5_17 | FIFO_CFG5_SF) ++ ++static void ag71xx_hw_stop(struct ag71xx *ag) ++{ ++ /* disable all interrupts and stop the rx/tx engine */ ++ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); ++ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); ++ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); ++} ++ ++static void ag71xx_hw_setup(struct ag71xx *ag) ++{ ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ ++ /* setup MAC configuration registers */ ++ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT); ++ ++ ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, ++ MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); ++ ++ /* setup max frame length */ ++ ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN); ++ ++ /* setup MII interface type */ ++ ag71xx_mii_ctrl_set_if(ag, pdata->mii_if); ++ ++ /* setup FIFO configuration registers */ ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); ++ if (pdata->is_ar724x) { ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1); ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2); ++ } else { ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000); ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff); ++ } ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); ++} ++ ++static void ag71xx_hw_init(struct ag71xx *ag) ++{ ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ u32 reset_mask = pdata->reset_bit; ++ ++ ag71xx_hw_stop(ag); ++ ++ if (pdata->is_ar724x) { ++ u32 reset_phy = reset_mask; ++ ++ reset_phy &= RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY; ++ reset_mask &= ~(RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY); ++ ++ ar71xx_device_stop(reset_phy); ++ mdelay(50); ++ ar71xx_device_start(reset_phy); ++ mdelay(200); ++ } ++ ++ ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); ++ udelay(20); ++ ++ ar71xx_device_stop(reset_mask); ++ mdelay(100); ++ ar71xx_device_start(reset_mask); ++ mdelay(200); ++ ++ ag71xx_hw_setup(ag); ++ ++ ag71xx_dma_reset(ag); ++} ++ ++static void ag71xx_fast_reset(struct ag71xx *ag) ++{ ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ struct net_device *dev = ag->dev; ++ u32 reset_mask = pdata->reset_bit; ++ u32 rx_ds, tx_ds; ++ u32 mii_reg; ++ ++ reset_mask &= RESET_MODULE_GE0_MAC | RESET_MODULE_GE1_MAC; ++ ++ mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG); ++ rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC); ++ tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC); ++ ++ ar71xx_device_stop(reset_mask); ++ udelay(10); ++ ar71xx_device_start(reset_mask); ++ udelay(10); ++ ++ ag71xx_dma_reset(ag); ++ ag71xx_hw_setup(ag); ++ ++ ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds); ++ ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds); ++ ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg); ++ ++ ag71xx_hw_set_macaddr(ag, dev->dev_addr); ++} ++ ++static void ag71xx_hw_start(struct ag71xx *ag) ++{ ++ /* start RX engine */ ++ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); ++ ++ /* enable interrupts */ ++ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); ++} ++ ++void ag71xx_link_adjust(struct ag71xx *ag) ++{ ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ u32 cfg2; ++ u32 ifctl; ++ u32 fifo5; ++ u32 mii_speed; ++ ++ if (!ag->link) { ++ ag71xx_hw_stop(ag); ++ netif_carrier_off(ag->dev); ++ if (netif_msg_link(ag)) ++ printk(KERN_INFO "%s: link down\n", ag->dev->name); ++ return; ++ } ++ ++ if (pdata->is_ar724x) ++ ag71xx_fast_reset(ag); ++ ++ cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); ++ cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); ++ cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0; ++ ++ ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); ++ ifctl &= ~(MAC_IFCTL_SPEED); ++ ++ fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); ++ fifo5 &= ~FIFO_CFG5_BM; ++ ++ switch (ag->speed) { ++ case SPEED_1000: ++ mii_speed = MII_CTRL_SPEED_1000; ++ cfg2 |= MAC_CFG2_IF_1000; ++ fifo5 |= FIFO_CFG5_BM; ++ break; ++ case SPEED_100: ++ mii_speed = MII_CTRL_SPEED_100; ++ cfg2 |= MAC_CFG2_IF_10_100; ++ ifctl |= MAC_IFCTL_SPEED; ++ break; ++ case SPEED_10: ++ mii_speed = MII_CTRL_SPEED_10; ++ cfg2 |= MAC_CFG2_IF_10_100; ++ break; ++ default: ++ BUG(); ++ return; ++ } ++ ++ if (pdata->is_ar91xx) ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff); ++ else if (pdata->is_ar724x) ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3); ++ else ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff); ++ ++ if (pdata->set_pll) ++ pdata->set_pll(ag->speed); ++ ++ ag71xx_mii_ctrl_set_speed(ag, mii_speed); ++ ++ ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); ++ ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); ++ ag71xx_hw_start(ag); ++ ++ netif_carrier_on(ag->dev); ++ if (netif_msg_link(ag)) ++ printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n", ++ ag->dev->name, ++ ag71xx_speed_str(ag), ++ (DUPLEX_FULL == ag->duplex) ? "Full" : "Half"); ++ ++ DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); ++ ++ DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); ++ ++ DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), ++ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), ++ ag71xx_mii_ctrl_rr(ag)); ++} ++ ++static int ag71xx_open(struct net_device *dev) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ int ret; ++ ++ ret = ag71xx_rings_init(ag); ++ if (ret) ++ goto err; ++ ++ napi_enable(&ag->napi); ++ ++ netif_carrier_off(dev); ++ ag71xx_phy_start(ag); ++ ++ ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); ++ ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); ++ ++ ag71xx_hw_set_macaddr(ag, dev->dev_addr); ++ ++ netif_start_queue(dev); ++ ++ return 0; ++ ++err: ++ ag71xx_rings_cleanup(ag); ++ return ret; ++} ++ ++static int ag71xx_stop(struct net_device *dev) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ unsigned long flags; ++ ++ netif_carrier_off(dev); ++ ag71xx_phy_stop(ag); ++ ++ spin_lock_irqsave(&ag->lock, flags); ++ ++ netif_stop_queue(dev); ++ ++ ag71xx_hw_stop(ag); ++ ag71xx_dma_reset(ag); ++ ++ napi_disable(&ag->napi); ++ del_timer_sync(&ag->oom_timer); ++ ++ spin_unlock_irqrestore(&ag->lock, flags); ++ ++ ag71xx_rings_cleanup(ag); ++ ++ return 0; ++} ++ ++static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, ++ struct net_device *dev) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ struct ag71xx_ring *ring = &ag->tx_ring; ++ struct ag71xx_desc *desc; ++ dma_addr_t dma_addr; ++ int i; ++ ++ i = ring->curr % ring->size; ++ desc = ring->buf[i].desc; ++ ++ if (!ag71xx_desc_empty(desc)) ++ goto err_drop; ++ ++ if (ag71xx_has_ar8216(ag)) ++ ag71xx_add_ar8216_header(ag, skb); ++ ++ if (skb->len <= 0) { ++ DBG("%s: packet len is too small\n", ag->dev->name); ++ goto err_drop; ++ } ++ ++ dma_addr = dma_map_single(&dev->dev, skb->data, skb->len, ++ DMA_TO_DEVICE); ++ ++ ring->buf[i].skb = skb; ++ ring->buf[i].timestamp = jiffies; ++ ++ /* setup descriptor fields */ ++ desc->data = (u32) dma_addr; ++ desc->ctrl = (skb->len & DESC_PKTLEN_M); ++ ++ /* flush descriptor */ ++ wmb(); ++ ++ ring->curr++; ++ if (ring->curr == (ring->dirty + ring->size)) { ++ DBG("%s: tx queue full\n", ag->dev->name); ++ netif_stop_queue(dev); ++ } ++ ++ DBG("%s: packet injected into TX queue\n", ag->dev->name); ++ ++ /* enable TX engine */ ++ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); ++ ++ return NETDEV_TX_OK; ++ ++err_drop: ++ dev->stats.tx_dropped++; ++ ++ dev_kfree_skb(skb); ++ return NETDEV_TX_OK; ++} ++ ++static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ int ret; ++ ++ switch (cmd) { ++ case SIOCETHTOOL: ++ if (ag->phy_dev == NULL) ++ break; ++ ++ spin_lock_irq(&ag->lock); ++ ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data); ++ spin_unlock_irq(&ag->lock); ++ return ret; ++ ++ case SIOCSIFHWADDR: ++ if (copy_from_user ++ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) ++ return -EFAULT; ++ return 0; ++ ++ case SIOCGIFHWADDR: ++ if (copy_to_user ++ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) ++ return -EFAULT; ++ return 0; ++ ++ case SIOCGMIIPHY: ++ case SIOCGMIIREG: ++ case SIOCSMIIREG: ++ if (ag->phy_dev == NULL) ++ break; ++ ++ return phy_mii_ioctl(ag->phy_dev, ifr, cmd); ++ ++ default: ++ break; ++ } ++ ++ return -EOPNOTSUPP; ++} ++ ++static void ag71xx_oom_timer_handler(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *) data; ++ struct ag71xx *ag = netdev_priv(dev); ++ ++ napi_schedule(&ag->napi); ++} ++ ++static void ag71xx_tx_timeout(struct net_device *dev) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ ++ if (netif_msg_tx_err(ag)) ++ printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name); ++ ++ schedule_work(&ag->restart_work); ++} ++ ++static void ag71xx_restart_work_func(struct work_struct *work) ++{ ++ struct ag71xx *ag = container_of(work, struct ag71xx, restart_work); ++ ++ if (ag71xx_get_pdata(ag)->is_ar724x) { ++ ag->link = 0; ++ ag71xx_link_adjust(ag); ++ return; ++ } ++ ++ ag71xx_stop(ag->dev); ++ ag71xx_open(ag->dev); ++} ++ ++static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp) ++{ ++ u32 rx_sm, tx_sm, rx_fd; ++ ++ if (likely(time_before(jiffies, timestamp + HZ/10))) ++ return false; ++ ++ if (!netif_carrier_ok(ag->dev)) ++ return false; ++ ++ rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM); ++ if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6) ++ return true; ++ ++ tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM); ++ rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH); ++ if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) && ++ ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0) ++ return true; ++ ++ return false; ++} ++ ++static int ag71xx_tx_packets(struct ag71xx *ag) ++{ ++ struct ag71xx_ring *ring = &ag->tx_ring; ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ int sent; ++ ++ DBG("%s: processing TX ring\n", ag->dev->name); ++ ++ sent = 0; ++ while (ring->dirty != ring->curr) { ++ unsigned int i = ring->dirty % ring->size; ++ struct ag71xx_desc *desc = ring->buf[i].desc; ++ struct sk_buff *skb = ring->buf[i].skb; ++ ++ if (!ag71xx_desc_empty(desc)) { ++ if (pdata->is_ar7240 && ++ ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp)) ++ schedule_work(&ag->restart_work); ++ break; ++ } ++ ++ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); ++ ++ ag->dev->stats.tx_bytes += skb->len; ++ ag->dev->stats.tx_packets++; ++ ++ dev_kfree_skb_any(skb); ++ ring->buf[i].skb = NULL; ++ ++ ring->dirty++; ++ sent++; ++ } ++ ++ DBG("%s: %d packets sent out\n", ag->dev->name, sent); ++ ++ if ((ring->curr - ring->dirty) < (ring->size * 3) / 4) ++ netif_wake_queue(ag->dev); ++ ++ return sent; ++} ++ ++static int ag71xx_rx_packets(struct ag71xx *ag, int limit) ++{ ++ struct net_device *dev = ag->dev; ++ struct ag71xx_ring *ring = &ag->rx_ring; ++ int done = 0; ++ ++ DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n", ++ dev->name, limit, ring->curr, ring->dirty); ++ ++ while (done < limit) { ++ unsigned int i = ring->curr % ring->size; ++ struct ag71xx_desc *desc = ring->buf[i].desc; ++ struct sk_buff *skb; ++ int pktlen; ++ int err = 0; ++ ++ if (ag71xx_desc_empty(desc)) ++ break; ++ ++ if ((ring->dirty + ring->size) == ring->curr) { ++ ag71xx_assert(0); ++ break; ++ } ++ ++ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); ++ ++ skb = ring->buf[i].skb; ++ pktlen = ag71xx_desc_pktlen(desc); ++ pktlen -= ETH_FCS_LEN; ++ ++ dma_unmap_single(&dev->dev, ring->buf[i].dma_addr, ++ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE); ++ ++ dev->last_rx = jiffies; ++ dev->stats.rx_packets++; ++ dev->stats.rx_bytes += pktlen; ++ ++ skb_put(skb, pktlen); ++ if (ag71xx_has_ar8216(ag)) ++ err = ag71xx_remove_ar8216_header(ag, skb, pktlen); ++ ++ if (err) { ++ dev->stats.rx_dropped++; ++ kfree_skb(skb); ++ } else { ++ skb->dev = dev; ++ skb->ip_summed = CHECKSUM_NONE; ++ if (ag->phy_dev) { ++ ag->phy_dev->netif_receive_skb(skb); ++ } else { ++ skb->protocol = eth_type_trans(skb, dev); ++ netif_receive_skb(skb); ++ } ++ } ++ ++ ring->buf[i].skb = NULL; ++ done++; ++ ++ ring->curr++; ++ } ++ ++ ag71xx_ring_rx_refill(ag); ++ ++ DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n", ++ dev->name, ring->curr, ring->dirty, done); ++ ++ return done; ++} ++ ++static int ag71xx_poll(struct napi_struct *napi, int limit) ++{ ++ struct ag71xx *ag = container_of(napi, struct ag71xx, napi); ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ struct net_device *dev = ag->dev; ++ struct ag71xx_ring *rx_ring; ++ unsigned long flags; ++ u32 status; ++ int tx_done; ++ int rx_done; ++ ++ pdata->ddr_flush(); ++ tx_done = ag71xx_tx_packets(ag); ++ ++ DBG("%s: processing RX ring\n", dev->name); ++ rx_done = ag71xx_rx_packets(ag, limit); ++ ++ ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done); ++ ++ rx_ring = &ag->rx_ring; ++ if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL) ++ goto oom; ++ ++ status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); ++ if (unlikely(status & RX_STATUS_OF)) { ++ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); ++ dev->stats.rx_fifo_errors++; ++ ++ /* restart RX */ ++ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); ++ } ++ ++ if (rx_done < limit) { ++ if (status & RX_STATUS_PR) ++ goto more; ++ ++ status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); ++ if (status & TX_STATUS_PS) ++ goto more; ++ ++ DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n", ++ dev->name, rx_done, tx_done, limit); ++ ++ napi_complete(napi); ++ ++ /* enable interrupts */ ++ spin_lock_irqsave(&ag->lock, flags); ++ ag71xx_int_enable(ag, AG71XX_INT_POLL); ++ spin_unlock_irqrestore(&ag->lock, flags); ++ return rx_done; ++ } ++ ++more: ++ DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n", ++ dev->name, rx_done, tx_done, limit); ++ return rx_done; ++ ++oom: ++ if (netif_msg_rx_err(ag)) ++ printk(KERN_DEBUG "%s: out of memory\n", dev->name); ++ ++ mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); ++ napi_complete(napi); ++ return 0; ++} ++ ++static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) ++{ ++ struct net_device *dev = dev_id; ++ struct ag71xx *ag = netdev_priv(dev); ++ u32 status; ++ ++ status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); ++ ag71xx_dump_intr(ag, "raw", status); ++ ++ if (unlikely(!status)) ++ return IRQ_NONE; ++ ++ if (unlikely(status & AG71XX_INT_ERR)) { ++ if (status & AG71XX_INT_TX_BE) { ++ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); ++ dev_err(&dev->dev, "TX BUS error\n"); ++ } ++ if (status & AG71XX_INT_RX_BE) { ++ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); ++ dev_err(&dev->dev, "RX BUS error\n"); ++ } ++ } ++ ++ if (likely(status & AG71XX_INT_POLL)) { ++ ag71xx_int_disable(ag, AG71XX_INT_POLL); ++ DBG("%s: enable polling mode\n", dev->name); ++ napi_schedule(&ag->napi); ++ } ++ ++ ag71xx_debugfs_update_int_stats(ag, status); ++ ++ return IRQ_HANDLED; ++} ++ ++static void ag71xx_set_multicast_list(struct net_device *dev) ++{ ++ /* TODO */ ++} ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++/* ++ * Polling 'interrupt' - used by things like netconsole to send skbs ++ * without having to re-enable interrupts. It's not called while ++ * the interrupt routine is executing. ++ */ ++static void ag71xx_netpoll(struct net_device *dev) ++{ ++ disable_irq(dev->irq); ++ ag71xx_interrupt(dev->irq, dev); ++ enable_irq(dev->irq); ++} ++#endif ++ ++static const struct net_device_ops ag71xx_netdev_ops = { ++ .ndo_open = ag71xx_open, ++ .ndo_stop = ag71xx_stop, ++ .ndo_start_xmit = ag71xx_hard_start_xmit, ++ .ndo_set_multicast_list = ag71xx_set_multicast_list, ++ .ndo_do_ioctl = ag71xx_do_ioctl, ++ .ndo_tx_timeout = ag71xx_tx_timeout, ++ .ndo_change_mtu = eth_change_mtu, ++ .ndo_set_mac_address = eth_mac_addr, ++ .ndo_validate_addr = eth_validate_addr, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = ag71xx_netpoll, ++#endif ++}; ++ ++static int __devinit ag71xx_probe(struct platform_device *pdev) ++{ ++ struct net_device *dev; ++ struct resource *res; ++ struct ag71xx *ag; ++ struct ag71xx_platform_data *pdata; ++ int err; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata) { ++ dev_err(&pdev->dev, "no platform data specified\n"); ++ err = -ENXIO; ++ goto err_out; ++ } ++ ++ if (pdata->mii_bus_dev == NULL) { ++ dev_err(&pdev->dev, "no MII bus device specified\n"); ++ err = -EINVAL; ++ goto err_out; ++ } ++ ++ dev = alloc_etherdev(sizeof(*ag)); ++ if (!dev) { ++ dev_err(&pdev->dev, "alloc_etherdev failed\n"); ++ err = -ENOMEM; ++ goto err_out; ++ } ++ ++ SET_NETDEV_DEV(dev, &pdev->dev); ++ ++ ag = netdev_priv(dev); ++ ag->pdev = pdev; ++ ag->dev = dev; ++ ag->msg_enable = netif_msg_init(ag71xx_msg_level, ++ AG71XX_DEFAULT_MSG_ENABLE); ++ spin_lock_init(&ag->lock); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base"); ++ if (!res) { ++ dev_err(&pdev->dev, "no mac_base resource found\n"); ++ err = -ENXIO; ++ goto err_out; ++ } ++ ++ ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1); ++ if (!ag->mac_base) { ++ dev_err(&pdev->dev, "unable to ioremap mac_base\n"); ++ err = -ENOMEM; ++ goto err_free_dev; ++ } ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl"); ++ if (!res) { ++ dev_err(&pdev->dev, "no mii_ctrl resource found\n"); ++ err = -ENXIO; ++ goto err_unmap_base; ++ } ++ ++ ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1); ++ if (!ag->mii_ctrl) { ++ dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n"); ++ err = -ENOMEM; ++ goto err_unmap_base; ++ } ++ ++ dev->irq = platform_get_irq(pdev, 0); ++ err = request_irq(dev->irq, ag71xx_interrupt, ++ IRQF_DISABLED, ++ dev->name, dev); ++ if (err) { ++ dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq); ++ goto err_unmap_mii_ctrl; ++ } ++ ++ dev->base_addr = (unsigned long)ag->mac_base; ++ dev->netdev_ops = &ag71xx_netdev_ops; ++ dev->ethtool_ops = &ag71xx_ethtool_ops; ++ ++ INIT_WORK(&ag->restart_work, ag71xx_restart_work_func); ++ ++ init_timer(&ag->oom_timer); ++ ag->oom_timer.data = (unsigned long) dev; ++ ag->oom_timer.function = ag71xx_oom_timer_handler; ++ ++ ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT; ++ ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT; ++ ++ ag->stop_desc = dma_alloc_coherent(NULL, ++ sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL); ++ ++ if (!ag->stop_desc) ++ goto err_free_irq; ++ ++ ag->stop_desc->data = 0; ++ ag->stop_desc->ctrl = 0; ++ ag->stop_desc->next = (u32) ag->stop_desc_dma; ++ ++ memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN); ++ ++ netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); ++ ++ err = register_netdev(dev); ++ if (err) { ++ dev_err(&pdev->dev, "unable to register net device\n"); ++ goto err_free_desc; ++ } ++ ++ printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n", ++ dev->name, dev->base_addr, dev->irq); ++ ++ ag71xx_dump_regs(ag); ++ ++ ag71xx_hw_init(ag); ++ ++ ag71xx_dump_regs(ag); ++ ++ err = ag71xx_phy_connect(ag); ++ if (err) ++ goto err_unregister_netdev; ++ ++ err = ag71xx_debugfs_init(ag); ++ if (err) ++ goto err_phy_disconnect; ++ ++ platform_set_drvdata(pdev, dev); ++ ++ return 0; ++ ++err_phy_disconnect: ++ ag71xx_phy_disconnect(ag); ++err_unregister_netdev: ++ unregister_netdev(dev); ++err_free_desc: ++ dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc, ++ ag->stop_desc_dma); ++err_free_irq: ++ free_irq(dev->irq, dev); ++err_unmap_mii_ctrl: ++ iounmap(ag->mii_ctrl); ++err_unmap_base: ++ iounmap(ag->mac_base); ++err_free_dev: ++ kfree(dev); ++err_out: ++ platform_set_drvdata(pdev, NULL); ++ return err; ++} ++ ++static int __devexit ag71xx_remove(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ ++ if (dev) { ++ struct ag71xx *ag = netdev_priv(dev); ++ ++ ag71xx_debugfs_exit(ag); ++ ag71xx_phy_disconnect(ag); ++ unregister_netdev(dev); ++ free_irq(dev->irq, dev); ++ iounmap(ag->mii_ctrl); ++ iounmap(ag->mac_base); ++ kfree(dev); ++ platform_set_drvdata(pdev, NULL); ++ } ++ ++ return 0; ++} ++ ++static struct platform_driver ag71xx_driver = { ++ .probe = ag71xx_probe, ++ .remove = __exit_p(ag71xx_remove), ++ .driver = { ++ .name = AG71XX_DRV_NAME, ++ } ++}; ++ ++static int __init ag71xx_module_init(void) ++{ ++ int ret; ++ ++ ret = ag71xx_debugfs_root_init(); ++ if (ret) ++ goto err_out; ++ ++ ret = ag71xx_mdio_driver_init(); ++ if (ret) ++ goto err_debugfs_exit; ++ ++ ret = platform_driver_register(&ag71xx_driver); ++ if (ret) ++ goto err_mdio_exit; ++ ++ return 0; ++ ++err_mdio_exit: ++ ag71xx_mdio_driver_exit(); ++err_debugfs_exit: ++ ag71xx_debugfs_root_exit(); ++err_out: ++ return ret; ++} ++ ++static void __exit ag71xx_module_exit(void) ++{ ++ platform_driver_unregister(&ag71xx_driver); ++ ag71xx_mdio_driver_exit(); ++ ag71xx_debugfs_root_exit(); ++} ++ ++module_init(ag71xx_module_init); ++module_exit(ag71xx_module_exit); ++ ++MODULE_VERSION(AG71XX_DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_AUTHOR("Imre Kaloz "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" AG71XX_DRV_NAME); +diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_mdio.c linux-2.6.39/drivers/net/ag71xx/ag71xx_mdio.c +--- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_mdio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/net/ag71xx/ag71xx_mdio.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,248 @@ ++/* ++ * Atheros AR71xx built-in ethernet mac driver ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Based on Atheros' AG7100 driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include "ag71xx.h" ++ ++#define AG71XX_MDIO_RETRY 1000 ++#define AG71XX_MDIO_DELAY 5 ++ ++static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg, ++ u32 value) ++{ ++ void __iomem *r; ++ ++ r = am->mdio_base + reg; ++ __raw_writel(value, r); ++ ++ /* flush write */ ++ (void) __raw_readl(r); ++} ++ ++static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg) ++{ ++ return __raw_readl(am->mdio_base + reg); ++} ++ ++static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am) ++{ ++ DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n", ++ am->mii_bus->name, ++ ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG), ++ ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD), ++ ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR)); ++ DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n", ++ am->mii_bus->name, ++ ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL), ++ ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS), ++ ag71xx_mdio_rr(am, AG71XX_REG_MII_IND)); ++} ++ ++int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg) ++{ ++ int ret; ++ int i; ++ ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, ++ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ); ++ ++ i = AG71XX_MDIO_RETRY; ++ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { ++ if (i-- == 0) { ++ printk(KERN_ERR "%s: mii_read timed out\n", ++ am->mii_bus->name); ++ ret = 0xffff; ++ goto out; ++ } ++ udelay(AG71XX_MDIO_DELAY); ++ } ++ ++ ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff; ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); ++ ++ DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret); ++ ++out: ++ return ret; ++} ++ ++void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val) ++{ ++ int i; ++ ++ DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val); ++ ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, ++ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val); ++ ++ i = AG71XX_MDIO_RETRY; ++ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { ++ if (i-- == 0) { ++ printk(KERN_ERR "%s: mii_write timed out\n", ++ am->mii_bus->name); ++ break; ++ } ++ udelay(AG71XX_MDIO_DELAY); ++ } ++} ++ ++static int ag71xx_mdio_reset(struct mii_bus *bus) ++{ ++ struct ag71xx_mdio *am = bus->priv; ++ u32 t; ++ ++ if (am->pdata->is_ar7240) ++ t = MII_CFG_CLK_DIV_6; ++ else ++ t = MII_CFG_CLK_DIV_28; ++ ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); ++ udelay(100); ++ ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t); ++ udelay(100); ++ ++ return 0; ++} ++ ++static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg) ++{ ++ struct ag71xx_mdio *am = bus->priv; ++ ++ if (am->pdata->is_ar7240) ++ return ar7240sw_phy_read(bus, addr, reg); ++ else ++ return ag71xx_mdio_mii_read(am, addr, reg); ++} ++ ++static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val) ++{ ++ struct ag71xx_mdio *am = bus->priv; ++ ++ if (am->pdata->is_ar7240) ++ ar7240sw_phy_write(bus, addr, reg, val); ++ else ++ ag71xx_mdio_mii_write(am, addr, reg, val); ++ return 0; ++} ++ ++static int __devinit ag71xx_mdio_probe(struct platform_device *pdev) ++{ ++ struct ag71xx_mdio_platform_data *pdata; ++ struct ag71xx_mdio *am; ++ struct resource *res; ++ int i; ++ int err; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata) { ++ dev_err(&pdev->dev, "no platform data specified\n"); ++ return -EINVAL; ++ } ++ ++ am = kzalloc(sizeof(*am), GFP_KERNEL); ++ if (!am) { ++ err = -ENOMEM; ++ goto err_out; ++ } ++ ++ am->pdata = pdata; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "no iomem resource found\n"); ++ err = -ENXIO; ++ goto err_out; ++ } ++ ++ am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1); ++ if (!am->mdio_base) { ++ dev_err(&pdev->dev, "unable to ioremap registers\n"); ++ err = -ENOMEM; ++ goto err_free_mdio; ++ } ++ ++ am->mii_bus = mdiobus_alloc(); ++ if (am->mii_bus == NULL) { ++ err = -ENOMEM; ++ goto err_iounmap; ++ } ++ ++ am->mii_bus->name = "ag71xx_mdio"; ++ am->mii_bus->read = ag71xx_mdio_read; ++ am->mii_bus->write = ag71xx_mdio_write; ++ am->mii_bus->reset = ag71xx_mdio_reset; ++ am->mii_bus->irq = am->mii_irq; ++ am->mii_bus->priv = am; ++ am->mii_bus->parent = &pdev->dev; ++ snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev)); ++ am->mii_bus->phy_mask = pdata->phy_mask; ++ ++ for (i = 0; i < PHY_MAX_ADDR; i++) ++ am->mii_irq[i] = PHY_POLL; ++ ++ ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0); ++ ++ err = mdiobus_register(am->mii_bus); ++ if (err) ++ goto err_free_bus; ++ ++ ag71xx_mdio_dump_regs(am); ++ ++ platform_set_drvdata(pdev, am); ++ return 0; ++ ++err_free_bus: ++ mdiobus_free(am->mii_bus); ++err_iounmap: ++ iounmap(am->mdio_base); ++err_free_mdio: ++ kfree(am); ++err_out: ++ return err; ++} ++ ++static int __devexit ag71xx_mdio_remove(struct platform_device *pdev) ++{ ++ struct ag71xx_mdio *am = platform_get_drvdata(pdev); ++ ++ if (am) { ++ mdiobus_unregister(am->mii_bus); ++ mdiobus_free(am->mii_bus); ++ iounmap(am->mdio_base); ++ kfree(am); ++ platform_set_drvdata(pdev, NULL); ++ } ++ ++ return 0; ++} ++ ++static struct platform_driver ag71xx_mdio_driver = { ++ .probe = ag71xx_mdio_probe, ++ .remove = __exit_p(ag71xx_mdio_remove), ++ .driver = { ++ .name = "ag71xx-mdio", ++ } ++}; ++ ++int __init ag71xx_mdio_driver_init(void) ++{ ++ return platform_driver_register(&ag71xx_mdio_driver); ++} ++ ++void ag71xx_mdio_driver_exit(void) ++{ ++ platform_driver_unregister(&ag71xx_mdio_driver); ++} +diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_phy.c linux-2.6.39/drivers/net/ag71xx/ag71xx_phy.c +--- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_phy.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/net/ag71xx/ag71xx_phy.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,228 @@ ++/* ++ * Atheros AR71xx built-in ethernet mac driver ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Based on Atheros' AG7100 driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include "ag71xx.h" ++ ++static void ag71xx_phy_link_adjust(struct net_device *dev) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ struct phy_device *phydev = ag->phy_dev; ++ unsigned long flags; ++ int status_change = 0; ++ ++ spin_lock_irqsave(&ag->lock, flags); ++ ++ if (phydev->link) { ++ if (ag->duplex != phydev->duplex ++ || ag->speed != phydev->speed) { ++ status_change = 1; ++ } ++ } ++ ++ if (phydev->link != ag->link) ++ status_change = 1; ++ ++ ag->link = phydev->link; ++ ag->duplex = phydev->duplex; ++ ag->speed = phydev->speed; ++ ++ if (status_change) ++ ag71xx_link_adjust(ag); ++ ++ spin_unlock_irqrestore(&ag->lock, flags); ++} ++ ++void ag71xx_phy_start(struct ag71xx *ag) ++{ ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ ++ if (ag->phy_dev) { ++ phy_start(ag->phy_dev); ++ } else if (pdata->has_ar7240_switch) { ++ ag71xx_ar7240_start(ag); ++ } else { ++ ag->link = 1; ++ ag71xx_link_adjust(ag); ++ } ++} ++ ++void ag71xx_phy_stop(struct ag71xx *ag) ++{ ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ ++ if (ag->phy_dev) { ++ phy_stop(ag->phy_dev); ++ } else { ++ if (pdata->has_ar7240_switch) ++ ag71xx_ar7240_stop(ag); ++ ag->link = 0; ++ ag71xx_link_adjust(ag); ++ } ++} ++ ++static int ag71xx_phy_connect_fixed(struct ag71xx *ag) ++{ ++ struct net_device *dev = ag->dev; ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ int ret = 0; ++ ++ /* use fixed settings */ ++ switch (pdata->speed) { ++ case SPEED_10: ++ case SPEED_100: ++ case SPEED_1000: ++ break; ++ default: ++ printk(KERN_ERR "%s: invalid speed specified\n", dev->name); ++ ret = -EINVAL; ++ break; ++ } ++ ++ printk(KERN_DEBUG "%s: using fixed link parameters\n", dev->name); ++ ++ ag->duplex = pdata->duplex; ++ ag->speed = pdata->speed; ++ ++ return ret; ++} ++ ++static int ag71xx_phy_connect_multi(struct ag71xx *ag) ++{ ++ struct net_device *dev = ag->dev; ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ struct phy_device *phydev = NULL; ++ int phy_addr; ++ int ret = 0; ++ ++ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { ++ if (!(pdata->phy_mask & (1 << phy_addr))) ++ continue; ++ ++ if (ag->mii_bus->phy_map[phy_addr] == NULL) ++ continue; ++ ++ DBG("%s: PHY found at %s, uid=%08x\n", ++ dev->name, ++ dev_name(&ag->mii_bus->phy_map[phy_addr]->dev), ++ ag->mii_bus->phy_map[phy_addr]->phy_id); ++ ++ if (phydev == NULL) ++ phydev = ag->mii_bus->phy_map[phy_addr]; ++ } ++ ++ if (!phydev) { ++ printk(KERN_ERR "%s: no PHY found with phy_mask=%08x\n", ++ dev->name, pdata->phy_mask); ++ return -ENODEV; ++ } ++ ++ ag->phy_dev = phy_connect(dev, dev_name(&phydev->dev), ++ &ag71xx_phy_link_adjust, 0, ++ pdata->phy_if_mode); ++ ++ if (IS_ERR(ag->phy_dev)) { ++ printk(KERN_ERR "%s: could not connect to PHY at %s\n", ++ dev->name, dev_name(&phydev->dev)); ++ return PTR_ERR(ag->phy_dev); ++ } ++ ++ /* mask with MAC supported features */ ++ if (pdata->has_gbit) ++ phydev->supported &= PHY_GBIT_FEATURES; ++ else ++ phydev->supported &= PHY_BASIC_FEATURES; ++ ++ phydev->advertising = phydev->supported; ++ ++ printk(KERN_DEBUG "%s: connected to PHY at %s [uid=%08x, driver=%s]\n", ++ dev->name, dev_name(&phydev->dev), ++ phydev->phy_id, phydev->drv->name); ++ ++ ag->link = 0; ++ ag->speed = 0; ++ ag->duplex = -1; ++ ++ return ret; ++} ++ ++static int dev_is_class(struct device *dev, void *class) ++{ ++ if (dev->class != NULL && !strcmp(dev->class->name, class)) ++ return 1; ++ ++ return 0; ++} ++ ++static struct device *dev_find_class(struct device *parent, char *class) ++{ ++ if (dev_is_class(parent, class)) { ++ get_device(parent); ++ return parent; ++ } ++ ++ return device_find_child(parent, class, dev_is_class); ++} ++ ++static struct mii_bus *dev_to_mii_bus(struct device *dev) ++{ ++ struct device *d; ++ ++ d = dev_find_class(dev, "mdio_bus"); ++ if (d != NULL) { ++ struct mii_bus *bus; ++ ++ bus = to_mii_bus(d); ++ put_device(d); ++ ++ return bus; ++ } ++ ++ return NULL; ++} ++ ++int __devinit ag71xx_phy_connect(struct ag71xx *ag) ++{ ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ ++ ag->mii_bus = dev_to_mii_bus(pdata->mii_bus_dev); ++ if (ag->mii_bus == NULL) { ++ printk(KERN_ERR "%s: unable to find MII bus on device '%s'\n", ++ ag->dev->name, dev_name(pdata->mii_bus_dev)); ++ return -ENODEV; ++ } ++ ++ /* Reset the mdio bus explicitly */ ++ if (ag->mii_bus->reset) { ++ mutex_lock(&ag->mii_bus->mdio_lock); ++ ag->mii_bus->reset(ag->mii_bus); ++ mutex_unlock(&ag->mii_bus->mdio_lock); ++ } ++ ++ if (pdata->has_ar7240_switch) ++ return ag71xx_ar7240_init(ag); ++ ++ if (pdata->phy_mask) ++ return ag71xx_phy_connect_multi(ag); ++ ++ return ag71xx_phy_connect_fixed(ag); ++} ++ ++void ag71xx_phy_disconnect(struct ag71xx *ag) ++{ ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ ++ if (pdata->has_ar7240_switch) ++ ag71xx_ar7240_cleanup(ag); ++ else if (ag->phy_dev) ++ phy_disconnect(ag->phy_dev); ++} +diff -Nur linux-2.6.39.orig/drivers/net/phy/Kconfig linux-2.6.39/drivers/net/phy/Kconfig +--- linux-2.6.39.orig/drivers/net/phy/Kconfig 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/net/phy/Kconfig 2011-08-24 18:17:24.000000000 +0200 +@@ -13,6 +13,12 @@ + + if PHYLIB + ++config SWCONFIG ++ tristate "Switch configuration API" ++ ---help--- ++ Switch configuration API using netlink. This allows ++ you to configure the VLAN features of certain switches. ++ + comment "MII PHY device drivers" + + config MARVELL_PHY +diff -Nur linux-2.6.39.orig/drivers/net/phy/Makefile linux-2.6.39/drivers/net/phy/Makefile +--- linux-2.6.39.orig/drivers/net/phy/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/net/phy/Makefile 2011-08-24 18:17:24.000000000 +0200 +@@ -3,6 +3,7 @@ + libphy-objs := phy.o phy_device.o mdio_bus.o + + obj-$(CONFIG_PHYLIB) += libphy.o ++obj-$(CONFIG_SWCONFIG) += swconfig.o + obj-$(CONFIG_MARVELL_PHY) += marvell.o + obj-$(CONFIG_DAVICOM_PHY) += davicom.o + obj-$(CONFIG_CICADA_PHY) += cicada.o +diff -Nur linux-2.6.39.orig/drivers/net/phy/micrel.c linux-2.6.39/drivers/net/phy/micrel.c +--- linux-2.6.39.orig/drivers/net/phy/micrel.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/net/phy/micrel.c 2011-08-24 18:17:24.000000000 +0200 +@@ -1,251 +1,82 @@ + /* +- * drivers/net/phy/micrel.c ++ * Driver for Micrel/Kendin PHYs + * +- * Driver for Micrel PHYs ++ * Copyright (c) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz + * +- * Author: David J. Choi ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. + * +- * Copyright (c) 2010 Micrel, Inc. +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License as published by the +- * Free Software Foundation; either version 2 of the License, or (at your +- * option) any later version. +- * +- * Support : ksz9021 1000/100/10 phy from Micrel +- * ks8001, ks8737, ks8721, ks8041, ks8051 100/10 phy + */ + +-#include +-#include ++#include ++#include + #include +-#include + +-/* general Interrupt control/status reg in vendor specific block. */ +-#define MII_KSZPHY_INTCS 0x1B +-#define KSZPHY_INTCS_JABBER (1 << 15) +-#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14) +-#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13) +-#define KSZPHY_INTCS_PARELLEL (1 << 12) +-#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11) +-#define KSZPHY_INTCS_LINK_DOWN (1 << 10) +-#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9) +-#define KSZPHY_INTCS_LINK_UP (1 << 8) +-#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ +- KSZPHY_INTCS_LINK_DOWN) +- +-/* general PHY control reg in vendor specific block. */ +-#define MII_KSZPHY_CTRL 0x1F +-/* bitmap of PHY register to set interrupt mode */ +-#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9) +-#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14) +-#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14) +-#define KSZ8051_RMII_50MHZ_CLK (1 << 7) ++#define KSZ_REG_INT_CTRL 0x1b + +-static int kszphy_ack_interrupt(struct phy_device *phydev) +-{ +- /* bit[7..0] int status, which is a read and clear register. */ +- int rc; ++#define KSZ_INT_LU_EN (1 << 8) /* enable Link Up interrupt */ ++#define KSZ_INT_RF_EN (1 << 9) /* enable Remote Fault interrupt */ ++#define KSZ_INT_LD_EN (1 << 10) /* enable Link Down interrupt */ + +- rc = phy_read(phydev, MII_KSZPHY_INTCS); +- +- return (rc < 0) ? rc : 0; +-} ++#define KSZ_INT_INIT (KSZ_INT_LU_EN | KSZ_INT_LD_EN) + +-static int kszphy_set_interrupt(struct phy_device *phydev) ++static int ksz8041_ack_interrupt(struct phy_device *phydev) + { +- int temp; +- temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ? +- KSZPHY_INTCS_ALL : 0; +- return phy_write(phydev, MII_KSZPHY_INTCS, temp); +-} ++ int err; + +-static int kszphy_config_intr(struct phy_device *phydev) +-{ +- int temp, rc; ++ err = phy_read(phydev, KSZ_REG_INT_CTRL); + +- /* set the interrupt pin active low */ +- temp = phy_read(phydev, MII_KSZPHY_CTRL); +- temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH; +- phy_write(phydev, MII_KSZPHY_CTRL, temp); +- rc = kszphy_set_interrupt(phydev); +- return rc < 0 ? rc : 0; ++ return (err < 0) ? err : 0; + } + +-static int ksz9021_config_intr(struct phy_device *phydev) ++static int ksz8041_config_intr(struct phy_device *phydev) + { +- int temp, rc; ++ int err; + +- /* set the interrupt pin active low */ +- temp = phy_read(phydev, MII_KSZPHY_CTRL); +- temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH; +- phy_write(phydev, MII_KSZPHY_CTRL, temp); +- rc = kszphy_set_interrupt(phydev); +- return rc < 0 ? rc : 0; +-} +- +-static int ks8737_config_intr(struct phy_device *phydev) +-{ +- int temp, rc; ++ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) ++ err = phy_write(phydev, KSZ_REG_INT_CTRL, ++ KSZ_INT_INIT); ++ else ++ err = phy_write(phydev, KSZ_REG_INT_CTRL, 0); + +- /* set the interrupt pin active low */ +- temp = phy_read(phydev, MII_KSZPHY_CTRL); +- temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH; +- phy_write(phydev, MII_KSZPHY_CTRL, temp); +- rc = kszphy_set_interrupt(phydev); +- return rc < 0 ? rc : 0; ++ return err; + } + +-static int kszphy_config_init(struct phy_device *phydev) +-{ +- return 0; +-} +- +-static int ks8051_config_init(struct phy_device *phydev) +-{ +- int regval; +- +- if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { +- regval = phy_read(phydev, MII_KSZPHY_CTRL); +- regval |= KSZ8051_RMII_50MHZ_CLK; +- phy_write(phydev, MII_KSZPHY_CTRL, regval); +- } +- +- return 0; +-} +- +-static struct phy_driver ks8737_driver = { +- .phy_id = PHY_ID_KS8737, +- .phy_id_mask = 0x00fffff0, +- .name = "Micrel KS8737", +- .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), +- .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, +- .config_init = kszphy_config_init, ++static struct phy_driver ksz8041_phy_driver = { ++ .phy_id = 0x00221512, ++ .name = "Micrel KSZ8041", ++ .phy_id_mask = 0x001fffff, ++ .features = PHY_BASIC_FEATURES, ++ .flags = PHY_HAS_INTERRUPT, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, +- .ack_interrupt = kszphy_ack_interrupt, +- .config_intr = ks8737_config_intr, +- .driver = { .owner = THIS_MODULE,}, ++ .ack_interrupt = ksz8041_ack_interrupt, ++ .config_intr = ksz8041_config_intr, ++ .driver = { ++ .owner = THIS_MODULE, ++ }, + }; + +-static struct phy_driver ks8041_driver = { +- .phy_id = PHY_ID_KS8041, +- .phy_id_mask = 0x00fffff0, +- .name = "Micrel KS8041", +- .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause +- | SUPPORTED_Asym_Pause), +- .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, +- .config_init = kszphy_config_init, +- .config_aneg = genphy_config_aneg, +- .read_status = genphy_read_status, +- .ack_interrupt = kszphy_ack_interrupt, +- .config_intr = kszphy_config_intr, +- .driver = { .owner = THIS_MODULE,}, +-}; +- +-static struct phy_driver ks8051_driver = { +- .phy_id = PHY_ID_KS8051, +- .phy_id_mask = 0x00fffff0, +- .name = "Micrel KS8051", +- .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause +- | SUPPORTED_Asym_Pause), +- .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, +- .config_init = ks8051_config_init, +- .config_aneg = genphy_config_aneg, +- .read_status = genphy_read_status, +- .ack_interrupt = kszphy_ack_interrupt, +- .config_intr = kszphy_config_intr, +- .driver = { .owner = THIS_MODULE,}, +-}; +- +-static struct phy_driver ks8001_driver = { +- .phy_id = PHY_ID_KS8001, +- .name = "Micrel KS8001 or KS8721", +- .phy_id_mask = 0x00fffff0, +- .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), +- .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, +- .config_init = kszphy_config_init, +- .config_aneg = genphy_config_aneg, +- .read_status = genphy_read_status, +- .ack_interrupt = kszphy_ack_interrupt, +- .config_intr = kszphy_config_intr, +- .driver = { .owner = THIS_MODULE,}, +-}; +- +-static struct phy_driver ksz9021_driver = { +- .phy_id = PHY_ID_KSZ9021, +- .phy_id_mask = 0x000fff10, +- .name = "Micrel KSZ9021 Gigabit PHY", +- .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause +- | SUPPORTED_Asym_Pause), +- .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, +- .config_init = kszphy_config_init, +- .config_aneg = genphy_config_aneg, +- .read_status = genphy_read_status, +- .ack_interrupt = kszphy_ack_interrupt, +- .config_intr = ksz9021_config_intr, +- .driver = { .owner = THIS_MODULE, }, +-}; +- +-static int __init ksphy_init(void) ++static int __init micrel_phy_init(void) + { +- int ret; +- +- ret = phy_driver_register(&ks8001_driver); +- if (ret) +- goto err1; +- +- ret = phy_driver_register(&ksz9021_driver); +- if (ret) +- goto err2; +- +- ret = phy_driver_register(&ks8737_driver); +- if (ret) +- goto err3; +- ret = phy_driver_register(&ks8041_driver); +- if (ret) +- goto err4; +- ret = phy_driver_register(&ks8051_driver); +- if (ret) +- goto err5; +- +- return 0; +- +-err5: +- phy_driver_unregister(&ks8041_driver); +-err4: +- phy_driver_unregister(&ks8737_driver); +-err3: +- phy_driver_unregister(&ksz9021_driver); +-err2: +- phy_driver_unregister(&ks8001_driver); +-err1: +- return ret; ++ return phy_driver_register(&ksz8041_phy_driver); + } + +-static void __exit ksphy_exit(void) ++static void __exit micrel_phy_exit(void) + { +- phy_driver_unregister(&ks8001_driver); +- phy_driver_unregister(&ks8737_driver); +- phy_driver_unregister(&ksz9021_driver); +- phy_driver_unregister(&ks8041_driver); +- phy_driver_unregister(&ks8051_driver); ++ phy_driver_unregister(&ksz8041_phy_driver); + } + +-module_init(ksphy_init); +-module_exit(ksphy_exit); +- +-MODULE_DESCRIPTION("Micrel PHY driver"); +-MODULE_AUTHOR("David J. Choi"); +-MODULE_LICENSE("GPL"); +- +-static struct mdio_device_id __maybe_unused micrel_tbl[] = { +- { PHY_ID_KSZ9021, 0x000fff10 }, +- { PHY_ID_KS8001, 0x00fffff0 }, +- { PHY_ID_KS8737, 0x00fffff0 }, +- { PHY_ID_KS8041, 0x00fffff0 }, +- { PHY_ID_KS8051, 0x00fffff0 }, +- { } +-}; ++#ifdef MODULE ++module_init(micrel_phy_init); ++module_exit(micrel_phy_exit); ++#else ++subsys_initcall(micrel_phy_init); ++#endif + +-MODULE_DEVICE_TABLE(mdio, micrel_tbl); ++MODULE_DESCRIPTION("Micrel/Kendin PHY driver"); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_AUTHOR("Imre Kaloz "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.39.orig/drivers/net/phy/phy.c linux-2.6.39/drivers/net/phy/phy.c +--- linux-2.6.39.orig/drivers/net/phy/phy.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/net/phy/phy.c 2011-08-24 18:17:24.000000000 +0200 +@@ -297,6 +297,50 @@ + } + EXPORT_SYMBOL(phy_ethtool_gset); + ++int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr) ++{ ++ u32 cmd; ++ int tmp; ++ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ ++ if (get_user(cmd, (u32 *) useraddr)) ++ return -EFAULT; ++ ++ switch (cmd) { ++ case ETHTOOL_GSET: ++ phy_ethtool_gset(phydev, &ecmd); ++ if (copy_to_user(useraddr, &ecmd, sizeof(ecmd))) ++ return -EFAULT; ++ return 0; ++ ++ case ETHTOOL_SSET: ++ if (copy_from_user(&ecmd, useraddr, sizeof(ecmd))) ++ return -EFAULT; ++ return phy_ethtool_sset(phydev, &ecmd); ++ ++ case ETHTOOL_NWAY_RST: ++ /* if autoneg is off, it's an error */ ++ tmp = phy_read(phydev, MII_BMCR); ++ if (tmp & BMCR_ANENABLE) { ++ tmp |= (BMCR_ANRESTART); ++ phy_write(phydev, MII_BMCR, tmp); ++ return 0; ++ } ++ return -EINVAL; ++ ++ case ETHTOOL_GLINK: ++ edata.data = (phy_read(phydev, ++ MII_BMSR) & BMSR_LSTATUS) ? 1 : 0; ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++ } ++ ++ return -EOPNOTSUPP; ++} ++EXPORT_SYMBOL(phy_ethtool_ioctl); ++ + /** + * phy_mii_ioctl - generic PHY MII ioctl interface + * @phydev: the phy_device struct +@@ -472,7 +516,7 @@ + int idx; + + idx = phy_find_setting(phydev->speed, phydev->duplex); +- ++ + idx++; + + idx = phy_find_valid(idx, phydev->supported); +diff -Nur linux-2.6.39.orig/drivers/net/phy/phy_device.c linux-2.6.39/drivers/net/phy/phy_device.c +--- linux-2.6.39.orig/drivers/net/phy/phy_device.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/net/phy/phy_device.c 2011-08-24 18:17:24.000000000 +0200 +@@ -149,6 +149,18 @@ + } + EXPORT_SYMBOL(phy_scan_fixups); + ++static int generic_receive_skb(struct sk_buff *skb) ++{ ++ skb->protocol = eth_type_trans(skb, skb->dev); ++ return netif_receive_skb(skb); ++} ++ ++static int generic_rx(struct sk_buff *skb) ++{ ++ skb->protocol = eth_type_trans(skb, skb->dev); ++ return netif_rx(skb); ++} ++ + static struct phy_device* phy_device_create(struct mii_bus *bus, + int addr, int phy_id) + { +@@ -180,6 +192,8 @@ + dev_set_name(&dev->dev, PHY_ID_FMT, bus->id, addr); + + dev->state = PHY_DOWN; ++ dev->netif_receive_skb = &generic_receive_skb; ++ dev->netif_rx = &generic_rx; + + mutex_init(&dev->lock); + INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine); +diff -Nur linux-2.6.39.orig/drivers/net/phy/swconfig.c linux-2.6.39/drivers/net/phy/swconfig.c +--- linux-2.6.39.orig/drivers/net/phy/swconfig.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/net/phy/swconfig.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,954 @@ ++/* ++ * swconfig.c: Switch configuration API ++ * ++ * Copyright (C) 2008 Felix Fietkau ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#define DEBUG 1 ++#ifdef DEBUG ++#define DPRINTF(format, ...) printk("%s: " format, __func__, ##__VA_ARGS__) ++#else ++#define DPRINTF(...) do {} while(0) ++#endif ++ ++#define SWCONFIG_DEVNAME "switch%d" ++ ++MODULE_AUTHOR("Felix Fietkau "); ++MODULE_LICENSE("GPL"); ++ ++static int swdev_id = 0; ++static struct list_head swdevs; ++static DEFINE_SPINLOCK(swdevs_lock); ++struct swconfig_callback; ++ ++struct swconfig_callback ++{ ++ struct sk_buff *msg; ++ struct genlmsghdr *hdr; ++ struct genl_info *info; ++ int cmd; ++ ++ /* callback for filling in the message data */ ++ int (*fill)(struct swconfig_callback *cb, void *arg); ++ ++ /* callback for closing the message before sending it */ ++ int (*close)(struct swconfig_callback *cb, void *arg); ++ ++ struct nlattr *nest[4]; ++ int args[4]; ++}; ++ ++/* defaults */ ++ ++static int ++swconfig_get_vlan_ports(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ int ret; ++ if (val->port_vlan >= dev->vlans) ++ return -EINVAL; ++ ++ if (!dev->ops->get_vlan_ports) ++ return -EOPNOTSUPP; ++ ++ ret = dev->ops->get_vlan_ports(dev, val); ++ return ret; ++} ++ ++static int ++swconfig_set_vlan_ports(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ struct switch_port *ports = val->value.ports; ++ const struct switch_dev_ops *ops = dev->ops; ++ int i; ++ ++ if (val->port_vlan >= dev->vlans) ++ return -EINVAL; ++ ++ /* validate ports */ ++ if (val->len > dev->ports) ++ return -EINVAL; ++ ++ if (!ops->set_vlan_ports) ++ return -EOPNOTSUPP; ++ ++ for (i = 0; i < val->len; i++) { ++ if (ports[i].id >= dev->ports) ++ return -EINVAL; ++ ++ if (ops->set_port_pvid && ++ !(ports[i].flags & (1 << SWITCH_PORT_FLAG_TAGGED))) ++ ops->set_port_pvid(dev, ports[i].id, val->port_vlan); ++ } ++ ++ return ops->set_vlan_ports(dev, val); ++} ++ ++static int ++swconfig_set_pvid(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ if (val->port_vlan >= dev->ports) ++ return -EINVAL; ++ ++ if (!dev->ops->set_port_pvid) ++ return -EOPNOTSUPP; ++ ++ return dev->ops->set_port_pvid(dev, val->port_vlan, val->value.i); ++} ++ ++static int ++swconfig_get_pvid(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ if (val->port_vlan >= dev->ports) ++ return -EINVAL; ++ ++ if (!dev->ops->get_port_pvid) ++ return -EOPNOTSUPP; ++ ++ return dev->ops->get_port_pvid(dev, val->port_vlan, &val->value.i); ++} ++ ++static int ++swconfig_apply_config(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ /* don't complain if not supported by the switch driver */ ++ if (!dev->ops->apply_config) ++ return 0; ++ ++ return dev->ops->apply_config(dev); ++} ++ ++static int ++swconfig_reset_switch(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ /* don't complain if not supported by the switch driver */ ++ if (!dev->ops->reset_switch) ++ return 0; ++ ++ return dev->ops->reset_switch(dev); ++} ++ ++enum global_defaults { ++ GLOBAL_APPLY, ++ GLOBAL_RESET, ++}; ++ ++enum vlan_defaults { ++ VLAN_PORTS, ++}; ++ ++enum port_defaults { ++ PORT_PVID, ++}; ++ ++static struct switch_attr default_global[] = { ++ [GLOBAL_APPLY] = { ++ .type = SWITCH_TYPE_NOVAL, ++ .name = "apply", ++ .description = "Activate changes in the hardware", ++ .set = swconfig_apply_config, ++ }, ++ [GLOBAL_RESET] = { ++ .type = SWITCH_TYPE_NOVAL, ++ .name = "reset", ++ .description = "Reset the switch", ++ .set = swconfig_reset_switch, ++ } ++}; ++ ++static struct switch_attr default_port[] = { ++ [PORT_PVID] = { ++ .type = SWITCH_TYPE_INT, ++ .name = "pvid", ++ .description = "Primary VLAN ID", ++ .set = swconfig_set_pvid, ++ .get = swconfig_get_pvid, ++ } ++}; ++ ++static struct switch_attr default_vlan[] = { ++ [VLAN_PORTS] = { ++ .type = SWITCH_TYPE_PORTS, ++ .name = "ports", ++ .description = "VLAN port mapping", ++ .set = swconfig_set_vlan_ports, ++ .get = swconfig_get_vlan_ports, ++ }, ++}; ++ ++ ++static void swconfig_defaults_init(struct switch_dev *dev) ++{ ++ const struct switch_dev_ops *ops = dev->ops; ++ ++ dev->def_global = 0; ++ dev->def_vlan = 0; ++ dev->def_port = 0; ++ ++ if (ops->get_vlan_ports || ops->set_vlan_ports) ++ set_bit(VLAN_PORTS, &dev->def_vlan); ++ ++ if (ops->get_port_pvid || ops->set_port_pvid) ++ set_bit(PORT_PVID, &dev->def_port); ++ ++ /* always present, can be no-op */ ++ set_bit(GLOBAL_APPLY, &dev->def_global); ++ set_bit(GLOBAL_RESET, &dev->def_global); ++} ++ ++ ++static struct genl_family switch_fam = { ++ .id = GENL_ID_GENERATE, ++ .name = "switch", ++ .hdrsize = 0, ++ .version = 1, ++ .maxattr = SWITCH_ATTR_MAX, ++}; ++ ++static const struct nla_policy switch_policy[SWITCH_ATTR_MAX+1] = { ++ [SWITCH_ATTR_ID] = { .type = NLA_U32 }, ++ [SWITCH_ATTR_OP_ID] = { .type = NLA_U32 }, ++ [SWITCH_ATTR_OP_PORT] = { .type = NLA_U32 }, ++ [SWITCH_ATTR_OP_VLAN] = { .type = NLA_U32 }, ++ [SWITCH_ATTR_OP_VALUE_INT] = { .type = NLA_U32 }, ++ [SWITCH_ATTR_OP_VALUE_STR] = { .type = NLA_NUL_STRING }, ++ [SWITCH_ATTR_OP_VALUE_PORTS] = { .type = NLA_NESTED }, ++ [SWITCH_ATTR_TYPE] = { .type = NLA_U32 }, ++}; ++ ++static const struct nla_policy port_policy[SWITCH_PORT_ATTR_MAX+1] = { ++ [SWITCH_PORT_ID] = { .type = NLA_U32 }, ++ [SWITCH_PORT_FLAG_TAGGED] = { .type = NLA_FLAG }, ++}; ++ ++static inline void ++swconfig_lock(void) ++{ ++ spin_lock(&swdevs_lock); ++} ++ ++static inline void ++swconfig_unlock(void) ++{ ++ spin_unlock(&swdevs_lock); ++} ++ ++static struct switch_dev * ++swconfig_get_dev(struct genl_info *info) ++{ ++ struct switch_dev *dev = NULL; ++ struct switch_dev *p; ++ int id; ++ ++ if (!info->attrs[SWITCH_ATTR_ID]) ++ goto done; ++ ++ id = nla_get_u32(info->attrs[SWITCH_ATTR_ID]); ++ swconfig_lock(); ++ list_for_each_entry(p, &swdevs, dev_list) { ++ if (id != p->id) ++ continue; ++ ++ dev = p; ++ break; ++ } ++ if (dev) ++ spin_lock(&dev->lock); ++ else ++ DPRINTF("device %d not found\n", id); ++ swconfig_unlock(); ++done: ++ return dev; ++} ++ ++static inline void ++swconfig_put_dev(struct switch_dev *dev) ++{ ++ spin_unlock(&dev->lock); ++} ++ ++static int ++swconfig_dump_attr(struct swconfig_callback *cb, void *arg) ++{ ++ struct switch_attr *op = arg; ++ struct genl_info *info = cb->info; ++ struct sk_buff *msg = cb->msg; ++ int id = cb->args[0]; ++ void *hdr; ++ ++ hdr = genlmsg_put(msg, info->snd_pid, info->snd_seq, &switch_fam, ++ NLM_F_MULTI, SWITCH_CMD_NEW_ATTR); ++ if (IS_ERR(hdr)) ++ return -1; ++ ++ NLA_PUT_U32(msg, SWITCH_ATTR_OP_ID, id); ++ NLA_PUT_U32(msg, SWITCH_ATTR_OP_TYPE, op->type); ++ NLA_PUT_STRING(msg, SWITCH_ATTR_OP_NAME, op->name); ++ if (op->description) ++ NLA_PUT_STRING(msg, SWITCH_ATTR_OP_DESCRIPTION, ++ op->description); ++ ++ return genlmsg_end(msg, hdr); ++nla_put_failure: ++ genlmsg_cancel(msg, hdr); ++ return -EMSGSIZE; ++} ++ ++/* spread multipart messages across multiple message buffers */ ++static int ++swconfig_send_multipart(struct swconfig_callback *cb, void *arg) ++{ ++ struct genl_info *info = cb->info; ++ int restart = 0; ++ int err; ++ ++ do { ++ if (!cb->msg) { ++ cb->msg = nlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); ++ if (cb->msg == NULL) ++ goto error; ++ } ++ ++ if (!(cb->fill(cb, arg) < 0)) ++ break; ++ ++ /* fill failed, check if this was already the second attempt */ ++ if (restart) ++ goto error; ++ ++ /* try again in a new message, send the current one */ ++ restart = 1; ++ if (cb->close) { ++ if (cb->close(cb, arg) < 0) ++ goto error; ++ } ++ err = genlmsg_reply(cb->msg, info); ++ cb->msg = NULL; ++ if (err < 0) ++ goto error; ++ ++ } while (restart); ++ ++ return 0; ++ ++error: ++ if (cb->msg) ++ nlmsg_free(cb->msg); ++ return -1; ++} ++ ++static int ++swconfig_list_attrs(struct sk_buff *skb, struct genl_info *info) ++{ ++ struct genlmsghdr *hdr = nlmsg_data(info->nlhdr); ++ const struct switch_attrlist *alist; ++ struct switch_dev *dev; ++ struct swconfig_callback cb; ++ int err = -EINVAL; ++ int i; ++ ++ /* defaults */ ++ struct switch_attr *def_list; ++ unsigned long *def_active; ++ int n_def; ++ ++ dev = swconfig_get_dev(info); ++ if (!dev) ++ return -EINVAL; ++ ++ switch(hdr->cmd) { ++ case SWITCH_CMD_LIST_GLOBAL: ++ alist = &dev->ops->attr_global; ++ def_list = default_global; ++ def_active = &dev->def_global; ++ n_def = ARRAY_SIZE(default_global); ++ break; ++ case SWITCH_CMD_LIST_VLAN: ++ alist = &dev->ops->attr_vlan; ++ def_list = default_vlan; ++ def_active = &dev->def_vlan; ++ n_def = ARRAY_SIZE(default_vlan); ++ break; ++ case SWITCH_CMD_LIST_PORT: ++ alist = &dev->ops->attr_port; ++ def_list = default_port; ++ def_active = &dev->def_port; ++ n_def = ARRAY_SIZE(default_port); ++ break; ++ default: ++ WARN_ON(1); ++ goto out; ++ } ++ ++ memset(&cb, 0, sizeof(cb)); ++ cb.info = info; ++ cb.fill = swconfig_dump_attr; ++ for (i = 0; i < alist->n_attr; i++) { ++ if (alist->attr[i].disabled) ++ continue; ++ cb.args[0] = i; ++ err = swconfig_send_multipart(&cb, (void *) &alist->attr[i]); ++ if (err < 0) ++ goto error; ++ } ++ ++ /* defaults */ ++ for (i = 0; i < n_def; i++) { ++ if (!test_bit(i, def_active)) ++ continue; ++ cb.args[0] = SWITCH_ATTR_DEFAULTS_OFFSET + i; ++ err = swconfig_send_multipart(&cb, (void *) &def_list[i]); ++ if (err < 0) ++ goto error; ++ } ++ swconfig_put_dev(dev); ++ ++ if (!cb.msg) ++ return 0; ++ ++ return genlmsg_reply(cb.msg, info); ++ ++error: ++ if (cb.msg) ++ nlmsg_free(cb.msg); ++out: ++ swconfig_put_dev(dev); ++ return err; ++} ++ ++static const struct switch_attr * ++swconfig_lookup_attr(struct switch_dev *dev, struct genl_info *info, ++ struct switch_val *val) ++{ ++ struct genlmsghdr *hdr = nlmsg_data(info->nlhdr); ++ const struct switch_attrlist *alist; ++ const struct switch_attr *attr = NULL; ++ int attr_id; ++ ++ /* defaults */ ++ struct switch_attr *def_list; ++ unsigned long *def_active; ++ int n_def; ++ ++ if (!info->attrs[SWITCH_ATTR_OP_ID]) ++ goto done; ++ ++ switch(hdr->cmd) { ++ case SWITCH_CMD_SET_GLOBAL: ++ case SWITCH_CMD_GET_GLOBAL: ++ alist = &dev->ops->attr_global; ++ def_list = default_global; ++ def_active = &dev->def_global; ++ n_def = ARRAY_SIZE(default_global); ++ break; ++ case SWITCH_CMD_SET_VLAN: ++ case SWITCH_CMD_GET_VLAN: ++ alist = &dev->ops->attr_vlan; ++ def_list = default_vlan; ++ def_active = &dev->def_vlan; ++ n_def = ARRAY_SIZE(default_vlan); ++ if (!info->attrs[SWITCH_ATTR_OP_VLAN]) ++ goto done; ++ val->port_vlan = nla_get_u32(info->attrs[SWITCH_ATTR_OP_VLAN]); ++ if (val->port_vlan >= dev->vlans) ++ goto done; ++ break; ++ case SWITCH_CMD_SET_PORT: ++ case SWITCH_CMD_GET_PORT: ++ alist = &dev->ops->attr_port; ++ def_list = default_port; ++ def_active = &dev->def_port; ++ n_def = ARRAY_SIZE(default_port); ++ if (!info->attrs[SWITCH_ATTR_OP_PORT]) ++ goto done; ++ val->port_vlan = nla_get_u32(info->attrs[SWITCH_ATTR_OP_PORT]); ++ if (val->port_vlan >= dev->ports) ++ goto done; ++ break; ++ default: ++ WARN_ON(1); ++ goto done; ++ } ++ ++ if (!alist) ++ goto done; ++ ++ attr_id = nla_get_u32(info->attrs[SWITCH_ATTR_OP_ID]); ++ if (attr_id >= SWITCH_ATTR_DEFAULTS_OFFSET) { ++ attr_id -= SWITCH_ATTR_DEFAULTS_OFFSET; ++ if (attr_id >= n_def) ++ goto done; ++ if (!test_bit(attr_id, def_active)) ++ goto done; ++ attr = &def_list[attr_id]; ++ } else { ++ if (attr_id >= alist->n_attr) ++ goto done; ++ attr = &alist->attr[attr_id]; ++ } ++ ++ if (attr->disabled) ++ attr = NULL; ++ ++done: ++ if (!attr) ++ DPRINTF("attribute lookup failed\n"); ++ val->attr = attr; ++ return attr; ++} ++ ++static int ++swconfig_parse_ports(struct sk_buff *msg, struct nlattr *head, ++ struct switch_val *val, int max) ++{ ++ struct nlattr *nla; ++ int rem; ++ ++ val->len = 0; ++ nla_for_each_nested(nla, head, rem) { ++ struct nlattr *tb[SWITCH_PORT_ATTR_MAX+1]; ++ struct switch_port *port = &val->value.ports[val->len]; ++ ++ if (val->len >= max) ++ return -EINVAL; ++ ++ if (nla_parse_nested(tb, SWITCH_PORT_ATTR_MAX, nla, ++ port_policy)) ++ return -EINVAL; ++ ++ if (!tb[SWITCH_PORT_ID]) ++ return -EINVAL; ++ ++ port->id = nla_get_u32(tb[SWITCH_PORT_ID]); ++ if (tb[SWITCH_PORT_FLAG_TAGGED]) ++ port->flags |= (1 << SWITCH_PORT_FLAG_TAGGED); ++ val->len++; ++ } ++ ++ return 0; ++} ++ ++static int ++swconfig_set_attr(struct sk_buff *skb, struct genl_info *info) ++{ ++ const struct switch_attr *attr; ++ struct switch_dev *dev; ++ struct switch_val val; ++ int err = -EINVAL; ++ ++ dev = swconfig_get_dev(info); ++ if (!dev) ++ return -EINVAL; ++ ++ memset(&val, 0, sizeof(val)); ++ attr = swconfig_lookup_attr(dev, info, &val); ++ if (!attr || !attr->set) ++ goto error; ++ ++ val.attr = attr; ++ switch(attr->type) { ++ case SWITCH_TYPE_NOVAL: ++ break; ++ case SWITCH_TYPE_INT: ++ if (!info->attrs[SWITCH_ATTR_OP_VALUE_INT]) ++ goto error; ++ val.value.i = ++ nla_get_u32(info->attrs[SWITCH_ATTR_OP_VALUE_INT]); ++ break; ++ case SWITCH_TYPE_STRING: ++ if (!info->attrs[SWITCH_ATTR_OP_VALUE_STR]) ++ goto error; ++ val.value.s = ++ nla_data(info->attrs[SWITCH_ATTR_OP_VALUE_STR]); ++ break; ++ case SWITCH_TYPE_PORTS: ++ val.value.ports = dev->portbuf; ++ memset(dev->portbuf, 0, ++ sizeof(struct switch_port) * dev->ports); ++ ++ /* TODO: implement multipart? */ ++ if (info->attrs[SWITCH_ATTR_OP_VALUE_PORTS]) { ++ err = swconfig_parse_ports(skb, ++ info->attrs[SWITCH_ATTR_OP_VALUE_PORTS], &val, dev->ports); ++ if (err < 0) ++ goto error; ++ } else { ++ val.len = 0; ++ err = 0; ++ } ++ break; ++ default: ++ goto error; ++ } ++ ++ err = attr->set(dev, attr, &val); ++error: ++ swconfig_put_dev(dev); ++ return err; ++} ++ ++static int ++swconfig_close_portlist(struct swconfig_callback *cb, void *arg) ++{ ++ if (cb->nest[0]) ++ nla_nest_end(cb->msg, cb->nest[0]); ++ return 0; ++} ++ ++static int ++swconfig_send_port(struct swconfig_callback *cb, void *arg) ++{ ++ const struct switch_port *port = arg; ++ struct nlattr *p = NULL; ++ ++ if (!cb->nest[0]) { ++ cb->nest[0] = nla_nest_start(cb->msg, cb->cmd); ++ if (!cb->nest[0]) ++ return -1; ++ } ++ ++ p = nla_nest_start(cb->msg, SWITCH_ATTR_PORT); ++ if (!p) ++ goto error; ++ ++ NLA_PUT_U32(cb->msg, SWITCH_PORT_ID, port->id); ++ if (port->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) ++ NLA_PUT_FLAG(cb->msg, SWITCH_PORT_FLAG_TAGGED); ++ ++ nla_nest_end(cb->msg, p); ++ return 0; ++ ++nla_put_failure: ++ nla_nest_cancel(cb->msg, p); ++error: ++ nla_nest_cancel(cb->msg, cb->nest[0]); ++ return -1; ++} ++ ++static int ++swconfig_send_ports(struct sk_buff **msg, struct genl_info *info, int attr, ++ const struct switch_val *val) ++{ ++ struct swconfig_callback cb; ++ int err = 0; ++ int i; ++ ++ if (!val->value.ports) ++ return -EINVAL; ++ ++ memset(&cb, 0, sizeof(cb)); ++ cb.cmd = attr; ++ cb.msg = *msg; ++ cb.info = info; ++ cb.fill = swconfig_send_port; ++ cb.close = swconfig_close_portlist; ++ ++ cb.nest[0] = nla_nest_start(cb.msg, cb.cmd); ++ for (i = 0; i < val->len; i++) { ++ err = swconfig_send_multipart(&cb, &val->value.ports[i]); ++ if (err) ++ goto done; ++ } ++ err = val->len; ++ swconfig_close_portlist(&cb, NULL); ++ *msg = cb.msg; ++ ++done: ++ return err; ++} ++ ++static int ++swconfig_get_attr(struct sk_buff *skb, struct genl_info *info) ++{ ++ struct genlmsghdr *hdr = nlmsg_data(info->nlhdr); ++ const struct switch_attr *attr; ++ struct switch_dev *dev; ++ struct sk_buff *msg = NULL; ++ struct switch_val val; ++ int err = -EINVAL; ++ int cmd = hdr->cmd; ++ ++ dev = swconfig_get_dev(info); ++ if (!dev) ++ return -EINVAL; ++ ++ memset(&val, 0, sizeof(val)); ++ attr = swconfig_lookup_attr(dev, info, &val); ++ if (!attr || !attr->get) ++ goto error; ++ ++ if (attr->type == SWITCH_TYPE_PORTS) { ++ val.value.ports = dev->portbuf; ++ memset(dev->portbuf, 0, ++ sizeof(struct switch_port) * dev->ports); ++ } ++ ++ err = attr->get(dev, attr, &val); ++ if (err) ++ goto error; ++ ++ msg = nlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); ++ if (!msg) ++ goto error; ++ ++ hdr = genlmsg_put(msg, info->snd_pid, info->snd_seq, &switch_fam, ++ 0, cmd); ++ if (IS_ERR(hdr)) ++ goto nla_put_failure; ++ ++ switch(attr->type) { ++ case SWITCH_TYPE_INT: ++ NLA_PUT_U32(msg, SWITCH_ATTR_OP_VALUE_INT, val.value.i); ++ break; ++ case SWITCH_TYPE_STRING: ++ NLA_PUT_STRING(msg, SWITCH_ATTR_OP_VALUE_STR, val.value.s); ++ break; ++ case SWITCH_TYPE_PORTS: ++ err = swconfig_send_ports(&msg, info, ++ SWITCH_ATTR_OP_VALUE_PORTS, &val); ++ if (err < 0) ++ goto nla_put_failure; ++ break; ++ default: ++ DPRINTF("invalid type in attribute\n"); ++ err = -EINVAL; ++ goto error; ++ } ++ err = genlmsg_end(msg, hdr); ++ if (err < 0) ++ goto nla_put_failure; ++ ++ swconfig_put_dev(dev); ++ return genlmsg_reply(msg, info); ++ ++nla_put_failure: ++ if (msg) ++ nlmsg_free(msg); ++error: ++ swconfig_put_dev(dev); ++ if (!err) ++ err = -ENOMEM; ++ return err; ++} ++ ++static int ++swconfig_send_switch(struct sk_buff *msg, u32 pid, u32 seq, int flags, ++ const struct switch_dev *dev) ++{ ++ void *hdr; ++ ++ hdr = genlmsg_put(msg, pid, seq, &switch_fam, flags, ++ SWITCH_CMD_NEW_ATTR); ++ if (IS_ERR(hdr)) ++ return -1; ++ ++ NLA_PUT_U32(msg, SWITCH_ATTR_ID, dev->id); ++ NLA_PUT_STRING(msg, SWITCH_ATTR_DEV_NAME, dev->devname); ++ NLA_PUT_STRING(msg, SWITCH_ATTR_ALIAS, dev->alias); ++ NLA_PUT_STRING(msg, SWITCH_ATTR_NAME, dev->name); ++ NLA_PUT_U32(msg, SWITCH_ATTR_VLANS, dev->vlans); ++ NLA_PUT_U32(msg, SWITCH_ATTR_PORTS, dev->ports); ++ NLA_PUT_U32(msg, SWITCH_ATTR_CPU_PORT, dev->cpu_port); ++ ++ return genlmsg_end(msg, hdr); ++nla_put_failure: ++ genlmsg_cancel(msg, hdr); ++ return -EMSGSIZE; ++} ++ ++static int swconfig_dump_switches(struct sk_buff *skb, ++ struct netlink_callback *cb) ++{ ++ struct switch_dev *dev; ++ int start = cb->args[0]; ++ int idx = 0; ++ ++ swconfig_lock(); ++ list_for_each_entry(dev, &swdevs, dev_list) { ++ if (++idx <= start) ++ continue; ++ if (swconfig_send_switch(skb, NETLINK_CB(cb->skb).pid, ++ cb->nlh->nlmsg_seq, NLM_F_MULTI, ++ dev) < 0) ++ break; ++ } ++ swconfig_unlock(); ++ cb->args[0] = idx; ++ ++ return skb->len; ++} ++ ++static int ++swconfig_done(struct netlink_callback *cb) ++{ ++ return 0; ++} ++ ++static struct genl_ops swconfig_ops[] = { ++ { ++ .cmd = SWITCH_CMD_LIST_GLOBAL, ++ .doit = swconfig_list_attrs, ++ .policy = switch_policy, ++ }, ++ { ++ .cmd = SWITCH_CMD_LIST_VLAN, ++ .doit = swconfig_list_attrs, ++ .policy = switch_policy, ++ }, ++ { ++ .cmd = SWITCH_CMD_LIST_PORT, ++ .doit = swconfig_list_attrs, ++ .policy = switch_policy, ++ }, ++ { ++ .cmd = SWITCH_CMD_GET_GLOBAL, ++ .doit = swconfig_get_attr, ++ .policy = switch_policy, ++ }, ++ { ++ .cmd = SWITCH_CMD_GET_VLAN, ++ .doit = swconfig_get_attr, ++ .policy = switch_policy, ++ }, ++ { ++ .cmd = SWITCH_CMD_GET_PORT, ++ .doit = swconfig_get_attr, ++ .policy = switch_policy, ++ }, ++ { ++ .cmd = SWITCH_CMD_SET_GLOBAL, ++ .doit = swconfig_set_attr, ++ .policy = switch_policy, ++ }, ++ { ++ .cmd = SWITCH_CMD_SET_VLAN, ++ .doit = swconfig_set_attr, ++ .policy = switch_policy, ++ }, ++ { ++ .cmd = SWITCH_CMD_SET_PORT, ++ .doit = swconfig_set_attr, ++ .policy = switch_policy, ++ }, ++ { ++ .cmd = SWITCH_CMD_GET_SWITCH, ++ .dumpit = swconfig_dump_switches, ++ .policy = switch_policy, ++ .done = swconfig_done, ++ } ++}; ++ ++int ++register_switch(struct switch_dev *dev, struct net_device *netdev) ++{ ++ struct switch_dev *sdev; ++ const int max_switches = 8 * sizeof(unsigned long); ++ unsigned long in_use = 0; ++ int i; ++ ++ INIT_LIST_HEAD(&dev->dev_list); ++ if (netdev) { ++ dev->netdev = netdev; ++ if (!dev->alias) ++ dev->alias = netdev->name; ++ } ++ BUG_ON(!dev->alias); ++ ++ if (dev->ports > 0) { ++ dev->portbuf = kzalloc(sizeof(struct switch_port) * dev->ports, ++ GFP_KERNEL); ++ if (!dev->portbuf) ++ return -ENOMEM; ++ } ++ swconfig_defaults_init(dev); ++ spin_lock_init(&dev->lock); ++ swconfig_lock(); ++ dev->id = ++swdev_id; ++ ++ list_for_each_entry(sdev, &swdevs, dev_list) { ++ if (!sscanf(sdev->devname, SWCONFIG_DEVNAME, &i)) ++ continue; ++ if (i < 0 || i > max_switches) ++ continue; ++ ++ set_bit(i, &in_use); ++ } ++ i = find_first_zero_bit(&in_use, max_switches); ++ ++ if (i == max_switches) ++ return -ENFILE; ++ ++ /* fill device name */ ++ snprintf(dev->devname, IFNAMSIZ, SWCONFIG_DEVNAME, i); ++ ++ list_add(&dev->dev_list, &swdevs); ++ swconfig_unlock(); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(register_switch); ++ ++void ++unregister_switch(struct switch_dev *dev) ++{ ++ kfree(dev->portbuf); ++ spin_lock(&dev->lock); ++ swconfig_lock(); ++ list_del(&dev->dev_list); ++ swconfig_unlock(); ++ spin_unlock(&dev->lock); ++} ++EXPORT_SYMBOL_GPL(unregister_switch); ++ ++ ++static int __init ++swconfig_init(void) ++{ ++ int i, err; ++ ++ INIT_LIST_HEAD(&swdevs); ++ err = genl_register_family(&switch_fam); ++ if (err) ++ return err; ++ ++ for (i = 0; i < ARRAY_SIZE(swconfig_ops); i++) { ++ err = genl_register_ops(&switch_fam, &swconfig_ops[i]); ++ if (err) ++ goto unregister; ++ } ++ ++ return 0; ++ ++unregister: ++ genl_unregister_family(&switch_fam); ++ return err; ++} ++ ++static void __exit ++swconfig_exit(void) ++{ ++ genl_unregister_family(&switch_fam); ++} ++ ++module_init(swconfig_init); ++module_exit(swconfig_exit); ++ +diff -Nur linux-2.6.39.orig/drivers/spi/Kconfig linux-2.6.39/drivers/spi/Kconfig +--- linux-2.6.39.orig/drivers/spi/Kconfig 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/spi/Kconfig 2011-08-24 18:17:24.000000000 +0200 +@@ -67,6 +67,13 @@ + This enables support for the SPI controller present on the + Atheros AR71XX/AR724X/AR913X SoCs. + ++config SPI_AR71XX ++ tristate "Atheros AR71xx SPI Controller" ++ depends on SPI_MASTER && ATHEROS_AR71XX ++ select SPI_BITBANG ++ help ++ This is the SPI contoller driver for Atheros AR71xx. ++ + config SPI_ATMEL + tristate "Atmel SPI Controller" + depends on (ARCH_AT91 || AVR32) +@@ -301,6 +308,12 @@ + config SPI_PXA2XX_PCI + def_bool SPI_PXA2XX && X86_32 && PCI + ++config SPI_RB4XX ++ tristate "Mikrotik RB4XX SPI master" ++ depends on SPI_MASTER && AR71XX_MACH_RB4XX ++ help ++ SPI controller driver for the Mikrotik RB4xx series boards. ++ + config SPI_S3C24XX + tristate "Samsung S3C24XX series SPI" + depends on ARCH_S3C2410 && EXPERIMENTAL +@@ -457,6 +470,13 @@ + sysfs interface, with each line presented as a kind of GPIO + exposing both switch control and diagnostic feedback. + ++config SPI_RB4XX_CPLD ++ tristate "MikroTik RB4XX CPLD driver" ++ depends on AR71XX_MACH_RB4XX ++ help ++ SPI driver for the Xilinx CPLD chip present on the ++ MikroTik RB4xx boards. ++ + # + # Add new SPI protocol masters in alphabetical order above this line + # +diff -Nur linux-2.6.39.orig/drivers/spi/Makefile linux-2.6.39/drivers/spi/Makefile +--- linux-2.6.39.orig/drivers/spi/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/spi/Makefile 2011-08-24 18:17:24.000000000 +0200 +@@ -10,6 +10,7 @@ + + # SPI master controller drivers (bus) + obj-$(CONFIG_SPI_ALTERA) += spi_altera.o ++obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o + obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o + obj-$(CONFIG_SPI_ATH79) += ath79_spi.o + obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o +@@ -54,6 +55,7 @@ + obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o + obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o + obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o ++obj-$(CONFIG_SPI_RB4XX) += rb4xx_spi.o + + # special build for s3c24xx spi driver with fiq support + spi_s3c24xx_hw-y := spi_s3c24xx.o +@@ -62,6 +64,7 @@ + # ... add above this line ... + + # SPI protocol drivers (device/link on bus) ++obj-$(CONFIG_SPI_RB4XX_CPLD) += spi_rb4xx_cpld.o + obj-$(CONFIG_SPI_SPIDEV) += spidev.o + obj-$(CONFIG_SPI_TLE62X0) += tle62x0.o + # ... add above this line ... +diff -Nur linux-2.6.39.orig/drivers/spi/ap83_spi.c linux-2.6.39/drivers/spi/ap83_spi.c +--- linux-2.6.39.orig/drivers/spi/ap83_spi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/spi/ap83_spi.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,283 @@ ++/* ++ * Atheros AP83 board specific SPI Controller driver ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define DRV_DESC "Atheros AP83 board SPI Controller driver" ++#define DRV_VERSION "0.1.0" ++#define DRV_NAME "ap83-spi" ++ ++#define AP83_SPI_CLK_HIGH (1 << 23) ++#define AP83_SPI_CLK_LOW 0 ++#define AP83_SPI_MOSI_HIGH (1 << 22) ++#define AP83_SPI_MOSI_LOW 0 ++ ++#define AP83_SPI_GPIO_CS 1 ++#define AP83_SPI_GPIO_MISO 3 ++ ++struct ap83_spi { ++ struct spi_bitbang bitbang; ++ void __iomem *base; ++ u32 addr; ++ ++ struct platform_device *pdev; ++}; ++ ++static inline u32 ap83_spi_rr(struct ap83_spi *sp, u32 reg) ++{ ++ return __raw_readl(sp->base + reg); ++} ++ ++static inline struct ap83_spi *spidev_to_sp(struct spi_device *spi) ++{ ++ return spi_master_get_devdata(spi->master); ++} ++ ++static inline void setsck(struct spi_device *spi, int val) ++{ ++ struct ap83_spi *sp = spidev_to_sp(spi); ++ ++ if (val) ++ sp->addr |= AP83_SPI_CLK_HIGH; ++ else ++ sp->addr &= ~AP83_SPI_CLK_HIGH; ++ ++ dev_dbg(&spi->dev, "addr=%08x, SCK set to %s\n", ++ sp->addr, (val) ? "HIGH" : "LOW"); ++ ++ ap83_spi_rr(sp, sp->addr); ++} ++ ++static inline void setmosi(struct spi_device *spi, int val) ++{ ++ struct ap83_spi *sp = spidev_to_sp(spi); ++ ++ if (val) ++ sp->addr |= AP83_SPI_MOSI_HIGH; ++ else ++ sp->addr &= ~AP83_SPI_MOSI_HIGH; ++ ++ dev_dbg(&spi->dev, "addr=%08x, MOSI set to %s\n", ++ sp->addr, (val) ? "HIGH" : "LOW"); ++ ++ ap83_spi_rr(sp, sp->addr); ++} ++ ++static inline u32 getmiso(struct spi_device *spi) ++{ ++ u32 ret; ++ ++ ret = gpio_get_value(AP83_SPI_GPIO_MISO) ? 1 : 0; ++ dev_dbg(&spi->dev, "get MISO: %d\n", ret); ++ ++ return ret; ++} ++ ++static inline void do_spidelay(struct spi_device *spi, unsigned nsecs) ++{ ++ ndelay(nsecs); ++} ++ ++static void ap83_spi_chipselect(struct spi_device *spi, int on) ++{ ++ struct ap83_spi *sp = spidev_to_sp(spi); ++ ++ dev_dbg(&spi->dev, "set CS to %d\n", (on) ? 0 : 1); ++ ++ if (on) { ++ ar71xx_flash_acquire(); ++ ++ sp->addr = 0; ++ ap83_spi_rr(sp, sp->addr); ++ ++ gpio_set_value(AP83_SPI_GPIO_CS, 0); ++ } else { ++ gpio_set_value(AP83_SPI_GPIO_CS, 1); ++ ar71xx_flash_release(); ++ } ++} ++ ++#define spidelay(nsecs) \ ++ do { \ ++ /* Steal the spi_device pointer from our caller. \ ++ * The bitbang-API should probably get fixed here... */ \ ++ do_spidelay(spi, nsecs); \ ++ } while (0) ++ ++#define EXPAND_BITBANG_TXRX ++#include ++#include "spi_bitbang_txrx.h" ++ ++static u32 ap83_spi_txrx_mode0(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ dev_dbg(&spi->dev, "TXRX0 word=%08x, bits=%u\n", word, bits); ++ return bitbang_txrx_be_cpha0(spi, nsecs, 0, 0, word, bits); ++} ++ ++static u32 ap83_spi_txrx_mode1(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ dev_dbg(&spi->dev, "TXRX1 word=%08x, bits=%u\n", word, bits); ++ return bitbang_txrx_be_cpha1(spi, nsecs, 0, 0, word, bits); ++} ++ ++static u32 ap83_spi_txrx_mode2(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ dev_dbg(&spi->dev, "TXRX2 word=%08x, bits=%u\n", word, bits); ++ return bitbang_txrx_be_cpha0(spi, nsecs, 1, 0, word, bits); ++} ++ ++static u32 ap83_spi_txrx_mode3(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ dev_dbg(&spi->dev, "TXRX3 word=%08x, bits=%u\n", word, bits); ++ return bitbang_txrx_be_cpha1(spi, nsecs, 1, 0, word, bits); ++} ++ ++static int ap83_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct ap83_spi *sp; ++ struct ap83_spi_platform_data *pdata; ++ struct resource *r; ++ int ret; ++ ++ ret = gpio_request(AP83_SPI_GPIO_MISO, "spi-miso"); ++ if (ret) { ++ dev_err(&pdev->dev, "gpio request failed for MISO\n"); ++ return ret; ++ } ++ ++ ret = gpio_request(AP83_SPI_GPIO_CS, "spi-cs"); ++ if (ret) { ++ dev_err(&pdev->dev, "gpio request failed for CS\n"); ++ goto err_free_miso; ++ } ++ ++ ret = gpio_direction_input(AP83_SPI_GPIO_MISO); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to set direction of MISO\n"); ++ goto err_free_cs; ++ } ++ ++ ret = gpio_direction_output(AP83_SPI_GPIO_CS, 0); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to set direction of CS\n"); ++ goto err_free_cs; ++ } ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); ++ if (master == NULL) { ++ dev_err(&pdev->dev, "failed to allocate spi master\n"); ++ return -ENOMEM; ++ } ++ ++ sp = spi_master_get_devdata(master); ++ platform_set_drvdata(pdev, sp); ++ ++ pdata = pdev->dev.platform_data; ++ ++ sp->bitbang.master = spi_master_get(master); ++ sp->bitbang.chipselect = ap83_spi_chipselect; ++ sp->bitbang.txrx_word[SPI_MODE_0] = ap83_spi_txrx_mode0; ++ sp->bitbang.txrx_word[SPI_MODE_1] = ap83_spi_txrx_mode1; ++ sp->bitbang.txrx_word[SPI_MODE_2] = ap83_spi_txrx_mode2; ++ sp->bitbang.txrx_word[SPI_MODE_3] = ap83_spi_txrx_mode3; ++ ++ sp->bitbang.master->bus_num = pdev->id; ++ sp->bitbang.master->num_chipselect = 1; ++ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (r == NULL) { ++ ret = -ENOENT; ++ goto err_spi_put; ++ } ++ ++ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); ++ if (!sp->base) { ++ ret = -ENXIO; ++ goto err_spi_put; ++ } ++ ++ ret = spi_bitbang_start(&sp->bitbang); ++ if (!ret) ++ goto err_unmap; ++ ++ dev_info(&pdev->dev, "AP83 SPI adapter at %08x\n", r->start); ++ ++ return 0; ++ ++err_unmap: ++ iounmap(sp->base); ++err_spi_put: ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(sp->bitbang.master); ++ ++err_free_cs: ++ gpio_free(AP83_SPI_GPIO_CS); ++err_free_miso: ++ gpio_free(AP83_SPI_GPIO_MISO); ++ return ret; ++} ++ ++static int ap83_spi_remove(struct platform_device *pdev) ++{ ++ struct ap83_spi *sp = platform_get_drvdata(pdev); ++ ++ spi_bitbang_stop(&sp->bitbang); ++ iounmap(sp->base); ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(sp->bitbang.master); ++ ++ return 0; ++} ++ ++static struct platform_driver ap83_spi_drv = { ++ .probe = ap83_spi_probe, ++ .remove = ap83_spi_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init ap83_spi_init(void) ++{ ++ return platform_driver_register(&ap83_spi_drv); ++} ++module_init(ap83_spi_init); ++ ++static void __exit ap83_spi_exit(void) ++{ ++ platform_driver_unregister(&ap83_spi_drv); ++} ++module_exit(ap83_spi_exit); ++ ++MODULE_ALIAS("platform:" DRV_NAME); ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.39.orig/drivers/spi/ar71xx_spi.c linux-2.6.39/drivers/spi/ar71xx_spi.c +--- linux-2.6.39.orig/drivers/spi/ar71xx_spi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/spi/ar71xx_spi.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,283 @@ ++/* ++ * Atheros AR71xx SPI Controller driver ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define DRV_DESC "Atheros AR71xx SPI Controller driver" ++#define DRV_VERSION "0.2.4" ++#define DRV_NAME "ar71xx-spi" ++ ++#undef PER_BIT_READ ++ ++struct ar71xx_spi { ++ struct spi_bitbang bitbang; ++ u32 ioc_base; ++ u32 reg_ctrl; ++ ++ void __iomem *base; ++ ++ struct platform_device *pdev; ++ u32 (*get_ioc_base)(u8 chip_select, int cs_high, ++ int is_on); ++}; ++ ++static inline u32 ar71xx_spi_rr(struct ar71xx_spi *sp, unsigned reg) ++{ ++ return __raw_readl(sp->base + reg); ++} ++ ++static inline void ar71xx_spi_wr(struct ar71xx_spi *sp, unsigned reg, u32 val) ++{ ++ __raw_writel(val, sp->base + reg); ++} ++ ++static inline struct ar71xx_spi *spidev_to_sp(struct spi_device *spi) ++{ ++ return spi_master_get_devdata(spi->master); ++} ++ ++static u32 ar71xx_spi_get_ioc_base(u8 chip_select, int cs_high, int is_on) ++{ ++ u32 ret; ++ ++ if (is_on == AR71XX_SPI_CS_INACTIVE) ++ ret = SPI_IOC_CS_ALL; ++ else ++ ret = SPI_IOC_CS_ALL & ~SPI_IOC_CS(chip_select); ++ ++ return ret; ++} ++ ++static void ar71xx_spi_chipselect(struct spi_device *spi, int value) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); ++ void __iomem *base = sp->base; ++ u32 ioc_base; ++ ++ switch (value) { ++ case BITBANG_CS_INACTIVE: ++ ioc_base = sp->get_ioc_base(spi->chip_select, ++ (spi->mode & SPI_CS_HIGH) != 0, ++ AR71XX_SPI_CS_INACTIVE); ++ __raw_writel(ioc_base, base + SPI_REG_IOC); ++ break; ++ ++ case BITBANG_CS_ACTIVE: ++ ioc_base = sp->get_ioc_base(spi->chip_select, ++ (spi->mode & SPI_CS_HIGH) != 0, ++ AR71XX_SPI_CS_ACTIVE); ++ ++ __raw_writel(ioc_base, base + SPI_REG_IOC); ++ sp->ioc_base = ioc_base; ++ break; ++ } ++} ++ ++static void ar71xx_spi_setup_regs(struct spi_device *spi) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); ++ ++ /* enable GPIO mode */ ++ ar71xx_spi_wr(sp, SPI_REG_FS, SPI_FS_GPIO); ++ ++ /* save CTRL register */ ++ sp->reg_ctrl = ar71xx_spi_rr(sp, SPI_REG_CTRL); ++ ++ /* TODO: setup speed? */ ++ ar71xx_spi_wr(sp, SPI_REG_CTRL, 0x43); ++} ++ ++static void ar71xx_spi_restore_regs(struct spi_device *spi) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); ++ ++ /* restore CTRL register */ ++ ar71xx_spi_wr(sp, SPI_REG_CTRL, sp->reg_ctrl); ++ /* disable GPIO mode */ ++ ar71xx_spi_wr(sp, SPI_REG_FS, 0); ++} ++ ++static int ar71xx_spi_setup(struct spi_device *spi) ++{ ++ int status; ++ ++ if (spi->bits_per_word > 32) ++ return -EINVAL; ++ ++ if (!spi->controller_state) ++ ar71xx_spi_setup_regs(spi); ++ ++ status = spi_bitbang_setup(spi); ++ if (status && !spi->controller_state) ++ ar71xx_spi_restore_regs(spi); ++ ++ return status; ++} ++ ++static void ar71xx_spi_cleanup(struct spi_device *spi) ++{ ++ ar71xx_spi_restore_regs(spi); ++ spi_bitbang_cleanup(spi); ++} ++ ++static u32 ar71xx_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, ++ u32 word, u8 bits) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); ++ void __iomem *base = sp->base; ++ u32 ioc = sp->ioc_base; ++ u32 ret; ++ ++ /* clock starts at inactive polarity */ ++ for (word <<= (32 - bits); likely(bits); bits--) { ++ u32 out; ++ ++ if (word & (1 << 31)) ++ out = ioc | SPI_IOC_DO; ++ else ++ out = ioc & ~SPI_IOC_DO; ++ ++ /* setup MSB (to slave) on trailing edge */ ++ __raw_writel(out, base + SPI_REG_IOC); ++ ++ __raw_writel(out | SPI_IOC_CLK, base + SPI_REG_IOC); ++ ++ word <<= 1; ++ ++#ifdef PER_BIT_READ ++ /* sample MSB (from slave) on leading edge */ ++ ret = __raw_readl(base + SPI_REG_RDS); ++ __raw_writel(out, base + SPI_REG_IOC); ++#endif ++ ++ } ++ ++#ifndef PER_BIT_READ ++ ret = __raw_readl(base + SPI_REG_RDS); ++#endif ++ return ret; ++} ++ ++static int ar71xx_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct ar71xx_spi *sp; ++ struct ar71xx_spi_platform_data *pdata; ++ struct resource *r; ++ int ret; ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); ++ if (master == NULL) { ++ dev_err(&pdev->dev, "failed to allocate spi master\n"); ++ return -ENOMEM; ++ } ++ ++ sp = spi_master_get_devdata(master); ++ platform_set_drvdata(pdev, sp); ++ ++ pdata = pdev->dev.platform_data; ++ ++ master->setup = ar71xx_spi_setup; ++ master->cleanup = ar71xx_spi_cleanup; ++ ++ sp->bitbang.master = spi_master_get(master); ++ sp->bitbang.chipselect = ar71xx_spi_chipselect; ++ sp->bitbang.txrx_word[SPI_MODE_0] = ar71xx_spi_txrx_mode0; ++ sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; ++ ++ sp->get_ioc_base = ar71xx_spi_get_ioc_base; ++ if (pdata) { ++ sp->bitbang.master->bus_num = pdata->bus_num; ++ sp->bitbang.master->num_chipselect = pdata->num_chipselect; ++ if (pdata->get_ioc_base) ++ sp->get_ioc_base = pdata->get_ioc_base; ++ } else { ++ sp->bitbang.master->bus_num = 0; ++ sp->bitbang.master->num_chipselect = 3; ++ } ++ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (r == NULL) { ++ ret = -ENOENT; ++ goto err1; ++ } ++ ++ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); ++ if (!sp->base) { ++ ret = -ENXIO; ++ goto err1; ++ } ++ ++ ret = spi_bitbang_start(&sp->bitbang); ++ if (!ret) ++ return 0; ++ ++ iounmap(sp->base); ++err1: ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(sp->bitbang.master); ++ ++ return ret; ++} ++ ++static int ar71xx_spi_remove(struct platform_device *pdev) ++{ ++ struct ar71xx_spi *sp = platform_get_drvdata(pdev); ++ ++ spi_bitbang_stop(&sp->bitbang); ++ iounmap(sp->base); ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(sp->bitbang.master); ++ ++ return 0; ++} ++ ++static struct platform_driver ar71xx_spi_drv = { ++ .probe = ar71xx_spi_probe, ++ .remove = ar71xx_spi_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init ar71xx_spi_init(void) ++{ ++ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); ++ return platform_driver_register(&ar71xx_spi_drv); ++} ++module_init(ar71xx_spi_init); ++ ++static void __exit ar71xx_spi_exit(void) ++{ ++ platform_driver_unregister(&ar71xx_spi_drv); ++} ++module_exit(ar71xx_spi_exit); ++ ++MODULE_ALIAS("platform:" DRV_NAME); ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_AUTHOR("Imre Kaloz "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.39.orig/drivers/spi/pb44_spi.c linux-2.6.39/drivers/spi/pb44_spi.c +--- linux-2.6.39.orig/drivers/spi/pb44_spi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/spi/pb44_spi.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,299 @@ ++/* ++ * Atheros PB44 board SPI controller driver ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define DRV_DESC "Atheros PB44 SPI Controller driver" ++#define DRV_VERSION "0.1.0" ++#define DRV_NAME "pb44-spi" ++ ++#undef PER_BIT_READ ++ ++struct ar71xx_spi { ++ struct spi_bitbang bitbang; ++ u32 ioc_base; ++ u32 reg_ctrl; ++ ++ void __iomem *base; ++ ++ struct platform_device *pdev; ++}; ++ ++static inline u32 pb44_spi_rr(struct ar71xx_spi *sp, unsigned reg) ++{ ++ return __raw_readl(sp->base + reg); ++} ++ ++static inline void pb44_spi_wr(struct ar71xx_spi *sp, unsigned reg, u32 val) ++{ ++ __raw_writel(val, sp->base + reg); ++} ++ ++static inline struct ar71xx_spi *spidev_to_sp(struct spi_device *spi) ++{ ++ return spi_master_get_devdata(spi->master); ++} ++ ++static void pb44_spi_chipselect(struct spi_device *spi, int is_active) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); ++ int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; ++ ++ if (is_active) { ++ /* set initial clock polarity */ ++ if (spi->mode & SPI_CPOL) ++ sp->ioc_base |= SPI_IOC_CLK; ++ else ++ sp->ioc_base &= ~SPI_IOC_CLK; ++ ++ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); ++ } ++ ++ if (spi->chip_select) { ++ unsigned long gpio = (unsigned long) spi->controller_data; ++ ++ /* SPI is normally active-low */ ++ gpio_set_value(gpio, cs_high); ++ } else { ++ if (cs_high) ++ sp->ioc_base |= SPI_IOC_CS0; ++ else ++ sp->ioc_base &= ~SPI_IOC_CS0; ++ ++ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); ++ } ++ ++} ++ ++static int pb44_spi_setup_cs(struct spi_device *spi) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); ++ ++ /* enable GPIO mode */ ++ pb44_spi_wr(sp, SPI_REG_FS, SPI_FS_GPIO); ++ ++ /* save CTRL register */ ++ sp->reg_ctrl = pb44_spi_rr(sp, SPI_REG_CTRL); ++ sp->ioc_base = pb44_spi_rr(sp, SPI_REG_IOC); ++ ++ /* TODO: setup speed? */ ++ pb44_spi_wr(sp, SPI_REG_CTRL, 0x43); ++ ++ if (spi->chip_select) { ++ unsigned long gpio = (unsigned long) spi->controller_data; ++ int status = 0; ++ ++ status = gpio_request(gpio, dev_name(&spi->dev)); ++ if (status) ++ return status; ++ ++ status = gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH); ++ if (status) { ++ gpio_free(gpio); ++ return status; ++ } ++ } else { ++ if (spi->mode & SPI_CS_HIGH) ++ sp->ioc_base |= SPI_IOC_CS0; ++ else ++ sp->ioc_base &= ~SPI_IOC_CS0; ++ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); ++ } ++ ++ return 0; ++} ++ ++static void pb44_spi_cleanup_cs(struct spi_device *spi) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); ++ ++ if (spi->chip_select) { ++ unsigned long gpio = (unsigned long) spi->controller_data; ++ gpio_free(gpio); ++ } ++ ++ /* restore CTRL register */ ++ pb44_spi_wr(sp, SPI_REG_CTRL, sp->reg_ctrl); ++ /* disable GPIO mode */ ++ pb44_spi_wr(sp, SPI_REG_FS, 0); ++} ++ ++static int pb44_spi_setup(struct spi_device *spi) ++{ ++ int status = 0; ++ ++ if (spi->bits_per_word > 32) ++ return -EINVAL; ++ ++ if (!spi->controller_state) { ++ status = pb44_spi_setup_cs(spi); ++ if (status) ++ return status; ++ } ++ ++ status = spi_bitbang_setup(spi); ++ if (status && !spi->controller_state) ++ pb44_spi_cleanup_cs(spi); ++ ++ return status; ++} ++ ++static void pb44_spi_cleanup(struct spi_device *spi) ++{ ++ pb44_spi_cleanup_cs(spi); ++ spi_bitbang_cleanup(spi); ++} ++ ++static u32 pb44_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, ++ u32 word, u8 bits) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); ++ u32 ioc = sp->ioc_base; ++ u32 ret; ++ ++ /* clock starts at inactive polarity */ ++ for (word <<= (32 - bits); likely(bits); bits--) { ++ u32 out; ++ ++ if (word & (1 << 31)) ++ out = ioc | SPI_IOC_DO; ++ else ++ out = ioc & ~SPI_IOC_DO; ++ ++ /* setup MSB (to slave) on trailing edge */ ++ pb44_spi_wr(sp, SPI_REG_IOC, out); ++ pb44_spi_wr(sp, SPI_REG_IOC, out | SPI_IOC_CLK); ++ ++ word <<= 1; ++ ++#ifdef PER_BIT_READ ++ /* sample MSB (from slave) on leading edge */ ++ ret = pb44_spi_rr(sp, SPI_REG_RDS); ++ pb44_spi_wr(sp, SPI_REG_IOC, out); ++#endif ++ } ++ ++#ifndef PER_BIT_READ ++ ret = pb44_spi_rr(sp, SPI_REG_RDS); ++#endif ++ return ret; ++} ++ ++static int pb44_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct ar71xx_spi *sp; ++ struct ar71xx_spi_platform_data *pdata; ++ struct resource *r; ++ int ret; ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); ++ if (master == NULL) { ++ dev_err(&pdev->dev, "failed to allocate spi master\n"); ++ return -ENOMEM; ++ } ++ ++ sp = spi_master_get_devdata(master); ++ platform_set_drvdata(pdev, sp); ++ ++ pdata = pdev->dev.platform_data; ++ ++ master->setup = pb44_spi_setup; ++ master->cleanup = pb44_spi_cleanup; ++ if (pdata) { ++ master->bus_num = pdata->bus_num; ++ master->num_chipselect = pdata->num_chipselect; ++ } else { ++ master->bus_num = 0; ++ master->num_chipselect = 1; ++ } ++ ++ sp->bitbang.master = spi_master_get(master); ++ sp->bitbang.chipselect = pb44_spi_chipselect; ++ sp->bitbang.txrx_word[SPI_MODE_0] = pb44_spi_txrx_mode0; ++ sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; ++ sp->bitbang.flags = SPI_CS_HIGH; ++ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (r == NULL) { ++ ret = -ENOENT; ++ goto err1; ++ } ++ ++ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); ++ if (!sp->base) { ++ ret = -ENXIO; ++ goto err1; ++ } ++ ++ ret = spi_bitbang_start(&sp->bitbang); ++ if (!ret) ++ return 0; ++ ++ iounmap(sp->base); ++err1: ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(sp->bitbang.master); ++ ++ return ret; ++} ++ ++static int pb44_spi_remove(struct platform_device *pdev) ++{ ++ struct ar71xx_spi *sp = platform_get_drvdata(pdev); ++ ++ spi_bitbang_stop(&sp->bitbang); ++ iounmap(sp->base); ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(sp->bitbang.master); ++ ++ return 0; ++} ++ ++static struct platform_driver pb44_spi_drv = { ++ .probe = pb44_spi_probe, ++ .remove = pb44_spi_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init pb44_spi_init(void) ++{ ++ return platform_driver_register(&pb44_spi_drv); ++} ++module_init(pb44_spi_init); ++ ++static void __exit pb44_spi_exit(void) ++{ ++ platform_driver_unregister(&pb44_spi_drv); ++} ++module_exit(pb44_spi_exit); ++ ++MODULE_ALIAS("platform:" DRV_NAME); ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.39.orig/drivers/spi/rb4xx_spi.c linux-2.6.39/drivers/spi/rb4xx_spi.c +--- linux-2.6.39.orig/drivers/spi/rb4xx_spi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/spi/rb4xx_spi.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,474 @@ ++/* ++ * SPI controller driver for the Mikrotik RB4xx boards ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This file was based on the patches for Linux 2.6.27.39 published by ++ * MikroTik for their RouterBoard 4xx series devices. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define DRV_NAME "rb4xx-spi" ++#define DRV_DESC "Mikrotik RB4xx SPI controller driver" ++#define DRV_VERSION "0.1.0" ++ ++#define SPI_CTRL_FASTEST 0x40 ++#define SPI_FLASH_HZ 33333334 ++#define SPI_CPLD_HZ 33333334 ++ ++#define CPLD_CMD_READ_FAST 0x0b ++ ++#undef RB4XX_SPI_DEBUG ++ ++struct rb4xx_spi { ++ void __iomem *base; ++ struct spi_master *master; ++ ++ unsigned spi_ctrl_flash; ++ unsigned spi_ctrl_fread; ++ ++ spinlock_t lock; ++ struct list_head queue; ++ int busy:1; ++ int cs_wait; ++}; ++ ++static unsigned spi_clk_low = SPI_IOC_CS1; ++ ++#ifdef RB4XX_SPI_DEBUG ++static inline void do_spi_delay(void) ++{ ++ ndelay(20000); ++} ++#else ++static inline void do_spi_delay(void) { } ++#endif ++ ++static inline void do_spi_init(struct spi_device *spi) ++{ ++ unsigned cs = SPI_IOC_CS0 | SPI_IOC_CS1; ++ ++ if (!(spi->mode & SPI_CS_HIGH)) ++ cs ^= (spi->chip_select == 2) ? SPI_IOC_CS1 : SPI_IOC_CS0; ++ ++ spi_clk_low = cs; ++} ++ ++static inline void do_spi_finish(void __iomem *base) ++{ ++ do_spi_delay(); ++ __raw_writel(SPI_IOC_CS0 | SPI_IOC_CS1, base + SPI_REG_IOC); ++} ++ ++static inline void do_spi_clk(void __iomem *base, int bit) ++{ ++ unsigned bval = spi_clk_low | ((bit & 1) ? SPI_IOC_DO : 0); ++ ++ do_spi_delay(); ++ __raw_writel(bval, base + SPI_REG_IOC); ++ do_spi_delay(); ++ __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC); ++} ++ ++static void do_spi_byte(void __iomem *base, unsigned char byte) ++{ ++ do_spi_clk(base, byte >> 7); ++ do_spi_clk(base, byte >> 6); ++ do_spi_clk(base, byte >> 5); ++ do_spi_clk(base, byte >> 4); ++ do_spi_clk(base, byte >> 3); ++ do_spi_clk(base, byte >> 2); ++ do_spi_clk(base, byte >> 1); ++ do_spi_clk(base, byte); ++ ++ pr_debug("spi_byte sent 0x%02x got 0x%02x\n", ++ (unsigned)byte, ++ (unsigned char)__raw_readl(base + SPI_REG_RDS)); ++} ++ ++static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1, ++ unsigned bit2) ++{ ++ unsigned bval = (spi_clk_low | ++ ((bit1 & 1) ? SPI_IOC_DO : 0) | ++ ((bit2 & 1) ? SPI_IOC_CS2 : 0)); ++ do_spi_delay(); ++ __raw_writel(bval, base + SPI_REG_IOC); ++ do_spi_delay(); ++ __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC); ++} ++ ++static void do_spi_byte_fast(void __iomem *base, unsigned char byte) ++{ ++ do_spi_clk_fast(base, byte >> 7, byte >> 6); ++ do_spi_clk_fast(base, byte >> 5, byte >> 4); ++ do_spi_clk_fast(base, byte >> 3, byte >> 2); ++ do_spi_clk_fast(base, byte >> 1, byte >> 0); ++ ++ pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n", ++ (unsigned)byte, ++ (unsigned char) __raw_readl(base + SPI_REG_RDS)); ++} ++ ++static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t) ++{ ++ const unsigned char *rxv_ptr = NULL; ++ const unsigned char *tx_ptr = t->tx_buf; ++ unsigned char *rx_ptr = t->rx_buf; ++ unsigned i; ++ ++ pr_debug("spi_txrx len %u tx %u rx %u\n", ++ t->len, ++ (t->tx_buf ? 1 : 0), ++ (t->rx_buf ? 1 : 0)); ++ ++ if (t->verify) { ++ rxv_ptr = tx_ptr; ++ tx_ptr = NULL; ++ } ++ ++ for (i = 0; i < t->len; ++i) { ++ unsigned char sdata = tx_ptr ? tx_ptr[i] : 0; ++ ++ if (t->fast_write) ++ do_spi_byte_fast(base, sdata); ++ else ++ do_spi_byte(base, sdata); ++ ++ if (rx_ptr) { ++ rx_ptr[i] = __raw_readl(base + SPI_REG_RDS) & 0xff; ++ } else if (rxv_ptr) { ++ unsigned char c = __raw_readl(base + SPI_REG_RDS); ++ if (rxv_ptr[i] != c) ++ return i; ++ } ++ } ++ ++ return i; ++} ++ ++static int rb4xx_spi_read_fast(struct rb4xx_spi *rbspi, ++ struct spi_message *m) ++{ ++ struct spi_transfer *t; ++ const unsigned char *tx_ptr; ++ unsigned addr; ++ void __iomem *base = rbspi->base; ++ ++ /* check for exactly two transfers */ ++ if (list_empty(&m->transfers) || ++ list_is_last(m->transfers.next, &m->transfers) || ++ !list_is_last(m->transfers.next->next, &m->transfers)) { ++ return -1; ++ } ++ ++ /* first transfer contains command and address */ ++ t = list_entry(m->transfers.next, ++ struct spi_transfer, transfer_list); ++ ++ if (t->len != 5 || t->tx_buf == NULL) ++ return -1; ++ ++ tx_ptr = t->tx_buf; ++ if (tx_ptr[0] != CPLD_CMD_READ_FAST) ++ return -1; ++ ++ addr = tx_ptr[1]; ++ addr = tx_ptr[2] | (addr << 8); ++ addr = tx_ptr[3] | (addr << 8); ++ addr += (unsigned) base; ++ ++ m->actual_length += t->len; ++ ++ /* second transfer contains data itself */ ++ t = list_entry(m->transfers.next->next, ++ struct spi_transfer, transfer_list); ++ ++ if (t->tx_buf && !t->verify) ++ return -1; ++ ++ __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS); ++ __raw_writel(rbspi->spi_ctrl_fread, base + SPI_REG_CTRL); ++ __raw_writel(0, base + SPI_REG_FS); ++ ++ if (t->rx_buf) { ++ memcpy(t->rx_buf, (const void *)addr, t->len); ++ } else if (t->tx_buf) { ++ unsigned char buf[t->len]; ++ memcpy(buf, (const void *)addr, t->len); ++ if (memcmp(t->tx_buf, buf, t->len) != 0) ++ m->status = -EMSGSIZE; ++ } ++ m->actual_length += t->len; ++ ++ if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) { ++ __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS); ++ __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL); ++ __raw_writel(0, base + SPI_REG_FS); ++ } ++ ++ return 0; ++} ++ ++static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m) ++{ ++ struct spi_transfer *t = NULL; ++ void __iomem *base = rbspi->base; ++ ++ m->status = 0; ++ if (list_empty(&m->transfers)) ++ return -1; ++ ++ if (m->fast_read) ++ if (rb4xx_spi_read_fast(rbspi, m) == 0) ++ return -1; ++ ++ __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS); ++ __raw_writel(SPI_CTRL_FASTEST, base + SPI_REG_CTRL); ++ do_spi_init(m->spi); ++ ++ list_for_each_entry(t, &m->transfers, transfer_list) { ++ int len; ++ ++ len = rb4xx_spi_txrx(base, t); ++ if (len != t->len) { ++ m->status = -EMSGSIZE; ++ break; ++ } ++ m->actual_length += len; ++ ++ if (t->cs_change) { ++ if (list_is_last(&t->transfer_list, &m->transfers)) { ++ /* wait for continuation */ ++ return m->spi->chip_select; ++ } ++ do_spi_finish(base); ++ ndelay(100); ++ } ++ } ++ ++ do_spi_finish(base); ++ __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL); ++ __raw_writel(0, base + SPI_REG_FS); ++ return -1; ++} ++ ++static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi, ++ unsigned long *flags) ++{ ++ int cs = rbspi->cs_wait; ++ ++ rbspi->busy = 1; ++ while (!list_empty(&rbspi->queue)) { ++ struct spi_message *m; ++ ++ list_for_each_entry(m, &rbspi->queue, queue) ++ if (cs < 0 || cs == m->spi->chip_select) ++ break; ++ ++ if (&m->queue == &rbspi->queue) ++ break; ++ ++ list_del_init(&m->queue); ++ spin_unlock_irqrestore(&rbspi->lock, *flags); ++ ++ cs = rb4xx_spi_msg(rbspi, m); ++ m->complete(m->context); ++ ++ spin_lock_irqsave(&rbspi->lock, *flags); ++ } ++ ++ rbspi->cs_wait = cs; ++ rbspi->busy = 0; ++ ++ if (cs >= 0) { ++ /* TODO: add timer to unlock cs after 1s inactivity */ ++ } ++} ++ ++static int rb4xx_spi_transfer(struct spi_device *spi, ++ struct spi_message *m) ++{ ++ struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master); ++ unsigned long flags; ++ ++ m->actual_length = 0; ++ m->status = -EINPROGRESS; ++ ++ spin_lock_irqsave(&rbspi->lock, flags); ++ list_add_tail(&m->queue, &rbspi->queue); ++ if (rbspi->busy || ++ (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) { ++ /* job will be done later */ ++ spin_unlock_irqrestore(&rbspi->lock, flags); ++ return 0; ++ } ++ ++ /* process job in current context */ ++ rb4xx_spi_process_queue_locked(rbspi, &flags); ++ spin_unlock_irqrestore(&rbspi->lock, flags); ++ ++ return 0; ++} ++ ++static int rb4xx_spi_setup(struct spi_device *spi) ++{ ++ struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master); ++ unsigned long flags; ++ ++ if (spi->mode & ~(SPI_CS_HIGH)) { ++ dev_err(&spi->dev, "mode %x not supported\n", ++ (unsigned) spi->mode); ++ return -EINVAL; ++ } ++ ++ if (spi->bits_per_word != 8 && spi->bits_per_word != 0) { ++ dev_err(&spi->dev, "bits_per_word %u not supported\n", ++ (unsigned) spi->bits_per_word); ++ return -EINVAL; ++ } ++ ++ spin_lock_irqsave(&rbspi->lock, flags); ++ if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) { ++ rbspi->cs_wait = -1; ++ rb4xx_spi_process_queue_locked(rbspi, &flags); ++ } ++ spin_unlock_irqrestore(&rbspi->lock, flags); ++ ++ return 0; ++} ++ ++static unsigned get_spi_ctrl(unsigned hz_max, const char *name) ++{ ++ unsigned div; ++ ++ div = (ar71xx_ahb_freq - 1) / (2 * hz_max); ++ ++ /* ++ * CPU has a bug at (div == 0) - first bit read is random ++ */ ++ if (div == 0) ++ ++div; ++ ++ if (name) { ++ unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000; ++ unsigned div_real = 2 * (div + 1); ++ pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n", ++ name, ++ ahb_khz / div_real, ++ ahb_khz, div_real); ++ } ++ ++ return SPI_CTRL_FASTEST + div; ++} ++ ++static int rb4xx_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct rb4xx_spi *rbspi; ++ struct resource *r; ++ int err = 0; ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*rbspi)); ++ if (master == NULL) { ++ dev_err(&pdev->dev, "no memory for spi_master\n"); ++ err = -ENOMEM; ++ goto err_out; ++ } ++ ++ master->bus_num = 0; ++ master->num_chipselect = 3; ++ master->setup = rb4xx_spi_setup; ++ master->transfer = rb4xx_spi_transfer; ++ ++ rbspi = spi_master_get_devdata(master); ++ platform_set_drvdata(pdev, rbspi); ++ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (r == NULL) { ++ err = -ENOENT; ++ goto err_put_master; ++ } ++ ++ rbspi->base = ioremap(r->start, r->end - r->start + 1); ++ if (!rbspi->base) { ++ err = -ENXIO; ++ goto err_put_master; ++ } ++ ++ rbspi->master = master; ++ rbspi->spi_ctrl_flash = get_spi_ctrl(SPI_FLASH_HZ, "FLASH"); ++ rbspi->spi_ctrl_fread = get_spi_ctrl(SPI_CPLD_HZ, "CPLD"); ++ rbspi->cs_wait = -1; ++ ++ spin_lock_init(&rbspi->lock); ++ INIT_LIST_HEAD(&rbspi->queue); ++ ++ err = spi_register_master(master); ++ if (err) { ++ dev_err(&pdev->dev, "failed to register SPI master\n"); ++ goto err_iounmap; ++ } ++ ++ return 0; ++ ++err_iounmap: ++ iounmap(rbspi->base); ++err_put_master: ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(master); ++err_out: ++ return err; ++} ++ ++static int rb4xx_spi_remove(struct platform_device *pdev) ++{ ++ struct rb4xx_spi *rbspi = platform_get_drvdata(pdev); ++ ++ iounmap(rbspi->base); ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(rbspi->master); ++ ++ return 0; ++} ++ ++static struct platform_driver rb4xx_spi_drv = { ++ .probe = rb4xx_spi_probe, ++ .remove = rb4xx_spi_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init rb4xx_spi_init(void) ++{ ++ return platform_driver_register(&rb4xx_spi_drv); ++} ++subsys_initcall(rb4xx_spi_init); ++ ++static void __exit rb4xx_spi_exit(void) ++{ ++ platform_driver_unregister(&rb4xx_spi_drv); ++} ++ ++module_exit(rb4xx_spi_exit); ++ ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.39.orig/drivers/spi/spi_rb4xx_cpld.c linux-2.6.39/drivers/spi/spi_rb4xx_cpld.c +--- linux-2.6.39.orig/drivers/spi/spi_rb4xx_cpld.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/spi/spi_rb4xx_cpld.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,440 @@ ++/* ++ * SPI driver for the CPLD chip on the Mikrotik RB4xx boards ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This file was based on the patches for Linux 2.6.27.39 published by ++ * MikroTik for their RouterBoard 4xx series devices. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define DRV_NAME "spi-rb4xx-cpld" ++#define DRV_DESC "RB4xx CPLD driver" ++#define DRV_VERSION "0.1.0" ++ ++#define CPLD_CMD_WRITE_NAND 0x08 /* send cmd, n x send data, send indle */ ++#define CPLD_CMD_WRITE_CFG 0x09 /* send cmd, n x send cfg */ ++#define CPLD_CMD_READ_NAND 0x0a /* send cmd, send idle, n x read data */ ++#define CPLD_CMD_READ_FAST 0x0b /* send cmd, 4 x idle, n x read data */ ++#define CPLD_CMD_LED5_ON 0x0c /* send cmd */ ++#define CPLD_CMD_LED5_OFF 0x0d /* send cmd */ ++ ++struct rb4xx_cpld { ++ struct spi_device *spi; ++ struct mutex lock; ++ struct gpio_chip chip; ++ unsigned int config; ++}; ++ ++static struct rb4xx_cpld *rb4xx_cpld; ++ ++static inline struct rb4xx_cpld *gpio_to_cpld(struct gpio_chip *chip) ++{ ++ return container_of(chip, struct rb4xx_cpld, chip); ++} ++ ++static int rb4xx_cpld_write_cmd(struct rb4xx_cpld *cpld, unsigned char cmd) ++{ ++ struct spi_transfer t[1]; ++ struct spi_message m; ++ unsigned char tx_buf[1]; ++ int err; ++ ++ spi_message_init(&m); ++ memset(&t, 0, sizeof(t)); ++ ++ t[0].tx_buf = tx_buf; ++ t[0].len = sizeof(tx_buf); ++ spi_message_add_tail(&t[0], &m); ++ ++ tx_buf[0] = cmd; ++ ++ err = spi_sync(cpld->spi, &m); ++ return err; ++} ++ ++static int rb4xx_cpld_write_cfg(struct rb4xx_cpld *cpld, unsigned char config) ++{ ++ struct spi_transfer t[1]; ++ struct spi_message m; ++ unsigned char cmd[2]; ++ int err; ++ ++ spi_message_init(&m); ++ memset(&t, 0, sizeof(t)); ++ ++ t[0].tx_buf = cmd; ++ t[0].len = sizeof(cmd); ++ spi_message_add_tail(&t[0], &m); ++ ++ cmd[0] = CPLD_CMD_WRITE_CFG; ++ cmd[1] = config; ++ ++ err = spi_sync(cpld->spi, &m); ++ return err; ++} ++ ++static int __rb4xx_cpld_change_cfg(struct rb4xx_cpld *cpld, unsigned mask, ++ unsigned value) ++{ ++ unsigned int config; ++ int err; ++ ++ config = cpld->config & ~mask; ++ config |= value; ++ ++ if ((cpld->config ^ config) & 0xff) { ++ err = rb4xx_cpld_write_cfg(cpld, config); ++ if (err) ++ return err; ++ } ++ ++ if ((cpld->config ^ config) & CPLD_CFG_nLED5) { ++ err = rb4xx_cpld_write_cmd(cpld, (value) ? CPLD_CMD_LED5_ON : ++ CPLD_CMD_LED5_OFF); ++ if (err) ++ return err; ++ } ++ ++ cpld->config = config; ++ return 0; ++} ++ ++int rb4xx_cpld_change_cfg(unsigned mask, unsigned value) ++{ ++ int ret; ++ ++ if (rb4xx_cpld == NULL) ++ return -ENODEV; ++ ++ mutex_lock(&rb4xx_cpld->lock); ++ ret = __rb4xx_cpld_change_cfg(rb4xx_cpld, mask, value); ++ mutex_unlock(&rb4xx_cpld->lock); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(rb4xx_cpld_change_cfg); ++ ++int rb4xx_cpld_read_from(unsigned addr, unsigned char *rx_buf, ++ const unsigned char *verify_buf, unsigned count) ++{ ++ const unsigned char cmd[5] = { ++ CPLD_CMD_READ_FAST, ++ (addr >> 16) & 0xff, ++ (addr >> 8) & 0xff, ++ addr & 0xff, ++ 0 ++ }; ++ struct spi_transfer t[2] = { ++ { ++ .tx_buf = &cmd, ++ .len = 5, ++ }, ++ { ++ .tx_buf = verify_buf, ++ .rx_buf = rx_buf, ++ .len = count, ++ .verify = (verify_buf != NULL), ++ }, ++ }; ++ struct spi_message m; ++ ++ if (rb4xx_cpld == NULL) ++ return -ENODEV; ++ ++ spi_message_init(&m); ++ m.fast_read = 1; ++ spi_message_add_tail(&t[0], &m); ++ spi_message_add_tail(&t[1], &m); ++ return spi_sync(rb4xx_cpld->spi, &m); ++} ++EXPORT_SYMBOL_GPL(rb4xx_cpld_read_from); ++ ++#if 0 ++int rb4xx_cpld_read(unsigned char *buf, unsigned char *verify_buf, ++ unsigned count) ++{ ++ struct spi_transfer t[2]; ++ struct spi_message m; ++ unsigned char cmd[2]; ++ ++ if (rb4xx_cpld == NULL) ++ return -ENODEV; ++ ++ spi_message_init(&m); ++ memset(&t, 0, sizeof(t)); ++ ++ /* send command */ ++ t[0].tx_buf = cmd; ++ t[0].len = sizeof(cmd); ++ spi_message_add_tail(&t[0], &m); ++ ++ cmd[0] = CPLD_CMD_READ_NAND; ++ cmd[1] = 0; ++ ++ /* read data */ ++ t[1].rx_buf = buf; ++ t[1].len = count; ++ spi_message_add_tail(&t[1], &m); ++ ++ return spi_sync(rb4xx_cpld->spi, &m); ++} ++#else ++int rb4xx_cpld_read(unsigned char *rx_buf, const unsigned char *verify_buf, ++ unsigned count) ++{ ++ static const unsigned char cmd[2] = { CPLD_CMD_READ_NAND, 0 }; ++ struct spi_transfer t[2] = { ++ { ++ .tx_buf = &cmd, ++ .len = 2, ++ }, { ++ .tx_buf = verify_buf, ++ .rx_buf = rx_buf, ++ .len = count, ++ .verify = (verify_buf != NULL), ++ }, ++ }; ++ struct spi_message m; ++ ++ if (rb4xx_cpld == NULL) ++ return -ENODEV; ++ ++ spi_message_init(&m); ++ spi_message_add_tail(&t[0], &m); ++ spi_message_add_tail(&t[1], &m); ++ return spi_sync(rb4xx_cpld->spi, &m); ++} ++#endif ++EXPORT_SYMBOL_GPL(rb4xx_cpld_read); ++ ++int rb4xx_cpld_write(const unsigned char *buf, unsigned count) ++{ ++#if 0 ++ struct spi_transfer t[3]; ++ struct spi_message m; ++ unsigned char cmd[1]; ++ ++ if (rb4xx_cpld == NULL) ++ return -ENODEV; ++ ++ memset(&t, 0, sizeof(t)); ++ spi_message_init(&m); ++ ++ /* send command */ ++ t[0].tx_buf = cmd; ++ t[0].len = sizeof(cmd); ++ spi_message_add_tail(&t[0], &m); ++ ++ cmd[0] = CPLD_CMD_WRITE_NAND; ++ ++ /* write data */ ++ t[1].tx_buf = buf; ++ t[1].len = count; ++ spi_message_add_tail(&t[1], &m); ++ ++ /* send idle */ ++ t[2].len = 1; ++ spi_message_add_tail(&t[2], &m); ++ ++ return spi_sync(rb4xx_cpld->spi, &m); ++#else ++ static const unsigned char cmd = CPLD_CMD_WRITE_NAND; ++ struct spi_transfer t[3] = { ++ { ++ .tx_buf = &cmd, ++ .len = 1, ++ }, { ++ .tx_buf = buf, ++ .len = count, ++ .fast_write = 1, ++ }, { ++ .len = 1, ++ .fast_write = 1, ++ }, ++ }; ++ struct spi_message m; ++ ++ if (rb4xx_cpld == NULL) ++ return -ENODEV; ++ ++ spi_message_init(&m); ++ spi_message_add_tail(&t[0], &m); ++ spi_message_add_tail(&t[1], &m); ++ spi_message_add_tail(&t[2], &m); ++ return spi_sync(rb4xx_cpld->spi, &m); ++#endif ++} ++EXPORT_SYMBOL_GPL(rb4xx_cpld_write); ++ ++static int rb4xx_cpld_gpio_get(struct gpio_chip *chip, unsigned offset) ++{ ++ struct rb4xx_cpld *cpld = gpio_to_cpld(chip); ++ int ret; ++ ++ mutex_lock(&cpld->lock); ++ ret = (cpld->config >> offset) & 1; ++ mutex_unlock(&cpld->lock); ++ ++ return ret; ++} ++ ++static void rb4xx_cpld_gpio_set(struct gpio_chip *chip, unsigned offset, ++ int value) ++{ ++ struct rb4xx_cpld *cpld = gpio_to_cpld(chip); ++ ++ mutex_lock(&cpld->lock); ++ __rb4xx_cpld_change_cfg(cpld, (1 << offset), !!value << offset); ++ mutex_unlock(&cpld->lock); ++} ++ ++static int rb4xx_cpld_gpio_direction_input(struct gpio_chip *chip, ++ unsigned offset) ++{ ++ return -EOPNOTSUPP; ++} ++ ++static int rb4xx_cpld_gpio_direction_output(struct gpio_chip *chip, ++ unsigned offset, ++ int value) ++{ ++ struct rb4xx_cpld *cpld = gpio_to_cpld(chip); ++ int ret; ++ ++ mutex_lock(&cpld->lock); ++ ret = __rb4xx_cpld_change_cfg(cpld, (1 << offset), !!value << offset); ++ mutex_unlock(&cpld->lock); ++ ++ return ret; ++} ++ ++static int rb4xx_cpld_gpio_init(struct rb4xx_cpld *cpld, unsigned int base) ++{ ++ int err; ++ ++ /* init config */ ++ cpld->config = CPLD_CFG_nLED1 | CPLD_CFG_nLED2 | CPLD_CFG_nLED3 | ++ CPLD_CFG_nLED4 | CPLD_CFG_nCE; ++ rb4xx_cpld_write_cfg(cpld, cpld->config); ++ ++ /* setup GPIO chip */ ++ cpld->chip.label = DRV_NAME; ++ ++ cpld->chip.get = rb4xx_cpld_gpio_get; ++ cpld->chip.set = rb4xx_cpld_gpio_set; ++ cpld->chip.direction_input = rb4xx_cpld_gpio_direction_input; ++ cpld->chip.direction_output = rb4xx_cpld_gpio_direction_output; ++ ++ cpld->chip.base = base; ++ cpld->chip.ngpio = CPLD_NUM_GPIOS; ++ cpld->chip.can_sleep = 1; ++ cpld->chip.dev = &cpld->spi->dev; ++ cpld->chip.owner = THIS_MODULE; ++ ++ err = gpiochip_add(&cpld->chip); ++ if (err) ++ dev_err(&cpld->spi->dev, "adding GPIO chip failed, err=%d\n", ++ err); ++ ++ return err; ++} ++ ++static int __devinit rb4xx_cpld_probe(struct spi_device *spi) ++{ ++ struct rb4xx_cpld *cpld; ++ struct rb4xx_cpld_platform_data *pdata; ++ int err; ++ ++ pdata = spi->dev.platform_data; ++ if (!pdata) { ++ dev_dbg(&spi->dev, "no platform data\n"); ++ return -EINVAL; ++ } ++ ++ cpld = kzalloc(sizeof(*cpld), GFP_KERNEL); ++ if (!cpld) { ++ dev_err(&spi->dev, "no memory for private data\n"); ++ return -ENOMEM; ++ } ++ ++ mutex_init(&cpld->lock); ++ cpld->spi = spi_dev_get(spi); ++ dev_set_drvdata(&spi->dev, cpld); ++ ++ spi->mode = SPI_MODE_0; ++ spi->bits_per_word = 8; ++ err = spi_setup(spi); ++ if (err) { ++ dev_err(&spi->dev, "spi_setup failed, err=%d\n", err); ++ goto err_drvdata; ++ } ++ ++ err = rb4xx_cpld_gpio_init(cpld, pdata->gpio_base); ++ if (err) ++ goto err_drvdata; ++ ++ rb4xx_cpld = cpld; ++ ++ return 0; ++ ++err_drvdata: ++ dev_set_drvdata(&spi->dev, NULL); ++ kfree(cpld); ++ ++ return err; ++} ++ ++static int __devexit rb4xx_cpld_remove(struct spi_device *spi) ++{ ++ struct rb4xx_cpld *cpld; ++ ++ rb4xx_cpld = NULL; ++ cpld = dev_get_drvdata(&spi->dev); ++ dev_set_drvdata(&spi->dev, NULL); ++ kfree(cpld); ++ ++ return 0; ++} ++ ++static struct spi_driver rb4xx_cpld_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .bus = &spi_bus_type, ++ .owner = THIS_MODULE, ++ }, ++ .probe = rb4xx_cpld_probe, ++ .remove = __devexit_p(rb4xx_cpld_remove), ++}; ++ ++static int __init rb4xx_cpld_init(void) ++{ ++ return spi_register_driver(&rb4xx_cpld_driver); ++} ++module_init(rb4xx_cpld_init); ++ ++static void __exit rb4xx_cpld_exit(void) ++{ ++ spi_unregister_driver(&rb4xx_cpld_driver); ++} ++module_exit(rb4xx_cpld_exit); ++ ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.39.orig/drivers/spi/spi_vsc7385.c linux-2.6.39/drivers/spi/spi_vsc7385.c +--- linux-2.6.39.orig/drivers/spi/spi_vsc7385.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/spi/spi_vsc7385.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,621 @@ ++/* ++ * SPI driver for the Vitesse VSC7385 ethernet switch ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRV_NAME "spi-vsc7385" ++#define DRV_DESC "Vitesse VSC7385 Gbit ethernet switch driver" ++#define DRV_VERSION "0.1.0" ++ ++#define VSC73XX_BLOCK_MAC 0x1 ++#define VSC73XX_BLOCK_2 0x2 ++#define VSC73XX_BLOCK_MII 0x3 ++#define VSC73XX_BLOCK_4 0x4 ++#define VSC73XX_BLOCK_5 0x5 ++#define VSC73XX_BLOCK_SYSTEM 0x7 ++ ++#define VSC73XX_SUBBLOCK_PORT_0 0 ++#define VSC73XX_SUBBLOCK_PORT_1 1 ++#define VSC73XX_SUBBLOCK_PORT_2 2 ++#define VSC73XX_SUBBLOCK_PORT_3 3 ++#define VSC73XX_SUBBLOCK_PORT_4 4 ++#define VSC73XX_SUBBLOCK_PORT_MAC 6 ++ ++/* MAC Block registers */ ++#define VSC73XX_MAC_CFG 0x0 ++#define VSC73XX_ADVPORTM 0x19 ++#define VSC73XX_RXOCT 0x50 ++#define VSC73XX_TXOCT 0x51 ++#define VSC73XX_C_RX0 0x52 ++#define VSC73XX_C_RX1 0x53 ++#define VSC73XX_C_RX2 0x54 ++#define VSC73XX_C_TX0 0x55 ++#define VSC73XX_C_TX1 0x56 ++#define VSC73XX_C_TX2 0x57 ++#define VSC73XX_C_CFG 0x58 ++ ++/* MAC_CFG register bits */ ++#define VSC73XX_MAC_CFG_WEXC_DIS (1 << 31) ++#define VSC73XX_MAC_CFG_PORT_RST (1 << 29) ++#define VSC73XX_MAC_CFG_TX_EN (1 << 28) ++#define VSC73XX_MAC_CFG_SEED_LOAD (1 << 27) ++#define VSC73XX_MAC_CFG_FDX (1 << 18) ++#define VSC73XX_MAC_CFG_GIGE (1 << 17) ++#define VSC73XX_MAC_CFG_RX_EN (1 << 16) ++#define VSC73XX_MAC_CFG_VLAN_DBLAWR (1 << 15) ++#define VSC73XX_MAC_CFG_VLAN_AWR (1 << 14) ++#define VSC73XX_MAC_CFG_100_BASE_T (1 << 13) ++#define VSC73XX_MAC_CFG_TX_IPG(x) (((x) & 0x1f) << 6) ++#define VSC73XX_MAC_CFG_MAC_RX_RST (1 << 5) ++#define VSC73XX_MAC_CFG_MAC_TX_RST (1 << 4) ++#define VSC73XX_MAC_CFG_BIT2 (1 << 2) ++#define VSC73XX_MAC_CFG_CLK_SEL(x) ((x) & 0x3) ++ ++/* ADVPORTM register bits */ ++#define VSC73XX_ADVPORTM_IFG_PPM (1 << 7) ++#define VSC73XX_ADVPORTM_EXC_COL_CONT (1 << 6) ++#define VSC73XX_ADVPORTM_EXT_PORT (1 << 5) ++#define VSC73XX_ADVPORTM_INV_GTX (1 << 4) ++#define VSC73XX_ADVPORTM_ENA_GTX (1 << 3) ++#define VSC73XX_ADVPORTM_DDR_MODE (1 << 2) ++#define VSC73XX_ADVPORTM_IO_LOOPBACK (1 << 1) ++#define VSC73XX_ADVPORTM_HOST_LOOPBACK (1 << 0) ++ ++/* MII Block registers */ ++#define VSC73XX_MII_STAT 0x0 ++#define VSC73XX_MII_CMD 0x1 ++#define VSC73XX_MII_DATA 0x2 ++ ++/* System Block registers */ ++#define VSC73XX_ICPU_SIPAD 0x01 ++#define VSC73XX_ICPU_CLOCK_DELAY 0x05 ++#define VSC73XX_ICPU_CTRL 0x10 ++#define VSC73XX_ICPU_ADDR 0x11 ++#define VSC73XX_ICPU_SRAM 0x12 ++#define VSC73XX_ICPU_MBOX_VAL 0x15 ++#define VSC73XX_ICPU_MBOX_SET 0x16 ++#define VSC73XX_ICPU_MBOX_CLR 0x17 ++#define VSC73XX_ICPU_CHIPID 0x18 ++#define VSC73XX_ICPU_GPIO 0x34 ++ ++#define VSC73XX_ICPU_CTRL_CLK_DIV (1 << 8) ++#define VSC73XX_ICPU_CTRL_SRST_HOLD (1 << 7) ++#define VSC73XX_ICPU_CTRL_BOOT_EN (1 << 3) ++#define VSC73XX_ICPU_CTRL_EXT_ACC_EN (1 << 2) ++#define VSC73XX_ICPU_CTRL_CLK_EN (1 << 1) ++#define VSC73XX_ICPU_CTRL_SRST (1 << 0) ++ ++#define VSC73XX_ICPU_CHIPID_ID_SHIFT 12 ++#define VSC73XX_ICPU_CHIPID_ID_MASK 0xffff ++#define VSC73XX_ICPU_CHIPID_REV_SHIFT 28 ++#define VSC73XX_ICPU_CHIPID_REV_MASK 0xf ++#define VSC73XX_ICPU_CHIPID_ID_7385 0x7385 ++#define VSC73XX_ICPU_CHIPID_ID_7395 0x7395 ++ ++#define VSC73XX_CMD_MODE_READ 0 ++#define VSC73XX_CMD_MODE_WRITE 1 ++#define VSC73XX_CMD_MODE_SHIFT 4 ++#define VSC73XX_CMD_BLOCK_SHIFT 5 ++#define VSC73XX_CMD_BLOCK_MASK 0x7 ++#define VSC73XX_CMD_SUBBLOCK_MASK 0xf ++ ++#define VSC7385_CLOCK_DELAY ((3 << 4) | 3) ++#define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) ++ ++#define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ ++ VSC73XX_ICPU_CTRL_BOOT_EN | \ ++ VSC73XX_ICPU_CTRL_EXT_ACC_EN) ++ ++#define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ ++ VSC73XX_ICPU_CTRL_BOOT_EN | \ ++ VSC73XX_ICPU_CTRL_CLK_EN | \ ++ VSC73XX_ICPU_CTRL_SRST) ++ ++#define VSC7385_ADVPORTM_MASK (VSC73XX_ADVPORTM_IFG_PPM | \ ++ VSC73XX_ADVPORTM_EXC_COL_CONT | \ ++ VSC73XX_ADVPORTM_EXT_PORT | \ ++ VSC73XX_ADVPORTM_INV_GTX | \ ++ VSC73XX_ADVPORTM_ENA_GTX | \ ++ VSC73XX_ADVPORTM_DDR_MODE | \ ++ VSC73XX_ADVPORTM_IO_LOOPBACK | \ ++ VSC73XX_ADVPORTM_HOST_LOOPBACK) ++ ++#define VSC7385_ADVPORTM_INIT (VSC73XX_ADVPORTM_EXT_PORT | \ ++ VSC73XX_ADVPORTM_ENA_GTX | \ ++ VSC73XX_ADVPORTM_DDR_MODE) ++ ++#define VSC7385_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ ++ VSC73XX_MAC_CFG_MAC_RX_RST | \ ++ VSC73XX_MAC_CFG_MAC_TX_RST) ++ ++#define VSC73XX_MAC_CFG_INIT (VSC73XX_MAC_CFG_TX_EN | \ ++ VSC73XX_MAC_CFG_FDX | \ ++ VSC73XX_MAC_CFG_GIGE | \ ++ VSC73XX_MAC_CFG_RX_EN) ++ ++#define VSC73XX_RESET_DELAY 100 ++ ++struct vsc7385 { ++ struct spi_device *spi; ++ struct mutex lock; ++ struct vsc7385_platform_data *pdata; ++}; ++ ++static int vsc7385_is_addr_valid(u8 block, u8 subblock) ++{ ++ switch (block) { ++ case VSC73XX_BLOCK_MAC: ++ switch (subblock) { ++ case 0 ... 4: ++ case 6: ++ return 1; ++ } ++ break; ++ ++ case VSC73XX_BLOCK_2: ++ case VSC73XX_BLOCK_SYSTEM: ++ switch (subblock) { ++ case 0: ++ return 1; ++ } ++ break; ++ ++ case VSC73XX_BLOCK_MII: ++ case VSC73XX_BLOCK_4: ++ case VSC73XX_BLOCK_5: ++ switch (subblock) { ++ case 0 ... 1: ++ return 1; ++ } ++ break; ++ } ++ ++ return 0; ++} ++ ++static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock) ++{ ++ u8 ret; ++ ++ ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT; ++ ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT; ++ ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK; ++ ++ return ret; ++} ++ ++static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, ++ u32 *value) ++{ ++ u8 cmd[4]; ++ u8 buf[4]; ++ struct spi_transfer t[2]; ++ struct spi_message m; ++ int err; ++ ++ if (!vsc7385_is_addr_valid(block, subblock)) ++ return -EINVAL; ++ ++ spi_message_init(&m); ++ ++ memset(&t, 0, sizeof(t)); ++ ++ t[0].tx_buf = cmd; ++ t[0].len = sizeof(cmd); ++ spi_message_add_tail(&t[0], &m); ++ ++ t[1].rx_buf = buf; ++ t[1].len = sizeof(buf); ++ spi_message_add_tail(&t[1], &m); ++ ++ cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock); ++ cmd[1] = reg; ++ cmd[2] = 0; ++ cmd[3] = 0; ++ ++ mutex_lock(&vsc->lock); ++ err = spi_sync(vsc->spi, &m); ++ mutex_unlock(&vsc->lock); ++ ++ if (err) ++ return err; ++ ++ *value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) | ++ (((u32) buf[2]) << 8) | ((u32) buf[3]); ++ ++ return 0; ++} ++ ++ ++static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, ++ u32 value) ++{ ++ u8 cmd[2]; ++ u8 buf[4]; ++ struct spi_transfer t[2]; ++ struct spi_message m; ++ int err; ++ ++ if (!vsc7385_is_addr_valid(block, subblock)) ++ return -EINVAL; ++ ++ spi_message_init(&m); ++ ++ memset(&t, 0, sizeof(t)); ++ ++ t[0].tx_buf = cmd; ++ t[0].len = sizeof(cmd); ++ spi_message_add_tail(&t[0], &m); ++ ++ t[1].tx_buf = buf; ++ t[1].len = sizeof(buf); ++ spi_message_add_tail(&t[1], &m); ++ ++ cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock); ++ cmd[1] = reg; ++ ++ buf[0] = (value >> 24) & 0xff; ++ buf[1] = (value >> 16) & 0xff; ++ buf[2] = (value >> 8) & 0xff; ++ buf[3] = value & 0xff; ++ ++ mutex_lock(&vsc->lock); ++ err = spi_sync(vsc->spi, &m); ++ mutex_unlock(&vsc->lock); ++ ++ return err; ++} ++ ++static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block, ++ u8 subblock, u8 reg, u32 value, ++ u32 read_mask, u32 read_val) ++{ ++ struct spi_device *spi = vsc->spi; ++ u32 t; ++ int err; ++ ++ err = vsc7385_write(vsc, block, subblock, reg, value); ++ if (err) ++ return err; ++ ++ err = vsc7385_read(vsc, block, subblock, reg, &t); ++ if (err) ++ return err; ++ ++ if ((t & read_mask) != read_val) { ++ dev_err(&spi->dev, "register write error\n"); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val) ++{ ++ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_CLOCK_DELAY, val); ++} ++ ++static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val) ++{ ++ return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_CLOCK_DELAY, val); ++} ++ ++static inline int vsc7385_icpu_stop(struct vsc7385 *vsc) ++{ ++ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, ++ VSC73XX_ICPU_CTRL_STOP); ++} ++ ++static inline int vsc7385_icpu_start(struct vsc7385 *vsc) ++{ ++ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, ++ VSC73XX_ICPU_CTRL_START); ++} ++ ++static inline int vsc7385_icpu_reset(struct vsc7385 *vsc) ++{ ++ int rc; ++ ++ rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR, ++ 0x0000); ++ if (rc) ++ dev_err(&vsc->spi->dev, ++ "could not reset microcode, err=%d\n", rc); ++ ++ return rc; ++} ++ ++static int vsc7385_upload_ucode(struct vsc7385 *vsc) ++{ ++ struct spi_device *spi = vsc->spi; ++ const struct firmware *firmware; ++ char *ucode_name; ++ unsigned char *dp; ++ unsigned int curVal; ++ int i; ++ int diffs; ++ int rc; ++ ++ ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name ++ : "vsc7385_ucode.bin"; ++ rc = request_firmware(&firmware, ucode_name, &spi->dev); ++ if (rc) { ++ dev_err(&spi->dev, "request_firmware failed, err=%d\n", ++ rc); ++ return rc; ++ } ++ ++ rc = vsc7385_icpu_stop(vsc); ++ if (rc) ++ goto out; ++ ++ rc = vsc7385_icpu_reset(vsc); ++ if (rc) ++ goto out; ++ ++ dev_info(&spi->dev, "uploading microcode...\n"); ++ ++ dp = (unsigned char *) firmware->data; ++ for (i = 0; i < firmware->size; i++) { ++ rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_SRAM, *dp++); ++ if (rc) { ++ dev_err(&spi->dev, "could not load microcode, err=%d\n", ++ rc); ++ goto out; ++ } ++ } ++ ++ rc = vsc7385_icpu_reset(vsc); ++ if (rc) ++ goto out; ++ ++ dev_info(&spi->dev, "verifying microcode...\n"); ++ ++ dp = (unsigned char *) firmware->data; ++ diffs = 0; ++ for (i = 0; i < firmware->size; i++) { ++ rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_SRAM, &curVal); ++ if (rc) { ++ dev_err(&spi->dev, "could not read microcode %d\n", ++ rc); ++ goto out; ++ } ++ ++ if (curVal > 0xff) { ++ dev_err(&spi->dev, "bad val read: %04x : %02x %02x\n", ++ i, *dp, curVal); ++ rc = -EIO; ++ goto out; ++ } ++ ++ if ((curVal & 0xff) != *dp) { ++ diffs++; ++ dev_err(&spi->dev, "verify error: %04x : %02x %02x\n", ++ i, *dp, curVal); ++ ++ if (diffs > 4) ++ break; ++ } ++ dp++; ++ } ++ ++ if (diffs) { ++ dev_err(&spi->dev, "microcode verification failed\n"); ++ rc = -EIO; ++ goto out; ++ } ++ ++ dev_info(&spi->dev, "microcode uploaded\n"); ++ ++ rc = vsc7385_icpu_start(vsc); ++ ++out: ++ release_firmware(firmware); ++ return rc; ++} ++ ++static int vsc7385_setup(struct vsc7385 *vsc) ++{ ++ struct vsc7385_platform_data *pdata = vsc->pdata; ++ u32 t; ++ int err; ++ ++ err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_CLOCK_DELAY, ++ VSC7385_CLOCK_DELAY, ++ VSC7385_CLOCK_DELAY_MASK, ++ VSC7385_CLOCK_DELAY); ++ if (err) ++ goto err; ++ ++ err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC, ++ VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM, ++ VSC7385_ADVPORTM_INIT, ++ VSC7385_ADVPORTM_MASK, ++ VSC7385_ADVPORTM_INIT); ++ if (err) ++ goto err; ++ ++ err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, ++ VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET); ++ if (err) ++ goto err; ++ ++ t = VSC73XX_MAC_CFG_INIT; ++ t |= VSC73XX_MAC_CFG_TX_IPG(pdata->mac_cfg.tx_ipg); ++ t |= VSC73XX_MAC_CFG_CLK_SEL(pdata->mac_cfg.clk_sel); ++ if (pdata->mac_cfg.bit2) ++ t |= VSC73XX_MAC_CFG_BIT2; ++ ++ err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, ++ VSC73XX_MAC_CFG, t); ++ if (err) ++ goto err; ++ ++ return 0; ++ ++err: ++ return err; ++} ++ ++static int vsc7385_detect(struct vsc7385 *vsc) ++{ ++ struct spi_device *spi = vsc->spi; ++ u32 t; ++ u32 id; ++ u32 rev; ++ int err; ++ ++ err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_MBOX_VAL, &t); ++ if (err) { ++ dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err); ++ return err; ++ } ++ ++ if (t == 0xffffffff) { ++ dev_dbg(&spi->dev, "assert chip reset\n"); ++ if (vsc->pdata->reset) ++ vsc->pdata->reset(); ++ ++ } ++ ++ err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_CHIPID, &t); ++ if (err) { ++ dev_err(&spi->dev, "unable to read chip id, err=%d\n", err); ++ return err; ++ } ++ ++ id = (t >> VSC73XX_ICPU_CHIPID_ID_SHIFT) & VSC73XX_ICPU_CHIPID_ID_MASK; ++ switch (id) { ++ case VSC73XX_ICPU_CHIPID_ID_7385: ++ case VSC73XX_ICPU_CHIPID_ID_7395: ++ break; ++ default: ++ dev_err(&spi->dev, "unsupported chip, id=%04x\n", id); ++ return -ENODEV; ++ } ++ ++ rev = (t >> VSC73XX_ICPU_CHIPID_REV_SHIFT) & ++ VSC73XX_ICPU_CHIPID_REV_MASK; ++ dev_info(&spi->dev, "VSC%04X (rev. %d) switch found\n", id, rev); ++ ++ return 0; ++} ++ ++static int __devinit vsc7385_probe(struct spi_device *spi) ++{ ++ struct vsc7385 *vsc; ++ struct vsc7385_platform_data *pdata; ++ int err; ++ ++ printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n"); ++ ++ pdata = spi->dev.platform_data; ++ if (!pdata) { ++ dev_err(&spi->dev, "no platform data specified\n"); ++ return -ENODEV; ++ } ++ ++ vsc = kzalloc(sizeof(*vsc), GFP_KERNEL); ++ if (!vsc) { ++ dev_err(&spi->dev, "no memory for private data\n"); ++ return -ENOMEM; ++ } ++ ++ mutex_init(&vsc->lock); ++ vsc->pdata = pdata; ++ vsc->spi = spi_dev_get(spi); ++ dev_set_drvdata(&spi->dev, vsc); ++ ++ spi->mode = SPI_MODE_0; ++ spi->bits_per_word = 8; ++ err = spi_setup(spi); ++ if (err) { ++ dev_err(&spi->dev, "spi_setup failed, err=%d\n", err); ++ goto err_drvdata; ++ } ++ ++ err = vsc7385_detect(vsc); ++ if (err) { ++ dev_err(&spi->dev, "no chip found, err=%d\n", err); ++ goto err_drvdata; ++ } ++ ++ err = vsc7385_upload_ucode(vsc); ++ if (err) ++ goto err_drvdata; ++ ++ err = vsc7385_setup(vsc); ++ if (err) ++ goto err_drvdata; ++ ++ return 0; ++ ++err_drvdata: ++ dev_set_drvdata(&spi->dev, NULL); ++ kfree(vsc); ++ return err; ++} ++ ++static int __devexit vsc7385_remove(struct spi_device *spi) ++{ ++ struct vsc7385_data *vsc; ++ ++ vsc = dev_get_drvdata(&spi->dev); ++ dev_set_drvdata(&spi->dev, NULL); ++ kfree(vsc); ++ ++ return 0; ++} ++ ++static struct spi_driver vsc7385_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .bus = &spi_bus_type, ++ .owner = THIS_MODULE, ++ }, ++ .probe = vsc7385_probe, ++ .remove = __devexit_p(vsc7385_remove), ++}; ++ ++static int __init vsc7385_init(void) ++{ ++ return spi_register_driver(&vsc7385_driver); ++} ++module_init(vsc7385_init); ++ ++static void __exit vsc7385_exit(void) ++{ ++ spi_unregister_driver(&vsc7385_driver); ++} ++module_exit(vsc7385_exit); ++ ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); ++ +diff -Nur linux-2.6.39.orig/drivers/tty/serial/ar933x_uart.c linux-2.6.39/drivers/tty/serial/ar933x_uart.c +--- linux-2.6.39.orig/drivers/tty/serial/ar933x_uart.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/tty/serial/ar933x_uart.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,688 @@ ++/* ++ * Atheros AR933X SoC built-in UART driver ++ * ++ * Copyright (C) 2011 Gabor Juhos ++ * ++ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define DRIVER_NAME "ar933x-uart" ++ ++#define AR933X_DUMMY_STATUS_RD 0x01 ++ ++static struct uart_driver ar933x_uart_driver; ++ ++struct ar933x_uart_port { ++ struct uart_port port; ++ unsigned int ier; /* shadow Interrupt Enable Register */ ++}; ++ ++static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up, ++ int offset) ++{ ++ return readl(up->port.membase + offset); ++} ++ ++static inline void ar933x_uart_write(struct ar933x_uart_port *up, ++ int offset, unsigned int value) ++{ ++ writel(value, up->port.membase + offset); ++} ++ ++static inline void ar933x_uart_rmw(struct ar933x_uart_port *up, ++ unsigned int offset, ++ unsigned int mask, ++ unsigned int val) ++{ ++ unsigned int t; ++ ++ t = ar933x_uart_read(up, offset); ++ t &= ~mask; ++ t |= val; ++ ar933x_uart_write(up, offset, t); ++} ++ ++static inline void ar933x_uart_rmw_set(struct ar933x_uart_port *up, ++ unsigned int offset, ++ unsigned int val) ++{ ++ ar933x_uart_rmw(up, offset, 0, val); ++} ++ ++static inline void ar933x_uart_rmw_clear(struct ar933x_uart_port *up, ++ unsigned int offset, ++ unsigned int val) ++{ ++ ar933x_uart_rmw(up, offset, val, 0); ++} ++ ++static inline void ar933x_uart_start_tx_interrupt(struct ar933x_uart_port *up) ++{ ++ up->ier |= AR933X_UART_INT_TX_EMPTY; ++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); ++} ++ ++static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up) ++{ ++ up->ier &= ~AR933X_UART_INT_TX_EMPTY; ++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); ++} ++ ++static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch) ++{ ++ unsigned int rdata; ++ ++ rdata = ch & AR933X_UART_DATA_TX_RX_MASK; ++ rdata |= AR933X_UART_DATA_TX_CSR; ++ ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata); ++} ++ ++static unsigned int ar933x_uart_tx_empty(struct uart_port *port) ++{ ++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; ++ unsigned long flags; ++ unsigned int rdata; ++ ++ spin_lock_irqsave(&up->port.lock, flags); ++ rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); ++ spin_unlock_irqrestore(&up->port.lock, flags); ++ ++ return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT; ++} ++ ++static unsigned int ar933x_uart_get_mctrl(struct uart_port *port) ++{ ++ return TIOCM_CAR; ++} ++ ++static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) ++{ ++} ++ ++static void ar933x_uart_start_tx(struct uart_port *port) ++{ ++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; ++ ++ ar933x_uart_start_tx_interrupt(up); ++} ++ ++static void ar933x_uart_stop_tx(struct uart_port *port) ++{ ++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; ++ ++ ar933x_uart_stop_tx_interrupt(up); ++} ++ ++static void ar933x_uart_stop_rx(struct uart_port *port) ++{ ++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; ++ ++ up->ier &= ~AR933X_UART_INT_RX_VALID; ++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); ++} ++ ++static void ar933x_uart_break_ctl(struct uart_port *port, int break_state) ++{ ++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&up->port.lock, flags); ++ if (break_state == -1) ++ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, ++ AR933X_UART_CS_TX_BREAK); ++ else ++ ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG, ++ AR933X_UART_CS_TX_BREAK); ++ spin_unlock_irqrestore(&up->port.lock, flags); ++} ++ ++static void ar933x_uart_enable_ms(struct uart_port *port) ++{ ++} ++ ++static void ar933x_uart_set_termios(struct uart_port *port, ++ struct ktermios *new, ++ struct ktermios *old) ++{ ++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; ++ unsigned int cs; ++ unsigned long flags; ++ unsigned int baud, scale; ++ ++ /* Only CS8 is supported */ ++ new->c_cflag &= ~CSIZE; ++ new->c_cflag |= CS8; ++ ++ /* Only one stop bit is supported */ ++ new->c_cflag &= ~CSTOPB; ++ ++ cs = 0; ++ if (new->c_cflag & PARENB) { ++ if (!(new->c_cflag & PARODD)) ++ cs |= AR933X_UART_CS_PARITY_EVEN; ++ else ++ cs |= AR933X_UART_CS_PARITY_ODD; ++ } else { ++ cs |= AR933X_UART_CS_PARITY_NONE; ++ } ++ ++ /* Mark/space parity is not supported */ ++ new->c_cflag &= ~CMSPAR; ++ ++ baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); ++ scale = (port->uartclk / (16 * baud)) - 1; ++ ++ /* ++ * Ok, we're now changing the port state. Do it with ++ * interrupts disabled. ++ */ ++ spin_lock_irqsave(&up->port.lock, flags); ++ ++ /* Update the per-port timeout. */ ++ uart_update_timeout(port, new->c_cflag, baud); ++ ++ up->port.ignore_status_mask = 0; ++ ++ /* ignore all characters if CREAD is not set */ ++ if ((new->c_cflag & CREAD) == 0) ++ up->port.ignore_status_mask |= AR933X_DUMMY_STATUS_RD; ++ ++ ar933x_uart_write(up, AR933X_UART_CLOCK_REG, ++ scale << AR933X_UART_CLOCK_SCALE_S | 8192); ++ ++ /* setup configuration register */ ++ ar933x_uart_rmw(up, AR933X_UART_CS_REG, AR933X_UART_CS_PARITY_M, cs); ++ ++ /* enable host interrupt */ ++ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, ++ AR933X_UART_CS_HOST_INT_EN); ++ ++ spin_unlock_irqrestore(&up->port.lock, flags); ++ ++ if (tty_termios_baud_rate(new)) ++ tty_termios_encode_baud_rate(new, baud, baud); ++} ++ ++static void ar933x_uart_rx_chars(struct ar933x_uart_port *up) ++{ ++ struct tty_struct *tty; ++ int max_count = 256; ++ ++ tty = tty_port_tty_get(&up->port.state->port); ++ do { ++ unsigned int rdata; ++ unsigned char ch; ++ ++ rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); ++ if ((rdata & AR933X_UART_DATA_RX_CSR) == 0) ++ break; ++ ++ /* remove the character from the FIFO */ ++ ar933x_uart_write(up, AR933X_UART_DATA_REG, ++ AR933X_UART_DATA_RX_CSR); ++ ++ if (!tty) { ++ /* discard the data if no tty available */ ++ continue; ++ } ++ ++ up->port.icount.rx++; ++ ch = rdata & AR933X_UART_DATA_TX_RX_MASK; ++ ++ if (uart_handle_sysrq_char(&up->port, ch)) ++ continue; ++ ++ if ((up->port.ignore_status_mask & AR933X_DUMMY_STATUS_RD) == 0) ++ tty_insert_flip_char(tty, ch, TTY_NORMAL); ++ } while (max_count-- > 0); ++ ++ if (tty) { ++ tty_flip_buffer_push(tty); ++ tty_kref_put(tty); ++ } ++} ++ ++static void ar933x_uart_tx_chars(struct ar933x_uart_port *up) ++{ ++ struct circ_buf *xmit = &up->port.state->xmit; ++ int count; ++ ++ if (uart_tx_stopped(&up->port)) ++ return; ++ ++ count = up->port.fifosize; ++ do { ++ unsigned int rdata; ++ ++ rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); ++ if ((rdata & AR933X_UART_DATA_TX_CSR) == 0) ++ break; ++ ++ if (up->port.x_char) { ++ ar933x_uart_putc(up, up->port.x_char); ++ up->port.icount.tx++; ++ up->port.x_char = 0; ++ continue; ++ } ++ ++ if (uart_circ_empty(xmit)) ++ break; ++ ++ ar933x_uart_putc(up, xmit->buf[xmit->tail]); ++ ++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); ++ up->port.icount.tx++; ++ } while (--count > 0); ++ ++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) ++ uart_write_wakeup(&up->port); ++ ++ if (!uart_circ_empty(xmit)) ++ ar933x_uart_start_tx_interrupt(up); ++} ++ ++static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id) ++{ ++ struct ar933x_uart_port *up = dev_id; ++ unsigned int status; ++ ++ status = ar933x_uart_read(up, AR933X_UART_CS_REG); ++ if ((status & AR933X_UART_CS_HOST_INT) == 0) ++ return IRQ_NONE; ++ ++ spin_lock(&up->port.lock); ++ ++ status = ar933x_uart_read(up, AR933X_UART_INT_REG); ++ status &= ar933x_uart_read(up, AR933X_UART_INT_EN_REG); ++ ++ if (status & AR933X_UART_INT_RX_VALID) { ++ ar933x_uart_write(up, AR933X_UART_INT_REG, ++ AR933X_UART_INT_RX_VALID); ++ ar933x_uart_rx_chars(up); ++ } ++ ++ if (status & AR933X_UART_INT_TX_EMPTY) { ++ ar933x_uart_write(up, AR933X_UART_INT_REG, ++ AR933X_UART_INT_TX_EMPTY); ++ ar933x_uart_stop_tx_interrupt(up); ++ ar933x_uart_tx_chars(up); ++ } ++ ++ spin_unlock(&up->port.lock); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ar933x_uart_startup(struct uart_port *port) ++{ ++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; ++ unsigned long flags; ++ int ret; ++ ++ ret = request_irq(up->port.irq, ar933x_uart_interrupt, ++ up->port.irqflags, dev_name(up->port.dev), up); ++ if (ret) ++ return ret; ++ ++ spin_lock_irqsave(&up->port.lock, flags); ++ ++ /* Enable HOST interrupts */ ++ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, ++ AR933X_UART_CS_HOST_INT_EN); ++ ++ /* Enable RX interrupts */ ++ up->ier = AR933X_UART_INT_RX_VALID; ++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); ++ ++ spin_unlock_irqrestore(&up->port.lock, flags); ++ ++ return 0; ++} ++ ++static void ar933x_uart_shutdown(struct uart_port *port) ++{ ++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; ++ ++ /* Disable all interrupts */ ++ up->ier = 0; ++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); ++ ++ /* Disable break condition */ ++ ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG, ++ AR933X_UART_CS_TX_BREAK); ++ ++ free_irq(up->port.irq, up); ++} ++ ++static const char *ar933x_uart_type(struct uart_port *port) ++{ ++ return (port->type == PORT_AR933X) ? "AR933X UART" : NULL; ++} ++ ++static void ar933x_uart_release_port(struct uart_port *port) ++{ ++ /* Nothing to release ... */ ++} ++ ++static int ar933x_uart_request_port(struct uart_port *port) ++{ ++ /* UARTs always present */ ++ return 0; ++} ++ ++static void ar933x_uart_config_port(struct uart_port *port, int flags) ++{ ++ if (flags & UART_CONFIG_TYPE) ++ port->type = PORT_AR933X; ++} ++ ++static int ar933x_uart_verify_port(struct uart_port *port, ++ struct serial_struct *ser) ++{ ++ if (ser->type != PORT_UNKNOWN && ++ ser->type != PORT_AR933X) ++ return -EINVAL; ++ ++ if (ser->irq < 0 || ser->irq >= NR_IRQS) ++ return -EINVAL; ++ ++ if (ser->baud_base < 28800) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static struct uart_ops ar933x_uart_ops = { ++ .tx_empty = ar933x_uart_tx_empty, ++ .set_mctrl = ar933x_uart_set_mctrl, ++ .get_mctrl = ar933x_uart_get_mctrl, ++ .stop_tx = ar933x_uart_stop_tx, ++ .start_tx = ar933x_uart_start_tx, ++ .stop_rx = ar933x_uart_stop_rx, ++ .enable_ms = ar933x_uart_enable_ms, ++ .break_ctl = ar933x_uart_break_ctl, ++ .startup = ar933x_uart_startup, ++ .shutdown = ar933x_uart_shutdown, ++ .set_termios = ar933x_uart_set_termios, ++ .type = ar933x_uart_type, ++ .release_port = ar933x_uart_release_port, ++ .request_port = ar933x_uart_request_port, ++ .config_port = ar933x_uart_config_port, ++ .verify_port = ar933x_uart_verify_port, ++}; ++ ++#ifdef CONFIG_SERIAL_AR933X_CONSOLE ++ ++static struct ar933x_uart_port * ++ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS]; ++ ++static void ar933x_uart_wait_xmitr(struct ar933x_uart_port *up) ++{ ++ unsigned int status; ++ unsigned int timeout = 60000; ++ ++ /* Wait up to 60ms for the character(s) to be sent. */ ++ do { ++ status = ar933x_uart_read(up, AR933X_UART_DATA_REG); ++ if (--timeout == 0) ++ break; ++ udelay(1); ++ } while ((status & AR933X_UART_DATA_TX_CSR) == 0); ++} ++ ++static void ar933x_uart_console_putchar(struct uart_port *port, int ch) ++{ ++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; ++ ++ ar933x_uart_wait_xmitr(up); ++ ar933x_uart_putc(up, ch); ++} ++ ++static void ar933x_uart_console_write(struct console *co, const char *s, ++ unsigned int count) ++{ ++ struct ar933x_uart_port *up = ar933x_console_ports[co->index]; ++ unsigned long flags; ++ unsigned int int_en; ++ int locked = 1; ++ ++ local_irq_save(flags); ++ ++ if (up->port.sysrq) ++ locked = 0; ++ else if (oops_in_progress) ++ locked = spin_trylock(&up->port.lock); ++ else ++ spin_lock(&up->port.lock); ++ ++ /* ++ * First save the IER then disable the interrupts ++ */ ++ int_en = ar933x_uart_read(up, AR933X_UART_INT_EN_REG); ++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0); ++ ++ uart_console_write(&up->port, s, count, ar933x_uart_console_putchar); ++ ++ /* ++ * Finally, wait for transmitter to become empty ++ * and restore the IER ++ */ ++ ar933x_uart_wait_xmitr(up); ++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, int_en); ++ ++ ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS); ++ ++ if (locked) ++ spin_unlock(&up->port.lock); ++ ++ local_irq_restore(flags); ++} ++ ++static int ar933x_uart_console_setup(struct console *co, char *options) ++{ ++ struct ar933x_uart_port *up; ++ int baud = 115200; ++ int bits = 8; ++ int parity = 'n'; ++ int flow = 'n'; ++ ++ if (co->index < 0 || co->index >= CONFIG_SERIAL_AR933X_NR_UARTS) ++ return -EINVAL; ++ ++ up = ar933x_console_ports[co->index]; ++ if (!up) ++ return -ENODEV; ++ ++ if (options) ++ uart_parse_options(options, &baud, &parity, &bits, &flow); ++ ++ return uart_set_options(&up->port, co, baud, parity, bits, flow); ++} ++ ++static struct console ar933x_uart_console = { ++ .name = "ttyATH", ++ .write = ar933x_uart_console_write, ++ .device = uart_console_device, ++ .setup = ar933x_uart_console_setup, ++ .flags = CON_PRINTBUFFER, ++ .index = -1, ++ .data = &ar933x_uart_driver, ++}; ++ ++static void ar933x_uart_add_console_port(struct ar933x_uart_port *up) ++{ ++ ar933x_console_ports[up->port.line] = up; ++} ++ ++#define AR933X_SERIAL_CONSOLE (&ar933x_uart_console) ++ ++#else ++ ++static inline void ar933x_uart_add_console_port(struct ar933x_uart_port *up) {} ++ ++#define AR933X_SERIAL_CONSOLE NULL ++ ++#endif /* CONFIG_SERIAL_AR933X_CONSOLE */ ++ ++static struct uart_driver ar933x_uart_driver = { ++ .owner = THIS_MODULE, ++ .driver_name = DRIVER_NAME, ++ .dev_name = "ttyATH", ++ .nr = CONFIG_SERIAL_AR933X_NR_UARTS, ++ .cons = AR933X_SERIAL_CONSOLE, ++}; ++ ++static int __devinit ar933x_uart_probe(struct platform_device *pdev) ++{ ++ struct ar933x_uart_platform_data *pdata; ++ struct ar933x_uart_port *up; ++ struct uart_port *port; ++ struct resource *mem_res; ++ struct resource *irq_res; ++ int id; ++ int ret; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata) ++ return -EINVAL; ++ ++ id = pdev->id; ++ if (id == -1) ++ id = 0; ++ ++ if (id > CONFIG_SERIAL_AR933X_NR_UARTS) ++ return -EINVAL; ++ ++ mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!mem_res) { ++ dev_err(&pdev->dev, "no MEM resource\n"); ++ return -EINVAL; ++ } ++ ++ irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (!irq_res) { ++ dev_err(&pdev->dev, "no IRQ resource\n"); ++ return -EINVAL; ++ } ++ ++ up = kzalloc(sizeof(struct ar933x_uart_port), GFP_KERNEL); ++ if (!up) ++ return -ENOMEM; ++ ++ port = &up->port; ++ port->mapbase = mem_res->start; ++ ++ port->membase = ioremap(mem_res->start, AR933X_UART_REGS_SIZE); ++ if (!port->membase) { ++ ret = -ENOMEM; ++ goto err_free_up; ++ } ++ ++ port->line = id; ++ port->irq = irq_res->start; ++ port->dev = &pdev->dev; ++ port->type = PORT_AR933X; ++ port->iotype = UPIO_MEM32; ++ port->uartclk = pdata->uartclk; ++ ++ port->regshift = 2; ++ port->fifosize = AR933X_UART_FIFO_SIZE; ++ port->ops = &ar933x_uart_ops; ++ ++ ar933x_uart_add_console_port(up); ++ ++ ret = uart_add_one_port(&ar933x_uart_driver, &up->port); ++ if (ret) ++ goto err_unmap; ++ ++ platform_set_drvdata(pdev, up); ++ return 0; ++ ++err_unmap: ++ iounmap(up->port.membase); ++err_free_up: ++ kfree(up); ++ return ret; ++} ++ ++static int __devexit ar933x_uart_remove(struct platform_device *pdev) ++{ ++ struct ar933x_uart_port *up; ++ ++ up = platform_get_drvdata(pdev); ++ platform_set_drvdata(pdev, NULL); ++ ++ if (up) { ++ uart_remove_one_port(&ar933x_uart_driver, &up->port); ++ iounmap(up->port.membase); ++ kfree(up); ++ } ++ ++ return 0; ++} ++ ++static struct platform_driver ar933x_uart_platform_driver = { ++ .probe = ar933x_uart_probe, ++ .remove = __devexit_p(ar933x_uart_remove), ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init ar933x_uart_init(void) ++{ ++ int ret; ++ ++ ar933x_uart_driver.nr = CONFIG_SERIAL_AR933X_NR_UARTS; ++ ret = uart_register_driver(&ar933x_uart_driver); ++ if (ret) ++ goto err_out; ++ ++ ret = platform_driver_register(&ar933x_uart_platform_driver); ++ if (ret) ++ goto err_unregister_uart_driver; ++ ++ return 0; ++ ++err_unregister_uart_driver: ++ uart_unregister_driver(&ar933x_uart_driver); ++err_out: ++ return ret; ++} ++ ++static void __exit ar933x_uart_exit(void) ++{ ++ platform_driver_unregister(&ar933x_uart_platform_driver); ++ uart_unregister_driver(&ar933x_uart_driver); ++} ++ ++module_init(ar933x_uart_init); ++module_exit(ar933x_uart_exit); ++ ++MODULE_DESCRIPTION("Atheros AR933X UART driver"); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" DRIVER_NAME); +diff -Nur linux-2.6.39.orig/drivers/usb/host/Kconfig linux-2.6.39/drivers/usb/host/Kconfig +--- linux-2.6.39.orig/drivers/usb/host/Kconfig 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/usb/host/Kconfig 2011-08-24 18:17:24.000000000 +0200 +@@ -129,6 +129,13 @@ + config USB_FSL_MPH_DR_OF + tristate + ++config USB_EHCI_AR71XX ++ bool "USB EHCI support for AR71xx" ++ depends on USB_EHCI_HCD && ATHEROS_AR71XX ++ default y ++ help ++ Support for Atheros AR71xx built-in EHCI controller ++ + config USB_EHCI_FSL + bool "Support for Freescale on-chip EHCI USB controller" + depends on USB_EHCI_HCD && FSL_SOC +@@ -287,6 +294,13 @@ + Enables support for the on-chip OHCI controller on + OMAP3 and later chips. + ++config USB_OHCI_AR71XX ++ bool "USB OHCI support for Atheros AR71xx" ++ depends on USB_OHCI_HCD && ATHEROS_AR71XX ++ default y ++ help ++ Support for Atheros AR71xx built-in OHCI controller ++ + config USB_OHCI_HCD_PPC_SOC + bool "OHCI support for on-chip PPC USB controller" + depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) +diff -Nur linux-2.6.39.orig/drivers/usb/host/ehci-ar71xx.c linux-2.6.39/drivers/usb/host/ehci-ar71xx.c +--- linux-2.6.39.orig/drivers/usb/host/ehci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/usb/host/ehci-ar71xx.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,242 @@ ++/* ++ * Bus Glue for Atheros AR71xx built-in EHCI controller. ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * Copyright (C) 2007 Atheros Communications, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++ ++extern int usb_disabled(void); ++ ++static int ehci_ar71xx_init(struct usb_hcd *hcd) ++{ ++ struct ehci_hcd *ehci = hcd_to_ehci(hcd); ++ int ret; ++ ++ ehci->caps = hcd->regs; ++ ehci->regs = hcd->regs + ++ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); ++ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); ++ ++ ehci->sbrn = 0x20; ++ ehci->has_synopsys_hc_bug = 1; ++ ++ ehci_reset(ehci); ++ ++ ret = ehci_init(hcd); ++ if (ret) ++ return ret; ++ ++ ehci_port_power(ehci, 0); ++ ++ return 0; ++} ++ ++static int ehci_ar91xx_init(struct usb_hcd *hcd) ++{ ++ struct ehci_hcd *ehci = hcd_to_ehci(hcd); ++ int ret; ++ ++ ehci->caps = hcd->regs + 0x100; ++ ehci->regs = hcd->regs + 0x100 + ++ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); ++ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); ++ ++ hcd->has_tt = 1; ++ ehci->sbrn = 0x20; ++ ++ ehci_reset(ehci); ++ ++ ret = ehci_init(hcd); ++ if (ret) ++ return ret; ++ ++ ehci_port_power(ehci, 0); ++ ++ return 0; ++} ++ ++static int ehci_ar71xx_probe(const struct hc_driver *driver, ++ struct usb_hcd **hcd_out, ++ struct platform_device *pdev) ++{ ++ struct usb_hcd *hcd; ++ struct resource *res; ++ int irq; ++ int ret; ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (!res) { ++ dev_dbg(&pdev->dev, "no IRQ specified for %s\n", ++ dev_name(&pdev->dev)); ++ return -ENODEV; ++ } ++ irq = res->start; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_dbg(&pdev->dev, "no base address specified for %s\n", ++ dev_name(&pdev->dev)); ++ return -ENODEV; ++ } ++ ++ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); ++ if (!hcd) ++ return -ENOMEM; ++ ++ hcd->rsrc_start = res->start; ++ hcd->rsrc_len = res->end - res->start + 1; ++ ++ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { ++ dev_dbg(&pdev->dev, "controller already in use\n"); ++ ret = -EBUSY; ++ goto err_put_hcd; ++ } ++ ++ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); ++ if (!hcd->regs) { ++ dev_dbg(&pdev->dev, "error mapping memory\n"); ++ ret = -EFAULT; ++ goto err_release_region; ++ } ++ ++ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); ++ if (ret) ++ goto err_iounmap; ++ ++ return 0; ++ ++err_iounmap: ++ iounmap(hcd->regs); ++ ++err_release_region: ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++err_put_hcd: ++ usb_put_hcd(hcd); ++ return ret; ++} ++ ++static void ehci_ar71xx_remove(struct usb_hcd *hcd, ++ struct platform_device *pdev) ++{ ++ usb_remove_hcd(hcd); ++ iounmap(hcd->regs); ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++ usb_put_hcd(hcd); ++} ++ ++static const struct hc_driver ehci_ar71xx_hc_driver = { ++ .description = hcd_name, ++ .product_desc = "Atheros AR71xx built-in EHCI controller", ++ .hcd_priv_size = sizeof(struct ehci_hcd), ++ ++ .irq = ehci_irq, ++ .flags = HCD_MEMORY | HCD_USB2, ++ ++ .reset = ehci_ar71xx_init, ++ .start = ehci_run, ++ .stop = ehci_stop, ++ .shutdown = ehci_shutdown, ++ ++ .urb_enqueue = ehci_urb_enqueue, ++ .urb_dequeue = ehci_urb_dequeue, ++ .endpoint_disable = ehci_endpoint_disable, ++ .endpoint_reset = ehci_endpoint_reset, ++ ++ .get_frame_number = ehci_get_frame, ++ ++ .hub_status_data = ehci_hub_status_data, ++ .hub_control = ehci_hub_control, ++#ifdef CONFIG_PM ++ .hub_suspend = ehci_hub_suspend, ++ .hub_resume = ehci_hub_resume, ++#endif ++ .relinquish_port = ehci_relinquish_port, ++ .port_handed_over = ehci_port_handed_over, ++ ++ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, ++}; ++ ++static const struct hc_driver ehci_ar91xx_hc_driver = { ++ .description = hcd_name, ++ .product_desc = "Atheros AR91xx built-in EHCI controller", ++ .hcd_priv_size = sizeof(struct ehci_hcd), ++ .irq = ehci_irq, ++ .flags = HCD_MEMORY | HCD_USB2, ++ ++ .reset = ehci_ar91xx_init, ++ .start = ehci_run, ++ .stop = ehci_stop, ++ .shutdown = ehci_shutdown, ++ ++ .urb_enqueue = ehci_urb_enqueue, ++ .urb_dequeue = ehci_urb_dequeue, ++ .endpoint_disable = ehci_endpoint_disable, ++ .endpoint_reset = ehci_endpoint_reset, ++ ++ .get_frame_number = ehci_get_frame, ++ ++ .hub_status_data = ehci_hub_status_data, ++ .hub_control = ehci_hub_control, ++#ifdef CONFIG_PM ++ .hub_suspend = ehci_hub_suspend, ++ .hub_resume = ehci_hub_resume, ++#endif ++ .relinquish_port = ehci_relinquish_port, ++ .port_handed_over = ehci_port_handed_over, ++ ++ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, ++}; ++ ++static int ehci_ar71xx_driver_probe(struct platform_device *pdev) ++{ ++ struct ar71xx_ehci_platform_data *pdata; ++ struct usb_hcd *hcd = NULL; ++ int ret; ++ ++ if (usb_disabled()) ++ return -ENODEV; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata) { ++ dev_err(&pdev->dev, "no platform data specified for %s\n", ++ dev_name(&pdev->dev)); ++ return -ENODEV; ++ } ++ ++ if (pdata->is_ar91xx) ++ ret = ehci_ar71xx_probe(&ehci_ar91xx_hc_driver, &hcd, pdev); ++ else ++ ret = ehci_ar71xx_probe(&ehci_ar71xx_hc_driver, &hcd, pdev); ++ ++ return ret; ++} ++ ++static int ehci_ar71xx_driver_remove(struct platform_device *pdev) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(pdev); ++ ++ ehci_ar71xx_remove(hcd, pdev); ++ return 0; ++} ++ ++MODULE_ALIAS("platform:ar71xx-ehci"); ++ ++static struct platform_driver ehci_ar71xx_driver = { ++ .probe = ehci_ar71xx_driver_probe, ++ .remove = ehci_ar71xx_driver_remove, ++ .driver = { ++ .name = "ar71xx-ehci", ++ } ++}; +diff -Nur linux-2.6.39.orig/drivers/usb/host/ehci-hcd.c linux-2.6.39/drivers/usb/host/ehci-hcd.c +--- linux-2.6.39.orig/drivers/usb/host/ehci-hcd.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/usb/host/ehci-hcd.c 2011-08-24 18:17:24.000000000 +0200 +@@ -1265,6 +1265,11 @@ + #define PLATFORM_DRIVER tegra_ehci_driver + #endif + ++#ifdef CONFIG_USB_EHCI_AR71XX ++#include "ehci-ar71xx.c" ++#define PLATFORM_DRIVER ehci_ar71xx_driver ++#endif ++ + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ + !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ + !defined(XILINX_OF_PLATFORM_DRIVER) +diff -Nur linux-2.6.39.orig/drivers/usb/host/ohci-ar71xx.c linux-2.6.39/drivers/usb/host/ohci-ar71xx.c +--- linux-2.6.39.orig/drivers/usb/host/ohci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/usb/host/ohci-ar71xx.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,165 @@ ++/* ++ * OHCI HCD (Host Controller Driver) for USB. ++ * ++ * Bus Glue for Atheros AR71xx built-in OHCI controller. ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * Copyright (C) 2007 Atheros Communications, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++extern int usb_disabled(void); ++ ++static int usb_hcd_ar71xx_probe(const struct hc_driver *driver, ++ struct platform_device *pdev) ++{ ++ struct usb_hcd *hcd; ++ struct resource *res; ++ int irq; ++ int ret; ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (!res) { ++ dev_dbg(&pdev->dev, "no IRQ specified for %s\n", ++ dev_name(&pdev->dev)); ++ return -ENODEV; ++ } ++ irq = res->start; ++ ++ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); ++ if (!hcd) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_dbg(&pdev->dev, "no base address specified for %s\n", ++ dev_name(&pdev->dev)); ++ ret = -ENODEV; ++ goto err_put_hcd; ++ } ++ hcd->rsrc_start = res->start; ++ hcd->rsrc_len = res->end - res->start + 1; ++ ++ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { ++ dev_dbg(&pdev->dev, "controller already in use\n"); ++ ret = -EBUSY; ++ goto err_put_hcd; ++ } ++ ++ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); ++ if (!hcd->regs) { ++ dev_dbg(&pdev->dev, "error mapping memory\n"); ++ ret = -EFAULT; ++ goto err_release_region; ++ } ++ ++ ohci_hcd_init(hcd_to_ohci(hcd)); ++ ++ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); ++ if (ret) ++ goto err_stop_hcd; ++ ++ return 0; ++ ++err_stop_hcd: ++ iounmap(hcd->regs); ++err_release_region: ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++err_put_hcd: ++ usb_put_hcd(hcd); ++ return ret; ++} ++ ++void usb_hcd_ar71xx_remove(struct usb_hcd *hcd, struct platform_device *pdev) ++{ ++ usb_remove_hcd(hcd); ++ iounmap(hcd->regs); ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++ usb_put_hcd(hcd); ++} ++ ++static int __devinit ohci_ar71xx_start(struct usb_hcd *hcd) ++{ ++ struct ohci_hcd *ohci = hcd_to_ohci(hcd); ++ int ret; ++ ++ ret = ohci_init(ohci); ++ if (ret < 0) ++ return ret; ++ ++ ret = ohci_run(ohci); ++ if (ret < 0) ++ goto err; ++ ++ return 0; ++ ++err: ++ ohci_stop(hcd); ++ return ret; ++} ++ ++static const struct hc_driver ohci_ar71xx_hc_driver = { ++ .description = hcd_name, ++ .product_desc = "Atheros AR71xx built-in OHCI controller", ++ .hcd_priv_size = sizeof(struct ohci_hcd), ++ ++ .irq = ohci_irq, ++ .flags = HCD_USB11 | HCD_MEMORY, ++ ++ .start = ohci_ar71xx_start, ++ .stop = ohci_stop, ++ .shutdown = ohci_shutdown, ++ ++ .urb_enqueue = ohci_urb_enqueue, ++ .urb_dequeue = ohci_urb_dequeue, ++ .endpoint_disable = ohci_endpoint_disable, ++ ++ /* ++ * scheduling support ++ */ ++ .get_frame_number = ohci_get_frame, ++ ++ /* ++ * root hub support ++ */ ++ .hub_status_data = ohci_hub_status_data, ++ .hub_control = ohci_hub_control, ++ .start_port_reset = ohci_start_port_reset, ++}; ++ ++static int ohci_hcd_ar71xx_drv_probe(struct platform_device *pdev) ++{ ++ if (usb_disabled()) ++ return -ENODEV; ++ ++ return usb_hcd_ar71xx_probe(&ohci_ar71xx_hc_driver, pdev); ++} ++ ++static int ohci_hcd_ar71xx_drv_remove(struct platform_device *pdev) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(pdev); ++ ++ usb_hcd_ar71xx_remove(hcd, pdev); ++ return 0; ++} ++ ++MODULE_ALIAS("platform:ar71xx-ohci"); ++ ++static struct platform_driver ohci_hcd_ar71xx_driver = { ++ .probe = ohci_hcd_ar71xx_drv_probe, ++ .remove = ohci_hcd_ar71xx_drv_remove, ++ .shutdown = usb_hcd_platform_shutdown, ++ .driver = { ++ .name = "ar71xx-ohci", ++ .owner = THIS_MODULE, ++ }, ++}; +diff -Nur linux-2.6.39.orig/drivers/usb/host/ohci-hcd.c linux-2.6.39/drivers/usb/host/ohci-hcd.c +--- linux-2.6.39.orig/drivers/usb/host/ohci-hcd.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/usb/host/ohci-hcd.c 2011-08-24 18:17:24.000000000 +0200 +@@ -1105,6 +1105,11 @@ + #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver + #endif + ++#ifdef CONFIG_USB_OHCI_AR71XX ++#include "ohci-ar71xx.c" ++#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver ++#endif ++ + #if !defined(PCI_DRIVER) && \ + !defined(PLATFORM_DRIVER) && \ + !defined(OMAP1_PLATFORM_DRIVER) && \ +diff -Nur linux-2.6.39.orig/drivers/watchdog/Kconfig linux-2.6.39/drivers/watchdog/Kconfig +--- linux-2.6.39.orig/drivers/watchdog/Kconfig 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/watchdog/Kconfig 2011-08-24 18:17:24.000000000 +0200 +@@ -990,6 +990,13 @@ + To compile this driver as a loadable module, choose M here. + The module will be called bcm63xx_wdt. + ++config AR71XX_WDT ++ tristate "Atheros AR71xx Watchdog Timer" ++ depends on ATHEROS_AR71XX ++ help ++ Hardware driver for the built-in watchdog timer on the Atheros ++ AR71xx SoCs. ++ + # PARISC Architecture + + # POWERPC Architecture +diff -Nur linux-2.6.39.orig/drivers/watchdog/Makefile linux-2.6.39/drivers/watchdog/Makefile +--- linux-2.6.39.orig/drivers/watchdog/Makefile 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/watchdog/Makefile 2011-08-24 18:17:24.000000000 +0200 +@@ -119,6 +119,7 @@ + obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o + obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o ++obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o + obj-$(CONFIG_TXX9_WDT) += txx9wdt.o + obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o +diff -Nur linux-2.6.39.orig/drivers/watchdog/ar71xx_wdt.c linux-2.6.39/drivers/watchdog/ar71xx_wdt.c +--- linux-2.6.39.orig/drivers/watchdog/ar71xx_wdt.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/drivers/watchdog/ar71xx_wdt.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,299 @@ ++/* ++ * Driver for the Atheros AR71xx SoC's built-in hardware watchdog timer. ++ * ++ * Copyright (C) 2010-2011 Jaiganesh Narayanan ++ * Copyright (C) 2008 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros 2.6.31 BSP ++ * ++ * This driver was based on: drivers/watchdog/ixp4xx_wdt.c ++ * Author: Deepak Saxena ++ * Copyright 2004 (c) MontaVista, Software, Inc. ++ * ++ * which again was based on sa1100 driver, ++ * Copyright (C) 2000 Oleg Drokin ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define DRV_NAME "ar71xx-wdt" ++#define DRV_DESC "Atheros AR71xx hardware watchdog driver" ++#define DRV_VERSION "0.1.0" ++ ++#define WDT_TIMEOUT 15 /* seconds */ ++ ++static int nowayout = WATCHDOG_NOWAYOUT; ++ ++#ifdef CONFIG_WATCHDOG_NOWAYOUT ++module_param(nowayout, int, 0); ++MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " ++ "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); ++#endif ++ ++static unsigned long wdt_flags; ++ ++#define WDT_FLAGS_BUSY 0 ++#define WDT_FLAGS_EXPECT_CLOSE 1 ++ ++static int wdt_timeout = WDT_TIMEOUT; ++static int boot_status; ++static int max_timeout; ++static u32 wdt_clk_freq; ++ ++static inline void ar71xx_wdt_keepalive(void) ++{ ++ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG, wdt_clk_freq * wdt_timeout); ++} ++ ++static inline void ar71xx_wdt_enable(void) ++{ ++ printk(KERN_DEBUG DRV_NAME ": enabling watchdog timer\n"); ++ ar71xx_wdt_keepalive(); ++ udelay(2); ++ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR); ++} ++ ++static inline void ar71xx_wdt_disable(void) ++{ ++ printk(KERN_DEBUG DRV_NAME ": disabling watchdog timer\n"); ++ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE); ++} ++ ++static int ar71xx_wdt_set_timeout(int val) ++{ ++ if (val < 1 || val > max_timeout) ++ return -EINVAL; ++ ++ wdt_timeout = val; ++ ar71xx_wdt_keepalive(); ++ ++ printk(KERN_DEBUG DRV_NAME ": timeout=%d secs\n", wdt_timeout); ++ ++ return 0; ++} ++ ++static int ar71xx_wdt_open(struct inode *inode, struct file *file) ++{ ++ if (test_and_set_bit(WDT_FLAGS_BUSY, &wdt_flags)) ++ return -EBUSY; ++ ++ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); ++ ++ ar71xx_wdt_enable(); ++ ++ return nonseekable_open(inode, file); ++} ++ ++static int ar71xx_wdt_release(struct inode *inode, struct file *file) ++{ ++ if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags)) { ++ ar71xx_wdt_disable(); ++ } else { ++ printk(KERN_CRIT DRV_NAME ": device closed unexpectedly, " ++ "watchdog timer will not stop!\n"); ++ } ++ ++ clear_bit(WDT_FLAGS_BUSY, &wdt_flags); ++ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); ++ ++ return 0; ++} ++ ++static ssize_t ar71xx_wdt_write(struct file *file, const char *data, ++ size_t len, loff_t *ppos) ++{ ++ if (len) { ++ if (!nowayout) { ++ size_t i; ++ ++ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); ++ ++ for (i = 0; i != len; i++) { ++ char c; ++ ++ if (get_user(c, data + i)) ++ return -EFAULT; ++ ++ if (c == 'V') ++ set_bit(WDT_FLAGS_EXPECT_CLOSE, ++ &wdt_flags); ++ } ++ } ++ ++ ar71xx_wdt_keepalive(); ++ } ++ ++ return len; ++} ++ ++static struct watchdog_info ar71xx_wdt_info = { ++ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | ++ WDIOF_MAGICCLOSE | WDIOF_CARDRESET, ++ .firmware_version = 0, ++ .identity = "AR71XX watchdog", ++}; ++ ++static long ar71xx_wdt_ioctl(struct file *file, ++ unsigned int cmd, unsigned long arg) ++{ ++ int t; ++ int ret; ++ ++ switch (cmd) { ++ case WDIOC_GETSUPPORT: ++ ret = copy_to_user((struct watchdog_info *)arg, ++ &ar71xx_wdt_info, ++ sizeof(ar71xx_wdt_info)) ? -EFAULT : 0; ++ break; ++ ++ case WDIOC_GETSTATUS: ++ ret = put_user(0, (int *)arg) ? -EFAULT : 0; ++ break; ++ ++ case WDIOC_GETBOOTSTATUS: ++ ret = put_user(boot_status, (int *)arg) ? -EFAULT : 0; ++ break; ++ ++ case WDIOC_KEEPALIVE: ++ ar71xx_wdt_keepalive(); ++ ret = 0; ++ break; ++ ++ case WDIOC_SETTIMEOUT: ++ ret = get_user(t, (int *)arg) ? -EFAULT : 0; ++ if (ret) ++ break; ++ ++ ret = ar71xx_wdt_set_timeout(t); ++ if (ret) ++ break; ++ ++ /* fallthrough */ ++ case WDIOC_GETTIMEOUT: ++ ret = put_user(wdt_timeout, (int *)arg) ? -EFAULT : 0; ++ break; ++ ++ default: ++ ret = -ENOTTY; ++ break; ++ } ++ ++ return ret; ++} ++ ++static const struct file_operations ar71xx_wdt_fops = { ++ .owner = THIS_MODULE, ++ .write = ar71xx_wdt_write, ++ .unlocked_ioctl = ar71xx_wdt_ioctl, ++ .open = ar71xx_wdt_open, ++ .release = ar71xx_wdt_release, ++}; ++ ++static struct miscdevice ar71xx_wdt_miscdev = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &ar71xx_wdt_fops, ++}; ++ ++static int __devinit ar71xx_wdt_probe(struct platform_device *pdev) ++{ ++ int ret; ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ wdt_clk_freq = ar71xx_ahb_freq; ++ break; ++ ++ case AR71XX_SOC_AR9330: ++ case AR71XX_SOC_AR9331: ++ case AR71XX_SOC_AR9341: ++ case AR71XX_SOC_AR9342: ++ case AR71XX_SOC_AR9344: ++ wdt_clk_freq = ar71xx_ref_freq; ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ max_timeout = (0xfffffffful / wdt_clk_freq); ++ wdt_timeout = (max_timeout < WDT_TIMEOUT) ? max_timeout : WDT_TIMEOUT; ++ ++ if (ar71xx_reset_rr(AR71XX_RESET_REG_WDOG_CTRL) & WDOG_CTRL_LAST_RESET) ++ boot_status = WDIOF_CARDRESET; ++ ++ ret = misc_register(&ar71xx_wdt_miscdev); ++ if (ret) ++ goto err_out; ++ ++ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); ++ ++ printk(KERN_DEBUG DRV_NAME ": timeout=%d secs (max=%d)\n", ++ wdt_timeout, max_timeout); ++ ++ return 0; ++ ++err_out: ++ return ret; ++} ++ ++static int __devexit ar71xx_wdt_remove(struct platform_device *pdev) ++{ ++ misc_deregister(&ar71xx_wdt_miscdev); ++ return 0; ++} ++ ++static struct platform_driver ar71xx_wdt_driver = { ++ .probe = ar71xx_wdt_probe, ++ .remove = __devexit_p(ar71xx_wdt_remove), ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init ar71xx_wdt_init(void) ++{ ++ return platform_driver_register(&ar71xx_wdt_driver); ++} ++module_init(ar71xx_wdt_init); ++ ++static void __exit ar71xx_wdt_exit(void) ++{ ++ platform_driver_unregister(&ar71xx_wdt_driver); ++} ++module_exit(ar71xx_wdt_exit); ++ ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos +diff -Nur linux-2.6.39.orig/include/linux/ipv6.h linux-2.6.39/include/linux/ipv6.h +--- linux-2.6.39.orig/include/linux/ipv6.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/include/linux/ipv6.h 2011-08-24 18:17:24.000000000 +0200 +@@ -126,7 +126,7 @@ + + struct in6_addr saddr; + struct in6_addr daddr; +-}; ++} __packed; + + #ifdef __KERNEL__ + /* +diff -Nur linux-2.6.39.orig/include/linux/myloader.h linux-2.6.39/include/linux/myloader.h +--- linux-2.6.39.orig/include/linux/myloader.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/include/linux/myloader.h 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,120 @@ ++/* ++ * Compex's MyLoader specific definitions ++ * ++ * Copyright (C) 2006-2008 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++ ++#ifndef _MYLOADER_H_ ++#define _MYLOADER_H_ ++ ++/* Myloader specific magic numbers */ ++#define MYLO_MAGIC_SYS_PARAMS 0x20021107 ++#define MYLO_MAGIC_PARTITIONS 0x20021103 ++#define MYLO_MAGIC_BOARD_PARAMS 0x20021103 ++ ++/* Vendor ID's (seems to be same as the PCI vendor ID's) */ ++#define VENID_COMPEX 0x11F6 ++ ++/* Devices based on the ADM5120 */ ++#define DEVID_COMPEX_NP27G 0x0078 ++#define DEVID_COMPEX_NP28G 0x044C ++#define DEVID_COMPEX_NP28GHS 0x044E ++#define DEVID_COMPEX_WP54Gv1C 0x0514 ++#define DEVID_COMPEX_WP54G 0x0515 ++#define DEVID_COMPEX_WP54AG 0x0546 ++#define DEVID_COMPEX_WPP54AG 0x0550 ++#define DEVID_COMPEX_WPP54G 0x0555 ++ ++/* Devices based on the Atheros AR2317 */ ++#define DEVID_COMPEX_NP25G 0x05E6 ++#define DEVID_COMPEX_WPE53G 0x05DC ++ ++/* Devices based on the Atheros AR71xx */ ++#define DEVID_COMPEX_WP543 0x0640 ++ ++/* Devices based on the IXP422 */ ++#define DEVID_COMPEX_WP18 0x047E ++#define DEVID_COMPEX_NP18A 0x0489 ++ ++/* Other devices */ ++#define DEVID_COMPEX_NP26G8M 0x03E8 ++#define DEVID_COMPEX_NP26G16M 0x03E9 ++ ++struct mylo_partition { ++ uint16_t flags; /* partition flags */ ++ uint16_t type; /* type of the partition */ ++ uint32_t addr; /* relative address of the partition from the ++ flash start */ ++ uint32_t size; /* size of the partition in bytes */ ++ uint32_t param; /* if this is the active partition, the ++ MyLoader load code to this address */ ++}; ++ ++#define PARTITION_FLAG_ACTIVE 0x8000 /* this is the active partition, ++ * MyLoader loads firmware from here */ ++#define PARTITION_FLAG_ISRAM 0x2000 /* FIXME: this is a RAM partition? */ ++#define PARTIIION_FLAG_RAMLOAD 0x1000 /* FIXME: load this partition into the RAM? */ ++#define PARTITION_FLAG_PRELOAD 0x0800 /* the partition data preloaded to RAM ++ * before decompression */ ++#define PARTITION_FLAG_LZMA 0x0100 /* partition data compressed by LZMA */ ++#define PARTITION_FLAG_HAVEHDR 0x0002 /* the partition data have a header */ ++ ++#define PARTITION_TYPE_FREE 0 ++#define PARTITION_TYPE_USED 1 ++ ++#define MYLO_MAX_PARTITIONS 8 /* maximum number of partitions in the ++ partition table */ ++ ++struct mylo_partition_table { ++ uint32_t magic; /* must be MYLO_MAGIC_PARTITIONS */ ++ uint32_t res0; /* unknown/unused */ ++ uint32_t res1; /* unknown/unused */ ++ uint32_t res2; /* unknown/unused */ ++ struct mylo_partition partitions[MYLO_MAX_PARTITIONS]; ++}; ++ ++struct mylo_partition_header { ++ uint32_t len; /* length of the partition data */ ++ uint32_t crc; /* CRC value of the partition data */ ++}; ++ ++struct mylo_system_params { ++ uint32_t magic; /* must be MYLO_MAGIC_SYS_PARAMS */ ++ uint32_t res0; ++ uint32_t res1; ++ uint32_t mylo_ver; ++ uint16_t vid; /* Vendor ID */ ++ uint16_t did; /* Device ID */ ++ uint16_t svid; /* Sub Vendor ID */ ++ uint16_t sdid; /* Sub Device ID */ ++ uint32_t rev; /* device revision */ ++ uint32_t fwhi; ++ uint32_t fwlo; ++ uint32_t tftp_addr; ++ uint32_t prog_start; ++ uint32_t flash_size; /* size of boot FLASH in bytes */ ++ uint32_t dram_size; /* size of onboard RAM in bytes */ ++}; ++ ++struct mylo_eth_addr { ++ uint8_t mac[6]; ++ uint8_t csum[2]; ++}; ++ ++#define MYLO_ETHADDR_COUNT 8 /* maximum number of ethernet address ++ in the board parameters */ ++ ++struct mylo_board_params { ++ uint32_t magic; /* must be MYLO_MAGIC_BOARD_PARAMS */ ++ uint32_t res0; ++ uint32_t res1; ++ uint32_t res2; ++ struct mylo_eth_addr addr[MYLO_ETHADDR_COUNT]; ++}; ++ ++#endif /* _MYLOADER_H_*/ +diff -Nur linux-2.6.39.orig/include/linux/netdevice.h linux-2.6.39/include/linux/netdevice.h +--- linux-2.6.39.orig/include/linux/netdevice.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/include/linux/netdevice.h 2011-08-24 18:17:24.000000000 +0200 +@@ -1182,6 +1182,7 @@ + void *ax25_ptr; /* AX.25 specific data */ + struct wireless_dev *ieee80211_ptr; /* IEEE 802.11 specific data, + assign before registering */ ++ void *phy_ptr; /* PHY device specific data */ + + /* + * Cache lines mostly used on receive path (including eth_type_trans()) +diff -Nur linux-2.6.39.orig/include/linux/nxp_74hc153.h linux-2.6.39/include/linux/nxp_74hc153.h +--- linux-2.6.39.orig/include/linux/nxp_74hc153.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/include/linux/nxp_74hc153.h 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,24 @@ ++/* ++ * NXP 74HC153 - Dual 4-input multiplexer defines ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _NXP_74HC153_H ++#define _NXP_74HC153_H ++ ++#define NXP_74HC153_DRIVER_NAME "nxp-74hc153" ++ ++struct nxp_74hc153_platform_data { ++ unsigned gpio_base; ++ unsigned gpio_pin_s0; ++ unsigned gpio_pin_s1; ++ unsigned gpio_pin_1y; ++ unsigned gpio_pin_2y; ++}; ++ ++#endif /* _NXP_74HC153_H */ +diff -Nur linux-2.6.39.orig/include/linux/phy.h linux-2.6.39/include/linux/phy.h +--- linux-2.6.39.orig/include/linux/phy.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/include/linux/phy.h 2011-08-24 18:17:24.000000000 +0200 +@@ -332,6 +332,20 @@ + void (*adjust_link)(struct net_device *dev); + + void (*adjust_state)(struct net_device *dev); ++ ++ /* ++ * By default these point to the original functions ++ * with the same name. adding them to the phy_device ++ * allows the phy driver to override them for packet ++ * mangling if the ethernet driver supports it ++ * This is required to support some really horrible ++ * switches such as the Marvell 88E6060 ++ */ ++ int (*netif_receive_skb)(struct sk_buff *skb); ++ int (*netif_rx)(struct sk_buff *skb); ++ ++ /* alignment offset for packets */ ++ int pkt_align; + }; + #define to_phy_device(d) container_of(d, struct phy_device, dev) + +@@ -508,6 +522,7 @@ + void phy_stop_machine(struct phy_device *phydev); + int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd); + int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd); ++int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr); + int phy_mii_ioctl(struct phy_device *phydev, + struct ifreq *ifr, int cmd); + int phy_start_interrupts(struct phy_device *phydev); +diff -Nur linux-2.6.39.orig/include/linux/spi/spi.h linux-2.6.39/include/linux/spi/spi.h +--- linux-2.6.39.orig/include/linux/spi/spi.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/include/linux/spi/spi.h 2011-08-24 18:17:24.000000000 +0200 +@@ -441,6 +441,8 @@ + dma_addr_t rx_dma; + + unsigned cs_change:1; ++ unsigned verify:1; ++ unsigned fast_write:1; + u8 bits_per_word; + u16 delay_usecs; + u32 speed_hz; +@@ -482,6 +484,7 @@ + struct spi_device *spi; + + unsigned is_dma_mapped:1; ++ unsigned fast_read:1; + + /* REVISIT: we might want a flag affecting the behavior of the + * last transfer ... allowing things like "read 16 bit length L" +diff -Nur linux-2.6.39.orig/include/linux/spi/vsc7385.h linux-2.6.39/include/linux/spi/vsc7385.h +--- linux-2.6.39.orig/include/linux/spi/vsc7385.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/include/linux/spi/vsc7385.h 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,19 @@ ++/* ++ * Platform data definition for the Vitesse VSC7385 ethernet switch driver ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++struct vsc7385_platform_data { ++ void (*reset)(void); ++ char *ucode_name; ++ struct { ++ u32 tx_ipg:5; ++ u32 bit2:1; ++ u32 clk_sel:3; ++ } mac_cfg; ++}; +diff -Nur linux-2.6.39.orig/include/linux/switch.h linux-2.6.39/include/linux/switch.h +--- linux-2.6.39.orig/include/linux/switch.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/include/linux/switch.h 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,204 @@ ++/* ++ * switch.h: Switch configuration API ++ * ++ * Copyright (C) 2008 Felix Fietkau ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __LINUX_SWITCH_H ++#define __LINUX_SWITCH_H ++ ++#include ++#include ++#include ++#include ++#ifndef __KERNEL__ ++#include ++#include ++#include ++#else ++#include ++#endif ++ ++/* main attributes */ ++enum { ++ SWITCH_ATTR_UNSPEC, ++ /* global */ ++ SWITCH_ATTR_TYPE, ++ /* device */ ++ SWITCH_ATTR_ID, ++ SWITCH_ATTR_DEV_NAME, ++ SWITCH_ATTR_ALIAS, ++ SWITCH_ATTR_NAME, ++ SWITCH_ATTR_VLANS, ++ SWITCH_ATTR_PORTS, ++ SWITCH_ATTR_CPU_PORT, ++ /* attributes */ ++ SWITCH_ATTR_OP_ID, ++ SWITCH_ATTR_OP_TYPE, ++ SWITCH_ATTR_OP_NAME, ++ SWITCH_ATTR_OP_PORT, ++ SWITCH_ATTR_OP_VLAN, ++ SWITCH_ATTR_OP_VALUE_INT, ++ SWITCH_ATTR_OP_VALUE_STR, ++ SWITCH_ATTR_OP_VALUE_PORTS, ++ SWITCH_ATTR_OP_DESCRIPTION, ++ /* port lists */ ++ SWITCH_ATTR_PORT, ++ SWITCH_ATTR_MAX ++}; ++ ++/* commands */ ++enum { ++ SWITCH_CMD_UNSPEC, ++ SWITCH_CMD_GET_SWITCH, ++ SWITCH_CMD_NEW_ATTR, ++ SWITCH_CMD_LIST_GLOBAL, ++ SWITCH_CMD_GET_GLOBAL, ++ SWITCH_CMD_SET_GLOBAL, ++ SWITCH_CMD_LIST_PORT, ++ SWITCH_CMD_GET_PORT, ++ SWITCH_CMD_SET_PORT, ++ SWITCH_CMD_LIST_VLAN, ++ SWITCH_CMD_GET_VLAN, ++ SWITCH_CMD_SET_VLAN ++}; ++ ++/* data types */ ++enum switch_val_type { ++ SWITCH_TYPE_UNSPEC, ++ SWITCH_TYPE_INT, ++ SWITCH_TYPE_STRING, ++ SWITCH_TYPE_PORTS, ++ SWITCH_TYPE_NOVAL, ++}; ++ ++/* port nested attributes */ ++enum { ++ SWITCH_PORT_UNSPEC, ++ SWITCH_PORT_ID, ++ SWITCH_PORT_FLAG_TAGGED, ++ SWITCH_PORT_ATTR_MAX ++}; ++ ++#define SWITCH_ATTR_DEFAULTS_OFFSET 0x1000 ++ ++#ifdef __KERNEL__ ++ ++struct switch_dev; ++struct switch_op; ++struct switch_val; ++struct switch_attr; ++struct switch_attrlist; ++ ++int register_switch(struct switch_dev *dev, struct net_device *netdev); ++void unregister_switch(struct switch_dev *dev); ++ ++/** ++ * struct switch_attrlist - attribute list ++ * ++ * @n_attr: number of attributes ++ * @attr: pointer to the attributes array ++ */ ++struct switch_attrlist { ++ int n_attr; ++ const struct switch_attr *attr; ++}; ++ ++/** ++ * struct switch_dev_ops - switch driver operations ++ * ++ * @attr_global: global switch attribute list ++ * @attr_port: port attribute list ++ * @attr_vlan: vlan attribute list ++ * ++ * Callbacks: ++ * ++ * @get_vlan_ports: read the port list of a VLAN ++ * @set_vlan_ports: set the port list of a VLAN ++ * ++ * @get_port_pvid: get the primary VLAN ID of a port ++ * @set_port_pvid: set the primary VLAN ID of a port ++ * ++ * @apply_config: apply all changed settings to the switch ++ * @reset_switch: resetting the switch ++ */ ++struct switch_dev_ops { ++ struct switch_attrlist attr_global, attr_port, attr_vlan; ++ ++ int (*get_vlan_ports)(struct switch_dev *dev, struct switch_val *val); ++ int (*set_vlan_ports)(struct switch_dev *dev, struct switch_val *val); ++ ++ int (*get_port_pvid)(struct switch_dev *dev, int port, int *val); ++ int (*set_port_pvid)(struct switch_dev *dev, int port, int val); ++ ++ int (*apply_config)(struct switch_dev *dev); ++ int (*reset_switch)(struct switch_dev *dev); ++}; ++ ++struct switch_dev { ++ const struct switch_dev_ops *ops; ++ /* will be automatically filled */ ++ char devname[IFNAMSIZ]; ++ ++ const char *name; ++ /* NB: either alias or netdev must be set */ ++ const char *alias; ++ struct net_device *netdev; ++ ++ int ports; ++ int vlans; ++ int cpu_port; ++ ++ /* the following fields are internal for swconfig */ ++ int id; ++ struct list_head dev_list; ++ unsigned long def_global, def_port, def_vlan; ++ ++ spinlock_t lock; ++ struct switch_port *portbuf; ++}; ++ ++struct switch_port { ++ u32 id; ++ u32 flags; ++}; ++ ++struct switch_val { ++ const struct switch_attr *attr; ++ int port_vlan; ++ int len; ++ union { ++ const char *s; ++ u32 i; ++ struct switch_port *ports; ++ } value; ++}; ++ ++struct switch_attr { ++ int disabled; ++ int type; ++ const char *name; ++ const char *description; ++ ++ int (*set)(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val); ++ int (*get)(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val); ++ ++ /* for driver internal use */ ++ int id; ++ int ofs; ++ int max; ++}; ++ ++#endif ++ ++#endif +diff -Nur linux-2.6.39.orig/include/linux/tcp.h linux-2.6.39/include/linux/tcp.h +--- linux-2.6.39.orig/include/linux/tcp.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/include/linux/tcp.h 2011-08-24 18:17:24.000000000 +0200 +@@ -54,7 +54,7 @@ + __be16 window; + __sum16 check; + __be16 urg_ptr; +-}; ++} __packed; + + /* + * The union cast uses a gcc extension to avoid aliasing problems +diff -Nur linux-2.6.39.orig/include/linux/udp.h linux-2.6.39/include/linux/udp.h +--- linux-2.6.39.orig/include/linux/udp.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/include/linux/udp.h 2011-08-24 18:17:24.000000000 +0200 +@@ -24,7 +24,7 @@ + __be16 dest; + __be16 len; + __sum16 check; +-}; ++} __packed; + + /* UDP socket options */ + #define UDP_CORK 1 /* Never send partially complete segments */ +diff -Nur linux-2.6.39.orig/net/dsa/mv88e6063.c linux-2.6.39/net/dsa/mv88e6063.c +--- linux-2.6.39.orig/net/dsa/mv88e6063.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39/net/dsa/mv88e6063.c 2011-08-24 18:17:24.000000000 +0200 +@@ -0,0 +1,294 @@ ++/* ++ * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips ++ * Copyright (c) 2009 Gabor Juhos ++ * ++ * This driver was base on: net/dsa/mv88e6060.c ++ * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips ++ * Copyright (c) 2008-2009 Marvell Semiconductor ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include "dsa_priv.h" ++ ++#define REG_BASE 0x10 ++#define REG_PHY(p) (REG_BASE + (p)) ++#define REG_PORT(p) (REG_BASE + 8 + (p)) ++#define REG_GLOBAL (REG_BASE + 0x0f) ++#define NUM_PORTS 7 ++ ++static int reg_read(struct dsa_switch *ds, int addr, int reg) ++{ ++ return mdiobus_read(ds->master_mii_bus, addr, reg); ++} ++ ++#define REG_READ(addr, reg) \ ++ ({ \ ++ int __ret; \ ++ \ ++ __ret = reg_read(ds, addr, reg); \ ++ if (__ret < 0) \ ++ return __ret; \ ++ __ret; \ ++ }) ++ ++ ++static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) ++{ ++ return mdiobus_write(ds->master_mii_bus, addr, reg, val); ++} ++ ++#define REG_WRITE(addr, reg, val) \ ++ ({ \ ++ int __ret; \ ++ \ ++ __ret = reg_write(ds, addr, reg, val); \ ++ if (__ret < 0) \ ++ return __ret; \ ++ }) ++ ++static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr) ++{ ++ int ret; ++ ++ ret = mdiobus_read(bus, REG_PORT(0), 0x03); ++ if (ret >= 0) { ++ ret &= 0xfff0; ++ if (ret == 0x1530) ++ return "Marvell 88E6063"; ++ } ++ ++ return NULL; ++} ++ ++static int mv88e6063_switch_reset(struct dsa_switch *ds) ++{ ++ int i; ++ int ret; ++ ++ /* ++ * Set all ports to the disabled state. ++ */ ++ for (i = 0; i < NUM_PORTS; i++) { ++ ret = REG_READ(REG_PORT(i), 0x04); ++ REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); ++ } ++ ++ /* ++ * Wait for transmit queues to drain. ++ */ ++ msleep(2); ++ ++ /* ++ * Reset the switch. ++ */ ++ REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); ++ ++ /* ++ * Wait up to one second for reset to complete. ++ */ ++ for (i = 0; i < 1000; i++) { ++ ret = REG_READ(REG_GLOBAL, 0x00); ++ if ((ret & 0x8000) == 0x0000) ++ break; ++ ++ msleep(1); ++ } ++ if (i == 1000) ++ return -ETIMEDOUT; ++ ++ return 0; ++} ++ ++static int mv88e6063_setup_global(struct dsa_switch *ds) ++{ ++ /* ++ * Disable discarding of frames with excessive collisions, ++ * set the maximum frame size to 1536 bytes, and mask all ++ * interrupt sources. ++ */ ++ REG_WRITE(REG_GLOBAL, 0x04, 0x0800); ++ ++ /* ++ * Enable automatic address learning, set the address ++ * database size to 1024 entries, and set the default aging ++ * time to 5 minutes. ++ */ ++ REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); ++ ++ return 0; ++} ++ ++static int mv88e6063_setup_port(struct dsa_switch *ds, int p) ++{ ++ int addr = REG_PORT(p); ++ ++ /* ++ * Do not force flow control, disable Ingress and Egress ++ * Header tagging, disable VLAN tunneling, and set the port ++ * state to Forwarding. Additionally, if this is the CPU ++ * port, enable Ingress and Egress Trailer tagging mode. ++ */ ++ REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); ++ ++ /* ++ * Port based VLAN map: give each port its own address ++ * database, allow the CPU port to talk to each of the 'real' ++ * ports, and allow each of the 'real' ports to only talk to ++ * the CPU port. ++ */ ++ REG_WRITE(addr, 0x06, ++ ((p & 0xf) << 12) | ++ (dsa_is_cpu_port(ds, p) ? ++ ds->phys_port_mask : ++ (1 << ds->dst->cpu_port))); ++ ++ /* ++ * Port Association Vector: when learning source addresses ++ * of packets, add the address to the address database using ++ * a port bitmap that has only the bit for this port set and ++ * the other bits clear. ++ */ ++ REG_WRITE(addr, 0x0b, 1 << p); ++ ++ return 0; ++} ++ ++static int mv88e6063_setup(struct dsa_switch *ds) ++{ ++ int i; ++ int ret; ++ ++ ret = mv88e6063_switch_reset(ds); ++ if (ret < 0) ++ return ret; ++ ++ /* @@@ initialise atu */ ++ ++ ret = mv88e6063_setup_global(ds); ++ if (ret < 0) ++ return ret; ++ ++ for (i = 0; i < NUM_PORTS; i++) { ++ ret = mv88e6063_setup_port(ds, i); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr) ++{ ++ REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); ++ REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); ++ REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); ++ ++ return 0; ++} ++ ++static int mv88e6063_port_to_phy_addr(int port) ++{ ++ if (port >= 0 && port <= NUM_PORTS) ++ return REG_PHY(port); ++ return -1; ++} ++ ++static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum) ++{ ++ int addr; ++ ++ addr = mv88e6063_port_to_phy_addr(port); ++ if (addr == -1) ++ return 0xffff; ++ ++ return reg_read(ds, addr, regnum); ++} ++ ++static int ++mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) ++{ ++ int addr; ++ ++ addr = mv88e6063_port_to_phy_addr(port); ++ if (addr == -1) ++ return 0xffff; ++ ++ return reg_write(ds, addr, regnum, val); ++} ++ ++static void mv88e6063_poll_link(struct dsa_switch *ds) ++{ ++ int i; ++ ++ for (i = 0; i < DSA_MAX_PORTS; i++) { ++ struct net_device *dev; ++ int uninitialized_var(port_status); ++ int link; ++ int speed; ++ int duplex; ++ int fc; ++ ++ dev = ds->ports[i]; ++ if (dev == NULL) ++ continue; ++ ++ link = 0; ++ if (dev->flags & IFF_UP) { ++ port_status = reg_read(ds, REG_PORT(i), 0x00); ++ if (port_status < 0) ++ continue; ++ ++ link = !!(port_status & 0x1000); ++ } ++ ++ if (!link) { ++ if (netif_carrier_ok(dev)) { ++ printk(KERN_INFO "%s: link down\n", dev->name); ++ netif_carrier_off(dev); ++ } ++ continue; ++ } ++ ++ speed = (port_status & 0x0100) ? 100 : 10; ++ duplex = (port_status & 0x0200) ? 1 : 0; ++ fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0; ++ ++ if (!netif_carrier_ok(dev)) { ++ printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " ++ "flow control %sabled\n", dev->name, ++ speed, duplex ? "full" : "half", ++ fc ? "en" : "dis"); ++ netif_carrier_on(dev); ++ } ++ } ++} ++ ++static struct dsa_switch_driver mv88e6063_switch_driver = { ++ .tag_protocol = htons(ETH_P_TRAILER), ++ .probe = mv88e6063_probe, ++ .setup = mv88e6063_setup, ++ .set_addr = mv88e6063_set_addr, ++ .phy_read = mv88e6063_phy_read, ++ .phy_write = mv88e6063_phy_write, ++ .poll_link = mv88e6063_poll_link, ++}; ++ ++static int __init mv88e6063_init(void) ++{ ++ register_switch_driver(&mv88e6063_switch_driver); ++ return 0; ++} ++module_init(mv88e6063_init); ++ ++static void __exit mv88e6063_cleanup(void) ++{ ++ unregister_switch_driver(&mv88e6063_switch_driver); ++} ++module_exit(mv88e6063_cleanup); +diff -Nur linux-2.6.39.orig/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c linux-2.6.39/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c +--- linux-2.6.39.orig/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c 2011-08-24 18:17:24.000000000 +0200 +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -44,8 +45,8 @@ + if (ap == NULL) + return false; + +- tuple->src.u3.ip = ap[0]; +- tuple->dst.u3.ip = ap[1]; ++ tuple->src.u3.ip = __get_unaligned_cpu32(ap++); ++ tuple->dst.u3.ip = __get_unaligned_cpu32(ap); + + return true; + } diff --git a/target/linux/patches/2.6.39.4/sparc-include.patch b/target/linux/patches/2.6.39.4/sparc-include.patch new file mode 100644 index 000000000..2f8ffd061 --- /dev/null +++ b/target/linux/patches/2.6.39.4/sparc-include.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c +--- linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c 2011-05-21 13:34:40.000000000 +0200 +@@ -25,7 +25,6 @@ + #include + #include + #include +-#include + + #define MAXSYMS 1024 + diff --git a/target/linux/patches/2.6.39.4/startup.patch b/target/linux/patches/2.6.39.4/startup.patch new file mode 100644 index 000000000..68e8987b0 --- /dev/null +++ b/target/linux/patches/2.6.39.4/startup.patch @@ -0,0 +1,20 @@ +diff -Nur linux-2.6.34.orig/init/main.c linux-2.6.34/init/main.c +--- linux-2.6.34.orig/init/main.c 2010-05-16 23:17:36.000000000 +0200 ++++ linux-2.6.34/init/main.c 2010-05-20 20:13:26.321613615 +0200 +@@ -842,6 +842,7 @@ + printk(KERN_WARNING "Failed to execute %s. Attempting " + "defaults...\n", execute_command); + } ++ run_init_process("/init"); + run_init_process("/sbin/init"); + run_init_process("/etc/init"); + run_init_process("/bin/init"); +@@ -889,6 +890,8 @@ + if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0) + printk(KERN_WARNING "Warning: unable to open an initial console.\n"); + ++ printk(KERN_WARNING "Starting Linux (built with OpenADK).\n"); ++ + (void) sys_dup(0); + (void) sys_dup(0); + /* diff --git a/target/linux/patches/2.6.39.4/usb-defaults-off.patch b/target/linux/patches/2.6.39.4/usb-defaults-off.patch new file mode 100644 index 000000000..31367108a --- /dev/null +++ b/target/linux/patches/2.6.39.4/usb-defaults-off.patch @@ -0,0 +1,32 @@ +diff -Nur linux-2.6.37.orig//drivers/usb/core/Kconfig linux-2.6.37/drivers/usb/core/Kconfig +--- linux-2.6.37.orig//drivers/usb/core/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/drivers/usb/core/Kconfig 2011-04-12 19:04:23.000000000 +0200 +@@ -59,7 +59,7 @@ + config USB_DEVICE_CLASS + bool "USB device class-devices (DEPRECATED)" + depends on USB +- default y ++ default n + ---help--- + Userspace access to USB devices is granted by device-nodes exported + directly from the usbdev in sysfs. Old versions of the driver +diff -Nur linux-2.6.37.orig//drivers/usb/host/Kconfig linux-2.6.37/drivers/usb/host/Kconfig +--- linux-2.6.37.orig//drivers/usb/host/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/drivers/usb/host/Kconfig 2011-04-12 19:04:48.000000000 +0200 +@@ -62,6 +62,7 @@ + config USB_EHCI_ROOT_HUB_TT + bool "Root Hub Transaction Translators" + depends on USB_EHCI_HCD ++ default n + ---help--- + Some EHCI chips have vendor-specific extensions to integrate + transaction translators, so that no OHCI or UHCI companion +@@ -74,7 +75,7 @@ + config USB_EHCI_TT_NEWSCHED + bool "Improved Transaction Translator scheduling" + depends on USB_EHCI_HCD +- default y ++ default n + ---help--- + This changes the periodic scheduling code to fill more of the low + and full speed bandwidth available from the Transaction Translator diff --git a/target/linux/patches/2.6.39.4/uuid.patch b/target/linux/patches/2.6.39.4/uuid.patch new file mode 100644 index 000000000..2529fdab5 --- /dev/null +++ b/target/linux/patches/2.6.39.4/uuid.patch @@ -0,0 +1,255 @@ +diff -Nur linux-2.6.38.4.orig/block/genhd.c linux-2.6.38.4/block/genhd.c +--- linux-2.6.38.4.orig/block/genhd.c 2011-04-21 23:34:46.000000000 +0200 ++++ linux-2.6.38.4/block/genhd.c 2011-04-27 19:21:18.668912036 +0200 +@@ -34,7 +34,7 @@ + static DEFINE_MUTEX(ext_devt_mutex); + static DEFINE_IDR(ext_devt_idr); + +-static struct device_type disk_type; ++struct device_type disk_type; + + static void disk_add_events(struct gendisk *disk); + static void disk_del_events(struct gendisk *disk); +@@ -1118,7 +1118,7 @@ + return NULL; + } + +-static struct device_type disk_type = { ++struct device_type disk_type = { + .name = "disk", + .groups = disk_attr_groups, + .release = disk_release, +diff -Nur linux-2.6.38.4.orig/init/do_mounts.c linux-2.6.38.4/init/do_mounts.c +--- linux-2.6.38.4.orig/init/do_mounts.c 2011-04-21 23:34:46.000000000 +0200 ++++ linux-2.6.38.4/init/do_mounts.c 2011-04-27 19:26:52.721413000 +0200 +@@ -32,6 +32,132 @@ + + dev_t ROOT_DEV; + ++#ifdef CONFIG_EXT2_FS ++/* support for root=UUID=ce40d6b2-18eb-4a75-aefe-7ddb0995ce63 bootargs */ ++ ++#include ++ ++__u8 root_dev_uuid[16]; ++int root_dev_type; /* 0 = normal (/dev/hda1, 0301); 1 = UUID; 3 = bad */ ++ ++/* imported from block/genhd.c after removing its static qualifier */ ++extern struct device_type disk_type; ++ ++/* helper function */ ++static __u8 __init fromhex(char c) ++{ ++ if (c >= '0' && c <= '9') ++ return (c - '0'); ++ c &= ~32; ++ if (c >= 'A' && c <= 'F') ++ return (c - 'A' + 10); ++ return (0xFF); ++} ++ ++static void __init parse_uuid(const char *s) ++{ ++ int i; ++ __u8 j, k; ++ ++ if (strlen(s) != 36 || s[8] != '-' || s[13] != '-' || ++ s[18] != '-' || s[23] != '-') ++ goto bad_uuid; ++ for (i = 0; i < 16; i++) { ++ if (*s == '-') ++ ++s; ++ j = fromhex(*s++); ++ k = fromhex(*s++); ++ if (j == 0xFF || k == 0xFF) ++ goto bad_uuid; ++ root_dev_uuid[i] = (j << 4) | k; ++ } ++ return; ++ bad_uuid: ++ /* we cannot panic here, defer */ ++ root_dev_type = 3; ++} ++ ++/* from drivers/md/md.c */ ++static void __init initcode_bi_complete(struct bio *bio, int error) ++{ ++ complete((struct completion*)bio->bi_private); ++} ++ ++static int __init initcode_sync_page_read(struct block_device *bdev, ++ sector_t sector, int size, struct page *page) ++{ ++ struct bio *bio = bio_alloc(GFP_NOIO, 1); ++ struct completion event; ++ int ret, rw = READ; ++ ++ rw |= REQ_SYNC; ++ ++ bio->bi_bdev = bdev; ++ bio->bi_sector = sector; ++ bio_add_page(bio, page, size, 0); ++ init_completion(&event); ++ bio->bi_private = &event; ++ bio->bi_end_io = initcode_bi_complete; ++ submit_bio(rw, bio); ++ wait_for_completion(&event); ++ ++ ret = test_bit(BIO_UPTODATE, &bio->bi_flags); ++ bio_put(bio); ++ /* 0 = failure */ ++ return ret; ++} ++ ++/* most of this taken from fs/ext2/super.c */ ++static int __init check_dev(struct gendisk *thedisk, dev_t devt, ++ int blocksize, struct page *page) ++{ ++ struct ext2_super_block * es; ++ struct block_device *bdev; ++ unsigned long sb_block = 1; ++ unsigned long logic_sb_block; ++ unsigned long offset = 0; ++ int rv = /* not found */ 0; ++ char bff[22]; ++ ++ bdev = bdget(devt); ++ if (blkdev_get(bdev, FMODE_READ, NULL)) { ++ printk(KERN_ERR "VFS: opening block device %s failed!\n", ++ format_dev_t(bff, devt)); ++ return (0); ++ } ++ ++ if (blocksize != BLOCK_SIZE) { ++ logic_sb_block = (sb_block*BLOCK_SIZE) / blocksize; ++ offset = (sb_block*BLOCK_SIZE) % blocksize; ++ } else { ++ logic_sb_block = sb_block; ++ } ++ ++// printk(KERN_ERR "D: attempting to read %d @%lu from " ++// "bdev %p devt %08X %s\n", blocksize, logic_sb_block, ++// bdev, devt, format_dev_t(bff, devt)); ++ if (!initcode_sync_page_read(bdev, logic_sb_block, blocksize, page)) { ++// printk(KERN_ERR "D: failed!\n"); ++ goto out; ++ } ++ es = (struct ext2_super_block *)(((char *)page_address(page)) + offset); ++ if (le16_to_cpu(es->s_magic) == EXT2_SUPER_MAGIC) { ++// printk(KERN_ERR "D: has uuid " ++// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", ++// es->s_uuid[0], es->s_uuid[1], es->s_uuid[2], es->s_uuid[3], ++// es->s_uuid[4], es->s_uuid[5], es->s_uuid[6], es->s_uuid[7], ++// es->s_uuid[8], es->s_uuid[9], es->s_uuid[10], es->s_uuid[11], ++// es->s_uuid[12], es->s_uuid[13], es->s_uuid[14], es->s_uuid[15]); ++ if (!memcmp(es->s_uuid, root_dev_uuid, 16)) ++ rv = /* found */ 1; ++ } ++// else printk(KERN_ERR "D: bad ext2fs magic\n"); ++ out: ++ blkdev_put(bdev, FMODE_READ); ++ return (rv); ++} ++#endif /* CONFIG_EXT2_FS for UUID support */ ++ + static int __init load_ramdisk(char *str) + { + rd_doload = simple_strtol(str,NULL,0) & 3; +@@ -218,6 +344,13 @@ + static int __init root_dev_setup(char *line) + { + strlcpy(saved_root_name, line, sizeof(saved_root_name)); ++#ifdef CONFIG_EXT2_FS ++ root_dev_type = 0; ++ if (!strncmp(line, "UUID=", 5)) { ++ root_dev_type = 1; ++ parse_uuid(line + 5); ++ } ++#endif /* CONFIG_EXT2_FS for UUID support */ + return 1; + } + +@@ -403,6 +536,83 @@ + + void __init mount_root(void) + { ++#ifdef CONFIG_EXT2_FS ++ /* UUID support */ ++// printk_all_partitions(); ++ if (root_dev_type == 1) { ++ int blocksize; ++ ++ /* from block/genhd.c printk_all_partitions */ ++ struct class_dev_iter iter; ++ struct device *dev; ++ ++ /* from drivers/md/md.c */ ++ struct page *sb_page; ++ ++ if (!(sb_page = alloc_page(GFP_KERNEL))) { ++ printk(KERN_ERR "VFS: no memory for bio page\n"); ++ goto nomemforbio; ++ } ++ ++// printk(KERN_ERR "D: root is: " ++// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", ++// root_dev_uuid[0], root_dev_uuid[1], root_dev_uuid[2], root_dev_uuid[3], ++// root_dev_uuid[4], root_dev_uuid[5], root_dev_uuid[6], root_dev_uuid[7], ++// root_dev_uuid[8], root_dev_uuid[9], root_dev_uuid[10], root_dev_uuid[11], ++// root_dev_uuid[12], root_dev_uuid[13], root_dev_uuid[14], root_dev_uuid[15]); ++ /* from block/genhd.c printk_all_partitions */ ++// printk(KERN_ERR "D: begin iter\n"); ++ class_dev_iter_init(&iter, &block_class, NULL, &disk_type); ++ while (root_dev_type && (dev = class_dev_iter_next(&iter))) { ++// char bff[22]; ++ struct gendisk *disk = dev_to_disk(dev); ++ struct disk_part_iter piter; ++ struct hd_struct *part; ++ if (get_capacity(disk) == 0 || ++ (disk->flags & GENHD_FL_SUPPRESS_PARTITION_INFO)) { ++// printk(KERN_ERR "D: ignoring\n"); ++ continue; ++ } ++ blocksize = queue_logical_block_size(disk->queue); ++// printk(KERN_ERR "D: gendisk, blocksize %d " ++// "name '%s' devt %08X %s #part %d\n", blocksize, ++// disk->disk_name, dev->devt, ++// format_dev_t(bff, dev->devt), ++// disk_max_parts(disk)); ++ disk_part_iter_init(&piter, disk, DISK_PITER_INCL_PART0); ++ while (root_dev_type && (part = disk_part_iter_next(&piter))) { ++ /* avoid empty or too small partitions */ ++// printk(KERN_ERR "D: part #%d start %llu " ++// "nr %llu\n", part->partno, ++// (__u64)part->start_sect, ++// (__u64)part->nr_sects); ++ if (part->nr_sects < 8) ++ continue; ++ if (check_dev(disk, MKDEV(MAJOR(dev->devt), ++ MINOR(dev->devt) + part->partno), ++ blocksize, sb_page)) { ++ ROOT_DEV = part_devt(part); ++// printk(KERN_ERR "D: got match!\n"); ++ // comment out below for debugging ++ root_dev_type = 0; ++ } ++ } ++ disk_part_iter_exit(&piter); ++ } ++// printk(KERN_ERR "D: end iter\n"); ++ class_dev_iter_exit(&iter); ++ put_page(sb_page); ++ } ++ nomemforbio: ++ if (root_dev_type == 1) ++ printk(KERN_ERR "VFS: Unable to find root by UUID %s.\n", ++ saved_root_name + 5); ++ else if (root_dev_type == 3) ++ /* execute deferred panic from parse_uuid */ ++ panic("Badly formatted UUID %s was supplied as kernel " ++ "parameter root", saved_root_name + 5); ++#endif /* CONFIG_EXT2_FS for UUID support */ ++ + #ifdef CONFIG_ROOT_NFS + if (MAJOR(ROOT_DEV) == UNNAMED_MAJOR) { + if (mount_nfs_root()) diff --git a/target/linux/patches/2.6.39.4/vga-cons-default-off.patch b/target/linux/patches/2.6.39.4/vga-cons-default-off.patch new file mode 100644 index 000000000..178aeeeb9 --- /dev/null +++ b/target/linux/patches/2.6.39.4/vga-cons-default-off.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.37.orig//drivers/video/console/Kconfig linux-2.6.37/drivers/video/console/Kconfig +--- linux-2.6.37.orig//drivers/video/console/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/drivers/video/console/Kconfig 2011-04-12 16:29:34.000000000 +0200 +@@ -7,7 +7,7 @@ + config VGA_CONSOLE + bool "VGA text console" if EMBEDDED || !X86 + depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) +- default y ++ default n + help + Saying Y here will allow you to use Linux in text mode through a + display that complies with the generic VGA standard. Virtually diff --git a/target/linux/patches/2.6.39.4/wlan-cf.patch b/target/linux/patches/2.6.39.4/wlan-cf.patch new file mode 100644 index 000000000..fc20759e2 --- /dev/null +++ b/target/linux/patches/2.6.39.4/wlan-cf.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c +--- linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c 2011-09-12 02:46:26.987984145 +0200 +@@ -623,6 +623,7 @@ + static struct pcmcia_device_id hostap_cs_ids[] = { + PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7100), + PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7300), ++ PCMCIA_DEVICE_MANF_CARD(0x0004, 0x2003), + PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0777), + PCMCIA_DEVICE_MANF_CARD(0x0126, 0x8000), + PCMCIA_DEVICE_MANF_CARD(0x0138, 0x0002), diff --git a/target/linux/patches/2.6.39.4/x86-build.patch b/target/linux/patches/2.6.39.4/x86-build.patch new file mode 100644 index 000000000..339140f41 --- /dev/null +++ b/target/linux/patches/2.6.39.4/x86-build.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c linux-2.6.39-rc6/arch/x86/boot/tools/build.c +--- linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/arch/x86/boot/tools/build.c 2011-05-05 20:10:07.000000000 +0200 +@@ -29,7 +29,6 @@ + #include + #include + #include +-#include + #include + #include + #include diff --git a/target/linux/patches/2.6.39.4/zlib-inflate.patch b/target/linux/patches/2.6.39.4/zlib-inflate.patch new file mode 100644 index 000000000..58e1f6d21 --- /dev/null +++ b/target/linux/patches/2.6.39.4/zlib-inflate.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.37.orig/lib/Kconfig linux-2.6.37/lib/Kconfig +--- linux-2.6.37.orig/lib/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/lib/Kconfig 2011-03-01 20:10:29.833370667 +0100 +@@ -95,7 +95,7 @@ + # compression support is select'ed if needed + # + config ZLIB_INFLATE +- tristate ++ boolean + + config ZLIB_DEFLATE + tristate diff --git a/target/linux/patches/3.0.8/bsd-compatibility.patch b/target/linux/patches/3.0.8/bsd-compatibility.patch new file mode 100644 index 000000000..9e91a62de --- /dev/null +++ b/target/linux/patches/3.0.8/bsd-compatibility.patch @@ -0,0 +1,2512 @@ +diff -Nur linux-2.6.36.orig/scripts/Makefile.lib linux-2.6.36/scripts/Makefile.lib +--- linux-2.6.36.orig/scripts/Makefile.lib 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/Makefile.lib 2010-11-28 18:34:22.000000000 +0100 +@@ -216,7 +216,12 @@ + size_append = printf $(shell \ + dec_size=0; \ + for F in $1; do \ +- fsize=$$(stat -c "%s" $$F); \ ++ if stat -qs .>/dev/null 2>&1; then \ ++ statcmd='stat -f %z'; \ ++ else \ ++ statcmd='stat -c %s'; \ ++ fi; \ ++ fsize=$$($$statcmd $$F); \ + dec_size=$$(expr $$dec_size + $$fsize); \ + done; \ + printf "%08x\n" $$dec_size | \ +diff -Nur linux-2.6.36.orig/scripts/mod/mk_elfconfig.c linux-2.6.36/scripts/mod/mk_elfconfig.c +--- linux-2.6.36.orig/scripts/mod/mk_elfconfig.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/mod/mk_elfconfig.c 2010-11-28 18:33:24.000000000 +0100 +@@ -1,7 +1,18 @@ + #include + #include + #include +-#include ++ ++#define EI_NIDENT (16) ++#define ELFMAG "\177ELF" ++ ++#define SELFMAG 4 ++#define EI_CLASS 4 ++#define ELFCLASS32 1 /* 32-bit objects */ ++#define ELFCLASS64 2 /* 64-bit objects */ ++ ++#define EI_DATA 5 /* Data encoding byte index */ ++#define ELFDATA2LSB 1 /* 2's complement, little endian */ ++#define ELFDATA2MSB 2 /* 2's complement, big endian */ + + int + main(int argc, char **argv) +diff -Nur linux-2.6.36.orig/scripts/mod/modpost.h linux-2.6.36/scripts/mod/modpost.h +--- linux-2.6.36.orig/scripts/mod/modpost.h 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/mod/modpost.h 2010-11-28 18:33:24.000000000 +0100 +@@ -7,7 +7,2453 @@ + #include + #include + #include +-#include ++ ++ ++/* This file defines standard ELF types, structures, and macros. ++ Copyright (C) 1995-1999,2000,2001,2002,2003 Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, write to the Free ++ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA ++ 02111-1307 USA. */ ++ ++#ifndef _ELF_H ++#define _ELF_H 1 ++ ++__BEGIN_DECLS ++ ++/* Standard ELF types. */ ++ ++#include ++ ++/* Type for a 16-bit quantity. */ ++typedef uint16_t Elf32_Half; ++typedef uint16_t Elf64_Half; ++ ++/* Types for signed and unsigned 32-bit quantities. */ ++typedef uint32_t Elf32_Word; ++typedef int32_t Elf32_Sword; ++typedef uint32_t Elf64_Word; ++typedef int32_t Elf64_Sword; ++ ++/* Types for signed and unsigned 64-bit quantities. */ ++typedef uint64_t Elf32_Xword; ++typedef int64_t Elf32_Sxword; ++typedef uint64_t Elf64_Xword; ++typedef int64_t Elf64_Sxword; ++ ++/* Type of addresses. */ ++typedef uint32_t Elf32_Addr; ++typedef uint64_t Elf64_Addr; ++ ++/* Type of file offsets. */ ++typedef uint32_t Elf32_Off; ++typedef uint64_t Elf64_Off; ++ ++/* Type for section indices, which are 16-bit quantities. */ ++typedef uint16_t Elf32_Section; ++typedef uint16_t Elf64_Section; ++ ++/* Type for version symbol information. */ ++typedef Elf32_Half Elf32_Versym; ++typedef Elf64_Half Elf64_Versym; ++ ++ ++/* The ELF file header. This appears at the start of every ELF file. */ ++ ++#define EI_NIDENT (16) ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf32_Half e_type; /* Object file type */ ++ Elf32_Half e_machine; /* Architecture */ ++ Elf32_Word e_version; /* Object file version */ ++ Elf32_Addr e_entry; /* Entry point virtual address */ ++ Elf32_Off e_phoff; /* Program header table file offset */ ++ Elf32_Off e_shoff; /* Section header table file offset */ ++ Elf32_Word e_flags; /* Processor-specific flags */ ++ Elf32_Half e_ehsize; /* ELF header size in bytes */ ++ Elf32_Half e_phentsize; /* Program header table entry size */ ++ Elf32_Half e_phnum; /* Program header table entry count */ ++ Elf32_Half e_shentsize; /* Section header table entry size */ ++ Elf32_Half e_shnum; /* Section header table entry count */ ++ Elf32_Half e_shstrndx; /* Section header string table index */ ++} Elf32_Ehdr; ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf64_Half e_type; /* Object file type */ ++ Elf64_Half e_machine; /* Architecture */ ++ Elf64_Word e_version; /* Object file version */ ++ Elf64_Addr e_entry; /* Entry point virtual address */ ++ Elf64_Off e_phoff; /* Program header table file offset */ ++ Elf64_Off e_shoff; /* Section header table file offset */ ++ Elf64_Word e_flags; /* Processor-specific flags */ ++ Elf64_Half e_ehsize; /* ELF header size in bytes */ ++ Elf64_Half e_phentsize; /* Program header table entry size */ ++ Elf64_Half e_phnum; /* Program header table entry count */ ++ Elf64_Half e_shentsize; /* Section header table entry size */ ++ Elf64_Half e_shnum; /* Section header table entry count */ ++ Elf64_Half e_shstrndx; /* Section header string table index */ ++} Elf64_Ehdr; ++ ++/* Fields in the e_ident array. The EI_* macros are indices into the ++ array. The macros under each EI_* macro are the values the byte ++ may have. */ ++ ++#define EI_MAG0 0 /* File identification byte 0 index */ ++#define ELFMAG0 0x7f /* Magic number byte 0 */ ++ ++#define EI_MAG1 1 /* File identification byte 1 index */ ++#define ELFMAG1 'E' /* Magic number byte 1 */ ++ ++#define EI_MAG2 2 /* File identification byte 2 index */ ++#define ELFMAG2 'L' /* Magic number byte 2 */ ++ ++#define EI_MAG3 3 /* File identification byte 3 index */ ++#define ELFMAG3 'F' /* Magic number byte 3 */ ++ ++/* Conglomeration of the identification bytes, for easy testing as a word. */ ++#define ELFMAG "\177ELF" ++#define SELFMAG 4 ++ ++#define EI_CLASS 4 /* File class byte index */ ++#define ELFCLASSNONE 0 /* Invalid class */ ++#define ELFCLASS32 1 /* 32-bit objects */ ++#define ELFCLASS64 2 /* 64-bit objects */ ++#define ELFCLASSNUM 3 ++ ++#define EI_DATA 5 /* Data encoding byte index */ ++#define ELFDATANONE 0 /* Invalid data encoding */ ++#define ELFDATA2LSB 1 /* 2's complement, little endian */ ++#define ELFDATA2MSB 2 /* 2's complement, big endian */ ++#define ELFDATANUM 3 ++ ++#define EI_VERSION 6 /* File version byte index */ ++ /* Value must be EV_CURRENT */ ++ ++#define EI_OSABI 7 /* OS ABI identification */ ++#define ELFOSABI_NONE 0 /* UNIX System V ABI */ ++#define ELFOSABI_SYSV 0 /* Alias. */ ++#define ELFOSABI_HPUX 1 /* HP-UX */ ++#define ELFOSABI_NETBSD 2 /* NetBSD. */ ++#define ELFOSABI_LINUX 3 /* Linux. */ ++#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ ++#define ELFOSABI_AIX 7 /* IBM AIX. */ ++#define ELFOSABI_IRIX 8 /* SGI Irix. */ ++#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ ++#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ ++#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ ++#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ ++#define ELFOSABI_ARM 97 /* ARM */ ++#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ ++ ++#define EI_ABIVERSION 8 /* ABI version */ ++ ++#define EI_PAD 9 /* Byte index of padding bytes */ ++ ++/* Legal values for e_type (object file type). */ ++ ++#define ET_NONE 0 /* No file type */ ++#define ET_REL 1 /* Relocatable file */ ++#define ET_EXEC 2 /* Executable file */ ++#define ET_DYN 3 /* Shared object file */ ++#define ET_CORE 4 /* Core file */ ++#define ET_NUM 5 /* Number of defined types */ ++#define ET_LOOS 0xfe00 /* OS-specific range start */ ++#define ET_HIOS 0xfeff /* OS-specific range end */ ++#define ET_LOPROC 0xff00 /* Processor-specific range start */ ++#define ET_HIPROC 0xffff /* Processor-specific range end */ ++ ++/* Legal values for e_machine (architecture). */ ++ ++#define EM_NONE 0 /* No machine */ ++#define EM_M32 1 /* AT&T WE 32100 */ ++#define EM_SPARC 2 /* SUN SPARC */ ++#define EM_386 3 /* Intel 80386 */ ++#define EM_68K 4 /* Motorola m68k family */ ++#define EM_88K 5 /* Motorola m88k family */ ++#define EM_860 7 /* Intel 80860 */ ++#define EM_MIPS 8 /* MIPS R3000 big-endian */ ++#define EM_S370 9 /* IBM System/370 */ ++#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ ++ ++#define EM_PARISC 15 /* HPPA */ ++#define EM_VPP500 17 /* Fujitsu VPP500 */ ++#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ ++#define EM_960 19 /* Intel 80960 */ ++#define EM_PPC 20 /* PowerPC */ ++#define EM_PPC64 21 /* PowerPC 64-bit */ ++#define EM_S390 22 /* IBM S390 */ ++ ++#define EM_V800 36 /* NEC V800 series */ ++#define EM_FR20 37 /* Fujitsu FR20 */ ++#define EM_RH32 38 /* TRW RH-32 */ ++#define EM_RCE 39 /* Motorola RCE */ ++#define EM_ARM 40 /* ARM */ ++#define EM_FAKE_ALPHA 41 /* Digital Alpha */ ++#define EM_SH 42 /* Hitachi SH */ ++#define EM_SPARCV9 43 /* SPARC v9 64-bit */ ++#define EM_TRICORE 44 /* Siemens Tricore */ ++#define EM_ARC 45 /* Argonaut RISC Core */ ++#define EM_H8_300 46 /* Hitachi H8/300 */ ++#define EM_H8_300H 47 /* Hitachi H8/300H */ ++#define EM_H8S 48 /* Hitachi H8S */ ++#define EM_H8_500 49 /* Hitachi H8/500 */ ++#define EM_IA_64 50 /* Intel Merced */ ++#define EM_MIPS_X 51 /* Stanford MIPS-X */ ++#define EM_COLDFIRE 52 /* Motorola Coldfire */ ++#define EM_68HC12 53 /* Motorola M68HC12 */ ++#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ ++#define EM_PCP 55 /* Siemens PCP */ ++#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ ++#define EM_NDR1 57 /* Denso NDR1 microprocessor */ ++#define EM_STARCORE 58 /* Motorola Start*Core processor */ ++#define EM_ME16 59 /* Toyota ME16 processor */ ++#define EM_ST100 60 /* STMicroelectronic ST100 processor */ ++#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ ++#define EM_X86_64 62 /* AMD x86-64 architecture */ ++#define EM_PDSP 63 /* Sony DSP Processor */ ++ ++#define EM_FX66 66 /* Siemens FX66 microcontroller */ ++#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ ++#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ ++#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ ++#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ ++#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ ++#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ ++#define EM_SVX 73 /* Silicon Graphics SVx */ ++#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ ++#define EM_VAX 75 /* Digital VAX */ ++#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ ++#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ ++#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ ++#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ ++#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ ++#define EM_HUANY 81 /* Harvard University machine-independent object files */ ++#define EM_PRISM 82 /* SiTera Prism */ ++#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ ++#define EM_FR30 84 /* Fujitsu FR30 */ ++#define EM_D10V 85 /* Mitsubishi D10V */ ++#define EM_D30V 86 /* Mitsubishi D30V */ ++#define EM_V850 87 /* NEC v850 */ ++#define EM_M32R 88 /* Mitsubishi M32R */ ++#define EM_MN10300 89 /* Matsushita MN10300 */ ++#define EM_MN10200 90 /* Matsushita MN10200 */ ++#define EM_PJ 91 /* picoJava */ ++#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ ++#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ ++#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ ++#define EM_NUM 95 ++ ++/* If it is necessary to assign new unofficial EM_* values, please ++ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the ++ chances of collision with official or non-GNU unofficial values. */ ++ ++#define EM_ALPHA 0x9026 ++ ++/* Legal values for e_version (version). */ ++ ++#define EV_NONE 0 /* Invalid ELF version */ ++#define EV_CURRENT 1 /* Current version */ ++#define EV_NUM 2 ++ ++/* Section header. */ ++ ++typedef struct ++{ ++ Elf32_Word sh_name; /* Section name (string tbl index) */ ++ Elf32_Word sh_type; /* Section type */ ++ Elf32_Word sh_flags; /* Section flags */ ++ Elf32_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf32_Off sh_offset; /* Section file offset */ ++ Elf32_Word sh_size; /* Section size in bytes */ ++ Elf32_Word sh_link; /* Link to another section */ ++ Elf32_Word sh_info; /* Additional section information */ ++ Elf32_Word sh_addralign; /* Section alignment */ ++ Elf32_Word sh_entsize; /* Entry size if section holds table */ ++} Elf32_Shdr; ++ ++typedef struct ++{ ++ Elf64_Word sh_name; /* Section name (string tbl index) */ ++ Elf64_Word sh_type; /* Section type */ ++ Elf64_Xword sh_flags; /* Section flags */ ++ Elf64_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf64_Off sh_offset; /* Section file offset */ ++ Elf64_Xword sh_size; /* Section size in bytes */ ++ Elf64_Word sh_link; /* Link to another section */ ++ Elf64_Word sh_info; /* Additional section information */ ++ Elf64_Xword sh_addralign; /* Section alignment */ ++ Elf64_Xword sh_entsize; /* Entry size if section holds table */ ++} Elf64_Shdr; ++ ++/* Special section indices. */ ++ ++#define SHN_UNDEF 0 /* Undefined section */ ++#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ ++#define SHN_LOPROC 0xff00 /* Start of processor-specific */ ++#define SHN_HIPROC 0xff1f /* End of processor-specific */ ++#define SHN_LOOS 0xff20 /* Start of OS-specific */ ++#define SHN_HIOS 0xff3f /* End of OS-specific */ ++#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ ++#define SHN_COMMON 0xfff2 /* Associated symbol is common */ ++#define SHN_XINDEX 0xffff /* Index is in extra table. */ ++#define SHN_HIRESERVE 0xffff /* End of reserved indices */ ++ ++/* Legal values for sh_type (section type). */ ++ ++#define SHT_NULL 0 /* Section header table entry unused */ ++#define SHT_PROGBITS 1 /* Program data */ ++#define SHT_SYMTAB 2 /* Symbol table */ ++#define SHT_STRTAB 3 /* String table */ ++#define SHT_RELA 4 /* Relocation entries with addends */ ++#define SHT_HASH 5 /* Symbol hash table */ ++#define SHT_DYNAMIC 6 /* Dynamic linking information */ ++#define SHT_NOTE 7 /* Notes */ ++#define SHT_NOBITS 8 /* Program space with no data (bss) */ ++#define SHT_REL 9 /* Relocation entries, no addends */ ++#define SHT_SHLIB 10 /* Reserved */ ++#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ ++#define SHT_INIT_ARRAY 14 /* Array of constructors */ ++#define SHT_FINI_ARRAY 15 /* Array of destructors */ ++#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ ++#define SHT_GROUP 17 /* Section group */ ++#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ ++#define SHT_NUM 19 /* Number of defined types. */ ++#define SHT_LOOS 0x60000000 /* Start OS-specific */ ++#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ ++#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ ++#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ ++#define SHT_SUNW_move 0x6ffffffa ++#define SHT_SUNW_COMDAT 0x6ffffffb ++#define SHT_SUNW_syminfo 0x6ffffffc ++#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ ++#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ ++#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ ++#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ ++#define SHT_HIOS 0x6fffffff /* End OS-specific type */ ++#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define SHT_LOUSER 0x80000000 /* Start of application-specific */ ++#define SHT_HIUSER 0x8fffffff /* End of application-specific */ ++ ++/* Legal values for sh_flags (section flags). */ ++ ++#define SHF_WRITE (1 << 0) /* Writable */ ++#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ ++#define SHF_EXECINSTR (1 << 2) /* Executable */ ++#define SHF_MERGE (1 << 4) /* Might be merged */ ++#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ ++#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ ++#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ ++#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling ++ required */ ++#define SHF_GROUP (1 << 9) /* Section is member of a group. */ ++#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ ++#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ ++#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ ++ ++/* Section group handling. */ ++#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ ++ ++/* Symbol table entry. */ ++ ++typedef struct ++{ ++ Elf32_Word st_name; /* Symbol name (string tbl index) */ ++ Elf32_Addr st_value; /* Symbol value */ ++ Elf32_Word st_size; /* Symbol size */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf32_Section st_shndx; /* Section index */ ++} Elf32_Sym; ++ ++typedef struct ++{ ++ Elf64_Word st_name; /* Symbol name (string tbl index) */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf64_Section st_shndx; /* Section index */ ++ Elf64_Addr st_value; /* Symbol value */ ++ Elf64_Xword st_size; /* Symbol size */ ++} Elf64_Sym; ++ ++/* The syminfo section if available contains additional information about ++ every dynamic symbol. */ ++ ++typedef struct ++{ ++ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf32_Half si_flags; /* Per symbol flags */ ++} Elf32_Syminfo; ++ ++typedef struct ++{ ++ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf64_Half si_flags; /* Per symbol flags */ ++} Elf64_Syminfo; ++ ++/* Possible values for si_boundto. */ ++#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ ++#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ ++#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ ++ ++/* Possible bitmasks for si_flags. */ ++#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ ++#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ ++#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ ++#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy ++ loaded */ ++/* Syminfo version values. */ ++#define SYMINFO_NONE 0 ++#define SYMINFO_CURRENT 1 ++#define SYMINFO_NUM 2 ++ ++ ++/* How to extract and insert information held in the st_info field. */ ++ ++#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) ++#define ELF32_ST_TYPE(val) ((val) & 0xf) ++#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) ++ ++/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ ++#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) ++#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) ++#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) ++ ++/* Legal values for ST_BIND subfield of st_info (symbol binding). */ ++ ++#define STB_LOCAL 0 /* Local symbol */ ++#define STB_GLOBAL 1 /* Global symbol */ ++#define STB_WEAK 2 /* Weak symbol */ ++#define STB_NUM 3 /* Number of defined types. */ ++#define STB_LOOS 10 /* Start of OS-specific */ ++#define STB_HIOS 12 /* End of OS-specific */ ++#define STB_LOPROC 13 /* Start of processor-specific */ ++#define STB_HIPROC 15 /* End of processor-specific */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_NOTYPE 0 /* Symbol type is unspecified */ ++#define STT_OBJECT 1 /* Symbol is a data object */ ++#define STT_FUNC 2 /* Symbol is a code object */ ++#define STT_SECTION 3 /* Symbol associated with a section */ ++#define STT_FILE 4 /* Symbol's name is file name */ ++#define STT_COMMON 5 /* Symbol is a common data object */ ++#define STT_TLS 6 /* Symbol is thread-local data object*/ ++#define STT_NUM 7 /* Number of defined types. */ ++#define STT_LOOS 10 /* Start of OS-specific */ ++#define STT_HIOS 12 /* End of OS-specific */ ++#define STT_LOPROC 13 /* Start of processor-specific */ ++#define STT_HIPROC 15 /* End of processor-specific */ ++ ++ ++/* Symbol table indices are found in the hash buckets and chain table ++ of a symbol hash table section. This special index value indicates ++ the end of a chain, meaning no further symbols are found in that bucket. */ ++ ++#define STN_UNDEF 0 /* End of a chain. */ ++ ++ ++/* How to extract and insert information held in the st_other field. */ ++ ++#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) ++ ++/* For ELF64 the definitions are the same. */ ++#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) ++ ++/* Symbol visibility specification encoded in the st_other field. */ ++#define STV_DEFAULT 0 /* Default symbol visibility rules */ ++#define STV_INTERNAL 1 /* Processor specific hidden class */ ++#define STV_HIDDEN 2 /* Sym unavailable in other modules */ ++#define STV_PROTECTED 3 /* Not preemptible, not exported */ ++ ++ ++/* Relocation table entry without addend (in section of type SHT_REL). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++} Elf32_Rel; ++ ++/* I have seen two different definitions of the Elf64_Rel and ++ Elf64_Rela structures, so we'll leave them out until Novell (or ++ whoever) gets their act together. */ ++/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++} Elf64_Rel; ++ ++/* Relocation table entry with addend (in section of type SHT_RELA). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++ Elf32_Sword r_addend; /* Addend */ ++} Elf32_Rela; ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++ Elf64_Sxword r_addend; /* Addend */ ++} Elf64_Rela; ++ ++/* How to extract and insert information held in the r_info field. */ ++ ++#define ELF32_R_SYM(val) ((val) >> 8) ++#define ELF32_R_TYPE(val) ((val) & 0xff) ++#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) ++ ++#define ELF64_R_SYM(i) ((i) >> 32) ++#define ELF64_R_TYPE(i) ((i) & 0xffffffff) ++#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) ++ ++/* Program segment header. */ ++ ++typedef struct ++{ ++ Elf32_Word p_type; /* Segment type */ ++ Elf32_Off p_offset; /* Segment file offset */ ++ Elf32_Addr p_vaddr; /* Segment virtual address */ ++ Elf32_Addr p_paddr; /* Segment physical address */ ++ Elf32_Word p_filesz; /* Segment size in file */ ++ Elf32_Word p_memsz; /* Segment size in memory */ ++ Elf32_Word p_flags; /* Segment flags */ ++ Elf32_Word p_align; /* Segment alignment */ ++} Elf32_Phdr; ++ ++typedef struct ++{ ++ Elf64_Word p_type; /* Segment type */ ++ Elf64_Word p_flags; /* Segment flags */ ++ Elf64_Off p_offset; /* Segment file offset */ ++ Elf64_Addr p_vaddr; /* Segment virtual address */ ++ Elf64_Addr p_paddr; /* Segment physical address */ ++ Elf64_Xword p_filesz; /* Segment size in file */ ++ Elf64_Xword p_memsz; /* Segment size in memory */ ++ Elf64_Xword p_align; /* Segment alignment */ ++} Elf64_Phdr; ++ ++/* Legal values for p_type (segment type). */ ++ ++#define PT_NULL 0 /* Program header table entry unused */ ++#define PT_LOAD 1 /* Loadable program segment */ ++#define PT_DYNAMIC 2 /* Dynamic linking information */ ++#define PT_INTERP 3 /* Program interpreter */ ++#define PT_NOTE 4 /* Auxiliary information */ ++#define PT_SHLIB 5 /* Reserved */ ++#define PT_PHDR 6 /* Entry for header table itself */ ++#define PT_TLS 7 /* Thread-local storage segment */ ++#define PT_NUM 8 /* Number of defined types */ ++#define PT_LOOS 0x60000000 /* Start of OS-specific */ ++#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ ++#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ ++#define PT_LOSUNW 0x6ffffffa ++#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ ++#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ ++#define PT_HISUNW 0x6fffffff ++#define PT_HIOS 0x6fffffff /* End of OS-specific */ ++#define PT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define PT_HIPROC 0x7fffffff /* End of processor-specific */ ++ ++/* Legal values for p_flags (segment flags). */ ++ ++#define PF_X (1 << 0) /* Segment is executable */ ++#define PF_W (1 << 1) /* Segment is writable */ ++#define PF_R (1 << 2) /* Segment is readable */ ++#define PF_MASKOS 0x0ff00000 /* OS-specific */ ++#define PF_MASKPROC 0xf0000000 /* Processor-specific */ ++ ++/* Legal values for note segment descriptor types for core files. */ ++ ++#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ ++#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ ++#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ ++#define NT_PRXREG 4 /* Contains copy of prxregset struct */ ++#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ ++#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ ++#define NT_AUXV 6 /* Contains copy of auxv array */ ++#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ ++#define NT_ASRS 8 /* Contains copy of asrset struct */ ++#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ ++#define NT_PSINFO 13 /* Contains copy of psinfo struct */ ++#define NT_PRCRED 14 /* Contains copy of prcred struct */ ++#define NT_UTSNAME 15 /* Contains copy of utsname struct */ ++#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ ++#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ ++#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct*/ ++ ++/* Legal values for the note segment descriptor types for object files. */ ++ ++#define NT_VERSION 1 /* Contains a version string. */ ++ ++ ++/* Dynamic section entry. */ ++ ++typedef struct ++{ ++ Elf32_Sword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf32_Word d_val; /* Integer value */ ++ Elf32_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf32_Dyn; ++ ++typedef struct ++{ ++ Elf64_Sxword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf64_Xword d_val; /* Integer value */ ++ Elf64_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf64_Dyn; ++ ++/* Legal values for d_tag (dynamic entry type). */ ++ ++#define DT_NULL 0 /* Marks end of dynamic section */ ++#define DT_NEEDED 1 /* Name of needed library */ ++#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ ++#define DT_PLTGOT 3 /* Processor defined value */ ++#define DT_HASH 4 /* Address of symbol hash table */ ++#define DT_STRTAB 5 /* Address of string table */ ++#define DT_SYMTAB 6 /* Address of symbol table */ ++#define DT_RELA 7 /* Address of Rela relocs */ ++#define DT_RELASZ 8 /* Total size of Rela relocs */ ++#define DT_RELAENT 9 /* Size of one Rela reloc */ ++#define DT_STRSZ 10 /* Size of string table */ ++#define DT_SYMENT 11 /* Size of one symbol table entry */ ++#define DT_INIT 12 /* Address of init function */ ++#define DT_FINI 13 /* Address of termination function */ ++#define DT_SONAME 14 /* Name of shared object */ ++#define DT_RPATH 15 /* Library search path (deprecated) */ ++#define DT_SYMBOLIC 16 /* Start symbol search here */ ++#define DT_REL 17 /* Address of Rel relocs */ ++#define DT_RELSZ 18 /* Total size of Rel relocs */ ++#define DT_RELENT 19 /* Size of one Rel reloc */ ++#define DT_PLTREL 20 /* Type of reloc in PLT */ ++#define DT_DEBUG 21 /* For debugging; unspecified */ ++#define DT_TEXTREL 22 /* Reloc might modify .text */ ++#define DT_JMPREL 23 /* Address of PLT relocs */ ++#define DT_BIND_NOW 24 /* Process relocations of object */ ++#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ ++#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ ++#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ ++#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ ++#define DT_RUNPATH 29 /* Library search path */ ++#define DT_FLAGS 30 /* Flags for the object being loaded */ ++#define DT_ENCODING 32 /* Start of encoded range */ ++#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ ++#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ ++#define DT_NUM 34 /* Number used */ ++#define DT_LOOS 0x6000000d /* Start of OS-specific */ ++#define DT_HIOS 0x6ffff000 /* End of OS-specific */ ++#define DT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define DT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ ++ ++/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the ++ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's ++ approach. */ ++#define DT_VALRNGLO 0x6ffffd00 ++#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ ++#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ ++#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ ++#define DT_CHECKSUM 0x6ffffdf8 ++#define DT_PLTPADSZ 0x6ffffdf9 ++#define DT_MOVEENT 0x6ffffdfa ++#define DT_MOVESZ 0x6ffffdfb ++#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ ++#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting ++ the following DT_* entry. */ ++#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ ++#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ ++#define DT_VALRNGHI 0x6ffffdff ++#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ ++#define DT_VALNUM 12 ++ ++/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the ++ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. ++ ++ If any adjustment is made to the ELF object after it has been ++ built these entries will need to be adjusted. */ ++#define DT_ADDRRNGLO 0x6ffffe00 ++#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ ++#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ ++#define DT_CONFIG 0x6ffffefa /* Configuration information. */ ++#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ ++#define DT_AUDIT 0x6ffffefc /* Object auditing. */ ++#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ ++#define DT_MOVETAB 0x6ffffefe /* Move table. */ ++#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ ++#define DT_ADDRRNGHI 0x6ffffeff ++#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ ++#define DT_ADDRNUM 10 ++ ++/* The versioning entry types. The next are defined as part of the ++ GNU extension. */ ++#define DT_VERSYM 0x6ffffff0 ++ ++#define DT_RELACOUNT 0x6ffffff9 ++#define DT_RELCOUNT 0x6ffffffa ++ ++/* These were chosen by Sun. */ ++#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ ++#define DT_VERDEF 0x6ffffffc /* Address of version definition ++ table */ ++#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ ++#define DT_VERNEED 0x6ffffffe /* Address of table with needed ++ versions */ ++#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ ++#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ ++#define DT_VERSIONTAGNUM 16 ++ ++/* Sun added these machine-independent extensions in the "processor-specific" ++ range. Be compatible. */ ++#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ ++#define DT_FILTER 0x7fffffff /* Shared object to get values from */ ++#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) ++#define DT_EXTRANUM 3 ++ ++/* Values of `d_un.d_val' in the DT_FLAGS entry. */ ++#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ ++#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ ++#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ ++#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ ++#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ ++ ++/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 ++ entry in the dynamic section. */ ++#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ ++#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ ++#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ ++#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ ++#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ ++#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ ++#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ ++#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ ++#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ ++#define DF_1_TRANS 0x00000200 ++#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ ++#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ ++#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ ++#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ ++#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ ++#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ ++#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ ++ ++/* Flags for the feature selection in DT_FEATURE_1. */ ++#define DTF_1_PARINIT 0x00000001 ++#define DTF_1_CONFEXP 0x00000002 ++ ++/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ ++#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ ++#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not ++ generally available. */ ++ ++/* Version definition sections. */ ++ ++typedef struct ++{ ++ Elf32_Half vd_version; /* Version revision */ ++ Elf32_Half vd_flags; /* Version information */ ++ Elf32_Half vd_ndx; /* Version Index */ ++ Elf32_Half vd_cnt; /* Number of associated aux entries */ ++ Elf32_Word vd_hash; /* Version name hash value */ ++ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf32_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf32_Verdef; ++ ++typedef struct ++{ ++ Elf64_Half vd_version; /* Version revision */ ++ Elf64_Half vd_flags; /* Version information */ ++ Elf64_Half vd_ndx; /* Version Index */ ++ Elf64_Half vd_cnt; /* Number of associated aux entries */ ++ Elf64_Word vd_hash; /* Version name hash value */ ++ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf64_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf64_Verdef; ++ ++ ++/* Legal values for vd_version (version revision). */ ++#define VER_DEF_NONE 0 /* No version */ ++#define VER_DEF_CURRENT 1 /* Current version */ ++#define VER_DEF_NUM 2 /* Given version number */ ++ ++/* Legal values for vd_flags (version information flags). */ ++#define VER_FLG_BASE 0x1 /* Version definition of file itself */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++/* Versym symbol index values. */ ++#define VER_NDX_LOCAL 0 /* Symbol is local. */ ++#define VER_NDX_GLOBAL 1 /* Symbol is global. */ ++#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ ++#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ ++ ++/* Auxialiary version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vda_name; /* Version or dependency names */ ++ Elf32_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf32_Verdaux; ++ ++typedef struct ++{ ++ Elf64_Word vda_name; /* Version or dependency names */ ++ Elf64_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf64_Verdaux; ++ ++ ++/* Version dependency section. */ ++ ++typedef struct ++{ ++ Elf32_Half vn_version; /* Version of structure */ ++ Elf32_Half vn_cnt; /* Number of associated aux entries */ ++ Elf32_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf32_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf32_Verneed; ++ ++typedef struct ++{ ++ Elf64_Half vn_version; /* Version of structure */ ++ Elf64_Half vn_cnt; /* Number of associated aux entries */ ++ Elf64_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf64_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf64_Verneed; ++ ++ ++/* Legal values for vn_version (version revision). */ ++#define VER_NEED_NONE 0 /* No version */ ++#define VER_NEED_CURRENT 1 /* Current version */ ++#define VER_NEED_NUM 2 /* Given version number */ ++ ++/* Auxiliary needed version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vna_hash; /* Hash value of dependency name */ ++ Elf32_Half vna_flags; /* Dependency specific information */ ++ Elf32_Half vna_other; /* Unused */ ++ Elf32_Word vna_name; /* Dependency name string offset */ ++ Elf32_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf32_Vernaux; ++ ++typedef struct ++{ ++ Elf64_Word vna_hash; /* Hash value of dependency name */ ++ Elf64_Half vna_flags; /* Dependency specific information */ ++ Elf64_Half vna_other; /* Unused */ ++ Elf64_Word vna_name; /* Dependency name string offset */ ++ Elf64_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf64_Vernaux; ++ ++ ++/* Legal values for vna_flags. */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++ ++/* Auxiliary vector. */ ++ ++/* This vector is normally only used by the program interpreter. The ++ usual definition in an ABI supplement uses the name auxv_t. The ++ vector is not usually defined in a standard file, but it ++ can't hurt. We rename it to avoid conflicts. The sizes of these ++ types are an arrangement between the exec server and the program ++ interpreter, so we don't fully specify them here. */ ++ ++typedef struct ++{ ++ int a_type; /* Entry type */ ++ union ++ { ++ long int a_val; /* Integer value */ ++ void *a_ptr; /* Pointer value */ ++ void (*a_fcn) (void); /* Function pointer value */ ++ } a_un; ++} Elf32_auxv_t; ++ ++typedef struct ++{ ++ long int a_type; /* Entry type */ ++ union ++ { ++ long int a_val; /* Integer value */ ++ void *a_ptr; /* Pointer value */ ++ void (*a_fcn) (void); /* Function pointer value */ ++ } a_un; ++} Elf64_auxv_t; ++ ++/* Legal values for a_type (entry type). */ ++ ++#define AT_NULL 0 /* End of vector */ ++#define AT_IGNORE 1 /* Entry should be ignored */ ++#define AT_EXECFD 2 /* File descriptor of program */ ++#define AT_PHDR 3 /* Program headers for program */ ++#define AT_PHENT 4 /* Size of program header entry */ ++#define AT_PHNUM 5 /* Number of program headers */ ++#define AT_PAGESZ 6 /* System page size */ ++#define AT_BASE 7 /* Base address of interpreter */ ++#define AT_FLAGS 8 /* Flags */ ++#define AT_ENTRY 9 /* Entry point of program */ ++#define AT_NOTELF 10 /* Program is not ELF */ ++#define AT_UID 11 /* Real uid */ ++#define AT_EUID 12 /* Effective uid */ ++#define AT_GID 13 /* Real gid */ ++#define AT_EGID 14 /* Effective gid */ ++#define AT_CLKTCK 17 /* Frequency of times() */ ++ ++/* Some more special a_type values describing the hardware. */ ++#define AT_PLATFORM 15 /* String identifying platform. */ ++#define AT_HWCAP 16 /* Machine dependent hints about ++ processor capabilities. */ ++ ++/* This entry gives some information about the FPU initialization ++ performed by the kernel. */ ++#define AT_FPUCW 18 /* Used FPU control word. */ ++ ++/* Cache block sizes. */ ++#define AT_DCACHEBSIZE 19 /* Data cache block size. */ ++#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ ++#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ ++ ++/* A special ignored value for PPC, used by the kernel to control the ++ interpretation of the AUXV. Must be > 16. */ ++#define AT_IGNOREPPC 22 /* Entry should be ignored. */ ++ ++#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ ++ ++/* Pointer to the global system page used for system calls and other ++ nice things. */ ++#define AT_SYSINFO 32 ++#define AT_SYSINFO_EHDR 33 ++ ++ ++/* Note section contents. Each entry in the note section begins with ++ a header of a fixed form. */ ++ ++typedef struct ++{ ++ Elf32_Word n_namesz; /* Length of the note's name. */ ++ Elf32_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf32_Word n_type; /* Type of the note. */ ++} Elf32_Nhdr; ++ ++typedef struct ++{ ++ Elf64_Word n_namesz; /* Length of the note's name. */ ++ Elf64_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf64_Word n_type; /* Type of the note. */ ++} Elf64_Nhdr; ++ ++/* Known names of notes. */ ++ ++/* Solaris entries in the note section have this name. */ ++#define ELF_NOTE_SOLARIS "SUNW Solaris" ++ ++/* Note entries for GNU systems have this name. */ ++#define ELF_NOTE_GNU "GNU" ++ ++ ++/* Defined types of notes for Solaris. */ ++ ++/* Value of descriptor (one word) is desired pagesize for the binary. */ ++#define ELF_NOTE_PAGESIZE_HINT 1 ++ ++ ++/* Defined note types for GNU systems. */ ++ ++/* ABI information. The descriptor consists of words: ++ word 0: OS descriptor ++ word 1: major version of the ABI ++ word 2: minor version of the ABI ++ word 3: subminor version of the ABI ++*/ ++#define ELF_NOTE_ABI 1 ++ ++/* Known OSes. These value can appear in word 0 of an ELF_NOTE_ABI ++ note section entry. */ ++#define ELF_NOTE_OS_LINUX 0 ++#define ELF_NOTE_OS_GNU 1 ++#define ELF_NOTE_OS_SOLARIS2 2 ++#define ELF_NOTE_OS_FREEBSD 3 ++ ++ ++/* Move records. */ ++typedef struct ++{ ++ Elf32_Xword m_value; /* Symbol value. */ ++ Elf32_Word m_info; /* Size and index. */ ++ Elf32_Word m_poffset; /* Symbol offset. */ ++ Elf32_Half m_repeat; /* Repeat count. */ ++ Elf32_Half m_stride; /* Stride info. */ ++} Elf32_Move; ++ ++typedef struct ++{ ++ Elf64_Xword m_value; /* Symbol value. */ ++ Elf64_Xword m_info; /* Size and index. */ ++ Elf64_Xword m_poffset; /* Symbol offset. */ ++ Elf64_Half m_repeat; /* Repeat count. */ ++ Elf64_Half m_stride; /* Stride info. */ ++} Elf64_Move; ++ ++/* Macro to construct move records. */ ++#define ELF32_M_SYM(info) ((info) >> 8) ++#define ELF32_M_SIZE(info) ((unsigned char) (info)) ++#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) ++ ++#define ELF64_M_SYM(info) ELF32_M_SYM (info) ++#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) ++#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) ++ ++ ++/* Motorola 68k specific definitions. */ ++ ++/* Values for Elf32_Ehdr.e_flags. */ ++#define EF_CPU32 0x00810000 ++ ++/* m68k relocs. */ ++ ++#define R_68K_NONE 0 /* No reloc */ ++#define R_68K_32 1 /* Direct 32 bit */ ++#define R_68K_16 2 /* Direct 16 bit */ ++#define R_68K_8 3 /* Direct 8 bit */ ++#define R_68K_PC32 4 /* PC relative 32 bit */ ++#define R_68K_PC16 5 /* PC relative 16 bit */ ++#define R_68K_PC8 6 /* PC relative 8 bit */ ++#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ ++#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ ++#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ ++#define R_68K_GOT32O 10 /* 32 bit GOT offset */ ++#define R_68K_GOT16O 11 /* 16 bit GOT offset */ ++#define R_68K_GOT8O 12 /* 8 bit GOT offset */ ++#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ ++#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ ++#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ ++#define R_68K_PLT32O 16 /* 32 bit PLT offset */ ++#define R_68K_PLT16O 17 /* 16 bit PLT offset */ ++#define R_68K_PLT8O 18 /* 8 bit PLT offset */ ++#define R_68K_COPY 19 /* Copy symbol at runtime */ ++#define R_68K_GLOB_DAT 20 /* Create GOT entry */ ++#define R_68K_JMP_SLOT 21 /* Create PLT entry */ ++#define R_68K_RELATIVE 22 /* Adjust by program base */ ++/* Keep this the last entry. */ ++#define R_68K_NUM 23 ++ ++/* Intel 80386 specific definitions. */ ++ ++/* i386 relocs. */ ++ ++#define R_386_NONE 0 /* No reloc */ ++#define R_386_32 1 /* Direct 32 bit */ ++#define R_386_PC32 2 /* PC relative 32 bit */ ++#define R_386_GOT32 3 /* 32 bit GOT entry */ ++#define R_386_PLT32 4 /* 32 bit PLT address */ ++#define R_386_COPY 5 /* Copy symbol at runtime */ ++#define R_386_GLOB_DAT 6 /* Create GOT entry */ ++#define R_386_JMP_SLOT 7 /* Create PLT entry */ ++#define R_386_RELATIVE 8 /* Adjust by program base */ ++#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ ++#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ ++#define R_386_32PLT 11 ++#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ ++#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS ++ block offset */ ++#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block ++ offset */ ++#define R_386_TLS_LE 17 /* Offset relative to static TLS ++ block */ ++#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of ++ general dynamic thread local data */ ++#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of ++ local dynamic thread local data ++ in LE code */ ++#define R_386_16 20 ++#define R_386_PC16 21 ++#define R_386_8 22 ++#define R_386_PC8 23 ++#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic ++ thread local data */ ++#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ ++#define R_386_TLS_GD_CALL 26 /* Relocation for call to ++ __tls_get_addr() */ ++#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ ++#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic ++ thread local data in LE code */ ++#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ ++#define R_386_TLS_LDM_CALL 30 /* Relocation for call to ++ __tls_get_addr() in LDM code */ ++#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ ++#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ ++#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS ++ block offset */ ++#define R_386_TLS_LE_32 34 /* Negated offset relative to static ++ TLS block */ ++#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ ++#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ ++#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ ++/* Keep this the last entry. */ ++#define R_386_NUM 38 ++ ++/* SUN SPARC specific definitions. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_REGISTER 13 /* Global register reserved to app. */ ++ ++/* Values for Elf64_Ehdr.e_flags. */ ++ ++#define EF_SPARCV9_MM 3 ++#define EF_SPARCV9_TSO 0 ++#define EF_SPARCV9_PSO 1 ++#define EF_SPARCV9_RMO 2 ++#define EF_SPARC_LEDATA 0x800000 /* little endian data */ ++#define EF_SPARC_EXT_MASK 0xFFFF00 ++#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ ++#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ ++#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ ++#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ ++ ++/* SPARC relocs. */ ++ ++#define R_SPARC_NONE 0 /* No reloc */ ++#define R_SPARC_8 1 /* Direct 8 bit */ ++#define R_SPARC_16 2 /* Direct 16 bit */ ++#define R_SPARC_32 3 /* Direct 32 bit */ ++#define R_SPARC_DISP8 4 /* PC relative 8 bit */ ++#define R_SPARC_DISP16 5 /* PC relative 16 bit */ ++#define R_SPARC_DISP32 6 /* PC relative 32 bit */ ++#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ ++#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ ++#define R_SPARC_HI22 9 /* High 22 bit */ ++#define R_SPARC_22 10 /* Direct 22 bit */ ++#define R_SPARC_13 11 /* Direct 13 bit */ ++#define R_SPARC_LO10 12 /* Truncated 10 bit */ ++#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ ++#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ ++#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ ++#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ ++#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ ++#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ ++#define R_SPARC_COPY 19 /* Copy symbol at runtime */ ++#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ ++#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ ++#define R_SPARC_RELATIVE 22 /* Adjust by program base */ ++#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ ++ ++/* Additional Sparc64 relocs. */ ++ ++#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ ++#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ ++#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ ++#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ ++#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ ++#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ ++#define R_SPARC_10 30 /* Direct 10 bit */ ++#define R_SPARC_11 31 /* Direct 11 bit */ ++#define R_SPARC_64 32 /* Direct 64 bit */ ++#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ ++#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ ++#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ ++#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ ++#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ ++#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ ++#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ ++#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ ++#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ ++#define R_SPARC_7 43 /* Direct 7 bit */ ++#define R_SPARC_5 44 /* Direct 5 bit */ ++#define R_SPARC_6 45 /* Direct 6 bit */ ++#define R_SPARC_DISP64 46 /* PC relative 64 bit */ ++#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ ++#define R_SPARC_HIX22 48 /* High 22 bit complemented */ ++#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ ++#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ ++#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ ++#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ ++#define R_SPARC_REGISTER 53 /* Global register usage */ ++#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ ++#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ ++#define R_SPARC_TLS_GD_HI22 56 ++#define R_SPARC_TLS_GD_LO10 57 ++#define R_SPARC_TLS_GD_ADD 58 ++#define R_SPARC_TLS_GD_CALL 59 ++#define R_SPARC_TLS_LDM_HI22 60 ++#define R_SPARC_TLS_LDM_LO10 61 ++#define R_SPARC_TLS_LDM_ADD 62 ++#define R_SPARC_TLS_LDM_CALL 63 ++#define R_SPARC_TLS_LDO_HIX22 64 ++#define R_SPARC_TLS_LDO_LOX10 65 ++#define R_SPARC_TLS_LDO_ADD 66 ++#define R_SPARC_TLS_IE_HI22 67 ++#define R_SPARC_TLS_IE_LO10 68 ++#define R_SPARC_TLS_IE_LD 69 ++#define R_SPARC_TLS_IE_LDX 70 ++#define R_SPARC_TLS_IE_ADD 71 ++#define R_SPARC_TLS_LE_HIX22 72 ++#define R_SPARC_TLS_LE_LOX10 73 ++#define R_SPARC_TLS_DTPMOD32 74 ++#define R_SPARC_TLS_DTPMOD64 75 ++#define R_SPARC_TLS_DTPOFF32 76 ++#define R_SPARC_TLS_DTPOFF64 77 ++#define R_SPARC_TLS_TPOFF32 78 ++#define R_SPARC_TLS_TPOFF64 79 ++/* Keep this the last entry. */ ++#define R_SPARC_NUM 80 ++ ++/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ ++ ++#define DT_SPARC_REGISTER 0x70000001 ++#define DT_SPARC_NUM 2 ++ ++/* Bits present in AT_HWCAP, primarily for Sparc32. */ ++ ++#define HWCAP_SPARC_FLUSH 1 /* The cpu supports flush insn. */ ++#define HWCAP_SPARC_STBAR 2 ++#define HWCAP_SPARC_SWAP 4 ++#define HWCAP_SPARC_MULDIV 8 ++#define HWCAP_SPARC_V9 16 /* The cpu is v9, so v8plus is ok. */ ++#define HWCAP_SPARC_ULTRA3 32 ++ ++/* MIPS R3000 specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ ++#define EF_MIPS_PIC 2 /* Contains PIC code */ ++#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ ++#define EF_MIPS_XGOT 8 ++#define EF_MIPS_64BIT_WHIRL 16 ++#define EF_MIPS_ABI2 32 ++#define EF_MIPS_ABI_ON32 64 ++#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ ++ ++/* Legal values for MIPS architecture level. */ ++ ++#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* The following are non-official names and should not be used. */ ++ ++#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* Special section indices. */ ++ ++#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ ++#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ ++#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ ++#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ ++#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ ++#define SHT_MIPS_MSYM 0x70000001 ++#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ ++#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ ++#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ ++#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ ++#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ ++#define SHT_MIPS_PACKAGE 0x70000007 ++#define SHT_MIPS_PACKSYM 0x70000008 ++#define SHT_MIPS_RELD 0x70000009 ++#define SHT_MIPS_IFACE 0x7000000b ++#define SHT_MIPS_CONTENT 0x7000000c ++#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ ++#define SHT_MIPS_SHDR 0x70000010 ++#define SHT_MIPS_FDESC 0x70000011 ++#define SHT_MIPS_EXTSYM 0x70000012 ++#define SHT_MIPS_DENSE 0x70000013 ++#define SHT_MIPS_PDESC 0x70000014 ++#define SHT_MIPS_LOCSYM 0x70000015 ++#define SHT_MIPS_AUXSYM 0x70000016 ++#define SHT_MIPS_OPTSYM 0x70000017 ++#define SHT_MIPS_LOCSTR 0x70000018 ++#define SHT_MIPS_LINE 0x70000019 ++#define SHT_MIPS_RFDESC 0x7000001a ++#define SHT_MIPS_DELTASYM 0x7000001b ++#define SHT_MIPS_DELTAINST 0x7000001c ++#define SHT_MIPS_DELTACLASS 0x7000001d ++#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ ++#define SHT_MIPS_DELTADECL 0x7000001f ++#define SHT_MIPS_SYMBOL_LIB 0x70000020 ++#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ ++#define SHT_MIPS_TRANSLATE 0x70000022 ++#define SHT_MIPS_PIXIE 0x70000023 ++#define SHT_MIPS_XLATE 0x70000024 ++#define SHT_MIPS_XLATE_DEBUG 0x70000025 ++#define SHT_MIPS_WHIRL 0x70000026 ++#define SHT_MIPS_EH_REGION 0x70000027 ++#define SHT_MIPS_XLATE_OLD 0x70000028 ++#define SHT_MIPS_PDR_EXCEPTION 0x70000029 ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ ++#define SHF_MIPS_MERGE 0x20000000 ++#define SHF_MIPS_ADDR 0x40000000 ++#define SHF_MIPS_STRINGS 0x80000000 ++#define SHF_MIPS_NOSTRIP 0x08000000 ++#define SHF_MIPS_LOCAL 0x04000000 ++#define SHF_MIPS_NAMES 0x02000000 ++#define SHF_MIPS_NODUPE 0x01000000 ++ ++ ++/* Symbol tables. */ ++ ++/* MIPS specific values for `st_other'. */ ++#define STO_MIPS_DEFAULT 0x0 ++#define STO_MIPS_INTERNAL 0x1 ++#define STO_MIPS_HIDDEN 0x2 ++#define STO_MIPS_PROTECTED 0x3 ++#define STO_MIPS_SC_ALIGN_UNUSED 0xff ++ ++/* MIPS specific values for `st_info'. */ ++#define STB_MIPS_SPLIT_COMMON 13 ++ ++/* Entries found in sections of type SHT_MIPS_GPTAB. */ ++ ++typedef union ++{ ++ struct ++ { ++ Elf32_Word gt_current_g_value; /* -G value used for compilation */ ++ Elf32_Word gt_unused; /* Not used */ ++ } gt_header; /* First entry in section */ ++ struct ++ { ++ Elf32_Word gt_g_value; /* If this value were used for -G */ ++ Elf32_Word gt_bytes; /* This many bytes would be used */ ++ } gt_entry; /* Subsequent entries in section */ ++} Elf32_gptab; ++ ++/* Entry found in sections of type SHT_MIPS_REGINFO. */ ++ ++typedef struct ++{ ++ Elf32_Word ri_gprmask; /* General registers used */ ++ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ ++ Elf32_Sword ri_gp_value; /* $gp register value */ ++} Elf32_RegInfo; ++ ++/* Entries found in sections of type SHT_MIPS_OPTIONS. */ ++ ++typedef struct ++{ ++ unsigned char kind; /* Determines interpretation of the ++ variable part of descriptor. */ ++ unsigned char size; /* Size of descriptor, including header. */ ++ Elf32_Section section; /* Section header index of section affected, ++ 0 for global options. */ ++ Elf32_Word info; /* Kind-specific information. */ ++} Elf_Options; ++ ++/* Values for `kind' field in Elf_Options. */ ++ ++#define ODK_NULL 0 /* Undefined. */ ++#define ODK_REGINFO 1 /* Register usage information. */ ++#define ODK_EXCEPTIONS 2 /* Exception processing options. */ ++#define ODK_PAD 3 /* Section padding options. */ ++#define ODK_HWPATCH 4 /* Hardware workarounds performed */ ++#define ODK_FILL 5 /* record the fill value used by the linker. */ ++#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ ++#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ ++#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ ++ ++/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ ++ ++#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ ++#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ ++#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ ++#define OEX_SMM 0x20000 /* Force sequential memory mode? */ ++#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ ++#define OEX_PRECISEFP OEX_FPDBUG ++#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ ++ ++#define OEX_FPU_INVAL 0x10 ++#define OEX_FPU_DIV0 0x08 ++#define OEX_FPU_OFLO 0x04 ++#define OEX_FPU_UFLO 0x02 ++#define OEX_FPU_INEX 0x01 ++ ++/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ ++ ++#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ ++#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ ++#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ ++#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ ++ ++#define OPAD_PREFIX 0x1 ++#define OPAD_POSTFIX 0x2 ++#define OPAD_SYMBOL 0x4 ++ ++/* Entry found in `.options' section. */ ++ ++typedef struct ++{ ++ Elf32_Word hwp_flags1; /* Extra flags. */ ++ Elf32_Word hwp_flags2; /* Extra flags. */ ++} Elf_Options_Hw; ++ ++/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ ++ ++#define OHWA0_R4KEOP_CHECKED 0x00000001 ++#define OHWA1_R4KEOP_CLEAN 0x00000002 ++ ++/* MIPS relocs. */ ++ ++#define R_MIPS_NONE 0 /* No reloc */ ++#define R_MIPS_16 1 /* Direct 16 bit */ ++#define R_MIPS_32 2 /* Direct 32 bit */ ++#define R_MIPS_REL32 3 /* PC relative 32 bit */ ++#define R_MIPS_26 4 /* Direct 26 bit shifted */ ++#define R_MIPS_HI16 5 /* High 16 bit */ ++#define R_MIPS_LO16 6 /* Low 16 bit */ ++#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ ++#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ ++#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ ++#define R_MIPS_PC16 10 /* PC relative 16 bit */ ++#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ ++#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ ++ ++#define R_MIPS_SHIFT5 16 ++#define R_MIPS_SHIFT6 17 ++#define R_MIPS_64 18 ++#define R_MIPS_GOT_DISP 19 ++#define R_MIPS_GOT_PAGE 20 ++#define R_MIPS_GOT_OFST 21 ++#define R_MIPS_GOT_HI16 22 ++#define R_MIPS_GOT_LO16 23 ++#define R_MIPS_SUB 24 ++#define R_MIPS_INSERT_A 25 ++#define R_MIPS_INSERT_B 26 ++#define R_MIPS_DELETE 27 ++#define R_MIPS_HIGHER 28 ++#define R_MIPS_HIGHEST 29 ++#define R_MIPS_CALL_HI16 30 ++#define R_MIPS_CALL_LO16 31 ++#define R_MIPS_SCN_DISP 32 ++#define R_MIPS_REL16 33 ++#define R_MIPS_ADD_IMMEDIATE 34 ++#define R_MIPS_PJUMP 35 ++#define R_MIPS_RELGOT 36 ++#define R_MIPS_JALR 37 ++/* Keep this the last entry. */ ++#define R_MIPS_NUM 38 ++ ++/* Legal values for p_type field of Elf32_Phdr. */ ++ ++#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ ++#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ ++#define PT_MIPS_OPTIONS 0x70000002 ++ ++/* Special program header types. */ ++ ++#define PF_MIPS_LOCAL 0x10000000 ++ ++/* Legal values for d_tag field of Elf32_Dyn. */ ++ ++#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ ++#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ ++#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ ++#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ ++#define DT_MIPS_FLAGS 0x70000005 /* Flags */ ++#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ ++#define DT_MIPS_MSYM 0x70000007 ++#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ ++#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ ++#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ ++#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ ++#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ ++#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ ++#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ ++#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ ++#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ ++#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ ++#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ ++#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in ++ DT_MIPS_DELTA_CLASS. */ ++#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ ++#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in ++ DT_MIPS_DELTA_INSTANCE. */ ++#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ ++#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in ++ DT_MIPS_DELTA_RELOC. */ ++#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta ++ relocations refer to. */ ++#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in ++ DT_MIPS_DELTA_SYM. */ ++#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the ++ class declaration. */ ++#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in ++ DT_MIPS_DELTA_CLASSSYM. */ ++#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ ++#define DT_MIPS_PIXIE_INIT 0x70000023 ++#define DT_MIPS_SYMBOL_LIB 0x70000024 ++#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 ++#define DT_MIPS_LOCAL_GOTIDX 0x70000026 ++#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 ++#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 ++#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ ++#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ ++#define DT_MIPS_DYNSTR_ALIGN 0x7000002b ++#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ ++#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve ++ function stored in GOT. */ ++#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added ++ by rld on dlopen() calls. */ ++#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ ++#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ ++#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ ++#define DT_MIPS_NUM 0x32 ++ ++/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ ++ ++#define RHF_NONE 0 /* No flags */ ++#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ ++#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ ++#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ ++#define RHF_NO_MOVE (1 << 3) ++#define RHF_SGI_ONLY (1 << 4) ++#define RHF_GUARANTEE_INIT (1 << 5) ++#define RHF_DELTA_C_PLUS_PLUS (1 << 6) ++#define RHF_GUARANTEE_START_INIT (1 << 7) ++#define RHF_PIXIE (1 << 8) ++#define RHF_DEFAULT_DELAY_LOAD (1 << 9) ++#define RHF_REQUICKSTART (1 << 10) ++#define RHF_REQUICKSTARTED (1 << 11) ++#define RHF_CORD (1 << 12) ++#define RHF_NO_UNRES_UNDEF (1 << 13) ++#define RHF_RLD_ORDER_SAFE (1 << 14) ++ ++/* Entries found in sections of type SHT_MIPS_LIBLIST. */ ++ ++typedef struct ++{ ++ Elf32_Word l_name; /* Name (string table index) */ ++ Elf32_Word l_time_stamp; /* Timestamp */ ++ Elf32_Word l_checksum; /* Checksum */ ++ Elf32_Word l_version; /* Interface version */ ++ Elf32_Word l_flags; /* Flags */ ++} Elf32_Lib; ++ ++typedef struct ++{ ++ Elf64_Word l_name; /* Name (string table index) */ ++ Elf64_Word l_time_stamp; /* Timestamp */ ++ Elf64_Word l_checksum; /* Checksum */ ++ Elf64_Word l_version; /* Interface version */ ++ Elf64_Word l_flags; /* Flags */ ++} Elf64_Lib; ++ ++ ++/* Legal values for l_flags. */ ++ ++#define LL_NONE 0 ++#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ ++#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ ++#define LL_REQUIRE_MINOR (1 << 2) ++#define LL_EXPORTS (1 << 3) ++#define LL_DELAY_LOAD (1 << 4) ++#define LL_DELTA (1 << 5) ++ ++/* Entries found in sections of type SHT_MIPS_CONFLICT. */ ++ ++typedef Elf32_Addr Elf32_Conflict; ++ ++ ++/* HPPA specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ ++#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ ++#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ ++#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ ++#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch ++ prediction. */ ++#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ ++#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ ++ ++/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ ++ ++#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ ++#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ ++#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ ++ ++/* Additional section indeces. */ ++ ++#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared ++ symbols in ANSI C. */ ++#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ ++#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ ++#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ ++#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ ++#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ ++ ++#define STT_HP_OPAQUE (STT_LOOS + 0x1) ++#define STT_HP_STUB (STT_LOOS + 0x2) ++ ++/* HPPA relocs. */ ++ ++#define R_PARISC_NONE 0 /* No reloc. */ ++#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ ++#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ ++#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ ++#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ ++#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ ++#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ ++#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ ++#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ ++#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ ++#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ ++#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ ++#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ ++#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ ++#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ ++#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ ++#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ ++#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ ++#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ ++#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ ++#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ ++#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ ++#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ ++#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ ++#define R_PARISC_FPTR64 64 /* 64 bits function address. */ ++#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ ++#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ ++#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ ++#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ ++#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ ++#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ ++#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ ++#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ ++#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ ++#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ ++#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ ++#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ ++#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ ++#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ ++#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ ++#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LORESERVE 128 ++#define R_PARISC_COPY 128 /* Copy relocation. */ ++#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ ++#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ ++#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ ++#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ ++#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ ++#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ ++#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ ++#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ ++#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_HIRESERVE 255 ++ ++/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PT_HP_TLS (PT_LOOS + 0x0) ++#define PT_HP_CORE_NONE (PT_LOOS + 0x1) ++#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) ++#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) ++#define PT_HP_CORE_COMM (PT_LOOS + 0x4) ++#define PT_HP_CORE_PROC (PT_LOOS + 0x5) ++#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) ++#define PT_HP_CORE_STACK (PT_LOOS + 0x7) ++#define PT_HP_CORE_SHM (PT_LOOS + 0x8) ++#define PT_HP_CORE_MMF (PT_LOOS + 0x9) ++#define PT_HP_PARALLEL (PT_LOOS + 0x10) ++#define PT_HP_FASTBIND (PT_LOOS + 0x11) ++#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) ++#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) ++#define PT_HP_STACK (PT_LOOS + 0x14) ++ ++#define PT_PARISC_ARCHEXT 0x70000000 ++#define PT_PARISC_UNWIND 0x70000001 ++ ++/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PF_PARISC_SBP 0x08000000 ++ ++#define PF_HP_PAGE_SIZE 0x00100000 ++#define PF_HP_FAR_SHARED 0x00200000 ++#define PF_HP_NEAR_SHARED 0x00400000 ++#define PF_HP_CODE 0x01000000 ++#define PF_HP_MODIFY 0x02000000 ++#define PF_HP_LAZYSWAP 0x04000000 ++#define PF_HP_SBP 0x08000000 ++ ++ ++/* Alpha specific definitions. */ ++ ++/* Legal values for e_flags field of Elf64_Ehdr. */ ++ ++#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ ++#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ ++ ++/* Legal values for sh_type field of Elf64_Shdr. */ ++ ++/* These two are primerily concerned with ECOFF debugging info. */ ++#define SHT_ALPHA_DEBUG 0x70000001 ++#define SHT_ALPHA_REGINFO 0x70000002 ++ ++/* Legal values for sh_flags field of Elf64_Shdr. */ ++ ++#define SHF_ALPHA_GPREL 0x10000000 ++ ++/* Legal values for st_other field of Elf64_Sym. */ ++#define STO_ALPHA_NOPV 0x80 /* No PV required. */ ++#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ ++ ++/* Alpha relocs. */ ++ ++#define R_ALPHA_NONE 0 /* No reloc */ ++#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ ++#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ ++#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ ++#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ ++#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ ++#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ ++#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ ++#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ ++#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ ++#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ ++#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ ++#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ ++#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ ++#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ ++#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ ++#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ ++#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ ++#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ ++#define R_ALPHA_TLS_GD_HI 28 ++#define R_ALPHA_TLSGD 29 ++#define R_ALPHA_TLS_LDM 30 ++#define R_ALPHA_DTPMOD64 31 ++#define R_ALPHA_GOTDTPREL 32 ++#define R_ALPHA_DTPREL64 33 ++#define R_ALPHA_DTPRELHI 34 ++#define R_ALPHA_DTPRELLO 35 ++#define R_ALPHA_DTPREL16 36 ++#define R_ALPHA_GOTTPREL 37 ++#define R_ALPHA_TPREL64 38 ++#define R_ALPHA_TPRELHI 39 ++#define R_ALPHA_TPRELLO 40 ++#define R_ALPHA_TPREL16 41 ++/* Keep this the last entry. */ ++#define R_ALPHA_NUM 46 ++ ++/* Magic values of the LITUSE relocation addend. */ ++#define LITUSE_ALPHA_ADDR 0 ++#define LITUSE_ALPHA_BASE 1 ++#define LITUSE_ALPHA_BYTOFF 2 ++#define LITUSE_ALPHA_JSR 3 ++#define LITUSE_ALPHA_TLS_GD 4 ++#define LITUSE_ALPHA_TLS_LDM 5 ++ ++ ++/* PowerPC specific declarations */ ++ ++/* Values for Elf32/64_Ehdr.e_flags. */ ++#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ ++ ++/* Cygnus local bits below */ ++#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ ++#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib ++ flag */ ++ ++/* PowerPC relocations defined by the ABIs */ ++#define R_PPC_NONE 0 ++#define R_PPC_ADDR32 1 /* 32bit absolute address */ ++#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ ++#define R_PPC_ADDR16 3 /* 16bit absolute address */ ++#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ ++#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ ++#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ ++#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ ++#define R_PPC_ADDR14_BRTAKEN 8 ++#define R_PPC_ADDR14_BRNTAKEN 9 ++#define R_PPC_REL24 10 /* PC relative 26 bit */ ++#define R_PPC_REL14 11 /* PC relative 16 bit */ ++#define R_PPC_REL14_BRTAKEN 12 ++#define R_PPC_REL14_BRNTAKEN 13 ++#define R_PPC_GOT16 14 ++#define R_PPC_GOT16_LO 15 ++#define R_PPC_GOT16_HI 16 ++#define R_PPC_GOT16_HA 17 ++#define R_PPC_PLTREL24 18 ++#define R_PPC_COPY 19 ++#define R_PPC_GLOB_DAT 20 ++#define R_PPC_JMP_SLOT 21 ++#define R_PPC_RELATIVE 22 ++#define R_PPC_LOCAL24PC 23 ++#define R_PPC_UADDR32 24 ++#define R_PPC_UADDR16 25 ++#define R_PPC_REL32 26 ++#define R_PPC_PLT32 27 ++#define R_PPC_PLTREL32 28 ++#define R_PPC_PLT16_LO 29 ++#define R_PPC_PLT16_HI 30 ++#define R_PPC_PLT16_HA 31 ++#define R_PPC_SDAREL16 32 ++#define R_PPC_SECTOFF 33 ++#define R_PPC_SECTOFF_LO 34 ++#define R_PPC_SECTOFF_HI 35 ++#define R_PPC_SECTOFF_HA 36 ++ ++/* PowerPC relocations defined for the TLS access ABI. */ ++#define R_PPC_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ ++#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ ++#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ ++#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ ++#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ ++#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ ++#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ ++#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ ++#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ ++ ++/* Keep this the last entry. */ ++#define R_PPC_NUM 95 ++ ++/* The remaining relocs are from the Embedded ELF ABI, and are not ++ in the SVR4 ELF ABI. */ ++#define R_PPC_EMB_NADDR32 101 ++#define R_PPC_EMB_NADDR16 102 ++#define R_PPC_EMB_NADDR16_LO 103 ++#define R_PPC_EMB_NADDR16_HI 104 ++#define R_PPC_EMB_NADDR16_HA 105 ++#define R_PPC_EMB_SDAI16 106 ++#define R_PPC_EMB_SDA2I16 107 ++#define R_PPC_EMB_SDA2REL 108 ++#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ ++#define R_PPC_EMB_MRKREF 110 ++#define R_PPC_EMB_RELSEC16 111 ++#define R_PPC_EMB_RELST_LO 112 ++#define R_PPC_EMB_RELST_HI 113 ++#define R_PPC_EMB_RELST_HA 114 ++#define R_PPC_EMB_BIT_FLD 115 ++#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ ++ ++/* Diab tool relocations. */ ++#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ ++#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ ++#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ ++#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ ++#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ ++#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ ++ ++/* This is a phony reloc to handle any old fashioned TOC16 references ++ that may still be in object files. */ ++#define R_PPC_TOC16 255 ++ ++ ++/* PowerPC64 relocations defined by the ABIs */ ++#define R_PPC64_NONE R_PPC_NONE ++#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ ++#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ ++#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ ++#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ ++#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ ++#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ ++#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ ++#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN ++#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN ++#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ ++#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ ++#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN ++#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN ++#define R_PPC64_GOT16 R_PPC_GOT16 ++#define R_PPC64_GOT16_LO R_PPC_GOT16_LO ++#define R_PPC64_GOT16_HI R_PPC_GOT16_HI ++#define R_PPC64_GOT16_HA R_PPC_GOT16_HA ++ ++#define R_PPC64_COPY R_PPC_COPY ++#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT ++#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT ++#define R_PPC64_RELATIVE R_PPC_RELATIVE ++ ++#define R_PPC64_UADDR32 R_PPC_UADDR32 ++#define R_PPC64_UADDR16 R_PPC_UADDR16 ++#define R_PPC64_REL32 R_PPC_REL32 ++#define R_PPC64_PLT32 R_PPC_PLT32 ++#define R_PPC64_PLTREL32 R_PPC_PLTREL32 ++#define R_PPC64_PLT16_LO R_PPC_PLT16_LO ++#define R_PPC64_PLT16_HI R_PPC_PLT16_HI ++#define R_PPC64_PLT16_HA R_PPC_PLT16_HA ++ ++#define R_PPC64_SECTOFF R_PPC_SECTOFF ++#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO ++#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI ++#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA ++#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ ++#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ ++#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ ++#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ ++#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ ++#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ ++#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ ++#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ ++#define R_PPC64_PLT64 45 /* doubleword64 L + A */ ++#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ ++#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ ++#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ ++#define R_PPC64_TOC 51 /* doubleword64 .TOC */ ++#define R_PPC64_PLTGOT16 52 /* half16* M + A */ ++#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ ++#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ ++#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ ++ ++#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ ++#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ ++#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ ++#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ ++#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ ++#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ ++#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ ++#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ ++#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ ++#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ ++#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ ++ ++/* PowerPC64 relocations defined for the TLS access ABI. */ ++#define R_PPC64_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ ++#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ ++#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ ++#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ ++#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ ++#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ ++#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ ++#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ ++#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ ++#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ ++#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ ++#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ ++#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ ++#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ ++#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ ++#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ ++#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ ++ ++/* Keep this the last entry. */ ++#define R_PPC64_NUM 107 ++ ++/* PowerPC64 specific values for the Dyn d_tag field. */ ++#define DT_PPC64_GLINK (DT_LOPROC + 0) ++#define DT_PPC64_NUM 1 ++ ++ ++/* ARM specific declarations */ ++ ++/* Processor specific flags for the ELF header e_flags field. */ ++#define EF_ARM_RELEXEC 0x01 ++#define EF_ARM_HASENTRY 0x02 ++#define EF_ARM_INTERWORK 0x04 ++#define EF_ARM_APCS_26 0x08 ++#define EF_ARM_APCS_FLOAT 0x10 ++#define EF_ARM_PIC 0x20 ++#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ ++#define EF_ARM_NEW_ABI 0x80 ++#define EF_ARM_OLD_ABI 0x100 ++ ++/* Other constants defined in the ARM ELF spec. version B-01. */ ++/* NB. These conflict with values defined above. */ ++#define EF_ARM_SYMSARESORTED 0x04 ++#define EF_ARM_DYNSYMSUSESEGIDX 0x08 ++#define EF_ARM_MAPSYMSFIRST 0x10 ++#define EF_ARM_EABIMASK 0XFF000000 ++ ++#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) ++#define EF_ARM_EABI_UNKNOWN 0x00000000 ++#define EF_ARM_EABI_VER1 0x01000000 ++#define EF_ARM_EABI_VER2 0x02000000 ++ ++/* Additional symbol types for Thumb */ ++#define STT_ARM_TFUNC 0xd ++ ++/* ARM-specific values for sh_flags */ ++#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ ++#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined ++ in the input to a link step */ ++ ++/* ARM-specific program header flags */ ++#define PF_ARM_SB 0x10000000 /* Segment contains the location ++ addressed by the static base */ ++ ++/* ARM relocs. */ ++#define R_ARM_NONE 0 /* No reloc */ ++#define R_ARM_PC24 1 /* PC relative 26 bit branch */ ++#define R_ARM_ABS32 2 /* Direct 32 bit */ ++#define R_ARM_REL32 3 /* PC relative 32 bit */ ++#define R_ARM_PC13 4 ++#define R_ARM_ABS16 5 /* Direct 16 bit */ ++#define R_ARM_ABS12 6 /* Direct 12 bit */ ++#define R_ARM_THM_ABS5 7 ++#define R_ARM_ABS8 8 /* Direct 8 bit */ ++#define R_ARM_SBREL32 9 ++#define R_ARM_THM_PC22 10 ++#define R_ARM_THM_PC8 11 ++#define R_ARM_AMP_VCALL9 12 ++#define R_ARM_SWI24 13 ++#define R_ARM_THM_SWI8 14 ++#define R_ARM_XPC25 15 ++#define R_ARM_THM_XPC22 16 ++#define R_ARM_COPY 20 /* Copy symbol at runtime */ ++#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ ++#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ ++#define R_ARM_RELATIVE 23 /* Adjust by program base */ ++#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ ++#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ ++#define R_ARM_GOT32 26 /* 32 bit GOT entry */ ++#define R_ARM_PLT32 27 /* 32 bit PLT address */ ++#define R_ARM_ALU_PCREL_7_0 32 ++#define R_ARM_ALU_PCREL_15_8 33 ++#define R_ARM_ALU_PCREL_23_15 34 ++#define R_ARM_LDR_SBREL_11_0 35 ++#define R_ARM_ALU_SBREL_19_12 36 ++#define R_ARM_ALU_SBREL_27_20 37 ++#define R_ARM_GNU_VTENTRY 100 ++#define R_ARM_GNU_VTINHERIT 101 ++#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ ++#define R_ARM_THM_PC9 103 /* thumb conditional branch */ ++#define R_ARM_RXPC25 249 ++#define R_ARM_RSBREL32 250 ++#define R_ARM_THM_RPC22 251 ++#define R_ARM_RREL32 252 ++#define R_ARM_RABS22 253 ++#define R_ARM_RPC24 254 ++#define R_ARM_RBASE 255 ++/* Keep this the last entry. */ ++#define R_ARM_NUM 256 ++ ++/* IA-64 specific declarations. */ ++ ++/* Processor specific flags for the Ehdr e_flags field. */ ++#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ ++#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ ++#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ ++ ++/* Processor specific values for the Phdr p_type field. */ ++#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ ++#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ ++ ++/* Processor specific flags for the Phdr p_flags field. */ ++#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Shdr sh_type field. */ ++#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ ++#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ ++ ++/* Processor specific flags for the Shdr sh_flags field. */ ++#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ ++#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Dyn d_tag field. */ ++#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) ++#define DT_IA_64_NUM 1 ++ ++/* IA-64 relocations. */ ++#define R_IA64_NONE 0x00 /* none */ ++#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ ++#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ ++#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ ++#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ ++#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ ++#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ ++#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ ++#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ ++#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ ++#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ ++#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ ++#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ ++#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ ++#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ ++#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ ++#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ ++#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ ++#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ ++#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ ++#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ ++#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ ++#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ ++#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ ++#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ ++#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ ++#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ ++#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ ++#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ ++#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ ++#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ ++#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ ++#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ ++#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ ++#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ ++#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ ++#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ ++#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ ++#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ ++#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ ++#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ ++#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ ++#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ ++#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ ++#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ ++#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ ++#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ ++#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ ++#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ ++#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ ++#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ ++#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ ++#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ ++#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ ++#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ ++#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ ++#define R_IA64_COPY 0x84 /* copy relocation */ ++#define R_IA64_SUB 0x85 /* Addend and symbol difference */ ++#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ ++#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ ++#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ ++#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ ++#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ ++#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ ++#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ ++#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ ++#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ ++#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ ++#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ ++#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ ++#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ ++#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ ++#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ ++#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ ++ ++/* SH specific declarations */ ++ ++/* SH relocs. */ ++#define R_SH_NONE 0 ++#define R_SH_DIR32 1 ++#define R_SH_REL32 2 ++#define R_SH_DIR8WPN 3 ++#define R_SH_IND12W 4 ++#define R_SH_DIR8WPL 5 ++#define R_SH_DIR8WPZ 6 ++#define R_SH_DIR8BP 7 ++#define R_SH_DIR8W 8 ++#define R_SH_DIR8L 9 ++#define R_SH_SWITCH16 25 ++#define R_SH_SWITCH32 26 ++#define R_SH_USES 27 ++#define R_SH_COUNT 28 ++#define R_SH_ALIGN 29 ++#define R_SH_CODE 30 ++#define R_SH_DATA 31 ++#define R_SH_LABEL 32 ++#define R_SH_SWITCH8 33 ++#define R_SH_GNU_VTINHERIT 34 ++#define R_SH_GNU_VTENTRY 35 ++#define R_SH_TLS_GD_32 144 ++#define R_SH_TLS_LD_32 145 ++#define R_SH_TLS_LDO_32 146 ++#define R_SH_TLS_IE_32 147 ++#define R_SH_TLS_LE_32 148 ++#define R_SH_TLS_DTPMOD32 149 ++#define R_SH_TLS_DTPOFF32 150 ++#define R_SH_TLS_TPOFF32 151 ++#define R_SH_GOT32 160 ++#define R_SH_PLT32 161 ++#define R_SH_COPY 162 ++#define R_SH_GLOB_DAT 163 ++#define R_SH_JMP_SLOT 164 ++#define R_SH_RELATIVE 165 ++#define R_SH_GOTOFF 166 ++#define R_SH_GOTPC 167 ++/* Keep this the last entry. */ ++#define R_SH_NUM 256 ++ ++/* Additional s390 relocs */ ++ ++#define R_390_NONE 0 /* No reloc. */ ++#define R_390_8 1 /* Direct 8 bit. */ ++#define R_390_12 2 /* Direct 12 bit. */ ++#define R_390_16 3 /* Direct 16 bit. */ ++#define R_390_32 4 /* Direct 32 bit. */ ++#define R_390_PC32 5 /* PC relative 32 bit. */ ++#define R_390_GOT12 6 /* 12 bit GOT offset. */ ++#define R_390_GOT32 7 /* 32 bit GOT offset. */ ++#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ ++#define R_390_COPY 9 /* Copy symbol at runtime. */ ++#define R_390_GLOB_DAT 10 /* Create GOT entry. */ ++#define R_390_JMP_SLOT 11 /* Create PLT entry. */ ++#define R_390_RELATIVE 12 /* Adjust by program base. */ ++#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ ++#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ ++#define R_390_GOT16 15 /* 16 bit GOT offset. */ ++#define R_390_PC16 16 /* PC relative 16 bit. */ ++#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ ++#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ ++#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ ++#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ ++#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ ++#define R_390_64 22 /* Direct 64 bit. */ ++#define R_390_PC64 23 /* PC relative 64 bit. */ ++#define R_390_GOT64 24 /* 64 bit GOT offset. */ ++#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ ++#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ ++#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ ++#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ ++#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ ++#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ ++#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ ++#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ ++#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ ++#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ ++#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ ++#define R_390_TLS_GDCALL 38 /* Tag for function call in general ++ dynamic TLS code. */ ++#define R_390_TLS_LDCALL 39 /* Tag for function call in local ++ dynamic TLS code. */ ++#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ ++#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ ++#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS ++ block. */ ++ ++/* Keep this the last entry. */ ++#define R_390_NUM 57 ++ ++/* CRIS relocations. */ ++#define R_CRIS_NONE 0 ++#define R_CRIS_8 1 ++#define R_CRIS_16 2 ++#define R_CRIS_32 3 ++#define R_CRIS_8_PCREL 4 ++#define R_CRIS_16_PCREL 5 ++#define R_CRIS_32_PCREL 6 ++#define R_CRIS_GNU_VTINHERIT 7 ++#define R_CRIS_GNU_VTENTRY 8 ++#define R_CRIS_COPY 9 ++#define R_CRIS_GLOB_DAT 10 ++#define R_CRIS_JUMP_SLOT 11 ++#define R_CRIS_RELATIVE 12 ++#define R_CRIS_16_GOT 13 ++#define R_CRIS_32_GOT 14 ++#define R_CRIS_16_GOTPLT 15 ++#define R_CRIS_32_GOTPLT 16 ++#define R_CRIS_32_GOTREL 17 ++#define R_CRIS_32_PLT_GOTREL 18 ++#define R_CRIS_32_PLT_PCREL 19 ++ ++#define R_CRIS_NUM 20 ++ ++/* AMD x86-64 relocations. */ ++#define R_X86_64_NONE 0 /* No reloc */ ++#define R_X86_64_64 1 /* Direct 64 bit */ ++#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ ++#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ ++#define R_X86_64_PLT32 4 /* 32 bit PLT address */ ++#define R_X86_64_COPY 5 /* Copy symbol at runtime */ ++#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ ++#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ ++#define R_X86_64_RELATIVE 8 /* Adjust by program base */ ++#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative ++ offset to GOT */ ++#define R_X86_64_32 10 /* Direct 32 bit zero extended */ ++#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ ++#define R_X86_64_16 12 /* Direct 16 bit zero extended */ ++#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ ++#define R_X86_64_8 14 /* Direct 8 bit sign extended */ ++#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ ++#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ ++#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ ++#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ ++#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset ++ to two GOT entries for GD symbol */ ++#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset ++ to two GOT entries for LD symbol */ ++#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ ++#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset ++ to GOT entry for IE symbol */ ++#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ ++ ++#define R_X86_64_NUM 24 ++ ++__END_DECLS ++ ++#endif /* elf.h */ + + #include "elfconfig.h" + +@@ -195,3 +2641,4 @@ + void fatal(const char *fmt, ...); + void warn(const char *fmt, ...); + void merror(const char *fmt, ...); ++ +diff -Nur linux-2.6.36.orig/scripts/mod/sumversion.c linux-2.6.36/scripts/mod/sumversion.c +--- linux-2.6.36.orig/scripts/mod/sumversion.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/mod/sumversion.c 2010-11-28 18:33:24.000000000 +0100 +@@ -1,4 +1,4 @@ +-#include ++/* #include */ + #ifdef __sun__ + #include + #else diff --git a/target/linux/patches/3.0.8/cris-etrax.patch b/target/linux/patches/3.0.8/cris-etrax.patch new file mode 100644 index 000000000..a80d9a8b8 --- /dev/null +++ b/target/linux/patches/3.0.8/cris-etrax.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h +--- linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h 2011-08-24 19:15:05.000000000 +0200 +@@ -2,7 +2,7 @@ + #include + + /* High level I2C actions */ +-int __init i2c_init(void); ++static int __init i2c_init(void); + int i2c_write(unsigned char theSlave, void *data, size_t nbytes); + int i2c_read(unsigned char theSlave, void *data, size_t nbytes); + int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue); diff --git a/target/linux/patches/3.0.8/defaults.patch b/target/linux/patches/3.0.8/defaults.patch new file mode 100644 index 000000000..58aae610b --- /dev/null +++ b/target/linux/patches/3.0.8/defaults.patch @@ -0,0 +1,22 @@ +diff -Nur linux-3.0.4.orig/fs/Kconfig linux-3.0.4/fs/Kconfig +--- linux-3.0.4.orig/fs/Kconfig 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/fs/Kconfig 2011-10-15 22:08:44.000000000 +0200 +@@ -47,7 +47,7 @@ + def_bool n + + config EXPORTFS +- tristate ++ def_bool y + + config FILE_LOCKING + bool "Enable POSIX file locking API" if EXPERT +diff -Nur linux-3.0.4.orig/fs/notify/Kconfig linux-3.0.4/fs/notify/Kconfig +--- linux-3.0.4.orig/fs/notify/Kconfig 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/fs/notify/Kconfig 2011-10-15 22:02:00.000000000 +0200 +@@ -1,5 +1,5 @@ + config FSNOTIFY +- def_bool n ++ def_bool y + + source "fs/notify/dnotify/Kconfig" + source "fs/notify/inotify/Kconfig" diff --git a/target/linux/patches/3.0.8/fon2100.patch b/target/linux/patches/3.0.8/fon2100.patch new file mode 100644 index 000000000..038ff7020 --- /dev/null +++ b/target/linux/patches/3.0.8/fon2100.patch @@ -0,0 +1,6279 @@ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms linux-2.6.39-rc7/arch/mips/Kbuild.platforms +--- linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/mips/Kbuild.platforms 2011-05-15 21:34:57.000000000 +0200 +@@ -6,6 +6,7 @@ + platforms += bcm47xx + platforms += bcm63xx + platforms += cavium-octeon ++platforms += ar231x + platforms += cobalt + platforms += dec + platforms += emma +diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kconfig linux-2.6.39-rc7/arch/mips/Kconfig +--- linux-2.6.39-rc7.orig/arch/mips/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/mips/Kconfig 2011-05-16 12:11:11.000000000 +0200 +@@ -121,6 +121,21 @@ + help + Support for BCM63XX based boards + ++config ATHEROS_AR231X ++ bool "Atheros 231x/531x SoC support" ++ select CEVT_R4K ++ select CSRC_R4K ++ select DMA_NONCOHERENT ++ select IRQ_CPU ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select GENERIC_GPIO ++ select SYS_HAS_EARLY_PRINTK ++ select SYS_SUPPORTS_ZBOOT ++ help ++ Support for AR231x and AR531x based boards ++ + config MIPS_COBALT + bool "Cobalt Server" + select CEVT_R4K +@@ -738,6 +753,7 @@ + + endchoice + ++source "arch/mips/ar231x/Kconfig" + source "arch/mips/alchemy/Kconfig" + source "arch/mips/ath79/Kconfig" + source "arch/mips/bcm63xx/Kconfig" +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig linux-2.6.39-rc7/arch/mips/ar231x/Kconfig +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,27 @@ ++config ATHEROS_AR5312 ++ bool "Atheros 5312/2312+ support" ++ depends on ATHEROS_AR231X ++ default y ++ ++config ATHEROS_AR2315 ++ bool "Atheros 2315+ support" ++ depends on ATHEROS_AR231X ++ select DMA_NONCOHERENT ++ select CEVT_R4K ++ select CSRC_R4K ++ select IRQ_CPU ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select GENERIC_GPIO ++ default y ++ ++config ATHEROS_AR2315_PCI ++ bool "PCI support" ++ depends on ATHEROS_AR2315 ++ select HW_HAS_PCI ++ select PCI ++ select USB_ARCH_HAS_HCD ++ select USB_ARCH_HAS_OHCI ++ select USB_ARCH_HAS_EHCI ++ default n +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile linux-2.6.39-rc7/arch/mips/ar231x/Makefile +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,17 @@ ++# ++# This file is subject to the terms and conditions of the GNU General Public ++# License. See the file "COPYING" in the main directory of this archive ++# for more details. ++# ++# Copyright (C) 2006 FON Technology, SL. ++# Copyright (C) 2006 Imre Kaloz ++# Copyright (C) 2006-2009 Felix Fietkau ++# ++ ++obj-y += board.o prom.o devices.o ++ ++obj-$(CONFIG_EARLY_PRINTK) += early_printk.o ++ ++obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o ++obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o ++obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform linux-2.6.39-rc7/arch/mips/ar231x/Platform +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/Platform 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,6 @@ ++# ++# Atheros AR5312/AR2312 WiSoC ++# ++platform-$(CONFIG_ATHEROS_AR231X) += ar231x/ ++cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x ++load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000 +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c 2011-05-15 21:47:07.000000000 +0200 +@@ -0,0 +1,654 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++/* ++ * Platform devices for Atheros SoCs ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "devices.h" ++#include "ar2315.h" ++ ++static u32 gpiointmask = 0, gpiointval = 0; ++ ++static inline void ar2315_gpio_irq(void) ++{ ++ u32 pend; ++ int bit = -1; ++ ++ /* only do one gpio interrupt at a time */ ++ pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask; ++ ++ if (pend) { ++ bit = fls(pend) - 1; ++ pend &= ~(1 << bit); ++ gpiointval ^= (1 << bit); ++ } ++ ++ if (!pend) ++ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO); ++ ++ /* Enable interrupt with edge detection */ ++ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit)) ++ return; ++ ++ if (bit >= 0) ++ do_IRQ(AR531X_GPIO_IRQ_BASE + bit); ++} ++ ++#ifdef CONFIG_ATHEROS_AR2315_PCI ++static inline void pci_abort_irq(void) ++{ ++ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT); ++} ++ ++static inline void pci_ack_irq(void) ++{ ++ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT); ++} ++ ++void ar2315_pci_irq(int irq) ++{ ++ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT) ++ pci_abort_irq(); ++ else { ++ do_IRQ(irq); ++ pci_ack_irq(); ++ } ++} ++#endif /* CONFIG_ATHEROS_AR2315_PCI */ ++ ++/* ++ * Called when an interrupt is received, this function ++ * determines exactly which interrupt it was, and it ++ * invokes the appropriate handler. ++ * ++ * Implicitly, we also define interrupt priority by ++ * choosing which to dispatch first. ++ */ ++static asmlinkage void ++ar2315_irq_dispatch(void) ++{ ++ int pending = read_c0_status() & read_c0_cause(); ++ ++ if (pending & CAUSEF_IP3) ++ do_IRQ(AR2315_IRQ_WLAN0_INTRS); ++ else if (pending & CAUSEF_IP4) ++ do_IRQ(AR2315_IRQ_ENET0_INTRS); ++#ifdef CONFIG_ATHEROS_AR2315_PCI ++ else if (pending & CAUSEF_IP5) ++ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI); ++#endif ++ else if (pending & CAUSEF_IP2) { ++ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR); ++ ++ if (misc_intr & AR2315_ISR_SPI) ++ do_IRQ(AR531X_MISC_IRQ_SPI); ++ else if (misc_intr & AR2315_ISR_TIMER) ++ do_IRQ(AR531X_MISC_IRQ_TIMER); ++ else if (misc_intr & AR2315_ISR_AHB) ++ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); ++ else if (misc_intr & AR2315_ISR_GPIO) ++ ar2315_gpio_irq(); ++ else if (misc_intr & AR2315_ISR_UART0) ++ do_IRQ(AR531X_MISC_IRQ_UART0); ++ else if (misc_intr & AR2315_ISR_WD) ++ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); ++ else ++ do_IRQ(AR531X_MISC_IRQ_NONE); ++ } else if (pending & CAUSEF_IP7) ++ do_IRQ(AR531X_IRQ_CPU_CLOCK); ++} ++ ++static void ar2315_set_gpiointmask(int gpio, int level) ++{ ++ u32 reg; ++ ++ reg = ar231x_read_reg(AR2315_GPIO_INT); ++ reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M); ++ reg |= gpio | AR2315_GPIO_INT_LVL(level); ++ ar231x_write_reg(AR2315_GPIO_INT, reg); ++} ++ ++static void ar2315_gpio_intr_enable(struct irq_data *d) ++{ ++ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; ++ ++ /* Enable interrupt with edge detection */ ++ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio)) ++ return; ++ ++ gpiointmask |= (1 << gpio); ++ ar2315_set_gpiointmask(gpio, 3); ++} ++ ++static void ar2315_gpio_intr_disable(struct irq_data *d) ++{ ++ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; ++ ++ /* Disable interrupt */ ++ gpiointmask &= ~(1 << gpio); ++ ar2315_set_gpiointmask(gpio, 0); ++} ++ ++static struct irq_chip ar2315_gpio_intr_controller = { ++ .name = "AR2315-GPIO", ++ .irq_ack = ar2315_gpio_intr_disable, ++ .irq_mask_ack = ar2315_gpio_intr_disable, ++ .irq_mask = ar2315_gpio_intr_disable, ++ .irq_unmask = ar2315_gpio_intr_enable, ++}; ++ ++static void ++ar2315_misc_intr_enable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR2315_IMR); ++ switch(d->irq) { ++ case AR531X_MISC_IRQ_SPI: ++ imr |= AR2315_ISR_SPI; ++ break; ++ case AR531X_MISC_IRQ_TIMER: ++ imr |= AR2315_ISR_TIMER; ++ break; ++ case AR531X_MISC_IRQ_AHB_PROC: ++ imr |= AR2315_ISR_AHB; ++ break; ++ case AR531X_MISC_IRQ_GPIO: ++ imr |= AR2315_ISR_GPIO; ++ break; ++ case AR531X_MISC_IRQ_UART0: ++ imr |= AR2315_ISR_UART0; ++ break; ++ case AR531X_MISC_IRQ_WATCHDOG: ++ imr |= AR2315_ISR_WD; ++ break; ++ default: ++ break; ++ } ++ ar231x_write_reg(AR2315_IMR, imr); ++} ++ ++static void ++ar2315_misc_intr_disable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR2315_IMR); ++ switch(d->irq) { ++ case AR531X_MISC_IRQ_SPI: ++ imr &= ~AR2315_ISR_SPI; ++ break; ++ case AR531X_MISC_IRQ_TIMER: ++ imr &= ~AR2315_ISR_TIMER; ++ break; ++ case AR531X_MISC_IRQ_AHB_PROC: ++ imr &= ~AR2315_ISR_AHB; ++ break; ++ case AR531X_MISC_IRQ_GPIO: ++ imr &= ~AR2315_ISR_GPIO; ++ break; ++ case AR531X_MISC_IRQ_UART0: ++ imr &= ~AR2315_ISR_UART0; ++ break; ++ case AR531X_MISC_IRQ_WATCHDOG: ++ imr &= ~AR2315_ISR_WD; ++ break; ++ default: ++ break; ++ } ++ ar231x_write_reg(AR2315_IMR, imr); ++} ++ ++ ++static struct irq_chip ar2315_misc_intr_controller = { ++ .name = "AR2315-MISC", ++ .irq_mask = ar2315_misc_intr_disable, ++ .irq_unmask = ar2315_misc_intr_enable, ++}; ++ ++static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id) ++{ ++ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET); ++ ar231x_read_reg(AR2315_AHB_ERR1); ++ ++ printk(KERN_ERR "AHB fatal error\n"); ++ machine_restart("AHB error"); /* Catastrophic failure */ ++ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction ar2315_ahb_proc_interrupt = { ++ .handler = ar2315_ahb_proc_handler, ++ .flags = IRQF_DISABLED, ++ .name = "ar2315_ahb_proc_interrupt", ++}; ++ ++static struct irqaction cascade = { ++ .handler = no_action, ++ .flags = IRQF_DISABLED, ++ .name = "cascade", ++}; ++ ++void ++ar2315_irq_init(void) ++{ ++ int i; ++ ++ if (!is_2315()) ++ return; ++ ++ ar231x_irq_dispatch = ar2315_irq_dispatch; ++ gpiointval = ar231x_read_reg(AR2315_GPIO_DI); ++ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { ++ int irq = AR531X_MISC_IRQ_BASE + i; ++ irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller, ++ handle_level_irq); ++ } ++ for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) { ++ int irq = AR531X_GPIO_IRQ_BASE + i; ++ irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller, ++ handle_level_irq); ++ } ++ setup_irq(AR531X_MISC_IRQ_GPIO, &cascade); ++ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt); ++ setup_irq(AR2315_IRQ_MISC_INTRS, &cascade); ++} ++ ++const struct ar231x_gpiodev ar2315_gpiodev; ++ ++static u32 ++ar2315_gpio_get_output(void) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR2315_GPIO_CR); ++ reg &= ar2315_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar2315_gpio_set_output(u32 mask, u32 val) ++{ ++ u32 reg; ++ ++ reg = ar231x_read_reg(AR2315_GPIO_CR); ++ reg &= ~mask; ++ reg |= val; ++ ar231x_write_reg(AR2315_GPIO_CR, reg); ++ return reg; ++} ++ ++static u32 ++ar2315_gpio_get(void) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR2315_GPIO_DI); ++ reg &= ar2315_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar2315_gpio_set(u32 mask, u32 value) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR2315_GPIO_DO); ++ reg &= ~mask; ++ reg |= value; ++ ar231x_write_reg(AR2315_GPIO_DO, reg); ++ return reg; ++} ++ ++const struct ar231x_gpiodev ar2315_gpiodev = { ++ .valid_mask = (1 << 22) - 1, ++ .get_output = ar2315_gpio_get_output, ++ .set_output = ar2315_gpio_set_output, ++ .get = ar2315_gpio_get, ++ .set = ar2315_gpio_set, ++}; ++ ++static struct ar231x_eth ar2315_eth_data = { ++ .reset_base = AR2315_RESET, ++ .reset_mac = AR2315_RESET_ENET0, ++ .reset_phy = AR2315_RESET_EPHY0, ++ .phy_base = KSEG1ADDR(AR2315_ENET0), ++ .config = &ar231x_board, ++}; ++ ++static struct resource ar2315_spiflash_res[] = { ++ { ++ .name = "flash_base", ++ .flags = IORESOURCE_MEM, ++ .start = KSEG1ADDR(AR2315_SPI_READ), ++ .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1, ++ }, ++ { ++ .name = "flash_regs", ++ .flags = IORESOURCE_MEM, ++ .start = 0x11300000, ++ .end = 0x11300012, ++ }, ++}; ++ ++static struct platform_device ar2315_spiflash = { ++ .id = 0, ++ .name = "spiflash", ++ .resource = ar2315_spiflash_res, ++ .num_resources = ARRAY_SIZE(ar2315_spiflash_res) ++}; ++ ++static struct platform_device ar2315_wdt = { ++ .id = 0, ++ .name = "ar2315_wdt", ++}; ++ ++#define SPI_FLASH_CTL 0x00 ++#define SPI_FLASH_OPCODE 0x04 ++#define SPI_FLASH_DATA 0x08 ++ ++static inline u32 ++spiflash_read_reg(int reg) ++{ ++ return ar231x_read_reg(AR2315_SPI + reg); ++} ++ ++static inline void ++spiflash_write_reg(int reg, u32 data) ++{ ++ ar231x_write_reg(AR2315_SPI + reg, data); ++} ++ ++static u32 ++spiflash_wait_status(void) ++{ ++ u32 reg; ++ ++ do { ++ reg = spiflash_read_reg(SPI_FLASH_CTL); ++ } while (reg & SPI_CTL_BUSY); ++ ++ return reg; ++} ++ ++static u8 ++spiflash_probe(void) ++{ ++ u32 reg; ++ ++ reg = spiflash_wait_status(); ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= (1 << 4) | 4 | SPI_CTL_START; ++ ++ spiflash_write_reg(SPI_FLASH_OPCODE, 0xab); ++ spiflash_write_reg(SPI_FLASH_CTL, reg); ++ ++ reg = spiflash_wait_status(); ++ reg = spiflash_read_reg(SPI_FLASH_DATA); ++ reg &= 0xff; ++ ++ return (u8) reg; ++} ++ ++ ++#define STM_8MBIT_SIGNATURE 0x13 ++#define STM_16MBIT_SIGNATURE 0x14 ++#define STM_32MBIT_SIGNATURE 0x15 ++#define STM_64MBIT_SIGNATURE 0x16 ++#define STM_128MBIT_SIGNATURE 0x17 ++ ++static u8 __init * ++ar2315_flash_limit(void) ++{ ++ u32 flash_size = 0; ++ ++ /* probe the flash chip size */ ++ switch(spiflash_probe()) { ++ case STM_8MBIT_SIGNATURE: ++ flash_size = 0x00100000; ++ break; ++ case STM_16MBIT_SIGNATURE: ++ flash_size = 0x00200000; ++ break; ++ case STM_32MBIT_SIGNATURE: ++ flash_size = 0x00400000; ++ break; ++ case STM_64MBIT_SIGNATURE: ++ flash_size = 0x00800000; ++ break; ++ case STM_128MBIT_SIGNATURE: ++ flash_size = 0x01000000; ++ break; ++ } ++ ++ ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start + ++ flash_size - 1; ++ return (u8 *) ar2315_spiflash_res[0].end + 1; ++} ++ ++#ifdef CONFIG_LEDS_GPIO ++static struct gpio_led ar2315_leds[6]; ++static struct gpio_led_platform_data ar2315_led_data = { ++ .leds = (void *) ar2315_leds, ++}; ++ ++static struct platform_device ar2315_gpio_leds = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev = { ++ .platform_data = (void *) &ar2315_led_data, ++ } ++}; ++ ++static void __init ++ar2315_init_gpio(void) ++{ ++ static char led_names[6][6]; ++ int i, led = 0; ++ ++ ar2315_led_data.num_leds = 0; ++ for(i = 1; i < 8; i++) ++ { ++ if((i == AR2315_RESET_GPIO) || ++ (i == ar231x_board.config->resetConfigGpio)) ++ continue; ++ ++ if(i == ar231x_board.config->sysLedGpio) ++ strcpy(led_names[led], "wlan"); ++ else ++ sprintf(led_names[led], "gpio%d", i); ++ ++ ar2315_leds[led].name = led_names[led]; ++ ar2315_leds[led].gpio = i; ++ ar2315_leds[led].active_low = 0; ++ led++; ++ } ++ ar2315_led_data.num_leds = led; ++ platform_device_register(&ar2315_gpio_leds); ++} ++#else ++static inline void ar2315_init_gpio(void) ++{ ++} ++#endif ++ ++int __init ++ar2315_init_devices(void) ++{ ++ if (!is_2315()) ++ return 0; ++ ++ /* Find board configuration */ ++ ar231x_find_config(ar2315_flash_limit()); ++ ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac; ++ ++ ar2315_init_gpio(); ++ platform_device_register(&ar2315_wdt); ++ platform_device_register(&ar2315_spiflash); ++ ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS, ++ &ar2315_eth_data); ++ ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS); ++ ++ return 0; ++} ++ ++static void ++ar2315_restart(char *command) ++{ ++ void (*mips_reset_vec)(void) = (void *) 0xbfc00000; ++ ++ local_irq_disable(); ++ ++ /* try reset the system via reset control */ ++ ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM); ++ ++ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround. ++ * give it some time to attempt a gpio based hardware reset ++ * (atheros reference design workaround) */ ++ gpio_direction_output(AR2315_RESET_GPIO, 0); ++ mdelay(100); ++ ++ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic ++ * workaround. Attempt to jump to the mips reset location - ++ * the boot loader itself might be able to recover the system */ ++ mips_reset_vec(); ++} ++ ++ ++/* ++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register ++ * to determine the predevisor value. ++ */ ++static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; ++static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 }; ++ ++static unsigned int __init ++ar2315_sys_clk(unsigned int clockCtl) ++{ ++ unsigned int pllcCtrl,cpuDiv; ++ unsigned int pllcOut,refdiv,fdiv,divby2; ++ unsigned int clkDiv; ++ ++ pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL); ++ refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S; ++ refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv]; ++ fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S; ++ divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S; ++ divby2 += 1; ++ pllcOut = (40000000/refdiv)*(2*divby2)*fdiv; ++ ++ ++ /* clkm input selected */ ++ switch(clockCtl & CPUCLK_CLK_SEL_M) { ++ case 0: ++ case 1: ++ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S]; ++ break; ++ case 2: ++ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S]; ++ break; ++ default: ++ pllcOut = 40000000; ++ clkDiv = 1; ++ break; ++ } ++ cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S; ++ cpuDiv = cpuDiv * 2 ?: 1; ++ return (pllcOut/(clkDiv * cpuDiv)); ++} ++ ++static inline unsigned int ++ar2315_cpu_frequency(void) ++{ ++ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK)); ++} ++ ++static inline unsigned int ++ar2315_apb_frequency(void) ++{ ++ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK)); ++} ++ ++void __init ++ar2315_time_init(void) ++{ ++ if (!is_2315()) ++ return; ++ ++ mips_hpt_frequency = ar2315_cpu_frequency() / 2; ++} ++ ++void __init ++ar2315_prom_init(void) ++{ ++ u32 memsize, memcfg, devid; ++ ++ if (!is_2315()) ++ return; ++ ++ memcfg = ar231x_read_reg(AR2315_MEM_CFG); ++ memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S); ++ memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S); ++ memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S); ++ memsize <<= 3; ++ add_memory_region(0, memsize, BOOT_MEM_RAM); ++ ++ /* Detect the hardware based on the device ID */ ++ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP; ++ switch(devid) { ++ case 0x90: ++ case 0x91: ++ ar231x_devtype = DEV_TYPE_AR2317; ++ break; ++ default: ++ ar231x_devtype = DEV_TYPE_AR2315; ++ break; ++ } ++ ar231x_gpiodev = &ar2315_gpiodev; ++ ar231x_board.devid = devid; ++} ++ ++void __init ++ar2315_plat_setup(void) ++{ ++ u32 config; ++ ++ if (!is_2315()) ++ return; ++ ++ /* Clear any lingering AHB errors */ ++ config = read_c0_config(); ++ write_c0_config(config & ~0x3); ++ ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET); ++ ar231x_read_reg(AR2315_AHB_ERR1); ++ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION); ++ ++ _machine_restart = ar2315_restart; ++ ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency()); ++} +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,37 @@ ++#ifndef __AR2315_H ++#define __AR2315_H ++ ++#ifdef CONFIG_ATHEROS_AR2315 ++ ++extern void ar2315_irq_init(void); ++extern int ar2315_init_devices(void); ++extern void ar2315_prom_init(void); ++extern void ar2315_plat_setup(void); ++extern void ar2315_time_init(void); ++ ++#else ++ ++static inline void ar2315_irq_init(void) ++{ ++} ++ ++static inline int ar2315_init_devices(void) ++{ ++ return 0; ++} ++ ++static inline void ar2315_prom_init(void) ++{ ++} ++ ++static inline void ar2315_plat_setup(void) ++{ ++} ++ ++static inline void ar2315_time_init(void) ++{ ++} ++ ++#endif ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,538 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ */ ++ ++/* ++ * Platform devices for Atheros SoCs ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "devices.h" ++#include "ar5312.h" ++ ++static void ++ar5312_misc_irq_dispatch(void) ++{ ++ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR); ++ ++ if (ar231x_misc_intrs & AR531X_ISR_TIMER) { ++ do_IRQ(AR531X_MISC_IRQ_TIMER); ++ (void)ar231x_read_reg(AR531X_TIMER); ++ } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC) ++ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); ++ else if ((ar231x_misc_intrs & AR531X_ISR_UART0)) ++ do_IRQ(AR531X_MISC_IRQ_UART0); ++ else if (ar231x_misc_intrs & AR531X_ISR_WD) ++ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); ++ else ++ do_IRQ(AR531X_MISC_IRQ_NONE); ++} ++ ++static asmlinkage void ++ar5312_irq_dispatch(void) ++{ ++ int pending = read_c0_status() & read_c0_cause(); ++ ++ if (pending & CAUSEF_IP2) ++ do_IRQ(AR5312_IRQ_WLAN0_INTRS); ++ else if (pending & CAUSEF_IP3) ++ do_IRQ(AR5312_IRQ_ENET0_INTRS); ++ else if (pending & CAUSEF_IP4) ++ do_IRQ(AR5312_IRQ_ENET1_INTRS); ++ else if (pending & CAUSEF_IP5) ++ do_IRQ(AR5312_IRQ_WLAN1_INTRS); ++ else if (pending & CAUSEF_IP6) ++ ar5312_misc_irq_dispatch(); ++ else if (pending & CAUSEF_IP7) ++ do_IRQ(AR531X_IRQ_CPU_CLOCK); ++} ++ ++ ++/* Enable the specified AR531X_MISC_IRQ interrupt */ ++static void ++ar5312_misc_intr_enable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR531X_IMR); ++ imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); ++ ar231x_write_reg(AR531X_IMR, imr); ++} ++ ++/* Disable the specified AR531X_MISC_IRQ interrupt */ ++static void ++ar5312_misc_intr_disable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR531X_IMR); ++ imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); ++ ar231x_write_reg(AR531X_IMR, imr); ++ ar231x_read_reg(AR531X_IMR); /* flush write buffer */ ++} ++ ++static struct irq_chip ar5312_misc_intr_controller = { ++ .name = "AR5312-MISC", ++ .irq_mask = ar5312_misc_intr_disable, ++ .irq_unmask = ar5312_misc_intr_enable, ++}; ++ ++ ++static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id) ++{ ++ u32 proc1 = ar231x_read_reg(AR531X_PROC1); ++ u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */ ++ u32 dma1 = ar231x_read_reg(AR531X_DMA1); ++ u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */ ++ ++ printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", ++ procAddr, proc1, dmaAddr, dma1); ++ ++ machine_restart("AHB error"); /* Catastrophic failure */ ++ return IRQ_HANDLED; ++} ++ ++ ++static struct irqaction ar5312_ahb_proc_interrupt = { ++ .handler = ar5312_ahb_proc_handler, ++ .flags = IRQF_DISABLED, ++ .name = "ar5312_ahb_proc_interrupt", ++}; ++ ++ ++static struct irqaction cascade = { ++ .handler = no_action, ++ .flags = IRQF_DISABLED, ++ .name = "cascade", ++}; ++ ++void __init ar5312_irq_init(void) ++{ ++ int i; ++ ++ if (!is_5312()) ++ return; ++ ++ ar231x_irq_dispatch = ar5312_irq_dispatch; ++ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { ++ int irq = AR531X_MISC_IRQ_BASE + i; ++ irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller, ++ handle_level_irq); ++ } ++ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt); ++ setup_irq(AR5312_IRQ_MISC_INTRS, &cascade); ++} ++ ++const struct ar231x_gpiodev ar5312_gpiodev; ++ ++static u32 ++ar5312_gpio_get_output(void) ++{ ++ u32 reg; ++ reg = ~(ar231x_read_reg(AR531X_GPIO_CR)); ++ reg &= ar5312_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar5312_gpio_set_output(u32 mask, u32 val) ++{ ++ u32 reg; ++ ++ reg = ar231x_read_reg(AR531X_GPIO_CR); ++ reg |= mask; ++ reg &= ~val; ++ ar231x_write_reg(AR531X_GPIO_CR, reg); ++ return reg; ++} ++ ++static u32 ++ar5312_gpio_get(void) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR531X_GPIO_DI); ++ reg &= ar5312_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar5312_gpio_set(u32 mask, u32 value) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR531X_GPIO_DO); ++ reg &= ~mask; ++ reg |= value; ++ ar231x_write_reg(AR531X_GPIO_DO, reg); ++ return reg; ++} ++ ++const struct ar231x_gpiodev ar5312_gpiodev = { ++ .valid_mask = (1 << 8) - 1, ++ .get_output = ar5312_gpio_get_output, ++ .set_output = ar5312_gpio_set_output, ++ .get = ar5312_gpio_get, ++ .set = ar5312_gpio_set, ++}; ++ ++static struct physmap_flash_data ar5312_flash_data = { ++ .width = 2, ++}; ++ ++static struct resource ar5312_flash_resource = { ++ .start = AR531X_FLASH, ++ .end = AR531X_FLASH + 0x800000 - 1, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct ar231x_eth ar5312_eth0_data = { ++ .reset_base = AR531X_RESET, ++ .reset_mac = AR531X_RESET_ENET0, ++ .reset_phy = AR531X_RESET_EPHY0, ++ .phy_base = KSEG1ADDR(AR531X_ENET0), ++ .config = &ar231x_board, ++}; ++ ++static struct ar231x_eth ar5312_eth1_data = { ++ .reset_base = AR531X_RESET, ++ .reset_mac = AR531X_RESET_ENET1, ++ .reset_phy = AR531X_RESET_EPHY1, ++ .phy_base = KSEG1ADDR(AR531X_ENET1), ++ .config = &ar231x_board, ++}; ++ ++static struct platform_device ar5312_physmap_flash = { ++ .name = "physmap-flash", ++ .id = 0, ++ .dev.platform_data = &ar5312_flash_data, ++ .resource = &ar5312_flash_resource, ++ .num_resources = 1, ++}; ++ ++#ifdef CONFIG_LEDS_GPIO ++static struct gpio_led ar5312_leds[] = { ++ { .name = "wlan", .gpio = 0, .active_low = 1, }, ++}; ++ ++static const struct gpio_led_platform_data ar5312_led_data = { ++ .num_leds = ARRAY_SIZE(ar5312_leds), ++ .leds = (void *) ar5312_leds, ++}; ++ ++static struct platform_device ar5312_gpio_leds = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = (void *) &ar5312_led_data, ++}; ++#endif ++ ++/* ++ * NB: This mapping size is larger than the actual flash size, ++ * but this shouldn't be a problem here, because the flash ++ * will simply be mapped multiple times. ++ */ ++static char __init *ar5312_flash_limit(void) ++{ ++ u32 ctl; ++ /* ++ * Configure flash bank 0. ++ * Assume 8M window size. Flash will be aliased if it's smaller ++ */ ++ ctl = FLASHCTL_E | ++ FLASHCTL_AC_8M | ++ FLASHCTL_RBLE | ++ (0x01 << FLASHCTL_IDCY_S) | ++ (0x07 << FLASHCTL_WST1_S) | ++ (0x07 << FLASHCTL_WST2_S) | ++ (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW); ++ ++ ar231x_write_reg(AR531X_FLASHCTL0, ctl); ++ ++ /* Disable other flash banks */ ++ ar231x_write_reg(AR531X_FLASHCTL1, ++ ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC)); ++ ++ ar231x_write_reg(AR531X_FLASHCTL2, ++ ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC)); ++ ++ return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000); ++} ++ ++int __init ar5312_init_devices(void) ++{ ++ struct ar231x_boarddata *config; ++ u32 fctl = 0; ++ const u8 *radio; ++ u8 *c; ++ ++ if (!is_5312()) ++ return 0; ++ ++ /* Locate board/radio config data */ ++ ar231x_find_config(ar5312_flash_limit()); ++ config = ar231x_board.config; ++ ++ ++ /* ++ * Chip IDs and hardware detection for some Atheros ++ * models are really broken! ++ * ++ * Atheros uses a disabled WMAC0 and Silicon ID of AR5312 ++ * as indication for AR2312, which is otherwise ++ * indistinguishable from the real AR5312. ++ */ ++ if (ar231x_board.radio) { ++ radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF; ++ if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0) ++ config->flags |= BD_ISCASPER; ++ } else ++ radio = NULL; ++ ++ /* AR2313 has CPU minor rev. 10 */ ++ if ((current_cpu_data.processor_id & 0xff) == 0x0a) ++ ar231x_devtype = DEV_TYPE_AR2313; ++ ++ /* AR2312 shares the same Silicon ID as AR5312 */ ++ else if (config->flags & BD_ISCASPER) ++ ar231x_devtype = DEV_TYPE_AR2312; ++ ++ /* Everything else is probably AR5312 or compatible */ ++ else ++ ar231x_devtype = DEV_TYPE_AR5312; ++ ++ /* fixup flash width */ ++ fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW; ++ switch (fctl) { ++ case FLASHCTL_MWx16: ++ ar5312_flash_data.width = 2; ++ break; ++ case FLASHCTL_MWx8: ++ default: ++ ar5312_flash_data.width = 1; ++ break; ++ } ++ ++ platform_device_register(&ar5312_physmap_flash); ++ ++#ifdef CONFIG_LEDS_GPIO ++ ar5312_leds[0].gpio = config->sysLedGpio; ++ platform_device_register(&ar5312_gpio_leds); ++#endif ++ ++ /* Fix up MAC addresses if necessary */ ++ if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6)) ++ memcpy(config->enet0_mac, config->enet1_mac, 6); ++ ++ /* If ENET0 and ENET1 have the same mac address, ++ * increment the one from ENET1 */ ++ if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) { ++ c = config->enet1_mac + 5; ++ while ((c >= config->enet1_mac) && !(++(*c))) ++ c--; ++ } ++ ++ switch(ar231x_devtype) { ++ case DEV_TYPE_AR5312: ++ ar5312_eth0_data.macaddr = config->enet0_mac; ++ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0), ++ AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data); ++ ++ ar5312_eth1_data.macaddr = config->enet1_mac; ++ ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1), ++ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); ++ ++ if (!ar231x_board.radio) ++ return 0; ++ ++ if ((*((u32 *) radio) & AR531X_RADIO0_MASK) && ++ (config->flags & BD_WLAN0)) ++ ar231x_add_wmac(0, AR531X_WLAN0, ++ AR5312_IRQ_WLAN0_INTRS); ++ ++ break; ++ /* ++ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC ++ * of ENET1. Atheros calls it 'twisted' for a reason :) ++ */ ++ case DEV_TYPE_AR2312: ++ case DEV_TYPE_AR2313: ++ ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base; ++ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy; ++ ar5312_eth1_data.macaddr = config->enet0_mac; ++ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1), ++ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); ++ ++ if (!ar231x_board.radio) ++ return 0; ++ break; ++ default: ++ break; ++ } ++ ++ if ((*((u32 *) radio) & AR531X_RADIO1_MASK) && ++ (config->flags & BD_WLAN1)) ++ ar231x_add_wmac(1, AR531X_WLAN1, ++ AR5312_IRQ_WLAN1_INTRS); ++ ++ return 0; ++} ++ ++ ++static void ar5312_restart(char *command) ++{ ++ /* reset the system */ ++ local_irq_disable(); ++ while(1) { ++ ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM); ++ } ++} ++ ++ ++/* ++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register ++ * to determine the predevisor value. ++ */ ++static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; ++ ++ ++static int __init ++ar5312_cpu_frequency(void) ++{ ++ unsigned int result; ++ unsigned int predivide_mask, predivide_shift; ++ unsigned int multiplier_mask, multiplier_shift; ++ unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier; ++ unsigned int doubler_mask; ++ u16 devid; ++ ++ /* Trust the bootrom's idea of cpu frequency. */ ++ if ((result = ar231x_read_reg(AR5312_SCRATCH))) ++ return result; ++ ++ devid = ar231x_read_reg(AR531X_REV); ++ devid &= AR531X_REV_MAJ; ++ devid >>= AR531X_REV_MAJ_S; ++ if (devid == AR531X_REV_MAJ_AR2313) { ++ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK; ++ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT; ++ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK; ++ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT; ++ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK; ++ } else { /* AR5312 and AR2312 */ ++ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK; ++ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT; ++ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK; ++ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT; ++ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK; ++ } ++ ++ /* ++ * Clocking is derived from a fixed 40MHz input clock. ++ * ++ * cpuFreq = InputClock * MULT (where MULT is PLL multiplier) ++ * sysFreq = cpuFreq / 4 (used for APB clock, serial, ++ * flash, Timer, Watchdog Timer) ++ * ++ * cntFreq = cpuFreq / 2 (use for CPU count/compare) ++ * ++ * So, for example, with a PLL multiplier of 5, we have ++ * ++ * cpuFreq = 200MHz ++ * sysFreq = 50MHz ++ * cntFreq = 100MHz ++ * ++ * We compute the CPU frequency, based on PLL settings. ++ */ ++ ++ clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1); ++ preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift; ++ preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect]; ++ multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift; ++ ++ if (clockCtl1 & doubler_mask) { ++ multiplier = multiplier << 1; ++ } ++ return (40000000 / preDivisor) * multiplier; ++} ++ ++static inline int ++ar5312_sys_frequency(void) ++{ ++ return ar5312_cpu_frequency() / 4; ++} ++ ++void __init ++ar5312_time_init(void) ++{ ++ if (!is_5312()) ++ return; ++ ++ mips_hpt_frequency = ar5312_cpu_frequency() / 2; ++} ++ ++ ++void __init ++ar5312_prom_init(void) ++{ ++ u32 memsize, memcfg, bank0AC, bank1AC; ++ u32 devid; ++ ++ if (!is_5312()) ++ return; ++ ++ /* Detect memory size */ ++ memcfg = ar231x_read_reg(AR531X_MEM_CFG1); ++ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S; ++ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S; ++ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) ++ + (bank1AC ? (1 << (bank1AC+1)) : 0); ++ memsize <<= 20; ++ add_memory_region(0, memsize, BOOT_MEM_RAM); ++ ++ devid = ar231x_read_reg(AR531X_REV); ++ devid >>= AR531X_REV_WMAC_MIN_S; ++ devid &= AR531X_REV_CHIP; ++ ar231x_board.devid = (u16) devid; ++ ar231x_gpiodev = &ar5312_gpiodev; ++} ++ ++void __init ++ar5312_plat_setup(void) ++{ ++ if (!is_5312()) ++ return; ++ ++ /* Clear any lingering AHB errors */ ++ ar231x_read_reg(AR531X_PROCADDR); ++ ar231x_read_reg(AR531X_DMAADDR); ++ ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION); ++ ++ _machine_restart = ar5312_restart; ++ ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency()); ++} ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,38 @@ ++#ifndef __AR5312_H ++#define __AR5312_H ++ ++#ifdef CONFIG_ATHEROS_AR5312 ++ ++extern void ar5312_irq_init(void); ++extern int ar5312_init_devices(void); ++extern void ar5312_prom_init(void); ++extern void ar5312_plat_setup(void); ++extern void ar5312_time_init(void); ++extern void ar5312_time_init(void); ++ ++#else ++ ++static inline void ar5312_irq_init(void) ++{ ++} ++ ++static inline int ar5312_init_devices(void) ++{ ++ return 0; ++} ++ ++static inline void ar5312_prom_init(void) ++{ ++} ++ ++static inline void ar5312_plat_setup(void) ++{ ++} ++ ++static inline void ar5312_time_init(void) ++{ ++} ++ ++#endif ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c linux-2.6.39-rc7/arch/mips/ar231x/board.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/board.c 2011-05-15 22:16:11.000000000 +0200 +@@ -0,0 +1,261 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "devices.h" ++#include "ar5312.h" ++#include "ar2315.h" ++ ++void (*ar231x_irq_dispatch)(void); ++ ++static inline bool ++check_radio_magic(u8 *addr) ++{ ++ addr += 0x7a; /* offset for flash magic */ ++ if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) { ++ return 1; ++ } ++ return 0; ++} ++ ++static inline bool ++check_board_data(u8 *flash_limit, u8 *addr, bool broken) ++{ ++ /* config magic found */ ++ if (*((u32 *)addr) == AR531X_BD_MAGIC) ++ return 1; ++ ++ if (!broken) ++ return 0; ++ ++ if (check_radio_magic(addr + 0xf8)) ++ ar231x_board.radio = addr + 0xf8; ++ if ((addr < flash_limit + 0x10000) && ++ check_radio_magic(addr + 0x10000)) ++ ar231x_board.radio = addr + 0x10000; ++ ++ if (ar231x_board.radio) { ++ /* broken board data detected, use radio data to find the offset, ++ * user will fix this */ ++ return 1; ++ } ++ return 0; ++} ++ ++static u8 * ++find_board_config(u8 *flash_limit, bool broken) ++{ ++ u8 *addr; ++ int found = 0; ++ ++ for (addr = flash_limit - 0x1000; ++ addr >= flash_limit - 0x30000; ++ addr -= 0x1000) { ++ ++ if (check_board_data(flash_limit, addr, broken)) { ++ found = 1; ++ break; ++ } ++ } ++ ++ if (!found) ++ addr = NULL; ++ ++ return addr; ++} ++ ++static u8 * ++find_radio_config(u8 *flash_limit, u8 *board_config) ++{ ++ int found; ++ u8 *radio_config; ++ ++ /* ++ * Now find the start of Radio Configuration data, using heuristics: ++ * Search forward from Board Configuration data by 0x1000 bytes ++ * at a time until we find non-0xffffffff. ++ */ ++ found = 0; ++ for (radio_config = board_config + 0x1000; ++ (radio_config < flash_limit); ++ radio_config += 0x1000) { ++ if ((*(u32 *)radio_config != 0xffffffff) && ++ check_radio_magic(radio_config)) { ++ found = 1; ++ break; ++ } ++ } ++ ++ /* AR2316 relocates radio config to new location */ ++ if (!found) { ++ for (radio_config = board_config + 0xf8; ++ (radio_config < flash_limit - 0x1000 + 0xf8); ++ radio_config += 0x1000) { ++ if ((*(u32 *)radio_config != 0xffffffff) && ++ check_radio_magic(radio_config)) { ++ found = 1; ++ break; ++ } ++ } ++ } ++ ++ if (!found) { ++ printk("Could not find Radio Configuration data\n"); ++ radio_config = 0; ++ } ++ ++ return (u8 *) radio_config; ++} ++ ++int __init ++ar231x_find_config(u8 *flash_limit) ++{ ++ struct ar231x_boarddata *config; ++ unsigned int rcfg_size; ++ int broken_boarddata = 0, i, tmp; ++ u8 *bcfg, *rcfg; ++ u8 *board_data; ++ u8 *radio_data; ++ u32 offset; ++ ++ ar231x_board.config = NULL; ++ ar231x_board.radio = NULL; ++ /* Copy the board and radio data to RAM, because accessing the mapped ++ * memory of the flash directly after booting is not safe */ ++ ++ /* Try to find valid board and radio data */ ++ bcfg = find_board_config(flash_limit, false); ++ ++ /* If that fails, try to at least find valid radio data */ ++ if (!bcfg) { ++ bcfg = find_board_config(flash_limit, true); ++ broken_boarddata = 1; ++ } ++ ++ if (!bcfg) { ++ printk(KERN_WARNING "WARNING: No board configuration data found!\n"); ++ return -ENODEV; ++ } ++ ++ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL); ++ ar231x_board.config = (struct ar231x_boarddata *) board_data; ++ memcpy(board_data, bcfg, 0x100); ++ if (broken_boarddata) { ++ printk(KERN_WARNING "WARNING: broken board data detected\n"); ++ config = ar231x_board.config; ++ if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) { ++ printk(KERN_INFO "Fixing up empty mac addresses\n"); ++ config->resetConfigGpio = 0xffff; ++ config->sysLedGpio = 0xffff; ++ random_ether_addr(config->wlan0_mac); ++ config->wlan0_mac[0] &= ~0x06; ++ random_ether_addr(config->enet0_mac); ++ random_ether_addr(config->enet1_mac); ++ } ++ } ++ ++ ++ /* Radio config starts 0x100 bytes after board config, regardless ++ * of what the physical layout on the flash chip looks like */ ++ ++ if (ar231x_board.radio) ++ rcfg = (u8 *) ar231x_board.radio; ++ else ++ rcfg = find_radio_config(flash_limit, bcfg); ++ ++ if (!rcfg) ++ return -ENODEV; ++ ++ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff); ++ ar231x_board.radio = radio_data; ++ offset = radio_data - board_data; ++ printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset); ++ rcfg_size = BOARD_CONFIG_BUFSZ - offset; ++ memcpy(radio_data, rcfg, rcfg_size); ++ ++ for (tmp = 0xff, i = 0; i < ETH_ALEN; i++) ++ tmp &= radio_data[i + 0x1d * 2]; ++ if (tmp == 0xff) { ++ u16 *eep = (u16 *)radio_data, *bcfgs = (u16 *)bcfg; ++ printk(KERN_INFO "Radio MAC is blank; using board-data\n"); ++ eep[0x1f] = bcfgs[0x30]; ++ eep[0x1e] = bcfgs[0x34]; ++ eep[0x1d] = bcfgs[0x32]; ++ } ++ ++ return 0; ++} ++ ++static void ++ar231x_halt(void) ++{ ++ local_irq_disable(); ++ while (1); ++} ++ ++void __init ++plat_mem_setup(void) ++{ ++ _machine_halt = ar231x_halt; ++ pm_power_off = ar231x_halt; ++ ++ ar5312_plat_setup(); ++ ar2315_plat_setup(); ++ ++ /* Disable data watchpoints */ ++ write_c0_watchlo0(0); ++} ++ ++ ++asmlinkage void ++plat_irq_dispatch(void) ++{ ++ ar231x_irq_dispatch(); ++} ++ ++void __init ++plat_time_init(void) ++{ ++ ar5312_time_init(); ++ ar2315_time_init(); ++} ++ ++unsigned int __cpuinit ++get_c0_compare_int(void) ++{ ++ return CP0_LEGACY_COMPARE_IRQ; ++} ++ ++void __init ++arch_init_irq(void) ++{ ++ clear_c0_status(ST0_IM); ++ mips_cpu_irq_init(); ++ ++ /* Initialize interrupt controllers */ ++ ar5312_irq_init(); ++ ar2315_irq_init(); ++} ++ ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c linux-2.6.39-rc7/arch/mips/ar231x/devices.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/devices.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,175 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "devices.h" ++#include "ar5312.h" ++#include "ar2315.h" ++ ++struct ar231x_board_config ar231x_board; ++int ar231x_devtype = DEV_TYPE_UNKNOWN; ++const struct ar231x_gpiodev *ar231x_gpiodev; ++EXPORT_SYMBOL(ar231x_gpiodev); ++ ++static struct resource ar231x_eth0_res[] = { ++ { ++ .name = "eth0_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "eth0_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct resource ar231x_eth1_res[] = { ++ { ++ .name = "eth1_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "eth1_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device ar231x_eth[] = { ++ { ++ .id = 0, ++ .name = "ar231x-eth", ++ .resource = ar231x_eth0_res, ++ .num_resources = ARRAY_SIZE(ar231x_eth0_res) ++ }, ++ { ++ .id = 1, ++ .name = "ar231x-eth", ++ .resource = ar231x_eth1_res, ++ .num_resources = ARRAY_SIZE(ar231x_eth1_res) ++ } ++}; ++ ++static struct resource ar231x_wmac0_res[] = { ++ { ++ .name = "wmac0_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "wmac0_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct resource ar231x_wmac1_res[] = { ++ { ++ .name = "wmac1_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "wmac1_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++ ++static struct platform_device ar231x_wmac[] = { ++ { ++ .id = 0, ++ .name = "ar231x-wmac", ++ .resource = ar231x_wmac0_res, ++ .num_resources = ARRAY_SIZE(ar231x_wmac0_res), ++ .dev.platform_data = &ar231x_board, ++ }, ++ { ++ .id = 1, ++ .name = "ar231x-wmac", ++ .resource = ar231x_wmac1_res, ++ .num_resources = ARRAY_SIZE(ar231x_wmac1_res), ++ .dev.platform_data = &ar231x_board, ++ }, ++}; ++ ++static const char *devtype_strings[] = { ++ [DEV_TYPE_AR5312] = "Atheros AR5312", ++ [DEV_TYPE_AR2312] = "Atheros AR2312", ++ [DEV_TYPE_AR2313] = "Atheros AR2313", ++ [DEV_TYPE_AR2315] = "Atheros AR2315", ++ [DEV_TYPE_AR2316] = "Atheros AR2316", ++ [DEV_TYPE_AR2317] = "Atheros AR2317", ++ [DEV_TYPE_UNKNOWN] = "Atheros (unknown)", ++}; ++ ++const char *get_system_type(void) ++{ ++ if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) || ++ !devtype_strings[ar231x_devtype]) ++ return devtype_strings[DEV_TYPE_UNKNOWN]; ++ return devtype_strings[ar231x_devtype]; ++} ++ ++ ++int __init ++ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata) ++{ ++ struct resource *res; ++ ++ ar231x_eth[nr].dev.platform_data = pdata; ++ res = &ar231x_eth[nr].resource[0]; ++ res->start = base; ++ res->end = base + 0x2000 - 1; ++ res++; ++ res->start = irq; ++ res->end = irq; ++ return platform_device_register(&ar231x_eth[nr]); ++} ++ ++void __init ++ar231x_serial_setup(u32 mapbase, unsigned int uartclk) ++{ ++ struct uart_port s; ++ ++ memset(&s, 0, sizeof(s)); ++ ++ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; ++ s.iotype = UPIO_MEM; ++ s.irq = AR531X_MISC_IRQ_UART0; ++ s.regshift = 2; ++ s.mapbase = mapbase; ++ s.uartclk = uartclk; ++ s.membase = (void __iomem *)s.mapbase; ++ ++ early_serial_setup(&s); ++} ++ ++int __init ++ar231x_add_wmac(int nr, u32 base, int irq) ++{ ++ struct resource *res; ++ ++ ar231x_wmac[nr].dev.platform_data = &ar231x_board; ++ res = &ar231x_wmac[nr].resource[0]; ++ res->start = base; ++ res->end = base + 0x10000 - 1; ++ res++; ++ res->start = irq; ++ res->end = irq; ++ return platform_device_register(&ar231x_wmac[nr]); ++} ++ ++static int __init ar231x_register_devices(void) ++{ ++ static struct resource res = { ++ .start = 0xFFFFFFFF, ++ }; ++ ++ platform_device_register_simple("GPIODEV", 0, &res, 1); ++ ar5312_init_devices(); ++ ar2315_init_devices(); ++ ++ return 0; ++} ++ ++device_initcall(ar231x_register_devices); +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h linux-2.6.39-rc7/arch/mips/ar231x/devices.h +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/devices.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,37 @@ ++#ifndef __AR231X_DEVICES_H ++#define __AR231X_DEVICES_H ++ ++enum { ++ /* handled by ar5312.c */ ++ DEV_TYPE_AR2312, ++ DEV_TYPE_AR2313, ++ DEV_TYPE_AR5312, ++ ++ /* handled by ar2315.c */ ++ DEV_TYPE_AR2315, ++ DEV_TYPE_AR2316, ++ DEV_TYPE_AR2317, ++ ++ DEV_TYPE_UNKNOWN ++}; ++ ++extern int ar231x_devtype; ++extern struct ar231x_board_config ar231x_board; ++extern asmlinkage void (*ar231x_irq_dispatch)(void); ++ ++extern int ar231x_find_config(u8 *flash_limit); ++extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk); ++extern int ar231x_add_wmac(int nr, u32 base, int irq); ++extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata); ++ ++static inline bool is_2315(void) ++{ ++ return (current_cpu_data.cputype == CPU_4KEC); ++} ++ ++static inline bool is_5312(void) ++{ ++ return !is_2315(); ++} ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "devices.h" ++ ++static inline void prom_uart_wr(void __iomem *base, unsigned reg, ++ unsigned char ch) ++{ ++ __raw_writeb(ch, base + 4 * reg); ++} ++ ++static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) ++{ ++ return __raw_readb(base + 4 * reg); ++} ++ ++void prom_putchar(unsigned char ch) ++{ ++ static void __iomem *base; ++ ++ if (unlikely(base == NULL)) { ++ if (is_2315()) ++ base = (void __iomem *)(KSEG1ADDR(AR2315_UART0)); ++ else ++ base = (void __iomem *)(KSEG1ADDR(AR531X_UART0)); ++ } ++ ++ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); ++ prom_uart_wr(base, UART_TX, ch); ++ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); ++} ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c linux-2.6.39-rc7/arch/mips/ar231x/pci.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/pci.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,230 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "devices.h" ++ ++#define AR531X_MEM_BASE 0x80800000UL ++#define AR531X_MEM_SIZE 0x00ffffffUL ++#define AR531X_IO_SIZE 0x00007fffUL ++ ++static unsigned long configspace; ++ ++static int config_access(int devfn, int where, int size, u32 *ptr, bool write) ++{ ++ unsigned long flags; ++ int func = PCI_FUNC(devfn); ++ int dev = PCI_SLOT(devfn); ++ u32 value = 0; ++ int err = 0; ++ u32 addr; ++ ++ if (((dev != 0) && (dev != 3)) || (func > 2)) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ /* Select Configuration access */ ++ local_irq_save(flags); ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL); ++ mb(); ++ ++ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where; ++ if (size == 1) ++ addr ^= 0x3; ++ else if (size == 2) ++ addr ^= 0x2; ++ ++ if (write) { ++ value = *ptr; ++ if (size == 1) ++ err = put_dbe(value, (u8 *) addr); ++ else if (size == 2) ++ err = put_dbe(value, (u16 *) addr); ++ else if (size == 4) ++ err = put_dbe(value, (u32 *) addr); ++ } else { ++ if (size == 1) ++ err = get_dbe(value, (u8 *) addr); ++ else if (size == 2) ++ err = get_dbe(value, (u16 *) addr); ++ else if (size == 4) ++ err = get_dbe(value, (u32 *) addr); ++ if (err) ++ *ptr = 0xffffffff; ++ else ++ *ptr = value; ++ } ++ ++ /* Select Memory access */ ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0); ++ local_irq_restore(flags); ++ ++ return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL); ++} ++ ++static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value) ++{ ++ return config_access(devfn, where, size, value, 0); ++} ++ ++static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) ++{ ++ return config_access(devfn, where, size, &value, 1); ++} ++ ++struct pci_ops ar231x_pci_ops = { ++ .read = ar231x_pci_read, ++ .write = ar231x_pci_write, ++}; ++ ++static struct resource ar231x_mem_resource = { ++ .name = "AR531x PCI MEM", ++ .start = AR531X_MEM_BASE, ++ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct resource ar231x_io_resource = { ++ .name = "AR531x PCI I/O", ++ .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE, ++ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1, ++ .flags = IORESOURCE_IO, ++}; ++ ++struct pci_controller ar231x_pci_controller = { ++ .pci_ops = &ar231x_pci_ops, ++ .mem_resource = &ar231x_mem_resource, ++ .io_resource = &ar231x_io_resource, ++ .mem_offset = 0x00000000UL, ++ .io_offset = 0x00000000UL, ++}; ++ ++int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ return AR2315_IRQ_LCBUS_PCI; ++} ++ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5); ++ pci_write_config_word(dev, 0x40, 0); ++ ++ /* Clear any pending Abort or external Interrupts ++ * and enable interrupt processing */ ++ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0); ++ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); ++ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); ++ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE); ++ ++ return 0; ++} ++ ++static void ++ar2315_pci_fixup(struct pci_dev *dev) ++{ ++ unsigned int devfn = dev->devfn; ++ ++ if (dev->bus->number != 0) ++ return; ++ ++ /* Only fix up the PCI host settings */ ++ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0)) ++ return; ++ ++ /* Fix up MBARs */ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2); ++ pci_write_config_dword(dev, PCI_COMMAND, ++ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | ++ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | ++ PCI_COMMAND_FAST_BACK); ++} ++DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup); ++ ++static int __init ++ar2315_pci_init(void) ++{ ++ u32 reg; ++ ++ if (ar231x_devtype != DEV_TYPE_AR2315) ++ return -ENODEV; ++ ++ configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */ ++ ar231x_pci_controller.io_map_base = ++ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE); ++ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */ ++ ++ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA); ++ msleep(10); ++ ++ reg &= ~AR2315_RESET_PCIDMA; ++ ar231x_write_reg(AR2315_RESET, reg); ++ msleep(10); ++ ++ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0, ++ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE); ++ ++ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | ++ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S)); ++ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); ++ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK, ++ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | ++ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT)); ++ ++ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */ ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, ++ AR2315_PCIRST_LOW); ++ msleep(100); ++ ++ /* Bring the PCI out of reset */ ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, ++ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8); ++ ++ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG, ++ 0x1E | /* 1GB uncached */ ++ (1 << 5) | /* Enable uncached */ ++ (0x2 << 30) /* Base: 0x80000000 */ ++ ); ++ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG); ++ ++ msleep(500); ++ ++ /* dirty hack - anyone with a datasheet that knows the memory map ? */ ++ ioport_resource.start = 0x10000000; ++ ioport_resource.end = 0xffffffff; ++ iomem_resource.start = 0x10000000; ++ iomem_resource.end = 0xffffffff; ++ ++ register_pci_controller(&ar231x_pci_controller); ++ ++ return 0; ++} ++ ++arch_initcall(ar2315_pci_init); +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c linux-2.6.39-rc7/arch/mips/ar231x/prom.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/prom.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,37 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright MontaVista Software Inc ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++/* ++ * Prom setup file for ar531x ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "ar5312.h" ++#include "ar2315.h" ++ ++void __init prom_init(void) ++{ ++ ar5312_prom_init(); ++ ar2315_prom_init(); ++} ++ ++void __init prom_free_prom_memory(void) ++{ ++} +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c linux-2.6.39-rc7/arch/mips/ar231x/reset.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/reset.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,161 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "devices.h" ++ ++#define AR531X_RESET_GPIO_IRQ (AR531X_GPIO_IRQ(ar231x_board.config->resetConfigGpio)) ++ ++struct event_t { ++ struct work_struct wq; ++ int set; ++ unsigned long jiffies; ++}; ++ ++static struct timer_list rst_button_timer; ++static unsigned long seen; ++ ++struct sock *uevent_sock = NULL; ++EXPORT_SYMBOL_GPL(uevent_sock); ++extern u64 uevent_next_seqnum(void); ++ ++static int no_release_workaround = 1; ++module_param(no_release_workaround, int, 0); ++ ++static inline void ++add_msg(struct sk_buff *skb, char *msg) ++{ ++ char *scratch; ++ scratch = skb_put(skb, strlen(msg) + 1); ++ sprintf(scratch, msg); ++} ++ ++static void ++hotplug_button(struct work_struct *wq) ++{ ++ struct sk_buff *skb; ++ struct event_t *event; ++ size_t len; ++ char *scratch, *s; ++ char buf[128]; ++ ++ event = container_of(wq, struct event_t, wq); ++ if (!uevent_sock) ++ goto done; ++ ++ /* allocate message with the maximum possible size */ ++ s = event->set ? "pressed" : "released"; ++ len = strlen(s) + 2; ++ skb = alloc_skb(NLMSG_GOODSIZE, GFP_KERNEL); ++ if (!skb) ++ goto done; ++ ++ /* add header */ ++ scratch = skb_put(skb, len); ++ sprintf(scratch, "%s@",s); ++ ++ /* copy keys to our continuous event payload buffer */ ++ add_msg(skb, "HOME=/"); ++ add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin"); ++ add_msg(skb, "SUBSYSTEM=button"); ++ add_msg(skb, "BUTTON=reset"); ++ add_msg(skb, (event->set ? "ACTION=pressed" : "ACTION=released")); ++ sprintf(buf, "SEEN=%ld", (event->jiffies - seen)/HZ); ++ add_msg(skb, buf); ++ snprintf(buf, 128, "SEQNUM=%llu", uevent_next_seqnum()); ++ add_msg(skb, buf); ++ ++ NETLINK_CB(skb).dst_group = 1; ++ netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL); ++ ++done: ++ kfree(event); ++} ++ ++static void ++reset_button_poll(unsigned long unused) ++{ ++ struct event_t *event; ++ int gpio = ~0; ++ ++ if(!no_release_workaround) ++ return; ++ ++ gpio = ar231x_gpiodev->get(); ++ gpio &= (1 << (AR531X_RESET_GPIO_IRQ - AR531X_GPIO_IRQ_BASE)); ++ if(gpio) { ++ rst_button_timer.expires = jiffies + (HZ / 4); ++ add_timer(&rst_button_timer); ++ return; ++ } ++ ++ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); ++ if (!event) ++ return; ++ ++ event->set = 0; ++ event->jiffies = jiffies; ++ INIT_WORK(&event->wq, hotplug_button); ++ schedule_work(&event->wq); ++} ++ ++static irqreturn_t ++button_handler(int irq, void *dev_id) ++{ ++ static int pressed = 0; ++ struct event_t *event; ++ u32 gpio = ~0; ++ ++ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); ++ if (!event) ++ return IRQ_NONE; ++ ++ pressed = !pressed; ++ ++ gpio = ar231x_gpiodev->get() & (1 << (irq - AR531X_GPIO_IRQ_BASE)); ++ ++ event->set = gpio; ++ if(!event->set) ++ no_release_workaround = 0; ++ ++ event->jiffies = jiffies; ++ ++ INIT_WORK(&event->wq, hotplug_button); ++ schedule_work(&event->wq); ++ ++ seen = jiffies; ++ if(event->set && no_release_workaround) ++ mod_timer(&rst_button_timer, jiffies + (HZ / 4)); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++static int __init ++ar231x_init_reset(void) ++{ ++ seen = jiffies; ++ ++ if (ar231x_board.config->resetConfigGpio == 0xffff) ++ return -ENODEV; ++ ++ init_timer(&rst_button_timer); ++ rst_button_timer.function = reset_button_poll; ++ rst_button_timer.expires = jiffies + HZ / 50; ++ add_timer(&rst_button_timer); ++ ++ request_irq(AR531X_RESET_GPIO_IRQ, &button_handler, IRQF_SAMPLE_RANDOM, "ar231x_reset", NULL); ++ ++ return 0; ++} ++ ++module_init(ar231x_init_reset); +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 2011-05-15 21:44:12.000000000 +0200 +@@ -0,0 +1,580 @@ ++/* ++ * Register definitions for AR2315+ ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2008 Felix Fietkau ++ */ ++ ++#ifndef __AR2315_REG_H ++#define __AR2315_REG_H ++ ++/* ++ * IRQs ++ */ ++#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ ++#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ ++#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ ++#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ ++#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ ++ ++/* ++ * Address map ++ */ ++#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */ ++#define AR2315_WLAN0 0x10000000 /* Wireless MMR */ ++#define AR2315_PCI 0x10100000 /* PCI MMR */ ++#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */ ++#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */ ++#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */ ++#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */ ++#define AR2315_UART0 0x11100003 /* UART MMR */ ++#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */ ++#define AR2315_PCIEXT 0x80000000 /* pci external */ ++ ++/* ++ * Reset Register ++ */ ++#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000) ++ ++#define AR2315_RESET_COLD_AHB 0x00000001 ++#define AR2315_RESET_COLD_APB 0x00000002 ++#define AR2315_RESET_COLD_CPU 0x00000004 ++#define AR2315_RESET_COLD_CPUWARM 0x00000008 ++#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */ ++#define AR2317_RESET_SYSTEM 0x00000010 ++ ++ ++#define AR2315_RESET (AR2315_DSLBASE + 0x0004) ++ ++#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */ ++#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */ ++#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */ ++#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */ ++#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */ ++#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */ ++#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */ ++#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */ ++#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */ ++#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */ ++#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */ ++#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */ ++ ++/* ++ * AHB master arbitration control ++ */ ++#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008) ++ ++#define AR2315_ARB_CPU 0x00000001 /* CPU, default */ ++#define AR2315_ARB_WLAN 0x00000002 /* WLAN */ ++#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ ++#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */ ++#define AR2315_ARB_PCI 0x00000010 /* PCI */ ++#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */ ++#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */ ++ ++/* ++ * Config Register ++ */ ++#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c) ++ ++#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */ ++#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ ++#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */ ++#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */ ++#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */ ++#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */ ++#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */ ++ ++#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */ ++#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */ ++#define AR2315_CONFIG_PCIAHB 0x00000800 ++#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000 ++#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */ ++#define AR2315_CONFIG_CPU_DRAM 0x00010000 ++#define AR2315_CONFIG_CPU_PCI 0x00020000 ++#define AR2315_CONFIG_CPU_MMR 0x00040000 ++#define AR2315_CONFIG_BIG 0x00000400 ++ ++ ++/* ++ * NMI control ++ */ ++#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010) ++ ++#define AR2315_NMI_EN 1 ++ ++/* ++ * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0). ++ */ ++#define AR2315_SREV (AR2315_DSLBASE + 0x0014) ++ ++#define AR2315_REV_MAJ 0x00f0 ++#define AR2315_REV_MAJ_S 4 ++#define AR2315_REV_MIN 0x000f ++#define AR2315_REV_MIN_S 0 ++#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN) ++ ++/* ++ * Interface Enable ++ */ ++#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018) ++ ++#define AR2315_IF_MASK 0x00000007 ++#define AR2315_IF_DISABLED 0 ++#define AR2315_IF_PCI 1 ++#define AR2315_IF_TS_LOCAL 2 ++#define AR2315_IF_ALL 3 /* only for emulation with separate pins */ ++#define AR2315_IF_LOCAL_HOST 0x00000008 ++#define AR2315_IF_PCI_HOST 0x00000010 ++#define AR2315_IF_PCI_INTR 0x00000020 ++#define AR2315_IF_PCI_CLK_MASK 0x00030000 ++#define AR2315_IF_PCI_CLK_INPUT 0 ++#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1 ++#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2 ++#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3 ++#define AR2315_IF_PCI_CLK_SHIFT 16 ++ ++/* ++ * APB Interrupt control ++ */ ++ ++#define AR2315_ISR (AR2315_DSLBASE + 0x0020) ++#define AR2315_IMR (AR2315_DSLBASE + 0x0024) ++#define AR2315_GISR (AR2315_DSLBASE + 0x0028) ++ ++#define AR2315_ISR_UART0 0x0001 /* high speed UART */ ++#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */ ++#define AR2315_ISR_SPI 0x0004 /* SPI bus */ ++#define AR2315_ISR_AHB 0x0008 /* AHB error */ ++#define AR2315_ISR_APB 0x0010 /* APB error */ ++#define AR2315_ISR_TIMER 0x0020 /* timer */ ++#define AR2315_ISR_GPIO 0x0040 /* GPIO */ ++#define AR2315_ISR_WD 0x0080 /* watchdog */ ++#define AR2315_ISR_IR_RSVD 0x0100 /* IR */ ++ ++#define AR2315_GISR_MISC 0x0001 ++#define AR2315_GISR_WLAN0 0x0002 ++#define AR2315_GISR_MPEGTS_RSVD 0x0004 ++#define AR2315_GISR_LOCALPCI 0x0008 ++#define AR2315_GISR_WMACPOLL 0x0010 ++#define AR2315_GISR_TIMER 0x0020 ++#define AR2315_GISR_ETHERNET 0x0040 ++ ++/* ++ * Interrupt routing from IO to the processor IP bits ++ * Define our inter mask and level ++ */ ++#define AR2315_INTR_MISCIO SR_IBIT3 ++#define AR2315_INTR_WLAN0 SR_IBIT4 ++#define AR2315_INTR_ENET0 SR_IBIT5 ++#define AR2315_INTR_LOCALPCI SR_IBIT6 ++#define AR2315_INTR_WMACPOLL SR_IBIT7 ++#define AR2315_INTR_COMPARE SR_IBIT8 ++ ++/* ++ * Timers ++ */ ++#define AR2315_TIMER (AR2315_DSLBASE + 0x0030) ++#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034) ++#define AR2315_WD (AR2315_DSLBASE + 0x0038) ++#define AR2315_WDC (AR2315_DSLBASE + 0x003c) ++ ++#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000 ++#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */ ++#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */ ++ ++/* ++ * CPU Performance Counters ++ */ ++#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048) ++#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c) ++ ++#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */ ++#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */ ++#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */ ++#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */ ++#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */ ++#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */ ++#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */ ++ ++#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */ ++#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */ ++#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */ ++#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */ ++#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */ ++#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */ ++#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */ ++ ++/* ++ * AHB Error Reporting. ++ */ ++#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */ ++#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */ ++#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */ ++#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */ ++#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */ ++ ++#define AHB_ERROR_DET 1 /* AHB Error has been detected, */ ++ /* write 1 to clear all bits in ERR0 */ ++#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */ ++#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */ ++ ++#define AR2315_PROCERR_HMAST 0x0000000f ++#define AR2315_PROCERR_HMAST_DFLT 0 ++#define AR2315_PROCERR_HMAST_WMAC 1 ++#define AR2315_PROCERR_HMAST_ENET 2 ++#define AR2315_PROCERR_HMAST_PCIENDPT 3 ++#define AR2315_PROCERR_HMAST_LOCAL 4 ++#define AR2315_PROCERR_HMAST_CPU 5 ++#define AR2315_PROCERR_HMAST_PCITGT 6 ++ ++#define AR2315_PROCERR_HMAST_S 0 ++#define AR2315_PROCERR_HWRITE 0x00000010 ++#define AR2315_PROCERR_HSIZE 0x00000060 ++#define AR2315_PROCERR_HSIZE_S 5 ++#define AR2315_PROCERR_HTRANS 0x00000180 ++#define AR2315_PROCERR_HTRANS_S 7 ++#define AR2315_PROCERR_HBURST 0x00000e00 ++#define AR2315_PROCERR_HBURST_S 9 ++ ++/* ++ * Clock Control ++ */ ++#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064) ++#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068) ++#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c) ++#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070) ++#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074) ++#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080) ++#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084) ++ ++/* PLLc Control fields */ ++#define PLLC_REF_DIV_M 0x00000003 ++#define PLLC_REF_DIV_S 0 ++#define PLLC_FDBACK_DIV_M 0x0000007C ++#define PLLC_FDBACK_DIV_S 2 ++#define PLLC_ADD_FDBACK_DIV_M 0x00000080 ++#define PLLC_ADD_FDBACK_DIV_S 7 ++#define PLLC_CLKC_DIV_M 0x0001c000 ++#define PLLC_CLKC_DIV_S 14 ++#define PLLC_CLKM_DIV_M 0x00700000 ++#define PLLC_CLKM_DIV_S 20 ++ ++/* CPU CLK Control fields */ ++#define CPUCLK_CLK_SEL_M 0x00000003 ++#define CPUCLK_CLK_SEL_S 0 ++#define CPUCLK_CLK_DIV_M 0x0000000c ++#define CPUCLK_CLK_DIV_S 2 ++ ++/* AMBA CLK Control fields */ ++#define AMBACLK_CLK_SEL_M 0x00000003 ++#define AMBACLK_CLK_SEL_S 0 ++#define AMBACLK_CLK_DIV_M 0x0000000c ++#define AMBACLK_CLK_DIV_S 2 ++ ++/* ++ * GPIO ++ */ ++#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088) ++#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090) ++#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098) ++#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0) ++ ++#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ ++#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */ ++#define AR2315_GPIO_CR_I(x) (0) /* input */ ++ ++#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */ ++#define AR2315_GPIO_INT_M (0x3F) /* mask for int */ ++#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */ ++#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */ ++ ++#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */ ++#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */ ++#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */ ++#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */ ++#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */ ++ ++#define AR2315_RESET_GPIO 5 ++#define AR2315_NUM_GPIO 22 ++ ++/* ++ * PCI Clock Control ++ */ ++#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4) ++ ++#define AR2315_PCICLK_INPUT_M 0x3 ++#define AR2315_PCICLK_INPUT_S 0 ++ ++#define AR2315_PCICLK_PLLC_CLKM 0 ++#define AR2315_PCICLK_PLLC_CLKM1 1 ++#define AR2315_PCICLK_PLLC_CLKC 2 ++#define AR2315_PCICLK_REF_CLK 3 ++ ++#define AR2315_PCICLK_DIV_M 0xc ++#define AR2315_PCICLK_DIV_S 2 ++ ++#define AR2315_PCICLK_IN_FREQ 0 ++#define AR2315_PCICLK_IN_FREQ_DIV_6 1 ++#define AR2315_PCICLK_IN_FREQ_DIV_8 2 ++#define AR2315_PCICLK_IN_FREQ_DIV_10 3 ++ ++/* ++ * Observation Control Register ++ */ ++#define AR2315_OCR (AR2315_DSLBASE + 0x00b0) ++#define OCR_GPIO0_IRIN 0x0040 ++#define OCR_GPIO1_IROUT 0x0080 ++#define OCR_GPIO3_RXCLR 0x0200 ++ ++/* ++ * General Clock Control ++ */ ++ ++#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4) ++#define MISCCLK_PLLBYPASS_EN 0x00000001 ++#define MISCCLK_PROCREFCLK 0x00000002 ++ ++/* ++ * SDRAM Controller ++ * - No read or write buffers are included. ++ */ ++#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00) ++#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c) ++#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10) ++ ++#define SDRAM_DATA_WIDTH_M 0x00006000 ++#define SDRAM_DATA_WIDTH_S 13 ++ ++#define SDRAM_COL_WIDTH_M 0x00001E00 ++#define SDRAM_COL_WIDTH_S 9 ++ ++#define SDRAM_ROW_WIDTH_M 0x000001E0 ++#define SDRAM_ROW_WIDTH_S 5 ++ ++#define SDRAM_BANKADDR_BITS_M 0x00000018 ++#define SDRAM_BANKADDR_BITS_S 3 ++ ++/* ++ * SPI Flash Interface Registers ++ */ ++ ++#define AR2315_SPI_CTL (AR2315_SPI + 0x00) ++#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04) ++#define AR2315_SPI_DATA (AR2315_SPI + 0x08) ++ ++#define SPI_CTL_START 0x00000100 ++#define SPI_CTL_BUSY 0x00010000 ++#define SPI_CTL_TXCNT_MASK 0x0000000f ++#define SPI_CTL_RXCNT_MASK 0x000000f0 ++#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff ++#define SPI_CTL_SIZE_MASK 0x00060000 ++ ++#define SPI_CTL_CLK_SEL_MASK 0x03000000 ++#define SPI_OPCODE_MASK 0x000000ff ++ ++/* ++ * PCI Bus Interface Registers ++ */ ++#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008) ++#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ ++ ++#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c) ++#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */ ++#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */ ++#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */ ++#define AR2315_PCIMISC_RST_MODE 0x00000030 ++#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */ ++#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */ ++#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */ ++#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */ ++#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */ ++#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */ ++#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */ ++#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */ ++ ++#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010) ++ ++#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014) ++ ++#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100) ++#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */ ++#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */ ++#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */ ++#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */ ++ ++#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104) ++#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */ ++#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */ ++#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */ ++#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */ ++ ++#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200) ++ ++#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400) ++#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */ ++ ++#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404) ++#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */ ++ ++#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408) ++ ++#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */ ++#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */ ++#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */ ++#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */ ++#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */ ++#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */ ++#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */ ++#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */ ++#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */ ++#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */ ++#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */ ++#define AR2315_PCI_EXT_INT 0x02000000 ++#define AR2315_PCI_ABORT_INT 0x04000000 ++ ++#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */ ++ ++#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508) ++#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */ ++#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */ ++ ++#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800) ++#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804) ++#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810) ++#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900) ++#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904) ++#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908) ++ ++ ++/* ++ * Local Bus Interface Registers ++ */ ++#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000) ++#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */ ++#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */ ++#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */ ++#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */ ++#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */ ++#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */ ++#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */ ++#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */ ++#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */ ++#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */ ++#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */ ++#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */ ++#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */ ++#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */ ++#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */ ++#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */ ++#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */ ++#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */ ++#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */ ++#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */ ++#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */ ++#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */ ++#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */ ++#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */ ++#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */ ++ ++#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004) ++#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */ ++ ++#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008) ++#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ ++ ++#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C) ++#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */ ++#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */ ++#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */ ++#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */ ++#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */ ++#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80 ++#define AR2315_LBM_TIMEOUT_SHFT 7 ++#define AR2315_LBM_PORTMUX 0x07000000 ++ ++ ++#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010) ++ ++#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100) ++#define AR2315_LB_TXEN_0 0x01 ++#define AR2315_LB_TXEN_1 0x02 ++#define AR2315_LB_TXEN_2 0x04 ++#define AR2315_LB_TXEN_3 0x08 ++ ++#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104) ++#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200) ++ ++#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400) ++#define AR2315_LB_RXEN 0x01 ++ ++#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404) ++#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408) ++ ++#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500) ++#define AR2315_INT_TX_DESC 0x0001 ++#define AR2315_INT_TX_OK 0x0002 ++#define AR2315_INT_TX_ERR 0x0004 ++#define AR2315_INT_TX_EOF 0x0008 ++#define AR2315_INT_RX_DESC 0x0010 ++#define AR2315_INT_RX_OK 0x0020 ++#define AR2315_INT_RX_ERR 0x0040 ++#define AR2315_INT_RX_EOF 0x0080 ++#define AR2315_INT_TX_TRUNC 0x0100 ++#define AR2315_INT_TX_STARVE 0x0200 ++#define AR2315_INT_LB_TIMEOUT 0x0400 ++#define AR2315_INT_LB_ERR 0x0800 ++#define AR2315_INT_MBOX_WR 0x1000 ++#define AR2315_INT_MBOX_RD 0x2000 ++ ++/* Bit definitions for INT MASK are the same as INT_STATUS */ ++#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504) ++ ++#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508) ++#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600) ++ ++/* ++ * IR Interface Registers ++ */ ++#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000) ++ ++#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */ ++ ++#define AR2315_IR_CONTROL (AR2315_IR + 0x0800) ++#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */ ++#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */ ++#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */ ++#define AR2315_IRCTL_SAMPLECLK_SHFT 1 ++#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */ ++#define AR2315_IRCTL_OUTPUTCLK_SHFT 14 ++ ++#define AR2315_IR_STATUS (AR2315_IR + 0x0804) ++#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */ ++#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */ ++ ++#define AR2315_IR_CONFIG (AR2315_IR + 0x0808) ++#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */ ++#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */ ++#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */ ++#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */ ++#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */ ++#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */ ++#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */ ++#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */ ++#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */ ++ ++#define HOST_PCI_DEV_ID 3 ++#define HOST_PCI_MBAR0 0x10000000 ++#define HOST_PCI_MBAR1 0x20000000 ++#define HOST_PCI_MBAR2 0x30000000 ++ ++#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1 ++#define PCI_DEVICE_MEM_SPACE 0x800000 ++ ++#endif /* __AR2315_REG_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,116 @@ ++/* ++ * SPI Flash Memory support header file. ++ * ++ * Copyright (c) 2005, Atheros Communications Inc. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * This code is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#ifndef __AR2315_SPIFLASH_H ++#define __AR2315_SPIFLASH_H ++ ++#define STM_PAGE_SIZE 256 ++ ++#define SFI_WRITE_BUFFER_SIZE 4 ++#define SFI_FLASH_ADDR_MASK 0x00ffffff ++ ++#define STM_8MBIT_SIGNATURE 0x13 ++#define STM_M25P80_BYTE_COUNT 1048576 ++#define STM_M25P80_SECTOR_COUNT 16 ++#define STM_M25P80_SECTOR_SIZE 0x10000 ++ ++#define STM_16MBIT_SIGNATURE 0x14 ++#define STM_M25P16_BYTE_COUNT 2097152 ++#define STM_M25P16_SECTOR_COUNT 32 ++#define STM_M25P16_SECTOR_SIZE 0x10000 ++ ++#define STM_32MBIT_SIGNATURE 0x15 ++#define STM_M25P32_BYTE_COUNT 4194304 ++#define STM_M25P32_SECTOR_COUNT 64 ++#define STM_M25P32_SECTOR_SIZE 0x10000 ++ ++#define STM_64MBIT_SIGNATURE 0x16 ++#define STM_M25P64_BYTE_COUNT 8388608 ++#define STM_M25P64_SECTOR_COUNT 128 ++#define STM_M25P64_SECTOR_SIZE 0x10000 ++ ++#define STM_128MBIT_SIGNATURE 0x17 ++#define STM_M25P128_BYTE_COUNT 16777216 ++#define STM_M25P128_SECTOR_COUNT 256 ++#define STM_M25P128_SECTOR_SIZE 0x10000 ++ ++#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT ++#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT ++#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE ++#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT ++#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT ++#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE ++#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT ++#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT ++#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE ++#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT ++#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT ++#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE ++#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT ++#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT ++#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE ++ ++/* ++ * ST Microelectronics Opcodes for Serial Flash ++ */ ++ ++#define STM_OP_WR_ENABLE 0x06 /* Write Enable */ ++#define STM_OP_WR_DISABLE 0x04 /* Write Disable */ ++#define STM_OP_RD_STATUS 0x05 /* Read Status */ ++#define STM_OP_WR_STATUS 0x01 /* Write Status */ ++#define STM_OP_RD_DATA 0x03 /* Read Data */ ++#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */ ++#define STM_OP_PAGE_PGRM 0x02 /* Page Program */ ++#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */ ++#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */ ++#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */ ++#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */ ++ ++#define STM_STATUS_WIP 0x01 /* Write-In-Progress */ ++#define STM_STATUS_WEL 0x02 /* Write Enable Latch */ ++#define STM_STATUS_BP0 0x04 /* Block Protect 0 */ ++#define STM_STATUS_BP1 0x08 /* Block Protect 1 */ ++#define STM_STATUS_BP2 0x10 /* Block Protect 2 */ ++#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */ ++ ++/* ++ * SPI Flash Interface Registers ++ */ ++#define AR531XPLUS_SPI_READ 0x08000000 ++#define AR531XPLUS_SPI_MMR 0x11300000 ++#define AR531XPLUS_SPI_MMR_SIZE 12 ++ ++#define AR531XPLUS_SPI_CTL 0x00 ++#define AR531XPLUS_SPI_OPCODE 0x04 ++#define AR531XPLUS_SPI_DATA 0x08 ++ ++#define SPI_FLASH_READ AR531XPLUS_SPI_READ ++#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR ++#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE ++#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL ++#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE ++#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA ++ ++#define SPI_CTL_START 0x00000100 ++#define SPI_CTL_BUSY 0x00010000 ++#define SPI_CTL_TXCNT_MASK 0x0000000f ++#define SPI_CTL_RXCNT_MASK 0x000000f0 ++#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff ++#define SPI_CTL_SIZE_MASK 0x00060000 ++ ++#define SPI_CTL_CLK_SEL_MASK 0x03000000 ++#define SPI_OPCODE_MASK 0x000000ff ++ ++#define SPI_STATUS_WIP STM_STATUS_WIP ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,54 @@ ++#ifndef __AR531X_H ++#define __AR531X_H ++ ++#define AR531X_MISC_IRQ_BASE 0x20 ++#define AR531X_GPIO_IRQ_BASE 0x30 ++ ++/* Software's idea of interrupts handled by "CPU Interrupt Controller" */ ++#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0 ++#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */ ++ ++/* Miscellaneous interrupts, which share IP6 */ ++#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0 ++#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1 ++#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2 ++#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3 ++#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4 ++#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5 ++#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6 ++#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7 ++#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8 ++#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9 ++#define AR531X_MISC_IRQ_COUNT 10 ++ ++/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */ ++#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0 ++#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n ++#define AR531X_GPIO_IRQ_COUNT 22 ++ ++static inline u32 ++ar231x_read_reg(u32 reg) ++{ ++ return __raw_readl((u32 *) KSEG1ADDR(reg)); ++} ++ ++static inline void ++ar231x_write_reg(u32 reg, u32 val) ++{ ++ __raw_writel(val, (u32 *) KSEG1ADDR(reg)); ++} ++ ++static inline u32 ++ar231x_mask_reg(u32 reg, u32 mask, u32 val) ++{ ++ u32 ret; ++ ++ ret = ar231x_read_reg(reg); ++ ret &= ~mask; ++ ret |= val; ++ ar231x_write_reg(reg, ret); ++ ++ return ret; ++} ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,83 @@ ++#ifndef __AR531X_PLATFORM_H ++#define __AR531X_PLATFORM_H ++ ++/* ++ * This is board-specific data that is stored in a "fixed" location in flash. ++ * It is shared across operating systems, so it should not be changed lightly. ++ * The main reason we need it is in order to extract the ethernet MAC ++ * address(es). ++ */ ++struct ar231x_boarddata { ++ u32 magic; /* board data is valid */ ++#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */ ++ u16 cksum; /* checksum (starting with BD_REV 2) */ ++ u16 rev; /* revision of this struct */ ++#define BD_REV 4 ++ char boardName[64]; /* Name of board */ ++ u16 major; /* Board major number */ ++ u16 minor; /* Board minor number */ ++ u32 flags; /* Board configuration */ ++#define BD_ENET0 0x00000001 /* ENET0 is stuffed */ ++#define BD_ENET1 0x00000002 /* ENET1 is stuffed */ ++#define BD_UART1 0x00000004 /* UART1 is stuffed */ ++#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */ ++#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */ ++#define BD_SYSLED 0x00000020 /* System LED stuffed */ ++#define BD_EXTUARTCLK 0x00000040 /* External UART clock */ ++#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */ ++#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */ ++#define BD_WLAN0 0x00000200 /* Enable WLAN0 */ ++#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */ ++#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */ ++#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */ ++#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */ ++#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */ ++#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */ ++#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */ ++#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */ ++ u16 resetConfigGpio; /* Reset factory GPIO pin */ ++ u16 sysLedGpio; /* System LED GPIO pin */ ++ ++ u32 cpuFreq; /* CPU core frequency in Hz */ ++ u32 sysFreq; /* System frequency in Hz */ ++ u32 cntFreq; /* Calculated C0_COUNT frequency */ ++ ++ u8 wlan0_mac[6]; ++ u8 enet0_mac[6]; ++ u8 enet1_mac[6]; ++ ++ u16 pciId; /* Pseudo PCIID for common code */ ++ u16 memCap; /* cap bank1 in MB */ ++ ++ /* version 3 */ ++ u8 wlan1_mac[6]; /* (ar5212) */ ++}; ++ ++#define BOARD_CONFIG_BUFSZ 0x1000 ++ ++/* ++ * Platform device information for the Wireless MAC ++ */ ++struct ar231x_board_config { ++ u16 devid; ++ ++ /* board config data */ ++ struct ar231x_boarddata *config; ++ ++ /* radio calibration data */ ++ const char *radio; ++}; ++ ++/* ++ * Platform device information for the Ethernet MAC ++ */ ++struct ar231x_eth { ++ u32 reset_base; ++ u32 reset_mac; ++ u32 reset_phy; ++ u32 phy_base; ++ struct ar231x_board_config *config; ++ char *macaddr; ++}; ++ ++#endif /* __AR531X_PLATFORM_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,236 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++#ifndef AR5312_H ++#define AR5312_H ++ ++#include ++ ++/* ++ * IRQs ++ */ ++ ++#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ ++#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ ++#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ ++#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ ++#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ ++ ++ ++/* Address Map */ ++#define AR531X_WLAN0 0x18000000 ++#define AR531X_WLAN1 0x18500000 ++#define AR531X_ENET0 0x18100000 ++#define AR531X_ENET1 0x18200000 ++#define AR531X_SDRAMCTL 0x18300000 ++#define AR531X_FLASHCTL 0x18400000 ++#define AR531X_APBBASE 0x1c000000 ++#define AR531X_FLASH 0x1e000000 ++#define AR531X_UART0 0xbc000003 /* UART MMR */ ++ ++/* ++ * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that ++ * should be considered available. The AR5312 supports 2 enet MACS, ++ * even though many reference boards only actually use 1 of them ++ * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch. ++ * The AR2312 supports 1 enet MAC. ++ */ ++#define AR531X_NUM_ENET_MAC 2 ++ ++/* ++ * Need these defines to determine true number of ethernet MACs ++ */ ++#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ ++#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ ++#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ ++#define AR531X_RADIO_MASK_OFF 0xc8 ++#define AR531X_RADIO0_MASK 0x0003 ++#define AR531X_RADIO1_MASK 0x000c ++#define AR531X_RADIO1_S 2 ++ ++/* ++ * AR531X_NUM_WMAC defines the number of Wireless MACs that\ ++ * should be considered available. ++ */ ++#define AR531X_NUM_WMAC 2 ++ ++/* Reset/Timer Block Address Map */ ++#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000) ++#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */ ++#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */ ++#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */ ++#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */ ++#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */ ++#define AR531X_RESET (AR531X_RESETTMR + 0x0020) ++#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064) ++#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c) ++#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070) ++#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074) ++#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078) ++#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c) ++#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */ ++#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */ ++ ++/* AR531X_WD_CTRL register bit field definitions */ ++#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000 ++#define AR531X_WD_CTRL_NMI 0x0001 ++#define AR531X_WD_CTRL_RESET 0x0002 ++ ++/* AR531X_ISR register bit field definitions */ ++#define AR531X_ISR_NONE 0x0000 ++#define AR531X_ISR_TIMER 0x0001 ++#define AR531X_ISR_AHBPROC 0x0002 ++#define AR531X_ISR_AHBDMA 0x0004 ++#define AR531X_ISR_GPIO 0x0008 ++#define AR531X_ISR_UART0 0x0010 ++#define AR531X_ISR_UART0DMA 0x0020 ++#define AR531X_ISR_WD 0x0040 ++#define AR531X_ISR_LOCAL 0x0080 ++ ++/* AR531X_RESET register bit field definitions */ ++#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */ ++#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */ ++#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */ ++#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */ ++#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */ ++#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */ ++#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */ ++#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */ ++#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */ ++#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */ ++#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */ ++#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */ ++#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */ ++#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */ ++#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */ ++#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */ ++#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */ ++#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */ ++ ++#define AR531X_RESET_WMAC0_BITS \ ++ AR531X_RESET_WLAN0 |\ ++ AR531X_RESET_WARM_WLAN0_MAC |\ ++ AR531X_RESET_WARM_WLAN0_BB ++ ++#define AR531X_RESERT_WMAC1_BITS \ ++ AR531X_RESET_WLAN1 |\ ++ AR531X_RESET_WARM_WLAN1_MAC |\ ++ AR531X_RESET_WARM_WLAN1_BB ++ ++/* AR5312_CLOCKCTL1 register bit field definitions */ ++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 ++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 ++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 ++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 ++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 ++ ++/* Valid for AR5312 and AR2312 */ ++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 ++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 ++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 ++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 ++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 ++ ++/* Valid for AR2313 */ ++#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000 ++#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12 ++#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000 ++#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16 ++#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000 ++ ++ ++/* AR531X_ENABLE register bit field definitions */ ++#define AR531X_ENABLE_WLAN0 0x0001 ++#define AR531X_ENABLE_ENET0 0x0002 ++#define AR531X_ENABLE_ENET1 0x0004 ++#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */ ++#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */ ++#define AR531X_ENABLE_WLAN1 \ ++ (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA) ++ ++/* AR531X_REV register bit field definitions */ ++#define AR531X_REV_WMAC_MAJ 0xf000 ++#define AR531X_REV_WMAC_MAJ_S 12 ++#define AR531X_REV_WMAC_MIN 0x0f00 ++#define AR531X_REV_WMAC_MIN_S 8 ++#define AR531X_REV_MAJ 0x00f0 ++#define AR531X_REV_MAJ_S 4 ++#define AR531X_REV_MIN 0x000f ++#define AR531X_REV_MIN_S 0 ++#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN) ++ ++/* Major revision numbers, bits 7..4 of Revision ID register */ ++#define AR531X_REV_MAJ_AR5312 0x4 ++#define AR531X_REV_MAJ_AR2313 0x5 ++ ++/* Minor revision numbers, bits 3..0 of Revision ID register */ ++#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */ ++#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */ ++ ++/* AR531X_FLASHCTL register bit field definitions */ ++#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */ ++#define FLASHCTL_IDCY_S 0 ++#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */ ++#define FLASHCTL_WST1_S 5 ++#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */ ++#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */ ++#define FLASHCTL_WST2_S 11 ++#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */ ++#define FLASHCTL_AC_S 16 ++#define FLASHCTL_AC_128K 0x00000000 ++#define FLASHCTL_AC_256K 0x00010000 ++#define FLASHCTL_AC_512K 0x00020000 ++#define FLASHCTL_AC_1M 0x00030000 ++#define FLASHCTL_AC_2M 0x00040000 ++#define FLASHCTL_AC_4M 0x00050000 ++#define FLASHCTL_AC_8M 0x00060000 ++#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */ ++#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */ ++#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */ ++#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */ ++#define FLASHCTL_WP 0x04000000 /* Write protect */ ++#define FLASHCTL_BM 0x08000000 /* Burst mode */ ++#define FLASHCTL_MW 0x30000000 /* Memory width */ ++#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */ ++#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */ ++#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */ ++#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */ ++#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */ ++#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */ ++ ++/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */ ++#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00) ++#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04) ++#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08) ++ ++/* ARM SDRAM Controller -- just enough to determine memory size */ ++#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04) ++#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */ ++#define MEM_CFG1_AC0_S 8 ++#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */ ++#define MEM_CFG1_AC1_S 12 ++ ++/* GPIO Address Map */ ++#define AR531X_GPIO (AR531X_APBBASE + 0x2000) ++#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */ ++#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */ ++#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */ ++ ++/* GPIO Control Register bit field definitions */ ++#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ ++#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */ ++#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */ ++#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */ ++#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */ ++#define AR531X_NUM_GPIO 8 ++ ++ ++#endif ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,84 @@ ++/* ++ * Atheros SoC specific CPU feature overrides ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * ++ * This file was derived from: include/asm-mips/cpu-features.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * Copyright (C) 2004 Maciej W. Rozycki ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H ++#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H ++ ++/* ++ * The ATHEROS SoCs have MIPS 4Kc/4KEc core. ++ */ ++#define cpu_has_tlb 1 ++#define cpu_has_4kex 1 ++#define cpu_has_3k_cache 0 ++#define cpu_has_4k_cache 1 ++#define cpu_has_tx39_cache 0 ++#define cpu_has_sb1_cache 0 ++#define cpu_has_fpu 0 ++#define cpu_has_32fpr 0 ++#define cpu_has_counter 1 ++/* #define cpu_has_watch ? */ ++/* #define cpu_has_divec ? */ ++/* #define cpu_has_vce ? */ ++/* #define cpu_has_cache_cdex_p ? */ ++/* #define cpu_has_cache_cdex_s ? */ ++/* #define cpu_has_prefetch ? */ ++/* #define cpu_has_mcheck ? */ ++#define cpu_has_ejtag 1 ++ ++#if !defined(CONFIG_ATHEROS_AR5312) ++# define cpu_has_llsc 1 ++#else ++/* ++ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the ++ * ll/sc instructions. ++ */ ++# define cpu_has_llsc 0 ++#endif ++ ++#define cpu_has_mips16 0 ++#define cpu_has_mdmx 0 ++#define cpu_has_mips3d 0 ++#define cpu_has_smartmips 0 ++ ++/* #define cpu_has_vtag_icache ? */ ++/* #define cpu_has_dc_aliases ? */ ++/* #define cpu_has_ic_fills_f_dc ? */ ++/* #define cpu_has_pindexed_dcache ? */ ++ ++/* #define cpu_icache_snoops_remote_store ? */ ++ ++#define cpu_has_mips32r1 1 ++ ++#if !defined(CONFIG_ATHEROS_AR5312) ++# define cpu_has_mips32r2 1 ++#endif ++ ++#define cpu_has_mips64r1 0 ++#define cpu_has_mips64r2 0 ++ ++#define cpu_has_dsp 0 ++#define cpu_has_mipsmt 0 ++ ++/* #define cpu_has_nofpuex ? */ ++#define cpu_has_64bits 0 ++#define cpu_has_64bit_zero_reg 0 ++#define cpu_has_64bit_gp_regs 0 ++#define cpu_has_64bit_addresses 0 ++ ++/* #define cpu_has_inclusive_pcaches ? */ ++ ++/* #define cpu_dcache_line_size() ? */ ++/* #define cpu_icache_line_size() ? */ ++ ++#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h 2011-05-15 21:41:19.000000000 +0200 +@@ -0,0 +1,76 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2006 Ralf Baechle ++ * Copyright (C) 2007 Felix Fietkau ++ * ++ */ ++#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H ++#define __ASM_MACH_GENERIC_DMA_COHERENCE_H ++ ++#define PCI_DMA_OFFSET 0x20000000 ++ ++#include ++ ++static inline dma_addr_t ar231x_dev_offset(struct device *dev) ++{ ++#ifdef CONFIG_PCI ++ extern struct bus_type pci_bus_type; ++ ++ if (dev && dev->bus == &pci_bus_type) ++ return PCI_DMA_OFFSET; ++ else ++#endif ++ return 0; ++} ++ ++static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) ++{ ++ return virt_to_phys(addr) + ar231x_dev_offset(dev); ++} ++ ++static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) ++{ ++ return page_to_phys(page) + ar231x_dev_offset(dev); ++} ++ ++static inline unsigned long plat_dma_addr_to_phys(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return dma_addr - ar231x_dev_offset(dev); ++} ++ ++static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, ++ size_t size, enum dma_data_direction direction) ++{ ++} ++ ++static inline int plat_dma_supported(struct device *dev, u64 mask) ++{ ++ return 1; ++} ++ ++static inline void plat_extra_sync_for_device(struct device *dev) ++{ ++ return; ++} ++ ++static inline int plat_dma_mapping_error(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return 0; ++} ++ ++static inline int plat_device_is_coherent(struct device *dev) ++{ ++#ifdef CONFIG_DMA_COHERENT ++ return 1; ++#endif ++#ifdef CONFIG_DMA_NONCOHERENT ++ return 0; ++#endif ++} ++ ++#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,84 @@ ++#ifndef _ATHEROS_GPIO_H_ ++#define _ATHEROS_GPIO_H_ ++ ++#include ++ ++struct ar231x_gpiodev { ++ u32 valid_mask; ++ u32 (*get_output)(void); ++ u32 (*set_output)(u32 mask, u32 val); ++ u32 (*get)(void); ++ u32 (*set)(u32 mask, u32 val); ++}; ++ ++extern const struct ar231x_gpiodev *ar231x_gpiodev; ++ ++/* ++ * Wrappers for the generic GPIO layer ++ */ ++ ++static inline int gpio_direction_input(unsigned gpio) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return -ENXIO; ++ ++ ar231x_gpiodev->set_output(mask, 0); ++ return 0; ++} ++ ++static inline void gpio_set_value(unsigned gpio, int value) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return; ++ ++ ar231x_gpiodev->set(mask, (!!value) * mask); ++} ++ ++static inline int gpio_direction_output(unsigned gpio, int value) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return -ENXIO; ++ ++ ar231x_gpiodev->set_output(mask, mask); ++ ar231x_gpiodev->set(mask, (!!value) * mask); ++ return 0; ++} ++ ++/* Reads the gpio pin. Unchecked function */ ++static inline int gpio_get_value(unsigned gpio) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return 0; ++ ++ return !!(ar231x_gpiodev->get() & mask); ++} ++ ++static inline int gpio_request(unsigned gpio, const char *label) { ++ return 0; ++} ++ ++static inline void gpio_free(unsigned gpio) { ++} ++ ++/* Returns IRQ to attach for gpio. Unchecked function */ ++static inline int gpio_to_irq(unsigned gpio) { ++ return AR531X_GPIO_IRQ(gpio); ++} ++ ++/* Returns gpio for IRQ attached. Unchecked function */ ++static inline int irq_to_gpio(unsigned irq) { ++ return (irq - (AR531X_GPIO_IRQ(0))); ++} ++ ++static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) ++{ ++ return -ENOSYS; ++} ++ ++#include /* cansleep wrappers */ ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,6 @@ ++#ifndef __AR531X_RESET_H ++#define __AR531X_RESET_H ++ ++void ar531x_disable_reset_button(void); ++ ++#endif /* __AR531X_RESET_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,25 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Felix Fietkau ++ */ ++#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H ++#define __ASM_MIPS_MACH_ATHEROS_WAR_H ++ ++#define R4600_V1_INDEX_ICACHEOP_WAR 0 ++#define R4600_V1_HIT_CACHEOP_WAR 0 ++#define R4600_V2_HIT_CACHEOP_WAR 0 ++#define R5432_CP0_INTERRUPT_WAR 0 ++#define BCM1250_M3_WAR 0 ++#define SIBYTE_1956_WAR 0 ++#define MIPS4K_ICACHE_REFILL_WAR 0 ++#define MIPS_CACHE_SYNC_WAR 0 ++#define TX49XX_ICACHE_INDEX_INV_WAR 0 ++#define RM9000_CDEX_SMP_WAR 0 ++#define ICACHE_REFILLS_WORKAROUND_WAR 0 ++#define R10000_LLSC_WAR 0 ++#define MIPS34K_MISSED_ITLB_WAR 0 ++ ++#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c +--- linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c 2011-05-15 21:34:57.000000000 +0200 +@@ -168,20 +168,23 @@ + struct clock_event_device *cd; + unsigned int irq; + +- if (!cpu_has_counter || !mips_hpt_frequency) +- return -ENXIO; +- +- if (!c0_compare_int_usable()) +- return -ENXIO; +- + /* + * With vectored interrupts things are getting platform specific. + * get_c0_compare_int is a hook to allow a platform to return the + * interrupt number of it's liking. + */ + irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; +- if (get_c0_compare_int) ++ if (get_c0_compare_int) { + irq = get_c0_compare_int(); ++ if ((irq >= MIPS_CPU_IRQ_BASE) && (irq < MIPS_CPU_IRQ_BASE + 8)) ++ cp0_compare_irq = irq - MIPS_CPU_IRQ_BASE; ++ } ++ ++ if (!cpu_has_counter || !mips_hpt_frequency) ++ return -ENXIO; ++ ++ if (!c0_compare_int_usable()) ++ return -ENXIO; + + cd = &per_cpu(mips_clockevent_device, cpu); + +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig linux-2.6.39-rc7/drivers/mtd/devices/Kconfig +--- linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/mtd/devices/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -112,6 +112,10 @@ + Set up your spi devices with the right board-specific platform data, + if you want to specify device partitioning. + ++config MTD_AR2315 ++ tristate "Atheros AR2315+ SPI Flash support" ++ depends on ATHEROS_AR2315 ++ + config MTD_SLRAM + tristate "Uncached system RAM" + help +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile linux-2.6.39-rc7/drivers/mtd/devices/Makefile +--- linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/mtd/devices/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -17,3 +17,4 @@ + obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o + obj-$(CONFIG_MTD_M25P80) += m25p80.o + obj-$(CONFIG_MTD_SST25L) += sst25l.o ++obj-$(CONFIG_MTD_AR2315) += ar2315.o +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c +--- linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,517 @@ ++ ++/* ++ * MTD driver for the SPI Flash Memory support on Atheros AR2315 ++ * ++ * Copyright (c) 2005-2006 Atheros Communications Inc. ++ * Copyright (C) 2006-2007 FON Technology, SL. ++ * Copyright (C) 2006-2007 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * This code is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++ ++#define SPIFLASH "spiflash: " ++#define busy_wait(_priv, _condition, _wait) do { \ ++ while (_condition) { \ ++ spin_unlock_bh(&_priv->lock); \ ++ if (_wait > 1) \ ++ msleep(_wait); \ ++ else if ((_wait == 1) && need_resched()) \ ++ schedule(); \ ++ else \ ++ udelay(1); \ ++ spin_lock_bh(&_priv->lock); \ ++ } \ ++} while (0) ++ ++enum { ++ FLASH_NONE, ++ FLASH_1MB, ++ FLASH_2MB, ++ FLASH_4MB, ++ FLASH_8MB, ++ FLASH_16MB, ++}; ++ ++/* Flash configuration table */ ++struct flashconfig { ++ u32 byte_cnt; ++ u32 sector_cnt; ++ u32 sector_size; ++}; ++ ++const struct flashconfig flashconfig_tbl[] = { ++ [FLASH_NONE] = { 0, 0, 0}, ++ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE}, ++ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE}, ++ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE}, ++ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE}, ++ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE} ++}; ++ ++/* Mapping of generic opcodes to STM serial flash opcodes */ ++enum { ++ SPI_WRITE_ENABLE, ++ SPI_WRITE_DISABLE, ++ SPI_RD_STATUS, ++ SPI_WR_STATUS, ++ SPI_RD_DATA, ++ SPI_FAST_RD_DATA, ++ SPI_PAGE_PROGRAM, ++ SPI_SECTOR_ERASE, ++ SPI_BULK_ERASE, ++ SPI_DEEP_PWRDOWN, ++ SPI_RD_SIG, ++}; ++ ++struct opcodes { ++ __u16 code; ++ __s8 tx_cnt; ++ __s8 rx_cnt; ++}; ++const struct opcodes stm_opcodes[] = { ++ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0}, ++ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0}, ++ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1}, ++ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0}, ++ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4}, ++ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0}, ++ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0}, ++ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0}, ++ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0}, ++ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0}, ++ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1}, ++}; ++ ++/* Driver private data structure */ ++struct spiflash_priv { ++ struct mtd_info mtd; ++ void *readaddr; /* memory mapped data for read */ ++ void *mmraddr; /* memory mapped register space */ ++ wait_queue_head_t wq; ++ spinlock_t lock; ++ int state; ++}; ++ ++#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd) ++ ++enum { ++ FL_READY, ++ FL_READING, ++ FL_ERASING, ++ FL_WRITING ++}; ++ ++/***************************************************************************************************/ ++ ++static u32 ++spiflash_read_reg(struct spiflash_priv *priv, int reg) ++{ ++ return ar231x_read_reg((u32) priv->mmraddr + reg); ++} ++ ++static void ++spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data) ++{ ++ ar231x_write_reg((u32) priv->mmraddr + reg, data); ++} ++ ++static u32 ++spiflash_wait_busy(struct spiflash_priv *priv) ++{ ++ u32 reg; ++ ++ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) & ++ SPI_CTL_BUSY, 0); ++ return reg; ++} ++ ++static u32 ++spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr) ++{ ++ const struct opcodes *op; ++ u32 reg, mask; ++ ++ op = &stm_opcodes[opcode]; ++ reg = spiflash_wait_busy(priv); ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, ++ ((u32) op->code) | (addr << 8)); ++ ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4); ++ ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ spiflash_wait_busy(priv); ++ ++ if (!op->rx_cnt) ++ return 0; ++ ++ reg = spiflash_read_reg(priv, SPI_FLASH_DATA); ++ ++ switch (op->rx_cnt) { ++ case 1: ++ mask = 0x000000ff; ++ break; ++ case 2: ++ mask = 0x0000ffff; ++ break; ++ case 3: ++ mask = 0x00ffffff; ++ break; ++ default: ++ mask = 0xffffffff; ++ break; ++ } ++ reg &= mask; ++ ++ return reg; ++} ++ ++ ++/* ++ * Probe SPI flash device ++ * Function returns 0 for failure. ++ * and flashconfig_tbl array index for success. ++ */ ++static int ++spiflash_probe_chip (struct spiflash_priv *priv) ++{ ++ u32 sig; ++ int flash_size; ++ ++ /* Read the signature on the flash device */ ++ spin_lock_bh(&priv->lock); ++ sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0); ++ spin_unlock_bh(&priv->lock); ++ ++ switch (sig) { ++ case STM_8MBIT_SIGNATURE: ++ flash_size = FLASH_1MB; ++ break; ++ case STM_16MBIT_SIGNATURE: ++ flash_size = FLASH_2MB; ++ break; ++ case STM_32MBIT_SIGNATURE: ++ flash_size = FLASH_4MB; ++ break; ++ case STM_64MBIT_SIGNATURE: ++ flash_size = FLASH_8MB; ++ break; ++ case STM_128MBIT_SIGNATURE: ++ flash_size = FLASH_16MB; ++ break; ++ default: ++ printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n"); ++ return 0; ++ } ++ ++ return flash_size; ++} ++ ++ ++/* wait until the flash chip is ready and grab a lock */ ++static int spiflash_wait_ready(struct spiflash_priv *priv, int state) ++{ ++ DECLARE_WAITQUEUE(wait, current); ++ ++retry: ++ spin_lock_bh(&priv->lock); ++ if (priv->state != FL_READY) { ++ set_current_state(TASK_UNINTERRUPTIBLE); ++ add_wait_queue(&priv->wq, &wait); ++ spin_unlock_bh(&priv->lock); ++ schedule(); ++ remove_wait_queue(&priv->wq, &wait); ++ ++ if(signal_pending(current)) ++ return 0; ++ ++ goto retry; ++ } ++ priv->state = state; ++ ++ return 1; ++} ++ ++static inline void spiflash_done(struct spiflash_priv *priv) ++{ ++ priv->state = FL_READY; ++ spin_unlock_bh(&priv->lock); ++ wake_up(&priv->wq); ++} ++ ++static void ++spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout) ++{ ++ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) & ++ SPI_STATUS_WIP, timeout); ++ spiflash_done(priv); ++} ++ ++ ++ ++static int ++spiflash_erase (struct mtd_info *mtd, struct erase_info *instr) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ const struct opcodes *op; ++ u32 temp, reg; ++ ++ if (instr->addr + instr->len > mtd->size) ++ return -EINVAL; ++ ++ if (!spiflash_wait_ready(priv, FL_ERASING)) ++ return -EINTR; ++ ++ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); ++ reg = spiflash_wait_busy(priv); ++ ++ op = &stm_opcodes[SPI_SECTOR_ERASE]; ++ temp = ((u32)instr->addr << 8) | (u32)(op->code); ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp); ++ ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= op->tx_cnt | SPI_CTL_START; ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ ++ spiflash_wait_complete(priv, 20); ++ ++ instr->state = MTD_ERASE_DONE; ++ mtd_erase_callback(instr); ++ ++ return 0; ++} ++ ++static int ++spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ u8 *read_addr; ++ ++ if (!len) ++ return 0; ++ ++ if (from + len > mtd->size) ++ return -EINVAL; ++ ++ *retlen = len; ++ ++ if (!spiflash_wait_ready(priv, FL_READING)) ++ return -EINTR; ++ ++ read_addr = (u8 *)(priv->readaddr + from); ++ memcpy_fromio(buf, read_addr, len); ++ spiflash_done(priv); ++ ++ return 0; ++} ++ ++static int ++spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ u32 opcode, bytes_left; ++ ++ *retlen = 0; ++ ++ if (!len) ++ return 0; ++ ++ if (to + len > mtd->size) ++ return -EINVAL; ++ ++ bytes_left = len; ++ ++ do { ++ u32 read_len, reg, page_offset, spi_data = 0; ++ ++ read_len = min(bytes_left, sizeof(u32)); ++ ++ /* 32-bit writes cannot span across a page boundary ++ * (256 bytes). This types of writes require two page ++ * program operations to handle it correctly. The STM part ++ * will write the overflow data to the beginning of the ++ * current page as opposed to the subsequent page. ++ */ ++ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len; ++ ++ if (page_offset > STM_PAGE_SIZE) ++ read_len -= (page_offset - STM_PAGE_SIZE); ++ ++ if (!spiflash_wait_ready(priv, FL_WRITING)) ++ return -EINTR; ++ ++ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); ++ spi_data = 0; ++ switch (read_len) { ++ case 4: ++ spi_data |= buf[3] << 24; ++ /* fall through */ ++ case 3: ++ spi_data |= buf[2] << 16; ++ /* fall through */ ++ case 2: ++ spi_data |= buf[1] << 8; ++ /* fall through */ ++ case 1: ++ spi_data |= buf[0] & 0xff; ++ break; ++ default: ++ break; ++ } ++ ++ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data); ++ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code | ++ (to & 0x00ffffff) << 8; ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode); ++ ++ reg = spiflash_read_reg(priv, SPI_FLASH_CTL); ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= (read_len + 4) | SPI_CTL_START; ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ ++ spiflash_wait_complete(priv, 1); ++ ++ bytes_left -= read_len; ++ to += read_len; ++ buf += read_len; ++ ++ *retlen += read_len; ++ } while (bytes_left != 0); ++ ++ return 0; ++} ++ ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL }; ++#endif ++ ++ ++static int ++spiflash_probe(struct platform_device *pdev) ++{ ++ struct spiflash_priv *priv; ++ struct mtd_partition *parts; ++ struct mtd_info *mtd; ++ int index, num_parts; ++ int result = 0; ++ ++ priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL); ++ spin_lock_init(&priv->lock); ++ init_waitqueue_head(&priv->wq); ++ priv->state = FL_READY; ++ mtd = &priv->mtd; ++ ++ priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE); ++ if (!priv->mmraddr) { ++ printk(KERN_WARNING SPIFLASH "Failed to map flash device\n"); ++ goto error; ++ } ++ ++ index = spiflash_probe_chip(priv); ++ if (!index) { ++ printk (KERN_WARNING SPIFLASH "Found no serial flash device\n"); ++ goto error; ++ } ++ ++ priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt); ++ if (!priv->readaddr) { ++ printk (KERN_WARNING SPIFLASH "Failed to map flash device\n"); ++ goto error; ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ mtd->name = "spiflash"; ++ mtd->type = MTD_NORFLASH; ++ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE); ++ mtd->size = flashconfig_tbl[index].byte_cnt; ++ mtd->erasesize = flashconfig_tbl[index].sector_size; ++ mtd->writesize = 1; ++ mtd->numeraseregions = 0; ++ mtd->eraseregions = NULL; ++ mtd->erase = spiflash_erase; ++ mtd->read = spiflash_read; ++ mtd->write = spiflash_write; ++ mtd->owner = THIS_MODULE; ++ ++#ifdef CONFIG_MTD_PARTITIONS ++ /* parse redboot partitions */ ++ num_parts = parse_mtd_partitions(mtd, part_probe_types, &parts, 0); ++ if (!num_parts) ++ goto error; ++ ++ result = add_mtd_partitions(mtd, parts, num_parts); ++#endif ++ ++ return result; ++ ++error: ++ if (priv->mmraddr) ++ iounmap(priv->mmraddr); ++ kfree(priv); ++ return -ENXIO; ++} ++ ++static int ++spiflash_remove (struct platform_device *pdev) ++{ ++ struct spiflash_priv *priv = platform_get_drvdata(pdev); ++ struct mtd_info *mtd = &priv->mtd; ++ ++ del_mtd_partitions(mtd); ++ iounmap(priv->mmraddr); ++ iounmap(priv->readaddr); ++ kfree(priv); ++ ++ return 0; ++} ++ ++struct platform_driver spiflash_driver = { ++ .driver.name = "spiflash", ++ .probe = spiflash_probe, ++ .remove = spiflash_remove, ++}; ++ ++int __init ++spiflash_init (void) ++{ ++ return platform_driver_register(&spiflash_driver); ++} ++ ++void __exit ++spiflash_exit (void) ++{ ++ return platform_driver_unregister(&spiflash_driver); ++} ++ ++module_init (spiflash_init); ++module_exit (spiflash_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc"); ++MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC"); ++ +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/redboot.c linux-2.6.39-rc7/drivers/mtd/redboot.c +--- linux-2.6.39-rc7.orig/drivers/mtd/redboot.c 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/mtd/redboot.c 2011-05-15 21:34:57.000000000 +0200 +@@ -55,6 +55,22 @@ + return 1; + } + ++static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset) ++{ ++ struct mtd_erase_region_info *regions = mtd->eraseregions; ++ int i; ++ ++ for (i = 0; i < mtd->numeraseregions; i++) { ++ if (regions[i].offset + ++ regions[i].numblocks * regions[i].erasesize <= offset) ++ continue; ++ ++ return regions[i].erasesize; ++ } ++ ++ return mtd->erasesize; ++} ++ + static int parse_redboot_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + unsigned long fis_origin) +@@ -70,36 +86,38 @@ + int namelen = 0; + int nulllen = 0; + int numslots; ++ int first_slot; + unsigned long offset; + #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + static char nullstring[] = "unallocated"; + #endif + ++ buf = vmalloc(master->erasesize); ++ if (!buf) ++ return -ENOMEM; ++ ++ restart: + if ( directory < 0 ) { + offset = master->size + directory * master->erasesize; +- while (master->block_isbad && ++ while (master->block_isbad && + master->block_isbad(master, offset)) { + if (!offset) { + nogood: + printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); ++ vfree(buf); + return -EIO; + } + offset -= master->erasesize; + } + } else { + offset = directory * master->erasesize; +- while (master->block_isbad && ++ while (master->block_isbad && + master->block_isbad(master, offset)) { + offset += master->erasesize; + if (offset == master->size) + goto nogood; + } + } +- buf = vmalloc(master->erasesize); +- +- if (!buf) +- return -ENOMEM; +- + printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", + master->name, offset); + +@@ -171,13 +189,21 @@ + } + if (i == numslots) { + /* Didn't find it */ ++ if (offset + master->erasesize < master->size) { ++ /* not at the end of the flash yet, maybe next block :) */ ++ directory++; ++ goto restart; ++ } + printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", + master->name); + ret = 0; + goto out; + } + +- for (i = 0; i < numslots; i++) { ++ first_slot = (buf[i].flash_base & (master->erasesize - 1)) / ++ sizeof(struct fis_image_desc); ++ ++ for (i = first_slot; i < first_slot + numslots; i++) { + struct fis_list *new_fl, **prev; + + if (buf[i].name[0] == 0xff) { +diff -Nur linux-2.6.39-rc7.orig/drivers/net/Kconfig linux-2.6.39-rc7/drivers/net/Kconfig +--- linux-2.6.39-rc7.orig/drivers/net/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/net/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -251,6 +251,12 @@ + help + Select this if your platform comes with an external 93CX6 eeprom. + ++config AR231X_ETHERNET ++ tristate "AR231x Ethernet support" ++ depends on ATHEROS_AR231X ++ help ++ Support for the AR231x/531x ethernet controller ++ + config MACE + tristate "MACE (Power Mac ethernet) support" + depends on PPC_PMAC && PPC32 +diff -Nur linux-2.6.39-rc7.orig/drivers/net/Makefile linux-2.6.39-rc7/drivers/net/Makefile +--- linux-2.6.39-rc7.orig/drivers/net/Makefile 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/net/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -226,6 +226,7 @@ + obj-$(CONFIG_KORINA) += korina.o + obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o + obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o ++obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o + obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o + obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o + obj-$(CONFIG_DECLANCE) += declance.o +diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.c linux-2.6.39-rc7/drivers/net/ar231x.c +--- linux-2.6.39-rc7.orig/drivers/net/ar231x.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/net/ar231x.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,1293 @@ ++/* ++ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device. ++ * ++ * Copyright (C) 2004 by Sameer Dekate ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * Thanks to Atheros for providing hardware and documentation ++ * enabling me to write this driver. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * Additional credits: ++ * This code is taken from John Taylor's Sibyte driver and then ++ * modified for the AR2313. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define AR2313_MTU 1692 ++#define AR2313_PRIOS 1 ++#define AR2313_QUEUES (2*AR2313_PRIOS) ++#define AR2313_DESCR_ENTRIES 64 ++ ++ ++#ifndef min ++#define min(a,b) (((a)<(b))?(a):(b)) ++#endif ++ ++#ifndef SMP_CACHE_BYTES ++#define SMP_CACHE_BYTES L1_CACHE_BYTES ++#endif ++ ++#define AR2313_MBOX_SET_BIT 0x8 ++ ++#include "ar231x.h" ++ ++/* ++ * New interrupt handler strategy: ++ * ++ * An old interrupt handler worked using the traditional method of ++ * replacing an skbuff with a new one when a packet arrives. However ++ * the rx rings do not need to contain a static number of buffer ++ * descriptors, thus it makes sense to move the memory allocation out ++ * of the main interrupt handler and do it in a bottom half handler ++ * and only allocate new buffers when the number of buffers in the ++ * ring is below a certain threshold. In order to avoid starving the ++ * NIC under heavy load it is however necessary to force allocation ++ * when hitting a minimum threshold. The strategy for alloction is as ++ * follows: ++ * ++ * RX_LOW_BUF_THRES - allocate buffers in the bottom half ++ * RX_PANIC_LOW_THRES - we are very low on buffers, allocate ++ * the buffers in the interrupt handler ++ * RX_RING_THRES - maximum number of buffers in the rx ring ++ * ++ * One advantagous side effect of this allocation approach is that the ++ * entire rx processing can be done without holding any spin lock ++ * since the rx rings and registers are totally independent of the tx ++ * ring and its registers. This of course includes the kmalloc's of ++ * new skb's. Thus start_xmit can run in parallel with rx processing ++ * and the memory allocation on SMP systems. ++ * ++ * Note that running the skb reallocation in a bottom half opens up ++ * another can of races which needs to be handled properly. In ++ * particular it can happen that the interrupt handler tries to run ++ * the reallocation while the bottom half is either running on another ++ * CPU or was interrupted on the same CPU. To get around this the ++ * driver uses bitops to prevent the reallocation routines from being ++ * reentered. ++ * ++ * TX handling can also be done without holding any spin lock, wheee ++ * this is fun! since tx_csm is only written to by the interrupt ++ * handler. ++ */ ++ ++/* ++ * Threshold values for RX buffer allocation - the low water marks for ++ * when to start refilling the rings are set to 75% of the ring ++ * sizes. It seems to make sense to refill the rings entirely from the ++ * intrrupt handler once it gets below the panic threshold, that way ++ * we don't risk that the refilling is moved to another CPU when the ++ * one running the interrupt handler just got the slab code hot in its ++ * cache. ++ */ ++#define RX_RING_SIZE AR2313_DESCR_ENTRIES ++#define RX_PANIC_THRES (RX_RING_SIZE/4) ++#define RX_LOW_THRES ((3*RX_RING_SIZE)/4) ++#define CRC_LEN 4 ++#define RX_OFFSET 2 ++ ++#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) ++#define VLAN_HDR 4 ++#else ++#define VLAN_HDR 0 ++#endif ++ ++#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET) ++ ++#ifdef MODULE ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Sameer Dekate , Imre Kaloz , Felix Fietkau "); ++MODULE_DESCRIPTION("AR231x Ethernet driver"); ++#endif ++ ++#define virt_to_phys(x) ((u32)(x) & 0x1fffffff) ++ ++// prototypes ++static void ar231x_halt(struct net_device *dev); ++static void rx_tasklet_func(unsigned long data); ++static void rx_tasklet_cleanup(struct net_device *dev); ++static void ar231x_multicast_list(struct net_device *dev); ++static void ar231x_tx_timeout(struct net_device *dev); ++ ++static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum); ++static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value); ++static int ar231x_mdiobus_reset(struct mii_bus *bus); ++static int ar231x_mdiobus_probe (struct net_device *dev); ++static void ar231x_adjust_link(struct net_device *dev); ++ ++#ifndef ERR ++#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) ++#endif ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++static void ++ar231x_netpoll(struct net_device *dev) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ ar231x_interrupt(dev->irq, dev); ++ local_irq_restore(flags); ++} ++#endif ++ ++static const struct net_device_ops ar231x_ops = { ++ .ndo_open = ar231x_open, ++ .ndo_stop = ar231x_close, ++ .ndo_start_xmit = ar231x_start_xmit, ++ .ndo_set_multicast_list = ar231x_multicast_list, ++ .ndo_do_ioctl = ar231x_ioctl, ++ .ndo_change_mtu = eth_change_mtu, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_set_mac_address = eth_mac_addr, ++ .ndo_tx_timeout = ar231x_tx_timeout, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = ar231x_netpoll, ++#endif ++}; ++ ++int __init ar231x_probe(struct platform_device *pdev) ++{ ++ struct net_device *dev; ++ struct ar231x_private *sp; ++ struct resource *res; ++ unsigned long ar_eth_base; ++ char buf[64]; ++ ++ dev = alloc_etherdev(sizeof(struct ar231x_private)); ++ ++ if (dev == NULL) { ++ printk(KERN_ERR ++ "ar231x: Unable to allocate net_device structure!\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(pdev, dev); ++ ++ sp = netdev_priv(dev); ++ sp->dev = dev; ++ sp->cfg = pdev->dev.platform_data; ++ ++ sprintf(buf, "eth%d_membase", pdev->id); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf); ++ if (!res) ++ return -ENODEV; ++ ++ sp->link = 0; ++ ar_eth_base = res->start; ++ ++ sprintf(buf, "eth%d_irq", pdev->id); ++ dev->irq = platform_get_irq_byname(pdev, buf); ++ ++ spin_lock_init(&sp->lock); ++ ++ dev->features |= NETIF_F_HIGHDMA; ++ dev->netdev_ops = &ar231x_ops; ++ ++ tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev); ++ tasklet_disable(&sp->rx_tasklet); ++ ++ sp->eth_regs = ++ ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs)); ++ if (!sp->eth_regs) { ++ printk("Can't remap eth registers\n"); ++ return (-ENXIO); ++ } ++ ++ /* ++ * When there's only one MAC, PHY regs are typically on ENET0, ++ * even though the MAC might be on ENET1. ++ * Needto remap PHY regs separately in this case ++ */ ++ if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs)) ++ sp->phy_regs = sp->eth_regs; ++ else { ++ sp->phy_regs = ++ ioremap_nocache(virt_to_phys(sp->cfg->phy_base), ++ sizeof(*sp->phy_regs)); ++ if (!sp->phy_regs) { ++ printk("Can't remap phy registers\n"); ++ return (-ENXIO); ++ } ++ } ++ ++ sp->dma_regs = ++ ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000), ++ sizeof(*sp->dma_regs)); ++ dev->base_addr = (unsigned int) sp->dma_regs; ++ if (!sp->dma_regs) { ++ printk("Can't remap DMA registers\n"); ++ return (-ENXIO); ++ } ++ ++ sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4); ++ if (!sp->int_regs) { ++ printk("Can't remap INTERRUPT registers\n"); ++ return (-ENXIO); ++ } ++ ++ strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1); ++ sp->name[sizeof(sp->name) - 1] = '\0'; ++ memcpy(dev->dev_addr, sp->cfg->macaddr, 6); ++ ++ if (ar231x_init(dev)) { ++ /* ++ * ar231x_init() calls ar231x_init_cleanup() on error. ++ */ ++ kfree(dev); ++ return -ENODEV; ++ } ++ ++ if (register_netdev(dev)) { ++ printk("%s: register_netdev failed\n", __func__); ++ return -1; ++ } ++ ++ printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n", ++ dev->name, sp->name, ++ dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], ++ dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq); ++ ++ sp->mii_bus = mdiobus_alloc(); ++ if (sp->mii_bus == NULL) ++ return -1; ++ ++ sp->mii_bus->priv = dev; ++ sp->mii_bus->read = ar231x_mdiobus_read; ++ sp->mii_bus->write = ar231x_mdiobus_write; ++ sp->mii_bus->reset = ar231x_mdiobus_reset; ++ sp->mii_bus->name = "ar231x_eth_mii"; ++ snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); ++ sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL); ++ *sp->mii_bus->irq = PHY_POLL; ++ ++ mdiobus_register(sp->mii_bus); ++ ++ if (ar231x_mdiobus_probe(dev) != 0) { ++ printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name); ++ rx_tasklet_cleanup(dev); ++ ar231x_init_cleanup(dev); ++ unregister_netdev(dev); ++ kfree(dev); ++ return -ENODEV; ++ } ++ ++ /* start link poll timer */ ++ ar231x_setup_timer(dev); ++ ++ return 0; ++} ++ ++ ++static void ar231x_multicast_list(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int filter; ++ ++ filter = sp->eth_regs->mac_control; ++ ++ if (dev->flags & IFF_PROMISC) ++ filter |= MAC_CONTROL_PR; ++ else ++ filter &= ~MAC_CONTROL_PR; ++ if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0)) ++ filter |= MAC_CONTROL_PM; ++ else ++ filter &= ~MAC_CONTROL_PM; ++ ++ sp->eth_regs->mac_control = filter; ++} ++ ++static void rx_tasklet_cleanup(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ /* ++ * Tasklet may be scheduled. Need to get it removed from the list ++ * since we're about to free the struct. ++ */ ++ ++ sp->unloading = 1; ++ tasklet_enable(&sp->rx_tasklet); ++ tasklet_kill(&sp->rx_tasklet); ++} ++ ++static int __devexit ar231x_remove(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ struct ar231x_private *sp = netdev_priv(dev); ++ rx_tasklet_cleanup(dev); ++ ar231x_init_cleanup(dev); ++ unregister_netdev(dev); ++ mdiobus_unregister(sp->mii_bus); ++ mdiobus_free(sp->mii_bus); ++ kfree(dev); ++ return 0; ++} ++ ++ ++/* ++ * Restart the AR2313 ethernet controller. ++ */ ++static int ar231x_restart(struct net_device *dev) ++{ ++ /* disable interrupts */ ++ disable_irq(dev->irq); ++ ++ /* stop mac */ ++ ar231x_halt(dev); ++ ++ /* initialize */ ++ ar231x_init(dev); ++ ++ /* enable interrupts */ ++ enable_irq(dev->irq); ++ ++ return 0; ++} ++ ++static struct platform_driver ar231x_driver = { ++ .driver.name = "ar231x-eth", ++ .probe = ar231x_probe, ++ .remove = __devexit_p(ar231x_remove), ++}; ++ ++int __init ar231x_module_init(void) ++{ ++ return platform_driver_register(&ar231x_driver); ++} ++ ++void __exit ar231x_module_cleanup(void) ++{ ++ platform_driver_unregister(&ar231x_driver); ++} ++ ++module_init(ar231x_module_init); ++module_exit(ar231x_module_cleanup); ++ ++ ++static void ar231x_free_descriptors(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ if (sp->rx_ring != NULL) { ++ kfree((void *) KSEG0ADDR(sp->rx_ring)); ++ sp->rx_ring = NULL; ++ sp->tx_ring = NULL; ++ } ++} ++ ++ ++static int ar231x_allocate_descriptors(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int size; ++ int j; ++ ar231x_descr_t *space; ++ ++ if (sp->rx_ring != NULL) { ++ printk("%s: already done.\n", __FUNCTION__); ++ return 0; ++ } ++ ++ size = ++ (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES)); ++ space = kmalloc(size, GFP_KERNEL); ++ if (space == NULL) ++ return 1; ++ ++ /* invalidate caches */ ++ dma_cache_inv((unsigned int) space, size); ++ ++ /* now convert pointer to KSEG1 */ ++ space = (ar231x_descr_t *) KSEG1ADDR(space); ++ ++ memset((void *) space, 0, size); ++ ++ sp->rx_ring = space; ++ space += AR2313_DESCR_ENTRIES; ++ ++ sp->tx_ring = space; ++ space += AR2313_DESCR_ENTRIES; ++ ++ /* Initialize the transmit Descriptors */ ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ ar231x_descr_t *td = &sp->tx_ring[j]; ++ td->status = 0; ++ td->devcs = DMA_TX1_CHAINED; ++ td->addr = 0; ++ td->descr = ++ virt_to_phys(&sp-> ++ tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]); ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * Generic cleanup handling data allocated during init. Used when the ++ * module is unloaded or if an error occurs during initialization ++ */ ++static void ar231x_init_cleanup(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ struct sk_buff *skb; ++ int j; ++ ++ ar231x_free_descriptors(dev); ++ ++ if (sp->eth_regs) ++ iounmap((void *) sp->eth_regs); ++ if (sp->dma_regs) ++ iounmap((void *) sp->dma_regs); ++ ++ if (sp->rx_skb) { ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ skb = sp->rx_skb[j]; ++ if (skb) { ++ sp->rx_skb[j] = NULL; ++ dev_kfree_skb(skb); ++ } ++ } ++ kfree(sp->rx_skb); ++ sp->rx_skb = NULL; ++ } ++ ++ if (sp->tx_skb) { ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ skb = sp->tx_skb[j]; ++ if (skb) { ++ sp->tx_skb[j] = NULL; ++ dev_kfree_skb(skb); ++ } ++ } ++ kfree(sp->tx_skb); ++ sp->tx_skb = NULL; ++ } ++} ++ ++static int ar231x_setup_timer(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ init_timer(&sp->link_timer); ++ ++ sp->link_timer.function = ar231x_link_timer_fn; ++ sp->link_timer.data = (int) dev; ++ sp->link_timer.expires = jiffies + HZ; ++ ++ add_timer(&sp->link_timer); ++ return 0; ++ ++} ++ ++static void ar231x_link_timer_fn(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *) data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ // see if the link status changed ++ // This was needed to make sure we set the PHY to the ++ // autonegotiated value of half or full duplex. ++ ar231x_check_link(dev); ++ ++ // Loop faster when we don't have link. ++ // This was needed to speed up the AP bootstrap time. ++ if (sp->link == 0) { ++ mod_timer(&sp->link_timer, jiffies + HZ / 2); ++ } else { ++ mod_timer(&sp->link_timer, jiffies + LINK_TIMER); ++ } ++} ++ ++static void ar231x_check_link(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ u16 phyData; ++ ++ phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR); ++ if (sp->phyData != phyData) { ++ if (phyData & BMSR_LSTATUS) { ++ /* link is present, ready link partner ability to deterine ++ duplexity */ ++ int duplex = 0; ++ u16 reg; ++ ++ sp->link = 1; ++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR); ++ if (reg & BMCR_ANENABLE) { ++ /* auto neg enabled */ ++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA); ++ duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0; ++ } else { ++ /* no auto neg, just read duplex config */ ++ duplex = (reg & BMCR_FULLDPLX) ? 1 : 0; ++ } ++ ++ printk(KERN_INFO "%s: Configuring MAC for %s duplex\n", ++ dev->name, (duplex) ? "full" : "half"); ++ ++ if (duplex) { ++ /* full duplex */ ++ sp->eth_regs->mac_control = ++ ((sp->eth_regs-> ++ mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO); ++ } else { ++ /* half duplex */ ++ sp->eth_regs->mac_control = ++ ((sp->eth_regs-> ++ mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F); ++ } ++ } else { ++ /* no link */ ++ sp->link = 0; ++ } ++ sp->phyData = phyData; ++ } ++} ++ ++static int ar231x_reset_reg(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int ethsal, ethsah; ++ unsigned int flags; ++ ++ *sp->int_regs |= sp->cfg->reset_mac; ++ mdelay(10); ++ *sp->int_regs &= ~sp->cfg->reset_mac; ++ mdelay(10); ++ *sp->int_regs |= sp->cfg->reset_phy; ++ mdelay(10); ++ *sp->int_regs &= ~sp->cfg->reset_phy; ++ mdelay(10); ++ ++ sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR); ++ mdelay(10); ++ sp->dma_regs->bus_mode = ++ ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE); ++ ++ /* enable interrupts */ ++ sp->dma_regs->intr_ena = (DMA_STATUS_AIS | ++ DMA_STATUS_NIS | ++ DMA_STATUS_RI | ++ DMA_STATUS_TI | DMA_STATUS_FBE); ++ sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring); ++ sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring); ++ sp->dma_regs->control = ++ (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF); ++ ++ sp->eth_regs->flow_control = (FLOW_CONTROL_FCE); ++ sp->eth_regs->vlan_tag = (0x8100); ++ ++ /* Enable Ethernet Interface */ ++ flags = (MAC_CONTROL_TE | /* transmit enable */ ++ MAC_CONTROL_PM | /* pass mcast */ ++ MAC_CONTROL_F | /* full duplex */ ++ MAC_CONTROL_HBD); /* heart beat disabled */ ++ ++ if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ ++ flags |= MAC_CONTROL_PR; ++ } ++ sp->eth_regs->mac_control = flags; ++ ++ /* Set all Ethernet station address registers to their initial values */ ++ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); ++ ++ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | ++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | ++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); ++ ++ sp->eth_regs->mac_addr[0] = ethsah; ++ sp->eth_regs->mac_addr[1] = ethsal; ++ ++ mdelay(10); ++ ++ return (0); ++} ++ ++ ++static int ar231x_init(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int ecode = 0; ++ ++ /* ++ * Allocate descriptors ++ */ ++ if (ar231x_allocate_descriptors(dev)) { ++ printk("%s: %s: ar231x_allocate_descriptors failed\n", ++ dev->name, __FUNCTION__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ ++ /* ++ * Get the memory for the skb rings. ++ */ ++ if (sp->rx_skb == NULL) { ++ sp->rx_skb = ++ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, ++ GFP_KERNEL); ++ if (!(sp->rx_skb)) { ++ printk("%s: %s: rx_skb kmalloc failed\n", ++ dev->name, __FUNCTION__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ } ++ memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); ++ ++ if (sp->tx_skb == NULL) { ++ sp->tx_skb = ++ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, ++ GFP_KERNEL); ++ if (!(sp->tx_skb)) { ++ printk("%s: %s: tx_skb kmalloc failed\n", ++ dev->name, __FUNCTION__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ } ++ memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); ++ ++ /* ++ * Set tx_csm before we start receiving interrupts, otherwise ++ * the interrupt handler might think it is supposed to process ++ * tx ints before we are up and running, which may cause a null ++ * pointer access in the int handler. ++ */ ++ sp->rx_skbprd = 0; ++ sp->cur_rx = 0; ++ sp->tx_prd = 0; ++ sp->tx_csm = 0; ++ ++ /* ++ * Zero the stats before starting the interface ++ */ ++ memset(&dev->stats, 0, sizeof(dev->stats)); ++ ++ /* ++ * We load the ring here as there seem to be no way to tell the ++ * firmware to wipe the ring without re-initializing it. ++ */ ++ ar231x_load_rx_ring(dev, RX_RING_SIZE); ++ ++ /* ++ * Init hardware ++ */ ++ ar231x_reset_reg(dev); ++ ++ /* ++ * Get the IRQ ++ */ ++ ecode = ++ request_irq(dev->irq, &ar231x_interrupt, ++ IRQF_DISABLED | IRQF_SAMPLE_RANDOM, ++ dev->name, dev); ++ if (ecode) { ++ printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n", ++ dev->name, __FUNCTION__, dev->irq); ++ goto init_error; ++ } ++ ++ ++ tasklet_enable(&sp->rx_tasklet); ++ ++ return 0; ++ ++ init_error: ++ ar231x_init_cleanup(dev); ++ return ecode; ++} ++ ++/* ++ * Load the rx ring. ++ * ++ * Loading rings is safe without holding the spin lock since this is ++ * done only before the device is enabled, thus no interrupts are ++ * generated and by the interrupt handler/tasklet handler. ++ */ ++static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs) ++{ ++ ++ struct ar231x_private *sp = netdev_priv(dev); ++ short i, idx; ++ ++ idx = sp->rx_skbprd; ++ ++ for (i = 0; i < nr_bufs; i++) { ++ struct sk_buff *skb; ++ ar231x_descr_t *rd; ++ ++ if (sp->rx_skb[idx]) ++ break; ++ ++ skb = netdev_alloc_skb(dev, AR2313_BUFSIZE); ++ if (!skb) { ++ printk("\n\n\n\n %s: No memory in system\n\n\n\n", ++ __FUNCTION__); ++ break; ++ } ++ ++ /* ++ * Make sure IP header starts on a fresh cache line. ++ */ ++ skb->dev = dev; ++ skb_reserve(skb, RX_OFFSET); ++ sp->rx_skb[idx] = skb; ++ ++ rd = (ar231x_descr_t *) & sp->rx_ring[idx]; ++ ++ /* initialize dma descriptor */ ++ rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | ++ DMA_RX1_CHAINED); ++ rd->addr = virt_to_phys(skb->data); ++ rd->descr = ++ virt_to_phys(&sp-> ++ rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]); ++ rd->status = DMA_RX_OWN; ++ ++ idx = DSC_NEXT(idx); ++ } ++ ++ if (i) ++ sp->rx_skbprd = idx; ++ ++ return; ++} ++ ++#define AR2313_MAX_PKTS_PER_CALL 64 ++ ++static int ar231x_rx_int(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ struct sk_buff *skb, *skb_new; ++ ar231x_descr_t *rxdesc; ++ unsigned int status; ++ u32 idx; ++ int pkts = 0; ++ int rval; ++ ++ idx = sp->cur_rx; ++ ++ /* process at most the entire ring and then wait for another interrupt ++ */ ++ while (1) { ++ ++ rxdesc = &sp->rx_ring[idx]; ++ status = rxdesc->status; ++ if (status & DMA_RX_OWN) { ++ /* SiByte owns descriptor or descr not yet filled in */ ++ rval = 0; ++ break; ++ } ++ ++ if (++pkts > AR2313_MAX_PKTS_PER_CALL) { ++ rval = 1; ++ break; ++ } ++ ++ if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) { ++ dev->stats.rx_errors++; ++ dev->stats.rx_dropped++; ++ ++ /* add statistics counters */ ++ if (status & DMA_RX_ERR_CRC) ++ dev->stats.rx_crc_errors++; ++ if (status & DMA_RX_ERR_COL) ++ dev->stats.rx_over_errors++; ++ if (status & DMA_RX_ERR_LENGTH) ++ dev->stats.rx_length_errors++; ++ if (status & DMA_RX_ERR_RUNT) ++ dev->stats.rx_over_errors++; ++ if (status & DMA_RX_ERR_DESC) ++ dev->stats.rx_over_errors++; ++ ++ } else { ++ /* alloc new buffer. */ ++ skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET); ++ if (skb_new != NULL) { ++ ++ skb = sp->rx_skb[idx]; ++ /* set skb */ ++ skb_put(skb, ++ ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN); ++ ++ dev->stats.rx_bytes += skb->len; ++ skb->protocol = eth_type_trans(skb, dev); ++ /* pass the packet to upper layers */ ++ netif_rx(skb); ++ ++ skb_new->dev = dev; ++ /* 16 bit align */ ++ skb_reserve(skb_new, RX_OFFSET); ++ /* reset descriptor's curr_addr */ ++ rxdesc->addr = virt_to_phys(skb_new->data); ++ ++ dev->stats.rx_packets++; ++ sp->rx_skb[idx] = skb_new; ++ } else { ++ dev->stats.rx_dropped++; ++ } ++ } ++ ++ rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | ++ DMA_RX1_CHAINED); ++ rxdesc->status = DMA_RX_OWN; ++ ++ idx = DSC_NEXT(idx); ++ } ++ ++ sp->cur_rx = idx; ++ ++ return rval; ++} ++ ++ ++static void ar231x_tx_int(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ u32 idx; ++ struct sk_buff *skb; ++ ar231x_descr_t *txdesc; ++ unsigned int status = 0; ++ ++ idx = sp->tx_csm; ++ ++ while (idx != sp->tx_prd) { ++ txdesc = &sp->tx_ring[idx]; ++ ++ if ((status = txdesc->status) & DMA_TX_OWN) { ++ /* ar231x dma still owns descr */ ++ break; ++ } ++ /* done with this descriptor */ ++ dma_unmap_single(NULL, txdesc->addr, ++ txdesc->devcs & DMA_TX1_BSIZE_MASK, ++ DMA_TO_DEVICE); ++ txdesc->status = 0; ++ ++ if (status & DMA_TX_ERROR) { ++ dev->stats.tx_errors++; ++ dev->stats.tx_dropped++; ++ if (status & DMA_TX_ERR_UNDER) ++ dev->stats.tx_fifo_errors++; ++ if (status & DMA_TX_ERR_HB) ++ dev->stats.tx_heartbeat_errors++; ++ if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK)) ++ dev->stats.tx_carrier_errors++; ++ if (status & (DMA_TX_ERR_LATE | ++ DMA_TX_ERR_COL | ++ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER)) ++ dev->stats.tx_aborted_errors++; ++ } else { ++ /* transmit OK */ ++ dev->stats.tx_packets++; ++ } ++ ++ skb = sp->tx_skb[idx]; ++ sp->tx_skb[idx] = NULL; ++ idx = DSC_NEXT(idx); ++ dev->stats.tx_bytes += skb->len; ++ dev_kfree_skb_irq(skb); ++ } ++ ++ sp->tx_csm = idx; ++ ++ return; ++} ++ ++ ++static void rx_tasklet_func(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *) data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ if (sp->unloading) { ++ return; ++ } ++ ++ if (ar231x_rx_int(dev)) { ++ tasklet_hi_schedule(&sp->rx_tasklet); ++ } else { ++ unsigned long flags; ++ spin_lock_irqsave(&sp->lock, flags); ++ sp->dma_regs->intr_ena |= DMA_STATUS_RI; ++ spin_unlock_irqrestore(&sp->lock, flags); ++ } ++} ++ ++static void rx_schedule(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ sp->dma_regs->intr_ena &= ~DMA_STATUS_RI; ++ ++ tasklet_hi_schedule(&sp->rx_tasklet); ++} ++ ++static irqreturn_t ar231x_interrupt(int irq, void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *) dev_id; ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int status, enabled; ++ ++ /* clear interrupt */ ++ /* ++ * Don't clear RI bit if currently disabled. ++ */ ++ status = sp->dma_regs->status; ++ enabled = sp->dma_regs->intr_ena; ++ sp->dma_regs->status = status & enabled; ++ ++ if (status & DMA_STATUS_NIS) { ++ /* normal status */ ++ /* ++ * Don't schedule rx processing if interrupt ++ * is already disabled. ++ */ ++ if (status & enabled & DMA_STATUS_RI) { ++ /* receive interrupt */ ++ rx_schedule(dev); ++ } ++ if (status & DMA_STATUS_TI) { ++ /* transmit interrupt */ ++ ar231x_tx_int(dev); ++ } ++ } ++ ++ /* abnormal status */ ++ if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) { ++ ar231x_restart(dev); ++ } ++ return IRQ_HANDLED; ++} ++ ++ ++static int ar231x_open(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int ethsal, ethsah; ++ ++ /* reset the hardware, in case the MAC address changed */ ++ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); ++ ++ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | ++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | ++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); ++ ++ sp->eth_regs->mac_addr[0] = ethsah; ++ sp->eth_regs->mac_addr[1] = ethsal; ++ ++ mdelay(10); ++ ++ dev->mtu = 1500; ++ netif_start_queue(dev); ++ ++ sp->eth_regs->mac_control |= MAC_CONTROL_RE; ++ ++ return 0; ++} ++ ++static void ar231x_tx_timeout(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sp->lock, flags); ++ ar231x_restart(dev); ++ spin_unlock_irqrestore(&sp->lock, flags); ++} ++ ++static void ar231x_halt(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int j; ++ ++ tasklet_disable(&sp->rx_tasklet); ++ ++ /* kill the MAC */ ++ sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */ ++ MAC_CONTROL_TE); /* disable Transmits */ ++ /* stop dma */ ++ sp->dma_regs->control = 0; ++ sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR; ++ ++ /* place phy and MAC in reset */ ++ *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy); ++ ++ /* free buffers on tx ring */ ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ struct sk_buff *skb; ++ ar231x_descr_t *txdesc; ++ ++ txdesc = &sp->tx_ring[j]; ++ txdesc->descr = 0; ++ ++ skb = sp->tx_skb[j]; ++ if (skb) { ++ dev_kfree_skb(skb); ++ sp->tx_skb[j] = NULL; ++ } ++ } ++} ++ ++/* ++ * close should do nothing. Here's why. It's called when ++ * 'ifconfig bond0 down' is run. If it calls free_irq then ++ * the irq is gone forever ! When bond0 is made 'up' again, ++ * the ar231x_open () does not call request_irq (). Worse, ++ * the call to ar231x_halt() generates a WDOG reset due to ++ * the write to 'sp->int_regs' and the box reboots. ++ * Commenting this out is good since it allows the ++ * system to resume when bond0 is made up again. ++ */ ++static int ar231x_close(struct net_device *dev) ++{ ++#if 0 ++ /* ++ * Disable interrupts ++ */ ++ disable_irq(dev->irq); ++ ++ /* ++ * Without (or before) releasing irq and stopping hardware, this ++ * is an absolute non-sense, by the way. It will be reset instantly ++ * by the first irq. ++ */ ++ netif_stop_queue(dev); ++ ++ /* stop the MAC and DMA engines */ ++ ar231x_halt(dev); ++ ++ /* release the interrupt */ ++ free_irq(dev->irq, dev); ++ ++#endif ++ return 0; ++} ++ ++static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ar231x_descr_t *td; ++ u32 idx; ++ ++ idx = sp->tx_prd; ++ td = &sp->tx_ring[idx]; ++ ++ if (td->status & DMA_TX_OWN) { ++ /* free skbuf and lie to the caller that we sent it out */ ++ dev->stats.tx_dropped++; ++ dev_kfree_skb(skb); ++ ++ /* restart transmitter in case locked */ ++ sp->dma_regs->xmt_poll = 0; ++ return 0; ++ } ++ ++ /* Setup the transmit descriptor. */ ++ td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) | ++ (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED)); ++ td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); ++ td->status = DMA_TX_OWN; ++ ++ /* kick transmitter last */ ++ sp->dma_regs->xmt_poll = 0; ++ ++ sp->tx_skb[idx] = skb; ++ idx = DSC_NEXT(idx); ++ sp->tx_prd = idx; ++ ++ return 0; ++} ++ ++static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ++{ ++ struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ int ret; ++ ++ switch (cmd) { ++ ++ case SIOCETHTOOL: ++ spin_lock_irq(&sp->lock); ++ ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data); ++ spin_unlock_irq(&sp->lock); ++ return ret; ++ ++ case SIOCSIFHWADDR: ++ if (copy_from_user ++ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) ++ return -EFAULT; ++ return 0; ++ ++ case SIOCGIFHWADDR: ++ if (copy_to_user ++ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) ++ return -EFAULT; ++ return 0; ++ ++ case SIOCGMIIPHY: ++ case SIOCGMIIREG: ++ case SIOCSMIIREG: ++ return phy_mii_ioctl(sp->phy_dev, data, cmd); ++ ++ default: ++ break; ++ } ++ ++ return -EOPNOTSUPP; ++} ++ ++static void ar231x_adjust_link(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int mc; ++ ++ if (!sp->phy_dev->link) ++ return; ++ ++ if (sp->phy_dev->duplex != sp->oldduplex) { ++ mc = readl(&sp->eth_regs->mac_control); ++ mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO); ++ if (sp->phy_dev->duplex) ++ mc |= MAC_CONTROL_F; ++ else ++ mc |= MAC_CONTROL_DRO; ++ writel(mc, &sp->eth_regs->mac_control); ++ sp->oldduplex = sp->phy_dev->duplex; ++ } ++} ++ ++#define MII_ADDR(phy, reg) \ ++ ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT)) ++ ++static int ++ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) ++{ ++ struct net_device *const dev = bus->priv; ++ struct ar231x_private *sp = netdev_priv(dev); ++ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; ++ ++ ethernet->mii_addr = MII_ADDR(phy_addr, regnum); ++ while (ethernet->mii_addr & MII_ADDR_BUSY); ++ return (ethernet->mii_data >> MII_DATA_SHIFT); ++} ++ ++static int ++ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, ++ u16 value) ++{ ++ struct net_device *const dev = bus->priv; ++ struct ar231x_private *sp = netdev_priv(dev); ++ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; ++ ++ while (ethernet->mii_addr & MII_ADDR_BUSY); ++ ethernet->mii_data = value << MII_DATA_SHIFT; ++ ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE; ++ ++ return 0; ++} ++ ++static int ar231x_mdiobus_reset(struct mii_bus *bus) ++{ ++ struct net_device *const dev = bus->priv; ++ ++ ar231x_reset_reg(dev); ++ ++ return 0; ++} ++ ++static int ar231x_mdiobus_probe (struct net_device *dev) ++{ ++ struct ar231x_private *const sp = netdev_priv(dev); ++ struct phy_device *phydev = NULL; ++ int phy_addr; ++ ++ /* find the first (lowest address) PHY on the current MAC's MII bus */ ++ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) ++ if (sp->mii_bus->phy_map[phy_addr]) { ++ phydev = sp->mii_bus->phy_map[phy_addr]; ++ sp->phy = phy_addr; ++ break; /* break out with first one found */ ++ } ++ ++ if (!phydev) { ++ printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name); ++ return -1; ++ } ++ ++ /* now we are supposed to have a proper phydev, to attach to... */ ++ BUG_ON(!phydev); ++ BUG_ON(phydev->attached_dev); ++ ++ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0, ++ PHY_INTERFACE_MODE_MII); ++ ++ if (IS_ERR(phydev)) { ++ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); ++ return PTR_ERR(phydev); ++ } ++ ++ /* mask with MAC supported features */ ++ phydev->supported &= (SUPPORTED_10baseT_Half ++ | SUPPORTED_10baseT_Full ++ | SUPPORTED_100baseT_Half ++ | SUPPORTED_100baseT_Full ++ | SUPPORTED_Autoneg ++ /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ ++ | SUPPORTED_MII ++ | SUPPORTED_TP); ++ ++ phydev->advertising = phydev->supported; ++ ++ sp->oldduplex = -1; ++ sp->phy_dev = phydev; ++ ++ printk(KERN_INFO "%s: attached PHY driver [%s] " ++ "(mii_bus:phy_addr=%s)\n", ++ dev->name, phydev->drv->name, dev_name(&phydev->dev)); ++ ++ return 0; ++} ++ +diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.h linux-2.6.39-rc7/drivers/net/ar231x.h +--- linux-2.6.39-rc7.orig/drivers/net/ar231x.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/net/ar231x.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,302 @@ ++/* ++ * ar231x.h: Linux driver for the Atheros AR231x Ethernet device. ++ * ++ * Copyright (C) 2004 by Sameer Dekate ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * Thanks to Atheros for providing hardware and documentation ++ * enabling me to write this driver. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef _AR2313_H_ ++#define _AR2313_H_ ++ ++#include ++#include ++#include ++#include ++ ++/* ++ * probe link timer - 5 secs ++ */ ++#define LINK_TIMER (5*HZ) ++ ++#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0) ++#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0) ++#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0) ++ ++#define AR2313_TX_TIMEOUT (HZ/4) ++ ++/* ++ * Rings ++ */ ++#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc)) ++#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1)) ++ ++#define AR2313_MBGET 2 ++#define AR2313_MBSET 3 ++#define AR2313_PCI_RECONFIG 4 ++#define AR2313_PCI_DUMP 5 ++#define AR2313_TEST_PANIC 6 ++#define AR2313_TEST_NULLPTR 7 ++#define AR2313_READ_DATA 8 ++#define AR2313_WRITE_DATA 9 ++#define AR2313_GET_VERSION 10 ++#define AR2313_TEST_HANG 11 ++#define AR2313_SYNC 12 ++ ++#define DMA_RX_ERR_CRC BIT(1) ++#define DMA_RX_ERR_DRIB BIT(2) ++#define DMA_RX_ERR_MII BIT(3) ++#define DMA_RX_EV2 BIT(5) ++#define DMA_RX_ERR_COL BIT(6) ++#define DMA_RX_LONG BIT(7) ++#define DMA_RX_LS BIT(8) /* last descriptor */ ++#define DMA_RX_FS BIT(9) /* first descriptor */ ++#define DMA_RX_MF BIT(10) /* multicast frame */ ++#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */ ++#define DMA_RX_ERR_LENGTH BIT(12) /* length error */ ++#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */ ++#define DMA_RX_ERROR BIT(15) /* error summary */ ++#define DMA_RX_LEN_MASK 0x3fff0000 ++#define DMA_RX_LEN_SHIFT 16 ++#define DMA_RX_FILT BIT(30) ++#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */ ++ ++#define DMA_RX1_BSIZE_MASK 0x000007ff ++#define DMA_RX1_BSIZE_SHIFT 0 ++#define DMA_RX1_CHAINED BIT(24) ++#define DMA_RX1_RER BIT(25) ++ ++#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */ ++#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */ ++#define DMA_TX_COL_MASK 0x78 ++#define DMA_TX_COL_SHIFT 3 ++#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */ ++#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */ ++#define DMA_TX_ERR_LATE BIT(9) /* late collision */ ++#define DMA_TX_ERR_LINK BIT(10) /* no carrier */ ++#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */ ++#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */ ++#define DMA_TX_ERROR BIT(15) /* frame aborted */ ++#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */ ++ ++#define DMA_TX1_BSIZE_MASK 0x000007ff ++#define DMA_TX1_BSIZE_SHIFT 0 ++#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */ ++#define DMA_TX1_TER BIT(25) /* transmit end of ring */ ++#define DMA_TX1_FS BIT(29) /* first segment */ ++#define DMA_TX1_LS BIT(30) /* last segment */ ++#define DMA_TX1_IC BIT(31) /* interrupt on completion */ ++ ++#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ ++ ++#define MAC_CONTROL_RE BIT(2) /* receive enable */ ++#define MAC_CONTROL_TE BIT(3) /* transmit enable */ ++#define MAC_CONTROL_DC BIT(5) /* Deferral check */ ++#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */ ++#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */ ++#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */ ++#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */ ++#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */ ++#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */ ++#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */ ++#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */ ++#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */ ++#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */ ++#define MAC_CONTROL_PM BIT(19) /* pass multicast */ ++#define MAC_CONTROL_F BIT(20) /* full-duplex */ ++#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */ ++#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */ ++#define MAC_CONTROL_BLE BIT(30) /* big endian mode */ ++#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */ ++ ++#define MII_ADDR_BUSY BIT(0) ++#define MII_ADDR_WRITE BIT(1) ++#define MII_ADDR_REG_SHIFT 6 ++#define MII_ADDR_PHY_SHIFT 11 ++#define MII_DATA_SHIFT 0 ++ ++#define FLOW_CONTROL_FCE BIT(1) ++ ++#define DMA_BUS_MODE_SWR BIT(0) /* software reset */ ++#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */ ++#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ ++#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */ ++ ++#define DMA_STATUS_TI BIT(0) /* transmit interrupt */ ++#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */ ++#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */ ++#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */ ++#define DMA_STATUS_UNF BIT(5) /* transmit underflow */ ++#define DMA_STATUS_RI BIT(6) /* receive interrupt */ ++#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */ ++#define DMA_STATUS_RPS BIT(8) /* receive process stopped */ ++#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */ ++#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */ ++#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */ ++#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */ ++#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */ ++#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ ++#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ ++#define DMA_STATUS_EB_SHIFT 23 /* error bits */ ++ ++#define DMA_CONTROL_SR BIT(1) /* start receive */ ++#define DMA_CONTROL_ST BIT(13) /* start transmit */ ++#define DMA_CONTROL_SF BIT(21) /* store and forward */ ++ ++ ++typedef struct { ++ volatile unsigned int status; // OWN, Device control and status. ++ volatile unsigned int devcs; // pkt Control bits + Length ++ volatile unsigned int addr; // Current Address. ++ volatile unsigned int descr; // Next descriptor in chain. ++} ar231x_descr_t; ++ ++ ++ ++// ++// New Combo structure for Both Eth0 AND eth1 ++// ++typedef struct { ++ volatile unsigned int mac_control; /* 0x00 */ ++ volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */ ++ volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */ ++ volatile unsigned int mii_addr; /* 0x14 */ ++ volatile unsigned int mii_data; /* 0x18 */ ++ volatile unsigned int flow_control; /* 0x1c */ ++ volatile unsigned int vlan_tag; /* 0x20 */ ++ volatile unsigned int pad[7]; /* 0x24 - 0x3c */ ++ volatile unsigned int ucast_table[8]; /* 0x40-0x5c */ ++ ++} ETHERNET_STRUCT; ++ ++/******************************************************************** ++ * Interrupt controller ++ ********************************************************************/ ++ ++typedef struct { ++ volatile unsigned int wdog_control; /* 0x08 */ ++ volatile unsigned int wdog_timer; /* 0x0c */ ++ volatile unsigned int misc_status; /* 0x10 */ ++ volatile unsigned int misc_mask; /* 0x14 */ ++ volatile unsigned int global_status; /* 0x18 */ ++ volatile unsigned int reserved; /* 0x1c */ ++ volatile unsigned int reset_control; /* 0x20 */ ++} INTERRUPT; ++ ++/******************************************************************** ++ * DMA controller ++ ********************************************************************/ ++typedef struct { ++ volatile unsigned int bus_mode; /* 0x00 (CSR0) */ ++ volatile unsigned int xmt_poll; /* 0x04 (CSR1) */ ++ volatile unsigned int rcv_poll; /* 0x08 (CSR2) */ ++ volatile unsigned int rcv_base; /* 0x0c (CSR3) */ ++ volatile unsigned int xmt_base; /* 0x10 (CSR4) */ ++ volatile unsigned int status; /* 0x14 (CSR5) */ ++ volatile unsigned int control; /* 0x18 (CSR6) */ ++ volatile unsigned int intr_ena; /* 0x1c (CSR7) */ ++ volatile unsigned int rcv_missed; /* 0x20 (CSR8) */ ++ volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */ ++ volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */ ++ volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */ ++} DMA; ++ ++/* ++ * Struct private for the Sibyte. ++ * ++ * Elements are grouped so variables used by the tx handling goes ++ * together, and will go into the same cache lines etc. in order to ++ * avoid cache line contention between the rx and tx handling on SMP. ++ * ++ * Frequently accessed variables are put at the beginning of the ++ * struct to help the compiler generate better/shorter code. ++ */ ++struct ar231x_private { ++ struct net_device *dev; ++ int version; ++ u32 mb[2]; ++ ++ volatile ETHERNET_STRUCT *phy_regs; ++ volatile ETHERNET_STRUCT *eth_regs; ++ volatile DMA *dma_regs; ++ volatile u32 *int_regs; ++ struct ar231x_eth *cfg; ++ ++ spinlock_t lock; /* Serialise access to device */ ++ ++ /* ++ * RX and TX descriptors, must be adjacent ++ */ ++ ar231x_descr_t *rx_ring; ++ ar231x_descr_t *tx_ring; ++ ++ ++ struct sk_buff **rx_skb; ++ struct sk_buff **tx_skb; ++ ++ /* ++ * RX elements ++ */ ++ u32 rx_skbprd; ++ u32 cur_rx; ++ ++ /* ++ * TX elements ++ */ ++ u32 tx_prd; ++ u32 tx_csm; ++ ++ /* ++ * Misc elements ++ */ ++ char name[48]; ++ struct { ++ u32 address; ++ u32 length; ++ char *mapping; ++ } desc; ++ ++ ++ struct timer_list link_timer; ++ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */ ++ unsigned short mac; ++ unsigned short link; /* 0 - link down, 1 - link up */ ++ u16 phyData; ++ ++ struct tasklet_struct rx_tasklet; ++ int unloading; ++ ++ struct phy_device *phy_dev; ++ struct mii_bus *mii_bus; ++ int oldduplex; ++}; ++ ++ ++/* ++ * Prototypes ++ */ ++static int ar231x_init(struct net_device *dev); ++#ifdef TX_TIMEOUT ++static void ar231x_tx_timeout(struct net_device *dev); ++#endif ++static int ar231x_restart(struct net_device *dev); ++static void ar231x_load_rx_ring(struct net_device *dev, int bufs); ++static irqreturn_t ar231x_interrupt(int irq, void *dev_id); ++static int ar231x_open(struct net_device *dev); ++static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev); ++static int ar231x_close(struct net_device *dev); ++static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, ++ int cmd); ++static void ar231x_init_cleanup(struct net_device *dev); ++static int ar231x_setup_timer(struct net_device *dev); ++static void ar231x_link_timer_fn(unsigned long data); ++static void ar231x_check_link(struct net_device *dev); ++#endif /* _AR2313_H_ */ +diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig linux-2.6.39-rc7/drivers/watchdog/Kconfig +--- linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/watchdog/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -990,6 +990,12 @@ + To compile this driver as a loadable module, choose M here. + The module will be called bcm63xx_wdt. + ++config ATHEROS_WDT ++ tristate "Atheros wisoc Watchdog Timer" ++ depends on ATHEROS_AR231X ++ help ++ Hardware driver for the Atheros wisoc Watchdog Timer. ++ + # PARISC Architecture + + # POWERPC Architecture +diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Makefile linux-2.6.39-rc7/drivers/watchdog/Makefile +--- linux-2.6.39-rc7.orig/drivers/watchdog/Makefile 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/watchdog/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -120,6 +120,7 @@ + obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o ++obj-$(CONFIG_ATHEROS_WDT) += ar2315-wtd.o + obj-$(CONFIG_TXX9_WDT) += txx9wdt.o + obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o + octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o +diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c +--- linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,200 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (C) 2008 John Crispin ++ * Based on EP93xx and ifxmips wdt driver ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define CLOCK_RATE 40000000 ++#define HEARTBEAT(x) (x < 1 || x > 90)?(20):(x) ++ ++static int wdt_timeout = 20; ++static int started = 0; ++static int in_use = 0; ++ ++static void ++ar2315_wdt_enable(void) ++{ ++ ar231x_write_reg(AR2315_WD, wdt_timeout * CLOCK_RATE); ++ ar231x_write_reg(AR2315_ISR, 0x80); ++} ++ ++static ssize_t ++ar2315_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) ++{ ++ if(len) ++ ar2315_wdt_enable(); ++ return len; ++} ++ ++static int ++ar2315_wdt_open(struct inode *inode, struct file *file) ++{ ++ if(in_use) ++ return -EBUSY; ++ ar2315_wdt_enable(); ++ in_use = started = 1; ++ return nonseekable_open(inode, file); ++} ++ ++static int ++ar2315_wdt_release(struct inode *inode, struct file *file) ++{ ++ in_use = 0; ++ return 0; ++} ++ ++static irqreturn_t ++ar2315_wdt_interrupt(int irq, void *dev_id) ++{ ++ if(started) ++ { ++ printk(KERN_CRIT "watchdog expired, rebooting system\n"); ++ emergency_restart(); ++ } else { ++ ar231x_write_reg(AR2315_WDC, 0); ++ ar231x_write_reg(AR2315_WD, 0); ++ ar231x_write_reg(AR2315_ISR, 0x80); ++ } ++ return IRQ_HANDLED; ++} ++ ++static struct watchdog_info ident = { ++ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, ++ .identity = "ar2315 Watchdog", ++}; ++ ++static int ++ar2315_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int new_wdt_timeout; ++ int ret = -ENOIOCTLCMD; ++ ++ switch(cmd) ++ { ++ case WDIOC_GETSUPPORT: ++ ret = copy_to_user((struct watchdog_info __user *)arg, &ident, sizeof(ident)) ? -EFAULT : 0; ++ break; ++ ++ case WDIOC_KEEPALIVE: ++ ar2315_wdt_enable(); ++ ret = 0; ++ break; ++ ++ case WDIOC_SETTIMEOUT: ++ if((ret = get_user(new_wdt_timeout, (int __user *)arg))) ++ break; ++ wdt_timeout = HEARTBEAT(new_wdt_timeout); ++ ar2315_wdt_enable(); ++ break; ++ ++ case WDIOC_GETTIMEOUT: ++ ret = put_user(wdt_timeout, (int __user *)arg); ++ break; ++ } ++ return ret; ++} ++ ++static struct file_operations ar2315_wdt_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .write = ar2315_wdt_write, ++ .unlocked_ioctl = ar2315_wdt_ioctl, ++ .open = ar2315_wdt_open, ++ .release = ar2315_wdt_release, ++}; ++ ++static struct miscdevice ar2315_wdt_miscdev = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &ar2315_wdt_fops, ++}; ++ ++static int ++ar2315_wdt_probe(struct platform_device *dev) ++{ ++ int ret = 0; ++ ++ ar2315_wdt_enable(); ++ ret = request_irq(AR531X_MISC_IRQ_WATCHDOG, ar2315_wdt_interrupt, IRQF_DISABLED, "ar2315_wdt", NULL); ++ if(ret) ++ { ++ printk(KERN_ERR "ar2315wdt: failed to register inetrrupt\n"); ++ goto out; ++ } ++ ++ ret = misc_register(&ar2315_wdt_miscdev); ++ if(ret) ++ printk(KERN_ERR "ar2315wdt: failed to register miscdev\n"); ++ ++out: ++ return ret; ++} ++ ++static int ++ar2315_wdt_remove(struct platform_device *dev) ++{ ++ misc_deregister(&ar2315_wdt_miscdev); ++ free_irq(AR531X_MISC_IRQ_WATCHDOG, NULL); ++ return 0; ++} ++ ++static struct platform_driver ar2315_wdt_driver = { ++ .probe = ar2315_wdt_probe, ++ .remove = ar2315_wdt_remove, ++ .driver = { ++ .name = "ar2315_wdt", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init ++init_ar2315_wdt(void) ++{ ++ int ret = platform_driver_register(&ar2315_wdt_driver); ++ if(ret) ++ printk(KERN_INFO "ar2315_wdt: error registering platfom driver!"); ++ return ret; ++} ++ ++static void __exit ++exit_ar2315_wdt(void) ++{ ++ platform_driver_unregister(&ar2315_wdt_driver); ++} ++ ++module_init(init_ar2315_wdt); ++module_exit(exit_ar2315_wdt); diff --git a/target/linux/patches/3.0.8/gemalto.patch b/target/linux/patches/3.0.8/gemalto.patch new file mode 100644 index 000000000..f3c223b5e --- /dev/null +++ b/target/linux/patches/3.0.8/gemalto.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.36.orig/drivers/tty/serial/serial_cs.c linux-2.6.36/drivers/serial/serial_cs.c +--- linux-2.6.36.orig/drivers/tty/serial/serial_cs.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/tty/serial/serial_cs.c 2010-12-13 23:03:40.000000000 +0100 +@@ -794,6 +794,7 @@ + PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025), + PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045), + PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052), ++ PCMCIA_DEVICE_MANF_CARD(0x0157, 0x0100), /* Gemalto SCR */ + PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */ + PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */ + PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae), diff --git a/target/linux/patches/3.0.8/mips-malta.patch b/target/linux/patches/3.0.8/mips-malta.patch new file mode 100644 index 000000000..cc8789dca --- /dev/null +++ b/target/linux/patches/3.0.8/mips-malta.patch @@ -0,0 +1,135 @@ +http://lkml.indiana.edu/hypermail/linux/kernel/1105.3/02199.html + +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/smp-ops.h linux-2.6.39/arch/mips/include/asm/smp-ops.h +--- linux-2.6.39.orig/arch/mips/include/asm/smp-ops.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/include/asm/smp-ops.h 2011-08-29 04:39:03.360480881 +0200 +@@ -56,8 +56,43 @@ + + #endif /* !CONFIG_SMP */ + +-extern struct plat_smp_ops up_smp_ops; +-extern struct plat_smp_ops cmp_smp_ops; +-extern struct plat_smp_ops vsmp_smp_ops; ++static inline int register_up_smp_ops(void) ++{ ++#ifdef CONFIG_SMP_UP ++ extern struct plat_smp_ops up_smp_ops; ++ ++ register_smp_ops(&up_smp_ops); ++ ++ return 0; ++#else ++ return -ENODEV; ++#endif ++} ++ ++static inline int register_cmp_smp_ops(void) ++{ ++#ifdef CONFIG_MIPS_CMP ++ extern struct plat_smp_ops cmp_smp_ops; ++ ++ register_smp_ops(&cmp_smp_ops); ++ ++ return 0; ++#else ++ return -ENODEV; ++#endif ++} ++ ++static inline int register_vsmp_smp_ops(void) ++{ ++#ifdef CONFIG_MIPS_MT_SMP ++ extern struct plat_smp_ops vsmp_smp_ops; ++ ++ register_smp_ops(&vsmp_smp_ops); ++ ++ return 0; ++#else ++ return -ENODEV; ++#endif ++} + + #endif /* __ASM_SMP_OPS_H */ +diff -Nur linux-2.6.39.orig/arch/mips/mipssim/sim_setup.c linux-2.6.39/arch/mips/mipssim/sim_setup.c +--- linux-2.6.39.orig/arch/mips/mipssim/sim_setup.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/mipssim/sim_setup.c 2011-08-29 04:39:03.390480572 +0200 +@@ -59,18 +59,17 @@ + + prom_meminit(); + +-#ifdef CONFIG_MIPS_MT_SMP +- if (cpu_has_mipsmt) +- register_smp_ops(&vsmp_smp_ops); +- else +- register_smp_ops(&up_smp_ops); +-#endif ++ if (cpu_has_mipsmt) { ++ if (!register_vsmp_smp_ops()) ++ return; ++ + #ifdef CONFIG_MIPS_MT_SMTC +- if (cpu_has_mipsmt) + register_smp_ops(&ssmtc_smp_ops); +- else +- register_smp_ops(&up_smp_ops); ++ return; + #endif ++ } ++ ++ register_up_smp_ops(); + } + + static void __init serial_init(void) +diff -Nur linux-2.6.39.orig/arch/mips/mti-malta/malta-init.c linux-2.6.39/arch/mips/mti-malta/malta-init.c +--- linux-2.6.39.orig/arch/mips/mti-malta/malta-init.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/mti-malta/malta-init.c 2011-08-29 04:39:03.700480601 +0200 +@@ -29,6 +29,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -358,15 +359,14 @@ + #ifdef CONFIG_SERIAL_8250_CONSOLE + console_config(); + #endif +-#ifdef CONFIG_MIPS_CMP + /* Early detection of CMP support */ + if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ)) +- register_smp_ops(&cmp_smp_ops); +- else +-#endif +-#ifdef CONFIG_MIPS_MT_SMP +- register_smp_ops(&vsmp_smp_ops); +-#endif ++ if (!register_cmp_smp_ops()) ++ return; ++ ++ if (!register_vsmp_smp_ops()) ++ return; ++ + #ifdef CONFIG_MIPS_MT_SMTC + register_smp_ops(&msmtc_smp_ops); + #endif +diff -Nur linux-2.6.39.orig/arch/mips/pmc-sierra/msp71xx/msp_setup.c linux-2.6.39/arch/mips/pmc-sierra/msp71xx/msp_setup.c +--- linux-2.6.39.orig/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2011-08-29 04:39:03.790480302 +0200 +@@ -228,13 +228,11 @@ + */ + msp_serial_setup(); + +-#ifdef CONFIG_MIPS_MT_SMP +- register_smp_ops(&vsmp_smp_ops); +-#endif +- ++ if (register_vsmp_smp_ops()) { + #ifdef CONFIG_MIPS_MT_SMTC +- register_smp_ops(&msp_smtc_smp_ops); ++ register_smp_ops(&msp_smtc_smp_ops); + #endif ++ } + + #ifdef CONFIG_PMCTWILED + /* diff --git a/target/linux/patches/3.0.8/mmc-host.patch b/target/linux/patches/3.0.8/mmc-host.patch new file mode 100644 index 000000000..3d0e37add --- /dev/null +++ b/target/linux/patches/3.0.8/mmc-host.patch @@ -0,0 +1,36 @@ +diff -Nur linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig linux-2.6.39-rc6/drivers/mmc/host/Kconfig +--- linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/drivers/mmc/host/Kconfig 2011-05-10 23:39:01.000000000 +0200 +@@ -253,13 +253,6 @@ + + If unsure, say N. + +-choice +- prompt "Atmel SD/MMC Driver" +- depends on AVR32 || ARCH_AT91 +- default MMC_ATMELMCI if AVR32 +- help +- Choose which driver to use for the Atmel MCI Silicon +- + config MMC_AT91 + tristate "AT91 SD/MMC Card Interface support" + depends on ARCH_AT91 +@@ -268,18 +261,6 @@ + + If unsure, say N. + +-config MMC_ATMELMCI +- tristate "Atmel Multimedia Card Interface support" +- depends on AVR32 || ARCH_AT91 +- help +- This selects the Atmel Multimedia Card Interface driver. If +- you have an AT32 (AVR32) or AT91 platform with a Multimedia +- Card slot, say Y or M here. +- +- If unsure, say N. +- +-endchoice +- + config MMC_ATMELMCI_DMA + bool "Atmel MCI DMA support (EXPERIMENTAL)" + depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45) && DMA_ENGINE && EXPERIMENTAL diff --git a/target/linux/patches/3.0.8/non-static.patch b/target/linux/patches/3.0.8/non-static.patch new file mode 100644 index 000000000..a967703d0 --- /dev/null +++ b/target/linux/patches/3.0.8/non-static.patch @@ -0,0 +1,33 @@ +diff -Nur linux-2.6.39-rc6.orig/fs/namei.c linux-2.6.39-rc6/fs/namei.c +--- linux-2.6.39-rc6.orig/fs/namei.c 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/fs/namei.c 2011-05-05 11:30:14.000000000 +0200 +@@ -1769,7 +1769,7 @@ + * needs parent already locked. Doesn't follow mounts. + * SMP-safe. + */ +-static struct dentry *lookup_hash(struct nameidata *nd) ++struct dentry *lookup_hash(struct nameidata *nd) + { + return __lookup_hash(&nd->last, nd->path.dentry, nd); + } +diff -Nur linux-2.6.39-rc6.orig/fs/splice.c linux-2.6.39-rc6/fs/splice.c +--- linux-2.6.39-rc6.orig/fs/splice.c 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/fs/splice.c 2011-05-05 11:31:04.000000000 +0200 +@@ -1081,7 +1081,7 @@ + /* + * Attempt to initiate a splice from pipe to file. + */ +-static long do_splice_from(struct pipe_inode_info *pipe, struct file *out, ++long do_splice_from(struct pipe_inode_info *pipe, struct file *out, + loff_t *ppos, size_t len, unsigned int flags) + { + ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, +@@ -1109,7 +1109,7 @@ + /* + * Attempt to initiate a splice from a file to a pipe. + */ +-static long do_splice_to(struct file *in, loff_t *ppos, ++long do_splice_to(struct file *in, loff_t *ppos, + struct pipe_inode_info *pipe, size_t len, + unsigned int flags) + { diff --git a/target/linux/patches/3.0.8/ocf-20110720.patch b/target/linux/patches/3.0.8/ocf-20110720.patch new file mode 100644 index 000000000..b5a257324 --- /dev/null +++ b/target/linux/patches/3.0.8/ocf-20110720.patch @@ -0,0 +1,99170 @@ +diff -Nur linux-3.0.4.orig/crypto/Kconfig linux-3.0.4/crypto/Kconfig +--- linux-3.0.4.orig/crypto/Kconfig 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/crypto/Kconfig 2011-10-17 04:36:27.356574299 +0200 +@@ -860,3 +860,6 @@ + source "drivers/crypto/Kconfig" + + endif # if CRYPTO ++ ++source "crypto/ocf/Kconfig" ++ +diff -Nur linux-3.0.4.orig/crypto/Kconfig.orig linux-3.0.4/crypto/Kconfig.orig +--- linux-3.0.4.orig/crypto/Kconfig.orig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/Kconfig.orig 2011-08-29 22:56:30.000000000 +0200 +@@ -0,0 +1,862 @@ ++# ++# Generic algorithms support ++# ++config XOR_BLOCKS ++ tristate ++ ++# ++# async_tx api: hardware offloaded memory transfer/transform support ++# ++source "crypto/async_tx/Kconfig" ++ ++# ++# Cryptographic API Configuration ++# ++menuconfig CRYPTO ++ tristate "Cryptographic API" ++ help ++ This option provides the core Cryptographic API. ++ ++if CRYPTO ++ ++comment "Crypto core or helper" ++ ++config CRYPTO_FIPS ++ bool "FIPS 200 compliance" ++ depends on CRYPTO_ANSI_CPRNG && !CRYPTO_MANAGER_DISABLE_TESTS ++ help ++ This options enables the fips boot option which is ++ required if you want to system to operate in a FIPS 200 ++ certification. You should say no unless you know what ++ this is. ++ ++config CRYPTO_ALGAPI ++ tristate ++ select CRYPTO_ALGAPI2 ++ help ++ This option provides the API for cryptographic algorithms. ++ ++config CRYPTO_ALGAPI2 ++ tristate ++ ++config CRYPTO_AEAD ++ tristate ++ select CRYPTO_AEAD2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_AEAD2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ ++config CRYPTO_BLKCIPHER ++ tristate ++ select CRYPTO_BLKCIPHER2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_BLKCIPHER2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ select CRYPTO_RNG2 ++ select CRYPTO_WORKQUEUE ++ ++config CRYPTO_HASH ++ tristate ++ select CRYPTO_HASH2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_HASH2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ ++config CRYPTO_RNG ++ tristate ++ select CRYPTO_RNG2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_RNG2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ ++config CRYPTO_PCOMP ++ tristate ++ select CRYPTO_PCOMP2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_PCOMP2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ ++config CRYPTO_MANAGER ++ tristate "Cryptographic algorithm manager" ++ select CRYPTO_MANAGER2 ++ help ++ Create default cryptographic template instantiations such as ++ cbc(aes). ++ ++config CRYPTO_MANAGER2 ++ def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y) ++ select CRYPTO_AEAD2 ++ select CRYPTO_HASH2 ++ select CRYPTO_BLKCIPHER2 ++ select CRYPTO_PCOMP2 ++ ++config CRYPTO_MANAGER_DISABLE_TESTS ++ bool "Disable run-time self tests" ++ default y ++ depends on CRYPTO_MANAGER2 ++ help ++ Disable run-time self tests that normally take place at ++ algorithm registration. ++ ++config CRYPTO_GF128MUL ++ tristate "GF(2^128) multiplication functions (EXPERIMENTAL)" ++ help ++ Efficient table driven implementation of multiplications in the ++ field GF(2^128). This is needed by some cypher modes. This ++ option will be selected automatically if you select such a ++ cipher mode. Only select this option by hand if you expect to load ++ an external module that requires these functions. ++ ++config CRYPTO_NULL ++ tristate "Null algorithms" ++ select CRYPTO_ALGAPI ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_HASH ++ help ++ These are 'Null' algorithms, used by IPsec, which do nothing. ++ ++config CRYPTO_PCRYPT ++ tristate "Parallel crypto engine (EXPERIMENTAL)" ++ depends on SMP && EXPERIMENTAL ++ select PADATA ++ select CRYPTO_MANAGER ++ select CRYPTO_AEAD ++ help ++ This converts an arbitrary crypto algorithm into a parallel ++ algorithm that executes in kernel threads. ++ ++config CRYPTO_WORKQUEUE ++ tristate ++ ++config CRYPTO_CRYPTD ++ tristate "Software async crypto daemon" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_HASH ++ select CRYPTO_MANAGER ++ select CRYPTO_WORKQUEUE ++ help ++ This is a generic software asynchronous crypto daemon that ++ converts an arbitrary synchronous software crypto algorithm ++ into an asynchronous algorithm that executes in a kernel thread. ++ ++config CRYPTO_AUTHENC ++ tristate "Authenc support" ++ select CRYPTO_AEAD ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ select CRYPTO_HASH ++ help ++ Authenc: Combined mode wrapper for IPsec. ++ This is required for IPSec. ++ ++config CRYPTO_TEST ++ tristate "Testing module" ++ depends on m ++ select CRYPTO_MANAGER ++ help ++ Quick & dirty crypto test module. ++ ++comment "Authenticated Encryption with Associated Data" ++ ++config CRYPTO_CCM ++ tristate "CCM support" ++ select CRYPTO_CTR ++ select CRYPTO_AEAD ++ help ++ Support for Counter with CBC MAC. Required for IPsec. ++ ++config CRYPTO_GCM ++ tristate "GCM/GMAC support" ++ select CRYPTO_CTR ++ select CRYPTO_AEAD ++ select CRYPTO_GHASH ++ help ++ Support for Galois/Counter Mode (GCM) and Galois Message ++ Authentication Code (GMAC). Required for IPSec. ++ ++config CRYPTO_SEQIV ++ tristate "Sequence Number IV Generator" ++ select CRYPTO_AEAD ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_RNG ++ help ++ This IV generator generates an IV based on a sequence number by ++ xoring it with a salt. This algorithm is mainly useful for CTR ++ ++comment "Block modes" ++ ++config CRYPTO_CBC ++ tristate "CBC support" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ help ++ CBC: Cipher Block Chaining mode ++ This block cipher algorithm is required for IPSec. ++ ++config CRYPTO_CTR ++ tristate "CTR support" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_SEQIV ++ select CRYPTO_MANAGER ++ help ++ CTR: Counter mode ++ This block cipher algorithm is required for IPSec. ++ ++config CRYPTO_CTS ++ tristate "CTS support" ++ select CRYPTO_BLKCIPHER ++ help ++ CTS: Cipher Text Stealing ++ This is the Cipher Text Stealing mode as described by ++ Section 8 of rfc2040 and referenced by rfc3962. ++ (rfc3962 includes errata information in its Appendix A) ++ This mode is required for Kerberos gss mechanism support ++ for AES encryption. ++ ++config CRYPTO_ECB ++ tristate "ECB support" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ help ++ ECB: Electronic CodeBook mode ++ This is the simplest block cipher algorithm. It simply encrypts ++ the input block by block. ++ ++config CRYPTO_LRW ++ tristate "LRW support (EXPERIMENTAL)" ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ select CRYPTO_GF128MUL ++ help ++ LRW: Liskov Rivest Wagner, a tweakable, non malleable, non movable ++ narrow block cipher mode for dm-crypt. Use it with cipher ++ specification string aes-lrw-benbi, the key must be 256, 320 or 384. ++ The first 128, 192 or 256 bits in the key are used for AES and the ++ rest is used to tie each cipher block to its logical position. ++ ++config CRYPTO_PCBC ++ tristate "PCBC support" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ help ++ PCBC: Propagating Cipher Block Chaining mode ++ This block cipher algorithm is required for RxRPC. ++ ++config CRYPTO_XTS ++ tristate "XTS support (EXPERIMENTAL)" ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ select CRYPTO_GF128MUL ++ help ++ XTS: IEEE1619/D16 narrow block cipher use with aes-xts-plain, ++ key size 256, 384 or 512 bits. This implementation currently ++ can't handle a sectorsize which is not a multiple of 16 bytes. ++ ++comment "Hash modes" ++ ++config CRYPTO_HMAC ++ tristate "HMAC support" ++ select CRYPTO_HASH ++ select CRYPTO_MANAGER ++ help ++ HMAC: Keyed-Hashing for Message Authentication (RFC2104). ++ This is required for IPSec. ++ ++config CRYPTO_XCBC ++ tristate "XCBC support" ++ depends on EXPERIMENTAL ++ select CRYPTO_HASH ++ select CRYPTO_MANAGER ++ help ++ XCBC: Keyed-Hashing with encryption algorithm ++ http://www.ietf.org/rfc/rfc3566.txt ++ http://csrc.nist.gov/encryption/modes/proposedmodes/ ++ xcbc-mac/xcbc-mac-spec.pdf ++ ++config CRYPTO_VMAC ++ tristate "VMAC support" ++ depends on EXPERIMENTAL ++ select CRYPTO_HASH ++ select CRYPTO_MANAGER ++ help ++ VMAC is a message authentication algorithm designed for ++ very high speed on 64-bit architectures. ++ ++ See also: ++ ++ ++comment "Digest" ++ ++config CRYPTO_CRC32C ++ tristate "CRC32c CRC algorithm" ++ select CRYPTO_HASH ++ help ++ Castagnoli, et al Cyclic Redundancy-Check Algorithm. Used ++ by iSCSI for header and data digests and by others. ++ See Castagnoli93. Module will be crc32c. ++ ++config CRYPTO_CRC32C_INTEL ++ tristate "CRC32c INTEL hardware acceleration" ++ depends on X86 ++ select CRYPTO_HASH ++ help ++ In Intel processor with SSE4.2 supported, the processor will ++ support CRC32C implementation using hardware accelerated CRC32 ++ instruction. This option will create 'crc32c-intel' module, ++ which will enable any routine to use the CRC32 instruction to ++ gain performance compared with software implementation. ++ Module will be crc32c-intel. ++ ++config CRYPTO_GHASH ++ tristate "GHASH digest algorithm" ++ select CRYPTO_SHASH ++ select CRYPTO_GF128MUL ++ help ++ GHASH is message digest algorithm for GCM (Galois/Counter Mode). ++ ++config CRYPTO_MD4 ++ tristate "MD4 digest algorithm" ++ select CRYPTO_HASH ++ help ++ MD4 message digest algorithm (RFC1320). ++ ++config CRYPTO_MD5 ++ tristate "MD5 digest algorithm" ++ select CRYPTO_HASH ++ help ++ MD5 message digest algorithm (RFC1321). ++ ++config CRYPTO_MICHAEL_MIC ++ tristate "Michael MIC keyed digest algorithm" ++ select CRYPTO_HASH ++ help ++ Michael MIC is used for message integrity protection in TKIP ++ (IEEE 802.11i). This algorithm is required for TKIP, but it ++ should not be used for other purposes because of the weakness ++ of the algorithm. ++ ++config CRYPTO_RMD128 ++ tristate "RIPEMD-128 digest algorithm" ++ select CRYPTO_HASH ++ help ++ RIPEMD-128 (ISO/IEC 10118-3:2004). ++ ++ RIPEMD-128 is a 128-bit cryptographic hash function. It should only ++ to be used as a secure replacement for RIPEMD. For other use cases ++ RIPEMD-160 should be used. ++ ++ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. ++ See ++ ++config CRYPTO_RMD160 ++ tristate "RIPEMD-160 digest algorithm" ++ select CRYPTO_HASH ++ help ++ RIPEMD-160 (ISO/IEC 10118-3:2004). ++ ++ RIPEMD-160 is a 160-bit cryptographic hash function. It is intended ++ to be used as a secure replacement for the 128-bit hash functions ++ MD4, MD5 and it's predecessor RIPEMD ++ (not to be confused with RIPEMD-128). ++ ++ It's speed is comparable to SHA1 and there are no known attacks ++ against RIPEMD-160. ++ ++ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. ++ See ++ ++config CRYPTO_RMD256 ++ tristate "RIPEMD-256 digest algorithm" ++ select CRYPTO_HASH ++ help ++ RIPEMD-256 is an optional extension of RIPEMD-128 with a ++ 256 bit hash. It is intended for applications that require ++ longer hash-results, without needing a larger security level ++ (than RIPEMD-128). ++ ++ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. ++ See ++ ++config CRYPTO_RMD320 ++ tristate "RIPEMD-320 digest algorithm" ++ select CRYPTO_HASH ++ help ++ RIPEMD-320 is an optional extension of RIPEMD-160 with a ++ 320 bit hash. It is intended for applications that require ++ longer hash-results, without needing a larger security level ++ (than RIPEMD-160). ++ ++ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. ++ See ++ ++config CRYPTO_SHA1 ++ tristate "SHA1 digest algorithm" ++ select CRYPTO_HASH ++ help ++ SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2). ++ ++config CRYPTO_SHA256 ++ tristate "SHA224 and SHA256 digest algorithm" ++ select CRYPTO_HASH ++ help ++ SHA256 secure hash standard (DFIPS 180-2). ++ ++ This version of SHA implements a 256 bit hash with 128 bits of ++ security against collision attacks. ++ ++ This code also includes SHA-224, a 224 bit hash with 112 bits ++ of security against collision attacks. ++ ++config CRYPTO_SHA512 ++ tristate "SHA384 and SHA512 digest algorithms" ++ select CRYPTO_HASH ++ help ++ SHA512 secure hash standard (DFIPS 180-2). ++ ++ This version of SHA implements a 512 bit hash with 256 bits of ++ security against collision attacks. ++ ++ This code also includes SHA-384, a 384 bit hash with 192 bits ++ of security against collision attacks. ++ ++config CRYPTO_TGR192 ++ tristate "Tiger digest algorithms" ++ select CRYPTO_HASH ++ help ++ Tiger hash algorithm 192, 160 and 128-bit hashes ++ ++ Tiger is a hash function optimized for 64-bit processors while ++ still having decent performance on 32-bit processors. ++ Tiger was developed by Ross Anderson and Eli Biham. ++ ++ See also: ++ . ++ ++config CRYPTO_WP512 ++ tristate "Whirlpool digest algorithms" ++ select CRYPTO_HASH ++ help ++ Whirlpool hash algorithm 512, 384 and 256-bit hashes ++ ++ Whirlpool-512 is part of the NESSIE cryptographic primitives. ++ Whirlpool will be part of the ISO/IEC 10118-3:2003(E) standard ++ ++ See also: ++ ++ ++config CRYPTO_GHASH_CLMUL_NI_INTEL ++ tristate "GHASH digest algorithm (CLMUL-NI accelerated)" ++ depends on (X86 || UML_X86) && 64BIT ++ select CRYPTO_SHASH ++ select CRYPTO_CRYPTD ++ help ++ GHASH is message digest algorithm for GCM (Galois/Counter Mode). ++ The implementation is accelerated by CLMUL-NI of Intel. ++ ++comment "Ciphers" ++ ++config CRYPTO_AES ++ tristate "AES cipher algorithms" ++ select CRYPTO_ALGAPI ++ help ++ AES cipher algorithms (FIPS-197). AES uses the Rijndael ++ algorithm. ++ ++ Rijndael appears to be consistently a very good performer in ++ both hardware and software across a wide range of computing ++ environments regardless of its use in feedback or non-feedback ++ modes. Its key setup time is excellent, and its key agility is ++ good. Rijndael's very low memory requirements make it very well ++ suited for restricted-space environments, in which it also ++ demonstrates excellent performance. Rijndael's operations are ++ among the easiest to defend against power and timing attacks. ++ ++ The AES specifies three key sizes: 128, 192 and 256 bits ++ ++ See for more information. ++ ++config CRYPTO_AES_586 ++ tristate "AES cipher algorithms (i586)" ++ depends on (X86 || UML_X86) && !64BIT ++ select CRYPTO_ALGAPI ++ select CRYPTO_AES ++ help ++ AES cipher algorithms (FIPS-197). AES uses the Rijndael ++ algorithm. ++ ++ Rijndael appears to be consistently a very good performer in ++ both hardware and software across a wide range of computing ++ environments regardless of its use in feedback or non-feedback ++ modes. Its key setup time is excellent, and its key agility is ++ good. Rijndael's very low memory requirements make it very well ++ suited for restricted-space environments, in which it also ++ demonstrates excellent performance. Rijndael's operations are ++ among the easiest to defend against power and timing attacks. ++ ++ The AES specifies three key sizes: 128, 192 and 256 bits ++ ++ See for more information. ++ ++config CRYPTO_AES_X86_64 ++ tristate "AES cipher algorithms (x86_64)" ++ depends on (X86 || UML_X86) && 64BIT ++ select CRYPTO_ALGAPI ++ select CRYPTO_AES ++ help ++ AES cipher algorithms (FIPS-197). AES uses the Rijndael ++ algorithm. ++ ++ Rijndael appears to be consistently a very good performer in ++ both hardware and software across a wide range of computing ++ environments regardless of its use in feedback or non-feedback ++ modes. Its key setup time is excellent, and its key agility is ++ good. Rijndael's very low memory requirements make it very well ++ suited for restricted-space environments, in which it also ++ demonstrates excellent performance. Rijndael's operations are ++ among the easiest to defend against power and timing attacks. ++ ++ The AES specifies three key sizes: 128, 192 and 256 bits ++ ++ See for more information. ++ ++config CRYPTO_AES_NI_INTEL ++ tristate "AES cipher algorithms (AES-NI)" ++ depends on (X86 || UML_X86) ++ select CRYPTO_AES_X86_64 if 64BIT ++ select CRYPTO_AES_586 if !64BIT ++ select CRYPTO_CRYPTD ++ select CRYPTO_ALGAPI ++ help ++ Use Intel AES-NI instructions for AES algorithm. ++ ++ AES cipher algorithms (FIPS-197). AES uses the Rijndael ++ algorithm. ++ ++ Rijndael appears to be consistently a very good performer in ++ both hardware and software across a wide range of computing ++ environments regardless of its use in feedback or non-feedback ++ modes. Its key setup time is excellent, and its key agility is ++ good. Rijndael's very low memory requirements make it very well ++ suited for restricted-space environments, in which it also ++ demonstrates excellent performance. Rijndael's operations are ++ among the easiest to defend against power and timing attacks. ++ ++ The AES specifies three key sizes: 128, 192 and 256 bits ++ ++ See for more information. ++ ++ In addition to AES cipher algorithm support, the acceleration ++ for some popular block cipher mode is supported too, including ++ ECB, CBC, LRW, PCBC, XTS. The 64 bit version has additional ++ acceleration for CTR. ++ ++config CRYPTO_ANUBIS ++ tristate "Anubis cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ Anubis cipher algorithm. ++ ++ Anubis is a variable key length cipher which can use keys from ++ 128 bits to 320 bits in length. It was evaluated as a entrant ++ in the NESSIE competition. ++ ++ See also: ++ ++ ++ ++config CRYPTO_ARC4 ++ tristate "ARC4 cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ ARC4 cipher algorithm. ++ ++ ARC4 is a stream cipher using keys ranging from 8 bits to 2048 ++ bits in length. This algorithm is required for driver-based ++ WEP, but it should not be for other purposes because of the ++ weakness of the algorithm. ++ ++config CRYPTO_BLOWFISH ++ tristate "Blowfish cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ Blowfish cipher algorithm, by Bruce Schneier. ++ ++ This is a variable key length cipher which can use keys from 32 ++ bits to 448 bits in length. It's fast, simple and specifically ++ designed for use on "large microprocessors". ++ ++ See also: ++ ++ ++config CRYPTO_CAMELLIA ++ tristate "Camellia cipher algorithms" ++ depends on CRYPTO ++ select CRYPTO_ALGAPI ++ help ++ Camellia cipher algorithms module. ++ ++ Camellia is a symmetric key block cipher developed jointly ++ at NTT and Mitsubishi Electric Corporation. ++ ++ The Camellia specifies three key sizes: 128, 192 and 256 bits. ++ ++ See also: ++ ++ ++config CRYPTO_CAST5 ++ tristate "CAST5 (CAST-128) cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ The CAST5 encryption algorithm (synonymous with CAST-128) is ++ described in RFC2144. ++ ++config CRYPTO_CAST6 ++ tristate "CAST6 (CAST-256) cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ The CAST6 encryption algorithm (synonymous with CAST-256) is ++ described in RFC2612. ++ ++config CRYPTO_DES ++ tristate "DES and Triple DES EDE cipher algorithms" ++ select CRYPTO_ALGAPI ++ help ++ DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3). ++ ++config CRYPTO_FCRYPT ++ tristate "FCrypt cipher algorithm" ++ select CRYPTO_ALGAPI ++ select CRYPTO_BLKCIPHER ++ help ++ FCrypt algorithm used by RxRPC. ++ ++config CRYPTO_KHAZAD ++ tristate "Khazad cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ Khazad cipher algorithm. ++ ++ Khazad was a finalist in the initial NESSIE competition. It is ++ an algorithm optimized for 64-bit processors with good performance ++ on 32-bit processors. Khazad uses an 128 bit key size. ++ ++ See also: ++ ++ ++config CRYPTO_SALSA20 ++ tristate "Salsa20 stream cipher algorithm (EXPERIMENTAL)" ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ help ++ Salsa20 stream cipher algorithm. ++ ++ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT ++ Stream Cipher Project. See ++ ++ The Salsa20 stream cipher algorithm is designed by Daniel J. ++ Bernstein . See ++ ++config CRYPTO_SALSA20_586 ++ tristate "Salsa20 stream cipher algorithm (i586) (EXPERIMENTAL)" ++ depends on (X86 || UML_X86) && !64BIT ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ help ++ Salsa20 stream cipher algorithm. ++ ++ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT ++ Stream Cipher Project. See ++ ++ The Salsa20 stream cipher algorithm is designed by Daniel J. ++ Bernstein . See ++ ++config CRYPTO_SALSA20_X86_64 ++ tristate "Salsa20 stream cipher algorithm (x86_64) (EXPERIMENTAL)" ++ depends on (X86 || UML_X86) && 64BIT ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ help ++ Salsa20 stream cipher algorithm. ++ ++ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT ++ Stream Cipher Project. See ++ ++ The Salsa20 stream cipher algorithm is designed by Daniel J. ++ Bernstein . See ++ ++config CRYPTO_SEED ++ tristate "SEED cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ SEED cipher algorithm (RFC4269). ++ ++ SEED is a 128-bit symmetric key block cipher that has been ++ developed by KISA (Korea Information Security Agency) as a ++ national standard encryption algorithm of the Republic of Korea. ++ It is a 16 round block cipher with the key size of 128 bit. ++ ++ See also: ++ ++ ++config CRYPTO_SERPENT ++ tristate "Serpent cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ Serpent cipher algorithm, by Anderson, Biham & Knudsen. ++ ++ Keys are allowed to be from 0 to 256 bits in length, in steps ++ of 8 bits. Also includes the 'Tnepres' algorithm, a reversed ++ variant of Serpent for compatibility with old kerneli.org code. ++ ++ See also: ++ ++ ++config CRYPTO_TEA ++ tristate "TEA, XTEA and XETA cipher algorithms" ++ select CRYPTO_ALGAPI ++ help ++ TEA cipher algorithm. ++ ++ Tiny Encryption Algorithm is a simple cipher that uses ++ many rounds for security. It is very fast and uses ++ little memory. ++ ++ Xtendend Tiny Encryption Algorithm is a modification to ++ the TEA algorithm to address a potential key weakness ++ in the TEA algorithm. ++ ++ Xtendend Encryption Tiny Algorithm is a mis-implementation ++ of the XTEA algorithm for compatibility purposes. ++ ++config CRYPTO_TWOFISH ++ tristate "Twofish cipher algorithm" ++ select CRYPTO_ALGAPI ++ select CRYPTO_TWOFISH_COMMON ++ help ++ Twofish cipher algorithm. ++ ++ Twofish was submitted as an AES (Advanced Encryption Standard) ++ candidate cipher by researchers at CounterPane Systems. It is a ++ 16 round block cipher supporting key sizes of 128, 192, and 256 ++ bits. ++ ++ See also: ++ ++ ++config CRYPTO_TWOFISH_COMMON ++ tristate ++ help ++ Common parts of the Twofish cipher algorithm shared by the ++ generic c and the assembler implementations. ++ ++config CRYPTO_TWOFISH_586 ++ tristate "Twofish cipher algorithms (i586)" ++ depends on (X86 || UML_X86) && !64BIT ++ select CRYPTO_ALGAPI ++ select CRYPTO_TWOFISH_COMMON ++ help ++ Twofish cipher algorithm. ++ ++ Twofish was submitted as an AES (Advanced Encryption Standard) ++ candidate cipher by researchers at CounterPane Systems. It is a ++ 16 round block cipher supporting key sizes of 128, 192, and 256 ++ bits. ++ ++ See also: ++ ++ ++config CRYPTO_TWOFISH_X86_64 ++ tristate "Twofish cipher algorithm (x86_64)" ++ depends on (X86 || UML_X86) && 64BIT ++ select CRYPTO_ALGAPI ++ select CRYPTO_TWOFISH_COMMON ++ help ++ Twofish cipher algorithm (x86_64). ++ ++ Twofish was submitted as an AES (Advanced Encryption Standard) ++ candidate cipher by researchers at CounterPane Systems. It is a ++ 16 round block cipher supporting key sizes of 128, 192, and 256 ++ bits. ++ ++ See also: ++ ++ ++comment "Compression" ++ ++config CRYPTO_DEFLATE ++ tristate "Deflate compression algorithm" ++ select CRYPTO_ALGAPI ++ select ZLIB_INFLATE ++ select ZLIB_DEFLATE ++ help ++ This is the Deflate algorithm (RFC1951), specified for use in ++ IPSec with the IPCOMP protocol (RFC3173, RFC2394). ++ ++ You will most probably want this if using IPSec. ++ ++config CRYPTO_ZLIB ++ tristate "Zlib compression algorithm" ++ select CRYPTO_PCOMP ++ select ZLIB_INFLATE ++ select ZLIB_DEFLATE ++ select NLATTR ++ help ++ This is the zlib algorithm. ++ ++config CRYPTO_LZO ++ tristate "LZO compression algorithm" ++ select CRYPTO_ALGAPI ++ select LZO_COMPRESS ++ select LZO_DECOMPRESS ++ help ++ This is the LZO algorithm. ++ ++comment "Random Number Generation" ++ ++config CRYPTO_ANSI_CPRNG ++ tristate "Pseudo Random Number Generation for Cryptographic modules" ++ default m ++ select CRYPTO_AES ++ select CRYPTO_RNG ++ help ++ This option enables the generic pseudo random number generator ++ for cryptographic modules. Uses the Algorithm specified in ++ ANSI X9.31 A.2.4. Note that this option must be enabled if ++ CRYPTO_FIPS is selected ++ ++config CRYPTO_USER_API ++ tristate ++ ++config CRYPTO_USER_API_HASH ++ tristate "User-space interface for hash algorithms" ++ depends on NET ++ select CRYPTO_HASH ++ select CRYPTO_USER_API ++ help ++ This option enables the user-spaces interface for hash ++ algorithms. ++ ++config CRYPTO_USER_API_SKCIPHER ++ tristate "User-space interface for symmetric key cipher algorithms" ++ depends on NET ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_USER_API ++ help ++ This option enables the user-spaces interface for symmetric ++ key cipher algorithms. ++ ++source "drivers/crypto/Kconfig" ++ ++endif # if CRYPTO +diff -Nur linux-3.0.4.orig/crypto/Makefile linux-3.0.4/crypto/Makefile +--- linux-3.0.4.orig/crypto/Makefile 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/crypto/Makefile 2011-10-17 04:36:27.356574299 +0200 +@@ -89,6 +89,8 @@ + obj-$(CONFIG_CRYPTO_USER_API_HASH) += algif_hash.o + obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) += algif_skcipher.o + ++obj-$(CONFIG_OCF_OCF) += ocf/ ++ + # + # generic algorithms and the async_tx api + # +diff -Nur linux-3.0.4.orig/crypto/ocf/Config.in linux-3.0.4/crypto/ocf/Config.in +--- linux-3.0.4.orig/crypto/ocf/Config.in 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/Config.in 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,38 @@ ++############################################################################# ++ ++mainmenu_option next_comment ++comment 'OCF Configuration' ++tristate 'OCF (Open Cryptograhic Framework)' CONFIG_OCF_OCF ++dep_mbool ' enable fips RNG checks (fips check on RNG data before use)' \ ++ CONFIG_OCF_FIPS $CONFIG_OCF_OCF ++dep_mbool ' enable harvesting entropy for /dev/random' \ ++ CONFIG_OCF_RANDOMHARVEST $CONFIG_OCF_OCF ++dep_tristate ' cryptodev (user space support)' \ ++ CONFIG_OCF_CRYPTODEV $CONFIG_OCF_OCF ++dep_tristate ' cryptosoft (software crypto engine)' \ ++ CONFIG_OCF_CRYPTOSOFT $CONFIG_OCF_OCF ++dep_tristate ' safenet (HW crypto engine)' \ ++ CONFIG_OCF_SAFE $CONFIG_OCF_OCF ++dep_tristate ' IXP4xx (HW crypto engine)' \ ++ CONFIG_OCF_IXP4XX $CONFIG_OCF_OCF ++dep_mbool ' Enable IXP4xx HW to perform SHA1 and MD5 hashing (very slow)' \ ++ CONFIG_OCF_IXP4XX_SHA1_MD5 $CONFIG_OCF_IXP4XX ++dep_tristate ' hifn (HW crypto engine)' \ ++ CONFIG_OCF_HIFN $CONFIG_OCF_OCF ++dep_tristate ' talitos (HW crypto engine)' \ ++ CONFIG_OCF_TALITOS $CONFIG_OCF_OCF ++dep_tristate ' pasemi (HW crypto engine)' \ ++ CONFIG_OCF_PASEMI $CONFIG_OCF_OCF ++dep_tristate ' ep80579 (HW crypto engine)' \ ++ CONFIG_OCF_EP80579 $CONFIG_OCF_OCF ++dep_tristate ' Micronas c7108 (HW crypto engine)' \ ++ CONFIG_OCF_C7108 $CONFIG_OCF_OCF ++dep_tristate ' uBsec BCM5365 (HW crypto engine)' ++ CONFIG_OCF_UBSEC_SSB $CONFIG_OCF_OCF ++dep_tristate ' ocfnull (does no crypto)' \ ++ CONFIG_OCF_OCFNULL $CONFIG_OCF_OCF ++dep_tristate ' ocf-bench (HW crypto in-kernel benchmark)' \ ++ CONFIG_OCF_BENCH $CONFIG_OCF_OCF ++endmenu ++ ++############################################################################# +diff -Nur linux-3.0.4.orig/crypto/ocf/Kconfig linux-3.0.4/crypto/ocf/Kconfig +--- linux-3.0.4.orig/crypto/ocf/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/Kconfig 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,125 @@ ++menu "OCF Configuration" ++ ++config OCF_OCF ++ tristate "OCF (Open Cryptograhic Framework)" ++ help ++ A linux port of the OpenBSD/FreeBSD crypto framework. ++ ++config OCF_RANDOMHARVEST ++ bool "crypto random --- harvest entropy for /dev/random" ++ depends on OCF_OCF ++ help ++ Includes code to harvest random numbers from devices that support it. ++ ++config OCF_FIPS ++ bool "enable fips RNG checks" ++ depends on OCF_OCF && OCF_RANDOMHARVEST ++ help ++ Run all RNG provided data through a fips check before ++ adding it /dev/random's entropy pool. ++ ++config OCF_CRYPTODEV ++ tristate "cryptodev (user space support)" ++ depends on OCF_OCF ++ help ++ The user space API to access crypto hardware. ++ ++config OCF_CRYPTOSOFT ++ tristate "cryptosoft (software crypto engine)" ++ depends on OCF_OCF ++ help ++ A software driver for the OCF framework that uses ++ the kernel CryptoAPI. ++ ++config OCF_SAFE ++ tristate "safenet (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ A driver for a number of the safenet Excel crypto accelerators. ++ Currently tested and working on the 1141 and 1741. ++ ++config OCF_IXP4XX ++ tristate "IXP4xx (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ XScale IXP4xx crypto accelerator driver. Requires the ++ Intel Access library. ++ ++config OCF_IXP4XX_SHA1_MD5 ++ bool "IXP4xx SHA1 and MD5 Hashing" ++ depends on OCF_IXP4XX ++ help ++ Allows the IXP4xx crypto accelerator to perform SHA1 and MD5 hashing. ++ Note: this is MUCH slower than using cryptosoft (software crypto engine). ++ ++config OCF_HIFN ++ tristate "hifn (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for various HIFN based crypto accelerators. ++ (7951, 7955, 7956, 7751, 7811) ++ ++config OCF_HIFNHIPP ++ tristate "Hifn HIPP (HW packet crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for various HIFN (HIPP) based crypto accelerators ++ (7855) ++ ++config OCF_TALITOS ++ tristate "talitos (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for Freescale's security engine (SEC/talitos). ++ ++config OCF_PASEMI ++ tristate "pasemi (HW crypto engine)" ++ depends on OCF_OCF && PPC_PASEMI ++ help ++ OCF driver for the PA Semi PWRficient DMA Engine ++ ++config OCF_EP80579 ++ tristate "ep80579 (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Intel EP80579 Integrated Processor Product Line. ++ ++config OCF_CRYPTOCTEON ++ tristate "cryptocteon (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Cavium OCTEON Processors. ++ ++config OCF_KIRKWOOD ++ tristate "kirkwood (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Marvell Kirkwood (88F6xxx) Processors. ++ ++config OCF_C7108 ++ tristate "Micronas 7108 (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Microna 7108 Cipher processors. ++ ++config OCF_UBSEC_SSB ++ tristate "uBsec BCM5365 (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for uBsec BCM5365 hardware crypto accelerator. ++ ++config OCF_OCFNULL ++ tristate "ocfnull (fake crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for measuring ipsec overheads (does no crypto) ++ ++config OCF_BENCH ++ tristate "ocf-bench (HW crypto in-kernel benchmark)" ++ depends on OCF_OCF ++ help ++ A very simple encryption test for the in-kernel interface ++ of OCF. Also includes code to benchmark the IXP Access library ++ for comparison. ++ ++endmenu +diff -Nur linux-3.0.4.orig/crypto/ocf/Makefile linux-3.0.4/crypto/ocf/Makefile +--- linux-3.0.4.orig/crypto/ocf/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,145 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++OCF_OBJS = crypto.o criov.o ++ ++ifdef CONFIG_OCF_RANDOMHARVEST ++ OCF_OBJS += random.o ++endif ++ ++ifdef CONFIG_OCF_FIPS ++ OCF_OBJS += rndtest.o ++endif ++ ++# Add in autoconf.h to get #defines for CONFIG_xxx ++AUTOCONF_H=$(ROOTDIR)/modules/autoconf.h ++ifeq ($(AUTOCONF_H), $(wildcard $(AUTOCONF_H))) ++ EXTRA_CFLAGS += -include $(AUTOCONF_H) ++ export EXTRA_CFLAGS ++endif ++ ++ifndef obj ++ obj ?= . ++ _obj = subdir ++ mod-subdirs := safe hifn ixp4xx talitos ocfnull ++ export-objs += crypto.o criov.o random.o ++ list-multi += ocf.o ++ _slash := ++else ++ _obj = obj ++ _slash := / ++endif ++ ++EXTRA_CFLAGS += -I$(obj)/. ++ ++obj-$(CONFIG_OCF_OCF) += ocf.o ++obj-$(CONFIG_OCF_CRYPTODEV) += cryptodev.o ++obj-$(CONFIG_OCF_CRYPTOSOFT) += cryptosoft.o ++obj-$(CONFIG_OCF_BENCH) += ocf-bench.o ++ ++$(_obj)-$(CONFIG_OCF_SAFE) += safe$(_slash) ++$(_obj)-$(CONFIG_OCF_HIFN) += hifn$(_slash) ++$(_obj)-$(CONFIG_OCF_IXP4XX) += ixp4xx$(_slash) ++$(_obj)-$(CONFIG_OCF_TALITOS) += talitos$(_slash) ++$(_obj)-$(CONFIG_OCF_PASEMI) += pasemi$(_slash) ++$(_obj)-$(CONFIG_OCF_EP80579) += ep80579$(_slash) ++$(_obj)-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon$(_slash) ++$(_obj)-$(CONFIG_OCF_KIRKWOOD) += kirkwood$(_slash) ++$(_obj)-$(CONFIG_OCF_OCFNULL) += ocfnull$(_slash) ++$(_obj)-$(CONFIG_OCF_C7108) += c7108$(_slash) ++$(_obj)-$(CONFIG_OCF_UBSEC_SSB) += ubsec_ssb$(_slash) ++ ++ocf-objs := $(OCF_OBJS) ++ ++dummy: ++ @echo "Please consult the README for how to build OCF." ++ @echo "If you can't wait then the following should do it:" ++ @echo "" ++ @echo " make ocf_modules" ++ @echo " sudo make ocf_install" ++ @echo "" ++ @exit 1 ++ ++$(list-multi) dummy1: $(ocf-objs) ++ $(LD) -r -o $@ $(ocf-objs) ++ ++.PHONY: ++clean: ++ rm -f *.o *.ko .*.o.flags .*.ko.cmd .*.o.cmd .*.mod.o.cmd *.mod.c ++ rm -f */*.o */*.ko */.*.o.cmd */.*.ko.cmd */.*.mod.o.cmd */*.mod.c */.*.o.flags ++ rm -f */modules.order */modules.builtin modules.order modules.builtin ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ ++# ++# targets to build easily on the current machine ++# ++ ++ocf_make: ++ make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m ++ make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_CRYPTOSOFT=m ++ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_BENCH=m ++ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_OCFNULL=m ++ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_HIFN=m ++ ++ocf_modules: ++ $(MAKE) ocf_make OCF_TARGET=modules ++ ++ocf_install: ++ $(MAKE) ocf_make OCF_TARGET="modules modules_install" ++ depmod ++ mkdir -p /usr/include/crypto ++ cp cryptodev.h /usr/include/crypto/. ++ ++# ++# generate full kernel patches for 2.4 and 2.6 kernels to make patching ++# your kernel easier ++# ++ ++.PHONY: patch ++patch: ++ patchbase=.; \ ++ [ -d $$patchbase/patches ] || patchbase=..; \ ++ patch=ocf-linux-base.patch; \ ++ patch24=ocf-linux-24.patch; \ ++ patch26=ocf-linux-26.patch; \ ++ ( \ ++ find . -name Makefile; \ ++ find . -name Config.in; \ ++ find . -name Kconfig; \ ++ find . -name README; \ ++ find . -name '*.[ch]' | grep -v '.mod.c'; \ ++ ) | while read t; do \ ++ diff -Nau /dev/null $$t | sed 's?^+++ \./?+++ linux/crypto/ocf/?'; \ ++ done > $$patch; \ ++ cat $$patchbase/patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \ ++ cat $$patchbase/patches/linux-2.6.38-ocf.patch $$patch > $$patch26; \ ++ ++# ++# this target probably does nothing for anyone but me - davidm ++# ++ ++.PHONY: release ++release: ++ REL=`date +%Y%m%d`; RELDIR=/tmp/ocf-linux-$$REL; \ ++ CURDIR=`pwd`; \ ++ rm -rf /tmp/ocf-linux-$$REL*; \ ++ mkdir -p $$RELDIR/ocf; \ ++ mkdir -p $$RELDIR/patches; \ ++ mkdir -p $$RELDIR/crypto-tools; \ ++ cp README* $$RELDIR/.; \ ++ cp patches/[!C]* $$RELDIR/patches/.; \ ++ cp tools/[!C]* $$RELDIR/crypto-tools/.; \ ++ cp -r [!C]* Config.in $$RELDIR/ocf/.; \ ++ rm -rf $$RELDIR/ocf/patches $$RELDIR/ocf/tools; \ ++ rm -f $$RELDIR/ocf/README*; \ ++ cp $$CURDIR/../../user/crypto-tools/[!C]* $$RELDIR/crypto-tools/.; \ ++ make -C $$RELDIR/crypto-tools clean; \ ++ make -C $$RELDIR/ocf clean; \ ++ find $$RELDIR/ocf -name CVS | xargs rm -rf; \ ++ cd $$RELDIR/..; \ ++ tar cvf ocf-linux-$$REL.tar ocf-linux-$$REL; \ ++ gzip -9 ocf-linux-$$REL.tar ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/c7108/Makefile linux-3.0.4/crypto/ocf/c7108/Makefile +--- linux-3.0.4.orig/crypto/ocf/c7108/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/c7108/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_C7108) += aes-7108.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.c linux-3.0.4/crypto/ocf/c7108/aes-7108.c +--- linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/c7108/aes-7108.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,839 @@ ++/* ++ * Copyright (C) 2006 Micronas USA ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Runtime mode */ ++static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; ++//static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; ++ ++static int32_t c7108_id = -1; ++static struct cipher_7108 **c7108_sessions = NULL; ++static u_int32_t c7108_sesnum = 0; ++static unsigned long iobar; ++ ++/* Crypto entry points */ ++static int c7108_process(void *, struct cryptop *, int); ++static int c7108_newsession(void *, u_int32_t *, struct cryptoini *); ++static int c7108_freesession(void *, u_int64_t); ++ ++/* Globals */ ++static int debug = 0; ++static spinlock_t csr_mutex; ++ ++/* Generic controller-based lock */ ++#define AES_LOCK()\ ++ spin_lock(&csr_mutex) ++#define AES_UNLOCK()\ ++ spin_unlock(&csr_mutex) ++ ++/* 7108 AES register access */ ++#define c7108_reg_wr8(a,d) iowrite8(d, (void*)(iobar+(a))) ++#define c7108_reg_wr16(a,d) iowrite16(d, (void*)(iobar+(a))) ++#define c7108_reg_wr32(a,d) iowrite32(d, (void*)(iobar+(a))) ++#define c7108_reg_rd8(a) ioread8((void*)(iobar+(a))) ++#define c7108_reg_rd16(a) ioread16((void*)(iobar+(a))) ++#define c7108_reg_rd32(a) ioread32((void*)(iobar+(a))) ++ ++static int ++c7108_xlate_key(int klen, u8* k8ptr, u32* k32ptr) ++{ ++ int i, nw=0; ++ nw = ((klen >= 256) ? 8 : (klen >= 192) ? 6 : 4); ++ for ( i = 0; i < nw; i++) { ++ k32ptr[i] = (k8ptr[i+3] << 24) | (k8ptr[i+2] << 16) | ++ (k8ptr[i+1] << 8) | k8ptr[i]; ++ ++ } ++ return 0; ++} ++ ++static int ++c7108_cache_key(int klen, u32* k32ptr, u8* k8ptr) ++{ ++ int i, nb=0; ++ u8* ptr = (u8*)k32ptr; ++ nb = ((klen >= 256) ? 32 : (klen >= 192) ? 24 : 16); ++ for ( i = 0; i < nb; i++) ++ k8ptr[i] = ptr[i]; ++ return 0; ++} ++ ++static int ++c7108_aes_setup_dma(u32 src, u32 dst, u32 len) ++{ ++ if (len < 16) { ++ printk("len < 16\n"); ++ return -10; ++ } ++ if (len % 16) { ++ printk("len not multiple of 16\n"); ++ return -11; ++ } ++ c7108_reg_wr16(C7108_AES_DMA_SRC0_LO, (u16) src); ++ c7108_reg_wr16(C7108_AES_DMA_SRC0_HI, (u16)((src & 0xffff0000) >> 16)); ++ c7108_reg_wr16(C7108_AES_DMA_DST0_LO, (u16) dst); ++ c7108_reg_wr16(C7108_AES_DMA_DST0_HI, (u16)((dst & 0xffff0000) >> 16)); ++ c7108_reg_wr16(C7108_AES_DMA_LEN, (u16) ((len / 16) - 1)); ++ ++ return 0; ++} ++ ++static int ++c7108_aes_set_hw_iv(u8 iv[16]) ++{ ++ c7108_reg_wr16(C7108_AES_IV0_LO, (u16) ((iv[1] << 8) | iv[0])); ++ c7108_reg_wr16(C7108_AES_IV0_HI, (u16) ((iv[3] << 8) | iv[2])); ++ c7108_reg_wr16(C7108_AES_IV1_LO, (u16) ((iv[5] << 8) | iv[4])); ++ c7108_reg_wr16(C7108_AES_IV1_HI, (u16) ((iv[7] << 8) | iv[6])); ++ c7108_reg_wr16(C7108_AES_IV2_LO, (u16) ((iv[9] << 8) | iv[8])); ++ c7108_reg_wr16(C7108_AES_IV2_HI, (u16) ((iv[11] << 8) | iv[10])); ++ c7108_reg_wr16(C7108_AES_IV3_LO, (u16) ((iv[13] << 8) | iv[12])); ++ c7108_reg_wr16(C7108_AES_IV3_HI, (u16) ((iv[15] << 8) | iv[14])); ++ ++ return 0; ++} ++ ++static void ++c7108_aes_read_dkey(u32 * dkey) ++{ ++ dkey[0] = (c7108_reg_rd16(C7108_AES_EKEY0_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY0_LO); ++ dkey[1] = (c7108_reg_rd16(C7108_AES_EKEY1_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY1_LO); ++ dkey[2] = (c7108_reg_rd16(C7108_AES_EKEY2_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY2_LO); ++ dkey[3] = (c7108_reg_rd16(C7108_AES_EKEY3_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY3_LO); ++ dkey[4] = (c7108_reg_rd16(C7108_AES_EKEY4_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY4_LO); ++ dkey[5] = (c7108_reg_rd16(C7108_AES_EKEY5_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY5_LO); ++ dkey[6] = (c7108_reg_rd16(C7108_AES_EKEY6_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY6_LO); ++ dkey[7] = (c7108_reg_rd16(C7108_AES_EKEY7_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY7_LO); ++} ++ ++static int ++c7108_aes_cipher(int op, ++ u32 dst, ++ u32 src, ++ u32 len, ++ int klen, ++ u16 mode, ++ u32 key[8], ++ u8 iv[16]) ++{ ++ int rv = 0, cnt=0; ++ u16 ctrl = 0, stat = 0; ++ ++ AES_LOCK(); ++ ++ /* Setup key length */ ++ if (klen == 128) { ++ ctrl |= C7108_AES_KEY_LEN_128; ++ } else if (klen == 192) { ++ ctrl |= C7108_AES_KEY_LEN_192; ++ } else if (klen == 256) { ++ ctrl |= C7108_AES_KEY_LEN_256; ++ } else { ++ AES_UNLOCK(); ++ return -3; ++ } ++ ++ /* Check opcode */ ++ if (C7108_AES_ENCRYPT == op) { ++ ctrl |= C7108_AES_ENCRYPT; ++ } else if (C7108_AES_DECRYPT == op) { ++ ctrl |= C7108_AES_DECRYPT; ++ } else { ++ AES_UNLOCK(); ++ return -4; ++ } ++ ++ /* check mode */ ++ if ( (mode != C7108_AES_CTRL_MODE_CBC) && ++ (mode != C7108_AES_CTRL_MODE_CFB) && ++ (mode != C7108_AES_CTRL_MODE_OFB) && ++ (mode != C7108_AES_CTRL_MODE_CTR) && ++ (mode != C7108_AES_CTRL_MODE_ECB) ) { ++ AES_UNLOCK(); ++ return -5; ++ } ++ ++ /* Now set mode */ ++ ctrl |= mode; ++ ++ /* For CFB, OFB, and CTR, neither backward key ++ * expansion nor key inversion is required. ++ */ ++ if ( (C7108_AES_DECRYPT == op) && ++ (C7108_AES_CTRL_MODE_CBC == mode || ++ C7108_AES_CTRL_MODE_ECB == mode ) ){ ++ ++ /* Program Key */ ++ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[4]); ++ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[4] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[5]); ++ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[5] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[6]); ++ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[6] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[7] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[2]); ++ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[2] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[3]); ++ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[3] >> 16)); ++ ++ ++ if (192 == klen) { ++ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[7] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[7] >> 16)); ++ ++ } else if (256 == klen) { ++ /* 256 */ ++ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[0]); ++ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[0] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[1]); ++ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[1] >> 16)); ++ ++ } ++ ++ } else { ++ /* Program Key */ ++ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[0]); ++ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[0] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[1]); ++ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[1] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[2]); ++ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[2] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[3]); ++ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[3] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[4]); ++ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[4] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[5]); ++ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[5] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[6]); ++ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[6] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[7] >> 16)); ++ ++ } ++ ++ /* Set IV always */ ++ c7108_aes_set_hw_iv(iv); ++ ++ /* Program DMA addresses */ ++ if ((rv = c7108_aes_setup_dma(src, dst, len)) < 0) { ++ AES_UNLOCK(); ++ return rv; ++ } ++ ++ ++ /* Start AES cipher */ ++ c7108_reg_wr16(C7108_AES_CTRL, ctrl | C7108_AES_GO); ++ ++ //printk("Ctrl: 0x%x\n", ctrl | C7108_AES_GO); ++ do { ++ /* TODO: interrupt mode */ ++ // printk("aes_stat=0x%x\n", stat); ++ //udelay(100); ++ } while ((cnt++ < 1000000) && ++ !((stat=c7108_reg_rd16(C7108_AES_CTRL))&C7108_AES_OP_DONE)); ++ ++ ++ if ((mode == C7108_AES_CTRL_MODE_ECB)|| ++ (mode == C7108_AES_CTRL_MODE_CBC)) { ++ /* Save out key when the lock is held ... */ ++ c7108_aes_read_dkey(key); ++ } ++ ++ AES_UNLOCK(); ++ return 0; ++ ++} ++ ++/* ++ * Generate a new crypto device session. ++ */ ++static int ++c7108_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct cipher_7108 **swd; ++ u_int32_t i; ++ char *algo; ++ int mode, xfm_type; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (c7108_sessions) { ++ for (i = 1; i < c7108_sesnum; i++) ++ if (c7108_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (c7108_sessions == NULL || i == c7108_sesnum) { ++ if (c7108_sessions == NULL) { ++ i = 1; /* We leave c7108_sessions[0] empty */ ++ c7108_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ c7108_sesnum *= 2; ++ ++ swd = kmalloc(c7108_sesnum * sizeof(struct cipher_7108 *), ++ GFP_ATOMIC); ++ if (swd == NULL) { ++ /* Reset session number */ ++ if (c7108_sesnum == CRYPTO_SW_SESSIONS) ++ c7108_sesnum = 0; ++ else ++ c7108_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(swd, 0, c7108_sesnum * sizeof(struct cipher_7108 *)); ++ ++ /* Copy existing sessions */ ++ if (c7108_sessions) { ++ memcpy(swd, c7108_sessions, ++ (c7108_sesnum / 2) * sizeof(struct cipher_7108 *)); ++ kfree(c7108_sessions); ++ } ++ ++ c7108_sessions = swd; ++ ++ } ++ ++ swd = &c7108_sessions[i]; ++ *sid = i; ++ ++ while (cri) { ++ *swd = (struct cipher_7108 *) ++ kmalloc(sizeof(struct cipher_7108), GFP_ATOMIC); ++ if (*swd == NULL) { ++ c7108_freesession(NULL, i); ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(*swd, 0, sizeof(struct cipher_7108)); ++ ++ algo = NULL; ++ mode = 0; ++ xfm_type = HW_TYPE_CIPHER; ++ ++ switch (cri->cri_alg) { ++ ++ case CRYPTO_AES_CBC: ++ algo = "aes"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; ++ break; ++#if 0 ++ case CRYPTO_AES_CTR: ++ algo = "aes_ctr"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; ++ break; ++ case CRYPTO_AES_ECB: ++ algo = "aes_ecb"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_ECB; ++ break; ++ case CRYPTO_AES_OFB: ++ algo = "aes_ofb"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_OFB; ++ break; ++ case CRYPTO_AES_CFB: ++ algo = "aes_cfb"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_CFB; ++ break; ++#endif ++ default: ++ printk("unsupported crypto algorithm: %d\n", ++ cri->cri_alg); ++ return -EINVAL; ++ break; ++ } ++ ++ ++ if (!algo || !*algo) { ++ printk("cypher_7108_crypto: Unknown algo 0x%x\n", ++ cri->cri_alg); ++ c7108_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ if (xfm_type == HW_TYPE_CIPHER) { ++ if (debug) { ++ dprintk("%s key:", __FUNCTION__); ++ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) ++ dprintk("%s0x%02x", (i % 8) ? " " : "\n ", ++ cri->cri_key[i]); ++ dprintk("\n"); ++ } ++ ++ } else if (xfm_type == SW_TYPE_HMAC || ++ xfm_type == SW_TYPE_HASH) { ++ printk("cypher_7108_crypto: HMAC unsupported!\n"); ++ return -EINVAL; ++ c7108_freesession(NULL, i); ++ } else { ++ printk("cypher_7108_crypto: " ++ "Unhandled xfm_type %d\n", xfm_type); ++ c7108_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ (*swd)->cri_alg = cri->cri_alg; ++ (*swd)->xfm_type = xfm_type; ++ ++ cri = cri->cri_next; ++ swd = &((*swd)->next); ++ } ++ return 0; ++} ++ ++/* ++ * Free a session. ++ */ ++static int ++c7108_freesession(void *arg, u_int64_t tid) ++{ ++ struct cipher_7108 *swd; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > c7108_sesnum || c7108_sessions == NULL || ++ c7108_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ while ((swd = c7108_sessions[sid]) != NULL) { ++ c7108_sessions[sid] = swd->next; ++ kfree(swd); ++ } ++ return 0; ++} ++ ++/* ++ * Process a hardware request. ++ */ ++static int ++c7108_process(void *arg, struct cryptop *crp, int hint) ++{ ++ struct cryptodesc *crd; ++ struct cipher_7108 *sw; ++ u_int32_t lid; ++ int type; ++ u32 hwkey[8]; ++ ++#define SCATTERLIST_MAX 16 ++ struct scatterlist sg[SCATTERLIST_MAX]; ++ int sg_num, sg_len, skip; ++ struct sk_buff *skb = NULL; ++ struct uio *uiop = NULL; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= c7108_sesnum || lid == 0 || c7108_sessions == NULL || ++ c7108_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ /* ++ * do some error checking outside of the loop for SKB and IOV ++ * processing this leaves us with valid skb or uiop pointers ++ * for later ++ */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ skb = (struct sk_buff *) crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { ++ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", ++ __FILE__, __LINE__, ++ skb_shinfo(skb)->nr_frags); ++ goto done; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ uiop = (struct uio *) crp->crp_buf; ++ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { ++ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", ++ __FILE__, __LINE__, ++ uiop->uio_iovcnt); ++ goto done; ++ } ++ } ++ ++ /* Go through crypto descriptors, processing as we go */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ /* ++ * Find the crypto context. ++ * ++ * XXX Note that the logic here prevents us from having ++ * XXX the same algorithm multiple times in a session ++ * XXX (or rather, we can but it won't give us the right ++ * XXX results). To do that, we'd need some way of differentiating ++ * XXX between the various instances of an algorithm (so we can ++ * XXX locate the correct crypto context). ++ */ ++ for (sw = c7108_sessions[lid]; ++ sw && sw->cri_alg != crd->crd_alg; ++ sw = sw->next) ++ ; ++ ++ /* No such context ? */ ++ if (sw == NULL) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ skip = crd->crd_skip; ++ ++ /* ++ * setup the SG list skip from the start of the buffer ++ */ ++ memset(sg, 0, sizeof(sg)); ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ int i, len; ++ type = CRYPTO_BUF_SKBUF; ++ ++ sg_num = 0; ++ sg_len = 0; ++ ++ if (skip < skb_headlen(skb)) { ++ //sg[sg_num].page = virt_to_page(skb->data + skip); ++ //sg[sg_num].offset = offset_in_page(skb->data + skip); ++ len = skb_headlen(skb) - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ //sg[sg_num].length = len; ++ sg_set_page(&sg[sg_num], virt_to_page(skb->data + skip), len, offset_in_page(skb->data + skip)); ++ sg_len += sg[sg_num].length; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_headlen(skb); ++ ++ for (i = 0; sg_len < crd->crd_len && ++ i < skb_shinfo(skb)->nr_frags && ++ sg_num < SCATTERLIST_MAX; i++) { ++ if (skip < skb_shinfo(skb)->frags[i].size) { ++ //sg[sg_num].page = skb_shinfo(skb)->frags[i].page; ++ //sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip; ++ len = skb_shinfo(skb)->frags[i].size - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ //sg[sg_num].length = len; ++ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, len, skb_shinfo(skb)->frags[i].page_offset + skip); ++ sg_len += sg[sg_num].length; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_shinfo(skb)->frags[i].size; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ int len; ++ type = CRYPTO_BUF_IOV; ++ sg_len = 0; ++ for (sg_num = 0; sg_len < crd->crd_len && ++ sg_num < uiop->uio_iovcnt && ++ sg_num < SCATTERLIST_MAX; sg_num++) { ++ if (skip < uiop->uio_iov[sg_num].iov_len) { ++ //sg[sg_num].page = virt_to_page(uiop->uio_iov[sg_num].iov_base+skip); ++ //sg[sg_num].offset = offset_in_page(uiop->uio_iov[sg_num].iov_base+skip); ++ len = uiop->uio_iov[sg_num].iov_len - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ //sg[sg_num].length = len; ++ sg_set_page(&sg[sg_num], virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), len, offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); ++ sg_len += sg[sg_num].length; ++ skip = 0; ++ } else ++ skip -= uiop->uio_iov[sg_num].iov_len; ++ } ++ } else { ++ type = CRYPTO_BUF_CONTIG; ++ //sg[0].page = virt_to_page(crp->crp_buf + skip); ++ //sg[0].offset = offset_in_page(crp->crp_buf + skip); ++ sg_len = (crp->crp_ilen - skip); ++ if (sg_len > crd->crd_len) ++ sg_len = crd->crd_len; ++ //sg[0].length = sg_len; ++ sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip)); ++ sg_num = 1; ++ } ++ ++ ++ switch (sw->xfm_type) { ++ ++ case HW_TYPE_CIPHER: { ++ ++ unsigned char iv[64]; ++ unsigned char *ivp = iv; ++ int i; ++ int ivsize = 16; /* fixed for AES */ ++ int blocksize = 16; /* fixed for AES */ ++ ++ if (sg_len < blocksize) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL len %d < %d\n", ++ __FILE__, __LINE__, ++ sg_len, ++ blocksize); ++ goto done; ++ } ++ ++ if (ivsize > sizeof(iv)) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ get_random_bytes(ivp, ivsize); ++ } ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_buf, ++ crd->crd_inject, ++ ivsize, ++ (caddr_t)ivp); ++ } ++ ++ c7108_xlate_key(crd->crd_klen, ++ (u8*)crd->crd_key, (u32*)hwkey); ++ ++ /* Encrypt SG list */ ++ for (i = 0; i < sg_num; i++) { ++ sg[i].dma_address = ++ dma_map_single(NULL, ++ kmap(sg_page(&sg[i])) + sg[i].offset, sg_len, DMA_BIDIRECTIONAL); ++#if 0 ++ printk("sg[%d]:0x%08x, off 0x%08x " ++ "kmap 0x%08x phys 0x%08x\n", ++ i, sg[i].page, sg[i].offset, ++ kmap(sg[i].page) + sg[i].offset, ++ sg[i].dma_address); ++#endif ++ c7108_aes_cipher(C7108_AES_ENCRYPT, ++ sg[i].dma_address, ++ sg[i].dma_address, ++ sg_len, ++ crd->crd_klen, ++ c7108_crypto_mode, ++ hwkey, ++ ivp); ++ ++ if ((c7108_crypto_mode == C7108_AES_CTRL_MODE_CBC)|| ++ (c7108_crypto_mode == C7108_AES_CTRL_MODE_ECB)) { ++ /* Read back expanded key and cache it in key ++ * context. ++ * NOTE: for ECB/CBC modes only (not CTR, CFB, OFB) ++ * where you set the key once. ++ */ ++ c7108_cache_key(crd->crd_klen, ++ (u32*)hwkey, (u8*)crd->crd_key); ++#if 0 ++ printk("%s expanded key:", __FUNCTION__); ++ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) ++ printk("%s0x%02x", (i % 8) ? " " : "\n ", ++ crd->crd_key[i]); ++ printk("\n"); ++#endif ++ } ++ } ++ } ++ else { /*decrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ crypto_copydata(crp->crp_buf, crd->crd_inject, ++ ivsize, (caddr_t)ivp); ++ } ++ ++ c7108_xlate_key(crd->crd_klen, ++ (u8*)crd->crd_key, (u32*)hwkey); ++ ++ /* Decrypt SG list */ ++ for (i = 0; i < sg_num; i++) { ++ sg[i].dma_address = ++ dma_map_single(NULL, ++ kmap(sg_page(&sg[i])) + sg[i].offset, ++ sg_len, DMA_BIDIRECTIONAL); ++ ++#if 0 ++ printk("sg[%d]:0x%08x, off 0x%08x " ++ "kmap 0x%08x phys 0x%08x\n", ++ i, sg[i].page, sg[i].offset, ++ kmap(sg[i].page) + sg[i].offset, ++ sg[i].dma_address); ++#endif ++ c7108_aes_cipher(C7108_AES_DECRYPT, ++ sg[i].dma_address, ++ sg[i].dma_address, ++ sg_len, ++ crd->crd_klen, ++ c7108_crypto_mode, ++ hwkey, ++ ivp); ++ } ++ } ++ } break; ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ crp->crp_etype = EINVAL; ++ goto done; ++ break; ++ ++ case SW_TYPE_COMP: ++ crp->crp_etype = EINVAL; ++ goto done; ++ break; ++ ++ default: ++ /* Unknown/unsupported algorithm */ ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ } ++ ++done: ++ crypto_done(crp); ++ return 0; ++} ++ ++static struct { ++ softc_device_decl sc_dev; ++} a7108dev; ++ ++static device_method_t a7108_methods = { ++/* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, c7108_newsession), ++ DEVMETHOD(cryptodev_freesession, c7108_freesession), ++ DEVMETHOD(cryptodev_process, c7108_process), ++ DEVMETHOD(cryptodev_kprocess, NULL) ++}; ++ ++static int ++cypher_7108_crypto_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, cypher_7108_crypto_init); ++ ++ iobar = (unsigned long)ioremap(CCU_AES_REG_BASE, 0x4000); ++ printk("7108: AES @ 0x%08x (0x%08x phys) %s mode\n", ++ iobar, CCU_AES_REG_BASE, ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_CBC ? "CBC" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_ECB ? "ECB" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_CTR ? "CTR" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_CFB ? "CFB" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_OFB ? "OFB" : "???"); ++ csr_mutex = SPIN_LOCK_UNLOCKED; ++ ++ memset(&a7108dev, 0, sizeof(a7108dev)); ++ softc_device_init(&a7108dev, "aes7108", 0, a7108_methods); ++ ++ c7108_id = crypto_get_driverid(softc_get_device(&a7108dev), CRYPTOCAP_F_HARDWARE); ++ if (c7108_id < 0) ++ panic("7108: crypto device cannot initialize!"); ++ ++// crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0, c7108_newsession, c7108_freesession, c7108_process, NULL); ++ crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0); ++ ++ return(0); ++} ++ ++static void ++cypher_7108_crypto_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(c7108_id); ++ c7108_id = -1; ++} ++ ++module_init(cypher_7108_crypto_init); ++module_exit(cypher_7108_crypto_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_DESCRIPTION("Cypher 7108 Crypto (OCF module for kernel crypto)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.h linux-3.0.4/crypto/ocf/c7108/aes-7108.h +--- linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/c7108/aes-7108.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,134 @@ ++/* ++ * Copyright (C) 2006 Micronas USA ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++#ifndef __AES_7108_H__ ++#define __AES_7108_H__ ++ ++/* Cypher 7108 AES Controller Hardware */ ++#define CCU_REG_BASE 0x1b500000 ++#define CCU_AES_REG_BASE (CCU_REG_BASE + 0x100) ++#define C7108_AES_KEY0_LO (0x0000) ++#define C7108_AES_KEY0_HI (0x0004) ++#define C7108_AES_KEY1_LO (0x0008) ++#define C7108_AES_KEY1_HI (0x000c) ++#define C7108_AES_KEY2_LO (0x0010) ++#define C7108_AES_KEY2_HI (0x0014) ++#define C7108_AES_KEY3_LO (0x0018) ++#define C7108_AES_KEY3_HI (0x001c) ++#define C7108_AES_KEY4_LO (0x0020) ++#define C7108_AES_KEY4_HI (0x0024) ++#define C7108_AES_KEY5_LO (0x0028) ++#define C7108_AES_KEY5_HI (0x002c) ++#define C7108_AES_KEY6_LO (0x0030) ++#define C7108_AES_KEY6_HI (0x0034) ++#define C7108_AES_KEY7_LO (0x0038) ++#define C7108_AES_KEY7_HI (0x003c) ++#define C7108_AES_IV0_LO (0x0040) ++#define C7108_AES_IV0_HI (0x0044) ++#define C7108_AES_IV1_LO (0x0048) ++#define C7108_AES_IV1_HI (0x004c) ++#define C7108_AES_IV2_LO (0x0050) ++#define C7108_AES_IV2_HI (0x0054) ++#define C7108_AES_IV3_LO (0x0058) ++#define C7108_AES_IV3_HI (0x005c) ++ ++#define C7108_AES_DMA_SRC0_LO (0x0068) /* Bits 0:15 */ ++#define C7108_AES_DMA_SRC0_HI (0x006c) /* Bits 27:16 */ ++#define C7108_AES_DMA_DST0_LO (0x0070) /* Bits 0:15 */ ++#define C7108_AES_DMA_DST0_HI (0x0074) /* Bits 27:16 */ ++#define C7108_AES_DMA_LEN (0x0078) /*Bytes:(Count+1)x16 */ ++ ++/* AES/Copy engine control register */ ++#define C7108_AES_CTRL (0x007c) /* AES control */ ++#define C7108_AES_CTRL_RS (1<<0) /* Which set of src/dst to use */ ++ ++/* AES Cipher mode, controlled by setting Bits 2:0 */ ++#define C7108_AES_CTRL_MODE_CBC 0 ++#define C7108_AES_CTRL_MODE_CFB (1<<0) ++#define C7108_AES_CTRL_MODE_OFB (1<<1) ++#define C7108_AES_CTRL_MODE_CTR ((1<<0)|(1<<1)) ++#define C7108_AES_CTRL_MODE_ECB (1<<2) ++ ++/* AES Key length , Bits 5:4 */ ++#define C7108_AES_KEY_LEN_128 0 /* 00 */ ++#define C7108_AES_KEY_LEN_192 (1<<4) /* 01 */ ++#define C7108_AES_KEY_LEN_256 (1<<5) /* 10 */ ++ ++/* AES Operation (crypt/decrypt), Bit 3 */ ++#define C7108_AES_DECRYPT (1<<3) /* Clear for encrypt */ ++#define C7108_AES_ENCRYPT 0 ++#define C7108_AES_INTR (1<<13) /* Set on done trans from 0->1*/ ++#define C7108_AES_GO (1<<14) /* Run */ ++#define C7108_AES_OP_DONE (1<<15) /* Set when complete */ ++ ++ ++/* Expanded key registers */ ++#define C7108_AES_EKEY0_LO (0x0080) ++#define C7108_AES_EKEY0_HI (0x0084) ++#define C7108_AES_EKEY1_LO (0x0088) ++#define C7108_AES_EKEY1_HI (0x008c) ++#define C7108_AES_EKEY2_LO (0x0090) ++#define C7108_AES_EKEY2_HI (0x0094) ++#define C7108_AES_EKEY3_LO (0x0098) ++#define C7108_AES_EKEY3_HI (0x009c) ++#define C7108_AES_EKEY4_LO (0x00a0) ++#define C7108_AES_EKEY4_HI (0x00a4) ++#define C7108_AES_EKEY5_LO (0x00a8) ++#define C7108_AES_EKEY5_HI (0x00ac) ++#define C7108_AES_EKEY6_LO (0x00b0) ++#define C7108_AES_EKEY6_HI (0x00b4) ++#define C7108_AES_EKEY7_LO (0x00b8) ++#define C7108_AES_EKEY7_HI (0x00bc) ++#define C7108_AES_OK (0x00fc) /* Reset: "OK" */ ++ ++#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) ++ ++/* Software session entry */ ++ ++#define HW_TYPE_CIPHER 0 ++#define SW_TYPE_HMAC 1 ++#define SW_TYPE_AUTH2 2 ++#define SW_TYPE_HASH 3 ++#define SW_TYPE_COMP 4 ++ ++struct cipher_7108 { ++ int xfm_type; ++ int cri_alg; ++ union { ++ struct { ++ char sw_key[HMAC_BLOCK_LEN]; ++ int sw_klen; ++ int sw_authlen; ++ } hmac; ++ } u; ++ struct cipher_7108 *next; ++}; ++ ++ ++ ++#endif /* __C7108_AES_7108_H__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/criov.c linux-3.0.4/crypto/ocf/criov.c +--- linux-3.0.4.orig/crypto/ocf/criov.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/criov.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,216 @@ ++/* $OpenBSD: criov.c,v 1.9 2002/01/29 15:48:29 jason Exp $ */ ++ ++/* ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 1999 Theo de Raadt ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++__FBSDID("$FreeBSD: src/sys/opencrypto/criov.c,v 1.5 2006/06/04 22:15:13 pjd Exp $"); ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/* ++ * This macro is only for avoiding code duplication, as we need to skip ++ * given number of bytes in the same way in three functions below. ++ */ ++#define CUIO_SKIP() do { \ ++ KASSERT(off >= 0, ("%s: off %d < 0", __func__, off)); \ ++ KASSERT(len >= 0, ("%s: len %d < 0", __func__, len)); \ ++ while (off > 0) { \ ++ KASSERT(iol >= 0, ("%s: empty in skip", __func__)); \ ++ if (off < iov->iov_len) \ ++ break; \ ++ off -= iov->iov_len; \ ++ iol--; \ ++ iov++; \ ++ } \ ++} while (0) ++ ++void ++cuio_copydata(struct uio* uio, int off, int len, caddr_t cp) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int iol = uio->uio_iovcnt; ++ unsigned count; ++ ++ CUIO_SKIP(); ++ while (len > 0) { ++ KASSERT(iol >= 0, ("%s: empty", __func__)); ++ count = min((int)(iov->iov_len - off), len); ++ memcpy(cp, ((caddr_t)iov->iov_base) + off, count); ++ len -= count; ++ cp += count; ++ off = 0; ++ iol--; ++ iov++; ++ } ++} ++ ++void ++cuio_copyback(struct uio* uio, int off, int len, caddr_t cp) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int iol = uio->uio_iovcnt; ++ unsigned count; ++ ++ CUIO_SKIP(); ++ while (len > 0) { ++ KASSERT(iol >= 0, ("%s: empty", __func__)); ++ count = min((int)(iov->iov_len - off), len); ++ memcpy(((caddr_t)iov->iov_base) + off, cp, count); ++ len -= count; ++ cp += count; ++ off = 0; ++ iol--; ++ iov++; ++ } ++} ++ ++/* ++ * Return a pointer to iov/offset of location in iovec list. ++ */ ++struct iovec * ++cuio_getptr(struct uio *uio, int loc, int *off) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int iol = uio->uio_iovcnt; ++ ++ while (loc >= 0) { ++ /* Normal end of search */ ++ if (loc < iov->iov_len) { ++ *off = loc; ++ return (iov); ++ } ++ ++ loc -= iov->iov_len; ++ if (iol == 0) { ++ if (loc == 0) { ++ /* Point at the end of valid data */ ++ *off = iov->iov_len; ++ return (iov); ++ } else ++ return (NULL); ++ } else { ++ iov++, iol--; ++ } ++ } ++ ++ return (NULL); ++} ++ ++EXPORT_SYMBOL(cuio_copyback); ++EXPORT_SYMBOL(cuio_copydata); ++EXPORT_SYMBOL(cuio_getptr); ++ ++ ++static void ++skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len) ++{ ++ int i; ++ if (offset < skb_headlen(skb)) { ++ memcpy(skb->data + offset, cp, min_t(int, skb_headlen(skb), len)); ++ len -= skb_headlen(skb); ++ cp += skb_headlen(skb); ++ } ++ offset -= skb_headlen(skb); ++ for (i = 0; len > 0 && i < skb_shinfo(skb)->nr_frags; i++) { ++ if (offset < skb_shinfo(skb)->frags[i].size) { ++ memcpy(page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ cp, min_t(int, skb_shinfo(skb)->frags[i].size, len)); ++ len -= skb_shinfo(skb)->frags[i].size; ++ cp += skb_shinfo(skb)->frags[i].size; ++ } ++ offset -= skb_shinfo(skb)->frags[i].size; ++ } ++} ++ ++void ++crypto_copyback(int flags, caddr_t buf, int off, int size, caddr_t in) ++{ ++ ++ if ((flags & CRYPTO_F_SKBUF) != 0) ++ skb_copy_bits_back((struct sk_buff *)buf, off, in, size); ++ else if ((flags & CRYPTO_F_IOV) != 0) ++ cuio_copyback((struct uio *)buf, off, size, in); ++ else ++ bcopy(in, buf + off, size); ++} ++ ++void ++crypto_copydata(int flags, caddr_t buf, int off, int size, caddr_t out) ++{ ++ ++ if ((flags & CRYPTO_F_SKBUF) != 0) ++ skb_copy_bits((struct sk_buff *)buf, off, out, size); ++ else if ((flags & CRYPTO_F_IOV) != 0) ++ cuio_copydata((struct uio *)buf, off, size, out); ++ else ++ bcopy(buf + off, out, size); ++} ++ ++int ++crypto_apply(int flags, caddr_t buf, int off, int len, ++ int (*f)(void *, void *, u_int), void *arg) ++{ ++#if 0 ++ int error; ++ ++ if ((flags & CRYPTO_F_SKBUF) != 0) ++ error = XXXXXX((struct mbuf *)buf, off, len, f, arg); ++ else if ((flags & CRYPTO_F_IOV) != 0) ++ error = cuio_apply((struct uio *)buf, off, len, f, arg); ++ else ++ error = (*f)(arg, buf + off, len); ++ return (error); ++#else ++ KASSERT(0, ("crypto_apply not implemented!\n")); ++#endif ++ return 0; ++} ++ ++EXPORT_SYMBOL(crypto_copyback); ++EXPORT_SYMBOL(crypto_copydata); ++EXPORT_SYMBOL(crypto_apply); ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/crypto.c linux-3.0.4/crypto/ocf/crypto.c +--- linux-3.0.4.orig/crypto/ocf/crypto.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/crypto.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1766 @@ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * Copyright (c) 2002-2006 Sam Leffler. All rights reserved. ++ * ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#if 0 ++#include ++__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.27 2007/03/21 03:42:51 sam Exp $"); ++#endif ++ ++/* ++ * Cryptographic Subsystem. ++ * ++ * This code is derived from the Openbsd Cryptographic Framework (OCF) ++ * that has the copyright shown below. Very little of the original ++ * code remains. ++ */ ++/*- ++ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) ++ * ++ * This code was written by Angelos D. Keromytis in Athens, Greece, in ++ * February 2000. Network Security Technologies Inc. (NSTI) kindly ++ * supported the development of this code. ++ * ++ * Copyright (c) 2000, 2001 Angelos D. Keromytis ++ * ++ * Permission to use, copy, and modify this software with or without fee ++ * is hereby granted, provided that this entire notice is included in ++ * all source code copies of any software which is or includes a copy or ++ * modification of this software. ++ * ++ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY ++ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE ++ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR ++ * PURPOSE. ++ * ++__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.16 2005/01/07 02:29:16 imp Exp $"); ++ */ ++ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,4) ++#include ++#endif ++#include ++ ++/* ++ * keep track of whether or not we have been initialised, a big ++ * issue if we are linked into the kernel and a driver gets started before ++ * us ++ */ ++static int crypto_initted = 0; ++ ++/* ++ * Crypto drivers register themselves by allocating a slot in the ++ * crypto_drivers table with crypto_get_driverid() and then registering ++ * each algorithm they support with crypto_register() and crypto_kregister(). ++ */ ++ ++/* ++ * lock on driver table ++ * we track its state as spin_is_locked does not do anything on non-SMP boxes ++ */ ++static spinlock_t crypto_drivers_lock; ++static int crypto_drivers_locked; /* for non-SMP boxes */ ++ ++#define CRYPTO_DRIVER_LOCK() \ ++ ({ \ ++ spin_lock_irqsave(&crypto_drivers_lock, d_flags); \ ++ crypto_drivers_locked = 1; \ ++ dprintk("%s,%d: DRIVER_LOCK()\n", __FILE__, __LINE__); \ ++ }) ++#define CRYPTO_DRIVER_UNLOCK() \ ++ ({ \ ++ dprintk("%s,%d: DRIVER_UNLOCK()\n", __FILE__, __LINE__); \ ++ crypto_drivers_locked = 0; \ ++ spin_unlock_irqrestore(&crypto_drivers_lock, d_flags); \ ++ }) ++#define CRYPTO_DRIVER_ASSERT() \ ++ ({ \ ++ if (!crypto_drivers_locked) { \ ++ dprintk("%s,%d: DRIVER_ASSERT!\n", __FILE__, __LINE__); \ ++ } \ ++ }) ++ ++/* ++ * Crypto device/driver capabilities structure. ++ * ++ * Synchronization: ++ * (d) - protected by CRYPTO_DRIVER_LOCK() ++ * (q) - protected by CRYPTO_Q_LOCK() ++ * Not tagged fields are read-only. ++ */ ++struct cryptocap { ++ device_t cc_dev; /* (d) device/driver */ ++ u_int32_t cc_sessions; /* (d) # of sessions */ ++ u_int32_t cc_koperations; /* (d) # os asym operations */ ++ /* ++ * Largest possible operator length (in bits) for each type of ++ * encryption algorithm. XXX not used ++ */ ++ u_int16_t cc_max_op_len[CRYPTO_ALGORITHM_MAX + 1]; ++ u_int8_t cc_alg[CRYPTO_ALGORITHM_MAX + 1]; ++ u_int8_t cc_kalg[CRK_ALGORITHM_MAX + 1]; ++ ++ int cc_flags; /* (d) flags */ ++#define CRYPTOCAP_F_CLEANUP 0x80000000 /* needs resource cleanup */ ++ int cc_qblocked; /* (q) symmetric q blocked */ ++ int cc_kqblocked; /* (q) asymmetric q blocked */ ++ ++ int cc_unqblocked; /* (q) symmetric q blocked */ ++ int cc_unkqblocked; /* (q) asymmetric q blocked */ ++}; ++static struct cryptocap *crypto_drivers = NULL; ++static int crypto_drivers_num = 0; ++ ++/* ++ * There are two queues for crypto requests; one for symmetric (e.g. ++ * cipher) operations and one for asymmetric (e.g. MOD)operations. ++ * A single mutex is used to lock access to both queues. We could ++ * have one per-queue but having one simplifies handling of block/unblock ++ * operations. ++ */ ++static LIST_HEAD(crp_q); /* crypto request queue */ ++static LIST_HEAD(crp_kq); /* asym request queue */ ++ ++static spinlock_t crypto_q_lock; ++ ++int crypto_all_qblocked = 0; /* protect with Q_LOCK */ ++module_param(crypto_all_qblocked, int, 0444); ++MODULE_PARM_DESC(crypto_all_qblocked, "Are all crypto queues blocked"); ++ ++int crypto_all_kqblocked = 0; /* protect with Q_LOCK */ ++module_param(crypto_all_kqblocked, int, 0444); ++MODULE_PARM_DESC(crypto_all_kqblocked, "Are all asym crypto queues blocked"); ++ ++#define CRYPTO_Q_LOCK() \ ++ ({ \ ++ spin_lock_irqsave(&crypto_q_lock, q_flags); \ ++ dprintk("%s,%d: Q_LOCK()\n", __FILE__, __LINE__); \ ++ }) ++#define CRYPTO_Q_UNLOCK() \ ++ ({ \ ++ dprintk("%s,%d: Q_UNLOCK()\n", __FILE__, __LINE__); \ ++ spin_unlock_irqrestore(&crypto_q_lock, q_flags); \ ++ }) ++ ++/* ++ * There are two queues for processing completed crypto requests; one ++ * for the symmetric and one for the asymmetric ops. We only need one ++ * but have two to avoid type futzing (cryptop vs. cryptkop). A single ++ * mutex is used to lock access to both queues. Note that this lock ++ * must be separate from the lock on request queues to insure driver ++ * callbacks don't generate lock order reversals. ++ */ ++static LIST_HEAD(crp_ret_q); /* callback queues */ ++static LIST_HEAD(crp_ret_kq); ++ ++static spinlock_t crypto_ret_q_lock; ++#define CRYPTO_RETQ_LOCK() \ ++ ({ \ ++ spin_lock_irqsave(&crypto_ret_q_lock, r_flags); \ ++ dprintk("%s,%d: RETQ_LOCK\n", __FILE__, __LINE__); \ ++ }) ++#define CRYPTO_RETQ_UNLOCK() \ ++ ({ \ ++ dprintk("%s,%d: RETQ_UNLOCK\n", __FILE__, __LINE__); \ ++ spin_unlock_irqrestore(&crypto_ret_q_lock, r_flags); \ ++ }) ++#define CRYPTO_RETQ_EMPTY() (list_empty(&crp_ret_q) && list_empty(&crp_ret_kq)) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++static kmem_cache_t *cryptop_zone; ++static kmem_cache_t *cryptodesc_zone; ++#else ++static struct kmem_cache *cryptop_zone; ++static struct kmem_cache *cryptodesc_zone; ++#endif ++ ++#define debug crypto_debug ++int crypto_debug = 0; ++module_param(crypto_debug, int, 0644); ++MODULE_PARM_DESC(crypto_debug, "Enable debug"); ++EXPORT_SYMBOL(crypto_debug); ++ ++/* ++ * Maximum number of outstanding crypto requests before we start ++ * failing requests. We need this to prevent DOS when too many ++ * requests are arriving for us to keep up. Otherwise we will ++ * run the system out of memory. Since crypto is slow, we are ++ * usually the bottleneck that needs to say, enough is enough. ++ * ++ * We cannot print errors when this condition occurs, we are already too ++ * slow, printing anything will just kill us ++ */ ++ ++static int crypto_q_cnt = 0; ++module_param(crypto_q_cnt, int, 0444); ++MODULE_PARM_DESC(crypto_q_cnt, ++ "Current number of outstanding crypto requests"); ++ ++static int crypto_q_max = 1000; ++module_param(crypto_q_max, int, 0644); ++MODULE_PARM_DESC(crypto_q_max, ++ "Maximum number of outstanding crypto requests"); ++ ++#define bootverbose crypto_verbose ++static int crypto_verbose = 0; ++module_param(crypto_verbose, int, 0644); ++MODULE_PARM_DESC(crypto_verbose, ++ "Enable verbose crypto startup"); ++ ++int crypto_usercrypto = 1; /* userland may do crypto reqs */ ++module_param(crypto_usercrypto, int, 0644); ++MODULE_PARM_DESC(crypto_usercrypto, ++ "Enable/disable user-mode access to crypto support"); ++ ++int crypto_userasymcrypto = 1; /* userland may do asym crypto reqs */ ++module_param(crypto_userasymcrypto, int, 0644); ++MODULE_PARM_DESC(crypto_userasymcrypto, ++ "Enable/disable user-mode access to asymmetric crypto support"); ++ ++int crypto_devallowsoft = 0; /* only use hardware crypto */ ++module_param(crypto_devallowsoft, int, 0644); ++MODULE_PARM_DESC(crypto_devallowsoft, ++ "Enable/disable use of software crypto support"); ++ ++/* ++ * This parameter controls the maximum number of crypto operations to ++ * do consecutively in the crypto kernel thread before scheduling to allow ++ * other processes to run. Without it, it is possible to get into a ++ * situation where the crypto thread never allows any other processes to run. ++ * Default to 1000 which should be less than one second. ++ */ ++static int crypto_max_loopcount = 1000; ++module_param(crypto_max_loopcount, int, 0644); ++MODULE_PARM_DESC(crypto_max_loopcount, ++ "Maximum number of crypto ops to do before yielding to other processes"); ++ ++#ifndef CONFIG_NR_CPUS ++#define CONFIG_NR_CPUS 1 ++#endif ++ ++static struct task_struct *cryptoproc[CONFIG_NR_CPUS]; ++static struct task_struct *cryptoretproc[CONFIG_NR_CPUS]; ++static DECLARE_WAIT_QUEUE_HEAD(cryptoproc_wait); ++static DECLARE_WAIT_QUEUE_HEAD(cryptoretproc_wait); ++ ++static int crypto_proc(void *arg); ++static int crypto_ret_proc(void *arg); ++static int crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint); ++static int crypto_kinvoke(struct cryptkop *krp, int flags); ++static void crypto_exit(void); ++static int crypto_init(void); ++ ++static struct cryptostats cryptostats; ++ ++static struct cryptocap * ++crypto_checkdriver(u_int32_t hid) ++{ ++ if (crypto_drivers == NULL) ++ return NULL; ++ return (hid >= crypto_drivers_num ? NULL : &crypto_drivers[hid]); ++} ++ ++/* ++ * Compare a driver's list of supported algorithms against another ++ * list; return non-zero if all algorithms are supported. ++ */ ++static int ++driver_suitable(const struct cryptocap *cap, const struct cryptoini *cri) ++{ ++ const struct cryptoini *cr; ++ ++ /* See if all the algorithms are supported. */ ++ for (cr = cri; cr; cr = cr->cri_next) ++ if (cap->cc_alg[cr->cri_alg] == 0) ++ return 0; ++ return 1; ++} ++ ++ ++/* ++ * Select a driver for a new session that supports the specified ++ * algorithms and, optionally, is constrained according to the flags. ++ * The algorithm we use here is pretty stupid; just use the ++ * first driver that supports all the algorithms we need. If there ++ * are multiple drivers we choose the driver with the fewest active ++ * sessions. We prefer hardware-backed drivers to software ones. ++ * ++ * XXX We need more smarts here (in real life too, but that's ++ * XXX another story altogether). ++ */ ++static struct cryptocap * ++crypto_select_driver(const struct cryptoini *cri, int flags) ++{ ++ struct cryptocap *cap, *best; ++ int match, hid; ++ ++ CRYPTO_DRIVER_ASSERT(); ++ ++ /* ++ * Look first for hardware crypto devices if permitted. ++ */ ++ if (flags & CRYPTOCAP_F_HARDWARE) ++ match = CRYPTOCAP_F_HARDWARE; ++ else ++ match = CRYPTOCAP_F_SOFTWARE; ++ best = NULL; ++again: ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ cap = &crypto_drivers[hid]; ++ /* ++ * If it's not initialized, is in the process of ++ * going away, or is not appropriate (hardware ++ * or software based on match), then skip. ++ */ ++ if (cap->cc_dev == NULL || ++ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || ++ (cap->cc_flags & match) == 0) ++ continue; ++ ++ /* verify all the algorithms are supported. */ ++ if (driver_suitable(cap, cri)) { ++ if (best == NULL || ++ cap->cc_sessions < best->cc_sessions) ++ best = cap; ++ } ++ } ++ if (best != NULL) ++ return best; ++ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { ++ /* sort of an Algol 68-style for loop */ ++ match = CRYPTOCAP_F_SOFTWARE; ++ goto again; ++ } ++ return best; ++} ++ ++/* ++ * Create a new session. The crid argument specifies a crypto ++ * driver to use or constraints on a driver to select (hardware ++ * only, software only, either). Whatever driver is selected ++ * must be capable of the requested crypto algorithms. ++ */ ++int ++crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int crid) ++{ ++ struct cryptocap *cap; ++ u_int32_t hid, lid; ++ int err; ++ unsigned long d_flags; ++ ++ CRYPTO_DRIVER_LOCK(); ++ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { ++ /* ++ * Use specified driver; verify it is capable. ++ */ ++ cap = crypto_checkdriver(crid); ++ if (cap != NULL && !driver_suitable(cap, cri)) ++ cap = NULL; ++ } else { ++ /* ++ * No requested driver; select based on crid flags. ++ */ ++ cap = crypto_select_driver(cri, crid); ++ /* ++ * if NULL then can't do everything in one session. ++ * XXX Fix this. We need to inject a "virtual" session ++ * XXX layer right about here. ++ */ ++ } ++ if (cap != NULL) { ++ /* Call the driver initialization routine. */ ++ hid = cap - crypto_drivers; ++ lid = hid; /* Pass the driver ID. */ ++ cap->cc_sessions++; ++ CRYPTO_DRIVER_UNLOCK(); ++ err = CRYPTODEV_NEWSESSION(cap->cc_dev, &lid, cri); ++ CRYPTO_DRIVER_LOCK(); ++ if (err == 0) { ++ (*sid) = (cap->cc_flags & 0xff000000) ++ | (hid & 0x00ffffff); ++ (*sid) <<= 32; ++ (*sid) |= (lid & 0xffffffff); ++ } else ++ cap->cc_sessions--; ++ } else ++ err = EINVAL; ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++static void ++crypto_remove(struct cryptocap *cap) ++{ ++ CRYPTO_DRIVER_ASSERT(); ++ if (cap->cc_sessions == 0 && cap->cc_koperations == 0) ++ bzero(cap, sizeof(*cap)); ++} ++ ++/* ++ * Delete an existing session (or a reserved session on an unregistered ++ * driver). ++ */ ++int ++crypto_freesession(u_int64_t sid) ++{ ++ struct cryptocap *cap; ++ u_int32_t hid; ++ int err = 0; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ ++ if (crypto_drivers == NULL) { ++ err = EINVAL; ++ goto done; ++ } ++ ++ /* Determine two IDs. */ ++ hid = CRYPTO_SESID2HID(sid); ++ ++ if (hid >= crypto_drivers_num) { ++ dprintk("%s - INVALID DRIVER NUM %d\n", __FUNCTION__, hid); ++ err = ENOENT; ++ goto done; ++ } ++ cap = &crypto_drivers[hid]; ++ ++ if (cap->cc_dev) { ++ CRYPTO_DRIVER_UNLOCK(); ++ /* Call the driver cleanup routine, if available, unlocked. */ ++ err = CRYPTODEV_FREESESSION(cap->cc_dev, sid); ++ CRYPTO_DRIVER_LOCK(); ++ } ++ ++ if (cap->cc_sessions) ++ cap->cc_sessions--; ++ ++ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) ++ crypto_remove(cap); ++ ++done: ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++/* ++ * Return an unused driver id. Used by drivers prior to registering ++ * support for the algorithms they handle. ++ */ ++int32_t ++crypto_get_driverid(device_t dev, int flags) ++{ ++ struct cryptocap *newdrv; ++ int i; ++ unsigned long d_flags; ++ ++ if ((flags & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { ++ printf("%s: no flags specified when registering driver\n", ++ device_get_nameunit(dev)); ++ return -1; ++ } ++ ++ CRYPTO_DRIVER_LOCK(); ++ ++ for (i = 0; i < crypto_drivers_num; i++) { ++ if (crypto_drivers[i].cc_dev == NULL && ++ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP) == 0) { ++ break; ++ } ++ } ++ ++ /* Out of entries, allocate some more. */ ++ if (i == crypto_drivers_num) { ++ /* Be careful about wrap-around. */ ++ if (2 * crypto_drivers_num <= crypto_drivers_num) { ++ CRYPTO_DRIVER_UNLOCK(); ++ printk("crypto: driver count wraparound!\n"); ++ return -1; ++ } ++ ++ newdrv = kmalloc(2 * crypto_drivers_num * sizeof(struct cryptocap), ++ GFP_KERNEL); ++ if (newdrv == NULL) { ++ CRYPTO_DRIVER_UNLOCK(); ++ printk("crypto: no space to expand driver table!\n"); ++ return -1; ++ } ++ ++ memcpy(newdrv, crypto_drivers, ++ crypto_drivers_num * sizeof(struct cryptocap)); ++ memset(&newdrv[crypto_drivers_num], 0, ++ crypto_drivers_num * sizeof(struct cryptocap)); ++ ++ crypto_drivers_num *= 2; ++ ++ kfree(crypto_drivers); ++ crypto_drivers = newdrv; ++ } ++ ++ /* NB: state is zero'd on free */ ++ crypto_drivers[i].cc_sessions = 1; /* Mark */ ++ crypto_drivers[i].cc_dev = dev; ++ crypto_drivers[i].cc_flags = flags; ++ if (bootverbose) ++ printf("crypto: assign %s driver id %u, flags %u\n", ++ device_get_nameunit(dev), i, flags); ++ ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ return i; ++} ++ ++/* ++ * Lookup a driver by name. We match against the full device ++ * name and unit, and against just the name. The latter gives ++ * us a simple widlcarding by device name. On success return the ++ * driver/hardware identifier; otherwise return -1. ++ */ ++int ++crypto_find_driver(const char *match) ++{ ++ int i, len = strlen(match); ++ unsigned long d_flags; ++ ++ CRYPTO_DRIVER_LOCK(); ++ for (i = 0; i < crypto_drivers_num; i++) { ++ device_t dev = crypto_drivers[i].cc_dev; ++ if (dev == NULL || ++ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP)) ++ continue; ++ if (strncmp(match, device_get_nameunit(dev), len) == 0 || ++ strncmp(match, device_get_name(dev), len) == 0) ++ break; ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ return i < crypto_drivers_num ? i : -1; ++} ++ ++/* ++ * Return the device_t for the specified driver or NULL ++ * if the driver identifier is invalid. ++ */ ++device_t ++crypto_find_device_byhid(int hid) ++{ ++ struct cryptocap *cap = crypto_checkdriver(hid); ++ return cap != NULL ? cap->cc_dev : NULL; ++} ++ ++/* ++ * Return the device/driver capabilities. ++ */ ++int ++crypto_getcaps(int hid) ++{ ++ struct cryptocap *cap = crypto_checkdriver(hid); ++ return cap != NULL ? cap->cc_flags : 0; ++} ++ ++/* ++ * Register support for a key-related algorithm. This routine ++ * is called once for each algorithm supported a driver. ++ */ ++int ++crypto_kregister(u_int32_t driverid, int kalg, u_int32_t flags) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL && ++ (CRK_ALGORITM_MIN <= kalg && kalg <= CRK_ALGORITHM_MAX)) { ++ /* ++ * XXX Do some performance testing to determine placing. ++ * XXX We probably need an auxiliary data structure that ++ * XXX describes relative performances. ++ */ ++ ++ cap->cc_kalg[kalg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; ++ if (bootverbose) ++ printf("crypto: %s registers key alg %u flags %u\n" ++ , device_get_nameunit(cap->cc_dev) ++ , kalg ++ , flags ++ ); ++ err = 0; ++ } else ++ err = EINVAL; ++ ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++/* ++ * Register support for a non-key-related algorithm. This routine ++ * is called once for each such algorithm supported by a driver. ++ */ ++int ++crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, ++ u_int32_t flags) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long d_flags; ++ ++ dprintk("%s(id=0x%x, alg=%d, maxoplen=%d, flags=0x%x)\n", __FUNCTION__, ++ driverid, alg, maxoplen, flags); ++ ++ CRYPTO_DRIVER_LOCK(); ++ ++ cap = crypto_checkdriver(driverid); ++ /* NB: algorithms are in the range [1..max] */ ++ if (cap != NULL && ++ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX)) { ++ /* ++ * XXX Do some performance testing to determine placing. ++ * XXX We probably need an auxiliary data structure that ++ * XXX describes relative performances. ++ */ ++ ++ cap->cc_alg[alg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; ++ cap->cc_max_op_len[alg] = maxoplen; ++ if (bootverbose) ++ printf("crypto: %s registers alg %u flags %u maxoplen %u\n" ++ , device_get_nameunit(cap->cc_dev) ++ , alg ++ , flags ++ , maxoplen ++ ); ++ cap->cc_sessions = 0; /* Unmark */ ++ err = 0; ++ } else ++ err = EINVAL; ++ ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++static void ++driver_finis(struct cryptocap *cap) ++{ ++ u_int32_t ses, kops; ++ ++ CRYPTO_DRIVER_ASSERT(); ++ ++ ses = cap->cc_sessions; ++ kops = cap->cc_koperations; ++ bzero(cap, sizeof(*cap)); ++ if (ses != 0 || kops != 0) { ++ /* ++ * If there are pending sessions, ++ * just mark as invalid. ++ */ ++ cap->cc_flags |= CRYPTOCAP_F_CLEANUP; ++ cap->cc_sessions = ses; ++ cap->cc_koperations = kops; ++ } ++} ++ ++/* ++ * Unregister a crypto driver. If there are pending sessions using it, ++ * leave enough information around so that subsequent calls using those ++ * sessions will correctly detect the driver has been unregistered and ++ * reroute requests. ++ */ ++int ++crypto_unregister(u_int32_t driverid, int alg) ++{ ++ struct cryptocap *cap; ++ int i, err; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL && ++ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX) && ++ cap->cc_alg[alg] != 0) { ++ cap->cc_alg[alg] = 0; ++ cap->cc_max_op_len[alg] = 0; ++ ++ /* Was this the last algorithm ? */ ++ for (i = 1; i <= CRYPTO_ALGORITHM_MAX; i++) ++ if (cap->cc_alg[i] != 0) ++ break; ++ ++ if (i == CRYPTO_ALGORITHM_MAX + 1) ++ driver_finis(cap); ++ err = 0; ++ } else ++ err = EINVAL; ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++/* ++ * Unregister all algorithms associated with a crypto driver. ++ * If there are pending sessions using it, leave enough information ++ * around so that subsequent calls using those sessions will ++ * correctly detect the driver has been unregistered and reroute ++ * requests. ++ */ ++int ++crypto_unregister_all(u_int32_t driverid) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL) { ++ driver_finis(cap); ++ err = 0; ++ } else ++ err = EINVAL; ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ return err; ++} ++ ++/* ++ * Clear blockage on a driver. The what parameter indicates whether ++ * the driver is now ready for cryptop's and/or cryptokop's. ++ */ ++int ++crypto_unblock(u_int32_t driverid, int what) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long q_flags; ++ ++ CRYPTO_Q_LOCK(); ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL) { ++ if (what & CRYPTO_SYMQ) { ++ cap->cc_qblocked = 0; ++ cap->cc_unqblocked = 0; ++ crypto_all_qblocked = 0; ++ } ++ if (what & CRYPTO_ASYMQ) { ++ cap->cc_kqblocked = 0; ++ cap->cc_unkqblocked = 0; ++ crypto_all_kqblocked = 0; ++ } ++ wake_up_interruptible(&cryptoproc_wait); ++ err = 0; ++ } else ++ err = EINVAL; ++ CRYPTO_Q_UNLOCK(); //DAVIDM should this be a driver lock ++ ++ return err; ++} ++ ++/* ++ * Add a crypto request to a queue, to be processed by the kernel thread. ++ */ ++int ++crypto_dispatch(struct cryptop *crp) ++{ ++ struct cryptocap *cap; ++ int result = -1; ++ unsigned long q_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ cryptostats.cs_ops++; ++ ++ CRYPTO_Q_LOCK(); ++ if (crypto_q_cnt >= crypto_q_max) { ++ cryptostats.cs_drops++; ++ CRYPTO_Q_UNLOCK(); ++ return ENOMEM; ++ } ++ crypto_q_cnt++; ++ ++ /* make sure we are starting a fresh run on this crp. */ ++ crp->crp_flags &= ~CRYPTO_F_DONE; ++ crp->crp_etype = 0; ++ ++ /* ++ * Caller marked the request to be processed immediately; dispatch ++ * it directly to the driver unless the driver is currently blocked. ++ */ ++ if ((crp->crp_flags & CRYPTO_F_BATCH) == 0) { ++ int hid = CRYPTO_SESID2HID(crp->crp_sid); ++ cap = crypto_checkdriver(hid); ++ /* Driver cannot disappear when there is an active session. */ ++ KASSERT(cap != NULL, ("%s: Driver disappeared.", __func__)); ++ if (!cap->cc_qblocked) { ++ crypto_all_qblocked = 0; ++ crypto_drivers[hid].cc_unqblocked = 1; ++ CRYPTO_Q_UNLOCK(); ++ result = crypto_invoke(cap, crp, 0); ++ CRYPTO_Q_LOCK(); ++ if (result == ERESTART) ++ if (crypto_drivers[hid].cc_unqblocked) ++ crypto_drivers[hid].cc_qblocked = 1; ++ crypto_drivers[hid].cc_unqblocked = 0; ++ } ++ } ++ if (result == ERESTART) { ++ /* ++ * The driver ran out of resources, mark the ++ * driver ``blocked'' for cryptop's and put ++ * the request back in the queue. It would ++ * best to put the request back where we got ++ * it but that's hard so for now we put it ++ * at the front. This should be ok; putting ++ * it at the end does not work. ++ */ ++ list_add(&crp->crp_next, &crp_q); ++ cryptostats.cs_blocks++; ++ result = 0; ++ } else if (result == -1) { ++ TAILQ_INSERT_TAIL(&crp_q, crp, crp_next); ++ result = 0; ++ } ++ wake_up_interruptible(&cryptoproc_wait); ++ CRYPTO_Q_UNLOCK(); ++ return result; ++} ++ ++/* ++ * Add an asymetric crypto request to a queue, ++ * to be processed by the kernel thread. ++ */ ++int ++crypto_kdispatch(struct cryptkop *krp) ++{ ++ int error; ++ unsigned long q_flags; ++ ++ cryptostats.cs_kops++; ++ ++ error = crypto_kinvoke(krp, krp->krp_crid); ++ if (error == ERESTART) { ++ CRYPTO_Q_LOCK(); ++ TAILQ_INSERT_TAIL(&crp_kq, krp, krp_next); ++ wake_up_interruptible(&cryptoproc_wait); ++ CRYPTO_Q_UNLOCK(); ++ error = 0; ++ } ++ return error; ++} ++ ++/* ++ * Verify a driver is suitable for the specified operation. ++ */ ++static __inline int ++kdriver_suitable(const struct cryptocap *cap, const struct cryptkop *krp) ++{ ++ return (cap->cc_kalg[krp->krp_op] & CRYPTO_ALG_FLAG_SUPPORTED) != 0; ++} ++ ++/* ++ * Select a driver for an asym operation. The driver must ++ * support the necessary algorithm. The caller can constrain ++ * which device is selected with the flags parameter. The ++ * algorithm we use here is pretty stupid; just use the first ++ * driver that supports the algorithms we need. If there are ++ * multiple suitable drivers we choose the driver with the ++ * fewest active operations. We prefer hardware-backed ++ * drivers to software ones when either may be used. ++ */ ++static struct cryptocap * ++crypto_select_kdriver(const struct cryptkop *krp, int flags) ++{ ++ struct cryptocap *cap, *best, *blocked; ++ int match, hid; ++ ++ CRYPTO_DRIVER_ASSERT(); ++ ++ /* ++ * Look first for hardware crypto devices if permitted. ++ */ ++ if (flags & CRYPTOCAP_F_HARDWARE) ++ match = CRYPTOCAP_F_HARDWARE; ++ else ++ match = CRYPTOCAP_F_SOFTWARE; ++ best = NULL; ++ blocked = NULL; ++again: ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ cap = &crypto_drivers[hid]; ++ /* ++ * If it's not initialized, is in the process of ++ * going away, or is not appropriate (hardware ++ * or software based on match), then skip. ++ */ ++ if (cap->cc_dev == NULL || ++ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || ++ (cap->cc_flags & match) == 0) ++ continue; ++ ++ /* verify all the algorithms are supported. */ ++ if (kdriver_suitable(cap, krp)) { ++ if (best == NULL || ++ cap->cc_koperations < best->cc_koperations) ++ best = cap; ++ } ++ } ++ if (best != NULL) ++ return best; ++ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { ++ /* sort of an Algol 68-style for loop */ ++ match = CRYPTOCAP_F_SOFTWARE; ++ goto again; ++ } ++ return best; ++} ++ ++/* ++ * Dispatch an assymetric crypto request. ++ */ ++static int ++crypto_kinvoke(struct cryptkop *krp, int crid) ++{ ++ struct cryptocap *cap = NULL; ++ int error; ++ unsigned long d_flags; ++ ++ KASSERT(krp != NULL, ("%s: krp == NULL", __func__)); ++ KASSERT(krp->krp_callback != NULL, ++ ("%s: krp->crp_callback == NULL", __func__)); ++ ++ CRYPTO_DRIVER_LOCK(); ++ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { ++ cap = crypto_checkdriver(crid); ++ if (cap != NULL) { ++ /* ++ * Driver present, it must support the necessary ++ * algorithm and, if s/w drivers are excluded, ++ * it must be registered as hardware-backed. ++ */ ++ if (!kdriver_suitable(cap, krp) || ++ (!crypto_devallowsoft && ++ (cap->cc_flags & CRYPTOCAP_F_HARDWARE) == 0)) ++ cap = NULL; ++ } ++ } else { ++ /* ++ * No requested driver; select based on crid flags. ++ */ ++ if (!crypto_devallowsoft) /* NB: disallow s/w drivers */ ++ crid &= ~CRYPTOCAP_F_SOFTWARE; ++ cap = crypto_select_kdriver(krp, crid); ++ } ++ if (cap != NULL && !cap->cc_kqblocked) { ++ krp->krp_hid = cap - crypto_drivers; ++ cap->cc_koperations++; ++ CRYPTO_DRIVER_UNLOCK(); ++ error = CRYPTODEV_KPROCESS(cap->cc_dev, krp, 0); ++ CRYPTO_DRIVER_LOCK(); ++ if (error == ERESTART) { ++ cap->cc_koperations--; ++ CRYPTO_DRIVER_UNLOCK(); ++ return (error); ++ } ++ /* return the actual device used */ ++ krp->krp_crid = krp->krp_hid; ++ } else { ++ /* ++ * NB: cap is !NULL if device is blocked; in ++ * that case return ERESTART so the operation ++ * is resubmitted if possible. ++ */ ++ error = (cap == NULL) ? ENODEV : ERESTART; ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ if (error) { ++ krp->krp_status = error; ++ crypto_kdone(krp); ++ } ++ return 0; ++} ++ ++ ++/* ++ * Dispatch a crypto request to the appropriate crypto devices. ++ */ ++static int ++crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint) ++{ ++ KASSERT(crp != NULL, ("%s: crp == NULL", __func__)); ++ KASSERT(crp->crp_callback != NULL, ++ ("%s: crp->crp_callback == NULL", __func__)); ++ KASSERT(crp->crp_desc != NULL, ("%s: crp->crp_desc == NULL", __func__)); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++#ifdef CRYPTO_TIMING ++ if (crypto_timing) ++ crypto_tstat(&cryptostats.cs_invoke, &crp->crp_tstamp); ++#endif ++ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) { ++ struct cryptodesc *crd; ++ u_int64_t nid; ++ ++ /* ++ * Driver has unregistered; migrate the session and return ++ * an error to the caller so they'll resubmit the op. ++ * ++ * XXX: What if there are more already queued requests for this ++ * session? ++ */ ++ crypto_freesession(crp->crp_sid); ++ ++ for (crd = crp->crp_desc; crd->crd_next; crd = crd->crd_next) ++ crd->CRD_INI.cri_next = &(crd->crd_next->CRD_INI); ++ ++ /* XXX propagate flags from initial session? */ ++ if (crypto_newsession(&nid, &(crp->crp_desc->CRD_INI), ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE) == 0) ++ crp->crp_sid = nid; ++ ++ crp->crp_etype = EAGAIN; ++ crypto_done(crp); ++ return 0; ++ } else { ++ /* ++ * Invoke the driver to process the request. ++ */ ++ return CRYPTODEV_PROCESS(cap->cc_dev, crp, hint); ++ } ++} ++ ++/* ++ * Release a set of crypto descriptors. ++ */ ++void ++crypto_freereq(struct cryptop *crp) ++{ ++ struct cryptodesc *crd; ++ ++ if (crp == NULL) ++ return; ++ ++#ifdef DIAGNOSTIC ++ { ++ struct cryptop *crp2; ++ unsigned long q_flags; ++ ++ CRYPTO_Q_LOCK(); ++ TAILQ_FOREACH(crp2, &crp_q, crp_next) { ++ KASSERT(crp2 != crp, ++ ("Freeing cryptop from the crypto queue (%p).", ++ crp)); ++ } ++ CRYPTO_Q_UNLOCK(); ++ CRYPTO_RETQ_LOCK(); ++ TAILQ_FOREACH(crp2, &crp_ret_q, crp_next) { ++ KASSERT(crp2 != crp, ++ ("Freeing cryptop from the return queue (%p).", ++ crp)); ++ } ++ CRYPTO_RETQ_UNLOCK(); ++ } ++#endif ++ ++ while ((crd = crp->crp_desc) != NULL) { ++ crp->crp_desc = crd->crd_next; ++ kmem_cache_free(cryptodesc_zone, crd); ++ } ++ kmem_cache_free(cryptop_zone, crp); ++} ++ ++/* ++ * Acquire a set of crypto descriptors. ++ */ ++struct cryptop * ++crypto_getreq(int num) ++{ ++ struct cryptodesc *crd; ++ struct cryptop *crp; ++ ++ crp = kmem_cache_alloc(cryptop_zone, SLAB_ATOMIC); ++ if (crp != NULL) { ++ memset(crp, 0, sizeof(*crp)); ++ INIT_LIST_HEAD(&crp->crp_next); ++ init_waitqueue_head(&crp->crp_waitq); ++ while (num--) { ++ crd = kmem_cache_alloc(cryptodesc_zone, SLAB_ATOMIC); ++ if (crd == NULL) { ++ crypto_freereq(crp); ++ return NULL; ++ } ++ memset(crd, 0, sizeof(*crd)); ++ crd->crd_next = crp->crp_desc; ++ crp->crp_desc = crd; ++ } ++ } ++ return crp; ++} ++ ++/* ++ * Invoke the callback on behalf of the driver. ++ */ ++void ++crypto_done(struct cryptop *crp) ++{ ++ unsigned long q_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if ((crp->crp_flags & CRYPTO_F_DONE) == 0) { ++ crp->crp_flags |= CRYPTO_F_DONE; ++ CRYPTO_Q_LOCK(); ++ crypto_q_cnt--; ++ CRYPTO_Q_UNLOCK(); ++ } else ++ printk("crypto: crypto_done op already done, flags 0x%x", ++ crp->crp_flags); ++ if (crp->crp_etype != 0) ++ cryptostats.cs_errs++; ++ /* ++ * CBIMM means unconditionally do the callback immediately; ++ * CBIFSYNC means do the callback immediately only if the ++ * operation was done synchronously. Both are used to avoid ++ * doing extraneous context switches; the latter is mostly ++ * used with the software crypto driver. ++ */ ++ if ((crp->crp_flags & CRYPTO_F_CBIMM) || ++ ((crp->crp_flags & CRYPTO_F_CBIFSYNC) && ++ (CRYPTO_SESID2CAPS(crp->crp_sid) & CRYPTOCAP_F_SYNC))) { ++ /* ++ * Do the callback directly. This is ok when the ++ * callback routine does very little (e.g. the ++ * /dev/crypto callback method just does a wakeup). ++ */ ++ crp->crp_callback(crp); ++ } else { ++ unsigned long r_flags; ++ /* ++ * Normal case; queue the callback for the thread. ++ */ ++ CRYPTO_RETQ_LOCK(); ++ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ ++ TAILQ_INSERT_TAIL(&crp_ret_q, crp, crp_next); ++ CRYPTO_RETQ_UNLOCK(); ++ } ++} ++ ++/* ++ * Invoke the callback on behalf of the driver. ++ */ ++void ++crypto_kdone(struct cryptkop *krp) ++{ ++ struct cryptocap *cap; ++ unsigned long d_flags; ++ ++ if ((krp->krp_flags & CRYPTO_KF_DONE) != 0) ++ printk("crypto: crypto_kdone op already done, flags 0x%x", ++ krp->krp_flags); ++ krp->krp_flags |= CRYPTO_KF_DONE; ++ if (krp->krp_status != 0) ++ cryptostats.cs_kerrs++; ++ ++ CRYPTO_DRIVER_LOCK(); ++ /* XXX: What if driver is loaded in the meantime? */ ++ if (krp->krp_hid < crypto_drivers_num) { ++ cap = &crypto_drivers[krp->krp_hid]; ++ cap->cc_koperations--; ++ KASSERT(cap->cc_koperations >= 0, ("cc_koperations < 0")); ++ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) ++ crypto_remove(cap); ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ /* ++ * CBIMM means unconditionally do the callback immediately; ++ * This is used to avoid doing extraneous context switches ++ */ ++ if ((krp->krp_flags & CRYPTO_KF_CBIMM)) { ++ /* ++ * Do the callback directly. This is ok when the ++ * callback routine does very little (e.g. the ++ * /dev/crypto callback method just does a wakeup). ++ */ ++ krp->krp_callback(krp); ++ } else { ++ unsigned long r_flags; ++ /* ++ * Normal case; queue the callback for the thread. ++ */ ++ CRYPTO_RETQ_LOCK(); ++ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ ++ TAILQ_INSERT_TAIL(&crp_ret_kq, krp, krp_next); ++ CRYPTO_RETQ_UNLOCK(); ++ } ++} ++ ++int ++crypto_getfeat(int *featp) ++{ ++ int hid, kalg, feat = 0; ++ unsigned long d_flags; ++ ++ CRYPTO_DRIVER_LOCK(); ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ const struct cryptocap *cap = &crypto_drivers[hid]; ++ ++ if ((cap->cc_flags & CRYPTOCAP_F_SOFTWARE) && ++ !crypto_devallowsoft) { ++ continue; ++ } ++ for (kalg = 0; kalg < CRK_ALGORITHM_MAX; kalg++) ++ if (cap->cc_kalg[kalg] & CRYPTO_ALG_FLAG_SUPPORTED) ++ feat |= 1 << kalg; ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ *featp = feat; ++ return (0); ++} ++ ++/* ++ * Crypto thread, dispatches crypto requests. ++ */ ++static int ++crypto_proc(void *arg) ++{ ++ struct cryptop *crp, *submit; ++ struct cryptkop *krp, *krpp; ++ struct cryptocap *cap; ++ u_int32_t hid; ++ int result, hint; ++ unsigned long q_flags; ++ int loopcount = 0; ++ ++ set_current_state(TASK_INTERRUPTIBLE); ++ ++ CRYPTO_Q_LOCK(); ++ for (;;) { ++ /* ++ * we need to make sure we don't get into a busy loop with nothing ++ * to do, the two crypto_all_*blocked vars help us find out when ++ * we are all full and can do nothing on any driver or Q. If so we ++ * wait for an unblock. ++ */ ++ crypto_all_qblocked = !list_empty(&crp_q); ++ ++ /* ++ * Find the first element in the queue that can be ++ * processed and look-ahead to see if multiple ops ++ * are ready for the same driver. ++ */ ++ submit = NULL; ++ hint = 0; ++ list_for_each_entry(crp, &crp_q, crp_next) { ++ hid = CRYPTO_SESID2HID(crp->crp_sid); ++ cap = crypto_checkdriver(hid); ++ /* ++ * Driver cannot disappear when there is an active ++ * session. ++ */ ++ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", ++ __func__, __LINE__)); ++ if (cap == NULL || cap->cc_dev == NULL) { ++ /* Op needs to be migrated, process it. */ ++ if (submit == NULL) ++ submit = crp; ++ break; ++ } ++ if (!cap->cc_qblocked) { ++ if (submit != NULL) { ++ /* ++ * We stop on finding another op, ++ * regardless whether its for the same ++ * driver or not. We could keep ++ * searching the queue but it might be ++ * better to just use a per-driver ++ * queue instead. ++ */ ++ if (CRYPTO_SESID2HID(submit->crp_sid) == hid) ++ hint = CRYPTO_HINT_MORE; ++ break; ++ } else { ++ submit = crp; ++ if ((submit->crp_flags & CRYPTO_F_BATCH) == 0) ++ break; ++ /* keep scanning for more are q'd */ ++ } ++ } ++ } ++ if (submit != NULL) { ++ hid = CRYPTO_SESID2HID(submit->crp_sid); ++ crypto_all_qblocked = 0; ++ list_del(&submit->crp_next); ++ crypto_drivers[hid].cc_unqblocked = 1; ++ cap = crypto_checkdriver(hid); ++ CRYPTO_Q_UNLOCK(); ++ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", ++ __func__, __LINE__)); ++ result = crypto_invoke(cap, submit, hint); ++ CRYPTO_Q_LOCK(); ++ if (result == ERESTART) { ++ /* ++ * The driver ran out of resources, mark the ++ * driver ``blocked'' for cryptop's and put ++ * the request back in the queue. It would ++ * best to put the request back where we got ++ * it but that's hard so for now we put it ++ * at the front. This should be ok; putting ++ * it at the end does not work. ++ */ ++ /* XXX validate sid again? */ ++ list_add(&submit->crp_next, &crp_q); ++ cryptostats.cs_blocks++; ++ if (crypto_drivers[hid].cc_unqblocked) ++ crypto_drivers[hid].cc_qblocked=0; ++ crypto_drivers[hid].cc_unqblocked=0; ++ } ++ crypto_drivers[hid].cc_unqblocked = 0; ++ } ++ ++ crypto_all_kqblocked = !list_empty(&crp_kq); ++ ++ /* As above, but for key ops */ ++ krp = NULL; ++ list_for_each_entry(krpp, &crp_kq, krp_next) { ++ cap = crypto_checkdriver(krpp->krp_hid); ++ if (cap == NULL || cap->cc_dev == NULL) { ++ /* ++ * Operation needs to be migrated, invalidate ++ * the assigned device so it will reselect a ++ * new one below. Propagate the original ++ * crid selection flags if supplied. ++ */ ++ krp->krp_hid = krp->krp_crid & ++ (CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE); ++ if (krp->krp_hid == 0) ++ krp->krp_hid = ++ CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE; ++ break; ++ } ++ if (!cap->cc_kqblocked) { ++ krp = krpp; ++ break; ++ } ++ } ++ if (krp != NULL) { ++ crypto_all_kqblocked = 0; ++ list_del(&krp->krp_next); ++ crypto_drivers[krp->krp_hid].cc_kqblocked = 1; ++ CRYPTO_Q_UNLOCK(); ++ result = crypto_kinvoke(krp, krp->krp_hid); ++ CRYPTO_Q_LOCK(); ++ if (result == ERESTART) { ++ /* ++ * The driver ran out of resources, mark the ++ * driver ``blocked'' for cryptkop's and put ++ * the request back in the queue. It would ++ * best to put the request back where we got ++ * it but that's hard so for now we put it ++ * at the front. This should be ok; putting ++ * it at the end does not work. ++ */ ++ /* XXX validate sid again? */ ++ list_add(&krp->krp_next, &crp_kq); ++ cryptostats.cs_kblocks++; ++ } else ++ crypto_drivers[krp->krp_hid].cc_kqblocked = 0; ++ } ++ ++ if (submit == NULL && krp == NULL) { ++ /* ++ * Nothing more to be processed. Sleep until we're ++ * woken because there are more ops to process. ++ * This happens either by submission or by a driver ++ * becoming unblocked and notifying us through ++ * crypto_unblock. Note that when we wakeup we ++ * start processing each queue again from the ++ * front. It's not clear that it's important to ++ * preserve this ordering since ops may finish ++ * out of order if dispatched to different devices ++ * and some become blocked while others do not. ++ */ ++ dprintk("%s - sleeping (qe=%d qb=%d kqe=%d kqb=%d)\n", ++ __FUNCTION__, ++ list_empty(&crp_q), crypto_all_qblocked, ++ list_empty(&crp_kq), crypto_all_kqblocked); ++ loopcount = 0; ++ CRYPTO_Q_UNLOCK(); ++ wait_event_interruptible(cryptoproc_wait, ++ !(list_empty(&crp_q) || crypto_all_qblocked) || ++ !(list_empty(&crp_kq) || crypto_all_kqblocked) || ++ kthread_should_stop()); ++ if (signal_pending (current)) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_lock_irq(¤t->sigmask_lock); ++#endif ++ flush_signals(current); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_unlock_irq(¤t->sigmask_lock); ++#endif ++ } ++ CRYPTO_Q_LOCK(); ++ dprintk("%s - awake\n", __FUNCTION__); ++ if (kthread_should_stop()) ++ break; ++ cryptostats.cs_intrs++; ++ } else if (loopcount > crypto_max_loopcount) { ++ /* ++ * Give other processes a chance to run if we've ++ * been using the CPU exclusively for a while. ++ */ ++ loopcount = 0; ++ CRYPTO_Q_UNLOCK(); ++ schedule(); ++ CRYPTO_Q_LOCK(); ++ } ++ loopcount++; ++ } ++ CRYPTO_Q_UNLOCK(); ++ return 0; ++} ++ ++/* ++ * Crypto returns thread, does callbacks for processed crypto requests. ++ * Callbacks are done here, rather than in the crypto drivers, because ++ * callbacks typically are expensive and would slow interrupt handling. ++ */ ++static int ++crypto_ret_proc(void *arg) ++{ ++ struct cryptop *crpt; ++ struct cryptkop *krpt; ++ unsigned long r_flags; ++ ++ set_current_state(TASK_INTERRUPTIBLE); ++ ++ CRYPTO_RETQ_LOCK(); ++ for (;;) { ++ /* Harvest return q's for completed ops */ ++ crpt = NULL; ++ if (!list_empty(&crp_ret_q)) ++ crpt = list_entry(crp_ret_q.next, typeof(*crpt), crp_next); ++ if (crpt != NULL) ++ list_del(&crpt->crp_next); ++ ++ krpt = NULL; ++ if (!list_empty(&crp_ret_kq)) ++ krpt = list_entry(crp_ret_kq.next, typeof(*krpt), krp_next); ++ if (krpt != NULL) ++ list_del(&krpt->krp_next); ++ ++ if (crpt != NULL || krpt != NULL) { ++ CRYPTO_RETQ_UNLOCK(); ++ /* ++ * Run callbacks unlocked. ++ */ ++ if (crpt != NULL) ++ crpt->crp_callback(crpt); ++ if (krpt != NULL) ++ krpt->krp_callback(krpt); ++ CRYPTO_RETQ_LOCK(); ++ } else { ++ /* ++ * Nothing more to be processed. Sleep until we're ++ * woken because there are more returns to process. ++ */ ++ dprintk("%s - sleeping\n", __FUNCTION__); ++ CRYPTO_RETQ_UNLOCK(); ++ wait_event_interruptible(cryptoretproc_wait, ++ !list_empty(&crp_ret_q) || ++ !list_empty(&crp_ret_kq) || ++ kthread_should_stop()); ++ if (signal_pending (current)) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_lock_irq(¤t->sigmask_lock); ++#endif ++ flush_signals(current); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_unlock_irq(¤t->sigmask_lock); ++#endif ++ } ++ CRYPTO_RETQ_LOCK(); ++ dprintk("%s - awake\n", __FUNCTION__); ++ if (kthread_should_stop()) { ++ dprintk("%s - EXITING!\n", __FUNCTION__); ++ break; ++ } ++ cryptostats.cs_rets++; ++ } ++ } ++ CRYPTO_RETQ_UNLOCK(); ++ return 0; ++} ++ ++ ++#if 0 /* should put this into /proc or something */ ++static void ++db_show_drivers(void) ++{ ++ int hid; ++ ++ db_printf("%12s %4s %4s %8s %2s %2s\n" ++ , "Device" ++ , "Ses" ++ , "Kops" ++ , "Flags" ++ , "QB" ++ , "KB" ++ ); ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ const struct cryptocap *cap = &crypto_drivers[hid]; ++ if (cap->cc_dev == NULL) ++ continue; ++ db_printf("%-12s %4u %4u %08x %2u %2u\n" ++ , device_get_nameunit(cap->cc_dev) ++ , cap->cc_sessions ++ , cap->cc_koperations ++ , cap->cc_flags ++ , cap->cc_qblocked ++ , cap->cc_kqblocked ++ ); ++ } ++} ++ ++DB_SHOW_COMMAND(crypto, db_show_crypto) ++{ ++ struct cryptop *crp; ++ ++ db_show_drivers(); ++ db_printf("\n"); ++ ++ db_printf("%4s %8s %4s %4s %4s %4s %8s %8s\n", ++ "HID", "Caps", "Ilen", "Olen", "Etype", "Flags", ++ "Desc", "Callback"); ++ TAILQ_FOREACH(crp, &crp_q, crp_next) { ++ db_printf("%4u %08x %4u %4u %4u %04x %8p %8p\n" ++ , (int) CRYPTO_SESID2HID(crp->crp_sid) ++ , (int) CRYPTO_SESID2CAPS(crp->crp_sid) ++ , crp->crp_ilen, crp->crp_olen ++ , crp->crp_etype ++ , crp->crp_flags ++ , crp->crp_desc ++ , crp->crp_callback ++ ); ++ } ++ if (!TAILQ_EMPTY(&crp_ret_q)) { ++ db_printf("\n%4s %4s %4s %8s\n", ++ "HID", "Etype", "Flags", "Callback"); ++ TAILQ_FOREACH(crp, &crp_ret_q, crp_next) { ++ db_printf("%4u %4u %04x %8p\n" ++ , (int) CRYPTO_SESID2HID(crp->crp_sid) ++ , crp->crp_etype ++ , crp->crp_flags ++ , crp->crp_callback ++ ); ++ } ++ } ++} ++ ++DB_SHOW_COMMAND(kcrypto, db_show_kcrypto) ++{ ++ struct cryptkop *krp; ++ ++ db_show_drivers(); ++ db_printf("\n"); ++ ++ db_printf("%4s %5s %4s %4s %8s %4s %8s\n", ++ "Op", "Status", "#IP", "#OP", "CRID", "HID", "Callback"); ++ TAILQ_FOREACH(krp, &crp_kq, krp_next) { ++ db_printf("%4u %5u %4u %4u %08x %4u %8p\n" ++ , krp->krp_op ++ , krp->krp_status ++ , krp->krp_iparams, krp->krp_oparams ++ , krp->krp_crid, krp->krp_hid ++ , krp->krp_callback ++ ); ++ } ++ if (!TAILQ_EMPTY(&crp_ret_q)) { ++ db_printf("%4s %5s %8s %4s %8s\n", ++ "Op", "Status", "CRID", "HID", "Callback"); ++ TAILQ_FOREACH(krp, &crp_ret_kq, krp_next) { ++ db_printf("%4u %5u %08x %4u %8p\n" ++ , krp->krp_op ++ , krp->krp_status ++ , krp->krp_crid, krp->krp_hid ++ , krp->krp_callback ++ ); ++ } ++ } ++} ++#endif ++ ++ ++static int ++crypto_init(void) ++{ ++ int error; ++ unsigned long cpu; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, (void *) crypto_init); ++ ++ if (crypto_initted) ++ return 0; ++ crypto_initted = 1; ++ ++ spin_lock_init(&crypto_drivers_lock); ++ spin_lock_init(&crypto_q_lock); ++ spin_lock_init(&crypto_ret_q_lock); ++ ++ cryptop_zone = kmem_cache_create("cryptop", sizeof(struct cryptop), ++ 0, SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ ++ cryptodesc_zone = kmem_cache_create("cryptodesc", sizeof(struct cryptodesc), ++ 0, SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ ++ if (cryptodesc_zone == NULL || cryptop_zone == NULL) { ++ printk("crypto: crypto_init cannot setup crypto zones\n"); ++ error = ENOMEM; ++ goto bad; ++ } ++ ++ crypto_drivers_num = CRYPTO_DRIVERS_INITIAL; ++ crypto_drivers = kmalloc(crypto_drivers_num * sizeof(struct cryptocap), ++ GFP_KERNEL); ++ if (crypto_drivers == NULL) { ++ printk("crypto: crypto_init cannot setup crypto drivers\n"); ++ error = ENOMEM; ++ goto bad; ++ } ++ ++ memset(crypto_drivers, 0, crypto_drivers_num * sizeof(struct cryptocap)); ++ ++ ocf_for_each_cpu(cpu) { ++ cryptoproc[cpu] = kthread_create(crypto_proc, (void *) cpu, ++ "ocf_%d", (int) cpu); ++ if (IS_ERR(cryptoproc[cpu])) { ++ error = PTR_ERR(cryptoproc[cpu]); ++ printk("crypto: crypto_init cannot start crypto thread; error %d", ++ error); ++ goto bad; ++ } ++ kthread_bind(cryptoproc[cpu], cpu); ++ wake_up_process(cryptoproc[cpu]); ++ ++ cryptoretproc[cpu] = kthread_create(crypto_ret_proc, (void *) cpu, ++ "ocf_ret_%d", (int) cpu); ++ if (IS_ERR(cryptoretproc[cpu])) { ++ error = PTR_ERR(cryptoretproc[cpu]); ++ printk("crypto: crypto_init cannot start cryptoret thread; error %d", ++ error); ++ goto bad; ++ } ++ kthread_bind(cryptoretproc[cpu], cpu); ++ wake_up_process(cryptoretproc[cpu]); ++ } ++ ++ return 0; ++bad: ++ crypto_exit(); ++ return error; ++} ++ ++ ++static void ++crypto_exit(void) ++{ ++ int cpu; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* ++ * Terminate any crypto threads. ++ */ ++ ocf_for_each_cpu(cpu) { ++ kthread_stop(cryptoproc[cpu]); ++ kthread_stop(cryptoretproc[cpu]); ++ } ++ ++ /* ++ * Reclaim dynamically allocated resources. ++ */ ++ if (crypto_drivers != NULL) ++ kfree(crypto_drivers); ++ ++ if (cryptodesc_zone != NULL) ++ kmem_cache_destroy(cryptodesc_zone); ++ if (cryptop_zone != NULL) ++ kmem_cache_destroy(cryptop_zone); ++} ++ ++ ++EXPORT_SYMBOL(crypto_newsession); ++EXPORT_SYMBOL(crypto_freesession); ++EXPORT_SYMBOL(crypto_get_driverid); ++EXPORT_SYMBOL(crypto_kregister); ++EXPORT_SYMBOL(crypto_register); ++EXPORT_SYMBOL(crypto_unregister); ++EXPORT_SYMBOL(crypto_unregister_all); ++EXPORT_SYMBOL(crypto_unblock); ++EXPORT_SYMBOL(crypto_dispatch); ++EXPORT_SYMBOL(crypto_kdispatch); ++EXPORT_SYMBOL(crypto_freereq); ++EXPORT_SYMBOL(crypto_getreq); ++EXPORT_SYMBOL(crypto_done); ++EXPORT_SYMBOL(crypto_kdone); ++EXPORT_SYMBOL(crypto_getfeat); ++EXPORT_SYMBOL(crypto_userasymcrypto); ++EXPORT_SYMBOL(crypto_getcaps); ++EXPORT_SYMBOL(crypto_find_driver); ++EXPORT_SYMBOL(crypto_find_device_byhid); ++ ++module_init(crypto_init); ++module_exit(crypto_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("OCF (OpenBSD Cryptographic Framework)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/Makefile linux-3.0.4/crypto/ocf/cryptocteon/Makefile +--- linux-3.0.4.orig/crypto/ocf/cryptocteon/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptocteon/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,17 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef CONFIG_OCF_CRYPTOCTEON ++# you need the cavium crypto component installed ++EXTRA_CFLAGS += -I$(ROOTDIR)/prop/include ++endif ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/README.txt linux-3.0.4/crypto/ocf/cryptocteon/README.txt +--- linux-3.0.4.orig/crypto/ocf/cryptocteon/README.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptocteon/README.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,11 @@ ++ ++You will need the CRYPTO package installed to build this driver, and ++potentially the ADK. ++ ++cavium_crypto sourced from: ++ ++ adk/components/source/cavium_ipsec_kame/cavium_ipsec.c ++ ++and significantly modified to suit use with OCF. All original ++copyright/ownership headers retained. ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/cavium_crypto.c linux-3.0.4/crypto/ocf/cryptocteon/cavium_crypto.c +--- linux-3.0.4.orig/crypto/ocf/cryptocteon/cavium_crypto.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptocteon/cavium_crypto.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,2283 @@ ++/* ++ * Copyright (c) 2009 David McCullough ++ * ++ * Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights ++ * reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by Cavium Networks ++ * 4. Cavium Networks' name may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * This Software, including technical data, may be subject to U.S. export ++ * control laws, including the U.S. Export Administration Act and its ++ * associated regulations, and may be subject to export or import regulations ++ * in other countries. You warrant that You will comply strictly in all ++ * respects with all such regulations and acknowledge that you have the ++ * responsibility to obtain licenses to export, re-export or import the ++ * Software. ++ * ++ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" AND ++ * WITH ALL FAULTS AND CAVIUM MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, ++ * EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE ++ * SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR ++ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM ++ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, ++ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF ++ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR ++ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR ++ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ++*/ ++/****************************************************************************/ ++ ++#include ++#include ++#include "octeon-asm.h" ++ ++/****************************************************************************/ ++ ++extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *); ++extern void octeon_crypto_disable(struct octeon_cop2_state *, unsigned long); ++ ++#define SG_INIT(s, p, i, l) \ ++ { \ ++ (i) = 0; \ ++ (l) = (s)[0].length; \ ++ (p) = (typeof(p)) sg_virt((s)); \ ++ CVMX_PREFETCH0((p)); \ ++ } ++ ++#define SG_CONSUME(s, p, i, l) \ ++ { \ ++ (p)++; \ ++ (l) -= sizeof(*(p)); \ ++ if ((l) < 0) { \ ++ dprintk("%s, %d: l = %d\n", __FILE__, __LINE__, l); \ ++ } else if ((l) == 0) { \ ++ (i)++; \ ++ (l) = (s)[0].length; \ ++ (p) = (typeof(p)) sg_virt(s); \ ++ CVMX_PREFETCH0((p)); \ ++ } \ ++ } ++ ++#define ESP_HEADER_LENGTH 8 ++#define DES_CBC_IV_LENGTH 8 ++#define AES_CBC_IV_LENGTH 16 ++#define ESP_HMAC_LEN 12 ++ ++#define ESP_HEADER_LENGTH 8 ++#define DES_CBC_IV_LENGTH 8 ++ ++/****************************************************************************/ ++ ++#define CVM_LOAD_SHA_UNIT(dat, next) { \ ++ if (next == 0) { \ ++ next = 1; \ ++ CVMX_MT_HSH_DAT (dat, 0); \ ++ } else if (next == 1) { \ ++ next = 2; \ ++ CVMX_MT_HSH_DAT (dat, 1); \ ++ } else if (next == 2) { \ ++ next = 3; \ ++ CVMX_MT_HSH_DAT (dat, 2); \ ++ } else if (next == 3) { \ ++ next = 4; \ ++ CVMX_MT_HSH_DAT (dat, 3); \ ++ } else if (next == 4) { \ ++ next = 5; \ ++ CVMX_MT_HSH_DAT (dat, 4); \ ++ } else if (next == 5) { \ ++ next = 6; \ ++ CVMX_MT_HSH_DAT (dat, 5); \ ++ } else if (next == 6) { \ ++ next = 7; \ ++ CVMX_MT_HSH_DAT (dat, 6); \ ++ } else { \ ++ CVMX_MT_HSH_STARTSHA (dat); \ ++ next = 0; \ ++ } \ ++} ++ ++#define CVM_LOAD2_SHA_UNIT(dat1, dat2, next) { \ ++ if (next == 0) { \ ++ CVMX_MT_HSH_DAT (dat1, 0); \ ++ CVMX_MT_HSH_DAT (dat2, 1); \ ++ next = 2; \ ++ } else if (next == 1) { \ ++ CVMX_MT_HSH_DAT (dat1, 1); \ ++ CVMX_MT_HSH_DAT (dat2, 2); \ ++ next = 3; \ ++ } else if (next == 2) { \ ++ CVMX_MT_HSH_DAT (dat1, 2); \ ++ CVMX_MT_HSH_DAT (dat2, 3); \ ++ next = 4; \ ++ } else if (next == 3) { \ ++ CVMX_MT_HSH_DAT (dat1, 3); \ ++ CVMX_MT_HSH_DAT (dat2, 4); \ ++ next = 5; \ ++ } else if (next == 4) { \ ++ CVMX_MT_HSH_DAT (dat1, 4); \ ++ CVMX_MT_HSH_DAT (dat2, 5); \ ++ next = 6; \ ++ } else if (next == 5) { \ ++ CVMX_MT_HSH_DAT (dat1, 5); \ ++ CVMX_MT_HSH_DAT (dat2, 6); \ ++ next = 7; \ ++ } else if (next == 6) { \ ++ CVMX_MT_HSH_DAT (dat1, 6); \ ++ CVMX_MT_HSH_STARTSHA (dat2); \ ++ next = 0; \ ++ } else { \ ++ CVMX_MT_HSH_STARTSHA (dat1); \ ++ CVMX_MT_HSH_DAT (dat2, 0); \ ++ next = 1; \ ++ } \ ++} ++ ++/****************************************************************************/ ++ ++#define CVM_LOAD_MD5_UNIT(dat, next) { \ ++ if (next == 0) { \ ++ next = 1; \ ++ CVMX_MT_HSH_DAT (dat, 0); \ ++ } else if (next == 1) { \ ++ next = 2; \ ++ CVMX_MT_HSH_DAT (dat, 1); \ ++ } else if (next == 2) { \ ++ next = 3; \ ++ CVMX_MT_HSH_DAT (dat, 2); \ ++ } else if (next == 3) { \ ++ next = 4; \ ++ CVMX_MT_HSH_DAT (dat, 3); \ ++ } else if (next == 4) { \ ++ next = 5; \ ++ CVMX_MT_HSH_DAT (dat, 4); \ ++ } else if (next == 5) { \ ++ next = 6; \ ++ CVMX_MT_HSH_DAT (dat, 5); \ ++ } else if (next == 6) { \ ++ next = 7; \ ++ CVMX_MT_HSH_DAT (dat, 6); \ ++ } else { \ ++ CVMX_MT_HSH_STARTMD5 (dat); \ ++ next = 0; \ ++ } \ ++} ++ ++#define CVM_LOAD2_MD5_UNIT(dat1, dat2, next) { \ ++ if (next == 0) { \ ++ CVMX_MT_HSH_DAT (dat1, 0); \ ++ CVMX_MT_HSH_DAT (dat2, 1); \ ++ next = 2; \ ++ } else if (next == 1) { \ ++ CVMX_MT_HSH_DAT (dat1, 1); \ ++ CVMX_MT_HSH_DAT (dat2, 2); \ ++ next = 3; \ ++ } else if (next == 2) { \ ++ CVMX_MT_HSH_DAT (dat1, 2); \ ++ CVMX_MT_HSH_DAT (dat2, 3); \ ++ next = 4; \ ++ } else if (next == 3) { \ ++ CVMX_MT_HSH_DAT (dat1, 3); \ ++ CVMX_MT_HSH_DAT (dat2, 4); \ ++ next = 5; \ ++ } else if (next == 4) { \ ++ CVMX_MT_HSH_DAT (dat1, 4); \ ++ CVMX_MT_HSH_DAT (dat2, 5); \ ++ next = 6; \ ++ } else if (next == 5) { \ ++ CVMX_MT_HSH_DAT (dat1, 5); \ ++ CVMX_MT_HSH_DAT (dat2, 6); \ ++ next = 7; \ ++ } else if (next == 6) { \ ++ CVMX_MT_HSH_DAT (dat1, 6); \ ++ CVMX_MT_HSH_STARTMD5 (dat2); \ ++ next = 0; \ ++ } else { \ ++ CVMX_MT_HSH_STARTMD5 (dat1); \ ++ CVMX_MT_HSH_DAT (dat2, 0); \ ++ next = 1; \ ++ } \ ++} ++ ++/****************************************************************************/ ++ ++static inline uint64_t ++swap64(uint64_t a) ++{ ++ return ((a >> 56) | ++ (((a >> 48) & 0xfful) << 8) | ++ (((a >> 40) & 0xfful) << 16) | ++ (((a >> 32) & 0xfful) << 24) | ++ (((a >> 24) & 0xfful) << 32) | ++ (((a >> 16) & 0xfful) << 40) | ++ (((a >> 8) & 0xfful) << 48) | (((a >> 0) & 0xfful) << 56)); ++} ++ ++/****************************************************************************/ ++ ++void ++octo_calc_hash(__u8 auth, unsigned char *key, uint64_t *inner, uint64_t *outer) ++{ ++ uint8_t hash_key[64]; ++ uint64_t *key1; ++ register uint64_t xor1 = 0x3636363636363636ULL; ++ register uint64_t xor2 = 0x5c5c5c5c5c5c5c5cULL; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ memset(hash_key, 0, sizeof(hash_key)); ++ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); ++ key1 = (uint64_t *) hash_key; ++ flags = octeon_crypto_enable(&state); ++ if (auth) { ++ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); ++ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); ++ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); ++ } else { ++ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); ++ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); ++ } ++ ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 0); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 1); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 2); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 3); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 4); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 5); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 6); ++ key1++; ++ if (auth) ++ CVMX_MT_HSH_STARTSHA((*key1 ^ xor1)); ++ else ++ CVMX_MT_HSH_STARTMD5((*key1 ^ xor1)); ++ ++ CVMX_MF_HSH_IV(inner[0], 0); ++ CVMX_MF_HSH_IV(inner[1], 1); ++ if (auth) { ++ inner[2] = 0; ++ CVMX_MF_HSH_IV(((uint64_t *) inner)[2], 2); ++ } ++ ++ memset(hash_key, 0, sizeof(hash_key)); ++ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); ++ key1 = (uint64_t *) hash_key; ++ if (auth) { ++ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); ++ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); ++ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); ++ } else { ++ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); ++ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); ++ } ++ ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 0); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 1); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 2); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 3); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 4); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 5); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 6); ++ key1++; ++ if (auth) ++ CVMX_MT_HSH_STARTSHA((*key1 ^ xor2)); ++ else ++ CVMX_MT_HSH_STARTMD5((*key1 ^ xor2)); ++ ++ CVMX_MF_HSH_IV(outer[0], 0); ++ CVMX_MF_HSH_IV(outer[1], 1); ++ if (auth) { ++ outer[2] = 0; ++ CVMX_MF_HSH_IV(outer[2], 2); ++ } ++ octeon_crypto_disable(&state, flags); ++ return; ++} ++ ++/****************************************************************************/ ++/* DES functions */ ++ ++int ++octo_des_cbc_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ CVMX_MT_3DES_ENC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 8; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++ ++int ++octo_des_cbc_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ CVMX_MT_3DES_DEC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 8; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* AES functions */ ++ ++int ++octo_aes_cbc_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data, *pdata; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ pdata = data; ++ CVMX_MT_AES_ENC_CBC0(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MT_AES_ENC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 16; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++ ++int ++octo_aes_cbc_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data, *pdata; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ pdata = data; ++ CVMX_MT_AES_DEC_CBC0(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MT_AES_DEC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 16; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* MD5 */ ++ ++int ++octo_null_md5_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ uint64_t *data; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ++ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (auth_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ auth_off -= 8; ++ } ++ ++ while (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ SG_CONSUME(sg, data, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ icv_off -= 8; ++ } ++ CVMX_MF_HSH_IV(*data, 0); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* SHA1 */ ++ ++int ++octo_null_sha1_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ uint64_t *data; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ++ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (auth_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ auth_off -= 8; ++ } ++ ++ while (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ SG_CONSUME(sg, data, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ icv_off -= 8; ++ } ++ CVMX_MF_HSH_IV(*data, 0); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* DES MD5 */ ++ ++int ++octo_des_cbc_md5_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_ENC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_des_cbc_md5_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_DEC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* DES SHA */ ++ ++int ++octo_des_cbc_sha1_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_ENC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_des_cbc_sha1_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_DEC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* AES MD5 */ ++ ++int ++octo_aes_cbc_md5_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ ++ mydata[1].data32[1] = *data32; ++ ++ CVMX_MT_AES_ENC_CBC0(*pdata); ++ CVMX_MT_AES_ENC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish any left over hashing */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_aes_cbc_md5_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[1].data32[1] = *data32; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ CVMX_MT_AES_DEC_CBC0(*pdata); ++ CVMX_MT_AES_DEC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish left over hash if any */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* AES SHA1 */ ++ ++int ++octo_aes_cbc_sha1_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", ++ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load SHA IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[1].data32[1] = *data32; ++ ++ CVMX_MT_AES_ENC_CBC0(*pdata); ++ CVMX_MT_AES_ENC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish and hashing */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_aes_cbc_sha1_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", ++ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[1].data32[1] = *data32; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ CVMX_MT_AES_DEC_CBC0(*pdata); ++ CVMX_MT_AES_DEC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish and leftover hashing */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/cryptocteon.c linux-3.0.4/crypto/ocf/cryptocteon/cryptocteon.c +--- linux-3.0.4.orig/crypto/ocf/cryptocteon/cryptocteon.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptocteon/cryptocteon.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,575 @@ ++/* ++ * Octeon Crypto for OCF ++ * ++ * Written by David McCullough ++ * Copyright (C) 2009-2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ * --------------------------------------------------------------------------- ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++struct { ++ softc_device_decl sc_dev; ++} octo_softc; ++ ++#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) ++ ++struct octo_sess { ++ int octo_encalg; ++ #define MAX_CIPHER_KEYLEN 64 ++ char octo_enckey[MAX_CIPHER_KEYLEN]; ++ int octo_encklen; ++ ++ int octo_macalg; ++ #define MAX_HASH_KEYLEN 64 ++ char octo_mackey[MAX_HASH_KEYLEN]; ++ int octo_macklen; ++ int octo_mackey_set; ++ ++ int octo_mlen; ++ int octo_ivsize; ++ ++ int (*octo_encrypt)(struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp); ++ int (*octo_decrypt)(struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp); ++ ++ uint64_t octo_hminner[3]; ++ uint64_t octo_hmouter[3]; ++}; ++ ++int32_t octo_id = -1; ++module_param(octo_id, int, 0444); ++MODULE_PARM_DESC(octo_id, "Read-Only OCF ID for cryptocteon driver"); ++ ++static struct octo_sess **octo_sessions = NULL; ++static u_int32_t octo_sesnum = 0; ++ ++static int octo_process(device_t, struct cryptop *, int); ++static int octo_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int octo_freesession(device_t, u_int64_t); ++ ++static device_method_t octo_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, octo_newsession), ++ DEVMETHOD(cryptodev_freesession,octo_freesession), ++ DEVMETHOD(cryptodev_process, octo_process), ++}; ++ ++#define debug octo_debug ++int octo_debug = 0; ++module_param(octo_debug, int, 0644); ++MODULE_PARM_DESC(octo_debug, "Enable debug"); ++ ++ ++#include "cavium_crypto.c" ++ ++ ++/* ++ * Generate a new octo session. We artifically limit it to a single ++ * hash/cipher or hash-cipher combo just to make it easier, most callers ++ * do not expect more than this anyway. ++ */ ++static int ++octo_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct octo_sess **ocd; ++ int i; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* ++ * To keep it simple, we only handle hash, cipher or hash/cipher in a ++ * session, you cannot currently do multiple ciphers/hashes in one ++ * session even though it would be possibel to code this driver to ++ * handle it. ++ */ ++ for (i = 0, c = cri; c && i < 2; i++) { ++ if (c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1_HMAC || ++ c->cri_alg == CRYPTO_NULL_HMAC) { ++ if (macini) { ++ break; ++ } ++ macini = c; ++ } ++ if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC || ++ c->cri_alg == CRYPTO_NULL_CBC) { ++ if (encini) { ++ break; ++ } ++ encini = c; ++ } ++ c = c->cri_next; ++ } ++ if (!macini && !encini) { ++ dprintk("%s,%d - EINVAL bad cipher/hash or combination\n", ++ __FILE__, __LINE__); ++ return EINVAL; ++ } ++ if (c) { ++ dprintk("%s,%d - EINVAL cannot handle chained cipher/hash combos\n", ++ __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* ++ * So we have something we can do, lets setup the session ++ */ ++ ++ if (octo_sessions) { ++ for (i = 1; i < octo_sesnum; i++) ++ if (octo_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (octo_sessions == NULL || i == octo_sesnum) { ++ if (octo_sessions == NULL) { ++ i = 1; /* We leave octo_sessions[0] empty */ ++ octo_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ octo_sesnum *= 2; ++ ++ ocd = kmalloc(octo_sesnum * sizeof(struct octo_sess *), SLAB_ATOMIC); ++ if (ocd == NULL) { ++ /* Reset session number */ ++ if (octo_sesnum == CRYPTO_SW_SESSIONS) ++ octo_sesnum = 0; ++ else ++ octo_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(ocd, 0, octo_sesnum * sizeof(struct octo_sess *)); ++ ++ /* Copy existing sessions */ ++ if (octo_sessions) { ++ memcpy(ocd, octo_sessions, ++ (octo_sesnum / 2) * sizeof(struct octo_sess *)); ++ kfree(octo_sessions); ++ } ++ ++ octo_sessions = ocd; ++ } ++ ++ ocd = &octo_sessions[i]; ++ *sid = i; ++ ++ ++ *ocd = (struct octo_sess *) kmalloc(sizeof(struct octo_sess), SLAB_ATOMIC); ++ if (*ocd == NULL) { ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(*ocd, 0, sizeof(struct octo_sess)); ++ ++ if (encini && encini->cri_key) { ++ (*ocd)->octo_encklen = (encini->cri_klen + 7) / 8; ++ memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen); ++ } ++ ++ if (macini && macini->cri_key) { ++ (*ocd)->octo_macklen = (macini->cri_klen + 7) / 8; ++ memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen); ++ } ++ ++ (*ocd)->octo_mlen = 0; ++ if (encini && encini->cri_mlen) ++ (*ocd)->octo_mlen = encini->cri_mlen; ++ else if (macini && macini->cri_mlen) ++ (*ocd)->octo_mlen = macini->cri_mlen; ++ else ++ (*ocd)->octo_mlen = 12; ++ ++ /* ++ * point c at the enc if it exists, otherwise the mac ++ */ ++ c = encini ? encini : macini; ++ ++ switch (c->cri_alg) { ++ case CRYPTO_DES_CBC: ++ case CRYPTO_3DES_CBC: ++ (*ocd)->octo_ivsize = 8; ++ switch (macini ? macini->cri_alg : -1) { ++ case CRYPTO_MD5_HMAC: ++ (*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt; ++ (*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt; ++ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ (*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt; ++ (*ocd)->octo_decrypt = octo_des_cbc_sha1_decrypt; ++ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case -1: ++ (*ocd)->octo_encrypt = octo_des_cbc_encrypt; ++ (*ocd)->octo_decrypt = octo_des_cbc_decrypt; ++ break; ++ default: ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ break; ++ case CRYPTO_AES_CBC: ++ (*ocd)->octo_ivsize = 16; ++ switch (macini ? macini->cri_alg : -1) { ++ case CRYPTO_MD5_HMAC: ++ (*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt; ++ (*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt; ++ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ (*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt; ++ (*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt; ++ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case -1: ++ (*ocd)->octo_encrypt = octo_aes_cbc_encrypt; ++ (*ocd)->octo_decrypt = octo_aes_cbc_decrypt; ++ break; ++ default: ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ break; ++ case CRYPTO_MD5_HMAC: ++ (*ocd)->octo_encrypt = octo_null_md5_encrypt; ++ (*ocd)->octo_decrypt = octo_null_md5_encrypt; /* encrypt == decrypt */ ++ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ (*ocd)->octo_encrypt = octo_null_sha1_encrypt; ++ (*ocd)->octo_decrypt = octo_null_sha1_encrypt; /* encrypt == decrypt */ ++ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ default: ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ (*ocd)->octo_encalg = encini ? encini->cri_alg : -1; ++ (*ocd)->octo_macalg = macini ? macini->cri_alg : -1; ++ ++ return 0; ++} ++ ++/* ++ * Free a session. ++ */ ++static int ++octo_freesession(device_t dev, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > octo_sesnum || octo_sessions == NULL || ++ octo_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ if (octo_sessions[sid]) ++ kfree(octo_sessions[sid]); ++ octo_sessions[sid] = NULL; ++ return 0; ++} ++ ++/* ++ * Process a request. ++ */ ++static int ++octo_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct cryptodesc *crd; ++ struct octo_sess *od; ++ u_int32_t lid; ++#define SCATTERLIST_MAX 16 ++ struct scatterlist sg[SCATTERLIST_MAX]; ++ int sg_num, sg_len; ++ struct sk_buff *skb = NULL; ++ struct uio *uiop = NULL; ++ struct cryptodesc *enccrd = NULL, *maccrd = NULL; ++ unsigned char *ivp = NULL; ++ unsigned char iv_data[HASH_MAX_LEN]; ++ int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= octo_sesnum || lid == 0 || octo_sessions == NULL || ++ octo_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ od = octo_sessions[lid]; ++ ++ /* ++ * do some error checking outside of the loop for SKB and IOV processing ++ * this leaves us with valid skb or uiop pointers for later ++ */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ skb = (struct sk_buff *) crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { ++ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, ++ skb_shinfo(skb)->nr_frags); ++ goto done; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ uiop = (struct uio *) crp->crp_buf; ++ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { ++ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, ++ uiop->uio_iovcnt); ++ goto done; ++ } ++ } ++ ++ /* point our enccrd and maccrd appropriately */ ++ crd = crp->crp_desc; ++ if (crd->crd_alg == od->octo_encalg) enccrd = crd; ++ if (crd->crd_alg == od->octo_macalg) maccrd = crd; ++ crd = crd->crd_next; ++ if (crd) { ++ if (crd->crd_alg == od->octo_encalg) enccrd = crd; ++ if (crd->crd_alg == od->octo_macalg) maccrd = crd; ++ crd = crd->crd_next; ++ } ++ if (crd) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: ENOENT - descriptors do not match session\n", ++ __FILE__, __LINE__); ++ goto done; ++ } ++ ++ if (enccrd) { ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ ivp = enccrd->crd_iv; ++ else ++ read_random((ivp = iv_data), od->octo_ivsize); ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, od->octo_ivsize, ivp); ++ } else { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = enccrd->crd_iv; ++ } else { ++ ivp = iv_data; ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp); ++ } ++ } ++ ++ if (maccrd) { ++ auth_off = maccrd->crd_skip; ++ auth_len = maccrd->crd_len; ++ icv_off = maccrd->crd_inject; ++ } ++ ++ crypt_off = enccrd->crd_skip; ++ crypt_len = enccrd->crd_len; ++ } else { /* if (maccrd) */ ++ auth_off = maccrd->crd_skip; ++ auth_len = maccrd->crd_len; ++ icv_off = maccrd->crd_inject; ++ } ++ ++ ++ /* ++ * setup the SG list to cover the buffer ++ */ ++ memset(sg, 0, sizeof(sg)); ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ int i, len; ++ ++ sg_num = 0; ++ sg_len = 0; ++ ++ len = skb_headlen(skb); ++ sg_set_page(&sg[sg_num], virt_to_page(skb->data), len, ++ offset_in_page(skb->data)); ++ sg_len += len; ++ sg_num++; ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags && sg_num < SCATTERLIST_MAX; ++ i++) { ++ len = skb_shinfo(skb)->frags[i].size; ++ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, ++ len, skb_shinfo(skb)->frags[i].page_offset); ++ sg_len += len; ++ sg_num++; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ int len; ++ ++ sg_len = 0; ++ for (sg_num = 0; sg_len < crp->crp_ilen && ++ sg_num < uiop->uio_iovcnt && ++ sg_num < SCATTERLIST_MAX; sg_num++) { ++ len = uiop->uio_iov[sg_num].iov_len; ++ sg_set_page(&sg[sg_num], ++ virt_to_page(uiop->uio_iov[sg_num].iov_base), len, ++ offset_in_page(uiop->uio_iov[sg_num].iov_base)); ++ sg_len += len; ++ } ++ } else { ++ sg_len = crp->crp_ilen; ++ sg_set_page(&sg[0], virt_to_page(crp->crp_buf), sg_len, ++ offset_in_page(crp->crp_buf)); ++ sg_num = 1; ++ } ++ ++ ++ /* ++ * setup a new explicit key ++ */ ++ if (enccrd) { ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ od->octo_encklen = (enccrd->crd_klen + 7) / 8; ++ memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen); ++ } ++ } ++ if (maccrd) { ++ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ od->octo_macklen = (maccrd->crd_klen + 7) / 8; ++ memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen); ++ od->octo_mackey_set = 0; ++ } ++ if (!od->octo_mackey_set) { ++ octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1, ++ maccrd->crd_key, od->octo_hminner, od->octo_hmouter); ++ od->octo_mackey_set = 1; ++ } ++ } ++ ++ ++ if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT)) ++ (*od->octo_encrypt)(od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ else ++ (*od->octo_decrypt)(od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ ++done: ++ crypto_done(crp); ++ return 0; ++} ++ ++static int ++cryptocteon_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, cryptocteon_init); ++ ++ softc_device_init(&octo_softc, "cryptocteon", 0, octo_methods); ++ ++ octo_id = crypto_get_driverid(softc_get_device(&octo_softc), ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC); ++ if (octo_id < 0) { ++ printk("Cryptocteon device cannot initialize!"); ++ return -ENODEV; ++ } ++ ++ crypto_register(octo_id, CRYPTO_MD5_HMAC, 0,0); ++ crypto_register(octo_id, CRYPTO_SHA1_HMAC, 0,0); ++ //crypto_register(octo_id, CRYPTO_MD5, 0,0); ++ //crypto_register(octo_id, CRYPTO_SHA1, 0,0); ++ crypto_register(octo_id, CRYPTO_DES_CBC, 0,0); ++ crypto_register(octo_id, CRYPTO_3DES_CBC, 0,0); ++ crypto_register(octo_id, CRYPTO_AES_CBC, 0,0); ++ ++ return(0); ++} ++ ++static void ++cryptocteon_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(octo_id); ++ octo_id = -1; ++} ++ ++module_init(cryptocteon_init); ++module_exit(cryptocteon_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Cryptocteon (OCF module for Cavium OCTEON crypto)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptodev.c linux-3.0.4/crypto/ocf/cryptodev.c +--- linux-3.0.4.orig/crypto/ocf/cryptodev.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptodev.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1069 @@ ++/* $OpenBSD: cryptodev.c,v 1.52 2002/06/19 07:22:46 deraadt Exp $ */ ++ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2001 Theo de Raadt ++ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++__FBSDID("$FreeBSD: src/sys/opencrypto/cryptodev.c,v 1.34 2007/05/09 19:37:02 gnn Exp $"); ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++extern asmlinkage long sys_dup(unsigned int fildes); ++ ++#define debug cryptodev_debug ++int cryptodev_debug = 0; ++module_param(cryptodev_debug, int, 0644); ++MODULE_PARM_DESC(cryptodev_debug, "Enable cryptodev debug"); ++ ++struct csession_info { ++ u_int16_t blocksize; ++ u_int16_t minkey, maxkey; ++ ++ u_int16_t keysize; ++ /* u_int16_t hashsize; */ ++ u_int16_t authsize; ++ u_int16_t authkey; ++ /* u_int16_t ctxsize; */ ++}; ++ ++struct csession { ++ struct list_head list; ++ u_int64_t sid; ++ u_int32_t ses; ++ ++ wait_queue_head_t waitq; ++ ++ u_int32_t cipher; ++ ++ u_int32_t mac; ++ ++ caddr_t key; ++ int keylen; ++ u_char tmp_iv[EALG_MAX_BLOCK_LEN]; ++ ++ caddr_t mackey; ++ int mackeylen; ++ ++ struct csession_info info; ++ ++ struct iovec iovec; ++ struct uio uio; ++ int error; ++}; ++ ++struct fcrypt { ++ struct list_head csessions; ++ int sesn; ++}; ++ ++static struct csession *csefind(struct fcrypt *, u_int); ++static int csedelete(struct fcrypt *, struct csession *); ++static struct csession *cseadd(struct fcrypt *, struct csession *); ++static struct csession *csecreate(struct fcrypt *, u_int64_t, ++ struct cryptoini *crie, struct cryptoini *cria, struct csession_info *); ++static int csefree(struct csession *); ++ ++static int cryptodev_op(struct csession *, struct crypt_op *); ++static int cryptodev_key(struct crypt_kop *); ++static int cryptodev_find(struct crypt_find_op *); ++ ++static int cryptodev_cb(void *); ++static int cryptodev_open(struct inode *inode, struct file *filp); ++ ++/* ++ * Check a crypto identifier to see if it requested ++ * a valid crid and it's capabilities match. ++ */ ++static int ++checkcrid(int crid) ++{ ++ int hid = crid & ~(CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); ++ int typ = crid & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); ++ int caps = 0; ++ ++ /* if the user hasn't selected a driver, then just call newsession */ ++ if (hid == 0 && typ != 0) ++ return 0; ++ ++ caps = crypto_getcaps(hid); ++ ++ /* didn't find anything with capabilities */ ++ if (caps == 0) { ++ dprintk("%s: hid=%x typ=%x not matched\n", __FUNCTION__, hid, typ); ++ return EINVAL; ++ } ++ ++ /* the user didn't specify SW or HW, so the driver is ok */ ++ if (typ == 0) ++ return 0; ++ ++ /* if the type specified didn't match */ ++ if (typ != (caps & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE))) { ++ dprintk("%s: hid=%x typ=%x caps=%x not matched\n", __FUNCTION__, ++ hid, typ, caps); ++ return EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int ++cryptodev_op(struct csession *cse, struct crypt_op *cop) ++{ ++ struct cryptop *crp = NULL; ++ struct cryptodesc *crde = NULL, *crda = NULL; ++ int error = 0; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (cop->len > CRYPTO_MAX_DATA_LEN) { ++ dprintk("%s: %d > %d\n", __FUNCTION__, cop->len, CRYPTO_MAX_DATA_LEN); ++ return (E2BIG); ++ } ++ ++ if (cse->info.blocksize && (cop->len % cse->info.blocksize) != 0) { ++ dprintk("%s: blocksize=%d len=%d\n", __FUNCTION__, cse->info.blocksize, ++ cop->len); ++ return (EINVAL); ++ } ++ ++ cse->uio.uio_iov = &cse->iovec; ++ cse->uio.uio_iovcnt = 1; ++ cse->uio.uio_offset = 0; ++#if 0 ++ cse->uio.uio_resid = cop->len; ++ cse->uio.uio_segflg = UIO_SYSSPACE; ++ cse->uio.uio_rw = UIO_WRITE; ++ cse->uio.uio_td = td; ++#endif ++ cse->uio.uio_iov[0].iov_len = cop->len; ++ if (cse->info.authsize) ++ cse->uio.uio_iov[0].iov_len += cse->info.authsize; ++ cse->uio.uio_iov[0].iov_base = kmalloc(cse->uio.uio_iov[0].iov_len, ++ GFP_KERNEL); ++ ++ if (cse->uio.uio_iov[0].iov_base == NULL) { ++ dprintk("%s: iov_base kmalloc(%d) failed\n", __FUNCTION__, ++ (int)cse->uio.uio_iov[0].iov_len); ++ return (ENOMEM); ++ } ++ ++ crp = crypto_getreq((cse->info.blocksize != 0) + (cse->info.authsize != 0)); ++ if (crp == NULL) { ++ dprintk("%s: ENOMEM\n", __FUNCTION__); ++ error = ENOMEM; ++ goto bail; ++ } ++ ++ if (cse->info.authsize && cse->info.blocksize) { ++ if (cop->op == COP_ENCRYPT) { ++ crde = crp->crp_desc; ++ crda = crde->crd_next; ++ } else { ++ crda = crp->crp_desc; ++ crde = crda->crd_next; ++ } ++ } else if (cse->info.authsize) { ++ crda = crp->crp_desc; ++ } else if (cse->info.blocksize) { ++ crde = crp->crp_desc; ++ } else { ++ dprintk("%s: bad request\n", __FUNCTION__); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ if ((error = copy_from_user(cse->uio.uio_iov[0].iov_base, cop->src, ++ cop->len))) { ++ dprintk("%s: bad copy\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (crda) { ++ crda->crd_skip = 0; ++ crda->crd_len = cop->len; ++ crda->crd_inject = cop->len; ++ ++ crda->crd_alg = cse->mac; ++ crda->crd_key = cse->mackey; ++ crda->crd_klen = cse->mackeylen * 8; ++ } ++ ++ if (crde) { ++ if (cop->op == COP_ENCRYPT) ++ crde->crd_flags |= CRD_F_ENCRYPT; ++ else ++ crde->crd_flags &= ~CRD_F_ENCRYPT; ++ crde->crd_len = cop->len; ++ crde->crd_inject = 0; ++ ++ crde->crd_alg = cse->cipher; ++ crde->crd_key = cse->key; ++ crde->crd_klen = cse->keylen * 8; ++ } ++ ++ crp->crp_ilen = cse->uio.uio_iov[0].iov_len; ++ crp->crp_flags = CRYPTO_F_IOV | CRYPTO_F_CBIMM ++ | (cop->flags & COP_F_BATCH); ++ crp->crp_buf = (caddr_t)&cse->uio; ++ crp->crp_callback = (int (*) (struct cryptop *)) cryptodev_cb; ++ crp->crp_sid = cse->sid; ++ crp->crp_opaque = (void *)cse; ++ ++ if (cop->iv) { ++ if (crde == NULL) { ++ error = EINVAL; ++ dprintk("%s no crde\n", __FUNCTION__); ++ goto bail; ++ } ++ if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ ++ error = EINVAL; ++ dprintk("%s arc4 with IV\n", __FUNCTION__); ++ goto bail; ++ } ++ if ((error = copy_from_user(cse->tmp_iv, cop->iv, ++ cse->info.blocksize))) { ++ dprintk("%s bad iv copy\n", __FUNCTION__); ++ goto bail; ++ } ++ memcpy(crde->crd_iv, cse->tmp_iv, cse->info.blocksize); ++ crde->crd_flags |= CRD_F_IV_EXPLICIT | CRD_F_IV_PRESENT; ++ crde->crd_skip = 0; ++ } else if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ ++ crde->crd_skip = 0; ++ } else if (crde) { ++ crde->crd_flags |= CRD_F_IV_PRESENT; ++ crde->crd_skip = cse->info.blocksize; ++ crde->crd_len -= cse->info.blocksize; ++ } ++ ++ if (cop->mac && crda == NULL) { ++ error = EINVAL; ++ dprintk("%s no crda\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ /* ++ * Let the dispatch run unlocked, then, interlock against the ++ * callback before checking if the operation completed and going ++ * to sleep. This insures drivers don't inherit our lock which ++ * results in a lock order reversal between crypto_dispatch forced ++ * entry and the crypto_done callback into us. ++ */ ++ error = crypto_dispatch(crp); ++ if (error) { ++ dprintk("%s error in crypto_dispatch\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ dprintk("%s about to WAIT\n", __FUNCTION__); ++ /* ++ * we really need to wait for driver to complete to maintain ++ * state, luckily interrupts will be remembered ++ */ ++ do { ++ error = wait_event_interruptible(crp->crp_waitq, ++ ((crp->crp_flags & CRYPTO_F_DONE) != 0)); ++ /* ++ * we can't break out of this loop or we will leave behind ++ * a huge mess, however, staying here means if your driver ++ * is broken user applications can hang and not be killed. ++ * The solution, fix your driver :-) ++ */ ++ if (error) { ++ schedule(); ++ error = 0; ++ } ++ } while ((crp->crp_flags & CRYPTO_F_DONE) == 0); ++ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); ++ ++ if (crp->crp_etype != 0) { ++ error = crp->crp_etype; ++ dprintk("%s error in crp processing\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (cse->error) { ++ error = cse->error; ++ dprintk("%s error in cse processing\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (cop->dst && (error = copy_to_user(cop->dst, ++ cse->uio.uio_iov[0].iov_base, cop->len))) { ++ dprintk("%s bad dst copy\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (cop->mac && ++ (error=copy_to_user(cop->mac, ++ (caddr_t)cse->uio.uio_iov[0].iov_base + cop->len, ++ cse->info.authsize))) { ++ dprintk("%s bad mac copy\n", __FUNCTION__); ++ goto bail; ++ } ++ ++bail: ++ if (crp) ++ crypto_freereq(crp); ++ if (cse->uio.uio_iov[0].iov_base) ++ kfree(cse->uio.uio_iov[0].iov_base); ++ ++ return (error); ++} ++ ++static int ++cryptodev_cb(void *op) ++{ ++ struct cryptop *crp = (struct cryptop *) op; ++ struct csession *cse = (struct csession *)crp->crp_opaque; ++ int error; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ error = crp->crp_etype; ++ if (error == EAGAIN) { ++ crp->crp_flags &= ~CRYPTO_F_DONE; ++#ifdef NOTYET ++ /* ++ * DAVIDM I am fairly sure that we should turn this into a batch ++ * request to stop bad karma/lockup, revisit ++ */ ++ crp->crp_flags |= CRYPTO_F_BATCH; ++#endif ++ return crypto_dispatch(crp); ++ } ++ if (error != 0 || (crp->crp_flags & CRYPTO_F_DONE)) { ++ cse->error = error; ++ wake_up_interruptible(&crp->crp_waitq); ++ } ++ return (0); ++} ++ ++static int ++cryptodevkey_cb(void *op) ++{ ++ struct cryptkop *krp = (struct cryptkop *) op; ++ dprintk("%s()\n", __FUNCTION__); ++ wake_up_interruptible(&krp->krp_waitq); ++ return (0); ++} ++ ++static int ++cryptodev_key(struct crypt_kop *kop) ++{ ++ struct cryptkop *krp = NULL; ++ int error = EINVAL; ++ int in, out, size, i; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (kop->crk_iparams + kop->crk_oparams > CRK_MAXPARAM) { ++ dprintk("%s params too big\n", __FUNCTION__); ++ return (EFBIG); ++ } ++ ++ in = kop->crk_iparams; ++ out = kop->crk_oparams; ++ switch (kop->crk_op) { ++ case CRK_MOD_EXP: ++ if (in == 3 && out == 1) ++ break; ++ return (EINVAL); ++ case CRK_MOD_EXP_CRT: ++ if (in == 6 && out == 1) ++ break; ++ return (EINVAL); ++ case CRK_DSA_SIGN: ++ if (in == 5 && out == 2) ++ break; ++ return (EINVAL); ++ case CRK_DSA_VERIFY: ++ if (in == 7 && out == 0) ++ break; ++ return (EINVAL); ++ case CRK_DH_COMPUTE_KEY: ++ if (in == 3 && out == 1) ++ break; ++ return (EINVAL); ++ default: ++ return (EINVAL); ++ } ++ ++ krp = (struct cryptkop *)kmalloc(sizeof *krp, GFP_KERNEL); ++ if (!krp) ++ return (ENOMEM); ++ bzero(krp, sizeof *krp); ++ krp->krp_op = kop->crk_op; ++ krp->krp_status = kop->crk_status; ++ krp->krp_iparams = kop->crk_iparams; ++ krp->krp_oparams = kop->crk_oparams; ++ krp->krp_crid = kop->crk_crid; ++ krp->krp_status = 0; ++ krp->krp_flags = CRYPTO_KF_CBIMM; ++ krp->krp_callback = (int (*) (struct cryptkop *)) cryptodevkey_cb; ++ init_waitqueue_head(&krp->krp_waitq); ++ ++ for (i = 0; i < CRK_MAXPARAM; i++) ++ krp->krp_param[i].crp_nbits = kop->crk_param[i].crp_nbits; ++ for (i = 0; i < krp->krp_iparams + krp->krp_oparams; i++) { ++ size = (krp->krp_param[i].crp_nbits + 7) / 8; ++ if (size == 0) ++ continue; ++ krp->krp_param[i].crp_p = (caddr_t) kmalloc(size, GFP_KERNEL); ++ if (i >= krp->krp_iparams) ++ continue; ++ error = copy_from_user(krp->krp_param[i].crp_p, ++ kop->crk_param[i].crp_p, size); ++ if (error) ++ goto fail; ++ } ++ ++ error = crypto_kdispatch(krp); ++ if (error) ++ goto fail; ++ ++ do { ++ error = wait_event_interruptible(krp->krp_waitq, ++ ((krp->krp_flags & CRYPTO_KF_DONE) != 0)); ++ /* ++ * we can't break out of this loop or we will leave behind ++ * a huge mess, however, staying here means if your driver ++ * is broken user applications can hang and not be killed. ++ * The solution, fix your driver :-) ++ */ ++ if (error) { ++ schedule(); ++ error = 0; ++ } ++ } while ((krp->krp_flags & CRYPTO_KF_DONE) == 0); ++ ++ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); ++ ++ kop->crk_crid = krp->krp_crid; /* device that did the work */ ++ if (krp->krp_status != 0) { ++ error = krp->krp_status; ++ goto fail; ++ } ++ ++ for (i = krp->krp_iparams; i < krp->krp_iparams + krp->krp_oparams; i++) { ++ size = (krp->krp_param[i].crp_nbits + 7) / 8; ++ if (size == 0) ++ continue; ++ error = copy_to_user(kop->crk_param[i].crp_p, krp->krp_param[i].crp_p, ++ size); ++ if (error) ++ goto fail; ++ } ++ ++fail: ++ if (krp) { ++ kop->crk_status = krp->krp_status; ++ for (i = 0; i < CRK_MAXPARAM; i++) { ++ if (krp->krp_param[i].crp_p) ++ kfree(krp->krp_param[i].crp_p); ++ } ++ kfree(krp); ++ } ++ return (error); ++} ++ ++static int ++cryptodev_find(struct crypt_find_op *find) ++{ ++ device_t dev; ++ ++ if (find->crid != -1) { ++ dev = crypto_find_device_byhid(find->crid); ++ if (dev == NULL) ++ return (ENOENT); ++ strlcpy(find->name, device_get_nameunit(dev), ++ sizeof(find->name)); ++ } else { ++ find->crid = crypto_find_driver(find->name); ++ if (find->crid == -1) ++ return (ENOENT); ++ } ++ return (0); ++} ++ ++static struct csession * ++csefind(struct fcrypt *fcr, u_int ses) ++{ ++ struct csession *cse; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ list_for_each_entry(cse, &fcr->csessions, list) ++ if (cse->ses == ses) ++ return (cse); ++ return (NULL); ++} ++ ++static int ++csedelete(struct fcrypt *fcr, struct csession *cse_del) ++{ ++ struct csession *cse; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ list_for_each_entry(cse, &fcr->csessions, list) { ++ if (cse == cse_del) { ++ list_del(&cse->list); ++ return (1); ++ } ++ } ++ return (0); ++} ++ ++static struct csession * ++cseadd(struct fcrypt *fcr, struct csession *cse) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ list_add_tail(&cse->list, &fcr->csessions); ++ cse->ses = fcr->sesn++; ++ return (cse); ++} ++ ++static struct csession * ++csecreate(struct fcrypt *fcr, u_int64_t sid, struct cryptoini *crie, ++ struct cryptoini *cria, struct csession_info *info) ++{ ++ struct csession *cse; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ cse = (struct csession *) kmalloc(sizeof(struct csession), GFP_KERNEL); ++ if (cse == NULL) ++ return NULL; ++ memset(cse, 0, sizeof(struct csession)); ++ ++ INIT_LIST_HEAD(&cse->list); ++ init_waitqueue_head(&cse->waitq); ++ ++ cse->key = crie->cri_key; ++ cse->keylen = crie->cri_klen/8; ++ cse->mackey = cria->cri_key; ++ cse->mackeylen = cria->cri_klen/8; ++ cse->sid = sid; ++ cse->cipher = crie->cri_alg; ++ cse->mac = cria->cri_alg; ++ cse->info = *info; ++ cseadd(fcr, cse); ++ return (cse); ++} ++ ++static int ++csefree(struct csession *cse) ++{ ++ int error; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ error = crypto_freesession(cse->sid); ++ if (cse->key) ++ kfree(cse->key); ++ if (cse->mackey) ++ kfree(cse->mackey); ++ kfree(cse); ++ return(error); ++} ++ ++static int ++cryptodev_ioctl( ++ struct inode *inode, ++ struct file *filp, ++ unsigned int cmd, ++ unsigned long arg) ++{ ++ struct cryptoini cria, crie; ++ struct fcrypt *fcr = filp->private_data; ++ struct csession *cse; ++ struct csession_info info; ++ struct session2_op sop; ++ struct crypt_op cop; ++ struct crypt_kop kop; ++ struct crypt_find_op fop; ++ u_int64_t sid; ++ u_int32_t ses = 0; ++ int feat, fd, error = 0, crid; ++ mm_segment_t fs; ++ ++ dprintk("%s(cmd=%x arg=%lx)\n", __FUNCTION__, cmd, arg); ++ ++ switch (cmd) { ++ ++ case CRIOGET: { ++ dprintk("%s(CRIOGET)\n", __FUNCTION__); ++ fs = get_fs(); ++ set_fs(get_ds()); ++ for (fd = 0; fd < files_fdtable(current->files)->max_fds; fd++) ++ if (files_fdtable(current->files)->fd[fd] == filp) ++ break; ++ fd = sys_dup(fd); ++ set_fs(fs); ++ put_user(fd, (int *) arg); ++ return IS_ERR_VALUE(fd) ? fd : 0; ++ } ++ ++#define CIOCGSESSSTR (cmd == CIOCGSESSION ? "CIOCGSESSION" : "CIOCGSESSION2") ++ case CIOCGSESSION: ++ case CIOCGSESSION2: ++ dprintk("%s(%s)\n", __FUNCTION__, CIOCGSESSSTR); ++ memset(&crie, 0, sizeof(crie)); ++ memset(&cria, 0, sizeof(cria)); ++ memset(&info, 0, sizeof(info)); ++ memset(&sop, 0, sizeof(sop)); ++ ++ if (copy_from_user(&sop, (void*)arg, (cmd == CIOCGSESSION) ? ++ sizeof(struct session_op) : sizeof(sop))) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ goto bail; ++ } ++ ++ switch (sop.cipher) { ++ case 0: ++ dprintk("%s(%s) - no cipher\n", __FUNCTION__, CIOCGSESSSTR); ++ break; ++ case CRYPTO_NULL_CBC: ++ info.blocksize = NULL_BLOCK_LEN; ++ info.minkey = NULL_MIN_KEY_LEN; ++ info.maxkey = NULL_MAX_KEY_LEN; ++ break; ++ case CRYPTO_DES_CBC: ++ info.blocksize = DES_BLOCK_LEN; ++ info.minkey = DES_MIN_KEY_LEN; ++ info.maxkey = DES_MAX_KEY_LEN; ++ break; ++ case CRYPTO_3DES_CBC: ++ info.blocksize = DES3_BLOCK_LEN; ++ info.minkey = DES3_MIN_KEY_LEN; ++ info.maxkey = DES3_MAX_KEY_LEN; ++ break; ++ case CRYPTO_BLF_CBC: ++ info.blocksize = BLOWFISH_BLOCK_LEN; ++ info.minkey = BLOWFISH_MIN_KEY_LEN; ++ info.maxkey = BLOWFISH_MAX_KEY_LEN; ++ break; ++ case CRYPTO_CAST_CBC: ++ info.blocksize = CAST128_BLOCK_LEN; ++ info.minkey = CAST128_MIN_KEY_LEN; ++ info.maxkey = CAST128_MAX_KEY_LEN; ++ break; ++ case CRYPTO_SKIPJACK_CBC: ++ info.blocksize = SKIPJACK_BLOCK_LEN; ++ info.minkey = SKIPJACK_MIN_KEY_LEN; ++ info.maxkey = SKIPJACK_MAX_KEY_LEN; ++ break; ++ case CRYPTO_AES_CBC: ++ info.blocksize = AES_BLOCK_LEN; ++ info.minkey = AES_MIN_KEY_LEN; ++ info.maxkey = AES_MAX_KEY_LEN; ++ break; ++ case CRYPTO_ARC4: ++ info.blocksize = ARC4_BLOCK_LEN; ++ info.minkey = ARC4_MIN_KEY_LEN; ++ info.maxkey = ARC4_MAX_KEY_LEN; ++ break; ++ case CRYPTO_CAMELLIA_CBC: ++ info.blocksize = CAMELLIA_BLOCK_LEN; ++ info.minkey = CAMELLIA_MIN_KEY_LEN; ++ info.maxkey = CAMELLIA_MAX_KEY_LEN; ++ break; ++ default: ++ dprintk("%s(%s) - bad cipher\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ switch (sop.mac) { ++ case 0: ++ dprintk("%s(%s) - no mac\n", __FUNCTION__, CIOCGSESSSTR); ++ break; ++ case CRYPTO_NULL_HMAC: ++ info.authsize = NULL_HASH_LEN; ++ break; ++ case CRYPTO_MD5: ++ info.authsize = MD5_HASH_LEN; ++ break; ++ case CRYPTO_SHA1: ++ info.authsize = SHA1_HASH_LEN; ++ break; ++ case CRYPTO_SHA2_256: ++ info.authsize = SHA2_256_HASH_LEN; ++ break; ++ case CRYPTO_SHA2_384: ++ info.authsize = SHA2_384_HASH_LEN; ++ break; ++ case CRYPTO_SHA2_512: ++ info.authsize = SHA2_512_HASH_LEN; ++ break; ++ case CRYPTO_RIPEMD160: ++ info.authsize = RIPEMD160_HASH_LEN; ++ break; ++ case CRYPTO_MD5_HMAC: ++ info.authsize = MD5_HASH_LEN; ++ info.authkey = 16; ++ break; ++ case CRYPTO_SHA1_HMAC: ++ info.authsize = SHA1_HASH_LEN; ++ info.authkey = 20; ++ break; ++ case CRYPTO_SHA2_256_HMAC: ++ info.authsize = SHA2_256_HASH_LEN; ++ info.authkey = 32; ++ break; ++ case CRYPTO_SHA2_384_HMAC: ++ info.authsize = SHA2_384_HASH_LEN; ++ info.authkey = 48; ++ break; ++ case CRYPTO_SHA2_512_HMAC: ++ info.authsize = SHA2_512_HASH_LEN; ++ info.authkey = 64; ++ break; ++ case CRYPTO_RIPEMD160_HMAC: ++ info.authsize = RIPEMD160_HASH_LEN; ++ info.authkey = 20; ++ break; ++ default: ++ dprintk("%s(%s) - bad mac\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ if (info.blocksize) { ++ crie.cri_alg = sop.cipher; ++ crie.cri_klen = sop.keylen * 8; ++ if ((info.maxkey && sop.keylen > info.maxkey) || ++ sop.keylen < info.minkey) { ++ dprintk("%s(%s) - bad key\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ crie.cri_key = (u_int8_t *) kmalloc(crie.cri_klen/8+1, GFP_KERNEL); ++ if (copy_from_user(crie.cri_key, sop.key, ++ crie.cri_klen/8)) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ goto bail; ++ } ++ if (info.authsize) ++ crie.cri_next = &cria; ++ } ++ ++ if (info.authsize) { ++ cria.cri_alg = sop.mac; ++ cria.cri_klen = sop.mackeylen * 8; ++ if (info.authkey && sop.mackeylen != info.authkey) { ++ dprintk("%s(%s) - mackeylen %d != %d\n", __FUNCTION__, ++ CIOCGSESSSTR, sop.mackeylen, info.authkey); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ if (cria.cri_klen) { ++ cria.cri_key = (u_int8_t *) kmalloc(cria.cri_klen/8,GFP_KERNEL); ++ if (copy_from_user(cria.cri_key, sop.mackey, ++ cria.cri_klen / 8)) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ goto bail; ++ } ++ } ++ } ++ ++ /* NB: CIOGSESSION2 has the crid */ ++ if (cmd == CIOCGSESSION2) { ++ crid = sop.crid; ++ error = checkcrid(crid); ++ if (error) { ++ dprintk("%s(%s) - checkcrid %x\n", __FUNCTION__, ++ CIOCGSESSSTR, error); ++ goto bail; ++ } ++ } else { ++ /* allow either HW or SW to be used */ ++ crid = CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; ++ } ++ error = crypto_newsession(&sid, (info.blocksize ? &crie : &cria), crid); ++ if (error) { ++ dprintk("%s(%s) - newsession %d\n",__FUNCTION__,CIOCGSESSSTR,error); ++ goto bail; ++ } ++ ++ cse = csecreate(fcr, sid, &crie, &cria, &info); ++ if (cse == NULL) { ++ crypto_freesession(sid); ++ error = EINVAL; ++ dprintk("%s(%s) - csecreate failed\n", __FUNCTION__, CIOCGSESSSTR); ++ goto bail; ++ } ++ sop.ses = cse->ses; ++ ++ if (cmd == CIOCGSESSION2) { ++ /* return hardware/driver id */ ++ sop.crid = CRYPTO_SESID2HID(cse->sid); ++ } ++ ++ if (copy_to_user((void*)arg, &sop, (cmd == CIOCGSESSION) ? ++ sizeof(struct session_op) : sizeof(sop))) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ } ++bail: ++ if (error) { ++ dprintk("%s(%s) - bail %d\n", __FUNCTION__, CIOCGSESSSTR, error); ++ if (crie.cri_key) ++ kfree(crie.cri_key); ++ if (cria.cri_key) ++ kfree(cria.cri_key); ++ } ++ break; ++ case CIOCFSESSION: ++ dprintk("%s(CIOCFSESSION)\n", __FUNCTION__); ++ get_user(ses, (uint32_t*)arg); ++ cse = csefind(fcr, ses); ++ if (cse == NULL) { ++ error = EINVAL; ++ dprintk("%s(CIOCFSESSION) - Fail %d\n", __FUNCTION__, error); ++ break; ++ } ++ csedelete(fcr, cse); ++ error = csefree(cse); ++ break; ++ case CIOCCRYPT: ++ dprintk("%s(CIOCCRYPT)\n", __FUNCTION__); ++ if(copy_from_user(&cop, (void*)arg, sizeof(cop))) { ++ dprintk("%s(CIOCCRYPT) - bad copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ cse = csefind(fcr, cop.ses); ++ if (cse == NULL) { ++ error = EINVAL; ++ dprintk("%s(CIOCCRYPT) - Fail %d\n", __FUNCTION__, error); ++ break; ++ } ++ error = cryptodev_op(cse, &cop); ++ if(copy_to_user((void*)arg, &cop, sizeof(cop))) { ++ dprintk("%s(CIOCCRYPT) - bad return copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ break; ++ case CIOCKEY: ++ case CIOCKEY2: ++ dprintk("%s(CIOCKEY)\n", __FUNCTION__); ++ if (!crypto_userasymcrypto) ++ return (EPERM); /* XXX compat? */ ++ if(copy_from_user(&kop, (void*)arg, sizeof(kop))) { ++ dprintk("%s(CIOCKEY) - bad copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ if (cmd == CIOCKEY) { ++ /* NB: crypto core enforces s/w driver use */ ++ kop.crk_crid = ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; ++ } ++ error = cryptodev_key(&kop); ++ if(copy_to_user((void*)arg, &kop, sizeof(kop))) { ++ dprintk("%s(CIOCGKEY) - bad return copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ break; ++ case CIOCASYMFEAT: ++ dprintk("%s(CIOCASYMFEAT)\n", __FUNCTION__); ++ if (!crypto_userasymcrypto) { ++ /* ++ * NB: if user asym crypto operations are ++ * not permitted return "no algorithms" ++ * so well-behaved applications will just ++ * fallback to doing them in software. ++ */ ++ feat = 0; ++ } else ++ error = crypto_getfeat(&feat); ++ if (!error) { ++ error = copy_to_user((void*)arg, &feat, sizeof(feat)); ++ } ++ break; ++ case CIOCFINDDEV: ++ if (copy_from_user(&fop, (void*)arg, sizeof(fop))) { ++ dprintk("%s(CIOCFINDDEV) - bad copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ error = cryptodev_find(&fop); ++ if (copy_to_user((void*)arg, &fop, sizeof(fop))) { ++ dprintk("%s(CIOCFINDDEV) - bad return copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ break; ++ default: ++ dprintk("%s(unknown ioctl 0x%x)\n", __FUNCTION__, cmd); ++ error = EINVAL; ++ break; ++ } ++ return(-error); ++} ++ ++#ifdef HAVE_UNLOCKED_IOCTL ++static long ++cryptodev_unlocked_ioctl( ++ struct file *filp, ++ unsigned int cmd, ++ unsigned long arg) ++{ ++ return cryptodev_ioctl(NULL, filp, cmd, arg); ++} ++#endif ++ ++static int ++cryptodev_open(struct inode *inode, struct file *filp) ++{ ++ struct fcrypt *fcr; ++ ++ dprintk("%s()\n", __FUNCTION__); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++ /* ++ * on 2.6.35 private_data points to a miscdevice structure, we override ++ * it, which is currently safe to do. ++ */ ++ if (filp->private_data) { ++ printk("cryptodev: Private data already exists - %p!\n", filp->private_data); ++ return(-ENODEV); ++ } ++#endif ++ ++ fcr = kmalloc(sizeof(*fcr), GFP_KERNEL); ++ if (!fcr) { ++ dprintk("%s() - malloc failed\n", __FUNCTION__); ++ return(-ENOMEM); ++ } ++ memset(fcr, 0, sizeof(*fcr)); ++ ++ INIT_LIST_HEAD(&fcr->csessions); ++ filp->private_data = fcr; ++ return(0); ++} ++ ++static int ++cryptodev_release(struct inode *inode, struct file *filp) ++{ ++ struct fcrypt *fcr = filp->private_data; ++ struct csession *cse, *tmp; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (!filp) { ++ printk("cryptodev: No private data on release\n"); ++ return(0); ++ } ++ ++ list_for_each_entry_safe(cse, tmp, &fcr->csessions, list) { ++ list_del(&cse->list); ++ (void)csefree(cse); ++ } ++ filp->private_data = NULL; ++ kfree(fcr); ++ return(0); ++} ++ ++static struct file_operations cryptodev_fops = { ++ .owner = THIS_MODULE, ++ .open = cryptodev_open, ++ .release = cryptodev_release, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ .ioctl = cryptodev_ioctl, ++#endif ++#ifdef HAVE_UNLOCKED_IOCTL ++ .unlocked_ioctl = cryptodev_unlocked_ioctl, ++#endif ++}; ++ ++static struct miscdevice cryptodev = { ++ .minor = CRYPTODEV_MINOR, ++ .name = "crypto", ++ .fops = &cryptodev_fops, ++}; ++ ++static int __init ++cryptodev_init(void) ++{ ++ int rc; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, cryptodev_init); ++ rc = misc_register(&cryptodev); ++ if (rc) { ++ printk(KERN_ERR "cryptodev: registration of /dev/crypto failed\n"); ++ return(rc); ++ } ++ ++ return(0); ++} ++ ++static void __exit ++cryptodev_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ misc_deregister(&cryptodev); ++} ++ ++module_init(cryptodev_init); ++module_exit(cryptodev_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Cryptodev (user interface to OCF)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptodev.h linux-3.0.4/crypto/ocf/cryptodev.h +--- linux-3.0.4.orig/crypto/ocf/cryptodev.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptodev.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,480 @@ ++/* $FreeBSD: src/sys/opencrypto/cryptodev.h,v 1.25 2007/05/09 19:37:02 gnn Exp $ */ ++/* $OpenBSD: cryptodev.h,v 1.31 2002/06/11 11:14:29 beck Exp $ */ ++ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) ++ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting ++ * ++ * This code was written by Angelos D. Keromytis in Athens, Greece, in ++ * February 2000. Network Security Technologies Inc. (NSTI) kindly ++ * supported the development of this code. ++ * ++ * Copyright (c) 2000 Angelos D. Keromytis ++ * ++ * Permission to use, copy, and modify this software with or without fee ++ * is hereby granted, provided that this entire notice is included in ++ * all source code copies of any software which is or includes a copy or ++ * modification of this software. ++ * ++ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY ++ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE ++ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR ++ * PURPOSE. ++ * ++ * Copyright (c) 2001 Theo de Raadt ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++#ifndef _CRYPTO_CRYPTO_H_ ++#define _CRYPTO_CRYPTO_H_ ++ ++/* Some initial values */ ++#define CRYPTO_DRIVERS_INITIAL 4 ++#define CRYPTO_SW_SESSIONS 32 ++ ++/* Hash values */ ++#define NULL_HASH_LEN 0 ++#define MD5_HASH_LEN 16 ++#define SHA1_HASH_LEN 20 ++#define RIPEMD160_HASH_LEN 20 ++#define SHA2_256_HASH_LEN 32 ++#define SHA2_384_HASH_LEN 48 ++#define SHA2_512_HASH_LEN 64 ++#define MD5_KPDK_HASH_LEN 16 ++#define SHA1_KPDK_HASH_LEN 20 ++/* Maximum hash algorithm result length */ ++#define HASH_MAX_LEN SHA2_512_HASH_LEN /* Keep this updated */ ++ ++/* HMAC values */ ++#define NULL_HMAC_BLOCK_LEN 1 ++#define MD5_HMAC_BLOCK_LEN 64 ++#define SHA1_HMAC_BLOCK_LEN 64 ++#define RIPEMD160_HMAC_BLOCK_LEN 64 ++#define SHA2_256_HMAC_BLOCK_LEN 64 ++#define SHA2_384_HMAC_BLOCK_LEN 128 ++#define SHA2_512_HMAC_BLOCK_LEN 128 ++/* Maximum HMAC block length */ ++#define HMAC_MAX_BLOCK_LEN SHA2_512_HMAC_BLOCK_LEN /* Keep this updated */ ++#define HMAC_IPAD_VAL 0x36 ++#define HMAC_OPAD_VAL 0x5C ++ ++/* Encryption algorithm block sizes */ ++#define NULL_BLOCK_LEN 1 ++#define DES_BLOCK_LEN 8 ++#define DES3_BLOCK_LEN 8 ++#define BLOWFISH_BLOCK_LEN 8 ++#define SKIPJACK_BLOCK_LEN 8 ++#define CAST128_BLOCK_LEN 8 ++#define RIJNDAEL128_BLOCK_LEN 16 ++#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN ++#define CAMELLIA_BLOCK_LEN 16 ++#define ARC4_BLOCK_LEN 1 ++#define EALG_MAX_BLOCK_LEN AES_BLOCK_LEN /* Keep this updated */ ++ ++/* Encryption algorithm min and max key sizes */ ++#define NULL_MIN_KEY_LEN 0 ++#define NULL_MAX_KEY_LEN 0 ++#define DES_MIN_KEY_LEN 8 ++#define DES_MAX_KEY_LEN 8 ++#define DES3_MIN_KEY_LEN 24 ++#define DES3_MAX_KEY_LEN 24 ++#define BLOWFISH_MIN_KEY_LEN 4 ++#define BLOWFISH_MAX_KEY_LEN 56 ++#define SKIPJACK_MIN_KEY_LEN 10 ++#define SKIPJACK_MAX_KEY_LEN 10 ++#define CAST128_MIN_KEY_LEN 5 ++#define CAST128_MAX_KEY_LEN 16 ++#define RIJNDAEL128_MIN_KEY_LEN 16 ++#define RIJNDAEL128_MAX_KEY_LEN 32 ++#define AES_MIN_KEY_LEN RIJNDAEL128_MIN_KEY_LEN ++#define AES_MAX_KEY_LEN RIJNDAEL128_MAX_KEY_LEN ++#define CAMELLIA_MIN_KEY_LEN 16 ++#define CAMELLIA_MAX_KEY_LEN 32 ++#define ARC4_MIN_KEY_LEN 1 ++#define ARC4_MAX_KEY_LEN 256 ++ ++/* Max size of data that can be processed */ ++#define CRYPTO_MAX_DATA_LEN 64*1024 - 1 ++ ++#define CRYPTO_ALGORITHM_MIN 1 ++#define CRYPTO_DES_CBC 1 ++#define CRYPTO_3DES_CBC 2 ++#define CRYPTO_BLF_CBC 3 ++#define CRYPTO_CAST_CBC 4 ++#define CRYPTO_SKIPJACK_CBC 5 ++#define CRYPTO_MD5_HMAC 6 ++#define CRYPTO_SHA1_HMAC 7 ++#define CRYPTO_RIPEMD160_HMAC 8 ++#define CRYPTO_MD5_KPDK 9 ++#define CRYPTO_SHA1_KPDK 10 ++#define CRYPTO_RIJNDAEL128_CBC 11 /* 128 bit blocksize */ ++#define CRYPTO_AES_CBC 11 /* 128 bit blocksize -- the same as above */ ++#define CRYPTO_ARC4 12 ++#define CRYPTO_MD5 13 ++#define CRYPTO_SHA1 14 ++#define CRYPTO_NULL_HMAC 15 ++#define CRYPTO_NULL_CBC 16 ++#define CRYPTO_DEFLATE_COMP 17 /* Deflate compression algorithm */ ++#define CRYPTO_SHA2_256_HMAC 18 ++#define CRYPTO_SHA2_384_HMAC 19 ++#define CRYPTO_SHA2_512_HMAC 20 ++#define CRYPTO_CAMELLIA_CBC 21 ++#define CRYPTO_SHA2_256 22 ++#define CRYPTO_SHA2_384 23 ++#define CRYPTO_SHA2_512 24 ++#define CRYPTO_RIPEMD160 25 ++#define CRYPTO_LZS_COMP 26 ++#define CRYPTO_ALGORITHM_MAX 26 /* Keep updated - see above */ ++ ++/* Algorithm flags */ ++#define CRYPTO_ALG_FLAG_SUPPORTED 0x01 /* Algorithm is supported */ ++#define CRYPTO_ALG_FLAG_RNG_ENABLE 0x02 /* Has HW RNG for DH/DSA */ ++#define CRYPTO_ALG_FLAG_DSA_SHA 0x04 /* Can do SHA on msg */ ++ ++/* ++ * Crypto driver/device flags. They can set in the crid ++ * parameter when creating a session or submitting a key ++ * op to affect the device/driver assigned. If neither ++ * of these are specified then the crid is assumed to hold ++ * the driver id of an existing (and suitable) device that ++ * must be used to satisfy the request. ++ */ ++#define CRYPTO_FLAG_HARDWARE 0x01000000 /* hardware accelerated */ ++#define CRYPTO_FLAG_SOFTWARE 0x02000000 /* software implementation */ ++ ++/* NB: deprecated */ ++struct session_op { ++ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ ++ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ ++ ++ u_int32_t keylen; /* cipher key */ ++ caddr_t key; ++ int mackeylen; /* mac key */ ++ caddr_t mackey; ++ ++ u_int32_t ses; /* returns: session # */ ++}; ++ ++struct session2_op { ++ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ ++ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ ++ ++ u_int32_t keylen; /* cipher key */ ++ caddr_t key; ++ int mackeylen; /* mac key */ ++ caddr_t mackey; ++ ++ u_int32_t ses; /* returns: session # */ ++ int crid; /* driver id + flags (rw) */ ++ int pad[4]; /* for future expansion */ ++}; ++ ++struct crypt_op { ++ u_int32_t ses; ++ u_int16_t op; /* i.e. COP_ENCRYPT */ ++#define COP_NONE 0 ++#define COP_ENCRYPT 1 ++#define COP_DECRYPT 2 ++ u_int16_t flags; ++#define COP_F_BATCH 0x0008 /* Batch op if possible */ ++ u_int len; ++ caddr_t src, dst; /* become iov[] inside kernel */ ++ caddr_t mac; /* must be big enough for chosen MAC */ ++ caddr_t iv; ++}; ++ ++/* ++ * Parameters for looking up a crypto driver/device by ++ * device name or by id. The latter are returned for ++ * created sessions (crid) and completed key operations. ++ */ ++struct crypt_find_op { ++ int crid; /* driver id + flags */ ++ char name[32]; /* device/driver name */ ++}; ++ ++/* bignum parameter, in packed bytes, ... */ ++struct crparam { ++ caddr_t crp_p; ++ u_int crp_nbits; ++}; ++ ++#define CRK_MAXPARAM 8 ++ ++struct crypt_kop { ++ u_int crk_op; /* ie. CRK_MOD_EXP or other */ ++ u_int crk_status; /* return status */ ++ u_short crk_iparams; /* # of input parameters */ ++ u_short crk_oparams; /* # of output parameters */ ++ u_int crk_crid; /* NB: only used by CIOCKEY2 (rw) */ ++ struct crparam crk_param[CRK_MAXPARAM]; ++}; ++#define CRK_ALGORITM_MIN 0 ++#define CRK_MOD_EXP 0 ++#define CRK_MOD_EXP_CRT 1 ++#define CRK_DSA_SIGN 2 ++#define CRK_DSA_VERIFY 3 ++#define CRK_DH_COMPUTE_KEY 4 ++#define CRK_ALGORITHM_MAX 4 /* Keep updated - see below */ ++ ++#define CRF_MOD_EXP (1 << CRK_MOD_EXP) ++#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT) ++#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN) ++#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY) ++#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY) ++ ++/* ++ * done against open of /dev/crypto, to get a cloned descriptor. ++ * Please use F_SETFD against the cloned descriptor. ++ */ ++#define CRIOGET _IOWR('c', 100, u_int32_t) ++#define CRIOASYMFEAT CIOCASYMFEAT ++#define CRIOFINDDEV CIOCFINDDEV ++ ++/* the following are done against the cloned descriptor */ ++#define CIOCGSESSION _IOWR('c', 101, struct session_op) ++#define CIOCFSESSION _IOW('c', 102, u_int32_t) ++#define CIOCCRYPT _IOWR('c', 103, struct crypt_op) ++#define CIOCKEY _IOWR('c', 104, struct crypt_kop) ++#define CIOCASYMFEAT _IOR('c', 105, u_int32_t) ++#define CIOCGSESSION2 _IOWR('c', 106, struct session2_op) ++#define CIOCKEY2 _IOWR('c', 107, struct crypt_kop) ++#define CIOCFINDDEV _IOWR('c', 108, struct crypt_find_op) ++ ++struct cryptotstat { ++ struct timespec acc; /* total accumulated time */ ++ struct timespec min; /* min time */ ++ struct timespec max; /* max time */ ++ u_int32_t count; /* number of observations */ ++}; ++ ++struct cryptostats { ++ u_int32_t cs_ops; /* symmetric crypto ops submitted */ ++ u_int32_t cs_errs; /* symmetric crypto ops that failed */ ++ u_int32_t cs_kops; /* asymetric/key ops submitted */ ++ u_int32_t cs_kerrs; /* asymetric/key ops that failed */ ++ u_int32_t cs_intrs; /* crypto swi thread activations */ ++ u_int32_t cs_rets; /* crypto return thread activations */ ++ u_int32_t cs_blocks; /* symmetric op driver block */ ++ u_int32_t cs_kblocks; /* symmetric op driver block */ ++ /* ++ * When CRYPTO_TIMING is defined at compile time and the ++ * sysctl debug.crypto is set to 1, the crypto system will ++ * accumulate statistics about how long it takes to process ++ * crypto requests at various points during processing. ++ */ ++ struct cryptotstat cs_invoke; /* crypto_dipsatch -> crypto_invoke */ ++ struct cryptotstat cs_done; /* crypto_invoke -> crypto_done */ ++ struct cryptotstat cs_cb; /* crypto_done -> callback */ ++ struct cryptotstat cs_finis; /* callback -> callback return */ ++ ++ u_int32_t cs_drops; /* crypto ops dropped due to congestion */ ++}; ++ ++#ifdef __KERNEL__ ++ ++/* Standard initialization structure beginning */ ++struct cryptoini { ++ int cri_alg; /* Algorithm to use */ ++ int cri_klen; /* Key length, in bits */ ++ int cri_mlen; /* Number of bytes we want from the ++ entire hash. 0 means all. */ ++ caddr_t cri_key; /* key to use */ ++ u_int8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */ ++ struct cryptoini *cri_next; ++}; ++ ++/* Describe boundaries of a single crypto operation */ ++struct cryptodesc { ++ int crd_skip; /* How many bytes to ignore from start */ ++ int crd_len; /* How many bytes to process */ ++ int crd_inject; /* Where to inject results, if applicable */ ++ int crd_flags; ++ ++#define CRD_F_ENCRYPT 0x01 /* Set when doing encryption */ ++#define CRD_F_IV_PRESENT 0x02 /* When encrypting, IV is already in ++ place, so don't copy. */ ++#define CRD_F_IV_EXPLICIT 0x04 /* IV explicitly provided */ ++#define CRD_F_DSA_SHA_NEEDED 0x08 /* Compute SHA-1 of buffer for DSA */ ++#define CRD_F_KEY_EXPLICIT 0x10 /* Key explicitly provided */ ++#define CRD_F_COMP 0x0f /* Set when doing compression */ ++ ++ struct cryptoini CRD_INI; /* Initialization/context data */ ++#define crd_iv CRD_INI.cri_iv ++#define crd_key CRD_INI.cri_key ++#define crd_alg CRD_INI.cri_alg ++#define crd_klen CRD_INI.cri_klen ++#define crd_mlen CRD_INI.cri_mlen ++ ++ struct cryptodesc *crd_next; ++}; ++ ++/* Structure describing complete operation */ ++struct cryptop { ++ struct list_head crp_next; ++ wait_queue_head_t crp_waitq; ++ ++ u_int64_t crp_sid; /* Session ID */ ++ int crp_ilen; /* Input data total length */ ++ int crp_olen; /* Result total length */ ++ ++ int crp_etype; /* ++ * Error type (zero means no error). ++ * All error codes except EAGAIN ++ * indicate possible data corruption (as in, ++ * the data have been touched). On all ++ * errors, the crp_sid may have changed ++ * (reset to a new one), so the caller ++ * should always check and use the new ++ * value on future requests. ++ */ ++ int crp_flags; ++ ++#define CRYPTO_F_SKBUF 0x0001 /* Input/output are skbuf chains */ ++#define CRYPTO_F_IOV 0x0002 /* Input/output are uio */ ++#define CRYPTO_F_REL 0x0004 /* Must return data in same place */ ++#define CRYPTO_F_BATCH 0x0008 /* Batch op if possible */ ++#define CRYPTO_F_CBIMM 0x0010 /* Do callback immediately */ ++#define CRYPTO_F_DONE 0x0020 /* Operation completed */ ++#define CRYPTO_F_CBIFSYNC 0x0040 /* Do CBIMM if op is synchronous */ ++ ++ caddr_t crp_buf; /* Data to be processed */ ++ caddr_t crp_opaque; /* Opaque pointer, passed along */ ++ struct cryptodesc *crp_desc; /* Linked list of processing descriptors */ ++ ++ int (*crp_callback)(struct cryptop *); /* Callback function */ ++}; ++ ++#define CRYPTO_BUF_CONTIG 0x0 ++#define CRYPTO_BUF_IOV 0x1 ++#define CRYPTO_BUF_SKBUF 0x2 ++ ++#define CRYPTO_OP_DECRYPT 0x0 ++#define CRYPTO_OP_ENCRYPT 0x1 ++ ++/* ++ * Hints passed to process methods. ++ */ ++#define CRYPTO_HINT_MORE 0x1 /* more ops coming shortly */ ++ ++struct cryptkop { ++ struct list_head krp_next; ++ wait_queue_head_t krp_waitq; ++ ++ int krp_flags; ++#define CRYPTO_KF_DONE 0x0001 /* Operation completed */ ++#define CRYPTO_KF_CBIMM 0x0002 /* Do callback immediately */ ++ ++ u_int krp_op; /* ie. CRK_MOD_EXP or other */ ++ u_int krp_status; /* return status */ ++ u_short krp_iparams; /* # of input parameters */ ++ u_short krp_oparams; /* # of output parameters */ ++ u_int krp_crid; /* desired device, etc. */ ++ u_int32_t krp_hid; ++ struct crparam krp_param[CRK_MAXPARAM]; /* kvm */ ++ int (*krp_callback)(struct cryptkop *); ++}; ++ ++#include ++ ++/* ++ * Session ids are 64 bits. The lower 32 bits contain a "local id" which ++ * is a driver-private session identifier. The upper 32 bits contain a ++ * "hardware id" used by the core crypto code to identify the driver and ++ * a copy of the driver's capabilities that can be used by client code to ++ * optimize operation. ++ */ ++#define CRYPTO_SESID2HID(_sid) (((_sid) >> 32) & 0x00ffffff) ++#define CRYPTO_SESID2CAPS(_sid) (((_sid) >> 32) & 0xff000000) ++#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff) ++ ++extern int crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int hard); ++extern int crypto_freesession(u_int64_t sid); ++#define CRYPTOCAP_F_HARDWARE CRYPTO_FLAG_HARDWARE ++#define CRYPTOCAP_F_SOFTWARE CRYPTO_FLAG_SOFTWARE ++#define CRYPTOCAP_F_SYNC 0x04000000 /* operates synchronously */ ++extern int32_t crypto_get_driverid(device_t dev, int flags); ++extern int crypto_find_driver(const char *); ++extern device_t crypto_find_device_byhid(int hid); ++extern int crypto_getcaps(int hid); ++extern int crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, ++ u_int32_t flags); ++extern int crypto_kregister(u_int32_t, int, u_int32_t); ++extern int crypto_unregister(u_int32_t driverid, int alg); ++extern int crypto_unregister_all(u_int32_t driverid); ++extern int crypto_dispatch(struct cryptop *crp); ++extern int crypto_kdispatch(struct cryptkop *); ++#define CRYPTO_SYMQ 0x1 ++#define CRYPTO_ASYMQ 0x2 ++extern int crypto_unblock(u_int32_t, int); ++extern void crypto_done(struct cryptop *crp); ++extern void crypto_kdone(struct cryptkop *); ++extern int crypto_getfeat(int *); ++ ++extern void crypto_freereq(struct cryptop *crp); ++extern struct cryptop *crypto_getreq(int num); ++ ++extern int crypto_usercrypto; /* userland may do crypto requests */ ++extern int crypto_userasymcrypto; /* userland may do asym crypto reqs */ ++extern int crypto_devallowsoft; /* only use hardware crypto */ ++ ++/* ++ * random number support, crypto_unregister_all will unregister ++ */ ++extern int crypto_rregister(u_int32_t driverid, ++ int (*read_random)(void *arg, u_int32_t *buf, int len), void *arg); ++extern int crypto_runregister_all(u_int32_t driverid); ++ ++/* ++ * Crypto-related utility routines used mainly by drivers. ++ * ++ * XXX these don't really belong here; but for now they're ++ * kept apart from the rest of the system. ++ */ ++struct uio; ++extern void cuio_copydata(struct uio* uio, int off, int len, caddr_t cp); ++extern void cuio_copyback(struct uio* uio, int off, int len, caddr_t cp); ++extern struct iovec *cuio_getptr(struct uio *uio, int loc, int *off); ++ ++extern void crypto_copyback(int flags, caddr_t buf, int off, int size, ++ caddr_t in); ++extern void crypto_copydata(int flags, caddr_t buf, int off, int size, ++ caddr_t out); ++extern int crypto_apply(int flags, caddr_t buf, int off, int len, ++ int (*f)(void *, void *, u_int), void *arg); ++ ++#endif /* __KERNEL__ */ ++#endif /* _CRYPTO_CRYPTO_H_ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptosoft.c linux-3.0.4/crypto/ocf/cryptosoft.c +--- linux-3.0.4.orig/crypto/ocf/cryptosoft.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptosoft.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1320 @@ ++/* ++ * An OCF module that uses the linux kernel cryptoapi, based on the ++ * original cryptosoft for BSD by Angelos D. Keromytis (angelos@cis.upenn.edu) ++ * but is mostly unrecognisable, ++ * ++ * Written by David McCullough ++ * Copyright (C) 2004-2011 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ * --------------------------------------------------------------------------- ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) ++#include ++#endif ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) ++#include ++#endif ++ ++#include ++#include ++ ++struct { ++ softc_device_decl sc_dev; ++} swcr_softc; ++ ++#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) ++ ++#define SW_TYPE_CIPHER 0x01 ++#define SW_TYPE_HMAC 0x02 ++#define SW_TYPE_HASH 0x04 ++#define SW_TYPE_COMP 0x08 ++#define SW_TYPE_BLKCIPHER 0x10 ++#define SW_TYPE_ALG_MASK 0x1f ++ ++#define SW_TYPE_ASYNC 0x8000 ++ ++#define SW_TYPE_INUSE 0x10000000 ++ ++/* We change some of the above if we have an async interface */ ++ ++#define SW_TYPE_ALG_AMASK (SW_TYPE_ALG_MASK | SW_TYPE_ASYNC) ++ ++#define SW_TYPE_ABLKCIPHER (SW_TYPE_BLKCIPHER | SW_TYPE_ASYNC) ++#define SW_TYPE_AHASH (SW_TYPE_HASH | SW_TYPE_ASYNC) ++#define SW_TYPE_AHMAC (SW_TYPE_HMAC | SW_TYPE_ASYNC) ++ ++#define SCATTERLIST_MAX 16 ++ ++struct swcr_data { ++ struct work_struct workq; ++ int sw_type; ++ int sw_alg; ++ struct crypto_tfm *sw_tfm; ++ spinlock_t sw_tfm_lock; ++ union { ++ struct { ++ char *sw_key; ++ int sw_klen; ++ int sw_mlen; ++ } hmac; ++ void *sw_comp_buf; ++ } u; ++ struct swcr_data *sw_next; ++}; ++ ++struct swcr_req { ++ struct swcr_data *sw_head; ++ struct swcr_data *sw; ++ struct cryptop *crp; ++ struct cryptodesc *crd; ++ struct scatterlist sg[SCATTERLIST_MAX]; ++ unsigned char iv[EALG_MAX_BLOCK_LEN]; ++ char result[HASH_MAX_LEN]; ++ void *crypto_req; ++}; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++static kmem_cache_t *swcr_req_cache; ++#else ++static struct kmem_cache *swcr_req_cache; ++#endif ++ ++#ifndef CRYPTO_TFM_MODE_CBC ++/* ++ * As of linux-2.6.21 this is no longer defined, and presumably no longer ++ * needed to be passed into the crypto core code. ++ */ ++#define CRYPTO_TFM_MODE_CBC 0 ++#define CRYPTO_TFM_MODE_ECB 0 ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ++ /* ++ * Linux 2.6.19 introduced a new Crypto API, setup macro's to convert new ++ * API into old API. ++ */ ++ ++ /* Symmetric/Block Cipher */ ++ struct blkcipher_desc ++ { ++ struct crypto_tfm *tfm; ++ void *info; ++ }; ++ #define ecb(X) #X , CRYPTO_TFM_MODE_ECB ++ #define cbc(X) #X , CRYPTO_TFM_MODE_CBC ++ #define crypto_has_blkcipher(X, Y, Z) crypto_alg_available(X, 0) ++ #define crypto_blkcipher_cast(X) X ++ #define crypto_blkcipher_tfm(X) X ++ #define crypto_alloc_blkcipher(X, Y, Z) crypto_alloc_tfm(X, mode) ++ #define crypto_blkcipher_ivsize(X) crypto_tfm_alg_ivsize(X) ++ #define crypto_blkcipher_blocksize(X) crypto_tfm_alg_blocksize(X) ++ #define crypto_blkcipher_setkey(X, Y, Z) crypto_cipher_setkey(X, Y, Z) ++ #define crypto_blkcipher_encrypt_iv(W, X, Y, Z) \ ++ crypto_cipher_encrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) ++ #define crypto_blkcipher_decrypt_iv(W, X, Y, Z) \ ++ crypto_cipher_decrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) ++ #define crypto_blkcipher_set_flags(x, y) /* nop */ ++ #define crypto_free_blkcipher(x) crypto_free_tfm(x) ++ #define crypto_free_comp crypto_free_tfm ++ #define crypto_free_hash crypto_free_tfm ++ ++ /* Hash/HMAC/Digest */ ++ struct hash_desc ++ { ++ struct crypto_tfm *tfm; ++ }; ++ #define hmac(X) #X , 0 ++ #define crypto_has_hash(X, Y, Z) crypto_alg_available(X, 0) ++ #define crypto_hash_cast(X) X ++ #define crypto_hash_tfm(X) X ++ #define crypto_alloc_hash(X, Y, Z) crypto_alloc_tfm(X, mode) ++ #define crypto_hash_digestsize(X) crypto_tfm_alg_digestsize(X) ++ #define crypto_hash_digest(W, X, Y, Z) \ ++ crypto_digest_digest((W)->tfm, X, sg_num, Z) ++ ++ /* Asymmetric Cipher */ ++ #define crypto_has_cipher(X, Y, Z) crypto_alg_available(X, 0) ++ ++ /* Compression */ ++ #define crypto_has_comp(X, Y, Z) crypto_alg_available(X, 0) ++ #define crypto_comp_tfm(X) X ++ #define crypto_comp_cast(X) X ++ #define crypto_alloc_comp(X, Y, Z) crypto_alloc_tfm(X, mode) ++ #define plain(X) #X , 0 ++#else ++ #define ecb(X) "ecb(" #X ")" , 0 ++ #define cbc(X) "cbc(" #X ")" , 0 ++ #define hmac(X) "hmac(" #X ")" , 0 ++ #define plain(X) #X , 0 ++#endif /* if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) ++/* no ablkcipher in older kernels */ ++#define crypto_alloc_ablkcipher(a,b,c) (NULL) ++#define crypto_ablkcipher_tfm(x) ((struct crypto_tfm *)(x)) ++#define crypto_ablkcipher_set_flags(a, b) /* nop */ ++#define crypto_ablkcipher_setkey(x, y, z) (-EINVAL) ++#define crypto_has_ablkcipher(a,b,c) (0) ++#else ++#define HAVE_ABLKCIPHER ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) ++/* no ahash in older kernels */ ++#define crypto_ahash_tfm(x) ((struct crypto_tfm *)(x)) ++#define crypto_alloc_ahash(a,b,c) (NULL) ++#define crypto_ahash_digestsize(x) 0 ++#else ++#define HAVE_AHASH ++#endif ++ ++struct crypto_details { ++ char *alg_name; ++ int mode; ++ int sw_type; ++}; ++ ++static struct crypto_details crypto_details[] = { ++ [CRYPTO_DES_CBC] = { cbc(des), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_3DES_CBC] = { cbc(des3_ede), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_BLF_CBC] = { cbc(blowfish), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_CAST_CBC] = { cbc(cast5), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_SKIPJACK_CBC] = { cbc(skipjack), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_MD5_HMAC] = { hmac(md5), SW_TYPE_HMAC, }, ++ [CRYPTO_SHA1_HMAC] = { hmac(sha1), SW_TYPE_HMAC, }, ++ [CRYPTO_RIPEMD160_HMAC] = { hmac(ripemd160), SW_TYPE_HMAC, }, ++ [CRYPTO_MD5_KPDK] = { plain(md5-kpdk), SW_TYPE_HASH, }, ++ [CRYPTO_SHA1_KPDK] = { plain(sha1-kpdk), SW_TYPE_HASH, }, ++ [CRYPTO_AES_CBC] = { cbc(aes), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_ARC4] = { ecb(arc4), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_MD5] = { plain(md5), SW_TYPE_HASH, }, ++ [CRYPTO_SHA1] = { plain(sha1), SW_TYPE_HASH, }, ++ [CRYPTO_NULL_HMAC] = { hmac(digest_null), SW_TYPE_HMAC, }, ++ [CRYPTO_NULL_CBC] = { cbc(cipher_null), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_DEFLATE_COMP] = { plain(deflate), SW_TYPE_COMP, }, ++ [CRYPTO_SHA2_256_HMAC] = { hmac(sha256), SW_TYPE_HMAC, }, ++ [CRYPTO_SHA2_384_HMAC] = { hmac(sha384), SW_TYPE_HMAC, }, ++ [CRYPTO_SHA2_512_HMAC] = { hmac(sha512), SW_TYPE_HMAC, }, ++ [CRYPTO_CAMELLIA_CBC] = { cbc(camellia), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_SHA2_256] = { plain(sha256), SW_TYPE_HASH, }, ++ [CRYPTO_SHA2_384] = { plain(sha384), SW_TYPE_HASH, }, ++ [CRYPTO_SHA2_512] = { plain(sha512), SW_TYPE_HASH, }, ++ [CRYPTO_RIPEMD160] = { plain(ripemd160), SW_TYPE_HASH, }, ++}; ++ ++int32_t swcr_id = -1; ++module_param(swcr_id, int, 0444); ++MODULE_PARM_DESC(swcr_id, "Read-Only OCF ID for cryptosoft driver"); ++ ++int swcr_fail_if_compression_grows = 1; ++module_param(swcr_fail_if_compression_grows, int, 0644); ++MODULE_PARM_DESC(swcr_fail_if_compression_grows, ++ "Treat compression that results in more data as a failure"); ++ ++int swcr_no_ahash = 0; ++module_param(swcr_no_ahash, int, 0644); ++MODULE_PARM_DESC(swcr_no_ahash, ++ "Do not use async hash/hmac even if available"); ++ ++int swcr_no_ablk = 0; ++module_param(swcr_no_ablk, int, 0644); ++MODULE_PARM_DESC(swcr_no_ablk, ++ "Do not use async blk ciphers even if available"); ++ ++static struct swcr_data **swcr_sessions = NULL; ++static u_int32_t swcr_sesnum = 0; ++ ++static int swcr_process(device_t, struct cryptop *, int); ++static int swcr_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int swcr_freesession(device_t, u_int64_t); ++ ++static device_method_t swcr_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, swcr_newsession), ++ DEVMETHOD(cryptodev_freesession,swcr_freesession), ++ DEVMETHOD(cryptodev_process, swcr_process), ++}; ++ ++#define debug swcr_debug ++int swcr_debug = 0; ++module_param(swcr_debug, int, 0644); ++MODULE_PARM_DESC(swcr_debug, "Enable debug"); ++ ++static void swcr_process_req(struct swcr_req *req); ++ ++/* ++ * somethings just need to be run with user context no matter whether ++ * the kernel compression libs use vmalloc/vfree for example. ++ */ ++ ++typedef struct { ++ struct work_struct wq; ++ void (*func)(void *arg); ++ void *arg; ++} execute_later_t; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++doing_it_now(struct work_struct *wq) ++{ ++ execute_later_t *w = container_of(wq, execute_later_t, wq); ++ (w->func)(w->arg); ++ kfree(w); ++} ++#else ++static void ++doing_it_now(void *arg) ++{ ++ execute_later_t *w = (execute_later_t *) arg; ++ (w->func)(w->arg); ++ kfree(w); ++} ++#endif ++ ++static void ++execute_later(void (fn)(void *), void *arg) ++{ ++ execute_later_t *w; ++ ++ w = (execute_later_t *) kmalloc(sizeof(execute_later_t), SLAB_ATOMIC); ++ if (w) { ++ memset(w, '\0', sizeof(w)); ++ w->func = fn; ++ w->arg = arg; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&w->wq, doing_it_now); ++#else ++ INIT_WORK(&w->wq, doing_it_now, w); ++#endif ++ schedule_work(&w->wq); ++ } ++} ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++swcr_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct swcr_data **swd; ++ u_int32_t i; ++ int error; ++ char *algo; ++ int mode; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (swcr_sessions) { ++ for (i = 1; i < swcr_sesnum; i++) ++ if (swcr_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (swcr_sessions == NULL || i == swcr_sesnum) { ++ if (swcr_sessions == NULL) { ++ i = 1; /* We leave swcr_sessions[0] empty */ ++ swcr_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ swcr_sesnum *= 2; ++ ++ swd = kmalloc(swcr_sesnum * sizeof(struct swcr_data *), SLAB_ATOMIC); ++ if (swd == NULL) { ++ /* Reset session number */ ++ if (swcr_sesnum == CRYPTO_SW_SESSIONS) ++ swcr_sesnum = 0; ++ else ++ swcr_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(swd, 0, swcr_sesnum * sizeof(struct swcr_data *)); ++ ++ /* Copy existing sessions */ ++ if (swcr_sessions) { ++ memcpy(swd, swcr_sessions, ++ (swcr_sesnum / 2) * sizeof(struct swcr_data *)); ++ kfree(swcr_sessions); ++ } ++ ++ swcr_sessions = swd; ++ } ++ ++ swd = &swcr_sessions[i]; ++ *sid = i; ++ ++ while (cri) { ++ *swd = (struct swcr_data *) kmalloc(sizeof(struct swcr_data), ++ SLAB_ATOMIC); ++ if (*swd == NULL) { ++ swcr_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(*swd, 0, sizeof(struct swcr_data)); ++ ++ if (cri->cri_alg < 0 || ++ cri->cri_alg>=sizeof(crypto_details)/sizeof(crypto_details[0])){ ++ printk("cryptosoft: Unknown algorithm 0x%x\n", cri->cri_alg); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ algo = crypto_details[cri->cri_alg].alg_name; ++ if (!algo || !*algo) { ++ printk("cryptosoft: Unsupported algorithm 0x%x\n", cri->cri_alg); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ mode = crypto_details[cri->cri_alg].mode; ++ (*swd)->sw_type = crypto_details[cri->cri_alg].sw_type; ++ (*swd)->sw_alg = cri->cri_alg; ++ ++ spin_lock_init(&(*swd)->sw_tfm_lock); ++ ++ /* Algorithm specific configuration */ ++ switch (cri->cri_alg) { ++ case CRYPTO_NULL_CBC: ++ cri->cri_klen = 0; /* make it work with crypto API */ ++ break; ++ default: ++ break; ++ } ++ ++ if ((*swd)->sw_type & SW_TYPE_BLKCIPHER) { ++ dprintk("%s crypto_alloc_*blkcipher(%s, 0x%x)\n", __FUNCTION__, ++ algo, mode); ++ ++ /* try async first */ ++ (*swd)->sw_tfm = swcr_no_ablk ? NULL : ++ crypto_ablkcipher_tfm(crypto_alloc_ablkcipher(algo, 0, 0)); ++ if ((*swd)->sw_tfm && !IS_ERR((*swd)->sw_tfm)) { ++ dprintk("%s %s cipher is async\n", __FUNCTION__, algo); ++ (*swd)->sw_type |= SW_TYPE_ASYNC; ++ } else { ++ (*swd)->sw_tfm = crypto_blkcipher_tfm( ++ crypto_alloc_blkcipher(algo, 0, CRYPTO_ALG_ASYNC)); ++ if ((*swd)->sw_tfm && !IS_ERR((*swd)->sw_tfm)) ++ dprintk("%s %s cipher is sync\n", __FUNCTION__, algo); ++ } ++ if (!(*swd)->sw_tfm || IS_ERR((*swd)->sw_tfm)) { ++ int err; ++ dprintk("cryptosoft: crypto_alloc_blkcipher failed(%s, 0x%x)\n", ++ algo,mode); ++ err = IS_ERR((*swd)->sw_tfm) ? -(PTR_ERR((*swd)->sw_tfm)) : EINVAL; ++ (*swd)->sw_tfm = NULL; /* ensure NULL */ ++ swcr_freesession(NULL, i); ++ return err; ++ } ++ ++ if (debug) { ++ dprintk("%s key:cri->cri_klen=%d,(cri->cri_klen + 7)/8=%d", ++ __FUNCTION__, cri->cri_klen, (cri->cri_klen + 7) / 8); ++ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) ++ dprintk("%s0x%x", (i % 8) ? " " : "\n ", ++ cri->cri_key[i] & 0xff); ++ dprintk("\n"); ++ } ++ if ((*swd)->sw_type & SW_TYPE_ASYNC) { ++ /* OCF doesn't enforce keys */ ++ crypto_ablkcipher_set_flags( ++ __crypto_ablkcipher_cast((*swd)->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_ablkcipher_setkey( ++ __crypto_ablkcipher_cast((*swd)->sw_tfm), ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } else { ++ /* OCF doesn't enforce keys */ ++ crypto_blkcipher_set_flags( ++ crypto_blkcipher_cast((*swd)->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_blkcipher_setkey( ++ crypto_blkcipher_cast((*swd)->sw_tfm), ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ if (error) { ++ printk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", error, ++ (*swd)->sw_tfm->crt_flags); ++ swcr_freesession(NULL, i); ++ return error; ++ } ++ } else if ((*swd)->sw_type & (SW_TYPE_HMAC | SW_TYPE_HASH)) { ++ dprintk("%s crypto_alloc_*hash(%s, 0x%x)\n", __FUNCTION__, ++ algo, mode); ++ ++ /* try async first */ ++ (*swd)->sw_tfm = swcr_no_ahash ? NULL : ++ crypto_ahash_tfm(crypto_alloc_ahash(algo, 0, 0)); ++ if ((*swd)->sw_tfm) { ++ dprintk("%s %s hash is async\n", __FUNCTION__, algo); ++ (*swd)->sw_type |= SW_TYPE_ASYNC; ++ } else { ++ dprintk("%s %s hash is sync\n", __FUNCTION__, algo); ++ (*swd)->sw_tfm = crypto_hash_tfm( ++ crypto_alloc_hash(algo, 0, CRYPTO_ALG_ASYNC)); ++ } ++ ++ if (!(*swd)->sw_tfm) { ++ dprintk("cryptosoft: crypto_alloc_hash failed(%s,0x%x)\n", ++ algo, mode); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ (*swd)->u.hmac.sw_klen = (cri->cri_klen + 7) / 8; ++ (*swd)->u.hmac.sw_key = (char *)kmalloc((*swd)->u.hmac.sw_klen, ++ SLAB_ATOMIC); ++ if ((*swd)->u.hmac.sw_key == NULL) { ++ swcr_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memcpy((*swd)->u.hmac.sw_key, cri->cri_key, (*swd)->u.hmac.sw_klen); ++ if (cri->cri_mlen) { ++ (*swd)->u.hmac.sw_mlen = cri->cri_mlen; ++ } else if ((*swd)->sw_type & SW_TYPE_ASYNC) { ++ (*swd)->u.hmac.sw_mlen = crypto_ahash_digestsize( ++ __crypto_ahash_cast((*swd)->sw_tfm)); ++ } else { ++ (*swd)->u.hmac.sw_mlen = crypto_hash_digestsize( ++ crypto_hash_cast((*swd)->sw_tfm)); ++ } ++ } else if ((*swd)->sw_type & SW_TYPE_COMP) { ++ (*swd)->sw_tfm = crypto_comp_tfm( ++ crypto_alloc_comp(algo, 0, CRYPTO_ALG_ASYNC)); ++ if (!(*swd)->sw_tfm) { ++ dprintk("cryptosoft: crypto_alloc_comp failed(%s,0x%x)\n", ++ algo, mode); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ (*swd)->u.sw_comp_buf = kmalloc(CRYPTO_MAX_DATA_LEN, SLAB_ATOMIC); ++ if ((*swd)->u.sw_comp_buf == NULL) { ++ swcr_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ } else { ++ printk("cryptosoft: Unhandled sw_type %d\n", (*swd)->sw_type); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ cri = cri->cri_next; ++ swd = &((*swd)->sw_next); ++ } ++ return 0; ++} ++ ++/* ++ * Free a session. ++ */ ++static int ++swcr_freesession(device_t dev, u_int64_t tid) ++{ ++ struct swcr_data *swd; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > swcr_sesnum || swcr_sessions == NULL || ++ swcr_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ while ((swd = swcr_sessions[sid]) != NULL) { ++ swcr_sessions[sid] = swd->sw_next; ++ if (swd->sw_tfm) { ++ switch (swd->sw_type & SW_TYPE_ALG_AMASK) { ++#ifdef HAVE_AHASH ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++ crypto_free_ahash(__crypto_ahash_cast(swd->sw_tfm)); ++ break; ++#endif ++#ifdef HAVE_ABLKCIPHER ++ case SW_TYPE_ABLKCIPHER: ++ crypto_free_ablkcipher(__crypto_ablkcipher_cast(swd->sw_tfm)); ++ break; ++#endif ++ case SW_TYPE_BLKCIPHER: ++ crypto_free_blkcipher(crypto_blkcipher_cast(swd->sw_tfm)); ++ break; ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ crypto_free_hash(crypto_hash_cast(swd->sw_tfm)); ++ break; ++ case SW_TYPE_COMP: ++ if (in_interrupt()) ++ execute_later((void (*)(void *))crypto_free_comp, (void *)crypto_comp_cast(swd->sw_tfm)); ++ else ++ crypto_free_comp(crypto_comp_cast(swd->sw_tfm)); ++ break; ++ default: ++ crypto_free_tfm(swd->sw_tfm); ++ break; ++ } ++ swd->sw_tfm = NULL; ++ } ++ if (swd->sw_type & SW_TYPE_COMP) { ++ if (swd->u.sw_comp_buf) ++ kfree(swd->u.sw_comp_buf); ++ } else { ++ if (swd->u.hmac.sw_key) ++ kfree(swd->u.hmac.sw_key); ++ } ++ kfree(swd); ++ } ++ return 0; ++} ++ ++static void swcr_process_req_complete(struct swcr_req *req) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (req->sw->sw_type & SW_TYPE_INUSE) { ++ unsigned long flags; ++ spin_lock_irqsave(&req->sw->sw_tfm_lock, flags); ++ req->sw->sw_type &= ~SW_TYPE_INUSE; ++ spin_unlock_irqrestore(&req->sw->sw_tfm_lock, flags); ++ } ++ ++ if (req->crp->crp_etype) ++ goto done; ++ ++ switch (req->sw->sw_type & SW_TYPE_ALG_AMASK) { ++#if defined(HAVE_AHASH) ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++ crypto_copyback(req->crp->crp_flags, req->crp->crp_buf, ++ req->crd->crd_inject, req->sw->u.hmac.sw_mlen, req->result); ++ ahash_request_free(req->crypto_req); ++ break; ++#endif ++#if defined(HAVE_ABLKCIPHER) ++ case SW_TYPE_ABLKCIPHER: ++ ablkcipher_request_free(req->crypto_req); ++ break; ++#endif ++ case SW_TYPE_CIPHER: ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ case SW_TYPE_COMP: ++ case SW_TYPE_BLKCIPHER: ++ break; ++ default: ++ req->crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ req->crd = req->crd->crd_next; ++ if (req->crd) { ++ swcr_process_req(req); ++ return; ++ } ++ ++done: ++ dprintk("%s crypto_done %p\n", __FUNCTION__, req); ++ crypto_done(req->crp); ++ kmem_cache_free(swcr_req_cache, req); ++} ++ ++#if defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) ++static void swcr_process_callback(struct crypto_async_request *creq, int err) ++{ ++ struct swcr_req *req = creq->data; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (err) { ++ if (err == -EINPROGRESS) ++ return; ++ dprintk("%s() fail %d\n", __FUNCTION__, -err); ++ req->crp->crp_etype = -err; ++ } ++ ++ swcr_process_req_complete(req); ++} ++#endif /* defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) */ ++ ++ ++static void swcr_process_req(struct swcr_req *req) ++{ ++ struct swcr_data *sw; ++ struct cryptop *crp = req->crp; ++ struct cryptodesc *crd = req->crd; ++ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; ++ struct uio *uiop = (struct uio *) crp->crp_buf; ++ int sg_num, sg_len, skip; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* ++ * Find the crypto context. ++ * ++ * XXX Note that the logic here prevents us from having ++ * XXX the same algorithm multiple times in a session ++ * XXX (or rather, we can but it won't give us the right ++ * XXX results). To do that, we'd need some way of differentiating ++ * XXX between the various instances of an algorithm (so we can ++ * XXX locate the correct crypto context). ++ */ ++ for (sw = req->sw_head; sw && sw->sw_alg != crd->crd_alg; sw = sw->sw_next) ++ ; ++ ++ /* No such context ? */ ++ if (sw == NULL) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ /* ++ * for some types we need to ensure only one user as info is stored in ++ * the tfm during an operation that can get corrupted ++ */ ++ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { ++#ifdef HAVE_AHASH ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++#endif ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: { ++ unsigned long flags; ++ spin_lock_irqsave(&sw->sw_tfm_lock, flags); ++ if (sw->sw_type & SW_TYPE_INUSE) { ++ spin_unlock_irqrestore(&sw->sw_tfm_lock, flags); ++ execute_later((void (*)(void *))swcr_process_req, (void *)req); ++ return; ++ } ++ sw->sw_type |= SW_TYPE_INUSE; ++ spin_unlock_irqrestore(&sw->sw_tfm_lock, flags); ++ } break; ++ } ++ ++ req->sw = sw; ++ skip = crd->crd_skip; ++ ++ /* ++ * setup the SG list skip from the start of the buffer ++ */ ++ memset(req->sg, 0, sizeof(req->sg)); ++ sg_init_table(req->sg, SCATTERLIST_MAX); ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ int i, len; ++ ++ sg_num = 0; ++ sg_len = 0; ++ ++ if (skip < skb_headlen(skb)) { ++ len = skb_headlen(skb) - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ sg_set_page(&req->sg[sg_num], ++ virt_to_page(skb->data + skip), len, ++ offset_in_page(skb->data + skip)); ++ sg_len += len; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_headlen(skb); ++ ++ for (i = 0; sg_len < crd->crd_len && ++ i < skb_shinfo(skb)->nr_frags && ++ sg_num < SCATTERLIST_MAX; i++) { ++ if (skip < skb_shinfo(skb)->frags[i].size) { ++ len = skb_shinfo(skb)->frags[i].size - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ sg_set_page(&req->sg[sg_num], ++ skb_shinfo(skb)->frags[i].page, ++ len, ++ skb_shinfo(skb)->frags[i].page_offset + skip); ++ sg_len += len; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_shinfo(skb)->frags[i].size; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ int len; ++ ++ sg_len = 0; ++ for (sg_num = 0; sg_len < crd->crd_len && ++ sg_num < uiop->uio_iovcnt && ++ sg_num < SCATTERLIST_MAX; sg_num++) { ++ if (skip <= uiop->uio_iov[sg_num].iov_len) { ++ len = uiop->uio_iov[sg_num].iov_len - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ sg_set_page(&req->sg[sg_num], ++ virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), ++ len, ++ offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); ++ sg_len += len; ++ skip = 0; ++ } else ++ skip -= uiop->uio_iov[sg_num].iov_len; ++ } ++ } else { ++ sg_len = (crp->crp_ilen - skip); ++ if (sg_len > crd->crd_len) ++ sg_len = crd->crd_len; ++ sg_set_page(&req->sg[0], virt_to_page(crp->crp_buf + skip), ++ sg_len, offset_in_page(crp->crp_buf + skip)); ++ sg_num = 1; ++ } ++ ++ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { ++ ++#ifdef HAVE_AHASH ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++ { ++ int ret; ++ ++ /* check we have room for the result */ ++ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { ++ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " ++ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, ++ crd->crd_inject, sw->u.hmac.sw_mlen); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ req->crypto_req = ++ ahash_request_alloc(__crypto_ahash_cast(sw->sw_tfm),GFP_ATOMIC); ++ if (!req->crypto_req) { ++ crp->crp_etype = ENOMEM; ++ dprintk("%s,%d: ENOMEM ahash_request_alloc", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ ahash_request_set_callback(req->crypto_req, ++ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); ++ ++ memset(req->result, 0, sizeof(req->result)); ++ ++ if (sw->sw_type & SW_TYPE_AHMAC) ++ crypto_ahash_setkey(__crypto_ahash_cast(sw->sw_tfm), ++ sw->u.hmac.sw_key, sw->u.hmac.sw_klen); ++ ahash_request_set_crypt(req->crypto_req, req->sg, req->result, sg_len); ++ ret = crypto_ahash_digest(req->crypto_req); ++ switch (ret) { ++ case -EINPROGRESS: ++ case -EBUSY: ++ return; ++ default: ++ case 0: ++ dprintk("hash OP %s %d\n", ret ? "failed" : "success", ret); ++ crp->crp_etype = ret; ++ goto done; ++ } ++ } break; ++#endif /* HAVE_AHASH */ ++ ++#ifdef HAVE_ABLKCIPHER ++ case SW_TYPE_ABLKCIPHER: { ++ int ret; ++ unsigned char *ivp = req->iv; ++ int ivsize = ++ crypto_ablkcipher_ivsize(__crypto_ablkcipher_cast(sw->sw_tfm)); ++ ++ if (sg_len < crypto_ablkcipher_blocksize( ++ __crypto_ablkcipher_cast(sw->sw_tfm))) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, ++ sg_len, crypto_ablkcipher_blocksize( ++ __crypto_ablkcipher_cast(sw->sw_tfm))); ++ goto done; ++ } ++ ++ if (ivsize > sizeof(req->iv)) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ req->crypto_req = ablkcipher_request_alloc( ++ __crypto_ablkcipher_cast(sw->sw_tfm), GFP_ATOMIC); ++ if (!req->crypto_req) { ++ crp->crp_etype = ENOMEM; ++ dprintk("%s,%d: ENOMEM ablkcipher_request_alloc", ++ __FILE__, __LINE__); ++ goto done; ++ } ++ ++ ablkcipher_request_set_callback(req->crypto_req, ++ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); ++ ++ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ int i, error; ++ ++ if (debug) { ++ dprintk("%s key:", __FUNCTION__); ++ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) ++ dprintk("%s0x%x", (i % 8) ? " " : "\n ", ++ crd->crd_key[i] & 0xff); ++ dprintk("\n"); ++ } ++ /* OCF doesn't enforce keys */ ++ crypto_ablkcipher_set_flags(__crypto_ablkcipher_cast(sw->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_ablkcipher_setkey( ++ __crypto_ablkcipher_cast(sw->sw_tfm), crd->crd_key, ++ (crd->crd_klen + 7) / 8); ++ if (error) { ++ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", ++ error, sw->sw_tfm->crt_flags); ++ crp->crp_etype = -error; ++ } ++ } ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) ++ ivp = crd->crd_iv; ++ else ++ get_random_bytes(ivp, ivsize); ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ } ++ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, ++ sg_len, ivp); ++ ret = crypto_ablkcipher_encrypt(req->crypto_req); ++ ++ } else { /*decrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) ++ ivp = crd->crd_iv; ++ else ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, ++ sg_len, ivp); ++ ret = crypto_ablkcipher_decrypt(req->crypto_req); ++ } ++ ++ switch (ret) { ++ case -EINPROGRESS: ++ case -EBUSY: ++ return; ++ default: ++ case 0: ++ dprintk("crypto OP %s %d\n", ret ? "failed" : "success", ret); ++ crp->crp_etype = ret; ++ goto done; ++ } ++ } break; ++#endif /* HAVE_ABLKCIPHER */ ++ ++ case SW_TYPE_BLKCIPHER: { ++ unsigned char iv[EALG_MAX_BLOCK_LEN]; ++ unsigned char *ivp = iv; ++ struct blkcipher_desc desc; ++ int ivsize = crypto_blkcipher_ivsize(crypto_blkcipher_cast(sw->sw_tfm)); ++ ++ if (sg_len < crypto_blkcipher_blocksize( ++ crypto_blkcipher_cast(sw->sw_tfm))) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, ++ sg_len, crypto_blkcipher_blocksize( ++ crypto_blkcipher_cast(sw->sw_tfm))); ++ goto done; ++ } ++ ++ if (ivsize > sizeof(iv)) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ int i, error; ++ ++ if (debug) { ++ dprintk("%s key:", __FUNCTION__); ++ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) ++ dprintk("%s0x%x", (i % 8) ? " " : "\n ", ++ crd->crd_key[i] & 0xff); ++ dprintk("\n"); ++ } ++ /* OCF doesn't enforce keys */ ++ crypto_blkcipher_set_flags(crypto_blkcipher_cast(sw->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_blkcipher_setkey( ++ crypto_blkcipher_cast(sw->sw_tfm), crd->crd_key, ++ (crd->crd_klen + 7) / 8); ++ if (error) { ++ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", ++ error, sw->sw_tfm->crt_flags); ++ crp->crp_etype = -error; ++ } ++ } ++ ++ memset(&desc, 0, sizeof(desc)); ++ desc.tfm = crypto_blkcipher_cast(sw->sw_tfm); ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ get_random_bytes(ivp, ivsize); ++ } ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ } ++ desc.info = ivp; ++ crypto_blkcipher_encrypt_iv(&desc, req->sg, req->sg, sg_len); ++ ++ } else { /*decrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ } ++ desc.info = ivp; ++ crypto_blkcipher_decrypt_iv(&desc, req->sg, req->sg, sg_len); ++ } ++ } break; ++ ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ { ++ char result[HASH_MAX_LEN]; ++ struct hash_desc desc; ++ ++ /* check we have room for the result */ ++ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { ++ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " ++ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, ++ crd->crd_inject, sw->u.hmac.sw_mlen); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ memset(&desc, 0, sizeof(desc)); ++ desc.tfm = crypto_hash_cast(sw->sw_tfm); ++ ++ memset(result, 0, sizeof(result)); ++ ++ if (sw->sw_type & SW_TYPE_HMAC) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ++ crypto_hmac(sw->sw_tfm, sw->u.hmac.sw_key, &sw->u.hmac.sw_klen, ++ req->sg, sg_num, result); ++#else ++ crypto_hash_setkey(desc.tfm, sw->u.hmac.sw_key, ++ sw->u.hmac.sw_klen); ++ crypto_hash_digest(&desc, req->sg, sg_len, result); ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ ++ ++ } else { /* SW_TYPE_HASH */ ++ crypto_hash_digest(&desc, req->sg, sg_len, result); ++ } ++ ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, sw->u.hmac.sw_mlen, result); ++ } ++ break; ++ ++ case SW_TYPE_COMP: { ++ void *ibuf = NULL; ++ void *obuf = sw->u.sw_comp_buf; ++ int ilen = sg_len, olen = CRYPTO_MAX_DATA_LEN; ++ int ret = 0; ++ ++ /* ++ * we need to use an additional copy if there is more than one ++ * input chunk since the kernel comp routines do not handle ++ * SG yet. Otherwise we just use the input buffer as is. ++ * Rather than allocate another buffer we just split the tmp ++ * buffer we already have. ++ * Perhaps we should just use zlib directly ? ++ */ ++ if (sg_num > 1) { ++ int blk; ++ ++ ibuf = obuf; ++ for (blk = 0; blk < sg_num; blk++) { ++ memcpy(obuf, sg_virt(&req->sg[blk]), ++ req->sg[blk].length); ++ obuf += req->sg[blk].length; ++ } ++ olen -= sg_len; ++ } else ++ ibuf = sg_virt(&req->sg[0]); ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* compress */ ++ ret = crypto_comp_compress(crypto_comp_cast(sw->sw_tfm), ++ ibuf, ilen, obuf, &olen); ++ if (!ret && olen > crd->crd_len) { ++ dprintk("cryptosoft: ERANGE compress %d into %d\n", ++ crd->crd_len, olen); ++ if (swcr_fail_if_compression_grows) ++ ret = ERANGE; ++ } ++ } else { /* decompress */ ++ ret = crypto_comp_decompress(crypto_comp_cast(sw->sw_tfm), ++ ibuf, ilen, obuf, &olen); ++ if (!ret && (olen + crd->crd_inject) > crp->crp_olen) { ++ dprintk("cryptosoft: ETOOSMALL decompress %d into %d, " ++ "space for %d,at offset %d\n", ++ crd->crd_len, olen, crp->crp_olen, crd->crd_inject); ++ ret = ETOOSMALL; ++ } ++ } ++ if (ret) ++ dprintk("%s,%d: ret = %d\n", __FILE__, __LINE__, ret); ++ ++ /* ++ * on success copy result back, ++ * linux crpyto API returns -errno, we need to fix that ++ */ ++ crp->crp_etype = ret < 0 ? -ret : ret; ++ if (ret == 0) { ++ /* copy back the result and return it's size */ ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, olen, obuf); ++ crp->crp_olen = olen; ++ } ++ } break; ++ ++ default: ++ /* Unknown/unsupported algorithm */ ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++done: ++ swcr_process_req_complete(req); ++} ++ ++ ++/* ++ * Process a crypto request. ++ */ ++static int ++swcr_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct swcr_req *req = NULL; ++ u_int32_t lid; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= swcr_sesnum || lid == 0 || swcr_sessions == NULL || ++ swcr_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ /* ++ * do some error checking outside of the loop for SKB and IOV processing ++ * this leaves us with valid skb or uiop pointers for later ++ */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { ++ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, ++ skb_shinfo(skb)->nr_frags); ++ goto done; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ struct uio *uiop = (struct uio *) crp->crp_buf; ++ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { ++ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, ++ uiop->uio_iovcnt); ++ goto done; ++ } ++ } ++ ++ /* ++ * setup a new request ready for queuing ++ */ ++ req = kmem_cache_alloc(swcr_req_cache, SLAB_ATOMIC); ++ if (req == NULL) { ++ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); ++ crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ memset(req, 0, sizeof(*req)); ++ ++ req->sw_head = swcr_sessions[lid]; ++ req->crp = crp; ++ req->crd = crp->crp_desc; ++ ++ swcr_process_req(req); ++ return 0; ++ ++done: ++ crypto_done(crp); ++ if (req) ++ kmem_cache_free(swcr_req_cache, req); ++ return 0; ++} ++ ++ ++static int ++cryptosoft_init(void) ++{ ++ int i, sw_type, mode; ++ char *algo; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, cryptosoft_init); ++ ++ swcr_req_cache = kmem_cache_create("cryptosoft_req", ++ sizeof(struct swcr_req), 0, SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ if (!swcr_req_cache) { ++ printk("cryptosoft: failed to create request cache\n"); ++ return -ENOENT; ++ } ++ ++ softc_device_init(&swcr_softc, "cryptosoft", 0, swcr_methods); ++ ++ swcr_id = crypto_get_driverid(softc_get_device(&swcr_softc), ++ CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_SYNC); ++ if (swcr_id < 0) { ++ printk("cryptosoft: Software crypto device cannot initialize!"); ++ return -ENODEV; ++ } ++ ++#define REGISTER(alg) \ ++ crypto_register(swcr_id, alg, 0,0) ++ ++ for (i = 0; i < sizeof(crypto_details)/sizeof(crypto_details[0]); i++) { ++ int found; ++ ++ algo = crypto_details[i].alg_name; ++ if (!algo || !*algo) { ++ dprintk("%s:Algorithm %d not supported\n", __FUNCTION__, i); ++ continue; ++ } ++ ++ mode = crypto_details[i].mode; ++ sw_type = crypto_details[i].sw_type; ++ ++ found = 0; ++ switch (sw_type & SW_TYPE_ALG_MASK) { ++ case SW_TYPE_CIPHER: ++ found = crypto_has_cipher(algo, 0, CRYPTO_ALG_ASYNC); ++ break; ++ case SW_TYPE_HMAC: ++ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); ++ break; ++ case SW_TYPE_HASH: ++ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); ++ break; ++ case SW_TYPE_COMP: ++ found = crypto_has_comp(algo, 0, CRYPTO_ALG_ASYNC); ++ break; ++ case SW_TYPE_BLKCIPHER: ++ found = crypto_has_blkcipher(algo, 0, CRYPTO_ALG_ASYNC); ++ if (!found && !swcr_no_ablk) ++ found = crypto_has_ablkcipher(algo, 0, 0); ++ break; ++ } ++ if (found) { ++ REGISTER(i); ++ } else { ++ dprintk("%s:Algorithm Type %d not supported (algorithm %d:'%s')\n", ++ __FUNCTION__, sw_type, i, algo); ++ } ++ } ++ return 0; ++} ++ ++static void ++cryptosoft_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(swcr_id); ++ swcr_id = -1; ++ kmem_cache_destroy(swcr_req_cache); ++} ++ ++late_initcall(cryptosoft_init); ++module_exit(cryptosoft_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Cryptosoft (OCF module for kernel crypto)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/Makefile linux-3.0.4/crypto/ocf/ep80579/Makefile +--- linux-3.0.4.orig/crypto/ocf/ep80579/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,119 @@ ++######################################################################### ++# ++# Targets supported ++# all - builds everything and installs ++# install - identical to all ++# depend - build dependencies ++# clean - clears derived objects except the .depend files ++# distclean- clears all derived objects and the .depend file ++# ++# @par ++# This file is provided under a dual BSD/GPLv2 license. When using or ++# redistributing this file, you may do so under either license. ++# ++# GPL LICENSE SUMMARY ++# ++# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of version 2 of the GNU General Public License as ++# published by the Free Software Foundation. ++# ++# This program is distributed in the hope that it will be useful, but ++# WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++# General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++# The full GNU General Public License is included in this distribution ++# in the file called LICENSE.GPL. ++# ++# Contact Information: ++# Intel Corporation ++# ++# BSD LICENSE ++# ++# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++# All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of Intel Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++# ++# ++# version: Security.L.1.0.2-229 ++############################################################################ ++ ++ ++####################Common variables and definitions######################## ++ ++ifndef ICP_ROOT ++$(warning ICP_ROOT is undefined. Please set the path to EP80579 release package directory \ ++ "-> setenv ICP_ROOT ") ++all fastdep: ++ : ++else ++ ++ifndef KERNEL_SOURCE_ROOT ++$(error KERNEL_SOURCE_ROOT is undefined. Please set the path to the kernel source directory \ ++ "-> setenv KERNEL_SOURCE_ROOT ") ++endif ++ ++# Ensure The ENV_DIR environmental var is defined. ++ifndef ICP_ENV_DIR ++$(error ICP_ENV_DIR is undefined. Please set the path to EP80579 driver environment.mk file \ ++ "-> setenv ICP_ENV_DIR ") ++endif ++ ++#Add your project environment Makefile ++include ${ICP_ENV_DIR}/environment.mk ++ ++#include the makefile with all the default and common Make variable definitions ++include ${ICP_BUILDSYSTEM_PATH}/build_files/common.mk ++ ++#Add the name for the executable, Library or Module output definitions ++OUTPUT_NAME= icp_ocf ++ ++# List of Source Files to be compiled ++SOURCES= icp_common.c icp_sym.c icp_asym.c icp_ocf_linux.c ++ ++#common includes between all supported OSes ++INCLUDES= -I ${ICP_API_DIR} -I${ICP_LAC_API} \ ++-I${ICP_OCF_SRC_DIR} ++ ++# The location of the os level makefile needs to be changed. ++include ${ICP_ENV_DIR}/${ICP_OS}_${ICP_OS_LEVEL}.mk ++ ++# On the line directly below list the outputs you wish to build for, ++# e.g "lib_static lib_shared exe module" as shown below ++install: module ++ ++###################Include rules makefiles######################## ++include ${ICP_BUILDSYSTEM_PATH}/build_files/rules.mk ++###################End of Rules inclusion######################### ++ ++endif +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/environment.mk linux-3.0.4/crypto/ocf/ep80579/environment.mk +--- linux-3.0.4.orig/crypto/ocf/ep80579/environment.mk 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/environment.mk 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,78 @@ ++ ########################################################################### ++ # ++# This file is provided under a dual BSD/GPLv2 license. When using or ++# redistributing this file, you may do so under either license. ++# ++# GPL LICENSE SUMMARY ++# ++# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of version 2 of the GNU General Public License as ++# published by the Free Software Foundation. ++# ++# This program is distributed in the hope that it will be useful, but ++# WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++# General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++# The full GNU General Public License is included in this distribution ++# in the file called LICENSE.GPL. ++# ++# Contact Information: ++# Intel Corporation ++# ++# BSD LICENSE ++# ++# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. ++# All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of Intel Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++# ++# ++# version: Security.L.1.0.130 ++ # ++ ########################################################################### ++ ++ ++ICP_LAC_API=$(ICP_ROOT)/Acceleration/include/lac ++ICP_BTR_API=$(ICP_ROOT)/Acceleration/include/btr ++ICP_API_DIR=$(ICP_ROOT)/Acceleration/include ++ICP_OCF_SHIM_DIR?=$(KERNEL_SOURCE_ROOT)/crypto/ocf/ ++ifeq ($(wildcard $(ICP_OCF_SHIM_DIR)),) ++ICP_OCF_SHIM_DIR?=$(ROOTDIR)/modules/ocf/ ++endif ++ ++ICP_OS_LEVEL?=kernel_space ++ ++ICP_OS?=linux_2.6 ++ ++ICP_CORE?=ia ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_asym.c linux-3.0.4/crypto/ocf/ep80579/icp_asym.c +--- linux-3.0.4.orig/crypto/ocf/ep80579/icp_asym.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/icp_asym.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1334 @@ ++/*************************************************************************** ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++ ++#include "icp_ocf.h" ++ ++/*The following define values (containing the word 'INDEX') are used to find ++the index of each input buffer of the crypto_kop struct (see OCF cryptodev.h). ++These values were found through analysis of the OCF OpenSSL patch. If the ++calling program uses different input buffer positions, these defines will have ++to be changed.*/ ++ ++/*DIFFIE HELLMAN buffer index values*/ ++#define ICP_DH_KRP_PARAM_PRIME_INDEX (0) ++#define ICP_DH_KRP_PARAM_BASE_INDEX (1) ++#define ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX (2) ++#define ICP_DH_KRP_PARAM_RESULT_INDEX (3) ++ ++/*MOD EXP buffer index values*/ ++#define ICP_MOD_EXP_KRP_PARAM_BASE_INDEX (0) ++#define ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX (1) ++#define ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX (2) ++#define ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX (3) ++ ++/*MOD EXP CRT buffer index values*/ ++#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX (0) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX (1) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX (2) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX (3) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX (4) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX (5) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX (6) ++ ++/*DSA sign buffer index values*/ ++#define ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX (0) ++#define ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX (1) ++#define ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX (2) ++#define ICP_DSA_SIGN_KRP_PARAM_G_INDEX (3) ++#define ICP_DSA_SIGN_KRP_PARAM_X_INDEX (4) ++#define ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX (5) ++#define ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX (6) ++ ++/*DSA verify buffer index values*/ ++#define ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX (0) ++#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX (1) ++#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX (2) ++#define ICP_DSA_VERIFY_KRP_PARAM_G_INDEX (3) ++#define ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX (4) ++#define ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX (5) ++#define ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX (6) ++ ++/*DSA sign prime Q vs random number K size check values*/ ++#define DONT_RUN_LESS_THAN_CHECK (0) ++#define FAIL_A_IS_GREATER_THAN_B (1) ++#define FAIL_A_IS_EQUAL_TO_B (1) ++#define SUCCESS_A_IS_LESS_THAN_B (0) ++#define DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS (500) ++ ++/* We need to set a cryptokp success value just in case it is set or allocated ++ and not set to zero outside of this module */ ++#define CRYPTO_OP_SUCCESS (0) ++ ++/*Function to compute Diffie Hellman (DH) phase 1 or phase 2 key values*/ ++static int icp_ocfDrvDHComputeKey(struct cryptkop *krp); ++ ++/*Function to compute a Modular Exponentiation (Mod Exp)*/ ++static int icp_ocfDrvModExp(struct cryptkop *krp); ++ ++/*Function to compute a Mod Exp using the Chinease Remainder Theorem*/ ++static int icp_ocfDrvModExpCRT(struct cryptkop *krp); ++ ++/*Helper function to compute whether the first big number argument is less than ++ the second big number argument */ ++static int ++icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck); ++ ++/*Function to sign an input with DSA R and S keys*/ ++static int icp_ocfDrvDsaSign(struct cryptkop *krp); ++ ++/*Function to Verify a DSA buffer signature*/ ++static int icp_ocfDrvDsaVerify(struct cryptkop *krp); ++ ++/*Callback function for DH operation*/ ++static void ++icp_ocfDrvDhP1CallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV); ++ ++/*Callback function for ME operation*/ ++static void ++icp_ocfDrvModExpCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pResult); ++ ++/*Callback function for ME CRT operation*/ ++static void ++icp_ocfDrvModExpCRTCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pOutputData); ++ ++/*Callback function for DSA sign operation*/ ++static void ++icp_ocfDrvDsaRSSignCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, ++ CpaBoolean protocolStatus, ++ CpaFlatBuffer * pR, CpaFlatBuffer * pS); ++ ++/*Callback function for DSA Verify operation*/ ++static void ++icp_ocfDrvDsaVerifyCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaBoolean verifyStatus); ++ ++/* Name : icp_ocfDrvPkeProcess ++ * ++ * Description : This function will choose which PKE process to follow ++ * based on the input arguments ++ */ ++int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ ++ if (NULL == krp) { ++ DPRINTK("%s(): Invalid input parameters, cryptkop = %p\n", ++ __FUNCTION__, krp); ++ return EINVAL; ++ } ++ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ switch (krp->krp_op) { ++ case CRK_DH_COMPUTE_KEY: ++ DPRINTK("%s() doing DH_COMPUTE_KEY\n", __FUNCTION__); ++ lacStatus = icp_ocfDrvDHComputeKey(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvDHComputeKey failed " ++ "(%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_MOD_EXP: ++ DPRINTK("%s() doing MOD_EXP \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvModExp(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvModExp failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_MOD_EXP_CRT: ++ DPRINTK("%s() doing MOD_EXP_CRT \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvModExpCRT(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvModExpCRT " ++ "failed (%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_DSA_SIGN: ++ DPRINTK("%s() doing DSA_SIGN \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvDsaSign(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvDsaSign " ++ "failed (%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_DSA_VERIFY: ++ DPRINTK("%s() doing DSA_VERIFY \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvDsaVerify(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvDsaVerify " ++ "failed (%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ default: ++ EPRINTK("%s(): Asymettric function not " ++ "supported (%d).\n", __FUNCTION__, krp->krp_op); ++ krp->krp_status = EOPNOTSUPP; ++ return EOPNOTSUPP; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvSwapBytes ++ * ++ * Description : This function is used to swap the byte order of a buffer. ++ * It has been seen that in general we are passed little endian byte order ++ * buffers, but LAC only accepts big endian byte order buffers. ++ */ ++static void inline icp_ocfDrvSwapBytes(u_int8_t * num, u_int32_t buff_len_bytes) ++{ ++ ++ int i; ++ u_int8_t *end_ptr; ++ u_int8_t hold_val; ++ ++ end_ptr = num + (buff_len_bytes - 1); ++ buff_len_bytes = buff_len_bytes >> 1; ++ for (i = 0; i < buff_len_bytes; i++) { ++ hold_val = *num; ++ *num = *end_ptr; ++ num++; ++ *end_ptr = hold_val; ++ end_ptr--; ++ } ++} ++ ++/* Name : icp_ocfDrvDHComputeKey ++ * ++ * Description : This function will map Diffie Hellman calls from OCF ++ * to the LAC API. OCF uses this function for Diffie Hellman Phase1 and ++ * Phase2. LAC has a separate Diffie Hellman Phase2 call, however both phases ++ * break down to a modular exponentiation. ++ */ ++static int icp_ocfDrvDHComputeKey(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ void *callbackTag = NULL; ++ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; ++ CpaFlatBuffer *pLocalOctetStringPV = NULL; ++ uint32_t dh_prime_len_bytes = 0, dh_prime_len_bits = 0; ++ ++ /* Input checks - check prime is a multiple of 8 bits to allow for ++ allocation later */ ++ dh_prime_len_bits = ++ (krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_nbits); ++ ++ /* LAC can reject prime lengths based on prime key sizes, we just ++ need to make sure we can allocate space for the base and ++ exponent buffers correctly */ ++ if ((dh_prime_len_bits % NUM_BITS_IN_BYTE) != 0) { ++ APRINTK("%s(): Warning Prime number buffer size is not a " ++ "multiple of 8 bits\n", __FUNCTION__); ++ } ++ ++ /* Result storage space should be the same size as the prime as this ++ value can take up the same amount of storage space */ ++ if (dh_prime_len_bits != ++ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits) { ++ DPRINTK("%s(): Return Buffer must be the same size " ++ "as the Prime buffer\n", __FUNCTION__); ++ krp->krp_status = EINVAL; ++ return EINVAL; ++ } ++ /* Switch to size in bytes */ ++ BITS_TO_BYTES(dh_prime_len_bytes, dh_prime_len_bits); ++ ++ callbackTag = krp; ++ ++/*All allocations are set to ICP_M_NOWAIT due to the possibility of getting ++called in interrupt context*/ ++ pPhase1OpData = icp_kmem_cache_zalloc(drvDH_zone, ICP_M_NOWAIT); ++ if (NULL == pPhase1OpData) { ++ APRINTK("%s():Failed to get memory for key gen data\n", ++ __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pLocalOctetStringPV = ++ icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pLocalOctetStringPV) { ++ APRINTK("%s():Failed to get memory for pLocalOctetStringPV\n", ++ __FUNCTION__); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /* Link parameters */ ++ pPhase1OpData->primeP.pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_p; ++ ++ pPhase1OpData->primeP.dataLenInBytes = dh_prime_len_bytes; ++ ++ icp_ocfDrvSwapBytes(pPhase1OpData->primeP.pData, dh_prime_len_bytes); ++ ++ pPhase1OpData->baseG.pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_p; ++ ++ BITS_TO_BYTES(pPhase1OpData->baseG.dataLenInBytes, ++ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pPhase1OpData->baseG.pData, ++ pPhase1OpData->baseG.dataLenInBytes); ++ ++ pPhase1OpData->privateValueX.pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX].crp_p; ++ ++ BITS_TO_BYTES(pPhase1OpData->privateValueX.dataLenInBytes, ++ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pPhase1OpData->privateValueX.pData, ++ pPhase1OpData->privateValueX.dataLenInBytes); ++ ++ /* Output parameters */ ++ pLocalOctetStringPV->pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_p; ++ ++ BITS_TO_BYTES(pLocalOctetStringPV->dataLenInBytes, ++ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits); ++ ++ lacStatus = cpaCyDhKeyGenPhase1(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvDhP1CallBack, ++ callbackTag, pPhase1OpData, ++ pLocalOctetStringPV); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): DH Phase 1 Key Gen failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvModExp ++ * ++ * Description : This function will map ordinary Modular Exponentiation calls ++ * from OCF to the LAC API. ++ * ++ */ ++static int icp_ocfDrvModExp(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ void *callbackTag = NULL; ++ CpaCyLnModExpOpData *pModExpOpData = NULL; ++ CpaFlatBuffer *pResult = NULL; ++ ++ if ((krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits % ++ NUM_BITS_IN_BYTE) != 0) { ++ DPRINTK("%s(): Warning - modulus buffer size (%d) is not a " ++ "multiple of 8 bits\n", __FUNCTION__, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. ++ crp_nbits); ++ } ++ ++ /* Result storage space should be the same size as the prime as this ++ value can take up the same amount of storage space */ ++ if (krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits > ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_nbits) { ++ APRINTK("%s(): Return Buffer size must be the same or" ++ " greater than the Modulus buffer\n", __FUNCTION__); ++ krp->krp_status = EINVAL; ++ return EINVAL; ++ } ++ ++ callbackTag = krp; ++ ++ pModExpOpData = icp_kmem_cache_zalloc(drvLnModExp_zone, ICP_M_NOWAIT); ++ if (NULL == pModExpOpData) { ++ APRINTK("%s():Failed to get memory for key gen data\n", ++ __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pResult = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pResult) { ++ APRINTK("%s():Failed to get memory for ModExp result\n", ++ __FUNCTION__); ++ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /* Link parameters */ ++ pModExpOpData->modulus.pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_p; ++ BITS_TO_BYTES(pModExpOpData->modulus.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pModExpOpData->modulus.pData, ++ pModExpOpData->modulus.dataLenInBytes); ++ ++ DPRINTK("%s : base (%d)\n", __FUNCTION__, krp-> ++ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits); ++ pModExpOpData->base.pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_p; ++ BITS_TO_BYTES(pModExpOpData->base.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(pModExpOpData->base.pData, ++ pModExpOpData->base.dataLenInBytes); ++ ++ pModExpOpData->exponent.pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX].crp_p; ++ BITS_TO_BYTES(pModExpOpData->exponent.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pModExpOpData->exponent.pData, ++ pModExpOpData->exponent.dataLenInBytes); ++ /* Output parameters */ ++ pResult->pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_p, ++ BITS_TO_BYTES(pResult->dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX]. ++ crp_nbits); ++ ++ lacStatus = cpaCyLnModExp(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvModExpCallBack, ++ callbackTag, pModExpOpData, pResult); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): Mod Exp Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ icp_ocfDrvFreeFlatBuffer(pResult); ++ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvModExpCRT ++ * ++ * Description : This function will map ordinary Modular Exponentiation Chinese ++ * Remainder Theorem implementaion calls from OCF to the LAC API. ++ * ++ * Note : Mod Exp CRT for this driver is accelerated through LAC RSA type 2 ++ * decrypt operation. Therefore P and Q input values must always be prime ++ * numbers. Although basic primality checks are done in LAC, it is up to the ++ * user to do any correct prime number checking before passing the inputs. ++ */ ++static int icp_ocfDrvModExpCRT(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ CpaCyRsaDecryptOpData *rsaDecryptOpData = NULL; ++ void *callbackTag = NULL; ++ CpaFlatBuffer *pOutputData = NULL; ++ ++ /*Parameter input checks are all done by LAC, no need to repeat ++ them here. */ ++ callbackTag = krp; ++ ++ rsaDecryptOpData = ++ icp_kmem_cache_zalloc(drvRSADecrypt_zone, ICP_M_NOWAIT); ++ if (NULL == rsaDecryptOpData) { ++ APRINTK("%s():Failed to get memory" ++ " for MOD EXP CRT Op data struct\n", __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ rsaDecryptOpData->pRecipientPrivateKey ++ = icp_kmem_cache_zalloc(drvRSAPrivateKey_zone, ICP_M_NOWAIT); ++ if (NULL == rsaDecryptOpData->pRecipientPrivateKey) { ++ APRINTK("%s():Failed to get memory for MOD EXP CRT" ++ " private key values struct\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ version = CPA_CY_RSA_VERSION_TWO_PRIME; ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; ++ ++ pOutputData = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pOutputData) { ++ APRINTK("%s():Failed to get memory" ++ " for MOD EXP CRT output data\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ rsaDecryptOpData->pRecipientPrivateKey); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ version = CPA_CY_RSA_VERSION_TWO_PRIME; ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; ++ ++ /* Link parameters */ ++ rsaDecryptOpData->inputData.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->inputData.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->inputData.pData, ++ rsaDecryptOpData->inputData.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime1P.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. ++ prime1P.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime1P.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime1P.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime2Q.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. ++ prime2Q.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime2Q.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime2Q.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent1Dp.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. ++ exponent1Dp.dataLenInBytes, ++ krp-> ++ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent1Dp.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent1Dp.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.dataLenInBytes, ++ krp-> ++ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.dataLenInBytes, ++ krp-> ++ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.dataLenInBytes); ++ ++ /* Output Parameter */ ++ pOutputData->pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX].crp_p; ++ BITS_TO_BYTES(pOutputData->dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX]. ++ crp_nbits); ++ ++ lacStatus = cpaCyRsaDecrypt(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvModExpCRTCallBack, ++ callbackTag, rsaDecryptOpData, pOutputData); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): Mod Exp CRT Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ icp_ocfDrvFreeFlatBuffer(pOutputData); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ rsaDecryptOpData->pRecipientPrivateKey); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvCheckALessThanB ++ * ++ * Description : This function will check whether the first argument is less ++ * than the second. It is used to check whether the DSA RS sign Random K ++ * value is less than the Prime Q value (as defined in the specification) ++ * ++ */ ++static int ++icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck) ++{ ++ ++ uint8_t *MSB_K = pK->pData; ++ uint8_t *MSB_Q = pQ->pData; ++ uint32_t buffer_lengths_in_bytes = pQ->dataLenInBytes; ++ ++ if (DONT_RUN_LESS_THAN_CHECK == *doCheck) { ++ return FAIL_A_IS_GREATER_THAN_B; ++ } ++ ++/*Check MSBs ++if A == B, check next MSB ++if A > B, return A_IS_GREATER_THAN_B ++if A < B, return A_IS_LESS_THAN_B (success) ++*/ ++ while (*MSB_K == *MSB_Q) { ++ MSB_K++; ++ MSB_Q++; ++ ++ buffer_lengths_in_bytes--; ++ if (0 == buffer_lengths_in_bytes) { ++ DPRINTK("%s() Buffers have equal value!!\n", ++ __FUNCTION__); ++ return FAIL_A_IS_EQUAL_TO_B; ++ } ++ ++ } ++ ++ if (*MSB_K < *MSB_Q) { ++ return SUCCESS_A_IS_LESS_THAN_B; ++ } else { ++ return FAIL_A_IS_GREATER_THAN_B; ++ } ++ ++} ++ ++/* Name : icp_ocfDrvDsaSign ++ * ++ * Description : This function will map DSA RS Sign from OCF to the LAC API. ++ * ++ * NOTE: From looking at OCF patch to OpenSSL and even the number of input ++ * parameters, OCF expects us to generate the random seed value. This value ++ * is generated and passed to LAC, however the number is discared in the ++ * callback and not returned to the user. ++ */ ++static int icp_ocfDrvDsaSign(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ CpaCyDsaRSSignOpData *dsaRsSignOpData = NULL; ++ void *callbackTag = NULL; ++ CpaCyRandGenOpData randGenOpData; ++ int primeQSizeInBytes = 0; ++ int doCheck = 0; ++ CpaFlatBuffer randData; ++ CpaBoolean protocolStatus = CPA_FALSE; ++ CpaFlatBuffer *pR = NULL; ++ CpaFlatBuffer *pS = NULL; ++ ++ callbackTag = krp; ++ ++ BITS_TO_BYTES(primeQSizeInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ ++ if (DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES != primeQSizeInBytes) { ++ APRINTK("%s(): DSA PRIME Q size not equal to the " ++ "FIPS defined 20bytes, = %d\n", ++ __FUNCTION__, primeQSizeInBytes); ++ krp->krp_status = EDOM; ++ return EDOM; ++ } ++ ++ dsaRsSignOpData = ++ icp_kmem_cache_zalloc(drvDSARSSign_zone, ICP_M_NOWAIT); ++ if (NULL == dsaRsSignOpData) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA RS Sign Op data struct\n", __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ dsaRsSignOpData->K.pData = ++ icp_kmem_cache_alloc(drvDSARSSignKValue_zone, ICP_M_NOWAIT); ++ ++ if (NULL == dsaRsSignOpData->K.pData) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA RS Sign Op Random value\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pR = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pR) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA signature R\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pS = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pS) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA signature S\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /*link prime number parameter for ease of processing */ ++ dsaRsSignOpData->P.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->P.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->P.pData, ++ dsaRsSignOpData->P.dataLenInBytes); ++ ++ dsaRsSignOpData->Q.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->Q.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->Q.pData, ++ dsaRsSignOpData->Q.dataLenInBytes); ++ ++ /*generate random number with equal buffer size to Prime value Q, ++ but value less than Q */ ++ dsaRsSignOpData->K.dataLenInBytes = dsaRsSignOpData->Q.dataLenInBytes; ++ ++ randGenOpData.generateBits = CPA_TRUE; ++ randGenOpData.lenInBytes = dsaRsSignOpData->K.dataLenInBytes; ++ ++ icp_ocfDrvPtrAndLenToFlatBuffer(dsaRsSignOpData->K.pData, ++ dsaRsSignOpData->K.dataLenInBytes, ++ &randData); ++ ++ doCheck = 0; ++ while (icp_ocfDrvCheckALessThanB(&(dsaRsSignOpData->K), ++ &(dsaRsSignOpData->Q), &doCheck)) { ++ ++ if (CPA_STATUS_SUCCESS ++ != cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, ++ NULL, NULL, &randGenOpData, &randData)) { ++ APRINTK("%s(): ERROR - Failed to generate DSA RS Sign K" ++ "value\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = EAGAIN; ++ return EAGAIN; ++ } ++ ++ doCheck++; ++ if (DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS == doCheck) { ++ APRINTK("%s(): ERROR - Failed to find DSA RS Sign K " ++ "value less than Q value\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = EAGAIN; ++ return EAGAIN; ++ } ++ ++ } ++ /*Rand Data - no need to swap bytes for pK */ ++ ++ /* Link parameters */ ++ dsaRsSignOpData->G.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->G.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_nbits); ++ ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->G.pData, ++ dsaRsSignOpData->G.dataLenInBytes); ++ ++ dsaRsSignOpData->X.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->X.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_nbits); ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->X.pData, ++ dsaRsSignOpData->X.dataLenInBytes); ++ ++ /*OpenSSL dgst parameter is left in big endian byte order, ++ therefore no byte swap is required */ ++ dsaRsSignOpData->M.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->M.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX]. ++ crp_nbits); ++ ++ /* Output Parameters */ ++ pS->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX].crp_p; ++ BITS_TO_BYTES(pS->dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX]. ++ crp_nbits); ++ ++ pR->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX].crp_p; ++ BITS_TO_BYTES(pR->dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX]. ++ crp_nbits); ++ ++ lacStatus = cpaCyDsaSignRS(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvDsaRSSignCallBack, ++ callbackTag, dsaRsSignOpData, ++ &protocolStatus, pR, pS); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): DSA RS Sign Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ icp_ocfDrvFreeFlatBuffer(pS); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvDsaVerify ++ * ++ * Description : This function will map DSA RS Verify from OCF to the LAC API. ++ * ++ */ ++static int icp_ocfDrvDsaVerify(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ CpaCyDsaVerifyOpData *dsaVerifyOpData = NULL; ++ void *callbackTag = NULL; ++ CpaBoolean verifyStatus = CPA_FALSE; ++ ++ callbackTag = krp; ++ ++ dsaVerifyOpData = ++ icp_kmem_cache_zalloc(drvDSAVerify_zone, ICP_M_NOWAIT); ++ if (NULL == dsaVerifyOpData) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA Verify Op data struct\n", __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /* Link parameters */ ++ dsaVerifyOpData->P.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->P.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->P.pData, ++ dsaVerifyOpData->P.dataLenInBytes); ++ ++ dsaVerifyOpData->Q.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->Q.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->Q.pData, ++ dsaVerifyOpData->Q.dataLenInBytes); ++ ++ dsaVerifyOpData->G.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->G.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->G.pData, ++ dsaVerifyOpData->G.dataLenInBytes); ++ ++ dsaVerifyOpData->Y.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->Y.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->Y.pData, ++ dsaVerifyOpData->Y.dataLenInBytes); ++ ++ /*OpenSSL dgst parameter is left in big endian byte order, ++ therefore no byte swap is required */ ++ dsaVerifyOpData->M.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->M.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX]. ++ crp_nbits); ++ ++ dsaVerifyOpData->R.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->R.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->R.pData, ++ dsaVerifyOpData->R.dataLenInBytes); ++ ++ dsaVerifyOpData->S.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->S.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->S.pData, ++ dsaVerifyOpData->S.dataLenInBytes); ++ ++ lacStatus = cpaCyDsaVerify(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvDsaVerifyCallBack, ++ callbackTag, dsaVerifyOpData, &verifyStatus); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): DSA Verify Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ ICP_CACHE_FREE(drvDSAVerify_zone, dsaVerifyOpData); ++ krp->krp_status = ECANCELED; ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvDhP1Callback ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the DH operation. ++ */ ++static void ++icp_ocfDrvDhP1CallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pPhase1OpData = (CpaCyDhPhase1KeyGenOpData *) pOpData; ++ ++ if (NULL == pLocalOctetStringPV) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "pLocalOctetStringPV Data is NULL\n", __FUNCTION__); ++ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ } else { ++ APRINTK("%s(): Diffie Hellman Phase1 Key Gen failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } ++ ++ icp_ocfDrvSwapBytes(pLocalOctetStringPV->pData, ++ pLocalOctetStringPV->dataLenInBytes); ++ ++ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); ++ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ ++ crypto_kdone(krp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvModExpCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the Mod Exp operation. ++ */ ++static void ++icp_ocfDrvModExpCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpdata, CpaFlatBuffer * pResult) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyLnModExpOpData *pLnModExpOpData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpdata) { ++ DPRINTK("%s(): Invalid Mod Exp input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pLnModExpOpData = (CpaCyLnModExpOpData *) pOpdata; ++ ++ if (NULL == pResult) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "pResult data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); ++ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ } else { ++ APRINTK("%s(): LAC Mod Exp Operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } ++ ++ icp_ocfDrvSwapBytes(pResult->pData, pResult->dataLenInBytes); ++ ++ /*switch base size value back to original */ ++ if (pLnModExpOpData->base.pData == ++ (uint8_t *) & (krp-> ++ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. ++ crp_nbits)) { ++ *((uint32_t *) pLnModExpOpData->base.pData) = ++ ntohl(*((uint32_t *) pLnModExpOpData->base.pData)); ++ } ++ icp_ocfDrvFreeFlatBuffer(pResult); ++ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); ++ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); ++ ++ crypto_kdone(krp); ++ ++ return; ++ ++} ++ ++/* Name : icp_ocfDrvModExpCRTCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the Mod Exp CRT operation. ++ */ ++static void ++icp_ocfDrvModExpCRTCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pOutputData) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyRsaDecryptOpData *pDecryptData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pDecryptData = (CpaCyRsaDecryptOpData *) pOpData; ++ ++ if (NULL == pOutputData) { ++ DPRINTK("%s(): Invalid input parameter - " ++ "pOutputData is NULL\n", __FUNCTION__); ++ memset(pDecryptData->pRecipientPrivateKey, 0, ++ sizeof(CpaCyRsaPrivateKey)); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ pDecryptData->pRecipientPrivateKey); ++ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ } else { ++ APRINTK("%s(): LAC Mod Exp CRT operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } ++ ++ icp_ocfDrvSwapBytes(pOutputData->pData, pOutputData->dataLenInBytes); ++ ++ icp_ocfDrvFreeFlatBuffer(pOutputData); ++ memset(pDecryptData->pRecipientPrivateKey, 0, ++ sizeof(CpaCyRsaPrivateKey)); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ pDecryptData->pRecipientPrivateKey); ++ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); ++ ++ crypto_kdone(krp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvDsaRSSignCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the DSA RS sign operation. ++ */ ++static void ++icp_ocfDrvDsaRSSignCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, ++ CpaBoolean protocolStatus, ++ CpaFlatBuffer * pR, CpaFlatBuffer * pS) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyDsaRSSignOpData *pSignData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pSignData = (CpaCyDsaRSSignOpData *) pOpData; ++ ++ if (NULL == pR) { ++ DPRINTK("%s(): Invalid input parameter - " ++ "pR sign is NULL\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (NULL == pS) { ++ DPRINTK("%s(): Invalid input parameter - " ++ "pS sign is NULL\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS != status) { ++ APRINTK("%s(): LAC DSA RS Sign operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } else { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ ++ if (CPA_TRUE != protocolStatus) { ++ DPRINTK("%s(): LAC DSA RS Sign operation failed due " ++ "to protocol error\n", __FUNCTION__); ++ krp->krp_status = EIO; ++ } ++ } ++ ++ /* Swap bytes only when the callback status is successful and ++ protocolStatus is set to true */ ++ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == protocolStatus) { ++ icp_ocfDrvSwapBytes(pR->pData, pR->dataLenInBytes); ++ icp_ocfDrvSwapBytes(pS->pData, pS->dataLenInBytes); ++ } ++ ++ icp_ocfDrvFreeFlatBuffer(pR); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ memset(pSignData->K.pData, 0, pSignData->K.dataLenInBytes); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, pSignData->K.pData); ++ memset(pSignData, 0, sizeof(CpaCyDsaRSSignOpData)); ++ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); ++ crypto_kdone(krp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvDsaVerifyCallback ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the DSA Verify operation. ++ */ ++static void ++icp_ocfDrvDsaVerifyCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaBoolean verifyStatus) ++{ ++ ++ struct cryptkop *krp = NULL; ++ CpaCyDsaVerifyOpData *pVerData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pVerData = (CpaCyDsaVerifyOpData *) pOpData; ++ ++ if (CPA_STATUS_SUCCESS != status) { ++ APRINTK("%s(): LAC DSA Verify operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } else { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ ++ if (CPA_TRUE != verifyStatus) { ++ DPRINTK("%s(): DSA signature invalid\n", __FUNCTION__); ++ krp->krp_status = EIO; ++ } ++ } ++ ++ /* Swap bytes only when the callback status is successful and ++ verifyStatus is set to true */ ++ /*Just swapping back the key values for now. Possibly all ++ swapped buffers need to be reverted */ ++ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == verifyStatus) { ++ icp_ocfDrvSwapBytes(pVerData->R.pData, ++ pVerData->R.dataLenInBytes); ++ icp_ocfDrvSwapBytes(pVerData->S.pData, ++ pVerData->S.dataLenInBytes); ++ } ++ ++ memset(pVerData, 0, sizeof(CpaCyDsaVerifyOpData)); ++ ICP_CACHE_FREE(drvDSAVerify_zone, pVerData); ++ crypto_kdone(krp); ++ ++ return; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_common.c linux-3.0.4/crypto/ocf/ep80579/icp_common.c +--- linux-3.0.4.orig/crypto/ocf/ep80579/icp_common.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/icp_common.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,773 @@ ++/************************************************************************* ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++ ++/* ++ * An OCF module that uses Intel® QuickAssist Integrated Accelerator to do the ++ * crypto. ++ * ++ * This driver requires the ICP Access Library that is available from Intel in ++ * order to operate. ++ */ ++ ++#include "icp_ocf.h" ++ ++#define ICP_OCF_COMP_NAME "ICP_OCF" ++#define ICP_OCF_VER_MAIN (2) ++#define ICP_OCF_VER_MJR (1) ++#define ICP_OCF_VER_MNR (0) ++ ++#define MAX_DEREG_RETRIES (100) ++#define DEFAULT_DEREG_RETRIES (10) ++#define DEFAULT_DEREG_DELAY_IN_JIFFIES (10) ++ ++/* This defines the maximum number of sessions possible between OCF ++ and the OCF EP80579 Driver. If set to zero, there is no limit. */ ++#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0) ++#define NUM_SUPPORTED_CAPABILITIES (21) ++ ++/*Slab zone names*/ ++#define ICP_SESSION_DATA_NAME "icp_ocf.SesDat" ++#define ICP_OP_DATA_NAME "icp_ocf.OpDat" ++#define ICP_DH_NAME "icp_ocf.DH" ++#define ICP_MODEXP_NAME "icp_ocf.ModExp" ++#define ICP_RSA_DECRYPT_NAME "icp_ocf.RSAdec" ++#define ICP_RSA_PKEY_NAME "icp_ocf.RSApk" ++#define ICP_DSA_SIGN_NAME "icp_ocf.DSAsg" ++#define ICP_DSA_VER_NAME "icp_ocf.DSAver" ++#define ICP_RAND_VAL_NAME "icp_ocf.DSArnd" ++#define ICP_FLAT_BUFF_NAME "icp_ocf.FB" ++ ++/*Slabs zones*/ ++icp_kmem_cache drvSessionData_zone = NULL; ++icp_kmem_cache drvOpData_zone = NULL; ++icp_kmem_cache drvDH_zone = NULL; ++icp_kmem_cache drvLnModExp_zone = NULL; ++icp_kmem_cache drvRSADecrypt_zone = NULL; ++icp_kmem_cache drvRSAPrivateKey_zone = NULL; ++icp_kmem_cache drvDSARSSign_zone = NULL; ++icp_kmem_cache drvDSARSSignKValue_zone = NULL; ++icp_kmem_cache drvDSAVerify_zone = NULL; ++ ++/*Slab zones for flatbuffers and bufferlist*/ ++icp_kmem_cache drvFlatBuffer_zone = NULL; ++ ++static inline int icp_cache_null_check(void) ++{ ++ return (drvSessionData_zone && drvOpData_zone ++ && drvDH_zone && drvLnModExp_zone && drvRSADecrypt_zone ++ && drvRSAPrivateKey_zone && drvDSARSSign_zone ++ && drvDSARSSign_zone && drvDSARSSignKValue_zone ++ && drvDSAVerify_zone && drvFlatBuffer_zone); ++} ++ ++/*Function to free all allocated slab caches before exiting the module*/ ++static void icp_ocfDrvFreeCaches(void); ++ ++int32_t icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ ++/* Module parameter - gives the number of times LAC deregistration shall be ++ re-tried */ ++int num_dereg_retries = DEFAULT_DEREG_RETRIES; ++ ++/* Module parameter - gives the delay time in jiffies before a LAC session ++ shall be attempted to be deregistered again */ ++int dereg_retry_delay_in_jiffies = DEFAULT_DEREG_DELAY_IN_JIFFIES; ++ ++/* Module parameter - gives the maximum number of sessions possible between ++ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ ++int max_sessions = DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT; ++ ++/* This is set when the module is removed from the system, no further ++ processing can take place if this is set */ ++icp_atomic_t icp_ocfDrvIsExiting = ICP_ATOMIC_INIT(0); ++ ++/* This is used to show how many lac sessions were not deregistered*/ ++icp_atomic_t lac_session_failed_dereg_count = ICP_ATOMIC_INIT(0); ++ ++/* This is used to track the number of registered sessions between OCF and ++ * and the OCF EP80579 driver, when max_session is set to value other than ++ * zero. This ensures that the max_session set for the OCF and the driver ++ * is equal to the LAC registered sessions */ ++icp_atomic_t num_ocf_to_drv_registered_sessions = ICP_ATOMIC_INIT(0); ++ ++/* Head of linked list used to store session data */ ++icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; ++icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; ++ ++icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; ++ ++/*Below pointer is only used in linux, FreeBSD uses the name to ++create its own variable name*/ ++icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ = NULL; ++ICP_WORKQUEUE_DEFINE_THREAD(icp_ocfDrvFreeLacSessionWorkQ); ++ ++struct icp_drvBuffListInfo defBuffListInfo; ++ ++/* Name : icp_ocfDrvInit ++ * ++ * Description : This function will register all the symmetric and asymmetric ++ * functionality that will be accelerated by the hardware. It will also ++ * get a unique driver ID from the OCF and initialise all slab caches ++ */ ++ICP_MODULE_INIT_FUNC(icp_ocfDrvInit) ++{ ++ int ocfStatus = 0; ++ ++ IPRINTK("=== %s ver %d.%d.%d ===\n", ICP_OCF_COMP_NAME, ++ ICP_OCF_VER_MAIN, ICP_OCF_VER_MJR, ICP_OCF_VER_MNR); ++ ++ if (MAX_DEREG_RETRIES < num_dereg_retries) { ++ EPRINTK("Session deregistration retry count set to greater " ++ "than %d", MAX_DEREG_RETRIES); ++ icp_module_return_code(EINVAL); ++ } ++ ++ /* Initialize and Start the Cryptographic component */ ++ if (CPA_STATUS_SUCCESS != ++ cpaCyStartInstance(CPA_INSTANCE_HANDLE_SINGLE)) { ++ EPRINTK("Failed to initialize and start the instance " ++ "of the Cryptographic component.\n"); ++ return icp_module_return_code(EINVAL); ++ } ++ ++ icp_spin_lock_init(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ /* Set the default size of BufferList to allocate */ ++ memset(&defBuffListInfo, 0, sizeof(struct icp_drvBuffListInfo)); ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvBufferListMemInfo(ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS, ++ &defBuffListInfo)) { ++ EPRINTK("Failed to get bufferlist memory info.\n"); ++ return icp_module_return_code(ENOMEM); ++ } ++ ++ /*Register OCF EP80579 Driver with OCF */ ++ icp_ocfDrvDriverId = ICP_CRYPTO_GET_DRIVERID(); ++ ++ if (icp_ocfDrvDriverId < 0) { ++ EPRINTK("%s : ICP driver failed to register with OCF!\n", ++ __FUNCTION__); ++ return icp_module_return_code(ENODEV); ++ } ++ ++ /*Create all the slab caches used by the OCF EP80579 Driver */ ++ drvSessionData_zone = ++ ICP_CACHE_CREATE(ICP_SESSION_DATA_NAME, struct icp_drvSessionData); ++ ++ /* ++ * Allocation of the OpData includes the allocation space for meta data. ++ * The memory after the opData structure is reserved for this meta data. ++ */ ++ drvOpData_zone = ++ icp_kmem_cache_create(ICP_OP_DATA_NAME, ++ sizeof(struct icp_drvOpData) + ++ defBuffListInfo.metaSize, ++ ICP_KERNEL_CACHE_ALIGN, ++ ICP_KERNEL_CACHE_NOINIT); ++ ++ drvDH_zone = ICP_CACHE_CREATE(ICP_DH_NAME, CpaCyDhPhase1KeyGenOpData); ++ ++ drvLnModExp_zone = ++ ICP_CACHE_CREATE(ICP_MODEXP_NAME, CpaCyLnModExpOpData); ++ ++ drvRSADecrypt_zone = ++ ICP_CACHE_CREATE(ICP_RSA_DECRYPT_NAME, CpaCyRsaDecryptOpData); ++ ++ drvRSAPrivateKey_zone = ++ ICP_CACHE_CREATE(ICP_RSA_PKEY_NAME, CpaCyRsaPrivateKey); ++ ++ drvDSARSSign_zone = ++ ICP_CACHE_CREATE(ICP_DSA_SIGN_NAME, CpaCyDsaRSSignOpData); ++ ++ /*too awkward to use a macro here */ ++ drvDSARSSignKValue_zone = ++ ICP_CACHE_CREATE(ICP_RAND_VAL_NAME, ++ DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES); ++ ++ drvDSAVerify_zone = ++ ICP_CACHE_CREATE(ICP_DSA_VER_NAME, CpaCyDsaVerifyOpData); ++ ++ drvFlatBuffer_zone = ++ ICP_CACHE_CREATE(ICP_FLAT_BUFF_NAME, CpaFlatBuffer); ++ ++ if (0 == icp_cache_null_check()) { ++ icp_ocfDrvFreeCaches(); ++ EPRINTK("%s() line %d: Not enough memory!\n", ++ __FUNCTION__, __LINE__); ++ return ENOMEM; ++ } ++ ++ /* Register the ICP symmetric crypto support. */ ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_NULL_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_DES_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_3DES_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_AES_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_ARC4, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5_HMAC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1_HMAC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256_HMAC, ++ ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384_HMAC, ++ ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512_HMAC, ++ ocfStatus); ++ ++ /* Register the ICP asymmetric algorithm support */ ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DH_COMPUTE_KEY, ++ ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP, ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP_CRT, ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_SIGN, ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_VERIFY, ocfStatus); ++ ++ /* Register the ICP random number generator support */ ++ ICP_REG_RAND_WITH_OCF(icp_ocfDrvDriverId, ++ icp_ocfDrvReadRandom, NULL, ocfStatus); ++ ++ if (OCF_ZERO_FUNCTIONALITY_REGISTERED == ocfStatus) { ++ DPRINTK("%s: Failed to register any device capabilities\n", ++ __FUNCTION__); ++ icp_ocfDrvFreeCaches(); ++ icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ return icp_module_return_code(ECANCELED); ++ } ++ ++ DPRINTK("%s: Registered %d of %d device capabilities\n", ++ __FUNCTION__, ocfStatus, NUM_SUPPORTED_CAPABILITIES); ++ ++ /*Session data linked list used during module exit */ ++ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead); ++ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList); ++ ++ ICP_WORKQUEUE_CREATE(icp_ocfDrvFreeLacSessionWorkQ, "icpwq"); ++ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { ++ EPRINTK("%s: Failed to create single " ++ "thread workqueue\n", __FUNCTION__); ++ icp_ocfDrvFreeCaches(); ++ icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ return icp_module_return_code(ENOMEM); ++ } ++ ++ return icp_module_return_code(0); ++} ++ ++/* Name : icp_ocfDrvExit ++ * ++ * Description : This function will deregister all the symmetric sessions ++ * registered with the LAC component. It will also deregister all symmetric ++ * and asymmetric functionality that can be accelerated by the hardware via OCF ++ * and random number generation if it is enabled. ++ */ ++ICP_MODULE_EXIT_FUNC(icp_ocfDrvExit) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ struct icp_drvSessionData *sessionData = NULL; ++ struct icp_drvSessionData *tempSessionData = NULL; ++ int i, remaining_delay_time_in_jiffies = 0; ++ ++ /* For FreeBSD the invariant macro below makes function to return */ ++ /* with EBUSY value in the case of any session which has been regi- */ ++ /* stered with LAC not being deregistered. */ ++ /* The Linux implementation is empty since it is purely to compensate */ ++ /* for a limitation of the FreeBSD 7.1 Opencrypto framework. */ ++ ++ ICP_MODULE_EXIT_INV(); ++ ++ /* There is a possibility of a process or new session command being */ ++ /* sent before this variable is incremented. The aim of this variable */ ++ /* is to stop a loop of calls creating a deadlock situation which */ ++ /* would prevent the driver from exiting. */ ++ icp_atomic_set(&icp_ocfDrvIsExiting, 1); ++ ++ /*Existing sessions will be routed to another driver after these calls */ ++ crypto_unregister_all(icp_ocfDrvDriverId); ++ crypto_runregister_all(icp_ocfDrvDriverId); ++ ++ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { ++ DPRINTK("%s: workqueue already " ++ "destroyed, therefore module exit " ++ " function already called. Exiting.\n", __FUNCTION__); ++ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; ++ } ++ /*If any sessions are waiting to be deregistered, do that. This also ++ flushes the work queue */ ++ ICP_WORKQUEUE_DESTROY(icp_ocfDrvFreeLacSessionWorkQ); ++ ++ /*ENTER CRITICAL SECTION */ ++ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, ++ &icp_ocfDrvGlobalSymListHead, listNode) { ++ for (i = 0; i < num_dereg_retries; i++) { ++ /*No harm if bad input - LAC will handle error cases */ ++ if (ICP_SESSION_RUNNING == tempSessionData->inUse) { ++ lacStatus = ++ cpaCySymRemoveSession ++ (CPA_INSTANCE_HANDLE_SINGLE, ++ tempSessionData->sessHandle); ++ if (CPA_STATUS_SUCCESS == lacStatus) { ++ /* Succesfully deregistered */ ++ break; ++ } else if (CPA_STATUS_RETRY != lacStatus) { ++ icp_atomic_inc ++ (&lac_session_failed_dereg_count); ++ break; ++ } ++ ++ /*schedule_timout returns the time left for completion if ++ * this task is set to TASK_INTERRUPTIBLE */ ++ remaining_delay_time_in_jiffies = ++ dereg_retry_delay_in_jiffies; ++ while (0 > remaining_delay_time_in_jiffies) { ++ remaining_delay_time_in_jiffies = ++ icp_schedule_timeout ++ (&icp_ocfDrvSymSessInfoListSpinlock, ++ remaining_delay_time_in_jiffies); ++ } ++ ++ DPRINTK ++ ("%s(): Retry %d to deregistrate the session\n", ++ __FUNCTION__, i); ++ } ++ } ++ ++ /*remove from current list */ ++ ICP_LIST_DEL(tempSessionData, listNode); ++ /*add to free mem linked list */ ++ ICP_LIST_ADD(tempSessionData, ++ &icp_ocfDrvGlobalSymListHead_FreeMemList, ++ listNode); ++ ++ } ++ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ /*set back to initial values */ ++ sessionData = NULL; ++ /*still have a reference in our list! */ ++ tempSessionData = NULL; ++ /*free memory */ ++ ++ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, ++ &icp_ocfDrvGlobalSymListHead_FreeMemList, ++ listNode) { ++ ++ ICP_LIST_DEL(tempSessionData, listNode); ++ /* Free allocated CpaCySymSessionCtx */ ++ if (NULL != tempSessionData->sessHandle) { ++ icp_kfree(tempSessionData->sessHandle); ++ } ++ memset(tempSessionData, 0, sizeof(struct icp_drvSessionData)); ++ ICP_CACHE_FREE(drvSessionData_zone, tempSessionData); ++ } ++ ++ if (0 != icp_atomic_read(&lac_session_failed_dereg_count)) { ++ DPRINTK("%s(): %d LAC sessions were not deregistered " ++ "correctly. This is not a clean exit! \n", ++ __FUNCTION__, ++ icp_atomic_read(&lac_session_failed_dereg_count)); ++ } ++ ++ icp_ocfDrvFreeCaches(); ++ icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ ++ icp_spin_lock_destroy(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ /* Shutdown the Cryptographic component */ ++ lacStatus = cpaCyStopInstance(CPA_INSTANCE_HANDLE_SINGLE); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ DPRINTK("%s(): Failed to stop instance of the " ++ "Cryptographic component.(status == %d)\n", ++ __FUNCTION__, lacStatus); ++ } ++ ++ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; ++} ++ ++/* Name : icp_ocfDrvFreeCaches ++ * ++ * Description : This function deregisters all slab caches ++ */ ++static void icp_ocfDrvFreeCaches(void) ++{ ++ icp_atomic_set(&icp_ocfDrvIsExiting, 1); ++ ++ /*Sym Zones */ ++ ICP_CACHE_DESTROY(drvSessionData_zone); ++ ICP_CACHE_DESTROY(drvOpData_zone); ++ ++ /*Asym zones */ ++ ICP_CACHE_DESTROY(drvDH_zone); ++ ICP_CACHE_DESTROY(drvLnModExp_zone); ++ ICP_CACHE_DESTROY(drvRSADecrypt_zone); ++ ICP_CACHE_DESTROY(drvRSAPrivateKey_zone); ++ ICP_CACHE_DESTROY(drvDSARSSignKValue_zone); ++ ICP_CACHE_DESTROY(drvDSARSSign_zone); ++ ICP_CACHE_DESTROY(drvDSAVerify_zone); ++ ++ /*FlatBuffer and BufferList Zones */ ++ ICP_CACHE_DESTROY(drvFlatBuffer_zone); ++ ++} ++ ++/* Name : icp_ocfDrvDeregRetry ++ * ++ * Description : This function will try to farm the session deregistration ++ * off to a work queue. If it fails, nothing more can be done and it ++ * returns an error ++ */ ++int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister) ++{ ++ struct icp_ocfDrvFreeLacSession *workstore = NULL; ++ ++ DPRINTK("%s(): Retry - Deregistering session (%p)\n", ++ __FUNCTION__, sessionToDeregister); ++ ++ /*make sure the session is not available to be allocated during this ++ process */ ++ icp_atomic_inc(&lac_session_failed_dereg_count); ++ ++ /*Farm off to work queue */ ++ workstore = ++ icp_kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), ICP_M_NOWAIT); ++ if (NULL == workstore) { ++ DPRINTK("%s(): unable to free session - no memory available " ++ "for work queue\n", __FUNCTION__); ++ return ENOMEM; ++ } ++ ++ workstore->sessionToDeregister = sessionToDeregister; ++ ++ icp_init_work(&(workstore->work), ++ icp_ocfDrvDeferedFreeLacSessionTaskFn, workstore); ++ ++ ICP_WORKQUEUE_ENQUEUE(icp_ocfDrvFreeLacSessionWorkQ, ++ &(workstore->work)); ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++ ++} ++ ++/* Name : icp_ocfDrvDeferedFreeLacSessionProcess ++ * ++ * Description : This function will retry (module input parameter) ++ * 'num_dereg_retries' times to deregister any symmetric session that recieves a ++ * CPA_STATUS_RETRY message from the LAC component. This function is run in ++ * Thread context because it is called from a worker thread ++ */ ++void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg) ++{ ++ struct icp_ocfDrvFreeLacSession *workstore = NULL; ++ CpaCySymSessionCtx sessionToDeregister = NULL; ++ int i = 0; ++ int remaining_delay_time_in_jiffies = 0; ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ ++ workstore = (struct icp_ocfDrvFreeLacSession *)arg; ++ if (NULL == workstore) { ++ DPRINTK("%s() function called with null parameter \n", ++ __FUNCTION__); ++ return; ++ } ++ ++ sessionToDeregister = workstore->sessionToDeregister; ++ icp_kfree(workstore); ++ ++ /*if exiting, give deregistration one more blast only */ ++ if (icp_atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) { ++ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, ++ sessionToDeregister); ++ ++ if (lacStatus != CPA_STATUS_SUCCESS) { ++ DPRINTK("%s() Failed to Dereg LAC session %p " ++ "during module exit\n", __FUNCTION__, ++ sessionToDeregister); ++ return; ++ } ++ ++ icp_atomic_dec(&lac_session_failed_dereg_count); ++ return; ++ } ++ ++ for (i = 0; i <= num_dereg_retries; i++) { ++ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, ++ sessionToDeregister); ++ ++ if (lacStatus == CPA_STATUS_SUCCESS) { ++ icp_atomic_dec(&lac_session_failed_dereg_count); ++ return; ++ } ++ if (lacStatus != CPA_STATUS_RETRY) { ++ DPRINTK("%s() Failed to deregister session - lacStatus " ++ " = %d", __FUNCTION__, lacStatus); ++ break; ++ } ++ ++ /*schedule_timout returns the time left for completion if this ++ task is set to TASK_INTERRUPTIBLE */ ++ remaining_delay_time_in_jiffies = dereg_retry_delay_in_jiffies; ++ while (0 < remaining_delay_time_in_jiffies) { ++ remaining_delay_time_in_jiffies = ++ icp_schedule_timeout(NULL, ++ remaining_delay_time_in_jiffies); ++ } ++ ++ } ++ ++ DPRINTK("%s(): Unable to deregister session\n", __FUNCTION__); ++ DPRINTK("%s(): Number of unavailable LAC sessions = %d\n", __FUNCTION__, ++ icp_atomic_read(&lac_session_failed_dereg_count)); ++} ++ ++/* Name : icp_ocfDrvPtrAndLenToFlatBuffer ++ * ++ * Description : This function converts a "pointer and length" buffer ++ * structure to Fredericksburg Flat Buffer (CpaFlatBuffer) format. ++ * ++ * This function assumes that the data passed in are valid. ++ */ ++inline void ++icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, ++ CpaFlatBuffer * pFlatBuffer) ++{ ++ pFlatBuffer->pData = pData; ++ pFlatBuffer->dataLenInBytes = len; ++} ++ ++/* Name : icp_ocfDrvPtrAndLenToBufferList ++ * ++ * Description : This function converts a "pointer and length" buffer ++ * structure to Fredericksburg Scatter/Gather Buffer (CpaBufferList) format. ++ * ++ * This function assumes that the data passed in are valid. ++ */ ++inline void ++icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, ++ CpaBufferList * pBufferList) ++{ ++ pBufferList->numBuffers = 1; ++ pBufferList->pBuffers->pData = pDataIn; ++ pBufferList->pBuffers->dataLenInBytes = length; ++} ++ ++/* Name : icp_ocfDrvBufferListToPtrAndLen ++ * ++ * Description : This function converts Fredericksburg Scatter/Gather Buffer ++ * (CpaBufferList) format to a "pointer and length" buffer structure. ++ * ++ * This function assumes that the data passed in are valid. ++ */ ++inline void ++icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, ++ void **ppDataOut, uint32_t * pLength) ++{ ++ *ppDataOut = pBufferList->pBuffers->pData; ++ *pLength = pBufferList->pBuffers->dataLenInBytes; ++} ++ ++/* Name : icp_ocfDrvBufferListMemInfo ++ * ++ * Description : This function will set the number of flat buffers in ++ * bufferlist, the size of memory to allocate for the pPrivateMetaData ++ * member of the CpaBufferList. ++ */ ++int ++icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, ++ struct icp_drvBuffListInfo *buffListInfo) ++{ ++ buffListInfo->numBuffers = numBuffers; ++ ++ if (CPA_STATUS_SUCCESS != ++ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, ++ buffListInfo->numBuffers, ++ &(buffListInfo->metaSize))) { ++ EPRINTK("%s() Failed to get buffer list meta size.\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvFreeFlatBuffer ++ * ++ * Description : This function will deallocate flat buffer. ++ */ ++inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer) ++{ ++ if (pFlatBuffer != NULL) { ++ memset(pFlatBuffer, 0, sizeof(CpaFlatBuffer)); ++ ICP_CACHE_FREE(drvFlatBuffer_zone, pFlatBuffer); ++ } ++} ++ ++/* Name : icp_ocfDrvAllocMetaData ++ * ++ * Description : This function will allocate memory for the ++ * pPrivateMetaData member of CpaBufferList. ++ */ ++inline int ++icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, ++ struct icp_drvOpData *pOpData) ++{ ++ Cpa32U metaSize = 0; ++ ++ if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { ++ uint8_t *pOpDataStartAddr = (uint8_t *) pOpData; ++ ++ if (0 == defBuffListInfo.metaSize) { ++ pBufferList->pPrivateMetaData = NULL; ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++ } ++ /* ++ * The meta data allocation has been included as part of the ++ * op data. It has been pre-allocated in memory just after the ++ * icp_drvOpData structure. ++ */ ++ pBufferList->pPrivateMetaData = (void *)(pOpDataStartAddr + ++ sizeof(struct ++ icp_drvOpData)); ++ } else { ++ if (CPA_STATUS_SUCCESS != ++ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, ++ pBufferList->numBuffers, ++ &metaSize)) { ++ EPRINTK("%s() Failed to get buffer list meta size.\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ if (0 == metaSize) { ++ pBufferList->pPrivateMetaData = NULL; ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++ } ++ ++ pBufferList->pPrivateMetaData = ++ icp_kmalloc(metaSize, ICP_M_NOWAIT); ++ } ++ if (NULL == pBufferList->pPrivateMetaData) { ++ EPRINTK("%s() Failed to allocate pPrivateMetaData.\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvFreeMetaData ++ * ++ * Description : This function will deallocate pPrivateMetaData memory. ++ */ ++inline void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList) ++{ ++ if (NULL == pBufferList->pPrivateMetaData) { ++ return; ++ } ++ ++ /* ++ * Only free the meta data if the BufferList has more than ++ * ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS number of buffers. ++ * Otherwise, the meta data shall be freed when the icp_drvOpData is ++ * freed. ++ */ ++ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers) { ++ icp_kfree(pBufferList->pPrivateMetaData); ++ } ++} ++ ++/* Module declaration, init and exit functions */ ++ICP_DECLARE_MODULE(icp_ocf, icp_ocfDrvInit, icp_ocfDrvExit); ++ICP_MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration"); ++ICP_MODULE_VERSION(icp_ocf, ICP_OCF_VER_MJR); ++ICP_MODULE_LICENSE("Dual BSD/GPL"); ++ICP_MODULE_AUTHOR("Intel"); ++ ++/* Module parameters */ ++ICP_MODULE_PARAM_INT(icp_ocf, num_dereg_retries, ++ "Number of times to retry LAC Sym Session Deregistration. " ++ "Default 10, Max 100"); ++ICP_MODULE_PARAM_INT(icp_ocf, dereg_retry_delay_in_jiffies, "Delay in jiffies " ++ "(added to a schedule() function call) before a LAC Sym " ++ "Session Dereg is retried. Default 10"); ++ICP_MODULE_PARAM_INT(icp_ocf, max_sessions, ++ "This sets the maximum number of sessions " ++ "between OCF and this driver. If this value is set to zero," ++ "max session count checking is disabled. Default is zero(0)"); ++ ++/* Module dependencies */ ++#define MODULE_MIN_VER 1 ++#define CRYPTO_MAX_VER 3 ++#define LAC_MAX_VER 2 ++ ++ICP_MODULE_DEPEND(icp_ocf, crypto, MODULE_MIN_VER, MODULE_MIN_VER, ++ CRYPTO_MAX_VER); ++ICP_MODULE_DEPEND(icp_ocf, cryptodev, MODULE_MIN_VER, MODULE_MIN_VER, ++ CRYPTO_MAX_VER); ++ICP_MODULE_DEPEND(icp_ocf, icp_crypto, MODULE_MIN_VER, MODULE_MIN_VER, ++ LAC_MAX_VER); +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_ocf.h linux-3.0.4/crypto/ocf/ep80579/icp_ocf.h +--- linux-3.0.4.orig/crypto/ocf/ep80579/icp_ocf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/icp_ocf.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,376 @@ ++/*************************************************************************** ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++ ++/* ++ * OCF driver header file for the Intel ICP processor. ++ */ ++ ++#ifndef ICP_OCF_H_ ++#define ICP_OCF_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "icp_os.h" ++ ++#define NUM_BITS_IN_BYTE (8) ++#define NUM_BITS_IN_BYTE_MINUS_ONE (NUM_BITS_IN_BYTE -1) ++#define INVALID_DRIVER_ID (-1) ++#define RETURN_RAND_NUM_GEN_FAILED (-1) ++ ++/*This is the max block cipher initialisation vector*/ ++#define MAX_IV_LEN_IN_BYTES (20) ++/*This is used to check whether the OCF to this driver session limit has ++ been disabled*/ ++#define NO_OCF_TO_DRV_MAX_SESSIONS (0) ++ ++/*OCF values mapped here*/ ++#define ICP_SHA1_DIGEST_SIZE_IN_BYTES (SHA1_HASH_LEN) ++#define ICP_SHA256_DIGEST_SIZE_IN_BYTES (SHA2_256_HASH_LEN) ++#define ICP_SHA384_DIGEST_SIZE_IN_BYTES (SHA2_384_HASH_LEN) ++#define ICP_SHA512_DIGEST_SIZE_IN_BYTES (SHA2_512_HASH_LEN) ++#define ICP_MD5_DIGEST_SIZE_IN_BYTES (MD5_HASH_LEN) ++#define ARC4_COUNTER_LEN (ARC4_BLOCK_LEN) ++ ++#define OCF_REGISTRATION_STATUS_SUCCESS (0) ++#define OCF_ZERO_FUNCTIONALITY_REGISTERED (0) ++#define ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR (0) ++#define ICP_OCF_DRV_STATUS_SUCCESS (0) ++#define ICP_OCF_DRV_STATUS_FAIL (1) ++ ++/*Turn on/off debug options*/ ++#define ICP_OCF_PRINT_DEBUG_MESSAGES (0) ++#define ICP_OCF_PRINT_KERN_ALERT (1) ++#define ICP_OCF_PRINT_KERN_ERRS (1) ++ ++#if ICP_OCF_PRINT_DEBUG_MESSAGES == 1 ++#define DPRINTK(args...) \ ++{ \ ++ ICP_IPRINTK(args); \ ++} ++ ++#else //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 ++ ++#define DPRINTK(args...) ++ ++#endif //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 ++ ++#if ICP_OCF_PRINT_KERN_ALERT == 1 ++#define APRINTK(args...) \ ++{ \ ++ ICP_APRINTK(args); \ ++} ++ ++#else //ICP_OCF_PRINT_KERN_ALERT == 1 ++ ++#define APRINTK(args...) ++ ++#endif //ICP_OCF_PRINT_KERN_ALERT == 1 ++ ++#if ICP_OCF_PRINT_KERN_ERRS == 1 ++#define EPRINTK(args...) \ ++{ \ ++ ICP_EPRINTK(args); \ ++} ++ ++#else //ICP_OCF_PRINT_KERN_ERRS == 1 ++ ++#define EPRINTK(args...) ++ ++#endif //ICP_OCF_PRINT_KERN_ERRS == 1 ++ ++#define IPRINTK(args...) \ ++{ \ ++ ICP_IPRINTK(args); \ ++} ++ ++/*DSA Prime Q size in bytes (as defined in the standard) */ ++#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20) ++ ++#define BITS_TO_BYTES(bytes, bits) \ ++ bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE ++ ++typedef enum { ++ ICP_OCF_DRV_ALG_CIPHER = 0, ++ ICP_OCF_DRV_ALG_HASH ++} icp_ocf_drv_alg_type_t; ++ ++typedef ICP_LIST_HEAD(icp_drvSessionListHead_s, ++ icp_drvSessionData) icp_drvSessionListHead_t; ++ ++/*Values used to derisk chances of performs being called against ++deregistered sessions (for which the slab page has been reclaimed) ++This is not a fix - since page frames are reclaimed from a slab, one cannot ++rely on that memory not being re-used by another app.*/ ++typedef enum { ++ ICP_SESSION_INITIALISED = 0x5C5C5C, ++ ICP_SESSION_RUNNING = 0x005C00, ++ ICP_SESSION_DEREGISTERED = 0xC5C5C5 ++} usage_derisk; ++ ++/* This struct is required for deferred session ++ deregistration as a work queue function can ++ only have one argument*/ ++struct icp_ocfDrvFreeLacSession { ++ CpaCySymSessionCtx sessionToDeregister; ++ icp_workstruct work; ++}; ++ ++/* ++This is the OCF<->OCF_DRV session object: ++ ++1.listNode ++ The first member is a listNode. These session objects are added to a linked ++ list in order to make it easier to remove them all at session exit time. ++ ++2.inUse ++ The second member is used to give the session object state and derisk the ++ possibility of OCF batch calls executing against a deregistered session (as ++ described above). ++ ++3.sessHandle ++ The third member is a LAC<->OCF_DRV session handle (initialised with the first ++ perform request for that session). ++ ++4.lacSessCtx ++ The fourth is the LAC session context. All the parameters for this structure ++ are only known when the first perform request for this session occurs. That is ++ why the OCF EP80579 Driver only registers a new LAC session at perform time ++*/ ++struct icp_drvSessionData { ++ ICP_LIST_ENTRY(icp_drvSessionData) listNode; ++ usage_derisk inUse; ++ CpaCySymSessionCtx sessHandle; ++ CpaCySymSessionSetupData lacSessCtx; ++}; ++ ++/* These are all defined in icp_common.c */ ++extern icp_atomic_t lac_session_failed_dereg_count; ++extern icp_atomic_t icp_ocfDrvIsExiting; ++extern icp_atomic_t num_ocf_to_drv_registered_sessions; ++ ++extern int32_t icp_ocfDrvDriverId; ++ ++extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; ++extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; ++extern icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ; ++extern icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; ++ ++/*Slab zones for symettric functionality, instantiated in icp_common.c*/ ++extern icp_kmem_cache drvSessionData_zone; ++extern icp_kmem_cache drvOpData_zone; ++ ++/*Slabs zones for asymettric functionality, instantiated in icp_common.c*/ ++extern icp_kmem_cache drvDH_zone; ++extern icp_kmem_cache drvLnModExp_zone; ++extern icp_kmem_cache drvRSADecrypt_zone; ++extern icp_kmem_cache drvRSAPrivateKey_zone; ++extern icp_kmem_cache drvDSARSSign_zone; ++extern icp_kmem_cache drvDSARSSignKValue_zone; ++extern icp_kmem_cache drvDSAVerify_zone; ++ ++/* Module parameters defined in icp_cpmmon.c*/ ++ ++/* Module parameters - gives the number of times LAC deregistration shall be ++ re-tried */ ++extern int num_dereg_retries; ++ ++/* Module parameter - gives the delay time in jiffies before a LAC session ++ shall be attempted to be deregistered again */ ++extern int dereg_retry_delay_in_jiffies; ++ ++/* Module parameter - gives the maximum number of sessions possible between ++ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ ++extern int max_sessions; ++ ++/*Slab zones for flatbuffers and bufferlist*/ ++extern icp_kmem_cache drvFlatBuffer_zone; ++ ++#define ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS (16) ++ ++struct icp_drvBuffListInfo { ++ Cpa16U numBuffers; ++ Cpa32U metaSize; ++ Cpa32U metaOffset; ++ Cpa32U buffListSize; ++}; ++ ++extern struct icp_drvBuffListInfo defBuffListInfo; ++ ++/* This struct is used to keep a reference to the relevant node in the list ++ of sessionData structs, to the buffer type required by OCF and to the OCF ++ provided crp struct that needs to be returned. All this info is needed in ++ the callback function.*/ ++struct icp_drvOpData { ++ CpaCySymOpData lacOpData; ++ uint32_t digestSizeInBytes; ++ struct cryptop *crp; ++ uint8_t bufferType; ++ uint8_t ivData[MAX_IV_LEN_IN_BYTES]; ++ uint16_t numBufferListArray; ++ CpaBufferList srcBuffer; ++ CpaFlatBuffer bufferListArray[ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS]; ++ CpaBoolean verifyResult; ++}; ++ ++/* Create a new session between OCF and this driver*/ ++int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sild, ++ struct cryptoini *cri); ++ ++/* Free a session between this driver and the Quick Assist Framework*/ ++int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid); ++ ++/* Defer freeing a Quick Assist session*/ ++void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg); ++ ++/* Process OCF cryptographic request for a symmetric algorithm*/ ++int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint); ++ ++/* Process OCF cryptographic request for an asymmetric algorithm*/ ++int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint); ++ ++/* Populate a buffer with random data*/ ++int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords); ++ ++/* Retry Quick Assist session deregistration*/ ++int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister); ++ ++/* Convert an OS scatter gather list to a CPA buffer list*/ ++int icp_ocfDrvPacketBuffToBufferList(icp_packet_buffer_t * pPacketBuffer, ++ CpaBufferList * bufferList); ++ ++/* Convert a CPA buffer list to an OS scatter gather list*/ ++int icp_ocfDrvBufferListToPacketBuff(CpaBufferList * bufferList, ++ icp_packet_buffer_t ** pPacketBuffer); ++ ++/* Get the number of buffers in an OS scatter gather list*/ ++uint16_t icp_ocfDrvGetPacketBuffFrags(icp_packet_buffer_t * pPacketBuffer); ++ ++/* Convert a single OS buffer to a CPA Flat Buffer*/ ++void icp_ocfDrvSinglePacketBuffToFlatBuffer(icp_packet_buffer_t * pPacketBuffer, ++ CpaFlatBuffer * pFlatBuffer); ++ ++/* Add pointer and length to a CPA Flat Buffer structure*/ ++void icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, ++ CpaFlatBuffer * pFlatBuffer); ++ ++/* Convert pointer and length values to a CPA buffer list*/ ++void icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, ++ CpaBufferList * pBufferList); ++ ++/* Convert a CPA buffer list to pointer and length values*/ ++void icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, ++ void **ppDataOut, uint32_t * pLength); ++ ++/* Set the number of flat buffers in bufferlist and the size of memory ++ to allocate for the pPrivateMetaData member of the CpaBufferList.*/ ++int icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, ++ struct icp_drvBuffListInfo *buffListInfo); ++ ++/* Find pointer position of the digest within an OS scatter gather list*/ ++uint8_t *icp_ocfDrvPacketBufferDigestPointerFind(struct icp_drvOpData ++ *drvOpData, ++ int offsetInBytes, ++ uint32_t digestSizeInBytes); ++ ++/*This top level function is used to find a pointer to where a digest is ++ stored/needs to be inserted. */ ++uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData, ++ struct cryptodesc *crp_desc); ++ ++/* Free a CPA flat buffer*/ ++void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer); ++ ++/* This function will allocate memory for the pPrivateMetaData ++ member of CpaBufferList. */ ++int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, ++ struct icp_drvOpData *pOpData); ++ ++/* Free data allocated for the pPrivateMetaData ++ member of CpaBufferList.*/ ++void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList); ++ ++#define ICP_CACHE_CREATE(cache_ID, cache_name) \ ++ icp_kmem_cache_create(cache_ID, sizeof(cache_name),ICP_KERNEL_CACHE_ALIGN,\ ++ ICP_KERNEL_CACHE_NOINIT) ++ ++#define ICP_CACHE_FREE(args...) \ ++ icp_kmem_cache_free (args) ++ ++#define ICP_CACHE_DESTROY(slab_zone)\ ++{\ ++ if(NULL != slab_zone){\ ++ icp_kmem_cache_destroy(slab_zone);\ ++ slab_zone = NULL;\ ++ }\ ++} ++ ++#endif ++/* ICP_OCF_H_ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_sym.c linux-3.0.4/crypto/ocf/ep80579/icp_sym.c +--- linux-3.0.4.orig/crypto/ocf/ep80579/icp_sym.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/icp_sym.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1153 @@ ++/*************************************************************************** ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++/* ++ * An OCF module that uses the API for Intel® QuickAssist Technology to do the ++ * cryptography. ++ * ++ * This driver requires the ICP Access Library that is available from Intel in ++ * order to operate. ++ */ ++ ++#include "icp_ocf.h" ++ ++/*This is the call back function for all symmetric cryptographic processes. ++ Its main functionality is to free driver crypto operation structure and to ++ call back to OCF*/ ++static void ++icp_ocfDrvSymCallBack(void *callbackTag, ++ CpaStatus status, ++ const CpaCySymOp operationType, ++ void *pOpData, ++ CpaBufferList * pDstBuffer, CpaBoolean verifyResult); ++ ++/*This function is used to extract crypto processing information from the OCF ++ inputs, so as that it may be passed onto LAC*/ ++static int ++icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, ++ struct cryptodesc *crp_desc); ++ ++/*This function checks whether the crp_desc argument pertains to a digest or a ++ cipher operation*/ ++static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc); ++ ++/*This function copies all the passed in session context information and stores ++ it in a LAC context structure*/ ++static int ++icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, ++ CpaCySymSessionSetupData * lacSessCtx); ++ ++/*This function is used to free an OCF->OCF_DRV session object*/ ++static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData); ++ ++/*max IOV buffs supported in a UIO structure*/ ++#define NUM_IOV_SUPPORTED (1) ++ ++/* Name : icp_ocfDrvSymCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the relevant symmetric operation. ++ * ++ * Notes : The callbackTag is a pointer to an icp_drvOpData. This memory ++ * object was passed to LAC for the cryptographic processing and contains all ++ * the relevant information for cleaning up buffer handles etc. so that the ++ * OCF EP80579 Driver portion of this crypto operation can be fully completed. ++ */ ++static void ++icp_ocfDrvSymCallBack(void *callbackTag, ++ CpaStatus status, ++ const CpaCySymOp operationType, ++ void *pOpData, ++ CpaBufferList * pDstBuffer, CpaBoolean verifyResult) ++{ ++ struct cryptop *crp = NULL; ++ struct icp_drvOpData *temp_drvOpData = ++ (struct icp_drvOpData *)callbackTag; ++ uint64_t *tempBasePtr = NULL; ++ uint32_t tempLen = 0; ++ ++ if (NULL == temp_drvOpData) { ++ DPRINTK("%s(): The callback from the LAC component" ++ " has failed due to Null userOpaque data" ++ "(status == %d).\n", __FUNCTION__, status); ++ DPRINTK("%s(): Unable to call OCF back! \n", __FUNCTION__); ++ return; ++ } ++ ++ crp = temp_drvOpData->crp; ++ crp->crp_etype = ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): The callback from the LAC component" ++ " has failed due to Null Symmetric Op data" ++ "(status == %d).\n", __FUNCTION__, status); ++ crp->crp_etype = ECANCELED; ++ crypto_done(crp); ++ return; ++ } ++ ++ if (NULL == pDstBuffer) { ++ DPRINTK("%s(): The callback from the LAC component" ++ " has failed due to Null Dst Bufferlist data" ++ "(status == %d).\n", __FUNCTION__, status); ++ crp->crp_etype = ECANCELED; ++ crypto_done(crp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ ++ if (temp_drvOpData->bufferType == ICP_CRYPTO_F_PACKET_BUF) { ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvBufferListToPacketBuff(pDstBuffer, ++ (icp_packet_buffer_t ++ **) ++ & (crp->crp_buf))) { ++ EPRINTK("%s(): BufferList to SkBuff " ++ "conversion error.\n", __FUNCTION__); ++ crp->crp_etype = EPERM; ++ } ++ } else { ++ icp_ocfDrvBufferListToPtrAndLen(pDstBuffer, ++ (void **)&tempBasePtr, ++ &tempLen); ++ crp->crp_olen = (int)tempLen; ++ } ++ ++ } else { ++ DPRINTK("%s(): The callback from the LAC component has failed" ++ "(status == %d).\n", __FUNCTION__, status); ++ ++ crp->crp_etype = ECANCELED; ++ } ++ ++ if (temp_drvOpData->numBufferListArray > ++ ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { ++ icp_kfree(pDstBuffer->pBuffers); ++ } ++ icp_ocfDrvFreeMetaData(pDstBuffer); ++ ICP_CACHE_FREE(drvOpData_zone, temp_drvOpData); ++ ++ /* Invoke the OCF callback function */ ++ crypto_done(crp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvNewSession ++ * ++ * Description : This function will create a new Driver<->OCF session ++ * ++ * Notes : LAC session registration happens during the first perform call. ++ * That is the first time we know all information about a given session. ++ */ ++int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sid, ++ struct cryptoini *cri) ++{ ++ struct icp_drvSessionData *sessionData = NULL; ++ uint32_t delete_session = 0; ++ ++ /* The SID passed in should be our driver ID. We can return the */ ++ /* local ID (LID) which is a unique identifier which we can use */ ++ /* to differentiate between the encrypt/decrypt LAC session handles */ ++ if (NULL == sid) { ++ EPRINTK("%s(): Invalid input parameters - NULL sid.\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (NULL == cri) { ++ EPRINTK("%s(): Invalid input parameters - NULL cryptoini.\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (icp_ocfDrvDriverId != *sid) { ++ EPRINTK("%s(): Invalid input parameters - bad driver ID\n", ++ __FUNCTION__); ++ EPRINTK("\t sid = 0x08%p \n \t cri = 0x08%p \n", sid, cri); ++ return EINVAL; ++ } ++ ++ sessionData = icp_kmem_cache_zalloc(drvSessionData_zone, ICP_M_NOWAIT); ++ if (NULL == sessionData) { ++ DPRINTK("%s():No memory for Session Data\n", __FUNCTION__); ++ return ENOMEM; ++ } ++ ++ /*ENTER CRITICAL SECTION */ ++ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); ++ /*put this check in the spinlock so no new sessions can be added to the ++ linked list when we are exiting */ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ delete_session++; ++ ++ } else if (NO_OCF_TO_DRV_MAX_SESSIONS != max_sessions) { ++ if (icp_atomic_read(&num_ocf_to_drv_registered_sessions) >= ++ (max_sessions - ++ icp_atomic_read(&lac_session_failed_dereg_count))) { ++ delete_session++; ++ } else { ++ icp_atomic_inc(&num_ocf_to_drv_registered_sessions); ++ /* Add to session data linked list */ ++ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, ++ listNode); ++ } ++ ++ } else if (NO_OCF_TO_DRV_MAX_SESSIONS == max_sessions) { ++ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, ++ listNode); ++ } ++ ++ sessionData->inUse = ICP_SESSION_INITIALISED; ++ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ if (delete_session) { ++ DPRINTK("%s():No Session handles available\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvSessionData_zone, sessionData); ++ return EPERM; ++ } ++ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvAlgorithmSetup(cri, &(sessionData->lacSessCtx))) { ++ DPRINTK("%s():algorithm not supported\n", __FUNCTION__); ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return EINVAL; ++ } ++ ++ if (cri->cri_next) { ++ if (cri->cri_next->cri_next != NULL) { ++ DPRINTK("%s():only two chained algorithms supported\n", ++ __FUNCTION__); ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return EPERM; ++ } ++ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvAlgorithmSetup(cri->cri_next, ++ &(sessionData->lacSessCtx))) { ++ DPRINTK("%s():second algorithm not supported\n", ++ __FUNCTION__); ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return EINVAL; ++ } ++ ++ sessionData->lacSessCtx.symOperation = ++ CPA_CY_SYM_OP_ALGORITHM_CHAINING; ++ } ++ ++ *sid = (uint32_t) sessionData; ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvAlgorithmSetup ++ * ++ * Description : This function builds the session context data from the ++ * information supplied through OCF. Algorithm chain order and whether the ++ * session is Encrypt/Decrypt can only be found out at perform time however, so ++ * the session is registered with LAC at that time. ++ */ ++static int ++icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, ++ CpaCySymSessionSetupData * lacSessCtx) ++{ ++ ++ lacSessCtx->sessionPriority = CPA_CY_PRIORITY_NORMAL; ++ ++ switch (cri->cri_alg) { ++ ++ case CRYPTO_NULL_CBC: ++ DPRINTK("%s(): NULL CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_NULL; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_DES_CBC: ++ DPRINTK("%s(): DES CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_DES_CBC; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_3DES_CBC: ++ DPRINTK("%s(): 3DES CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_3DES_CBC; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_AES_CBC: ++ DPRINTK("%s(): AES CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_AES_CBC; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_ARC4: ++ DPRINTK("%s(): ARC4\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_ARC4; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_SHA1: ++ DPRINTK("%s(): SHA1\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA1_HMAC: ++ DPRINTK("%s(): SHA1_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_SHA2_256: ++ DPRINTK("%s(): SHA256\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA256; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA2_256_HMAC: ++ DPRINTK("%s(): SHA256_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA256; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_SHA2_384: ++ DPRINTK("%s(): SHA384\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA384; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA2_384_HMAC: ++ DPRINTK("%s(): SHA384_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA384; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_SHA2_512: ++ DPRINTK("%s(): SHA512\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA512; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA2_512_HMAC: ++ DPRINTK("%s(): SHA512_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA512; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_MD5: ++ DPRINTK("%s(): MD5\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_MD5_HMAC: ++ DPRINTK("%s(): MD5_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ default: ++ DPRINTK("%s(): ALG Setup FAIL\n", __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvFreeOCFSession ++ * ++ * Description : This function deletes all existing Session data representing ++ * the Cryptographic session established between OCF and this driver. This ++ * also includes freeing the memory allocated for the session context. The ++ * session object is also removed from the session linked list. ++ */ ++static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData) ++{ ++ ++ sessionData->inUse = ICP_SESSION_DEREGISTERED; ++ ++ /*ENTER CRITICAL SECTION */ ++ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ /*If the Driver is exiting, allow that process to ++ handle any deletions */ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ return; ++ } ++ ++ icp_atomic_dec(&num_ocf_to_drv_registered_sessions); ++ ++ ICP_LIST_DEL(sessionData, listNode); ++ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ if (NULL != sessionData->sessHandle) { ++ icp_kfree(sessionData->sessHandle); ++ } ++ ICP_CACHE_FREE(drvSessionData_zone, sessionData); ++} ++ ++/* Name : icp_ocfDrvFreeLACSession ++ * ++ * Description : This attempts to deregister a LAC session. If it fails, the ++ * deregistation retry function is called. ++ */ ++int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid) ++{ ++ CpaCySymSessionCtx sessionToDeregister = NULL; ++ struct icp_drvSessionData *sessionData = NULL; ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ int retval = 0; ++ ++ sessionData = (struct icp_drvSessionData *)CRYPTO_SESID2LID(sid); ++ if (NULL == sessionData) { ++ EPRINTK("%s(): OCF Free session called with Null Session ID.\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ sessionToDeregister = sessionData->sessHandle; ++ ++ if ((ICP_SESSION_INITIALISED != sessionData->inUse) && ++ (ICP_SESSION_RUNNING != sessionData->inUse) && ++ (ICP_SESSION_DEREGISTERED != sessionData->inUse)) { ++ DPRINTK("%s() Session not initialised.\n", __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (ICP_SESSION_RUNNING == sessionData->inUse) { ++ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, ++ sessionToDeregister); ++ if (CPA_STATUS_RETRY == lacStatus) { ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvDeregRetry(&sessionToDeregister)) { ++ /* the retry function increments the ++ dereg failed count */ ++ DPRINTK("%s(): LAC failed to deregister the " ++ "session. (localSessionId= %p)\n", ++ __FUNCTION__, sessionToDeregister); ++ retval = EPERM; ++ } ++ ++ } else if (CPA_STATUS_SUCCESS != lacStatus) { ++ DPRINTK("%s(): LAC failed to deregister the session. " ++ "localSessionId= %p, lacStatus = %d\n", ++ __FUNCTION__, sessionToDeregister, lacStatus); ++ icp_atomic_inc(&lac_session_failed_dereg_count); ++ retval = EPERM; ++ } ++ } else { ++ DPRINTK("%s() Session not registered with LAC.\n", ++ __FUNCTION__); ++ } ++ ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return retval; ++ ++} ++ ++/* Name : icp_ocfDrvAlgCheck ++ * ++ * Description : This function checks whether the cryptodesc argument pertains ++ * to a sym or hash function ++ */ ++static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc) ++{ ++ ++ if (crp_desc->crd_alg == CRYPTO_3DES_CBC || ++ crp_desc->crd_alg == CRYPTO_AES_CBC || ++ crp_desc->crd_alg == CRYPTO_DES_CBC || ++ crp_desc->crd_alg == CRYPTO_NULL_CBC || ++ crp_desc->crd_alg == CRYPTO_ARC4) { ++ return ICP_OCF_DRV_ALG_CIPHER; ++ } ++ ++ return ICP_OCF_DRV_ALG_HASH; ++} ++ ++/* Name : icp_ocfDrvSymProcess ++ * ++ * Description : This function will map symmetric functionality calls from OCF ++ * to the LAC API. It will also allocate memory to store the session context. ++ * ++ * Notes: If it is the first perform call for a given session, then a LAC ++ * session is registered. After the session is registered, no checks as ++ * to whether session paramaters have changed (e.g. alg chain order) are ++ * done. ++ */ ++int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint) ++{ ++ struct icp_drvSessionData *sessionData = NULL; ++ struct icp_drvOpData *drvOpData = NULL; ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ Cpa32U sessionCtxSizeInBytes = 0; ++ ++ if (NULL == crp) { ++ DPRINTK("%s(): Invalid input parameters, cryptop is NULL\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (NULL == crp->crp_desc) { ++ DPRINTK("%s(): Invalid input parameters, no crp_desc attached " ++ "to crp\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ if (NULL == crp->crp_buf) { ++ DPRINTK("%s(): Invalid input parameters, no buffer attached " ++ "to crp\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ crp->crp_etype = EFAULT; ++ return EFAULT; ++ } ++ ++ sessionData = (struct icp_drvSessionData *) ++ (CRYPTO_SESID2LID(crp->crp_sid)); ++ if (NULL == sessionData) { ++ DPRINTK("%s(): Invalid input parameters, Null Session ID \n", ++ __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++/*If we get a request against a deregisted session, cancel operation*/ ++ if (ICP_SESSION_DEREGISTERED == sessionData->inUse) { ++ DPRINTK("%s(): Session ID %d was deregistered \n", ++ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); ++ crp->crp_etype = EFAULT; ++ return EFAULT; ++ } ++ ++/*If none of the session states are set, then the session structure was either ++ not initialised properly or we are reading from a freed memory area (possible ++ due to OCF batch mode not removing queued requests against deregistered ++ sessions*/ ++ if (ICP_SESSION_INITIALISED != sessionData->inUse && ++ ICP_SESSION_RUNNING != sessionData->inUse) { ++ DPRINTK("%s(): Session - ID %d - not properly initialised or " ++ "memory freed back to the kernel \n", ++ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ /*For the below checks, remember error checking is already done in LAC. ++ We're not validating inputs subsequent to registration */ ++ if (sessionData->inUse == ICP_SESSION_INITIALISED) { ++ DPRINTK("%s(): Initialising session\n", __FUNCTION__); ++ ++ if (NULL != crp->crp_desc->crd_next) { ++ if (ICP_OCF_DRV_ALG_CIPHER == ++ icp_ocfDrvAlgCheck(crp->crp_desc)) { ++ ++ sessionData->lacSessCtx.algChainOrder = ++ CPA_CY_SYM_ALG_CHAIN_ORDER_CIPHER_THEN_HASH; ++ ++ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; ++ } else { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; ++ } ++ } else { ++ sessionData->lacSessCtx.algChainOrder = ++ CPA_CY_SYM_ALG_CHAIN_ORDER_HASH_THEN_CIPHER; ++ ++ if (crp->crp_desc->crd_next->crd_flags & ++ CRD_F_ENCRYPT) { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; ++ } else { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; ++ } ++ ++ } ++ ++ } else if (ICP_OCF_DRV_ALG_CIPHER == ++ icp_ocfDrvAlgCheck(crp->crp_desc)) { ++ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; ++ } else { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; ++ } ++ ++ } ++ ++ /*No action required for standalone Auth here */ ++ ++ /* Allocate memory for SymSessionCtx before the Session Registration */ ++ lacStatus = ++ cpaCySymSessionCtxGetSize(CPA_INSTANCE_HANDLE_SINGLE, ++ &(sessionData->lacSessCtx), ++ &sessionCtxSizeInBytes); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): cpaCySymSessionCtxGetSize failed - %d\n", ++ __FUNCTION__, lacStatus); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ sessionData->sessHandle = ++ icp_kmalloc(sessionCtxSizeInBytes, ICP_M_NOWAIT); ++ if (NULL == sessionData->sessHandle) { ++ EPRINTK ++ ("%s(): Failed to get memory for SymSessionCtx\n", ++ __FUNCTION__); ++ crp->crp_etype = ENOMEM; ++ return ENOMEM; ++ } ++ ++ lacStatus = cpaCySymInitSession(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvSymCallBack, ++ &(sessionData->lacSessCtx), ++ sessionData->sessHandle); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): cpaCySymInitSession failed -%d \n", ++ __FUNCTION__, lacStatus); ++ crp->crp_etype = EFAULT; ++ return EFAULT; ++ } ++ ++ sessionData->inUse = ICP_SESSION_RUNNING; ++ } ++ ++ drvOpData = icp_kmem_cache_zalloc(drvOpData_zone, ICP_M_NOWAIT); ++ if (NULL == drvOpData) { ++ EPRINTK("%s():Failed to get memory for drvOpData\n", ++ __FUNCTION__); ++ crp->crp_etype = ENOMEM; ++ return ENOMEM; ++ } ++ ++ drvOpData->lacOpData.pSessionCtx = sessionData->sessHandle; ++ drvOpData->digestSizeInBytes = sessionData->lacSessCtx.hashSetupData. ++ digestResultLenInBytes; ++ drvOpData->crp = crp; ++ ++ /* Set the default buffer list array memory allocation */ ++ drvOpData->srcBuffer.pBuffers = drvOpData->bufferListArray; ++ drvOpData->numBufferListArray = ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS; ++ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->crp_desc)) { ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ if (drvOpData->crp->crp_desc->crd_next != NULL) { ++ if (icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp-> ++ crp_desc->crd_next)) { ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ } ++ ++ /* ++ * Allocate buffer list array memory if the data fragment is more than ++ * the default number (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) and not ++ * calculated already ++ */ ++ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { ++ if (NULL == drvOpData->lacOpData.pDigestResult) { ++ drvOpData->numBufferListArray = ++ icp_ocfDrvGetPacketBuffFrags((icp_packet_buffer_t *) ++ crp->crp_buf); ++ } ++ ++ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < ++ drvOpData->numBufferListArray) { ++ DPRINTK("%s() numBufferListArray more than default\n", ++ __FUNCTION__); ++ drvOpData->srcBuffer.pBuffers = NULL; ++ drvOpData->srcBuffer.pBuffers = ++ icp_kmalloc(drvOpData->numBufferListArray * ++ sizeof(CpaFlatBuffer), ICP_M_NOWAIT); ++ if (NULL == drvOpData->srcBuffer.pBuffers) { ++ EPRINTK("%s() Failed to get memory for " ++ "pBuffers\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvOpData_zone, drvOpData); ++ crp->crp_etype = ENOMEM; ++ return ENOMEM; ++ } ++ } ++ } ++ ++ /* ++ * Check the type of buffer structure we got and convert it into ++ * CpaBufferList format. ++ */ ++ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvPacketBuffToBufferList((icp_packet_buffer_t *) ++ crp->crp_buf, ++ &(drvOpData->srcBuffer))) { ++ EPRINTK("%s():Failed to translate from packet buffer " ++ "to bufferlist\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ drvOpData->bufferType = ICP_CRYPTO_F_PACKET_BUF; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ /* OCF only supports IOV of one entry. */ ++ if (NUM_IOV_SUPPORTED == ++ ((struct uio *)(crp->crp_buf))->uio_iovcnt) { ++ ++ icp_ocfDrvPtrAndLenToBufferList(((struct uio *)(crp-> ++ crp_buf))-> ++ uio_iov[0].iov_base, ++ ((struct uio *)(crp-> ++ crp_buf))-> ++ uio_iov[0].iov_len, ++ &(drvOpData-> ++ srcBuffer)); ++ ++ drvOpData->bufferType = CRYPTO_F_IOV; ++ ++ } else { ++ DPRINTK("%s():Unable to handle IOVs with lengths of " ++ "greater than one!\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ } else { ++ icp_ocfDrvPtrAndLenToBufferList(crp->crp_buf, ++ crp->crp_ilen, ++ &(drvOpData->srcBuffer)); ++ ++ drvOpData->bufferType = CRYPTO_BUF_CONTIG; ++ } ++ ++ /* Allocate srcBuffer's private meta data */ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvAllocMetaData(&(drvOpData->srcBuffer), drvOpData)) { ++ EPRINTK("%s() icp_ocfDrvAllocMetaData failed\n", __FUNCTION__); ++ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ /* Perform "in-place" crypto operation */ ++ lacStatus = cpaCySymPerformOp(CPA_INSTANCE_HANDLE_SINGLE, ++ (void *)drvOpData, ++ &(drvOpData->lacOpData), ++ &(drvOpData->srcBuffer), ++ &(drvOpData->srcBuffer), ++ &(drvOpData->verifyResult)); ++ if (CPA_STATUS_RETRY == lacStatus) { ++ DPRINTK("%s(): cpaCySymPerformOp retry, lacStatus = %d\n", ++ __FUNCTION__, lacStatus); ++ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); ++ crp->crp_etype = ERESTART; ++ goto err; ++ } ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): cpaCySymPerformOp failed, lacStatus = %d\n", ++ __FUNCTION__, lacStatus); ++ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ return 0; //OCF success status value ++ ++ err: ++ if (drvOpData->numBufferListArray > ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { ++ icp_kfree(drvOpData->srcBuffer.pBuffers); ++ } ++ icp_ocfDrvFreeMetaData(&(drvOpData->srcBuffer)); ++ ICP_CACHE_FREE(drvOpData_zone, drvOpData); ++ ++ return crp->crp_etype; ++} ++ ++/* Name : icp_ocfDrvProcessDataSetup ++ * ++ * Description : This function will setup all the cryptographic operation data ++ * that is required by LAC to execute the operation. ++ */ ++static int icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, ++ struct cryptodesc *crp_desc) ++{ ++ CpaCyRandGenOpData randGenOpData; ++ CpaFlatBuffer randData; ++ ++ drvOpData->lacOpData.packetType = CPA_CY_SYM_PACKET_TYPE_FULL; ++ ++ /* Convert from the cryptop to the ICP LAC crypto parameters */ ++ switch (crp_desc->crd_alg) { ++ case CRYPTO_NULL_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = NULL_BLOCK_LEN; ++ break; ++ case CRYPTO_DES_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = DES_BLOCK_LEN; ++ break; ++ case CRYPTO_3DES_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = DES3_BLOCK_LEN; ++ break; ++ case CRYPTO_ARC4: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = ARC4_COUNTER_LEN; ++ break; ++ case CRYPTO_AES_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = RIJNDAEL128_BLOCK_LEN; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ case CRYPTO_SHA2_256: ++ case CRYPTO_SHA2_256_HMAC: ++ case CRYPTO_SHA2_384: ++ case CRYPTO_SHA2_384_HMAC: ++ case CRYPTO_SHA2_512: ++ case CRYPTO_SHA2_512_HMAC: ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ drvOpData->lacOpData. ++ hashStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToHashInBytes = crp_desc->crd_len; ++ drvOpData->lacOpData. ++ pDigestResult = ++ icp_ocfDrvDigestPointerFind(drvOpData, crp_desc); ++ ++ if (NULL == drvOpData->lacOpData.pDigestResult) { ++ DPRINTK("%s(): ERROR - could not calculate " ++ "Digest Result memory address\n", __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ drvOpData->lacOpData.digestVerify = CPA_FALSE; ++ break; ++ default: ++ DPRINTK("%s(): Crypto process error - algorithm not " ++ "found \n", __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ /* Figure out what the IV is supposed to be */ ++ if ((crp_desc->crd_alg == CRYPTO_DES_CBC) || ++ (crp_desc->crd_alg == CRYPTO_3DES_CBC) || ++ (crp_desc->crd_alg == CRYPTO_AES_CBC)) { ++ /*ARC4 doesn't use an IV */ ++ if (crp_desc->crd_flags & CRD_F_IV_EXPLICIT) { ++ /* Explicit IV provided to OCF */ ++ drvOpData->lacOpData.pIv = crp_desc->crd_iv; ++ } else { ++ /* IV is not explicitly provided to OCF */ ++ ++ /* Point the LAC OP Data IV pointer to our allocated ++ storage location for this session. */ ++ drvOpData->lacOpData.pIv = drvOpData->ivData; ++ ++ if ((crp_desc->crd_flags & CRD_F_ENCRYPT) && ++ ((crp_desc->crd_flags & CRD_F_IV_PRESENT) == 0)) { ++ ++ /* Encrypting - need to create IV */ ++ randGenOpData.generateBits = CPA_TRUE; ++ randGenOpData.lenInBytes = MAX_IV_LEN_IN_BYTES; ++ ++ icp_ocfDrvPtrAndLenToFlatBuffer((Cpa8U *) ++ drvOpData-> ++ ivData, ++ MAX_IV_LEN_IN_BYTES, ++ &randData); ++ ++ if (CPA_STATUS_SUCCESS != ++ cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, ++ NULL, NULL, ++ &randGenOpData, &randData)) { ++ DPRINTK("%s(): ERROR - Failed to" ++ " generate" ++ " Initialisation Vector\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ crypto_copyback(drvOpData->crp-> ++ crp_flags, ++ drvOpData->crp->crp_buf, ++ crp_desc->crd_inject, ++ drvOpData->lacOpData. ++ ivLenInBytes, ++ (caddr_t) (drvOpData->lacOpData. ++ pIv)); ++ } else { ++ /* Reading IV from buffer */ ++ crypto_copydata(drvOpData->crp-> ++ crp_flags, ++ drvOpData->crp->crp_buf, ++ crp_desc->crd_inject, ++ drvOpData->lacOpData. ++ ivLenInBytes, ++ (caddr_t) (drvOpData->lacOpData. ++ pIv)); ++ } ++ ++ } ++ ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvDigestPointerFind ++ * ++ * Description : This function is used to find the memory address of where the ++ * digest information shall be stored in. Input buffer types are an skbuff, iov ++ * or flat buffer. The address is found using the buffer data start address and ++ * an offset. ++ * ++ * Note: In the case of a linux skbuff, the digest address may exist within ++ * a memory space linked to from the start buffer. These linked memory spaces ++ * must be traversed by the data length offset in order to find the digest start ++ * address. Whether there is enough space for the digest must also be checked. ++ */ ++uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData * drvOpData, ++ struct cryptodesc * crp_desc) ++{ ++ ++ int offsetInBytes = crp_desc->crd_inject; ++ uint32_t digestSizeInBytes = drvOpData->digestSizeInBytes; ++ uint8_t *flat_buffer_base = NULL; ++ int flat_buffer_length = 0; ++ ++ if (drvOpData->crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { ++ ++ return icp_ocfDrvPacketBufferDigestPointerFind(drvOpData, ++ offsetInBytes, ++ digestSizeInBytes); ++ ++ } else { ++ /* IOV or flat buffer */ ++ if (drvOpData->crp->crp_flags & CRYPTO_F_IOV) { ++ /*single IOV check has already been done */ ++ flat_buffer_base = ((struct uio *) ++ (drvOpData->crp->crp_buf))-> ++ uio_iov[0].iov_base; ++ flat_buffer_length = ((struct uio *) ++ (drvOpData->crp->crp_buf))-> ++ uio_iov[0].iov_len; ++ } else { ++ flat_buffer_base = (uint8_t *) drvOpData->crp->crp_buf; ++ flat_buffer_length = drvOpData->crp->crp_ilen; ++ } ++ ++ if (flat_buffer_length < (offsetInBytes + digestSizeInBytes)) { ++ DPRINTK("%s() Not enough space for Digest " ++ "(IOV/Flat Buffer) \n", __FUNCTION__); ++ return NULL; ++ } else { ++ return (uint8_t *) (flat_buffer_base + offsetInBytes); ++ } ++ } ++ DPRINTK("%s() Should not reach this point\n", __FUNCTION__); ++ return NULL; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/linux_2.6_kernel_space.mk linux-3.0.4/crypto/ocf/ep80579/linux_2.6_kernel_space.mk +--- linux-3.0.4.orig/crypto/ocf/ep80579/linux_2.6_kernel_space.mk 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/linux_2.6_kernel_space.mk 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,69 @@ ++################### ++# @par ++# This file is provided under a dual BSD/GPLv2 license. When using or ++# redistributing this file, you may do so under either license. ++# ++# GPL LICENSE SUMMARY ++# ++# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of version 2 of the GNU General Public License as ++# published by the Free Software Foundation. ++# ++# This program is distributed in the hope that it will be useful, but ++# WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++# General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++# The full GNU General Public License is included in this distribution ++# in the file called LICENSE.GPL. ++# ++# Contact Information: ++# Intel Corporation ++# ++# BSD LICENSE ++# ++# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. ++# All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of Intel Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++# ++# ++# version: Security.L.1.0.130 ++################### ++ ++#specific include directories in kernel space ++INCLUDES+=#e.g. -I$(OSAL_DIR)/include \ ++ ++#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include ++EXTRA_CFLAGS += $(INCLUDES) -O2 -Wall ++EXTRA_LDFLAGS +=-whole-archive ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/Makefile linux-3.0.4/crypto/ocf/hifn/Makefile +--- linux-3.0.4.orig/crypto/ocf/hifn/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,13 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_HIFN) += hifn7751.o ++obj-$(CONFIG_OCF_HIFNHIPP) += hifnHIPP.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifn7751.c linux-3.0.4/crypto/ocf/hifn/hifn7751.c +--- linux-3.0.4.orig/crypto/ocf/hifn/hifn7751.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/hifn7751.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,2954 @@ ++/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ ++ ++/*- ++ * Invertex AEON / Hifn 7751 driver ++ * Copyright (c) 1999 Invertex Inc. All rights reserved. ++ * Copyright (c) 1999 Theo de Raadt ++ * Copyright (c) 2000-2001 Network Security Technologies, Inc. ++ * http://www.netsec.net ++ * Copyright (c) 2003 Hifn Inc. ++ * ++ * This driver is based on a previous driver by Invertex, for which they ++ * requested: Please send any comments, feedback, bug-fixes, or feature ++ * requests to software@invertex.com. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ * ++__FBSDID("$FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.40 2007/03/21 03:42:49 sam Exp $"); ++ */ ++ ++/* ++ * Driver for various Hifn encryption processors. ++ */ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#if 1 ++#define DPRINTF(a...) if (hifn_debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_dev) : "hifn"); \ ++ printk(a); \ ++ } else ++#else ++#define DPRINTF(a...) ++#endif ++ ++static inline int ++pci_get_revid(struct pci_dev *dev) ++{ ++ u8 rid = 0; ++ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); ++ return rid; ++} ++ ++static struct hifn_stats hifnstats; ++ ++#define debug hifn_debug ++int hifn_debug = 0; ++module_param(hifn_debug, int, 0644); ++MODULE_PARM_DESC(hifn_debug, "Enable debug"); ++ ++int hifn_maxbatch = 1; ++module_param(hifn_maxbatch, int, 0644); ++MODULE_PARM_DESC(hifn_maxbatch, "max ops to batch w/o interrupt"); ++ ++int hifn_cache_linesize = 0x10; ++module_param(hifn_cache_linesize, int, 0444); ++MODULE_PARM_DESC(hifn_cache_linesize, "PCI config cache line size"); ++ ++#ifdef MODULE_PARM ++char *hifn_pllconfig = NULL; ++MODULE_PARM(hifn_pllconfig, "s"); ++#else ++char hifn_pllconfig[32]; /* This setting is RO after loading */ ++module_param_string(hifn_pllconfig, hifn_pllconfig, 32, 0444); ++#endif ++MODULE_PARM_DESC(hifn_pllconfig, "PLL config, ie., pci66, ext33, ..."); ++ ++#ifdef HIFN_VULCANDEV ++#include ++#include ++ ++static struct cdevsw vulcanpk_cdevsw; /* forward declaration */ ++#endif ++ ++/* ++ * Prototypes and count for the pci_device structure ++ */ ++static int hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent); ++static void hifn_remove(struct pci_dev *dev); ++ ++static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int hifn_freesession(device_t, u_int64_t); ++static int hifn_process(device_t, struct cryptop *, int); ++ ++static device_method_t hifn_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, hifn_newsession), ++ DEVMETHOD(cryptodev_freesession,hifn_freesession), ++ DEVMETHOD(cryptodev_process, hifn_process), ++}; ++ ++static void hifn_reset_board(struct hifn_softc *, int); ++static void hifn_reset_puc(struct hifn_softc *); ++static void hifn_puc_wait(struct hifn_softc *); ++static int hifn_enable_crypto(struct hifn_softc *); ++static void hifn_set_retry(struct hifn_softc *sc); ++static void hifn_init_dma(struct hifn_softc *); ++static void hifn_init_pci_registers(struct hifn_softc *); ++static int hifn_sramsize(struct hifn_softc *); ++static int hifn_dramsize(struct hifn_softc *); ++static int hifn_ramtype(struct hifn_softc *); ++static void hifn_sessions(struct hifn_softc *); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++static irqreturn_t hifn_intr(int irq, void *arg); ++#else ++static irqreturn_t hifn_intr(int irq, void *arg, struct pt_regs *regs); ++#endif ++static u_int hifn_write_command(struct hifn_command *, u_int8_t *); ++static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); ++static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); ++static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); ++static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); ++static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); ++static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); ++static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); ++static int hifn_init_pubrng(struct hifn_softc *); ++static void hifn_tick(unsigned long arg); ++static void hifn_abort(struct hifn_softc *); ++static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); ++ ++static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); ++static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++static int hifn_read_random(void *arg, u_int32_t *buf, int len); ++#endif ++ ++#define HIFN_MAX_CHIPS 8 ++static struct hifn_softc *hifn_chip_idx[HIFN_MAX_CHIPS]; ++ ++static __inline u_int32_t ++READ_REG_0(struct hifn_softc *sc, bus_size_t reg) ++{ ++ u_int32_t v = readl(sc->sc_bar0 + reg); ++ sc->sc_bar0_lastreg = (bus_size_t) -1; ++ return (v); ++} ++#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) ++ ++static __inline u_int32_t ++READ_REG_1(struct hifn_softc *sc, bus_size_t reg) ++{ ++ u_int32_t v = readl(sc->sc_bar1 + reg); ++ sc->sc_bar1_lastreg = (bus_size_t) -1; ++ return (v); ++} ++#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) ++ ++/* ++ * map in a given buffer (great on some arches :-) ++ */ ++ ++static int ++pci_map_uio(struct hifn_softc *sc, struct hifn_operand *buf, struct uio *uio) ++{ ++ struct iovec *iov = uio->uio_iov; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf->mapsize = 0; ++ for (buf->nsegs = 0; buf->nsegs < uio->uio_iovcnt; ) { ++ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, ++ iov->iov_base, iov->iov_len, ++ PCI_DMA_BIDIRECTIONAL); ++ buf->segs[buf->nsegs].ds_len = iov->iov_len; ++ buf->mapsize += iov->iov_len; ++ iov++; ++ buf->nsegs++; ++ } ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++/* ++ * map in a given sk_buff ++ */ ++ ++static int ++pci_map_skb(struct hifn_softc *sc,struct hifn_operand *buf,struct sk_buff *skb) ++{ ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf->mapsize = 0; ++ ++ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, ++ skb->data, skb_headlen(skb), PCI_DMA_BIDIRECTIONAL); ++ buf->segs[0].ds_len = skb_headlen(skb); ++ buf->mapsize += buf->segs[0].ds_len; ++ ++ buf->nsegs = 1; ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; ) { ++ buf->segs[buf->nsegs].ds_len = skb_shinfo(skb)->frags[i].size; ++ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, ++ page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ buf->segs[buf->nsegs].ds_len, PCI_DMA_BIDIRECTIONAL); ++ buf->mapsize += buf->segs[buf->nsegs].ds_len; ++ buf->nsegs++; ++ } ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++/* ++ * map in a given contiguous buffer ++ */ ++ ++static int ++pci_map_buf(struct hifn_softc *sc,struct hifn_operand *buf, void *b, int len) ++{ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf->mapsize = 0; ++ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, ++ b, len, PCI_DMA_BIDIRECTIONAL); ++ buf->segs[0].ds_len = len; ++ buf->mapsize += buf->segs[0].ds_len; ++ buf->nsegs = 1; ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++#if 0 /* not needed at this time */ ++static void ++pci_sync_iov(struct hifn_softc *sc, struct hifn_operand *buf) ++{ ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ for (i = 0; i < buf->nsegs; i++) ++ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); ++} ++#endif ++ ++static void ++pci_unmap_buf(struct hifn_softc *sc, struct hifn_operand *buf) ++{ ++ int i; ++ DPRINTF("%s()\n", __FUNCTION__); ++ for (i = 0; i < buf->nsegs; i++) { ++ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); ++ buf->segs[i].ds_addr = 0; ++ buf->segs[i].ds_len = 0; ++ } ++ buf->nsegs = 0; ++ buf->mapsize = 0; ++ buf->map = 0; ++} ++ ++static const char* ++hifn_partname(struct hifn_softc *sc) ++{ ++ /* XXX sprintf numbers when not decoded */ ++ switch (pci_get_vendor(sc->sc_pcidev)) { ++ case PCI_VENDOR_HIFN: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; ++ case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; ++ case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; ++ case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; ++ case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; ++ case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; ++ } ++ return "Hifn unknown-part"; ++ case PCI_VENDOR_INVERTEX: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; ++ } ++ return "Invertex unknown-part"; ++ case PCI_VENDOR_NETSEC: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; ++ } ++ return "NetSec unknown-part"; ++ } ++ return "Unknown-vendor unknown-part"; ++} ++ ++static u_int ++checkmaxmin(struct pci_dev *dev, const char *what, u_int v, u_int min, u_int max) ++{ ++ struct hifn_softc *sc = pci_get_drvdata(dev); ++ if (v > max) { ++ device_printf(sc->sc_dev, "Warning, %s %u out of range, " ++ "using max %u\n", what, v, max); ++ v = max; ++ } else if (v < min) { ++ device_printf(sc->sc_dev, "Warning, %s %u out of range, " ++ "using min %u\n", what, v, min); ++ v = min; ++ } ++ return v; ++} ++ ++/* ++ * Select PLL configuration for 795x parts. This is complicated in ++ * that we cannot determine the optimal parameters without user input. ++ * The reference clock is derived from an external clock through a ++ * multiplier. The external clock is either the host bus (i.e. PCI) ++ * or an external clock generator. When using the PCI bus we assume ++ * the clock is either 33 or 66 MHz; for an external source we cannot ++ * tell the speed. ++ * ++ * PLL configuration is done with a string: "pci" for PCI bus, or "ext" ++ * for an external source, followed by the frequency. We calculate ++ * the appropriate multiplier and PLL register contents accordingly. ++ * When no configuration is given we default to "pci66" since that ++ * always will allow the card to work. If a card is using the PCI ++ * bus clock and in a 33MHz slot then it will be operating at half ++ * speed until the correct information is provided. ++ * ++ * We use a default setting of "ext66" because according to Mike Ham ++ * of HiFn, almost every board in existence has an external crystal ++ * populated at 66Mhz. Using PCI can be a problem on modern motherboards, ++ * because PCI33 can have clocks from 0 to 33Mhz, and some have ++ * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. ++ */ ++static void ++hifn_getpllconfig(struct pci_dev *dev, u_int *pll) ++{ ++ const char *pllspec = hifn_pllconfig; ++ u_int freq, mul, fl, fh; ++ u_int32_t pllconfig; ++ char *nxt; ++ ++ if (pllspec == NULL) ++ pllspec = "ext66"; ++ fl = 33, fh = 66; ++ pllconfig = 0; ++ if (strncmp(pllspec, "ext", 3) == 0) { ++ pllspec += 3; ++ pllconfig |= HIFN_PLL_REF_SEL; ++ switch (pci_get_device(dev)) { ++ case PCI_PRODUCT_HIFN_7955: ++ case PCI_PRODUCT_HIFN_7956: ++ fl = 20, fh = 100; ++ break; ++#ifdef notyet ++ case PCI_PRODUCT_HIFN_7954: ++ fl = 20, fh = 66; ++ break; ++#endif ++ } ++ } else if (strncmp(pllspec, "pci", 3) == 0) ++ pllspec += 3; ++ freq = strtoul(pllspec, &nxt, 10); ++ if (nxt == pllspec) ++ freq = 66; ++ else ++ freq = checkmaxmin(dev, "frequency", freq, fl, fh); ++ /* ++ * Calculate multiplier. We target a Fck of 266 MHz, ++ * allowing only even values, possibly rounded down. ++ * Multipliers > 8 must set the charge pump current. ++ */ ++ mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); ++ pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; ++ if (mul > 8) ++ pllconfig |= HIFN_PLL_IS; ++ *pll = pllconfig; ++} ++ ++/* ++ * Attach an interface that successfully probed. ++ */ ++static int ++hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent) ++{ ++ struct hifn_softc *sc = NULL; ++ char rbase; ++ u_int16_t ena, rev; ++ int rseg, rc; ++ unsigned long mem_start, mem_len; ++ static int num_chips = 0; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (pci_enable_device(dev) < 0) ++ return(-ENODEV); ++ ++ if (pci_set_mwi(dev)) ++ return(-ENODEV); ++ ++ if (!dev->irq) { ++ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); ++ pci_disable_device(dev); ++ return(-ENODEV); ++ } ++ ++ sc = (struct hifn_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, "hifn", num_chips, hifn_methods); ++ ++ sc->sc_pcidev = dev; ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++ sc->sc_num = num_chips++; ++ if (sc->sc_num < HIFN_MAX_CHIPS) ++ hifn_chip_idx[sc->sc_num] = sc; ++ ++ pci_set_drvdata(sc->sc_pcidev, sc); ++ ++ spin_lock_init(&sc->sc_mtx); ++ ++ /* XXX handle power management */ ++ ++ /* ++ * The 7951 and 795x have a random number generator and ++ * public key support; note this. ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && ++ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) ++ sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; ++ /* ++ * The 7811 has a random number generator and ++ * we also note it's identity 'cuz of some quirks. ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) ++ sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; ++ ++ /* ++ * The 795x parts support AES. ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && ++ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { ++ sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; ++ /* ++ * Select PLL configuration. This depends on the ++ * bus and board design and must be manually configured ++ * if the default setting is unacceptable. ++ */ ++ hifn_getpllconfig(dev, &sc->sc_pllconfig); ++ } ++ ++ /* ++ * Setup PCI resources. Note that we record the bus ++ * tag and handle for each register mapping, this is ++ * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, ++ * and WRITE_REG_1 macros throughout the driver. ++ */ ++ mem_start = pci_resource_start(sc->sc_pcidev, 0); ++ mem_len = pci_resource_len(sc->sc_pcidev, 0); ++ sc->sc_bar0 = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_bar0) { ++ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 0); ++ goto fail; ++ } ++ sc->sc_bar0_lastreg = (bus_size_t) -1; ++ ++ mem_start = pci_resource_start(sc->sc_pcidev, 1); ++ mem_len = pci_resource_len(sc->sc_pcidev, 1); ++ sc->sc_bar1 = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_bar1) { ++ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 1); ++ goto fail; ++ } ++ sc->sc_bar1_lastreg = (bus_size_t) -1; ++ ++ /* fix up the bus size */ ++ if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); ++ goto fail; ++ } ++ if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, ++ "No usable consistent DMA configuration, aborting.\n"); ++ goto fail; ++ } ++ ++ hifn_set_retry(sc); ++ ++ /* ++ * Setup the area where the Hifn DMA's descriptors ++ * and associated data structures. ++ */ ++ sc->sc_dma = (struct hifn_dma *) pci_alloc_consistent(dev, ++ sizeof(*sc->sc_dma), ++ &sc->sc_dma_physaddr); ++ if (!sc->sc_dma) { ++ device_printf(sc->sc_dev, "cannot alloc sc_dma\n"); ++ goto fail; ++ } ++ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); ++ ++ /* ++ * Reset the board and do the ``secret handshake'' ++ * to enable the crypto support. Then complete the ++ * initialization procedure by setting up the interrupt ++ * and hooking in to the system crypto support so we'll ++ * get used for system services like the crypto device, ++ * IPsec, RNG device, etc. ++ */ ++ hifn_reset_board(sc, 0); ++ ++ if (hifn_enable_crypto(sc) != 0) { ++ device_printf(sc->sc_dev, "crypto enabling failed\n"); ++ goto fail; ++ } ++ hifn_reset_puc(sc); ++ ++ hifn_init_dma(sc); ++ hifn_init_pci_registers(sc); ++ ++ pci_set_master(sc->sc_pcidev); ++ ++ /* XXX can't dynamically determine ram type for 795x; force dram */ ++ if (sc->sc_flags & HIFN_IS_7956) ++ sc->sc_drammodel = 1; ++ else if (hifn_ramtype(sc)) ++ goto fail; ++ ++ if (sc->sc_drammodel == 0) ++ hifn_sramsize(sc); ++ else ++ hifn_dramsize(sc); ++ ++ /* ++ * Workaround for NetSec 7751 rev A: half ram size because two ++ * of the address lines were left floating ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && ++ pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && ++ pci_get_revid(dev) == 0x61) /*XXX???*/ ++ sc->sc_ramsize >>= 1; ++ ++ /* ++ * Arrange the interrupt line. ++ */ ++ rc = request_irq(dev->irq, hifn_intr, IRQF_SHARED, "hifn", sc); ++ if (rc) { ++ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); ++ goto fail; ++ } ++ sc->sc_irq = dev->irq; ++ ++ hifn_sessions(sc); ++ ++ /* ++ * NB: Keep only the low 16 bits; this masks the chip id ++ * from the 7951. ++ */ ++ rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; ++ ++ rseg = sc->sc_ramsize / 1024; ++ rbase = 'K'; ++ if (sc->sc_ramsize >= (1024 * 1024)) { ++ rbase = 'M'; ++ rseg /= 1024; ++ } ++ device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", ++ hifn_partname(sc), rev, ++ rseg, rbase, sc->sc_drammodel ? 'd' : 's'); ++ if (sc->sc_flags & HIFN_IS_7956) ++ printf(", pll=0x%x<%s clk, %ux mult>", ++ sc->sc_pllconfig, ++ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", ++ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); ++ printf("\n"); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ goto fail; ++ } ++ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ++ READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); ++ ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; ++ ++ switch (ena) { ++ case HIFN_PUSTAT_ENA_2: ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); ++ if (sc->sc_flags & HIFN_HAS_AES) ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ /*FALLTHROUGH*/ ++ case HIFN_PUSTAT_ENA_1: ++ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ break; ++ } ++ ++ if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) ++ hifn_init_pubrng(sc); ++ ++ init_timer(&sc->sc_tickto); ++ sc->sc_tickto.function = hifn_tick; ++ sc->sc_tickto.data = (unsigned long) sc->sc_num; ++ mod_timer(&sc->sc_tickto, jiffies + HZ); ++ ++ return (0); ++ ++fail: ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_dma) { ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ pci_free_consistent(sc->sc_pcidev, ++ sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++ } ++ kfree(sc); ++ return (-ENXIO); ++} ++ ++/* ++ * Detach an interface that successfully probed. ++ */ ++static void ++hifn_remove(struct pci_dev *dev) ++{ ++ struct hifn_softc *sc = pci_get_drvdata(dev); ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); ++ ++ /* disable interrupts */ ++ HIFN_LOCK(sc); ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); ++ HIFN_UNLOCK(sc); ++ ++ /*XXX other resources */ ++ del_timer_sync(&sc->sc_tickto); ++ ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ crypto_unregister_all(sc->sc_cid); ++ ++ free_irq(sc->sc_irq, sc); ++ ++ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++} ++ ++ ++static int ++hifn_init_pubrng(struct hifn_softc *sc) ++{ ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if ((sc->sc_flags & HIFN_IS_7811) == 0) { ++ /* Reset 7951 public key/rng engine */ ++ WRITE_REG_1(sc, HIFN_1_PUB_RESET, ++ READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); ++ ++ for (i = 0; i < 100; i++) { ++ DELAY(1000); ++ if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & ++ HIFN_PUBRST_RESET) == 0) ++ break; ++ } ++ ++ if (i == 100) { ++ device_printf(sc->sc_dev, "public key init failed\n"); ++ return (1); ++ } ++ } ++ ++ /* Enable the rng, if available */ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ if (sc->sc_flags & HIFN_HAS_RNG) { ++ if (sc->sc_flags & HIFN_IS_7811) { ++ u_int32_t r; ++ r = READ_REG_1(sc, HIFN_1_7811_RNGENA); ++ if (r & HIFN_7811_RNGENA_ENA) { ++ r &= ~HIFN_7811_RNGENA_ENA; ++ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); ++ } ++ WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, ++ HIFN_7811_RNGCFG_DEFL); ++ r |= HIFN_7811_RNGENA_ENA; ++ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); ++ } else ++ WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, ++ READ_REG_1(sc, HIFN_1_RNG_CONFIG) | ++ HIFN_RNGCFG_ENA); ++ ++ sc->sc_rngfirst = 1; ++ crypto_rregister(sc->sc_cid, hifn_read_random, sc); ++ } ++#endif ++ ++ /* Enable public key engine, if available */ ++ if (sc->sc_flags & HIFN_HAS_PUBLIC) { ++ WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); ++ sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++#ifdef HIFN_VULCANDEV ++ sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, ++ UID_ROOT, GID_WHEEL, 0666, ++ "vulcanpk"); ++ sc->sc_pkdev->si_drv1 = sc; ++#endif ++ } ++ ++ return (0); ++} ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++static int ++hifn_read_random(void *arg, u_int32_t *buf, int len) ++{ ++ struct hifn_softc *sc = (struct hifn_softc *) arg; ++ u_int32_t sts; ++ int i, rc = 0; ++ ++ if (len <= 0) ++ return rc; ++ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ /* ONLY VALID ON 7811!!!! */ ++ for (i = 0; i < 5; i++) { ++ sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); ++ if (sts & HIFN_7811_RNGSTS_UFL) { ++ device_printf(sc->sc_dev, ++ "RNG underflow: disabling\n"); ++ /* DAVIDM perhaps return -1 */ ++ break; ++ } ++ if ((sts & HIFN_7811_RNGSTS_RDY) == 0) ++ break; ++ ++ /* ++ * There are at least two words in the RNG FIFO ++ * at this point. ++ */ ++ if (rc < len) ++ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); ++ if (rc < len) ++ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); ++ } ++ } else ++ buf[rc++] = READ_REG_1(sc, HIFN_1_RNG_DATA); ++ ++ /* NB: discard first data read */ ++ if (sc->sc_rngfirst) { ++ sc->sc_rngfirst = 0; ++ rc = 0; ++ } ++ ++ return(rc); ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++static void ++hifn_puc_wait(struct hifn_softc *sc) ++{ ++ int i; ++ int reg = HIFN_0_PUCTRL; ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ reg = HIFN_0_PUCTRL2; ++ } ++ ++ for (i = 5000; i > 0; i--) { ++ DELAY(1); ++ if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) ++ break; ++ } ++ if (!i) ++ device_printf(sc->sc_dev, "proc unit did not reset(0x%x)\n", ++ READ_REG_0(sc, HIFN_0_PUCTRL)); ++} ++ ++/* ++ * Reset the processing unit. ++ */ ++static void ++hifn_reset_puc(struct hifn_softc *sc) ++{ ++ /* Reset processing unit */ ++ int reg = HIFN_0_PUCTRL; ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ reg = HIFN_0_PUCTRL2; ++ } ++ WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); ++ ++ hifn_puc_wait(sc); ++} ++ ++/* ++ * Set the Retry and TRDY registers; note that we set them to ++ * zero because the 7811 locks up when forced to retry (section ++ * 3.6 of "Specification Update SU-0014-04". Not clear if we ++ * should do this for all Hifn parts, but it doesn't seem to hurt. ++ */ ++static void ++hifn_set_retry(struct hifn_softc *sc) ++{ ++ DPRINTF("%s()\n", __FUNCTION__); ++ /* NB: RETRY only responds to 8-bit reads/writes */ ++ pci_write_config_byte(sc->sc_pcidev, HIFN_RETRY_TIMEOUT, 0); ++ pci_write_config_byte(sc->sc_pcidev, HIFN_TRDY_TIMEOUT, 0); ++ /* piggy back the cache line setting here */ ++ pci_write_config_byte(sc->sc_pcidev, PCI_CACHE_LINE_SIZE, hifn_cache_linesize); ++} ++ ++/* ++ * Resets the board. Values in the regesters are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++static void ++hifn_reset_board(struct hifn_softc *sc, int full) ++{ ++ u_int32_t reg; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ /* ++ * Set polling in the DMA configuration register to zero. 0x7 avoids ++ * resetting the board and zeros out the other fields. ++ */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ /* ++ * Now that polling has been disabled, we have to wait 1 ms ++ * before resetting the board. ++ */ ++ DELAY(1000); ++ ++ /* Reset the DMA unit */ ++ if (full) { ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); ++ DELAY(1000); ++ } else { ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, ++ HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); ++ hifn_reset_puc(sc); ++ } ++ ++ KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); ++ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); ++ ++ /* Bring dma unit out of reset */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ hifn_puc_wait(sc); ++ hifn_set_retry(sc); ++ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ for (reg = 0; reg < 1000; reg++) { ++ if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & ++ HIFN_MIPSRST_CRAMINIT) ++ break; ++ DELAY(1000); ++ } ++ if (reg == 1000) ++ device_printf(sc->sc_dev, ": cram init timeout\n"); ++ } else { ++ /* set up DMA configuration register #2 */ ++ /* turn off all PK and BAR0 swaps */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, ++ (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| ++ (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| ++ (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| ++ (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); ++ } ++} ++ ++static u_int32_t ++hifn_next_signature(u_int32_t a, u_int cnt) ++{ ++ int i; ++ u_int32_t v; ++ ++ for (i = 0; i < cnt; i++) { ++ ++ /* get the parity */ ++ v = a & 0x80080125; ++ v ^= v >> 16; ++ v ^= v >> 8; ++ v ^= v >> 4; ++ v ^= v >> 2; ++ v ^= v >> 1; ++ ++ a = (v & 1) ^ (a << 1); ++ } ++ ++ return a; ++} ++ ++ ++/* ++ * Checks to see if crypto is already enabled. If crypto isn't enable, ++ * "hifn_enable_crypto" is called to enable it. The check is important, ++ * as enabling crypto twice will lock the board. ++ */ ++static int ++hifn_enable_crypto(struct hifn_softc *sc) ++{ ++ u_int32_t dmacfg, ramcfg, encl, addr, i; ++ char offtbl[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00 }; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); ++ dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); ++ ++ /* ++ * The RAM config register's encrypt level bit needs to be set before ++ * every read performed on the encryption level register. ++ */ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); ++ ++ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; ++ ++ /* ++ * Make sure we don't re-unlock. Two unlocks kills chip until the ++ * next reboot. ++ */ ++ if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, ++ "Strong crypto already enabled!\n"); ++#endif ++ goto report; ++ } ++ ++ if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, ++ "Unknown encryption level 0x%x\n", encl); ++#endif ++ return 1; ++ } ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | ++ HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ DELAY(1000); ++ addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); ++ DELAY(1000); ++ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); ++ DELAY(1000); ++ ++ for (i = 0; i <= 12; i++) { ++ addr = hifn_next_signature(addr, offtbl[i] + 0x101); ++ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); ++ ++ DELAY(1000); ++ } ++ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); ++ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) ++ device_printf(sc->sc_dev, "Engine is permanently " ++ "locked until next system reset!\n"); ++ else ++ device_printf(sc->sc_dev, "Engine enabled " ++ "successfully!\n"); ++ } ++#endif ++ ++report: ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); ++ ++ switch (encl) { ++ case HIFN_PUSTAT_ENA_1: ++ case HIFN_PUSTAT_ENA_2: ++ break; ++ case HIFN_PUSTAT_ENA_0: ++ default: ++ device_printf(sc->sc_dev, "disabled\n"); ++ break; ++ } ++ ++ return 0; ++} ++ ++/* ++ * Give initial values to the registers listed in the "Register Space" ++ * section of the HIFN Software Development reference manual. ++ */ ++static void ++hifn_init_pci_registers(struct hifn_softc *sc) ++{ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* write fixed values needed by the Initialization registers */ ++ WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); ++ WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); ++ WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); ++ ++ /* write all 4 ring address registers */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, cmdr[0])); ++ WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, srcr[0])); ++ WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, dstr[0])); ++ WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, resr[0])); ++ ++ DELAY(2000); ++ ++ /* write status register */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | ++ HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | ++ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | ++ HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | ++ HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | ++ HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | ++ HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | ++ HIFN_DMACSR_S_WAIT | ++ HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | ++ HIFN_DMACSR_C_WAIT | ++ HIFN_DMACSR_ENGINE | ++ ((sc->sc_flags & HIFN_HAS_PUBLIC) ? ++ HIFN_DMACSR_PUBDONE : 0) | ++ ((sc->sc_flags & HIFN_IS_7811) ? ++ HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); ++ ++ sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; ++ sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | ++ HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | ++ HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | ++ ((sc->sc_flags & HIFN_IS_7811) ? ++ HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); ++ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++ ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ u_int32_t pll; ++ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | ++ HIFN_PUCNFG_TCALLPHASES | ++ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); ++ ++ /* turn off the clocks and insure bypass is set */ ++ pll = READ_REG_1(sc, HIFN_1_PLL); ++ pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) ++ | HIFN_PLL_BP | HIFN_PLL_MBSET; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ DELAY(10*1000); /* 10ms */ ++ ++ /* change configuration */ ++ pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ DELAY(10*1000); /* 10ms */ ++ ++ /* disable bypass */ ++ pll &= ~HIFN_PLL_BP; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ /* enable clocks with new configuration */ ++ pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ } else { ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | ++ HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | ++ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | ++ (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); ++ } ++ ++ WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | ++ ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | ++ ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); ++} ++ ++/* ++ * The maximum number of sessions supported by the card ++ * is dependent on the amount of context ram, which ++ * encryption algorithms are enabled, and how compression ++ * is configured. This should be configured before this ++ * routine is called. ++ */ ++static void ++hifn_sessions(struct hifn_softc *sc) ++{ ++ u_int32_t pucnfg; ++ int ctxsize; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); ++ ++ if (pucnfg & HIFN_PUCNFG_COMPSING) { ++ if (pucnfg & HIFN_PUCNFG_ENCCNFG) ++ ctxsize = 128; ++ else ++ ctxsize = 512; ++ /* ++ * 7955/7956 has internal context memory of 32K ++ */ ++ if (sc->sc_flags & HIFN_IS_7956) ++ sc->sc_maxses = 32768 / ctxsize; ++ else ++ sc->sc_maxses = 1 + ++ ((sc->sc_ramsize - 32768) / ctxsize); ++ } else ++ sc->sc_maxses = sc->sc_ramsize / 16384; ++ ++ if (sc->sc_maxses > 2048) ++ sc->sc_maxses = 2048; ++} ++ ++/* ++ * Determine ram type (sram or dram). Board should be just out of a reset ++ * state when this is called. ++ */ ++static int ++hifn_ramtype(struct hifn_softc *sc) ++{ ++ u_int8_t data[8], dataexpect[8]; ++ int i; ++ ++ for (i = 0; i < sizeof(data); i++) ++ data[i] = dataexpect[i] = 0x55; ++ if (hifn_writeramaddr(sc, 0, data)) ++ return (-1); ++ if (hifn_readramaddr(sc, 0, data)) ++ return (-1); ++ if (bcmp(data, dataexpect, sizeof(data)) != 0) { ++ sc->sc_drammodel = 1; ++ return (0); ++ } ++ ++ for (i = 0; i < sizeof(data); i++) ++ data[i] = dataexpect[i] = 0xaa; ++ if (hifn_writeramaddr(sc, 0, data)) ++ return (-1); ++ if (hifn_readramaddr(sc, 0, data)) ++ return (-1); ++ if (bcmp(data, dataexpect, sizeof(data)) != 0) { ++ sc->sc_drammodel = 1; ++ return (0); ++ } ++ ++ return (0); ++} ++ ++#define HIFN_SRAM_MAX (32 << 20) ++#define HIFN_SRAM_STEP_SIZE 16384 ++#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) ++ ++static int ++hifn_sramsize(struct hifn_softc *sc) ++{ ++ u_int32_t a; ++ u_int8_t data[8]; ++ u_int8_t dataexpect[sizeof(data)]; ++ int32_t i; ++ ++ for (i = 0; i < sizeof(data); i++) ++ data[i] = dataexpect[i] = i ^ 0x5a; ++ ++ for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { ++ a = i * HIFN_SRAM_STEP_SIZE; ++ bcopy(&i, data, sizeof(i)); ++ hifn_writeramaddr(sc, a, data); ++ } ++ ++ for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { ++ a = i * HIFN_SRAM_STEP_SIZE; ++ bcopy(&i, dataexpect, sizeof(i)); ++ if (hifn_readramaddr(sc, a, data) < 0) ++ return (0); ++ if (bcmp(data, dataexpect, sizeof(data)) != 0) ++ return (0); ++ sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; ++ } ++ ++ return (0); ++} ++ ++/* ++ * XXX For dram boards, one should really try all of the ++ * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG ++ * is already set up correctly. ++ */ ++static int ++hifn_dramsize(struct hifn_softc *sc) ++{ ++ u_int32_t cnfg; ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ /* ++ * 7955/7956 have a fixed internal ram of only 32K. ++ */ ++ sc->sc_ramsize = 32768; ++ } else { ++ cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & ++ HIFN_PUCNFG_DRAMMASK; ++ sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); ++ } ++ return (0); ++} ++ ++static void ++hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (dma->cmdi == HIFN_D_CMD_RSIZE) { ++ dma->cmdi = 0; ++ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *cmdp = dma->cmdi++; ++ dma->cmdk = dma->cmdi; ++ ++ if (dma->srci == HIFN_D_SRC_RSIZE) { ++ dma->srci = 0; ++ dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->srcr[HIFN_D_SRC_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *srcp = dma->srci++; ++ dma->srck = dma->srci; ++ ++ if (dma->dsti == HIFN_D_DST_RSIZE) { ++ dma->dsti = 0; ++ dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->dstr[HIFN_D_DST_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *dstp = dma->dsti++; ++ dma->dstk = dma->dsti; ++ ++ if (dma->resi == HIFN_D_RES_RSIZE) { ++ dma->resi = 0; ++ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *resp = dma->resi++; ++ dma->resk = dma->resi; ++} ++ ++static int ++hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ hifn_base_command_t wc; ++ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; ++ int r, cmdi, resi, srci, dsti; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ wc.masks = htole16(3 << 13); ++ wc.session_num = htole16(addr >> 14); ++ wc.total_source_count = htole16(8); ++ wc.total_dest_count = htole16(addr & 0x3fff); ++ ++ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | ++ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); ++ ++ /* build write command */ ++ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); ++ *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; ++ bcopy(data, &dma->test_src, sizeof(dma->test_src)); ++ ++ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr ++ + offsetof(struct hifn_dma, test_src)); ++ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr ++ + offsetof(struct hifn_dma, test_dst)); ++ ++ dma->cmdr[cmdi].l = htole32(16 | masks); ++ dma->srcr[srci].l = htole32(8 | masks); ++ dma->dstr[dsti].l = htole32(4 | masks); ++ dma->resr[resi].l = htole32(4 | masks); ++ ++ for (r = 10000; r >= 0; r--) { ++ DELAY(10); ++ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) ++ break; ++ } ++ if (r == 0) { ++ device_printf(sc->sc_dev, "writeramaddr -- " ++ "result[%d](addr %d) still valid\n", resi, addr); ++ r = -1; ++ return (-1); ++ } else ++ r = 0; ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | ++ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); ++ ++ return (r); ++} ++ ++static int ++hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ hifn_base_command_t rc; ++ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; ++ int r, cmdi, srci, dsti, resi; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ rc.masks = htole16(2 << 13); ++ rc.session_num = htole16(addr >> 14); ++ rc.total_source_count = htole16(addr & 0x3fff); ++ rc.total_dest_count = htole16(8); ++ ++ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | ++ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); ++ ++ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); ++ *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; ++ ++ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, test_src)); ++ dma->test_src = 0; ++ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, test_dst)); ++ dma->test_dst = 0; ++ dma->cmdr[cmdi].l = htole32(8 | masks); ++ dma->srcr[srci].l = htole32(8 | masks); ++ dma->dstr[dsti].l = htole32(8 | masks); ++ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); ++ ++ for (r = 10000; r >= 0; r--) { ++ DELAY(10); ++ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) ++ break; ++ } ++ if (r == 0) { ++ device_printf(sc->sc_dev, "readramaddr -- " ++ "result[%d](addr %d) still valid\n", resi, addr); ++ r = -1; ++ } else { ++ r = 0; ++ bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); ++ } ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | ++ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); ++ ++ return (r); ++} ++ ++/* ++ * Initialize the descriptor rings. ++ */ ++static void ++hifn_init_dma(struct hifn_softc *sc) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ hifn_set_retry(sc); ++ ++ /* initialize static pointer values */ ++ for (i = 0; i < HIFN_D_CMD_RSIZE; i++) ++ dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, command_bufs[i][0])); ++ for (i = 0; i < HIFN_D_RES_RSIZE; i++) ++ dma->resr[i].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, result_bufs[i][0])); ++ ++ dma->cmdr[HIFN_D_CMD_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); ++ dma->srcr[HIFN_D_SRC_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); ++ dma->dstr[HIFN_D_DST_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); ++ dma->resr[HIFN_D_RES_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); ++ ++ dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; ++ dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; ++ dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; ++} ++ ++/* ++ * Writes out the raw command buffer space. Returns the ++ * command buffer size. ++ */ ++static u_int ++hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) ++{ ++ struct hifn_softc *sc = NULL; ++ u_int8_t *buf_pos; ++ hifn_base_command_t *base_cmd; ++ hifn_mac_command_t *mac_cmd; ++ hifn_crypt_command_t *cry_cmd; ++ int using_mac, using_crypt, len, ivlen; ++ u_int32_t dlen, slen; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf_pos = buf; ++ using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; ++ using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; ++ ++ base_cmd = (hifn_base_command_t *)buf_pos; ++ base_cmd->masks = htole16(cmd->base_masks); ++ slen = cmd->src_mapsize; ++ if (cmd->sloplen) ++ dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); ++ else ++ dlen = cmd->dst_mapsize; ++ base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); ++ base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); ++ dlen >>= 16; ++ slen >>= 16; ++ base_cmd->session_num = htole16( ++ ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | ++ ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); ++ buf_pos += sizeof(hifn_base_command_t); ++ ++ if (using_mac) { ++ mac_cmd = (hifn_mac_command_t *)buf_pos; ++ dlen = cmd->maccrd->crd_len; ++ mac_cmd->source_count = htole16(dlen & 0xffff); ++ dlen >>= 16; ++ mac_cmd->masks = htole16(cmd->mac_masks | ++ ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); ++ mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); ++ mac_cmd->reserved = 0; ++ buf_pos += sizeof(hifn_mac_command_t); ++ } ++ ++ if (using_crypt) { ++ cry_cmd = (hifn_crypt_command_t *)buf_pos; ++ dlen = cmd->enccrd->crd_len; ++ cry_cmd->source_count = htole16(dlen & 0xffff); ++ dlen >>= 16; ++ cry_cmd->masks = htole16(cmd->cry_masks | ++ ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); ++ cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); ++ cry_cmd->reserved = 0; ++ buf_pos += sizeof(hifn_crypt_command_t); ++ } ++ ++ if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { ++ bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); ++ buf_pos += HIFN_MAC_KEY_LENGTH; ++ } ++ ++ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { ++ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { ++ case HIFN_CRYPT_CMD_ALG_3DES: ++ bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); ++ buf_pos += HIFN_3DES_KEY_LENGTH; ++ break; ++ case HIFN_CRYPT_CMD_ALG_DES: ++ bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); ++ buf_pos += HIFN_DES_KEY_LENGTH; ++ break; ++ case HIFN_CRYPT_CMD_ALG_RC4: ++ len = 256; ++ do { ++ int clen; ++ ++ clen = MIN(cmd->cklen, len); ++ bcopy(cmd->ck, buf_pos, clen); ++ len -= clen; ++ buf_pos += clen; ++ } while (len > 0); ++ bzero(buf_pos, 4); ++ buf_pos += 4; ++ break; ++ case HIFN_CRYPT_CMD_ALG_AES: ++ /* ++ * AES keys are variable 128, 192 and ++ * 256 bits (16, 24 and 32 bytes). ++ */ ++ bcopy(cmd->ck, buf_pos, cmd->cklen); ++ buf_pos += cmd->cklen; ++ break; ++ } ++ } ++ ++ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { ++ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { ++ case HIFN_CRYPT_CMD_ALG_AES: ++ ivlen = HIFN_AES_IV_LENGTH; ++ break; ++ default: ++ ivlen = HIFN_IV_LENGTH; ++ break; ++ } ++ bcopy(cmd->iv, buf_pos, ivlen); ++ buf_pos += ivlen; ++ } ++ ++ if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { ++ bzero(buf_pos, 8); ++ buf_pos += 8; ++ } ++ ++ return (buf_pos - buf); ++} ++ ++static int ++hifn_dmamap_aligned(struct hifn_operand *op) ++{ ++ struct hifn_softc *sc = NULL; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ for (i = 0; i < op->nsegs; i++) { ++ if (op->segs[i].ds_addr & 3) ++ return (0); ++ if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) ++ return (0); ++ } ++ return (1); ++} ++ ++static __inline int ++hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ ++ if (++idx == HIFN_D_DST_RSIZE) { ++ dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | ++ HIFN_D_MASKDONEIRQ); ++ HIFN_DSTR_SYNC(sc, idx, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ idx = 0; ++ } ++ return (idx); ++} ++ ++static int ++hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct hifn_operand *dst = &cmd->dst; ++ u_int32_t p, l; ++ int idx, used = 0, i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ idx = dma->dsti; ++ for (i = 0; i < dst->nsegs - 1; i++) { ++ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); ++ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); ++ wmb(); ++ dma->dstr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, idx, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ used++; ++ ++ idx = hifn_dmamap_dstwrap(sc, idx); ++ } ++ ++ if (cmd->sloplen == 0) { ++ p = dst->segs[i].ds_addr; ++ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | ++ dst->segs[i].ds_len; ++ } else { ++ p = sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, slop[cmd->slopidx]); ++ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | ++ sizeof(u_int32_t); ++ ++ if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { ++ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); ++ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | ++ (dst->segs[i].ds_len - cmd->sloplen)); ++ wmb(); ++ dma->dstr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, idx, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ used++; ++ ++ idx = hifn_dmamap_dstwrap(sc, idx); ++ } ++ } ++ dma->dstr[idx].p = htole32(p); ++ dma->dstr[idx].l = htole32(l); ++ wmb(); ++ dma->dstr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ used++; ++ ++ idx = hifn_dmamap_dstwrap(sc, idx); ++ ++ dma->dsti = idx; ++ dma->dstu += used; ++ return (idx); ++} ++ ++static __inline int ++hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ ++ if (++idx == HIFN_D_SRC_RSIZE) { ++ dma->srcr[idx].l = htole32(HIFN_D_VALID | ++ HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); ++ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ idx = 0; ++ } ++ return (idx); ++} ++ ++static int ++hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct hifn_operand *src = &cmd->src; ++ int idx, i; ++ u_int32_t last = 0; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ idx = dma->srci; ++ for (i = 0; i < src->nsegs; i++) { ++ if (i == src->nsegs - 1) ++ last = HIFN_D_LAST; ++ ++ dma->srcr[idx].p = htole32(src->segs[i].ds_addr); ++ dma->srcr[idx].l = htole32(src->segs[i].ds_len | ++ HIFN_D_MASKDONEIRQ | last); ++ wmb(); ++ dma->srcr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_SRCR_SYNC(sc, idx, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ ++ idx = hifn_dmamap_srcwrap(sc, idx); ++ } ++ dma->srci = idx; ++ dma->srcu += src->nsegs; ++ return (idx); ++} ++ ++ ++static int ++hifn_crypto( ++ struct hifn_softc *sc, ++ struct hifn_command *cmd, ++ struct cryptop *crp, ++ int hint) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ u_int32_t cmdlen, csr; ++ int cmdi, resi, err = 0; ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* ++ * need 1 cmd, and 1 res ++ * ++ * NB: check this first since it's easy. ++ */ ++ HIFN_LOCK(sc); ++ if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || ++ (dma->resu + 1) > HIFN_D_RES_RSIZE) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "cmd/result exhaustion, cmdu %u resu %u\n", ++ dma->cmdu, dma->resu); ++ } ++#endif ++ hifnstats.hst_nomem_cr++; ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ HIFN_UNLOCK(sc); ++ return (ERESTART); ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (pci_map_skb(sc, &cmd->src, cmd->src_skb)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_srcmap1; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (pci_map_uio(sc, &cmd->src, cmd->src_io)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_srcmap1; ++ } ++ } else { ++ if (pci_map_buf(sc, &cmd->src, cmd->src_buf, crp->crp_ilen)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_srcmap1; ++ } ++ } ++ ++ if (hifn_dmamap_aligned(&cmd->src)) { ++ cmd->sloplen = cmd->src_mapsize & 3; ++ cmd->dst = cmd->src; ++ } else { ++ if (crp->crp_flags & CRYPTO_F_IOV) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto err_srcmap; ++ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { ++#ifdef NOTYET ++ int totlen, len; ++ struct mbuf *m, *m0, *mlast; ++ ++ KASSERT(cmd->dst_m == cmd->src_m, ++ ("hifn_crypto: dst_m initialized improperly")); ++ hifnstats.hst_unaligned++; ++ /* ++ * Source is not aligned on a longword boundary. ++ * Copy the data to insure alignment. If we fail ++ * to allocate mbufs or clusters while doing this ++ * we return ERESTART so the operation is requeued ++ * at the crypto later, but only if there are ++ * ops already posted to the hardware; otherwise we ++ * have no guarantee that we'll be re-entered. ++ */ ++ totlen = cmd->src_mapsize; ++ if (cmd->src_m->m_flags & M_PKTHDR) { ++ len = MHLEN; ++ MGETHDR(m0, M_DONTWAIT, MT_DATA); ++ if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { ++ m_free(m0); ++ m0 = NULL; ++ } ++ } else { ++ len = MLEN; ++ MGET(m0, M_DONTWAIT, MT_DATA); ++ } ++ if (m0 == NULL) { ++ hifnstats.hst_nomem_mbuf++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ goto err_srcmap; ++ } ++ if (totlen >= MINCLSIZE) { ++ MCLGET(m0, M_DONTWAIT); ++ if ((m0->m_flags & M_EXT) == 0) { ++ hifnstats.hst_nomem_mcl++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ m_freem(m0); ++ goto err_srcmap; ++ } ++ len = MCLBYTES; ++ } ++ totlen -= len; ++ m0->m_pkthdr.len = m0->m_len = len; ++ mlast = m0; ++ ++ while (totlen > 0) { ++ MGET(m, M_DONTWAIT, MT_DATA); ++ if (m == NULL) { ++ hifnstats.hst_nomem_mbuf++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ m_freem(m0); ++ goto err_srcmap; ++ } ++ len = MLEN; ++ if (totlen >= MINCLSIZE) { ++ MCLGET(m, M_DONTWAIT); ++ if ((m->m_flags & M_EXT) == 0) { ++ hifnstats.hst_nomem_mcl++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ mlast->m_next = m; ++ m_freem(m0); ++ goto err_srcmap; ++ } ++ len = MCLBYTES; ++ } ++ ++ m->m_len = len; ++ m0->m_pkthdr.len += len; ++ totlen -= len; ++ ++ mlast->m_next = m; ++ mlast = m; ++ } ++ cmd->dst_m = m0; ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", ++ __FILE__, __LINE__); ++ err = EINVAL; ++ goto err_srcmap; ++#endif ++ } else { ++ device_printf(sc->sc_dev, ++ "%s,%d: unaligned contig buffers not implemented\n", ++ __FILE__, __LINE__); ++ err = EINVAL; ++ goto err_srcmap; ++ } ++ } ++ ++ if (cmd->dst_map == NULL) { ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (pci_map_skb(sc, &cmd->dst, cmd->dst_skb)) { ++ hifnstats.hst_nomem_map++; ++ err = ENOMEM; ++ goto err_dstmap1; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (pci_map_uio(sc, &cmd->dst, cmd->dst_io)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_dstmap1; ++ } ++ } else { ++ if (pci_map_buf(sc, &cmd->dst, cmd->dst_buf, crp->crp_ilen)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_dstmap1; ++ } ++ } ++ } ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", ++ READ_REG_1(sc, HIFN_1_DMA_CSR), ++ READ_REG_1(sc, HIFN_1_DMA_IER), ++ dma->cmdu, dma->srcu, dma->dstu, dma->resu, ++ cmd->src_nsegs, cmd->dst_nsegs); ++ } ++#endif ++ ++#if 0 ++ if (cmd->src_map == cmd->dst_map) { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); ++ } else { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_PREWRITE); ++ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, ++ BUS_DMASYNC_PREREAD); ++ } ++#endif ++ ++ /* ++ * need N src, and N dst ++ */ ++ if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || ++ (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", ++ dma->srcu, cmd->src_nsegs, ++ dma->dstu, cmd->dst_nsegs); ++ } ++#endif ++ hifnstats.hst_nomem_sd++; ++ err = ERESTART; ++ goto err_dstmap; ++ } ++ ++ if (dma->cmdi == HIFN_D_CMD_RSIZE) { ++ dma->cmdi = 0; ++ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ cmdi = dma->cmdi++; ++ cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); ++ HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); ++ ++ /* .p for command/result already set */ ++ dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_LAST | ++ HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->cmdr[cmdi].l |= htole32(HIFN_D_VALID); ++ HIFN_CMDR_SYNC(sc, cmdi, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ dma->cmdu++; ++ ++ /* ++ * We don't worry about missing an interrupt (which a "command wait" ++ * interrupt salvages us from), unless there is more than one command ++ * in the queue. ++ */ ++ if (dma->cmdu > 1) { ++ sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++ } ++ ++ hifnstats.hst_ipackets++; ++ hifnstats.hst_ibytes += cmd->src_mapsize; ++ ++ hifn_dmamap_load_src(sc, cmd); ++ ++ /* ++ * Unlike other descriptors, we don't mask done interrupt from ++ * result descriptor. ++ */ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, "load res\n"); ++#endif ++ if (dma->resi == HIFN_D_RES_RSIZE) { ++ dma->resi = 0; ++ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ } ++ resi = dma->resi++; ++ KASSERT(dma->hifn_commands[resi] == NULL, ++ ("hifn_crypto: command slot %u busy", resi)); ++ dma->hifn_commands[resi] = cmd; ++ HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); ++ if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { ++ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | ++ HIFN_D_LAST | HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->resr[resi].l |= htole32(HIFN_D_VALID); ++ sc->sc_curbatch++; ++ if (sc->sc_curbatch > hifnstats.hst_maxbatch) ++ hifnstats.hst_maxbatch = sc->sc_curbatch; ++ hifnstats.hst_totbatch++; ++ } else { ++ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | HIFN_D_LAST); ++ wmb(); ++ dma->resr[resi].l |= htole32(HIFN_D_VALID); ++ sc->sc_curbatch = 0; ++ } ++ HIFN_RESR_SYNC(sc, resi, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ dma->resu++; ++ ++ if (cmd->sloplen) ++ cmd->slopidx = resi; ++ ++ hifn_dmamap_load_dst(sc, cmd); ++ ++ csr = 0; ++ if (sc->sc_c_busy == 0) { ++ csr |= HIFN_DMACSR_C_CTRL_ENA; ++ sc->sc_c_busy = 1; ++ } ++ if (sc->sc_s_busy == 0) { ++ csr |= HIFN_DMACSR_S_CTRL_ENA; ++ sc->sc_s_busy = 1; ++ } ++ if (sc->sc_r_busy == 0) { ++ csr |= HIFN_DMACSR_R_CTRL_ENA; ++ sc->sc_r_busy = 1; ++ } ++ if (sc->sc_d_busy == 0) { ++ csr |= HIFN_DMACSR_D_CTRL_ENA; ++ sc->sc_d_busy = 1; ++ } ++ if (csr) ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", ++ READ_REG_1(sc, HIFN_1_DMA_CSR), ++ READ_REG_1(sc, HIFN_1_DMA_IER)); ++ } ++#endif ++ ++ sc->sc_active = 5; ++ HIFN_UNLOCK(sc); ++ KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); ++ return (err); /* success */ ++ ++err_dstmap: ++ if (cmd->src_map != cmd->dst_map) ++ pci_unmap_buf(sc, &cmd->dst); ++err_dstmap1: ++err_srcmap: ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (cmd->src_skb != cmd->dst_skb) ++#ifdef NOTYET ++ m_freem(cmd->dst_m); ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", ++ __FILE__, __LINE__); ++#endif ++ } ++ pci_unmap_buf(sc, &cmd->src); ++err_srcmap1: ++ HIFN_UNLOCK(sc); ++ return (err); ++} ++ ++static void ++hifn_tick(unsigned long arg) ++{ ++ struct hifn_softc *sc; ++ unsigned long l_flags; ++ ++ if (arg >= HIFN_MAX_CHIPS) ++ return; ++ sc = hifn_chip_idx[arg]; ++ if (!sc) ++ return; ++ ++ HIFN_LOCK(sc); ++ if (sc->sc_active == 0) { ++ struct hifn_dma *dma = sc->sc_dma; ++ u_int32_t r = 0; ++ ++ if (dma->cmdu == 0 && sc->sc_c_busy) { ++ sc->sc_c_busy = 0; ++ r |= HIFN_DMACSR_C_CTRL_DIS; ++ } ++ if (dma->srcu == 0 && sc->sc_s_busy) { ++ sc->sc_s_busy = 0; ++ r |= HIFN_DMACSR_S_CTRL_DIS; ++ } ++ if (dma->dstu == 0 && sc->sc_d_busy) { ++ sc->sc_d_busy = 0; ++ r |= HIFN_DMACSR_D_CTRL_DIS; ++ } ++ if (dma->resu == 0 && sc->sc_r_busy) { ++ sc->sc_r_busy = 0; ++ r |= HIFN_DMACSR_R_CTRL_DIS; ++ } ++ if (r) ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); ++ } else ++ sc->sc_active--; ++ HIFN_UNLOCK(sc); ++ mod_timer(&sc->sc_tickto, jiffies + HZ); ++} ++ ++static irqreturn_t ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++hifn_intr(int irq, void *arg) ++#else ++hifn_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct hifn_softc *sc = arg; ++ struct hifn_dma *dma; ++ u_int32_t dmacsr, restart; ++ int i, u; ++ unsigned long l_flags; ++ ++ dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); ++ ++ /* Nothing in the DMA unit interrupted */ ++ if ((dmacsr & sc->sc_dmaier) == 0) ++ return IRQ_NONE; ++ ++ HIFN_LOCK(sc); ++ ++ dma = sc->sc_dma; ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", ++ dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, ++ dma->cmdi, dma->srci, dma->dsti, dma->resi, ++ dma->cmdk, dma->srck, dma->dstk, dma->resk, ++ dma->cmdu, dma->srcu, dma->dstu, dma->resu); ++ } ++#endif ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); ++ ++ if ((sc->sc_flags & HIFN_HAS_PUBLIC) && ++ (dmacsr & HIFN_DMACSR_PUBDONE)) ++ WRITE_REG_1(sc, HIFN_1_PUB_STATUS, ++ READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); ++ ++ restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); ++ if (restart) ++ device_printf(sc->sc_dev, "overrun %x\n", dmacsr); ++ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ if (dmacsr & HIFN_DMACSR_ILLR) ++ device_printf(sc->sc_dev, "illegal read\n"); ++ if (dmacsr & HIFN_DMACSR_ILLW) ++ device_printf(sc->sc_dev, "illegal write\n"); ++ } ++ ++ restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | ++ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); ++ if (restart) { ++ device_printf(sc->sc_dev, "abort, resetting.\n"); ++ hifnstats.hst_abort++; ++ hifn_abort(sc); ++ HIFN_UNLOCK(sc); ++ return IRQ_HANDLED; ++ } ++ ++ if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { ++ /* ++ * If no slots to process and we receive a "waiting on ++ * command" interrupt, we disable the "waiting on command" ++ * (by clearing it). ++ */ ++ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++ } ++ ++ /* clear the rings */ ++ i = dma->resk; u = dma->resu; ++ while (u != 0) { ++ HIFN_RESR_SYNC(sc, i, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ if (dma->resr[i].l & htole32(HIFN_D_VALID)) { ++ HIFN_RESR_SYNC(sc, i, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ break; ++ } ++ ++ if (i != HIFN_D_RES_RSIZE) { ++ struct hifn_command *cmd; ++ u_int8_t *macbuf = NULL; ++ ++ HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); ++ cmd = dma->hifn_commands[i]; ++ KASSERT(cmd != NULL, ++ ("hifn_intr: null command slot %u", i)); ++ dma->hifn_commands[i] = NULL; ++ ++ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { ++ macbuf = dma->result_bufs[i]; ++ macbuf += 12; ++ } ++ ++ hifn_callback(sc, cmd, macbuf); ++ hifnstats.hst_opackets++; ++ u--; ++ } ++ ++ if (++i == (HIFN_D_RES_RSIZE + 1)) ++ i = 0; ++ } ++ dma->resk = i; dma->resu = u; ++ ++ i = dma->srck; u = dma->srcu; ++ while (u != 0) { ++ if (i == HIFN_D_SRC_RSIZE) ++ i = 0; ++ HIFN_SRCR_SYNC(sc, i, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { ++ HIFN_SRCR_SYNC(sc, i, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ break; ++ } ++ i++, u--; ++ } ++ dma->srck = i; dma->srcu = u; ++ ++ i = dma->cmdk; u = dma->cmdu; ++ while (u != 0) { ++ HIFN_CMDR_SYNC(sc, i, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { ++ HIFN_CMDR_SYNC(sc, i, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ break; ++ } ++ if (i != HIFN_D_CMD_RSIZE) { ++ u--; ++ HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); ++ } ++ if (++i == (HIFN_D_CMD_RSIZE + 1)) ++ i = 0; ++ } ++ dma->cmdk = i; dma->cmdu = u; ++ ++ HIFN_UNLOCK(sc); ++ ++ if (sc->sc_needwakeup) { /* XXX check high watermark */ ++ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, ++ "wakeup crypto (%x) u %d/%d/%d/%d\n", ++ sc->sc_needwakeup, ++ dma->cmdu, dma->srcu, dma->dstu, dma->resu); ++#endif ++ sc->sc_needwakeup &= ~wakeup; ++ crypto_unblock(sc->sc_cid, wakeup); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Allocate a new 'session' and return an encoded session id. 'sidp' ++ * contains our registration id, and should contain an encoded session ++ * id on successful allocation. ++ */ ++static int ++hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct hifn_softc *sc = device_get_softc(dev); ++ struct cryptoini *c; ++ int mac = 0, cry = 0, sesn; ++ struct hifn_session *ses = NULL; ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ KASSERT(sc != NULL, ("hifn_newsession: null softc")); ++ if (sidp == NULL || cri == NULL || sc == NULL) { ++ DPRINTF("%s,%d: %s - EINVAL\n", __FILE__, __LINE__, __FUNCTION__); ++ return (EINVAL); ++ } ++ ++ HIFN_LOCK(sc); ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct hifn_session *)kmalloc(sizeof(*ses), ++ SLAB_ATOMIC); ++ if (ses == NULL) { ++ HIFN_UNLOCK(sc); ++ return (ENOMEM); ++ } ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (!sc->sc_sessions[sesn].hs_used) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sesn = sc->sc_nsessions; ++ ses = (struct hifn_session *)kmalloc((sesn + 1) * sizeof(*ses), ++ SLAB_ATOMIC); ++ if (ses == NULL) { ++ HIFN_UNLOCK(sc); ++ return (ENOMEM); ++ } ++ bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); ++ bzero(sc->sc_sessions, sesn * sizeof(*ses)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ HIFN_UNLOCK(sc); ++ ++ bzero(ses, sizeof(*ses)); ++ ses->hs_used = 1; ++ ++ for (c = cri; c != NULL; c = c->cri_next) { ++ switch (c->cri_alg) { ++ case CRYPTO_MD5: ++ case CRYPTO_SHA1: ++ case CRYPTO_MD5_HMAC: ++ case CRYPTO_SHA1_HMAC: ++ if (mac) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ mac = 1; ++ ses->hs_mlen = c->cri_mlen; ++ if (ses->hs_mlen == 0) { ++ switch (c->cri_alg) { ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ ses->hs_mlen = 16; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ ses->hs_mlen = 20; ++ break; ++ } ++ } ++ break; ++ case CRYPTO_DES_CBC: ++ case CRYPTO_3DES_CBC: ++ case CRYPTO_AES_CBC: ++ case CRYPTO_ARC4: ++ if (cry) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ cry = 1; ++ break; ++ default: ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ } ++ if (mac == 0 && cry == 0) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ ++ *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); ++ ++ return (0); ++} ++ ++/* ++ * Deallocate a session. ++ * XXX this routine should run a zero'd mac/encrypt key into context ram. ++ * XXX to blow away any keys already stored there. ++ */ ++static int ++hifn_freesession(device_t dev, u_int64_t tid) ++{ ++ struct hifn_softc *sc = device_get_softc(dev); ++ int session, error; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ KASSERT(sc != NULL, ("hifn_freesession: null softc")); ++ if (sc == NULL) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ ++ HIFN_LOCK(sc); ++ session = HIFN_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); ++ error = 0; ++ } else { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ error = EINVAL; ++ } ++ HIFN_UNLOCK(sc); ++ ++ return (error); ++} ++ ++static int ++hifn_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct hifn_softc *sc = device_get_softc(dev); ++ struct hifn_command *cmd = NULL; ++ int session, err, ivlen; ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (crp == NULL || crp->crp_callback == NULL) { ++ hifnstats.hst_invalid++; ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ session = HIFN_SESSION(crp->crp_sid); ++ ++ if (sc == NULL || session >= sc->sc_nsessions) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ ++ cmd = kmalloc(sizeof(struct hifn_command), SLAB_ATOMIC); ++ if (cmd == NULL) { ++ hifnstats.hst_nomem++; ++ err = ENOMEM; ++ goto errout; ++ } ++ memset(cmd, 0, sizeof(*cmd)); ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ cmd->src_skb = (struct sk_buff *)crp->crp_buf; ++ cmd->dst_skb = (struct sk_buff *)crp->crp_buf; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ cmd->src_io = (struct uio *)crp->crp_buf; ++ cmd->dst_io = (struct uio *)crp->crp_buf; ++ } else { ++ cmd->src_buf = crp->crp_buf; ++ cmd->dst_buf = crp->crp_buf; ++ } ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ if (crd2 == NULL) { ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1 || ++ crd1->crd_alg == CRYPTO_MD5) { ++ maccrd = crd1; ++ enccrd = NULL; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4) { ++ if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) ++ cmd->base_masks |= HIFN_BASE_CMD_DECODE; ++ maccrd = NULL; ++ enccrd = crd1; ++ } else { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_MD5 || ++ crd1->crd_alg == CRYPTO_SHA1) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC || ++ crd2->crd_alg == CRYPTO_ARC4) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ cmd->base_masks = HIFN_BASE_CMD_DECODE; ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4 || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC || ++ crd2->crd_alg == CRYPTO_MD5 || ++ crd2->crd_alg == CRYPTO_SHA1) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ /* ++ * We cannot order the 7751 as requested ++ */ ++ DPRINTF("%s,%d: %s %d,%d,%d - EINVAL\n",__FILE__,__LINE__,__FUNCTION__, crd1->crd_alg, crd2->crd_alg, crd1->crd_flags & CRD_F_ENCRYPT); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ ++ if (enccrd) { ++ cmd->enccrd = enccrd; ++ cmd->base_masks |= HIFN_BASE_CMD_CRYPT; ++ switch (enccrd->crd_alg) { ++ case CRYPTO_ARC4: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; ++ break; ++ case CRYPTO_DES_CBC: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | ++ HIFN_CRYPT_CMD_MODE_CBC | ++ HIFN_CRYPT_CMD_NEW_IV; ++ break; ++ case CRYPTO_3DES_CBC: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | ++ HIFN_CRYPT_CMD_MODE_CBC | ++ HIFN_CRYPT_CMD_NEW_IV; ++ break; ++ case CRYPTO_AES_CBC: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | ++ HIFN_CRYPT_CMD_MODE_CBC | ++ HIFN_CRYPT_CMD_NEW_IV; ++ break; ++ default: ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ if (enccrd->crd_alg != CRYPTO_ARC4) { ++ ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? ++ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ bcopy(enccrd->crd_iv, cmd->iv, ivlen); ++ else ++ read_random(cmd->iv, ivlen); ++ ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) ++ == 0) { ++ crypto_copyback(crp->crp_flags, ++ crp->crp_buf, enccrd->crd_inject, ++ ivlen, cmd->iv); ++ } ++ } else { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ bcopy(enccrd->crd_iv, cmd->iv, ivlen); ++ else { ++ crypto_copydata(crp->crp_flags, ++ crp->crp_buf, enccrd->crd_inject, ++ ivlen, cmd->iv); ++ } ++ } ++ } ++ ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) ++ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; ++ cmd->ck = enccrd->crd_key; ++ cmd->cklen = enccrd->crd_klen >> 3; ++ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; ++ ++ /* ++ * Need to specify the size for the AES key in the masks. ++ */ ++ if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == ++ HIFN_CRYPT_CMD_ALG_AES) { ++ switch (cmd->cklen) { ++ case 16: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; ++ break; ++ case 24: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; ++ break; ++ case 32: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; ++ break; ++ default: ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ } ++ ++ if (maccrd) { ++ cmd->maccrd = maccrd; ++ cmd->base_masks |= HIFN_BASE_CMD_MAC; ++ ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | ++ HIFN_MAC_CMD_POS_IPSEC; ++ break; ++ case CRYPTO_MD5_HMAC: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | ++ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; ++ break; ++ case CRYPTO_SHA1: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | ++ HIFN_MAC_CMD_POS_IPSEC; ++ break; ++ case CRYPTO_SHA1_HMAC: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | ++ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; ++ break; ++ } ++ ++ if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || ++ maccrd->crd_alg == CRYPTO_MD5_HMAC) { ++ cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; ++ bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); ++ bzero(cmd->mac + (maccrd->crd_klen >> 3), ++ HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); ++ } ++ } ++ ++ cmd->crp = crp; ++ cmd->session_num = session; ++ cmd->softc = sc; ++ ++ err = hifn_crypto(sc, cmd, crp, hint); ++ if (!err) { ++ return 0; ++ } else if (err == ERESTART) { ++ /* ++ * There weren't enough resources to dispatch the request ++ * to the part. Notify the caller so they'll requeue this ++ * request and resubmit it again soon. ++ */ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, "requeue request\n"); ++#endif ++ kfree(cmd); ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ return (err); ++ } ++ ++errout: ++ if (cmd != NULL) ++ kfree(cmd); ++ if (err == EINVAL) ++ hifnstats.hst_invalid++; ++ else ++ hifnstats.hst_nomem++; ++ crp->crp_etype = err; ++ crypto_done(crp); ++ return (err); ++} ++ ++static void ++hifn_abort(struct hifn_softc *sc) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct hifn_command *cmd; ++ struct cryptop *crp; ++ int i, u; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ i = dma->resk; u = dma->resu; ++ while (u != 0) { ++ cmd = dma->hifn_commands[i]; ++ KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); ++ dma->hifn_commands[i] = NULL; ++ crp = cmd->crp; ++ ++ if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { ++ /* Salvage what we can. */ ++ u_int8_t *macbuf; ++ ++ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { ++ macbuf = dma->result_bufs[i]; ++ macbuf += 12; ++ } else ++ macbuf = NULL; ++ hifnstats.hst_opackets++; ++ hifn_callback(sc, cmd, macbuf); ++ } else { ++#if 0 ++ if (cmd->src_map == cmd->dst_map) { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); ++ } else { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, ++ BUS_DMASYNC_POSTREAD); ++ } ++#endif ++ ++ if (cmd->src_skb != cmd->dst_skb) { ++#ifdef NOTYET ++ m_freem(cmd->src_m); ++ crp->crp_buf = (caddr_t)cmd->dst_m; ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", ++ __FILE__, __LINE__); ++#endif ++ } ++ ++ /* non-shared buffers cannot be restarted */ ++ if (cmd->src_map != cmd->dst_map) { ++ /* ++ * XXX should be EAGAIN, delayed until ++ * after the reset. ++ */ ++ crp->crp_etype = ENOMEM; ++ pci_unmap_buf(sc, &cmd->dst); ++ } else ++ crp->crp_etype = ENOMEM; ++ ++ pci_unmap_buf(sc, &cmd->src); ++ ++ kfree(cmd); ++ if (crp->crp_etype != EAGAIN) ++ crypto_done(crp); ++ } ++ ++ if (++i == HIFN_D_RES_RSIZE) ++ i = 0; ++ u--; ++ } ++ dma->resk = i; dma->resu = u; ++ ++ hifn_reset_board(sc, 1); ++ hifn_init_dma(sc); ++ hifn_init_pci_registers(sc); ++} ++ ++static void ++hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct cryptop *crp = cmd->crp; ++ struct cryptodesc *crd; ++ int i, u; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++#if 0 ++ if (cmd->src_map == cmd->dst_map) { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); ++ } else { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, ++ BUS_DMASYNC_POSTREAD); ++ } ++#endif ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (cmd->src_skb != cmd->dst_skb) { ++#ifdef NOTYET ++ crp->crp_buf = (caddr_t)cmd->dst_m; ++ totlen = cmd->src_mapsize; ++ for (m = cmd->dst_m; m != NULL; m = m->m_next) { ++ if (totlen < m->m_len) { ++ m->m_len = totlen; ++ totlen = 0; ++ } else ++ totlen -= m->m_len; ++ } ++ cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; ++ m_freem(cmd->src_m); ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", ++ __FILE__, __LINE__); ++#endif ++ } ++ } ++ ++ if (cmd->sloplen != 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ cmd->src_mapsize - cmd->sloplen, cmd->sloplen, ++ (caddr_t)&dma->slop[cmd->slopidx]); ++ } ++ ++ i = dma->dstk; u = dma->dstu; ++ while (u != 0) { ++ if (i == HIFN_D_DST_RSIZE) ++ i = 0; ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++#endif ++ if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++#endif ++ break; ++ } ++ i++, u--; ++ } ++ dma->dstk = i; dma->dstu = u; ++ ++ hifnstats.hst_obytes += cmd->dst_mapsize; ++ ++ if (macbuf != NULL) { ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ int len; ++ ++ if (crd->crd_alg != CRYPTO_MD5 && ++ crd->crd_alg != CRYPTO_SHA1 && ++ crd->crd_alg != CRYPTO_MD5_HMAC && ++ crd->crd_alg != CRYPTO_SHA1_HMAC) { ++ continue; ++ } ++ len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, len, macbuf); ++ break; ++ } ++ } ++ ++ if (cmd->src_map != cmd->dst_map) ++ pci_unmap_buf(sc, &cmd->dst); ++ pci_unmap_buf(sc, &cmd->src); ++ kfree(cmd); ++ crypto_done(crp); ++} ++ ++/* ++ * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 ++ * and Group 1 registers; avoid conditions that could create ++ * burst writes by doing a read in between the writes. ++ * ++ * NB: The read we interpose is always to the same register; ++ * we do this because reading from an arbitrary (e.g. last) ++ * register may not always work. ++ */ ++static void ++hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) ++{ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ if (sc->sc_bar0_lastreg == reg - 4) ++ readl(sc->sc_bar0 + HIFN_0_PUCNFG); ++ sc->sc_bar0_lastreg = reg; ++ } ++ writel(val, sc->sc_bar0 + reg); ++} ++ ++static void ++hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) ++{ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ if (sc->sc_bar1_lastreg == reg - 4) ++ readl(sc->sc_bar1 + HIFN_1_REVID); ++ sc->sc_bar1_lastreg = reg; ++ } ++ writel(val, sc->sc_bar1 + reg); ++} ++ ++ ++static struct pci_device_id hifn_pci_tbl[] = { ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7951, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7955, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7956, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_NETSEC, PCI_PRODUCT_NETSEC_7751, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_INVERTEX, PCI_PRODUCT_INVERTEX_AEON, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7811, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ /* ++ * Other vendors share this PCI ID as well, such as ++ * http://www.powercrypt.com, and obviously they also ++ * use the same key. ++ */ ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { 0, 0, 0, 0, 0, 0, } ++}; ++MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); ++ ++static struct pci_driver hifn_driver = { ++ .name = "hifn", ++ .id_table = hifn_pci_tbl, ++ .probe = hifn_probe, ++ .remove = hifn_remove, ++ /* add PM stuff here one day */ ++}; ++ ++static int __init hifn_init (void) ++{ ++ struct hifn_softc *sc = NULL; ++ int rc; ++ ++ DPRINTF("%s(%p)\n", __FUNCTION__, hifn_init); ++ ++ rc = pci_register_driver(&hifn_driver); ++ pci_register_driver_compat(&hifn_driver, rc); ++ ++ return rc; ++} ++ ++static void __exit hifn_exit (void) ++{ ++ pci_unregister_driver(&hifn_driver); ++} ++ ++module_init(hifn_init); ++module_exit(hifn_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("OCF driver for hifn PCI crypto devices"); +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifn7751reg.h linux-3.0.4/crypto/ocf/hifn/hifn7751reg.h +--- linux-3.0.4.orig/crypto/ocf/hifn/hifn7751reg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/hifn7751reg.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,540 @@ ++/* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.7 2007/03/21 03:42:49 sam Exp $ */ ++/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ ++ ++/*- ++ * Invertex AEON / Hifn 7751 driver ++ * Copyright (c) 1999 Invertex Inc. All rights reserved. ++ * Copyright (c) 1999 Theo de Raadt ++ * Copyright (c) 2000-2001 Network Security Technologies, Inc. ++ * http://www.netsec.net ++ * ++ * Please send any comments, feedback, bug-fixes, or feature requests to ++ * software@invertex.com. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++#ifndef __HIFN_H__ ++#define __HIFN_H__ ++ ++/* ++ * Some PCI configuration space offset defines. The names were made ++ * identical to the names used by the Linux kernel. ++ */ ++#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ ++#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ ++#define HIFN_TRDY_TIMEOUT 0x40 ++#define HIFN_RETRY_TIMEOUT 0x41 ++ ++/* ++ * PCI vendor and device identifiers ++ * (the names are preserved from their OpenBSD source). ++ */ ++#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ ++#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ ++#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ ++#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ ++#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ ++#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ ++#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ ++#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ ++ ++#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ ++#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ ++ ++#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ ++#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ ++ ++/* ++ * The values below should multiple of 4 -- and be large enough to handle ++ * any command the driver implements. ++ * ++ * MAX_COMMAND = base command + mac command + encrypt command + ++ * mac-key + rc4-key ++ * MAX_RESULT = base result + mac result + mac + encrypt result ++ * ++ * ++ */ ++#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) ++#define HIFN_MAX_RESULT (8 + 4 + 20 + 4) ++ ++/* ++ * hifn_desc_t ++ * ++ * Holds an individual descriptor for any of the rings. ++ */ ++typedef struct hifn_desc { ++ volatile u_int32_t l; /* length and status bits */ ++ volatile u_int32_t p; ++} hifn_desc_t; ++ ++/* ++ * Masks for the "length" field of struct hifn_desc. ++ */ ++#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ ++#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ ++#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ ++#define HIFN_D_OVER 0x08000000 /* overflow */ ++#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ ++#define HIFN_D_JUMP 0x40000000 /* jump descriptor */ ++#define HIFN_D_VALID 0x80000000 /* valid bit */ ++ ++ ++/* ++ * Processing Unit Registers (offset from BASEREG0) ++ */ ++#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ ++#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ ++#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ ++#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ ++#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ ++#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ ++#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ ++#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ ++#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ ++#define HIFN_0_MUTE1 0x80 ++#define HIFN_0_MUTE2 0x90 ++#define HIFN_0_SPACESIZE 0x100 /* Register space size */ ++ ++/* Processing Unit Control Register (HIFN_0_PUCTRL) */ ++#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ ++#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ ++#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ ++#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ ++#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ ++ ++/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ ++#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ ++#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ ++#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ ++#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ ++#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ ++#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ ++#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ ++#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ ++#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ ++#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ ++ ++/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ ++#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ ++#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ ++#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ ++#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ ++#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ ++#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ ++#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ ++#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ ++#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ ++#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ ++#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ ++#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ ++#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ ++#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ ++#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ ++#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ ++#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ ++#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ ++#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ ++#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ ++#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ ++#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ ++#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ ++ ++/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ ++#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ ++#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ ++#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ ++#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ ++#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ ++#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ ++#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ ++#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ ++#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ ++#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ ++ ++/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ ++#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ ++#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ ++#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ ++#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ ++#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ ++#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ ++#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ ++#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ ++#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ ++#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ ++#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ ++#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ ++#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ ++#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ ++#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ ++#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ ++#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ ++ ++/* FIFO Status Register (HIFN_0_FIFOSTAT) */ ++#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ ++#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ ++ ++/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ ++#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */ ++ ++/* ++ * DMA Interface Registers (offset from BASEREG1) ++ */ ++#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ ++#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ ++#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ ++#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ ++#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ ++#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ ++#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ ++#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ ++#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ ++#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ ++#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ ++#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ ++#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ ++#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ ++#define HIFN_1_REVID 0x98 /* Revision ID */ ++ ++#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ ++#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ ++#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */ ++#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */ ++#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */ ++#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ ++#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ ++#define HIFN_1_RNG_DATA 0x318 /* RNG data */ ++#define HIFN_1_PUB_MODE 0x320 /* PK mode */ ++#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ ++#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ ++#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ ++#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ ++ ++/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ ++#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ ++#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ ++#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ ++#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ ++#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ ++#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ ++#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ ++#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ ++#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ ++#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ ++#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ ++#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ ++#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ ++#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ ++#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ ++#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ ++#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ ++#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ ++#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ ++#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ ++#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ ++#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ ++#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ ++#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ ++#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ ++#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ ++#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ ++#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ ++#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ ++#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ ++#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ ++#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ ++#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ ++#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ ++#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ ++#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ ++#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ ++#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ ++ ++/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ ++#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ ++#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ ++#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ ++#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ ++#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ ++#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ ++#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ ++#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ ++#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ ++#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ ++#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ ++#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ ++#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ ++#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ ++#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ ++#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ ++#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ ++#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ ++#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ ++#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ ++#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ ++#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ ++ ++/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ ++#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ ++#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ ++#define HIFN_DMACNFG_UNLOCK 0x00000800 ++#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ ++#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ ++#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ ++#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ ++#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ ++ ++/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ ++#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ ++#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ ++#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ ++#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ ++#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 ++#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 ++#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 ++#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 ++ ++/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ ++#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ ++ ++/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ ++#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ ++#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ ++#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ ++ ++/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ ++#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ ++#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ ++ ++/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ ++#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ ++#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ ++#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ ++#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ ++#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ ++#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ ++#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ ++#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ ++#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ ++ ++/* Public key reset register (HIFN_1_PUB_RESET) */ ++#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ ++ ++/* Public operation register (HIFN_1_PUB_OP) */ ++#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ ++#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ ++#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ ++#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ ++#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ ++#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ ++#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ ++#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ ++#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ ++#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ ++#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ ++#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ ++#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ ++#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ ++#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ ++#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ ++#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ ++ ++/* Public operand length register (HIFN_1_PUB_OPLEN) */ ++#define HIFN_PUBOPLEN_MODLEN 0x0000007f ++#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 ++#define HIFN_PUBOPLEN_REDLEN 0x003c0000 ++ ++/* Public status register (HIFN_1_PUB_STATUS) */ ++#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ ++#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ ++#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ ++#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ ++#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ ++#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ ++#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ ++ ++/* Public interrupt enable register (HIFN_1_PUB_IEN) */ ++#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ ++ ++/* Random number generator config register (HIFN_1_RNG_CONFIG) */ ++#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ ++ ++/* ++ * Register offsets in register set 1 ++ */ ++ ++#define HIFN_UNLOCK_SECRET1 0xf4 ++#define HIFN_UNLOCK_SECRET2 0xfc ++ ++/* ++ * PLL config register ++ * ++ * This register is present only on 7954/7955/7956 parts. It must be ++ * programmed according to the bus interface method used by the h/w. ++ * Note that the parts require a stable clock. Since the PCI clock ++ * may vary the reference clock must usually be used. To avoid ++ * overclocking the core logic, setup must be done carefully, refer ++ * to the driver for details. The exact multiplier required varies ++ * by part and system configuration; refer to the Hifn documentation. ++ */ ++#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ ++#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ ++/* bit 2 reserved */ ++#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ ++#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ ++/* bits 5-9 reserved */ ++#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ ++#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ ++#define HIFN_PLL_ND_SHIFT 11 ++#define HIFN_PLL_ND_2 0x00000000 /* 2x */ ++#define HIFN_PLL_ND_4 0x00000800 /* 4x */ ++#define HIFN_PLL_ND_6 0x00001000 /* 6x */ ++#define HIFN_PLL_ND_8 0x00001800 /* 8x */ ++#define HIFN_PLL_ND_10 0x00002000 /* 10x */ ++#define HIFN_PLL_ND_12 0x00002800 /* 12x */ ++/* bits 14-15 reserved */ ++#define HIFN_PLL_IS 0x00010000 /* charge pump current select */ ++/* bits 17-31 reserved */ ++ ++/* ++ * Board configuration specifies only these bits. ++ */ ++#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) ++ ++/* ++ * Public Key Engine Mode Register ++ */ ++#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ ++#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ ++ ++ ++/********************************************************************* ++ * Structs for board commands ++ * ++ *********************************************************************/ ++ ++/* ++ * Structure to help build up the command data structure. ++ */ ++typedef struct hifn_base_command { ++ volatile u_int16_t masks; ++ volatile u_int16_t session_num; ++ volatile u_int16_t total_source_count; ++ volatile u_int16_t total_dest_count; ++} hifn_base_command_t; ++ ++#define HIFN_BASE_CMD_MAC 0x0400 ++#define HIFN_BASE_CMD_CRYPT 0x0800 ++#define HIFN_BASE_CMD_DECODE 0x2000 ++#define HIFN_BASE_CMD_SRCLEN_M 0xc000 ++#define HIFN_BASE_CMD_SRCLEN_S 14 ++#define HIFN_BASE_CMD_DSTLEN_M 0x3000 ++#define HIFN_BASE_CMD_DSTLEN_S 12 ++#define HIFN_BASE_CMD_LENMASK_HI 0x30000 ++#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff ++ ++/* ++ * Structure to help build up the command data structure. ++ */ ++typedef struct hifn_crypt_command { ++ volatile u_int16_t masks; ++ volatile u_int16_t header_skip; ++ volatile u_int16_t source_count; ++ volatile u_int16_t reserved; ++} hifn_crypt_command_t; ++ ++#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ ++#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ ++#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ ++#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ ++#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ ++#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ ++#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ ++#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ ++#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ ++#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ ++#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ ++#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ ++#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ ++ ++#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 ++#define HIFN_CRYPT_CMD_SRCLEN_S 14 ++ ++#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ ++#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ ++#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ ++#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ ++ ++/* ++ * Structure to help build up the command data structure. ++ */ ++typedef struct hifn_mac_command { ++ volatile u_int16_t masks; ++ volatile u_int16_t header_skip; ++ volatile u_int16_t source_count; ++ volatile u_int16_t reserved; ++} hifn_mac_command_t; ++ ++#define HIFN_MAC_CMD_ALG_MASK 0x0001 ++#define HIFN_MAC_CMD_ALG_SHA1 0x0000 ++#define HIFN_MAC_CMD_ALG_MD5 0x0001 ++#define HIFN_MAC_CMD_MODE_MASK 0x000c ++#define HIFN_MAC_CMD_MODE_HMAC 0x0000 ++#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 ++#define HIFN_MAC_CMD_MODE_HASH 0x0008 ++#define HIFN_MAC_CMD_MODE_FULL 0x0004 ++#define HIFN_MAC_CMD_TRUNC 0x0010 ++#define HIFN_MAC_CMD_RESULT 0x0020 ++#define HIFN_MAC_CMD_APPEND 0x0040 ++#define HIFN_MAC_CMD_SRCLEN_M 0xc000 ++#define HIFN_MAC_CMD_SRCLEN_S 14 ++ ++/* ++ * MAC POS IPsec initiates authentication after encryption on encodes ++ * and before decryption on decodes. ++ */ ++#define HIFN_MAC_CMD_POS_IPSEC 0x0200 ++#define HIFN_MAC_CMD_NEW_KEY 0x0800 ++ ++/* ++ * The poll frequency and poll scalar defines are unshifted values used ++ * to set fields in the DMA Configuration Register. ++ */ ++#ifndef HIFN_POLL_FREQUENCY ++#define HIFN_POLL_FREQUENCY 0x1 ++#endif ++ ++#ifndef HIFN_POLL_SCALAR ++#define HIFN_POLL_SCALAR 0x0 ++#endif ++ ++#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ ++#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ ++#endif /* __HIFN_H__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifn7751var.h linux-3.0.4/crypto/ocf/hifn/hifn7751var.h +--- linux-3.0.4.orig/crypto/ocf/hifn/hifn7751var.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/hifn7751var.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,368 @@ ++/* $FreeBSD: src/sys/dev/hifn/hifn7751var.h,v 1.9 2007/03/21 03:42:49 sam Exp $ */ ++/* $OpenBSD: hifn7751var.h,v 1.42 2002/04/08 17:49:42 jason Exp $ */ ++ ++/*- ++ * Invertex AEON / Hifn 7751 driver ++ * Copyright (c) 1999 Invertex Inc. All rights reserved. ++ * Copyright (c) 1999 Theo de Raadt ++ * Copyright (c) 2000-2001 Network Security Technologies, Inc. ++ * http://www.netsec.net ++ * ++ * Please send any comments, feedback, bug-fixes, or feature requests to ++ * software@invertex.com. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++#ifndef __HIFN7751VAR_H__ ++#define __HIFN7751VAR_H__ ++ ++#ifdef __KERNEL__ ++ ++/* ++ * Some configurable values for the driver. By default command+result ++ * descriptor rings are the same size. The src+dst descriptor rings ++ * are sized at 3.5x the number of potential commands. Slower parts ++ * (e.g. 7951) tend to run out of src descriptors; faster parts (7811) ++ * src+cmd/result descriptors. It's not clear that increasing the size ++ * of the descriptor rings helps performance significantly as other ++ * factors tend to come into play (e.g. copying misaligned packets). ++ */ ++#define HIFN_D_CMD_RSIZE 24 /* command descriptors */ ++#define HIFN_D_SRC_RSIZE ((HIFN_D_CMD_RSIZE * 7) / 2) /* source descriptors */ ++#define HIFN_D_RES_RSIZE HIFN_D_CMD_RSIZE /* result descriptors */ ++#define HIFN_D_DST_RSIZE HIFN_D_SRC_RSIZE /* destination descriptors */ ++ ++/* ++ * Length values for cryptography ++ */ ++#define HIFN_DES_KEY_LENGTH 8 ++#define HIFN_3DES_KEY_LENGTH 24 ++#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH ++#define HIFN_IV_LENGTH 8 ++#define HIFN_AES_IV_LENGTH 16 ++#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH ++ ++/* ++ * Length values for authentication ++ */ ++#define HIFN_MAC_KEY_LENGTH 64 ++#define HIFN_MD5_LENGTH 16 ++#define HIFN_SHA1_LENGTH 20 ++#define HIFN_MAC_TRUNC_LENGTH 12 ++ ++#define MAX_SCATTER 64 ++ ++/* ++ * Data structure to hold all 4 rings and any other ring related data. ++ */ ++struct hifn_dma { ++ /* ++ * Descriptor rings. We add +1 to the size to accomidate the ++ * jump descriptor. ++ */ ++ struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; ++ struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; ++ struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; ++ struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; ++ ++ struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE]; ++ ++ u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; ++ u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; ++ u_int32_t slop[HIFN_D_CMD_RSIZE]; ++ ++ u_int64_t test_src, test_dst; ++ ++ /* ++ * Our current positions for insertion and removal from the desriptor ++ * rings. ++ */ ++ int cmdi, srci, dsti, resi; ++ volatile int cmdu, srcu, dstu, resu; ++ int cmdk, srck, dstk, resk; ++}; ++ ++struct hifn_session { ++ int hs_used; ++ int hs_mlen; ++}; ++ ++#define HIFN_RING_SYNC(sc, r, i, f) \ ++ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ ++ ++#define HIFN_CMDR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), cmdr, (i), (f)) ++#define HIFN_RESR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), resr, (i), (f)) ++#define HIFN_SRCR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), srcr, (i), (f)) ++#define HIFN_DSTR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), dstr, (i), (f)) ++ ++#define HIFN_CMD_SYNC(sc, i, f) \ ++ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ ++ ++#define HIFN_RES_SYNC(sc, i, f) \ ++ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ ++ ++typedef int bus_size_t; ++ ++/* ++ * Holds data specific to a single HIFN board. ++ */ ++struct hifn_softc { ++ softc_device_decl sc_dev; ++ ++ struct pci_dev *sc_pcidev; /* PCI device pointer */ ++ spinlock_t sc_mtx; /* per-instance lock */ ++ ++ int sc_num; /* for multiple devs */ ++ ++ ocf_iomem_t sc_bar0; ++ bus_size_t sc_bar0_lastreg;/* bar0 last reg written */ ++ ocf_iomem_t sc_bar1; ++ bus_size_t sc_bar1_lastreg;/* bar1 last reg written */ ++ ++ int sc_irq; ++ ++ u_int32_t sc_dmaier; ++ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ ++ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ ++ ++ struct hifn_dma *sc_dma; ++ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ ++ ++ int sc_dmansegs; ++ int32_t sc_cid; ++ int sc_maxses; ++ int sc_nsessions; ++ struct hifn_session *sc_sessions; ++ int sc_ramsize; ++ int sc_flags; ++#define HIFN_HAS_RNG 0x1 /* includes random number generator */ ++#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ ++#define HIFN_HAS_AES 0x4 /* includes AES support */ ++#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ ++#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ ++ ++ struct timer_list sc_tickto; /* for managing DMA */ ++ ++ int sc_rngfirst; ++ int sc_rnghz; /* RNG polling frequency */ ++ ++ int sc_c_busy; /* command ring busy */ ++ int sc_s_busy; /* source data ring busy */ ++ int sc_d_busy; /* destination data ring busy */ ++ int sc_r_busy; /* result ring busy */ ++ int sc_active; /* for initial countdown */ ++ int sc_needwakeup; /* ops q'd wating on resources */ ++ int sc_curbatch; /* # ops submitted w/o int */ ++ int sc_suspended; ++#ifdef HIFN_VULCANDEV ++ struct cdev *sc_pkdev; ++#endif ++}; ++ ++#define HIFN_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) ++#define HIFN_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) ++ ++/* ++ * hifn_command_t ++ * ++ * This is the control structure used to pass commands to hifn_encrypt(). ++ * ++ * flags ++ * ----- ++ * Flags is the bitwise "or" values for command configuration. A single ++ * encrypt direction needs to be set: ++ * ++ * HIFN_ENCODE or HIFN_DECODE ++ * ++ * To use cryptography, a single crypto algorithm must be included: ++ * ++ * HIFN_CRYPT_3DES or HIFN_CRYPT_DES ++ * ++ * To use authentication is used, a single MAC algorithm must be included: ++ * ++ * HIFN_MAC_MD5 or HIFN_MAC_SHA1 ++ * ++ * By default MD5 uses a 16 byte hash and SHA-1 uses a 20 byte hash. ++ * If the value below is set, hash values are truncated or assumed ++ * truncated to 12 bytes: ++ * ++ * HIFN_MAC_TRUNC ++ * ++ * Keys for encryption and authentication can be sent as part of a command, ++ * or the last key value used with a particular session can be retrieved ++ * and used again if either of these flags are not specified. ++ * ++ * HIFN_CRYPT_NEW_KEY, HIFN_MAC_NEW_KEY ++ * ++ * session_num ++ * ----------- ++ * A number between 0 and 2048 (for DRAM models) or a number between ++ * 0 and 768 (for SRAM models). Those who don't want to use session ++ * numbers should leave value at zero and send a new crypt key and/or ++ * new MAC key on every command. If you use session numbers and ++ * don't send a key with a command, the last key sent for that same ++ * session number will be used. ++ * ++ * Warning: Using session numbers and multiboard at the same time ++ * is currently broken. ++ * ++ * mbuf ++ * ---- ++ * Either fill in the mbuf pointer and npa=0 or ++ * fill packp[] and packl[] and set npa to > 0 ++ * ++ * mac_header_skip ++ * --------------- ++ * The number of bytes of the source_buf that are skipped over before ++ * authentication begins. This must be a number between 0 and 2^16-1 ++ * and can be used by IPsec implementers to skip over IP headers. ++ * *** Value ignored if authentication not used *** ++ * ++ * crypt_header_skip ++ * ----------------- ++ * The number of bytes of the source_buf that are skipped over before ++ * the cryptographic operation begins. This must be a number between 0 ++ * and 2^16-1. For IPsec, this number will always be 8 bytes larger ++ * than the auth_header_skip (to skip over the ESP header). ++ * *** Value ignored if cryptography not used *** ++ * ++ */ ++struct hifn_operand { ++ union { ++ struct sk_buff *skb; ++ struct uio *io; ++ unsigned char *buf; ++ } u; ++ void *map; ++ bus_size_t mapsize; ++ int nsegs; ++ struct { ++ dma_addr_t ds_addr; ++ int ds_len; ++ } segs[MAX_SCATTER]; ++}; ++ ++struct hifn_command { ++ u_int16_t session_num; ++ u_int16_t base_masks, cry_masks, mac_masks; ++ u_int8_t iv[HIFN_MAX_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH]; ++ int cklen; ++ int sloplen, slopidx; ++ ++ struct hifn_operand src; ++ struct hifn_operand dst; ++ ++ struct hifn_softc *softc; ++ struct cryptop *crp; ++ struct cryptodesc *enccrd, *maccrd; ++}; ++ ++#define src_skb src.u.skb ++#define src_io src.u.io ++#define src_map src.map ++#define src_mapsize src.mapsize ++#define src_segs src.segs ++#define src_nsegs src.nsegs ++#define src_buf src.u.buf ++ ++#define dst_skb dst.u.skb ++#define dst_io dst.u.io ++#define dst_map dst.map ++#define dst_mapsize dst.mapsize ++#define dst_segs dst.segs ++#define dst_nsegs dst.nsegs ++#define dst_buf dst.u.buf ++ ++/* ++ * Return values for hifn_crypto() ++ */ ++#define HIFN_CRYPTO_SUCCESS 0 ++#define HIFN_CRYPTO_BAD_INPUT (-1) ++#define HIFN_CRYPTO_RINGS_FULL (-2) ++ ++/************************************************************************** ++ * ++ * Function: hifn_crypto ++ * ++ * Purpose: Called by external drivers to begin an encryption on the ++ * HIFN board. ++ * ++ * Blocking/Non-blocking Issues ++ * ============================ ++ * The driver cannot block in hifn_crypto (no calls to tsleep) currently. ++ * hifn_crypto() returns HIFN_CRYPTO_RINGS_FULL if there is not enough ++ * room in any of the rings for the request to proceed. ++ * ++ * Return Values ++ * ============= ++ * 0 for success, negative values on error ++ * ++ * Defines for negative error codes are: ++ * ++ * HIFN_CRYPTO_BAD_INPUT : The passed in command had invalid settings. ++ * HIFN_CRYPTO_RINGS_FULL : All DMA rings were full and non-blocking ++ * behaviour was requested. ++ * ++ *************************************************************************/ ++ ++/* ++ * Convert back and forth from 'sid' to 'card' and 'session' ++ */ ++#define HIFN_CARD(sid) (((sid) & 0xf0000000) >> 28) ++#define HIFN_SESSION(sid) ((sid) & 0x000007ff) ++#define HIFN_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) ++ ++#endif /* _KERNEL */ ++ ++struct hifn_stats { ++ u_int64_t hst_ibytes; ++ u_int64_t hst_obytes; ++ u_int32_t hst_ipackets; ++ u_int32_t hst_opackets; ++ u_int32_t hst_invalid; ++ u_int32_t hst_nomem; /* malloc or one of hst_nomem_* */ ++ u_int32_t hst_abort; ++ u_int32_t hst_noirq; /* IRQ for no reason */ ++ u_int32_t hst_totbatch; /* ops submitted w/o interrupt */ ++ u_int32_t hst_maxbatch; /* max ops submitted together */ ++ u_int32_t hst_unaligned; /* unaligned src caused copy */ ++ /* ++ * The following divides hst_nomem into more specific buckets. ++ */ ++ u_int32_t hst_nomem_map; /* bus_dmamap_create failed */ ++ u_int32_t hst_nomem_load; /* bus_dmamap_load_* failed */ ++ u_int32_t hst_nomem_mbuf; /* MGET* failed */ ++ u_int32_t hst_nomem_mcl; /* MCLGET* failed */ ++ u_int32_t hst_nomem_cr; /* out of command/result descriptor */ ++ u_int32_t hst_nomem_sd; /* out of src/dst descriptors */ ++}; ++ ++#endif /* __HIFN7751VAR_H__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPP.c linux-3.0.4/crypto/ocf/hifn/hifnHIPP.c +--- linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPP.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/hifnHIPP.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,420 @@ ++/*- ++ * Driver for Hifn HIPP-I/II chipset ++ * Copyright (c) 2006 Michael Richardson ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored by Hifn Inc. ++ * ++ */ ++ ++/* ++ * Driver for various Hifn encryption processors. ++ */ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "hifnHIPPreg.h" ++#include "hifnHIPPvar.h" ++ ++#if 1 ++#define DPRINTF(a...) if (hipp_debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_dev) : "hifn"); \ ++ printk(a); \ ++ } else ++#else ++#define DPRINTF(a...) ++#endif ++ ++typedef int bus_size_t; ++ ++static inline int ++pci_get_revid(struct pci_dev *dev) ++{ ++ u8 rid = 0; ++ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); ++ return rid; ++} ++ ++#define debug hipp_debug ++int hipp_debug = 0; ++module_param(hipp_debug, int, 0644); ++MODULE_PARM_DESC(hipp_debug, "Enable debug"); ++ ++int hipp_maxbatch = 1; ++module_param(hipp_maxbatch, int, 0644); ++MODULE_PARM_DESC(hipp_maxbatch, "max ops to batch w/o interrupt"); ++ ++static int hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent); ++static void hipp_remove(struct pci_dev *dev); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++static irqreturn_t hipp_intr(int irq, void *arg); ++#else ++static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs); ++#endif ++ ++static int hipp_num_chips = 0; ++static struct hipp_softc *hipp_chip_idx[HIPP_MAX_CHIPS]; ++ ++static int hipp_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int hipp_freesession(device_t, u_int64_t); ++static int hipp_process(device_t, struct cryptop *, int); ++ ++static device_method_t hipp_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, hipp_newsession), ++ DEVMETHOD(cryptodev_freesession,hipp_freesession), ++ DEVMETHOD(cryptodev_process, hipp_process), ++}; ++ ++static __inline u_int32_t ++READ_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg) ++{ ++ u_int32_t v = readl(sc->sc_bar[barno] + reg); ++ //sc->sc_bar0_lastreg = (bus_size_t) -1; ++ return (v); ++} ++static __inline void ++WRITE_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg, u_int32_t val) ++{ ++ writel(val, sc->sc_bar[barno] + reg); ++} ++ ++#define READ_REG_0(sc, reg) READ_REG(sc, 0, reg) ++#define WRITE_REG_0(sc, reg, val) WRITE_REG(sc,0, reg, val) ++#define READ_REG_1(sc, reg) READ_REG(sc, 1, reg) ++#define WRITE_REG_1(sc, reg, val) WRITE_REG(sc,1, reg, val) ++ ++static int ++hipp_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ return EINVAL; ++} ++ ++static int ++hipp_freesession(device_t dev, u_int64_t tid) ++{ ++ return EINVAL; ++} ++ ++static int ++hipp_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ return EINVAL; ++} ++ ++static const char* ++hipp_partname(struct hipp_softc *sc, char buf[128], size_t blen) ++{ ++ char *n = NULL; ++ ++ switch (pci_get_vendor(sc->sc_pcidev)) { ++ case PCI_VENDOR_HIFN: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_HIFN_7855: n = "Hifn 7855"; ++ case PCI_PRODUCT_HIFN_8155: n = "Hifn 8155"; ++ case PCI_PRODUCT_HIFN_6500: n = "Hifn 6500"; ++ } ++ } ++ ++ if(n==NULL) { ++ snprintf(buf, blen, "VID=%02x,PID=%02x", ++ pci_get_vendor(sc->sc_pcidev), ++ pci_get_device(sc->sc_pcidev)); ++ } else { ++ buf[0]='\0'; ++ strncat(buf, n, blen); ++ } ++ return buf; ++} ++ ++struct hipp_fs_entry { ++ struct attribute attr; ++ /* other stuff */ ++}; ++ ++ ++static ssize_t ++cryptoid_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct hipp_softc *sc; ++ ++ sc = pci_get_drvdata(to_pci_dev (dev)); ++ return sprintf (buf, "%d\n", sc->sc_cid); ++} ++ ++struct device_attribute hipp_dev_cryptoid = __ATTR_RO(cryptoid); ++ ++/* ++ * Attach an interface that successfully probed. ++ */ ++static int ++hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent) ++{ ++ struct hipp_softc *sc = NULL; ++ int i; ++ //char rbase; ++ //u_int16_t ena; ++ int rev; ++ //int rseg; ++ int rc; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (pci_enable_device(dev) < 0) ++ return(-ENODEV); ++ ++ if (pci_set_mwi(dev)) ++ return(-ENODEV); ++ ++ if (!dev->irq) { ++ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); ++ pci_disable_device(dev); ++ return(-ENODEV); ++ } ++ ++ sc = (struct hipp_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, "hifn-hipp", hipp_num_chips, hipp_methods); ++ ++ sc->sc_pcidev = dev; ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++ sc->sc_num = hipp_num_chips++; ++ ++ if (sc->sc_num < HIPP_MAX_CHIPS) ++ hipp_chip_idx[sc->sc_num] = sc; ++ ++ pci_set_drvdata(sc->sc_pcidev, sc); ++ ++ spin_lock_init(&sc->sc_mtx); ++ ++ /* ++ * Setup PCI resources. ++ * The READ_REG_0, WRITE_REG_0, READ_REG_1, ++ * and WRITE_REG_1 macros throughout the driver are used ++ * to permit better debugging. ++ */ ++ for(i=0; i<4; i++) { ++ unsigned long mem_start, mem_len; ++ mem_start = pci_resource_start(sc->sc_pcidev, i); ++ mem_len = pci_resource_len(sc->sc_pcidev, i); ++ sc->sc_barphy[i] = (caddr_t)mem_start; ++ sc->sc_bar[i] = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_bar[i]) { ++ device_printf(sc->sc_dev, "cannot map bar%d register space\n", i); ++ goto fail; ++ } ++ } ++ ++ //hipp_reset_board(sc, 0); ++ pci_set_master(sc->sc_pcidev); ++ ++ /* ++ * Arrange the interrupt line. ++ */ ++ rc = request_irq(dev->irq, hipp_intr, IRQF_SHARED, "hifn", sc); ++ if (rc) { ++ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); ++ goto fail; ++ } ++ sc->sc_irq = dev->irq; ++ ++ rev = READ_REG_1(sc, HIPP_1_REVID) & 0xffff; ++ ++ { ++ char b[32]; ++ device_printf(sc->sc_dev, "%s, rev %u", ++ hipp_partname(sc, b, sizeof(b)), rev); ++ } ++ ++#if 0 ++ if (sc->sc_flags & HIFN_IS_7956) ++ printf(", pll=0x%x<%s clk, %ux mult>", ++ sc->sc_pllconfig, ++ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", ++ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); ++#endif ++ printf("\n"); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ goto fail; ++ } ++ ++#if 0 /* cannot work with a non-GPL module */ ++ /* make a sysfs entry to let the world know what entry we got */ ++ sysfs_create_file(&sc->sc_pcidev->dev.kobj, &hipp_dev_cryptoid.attr); ++#endif ++ ++#if 0 ++ init_timer(&sc->sc_tickto); ++ sc->sc_tickto.function = hifn_tick; ++ sc->sc_tickto.data = (unsigned long) sc->sc_num; ++ mod_timer(&sc->sc_tickto, jiffies + HZ); ++#endif ++ ++#if 0 /* no code here yet ?? */ ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++#endif ++ ++ return (0); ++ ++fail: ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ ++#if 0 ++ if (sc->sc_dma) { ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ pci_free_consistent(sc->sc_pcidev, ++ sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++ } ++#endif ++ kfree(sc); ++ return (-ENXIO); ++} ++ ++/* ++ * Detach an interface that successfully probed. ++ */ ++static void ++hipp_remove(struct pci_dev *dev) ++{ ++ struct hipp_softc *sc = pci_get_drvdata(dev); ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* disable interrupts */ ++ HIPP_LOCK(sc); ++ ++#if 0 ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); ++ HIFN_UNLOCK(sc); ++ ++ /*XXX other resources */ ++ del_timer_sync(&sc->sc_tickto); ++ ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++#endif ++ ++ crypto_unregister_all(sc->sc_cid); ++ ++ free_irq(sc->sc_irq, sc); ++ ++#if 0 ++ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++#endif ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++static irqreturn_t hipp_intr(int irq, void *arg) ++#else ++static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct hipp_softc *sc = arg; ++ ++ sc = sc; /* shut up compiler */ ++ ++ return IRQ_HANDLED; ++} ++ ++static struct pci_device_id hipp_pci_tbl[] = { ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7855, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++}; ++MODULE_DEVICE_TABLE(pci, hipp_pci_tbl); ++ ++static struct pci_driver hipp_driver = { ++ .name = "hipp", ++ .id_table = hipp_pci_tbl, ++ .probe = hipp_probe, ++ .remove = hipp_remove, ++ /* add PM stuff here one day */ ++}; ++ ++static int __init hipp_init (void) ++{ ++ struct hipp_softc *sc = NULL; ++ int rc; ++ ++ DPRINTF("%s(%p)\n", __FUNCTION__, hipp_init); ++ ++ rc = pci_register_driver(&hipp_driver); ++ pci_register_driver_compat(&hipp_driver, rc); ++ ++ return rc; ++} ++ ++static void __exit hipp_exit (void) ++{ ++ pci_unregister_driver(&hipp_driver); ++} ++ ++module_init(hipp_init); ++module_exit(hipp_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("Michael Richardson "); ++MODULE_DESCRIPTION("OCF driver for hifn HIPP-I/II PCI crypto devices"); +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPreg.h linux-3.0.4/crypto/ocf/hifn/hifnHIPPreg.h +--- linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPreg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/hifnHIPPreg.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,46 @@ ++/*- ++ * Hifn HIPP-I/HIPP-II (7855/8155) driver. ++ * Copyright (c) 2006 Michael Richardson ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored by Hifn inc. ++ * ++ */ ++ ++#ifndef __HIFNHIPP_H__ ++#define __HIFNHIPP_H__ ++ ++/* ++ * PCI vendor and device identifiers ++ */ ++#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ ++#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ ++#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ ++#define PCI_PRODUCT_HIFN_8155 0x999 /* XXX 8155 */ ++ ++#define HIPP_1_REVID 0x01 /* BOGUS */ ++ ++#endif /* __HIPP_H__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPvar.h linux-3.0.4/crypto/ocf/hifn/hifnHIPPvar.h +--- linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPvar.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/hifnHIPPvar.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,93 @@ ++/* ++ * Hifn HIPP-I/HIPP-II (7855/8155) driver. ++ * Copyright (c) 2006 Michael Richardson * ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored by Hifn inc. ++ * ++ */ ++ ++#ifndef __HIFNHIPPVAR_H__ ++#define __HIFNHIPPVAR_H__ ++ ++#define HIPP_MAX_CHIPS 8 ++ ++/* ++ * Holds data specific to a single Hifn HIPP-I board. ++ */ ++struct hipp_softc { ++ softc_device_decl sc_dev; ++ ++ struct pci_dev *sc_pcidev; /* device backpointer */ ++ ocf_iomem_t sc_bar[5]; ++ caddr_t sc_barphy[5]; /* physical address */ ++ int sc_num; /* for multiple devs */ ++ spinlock_t sc_mtx; /* per-instance lock */ ++ int32_t sc_cid; ++ int sc_irq; ++ ++#if 0 ++ ++ u_int32_t sc_dmaier; ++ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ ++ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ ++ ++ struct hifn_dma *sc_dma; ++ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ ++ ++ int sc_dmansegs; ++ int sc_maxses; ++ int sc_nsessions; ++ struct hifn_session *sc_sessions; ++ int sc_ramsize; ++ int sc_flags; ++#define HIFN_HAS_RNG 0x1 /* includes random number generator */ ++#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ ++#define HIFN_HAS_AES 0x4 /* includes AES support */ ++#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ ++#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ ++ ++ struct timer_list sc_tickto; /* for managing DMA */ ++ ++ int sc_rngfirst; ++ int sc_rnghz; /* RNG polling frequency */ ++ ++ int sc_c_busy; /* command ring busy */ ++ int sc_s_busy; /* source data ring busy */ ++ int sc_d_busy; /* destination data ring busy */ ++ int sc_r_busy; /* result ring busy */ ++ int sc_active; /* for initial countdown */ ++ int sc_needwakeup; /* ops q'd wating on resources */ ++ int sc_curbatch; /* # ops submitted w/o int */ ++ int sc_suspended; ++ struct miscdevice sc_miscdev; ++#endif ++}; ++ ++#define HIPP_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) ++#define HIPP_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) ++ ++#endif /* __HIFNHIPPVAR_H__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 linux-3.0.4/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 +--- linux-3.0.4.orig/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1323 @@ ++/* ++ * An OCF module that uses Intels IXP CryptACC API to do the crypto. ++ * This driver requires the IXP400 Access Library that is available ++ * from Intel in order to operate (or compile). ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2007 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#ifndef IX_MBUF_PRIV ++#define IX_MBUF_PRIV(x) ((x)->priv) ++#endif ++ ++struct ixp_data; ++ ++struct ixp_q { ++ struct list_head ixp_q_list; ++ struct ixp_data *ixp_q_data; ++ struct cryptop *ixp_q_crp; ++ struct cryptodesc *ixp_q_ccrd; ++ struct cryptodesc *ixp_q_acrd; ++ IX_MBUF ixp_q_mbuf; ++ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ ++ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ ++ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; ++ unsigned char *ixp_q_iv; ++}; ++ ++struct ixp_data { ++ int ixp_registered; /* is the context registered */ ++ int ixp_crd_flags; /* detect direction changes */ ++ ++ int ixp_cipher_alg; ++ int ixp_auth_alg; ++ ++ UINT32 ixp_ctx_id; ++ UINT32 ixp_hash_key_id; /* used when hashing */ ++ IxCryptoAccCtx ixp_ctx; ++ IX_MBUF ixp_pri_mbuf; ++ IX_MBUF ixp_sec_mbuf; ++ ++ struct work_struct ixp_pending_work; ++ struct work_struct ixp_registration_work; ++ struct list_head ixp_q; /* unprocessed requests */ ++}; ++ ++#ifdef __ixp46X ++ ++#define MAX_IOP_SIZE 64 /* words */ ++#define MAX_OOP_SIZE 128 ++ ++#define MAX_PARAMS 3 ++ ++struct ixp_pkq { ++ struct list_head pkq_list; ++ struct cryptkop *pkq_krp; ++ ++ IxCryptoAccPkeEauInOperands pkq_op; ++ IxCryptoAccPkeEauOpResult pkq_result; ++ ++ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; ++ UINT32 pkq_obuf[MAX_OOP_SIZE]; ++}; ++ ++static LIST_HEAD(ixp_pkq); /* current PK wait list */ ++static struct ixp_pkq *ixp_pk_cur; ++static spinlock_t ixp_pkq_lock; ++ ++#endif /* __ixp46X */ ++ ++static int ixp_blocked = 0; ++ ++static int32_t ixp_id = -1; ++static struct ixp_data **ixp_sessions = NULL; ++static u_int32_t ixp_sesnum = 0; ++ ++static int ixp_process(device_t, struct cryptop *, int); ++static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int ixp_freesession(device_t, u_int64_t); ++#ifdef __ixp46X ++static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); ++#endif ++ ++static struct kmem_cache *qcache; ++ ++#define debug ixp_debug ++static int ixp_debug = 0; ++module_param(ixp_debug, int, 0644); ++MODULE_PARM_DESC(ixp_debug, "Enable debug"); ++ ++static int ixp_init_crypto = 1; ++module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ ++MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); ++ ++static void ixp_process_pending(void *arg); ++static void ixp_registration(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ixp_process_pending_wq(struct work_struct *work); ++static void ixp_registration_wq(struct work_struct *work); ++#endif ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} ixpdev; ++ ++static device_method_t ixp_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, ixp_newsession), ++ DEVMETHOD(cryptodev_freesession,ixp_freesession), ++ DEVMETHOD(cryptodev_process, ixp_process), ++#ifdef __ixp46X ++ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), ++#endif ++}; ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct ixp_data *ixp; ++ u_int32_t i; ++#define AUTH_LEN(cri, def) \ ++ (cri->cri_mlen ? cri->cri_mlen : (def)) ++ ++ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (ixp_sessions) { ++ for (i = 1; i < ixp_sesnum; i++) ++ if (ixp_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (ixp_sessions == NULL || i == ixp_sesnum) { ++ struct ixp_data **ixpd; ++ ++ if (ixp_sessions == NULL) { ++ i = 1; /* We leave ixp_sessions[0] empty */ ++ ixp_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ ixp_sesnum *= 2; ++ ++ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); ++ if (ixpd == NULL) { ++ /* Reset session number */ ++ if (ixp_sesnum == CRYPTO_SW_SESSIONS) ++ ixp_sesnum = 0; ++ else ++ ixp_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); ++ ++ /* Copy existing sessions */ ++ if (ixp_sessions) { ++ memcpy(ixpd, ixp_sessions, ++ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); ++ kfree(ixp_sessions); ++ } ++ ++ ixp_sessions = ixpd; ++ } ++ ++ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), ++ SLAB_ATOMIC); ++ if (ixp_sessions[i] == NULL) { ++ ixp_freesession(NULL, i); ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ ++ *sid = i; ++ ++ ixp = ixp_sessions[i]; ++ memset(ixp, 0, sizeof(*ixp)); ++ ++ ixp->ixp_cipher_alg = -1; ++ ixp->ixp_auth_alg = -1; ++ ixp->ixp_ctx_id = -1; ++ INIT_LIST_HEAD(&ixp->ixp_q); ++ ++ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; ++ ++ while (cri) { ++ switch (cri->cri_alg) { ++ case CRYPTO_DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_3DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_RIJNDAEL128_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only MD5_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_MD5_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only SHA1_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ default: ++ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ cri = cri->cri_next; ++ } ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); ++#else ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); ++#endif ++ ++ return 0; ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++ixp_freesession(device_t dev, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > ixp_sesnum || ixp_sessions == NULL || ++ ixp_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return 0; ++ ++ if (ixp_sessions[sid]) { ++ if (ixp_sessions[sid]->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); ++ ixp_sessions[sid]->ixp_ctx_id = -1; ++ } ++ ++ flush_scheduled_work(); ++ ++ kfree(ixp_sessions[sid]); ++ } ++ ixp_sessions[sid] = NULL; ++ if (ixp_blocked) { ++ ixp_blocked = 0; ++ crypto_unblock(ixp_id, CRYPTO_SYMQ); ++ } ++ return 0; ++} ++ ++ ++/* ++ * callback for when hash processing is complete ++ */ ++ ++static void ++ixp_hash_perform_cb( ++ UINT32 hash_key_id, ++ IX_MBUF *bufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); ++ ++ if (bufp == NULL) { ++ printk("ixp: NULL buf in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(bufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ /* On success, need to copy hash back into original client buffer */ ++ memcpy(q->ixp_hash_dest, q->ixp_hash_src, ++ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? ++ SHA1_HASH_LEN : MD5_HASH_LEN); ++ } ++ else { ++ printk("ixp: hash perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ /* Free internal buffer used for hashing */ ++ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++/* ++ * setup a request and perform it ++ */ ++static void ++ixp_q_process(struct ixp_q *q) ++{ ++ IxCryptoAccStatus status; ++ struct ixp_data *ixp = q->ixp_q_data; ++ int auth_off = 0; ++ int auth_len = 0; ++ int crypt_off = 0; ++ int crypt_len = 0; ++ int icv_off = 0; ++ char *crypt_func; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, q); ++ ++ if (q->ixp_q_ccrd) { ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; ++ } else { ++ q->ixp_q_iv = q->ixp_q_iv_data; ++ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, ++ q->ixp_q_ccrd->crd_inject, ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, ++ (caddr_t) q->ixp_q_iv); ++ } ++ ++ if (q->ixp_q_acrd) { ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ crypt_off = q->ixp_q_ccrd->crd_skip; ++ crypt_len = q->ixp_q_ccrd->crd_len; ++ } else { /* if (q->ixp_q_acrd) */ ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { ++ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle fragmented skb's yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; ++ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { ++ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; ++ if (uiop->uio_iovcnt != 1) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle more than 1 iovec yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; ++ } else /* contig buffer */ { ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; ++ } ++ ++ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; ++ ++ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { ++ /* ++ * For SHA1 and MD5 hash, need to create an internal buffer that is big ++ * enough to hold the original data + the appropriate padding for the ++ * hash algorithm. ++ */ ++ UINT8 *tbuf = NULL; ++ ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = ++ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; ++ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); ++ ++ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { ++ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", ++ IX_MBUF_MLEN(&q->ixp_q_mbuf)); ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); ++ ++ /* Set location in client buffer to copy hash into */ ++ q->ixp_hash_dest = ++ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; ++ ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; ++ ++ /* Set location in internal buffer for where hash starts */ ++ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; ++ ++ crypt_func = "ixCryptoAccHashPerform"; ++ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, ++ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, ++ &ixp->ixp_hash_key_id); ++ } ++ else { ++ crypt_func = "ixCryptoAccAuthCryptPerform"; ++ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, ++ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, ++ q->ixp_q_iv); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("ixp: %s failed %u\n", crypt_func, status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++done: ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * because we cannot process the Q from the Register callback ++ * we do it here on a task Q. ++ */ ++ ++static void ++ixp_process_pending(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, arg); ++ ++ if (!ixp) ++ return; ++ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ ixp_q_process(q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_process_pending_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ++ ixp_pending_work); ++ ixp_process_pending(ixp); ++} ++#endif ++ ++/* ++ * callback for when context registration is complete ++ */ ++ ++static void ++ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) ++{ ++ int i; ++ struct ixp_data *ixp; ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); ++ ++ /* ++ * free any buffer passed in to this routine ++ */ ++ if (bufp) { ++ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; ++ kfree(IX_MBUF_MDATA(bufp)); ++ IX_MBUF_MDATA(bufp) = NULL; ++ } ++ ++ for (i = 0; i < ixp_sesnum; i++) { ++ ixp = ixp_sessions[i]; ++ if (ixp && ixp->ixp_ctx_id == ctx_id) ++ break; ++ } ++ if (i >= ixp_sesnum) { ++ printk("ixp: invalid context id %d\n", ctx_id); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { ++ /* this is normal to free the first of two buffers */ ++ dprintk("ixp: register not finished yet.\n"); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("ixp: register failed 0x%x\n", status); ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++ return; ++ } ++ ++ /* ++ * we are now registered, we cannot start processing the Q here ++ * or we get strange errors with AES (DES/3DES seem to be ok). ++ */ ++ ixp->ixp_registered = 1; ++ schedule_work(&ixp->ixp_pending_work); ++} ++ ++ ++/* ++ * callback for when data processing is complete ++ */ ++ ++static void ++ixp_perform_cb( ++ UINT32 ctx_id, ++ IX_MBUF *sbufp, ++ IX_MBUF *dbufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, ++ dbufp, status); ++ ++ if (sbufp == NULL) { ++ printk("ixp: NULL sbuf in ixp_perform_cb\n"); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(sbufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in ixp_perform_cb\n"); ++ return; ++ } ++ ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ printk("ixp: perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * registration is not callable at IRQ time, so we defer ++ * to a task queue, this routines completes the registration for us ++ * when the task queue runs ++ * ++ * Unfortunately this means we cannot tell OCF that the driver is blocked, ++ * we do that on the next request. ++ */ ++ ++static void ++ixp_registration(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ IX_MBUF *pri = NULL, *sec = NULL; ++ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; ++ ++ if (!ixp) { ++ printk("ixp: ixp_registration with no arg\n"); ++ return; ++ } ++ ++ if (ixp->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); ++ ixp->ixp_ctx_id = -1; ++ } ++ ++ if (list_empty(&ixp->ixp_q)) { ++ printk("ixp: ixp_registration with no Q\n"); ++ return; ++ } ++ ++ /* ++ * setup the primary and secondary buffers ++ */ ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ if (q->ixp_q_acrd) { ++ pri = &ixp->ixp_pri_mbuf; ++ sec = &ixp->ixp_sec_mbuf; ++ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; ++ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; ++ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ } ++ ++ /* Only need to register if a crypt op or HMAC op */ ++ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || ++ ixp->ixp_auth_alg == CRYPTO_MD5)) { ++ status = ixCryptoAccCtxRegister( ++ &ixp->ixp_ctx, ++ pri, sec, ++ ixp_register_cb, ++ ixp_perform_cb, ++ &ixp->ixp_ctx_id); ++ } ++ else { ++ /* Otherwise we start processing pending q */ ++ schedule_work(&ixp->ixp_pending_work); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ return; ++ ++ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { ++ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); ++ ixp_blocked = 1; ++ /* perhaps we should return EGAIN on queued ops ? */ ++ return; ++ } ++ ++ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); ++ ixp->ixp_ctx_id = -1; ++ ++ /* ++ * everything waiting is toasted ++ */ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_registration_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ++ ixp_registration_work); ++ ixp_registration(ixp); ++} ++#endif ++ ++/* ++ * Process a request. ++ */ ++static int ++ixp_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct ixp_data *ixp; ++ unsigned int lid; ++ struct ixp_q *q = NULL; ++ int status; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (ixp_blocked) ++ return ERESTART; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ /* ++ * find the session we are using ++ */ ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || ++ ixp_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ixp = ixp_sessions[lid]; ++ ++ /* ++ * setup a new request ready for queuing ++ */ ++ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); ++ if (q == NULL) { ++ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); ++ crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ /* ++ * save some cycles by only zeroing the important bits ++ */ ++ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); ++ q->ixp_q_ccrd = NULL; ++ q->ixp_q_acrd = NULL; ++ q->ixp_q_crp = crp; ++ q->ixp_q_data = ixp; ++ ++ /* ++ * point the cipher and auth descriptors appropriately ++ * check that we have something to do ++ */ ++ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc; ++ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ if (crp->crp_desc->crd_next) { ++ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc->crd_next; ++ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc->crd_next; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ } ++ ++ /* ++ * If there is a direction change for this context then we mark it as ++ * unregistered and re-register is for the new direction. This is not ++ * a very expensive operation and currently only tends to happen when ++ * user-space application are doing benchmarks ++ * ++ * DM - we should be checking for pending requests before unregistering. ++ */ ++ if (q->ixp_q_ccrd && ixp->ixp_registered && ++ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { ++ dprintk("%s - detected direction change on session\n", __FUNCTION__); ++ ixp->ixp_registered = 0; ++ } ++ ++ /* ++ * if we are registered, call straight into the perform code ++ */ ++ if (ixp->ixp_registered) { ++ ixp_q_process(q); ++ return 0; ++ } ++ ++ /* ++ * the only part of the context not set in newsession is the direction ++ * dependent parts ++ */ ++ if (q->ixp_q_ccrd) { ++ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; ++ } else { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; ++ } ++ } else { ++ /* q->ixp_q_acrd must be set if we are here */ ++ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; ++ } ++ ++ status = list_empty(&ixp->ixp_q); ++ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); ++ if (status) ++ schedule_work(&ixp->ixp_registration_work); ++ return 0; ++ ++done: ++ if (q) ++ kmem_cache_free(qcache, q); ++ crypto_done(crp); ++ return 0; ++} ++ ++ ++#ifdef __ixp46X ++/* ++ * key processing support for the ixp465 ++ */ ++ ++ ++/* ++ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately ++ * assume zeroed and only copy bits that are significant ++ */ ++ ++static int ++ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) ++{ ++ unsigned char *src = (unsigned char *) p->crp_p; ++ unsigned char *dst; ++ int len, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { ++ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, ++ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); ++ return -1; ++ } ++ ++ len = (bits + 31) / 32; /* the number UINT32's needed */ ++ ++ dst = (unsigned char *) &buf[len]; ++ dst--; ++ ++ while (bits > 0) { ++ *dst-- = *src++; ++ bits -= 8; ++ } ++ ++#if 0 /* no need to zero remaining bits as it is done during request alloc */ ++ while (dst > (unsigned char *) buf) ++ *dst-- = '\0'; ++#endif ++ ++ op->pData = buf; ++ op->dataLen = len; ++ return 0; ++} ++ ++/* ++ * copy out the result, be as forgiving as we can about small output buffers ++ */ ++ ++static int ++ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) ++{ ++ unsigned char *dst = (unsigned char *) p->crp_p; ++ unsigned char *src = (unsigned char *) buf; ++ int len, z, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ len = op->dataLen * sizeof(UINT32); ++ ++ /* skip leading zeroes to be small buffer friendly */ ++ z = 0; ++ while (z < len && src[z] == '\0') ++ z++; ++ ++ src += len; ++ src--; ++ len -= z; ++ ++ while (len > 0 && bits > 0) { ++ *dst++ = *src--; ++ len--; ++ bits -= 8; ++ } ++ ++ while (bits > 0) { ++ *dst++ = '\0'; ++ bits -= 8; ++ } ++ ++ if (len > 0) { ++ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", ++ __FUNCTION__, len, z, p->crp_nbits / 8); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * the parameter offsets for exp_mod ++ */ ++ ++#define IXP_PARAM_BASE 0 ++#define IXP_PARAM_EXP 1 ++#define IXP_PARAM_MOD 2 ++#define IXP_PARAM_RES 3 ++ ++/* ++ * key processing complete callback, is also used to start processing ++ * by passing a NULL for pResult ++ */ ++ ++static void ++ixp_kperform_cb( ++ IxCryptoAccPkeEauOperation operation, ++ IxCryptoAccPkeEauOpResult *pResult, ++ BOOL carryOrBorrow, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_pkq *q, *tmp; ++ unsigned long flags; ++ ++ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, ++ carryOrBorrow, status); ++ ++ /* handle a completed request */ ++ if (pResult) { ++ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { ++ q = ixp_pk_cur; ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ } else { ++ /* copy out the result */ ++ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], ++ &q->pkq_result, q->pkq_obuf)) ++ q->pkq_krp->krp_status = ERANGE; ++ } ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ ixp_pk_cur = NULL; ++ } else ++ printk("%s - callback with invalid result pointer\n", __FUNCTION__); ++ } ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ if (ixp_pk_cur || list_empty(&ixp_pkq)) { ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ return; ++ } ++ ++ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { ++ ++ list_del(&q->pkq_list); ++ ixp_pk_cur = q; ++ ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ status = ixCryptoAccPkeEauPerform( ++ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, ++ &q->pkq_op, ++ ixp_kperform_cb, ++ &q->pkq_result); ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); ++ return; /* callback will return here for callback */ ++ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { ++ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); ++ } else { ++ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", ++ __FUNCTION__, status); ++ } ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ } ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++} ++ ++ ++static int ++ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) ++{ ++ struct ixp_pkq *q; ++ int rc = 0; ++ unsigned long flags; ++ ++ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, ++ krp->krp_param[IXP_PARAM_BASE].crp_nbits, ++ krp->krp_param[IXP_PARAM_EXP].crp_nbits, ++ krp->krp_param[IXP_PARAM_MOD].crp_nbits, ++ krp->krp_param[IXP_PARAM_RES].crp_nbits); ++ ++ ++ if (krp->krp_op != CRK_MOD_EXP) { ++ krp->krp_status = EOPNOTSUPP; ++ goto err; ++ } ++ ++ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); ++ if (q == NULL) { ++ krp->krp_status = ENOMEM; ++ goto err; ++ } ++ ++ /* ++ * The PKE engine does not appear to zero the output buffer ++ * appropriately, so we need to do it all here. ++ */ ++ memset(q, 0, sizeof(*q)); ++ ++ q->pkq_krp = krp; ++ INIT_LIST_HEAD(&q->pkq_list); ++ ++ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, ++ q->pkq_ibuf0)) ++ rc = 1; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], ++ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) ++ rc = 2; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], ++ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) ++ rc = 3; ++ ++ if (rc) { ++ kfree(q); ++ krp->krp_status = ERANGE; ++ goto err; ++ } ++ ++ q->pkq_result.pData = q->pkq_obuf; ++ q->pkq_result.dataLen = ++ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ list_add_tail(&q->pkq_list, &ixp_pkq); ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ if (!ixp_pk_cur) ++ ixp_kperform_cb(0, NULL, 0, 0); ++ return (0); ++ ++err: ++ crypto_kdone(krp); ++ return (0); ++} ++ ++ ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++/* ++ * We run the random number generator output through SHA so that it ++ * is FIPS compliant. ++ */ ++ ++static volatile int sha_done = 0; ++static unsigned char sha_digest[20]; ++ ++static void ++ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) ++{ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); ++ if (sha_digest != digest) ++ printk("digest error\n"); ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ sha_done = 1; ++ else ++ sha_done = -status; ++} ++ ++static int ++ixp_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ IxCryptoAccStatus status; ++ int i, n, rc; ++ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); ++ memset(buf, 0, maxwords * sizeof(*buf)); ++ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", ++ __FUNCTION__, status); ++ return 0; ++ } ++ ++ /* ++ * run the random data through SHA to make it look more random ++ */ ++ ++ n = sizeof(sha_digest); /* process digest bytes at a time */ ++ ++ rc = 0; ++ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { ++ if ((maxwords - i) * sizeof(*buf) < n) ++ n = (maxwords - i) * sizeof(*buf); ++ sha_done = 0; ++ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, ++ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); ++ return -EIO; ++ } ++ while (!sha_done) ++ schedule(); ++ if (sha_done < 0) { ++ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); ++ return 0; ++ } ++ memcpy(&buf[i], sha_digest, n); ++ rc += n / sizeof(*buf);; ++ } ++ ++ return rc; ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++#endif /* __ixp46X */ ++ ++ ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++ ++static int ++ixp_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); ++ ++ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) ++ printk("ixCryptoAccInit failed, assuming already initialised!\n"); ++ ++ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, ++ SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ if (!qcache) { ++ printk("failed to create Qcache\n"); ++ return -ENOENT; ++ } ++ ++ memset(&ixpdev, 0, sizeof(ixpdev)); ++ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); ++ ++ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), ++ CRYPTOCAP_F_HARDWARE); ++ if (ixp_id < 0) ++ panic("IXP/OCF crypto device cannot initialize!"); ++ ++#define REGISTER(alg) \ ++ crypto_register(ixp_id,alg,0,0) ++ ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_RIJNDAEL128_CBC); ++#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_SHA1); ++#endif ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++#ifdef __ixp46X ++ spin_lock_init(&ixp_pkq_lock); ++ /* ++ * we do not enable the go fast options here as they can potentially ++ * allow timing based attacks ++ * ++ * http://www.openssl.org/news/secadv_20030219.txt ++ */ ++ ixCryptoAccPkeEauExpConfig(0, 0); ++ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ crypto_rregister(ixp_id, ixp_read_random, NULL); ++#endif ++#endif ++ ++ return 0; ++} ++ ++static void ++ixp_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(ixp_id); ++ ixp_id = -1; ++ kmem_cache_destroy(qcache); ++ qcache = NULL; ++} ++ ++module_init(ixp_init); ++module_exit(ixp_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/ixp4xx/Makefile linux-3.0.4/crypto/ocf/ixp4xx/Makefile +--- linux-3.0.4.orig/crypto/ocf/ixp4xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ixp4xx/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,104 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++# ++# You will need to point this at your Intel ixp425 includes, this portion ++# of the Makefile only really works under SGLinux with the appropriate libs ++# installed. They can be downloaded from http://www.snapgear.org/ ++# ++ifeq ($(CONFIG_CPU_IXP46X),y) ++IXPLATFORM = ixp46X ++else ++ifeq ($(CONFIG_CPU_IXP43X),y) ++IXPLATFORM = ixp43X ++else ++IXPLATFORM = ixp42X ++endif ++endif ++ ++ifdef CONFIG_IXP400_LIB_2_4 ++IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp400_xscale_sw ++OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp_osal ++endif ++ifdef CONFIG_IXP400_LIB_2_1 ++IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp400_xscale_sw ++OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp_osal ++endif ++ifdef CONFIG_IXP400_LIB_2_0 ++IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp400_xscale_sw ++OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp_osal ++endif ++ifdef IX_XSCALE_SW ++ifdef CONFIG_IXP400_LIB_2_4 ++IXP_CFLAGS = \ ++ -I$(ROOTDIR)/. \ ++ -I$(IX_XSCALE_SW)/src/include \ ++ -I$(OSAL_DIR)/common/include/ \ ++ -I$(OSAL_DIR)/common/include/modules/ \ ++ -I$(OSAL_DIR)/common/include/modules/ddk/ \ ++ -I$(OSAL_DIR)/common/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/common/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/core/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/ddk/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/include/ \ ++ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/os/linux/include/ \ ++ -DENABLE_IOMEM -DENABLE_BUFFERMGT -DENABLE_DDK \ ++ -DUSE_IXP4XX_CRYPTO ++else ++IXP_CFLAGS = \ ++ -I$(ROOTDIR)/. \ ++ -I$(IX_XSCALE_SW)/src/include \ ++ -I$(OSAL_DIR)/ \ ++ -I$(OSAL_DIR)/os/linux/include/ \ ++ -I$(OSAL_DIR)/os/linux/include/modules/ \ ++ -I$(OSAL_DIR)/os/linux/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/os/linux/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/os/linux/include/core/ \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp425 \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp465 \ ++ -I$(OSAL_DIR)/os/linux/include/core/ \ ++ -I$(OSAL_DIR)/include/ \ ++ -I$(OSAL_DIR)/include/modules/ \ ++ -I$(OSAL_DIR)/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/include/platforms/ \ ++ -I$(OSAL_DIR)/include/platforms/ixp400/ \ ++ -DUSE_IXP4XX_CRYPTO ++endif ++endif ++ifdef CONFIG_IXP400_LIB_1_4 ++IXP_CFLAGS = \ ++ -I$(ROOTDIR)/. \ ++ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/include \ ++ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/linux \ ++ -DUSE_IXP4XX_CRYPTO ++endif ++ifndef IXPDIR ++IXPDIR = ixp-version-is-not-supported ++endif ++ ++ifeq ($(CONFIG_CPU_IXP46X),y) ++IXP_CFLAGS += -D__ixp46X ++else ++ifeq ($(CONFIG_CPU_IXP43X),y) ++IXP_CFLAGS += -D__ixp43X ++else ++IXP_CFLAGS += -D__ixp42X ++endif ++endif ++ ++obj-$(CONFIG_OCF_IXP4XX) += ixp4xx.o ++ ++obj ?= . ++EXTRA_CFLAGS += $(IXP_CFLAGS) -I$(obj)/.. -I$(obj)/. ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/ixp4xx/ixp4xx.c linux-3.0.4/crypto/ocf/ixp4xx/ixp4xx.c +--- linux-3.0.4.orig/crypto/ocf/ixp4xx/ixp4xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ixp4xx/ixp4xx.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1339 @@ ++/* ++ * An OCF module that uses Intels IXP CryptACC API to do the crypto. ++ * This driver requires the IXP400 Access Library that is available ++ * from Intel in order to operate (or compile). ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2011 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#ifndef IX_MBUF_PRIV ++#define IX_MBUF_PRIV(x) ((x)->priv) ++#endif ++ ++struct ixp_data; ++ ++struct ixp_q { ++ struct list_head ixp_q_list; ++ struct ixp_data *ixp_q_data; ++ struct cryptop *ixp_q_crp; ++ struct cryptodesc *ixp_q_ccrd; ++ struct cryptodesc *ixp_q_acrd; ++ IX_MBUF ixp_q_mbuf; ++ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ ++ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ ++ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; ++ unsigned char *ixp_q_iv; ++}; ++ ++struct ixp_data { ++ int ixp_registered; /* is the context registered */ ++ int ixp_crd_flags; /* detect direction changes */ ++ ++ int ixp_cipher_alg; ++ int ixp_auth_alg; ++ ++ UINT32 ixp_ctx_id; ++ UINT32 ixp_hash_key_id; /* used when hashing */ ++ IxCryptoAccCtx ixp_ctx; ++ IX_MBUF ixp_pri_mbuf; ++ IX_MBUF ixp_sec_mbuf; ++ ++ struct work_struct ixp_pending_work; ++ struct work_struct ixp_registration_work; ++ struct list_head ixp_q; /* unprocessed requests */ ++}; ++ ++#ifdef __ixp46X ++ ++#define MAX_IOP_SIZE 64 /* words */ ++#define MAX_OOP_SIZE 128 ++ ++#define MAX_PARAMS 3 ++ ++struct ixp_pkq { ++ struct list_head pkq_list; ++ struct cryptkop *pkq_krp; ++ ++ IxCryptoAccPkeEauInOperands pkq_op; ++ IxCryptoAccPkeEauOpResult pkq_result; ++ ++ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; ++ UINT32 pkq_obuf[MAX_OOP_SIZE]; ++}; ++ ++static LIST_HEAD(ixp_pkq); /* current PK wait list */ ++static struct ixp_pkq *ixp_pk_cur; ++static spinlock_t ixp_pkq_lock; ++ ++#endif /* __ixp46X */ ++ ++static int ixp_blocked = 0; ++ ++static int32_t ixp_id = -1; ++static struct ixp_data **ixp_sessions = NULL; ++static u_int32_t ixp_sesnum = 0; ++ ++static int ixp_process(device_t, struct cryptop *, int); ++static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int ixp_freesession(device_t, u_int64_t); ++#ifdef __ixp46X ++static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++static kmem_cache_t *qcache; ++#else ++static struct kmem_cache *qcache; ++#endif ++ ++#define debug ixp_debug ++static int ixp_debug = 0; ++module_param(ixp_debug, int, 0644); ++MODULE_PARM_DESC(ixp_debug, "Enable debug"); ++ ++static int ixp_init_crypto = 1; ++module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ ++MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); ++ ++static void ixp_process_pending(void *arg); ++static void ixp_registration(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ixp_process_pending_wq(struct work_struct *work); ++static void ixp_registration_wq(struct work_struct *work); ++#endif ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} ixpdev; ++ ++static device_method_t ixp_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, ixp_newsession), ++ DEVMETHOD(cryptodev_freesession,ixp_freesession), ++ DEVMETHOD(cryptodev_process, ixp_process), ++#ifdef __ixp46X ++ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), ++#endif ++}; ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct ixp_data *ixp; ++ u_int32_t i; ++#define AUTH_LEN(cri, def) \ ++ (cri->cri_mlen ? cri->cri_mlen : (def)) ++ ++ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (ixp_sessions) { ++ for (i = 1; i < ixp_sesnum; i++) ++ if (ixp_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (ixp_sessions == NULL || i == ixp_sesnum) { ++ struct ixp_data **ixpd; ++ ++ if (ixp_sessions == NULL) { ++ i = 1; /* We leave ixp_sessions[0] empty */ ++ ixp_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ ixp_sesnum *= 2; ++ ++ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); ++ if (ixpd == NULL) { ++ /* Reset session number */ ++ if (ixp_sesnum == CRYPTO_SW_SESSIONS) ++ ixp_sesnum = 0; ++ else ++ ixp_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); ++ ++ /* Copy existing sessions */ ++ if (ixp_sessions) { ++ memcpy(ixpd, ixp_sessions, ++ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); ++ kfree(ixp_sessions); ++ } ++ ++ ixp_sessions = ixpd; ++ } ++ ++ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), ++ SLAB_ATOMIC); ++ if (ixp_sessions[i] == NULL) { ++ ixp_freesession(NULL, i); ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ ++ *sid = i; ++ ++ ixp = ixp_sessions[i]; ++ memset(ixp, 0, sizeof(*ixp)); ++ ++ ixp->ixp_cipher_alg = -1; ++ ixp->ixp_auth_alg = -1; ++ ixp->ixp_ctx_id = -1; ++ INIT_LIST_HEAD(&ixp->ixp_q); ++ ++ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; ++ ++ while (cri) { ++ switch (cri->cri_alg) { ++ case CRYPTO_DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_3DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_RIJNDAEL128_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only MD5_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_MD5_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only SHA1_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ default: ++ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ cri = cri->cri_next; ++ } ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); ++#else ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); ++#endif ++ ++ return 0; ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++ixp_freesession(device_t dev, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > ixp_sesnum || ixp_sessions == NULL || ++ ixp_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return 0; ++ ++ if (ixp_sessions[sid]) { ++ if (ixp_sessions[sid]->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); ++ ixp_sessions[sid]->ixp_ctx_id = -1; ++ } ++ kfree(ixp_sessions[sid]); ++ } ++ ixp_sessions[sid] = NULL; ++ if (ixp_blocked) { ++ ixp_blocked = 0; ++ crypto_unblock(ixp_id, CRYPTO_SYMQ); ++ } ++ return 0; ++} ++ ++ ++/* ++ * callback for when hash processing is complete ++ */ ++ ++static void ++ixp_hash_perform_cb( ++ UINT32 hash_key_id, ++ IX_MBUF *bufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); ++ ++ if (bufp == NULL) { ++ printk("ixp: NULL buf in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(bufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ /* On success, need to copy hash back into original client buffer */ ++ memcpy(q->ixp_hash_dest, q->ixp_hash_src, ++ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? ++ SHA1_HASH_LEN : MD5_HASH_LEN); ++ } ++ else { ++ printk("ixp: hash perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ /* Free internal buffer used for hashing */ ++ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++/* ++ * setup a request and perform it ++ */ ++static void ++ixp_q_process(struct ixp_q *q) ++{ ++ IxCryptoAccStatus status; ++ struct ixp_data *ixp = q->ixp_q_data; ++ int auth_off = 0; ++ int auth_len = 0; ++ int crypt_off = 0; ++ int crypt_len = 0; ++ int icv_off = 0; ++ char *crypt_func; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, q); ++ ++ if (q->ixp_q_ccrd) { ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; ++ } else { ++ q->ixp_q_iv = q->ixp_q_iv_data; ++ read_random(q->ixp_q_iv, ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen); ++ } ++ if ((q->ixp_q_ccrd->crd_flags & CRD_F_IV_PRESENT) == 0) ++ crypto_copyback(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, ++ q->ixp_q_ccrd->crd_inject, ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, ++ (caddr_t) q->ixp_q_iv); ++ } else { ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; ++ else { ++ q->ixp_q_iv = q->ixp_q_iv_data; ++ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, ++ q->ixp_q_ccrd->crd_inject, ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, ++ (caddr_t) q->ixp_q_iv); ++ } ++ } ++ ++ if (q->ixp_q_acrd) { ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ crypt_off = q->ixp_q_ccrd->crd_skip; ++ crypt_len = q->ixp_q_ccrd->crd_len; ++ } else { /* if (q->ixp_q_acrd) */ ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { ++ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle fragmented skb's yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; ++ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { ++ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; ++ if (uiop->uio_iovcnt != 1) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle more than 1 iovec yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; ++ } else /* contig buffer */ { ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; ++ } ++ ++ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; ++ ++ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { ++ /* ++ * For SHA1 and MD5 hash, need to create an internal buffer that is big ++ * enough to hold the original data + the appropriate padding for the ++ * hash algorithm. ++ */ ++ UINT8 *tbuf = NULL; ++ ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = ++ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; ++ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); ++ ++ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { ++ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", ++ IX_MBUF_MLEN(&q->ixp_q_mbuf)); ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); ++ ++ /* Set location in client buffer to copy hash into */ ++ q->ixp_hash_dest = ++ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; ++ ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; ++ ++ /* Set location in internal buffer for where hash starts */ ++ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; ++ ++ crypt_func = "ixCryptoAccHashPerform"; ++ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, ++ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, ++ &ixp->ixp_hash_key_id); ++ } ++ else { ++ crypt_func = "ixCryptoAccAuthCryptPerform"; ++ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, ++ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, ++ q->ixp_q_iv); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ return; ++ ++ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ ++ printk("ixp: %s failed %u\n", crypt_func, status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ ++done: ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * because we cannot process the Q from the Register callback ++ * we do it here on a task Q. ++ */ ++ ++static void ++ixp_process_pending(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, arg); ++ ++ if (!ixp) ++ return; ++ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ ixp_q_process(q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_process_pending_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ixp_pending_work); ++ ixp_process_pending(ixp); ++} ++#endif ++ ++/* ++ * callback for when context registration is complete ++ */ ++ ++static void ++ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) ++{ ++ int i; ++ struct ixp_data *ixp; ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); ++ ++ /* ++ * free any buffer passed in to this routine ++ */ ++ if (bufp) { ++ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; ++ kfree(IX_MBUF_MDATA(bufp)); ++ IX_MBUF_MDATA(bufp) = NULL; ++ } ++ ++ for (i = 0; i < ixp_sesnum; i++) { ++ ixp = ixp_sessions[i]; ++ if (ixp && ixp->ixp_ctx_id == ctx_id) ++ break; ++ } ++ if (i >= ixp_sesnum) { ++ printk("ixp: invalid context id %d\n", ctx_id); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { ++ /* this is normal to free the first of two buffers */ ++ dprintk("ixp: register not finished yet.\n"); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("ixp: register failed 0x%x\n", status); ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++ return; ++ } ++ ++ /* ++ * we are now registered, we cannot start processing the Q here ++ * or we get strange errors with AES (DES/3DES seem to be ok). ++ */ ++ ixp->ixp_registered = 1; ++ schedule_work(&ixp->ixp_pending_work); ++} ++ ++ ++/* ++ * callback for when data processing is complete ++ */ ++ ++static void ++ixp_perform_cb( ++ UINT32 ctx_id, ++ IX_MBUF *sbufp, ++ IX_MBUF *dbufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, ++ dbufp, status); ++ ++ if (sbufp == NULL) { ++ printk("ixp: NULL sbuf in ixp_perform_cb\n"); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(sbufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in ixp_perform_cb\n"); ++ return; ++ } ++ ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ printk("ixp: perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * registration is not callable at IRQ time, so we defer ++ * to a task queue, this routines completes the registration for us ++ * when the task queue runs ++ * ++ * Unfortunately this means we cannot tell OCF that the driver is blocked, ++ * we do that on the next request. ++ */ ++ ++static void ++ixp_registration(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ IX_MBUF *pri = NULL, *sec = NULL; ++ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; ++ ++ if (!ixp) { ++ printk("ixp: ixp_registration with no arg\n"); ++ return; ++ } ++ ++ if (ixp->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); ++ ixp->ixp_ctx_id = -1; ++ } ++ ++ if (list_empty(&ixp->ixp_q)) { ++ printk("ixp: ixp_registration with no Q\n"); ++ return; ++ } ++ ++ /* ++ * setup the primary and secondary buffers ++ */ ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ if (q->ixp_q_acrd) { ++ pri = &ixp->ixp_pri_mbuf; ++ sec = &ixp->ixp_sec_mbuf; ++ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; ++ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; ++ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ } ++ ++ /* Only need to register if a crypt op or HMAC op */ ++ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || ++ ixp->ixp_auth_alg == CRYPTO_MD5)) { ++ status = ixCryptoAccCtxRegister( ++ &ixp->ixp_ctx, ++ pri, sec, ++ ixp_register_cb, ++ ixp_perform_cb, ++ &ixp->ixp_ctx_id); ++ } ++ else { ++ /* Otherwise we start processing pending q */ ++ schedule_work(&ixp->ixp_pending_work); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ return; ++ ++ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { ++ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); ++ ixp_blocked = 1; ++ /* perhaps we should return EGAIN on queued ops ? */ ++ return; ++ } ++ ++ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); ++ ixp->ixp_ctx_id = -1; ++ ++ /* ++ * everything waiting is toasted ++ */ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_registration_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ++ ixp_registration_work); ++ ixp_registration(ixp); ++} ++#endif ++ ++/* ++ * Process a request. ++ */ ++static int ++ixp_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct ixp_data *ixp; ++ unsigned int lid; ++ struct ixp_q *q = NULL; ++ int status; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (ixp_blocked) ++ return ERESTART; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ /* ++ * find the session we are using ++ */ ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || ++ ixp_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ixp = ixp_sessions[lid]; ++ ++ /* ++ * setup a new request ready for queuing ++ */ ++ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); ++ if (q == NULL) { ++ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); ++ crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ /* ++ * save some cycles by only zeroing the important bits ++ */ ++ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); ++ q->ixp_q_ccrd = NULL; ++ q->ixp_q_acrd = NULL; ++ q->ixp_q_crp = crp; ++ q->ixp_q_data = ixp; ++ ++ /* ++ * point the cipher and auth descriptors appropriately ++ * check that we have something to do ++ */ ++ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc; ++ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ if (crp->crp_desc->crd_next) { ++ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc->crd_next; ++ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc->crd_next; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ } ++ ++ /* ++ * If there is a direction change for this context then we mark it as ++ * unregistered and re-register is for the new direction. This is not ++ * a very expensive operation and currently only tends to happen when ++ * user-space application are doing benchmarks ++ * ++ * DM - we should be checking for pending requests before unregistering. ++ */ ++ if (q->ixp_q_ccrd && ixp->ixp_registered && ++ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { ++ dprintk("%s - detected direction change on session\n", __FUNCTION__); ++ ixp->ixp_registered = 0; ++ } ++ ++ /* ++ * if we are registered, call straight into the perform code ++ */ ++ if (ixp->ixp_registered) { ++ ixp_q_process(q); ++ return 0; ++ } ++ ++ /* ++ * the only part of the context not set in newsession is the direction ++ * dependent parts ++ */ ++ if (q->ixp_q_ccrd) { ++ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; ++ } else { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; ++ } ++ } else { ++ /* q->ixp_q_acrd must be set if we are here */ ++ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; ++ } ++ ++ status = list_empty(&ixp->ixp_q); ++ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); ++ if (status) ++ schedule_work(&ixp->ixp_registration_work); ++ return 0; ++ ++done: ++ if (q) ++ kmem_cache_free(qcache, q); ++ crypto_done(crp); ++ return 0; ++} ++ ++ ++#ifdef __ixp46X ++/* ++ * key processing support for the ixp465 ++ */ ++ ++ ++/* ++ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately ++ * assume zeroed and only copy bits that are significant ++ */ ++ ++static int ++ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) ++{ ++ unsigned char *src = (unsigned char *) p->crp_p; ++ unsigned char *dst; ++ int len, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { ++ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, ++ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); ++ return -1; ++ } ++ ++ len = (bits + 31) / 32; /* the number UINT32's needed */ ++ ++ dst = (unsigned char *) &buf[len]; ++ dst--; ++ ++ while (bits > 0) { ++ *dst-- = *src++; ++ bits -= 8; ++ } ++ ++#if 0 /* no need to zero remaining bits as it is done during request alloc */ ++ while (dst > (unsigned char *) buf) ++ *dst-- = '\0'; ++#endif ++ ++ op->pData = buf; ++ op->dataLen = len; ++ return 0; ++} ++ ++/* ++ * copy out the result, be as forgiving as we can about small output buffers ++ */ ++ ++static int ++ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) ++{ ++ unsigned char *dst = (unsigned char *) p->crp_p; ++ unsigned char *src = (unsigned char *) buf; ++ int len, z, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ len = op->dataLen * sizeof(UINT32); ++ ++ /* skip leading zeroes to be small buffer friendly */ ++ z = 0; ++ while (z < len && src[z] == '\0') ++ z++; ++ ++ src += len; ++ src--; ++ len -= z; ++ ++ while (len > 0 && bits > 0) { ++ *dst++ = *src--; ++ len--; ++ bits -= 8; ++ } ++ ++ while (bits > 0) { ++ *dst++ = '\0'; ++ bits -= 8; ++ } ++ ++ if (len > 0) { ++ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", ++ __FUNCTION__, len, z, p->crp_nbits / 8); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * the parameter offsets for exp_mod ++ */ ++ ++#define IXP_PARAM_BASE 0 ++#define IXP_PARAM_EXP 1 ++#define IXP_PARAM_MOD 2 ++#define IXP_PARAM_RES 3 ++ ++/* ++ * key processing complete callback, is also used to start processing ++ * by passing a NULL for pResult ++ */ ++ ++static void ++ixp_kperform_cb( ++ IxCryptoAccPkeEauOperation operation, ++ IxCryptoAccPkeEauOpResult *pResult, ++ BOOL carryOrBorrow, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_pkq *q, *tmp; ++ unsigned long flags; ++ ++ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, ++ carryOrBorrow, status); ++ ++ /* handle a completed request */ ++ if (pResult) { ++ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { ++ q = ixp_pk_cur; ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ } else { ++ /* copy out the result */ ++ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], ++ &q->pkq_result, q->pkq_obuf)) ++ q->pkq_krp->krp_status = ERANGE; ++ } ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ ixp_pk_cur = NULL; ++ } else ++ printk("%s - callback with invalid result pointer\n", __FUNCTION__); ++ } ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ if (ixp_pk_cur || list_empty(&ixp_pkq)) { ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ return; ++ } ++ ++ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { ++ ++ list_del(&q->pkq_list); ++ ixp_pk_cur = q; ++ ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ status = ixCryptoAccPkeEauPerform( ++ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, ++ &q->pkq_op, ++ ixp_kperform_cb, ++ &q->pkq_result); ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); ++ return; /* callback will return here for callback */ ++ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { ++ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); ++ } else { ++ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", ++ __FUNCTION__, status); ++ } ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ } ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++} ++ ++ ++static int ++ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) ++{ ++ struct ixp_pkq *q; ++ int rc = 0; ++ unsigned long flags; ++ ++ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, ++ krp->krp_param[IXP_PARAM_BASE].crp_nbits, ++ krp->krp_param[IXP_PARAM_EXP].crp_nbits, ++ krp->krp_param[IXP_PARAM_MOD].crp_nbits, ++ krp->krp_param[IXP_PARAM_RES].crp_nbits); ++ ++ ++ if (krp->krp_op != CRK_MOD_EXP) { ++ krp->krp_status = EOPNOTSUPP; ++ goto err; ++ } ++ ++ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); ++ if (q == NULL) { ++ krp->krp_status = ENOMEM; ++ goto err; ++ } ++ ++ /* ++ * The PKE engine does not appear to zero the output buffer ++ * appropriately, so we need to do it all here. ++ */ ++ memset(q, 0, sizeof(*q)); ++ ++ q->pkq_krp = krp; ++ INIT_LIST_HEAD(&q->pkq_list); ++ ++ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, ++ q->pkq_ibuf0)) ++ rc = 1; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], ++ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) ++ rc = 2; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], ++ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) ++ rc = 3; ++ ++ if (rc) { ++ kfree(q); ++ krp->krp_status = ERANGE; ++ goto err; ++ } ++ ++ q->pkq_result.pData = q->pkq_obuf; ++ q->pkq_result.dataLen = ++ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ list_add_tail(&q->pkq_list, &ixp_pkq); ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ if (!ixp_pk_cur) ++ ixp_kperform_cb(0, NULL, 0, 0); ++ return (0); ++ ++err: ++ crypto_kdone(krp); ++ return (0); ++} ++ ++ ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++/* ++ * We run the random number generator output through SHA so that it ++ * is FIPS compliant. ++ */ ++ ++static volatile int sha_done = 0; ++static unsigned char sha_digest[20]; ++ ++static void ++ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) ++{ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); ++ if (sha_digest != digest) ++ printk("digest error\n"); ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ sha_done = 1; ++ else ++ sha_done = -status; ++} ++ ++static int ++ixp_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ IxCryptoAccStatus status; ++ int i, n, rc; ++ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); ++ memset(buf, 0, maxwords * sizeof(*buf)); ++ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", ++ __FUNCTION__, status); ++ return 0; ++ } ++ ++ /* ++ * run the random data through SHA to make it look more random ++ */ ++ ++ n = sizeof(sha_digest); /* process digest bytes at a time */ ++ ++ rc = 0; ++ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { ++ if ((maxwords - i) * sizeof(*buf) < n) ++ n = (maxwords - i) * sizeof(*buf); ++ sha_done = 0; ++ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, ++ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); ++ return -EIO; ++ } ++ while (!sha_done) ++ schedule(); ++ if (sha_done < 0) { ++ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); ++ return 0; ++ } ++ memcpy(&buf[i], sha_digest, n); ++ rc += n / sizeof(*buf);; ++ } ++ ++ return rc; ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++#endif /* __ixp46X */ ++ ++ ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++ ++static int ++ixp_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); ++ ++ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) ++ printk("ixCryptoAccInit failed, assuming already initialised!\n"); ++ ++ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, ++ SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ if (!qcache) { ++ printk("failed to create Qcache\n"); ++ return -ENOENT; ++ } ++ ++ memset(&ixpdev, 0, sizeof(ixpdev)); ++ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); ++ ++ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), ++ CRYPTOCAP_F_HARDWARE); ++ if (ixp_id < 0) ++ panic("IXP/OCF crypto device cannot initialize!"); ++ ++#define REGISTER(alg) \ ++ crypto_register(ixp_id,alg,0,0) ++ ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_RIJNDAEL128_CBC); ++#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_SHA1); ++#endif ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++#ifdef __ixp46X ++ spin_lock_init(&ixp_pkq_lock); ++ /* ++ * we do not enable the go fast options here as they can potentially ++ * allow timing based attacks ++ * ++ * http://www.openssl.org/news/secadv_20030219.txt ++ */ ++ ixCryptoAccPkeEauExpConfig(0, 0); ++ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ crypto_rregister(ixp_id, ixp_read_random, NULL); ++#endif ++#endif ++ ++ return 0; ++} ++ ++static void ++ixp_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(ixp_id); ++ ixp_id = -1; ++ kmem_cache_destroy(qcache); ++ qcache = NULL; ++} ++ ++module_init(ixp_init); ++module_exit(ixp_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/Makefile linux-3.0.4/crypto/ocf/kirkwood/Makefile +--- linux-3.0.4.orig/crypto/ocf/kirkwood/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,19 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_KIRKWOOD) += mv_cesa.o ++ ++mv_cesa-y := cesa/mvCesa.o cesa/mvLru.o cesa/mvMD5.o cesa/mvSHA1.o cesa/AES/mvAesAlg.o cesa/AES/mvAesApi.o cesa/mvCesaDebug.o cesa_ocf_drv.o ++ ++# Extra objects required by the CESA driver ++mv_cesa-y += mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.o mvHal/kw_family/boardEnv/mvBoardEnvLib.o mvHal/mv_hal/twsi/mvTwsi.o mvHal/kw_family/ctrlEnv/sys/mvCpuIf.o mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.o mvHal/kw_family/ctrlEnv/sys/mvSysDram.o mvHal/linux_oss/mvOs.o mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.o mvHal/mv_hal/gpp/mvGpp.o mvHal/kw_family/ctrlEnv/sys/mvSysPex.o mvHal/mv_hal/pex/mvPex.o mvHal/kw_family/boardEnv/mvBoardEnvSpec.o mvHal/common/mvCommon.o mvHal/common/mvDebug.o mvHal/kw_family/ctrlEnv/sys/mvSysCesa.o ++ ++ifdef src ++EXTRA_CFLAGS += -I$(src)/.. -I$(src)/cesa -I$(src)/mvHal -I$(src)/mvHal/common -I$(src)/mvHal/kw_family -I$(src)/mvHal/mv_hal -I$(src)/mvHal/linux_oss -I$(src) ++endif ++ ++EXTRA_CFLAGS += -DMV_LINUX -DMV_CPU_LE -DMV_ARM -DMV_INCLUDE_CESA -DMV_INCLUDE_PEX -DMV_CACHE_COHERENCY=3 ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAes.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAes.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,62 @@ ++/* mvAes.h v2.0 August '99 ++ * Reference ANSI C code ++ */ ++ ++/* AES Cipher header file for ANSI C Submissions ++ Lawrence E. Bassham III ++ Computer Security Division ++ National Institute of Standards and Technology ++ ++ April 15, 1998 ++ ++ This sample is to assist implementers developing to the Cryptographic ++API Profile for AES Candidate Algorithm Submissions. Please consult this ++document as a cross-reference. ++ ++ ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE ++MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH ++THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT ++BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE ++IMPLEMENTATION SPECIFIC INFORMATION. ++*/ ++ ++/* Includes: ++ Standard include files ++*/ ++ ++#include "mvOs.h" ++ ++ ++/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */ ++ ++/* Key direction is invalid, e.g., unknown value */ ++#define AES_BAD_KEY_DIR -1 ++ ++/* Key material not of correct length */ ++#define AES_BAD_KEY_MAT -2 ++ ++/* Key passed is not valid */ ++#define AES_BAD_KEY_INSTANCE -3 ++ ++/* Params struct passed to cipherInit invalid */ ++#define AES_BAD_CIPHER_MODE -4 ++ ++/* Cipher in wrong state (e.g., not initialized) */ ++#define AES_BAD_CIPHER_STATE -5 ++ ++#define AES_BAD_CIPHER_INSTANCE -7 ++ ++ ++/* Function protoypes */ ++/* CHANGED: makeKey(): parameter blockLen added ++ this parameter is absolutely necessary if you want to ++ setup the round keys in a variable block length setting ++ cipherInit(): parameter blockLen added (for obvious reasons) ++ */ ++int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen); ++int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, ++ MV_U32 *plain, int numBlocks, MV_U32 *cipher); ++int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, ++ MV_U32 *plain, int numBlocks, MV_U32 *cipher); ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,317 @@ ++/* rijndael-alg-ref.c v2.0 August '99 ++ * Reference ANSI C code ++ * authors: Paulo Barreto ++ * Vincent Rijmen, K.U.Leuven ++ * ++ * This code is placed in the public domain. ++ */ ++ ++#include "mvOs.h" ++ ++#include "mvAesAlg.h" ++ ++#include "mvAesBoxes.dat" ++ ++ ++MV_U8 mul1(MV_U8 aa, MV_U8 bb); ++void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); ++void ShiftRow128Enc(MV_U8 a[4][MAXBC]); ++void ShiftRow128Dec(MV_U8 a[4][MAXBC]); ++void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); ++void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); ++void InvMixColumn(MV_U8 a[4][MAXBC]); ++ ++ ++#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) ++ ++MV_U8 mul1(MV_U8 aa, MV_U8 bb) ++{ ++ return mask[bb] & Alogtable[aa + Logtable[bb]]; ++} ++ ++ ++void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) ++{ ++ /* Exor corresponding text input and round key input bytes ++ */ ++ ((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0]; ++ ((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0]; ++ ((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0]; ++ ((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0]; ++ ++} ++ ++void ShiftRow128Enc(MV_U8 a[4][MAXBC]) { ++ /* Row 0 remains unchanged ++ * The other three rows are shifted a variable amount ++ */ ++ MV_U8 tmp[MAXBC]; ++ ++ tmp[0] = a[1][1]; ++ tmp[1] = a[1][2]; ++ tmp[2] = a[1][3]; ++ tmp[3] = a[1][0]; ++ ++ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[1][0] = tmp[0]; ++ a[1][1] = tmp[1]; ++ a[1][2] = tmp[2]; ++ a[1][3] = tmp[3]; ++ */ ++ tmp[0] = a[2][2]; ++ tmp[1] = a[2][3]; ++ tmp[2] = a[2][0]; ++ tmp[3] = a[2][1]; ++ ++ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[2][0] = tmp[0]; ++ a[2][1] = tmp[1]; ++ a[2][2] = tmp[2]; ++ a[2][3] = tmp[3]; ++ */ ++ tmp[0] = a[3][3]; ++ tmp[1] = a[3][0]; ++ tmp[2] = a[3][1]; ++ tmp[3] = a[3][2]; ++ ++ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[3][0] = tmp[0]; ++ a[3][1] = tmp[1]; ++ a[3][2] = tmp[2]; ++ a[3][3] = tmp[3]; ++ */ ++} ++ ++void ShiftRow128Dec(MV_U8 a[4][MAXBC]) { ++ /* Row 0 remains unchanged ++ * The other three rows are shifted a variable amount ++ */ ++ MV_U8 tmp[MAXBC]; ++ ++ tmp[0] = a[1][3]; ++ tmp[1] = a[1][0]; ++ tmp[2] = a[1][1]; ++ tmp[3] = a[1][2]; ++ ++ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[1][0] = tmp[0]; ++ a[1][1] = tmp[1]; ++ a[1][2] = tmp[2]; ++ a[1][3] = tmp[3]; ++ */ ++ ++ tmp[0] = a[2][2]; ++ tmp[1] = a[2][3]; ++ tmp[2] = a[2][0]; ++ tmp[3] = a[2][1]; ++ ++ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[2][0] = tmp[0]; ++ a[2][1] = tmp[1]; ++ a[2][2] = tmp[2]; ++ a[2][3] = tmp[3]; ++ */ ++ ++ tmp[0] = a[3][1]; ++ tmp[1] = a[3][2]; ++ tmp[2] = a[3][3]; ++ tmp[3] = a[3][0]; ++ ++ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[3][0] = tmp[0]; ++ a[3][1] = tmp[1]; ++ a[3][2] = tmp[2]; ++ a[3][3] = tmp[3]; ++ */ ++} ++ ++void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) { ++ /* Replace every byte of the input by the byte at that place ++ * in the nonlinear S-box ++ */ ++ int i, j; ++ ++ for(i = 0; i < 4; i++) ++ for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ; ++} ++ ++void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) { ++ /* Mix the four bytes of every column in a linear way ++ */ ++ MV_U8 b[4][MAXBC]; ++ int i, j; ++ ++ for(j = 0; j < 4; j++){ ++ b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j]; ++ b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j]; ++ b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j]; ++ b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j]; ++ } ++ for(i = 0; i < 4; i++) ++ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ ++ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; ++} ++ ++void InvMixColumn(MV_U8 a[4][MAXBC]) { ++ /* Mix the four bytes of every column in a linear way ++ * This is the opposite operation of Mixcolumn ++ */ ++ MV_U8 b[4][MAXBC]; ++ int i, j; ++ ++ for(j = 0; j < 4; j++){ ++ b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]); ++ b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]); ++ b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]); ++ b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]); ++ } ++ for(i = 0; i < 4; i++) ++ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ ++ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0]; ++} ++ ++int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC]) ++{ ++ /* Calculate the necessary round keys ++ * The number of calculations depends on keyBits and blockBits ++ */ ++ int KC, BC, ROUNDS; ++ int i, j, t, rconpointer = 0; ++ MV_U8 tk[4][MAXKC]; ++ ++ switch (keyBits) { ++ case 128: KC = 4; break; ++ case 192: KC = 6; break; ++ case 256: KC = 8; break; ++ default : return (-1); ++ } ++ ++ switch (blockBits) { ++ case 128: BC = 4; break; ++ case 192: BC = 6; break; ++ case 256: BC = 8; break; ++ default : return (-2); ++ } ++ ++ switch (keyBits >= blockBits ? keyBits : blockBits) { ++ case 128: ROUNDS = 10; break; ++ case 192: ROUNDS = 12; break; ++ case 256: ROUNDS = 14; break; ++ default : return (-3); /* this cannot happen */ ++ } ++ ++ ++ for(j = 0; j < KC; j++) ++ for(i = 0; i < 4; i++) ++ tk[i][j] = k[i][j]; ++ t = 0; ++ /* copy values into round key array */ ++ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) ++ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; ++ ++ while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */ ++ /* calculate new values */ ++ for(i = 0; i < 4; i++) ++ tk[i][0] ^= S[tk[(i+1)%4][KC-1]]; ++ tk[0][0] ^= rcon[rconpointer++]; ++ ++ if (KC != 8) ++ for(j = 1; j < KC; j++) ++ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; ++ else { ++ for(j = 1; j < KC/2; j++) ++ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; ++ for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]]; ++ for(j = KC/2 + 1; j < KC; j++) ++ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; ++ } ++ /* copy values into round key array */ ++ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) ++ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; ++ } ++ ++ return 0; ++} ++ ++ ++ ++int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) ++{ ++ /* Encryption of one block. ++ */ ++ int r, BC, ROUNDS; ++ ++ BC = 4; ++ ROUNDS = rounds; ++ ++ /* begin with a key addition ++ */ ++ ++ KeyAddition(a,rk[0],BC); ++ ++ /* ROUNDS-1 ordinary rounds ++ */ ++ for(r = 1; r < ROUNDS; r++) { ++ Substitution(a,S); ++ ShiftRow128Enc(a); ++ MixColumn(a, rk[r]); ++ /*KeyAddition(a,rk[r],BC);*/ ++ } ++ ++ /* Last round is special: there is no MixColumn ++ */ ++ Substitution(a,S); ++ ShiftRow128Enc(a); ++ KeyAddition(a,rk[ROUNDS],BC); ++ ++ return 0; ++} ++ ++ ++int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) ++{ ++ int r, BC, ROUNDS; ++ ++ BC = 4; ++ ROUNDS = rounds; ++ ++ /* To decrypt: apply the inverse operations of the encrypt routine, ++ * in opposite order ++ * ++ * (KeyAddition is an involution: it 's equal to its inverse) ++ * (the inverse of Substitution with table S is Substitution with the inverse table of S) ++ * (the inverse of Shiftrow is Shiftrow over a suitable distance) ++ */ ++ ++ /* First the special round: ++ * without InvMixColumn ++ * with extra KeyAddition ++ */ ++ KeyAddition(a,rk[ROUNDS],BC); ++ ShiftRow128Dec(a); ++ Substitution(a,Si); ++ ++ /* ROUNDS-1 ordinary rounds ++ */ ++ for(r = ROUNDS-1; r > 0; r--) { ++ KeyAddition(a,rk[r],BC); ++ InvMixColumn(a); ++ ShiftRow128Dec(a); ++ Substitution(a,Si); ++ ++ } ++ ++ /* End with the extra key addition ++ */ ++ ++ KeyAddition(a,rk[0],BC); ++ ++ return 0; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,19 @@ ++/* rijndael-alg-ref.h v2.0 August '99 ++ * Reference ANSI C code ++ * authors: Paulo Barreto ++ * Vincent Rijmen, K.U.Leuven ++ */ ++#ifndef __RIJNDAEL_ALG_H ++#define __RIJNDAEL_ALG_H ++ ++#define MAXBC (128/32) ++#define MAXKC (256/32) ++#define MAXROUNDS 14 ++ ++ ++int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]); ++ ++int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); ++int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); ++ ++#endif /* __RIJNDAEL_ALG_H */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,312 @@ ++/* rijndael-api-ref.c v2.1 April 2000 ++ * Reference ANSI C code ++ * authors: v2.0 Paulo Barreto ++ * Vincent Rijmen, K.U.Leuven ++ * v2.1 Vincent Rijmen, K.U.Leuven ++ * ++ * This code is placed in the public domain. ++ */ ++#include "mvOs.h" ++ ++#include "mvAes.h" ++#include "mvAesAlg.h" ++ ++ ++/* Defines: ++ Add any additional defines you need ++*/ ++ ++#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ ++#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ ++#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ ++ ++ ++int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) ++{ ++ MV_U8 W[MAXROUNDS+1][4][MAXBC]; ++ MV_U8 k[4][MAXKC]; ++ MV_U8 j; ++ int i, rounds, KC; ++ ++ if (expandedKey == NULL) ++ { ++ return AES_BAD_KEY_INSTANCE; ++ } ++ ++ if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) ++ { ++ return AES_BAD_KEY_MAT; ++ } ++ ++ if (keyMaterial == NULL) ++ { ++ return AES_BAD_KEY_MAT; ++ } ++ ++ /* initialize key schedule: */ ++ for(i=0; i= 3) ++MV_U32 cesaChainLength = 0; ++int chainReqNum = 0; ++MV_U32 chainIndex = 0; ++MV_CESA_REQ* pNextActiveChain = 0; ++MV_CESA_REQ* pEndCurrChain = 0; ++MV_BOOL isFirstReq = MV_TRUE; ++#endif ++ ++static INLINE MV_U8* mvCesaSramAddrGet(void) ++{ ++#ifdef MV_CESA_NO_SRAM ++ return (MV_U8*)cesaSramVirtPtr; ++#else ++ return (MV_U8*)cesaCryptEngBase; ++#endif /* MV_CESA_NO_SRAM */ ++} ++ ++static INLINE MV_ULONG mvCesaSramVirtToPhys(void* pDev, MV_U8* pSramVirt) ++{ ++#ifdef MV_CESA_NO_SRAM ++ return (MV_ULONG)mvOsIoVirtToPhy(NULL, pSramVirt); ++#else ++ return (MV_ULONG)pSramVirt; ++#endif /* MV_CESA_NO_SRAM */ ++} ++ ++/* Internal Function prototypes */ ++ ++static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, ++ int cryptoOffset, int ivOffset, int cryptoLength, ++ int macOffset, int digestOffset, int macLength, int macTotalLen, ++ MV_CESA_REQ *pCesaReq, MV_DMA_DESC* pDmaDesc); ++ ++static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); ++ ++static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, ++ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, ++ int offset, int copySize, MV_BOOL skipFlush); ++ ++static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, ++ unsigned char innerIV[], unsigned char outerIV[]); ++ ++static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ* pReq, MV_CESA_SA* pSA, ++ int macDataSize); ++ ++static MV_CESA_COMMAND* mvCesaCtrModeInit(void); ++ ++static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); ++static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); ++static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); ++ ++static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq); ++static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag); ++ ++static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset); ++static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd); ++ ++static INLINE void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, ++ int cryptoOffset, int macOffset, ++ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize); ++static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size); ++ ++ ++/* Go to the next request in the request queue */ ++static INLINE MV_CESA_REQ* MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ* pReq) ++{ ++ if(pReq == pCesaReqLast) ++ return pCesaReqFirst; ++ ++ return pReq+1; ++} ++ ++#if (MV_CESA_VERSION >= 3) ++/* Go to the previous request in the request queue */ ++static INLINE MV_CESA_REQ* MV_CESA_REQ_PREV_PTR(MV_CESA_REQ* pReq) ++{ ++ if(pReq == pCesaReqFirst) ++ return pCesaReqLast; ++ ++ return pReq-1; ++} ++ ++#endif ++ ++ ++static INLINE void mvCesaReqProcessStart(MV_CESA_REQ* pReq) ++{ ++ int frag; ++ ++#if (MV_CESA_VERSION >= 3) ++ pReq->state = MV_CESA_CHAIN; ++#else ++ pReq->state = MV_CESA_PROCESS; ++#endif ++ cesaStats.startCount++; ++ ++ if(pReq->fragMode == MV_CESA_FRAG_NONE) ++ { ++ frag = 0; ++ } ++ else ++ { ++ frag = pReq->frags.nextFrag; ++ pReq->frags.nextFrag++; ++ } ++#if (MV_CESA_VERSION >= 2) ++ /* Enable TDMA engine */ ++ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); ++ MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, ++ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); ++#else ++ /* Enable IDMA engine */ ++ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); ++ MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), ++ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); ++#endif /* MV_CESA_VERSION >= 2 */ ++ ++#if defined(MV_BRIDGE_SYNC_REORDER) ++ mvOsBridgeReorderWA(); ++#endif ++ ++ /* Start Accelerator */ ++ MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); ++} ++ ++ ++/******************************************************************************* ++* mvCesaHalInit - Initialize the CESA driver ++* ++* DESCRIPTION: ++* This function initialize the CESA driver. ++* 1) Session database ++* 2) Request queue ++* 4) DMA descriptor lists - one list per request. Each list ++* has MV_CESA_MAX_DMA_DESC descriptors. ++* ++* INPUT: ++* numOfSession - maximum number of supported sessions ++* queueDepth - number of elements in the request queue. ++* pSramBase - virtual address of Sram ++* osHandle - A handle used by the OS to allocate memory for the ++* module (Passed to the OS Services layer) ++* ++* RETURN: ++* MV_OK - Success ++* MV_NO_RESOURCE - Fail, can't allocate resources: ++* Session database, request queue, ++* DMA descriptors list, LRU cache database. ++* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, ++ void *osHandle) ++{ ++ int i, req; ++ MV_U32 descOffsetReg, configReg; ++ MV_CESA_SRAM_SA *pSramSA; ++ ++ ++ mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSram=%p\n", ++ numOfSession, queueDepth, pSramBase); ++ ++ cesaOsHandle = osHandle; ++ /* Create Session database */ ++ pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA)*numOfSession); ++ if(pCesaSAD == NULL) ++ { ++ mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", ++ sizeof(MV_CESA_SA)*numOfSession, numOfSession); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(pCesaSAD, 0, sizeof(MV_CESA_SA)*numOfSession); ++ cesaMaxSA = numOfSession; ++ ++ /* Allocate imag of sramSA in the DRAM */ ++ cesaSramSaBuf.bufSize = sizeof(MV_CESA_SRAM_SA)*numOfSession + ++ CPU_D_CACHE_LINE_SIZE; ++ ++ cesaSramSaBuf.bufVirtPtr = mvOsIoCachedMalloc(osHandle,cesaSramSaBuf.bufSize, ++ &cesaSramSaBuf.bufPhysAddr, ++ &cesaSramSaBuf.memHandle); ++ ++ if(cesaSramSaBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("mvCesaInit: Can't allocate %d bytes for sramSA structures\n", ++ cesaSramSaBuf.bufSize); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(cesaSramSaBuf.bufVirtPtr, 0, cesaSramSaBuf.bufSize); ++ pSramSA = (MV_CESA_SRAM_SA*)MV_ALIGN_UP((MV_ULONG)cesaSramSaBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ for(i=0; i= 3) ++ cesaChainLength = MAX_CESA_CHAIN_LENGTH; ++#endif ++ /* pSramBase must be 8 byte aligned */ ++ if( MV_IS_NOT_ALIGN((MV_ULONG)pSramBase, 8) ) ++ { ++ mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", ++ pSramBase); ++ mvCesaFinish(); ++ return MV_NOT_ALIGNED; ++ } ++ cesaSramVirtPtr = (MV_CESA_SRAM_MAP*)pSramBase; ++ ++ cesaCryptEngBase = cryptEngBase; ++ ++ /*memset(cesaSramVirtPtr, 0, sizeof(MV_CESA_SRAM_MAP));*/ ++ ++ /* Clear registers */ ++ MV_REG_WRITE( MV_CESA_CFG_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); ++ ++ /* Initialize DMA descriptor lists for all requests in Request queue */ ++ descOffsetReg = configReg = 0; ++ for(req=0; reqcesaDescBuf.bufSize = sizeof(MV_CESA_DESC)*MV_CESA_MAX_REQ_FRAGS + ++ CPU_D_CACHE_LINE_SIZE; ++ ++ pReq->cesaDescBuf.bufVirtPtr = ++ mvOsIoCachedMalloc(osHandle,pReq->cesaDescBuf.bufSize, ++ &pReq->cesaDescBuf.bufPhysAddr, ++ &pReq->cesaDescBuf.memHandle); ++ ++ if(pReq->cesaDescBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", ++ req, pReq->cesaDescBuf.bufSize); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); ++ pReq->pCesaDesc = (MV_CESA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->cesaDescBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC)*MV_CESA_MAX_DMA_DESC*MV_CESA_MAX_REQ_FRAGS + ++ CPU_D_CACHE_LINE_SIZE; ++ ++ pReq->dmaDescBuf.bufVirtPtr = ++ mvOsIoCachedMalloc(osHandle,pReq->dmaDescBuf.bufSize, ++ &pReq->dmaDescBuf.bufPhysAddr, ++ &pReq->dmaDescBuf.memHandle); ++ ++ if(pReq->dmaDescBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", ++ req, pReq->dmaDescBuf.bufSize); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); ++ pDmaDesc = (MV_DMA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->dmaDescBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ for(frag=0; fragdma[frag]; ++ ++ pDma->pDmaFirst = pDmaDesc; ++ pDma->pDmaLast = NULL; ++ ++ for(i=0; ipDmaFirst[i].phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i+1])); ++ } ++ pDma->pDmaFirst[i].phyNextDescPtr = 0; ++ mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC*sizeof(MV_DMA_DESC)); ++ ++ pDmaDesc += MV_CESA_MAX_DMA_DESC; ++ } ++ } ++ /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH);*/ ++ descOffsetReg = (MV_U16)((MV_U8*)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); ++ MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); ++ ++ configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); ++#if (MV_CESA_VERSION >= 3) ++ configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; ++#endif ++ ++#if (MV_CESA_VERSION >= 2) ++ /* Initialize TDMA engine */ ++ MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); ++ MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); ++ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); ++#else ++ /* Initialize IDMA #0 engine */ ++ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); ++ MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); ++ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); ++ MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE ++#ifdef MV_CPU_LE ++ | ICCHR_DESC_BYTE_SWAP_EN ++#endif ++ ); ++ /* Clear Cause Byte of IDMA channel to be used */ ++ MV_REG_WRITE( IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); ++ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); ++#endif /* (MV_CESA_VERSION >= 2) */ ++ ++ /* Set CESA configuration registers */ ++ MV_REG_WRITE( MV_CESA_CFG_REG, configReg); ++ mvCesaDebugStatsClear(); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaFinish - Shutdown the CESA driver ++* ++* DESCRIPTION: ++* This function shutdown the CESA driver and free all allocted resources. ++* ++* INPUT: None ++* ++* RETURN: ++* MV_OK - Success ++* Other - Fail ++* ++*******************************************************************************/ ++MV_STATUS mvCesaFinish (void) ++{ ++ int req; ++ MV_CESA_REQ* pReq; ++ ++ mvOsPrintf("mvCesaFinish: \n"); ++ ++ cesaSramVirtPtr = NULL; ++ ++ /* Free all resources: DMA list, etc. */ ++ for(req=0; reqdmaDescBuf.bufVirtPtr != NULL) ++ { ++ mvOsIoCachedFree(cesaOsHandle,pReq->dmaDescBuf.bufSize, ++ pReq->dmaDescBuf.bufPhysAddr, ++ pReq->dmaDescBuf.bufVirtPtr, ++ pReq->dmaDescBuf.memHandle); ++ } ++ if(pReq->cesaDescBuf.bufVirtPtr != NULL) ++ { ++ mvOsIoCachedFree(cesaOsHandle,pReq->cesaDescBuf.bufSize, ++ pReq->cesaDescBuf.bufPhysAddr, ++ pReq->cesaDescBuf.bufVirtPtr, ++ pReq->cesaDescBuf.memHandle); ++ } ++ } ++#if (MV_CESA_VERSION < 2) ++ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); ++#endif /* (MV_CESA_VERSION < 2) */ ++ ++ /* Free request queue */ ++ if(pCesaReqFirst != NULL) ++ { ++ mvOsFree(pCesaReqFirst); ++ pCesaReqFirst = pCesaReqLast = NULL; ++ pCesaReqEmpty = pCesaReqProcess = NULL; ++ cesaQueueDepth = cesaReqResources = 0; ++ } ++ /* Free SA database */ ++ if(pCesaSAD != NULL) ++ { ++ mvOsFree(pCesaSAD); ++ pCesaSAD = NULL; ++ cesaMaxSA = 0; ++ } ++ MV_REG_WRITE( MV_CESA_CFG_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode ++* ++* DESCRIPTION: ++* This function set IV value using by Crypto algorithms in CBC mode. ++* Each channel has its own IV value. ++* This function gets IV value from the caller. If no IV value passed from ++* the caller or only part of IV passed, the function will init the rest part ++* of IV value (or the whole IV) by random value. ++* ++* INPUT: ++* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL ++* the function will generate random IV value. ++* int ivSize - size (in bytes) of IV provided by user. If ivSize is ++* smaller than maximum IV size, the function will complete ++* IV by random value. ++* ++* RETURN: ++* MV_OK - Success ++* Other - Fail ++* ++*******************************************************************************/ ++MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize) ++{ ++ MV_U8* pSramIV; ++#if defined(MV646xx) ++ mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); ++#endif ++ pSramIV = cesaSramVirtPtr->cryptoIV; ++ if(ivSize > MV_CESA_MAX_IV_LENGTH) ++ { ++ mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); ++ ivSize = MV_CESA_MAX_IV_LENGTH; ++ } ++ if(pIV != NULL) ++ { ++ memcpy(pSramIV, pIV, ivSize); ++ ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; ++ pSramIV += ivSize; ++ } ++ ++ while(ivSize > 0) ++ { ++ int size, mv_random = mvOsRand(); ++ ++ size = MV_MIN(ivSize, sizeof(mv_random)); ++ memcpy(pSramIV, (void*)&mv_random, size); ++ ++ pSramIV += size; ++ ivSize -= size; ++ } ++/* ++ mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, ++ MV_CESA_MAX_IV_LENGTH); ++ mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, ++ MV_CESA_MAX_IV_LENGTH); ++*/ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaSessionOpen - Open new uni-directional crypto session ++* ++* DESCRIPTION: ++* This function open new session. ++* ++* INPUT: ++* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters ++* ++* OUTPUT: ++* short *pSid - session ID, should be used for all future ++* requests over this session. ++* ++* RETURN: ++* MV_OK - Session opend successfully. ++* MV_FULL - All sessions are in use, no free place in ++* SA database. ++* MV_BAD_PARAM - One of session input parameters is invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid) ++{ ++ short sid; ++ MV_U32 config = 0; ++ int digestSize; ++ ++ cesaStats.openedCount++; ++ ++ /* Find free entry in SAD */ ++ for(sid=0; sidoperation >= MV_CESA_MAX_OPERATION) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", ++ pSession->operation); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); ++ ++ if( (pSession->direction != MV_CESA_DIR_ENCODE) && ++ (pSession->direction != MV_CESA_DIR_DECODE) ) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", ++ pSession->direction); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->direction << MV_CESA_DIRECTION_BIT); ++ /* Clear SA entry */ ++ /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ ++ ++ /* Check AUTH parameters and update SA entry */ ++ if(pSession->operation != MV_CESA_CRYPTO_ONLY) ++ { ++ /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ ++ if( (pSession->macMode == MV_CESA_MAC_HMAC_MD5) || ++ (pSession->macMode == MV_CESA_MAC_HMAC_SHA1) ) ++ { ++ if(pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) ++ { ++ mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", ++ pSession->macKeyLength); ++ return MV_BAD_PARAM; ++ } ++ mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, ++ pCesaSAD[sid].pSramSA->macInnerIV, ++ pCesaSAD[sid].pSramSA->macOuterIV); ++ pCesaSAD[sid].macKeyLength = pSession->macKeyLength; ++ } ++ switch(pSession->macMode) ++ { ++ case MV_CESA_MAC_MD5: ++ case MV_CESA_MAC_HMAC_MD5: ++ digestSize = MV_CESA_MD5_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_SHA1: ++ case MV_CESA_MAC_HMAC_SHA1: ++ digestSize = MV_CESA_SHA1_DIGEST_SIZE; ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", ++ pSession->macMode); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); ++ ++ /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ ++ /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ ++ if( (pSession->digestSize != digestSize) && (pSession->digestSize != 12)) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", ++ pSession->digestSize); ++ mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); ++ return MV_BAD_PARAM; ++ } ++ pCesaSAD[sid].digestSize = pSession->digestSize; ++ ++ if(pCesaSAD[sid].digestSize == 12) ++ { ++ /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ ++ config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); ++ } ++ } ++ ++ /* Check CRYPTO parameters and update SA entry */ ++ if(pSession->operation != MV_CESA_MAC_ONLY) ++ { ++ switch(pSession->cryptoAlgorithm) ++ { ++ case MV_CESA_CRYPTO_DES: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; ++ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; ++ break; ++ ++ case MV_CESA_CRYPTO_3DES: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; ++ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; ++ /* Only EDE mode is supported */ ++ config |= (MV_CESA_CRYPTO_3DES_EDE << ++ MV_CESA_CRYPTO_3DES_MODE_BIT); ++ break; ++ ++ case MV_CESA_CRYPTO_AES: ++ switch(pSession->cryptoKeyLength) ++ { ++ case 16: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; ++ config |= (MV_CESA_CRYPTO_AES_KEY_128 << ++ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); ++ break; ++ ++ case 24: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; ++ config |= (MV_CESA_CRYPTO_AES_KEY_192 << ++ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); ++ break; ++ ++ case 32: ++ default: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; ++ config |= (MV_CESA_CRYPTO_AES_KEY_256 << ++ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); ++ break; ++ } ++ pCesaSAD[sid].cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", ++ pSession->cryptoAlgorithm); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); ++ ++ if(pSession->cryptoKeyLength != pCesaSAD[sid].cryptoKeyLength) ++ { ++ mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", ++ pSession->cryptoKeyLength, pCesaSAD[sid].cryptoKeyLength); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Copy Crypto key */ ++ if( (pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && ++ (pSession->direction == MV_CESA_DIR_DECODE)) ++ { ++ /* Crypto Key for AES decode is computed from original key material */ ++ /* and depend on cryptoKeyLength (128/192/256 bits) */ ++ aesMakeKey(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, ++ pSession->cryptoKeyLength*8, MV_CESA_AES_BLOCK_SIZE*8); ++ } ++ else ++ { ++ /*panic("mvCesaSessionOpen2");*/ ++ memcpy(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, ++ pCesaSAD[sid].cryptoKeyLength); ++ ++ } ++ ++ switch(pSession->cryptoMode) ++ { ++ case MV_CESA_CRYPTO_ECB: ++ pCesaSAD[sid].cryptoIvSize = 0; ++ break; ++ ++ case MV_CESA_CRYPTO_CBC: ++ pCesaSAD[sid].cryptoIvSize = pCesaSAD[sid].cryptoBlockSize; ++ break; ++ ++ case MV_CESA_CRYPTO_CTR: ++ /* Supported only for AES algorithm */ ++ if(pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) ++ { ++ mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); ++ return MV_BAD_PARAM; ++ } ++ pCesaSAD[sid].cryptoIvSize = 0; ++ pCesaSAD[sid].ctrMode = 1; ++ /* Replace to ECB mode for HW */ ++ pSession->cryptoMode = MV_CESA_CRYPTO_ECB; ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", ++ pSession->cryptoMode); ++ return MV_BAD_PARAM; ++ } ++ ++ config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); ++ } ++ pCesaSAD[sid].config = config; ++ ++ mvOsCacheFlush(NULL, pCesaSAD[sid].pSramSA, sizeof(MV_CESA_SRAM_SA)); ++ if(pSid != NULL) ++ *pSid = sid; ++ ++ pCesaSAD[sid].valid = 1; ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaSessionClose - Close active crypto session ++* ++* DESCRIPTION: ++* This function closes existing session ++* ++* INPUT: ++* short sid - Unique identifier of the session to be closed ++* ++* RETURN: ++* MV_OK - Session closed successfully. ++* MV_BAD_PARAM - Session identifier is out of valid range. ++* MV_NOT_FOUND - There is no active session with such ID. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaSessionClose(short sid) ++{ ++ cesaStats.closedCount++; ++ ++ if(sid >= cesaMaxSA) ++ { ++ mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); ++ return MV_BAD_PARAM; ++ } ++ if(pCesaSAD[sid].valid == 0) ++ { ++ mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); ++ return MV_NOT_FOUND; ++ } ++ if(cesaLastSid == sid) ++ cesaLastSid = -1; ++ ++ pCesaSAD[sid].valid = 0; ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaAction - Perform crypto operation ++* ++* DESCRIPTION: ++* This function set new CESA request FIFO queue for further HW processing. ++* The function checks request parameters before set new request to the queue. ++* If one of the CESA channels is ready for processing the request will be ++* passed to HW. When request processing is finished the CESA interrupt will ++* be generated by HW. The caller should call mvCesaReadyGet() function to ++* complete request processing and get result. ++* ++* INPUT: ++* MV_CESA_COMMAND *pCmd - pointer to new CESA request. ++* It includes pointers to Source and Destination ++* buffers, session identifier get from ++* mvCesaSessionOpen() function, pointer to caller ++* private data and all needed crypto parameters. ++* ++* RETURN: ++* MV_OK - request successfully added to request queue ++* and will be processed. ++* MV_NO_MORE - request successfully added to request queue and will ++* be processed, but request queue became Full and next ++* request will not be accepted. ++* MV_NO_RESOURCE - request queue is FULL and the request can not ++* be processed. ++* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is ++* failed. Request can not be processed. ++* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed ++* as one request and should be splitted for two requests: ++* CRYPTO_ONLY and MAC_ONLY. ++* MV_BAD_PARAM - One of the request parameters is out of valid range. ++* The request can not be processed. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaAction (MV_CESA_COMMAND *pCmd) ++{ ++ MV_STATUS status; ++ MV_CESA_REQ* pReq = pCesaReqEmpty; ++ int sid = pCmd->sessionId; ++ MV_CESA_SA* pSA = &pCesaSAD[sid]; ++#if (MV_CESA_VERSION >= 3) ++ MV_CESA_REQ* pFromReq; ++ MV_CESA_REQ* pToReq; ++#endif ++ cesaStats.reqCount++; ++ ++ /* Check that the request queue is not FULL */ ++ if(cesaReqResources == 0) ++ return MV_NO_RESOURCE; ++ ++ if( (sid >= cesaMaxSA) || (!pSA->valid) ) ++ { ++ mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); ++ return MV_BAD_PARAM; ++ } ++ pSA->count++; ++ ++ if(pSA->ctrMode) ++ { ++ /* AES in CTR mode can't be mixed with Authentication */ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); ++ return MV_NOT_ALLOWED; ++ } ++ /* All other request parameters should not be checked because key stream */ ++ /* (not user data) processed by AES HW engine */ ++ pReq->pOrgCmd = pCmd; ++ /* Allocate temporary pCmd structure for Key stream */ ++ pCmd = mvCesaCtrModeInit(); ++ if(pCmd == NULL) ++ return MV_OUT_OF_CPU_MEM; ++ ++ /* Prepare Key stream */ ++ mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); ++ pReq->fixOffset = 0; ++ } ++ else ++ { ++ /* Check request parameters and calculae fixOffset */ ++ status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); ++ if(status != MV_OK) ++ { ++ return status; ++ } ++ } ++ pReq->pCmd = pCmd; ++ ++ /* Check if the packet need fragmentation */ ++ if(pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf) ) ++ { ++ /* request size is smaller than single buffer size */ ++ pReq->fragMode = MV_CESA_FRAG_NONE; ++ ++ /* Prepare NOT fragmented packets */ ++ status = mvCesaReqProcess(pReq); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", ++ pReq, status); ++ } ++#if (MV_CESA_VERSION >= 3) ++ pReq->frags.numFrag = 1; ++#endif ++ } ++ else ++ { ++ MV_U8 frag = 0; ++ ++ /* request size is larger than buffer size - needs fragmentation */ ++ ++ /* Check restrictions for processing fragmented packets */ ++ status = mvCesaFragParamCheck(pSA, pCmd); ++ if(status != MV_OK) ++ return status; ++ ++ pReq->fragMode = MV_CESA_FRAG_FIRST; ++ pReq->frags.nextFrag = 0; ++ ++ /* Prepare Process Fragmented packets */ ++ while(pReq->fragMode != MV_CESA_FRAG_LAST) ++ { ++ if(frag >= MV_CESA_MAX_REQ_FRAGS) ++ { ++ mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); ++ return MV_OUT_OF_CPU_MEM; ++ } ++ status = mvCesaFragReqProcess(pReq, frag); ++ if(status == MV_OK) { ++#if (MV_CESA_VERSION >= 3) ++ if(frag) { ++ pReq->dma[frag-1].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); ++ mvOsCacheFlush(NULL, pReq->dma[frag-1].pDmaLast, sizeof(MV_DMA_DESC)); ++ } ++#endif ++ frag++; ++ } ++ } ++ pReq->frags.numFrag = frag; ++#if (MV_CESA_VERSION >= 3) ++ if(chainReqNum) { ++ chainReqNum += pReq->frags.numFrag; ++ if(chainReqNum >= MAX_CESA_CHAIN_LENGTH) ++ chainReqNum = MAX_CESA_CHAIN_LENGTH; ++ } ++#endif ++ } ++ ++ pReq->state = MV_CESA_PENDING; ++ ++ pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); ++ cesaReqResources -= 1; ++ ++/* #ifdef CESA_DEBUG */ ++ if( (cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) ++ cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); ++/* #endif CESA_DEBUG */ ++ ++ cesaLastSid = sid; ++ ++#if (MV_CESA_VERSION >= 3) ++ /* Are we within chain bounderies and follows the first request ? */ ++ if((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { ++ if(chainIndex) { ++ pFromReq = MV_CESA_REQ_PREV_PTR(pReq); ++ pToReq = pReq; ++ pReq->state = MV_CESA_CHAIN; ++ /* assume concatenating is possible */ ++ pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); ++ mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast, sizeof(MV_DMA_DESC)); ++ ++ /* align active & next pointers */ ++ if(pNextActiveChain->state != MV_CESA_PENDING) ++ pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); ++ } ++ else { /* we have only one chain, start new one */ ++ chainReqNum = 0; ++ chainIndex++; ++ /* align active & next pointers */ ++ if(pNextActiveChain->state != MV_CESA_PENDING) ++ pEndCurrChain = pNextActiveChain = pReq; ++ } ++ } ++ else { ++ /* In case we concatenate full chain */ ++ if(chainReqNum == MAX_CESA_CHAIN_LENGTH) { ++ chainIndex++; ++ if(pNextActiveChain->state != MV_CESA_PENDING) ++ pEndCurrChain = pNextActiveChain = pReq; ++ chainReqNum = 0; ++ } ++ ++ pReq = pCesaReqProcess; ++ if(pReq->state == MV_CESA_PENDING) { ++ pNextActiveChain = pReq; ++ pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); ++ /* Start Process new request */ ++ mvCesaReqProcessStart(pReq); ++ } ++ } ++ ++ chainReqNum++; ++ ++ if((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) ++ cesaStats.maxChainUsage = chainReqNum; ++ ++#else ++ ++ /* Check status of CESA channels and process requests if possible */ ++ pReq = pCesaReqProcess; ++ if(pReq->state == MV_CESA_PENDING) ++ { ++ /* Start Process new request */ ++ mvCesaReqProcessStart(pReq); ++ } ++#endif ++ /* If request queue became FULL - return MV_NO_MORE */ ++ if(cesaReqResources == 0) ++ return MV_NO_MORE; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCesaReadyGet - Get crypto request that processing is finished ++* ++* DESCRIPTION: ++* This function complete request processing and return ready request to ++* caller. To don't miss interrupts the caller must call this function ++* while MV_OK or MV_TERMINATE values returned. ++* ++* INPUT: ++* MV_U32 chanMap - map of CESA channels finished thier job ++* accordingly with CESA Cause register. ++* MV_CESA_RESULT* pResult - pointer to structure contains information ++* about ready request. It includes pointer to ++* user private structure "pReqPrv", session identifier ++* for this request "sessionId" and return code. ++* Return code set to MV_FAIL if calculated digest value ++* on decode direction is different than digest value ++* in the packet. ++* ++* RETURN: ++* MV_OK - Success, ready request is returned. ++* MV_NOT_READY - Next request is not ready yet. New interrupt will ++* be generated for futher request processing. ++* MV_EMPTY - There is no more request for processing. ++* MV_BUSY - Fragmented request is not ready yet. ++* MV_TERMINATE - Call this function once more to complete processing ++* of fragmented request. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult) ++{ ++ MV_STATUS status, readyStatus = MV_NOT_READY; ++ MV_U32 statusReg; ++ MV_CESA_REQ* pReq; ++ MV_CESA_SA* pSA; ++ ++#if (MV_CESA_VERSION >= 3) ++ if(isFirstReq == MV_TRUE) { ++ if(chainIndex == 0) ++ chainReqNum = 0; ++ ++ isFirstReq = MV_FALSE; ++ ++ if(pNextActiveChain->state == MV_CESA_PENDING) { ++ /* Start request Process */ ++ mvCesaReqProcessStart(pNextActiveChain); ++ pEndCurrChain = pNextActiveChain; ++ if(chainIndex > 0) ++ chainIndex--; ++ /* Update pNextActiveChain to next chain head */ ++ while(pNextActiveChain->state == MV_CESA_CHAIN) ++ pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); ++ } ++ } ++ ++ /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ ++ if(pCesaReqProcess == pEndCurrChain) { ++ isFirstReq = MV_TRUE; ++ pEndCurrChain = pNextActiveChain; ++#else ++ if(pCesaReqProcess->state != MV_CESA_PROCESS) { ++#endif ++ return MV_EMPTY; ++ } ++ ++#ifdef CESA_DEBUG ++ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); ++ if( statusReg & MV_CESA_STATUS_ACTIVE_MASK ) ++ { ++ mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); ++ cesaStats.notReadyCount++; ++ return MV_NOT_READY; ++ } ++#endif /* CESA_DEBUG */ ++ ++ cesaStats.readyCount++; ++ ++ pReq = pCesaReqProcess; ++ pSA = &pCesaSAD[pReq->pCmd->sessionId]; ++ ++ pResult->retCode = MV_OK; ++ if(pReq->fragMode != MV_CESA_FRAG_NONE) ++ { ++ MV_U8* pNewDigest; ++ int frag; ++#if (MV_CESA_VERSION >= 3) ++ pReq->frags.nextFrag = 1; ++ while(pReq->frags.nextFrag <= pReq->frags.numFrag) { ++#endif ++ frag = (pReq->frags.nextFrag - 1); ++ ++ /* Restore DMA descriptor list */ ++ pReq->dma[frag].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); ++ pReq->dma[frag].pDmaLast = NULL; ++ ++ /* Special processing for finished fragmented request */ ++ if(pReq->frags.nextFrag >= pReq->frags.numFrag) ++ { ++ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); ++ ++ /* Fragmented packet is ready */ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; ++ ++ if(macDataSize != 0) ++ { ++ /* Calculate all other blocks by SW */ ++ mvCesaFragAuthComplete(pReq, pSA, macDataSize); ++ } ++ ++ /* Copy new digest from SRAM to the Destination buffer */ ++ pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; ++ status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, ++ pReq->pCmd->digestOffset, pSA->digestSize); ++ ++ /* For decryption: Compare new digest value with original one */ ++ if((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ++ { ++ if( memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) ++ { ++/* ++ mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", ++ chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); ++*/ ++ /* Signiture verification is failed */ ++ pResult->retCode = MV_FAIL; ++ } ++ } ++ } ++ readyStatus = MV_OK; ++ } ++#if (MV_CESA_VERSION >= 3) ++ pReq->frags.nextFrag++; ++ } ++#endif ++ } ++ else ++ { ++ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); ++ ++ /* Restore DMA descriptor list */ ++ pReq->dma[0].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); ++ pReq->dma[0].pDmaLast = NULL; ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) && ++ ((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ) ++ { ++ /* For AUTH on decode : Check Digest result in Status register */ ++ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); ++ if(statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) ++ { ++/* ++ mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", ++ chan, statusReg); ++*/ ++ /* Signiture verification is failed */ ++ pResult->retCode = MV_FAIL; ++ } ++ } ++ readyStatus = MV_OK; ++ } ++ ++ if(readyStatus == MV_OK) ++ { ++ /* If Request is ready - Prepare pResult structure */ ++ pResult->pReqPrv = pReq->pCmd->pReqPrv; ++ pResult->sessionId = pReq->pCmd->sessionId; ++ ++ pReq->state = MV_CESA_IDLE; ++ pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); ++ cesaReqResources++; ++ ++ if(pSA->ctrMode) ++ { ++ /* For AES CTR mode - complete processing and free allocated resources */ ++ mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); ++ mvCesaCtrModeFinish(pReq->pCmd); ++ pReq->pOrgCmd = NULL; ++ } ++ } ++ ++#if (MV_CESA_VERSION < 3) ++ if(pCesaReqProcess->state == MV_CESA_PROCESS) ++ { ++ /* Start request Process */ ++ mvCesaReqProcessStart(pCesaReqProcess); ++ if(readyStatus == MV_NOT_READY) ++ readyStatus = MV_BUSY; ++ } ++ else if(pCesaReqProcess != pCesaReqEmpty) ++ { ++ /* Start process new request from the queue */ ++ mvCesaReqProcessStart(pCesaReqProcess); ++ } ++#endif ++ return readyStatus; ++} ++ ++/***************** Functions to work with CESA_MBUF structure ******************/ ++ ++/******************************************************************************* ++* mvCesaMbufOffset - Locate offset in the Mbuf structure ++* ++* DESCRIPTION: ++* This function locates offset inside Multi-Bufeer structure. ++* It get fragment number and place in the fragment where the offset ++* is located. ++* ++* ++* INPUT: ++* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure ++* int offset - Offset from the beginning of the data presented by ++* the Mbuf structure. ++* ++* OUTPUT: ++* int* pBufOffset - Offset from the beginning of the fragment where ++* the offset is located. ++* ++* RETURN: ++* int - Number of fragment, where the offset is located\ ++* ++*******************************************************************************/ ++int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset) ++{ ++ int frag = 0; ++ ++ while(offset > 0) ++ { ++ if(frag >= pMbuf->numFrags) ++ { ++ mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", ++ frag, pMbuf->numFrags); ++ return MV_INVALID; ++ } ++ if(offset < pMbuf->pFrags[frag].bufSize) ++ { ++ break; ++ } ++ offset -= pMbuf->pFrags[frag].bufSize; ++ frag++; ++ } ++ if(pBufOffset != NULL) ++ *pBufOffset = offset; ++ ++ return frag; ++} ++ ++/******************************************************************************* ++* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_U8* pDstBuf - Pointer to continuous buffer, where data is ++* copied to. ++* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is ++* copied from. ++* int offset - Offset in the Mbuf structure where located first ++* byte of data should be copied. ++* int size - Size of data should be copied ++* ++* RETURN: ++* MV_OK - Success, all data is copied successfully. ++* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. ++* No data is copied. ++* MV_EMPTY - Multi-buffer structure has not enough data to copy ++* Data from the offset to end of Mbuf data is copied. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDstBuf, MV_CESA_MBUF* pSrcMbuf, ++ int offset, int size) ++{ ++ int frag, fragOffset, bufSize; ++ MV_U8* pBuf; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; ++ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; ++ while(MV_TRUE) ++ { ++ if(size <= bufSize) ++ { ++ memcpy(pDstBuf, pBuf, size); ++ return MV_OK; ++ } ++ memcpy(pDstBuf, pBuf, bufSize); ++ size -= bufSize; ++ frag++; ++ pDstBuf += bufSize; ++ if(frag >= pSrcMbuf->numFrags) ++ break; ++ ++ bufSize = pSrcMbuf->pFrags[frag].bufSize; ++ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; ++ } ++ mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", ++ size); ++ return MV_EMPTY; ++} ++ ++/******************************************************************************* ++* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is ++* copied from. ++* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is ++* copied to. ++* int offset - Offset in the Mbuf structure where located first ++* byte of data should be copied. ++* int size - Size of data should be copied ++* ++* RETURN: ++* MV_OK - Success, all data is copied successfully. ++* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. ++* No data is copied. ++* MV_FULL - Multi-buffer structure has not enough place to copy ++* all data. Data from the offset to end of Mbuf data ++* is copied. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrcBuf, MV_CESA_MBUF* pDstMbuf, ++ int offset, int size) ++{ ++ int frag, fragOffset, bufSize; ++ MV_U8* pBuf; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; ++ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; ++ while(MV_TRUE) ++ { ++ if(size <= bufSize) ++ { ++ memcpy(pBuf, pSrcBuf, size); ++ return MV_OK; ++ } ++ memcpy(pBuf, pSrcBuf, bufSize); ++ size -= bufSize; ++ frag++; ++ pSrcBuf += bufSize; ++ if(frag >= pDstMbuf->numFrags) ++ break; ++ ++ bufSize = pDstMbuf->pFrags[frag].bufSize; ++ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; ++ } ++ mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", ++ size); ++ return MV_FULL; ++} ++ ++/******************************************************************************* ++* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* ++* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is ++* copied to. ++* int dstMbufOffset - Offset in the dstMbuf structure where first byte ++* of data should be copied to. ++* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is ++* copied from. ++* int srcMbufOffset - Offset in the srcMbuf structure where first byte ++* of data should be copied from. ++* int size - Size of data should be copied ++* ++* RETURN: ++* MV_OK - Success, all data is copied successfully. ++* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of ++* srcMbuf or dstMbuf structure correspondently. ++* No data is copied. ++* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy ++* all data. Partial data is copied ++* ++*******************************************************************************/ ++MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, ++ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size) ++{ ++ int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; ++ int copySize; ++ MV_U8 *pSrc, *pDst; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); ++ if(srcFrag == MV_INVALID) ++ { ++ mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); ++ return MV_OUT_OF_RANGE; ++ } ++ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; ++ srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; ++ ++ dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); ++ if(dstFrag == MV_INVALID) ++ { ++ mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); ++ return MV_OUT_OF_RANGE; ++ } ++ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; ++ dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; ++ ++ while(size > 0) ++ { ++ copySize = MV_MIN(srcSize, dstSize); ++ if(size <= copySize) ++ { ++ memcpy(pDst, pSrc, size); ++ return MV_OK; ++ } ++ memcpy(pDst, pSrc, copySize); ++ size -= copySize; ++ srcSize -= copySize; ++ dstSize -= copySize; ++ ++ if(srcSize == 0) ++ { ++ srcFrag++; ++ if(srcFrag >= pMbufSrc->numFrags) ++ break; ++ ++ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; ++ srcSize = pMbufSrc->pFrags[srcFrag].bufSize; ++ } ++ ++ if(dstSize == 0) ++ { ++ dstFrag++; ++ if(dstFrag >= pMbufDst->numFrags) ++ break; ++ ++ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; ++ dstSize = pMbufDst->pFrags[dstFrag].bufSize; ++ } ++ } ++ mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", ++ size); ++ ++ return MV_BAD_SIZE; ++} ++ ++static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size) ++{ ++ int frag, fragOffset, bufSize; ++ MV_U8* pBuf; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; ++ while(MV_TRUE) ++ { ++ if(size <= bufSize) ++ { ++ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); ++ return MV_OK; ++ } ++ ++ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); ++ size -= bufSize; ++ frag++; ++ if(frag >= pMbuf->numFrags) ++ break; ++ ++ bufSize = pMbuf->pFrags[frag].bufSize; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr; ++ } ++ mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", ++ __FUNCTION__, size); ++ return MV_FULL; ++} ++ ++ ++/*************************************** Local Functions ******************************/ ++ ++/******************************************************************************* ++* mvCesaFragReqProcess - Process fragmented request ++* ++* DESCRIPTION: ++* This function processes a fragment of fragmented request (First, Middle or Last) ++* ++* ++* INPUT: ++* MV_CESA_REQ* pReq - Pointer to the request in the request queue. ++* ++* RETURN: ++* MV_OK - The fragment is successfully passed to HW for processing. ++* MV_TERMINATE - Means, that HW finished its work on this packet and no more ++* interrupts will be generated for this request. ++* Function mvCesaReadyGet() must be called to complete request ++* processing and get request result. ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag) ++{ ++ int i, copySize, cryptoDataSize, macDataSize, sid; ++ int cryptoIvOffset, digestOffset; ++ MV_U32 config; ++ MV_CESA_COMMAND* pCmd = pReq->pCmd; ++ MV_CESA_SA* pSA; ++ MV_CESA_MBUF* pMbuf; ++ MV_DMA_DESC* pDmaDesc = pReq->dma[frag].pDmaFirst; ++ MV_U8* pSramBuf = cesaSramVirtPtr->buf; ++ int macTotalLen = 0; ++ int fixOffset, cryptoOffset, macOffset; ++ ++ cesaStats.fragCount++; ++ ++ sid = pReq->pCmd->sessionId; ++ ++ pSA = &pCesaSAD[sid]; ++ ++ cryptoIvOffset = digestOffset = 0; ++ i = macDataSize = 0; ++ cryptoDataSize = 0; ++ ++ /* First fragment processing */ ++ if(pReq->fragMode == MV_CESA_FRAG_FIRST) ++ { ++ /* pReq->frags monitors processing of fragmented request between fragments */ ++ pReq->frags.bufOffset = 0; ++ pReq->frags.cryptoSize = 0; ++ pReq->frags.macSize = 0; ++ ++ config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); ++ ++ /* fixOffset can be not equal to zero only for FIRST fragment */ ++ fixOffset = pReq->fixOffset; ++ /* For FIRST fragment crypto and mac offsets are taken from pCmd */ ++ cryptoOffset = pCmd->cryptoOffset; ++ macOffset = pCmd->macOffset; ++ ++ copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; ++ ++ /* Find fragment size: Must meet all requirements for CRYPTO and MAC ++ * cryptoDataSize - size of data will be encrypted/decrypted in this fragment ++ * macDataSize - size of data will be signed/verified in this fragment ++ * copySize - size of data will be copied from srcMbuf to SRAM and ++ * back to dstMbuf for this fragment ++ */ ++ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, ++ ©Size, &cryptoDataSize, &macDataSize); ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ++ { ++ /* CryptoIV special processing */ ++ if( (pSA->config & MV_CESA_CRYPTO_MODE_MASK) == ++ (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT) ) ++ { ++ /* In CBC mode for encode direction when IV from user */ ++ if( (pCmd->ivFromUser) && ++ ((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) ) ++ { ++ ++ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, ++ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place ++ * in the buffer to SRAM IVPointer ++ */ ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], ++ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ ++ /* Special processing when IV is not located in the first fragment */ ++ if(pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) ++ { ++ /* Prepare dummy place for cryptoIV in SRAM */ ++ cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); ++ ++ /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ ++ if((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ++ { ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, &pDmaDesc[i], ++ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ else ++ { ++ /* For Encryption when IV is NOT from User: */ ++ /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ ++ if(pCmd->ivFromUser == 0) ++ { ++ /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], ++ MV_TRUE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ } ++ } ++ else ++ { ++ cryptoIvOffset = pCmd->ivOffset; ++ } ++ } ++ } ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ /* MAC digest special processing on Decode direction */ ++ if((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ++ { ++ /* Save digest from pCmd->digestOffset */ ++ mvCesaCopyFromMbuf(pReq->frags.orgDigest, ++ pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); ++ ++ /* If pCmd->digestOffset is not located on the first */ ++ if(pCmd->digestOffset > (copySize - pSA->digestSize)) ++ { ++ MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; ++ ++ /* Set zeros to pCmd->digestOffset (DRAM) */ ++ memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); ++ mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); ++ ++ /* Prepare dummy place for digest in SRAM */ ++ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); ++ } ++ else ++ { ++ digestOffset = pCmd->digestOffset; ++ } ++ } ++ } ++ /* Update SA in SRAM */ ++ if(cesaLastSid != sid) ++ { ++ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); ++ i++; ++ } ++ ++ pReq->fragMode = MV_CESA_FRAG_MIDDLE; ++ } ++ else ++ { ++ /* Continue fragment */ ++ fixOffset = 0; ++ cryptoOffset = 0; ++ macOffset = 0; ++ if( (pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) ++ { ++ /* Last fragment */ ++ config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); ++ pReq->fragMode = MV_CESA_FRAG_LAST; ++ copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ macDataSize = pCmd->macLength - pReq->frags.macSize; ++ ++ /* If pCmd->digestOffset is not located on last fragment */ ++ if(pCmd->digestOffset < pReq->frags.bufOffset) ++ { ++ /* Prepare dummy place for digest in SRAM */ ++ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); ++ } ++ else ++ { ++ digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; ++ } ++ pReq->frags.newDigestOffset = digestOffset; ++ macTotalLen = pCmd->macLength; ++ ++ /* HW can't calculate the Digest correctly for fragmented packets ++ * in the following cases: ++ * - MV88F5182 || ++ * - MV88F5181L when total macLength more that 16 Kbytes || ++ * - total macLength more that 64 Kbytes ++ */ ++ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || ++ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && ++ (mvCtrlRevGet() >= MV_5181L_A0_REV) && ++ (pCmd->macLength >= (1 << 14)) ) ) ++ { ++ return MV_TERMINATE; ++ } ++ } ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; ++ } ++ ++ /* cryptoIvOffset - don't care */ ++ } ++ else ++ { ++ /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ ++ if( (mvCtrlModelGet() == MV_5182_DEV_ID) && ++ (((pSA->config & MV_CESA_MAC_MODE_MASK) == ++ (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || ++ ((pSA->config & MV_CESA_MAC_MODE_MASK) == ++ (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET))) ) ++ { ++ pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); ++ pReq->fragMode = MV_CESA_FRAG_LAST; ++ ++ return MV_TERMINATE; ++ } ++ /* Middle fragment */ ++ config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); ++ copySize = sizeof(cesaSramVirtPtr->buf); ++ /* digestOffset and cryptoIvOffset - don't care */ ++ ++ /* Find fragment size */ ++ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, ++ ©Size, &cryptoDataSize, &macDataSize); ++ } ++ } ++ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ ++ pMbuf = pCmd->pSrc; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); ++ ++ /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ ++ mvCesaSramDescrBuild(config, frag, ++ cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, ++ cryptoDataSize, macOffset + fixOffset, ++ digestOffset + fixOffset, macDataSize, macTotalLen, ++ pReq, &pDmaDesc[i]); ++ i++; ++ ++ /* Add special descriptor Ownership for CPU */ ++ pDmaDesc[i].byteCnt = 0; ++ pDmaDesc[i].phySrcAdd = 0; ++ pDmaDesc[i].phyDestAdd = 0; ++ i++; ++ ++ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ ++ pMbuf = pCmd->pDst; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); ++ ++ /* Next field of Last DMA descriptor must be NULL */ ++ pDmaDesc[i-1].phyNextDescPtr = 0; ++ pReq->dma[frag].pDmaLast = &pDmaDesc[i-1]; ++ mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, ++ i*sizeof(MV_DMA_DESC)); ++ ++ /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]);*/ ++ ++ pReq->frags.bufOffset += copySize; ++ pReq->frags.cryptoSize += cryptoDataSize; ++ pReq->frags.macSize += macDataSize; ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCesaReqProcess - Process regular (Non-fragmented) request ++* ++* DESCRIPTION: ++* This function processes the whole (not fragmented) request ++* ++* INPUT: ++* MV_CESA_REQ* pReq - Pointer to the request in the request queue. ++* ++* RETURN: ++* MV_OK - The request is successfully passed to HW for processing. ++* Other - Failure. The request will not be processed ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq) ++{ ++ MV_CESA_MBUF *pMbuf; ++ MV_DMA_DESC *pDmaDesc; ++ MV_U8 *pSramBuf; ++ int sid, i, fixOffset; ++ MV_CESA_SA *pSA; ++ MV_CESA_COMMAND *pCmd = pReq->pCmd; ++ ++ cesaStats.procCount++; ++ ++ sid = pCmd->sessionId; ++ pSA = &pCesaSAD[sid]; ++ pDmaDesc = pReq->dma[0].pDmaFirst; ++ pSramBuf = cesaSramVirtPtr->buf; ++ fixOffset = pReq->fixOffset; ++ ++/* ++ mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", ++ sid, pSA, pDmaDesc, pSramBuf); ++*/ ++ i = 0; ++ ++ /* Crypto IV Special processing in CBC mode for Encryption direction */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && ++ ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && ++ ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && ++ (pCmd->ivFromUser) ) ++ { ++ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, ++ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place ++ * in the buffer to SRAM IVPointer ++ */ ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], ++ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ ++ /* Update SA in SRAM */ ++ if(cesaLastSid != sid) ++ { ++ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); ++ i++; ++ } ++ ++ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ ++ pMbuf = pCmd->pSrc; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); ++ ++ /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ ++ mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, ++ pCmd->ivOffset + fixOffset, pCmd->cryptoLength, ++ pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, ++ pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); ++ i++; ++ ++ /* Add special descriptor Ownership for CPU */ ++ pDmaDesc[i].byteCnt = 0; ++ pDmaDesc[i].phySrcAdd = 0; ++ pDmaDesc[i].phyDestAdd = 0; ++ i++; ++ ++ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ ++ pMbuf = pCmd->pDst; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); ++ ++ /* Next field of Last DMA descriptor must be NULL */ ++ pDmaDesc[i-1].phyNextDescPtr = 0; ++ pReq->dma[0].pDmaLast = &pDmaDesc[i-1]; ++ mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i*sizeof(MV_DMA_DESC)); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCesaSramDescrBuild - Set CESA descriptor in SRAM ++* ++* DESCRIPTION: ++* This function builds CESA descriptor in SRAM from all Command parameters ++* ++* ++* INPUT: ++* int chan - CESA channel uses the descriptor ++* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure ++* int cryptoOffset - Offset from the beginning of SRAM buffer where ++* data for encryption/decription is started. ++* int ivOffset - Offset of crypto IV from the SRAM base. Valid only ++* for first fragment. ++* int cryptoLength - Size (in bytes) of data for encryption/descryption ++* operation on this fragment. ++* int macOffset - Offset from the beginning of SRAM buffer where ++* data for Authentication is started ++* int digestOffset - Offset from the beginning of SRAM buffer where ++* digest is located. Valid for first and last fragments. ++* int macLength - Size (in bytes) of data for Authentication ++* operation on this fragment. ++* int macTotalLen - Toatl size (in bytes) of data for Authentication ++* operation on the whole request (packet). Valid for ++* last fragment only. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static void mvCesaSramDescrBuild(MV_U32 config, int frag, ++ int cryptoOffset, int ivOffset, int cryptoLength, ++ int macOffset, int digestOffset, int macLength, ++ int macTotalLen, MV_CESA_REQ* pReq, MV_DMA_DESC* pDmaDesc) ++{ ++ MV_CESA_DESC* pCesaDesc = &pReq->pCesaDesc[frag]; ++ MV_CESA_DESC* pSramDesc = pSramDesc = &cesaSramVirtPtr->desc; ++ MV_U16 sramBufOffset = (MV_U16)((MV_U8*)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); ++ ++ pCesaDesc->config = MV_32BIT_LE(config); ++ ++ if( (config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ /* word 1 */ ++ pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); ++ pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); ++ /* word 2 */ ++ pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); ++ /* word 3 */ ++ pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.cryptoKey - ++ mvCesaSramAddrGet())); ++ /* word 4 */ ++ pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->cryptoIV - ++ mvCesaSramAddrGet())); ++ pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); ++ } ++ ++ if( (config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ /* word 5 */ ++ pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); ++ pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); ++ ++ /* word 6 */ ++ pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); ++ pCesaDesc->macDataLen = MV_16BIT_LE(macLength); ++ ++ /* word 7 */ ++ pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macInnerIV - ++ mvCesaSramAddrGet())); ++ pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macOuterIV - ++ mvCesaSramAddrGet())); ++ } ++ /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ ++ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); ++ pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)pSramDesc)); ++ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); ++ ++ /* flush Source buffer */ ++ mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); ++} ++ ++/******************************************************************************* ++* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. ++* ++* DESCRIPTION: ++* Copy to SRAM values of the required SA. ++* ++* ++* INPUT: ++* short sid - Session ID needs SRAM Cache update ++* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to ++* copy SA values from DRAM to SRAM. ++* ++* RETURN: ++* MV_OK - Cache entry for this SA copied to SRAM. ++* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM ++* ++*******************************************************************************/ ++static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) ++{ ++ MV_CESA_SA *pSA = &pCesaSAD[sid]; ++ ++ /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ ++ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); ++ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pSA->pSramSA)); ++ pDmaDesc->phyDestAdd = ++ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)&cesaSramVirtPtr->sramSA)); ++ ++ /* Source buffer is already flushed during OpenSession*/ ++ /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA));*/ ++} ++ ++/******************************************************************************* ++* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by ++* Mbuf structure from DRAM to SRAM ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request ++* data in DRAM ++* MV_U8* pSramBuf - pointer to buffer in SRAM where data should ++* be copied to. ++* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. ++* The function set number of DMA descriptors needed ++* to copy the copySize bytes from Mbuf. ++* MV_BOOL isToMbuf - Copy direction. ++* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. ++* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. ++* int offset - Offset in the Mbuf structure that copy should be ++* started from. ++* int copySize - Size of data should be copied. ++* ++* RETURN: ++* int - number of DMA descriptors used for the copy. ++* ++*******************************************************************************/ ++#ifndef MV_NETBSD ++static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, ++ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, ++ int offset, int copySize, MV_BOOL skipFlush) ++{ ++ int bufOffset, bufSize, size, frag, i; ++ MV_U8* pBuf; ++ ++ i = 0; ++ ++ /* Calculate start place for copy: fragment number and offset in the fragment */ ++ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); ++ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; ++ ++ /* Size accumulate total copy size */ ++ size = 0; ++ ++ /* Create DMA lists to copy mBuf from pSrc to SRAM */ ++ while(size < copySize) ++ { ++ /* Find copy size for each DMA descriptor */ ++ bufSize = MV_MIN(bufSize, (copySize - size)); ++ pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); ++ if(isToMbuf) ++ { ++ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); ++ pDmaDesc[i].phySrcAdd = ++ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); ++ /* invalidate the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheInvalidate(NULL, pBuf, bufSize); ++ } ++ else ++ { ++ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); ++ pDmaDesc[i].phyDestAdd = ++ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); ++ /* flush the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheFlush(NULL, pBuf, bufSize); ++ } ++ ++ /* Count number of used DMA descriptors */ ++ i++; ++ size += bufSize; ++ ++ /* go to next fragment in the Mbuf */ ++ frag++; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr; ++ bufSize = pMbuf->pFrags[frag].bufSize; ++ } ++ return i; ++} ++#else /* MV_NETBSD */ ++static int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, ++ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, ++ int offset, int copySize, MV_BOOL skipFlush) ++{ ++ int bufOffset, bufSize, thisSize, size, frag, i; ++ MV_ULONG bufPhys, sramPhys; ++ MV_U8* pBuf; ++ ++ /* ++ * Calculate start place for copy: fragment number and offset in ++ * the fragment ++ */ ++ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); ++ ++ /* ++ * Get SRAM physical address only once. We can update it in-place ++ * as we build the descriptor chain. ++ */ ++ sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); ++ ++ /* ++ * 'size' accumulates total copy size, 'i' counts desccriptors. ++ */ ++ size = i = 0; ++ ++ /* Create DMA lists to copy mBuf from pSrc to SRAM */ ++ while (size < copySize) { ++ /* ++ * Calculate # of bytes to copy from the current fragment, ++ * and the pointer to the start of data ++ */ ++ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; ++ bufOffset = 0; /* First frag may be non-zero */ ++ frag++; ++ ++ /* ++ * As long as there is data in the current fragment... ++ */ ++ while (bufSize > 0) { ++ /* ++ * Ensure we don't cross an MMU page boundary. ++ * XXX: This is NetBSD-specific, but it is a ++ * quick and dirty way to fix the problem. ++ * A true HAL would rely on the OS-specific ++ * driver to do this... ++ */ ++ thisSize = PAGE_SIZE - ++ (((MV_ULONG)pBuf) & (PAGE_SIZE - 1)); ++ thisSize = MV_MIN(bufSize, thisSize); ++ /* ++ * Make sure we don't copy more than requested ++ */ ++ if (thisSize > (copySize - size)) { ++ thisSize = copySize - size; ++ bufSize = 0; ++ } ++ ++ /* ++ * Physicall address of this fragment ++ */ ++ bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); ++ ++ /* ++ * Set up the descriptor ++ */ ++ pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); ++ if(isToMbuf) { ++ pDmaDesc[i].phyDestAdd = bufPhys; ++ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); ++ /* invalidate the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheInvalidate(NULL, pBuf, thisSize); ++ } else { ++ pDmaDesc[i].phySrcAdd = bufPhys; ++ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); ++ /* flush the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheFlush(NULL, pBuf, thisSize); ++ } ++ ++ pDmaDesc[i].phyNextDescPtr = ++ MV_32BIT_LE(mvOsIoVirtToPhy(NULL,(&pDmaDesc[i+1]))); ++ ++ /* flush the DMA desc */ ++ mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); ++ ++ /* Update state */ ++ bufSize -= thisSize; ++ sramPhys += thisSize; ++ pBuf += thisSize; ++ size += thisSize; ++ i++; ++ } ++ } ++ ++ return i; ++} ++#endif /* MV_NETBSD */ ++/******************************************************************************* ++* mvCesaHmacIvGet - Calculate Inner and Outter values from HMAC key ++* ++* DESCRIPTION: ++* This function calculate Inner and Outer values used for HMAC algorithm. ++* This operation allows improve performance fro the whole HMAC processing. ++* ++* INPUT: ++* MV_CESA_MAC_MODE macMode - Authentication mode: HMAC_MD5 or HMAC_SHA1. ++* unsigned char key[] - Pointer to HMAC key. ++* int keyLength - Size of HMAC key (maximum 64 bytes) ++* ++* OUTPUT: ++* unsigned char innerIV[] - HASH(key^inner) ++* unsigned char outerIV[] - HASH(key^outter) ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, ++ unsigned char innerIV[], unsigned char outerIV[]) ++{ ++ unsigned char inner[MV_CESA_MAX_MAC_KEY_LENGTH]; ++ unsigned char outer[MV_CESA_MAX_MAC_KEY_LENGTH]; ++ int i, digestSize = 0; ++#if defined(MV_CPU_LE) || defined(MV_PPC) ++ MV_U32 swapped32, val32, *pVal32; ++#endif ++ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; ++ size = pMbuf->pFrags[frag].bufSize - fragOffset; ++ ++ /* Complete Inner part */ ++ while(macLeftSize > 0) ++ { ++ if(macLeftSize <= size) ++ { ++ mvSHA1Update(&ctx, pData, macLeftSize); ++ break; ++ } ++ mvSHA1Update(&ctx, pData, size); ++ macLeftSize -= size; ++ frag++; ++ pData = pMbuf->pFrags[frag].bufVirtPtr; ++ size = pMbuf->pFrags[frag].bufSize; ++ } ++ mvSHA1Final(pDigest, &ctx); ++/* ++ mvOsPrintf("mvCesaFragSha1Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", ++ pOuterIV, macLeftSize, macTotalSize); ++ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); ++*/ ++ ++ if(pOuterIV != NULL) ++ { ++ /* If HMAC - Complete Outer part */ ++ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; ++ size = pMbuf->pFrags[frag].bufSize - fragOffset; ++ ++ /* Complete Inner part */ ++ while(macLeftSize > 0) ++ { ++ if(macLeftSize <= size) ++ { ++ mvMD5Update(&ctx, pData, macLeftSize); ++ break; ++ } ++ mvMD5Update(&ctx, pData, size); ++ macLeftSize -= size; ++ frag++; ++ pData = pMbuf->pFrags[frag].bufVirtPtr; ++ size = pMbuf->pFrags[frag].bufSize; ++ } ++ mvMD5Final(pDigest, &ctx); ++ ++/* ++ mvOsPrintf("mvCesaFragMd5Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", ++ pOuterIV, macLeftSize, macTotalSize); ++ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); ++*/ ++ if(pOuterIV != NULL) ++ { ++ /* Complete Outer part */ ++ for(i=0; ipCmd; ++ MV_U8* pDigest; ++ MV_CESA_MAC_MODE macMode; ++ MV_U8* pOuterIV = NULL; ++ ++ /* Copy data from Source fragment to Destination */ ++ if(pCmd->pSrc != pCmd->pDst) ++ { ++ mvCesaMbufCopy(pCmd->pDst, pReq->frags.bufOffset, ++ pCmd->pSrc, pReq->frags.bufOffset, macDataSize); ++ } ++ ++/* ++ mvCesaCopyFromMbuf(cesaSramVirtPtr->buf[0], pCmd->pSrc, pReq->frags.bufOffset, macDataSize); ++ mvCesaCopyToMbuf(cesaSramVirtPtr->buf[0], pCmd->pDst, pReq->frags.bufOffset, macDataSize); ++*/ ++ pDigest = (mvCesaSramAddrGet() + pReq->frags.newDigestOffset); ++ ++ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; ++/* ++ mvOsPrintf("macDataSize=%d, macLength=%d, digestOffset=%d, macMode=%d\n", ++ macDataSize, pCmd->macLength, pCmd->digestOffset, macMode); ++*/ ++ switch(macMode) ++ { ++ case MV_CESA_MAC_HMAC_MD5: ++ pOuterIV = pSA->pSramSA->macOuterIV; ++ ++ case MV_CESA_MAC_MD5: ++ mvCesaFragMd5Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, ++ macDataSize, pCmd->macLength, pDigest); ++ break; ++ ++ case MV_CESA_MAC_HMAC_SHA1: ++ pOuterIV = pSA->pSramSA->macOuterIV; ++ ++ case MV_CESA_MAC_SHA1: ++ mvCesaFragSha1Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, ++ macDataSize, pCmd->macLength, pDigest); ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaFragAuthComplete: Unexpected macMode %d\n", macMode); ++ return MV_BAD_PARAM; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModeInit - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: NONE ++* ++* ++* RETURN: ++* MV_CESA_COMMAND* ++* ++*******************************************************************************/ ++static MV_CESA_COMMAND* mvCesaCtrModeInit(void) ++{ ++ MV_CESA_MBUF *pMbuf; ++ MV_U8 *pBuf; ++ MV_CESA_COMMAND *pCmd; ++ ++ pBuf = mvOsMalloc(sizeof(MV_CESA_COMMAND) + ++ sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) + 100); ++ if(pBuf == NULL) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Can't allocate %u bytes for CTR Mode\n", ++ sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) ); ++ return NULL; ++ } ++ pCmd = (MV_CESA_COMMAND*)pBuf; ++ pBuf += sizeof(MV_CESA_COMMAND); ++ ++ pMbuf = (MV_CESA_MBUF*)pBuf; ++ pBuf += sizeof(MV_CESA_MBUF); ++ ++ pMbuf->pFrags = (MV_BUF_INFO*)pBuf; ++ ++ pMbuf->numFrags = 1; ++ pCmd->pSrc = pMbuf; ++ pCmd->pDst = pMbuf; ++/* ++ mvOsPrintf("CtrModeInit: pCmd=%p, pSrc=%p, pDst=%p, pFrags=%p\n", ++ pCmd, pCmd->pSrc, pCmd->pDst, ++ pMbuf->pFrags); ++*/ ++ return pCmd; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModePrepare - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd) ++{ ++ MV_CESA_MBUF *pMbuf; ++ MV_U8 *pBuf, *pIV; ++ MV_U32 counter, *pCounter; ++ int cryptoSize = MV_ALIGN_UP(pCmd->cryptoLength, MV_CESA_AES_BLOCK_SIZE); ++/* ++ mvOsPrintf("CtrModePrepare: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", ++ pCmd, pCmd->pSrc, pCmd->pDst, ++ pCtrModeCmd, pCtrModeCmd->pSrc, pCtrModeCmd->pDst); ++*/ ++ pMbuf = pCtrModeCmd->pSrc; ++ ++ /* Allocate buffer for Key stream */ ++ pBuf = mvOsIoCachedMalloc(cesaOsHandle,cryptoSize, ++ &pMbuf->pFrags[0].bufPhysAddr, ++ &pMbuf->pFrags[0].memHandle); ++ if(pBuf == NULL) ++ { ++ mvOsPrintf("mvCesaCtrModePrepare: Can't allocate %d bytes\n", cryptoSize); ++ return MV_OUT_OF_CPU_MEM; ++ } ++ memset(pBuf, 0, cryptoSize); ++ mvOsCacheFlush(NULL, pBuf, cryptoSize); ++ ++ pMbuf->pFrags[0].bufVirtPtr = pBuf; ++ pMbuf->mbufSize = cryptoSize; ++ pMbuf->pFrags[0].bufSize = cryptoSize; ++ ++ pCtrModeCmd->pReqPrv = pCmd->pReqPrv; ++ pCtrModeCmd->sessionId = pCmd->sessionId; ++ ++ /* ivFromUser and ivOffset are don't care */ ++ pCtrModeCmd->cryptoOffset = 0; ++ pCtrModeCmd->cryptoLength = cryptoSize; ++ ++ /* digestOffset, macOffset and macLength are don't care */ ++ ++ mvCesaCopyFromMbuf(pBuf, pCmd->pSrc, pCmd->ivOffset, MV_CESA_AES_BLOCK_SIZE); ++ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); ++ counter = *pCounter; ++ counter = MV_32BIT_BE(counter); ++ pIV = pBuf; ++ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; ++ ++ /* fill key stream */ ++ while(cryptoSize > 0) ++ { ++ pBuf += MV_CESA_AES_BLOCK_SIZE; ++ memcpy(pBuf, pIV, MV_CESA_AES_BLOCK_SIZE - sizeof(counter)); ++ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); ++ counter++; ++ *pCounter = MV_32BIT_BE(counter); ++ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModeComplete - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd) ++{ ++ int srcFrag, dstFrag, srcOffset, dstOffset, keyOffset, srcSize, dstSize; ++ int cryptoSize = pCmd->cryptoLength; ++ MV_U8 *pSrc, *pDst, *pKey; ++ MV_STATUS status = MV_OK; ++/* ++ mvOsPrintf("CtrModeComplete: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", ++ pCmd, pCmd->pSrc, pCmd->pDst, ++ pOrgCmd, pOrgCmd->pSrc, pOrgCmd->pDst); ++*/ ++ /* XOR source data with key stream to destination data */ ++ pKey = pCmd->pDst->pFrags[0].bufVirtPtr; ++ keyOffset = 0; ++ ++ if( (pOrgCmd->pSrc != pOrgCmd->pDst) && ++ (pOrgCmd->cryptoOffset > 0) ) ++ { ++ /* Copy Prefix from source buffer to destination buffer */ ++ ++ status = mvCesaMbufCopy(pOrgCmd->pDst, 0, ++ pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); ++/* ++ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, ++ 0, pOrgCmd->cryptoOffset); ++ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, ++ 0, pOrgCmd->cryptoOffset); ++*/ ++ } ++ ++ srcFrag = mvCesaMbufOffset(pOrgCmd->pSrc, pOrgCmd->cryptoOffset, &srcOffset); ++ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; ++ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; ++ ++ dstFrag = mvCesaMbufOffset(pOrgCmd->pDst, pOrgCmd->cryptoOffset, &dstOffset); ++ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; ++ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; ++ ++ while(cryptoSize > 0) ++ { ++ pDst[dstOffset] = (pSrc[srcOffset] ^ pKey[keyOffset]); ++ ++ cryptoSize--; ++ dstOffset++; ++ srcOffset++; ++ keyOffset++; ++ ++ if(srcOffset >= srcSize) ++ { ++ srcFrag++; ++ srcOffset = 0; ++ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; ++ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; ++ } ++ ++ if(dstOffset >= dstSize) ++ { ++ dstFrag++; ++ dstOffset = 0; ++ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; ++ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; ++ } ++ } ++ ++ if(pOrgCmd->pSrc != pOrgCmd->pDst) ++ { ++ /* Copy Suffix from source buffer to destination buffer */ ++ srcOffset = pOrgCmd->cryptoOffset + pOrgCmd->cryptoLength; ++ ++ if( (pOrgCmd->pDst->mbufSize - srcOffset) > 0) ++ { ++ status = mvCesaMbufCopy(pOrgCmd->pDst, srcOffset, ++ pOrgCmd->pSrc, srcOffset, ++ pOrgCmd->pDst->mbufSize - srcOffset); ++ } ++ ++/* ++ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, ++ srcOffset, pOrgCmd->pSrc->mbufSize - srcOffset); ++ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, ++ srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); ++*/ ++ } ++ ++ /* Free buffer used for Key stream */ ++ mvOsIoCachedFree(cesaOsHandle,pCmd->pDst->pFrags[0].bufSize, ++ pCmd->pDst->pFrags[0].bufPhysAddr, ++ pCmd->pDst->pFrags[0].bufVirtPtr, ++ pCmd->pDst->pFrags[0].memHandle); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModeFinish - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_COMMAND* pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static void mvCesaCtrModeFinish(MV_CESA_COMMAND* pCmd) ++{ ++ mvOsFree(pCmd); ++} ++ ++/******************************************************************************* ++* mvCesaParamCheck - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, ++ MV_U8* pFixOffset) ++{ ++ MV_U8 fixOffset = 0xFF; ++ ++ /* Check AUTH operation parameters */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* MAC offset should be at least 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->macOffset, 4) ) ++ { ++ mvOsPrintf("mvCesaAction: macOffset %d must be 4 byte aligned\n", ++ pCmd->macOffset); ++ return MV_BAD_PARAM; ++ } ++ /* Digest offset must be 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->digestOffset, 4) ) ++ { ++ mvOsPrintf("mvCesaAction: digestOffset %d must be 4 byte aligned\n", ++ pCmd->digestOffset); ++ return MV_BAD_PARAM; ++ } ++ /* In addition all offsets should be the same alignment: 8 or 4 */ ++ if(fixOffset == 0xFF) ++ { ++ fixOffset = (pCmd->macOffset % 8); ++ } ++ else ++ { ++ if( (pCmd->macOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: macOffset %d mod 8 must be equal %d\n", ++ pCmd->macOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ if( (pCmd->digestOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: digestOffset %d mod 8 must be equal %d\n", ++ pCmd->digestOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ /* Check CRYPTO operation parameters */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* CryptoOffset should be at least 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->cryptoOffset, 4) ) ++ { ++ mvOsPrintf("CesaAction: cryptoOffset=%d must be 4 byte aligned\n", ++ pCmd->cryptoOffset); ++ return MV_BAD_PARAM; ++ } ++ /* cryptoLength should be the whole number of blocks */ ++ if( MV_IS_NOT_ALIGN(pCmd->cryptoLength, pSA->cryptoBlockSize) ) ++ { ++ mvOsPrintf("mvCesaAction: cryptoLength=%d must be %d byte aligned\n", ++ pCmd->cryptoLength, pSA->cryptoBlockSize); ++ return MV_BAD_PARAM; ++ } ++ if(fixOffset == 0xFF) ++ { ++ fixOffset = (pCmd->cryptoOffset % 8); ++ } ++ else ++ { ++ /* In addition all offsets should be the same alignment: 8 or 4 */ ++ if( (pCmd->cryptoOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: cryptoOffset %d mod 8 must be equal %d \n", ++ pCmd->cryptoOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ ++ /* check for CBC mode */ ++ if(pSA->cryptoIvSize > 0) ++ { ++ /* cryptoIV must not be part of CryptoLength */ ++ if( ((pCmd->ivOffset + pSA->cryptoIvSize) > pCmd->cryptoOffset) && ++ (pCmd->ivOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: cryptoIvOffset (%d) is part of cryptoLength (%d+%d)\n", ++ pCmd->ivOffset, pCmd->macOffset, pCmd->macLength); ++ return MV_BAD_PARAM; ++ } ++ ++ /* ivOffset must be 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->ivOffset, 4) ) ++ { ++ mvOsPrintf("CesaAction: ivOffset=%d must be 4 byte aligned\n", ++ pCmd->ivOffset); ++ return MV_BAD_PARAM; ++ } ++ /* In addition all offsets should be the same alignment: 8 or 4 */ ++ if( (pCmd->ivOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: ivOffset %d mod 8 must be %d\n", ++ pCmd->ivOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaFragParamCheck - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd) ++{ ++ int offset; ++ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* macOffset must be less that SRAM buffer size */ ++ if(pCmd->macOffset > (sizeof(cesaSramVirtPtr->buf) - MV_CESA_AUTH_BLOCK_SIZE)) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: macOffset is too large (%d)\n", ++ pCmd->macOffset); ++ return MV_BAD_PARAM; ++ } ++ /* macOffset+macSize must be more than mbufSize - SRAM buffer size */ ++ if( ((pCmd->macOffset + pCmd->macLength) > pCmd->pSrc->mbufSize) || ++ ((pCmd->pSrc->mbufSize - (pCmd->macOffset + pCmd->macLength)) >= ++ sizeof(cesaSramVirtPtr->buf)) ) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: macLength is too large (%d), mbufSize=%d\n", ++ pCmd->macLength, pCmd->pSrc->mbufSize); ++ return MV_BAD_PARAM; ++ } ++ } ++ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* cryptoOffset must be less that SRAM buffer size */ ++ /* 4 for possible fixOffset */ ++ if( (pCmd->cryptoOffset + 4) > (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: cryptoOffset is too large (%d)\n", ++ pCmd->cryptoOffset); ++ return MV_BAD_PARAM; ++ } ++ ++ /* cryptoOffset+cryptoSize must be more than mbufSize - SRAM buffer size */ ++ if( ((pCmd->cryptoOffset + pCmd->cryptoLength) > pCmd->pSrc->mbufSize) || ++ ((pCmd->pSrc->mbufSize - (pCmd->cryptoOffset + pCmd->cryptoLength)) >= ++ (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: cryptoLength is too large (%d), mbufSize=%d\n", ++ pCmd->cryptoLength, pCmd->pSrc->mbufSize); ++ return MV_BAD_PARAM; ++ } ++ } ++ ++ /* When MAC_THEN_CRYPTO or CRYPTO_THEN_MAC */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) == ++ (MV_CESA_MAC_THEN_CRYPTO << MV_CESA_OPERATION_OFFSET)) || ++ ((pSA->config & MV_CESA_OPERATION_MASK) == ++ (MV_CESA_CRYPTO_THEN_MAC << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || ++ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && ++ (mvCtrlRevGet() >= MV_5181L_A0_REV) && ++ (pCmd->macLength >= (1 << 14)) ) ) ++ { ++ return MV_NOT_ALLOWED; ++ } ++ ++ /* abs(cryptoOffset-macOffset) must be aligned cryptoBlockSize */ ++ if(pCmd->cryptoOffset > pCmd->macOffset) ++ { ++ offset = pCmd->cryptoOffset - pCmd->macOffset; ++ } ++ else ++ { ++ offset = pCmd->macOffset - pCmd->cryptoOffset; ++ } ++ ++ if( MV_IS_NOT_ALIGN(offset, pSA->cryptoBlockSize) ) ++ { ++/* ++ mvOsPrintf("mvCesaFragParamCheck: (cryptoOffset - macOffset) must be %d byte aligned\n", ++ pSA->cryptoBlockSize); ++*/ ++ return MV_NOT_ALLOWED; ++ } ++ /* Digest must not be part of CryptoLength */ ++ if( ((pCmd->digestOffset + pSA->digestSize) > pCmd->cryptoOffset) && ++ (pCmd->digestOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) ++ { ++/* ++ mvOsPrintf("mvCesaFragParamCheck: digestOffset (%d) is part of cryptoLength (%d+%d)\n", ++ pCmd->digestOffset, pCmd->cryptoOffset, pCmd->cryptoLength); ++*/ ++ return MV_NOT_ALLOWED; ++ } ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaFragSizeFind - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, ++* int cryptoOffset, int macOffset, ++* ++* OUTPUT: ++* int* pCopySize, int* pCryptoDataSize, int* pMacDataSize ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, ++ int cryptoOffset, int macOffset, ++ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize) ++{ ++ MV_CESA_COMMAND *pCmd = pReq->pCmd; ++ int cryptoDataSize, macDataSize, copySize; ++ ++ cryptoDataSize = macDataSize = 0; ++ copySize = *pCopySize; ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ cryptoDataSize = MV_MIN( (copySize - cryptoOffset), ++ (pCmd->cryptoLength - (pReq->frags.cryptoSize + 1)) ); ++ ++ /* cryptoSize for each fragment must be the whole number of blocksSize */ ++ if( MV_IS_NOT_ALIGN(cryptoDataSize, pSA->cryptoBlockSize) ) ++ { ++ cryptoDataSize = MV_ALIGN_DOWN(cryptoDataSize, pSA->cryptoBlockSize); ++ copySize = cryptoOffset + cryptoDataSize; ++ } ++ } ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ macDataSize = MV_MIN( (copySize - macOffset), ++ (pCmd->macLength - (pReq->frags.macSize + 1))); ++ ++ /* macSize for each fragment (except last) must be the whole number of blocksSize */ ++ if( MV_IS_NOT_ALIGN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE) ) ++ { ++ macDataSize = MV_ALIGN_DOWN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE); ++ copySize = macOffset + macDataSize; ++ } ++ cryptoDataSize = copySize - cryptoOffset; ++ } ++ *pCopySize = copySize; ++ ++ if(pCryptoDataSize != NULL) ++ *pCryptoDataSize = cryptoDataSize; ++ ++ if(pMacDataSize != NULL) ++ *pMacDataSize = macDataSize; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesa.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesa.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesa.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesa.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,412 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator ++* ++* DESCRIPTION: ++* This header file contains macros typedefs and function declaration for ++* the Marvell Cryptographic Engines and Security Accelerator. ++* ++*******************************************************************************/ ++ ++#ifndef __mvCesa_h__ ++#define __mvCesa_h__ ++ ++#include "mvOs.h" ++#include "mvCommon.h" ++#include "mvDebug.h" ++ ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#include "cesa/mvCesa.h" ++#include "cesa/AES/mvAes.h" ++#include "mvSysHwConfig.h" ++ ++#ifdef MV_INCLUDE_IDMA ++#include "idma/mvIdma.h" ++#include "idma/mvIdmaRegs.h" ++#else ++/* Redefine MV_DMA_DESC structure */ ++typedef struct _mvDmaDesc ++{ ++ MV_U32 byteCnt; /* The total number of bytes to transfer */ ++ MV_U32 phySrcAdd; /* The physical source address */ ++ MV_U32 phyDestAdd; /* The physical destination address */ ++ MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ ++ /* then this pointer should point to the */ ++ /* physical address of the next descriptor, */ ++ /* otherwise it should be NULL. */ ++}MV_DMA_DESC; ++#endif /* MV_INCLUDE_IDMA */ ++ ++#include "cesa/mvCesaRegs.h" ++ ++#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */ ++ ++#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */ ++#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */ ++ ++#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE ++ ++#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */ ++#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */ ++#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */ ++#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */ ++#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */ ++ ++#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH ++ ++#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */ ++#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */ ++ ++#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */ ++ ++#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE ++ ++#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */ ++ ++typedef struct ++{ ++ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; ++ MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH]; ++ MV_CESA_OPERATION operation; ++ MV_CESA_DIRECTION direction; ++ MV_CESA_CRYPTO_ALG cryptoAlgorithm; ++ MV_CESA_CRYPTO_MODE cryptoMode; ++ MV_U8 cryptoKeyLength; ++ MV_CESA_MAC_MODE macMode; ++ MV_U8 macKeyLength; ++ MV_U8 digestSize; ++ ++} MV_CESA_OPEN_SESSION; ++ ++typedef struct ++{ ++ MV_BUF_INFO *pFrags; ++ MV_U16 numFrags; ++ MV_U16 mbufSize; ++ ++} MV_CESA_MBUF; ++ ++typedef struct ++{ ++ void* pReqPrv; /* instead of reqId */ ++ MV_U32 retCode; ++ MV_16 sessionId; ++ ++} MV_CESA_RESULT; ++ ++typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult); ++ ++ ++typedef struct ++{ ++ void* pReqPrv; /* instead of reqId */ ++ MV_CESA_MBUF* pSrc; ++ MV_CESA_MBUF* pDst; ++ MV_CESA_CALLBACK* pFuncCB; ++ MV_16 sessionId; ++ MV_U16 ivFromUser; ++ MV_U16 ivOffset; ++ MV_U16 cryptoOffset; ++ MV_U16 cryptoLength; ++ MV_U16 digestOffset; ++ MV_U16 macOffset; ++ MV_U16 macLength; ++ MV_BOOL skipFlush; ++} MV_CESA_COMMAND; ++ ++ ++ ++MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle); ++MV_STATUS mvCesaFinish (void); ++MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid); ++MV_STATUS mvCesaSessionClose(short sid); ++MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize); ++ ++MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd); ++ ++MV_U32 mvCesaInProcessGet(void); ++MV_STATUS mvCesaReadyDispatch(void); ++MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult); ++MV_BOOL mvCesaIsReady(void); ++ ++int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset); ++MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf, ++ int offset, int size); ++MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf, ++ int offset, int size); ++MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, ++ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size); ++ ++/********** Debug functions ********/ ++ ++void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size); ++void mvCesaDebugSA(short sid, int mode); ++void mvCesaDebugStats(void); ++void mvCesaDebugStatsClear(void); ++void mvCesaDebugRegs(void); ++void mvCesaDebugStatus(void); ++void mvCesaDebugQueue(int mode); ++void mvCesaDebugSram(int mode); ++void mvCesaDebugSAD(int mode); ++ ++ ++/******** CESA Private definitions ********/ ++#if (MV_CESA_VERSION >= 2) ++#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW) ++#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ ++ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ ++ | MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \ ++ | MV_CESA_TDMA_NO_BYTE_SWAP_MASK \ ++ | MV_CESA_TDMA_ENABLE_MASK ++#else ++#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \ ++ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ ++ /*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\ ++ | MV_CESA_TDMA_ENABLE_MASK ++ ++#endif ++#else ++#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \ ++ | ICCLR_SRC_BURST_LIM_128BYTE \ ++ | ICCLR_INT_MODE_MASK \ ++ | ICCLR_BLOCK_MODE \ ++ | ICCLR_CHAN_ENABLE \ ++ | ICCLR_DESC_MODE_16M ++#endif /* MV_CESA_VERSION >= 2 */ ++ ++#define MV_CESA_MAX_PKT_SIZE (64 * 1024) ++#define MV_CESA_MAX_MBUF_FRAGS 20 ++ ++#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1) ++ ++#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5) ++ ++#define MAX_CESA_CHAIN_LENGTH 20 ++ ++typedef enum ++{ ++ MV_CESA_IDLE = 0, ++ MV_CESA_PENDING, ++ MV_CESA_PROCESS, ++ MV_CESA_READY, ++#if (MV_CESA_VERSION >= 3) ++ MV_CESA_CHAIN, ++#endif ++} MV_CESA_STATE; ++ ++ ++/* Session database */ ++ ++/* Map of Key materials of the session in SRAM. ++ * Each field must be 8 byte aligned ++ * Total size: 32 + 24 + 24 = 80 bytes ++ */ ++typedef struct ++{ ++ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; ++ MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE]; ++ MV_U8 reservedInner[4]; ++ MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE]; ++ MV_U8 reservedOuter[4]; ++ ++} MV_CESA_SRAM_SA; ++ ++typedef struct ++{ ++ MV_CESA_SRAM_SA* pSramSA; ++ MV_U32 config; ++ MV_U8 cryptoKeyLength; ++ MV_U8 cryptoIvSize; ++ MV_U8 cryptoBlockSize; ++ MV_U8 digestSize; ++ MV_U8 macKeyLength; ++ MV_U8 valid; ++ MV_U8 ctrMode; ++ MV_U32 count; ++ ++} MV_CESA_SA; ++ ++/* DMA list management */ ++typedef struct ++{ ++ MV_DMA_DESC* pDmaFirst; ++ MV_DMA_DESC* pDmaLast; ++ ++} MV_CESA_DMA; ++ ++ ++typedef struct ++{ ++ MV_U8 numFrag; ++ MV_U8 nextFrag; ++ int bufOffset; ++ int cryptoSize; ++ int macSize; ++ int newDigestOffset; ++ MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; ++ ++} MV_CESA_FRAGS; ++ ++/* Request queue */ ++typedef struct ++{ ++ MV_U8 state; ++ MV_U8 fragMode; ++ MV_U8 fixOffset; ++ MV_CESA_COMMAND* pCmd; ++ MV_CESA_COMMAND* pOrgCmd; ++ MV_BUF_INFO dmaDescBuf; ++ MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS]; ++ MV_BUF_INFO cesaDescBuf; ++ MV_CESA_DESC* pCesaDesc; ++ MV_CESA_FRAGS frags; ++ ++ ++} MV_CESA_REQ; ++ ++ ++/* SRAM map */ ++/* Total SRAM size calculation */ ++/* SRAM size = ++ * MV_CESA_MAX_BUF_SIZE + ++ * sizeof(MV_CESA_DESC) + ++ * MV_CESA_MAX_IV_LENGTH + ++ * MV_CESA_MAX_IV_LENGTH + ++ * MV_CESA_MAX_DIGEST_SIZE + ++ * sizeof(MV_CESA_SRAM_SA) ++ * = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes ++ * = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes ++ */ ++typedef struct ++{ ++ MV_U8 buf[MV_CESA_MAX_BUF_SIZE]; ++ MV_CESA_DESC desc; ++ MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH]; ++ MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH]; ++ MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4]; ++ MV_CESA_SRAM_SA sramSA; ++ ++} MV_CESA_SRAM_MAP; ++ ++ ++typedef struct ++{ ++ MV_U32 openedCount; ++ MV_U32 closedCount; ++ MV_U32 fragCount; ++ MV_U32 reqCount; ++ MV_U32 maxReqCount; ++ MV_U32 procCount; ++ MV_U32 readyCount; ++ MV_U32 notReadyCount; ++ MV_U32 startCount; ++#if (MV_CESA_VERSION >= 3) ++ MV_U32 maxChainUsage; ++#endif ++ ++} MV_CESA_STATS; ++ ++ ++/* External variables */ ++ ++extern MV_CESA_STATS cesaStats; ++extern MV_CESA_FRAGS cesaFrags; ++ ++extern MV_BUF_INFO cesaSramSaBuf; ++ ++extern MV_CESA_SA* pCesaSAD; ++extern MV_U16 cesaMaxSA; ++ ++extern MV_CESA_REQ* pCesaReqFirst; ++extern MV_CESA_REQ* pCesaReqLast; ++extern MV_CESA_REQ* pCesaReqEmpty; ++extern MV_CESA_REQ* pCesaReqProcess; ++extern int cesaQueueDepth; ++extern int cesaReqResources; ++#if (MV_CESA_VERSION>= 3) ++extern MV_U32 cesaChainLength; ++#endif ++ ++extern MV_CESA_SRAM_MAP* cesaSramVirtPtr; ++extern MV_U32 cesaSramPhysAddr; ++ ++static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt) ++{ ++ return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr)); ++} ++ ++/* Additional DEBUG functions */ ++void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode); ++void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode); ++void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc); ++ ++ ++ ++#endif /* __mvCesa_h__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaDebug.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,484 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvDebug.h" ++ ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#include "cesa/mvCesa.h" ++#include "cesa/mvCesaRegs.h" ++#include "cesa/AES/mvAes.h" ++ ++static const char* mvCesaDebugStateStr(MV_CESA_STATE state) ++{ ++ switch(state) ++ { ++ case MV_CESA_IDLE: ++ return "Idle"; ++ ++ case MV_CESA_PENDING: ++ return "Pend"; ++ ++ case MV_CESA_PROCESS: ++ return "Proc"; ++ ++ case MV_CESA_READY: ++ return "Ready"; ++ ++ default: ++ break; ++ } ++ return "Unknown"; ++} ++ ++static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper) ++{ ++ switch(oper) ++ { ++ case MV_CESA_MAC_ONLY: ++ return "MacOnly"; ++ ++ case MV_CESA_CRYPTO_ONLY: ++ return "CryptoOnly"; ++ ++ case MV_CESA_MAC_THEN_CRYPTO: ++ return "MacCrypto"; ++ ++ case MV_CESA_CRYPTO_THEN_MAC: ++ return "CryptoMac"; ++ ++ default: ++ break; ++ } ++ return "Null"; ++} ++ ++static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg) ++{ ++ switch(cryptoAlg) ++ { ++ case MV_CESA_CRYPTO_DES: ++ return "DES"; ++ ++ case MV_CESA_CRYPTO_3DES: ++ return "3DES"; ++ ++ case MV_CESA_CRYPTO_AES: ++ return "AES"; ++ ++ default: ++ break; ++ } ++ return "Null"; ++} ++ ++static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode) ++{ ++ switch(macMode) ++ { ++ case MV_CESA_MAC_MD5: ++ return "MD5"; ++ ++ case MV_CESA_MAC_SHA1: ++ return "SHA1"; ++ ++ case MV_CESA_MAC_HMAC_MD5: ++ return "HMAC-MD5"; ++ ++ case MV_CESA_MAC_HMAC_SHA1: ++ return "HMAC_SHA1"; ++ ++ default: ++ break; ++ } ++ return "Null"; ++} ++ ++void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode) ++{ ++ mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n", ++ pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst, ++ pCmd->pFuncCB, pCmd->sessionId); ++ mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n", ++ pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength, ++ pCmd->digestOffset, pCmd->macOffset, pCmd->macLength); ++} ++ ++/* no need to use in tool */ ++void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size) ++{ ++ int frag, len, fragOffset; ++ ++ if(str != NULL) ++ mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n", ++ str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize); ++ ++ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return; ++ } ++ ++ for(; fragnumFrags; frag++) ++ { ++ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", ++ frag, pMbuf->pFrags[frag].bufVirtPtr, ++ pMbuf->pFrags[frag].bufSize); ++ if(size > 0) ++ { ++ len = MV_MIN(pMbuf->pFrags[frag].bufSize, size); ++ mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1); ++ size -= len; ++ fragOffset = 0; ++ } ++ } ++} ++ ++void mvCesaDebugRegs(void) ++{ ++ mvOsPrintf("\t CESA Registers:\n"); ++ ++ mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n", ++ MV_CESA_CMD_REG, ++ MV_REG_READ( MV_CESA_CMD_REG ) ); ++ ++ mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n", ++ MV_CESA_CHAN_DESC_OFFSET_REG, ++ MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) ); ++ ++ mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n", ++ MV_CESA_CFG_REG, ++ MV_REG_READ( MV_CESA_CFG_REG ) ); ++ ++ mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n", ++ MV_CESA_STATUS_REG, ++ MV_REG_READ( MV_CESA_STATUS_REG ) ); ++ ++ mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n", ++ MV_CESA_ISR_CAUSE_REG, ++ MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) ); ++ ++ mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n", ++ MV_CESA_ISR_MASK_REG, ++ MV_REG_READ( MV_CESA_ISR_MASK_REG ) ); ++#if (MV_CESA_VERSION >= 2) ++ mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_CTRL_REG, ++ MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_BYTE_COUNT_REG, ++ MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_SRC_ADDR_REG, ++ MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_DST_ADDR_REG, ++ MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_NEXT_DESC_PTR_REG, ++ MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_CURR_DESC_PTR_REG, ++ MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_ERROR_CAUSE_REG, ++ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_ERROR_MASK_REG, ++ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); ++ ++#endif ++} ++ ++void mvCesaDebugStatus(void) ++{ ++ mvOsPrintf("\n\t CESA Status\n\n"); ++ ++ mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ", ++ pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ), ++ cesaReqResources); ++#if (MV_CESA_VERSION >= 3) ++ mvOsPrintf("chainLength=%u\n",cesaChainLength); ++#else ++ mvOsPrintf("\n"); ++#endif ++ ++ mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n", ++ pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA)); ++ ++ mvOsPrintf("\n"); ++ ++ mvCesaDebugRegs(); ++ mvCesaDebugStats(); ++ mvCesaDebugStatsClear(); ++} ++ ++void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc) ++{ ++ mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n", ++ pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset); ++ ++ mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n", ++ pDesc->cryptoDataLen, pDesc->cryptoKeyOffset, ++ pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset); ++ ++ mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n", ++ pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen, ++ pDesc->macInnerIvOffset, pDesc->macOuterIvOffset); ++} ++ ++void mvCesaDebugQueue(int mode) ++{ ++ mvOsPrintf("\n\t CESA Request Queue:\n\n"); ++ ++ mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n", ++ pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ)); ++ ++ mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n", ++ pCesaReqEmpty, pCesaReqProcess, ++ cesaReqResources); ++ ++ if(mode != 0) ++ { ++ int count = 0; ++ MV_CESA_REQ* pReq = pCesaReqFirst; ++ ++ for(count=0; countstate), ++ pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]); ++ if(pReq->fragMode != MV_CESA_FRAG_NONE) ++ { ++ int frag; ++ ++ mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n", ++ &pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag, ++ pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize); ++ for(frag=0; fragfrags.numFrag; frag++) ++ { ++ mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag, ++ pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]); ++ } ++ } ++ if(mode > 1) ++ { ++ /* Print out Command */ ++ mvCesaDebugCmd(pReq->pCmd, mode); ++ ++ /* Print out Descriptor */ ++ mvCesaDebugDescriptor(&pReq->pCesaDesc[0]); ++ } ++ pReq++; ++ } ++ } ++} ++ ++ ++void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode) ++{ ++ if(pSramSA == NULL) ++ { ++ mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA); ++ return; ++ } ++ mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n", ++ pSramSA, sizeof(MV_CESA_SRAM_SA)); ++ ++ if(mode != 0) ++ { ++ mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n", ++ pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH); ++ mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1); ++ ++ mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n", ++ pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE); ++ mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1); ++ ++ mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n", ++ pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE); ++ mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1); ++ } ++} ++ ++void mvCesaDebugSA(short sid, int mode) ++{ ++ MV_CESA_OPERATION oper; ++ MV_CESA_DIRECTION dir; ++ MV_CESA_CRYPTO_ALG cryptoAlg; ++ MV_CESA_CRYPTO_MODE cryptoMode; ++ MV_CESA_MAC_MODE macMode; ++ MV_CESA_SA* pSA = &pCesaSAD[sid]; ++ ++ if( (pSA->valid) || ((pSA->count != 0) && (mode > 0)) || (mode >= 2) ) ++ { ++ mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n", ++ sid, pSA, ++ pSA->valid ? "Valid" : "Invalid", pSA->count); ++ ++ oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET; ++ dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT; ++ mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper), ++ (dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode"); ++ if(oper != MV_CESA_MAC_ONLY) ++ { ++ cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET; ++ cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT; ++ mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg), ++ (cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC"); ++ } ++ if(oper != MV_CESA_CRYPTO_ONLY) ++ { ++ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; ++ mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode)); ++ } ++ mvOsPrintf("\n"); ++ ++ if(mode > 0) ++ { ++ mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n", ++ pCesaSAD[sid].config, pCesaSAD[sid].cryptoKeyLength, ++ pCesaSAD[sid].digestSize); ++ ++ mvCesaDebugSramSA(pCesaSAD[sid].pSramSA, mode); ++ } ++ } ++} ++ ++ ++/**/ ++void mvCesaDebugSram(int mode) ++{ ++ mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n", ++ sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr); ++ ++ mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n", ++ MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf); ++ if(mode != 0) ++ mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1); ++ ++ mvOsPrintf("\n"); ++ mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n", ++ sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc); ++ if(mode != 0) ++ { ++ mvOsPrintf("\n"); ++ mvCesaDebugDescriptor(&cesaSramVirtPtr->desc); ++ } ++ mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n", ++ MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV); ++ if(mode != 0) ++ { ++ mvOsPrintf("\n"); ++ mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1); ++ } ++ mvOsPrintf("\n"); ++ mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0); ++} ++ ++void mvCesaDebugSAD(int mode) ++{ ++ int sid; ++ ++ mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n", ++ pCesaSAD, cesaMaxSA); ++ ++ for(sid=0; sid= 3) ++ mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage); ++#endif ++ mvOsPrintf("\n"); ++ mvOsPrintf("proc=%u, ready=%u, notReady=%u\n", ++ cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount); ++} ++ ++void mvCesaDebugStatsClear(void) ++{ ++ memset(&cesaStats, 0, sizeof(cesaStats)); ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,357 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvCesaRegs_h__ ++#define __mvCesaRegs_h__ ++ ++#include "mvTypes.h" ++ ++typedef struct ++{ ++ /* word 0 */ ++ MV_U32 config; ++ /* word 1 */ ++ MV_U16 cryptoSrcOffset; ++ MV_U16 cryptoDstOffset; ++ /* word 2 */ ++ MV_U16 cryptoDataLen; ++ MV_U16 reserved1; ++ /* word 3 */ ++ MV_U16 cryptoKeyOffset; ++ MV_U16 reserved2; ++ /* word 4 */ ++ MV_U16 cryptoIvOffset; ++ MV_U16 cryptoIvBufOffset; ++ /* word 5 */ ++ MV_U16 macSrcOffset; ++ MV_U16 macTotalLen; ++ /* word 6 */ ++ MV_U16 macDigestOffset; ++ MV_U16 macDataLen; ++ /* word 7 */ ++ MV_U16 macInnerIvOffset; ++ MV_U16 macOuterIvOffset; ++ ++} MV_CESA_DESC; ++ ++/* operation */ ++typedef enum ++{ ++ MV_CESA_MAC_ONLY = 0, ++ MV_CESA_CRYPTO_ONLY = 1, ++ MV_CESA_MAC_THEN_CRYPTO = 2, ++ MV_CESA_CRYPTO_THEN_MAC = 3, ++ ++ MV_CESA_MAX_OPERATION ++ ++} MV_CESA_OPERATION; ++ ++#define MV_CESA_OPERATION_OFFSET 0 ++#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET) ++ ++/* mac algorithm */ ++typedef enum ++{ ++ MV_CESA_MAC_NULL = 0, ++ MV_CESA_MAC_MD5 = 4, ++ MV_CESA_MAC_SHA1 = 5, ++ MV_CESA_MAC_HMAC_MD5 = 6, ++ MV_CESA_MAC_HMAC_SHA1 = 7, ++ ++} MV_CESA_MAC_MODE; ++ ++#define MV_CESA_MAC_MODE_OFFSET 4 ++#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET) ++ ++typedef enum ++{ ++ MV_CESA_MAC_DIGEST_FULL = 0, ++ MV_CESA_MAC_DIGEST_96B = 1, ++ ++} MV_CESA_MAC_DIGEST_SIZE; ++ ++#define MV_CESA_MAC_DIGEST_SIZE_BIT 7 ++#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT) ++ ++ ++typedef enum ++{ ++ MV_CESA_CRYPTO_NULL = 0, ++ MV_CESA_CRYPTO_DES = 1, ++ MV_CESA_CRYPTO_3DES = 2, ++ MV_CESA_CRYPTO_AES = 3, ++ ++} MV_CESA_CRYPTO_ALG; ++ ++#define MV_CESA_CRYPTO_ALG_OFFSET 8 ++#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET) ++ ++ ++/* direction */ ++typedef enum ++{ ++ MV_CESA_DIR_ENCODE = 0, ++ MV_CESA_DIR_DECODE = 1, ++ ++} MV_CESA_DIRECTION; ++ ++#define MV_CESA_DIRECTION_BIT 12 ++#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT) ++ ++/* crypto IV mode */ ++typedef enum ++{ ++ MV_CESA_CRYPTO_ECB = 0, ++ MV_CESA_CRYPTO_CBC = 1, ++ ++ /* NO HW Support */ ++ MV_CESA_CRYPTO_CTR = 10, ++ ++} MV_CESA_CRYPTO_MODE; ++ ++#define MV_CESA_CRYPTO_MODE_BIT 16 ++#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) ++ ++/* 3DES mode */ ++typedef enum ++{ ++ MV_CESA_CRYPTO_3DES_EEE = 0, ++ MV_CESA_CRYPTO_3DES_EDE = 1, ++ ++} MV_CESA_CRYPTO_3DES_MODE; ++ ++#define MV_CESA_CRYPTO_3DES_MODE_BIT 20 ++#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT) ++ ++ ++/* AES Key Length */ ++typedef enum ++{ ++ MV_CESA_CRYPTO_AES_KEY_128 = 0, ++ MV_CESA_CRYPTO_AES_KEY_192 = 1, ++ MV_CESA_CRYPTO_AES_KEY_256 = 2, ++ ++} MV_CESA_CRYPTO_AES_KEY_LEN; ++ ++#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24 ++#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET) ++ ++/* Fragmentation mode */ ++typedef enum ++{ ++ MV_CESA_FRAG_NONE = 0, ++ MV_CESA_FRAG_FIRST = 1, ++ MV_CESA_FRAG_LAST = 2, ++ MV_CESA_FRAG_MIDDLE = 3, ++ ++} MV_CESA_FRAG_MODE; ++ ++#define MV_CESA_FRAG_MODE_OFFSET 30 ++#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET) ++/*---------------------------------------------------------------------------*/ ++ ++/********** Security Accelerator Command Register **************/ ++#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00) ++ ++#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 ++#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT) ++ ++#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 ++#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) ++ ++/********** Security Accelerator Descriptor Pointers Register **********/ ++#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04) ++ ++/********** Security Accelerator Configuration Register **********/ ++#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08) ++ ++#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0 ++#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT) ++ ++#define MV_CESA_CFG_WAIT_DMA_BIT 7 ++#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT) ++ ++#define MV_CESA_CFG_ACT_DMA_BIT 9 ++#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT) ++ ++#define MV_CESA_CFG_CHAIN_MODE_BIT 11 ++#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT) ++ ++/********** Security Accelerator Status Register ***********/ ++#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C) ++ ++#define MV_CESA_STATUS_ACTIVE_BIT 0 ++#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT) ++ ++#define MV_CESA_STATUS_DIGEST_ERR_BIT 8 ++#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT) ++ ++ ++/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */ ++#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20) ++ ++/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */ ++#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24) ++ ++#define MV_CESA_CAUSE_AUTH_MASK (1 << 0) ++#define MV_CESA_CAUSE_DES_MASK (1 << 1) ++#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2) ++#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3) ++#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4) ++ ++#define MV_CESA_CAUSE_ACC_BIT 5 ++#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT) ++ ++#define MV_CESA_CAUSE_ACC_DMA_BIT 7 ++#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT) ++#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT) ++ ++#define MV_CESA_CAUSE_DMA_COMPL_BIT 9 ++#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT) ++ ++#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10 ++#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT) ++ ++#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11 ++#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT) ++ ++ ++#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38) ++#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20) ++#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24) ++ ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2)) ++ ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10) ++#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18) ++ ++#define MV_CESA_AUTH_ALGORITHM_BIT 0 ++#define MV_CESA_AUTH_ALGORITHM_MD5 (0< ++wait_queue_head_t cesaTest_waitq; ++spinlock_t cesaLock; ++ ++#define CESA_TEST_LOCK(flags) spin_lock_irqsave( &cesaLock, flags) ++#define CESA_TEST_UNLOCK(flags) spin_unlock_irqrestore( &cesaLock, flags); ++ ++#define CESA_TEST_WAIT_INIT() init_waitqueue_head(&cesaTest_waitq) ++#define CESA_TEST_WAKE_UP() wake_up(&cesaTest_waitq) ++#define CESA_TEST_WAIT(cond, ms) wait_event_timeout(cesaTest_waitq, (cond), msecs_to_jiffies(ms)) ++ ++#define CESA_TEST_TICK_GET() jiffies ++#define CESA_TEST_TICK_TO_MS(tick) jiffies_to_msecs(tick) ++ ++#elif defined(MV_NETBSD) ++ ++#include ++#include ++static int cesaLock; ++ ++#define CESA_TEST_LOCK(flags) flags = splnet() ++#define CESA_TEST_UNLOCK(flags) splx(flags) ++ ++#define CESA_TEST_WAIT_INIT() /* nothing */ ++#define CESA_TEST_WAKE_UP() wakeup(&cesaLock) ++#define CESA_TEST_WAIT(cond, ms) \ ++do { \ ++ while (!(cond)) \ ++ tsleep(&cesaLock, PWAIT, "cesatest",mstohz(ms)); \ ++} while (/*CONSTCOND*/0) ++ ++#define CESA_TEST_TICK_GET() hardclock_ticks ++#define CESA_TEST_TICK_TO_MS(tick) ((1000/hz)*(tick)) ++ ++#define request_irq(i,h,t,n,a) \ ++ !mv_intr_establish((i),IPL_NET,(int(*)(void *))(h),(a)) ++ ++#else ++#error "Only Linux, VxWorks, or NetBSD OS are supported" ++#endif ++ ++#include "mvDebug.h" ++ ++#include "mvSysHwConfig.h" ++#include "boardEnv/mvBoardEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "cntmr/mvCntmr.h" ++#include "cesa/mvCesa.h" ++#include "cesa/mvCesaRegs.h" ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#if defined(CONFIG_MV646xx) ++#include "marvell_pic.h" ++#endif ++ ++#define MV_CESA_USE_TIMER_ID 0 ++#define CESA_DEF_BUF_SIZE 1500 ++#define CESA_DEF_BUF_NUM 1 ++#define CESA_DEF_SESSION_NUM 32 ++ ++#define CESA_DEF_ITER_NUM 100 ++ ++#define CESA_DEF_REQ_SIZE 256 ++ ++ ++/* CESA Tests Debug */ ++#undef CESA_TEST_DEBUG ++ ++#ifdef CESA_TEST_DEBUG ++ ++# define CESA_TEST_DEBUG_PRINT(msg) mvOsPrintf msg ++# define CESA_TEST_DEBUG_CODE(code) code ++ ++typedef struct ++{ ++ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ ++ MV_U32 timeStamp; ++ MV_U32 cause; ++ MV_U32 realCause; ++ MV_U32 dmaCause; ++ int resources; ++ MV_CESA_REQ* pReqReady; ++ MV_CESA_REQ* pReqEmpty; ++ MV_CESA_REQ* pReqProcess; ++} MV_CESA_TEST_TRACE; ++ ++#define MV_CESA_TEST_TRACE_SIZE 25 ++ ++static int cesaTestTraceIdx = 0; ++static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; ++ ++static void cesaTestTraceAdd(int type, MV_U32 cause) ++{ ++ cesaTestTrace[cesaTestTraceIdx].type = type; ++ cesaTestTrace[cesaTestTraceIdx].cause = cause; ++ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ cesaTestTrace[cesaTestTraceIdx].dmaCause = MV_REG_READ(IDMA_CAUSE_REG); ++ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; ++ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; ++ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; ++ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; ++ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); ++ cesaTestTraceIdx++; ++ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) ++ cesaTestTraceIdx = 0; ++} ++ ++#else ++ ++# define CESA_TEST_DEBUG_PRINT(msg) ++# define CESA_TEST_DEBUG_CODE(code) ++ ++#endif /* CESA_TEST_DEBUG */ ++ ++int cesaExpReqId=0; ++int cesaCbIter=0; ++ ++int cesaIdx; ++int cesaIteration; ++int cesaRateSize; ++int cesaReqSize; ++unsigned long cesaTaskId; ++int cesaBufNum; ++int cesaBufSize; ++int cesaCheckOffset; ++int cesaCheckSize; ++int cesaCheckMode; ++int cesaTestIdx; ++int cesaCaseIdx; ++ ++ ++MV_U32 cesaTestIsrCount = 0; ++MV_U32 cesaTestIsrMissCount = 0; ++ ++MV_U32 cesaCryptoError = 0; ++MV_U32 cesaReqIdError = 0; ++MV_U32 cesaError = 0; ++ ++char* cesaHexBuffer = NULL; ++ ++char* cesaBinBuffer = NULL; ++char* cesaExpBinBuffer = NULL; ++ ++char* cesaInputHexStr = NULL; ++char* cesaOutputHexStr = NULL; ++ ++MV_BUF_INFO cesaReqBufs[CESA_DEF_REQ_SIZE]; ++ ++MV_CESA_COMMAND* cesaCmdRing; ++MV_CESA_RESULT cesaResult; ++ ++int cesaTestFull = 0; ++ ++MV_BOOL cesaIsReady = MV_FALSE; ++MV_U32 cesaCycles = 0; ++MV_U32 cesaBeginTicks = 0; ++MV_U32 cesaEndTicks = 0; ++MV_U32 cesaRate = 0; ++MV_U32 cesaRateAfterDot = 0; ++ ++void *cesaTestOSHandle = NULL; ++ ++enum ++{ ++ CESA_FAST_CHECK_MODE = 0, ++ CESA_FULL_CHECK_MODE, ++ CESA_NULL_CHECK_MODE, ++ CESA_SHOW_CHECK_MODE, ++ CESA_SW_SHOW_CHECK_MODE, ++ CESA_SW_NULL_CHECK_MODE, ++ ++ CESA_MAX_CHECK_MODE ++}; ++ ++enum ++{ ++ DES_TEST_TYPE = 0, ++ TRIPLE_DES_TEST_TYPE = 1, ++ AES_TEST_TYPE = 2, ++ MD5_TEST_TYPE = 3, ++ SHA_TEST_TYPE = 4, ++ COMBINED_TEST_TYPE = 5, ++ ++ MAX_TEST_TYPE ++}; ++ ++/* Tests data base */ ++typedef struct ++{ ++ short sid; ++ char cryptoAlgorithm; /* DES/3DES/AES */ ++ char cryptoMode; /* ECB or CBC */ ++ char macAlgorithm; /* MD5 / SHA1 */ ++ char operation; /* CRYPTO/HMAC/CRYPTO+HMAC/HMAC+CRYPTO */ ++ char direction; /* ENCODE(SIGN)/DECODE(VERIFY) */ ++ unsigned char* pCryptoKey; ++ int cryptoKeySize; ++ unsigned char* pMacKey; ++ int macKeySize; ++ const char* name; ++ ++} MV_CESA_TEST_SESSION; ++ ++typedef struct ++{ ++ MV_CESA_TEST_SESSION* pSessions; ++ int numSessions; ++ ++} MV_CESA_TEST_DB_ENTRY; ++ ++typedef struct ++{ ++ char* plainHexStr; ++ char* cipherHexStr; ++ unsigned char* pCryptoIV; ++ int cryptoLength; ++ int macLength; ++ int digestOffset; ++ ++} MV_CESA_TEST_CASE; ++ ++typedef struct ++{ ++ int size; ++ const char* outputHexStr; ++ ++} MV_CESA_SIZE_TEST; ++ ++static unsigned char cryptoKey1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, ++ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, ++ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; ++ ++static unsigned char cryptoKey7[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; ++static unsigned char iv1[] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef}; ++ ++ ++static unsigned char cryptoKey2[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; ++ ++static unsigned char cryptoKey3[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; ++ ++static unsigned char cryptoKey4[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, ++ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}; ++ ++static unsigned char cryptoKey5[] = {0x56, 0xe4, 0x7a, 0x38, 0xc5, 0x59, 0x89, 0x74, ++ 0xbc, 0x46, 0x90, 0x3d, 0xba, 0x29, 0x03, 0x49}; ++ ++ ++static unsigned char key3des1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, ++ 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, ++ 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, 0x23}; ++ ++/* Input ASCII string: The quick brown fox jump */ ++static char plain3des1[] = "54686520717566636B2062726F776E20666F78206A756D70"; ++static char cipher3des1[] = "A826FD8CE53B855FCCE21C8112256FE668D5C05DD9B6B900"; ++ ++static unsigned char key3des2[] = {0x62, 0x7f, 0x46, 0x0e, 0x08, 0x10, 0x4a, 0x10, ++ 0x43, 0xcd, 0x26, 0x5d, 0x58, 0x40, 0xea, 0xf1, ++ 0x31, 0x3e, 0xdf, 0x97, 0xdf, 0x2a, 0x8a, 0x8c}; ++ ++static unsigned char iv3des2[] = {0x8e, 0x29, 0xf7, 0x5e, 0xa7, 0x7e, 0x54, 0x75}; ++ ++static char plain3des2[] = "326a494cd33fe756"; ++ ++static char cipher3desCbc2[] = "8e29f75ea77e5475" ++ "b22b8d66de970692"; ++ ++static unsigned char key3des3[] = {0x37, 0xae, 0x5e, 0xbf, 0x46, 0xdf, 0xf2, 0xdc, ++ 0x07, 0x54, 0xb9, 0x4f, 0x31, 0xcb, 0xb3, 0x85, ++ 0x5e, 0x7f, 0xd3, 0x6d, 0xc8, 0x70, 0xbf, 0xae}; ++ ++static unsigned char iv3des3[] = {0x3d, 0x1d, 0xe3, 0xcc, 0x13, 0x2e, 0x3b, 0x65}; ++ ++static char plain3des3[] = "84401f78fe6c10876d8ea23094ea5309"; ++ ++static char cipher3desCbc3[] = "3d1de3cc132e3b65" ++ "7b1f7c7e3b1c948ebd04a75ffba7d2f5"; ++ ++static unsigned char iv5[] = {0x8c, 0xe8, 0x2e, 0xef, 0xbe, 0xa0, 0xda, 0x3c, ++ 0x44, 0x69, 0x9e, 0xd7, 0xdb, 0x51, 0xb7, 0xd9}; ++ ++static unsigned char aesCtrKey[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, ++ 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; ++ ++static unsigned char mdKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, ++ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b}; ++ ++static unsigned char mdKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}; ++ ++static unsigned char shaKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, ++ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, ++ 0x0b, 0x0b, 0x0b, 0x0b}; ++ ++static unsigned char shaKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ 0xaa, 0xaa, 0xaa, 0xaa}; ++ ++static unsigned char mdKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10}; ++ ++static unsigned char shaKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, ++ 0x11, 0x12, 0x13, 0x14}; ++ ++ ++static MV_CESA_TEST_SESSION desTestSessions[] = ++{ ++/*000*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES ECB encode", ++ }, ++/*001*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES ECB decode", ++ }, ++/*002*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES CBC encode" ++ }, ++/*003*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES CBC decode" ++ }, ++/*004*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, NULL, 0, ++ "NULL Crypto Algorithm encode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION tripleDesTestSessions[] = ++{ ++/*100*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES ECB encode", ++ }, ++/*101*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES ECB decode", ++ }, ++/*102*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES CBC encode" ++ }, ++/*103*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES CBC decode" ++ }, ++/*104*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ key3des1, sizeof(key3des1), ++ NULL, 0, ++ "3DES ECB encode" ++ }, ++/*105*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ key3des2, sizeof(key3des2), ++ NULL, 0, ++ "3DES ECB encode" ++ }, ++/*106*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ key3des3, sizeof(key3des3), ++ NULL, 0, ++ "3DES ECB encode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION aesTestSessions[] = ++{ ++/*200*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), ++ NULL, 0, ++ "AES-128 ECB encode" ++ }, ++/*201*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), ++ NULL, 0, ++ "AES-128 ECB decode" ++ }, ++/*202*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ NULL, 0, ++ "AES-128 CBC encode" ++ }, ++/*203*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ NULL, 0, ++ "AES-128 CBC decode" ++ }, ++/*204*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), ++ NULL, 0, ++ "AES-192 ECB encode" ++ }, ++/*205*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), ++ NULL, 0, ++ "AES-192 ECB decode" ++ }, ++/*206*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), ++ NULL, 0, ++ "AES-256 ECB encode" ++ }, ++/*207*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), ++ NULL, 0, ++ "AES-256 ECB decode" ++ }, ++/*208*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CTR, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ aesCtrKey, sizeof(aesCtrKey)/sizeof(aesCtrKey[0]), ++ NULL, 0, ++ "AES-128 CTR encode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION md5TestSessions[] = ++{ ++/*300*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ mdKey1, sizeof(mdKey1), ++ "HMAC-MD5 Generate Signature" ++ }, ++/*301*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ mdKey1, sizeof(mdKey1), ++ "HMAC-MD5 Verify Signature" ++ }, ++/*302*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ mdKey2, sizeof(mdKey2), ++ "HMAC-MD5 Generate Signature" ++ }, ++/*303*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ mdKey2, sizeof(mdKey2), ++ "HMAC-MD5 Verify Signature" ++ }, ++/*304*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ mdKey4, sizeof(mdKey4), ++ "HMAC-MD5 Generate Signature" ++ }, ++/*305*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ NULL, 0, ++ "HASH-MD5 Generate Signature" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION shaTestSessions[] = ++{ ++/*400*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ shaKey1, sizeof(shaKey1), ++ "HMAC-SHA1 Generate Signature" ++ }, ++/*401*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ shaKey1, sizeof(shaKey1), ++ "HMAC-SHA1 Verify Signature" ++ }, ++/*402*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ shaKey2, sizeof(shaKey2), ++ "HMAC-SHA1 Generate Signature" ++ }, ++/*403*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ shaKey2, sizeof(shaKey2), ++ "HMAC-SHA1 Verify Signature" ++ }, ++/*404*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ shaKey4, sizeof(shaKey4), ++ "HMAC-SHA1 Generate Signature" ++ }, ++/*405*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ NULL, 0, ++ "HASH-SHA1 Generate Signature" ++ }, ++}; ++ ++static MV_CESA_TEST_SESSION combinedTestSessions[] = ++{ ++/*500*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, MV_CESA_DES_KEY_LENGTH, ++ mdKey4, sizeof(mdKey4), ++ "DES + MD5 encode" ++ }, ++/*501*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, MV_CESA_DES_KEY_LENGTH, ++ shaKey4, sizeof(shaKey4), ++ "DES + SHA1 encode" ++ }, ++/*502*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ mdKey4, sizeof(mdKey4), ++ "3DES + MD5 encode" ++ }, ++/*503*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ shaKey4, sizeof(shaKey4), ++ "3DES + SHA1 encode" ++ }, ++/*504*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ mdKey4, sizeof(mdKey4), ++ "3DES CBC + MD5 encode" ++ }, ++/*505*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ shaKey4, sizeof(shaKey4), ++ "3DES CBC + SHA1 encode" ++ }, ++/*506*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ mdKey4, sizeof(mdKey4), ++ "AES-128 CBC + MD5 encode" ++ }, ++/*507*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ shaKey4, sizeof(shaKey4), ++ "AES-128 CBC + SHA1 encode" ++ }, ++/*508*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_THEN_CRYPTO, ++ MV_CESA_DIR_DECODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ mdKey4, sizeof(mdKey4), ++ "HMAC-MD5 + 3DES decode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_DB_ENTRY cesaTestsDB[MAX_TEST_TYPE+1] = ++{ ++ { desTestSessions, sizeof(desTestSessions)/sizeof(desTestSessions[0]) }, ++ { tripleDesTestSessions, sizeof(tripleDesTestSessions)/sizeof(tripleDesTestSessions[0]) }, ++ { aesTestSessions, sizeof(aesTestSessions)/sizeof(aesTestSessions[0]) }, ++ { md5TestSessions, sizeof(md5TestSessions)/sizeof(md5TestSessions[0]) }, ++ { shaTestSessions, sizeof(shaTestSessions)/sizeof(shaTestSessions[0]) }, ++ { combinedTestSessions, sizeof(combinedTestSessions)/sizeof(combinedTestSessions[0]) }, ++ { NULL, 0 } ++}; ++ ++ ++char cesaNullPlainHexText[] = "000000000000000000000000000000000000000000000000"; ++ ++char cesaPlainAsciiText[] = "Now is the time for all "; ++char cesaPlainHexEbc[] = "4e6f77206973207468652074696d6520666f7220616c6c20"; ++char cesaCipherHexEcb[] = "3fa40e8a984d48156a271787ab8883f9893d51ec4b563b53"; ++char cesaPlainHexCbc[] = "1234567890abcdef4e6f77206973207468652074696d6520666f7220616c6c20"; ++char cesaCipherHexCbc[] = "1234567890abcdefe5c7cdde872bf27c43e934008c389c0f683788499a7c05f6"; ++ ++char cesaAesPlainHexEcb[] = "000102030405060708090a0b0c0d0e0f"; ++char cesaAes128cipherHexEcb[] = "0a940bb5416ef045f1c39458c653ea5a"; ++char cesaAes192cipherHexEcb[] = "0060bffe46834bb8da5cf9a61ff220ae"; ++char cesaAes256cipherHexEcb[] = "5a6e045708fb7196f02e553d02c3a692"; ++ ++char cesaAsciiStr1[] = "Hi There"; ++char cesaDataHexStr1[] = "4869205468657265"; ++char cesaHmacMd5digestHex1[] = "9294727a3638bb1c13f48ef8158bfc9d"; ++char cesaHmacSha1digestHex1[] = "b617318655057264e28bc0b6fb378c8ef146be00"; ++char cesaDataAndMd5digest1[] = "48692054686572659294727a3638bb1c13f48ef8158bfc9d"; ++char cesaDataAndSha1digest1[] = "4869205468657265b617318655057264e28bc0b6fb378c8ef146be00"; ++ ++char cesaAesPlainText[] = "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" ++ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" ++ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" ++ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; ++ ++char cesaAes128CipherCbc[] = "c30e32ffedc0774e6aff6af0869f71aa" ++ "0f3af07a9a31a9c684db207eb0ef8e4e" ++ "35907aa632c3ffdf868bb7b29d3d46ad" ++ "83ce9f9a102ee99d49a53e87f4c3da55"; ++ ++char cesaAesIvPlainText[] = "8ce82eefbea0da3c44699ed7db51b7d9" ++ "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" ++ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" ++ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" ++ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; ++ ++char cesaAes128IvCipherCbc[] = "8ce82eefbea0da3c44699ed7db51b7d9" ++ "c30e32ffedc0774e6aff6af0869f71aa" ++ "0f3af07a9a31a9c684db207eb0ef8e4e" ++ "35907aa632c3ffdf868bb7b29d3d46ad" ++ "83ce9f9a102ee99d49a53e87f4c3da55"; ++ ++char cesaAesCtrPlain[] = "00E0017B27777F3F4A1786F000000001" ++ "000102030405060708090A0B0C0D0E0F" ++ "101112131415161718191A1B1C1D1E1F" ++ "20212223"; ++ ++char cesaAesCtrCipher[] = "00E0017B27777F3F4A1786F000000001" ++ "C1CF48A89F2FFDD9CF4652E9EFDB72D7" ++ "4540A42BDE6D7836D59A5CEAAEF31053" ++ "25B2072F"; ++ ++ ++ ++/* Input cesaHmacHex3 is '0xdd' repeated 50 times */ ++char cesaHmacMd5digestHex3[] = "56be34521d144c88dbb8c733f0e8b3f6"; ++char cesaHmacSha1digestHex3[] = "125d7342b9ac11cd91a39af48aa17b4f63f175d3"; ++char cesaDataHexStr3[50*2+1] = ""; ++char cesaDataAndMd5digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacMd5digestHex3)+8*2+1] = ""; ++char cesaDataAndSha1digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacSha1digestHex3)+8*2+1] = ""; ++ ++/* Ascii string is "abc" */ ++char hashHexStr3[] = "616263"; ++char hashMd5digest3[] = "900150983cd24fb0d6963f7d28e17f72"; ++char hashSha1digest3[] = "a9993e364706816aba3e25717850c26c9cd0d89d"; ++ ++char hashHexStr80[] = "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930"; ++ ++char hashMd5digest80[] = "57edf4a22be3c955ac49da2e2107b67a"; ++ ++char tripleDesThenMd5digest80[] = "b7726a03aad490bd6c5a452a89a1b271"; ++char tripleDesThenSha1digest80[] = "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"; ++ ++char cbc3desThenMd5digest80[] = "6f463057e1a90e0e91ae505b527bcec0"; ++char cbc3desThenSha1digest80[] = "1b002ed050be743aa98860cf35659646bb8efcc0"; ++ ++char cbcAes128ThenMd5digest80[] = "6b6e863ac5a71d15e3e9b1c86c9ba05f"; ++char cbcAes128ThenSha1digest80[] = "13558472d1fc1c90dffec6e5136c7203452d509b"; ++ ++ ++static MV_CESA_TEST_CASE cesaTestCases[] = ++{ ++ /* plainHexStr cipherHexStr IV crypto mac digest */ ++ /* Length Length Offset */ ++ /*0*/ { NULL, NULL, NULL, 0, 0, -1 }, ++ /*1*/ { cesaPlainHexEbc, cesaCipherHexEcb, NULL, 24, 0, -1 }, ++ /*2*/ { cesaPlainHexCbc, cesaCipherHexCbc, NULL, 24, 0, -1 }, ++ /*3*/ { cesaAesPlainHexEcb, cesaAes128cipherHexEcb, NULL, 16, 0, -1 }, ++ /*4*/ { cesaAesPlainHexEcb, cesaAes192cipherHexEcb, NULL, 16, 0, -1 }, ++ /*5*/ { cesaAesPlainHexEcb, cesaAes256cipherHexEcb, NULL, 16, 0, -1 }, ++ /*6*/ { cesaDataHexStr1, cesaHmacMd5digestHex1, NULL, 0, 8, -1 }, ++ /*7*/ { NULL, cesaDataAndMd5digest1, NULL, 0, 8, -1 }, ++ /*8*/ { cesaDataHexStr3, cesaHmacMd5digestHex3, NULL, 0, 50, -1 }, ++ /*9*/ { NULL, cesaDataAndMd5digest3, NULL, 0, 50, -1 }, ++/*10*/ { cesaAesPlainText, cesaAes128IvCipherCbc, iv5, 64, 0, -1 }, ++/*11*/ { cesaDataHexStr1, cesaHmacSha1digestHex1, NULL, 0, 8, -1 }, ++/*12*/ { NULL, cesaDataAndSha1digest1, NULL, 0, 8, -1 }, ++/*13*/ { cesaDataHexStr3, cesaHmacSha1digestHex3, NULL, 0, 50, -1 }, ++/*14*/ { NULL, cesaDataAndSha1digest3, NULL, 0, 50, -1 }, ++/*15*/ { hashHexStr3, hashMd5digest3, NULL, 0, 3, -1 }, ++/*16*/ { hashHexStr3, hashSha1digest3, NULL, 0, 3, -1 }, ++/*17*/ { hashHexStr80, tripleDesThenMd5digest80, NULL, 80, 80, -1 }, ++/*18*/ { hashHexStr80, tripleDesThenSha1digest80, NULL, 80, 80, -1 }, ++/*19*/ { hashHexStr80, cbc3desThenMd5digest80, iv1, 80, 80, -1 }, ++/*20*/ { hashHexStr80, cbc3desThenSha1digest80, iv1, 80, 80, -1 }, ++/*21*/ { hashHexStr80, cbcAes128ThenMd5digest80, iv5, 80, 80, -1 }, ++/*22*/ { hashHexStr80, cbcAes128ThenSha1digest80, iv5, 80, 80, -1 }, ++/*23*/ { cesaAesCtrPlain, cesaAesCtrCipher, NULL, 36, 0, -1 }, ++/*24*/ { cesaAesIvPlainText, cesaAes128IvCipherCbc, NULL, 64, 0, -1 }, ++/*25*/ { plain3des1, cipher3des1, NULL, 0, 0, -1 }, ++/*26*/ { plain3des2, cipher3desCbc2, iv3des2,0, 0, -1 }, ++/*27*/ { plain3des3, cipher3desCbc3, iv3des3,0, 0, -1 }, ++}; ++ ++ ++/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa ++ * Input 0xdd repeated "size" times ++ */ ++static MV_CESA_SIZE_TEST mdMultiSizeTest302[] = ++{ ++ { 80, "7a031a640c14a4872814930b1ef3a5b2" }, ++ { 512, "5488e6c5a14dc72a79f28312ca5b939b" }, ++ { 1000, "d00814f586a8b78a05724239d2531821" }, ++ { 1001, "bf07df7b7f49d3f5b5ecacd4e9e63281" }, ++ { 1002, "1ed4a1a802e87817a819d4e37bb4d0f7" }, ++ { 1003, "5972ab64a4f265ee371dac2f2f137f90" }, ++ { 1004, "71f95e7ec3aa7df2548e90898abdb28e" }, ++ { 1005, "e082790b4857fcfc266e92e59e608814" }, ++ { 1006, "9500f02fd8ac7fde8b10e4fece9a920d" }, ++ { 1336, "e42edcce57d0b75b01aa09d71427948b" }, ++ { 1344, "bb5454ada0deb49ba0a97ffd60f57071" }, ++ { 1399, "0f44d793e744b24d53f44f295082ee8c" }, ++ { 1400, "359de8a03a9b707928c6c60e0e8d79f1" }, ++ { 1401, "e913858b484cbe2b384099ea88d8855b" }, ++ { 1402, "d9848a164af53620e0540c1d7d87629e" }, ++ { 1403, "0c9ee1c2c9ef45e9b625c26cbaf3e822" }, ++ { 1404, "12edd4f609416e3c936170360561b064" }, ++ { 1405, "7fc912718a05446395345009132bf562" }, ++ { 1406, "882f17425e579ff0d85a91a59f308aa0" }, ++ { 1407, "005cae408630a2fb5db82ad9db7e59da" }, ++ { 1408, "64655f8b404b3fea7a3e3e609bc5088f" }, ++ { 1409, "4a145284a7f74e01b6bb1a0ec6a0dd80" }, ++ { 2048, "67caf64475650732def374ebb8bde3fd" }, ++ { 2049, "6c84f11f472825f7e6cd125c2981884b" }, ++ { 2050, "8999586754a73a99efbe4dbad2816d41" }, ++ { 2051, "ba6946b610e098d286bc81091659dfff" }, ++ { 2052, "d0afa01c92d4d13def2b024f36faed83" }, ++ { 3072, "61d8beac61806afa2585d74a9a0e6974" }, ++ { 3074, "f6501a28dcc24d1e4770505c51a87ed3" }, ++ { 3075, "ea4a6929be67e33e61ff475369248b73" }, ++ { 4048, "aa8c4d68f282a07e7385acdfa69f4bed" }, ++ { 4052, "afb5ed2c0e1d430ea59e59ed5ed6b18a" }, ++ { 4058, "9e8553f9bdd43aebe0bd729f0e600c99" }, ++ { 6144, "f628f3e5d183fe5cdd3a5abee39cf872" }, ++ { 6150, "89a3efcea9a2f25f919168ad4a1fd292" }, ++ { 6400, "cdd176b7fb747873efa4da5e32bdf88f" }, ++ { 6528, "b1d707b027354aca152c45ee559ccd3f" }, ++ { 8192, "c600ea4429ac47f9941f09182166e51a" }, ++ {16384, "16e8754bfbeb4c649218422792267a37" }, ++ {18432, "0fd0607521b0aa8b52219cfbe215f63e" }, ++ { 0, NULL }, ++}; ++ ++/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ */ ++static MV_CESA_SIZE_TEST mdMultiSizeTest304[] = ++{ ++ { 80, "a456c4723fee6068530af5a2afa71627" }, ++ { 512, "f85c2a2344f5de68b432208ad13e5794" }, ++ { 1000, "35464d6821fd4a293a41eb84e274c8c5" }, ++ { 1001, "c08eedbdce60cceb54bc2d732bb32c8b" }, ++ { 1002, "5664f71800c011cc311cb6943339c1b8" }, ++ { 1003, "779c723b044c585dc7802b13e8501bdc" }, ++ { 1004, "55e500766a2c307bc5c5fdd15e4cacd4" }, ++ { 1005, "d5f978954f5c38529d1679d2b714f068" }, ++ { 1006, "cd3efc827ce628b7281b72172693abf9" }, ++ { 1336, "6f04479910785878ae6335b8d1e87edf" }, ++ { 1344, "b6d27b50c2bce1ba2a8e1b5cc4324368" }, ++ { 1399, "65f70a1d4c86e5eaeb0704c8a7816795" }, ++ { 1400, "3394b5adc4cb3ff98843ca260a44a88a" }, ++ { 1401, "3a06f3582033a66a4e57e0603ce94e74" }, ++ { 1402, "e4d97f5ed51edc48abfa46eeb5c31752" }, ++ { 1403, "3d05e40b080ee3bedf293cb87b7140e7" }, ++ { 1404, "8cf294fc3cd153ab18dccb2a52cbf244" }, ++ { 1405, "d1487bd42f6edd9b4dab316631159221" }, ++ { 1406, "0527123b6bf6936cf5d369dc18c6c70f" }, ++ { 1407, "3224a06639db70212a0cd1ae1fcc570a" }, ++ { 1408, "a9e13335612c0356f5e2c27086e86c43" }, ++ { 1409, "a86d1f37d1ed8a3552e9a4f04dceea98" }, ++ { 2048, "396905c9b961cd0f6152abfb69c4449c" }, ++ { 2049, "49f39bff85d9dcf059fadb89efc4a70f" }, ++ { 2050, "3a2b4823bc4d0415656550226a63e34a" }, ++ { 2051, "dec60580d406c782540f398ad0bcc7e0" }, ++ { 2052, "32f76610a14310309eb748fe025081bf" }, ++ { 3072, "45edc1a42bf9d708a621076b63b774da" }, ++ { 3074, "9be1b333fe7c0c9f835fb369dc45f778" }, ++ { 3075, "8c06fcac7bd0e7b7a17fd6508c09a549" }, ++ { 4048, "0ddaef848184bf0ad98507a10f1e90e4" }, ++ { 4052, "81976bcaeb274223983996c137875cb8" }, ++ { 4058, "0b0a7a1c82bc7cbc64d8b7cd2dc2bb22" }, ++ { 6144, "1c24056f52725ede2dff0d7f9fc9855f" }, ++ { 6150, "b7f4b65681c4e43ee68ca466ca9ca4ec" }, ++ { 6400, "443bbaab9f7331ddd4bf11b659cd43c8" }, ++ { 6528, "216f44f23047cfee03a7a64f88f9a995" }, ++ { 8192, "ac7a993b2cad54879dba1bde63e39097" }, ++ { 8320, "55ed7be9682d6c0025b3221a62088d08" }, ++ {16384, "c6c722087653b62007aea668277175e5" }, ++ {18432, "f1faca8e907872c809e14ffbd85792d6" }, ++ { 0, NULL }, ++}; ++ ++/* HASH-MD5 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * repeated "size" times ++ */ ++static MV_CESA_SIZE_TEST mdMultiSizeTest305[] = ++{ ++ { 80, "57edf4a22be3c955ac49da2e2107b67a" }, ++ { 512, "c729ae8f0736cc377a9767a660eaa04e" }, ++ { 1000, "f1257a8659eb92d36fe14c6bf3852a6a" }, ++ { 1001, "f8a46fe8ea04fdc8c7de0e84042d3878" }, ++ { 1002, "da188dd67bff87d58aa3c02af2d0cc0f" }, ++ { 1003, "961753017feee04c9b93a8e51658a829" }, ++ { 1004, "dd68c4338608dcc87807a711636bf2af" }, ++ { 1005, "e338d567d3ce66bf69ada29658a8759b" }, ++ { 1006, "443c9811e8b92599b0b149e8d7ec700a" }, ++ { 1336, "89a98511706008ba4cbd0b4a24fa5646" }, ++ { 1344, "335a919805f370b9e402a62c6fe01739" }, ++ { 1399, "5d18d0eddcd84212fe28d812b5e80e3b" }, ++ { 1400, "6b695c240d2dffd0dffc99459ca76db6" }, ++ { 1401, "49590f61298a76719bc93a57a30136f5" }, ++ { 1402, "94c2999fa3ef1910a683d69b2b8476f2" }, ++ { 1403, "37073a02ab00ecba2645c57c228860db" }, ++ { 1404, "1bcd06994fce28b624f0c5fdc2dcdd2b" }, ++ { 1405, "11b93671a64c95079e8cf9e7cddc8b3d" }, ++ { 1406, "4b6695772a4c66313fa4871017d05f36" }, ++ { 1407, "d1539b97fbfda1c075624e958de19c5b" }, ++ { 1408, "b801b9b69920907cd018e8063092ede9" }, ++ { 1409, "b765f1406cfe78e238273ed01bbcaf7e" }, ++ { 2048, "1d7e2c64ac29e2b3fb4c272844ed31f5" }, ++ { 2049, "71d38fac49c6b1f4478d8d88447bcdd0" }, ++ { 2050, "141c34a5592b1bebfa731e0b23d0cdba" }, ++ { 2051, "c5e1853f21c59f5d6039bd13d4b380d8" }, ++ { 2052, "dd44a0d128b63d4b5cccd967906472d7" }, ++ { 3072, "37d158e33b21390822739d13db7b87fe" }, ++ { 3074, "aef3b209d01d39d0597fe03634bbf441" }, ++ { 3075, "335ffb428eabf210bada96d74d5a4012" }, ++ { 4048, "2434c2b43d798d2819487a886261fc64" }, ++ { 4052, "ac2fa84a8a33065b2e92e36432e861f8" }, ++ { 4058, "856781f85616c341c3533d090c1e1e84" }, ++ { 6144, "e5d134c652c18bf19833e115f7a82e9b" }, ++ { 6150, "a09a353be7795fac2401dac5601872e6" }, ++ { 6400, "08b9033ac6a1821398f50af75a2dbc83" }, ++ { 6528, "3d47aa193a8540c091e7e02f779e6751" }, ++ { 8192, "d3164e710c0626f6f395b38f20141cb7" }, ++ { 8320, "b727589d9183ff4e8491dd24466974a3" }, ++ {16384, "3f54d970793d2274d5b20d10a69938ac" }, ++ {18432, "f558511dcf81985b7a1bb57fad970531" }, ++ { 0, NULL }, ++}; ++ ++ ++/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa ++ * 0xaa, 0xaa, 0xaa, 0xaa ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ */ ++static MV_CESA_SIZE_TEST shaMultiSizeTest402[] = ++{ ++ { 80, "e812f370e659705a1649940d1f78cd7af18affd3" }, ++ { 512, "e547f886b2c15d995ed76a8a924cb408c8080f66" }, ++ { 1000, "239443194409f1a5342ecde1a092c8f3a3ed790a" }, ++ { 1001, "f278ab9a102850a9f48dc4e9e6822afe2d0c52b5" }, ++ { 1002, "8bcc667df5ab6ece988b3af361d09747c77f4e72" }, ++ { 1003, "0fae6046c7dc1d3e356b25af836f6077a363f338" }, ++ { 1004, "0ea48401cc92ae6bc92ae76685269cb0167fbe1a" }, ++ { 1005, "ecbcd7c879b295bafcd8766cbeac58cc371e31d1" }, ++ { 1006, "eb4a4a3d07d1e9a15e6f1ab8a9c47f243e27324c" }, ++ { 1336, "f5950ee1d77c10e9011d2149699c9366fe52529c" }, ++ { 1344, "b04263604a63c351b0b3b9cf1785b4bdba6c8838" }, ++ { 1399, "8cb1cff61d5b784045974a2fc69386e3b8d24218" }, ++ { 1400, "9bb2f3fcbeddb2b90f0be797cd647334a2816d51" }, ++ { 1401, "23ae462a7a0cb440f7445791079a5d75a535dd33" }, ++ { 1402, "832974b524a4d3f9cc2f45a3cabf5ccef65cd2aa" }, ++ { 1403, "d1c683742fe404c3c20d5704a5430e7832a7ec95" }, ++ { 1404, "867c79042e64f310628e219d8b85594cd0c7adc3" }, ++ { 1405, "c9d81d49d13d94358f56ccfd61af02b36c69f7c3" }, ++ { 1406, "0df43daab2786172f9b8d07d61f14a070cf1287a" }, ++ { 1407, "0fd8f3ad7f169534b274d4c66bbddd89f759e391" }, ++ { 1408, "3987511182b18473a564436003139b808fa46343" }, ++ { 1409, "ef667e063c9e9f539a8987a8d0bd3066ee85d901" }, ++ { 2048, "921109c99f3fedaca21727156d5f2b4460175327" }, ++ { 2049, "47188600dd165eb45f27c27196d3c46f4f042c1b" }, ++ { 2050, "8831939904009338de10e7fa670847041387807d" }, ++ { 2051, "2f8ebb5db2997d614e767be1050366f3641e7520" }, ++ { 2052, "669e51cd730dae158d3bef8adba075bd95a0d011" }, ++ { 3072, "cfee66cfd83abc8451af3c96c6b35a41cc6c55f5" }, ++ { 3074, "216ea26f02976a261b7d21a4dd3085157bedfabd" }, ++ { 3075, "bd612ebba021fd8e012b14c3bd60c8c5161fabc0" }, ++ { 4048, "c2564c1fdf2d5e9d7dde7aace2643428e90662e8" }, ++ { 4052, "91ce61fe924b445dfe7b5a1dcd10a27caec16df6" }, ++ { 4058, "db2a9be5ee8124f091c7ebd699266c5de223c164" }, ++ { 6144, "855109903feae2ba3a7a05a326b8a171116eb368" }, ++ { 6150, "37520bb3a668294d9c7b073e7e3daf8fee248a78" }, ++ { 6400, "60a353c841b6d2b1a05890349dad2fa33c7536b7" }, ++ { 6528, "9e53a43a69bb42d7c8522ca8bd632e421d5edb36" }, ++ { 8192, "a918cb0da862eaea0a33ee0efea50243e6b4927c" }, ++ { 8320, "29a5dcf55d1db29cd113fcf0572ae414f1c71329" }, ++ {16384, "6fb27966138e0c8d5a0d65ace817ebd53633cee1" }, ++ {18432, "ca09900d891c7c9ae2a559b10f63a217003341c1" }, ++ { 0, NULL }, ++}; ++ ++/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ */ ++static MV_CESA_SIZE_TEST shaMultiSizeTest404[] = ++{ ++ { 80, "beaf20a34b06a87558d156c0949bc3957d40222e" }, ++ { 512, "3353955358d886bc2940a3c7f337ff7dafb59c7b" }, ++ { 1000, "8737a542c5e9b2b6244b757ebb69d5bd602a829f" }, ++ { 1001, "fd9e7582d8a5d3c9fe3b923e4e6a41b07a1eb4d4" }, ++ { 1002, "a146d14a6fc3c274ff600568f4d75b977989e00d" }, ++ { 1003, "be22601bbc027ddef2dec97d30b3dc424fd803c5" }, ++ { 1004, "3e71fe99b2fe2b7bfdf4dbf0c7f3da25d7ea35e7" }, ++ { 1005, "2c422735d7295408fddd76f5e8a83a2a8da13df3" }, ++ { 1006, "6d875319049314b61855101a647b9ba3313428e6" }, ++ { 1336, "c1631ea80bad9dc43a180712461b65a0598c711c" }, ++ { 1344, "816069bf91d34581005746e2e0283d0f9c7b7605" }, ++ { 1399, "4e139866dc61cfcb8b67ca2ebd637b3a538593af" }, ++ { 1400, "ff2a0f8dd2b02c5417910f6f55d33a78e081a723" }, ++ { 1401, "ab00c12be62336964cbce31ae97fe2a0002984d5" }, ++ { 1402, "61349e7f999f3a1acc56c3e9a5060a9c4a7b05b6" }, ++ { 1403, "3edbc0f61e435bc1317fa27d840076093fb79353" }, ++ { 1404, "d052c6dfdbe63d45dab23ef9893e2aa4636aca1e" }, ++ { 1405, "0cc16b7388d67bf0add15a31e6e6c753cfae4987" }, ++ { 1406, "c96ba7eaad74253c38c22101b558d2850b1d1b90" }, ++ { 1407, "3445428a40d2c6556e7c55797ad8d323b61a48d9" }, ++ { 1408, "8d6444f937a09317c89834187b8ea9b8d3a8c56b" }, ++ { 1409, "c700acd3ecd19014ea2bdb4d42510c467e088475" }, ++ { 2048, "ee27d2a0cb77470c2f496212dfd68b5bb7b04e4b" }, ++ { 2049, "683762d7a02983b26a6d046e6451d9cd82c25932" }, ++ { 2050, "0fd20f1d55a9ee18363c2a6fd54aa13aee69992f" }, ++ { 2051, "86c267d8cc4bc8d59090e4f8b303da960fd228b7" }, ++ { 2052, "452395ae05b3ec503eea34f86fc0832485ad97c1" }, ++ { 3072, "75198e3cfd0b9bcff2dabdf8e38e6fdaa33ca49a" }, ++ { 3074, "4e24785ef080141ce4aab4675986d9acea624d7c" }, ++ { 3075, "3a20c5978dd637ec0e809bf84f0d9ccf30bc65bf" }, ++ { 4048, "3c32da256be7a7554922bf5fed51b0d2d09e59ad" }, ++ { 4052, "fff898426ea16e54325ae391a32c6c9bce4c23c0" }, ++ { 4058, "c800b9e562e1c91e1310116341a3c91d37f848ec" }, ++ { 6144, "d91d509d0cc4376c2d05bf9a5097717a373530e6" }, ++ { 6150, "d957030e0f13c5df07d9eec298542d8f94a07f12" }, ++ { 6400, "bb745313c3d7dc17b3f955e5534ad500a1082613" }, ++ { 6528, "77905f80d9ca82080bbb3e5654896dabfcfd1bdb" }, ++ { 8192, "5237fd9a81830c974396f99f32047586612ff3c0" }, ++ { 8320, "57668e28d5f2dba0839518a11db0f6af3d7e08bf" }, ++ {16384, "62e093fde467f0748087beea32e9af97d5c61241" }, ++ {18432, "845fb33130c7d6ea554fd5aacb9c50cf7ccb5929" }, ++ { 0, NULL }, ++}; ++ ++/* HASH-SHA1 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * repeated "size" times ++ */ ++static MV_CESA_SIZE_TEST shaMultiSizeTest405[] = ++{ ++ { 80, "50abf5706a150990a08b2c5ea40fa0e585554732" }, ++ { 512, "f14516a08948fa27917a974d219741a697ba0087" }, ++ { 1000, "0bd18c378d5788817eb4f1e5dc07d867efa5cbf4" }, ++ { 1001, "ca29b85c35db1b8aef83c977893a11159d1b7aa2" }, ++ { 1002, "d83bc973eaaedb8a31437994dabbb3304b0be086" }, ++ { 1003, "2cf7bbef0acd6c00536b5c58ca470df9a3a90b6c" }, ++ { 1004, "e4375d09b1223385a8a393066f8209acfd936a80" }, ++ { 1005, "1029b38043e027745d019ce1d2d68e3d8b9d8f99" }, ++ { 1006, "deea16dcebbd8ac137e2b984deb639b9fb5e9680" }, ++ { 1336, "ea031b065fff63dcfb6a41956e4777520cdbc55d" }, ++ { 1344, "b52096c6445e6c0a8355995c70dc36ae186c863c" }, ++ { 1399, "cde2f6f8379870db4b32cf17471dc828a8dbff2b" }, ++ { 1400, "e53ff664064bc09fe5054c650806bd42d8179518" }, ++ { 1401, "d1156db5ddafcace64cdb510ff0d4af9b9a8ad64" }, ++ { 1402, "34ede0e9a909dd84a2ae291539105c0507b958e1" }, ++ { 1403, "a772ca3536da77e6ad3251e4f9e1234a4d7b87c0" }, ++ { 1404, "29740fd2b04e7a8bfd32242db6233156ad699948" }, ++ { 1405, "65b17397495b70ce4865dad93bf991b74c97cce1" }, ++ { 1406, "a7ee89cd0754061fdb91af7ea6abad2c69d542e3" }, ++ { 1407, "3eebf82f7420188e23d328b7ce93580b279a5715" }, ++ { 1408, "e08d3363a8b9a490dfb3a4c453452b8f114deeec" }, ++ { 1409, "95d74df739181a4ff30b8c39e28793a36598e924" }, ++ { 2048, "aa40262509c2abf84aab0197f83187fc90056d91" }, ++ { 2049, "7dec28ef105bc313bade8d9a7cdeac58b99de5ea" }, ++ { 2050, "d2e30f77ec81197de20f56588a156094ecb88450" }, ++ { 2051, "6b22ccc874833e96551a39da0c0edcaa0d969d92" }, ++ { 2052, "f843141e57875cd669af58744bc60aa9ea59549c" }, ++ { 3072, "09c5fedeaa62c132e673cc3c608a00142273d086" }, ++ { 3074, "b09e95eea9c7b1b007a58accec488301901a7f3d" }, ++ { 3075, "e6226b77b4ada287a8c9bbcf4ed71eec5ce632dc" }, ++ { 4048, "e99394894f855821951ddddf5bfc628547435f5c" }, ++ { 4052, "32d2f1af38be9cfba6cd03d55a254d0b3e1eb382" }, ++ { 4058, "d906552a4f2aca3a22e1fecccbcd183d7289d0ef" }, ++ { 6144, "2e7f62d35a860988e1224dc0543204af19316041" }, ++ { 6150, "d6b89698ee133df46fec9d552fadc328aa5a1b51" }, ++ { 6400, "dff50e90c46853988fa3a4b4ce5dda6945aae976" }, ++ { 6528, "9e63ec0430b96db02d38bc78357a2f63de2ab7f8" }, ++ { 8192, "971eb71ed60394d5ab5abb12e88420bdd41b5992" }, ++ { 8320, "91606a31b46afeaac965cecf87297e791b211013" }, ++ {16384, "547f830a5ec1f5f170ce818f156b1002cabc7569" }, ++ {18432, "f16f272787f3b8d539652e4dc315af6ab4fda0ef" }, ++ { 0, NULL }, ++}; ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST tripleDesMdMultiSizeTest502[] = ++{ ++ { 64, "9586962a2aaaef28803dec2e17807a7f" }, ++ { 80, "b7726a03aad490bd6c5a452a89a1b271" }, ++ { 352, "f1ed9563aecc3c0d2766eb2bed3b4e4c" }, ++ { 512, "0f9decb11ab40fe86f4d4d9397bc020e" }, ++ { 1000, "3ba69deac12cab8ff9dff7dbd9669927" }, ++ { 1336, "6cf47bf1e80e03e2c1d0945bc50d37d2" }, ++ { 1344, "4be388dab21ceb3fa1b8d302e9b821f7" }, ++ { 1400, "a58b79fb21dd9bfc6ec93e3b99fb0ef1" }, ++ { 1408, "8bc97379fc2ac3237effcdd4f7a86528" }, ++ { 2048, "1339f03ab3076f25a20bc4cba16eb5bf" }, ++ { 3072, "731204d2d90c4b36ae41f5e1fb874288" }, ++ { 4048, "c028d998cfda5642547b7e1ed5ea16e4" }, ++ { 6144, "b1b19cd910cc51bd22992f1e59f1e068" }, ++ { 6400, "44e4613496ba622deb0e7cb768135a2f" }, ++ { 6528, "3b06b0a86f8db9cd67f9448dfcf10549" }, ++ { 8192, "d581780b7163138a0f412be681457d82" }, ++ {16384, "03b8ac05527faaf1bed03df149c65ccf" }, ++ {18432, "677c8a86a41dab6c5d81b85b8fb10ff6" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST tripleDesShaMultiSizeTest503[] = ++{ ++ { 64, "44a1e9bcbfc1429630d9ea68b7a48b0427a684f2" }, ++ { 80, "b2ddeaca91030eab5b95a234ef2c0f6e738ff883" }, ++ { 352, "4b91864c7ff629bdff75d9726421f76705452aaf" }, ++ { 512, "6dd37faceeb2aa98ba74f4242ed6734a4d546af5" }, ++ { 1000, "463661c30300be512a9df40904f0757cde5f1141" }, ++ { 1336, "b931f831d9034fe59c65176400b039fe9c1f44a5" }, ++ { 1344, "af8866b1cd4a4887d6185bfe72470ffdfb3648e1" }, ++ { 1400, "49c6caf07296d5e31d2504d088bc5b20c3ee7cdb" }, ++ { 1408, "fcae8deedbc6ebf0763575dc7e9de075b448a0f4" }, ++ { 2048, "edece5012146c1faa0dd10f50b183ba5d2af58ac" }, ++ { 3072, "5b83625adb43a488b8d64fecf39bb766818547b7" }, ++ { 4048, "d2c533678d26c970293af60f14c8279dc708bfc9" }, ++ { 6144, "b8f67af4f991b08b725f969b049ebf813bfacc5c" }, ++ { 6400, "d9a6c7f746ac7a60ef2edbed2841cf851c25cfb0" }, ++ { 6528, "376792b8c8d18161d15579fb7829e6e3a27e9946" }, ++ { 8192, "d890eabdca195b34ef8724b28360cffa92ae5655" }, ++ {16384, "a167ee52639ec7bf19aee9c6e8f76667c14134b9" }, ++ {18432, "e4396ab56f67296b220985a12078f4a0e365d2cc" }, ++ { 0, NULL }, ++}; ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbc3desMdMultiSizeTest504[] = ++{ ++ { 64, "8d10e00802460ede0058c139ba48bd2d" }, ++ { 80, "6f463057e1a90e0e91ae505b527bcec0" }, ++ { 352, "4938d48bdf86aece2c6851e7c6079788" }, ++ { 512, "516705d59f3cf810ebf2a13a23a7d42e" }, ++ { 1000, "a5a000ee5c830e67ddc6a2d2e5644b31" }, ++ { 1336, "44af60087b74ed07950088efbe3b126a" }, ++ { 1344, "1f5b39e0577920af731dabbfcf6dfc2a" }, ++ { 1400, "6804ea640e29b9cd39e08bc37dbce734" }, ++ { 1408, "4fb436624b02516fc9d1535466574bf9" }, ++ { 2048, "c909b0985c423d8d86719f701e9e83db" }, ++ { 3072, "cfe0bc34ef97213ee3d3f8b10122db21" }, ++ { 4048, "03ea10b5ae4ddeb20aed6af373082ed1" }, ++ { 6144, "b9a0ff4f87fc14b3c2dc6f0ed0998fdf" }, ++ { 6400, "6995f85d9d4985dd99e974ec7dda9dd6" }, ++ { 6528, "bbbb548ce2fa3d58467f6a6a5168a0e6" }, ++ { 8192, "afe101fbe745bb449ae4f50d10801456" }, ++ {16384, "9741706d0b1c923340c4660ff97cacdf" }, ++ {18432, "b0217becb73cb8f61fd79c7ce9d023fb" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbc3desShaMultiSizeTest505[] = ++{ ++ { 64, "409187e5bdb0be4a7754ca3747f7433dc4f01b98" }, ++ { 80, "1b002ed050be743aa98860cf35659646bb8efcc0" }, ++ { 352, "6cbf7ebe50fa4fa6eecc19eca23f9eae553ccfff" }, ++ { 512, "cfb5253fb4bf72b743320c30c7e48c54965853b0" }, ++ { 1000, "95e04e1ca2937e7c5a9aba9e42d2bcdb8a7af21f" }, ++ { 1336, "3b5c1f5eee5837ebf67b83ae01405542d77a6627" }, ++ { 1344, "2b3d42ab25615437f98a1ee310b81d07a02badc2" }, ++ { 1400, "7f8687df7c1af44e4baf3c934b6cca5ab6bc993e" }, ++ { 1408, "473a581c5f04f7527d50793c845471ac87e86430" }, ++ { 2048, "e41d20cae7ebe34e6e828ed62b1e5734019037bb" }, ++ { 3072, "275664afd7a561d804e6b0d204e53939cde653ae" }, ++ { 4048, "0d220cc5b34aeeb46bbbd637dde6290b5a8285a3" }, ++ { 6144, "cb393ddcc8b1c206060625b7d822ef9839e67bc5" }, ++ { 6400, "dd3317e2a627fc04800f74a4b05bfda00fab0347" }, ++ { 6528, "8a74c3b2441ab3f5a7e08895cc432566219a7c41" }, ++ { 8192, "b8e6ef3a549ed0e005bd5b8b1a5fe6689e9711a7" }, ++ {16384, "55f59404008276cdac0e2ba0d193af2d40eac5ce" }, ++ {18432, "86ae6c4fc72369a54cce39938e2d0296cd9c6ec5" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to AES block size (16 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbcAes128md5multiSizeTest506[] = ++{ ++ { 16, "7ca4c2ba866751598720c5c4aa0d6786" }, ++ { 64, "7dba7fb988e80da609b1fea7254bced8" }, ++ { 80, "6b6e863ac5a71d15e3e9b1c86c9ba05f" }, ++ { 352, "a1ceb9c2e3021002400d525187a9f38c" }, ++ { 512, "596c055c1c55db748379223164075641" }, ++ { 1008, "f920989c02f3b3603f53c99d89492377" }, ++ { 1344, "2e496b73759d77ed32ea222dbd2e7b41" }, ++ { 1408, "7178c046b3a8d772efdb6a71c4991ea4" }, ++ { 2048, "a917f0099c69eb94079a8421714b6aad" }, ++ { 3072, "693cd5033d7f5391d3c958519fa9e934" }, ++ { 4048, "139dca91bcff65b3c40771749052906b" }, ++ { 6144, "428d9cef6df4fb70a6e9b6bbe4819e55" }, ++ { 6400, "9c0b909e76daa811e12b1fc17000a0c4" }, ++ { 6528, "ad876f6297186a7be1f1b907ed860eda" }, ++ { 8192, "479cbbaca37dd3191ea1f3e8134a0ef4" }, ++ {16384, "60fda559c74f91df538100c9842f2f15" }, ++ {18432, "4a3eb1cba1fa45f3981270953f720c42" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to AES block size (16 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbcAes128sha1multiSizeTest507[] = ++{ ++ { 16, "9aa8dc1c45f0946daf78057fa978759c625c1fee" }, ++ { 64, "9f588fc1ede851e5f8b20256abc9979465ae2189" }, ++ { 80, "13558472d1fc1c90dffec6e5136c7203452d509b" }, ++ { 352, "6b93518e006cfaa1f7adb24615e7291fb0a27e06" }, ++ { 512, "096874951a77fbbf333e49d80c096ee2016e09bd" }, ++ { 1008, "696fc203c2e4b5ae0ec5d1db3f623c490bc6dbac" }, ++ { 1344, "79bf77509935ccd3528caaac6a5eb6481f74029b" }, ++ { 1408, "627f9462b95fc188e8cfa7eec15119bdc5d4fcf1" }, ++ { 2048, "3d50d0c005feba92fe41502d609fced9c882b4d1" }, ++ { 3072, "758807e5b983e3a91c06fb218fe0f73f77111e94" }, ++ { 4048, "ca90e85242e33f005da3504416a52098d0d31fb2" }, ++ { 6144, "8044c1d4fd06642dfc46990b4f18b61ef1e972cf" }, ++ { 6400, "166f1f4ea57409f04feba9fb1e39af0e00bd6f43" }, ++ { 6528, "0389016a39485d6e330f8b4215ddf718b404f7e9" }, ++ { 8192, "6df7ee2a8b61d6f7f860ce8dbf778f0c2a5b508b" }, ++ {16384, "a70a6d8dfa1f91ded621c3dbaed34162bc48783f" }, ++ {18432, "8dfad627922ce15df1eed10bdbed49244efa57db" }, ++ { 0, NULL }, ++}; ++ ++ ++void cesaTestPrintStatus(void); ++ ++ ++/*------------------------- LOCAL FUNCTIONs ---------------------------------*/ ++MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, ++ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize); ++MV_STATUS testClose(int idx); ++MV_STATUS testOpen(int idx); ++void close_session(int sid); ++void cesaTestCheckReady(const MV_CESA_RESULT *r); ++void cesaCheckReady(MV_CESA_RESULT* r); ++void printTestResults(int idx, MV_STATUS status, int checkMode); ++void cesaLastResult(void); ++void cesaTestPrintReq(int req, int offset, int size); ++ ++void cesaTestPrintStatus(void); ++void cesaTestPrintSession(int idx); ++void sizeTest(int testIdx, int iter, int checkMode); ++void multiTest(int iter, int reqSize, int checkMode); ++void oneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); ++void multiSizeTest(int idx, int iter, int checkMode, char* inputData); ++void cesaTest(int iter, int reqSize, int checkMode); ++void cesaOneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); ++void combiTest(int iter, int reqSize, int checkMode); ++void shaTest(int iter, int reqSize, int checkMode); ++void mdTest(int iter, int reqSize, int checkMode); ++void aesTest(int iter, int reqSize, int checkMode); ++void tripleDesTest(int iter, int reqSize, int checkMode); ++void desTest(int iter, int reqSize, int checkMode); ++void cesaTestStop(void); ++MV_STATUS testRun(int idx, int caseIdx, int iter,int reqSize, int checkMode); ++void cesaTestStart(int bufNum, int bufSize); ++ ++ ++static MV_U32 getRate(MV_U32* remainder) ++{ ++ MV_U32 kBits, milliSec, rate; ++ ++ milliSec = 0; ++ if( (cesaEndTicks - cesaBeginTicks) > 0) ++ { ++ milliSec = CESA_TEST_TICK_TO_MS(cesaEndTicks - cesaBeginTicks); ++ } ++ if(milliSec == 0) ++ { ++ if(remainder != NULL) ++ *remainder = 0; ++ return 0; ++ } ++ ++ kBits = (cesaIteration*cesaRateSize*8)/1000; ++ rate = kBits/milliSec; ++ if(remainder != NULL) ++ *remainder = ((kBits % milliSec)*10)/milliSec; ++ ++ return rate; ++} ++ ++static char* extractMbuf(MV_CESA_MBUF *pMbuf, ++ int offset, int size, char* hexStr) ++{ ++ mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, size); ++ mvBinToHex((const MV_U8*)cesaBinBuffer, hexStr, size); ++ ++ return hexStr; ++} ++ ++static MV_BOOL cesaCheckMbuf(MV_CESA_MBUF *pMbuf, ++ const char* hexString, int offset, ++ int checkSize) ++{ ++ MV_BOOL isFailed = MV_FALSE; ++ MV_STATUS status; ++ int size = strlen(hexString)/2; ++ int checkedSize = 0; ++/* ++ mvOsPrintf("cesaCheckMbuf: pMbuf=%p, offset=%d, checkSize=%d, mBufSize=%d\n", ++ pMbuf, offset, checkSize, pMbuf->mbufSize); ++*/ ++ if(pMbuf->mbufSize < (checkSize + offset)) ++ { ++ mvOsPrintf("checkSize (%d) is too large: offset=%d, mbufSize=%d\n", ++ checkSize, offset, pMbuf->mbufSize); ++ return MV_TRUE; ++ } ++ status = mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, checkSize); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaTest: Can't copy %d bytes from Mbuf=%p to checkBuf=%p\n", ++ checkSize, pMbuf, cesaBinBuffer); ++ return MV_TRUE; ++ } ++/* ++ mvDebugMemDump(cesaBinBuffer, size, 1); ++*/ ++ mvHexToBin(hexString, (MV_U8*)cesaExpBinBuffer, size); ++ ++ /* Compare buffers */ ++ while(checkSize > checkedSize) ++ { ++ size = MV_MIN(size, (checkSize - checkedSize)); ++ if(memcmp(cesaExpBinBuffer, &cesaBinBuffer[checkedSize], size) != 0) ++ { ++ mvOsPrintf("CheckMbuf failed: checkSize=%d, size=%d, checkedSize=%d\n", ++ checkSize, size, checkedSize); ++ mvDebugMemDump(&cesaBinBuffer[checkedSize], size, 1); ++ mvDebugMemDump(cesaExpBinBuffer, size, 1); ++ ++ isFailed = MV_TRUE; ++ break; ++ } ++ checkedSize += size; ++ } ++ ++ return isFailed; ++} ++ ++static MV_STATUS cesaSetMbuf(MV_CESA_MBUF *pMbuf, ++ const char* hexString, ++ int offset, int reqSize) ++{ ++ MV_STATUS status = MV_OK; ++ int copySize, size = strlen(hexString)/2; ++ ++ mvHexToBin(hexString, (MV_U8*)cesaBinBuffer, size); ++ ++ copySize = 0; ++ while(reqSize > copySize) ++ { ++ size = MV_MIN(size, (reqSize - copySize)); ++ ++ status = mvCesaCopyToMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset+copySize, size); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("cesaSetMbuf Error: Copy %d of %d bytes to MBuf\n", ++ copySize, reqSize); ++ break; ++ } ++ copySize += size; ++ } ++ pMbuf->mbufSize = offset+copySize; ++ return status; ++} ++ ++static MV_CESA_TEST_SESSION* getTestSessionDb(int idx, int* pTestIdx) ++{ ++ int testIdx, dbIdx = idx/100; ++ ++ if(dbIdx > MAX_TEST_TYPE) ++ { ++ mvOsPrintf("Wrong index %d - No such test type\n", idx); ++ return NULL; ++ } ++ testIdx = idx % 100; ++ ++ if(testIdx >= cesaTestsDB[dbIdx].numSessions) ++ { ++ mvOsPrintf("Wrong index %d - No such test\n", idx); ++ return NULL; ++ } ++ if(pTestIdx != NULL) ++ *pTestIdx = testIdx; ++ ++ return cesaTestsDB[dbIdx].pSessions; ++} ++ ++/* Debug */ ++void cesaTestPrintReq(int req, int offset, int size) ++{ ++ MV_CESA_MBUF* pMbuf; ++ ++ mvOsPrintf("cesaTestPrintReq: req=%d, offset=%d, size=%d\n", ++ req, offset, size); ++ mvDebugMemDump(cesaCmdRing, 128, 4); ++ ++ pMbuf = cesaCmdRing[req].pSrc; ++ mvCesaDebugMbuf("src", pMbuf, offset,size); ++ pMbuf = cesaCmdRing[req].pDst; ++ mvCesaDebugMbuf("dst", pMbuf, offset, size); ++ ++ cesaTestPrintStatus(); ++} ++ ++void cesaLastResult(void) ++{ ++ mvOsPrintf("Last Result: ReqId = %d, SessionId = %d, rc = (%d)\n", ++ (MV_U32)cesaResult.pReqPrv, cesaResult.sessionId, ++ cesaResult.retCode); ++} ++ ++void printTestResults(int idx, MV_STATUS status, int checkMode) ++{ ++ int testIdx; ++ MV_CESA_TEST_SESSION* pTestSessions = getTestSessionDb(idx, &testIdx); ++ ++ if(pTestSessions == NULL) ++ return; ++ ++ mvOsPrintf("%-35s %4dx%-4d : ", pTestSessions[testIdx].name, ++ cesaIteration, cesaReqSize); ++ if( (status == MV_OK) && ++ (cesaCryptoError == 0) && ++ (cesaError == 0) && ++ (cesaReqIdError == 0) ) ++ { ++ mvOsPrintf("Passed, Rate=%3u.%u Mbps (%5u cpp)\n", ++ cesaRate, cesaRateAfterDot, cesaEndTicks - cesaBeginTicks); ++ } ++ else ++ { ++ mvOsPrintf("Failed, Status = 0x%x\n", status); ++ if(cesaCryptoError > 0) ++ mvOsPrintf("cryptoError : %d\n", cesaCryptoError); ++ if(cesaReqIdError > 0) ++ mvOsPrintf("reqIdError : %d\n", cesaReqIdError); ++ if(cesaError > 0) ++ mvOsPrintf("cesaError : %d\n", cesaError); ++ } ++ if(cesaTestIsrMissCount > 0) ++ mvOsPrintf("cesaIsrMissed : %d\n", cesaTestIsrMissCount); ++} ++ ++void cesaCheckReady(MV_CESA_RESULT* r) ++{ ++ int reqId; ++ MV_CESA_MBUF *pMbuf; ++ MV_BOOL isFailed; ++ ++ cesaResult = *r; ++ reqId = (int)cesaResult.pReqPrv; ++ pMbuf = cesaCmdRing[reqId].pDst; ++ ++/* ++ mvOsPrintf("cesaCheckReady: reqId=%d, checkOffset=%d, checkSize=%d\n", ++ reqId, cesaCheckOffset, cesaCheckSize); ++*/ ++ /* Check expected reqId */ ++ if(reqId != cesaExpReqId) ++ { ++ cesaReqIdError++; ++/* ++ mvOsPrintf("CESA reqId Error: cbIter=%d (%d), reqId=%d, expReqId=%d\n", ++ cesaCbIter, cesaIteration, reqId, cesaExpReqId); ++*/ ++ } ++ else ++ { ++ if( (cesaCheckMode == CESA_FULL_CHECK_MODE) || ++ (cesaCheckMode == CESA_FAST_CHECK_MODE) ) ++ { ++ if(cesaResult.retCode != MV_OK) ++ { ++ cesaError++; ++ ++ mvOsPrintf("CESA Error: cbIter=%d (%d), reqId=%d, rc=%d\n", ++ cesaCbIter, cesaIteration, reqId, cesaResult.retCode); ++ } ++ else ++ { ++ if( (cesaCheckSize > 0) && (cesaOutputHexStr != NULL) ) ++ { ++ /* Check expected output */ ++ ++ isFailed = cesaCheckMbuf(pMbuf, cesaOutputHexStr, cesaCheckOffset, cesaCheckSize); ++ if(isFailed) ++ { ++ mvOsPrintf("CESA Crypto Error: cbIter=%d (%d), reqId=%d\n", ++ cesaCbIter, cesaIteration, reqId); ++ ++ CESA_TEST_DEBUG_PRINT(("Error: reqId=%d, reqSize=%d, checkOffset=%d, checkSize=%d\n", ++ reqId, cesaReqSize, cesaCheckOffset, cesaCheckSize)); ++ ++ CESA_TEST_DEBUG_PRINT(("Output str: %s\n", cesaOutputHexStr)); ++ ++ CESA_TEST_DEBUG_CODE( mvCesaDebugMbuf("error", pMbuf, 0, cesaCheckOffset+cesaCheckSize) ); ++ ++ cesaCryptoError++; ++ } ++ } ++ } ++ } ++ } ++ if(cesaCheckMode == CESA_SHOW_CHECK_MODE) ++ { ++ extractMbuf(pMbuf, cesaCheckOffset, cesaCheckSize, cesaHexBuffer); ++ mvOsPrintf("%4d, %s\n", cesaCheckOffset, cesaHexBuffer); ++ } ++ ++ cesaCbIter++; ++ if(cesaCbIter >= cesaIteration) ++ { ++ cesaCbIter = 0; ++ cesaExpReqId = 0; ++ cesaIsReady = MV_TRUE; ++ ++ cesaEndTicks = CESA_TEST_TICK_GET(); ++ cesaRate = getRate(&cesaRateAfterDot); ++ } ++ else ++ { ++ cesaExpReqId = reqId + 1; ++ if(cesaExpReqId == CESA_DEF_REQ_SIZE) ++ cesaExpReqId = 0; ++ } ++} ++ ++ ++#ifdef MV_NETBSD ++static int cesaTestReadyIsr(void *arg) ++#else ++#ifdef __KERNEL__ ++static irqreturn_t cesaTestReadyIsr( int irq , void *dev_id) ++#endif ++#ifdef MV_VXWORKS ++void cesaTestReadyIsr(void) ++#endif ++#endif ++{ ++ MV_U32 cause; ++ MV_STATUS status; ++ MV_CESA_RESULT result; ++ ++ cesaTestIsrCount++; ++ /* Clear cause register */ ++ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) ++ { ++ mvOsPrintf("cesaTestReadyIsr: cause=0x%x\n", cause); ++#ifdef MV_NETBSD ++ return 0; ++#else ++#ifdef __KERNEL__ ++ return 1; ++#else ++ return; ++#endif ++#endif ++ } ++ ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++ ++ while(MV_TRUE) ++ { ++ /* Get Ready requests */ ++ status = mvCesaReadyGet(&result); ++ if(status == MV_OK) ++ cesaCheckReady(&result); ++ ++ break; ++ } ++ if( (cesaTestFull == 1) && (status != MV_BUSY) ) ++ { ++ cesaTestFull = 0; ++ CESA_TEST_WAKE_UP(); ++ } ++ ++#ifdef __KERNEL__ ++ return 1; ++#endif ++} ++ ++void ++cesaTestCheckReady(const MV_CESA_RESULT *r) ++{ ++ MV_CESA_RESULT result = *r; ++ ++ cesaCheckReady(&result); ++ ++ if (cesaTestFull == 1) { ++ cesaTestFull = 0; ++ CESA_TEST_WAKE_UP(); ++ } ++} ++ ++static INLINE int open_session(MV_CESA_OPEN_SESSION* pOs) ++{ ++ MV_U16 sid; ++ MV_STATUS status; ++ ++ status = mvCesaSessionOpen(pOs, (short*)&sid); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaTest: Can't open new session - status = 0x%x\n", ++ status); ++ return -1; ++ } ++ ++ return (int)sid; ++} ++ ++void close_session(int sid) ++{ ++ MV_STATUS status; ++ ++ status = mvCesaSessionClose(sid); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaTest: Can't close session %d - status = 0x%x\n", ++ sid, status); ++ } ++} ++ ++MV_STATUS testOpen(int idx) ++{ ++ MV_CESA_OPEN_SESSION os; ++ int sid, i, testIdx; ++ MV_CESA_TEST_SESSION* pTestSession; ++ MV_U16 digestSize = 0; ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return MV_BAD_PARAM; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ if(pTestSession->sid != -1) ++ { ++ mvOsPrintf("Session for test %d already created: sid=%d\n", ++ idx, pTestSession->sid); ++ return MV_OK; ++ } ++ ++ os.cryptoAlgorithm = pTestSession->cryptoAlgorithm; ++ os.macMode = pTestSession->macAlgorithm; ++ switch(os.macMode) ++ { ++ case MV_CESA_MAC_MD5: ++ case MV_CESA_MAC_HMAC_MD5: ++ digestSize = MV_CESA_MD5_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_SHA1: ++ case MV_CESA_MAC_HMAC_SHA1: ++ digestSize = MV_CESA_SHA1_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_NULL: ++ digestSize = 0; ++ } ++ os.cryptoMode = pTestSession->cryptoMode; ++ os.direction = pTestSession->direction; ++ os.operation = pTestSession->operation; ++ ++ for(i=0; icryptoKeySize; i++) ++ os.cryptoKey[i] = pTestSession->pCryptoKey[i]; ++ ++ os.cryptoKeyLength = pTestSession->cryptoKeySize; ++ ++ for(i=0; imacKeySize; i++) ++ os.macKey[i] = pTestSession->pMacKey[i]; ++ ++ os.macKeyLength = pTestSession->macKeySize; ++ os.digestSize = digestSize; ++ ++ sid = open_session(&os); ++ if(sid == -1) ++ { ++ mvOsPrintf("Can't open session for test %d: rc=0x%x\n", ++ idx, cesaResult.retCode); ++ return cesaResult.retCode; ++ } ++ CESA_TEST_DEBUG_PRINT(("Opened session: sid = %d\n", sid)); ++ pTestSession->sid = sid; ++ return MV_OK; ++} ++ ++MV_STATUS testClose(int idx) ++{ ++ int testIdx; ++ MV_CESA_TEST_SESSION* pTestSession; ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return MV_BAD_PARAM; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ if(pTestSession->sid == -1) ++ { ++ mvOsPrintf("Test session %d is not opened\n", idx); ++ return MV_NO_SUCH; ++ } ++ ++ close_session(pTestSession->sid); ++ pTestSession->sid = -1; ++ ++ return MV_OK; ++} ++ ++MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, ++ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize) ++{ ++ int cmdReqId = 0; ++ int i; ++ MV_STATUS rc = MV_OK; ++ char ivZeroHex[] = "0000"; ++ ++ if(iter == 0) ++ iter = CESA_DEF_ITER_NUM; ++ ++ if(pCmd == NULL) ++ { ++ mvOsPrintf("testCmd failed: pCmd=NULL\n"); ++ return MV_BAD_PARAM; ++ } ++ pCmd->sessionId = sid; ++ ++ cesaCryptoError = 0; ++ cesaReqIdError = 0; ++ cesaError = 0; ++ cesaTestIsrMissCount = 0; ++ cesaIsReady = MV_FALSE; ++ cesaIteration = iter; ++ ++ if(cesaInputHexStr == NULL) ++ cesaInputHexStr = cesaPlainHexEbc; ++ ++ for(i=0; ipSrc = (MV_CESA_MBUF*)(cesaCmdRing[i].pSrc); ++ if(pIV != NULL) ++ { ++ /* If IV from SA - set IV in Source buffer to zeros */ ++ cesaSetMbuf(pCmd->pSrc, ivZeroHex, 0, pCmd->cryptoOffset); ++ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, pCmd->cryptoOffset, ++ (cesaReqSize - pCmd->cryptoOffset)); ++ } ++ else ++ { ++ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, 0, cesaReqSize); ++ } ++ pCmd->pDst = (MV_CESA_MBUF*)(cesaCmdRing[i].pDst); ++ cesaSetMbuf(pCmd->pDst, cesaNullPlainHexText, 0, cesaReqSize); ++ ++ memcpy(&cesaCmdRing[i], pCmd, sizeof(*pCmd)); ++ } ++ ++ if(cesaCheckMode == CESA_SW_SHOW_CHECK_MODE) ++ { ++ MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; ++ ++ if(pTestSession->macAlgorithm == MV_CESA_MAC_MD5) ++ { ++ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); ++ mvOsPrintf("SW HASH_MD5: reqSize=%d, macLength=%d\n", ++ cesaReqSize, pCmd->macLength); ++ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); ++ return MV_OK; ++ } ++ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) ++ { ++ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); ++ mvOsPrintf("SW HASH_SHA1: reqSize=%d, macLength=%d\n", ++ cesaReqSize, pCmd->macLength); ++ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); ++ return MV_OK; ++ } ++ } ++ ++ cesaBeginTicks = CESA_TEST_TICK_GET(); ++ CESA_TEST_DEBUG_CODE( memset(cesaTestTrace, 0, sizeof(cesaTestTrace)); ++ cesaTestTraceIdx = 0; ++ ); ++ ++ if(cesaCheckMode == CESA_SW_NULL_CHECK_MODE) ++ { ++ volatile MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; ++ ++ for(i=0; imacAlgorithm == MV_CESA_MAC_MD5) ++ { ++ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (unsigned char*)pDigest); ++ } ++ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) ++ { ++ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (MV_U8 *)pDigest); ++ } ++ } ++ cesaEndTicks = CESA_TEST_TICK_GET(); ++ cesaRate = getRate(&cesaRateAfterDot); ++ cesaIsReady = MV_TRUE; ++ ++ return MV_OK; ++ } ++ ++ /*cesaTestIsrCount = 0;*/ ++ /*mvCesaDebugStatsClear();*/ ++ ++#ifndef MV_NETBSD ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++#endif ++ ++ for(i=0; ipReqPrv = (void*)cmdReqId; ++ ++ CESA_TEST_LOCK(flags); ++ ++ rc = mvCesaAction(pCmd); ++ if(rc == MV_NO_RESOURCE) ++ cesaTestFull = 1; ++ ++ CESA_TEST_UNLOCK(flags); ++ ++ if(rc == MV_NO_RESOURCE) ++ { ++ CESA_TEST_LOCK(flags); ++ CESA_TEST_WAIT( (cesaTestFull == 0), 100); ++ CESA_TEST_UNLOCK(flags); ++ if(cesaTestFull == 1) ++ { ++ mvOsPrintf("CESA Test timeout: i=%d, iter=%d, cesaTestFull=%d\n", ++ i, iter, cesaTestFull); ++ cesaTestFull = 0; ++ return MV_TIMEOUT; ++ } ++ ++ CESA_TEST_LOCK(flags); ++ ++ rc = mvCesaAction(pCmd); ++ ++ CESA_TEST_UNLOCK(flags); ++ } ++ if( (rc != MV_OK) && (rc != MV_NO_MORE) ) ++ { ++ mvOsPrintf("mvCesaAction failed: rc=%d\n", rc); ++ return rc; ++ } ++ ++ cmdReqId++; ++ if(cmdReqId >= CESA_DEF_REQ_SIZE) ++ cmdReqId = 0; ++ ++#ifdef MV_LINUX ++ /* Reschedule each 16 requests */ ++ if( (i & 0xF) == 0) ++ schedule(); ++#endif ++ } ++ return MV_OK; ++} ++ ++void cesaTestStart(int bufNum, int bufSize) ++{ ++ int i, j, idx; ++ MV_CESA_MBUF *pMbufSrc, *pMbufDst; ++ MV_BUF_INFO *pFragsSrc, *pFragsDst; ++ char *pBuf; ++#ifndef MV_NETBSD ++ int numOfSessions, queueDepth; ++ char *pSram; ++ MV_STATUS status; ++ MV_CPU_DEC_WIN addrDecWin; ++#endif ++ ++ cesaCmdRing = mvOsMalloc(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); ++ if(cesaCmdRing == NULL) ++ { ++ mvOsPrintf("testStart: Can't allocate %ld bytes of memory\n", ++ sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); ++ return; ++ } ++ memset(cesaCmdRing, 0, sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); ++ ++ if(bufNum == 0) ++ bufNum = CESA_DEF_BUF_NUM; ++ ++ if(bufSize == 0) ++ bufSize = CESA_DEF_BUF_SIZE; ++ ++ cesaBufNum = bufNum; ++ cesaBufSize = bufSize; ++ mvOsPrintf("CESA test started: bufNum = %d, bufSize = %d\n", ++ bufNum, bufSize); ++ ++ cesaHexBuffer = mvOsMalloc(2*bufNum*bufSize); ++ if(cesaHexBuffer == NULL) ++ { ++ mvOsPrintf("testStart: Can't malloc %d bytes for cesaHexBuffer.\n", ++ 2*bufNum*bufSize); ++ return; ++ } ++ memset(cesaHexBuffer, 0, (2*bufNum*bufSize)); ++ ++ cesaBinBuffer = mvOsMalloc(bufNum*bufSize); ++ if(cesaBinBuffer == NULL) ++ { ++ mvOsPrintf("testStart: Can't malloc %d bytes for cesaBinBuffer\n", ++ bufNum*bufSize); ++ return; ++ } ++ memset(cesaBinBuffer, 0, (bufNum*bufSize)); ++ ++ cesaExpBinBuffer = mvOsMalloc(bufNum*bufSize); ++ if(cesaExpBinBuffer == NULL) ++ { ++ mvOsPrintf("testStart: Can't malloc %d bytes for cesaExpBinBuffer\n", ++ bufNum*bufSize); ++ return; ++ } ++ memset(cesaExpBinBuffer, 0, (bufNum*bufSize)); ++ ++ CESA_TEST_WAIT_INIT(); ++ ++ pMbufSrc = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ pFragsSrc = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ pMbufDst = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ pFragsDst = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ if( (pMbufSrc == NULL) || (pFragsSrc == NULL) || ++ (pMbufDst == NULL) || (pFragsDst == NULL) ) ++ { ++ mvOsPrintf("testStart: Can't malloc Src and Dst pMbuf and pFrags structures.\n"); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ ++ memset(pMbufSrc, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ memset(pFragsSrc, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ memset(pMbufDst, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ memset(pFragsDst, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ mvOsPrintf("Cesa Test Start: pMbufSrc=%p, pFragsSrc=%p, pMbufDst=%p, pFragsDst=%p\n", ++ pMbufSrc, pFragsSrc, pMbufDst, pFragsDst); ++ ++ idx = 0; ++ for(i=0; ipFrags = &pFragsSrc[idx]; ++ cesaCmdRing[i].pSrc->numFrags = bufNum; ++ cesaCmdRing[i].pSrc->mbufSize = 0; ++ ++ cesaCmdRing[i].pDst = &pMbufDst[i]; ++ cesaCmdRing[i].pDst->pFrags = &pFragsDst[idx]; ++ cesaCmdRing[i].pDst->numFrags = bufNum; ++ cesaCmdRing[i].pDst->mbufSize = 0; ++ ++ for(j=0; jpFrags[j].bufVirtPtr = (MV_U8*)pBuf; ++ cesaCmdRing[i].pSrc->pFrags[j].bufSize = bufSize; ++ pBuf += bufSize; ++ cesaCmdRing[i].pDst->pFrags[j].bufVirtPtr = (MV_U8*)pBuf; ++ cesaCmdRing[i].pDst->pFrags[j].bufSize = bufSize; ++ pBuf += bufSize; ++ } ++ idx += bufNum; ++ } ++ ++#ifndef MV_NETBSD ++ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) ++ pSram = (char*)addrDecWin.addrWin.baseLow; ++ else ++ { ++ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); ++ return; ++ } ++ ++#ifdef MV_CESA_NO_SRAM ++ pSram = mvOsMalloc(4*1024+8); ++ if(pSram == NULL) ++ { ++ mvOsPrintf("CesaTest: can't allocate %d bytes for SRAM simulation\n", ++ 4*1024+8); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ pSram = (MV_U8*)MV_ALIGN_UP((MV_U32)pSram, 8); ++#endif /* MV_CESA_NO_SRAM */ ++ ++ numOfSessions = CESA_DEF_SESSION_NUM; ++ queueDepth = CESA_DEF_REQ_SIZE - MV_CESA_MAX_CHAN; ++ ++ status = mvCesaInit(numOfSessions, queueDepth, pSram, NULL); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("mvCesaInit is Failed: status = 0x%x\n", status); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++#endif /* !MV_NETBSD */ ++ ++ /* Prepare data for tests */ ++ for(i=0; i<50; i++) ++ strcat((char*)cesaDataHexStr3, "dd"); ++ ++ strcpy((char*)cesaDataAndMd5digest3, cesaDataHexStr3); ++ strcpy((char*)cesaDataAndSha1digest3, cesaDataHexStr3); ++ ++ /* Digest must be 8 byte aligned */ ++ for(; i<56; i++) ++ { ++ strcat((char*)cesaDataAndMd5digest3, "00"); ++ strcat((char*)cesaDataAndSha1digest3, "00"); ++ } ++ strcat((char*)cesaDataAndMd5digest3, cesaHmacMd5digestHex3); ++ strcat((char*)cesaDataAndSha1digest3, cesaHmacSha1digestHex3); ++ ++#ifndef MV_NETBSD ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); ++#endif ++ ++#ifdef MV_VXWORKS ++ { ++ MV_STATUS status; ++ ++ status = intConnect((VOIDFUNCPTR *)INT_LVL_CESA, cesaTestReadyIsr, (int)NULL); ++ if (status != OK) ++ { ++ mvOsPrintf("CESA: Can't connect CESA (%d) interrupt, status=0x%x \n", ++ INT_LVL_CESA, status); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ cesaSemId = semMCreate(SEM_Q_PRIORITY | SEM_INVERSION_SAFE | SEM_DELETE_SAFE); ++ if(cesaSemId == NULL) ++ { ++ mvOsPrintf("cesaTestStart: Can't create semaphore\n"); ++ return; ++ } ++ intEnable(INT_LVL_CESA); ++ } ++#endif /* MV_VXWORKS */ ++ ++#if !defined(MV_NETBSD) && defined(__KERNEL__) ++ if( request_irq(CESA_IRQ, cesaTestReadyIsr, (SA_INTERRUPT) , "cesa_test", NULL ) ) ++ { ++ mvOsPrintf( "cannot assign irq\n" ); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ spin_lock_init( &cesaLock ); ++#endif ++} ++ ++MV_STATUS testRun(int idx, int caseIdx, int iter, ++ int reqSize, int checkMode) ++{ ++ int testIdx, count, sid, digestSize; ++ int blockSize; ++ MV_CESA_TEST_SESSION* pTestSession; ++ MV_CESA_COMMAND cmd; ++ MV_STATUS status; ++ ++ memset(&cmd, 0, sizeof(cmd)); ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return MV_BAD_PARAM; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ sid = pTestSession->sid; ++ if(sid == -1) ++ { ++ mvOsPrintf("Test %d is not opened\n", idx); ++ return MV_BAD_STATE; ++ } ++ switch(pTestSession->cryptoAlgorithm) ++ { ++ case MV_CESA_CRYPTO_DES: ++ case MV_CESA_CRYPTO_3DES: ++ blockSize = MV_CESA_DES_BLOCK_SIZE; ++ break; ++ ++ case MV_CESA_CRYPTO_AES: ++ blockSize = MV_CESA_AES_BLOCK_SIZE; ++ break; ++ ++ case MV_CESA_CRYPTO_NULL: ++ blockSize = 0; ++ break; ++ ++ default: ++ mvOsPrintf("cesaTestRun: Bad CryptoAlgorithm=%d\n", ++ pTestSession->cryptoAlgorithm); ++ return MV_BAD_PARAM; ++ } ++ switch(pTestSession->macAlgorithm) ++ { ++ case MV_CESA_MAC_MD5: ++ case MV_CESA_MAC_HMAC_MD5: ++ digestSize = MV_CESA_MD5_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_SHA1: ++ case MV_CESA_MAC_HMAC_SHA1: ++ digestSize = MV_CESA_SHA1_DIGEST_SIZE; ++ break; ++ default: ++ digestSize = 0; ++ } ++ ++ if(iter == 0) ++ iter = CESA_DEF_ITER_NUM; ++ ++ if(pTestSession->direction == MV_CESA_DIR_ENCODE) ++ { ++ cesaOutputHexStr = cesaTestCases[caseIdx].cipherHexStr; ++ cesaInputHexStr = cesaTestCases[caseIdx].plainHexStr; ++ } ++ else ++ { ++ cesaOutputHexStr = cesaTestCases[caseIdx].plainHexStr; ++ cesaInputHexStr = cesaTestCases[caseIdx].cipherHexStr; ++ } ++ ++ cmd.sessionId = sid; ++ if(checkMode == CESA_FAST_CHECK_MODE) ++ { ++ cmd.cryptoLength = cesaTestCases[caseIdx].cryptoLength; ++ cmd.macLength = cesaTestCases[caseIdx].macLength; ++ } ++ else ++ { ++ cmd.cryptoLength = reqSize; ++ cmd.macLength = reqSize; ++ } ++ cesaRateSize = cmd.cryptoLength; ++ cesaReqSize = cmd.cryptoLength; ++ cmd.cryptoOffset = 0; ++ if(pTestSession->operation != MV_CESA_MAC_ONLY) ++ { ++ if( (pTestSession->cryptoMode == MV_CESA_CRYPTO_CBC) || ++ (pTestSession->cryptoMode == MV_CESA_CRYPTO_CTR) ) ++ { ++ cmd.ivOffset = 0; ++ cmd.cryptoOffset = blockSize; ++ if(cesaTestCases[caseIdx].pCryptoIV == NULL) ++ { ++ cmd.ivFromUser = 1; ++ } ++ else ++ { ++ cmd.ivFromUser = 0; ++ mvCesaCryptoIvSet(cesaTestCases[caseIdx].pCryptoIV, blockSize); ++ } ++ cesaReqSize = cmd.cryptoOffset + cmd.cryptoLength; ++ } ++ } ++ ++/* ++ mvOsPrintf("ivFromUser=%d, cryptoLength=%d, cesaReqSize=%d, cryptoOffset=%d\n", ++ cmd.ivFromUser, cmd.cryptoLength, cesaReqSize, cmd.cryptoOffset); ++*/ ++ if(pTestSession->operation != MV_CESA_CRYPTO_ONLY) ++ { ++ cmd.macOffset = cmd.cryptoOffset; ++ ++ if(cesaTestCases[caseIdx].digestOffset == -1) ++ { ++ cmd.digestOffset = cmd.macOffset + cmd.macLength; ++ cmd.digestOffset = MV_ALIGN_UP(cmd.digestOffset, 8); ++ } ++ else ++ { ++ cmd.digestOffset = cesaTestCases[caseIdx].digestOffset; ++ } ++ if( (cmd.digestOffset + digestSize) > cesaReqSize) ++ cesaReqSize = cmd.digestOffset + digestSize; ++ } ++ ++ cesaCheckMode = checkMode; ++ ++ if(checkMode == CESA_NULL_CHECK_MODE) ++ { ++ cesaCheckSize = 0; ++ cesaCheckOffset = 0; ++ } ++ else ++ { ++ if(pTestSession->operation == MV_CESA_CRYPTO_ONLY) ++ { ++ cesaCheckOffset = 0; ++ cesaCheckSize = cmd.cryptoLength; ++ } ++ else ++ { ++ cesaCheckSize = digestSize; ++ cesaCheckOffset = cmd.digestOffset; ++ } ++ } ++/* ++ mvOsPrintf("reqSize=%d, checkSize=%d, checkOffset=%d, checkMode=%d\n", ++ cesaReqSize, cesaCheckSize, cesaCheckOffset, cesaCheckMode); ++ ++ mvOsPrintf("blockSize=%d, ivOffset=%d, ivFromUser=%d, crOffset=%d, crLength=%d\n", ++ blockSize, cmd.ivOffset, cmd.ivFromUser, ++ cmd.cryptoOffset, cmd.cryptoLength); ++ ++ mvOsPrintf("macOffset=%d, digestOffset=%d, macLength=%d\n", ++ cmd.macOffset, cmd.digestOffset, cmd.macLength); ++*/ ++ status = testCmd(sid, iter, &cmd, pTestSession, ++ cesaTestCases[caseIdx].pCryptoIV, blockSize); ++ ++ if(status != MV_OK) ++ return status; ++ ++ /* Wait when all callbacks is received */ ++ count = 0; ++ while(cesaIsReady == MV_FALSE) ++ { ++ mvOsSleep(10); ++ count++; ++ if(count > 100) ++ { ++ mvOsPrintf("testRun: Timeout occured\n"); ++ return MV_TIMEOUT; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++ ++void cesaTestStop(void) ++{ ++ MV_CESA_MBUF *pMbufSrc, *pMbufDst; ++ MV_BUF_INFO *pFragsSrc, *pFragsDst; ++ int i; ++ ++ /* Release all allocated memories */ ++ pMbufSrc = (MV_CESA_MBUF*)(cesaCmdRing[0].pSrc); ++ pFragsSrc = cesaCmdRing[0].pSrc->pFrags; ++ ++ pMbufDst = (MV_CESA_MBUF*)(cesaCmdRing[0].pDst); ++ pFragsDst = cesaCmdRing[0].pDst->pFrags; ++ ++ mvOsFree(pMbufSrc); ++ mvOsFree(pMbufDst); ++ mvOsFree(pFragsSrc); ++ mvOsFree(pFragsDst); ++ ++ for(i=0; i 0) ++ cryptoError++; ++ if(cesaReqIdError > 0) ++ reqIdError++; ++ ++ testClose(idx); ++ } ++ } ++ if(cryptoError > 0) ++ mvOsPrintf("cryptoError : %d\n", cryptoError); ++ if(reqIdError > 0) ++ mvOsPrintf("reqIdError : %d\n", reqIdError); ++ ++ if(openErrors > 0) ++ { ++ mvOsPrintf("Open Errors = %d\n", openErrors); ++ for(i=0; i<100; i++) ++ { ++ if(openErrDisp[i] != 0) ++ mvOsPrintf("Error %d - occurs %d times\n", i, openErrDisp[i]); ++ } ++ } ++} ++ ++ ++void loopback_test(int idx, int iter, int size, char* pPlainData) ++{ ++} ++ ++ ++#if defined(MV_VXWORKS) ++int testMode = 0; ++unsigned __TASKCONV cesaTask(void* args) ++{ ++ int reqSize = cesaReqSize; ++ ++ if(testMode == 0) ++ { ++ cesaOneTest(cesaTestIdx, cesaCaseIdx, cesaIteration, ++ reqSize, cesaCheckMode); ++ } ++ else ++ { ++ if(testMode == 1) ++ { ++ cesaTest(cesaIteration, reqSize, cesaCheckMode); ++ combiTest(cesaIteration, reqSize, cesaCheckMode); ++ } ++ else ++ { ++ multiSizeTest(cesaIdx, cesaIteration, cesaCheckMode, NULL); ++ } ++ } ++ return 0; ++} ++ ++void oneTest(int testIdx, int caseIdx, ++ int iter, int reqSize, int checkMode) ++{ ++ long rc; ++ ++ cesaIteration = iter; ++ cesaReqSize = cesaRateSize = reqSize; ++ cesaCheckMode = checkMode; ++ testMode = 0; ++ cesaTestIdx = testIdx; ++ cesaCaseIdx = caseIdx; ++ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); ++ if (rc != MV_OK) ++ { ++ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); ++ } ++} ++ ++void multiTest(int iter, int reqSize, int checkMode) ++{ ++ long rc; ++ ++ cesaIteration = iter; ++ cesaCheckMode = checkMode; ++ cesaReqSize = reqSize; ++ testMode = 1; ++ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); ++ if (rc != MV_OK) ++ { ++ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); ++ } ++} ++ ++void sizeTest(int testIdx, int iter, int checkMode) ++{ ++ long rc; ++ ++ cesaIteration = iter; ++ cesaCheckMode = checkMode; ++ testMode = 2; ++ cesaIdx = testIdx; ++ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); ++ if (rc != MV_OK) ++ { ++ mvOsPrintf("hMW: Can't create CESA test task, rc = %ld\n", rc); ++ } ++} ++ ++#endif /* MV_VXWORKS */ ++ ++extern void mvCesaDebugSA(short sid, int mode); ++void cesaTestPrintSession(int idx) ++{ ++ int testIdx; ++ MV_CESA_TEST_SESSION* pTestSession; ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ if(pTestSession->sid == -1) ++ { ++ mvOsPrintf("Test session %d is not opened\n", idx); ++ return; ++ } ++ ++ mvCesaDebugSA(pTestSession->sid, 1); ++} ++ ++void cesaTestPrintStatus(void) ++{ ++ mvOsPrintf("\n\t Cesa Test Status\n\n"); ++ ++ mvOsPrintf("isrCount=%d\n", ++ cesaTestIsrCount); ++ ++#ifdef CESA_TEST_DEBUG ++ { ++ int i, j; ++ j = cesaTestTraceIdx; ++ mvOsPrintf("No Type Cause rCause iCause Res Time pReady pProc pEmpty\n"); ++ for(i=0; itable = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY)); ++ if(pLruCache->table == NULL) ++ { ++ mvOsFree(pLruCache); ++ return NULL; ++ } ++ memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY)); ++ pLruCache->tableSize = numOfEntries; ++ ++ for(i=0; itable[i].next = i+1; ++ pLruCache->table[i].prev = i-1; ++ } ++ pLruCache->least = 0; ++ pLruCache->most = numOfEntries-1; ++ ++ return pLruCache; ++} ++ ++void mvLruCacheFinish(MV_LRU_CACHE* pLruCache) ++{ ++ mvOsFree(pLruCache->table); ++ mvOsFree(pLruCache); ++} ++ ++/* Update LRU cache database after using cache Index */ ++void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx) ++{ ++ int prev, next; ++ ++ if(cacheIdx == pLruHndl->most) ++ return; ++ ++ next = pLruHndl->table[cacheIdx].next; ++ if(cacheIdx == pLruHndl->least) ++ { ++ pLruHndl->least = next; ++ } ++ else ++ { ++ prev = pLruHndl->table[cacheIdx].prev; ++ ++ pLruHndl->table[next].prev = prev; ++ pLruHndl->table[prev].next = next; ++ } ++ ++ pLruHndl->table[pLruHndl->most].next = cacheIdx; ++ pLruHndl->table[cacheIdx].prev = pLruHndl->most; ++ pLruHndl->most = cacheIdx; ++} ++ ++/* Delete LRU cache entry */ ++void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx) ++{ ++ int prev, next; ++ ++ if(cacheIdx == pLruHndl->least) ++ return; ++ ++ prev = pLruHndl->table[cacheIdx].prev; ++ if(cacheIdx == pLruHndl->most) ++ { ++ pLruHndl->most = prev; ++ } ++ else ++ { ++ next = pLruHndl->table[cacheIdx].next; ++ ++ pLruHndl->table[next].prev = prev; ++ pLruHndl->table[prev].next = next; ++ } ++ pLruHndl->table[pLruHndl->least].prev = cacheIdx; ++ pLruHndl->table[cacheIdx].next = pLruHndl->least; ++ pLruHndl->least = cacheIdx; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvLru.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvLru.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvLru.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvLru.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,112 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++/******************************************************************************* ++* mvLru.h - Header File for Least Recently Used Cache algorithm ++* ++* DESCRIPTION: ++* This header file contains macros typedefs and function declaration for ++* the Least Recently Used Cache algorithm. ++* ++*******************************************************************************/ ++ ++#ifndef __mvLru_h__ ++#define __mvLru_h__ ++ ++ ++typedef struct ++{ ++ int next; ++ int prev; ++} MV_LRU_ENTRY; ++ ++typedef struct ++{ ++ int least; ++ int most; ++ MV_LRU_ENTRY* table; ++ int tableSize; ++ ++}MV_LRU_CACHE; ++ ++ ++/* Find Cache index for replacement LRU */ ++static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl) ++{ ++ return pLruHndl->least; ++} ++ ++/* Init LRU cache module */ ++MV_LRU_CACHE* mvLruCacheInit(int numOfEntries); ++ ++/* Finish LRU cache module */ ++void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl); ++ ++/* Update LRU cache database after using cache Index */ ++void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx); ++ ++/* Delete LRU cache entry */ ++void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx); ++ ++ ++#endif /* __mvLru_h__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.c linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,349 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvMD5.h" ++ ++static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]); ++ ++#ifdef MV_CPU_LE ++#define mvByteReverse(buf, len) /* Nothing */ ++#else ++static void mvByteReverse(unsigned char *buf, unsigned longs); ++ ++/* ++ * Note: this code is harmless on little-endian machines. ++ */ ++static void mvByteReverse(unsigned char *buf, unsigned longs) ++{ ++ MV_U32 t; ++ ++ do ++ { ++ t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 | ++ ((unsigned) buf[1] << 8 | buf[0]); ++ *(MV_U32 *) buf = t; ++ buf += 4; ++ } while (--longs); ++} ++#endif ++ ++/* ++ * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious ++ * initialization constants. ++ */ ++void mvMD5Init(MV_MD5_CONTEXT *ctx) ++{ ++ ctx->buf[0] = 0x67452301; ++ ctx->buf[1] = 0xefcdab89; ++ ctx->buf[2] = 0x98badcfe; ++ ctx->buf[3] = 0x10325476; ++ ++ ctx->bits[0] = 0; ++ ctx->bits[1] = 0; ++} ++ ++/* ++ * Update context to reflect the concatenation of another buffer full ++ * of bytes. ++ */ ++void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len) ++{ ++ MV_U32 t; ++ ++ /* Update bitcount */ ++ ++ t = ctx->bits[0]; ++ if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t) ++ ctx->bits[1]++; /* Carry from low to high */ ++ ctx->bits[1] += len >> 29; ++ ++ t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */ ++ ++ /* Handle any leading odd-sized chunks */ ++ ++ if (t) ++ { ++ unsigned char *p = (unsigned char *) ctx->in + t; ++ ++ t = 64 - t; ++ if (len < t) ++ { ++ memcpy(p, buf, len); ++ return; ++ } ++ memcpy(p, buf, t); ++ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ buf += t; ++ len -= t; ++ } ++ /* Process data in 64-byte chunks */ ++ ++ while (len >= 64) ++ { ++ memcpy(ctx->in, buf, 64); ++ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ buf += 64; ++ len -= 64; ++ } ++ ++ /* Handle any remaining bytes of data. */ ++ ++ memcpy(ctx->in, buf, len); ++} ++ ++/* ++ * Final wrapup - pad to 64-byte boundary with the bit pattern ++ * 1 0* (64-bit count of bits processed, MSB-first) ++ */ ++void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx) ++{ ++ unsigned count; ++ unsigned char *p; ++ ++ /* Compute number of bytes mod 64 */ ++ count = (ctx->bits[0] >> 3) & 0x3F; ++ ++ /* Set the first char of padding to 0x80. This is safe since there is ++ always at least one byte free */ ++ p = ctx->in + count; ++ *p++ = 0x80; ++ ++ /* Bytes of padding needed to make 64 bytes */ ++ count = 64 - 1 - count; ++ ++ /* Pad out to 56 mod 64 */ ++ if (count < 8) ++ { ++ /* Two lots of padding: Pad the first block to 64 bytes */ ++ memset(p, 0, count); ++ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ ++ /* Now fill the next block with 56 bytes */ ++ memset(ctx->in, 0, 56); ++ } ++ else ++ { ++ /* Pad block to 56 bytes */ ++ memset(p, 0, count - 8); ++ } ++ mvByteReverse(ctx->in, 14); ++ ++ /* Append length in bits and transform */ ++ ((MV_U32 *) ctx->in)[14] = ctx->bits[0]; ++ ((MV_U32 *) ctx->in)[15] = ctx->bits[1]; ++ ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ mvByteReverse((unsigned char *) ctx->buf, 4); ++ memcpy(digest, ctx->buf, MV_MD5_MAC_LEN); ++ memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */ ++} ++ ++/* The four core functions - F1 is optimized somewhat */ ++ ++/* #define F1(x, y, z) (x & y | ~x & z) */ ++#define F1(x, y, z) (z ^ (x & (y ^ z))) ++#define F2(x, y, z) F1(z, x, y) ++#define F3(x, y, z) (x ^ y ^ z) ++#define F4(x, y, z) (y ^ (x | ~z)) ++ ++/* This is the central step in the MD5 algorithm. */ ++#define MD5STEP(f, w, x, y, z, data, s) \ ++ ( w += f(x, y, z) + data, w = w<>(32-s), w += x ) ++ ++/* ++ * The core of the MD5 algorithm, this alters an existing MD5 hash to ++ * reflect the addition of 16 longwords of new data. MD5Update blocks ++ * the data and converts bytes into longwords for this routine. ++ */ ++static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]) ++{ ++ register MV_U32 a, b, c, d; ++ ++ a = buf[0]; ++ b = buf[1]; ++ c = buf[2]; ++ d = buf[3]; ++ ++ MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); ++ MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); ++ MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); ++ MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); ++ MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); ++ MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); ++ MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); ++ MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); ++ MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); ++ MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); ++ MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); ++ MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); ++ MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); ++ MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); ++ MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); ++ MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); ++ ++ MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); ++ MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); ++ MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); ++ MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); ++ MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); ++ MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); ++ MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); ++ MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); ++ MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); ++ MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); ++ MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); ++ MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); ++ MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); ++ MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); ++ MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); ++ MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); ++ ++ MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); ++ MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); ++ MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); ++ MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); ++ MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); ++ MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); ++ MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); ++ MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); ++ MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); ++ MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); ++ MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); ++ MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); ++ MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); ++ MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); ++ MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); ++ MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); ++ ++ MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); ++ MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); ++ MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); ++ MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); ++ MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); ++ MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); ++ MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); ++ MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); ++ MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); ++ MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); ++ MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); ++ MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); ++ MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); ++ MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); ++ MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); ++ MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); ++ ++ buf[0] += a; ++ buf[1] += b; ++ buf[2] += c; ++ buf[3] += d; ++} ++ ++void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest) ++{ ++ MV_MD5_CONTEXT ctx; ++ ++ mvMD5Init(&ctx); ++ mvMD5Update(&ctx, buf, len); ++ mvMD5Final(digest, &ctx); ++} ++ ++ ++void mvHmacMd5(unsigned char const* text, int text_len, ++ unsigned char const* key, int key_len, ++ unsigned char* digest) ++{ ++ int i; ++ MV_MD5_CONTEXT ctx; ++ unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */ ++ unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */ ++ ++ /* start out by storing key in pads */ ++ memset(k_ipad, 0, 64); ++ memcpy(k_ipad, key, key_len); ++ memset(k_opad, 0, 64); ++ memcpy(k_opad, key, key_len); ++ ++ /* XOR key with ipad and opad values */ ++ for (i=0; i<64; i++) ++ { ++ k_ipad[i] ^= 0x36; ++ k_opad[i] ^= 0x5c; ++ } ++ ++ /* perform inner MD5 */ ++ mvMD5Init(&ctx); /* init ctx for 1st pass */ ++ mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */ ++ mvMD5Update(&ctx, text, text_len); /* then text of datagram */ ++ mvMD5Final(digest, &ctx); /* finish up 1st pass */ ++ ++ /* perform outer MD5 */ ++ mvMD5Init(&ctx); /* init ctx for 2nd pass */ ++ mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */ ++ mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */ ++ mvMD5Final(digest, &ctx); /* finish up 2nd pass */ ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,93 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvMD5_h__ ++#define __mvMD5_h__ ++ ++#include "mvMD5.h" ++ ++#define MV_MD5_MAC_LEN 16 ++ ++ ++typedef struct ++{ ++ MV_U32 buf[4]; ++ MV_U32 bits[2]; ++ MV_U8 in[64]; ++ ++} MV_MD5_CONTEXT; ++ ++void mvMD5Init(MV_MD5_CONTEXT *context); ++void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf, ++ unsigned len); ++void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context); ++ ++void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest); ++ ++void mvHmacMd5(unsigned char const* text, int text_len, ++ unsigned char const* key, int key_len, ++ unsigned char* digest); ++ ++ ++#endif /* __mvMD5_h__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,239 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvSHA1.h" ++ ++#define SHA1HANDSOFF ++ ++typedef union ++{ ++ MV_U8 c[64]; ++ MV_U32 l[16]; ++ ++} CHAR64LONG16; ++ ++static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer); ++ ++#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) ++ ++ ++#ifdef MV_CPU_LE ++#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \ ++ (rol(block->l[i], 8) & 0x00FF00FF)) ++#else ++#define blk0(i) block->l[i] ++#endif ++#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \ ++ block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1)) ++ ++/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */ ++#define R0(v,w,x,y,z,i) \ ++ z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \ ++ w = rol(w, 30); ++#define R1(v,w,x,y,z,i) \ ++ z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \ ++ w = rol(w, 30); ++#define R2(v,w,x,y,z,i) \ ++ z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30); ++#define R3(v,w,x,y,z,i) \ ++ z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \ ++ w = rol(w, 30); ++#define R4(v,w,x,y,z,i) \ ++ z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \ ++ w=rol(w, 30); ++ ++/* Hash a single 512-bit block. This is the core of the algorithm. */ ++static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer) ++{ ++ MV_U32 a, b, c, d, e; ++ CHAR64LONG16* block; ++ ++#ifdef SHA1HANDSOFF ++ static MV_U32 workspace[16]; ++ ++ block = (CHAR64LONG16 *) workspace; ++ memcpy(block, buffer, 64); ++#else ++ block = (CHAR64LONG16 *) buffer; ++#endif ++ /* Copy context->state[] to working vars */ ++ a = state[0]; ++ b = state[1]; ++ c = state[2]; ++ d = state[3]; ++ e = state[4]; ++ /* 4 rounds of 20 operations each. Loop unrolled. */ ++ R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); ++ R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); ++ R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); ++ R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); ++ R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); ++ R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); ++ R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); ++ R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); ++ R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); ++ R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); ++ R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); ++ R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); ++ R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); ++ R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); ++ R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); ++ R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); ++ R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); ++ R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); ++ R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); ++ R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); ++ /* Add the working vars back into context.state[] */ ++ state[0] += a; ++ state[1] += b; ++ state[2] += c; ++ state[3] += d; ++ state[4] += e; ++ /* Wipe variables */ ++ a = b = c = d = e = 0; ++} ++ ++void mvSHA1Init(MV_SHA1_CTX* context) ++{ ++ /* SHA1 initialization constants */ ++ context->state[0] = 0x67452301; ++ context->state[1] = 0xEFCDAB89; ++ context->state[2] = 0x98BADCFE; ++ context->state[3] = 0x10325476; ++ context->state[4] = 0xC3D2E1F0; ++ context->count[0] = context->count[1] = 0; ++} ++ ++ ++/* Run your data through this. */ ++void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data, ++ unsigned int len) ++{ ++ MV_U32 i, j; ++ ++ j = (context->count[0] >> 3) & 63; ++ if ((context->count[0] += len << 3) < (len << 3)) ++ context->count[1]++; ++ context->count[1] += (len >> 29); ++ if ((j + len) > 63) ++ { ++ memcpy(&context->buffer[j], data, (i = 64-j)); ++ mvSHA1Transform(context->state, context->buffer); ++ for ( ; i + 63 < len; i += 64) ++ { ++ mvSHA1Transform(context->state, &data[i]); ++ } ++ j = 0; ++ } ++ else ++ { ++ i = 0; ++ } ++ memcpy(&context->buffer[j], &data[i], len - i); ++} ++ ++void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context) ++{ ++ MV_U32 i; ++ MV_U8 finalcount[8]; ++ ++ for (i = 0; i < 8; i++) ++ { ++ finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >> ++ ((3-(i & 3)) * 8) ) & 255); /* Endian independent */ ++ } ++ mvSHA1Update(context, (const unsigned char *) "\200", 1); ++ while ((context->count[0] & 504) != 448) ++ { ++ mvSHA1Update(context, (const unsigned char *) "\0", 1); ++ } ++ mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform() ++ */ ++ for (i = 0; i < 20; i++) ++ { ++ digest[i] = (unsigned char) ++ ((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255); ++ } ++ /* Wipe variables */ ++ i = 0; ++ memset(context->buffer, 0, 64); ++ memset(context->state, 0, 20); ++ memset(context->count, 0, 8); ++ memset(finalcount, 0, 8); ++ ++#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */ ++ mvSHA1Transform(context->state, context->buffer); ++#endif ++} ++ ++ ++void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest) ++{ ++ MV_SHA1_CTX ctx; ++ ++ mvSHA1Init(&ctx); ++ mvSHA1Update(&ctx, buf, len); ++ mvSHA1Final(digest, &ctx); ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,88 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvSHA1_h__ ++#define __mvSHA1_h__ ++ ++#include "mvSHA1.h" ++ ++#define MV_SHA1_MAC_LEN 20 ++ ++ ++typedef struct ++{ ++ MV_U32 state[5]; ++ MV_U32 count[2]; ++ MV_U8 buffer[64]; ++ ++} MV_SHA1_CTX; ++ ++void mvSHA1Init(MV_SHA1_CTX *context); ++void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len); ++void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context); ++ ++void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest); ++ ++ ++#endif /* __mvSHA1_h__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c linux-3.0.4/crypto/ocf/kirkwood/cesa_ocf_drv.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa_ocf_drv.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1297 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ctrlEnv/sys/mvSysCesa.h" ++#include "cesa/mvCesa.h" /* moved here before cryptodev.h due to include dependencies */ ++#include ++#include ++#include ++#include ++#include "mvDebug.h" ++ ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#include "cesa/mvCesaRegs.h" ++#include "cesa/AES/mvAes.h" ++#include "cesa/mvLru.h" ++ ++#undef RT_DEBUG ++#ifdef RT_DEBUG ++static int debug = 1; ++module_param(debug, int, 1); ++MODULE_PARM_DESC(debug, "Enable debug"); ++#undef dprintk ++#define dprintk(a...) if (debug) { printk(a); } else ++#else ++static int debug = 0; ++#undef dprintk ++#define dprintk(a...) ++#endif ++ ++ ++/* TDMA Regs */ ++#define WINDOW_BASE(i) 0xA00 + (i << 3) ++#define WINDOW_CTRL(i) 0xA04 + (i << 3) ++ ++/* interrupt handling */ ++#undef CESA_OCF_POLLING ++#undef CESA_OCF_TASKLET ++ ++#if defined(CESA_OCF_POLLING) && defined(CESA_OCF_TASKLET) ++#error "don't use both tasklet and polling mode" ++#endif ++ ++extern int cesaReqResources; ++/* support for spliting action into 2 actions */ ++#define CESA_OCF_SPLIT ++ ++/* general defines */ ++#define CESA_OCF_MAX_SES 128 ++#define CESA_Q_SIZE 64 ++ ++ ++/* data structures */ ++struct cesa_ocf_data { ++ int cipher_alg; ++ int auth_alg; ++ int encrypt_tn_auth; ++#define auth_tn_decrypt encrypt_tn_auth ++ int ivlen; ++ int digestlen; ++ short sid_encrypt; ++ short sid_decrypt; ++ /* fragment workaround sessions */ ++ short frag_wa_encrypt; ++ short frag_wa_decrypt; ++ short frag_wa_auth; ++}; ++ ++/* CESA device data */ ++struct cesa_dev { ++ void __iomem *sram; ++ void __iomem *reg; ++ struct mv_cesa_platform_data *plat_data; ++ int irq; ++}; ++ ++#define DIGEST_BUF_SIZE 32 ++struct cesa_ocf_process { ++ MV_CESA_COMMAND cesa_cmd; ++ MV_CESA_MBUF cesa_mbuf; ++ MV_BUF_INFO cesa_bufs[MV_CESA_MAX_MBUF_FRAGS]; ++ char digest[DIGEST_BUF_SIZE]; ++ int digest_len; ++ struct cryptop *crp; ++ int need_cb; ++}; ++ ++/* global variables */ ++static int32_t cesa_ocf_id = -1; ++static struct cesa_ocf_data *cesa_ocf_sessions[CESA_OCF_MAX_SES]; ++static spinlock_t cesa_lock; ++static struct cesa_dev cesa_device; ++ ++/* static APIs */ ++static int cesa_ocf_process (device_t, struct cryptop *, int); ++static int cesa_ocf_newsession (device_t, u_int32_t *, struct cryptoini *); ++static int cesa_ocf_freesession (device_t, u_int64_t); ++static void cesa_callback (unsigned long); ++static irqreturn_t cesa_interrupt_handler (int, void *); ++#ifdef CESA_OCF_POLLING ++static void cesa_interrupt_polling(void); ++#endif ++#ifdef CESA_OCF_TASKLET ++static struct tasklet_struct cesa_ocf_tasklet; ++#endif ++ ++static struct timeval tt_start; ++static struct timeval tt_end; ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} mv_cesa_dev; ++ ++static device_method_t mv_cesa_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, cesa_ocf_newsession), ++ DEVMETHOD(cryptodev_freesession,cesa_ocf_freesession), ++ DEVMETHOD(cryptodev_process, cesa_ocf_process), ++ DEVMETHOD(cryptodev_kprocess, NULL), ++}; ++ ++ ++ ++/* Add debug Trace */ ++#undef CESA_OCF_TRACE_DEBUG ++#ifdef CESA_OCF_TRACE_DEBUG ++ ++#define MV_CESA_USE_TIMER_ID 0 ++ ++typedef struct ++{ ++ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ ++ MV_U32 timeStamp; ++ MV_U32 cause; ++ MV_U32 realCause; ++ MV_U32 dmaCause; ++ int resources; ++ MV_CESA_REQ* pReqReady; ++ MV_CESA_REQ* pReqEmpty; ++ MV_CESA_REQ* pReqProcess; ++} MV_CESA_TEST_TRACE; ++ ++#define MV_CESA_TEST_TRACE_SIZE 50 ++ ++static int cesaTestTraceIdx = 0; ++static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; ++ ++static void cesaTestTraceAdd(int type) ++{ ++ cesaTestTrace[cesaTestTraceIdx].type = type; ++ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ //cesaTestTrace[cesaTestTraceIdx].idmaCause = MV_REG_READ(IDMA_CAUSE_REG); ++ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; ++ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; ++ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; ++ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; ++ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); ++ cesaTestTraceIdx++; ++ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) ++ cesaTestTraceIdx = 0; ++} ++ ++#else /* CESA_OCF_TRACE_DEBUG */ ++ ++#define cesaTestTraceAdd(x) ++ ++#endif /* CESA_OCF_TRACE_DEBUG */ ++ ++unsigned int ++get_usec(unsigned int start) ++{ ++ if(start) { ++ do_gettimeofday (&tt_start); ++ return 0; ++ } ++ else { ++ do_gettimeofday (&tt_end); ++ tt_end.tv_sec -= tt_start.tv_sec; ++ tt_end.tv_usec -= tt_start.tv_usec; ++ if (tt_end.tv_usec < 0) { ++ tt_end.tv_usec += 1000 * 1000; ++ tt_end.tv_sec -= 1; ++ } ++ } ++ printk("time taken is %d\n", (unsigned int)(tt_end.tv_usec + tt_end.tv_sec * 1000000)); ++ return (tt_end.tv_usec + tt_end.tv_sec * 1000000); ++} ++ ++#ifdef RT_DEBUG ++/* ++ * check that the crp action match the current session ++ */ ++static int ++ocf_check_action(struct cryptop *crp, struct cesa_ocf_data *cesa_ocf_cur_ses) { ++ int count = 0; ++ int encrypt = 0, decrypt = 0, auth = 0; ++ struct cryptodesc *crd; ++ ++ /* Go through crypto descriptors, processing as we go */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next, count++) { ++ if(count > 2) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ ++ /* Encryption /Decryption */ ++ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { ++ /* check that the action is compatible with session */ ++ if(encrypt || decrypt) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ ++ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ if( (count == 2) && (cesa_ocf_cur_ses->encrypt_tn_auth) ) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ encrypt++; ++ } ++ else { /* decrypt */ ++ if( (count == 2) && !(cesa_ocf_cur_ses->auth_tn_decrypt) ) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ decrypt++; ++ } ++ ++ } ++ /* Authentication */ ++ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { ++ /* check that the action is compatible with session */ ++ if(auth) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ if( (count == 2) && (decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ if( (count == 2) && (encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ auth++; ++ } ++ else { ++ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ } ++ return 0; ++ ++} ++#endif ++ ++/* ++ * Process a request. ++ */ ++static int ++cesa_ocf_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct cesa_ocf_process *cesa_ocf_cmd = NULL; ++ struct cesa_ocf_process *cesa_ocf_cmd_wa = NULL; ++ MV_CESA_COMMAND *cesa_cmd; ++ struct cryptodesc *crd; ++ struct cesa_ocf_data *cesa_ocf_cur_ses; ++ int sid = 0, temp_len = 0, i; ++ int encrypt = 0, decrypt = 0, auth = 0; ++ int status; ++ struct sk_buff *skb = NULL; ++ struct uio *uiop = NULL; ++ unsigned char *ivp; ++ MV_BUF_INFO *p_buf_info; ++ MV_CESA_MBUF *p_mbuf_info; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if( cesaReqResources <= 1 ) { ++ dprintk("%s,%d: ERESTART\n", __FILE__, __LINE__); ++ return ERESTART; ++ } ++ ++#ifdef RT_DEBUG ++ /* Sanity check */ ++ if (crp == NULL) { ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL ) { ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ sid = crp->crp_sid & 0xffffffff; ++ if ((sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL)) { ++ crp->crp_etype = ENOENT; ++ printk("%s,%d: ENOENT session %d \n", __FILE__, __LINE__, sid); ++ return EINVAL; ++ } ++#endif ++ ++ sid = crp->crp_sid & 0xffffffff; ++ crp->crp_etype = 0; ++ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; ++ ++#ifdef RT_DEBUG ++ if(ocf_check_action(crp, cesa_ocf_cur_ses)){ ++ goto p_error; ++ } ++#endif ++ ++ /* malloc a new cesa process */ ++ cesa_ocf_cmd = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); ++ ++ if (cesa_ocf_cmd == NULL) { ++ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ memset(cesa_ocf_cmd, 0, sizeof(struct cesa_ocf_process)); ++ ++ /* init cesa_process */ ++ cesa_ocf_cmd->crp = crp; ++ /* always call callback */ ++ cesa_ocf_cmd->need_cb = 1; ++ ++ /* init cesa_cmd for usage of the HALs */ ++ cesa_cmd = &cesa_ocf_cmd->cesa_cmd; ++ cesa_cmd->pReqPrv = (void *)cesa_ocf_cmd; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_encrypt; /* defualt use encrypt */ ++ ++ /* prepare src buffer */ ++ /* we send the entire buffer to the HAL, even if only part of it should be encrypt/auth. */ ++ /* if not using seesions for both encrypt and auth, then it will be wiser to to copy only */ ++ /* from skip to crd_len. */ ++ p_buf_info = cesa_ocf_cmd->cesa_bufs; ++ p_mbuf_info = &cesa_ocf_cmd->cesa_mbuf; ++ ++ p_buf_info += 2; /* save 2 first buffers for IV and digest - ++ we won't append them to the end since, they ++ might be places in an unaligned addresses. */ ++ ++ p_mbuf_info->pFrags = p_buf_info; ++ temp_len = 0; ++ ++ /* handle SKB */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ ++ dprintk("%s,%d: handle SKB.\n", __FILE__, __LINE__); ++ skb = (struct sk_buff *) crp->crp_buf; ++ ++ if (skb_shinfo(skb)->nr_frags >= (MV_CESA_MAX_MBUF_FRAGS - 1)) { ++ printk("%s,%d: %d nr_frags > MV_CESA_MAX_MBUF_FRAGS", __FILE__, __LINE__, skb_shinfo(skb)->nr_frags); ++ goto p_error; ++ } ++ ++ p_mbuf_info->mbufSize = skb->len; ++ temp_len = skb->len; ++ /* first skb fragment */ ++ p_buf_info->bufSize = skb_headlen(skb); ++ p_buf_info->bufVirtPtr = skb->data; ++ p_buf_info++; ++ ++ /* now handle all other skb fragments */ ++ for ( i = 0; i < skb_shinfo(skb)->nr_frags; i++ ) { ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ p_buf_info->bufSize = frag->size; ++ p_buf_info->bufVirtPtr = page_address(frag->page) + frag->page_offset; ++ p_buf_info++; ++ } ++ p_mbuf_info->numFrags = skb_shinfo(skb)->nr_frags + 1; ++ } ++ /* handle UIO */ ++ else if(crp->crp_flags & CRYPTO_F_IOV) { ++ ++ dprintk("%s,%d: handle UIO.\n", __FILE__, __LINE__); ++ uiop = (struct uio *) crp->crp_buf; ++ ++ if (uiop->uio_iovcnt > (MV_CESA_MAX_MBUF_FRAGS - 1)) { ++ printk("%s,%d: %d uio_iovcnt > MV_CESA_MAX_MBUF_FRAGS \n", __FILE__, __LINE__, uiop->uio_iovcnt); ++ goto p_error; ++ } ++ ++ p_mbuf_info->mbufSize = crp->crp_ilen; ++ p_mbuf_info->numFrags = uiop->uio_iovcnt; ++ for(i = 0; i < uiop->uio_iovcnt; i++) { ++ p_buf_info->bufVirtPtr = uiop->uio_iov[i].iov_base; ++ p_buf_info->bufSize = uiop->uio_iov[i].iov_len; ++ temp_len += p_buf_info->bufSize; ++ dprintk("%s,%d: buf %x-> addr %x, size %x \n" ++ , __FILE__, __LINE__, i, (unsigned int)p_buf_info->bufVirtPtr, p_buf_info->bufSize); ++ p_buf_info++; ++ } ++ ++ } ++ /* handle CONTIG */ ++ else { ++ dprintk("%s,%d: handle CONTIG.\n", __FILE__, __LINE__); ++ p_mbuf_info->numFrags = 1; ++ p_mbuf_info->mbufSize = crp->crp_ilen; ++ p_buf_info->bufVirtPtr = crp->crp_buf; ++ p_buf_info->bufSize = crp->crp_ilen; ++ temp_len = crp->crp_ilen; ++ p_buf_info++; ++ } ++ ++ /* Support up to 64K why? cause! */ ++ if(crp->crp_ilen > 64*1024) { ++ printk("%s,%d: buf too big %x \n", __FILE__, __LINE__, crp->crp_ilen); ++ goto p_error; ++ } ++ ++ if( temp_len != crp->crp_ilen ) { ++ printk("%s,%d: warning size don't match.(%x %x) \n", __FILE__, __LINE__, temp_len, crp->crp_ilen); ++ } ++ ++ cesa_cmd->pSrc = p_mbuf_info; ++ cesa_cmd->pDst = p_mbuf_info; ++ ++ /* restore p_buf_info to point to first available buf */ ++ p_buf_info = cesa_ocf_cmd->cesa_bufs; ++ p_buf_info += 1; ++ ++ ++ /* Go through crypto descriptors, processing as we go */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ ++ /* Encryption /Decryption */ ++ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { ++ ++ dprintk("%s,%d: cipher", __FILE__, __LINE__); ++ ++ cesa_cmd->cryptoOffset = crd->crd_skip; ++ cesa_cmd->cryptoLength = crd->crd_len; ++ ++ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ dprintk(" encrypt \n"); ++ encrypt++; ++ ++ /* handle IV */ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { /* IV from USER */ ++ dprintk("%s,%d: IV from USER (offset %x) \n", __FILE__, __LINE__, crd->crd_inject); ++ cesa_cmd->ivFromUser = 1; ++ ivp = crd->crd_iv; ++ ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ dprintk("%s,%d: copy the IV back to the buffer\n", __FILE__, __LINE__); ++ cesa_cmd->ivOffset = crd->crd_inject; ++ crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, cesa_ocf_cur_ses->ivlen, ivp); ++ } ++ else { ++ dprintk("%s,%d: don't copy the IV back to the buffer \n", __FILE__, __LINE__); ++ p_mbuf_info->numFrags++; ++ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; ++ p_mbuf_info->pFrags = p_buf_info; ++ ++ p_buf_info->bufVirtPtr = ivp; ++ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; ++ p_buf_info--; ++ ++ /* offsets */ ++ cesa_cmd->ivOffset = 0; ++ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; ++ if(auth) { ++ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; ++ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; ++ } ++ } ++ } ++ else { /* random IV */ ++ dprintk("%s,%d: random IV \n", __FILE__, __LINE__); ++ cesa_cmd->ivFromUser = 0; ++ ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ /* in this mode the HAL will always copy the IV */ ++ /* given by the session to the ivOffset */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ cesa_cmd->ivOffset = crd->crd_inject; ++ } ++ else { ++ /* if IV isn't copy, then how will the user know which IV did we use??? */ ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ } ++ } ++ else { /* decrypt */ ++ dprintk(" decrypt \n"); ++ decrypt++; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_decrypt; ++ ++ /* handle IV */ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ dprintk("%s,%d: IV from USER \n", __FILE__, __LINE__); ++ /* append the IV buf to the mbuf */ ++ cesa_cmd->ivFromUser = 1; ++ p_mbuf_info->numFrags++; ++ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; ++ p_mbuf_info->pFrags = p_buf_info; ++ ++ p_buf_info->bufVirtPtr = crd->crd_iv; ++ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; ++ p_buf_info--; ++ ++ /* offsets */ ++ cesa_cmd->ivOffset = 0; ++ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; ++ if(auth) { ++ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; ++ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; ++ } ++ } ++ else { ++ dprintk("%s,%d: IV inside the buffer \n", __FILE__, __LINE__); ++ cesa_cmd->ivFromUser = 0; ++ cesa_cmd->ivOffset = crd->crd_inject; ++ } ++ } ++ ++ } ++ /* Authentication */ ++ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { ++ dprintk("%s,%d: Authentication \n", __FILE__, __LINE__); ++ auth++; ++ cesa_cmd->macOffset = crd->crd_skip; ++ cesa_cmd->macLength = crd->crd_len; ++ ++ /* digest + mac */ ++ cesa_cmd->digestOffset = crd->crd_inject; ++ } ++ else { ++ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ } ++ ++ dprintk("\n"); ++ dprintk("%s,%d: Sending Action: \n", __FILE__, __LINE__); ++ dprintk("%s,%d: IV from user: %d. IV offset %x \n", __FILE__, __LINE__, cesa_cmd->ivFromUser, cesa_cmd->ivOffset); ++ dprintk("%s,%d: crypt offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->cryptoOffset, cesa_cmd->cryptoLength); ++ dprintk("%s,%d: Auth offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->macOffset, cesa_cmd->macLength); ++ dprintk("%s,%d: set digest in offset %x . \n", __FILE__, __LINE__, cesa_cmd->digestOffset); ++ if(debug) { ++ mvCesaDebugMbuf("SRC BUFFER", cesa_cmd->pSrc, 0, cesa_cmd->pSrc->mbufSize); ++ } ++ ++ ++ /* send action to HAL */ ++ spin_lock_irqsave(&cesa_lock, flags); ++ status = mvCesaAction(cesa_cmd); ++ spin_unlock_irqrestore(&cesa_lock, flags); ++ ++ /* action not allowed */ ++ if(status == MV_NOT_ALLOWED) { ++#ifdef CESA_OCF_SPLIT ++ /* if both encrypt and auth try to split */ ++ if(auth && (encrypt || decrypt)) { ++ MV_CESA_COMMAND *cesa_cmd_wa; ++ ++ /* malloc a new cesa process and init it */ ++ cesa_ocf_cmd_wa = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); ++ ++ if (cesa_ocf_cmd_wa == NULL) { ++ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ memcpy(cesa_ocf_cmd_wa, cesa_ocf_cmd, sizeof(struct cesa_ocf_process)); ++ cesa_cmd_wa = &cesa_ocf_cmd_wa->cesa_cmd; ++ cesa_cmd_wa->pReqPrv = (void *)cesa_ocf_cmd_wa; ++ cesa_ocf_cmd_wa->need_cb = 0; ++ ++ /* break requests to two operation, first operation completion won't call callback */ ++ if((decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; ++ } ++ else if((decrypt) && !(cesa_ocf_cur_ses->auth_tn_decrypt)) { ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ } ++ else if((encrypt) && (cesa_ocf_cur_ses->encrypt_tn_auth)) { ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ } ++ else if((encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)){ ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; ++ } ++ else { ++ printk("%s,%d: Unsupporterd fragment wa mode \n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ ++ /* send the 2 actions to the HAL */ ++ spin_lock_irqsave(&cesa_lock, flags); ++ status = mvCesaAction(cesa_cmd_wa); ++ spin_unlock_irqrestore(&cesa_lock, flags); ++ ++ if((status != MV_NO_MORE) && (status != MV_OK)) { ++ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); ++ goto p_error; ++ } ++ spin_lock_irqsave(&cesa_lock, flags); ++ status = mvCesaAction(cesa_cmd); ++ spin_unlock_irqrestore(&cesa_lock, flags); ++ ++ } ++ /* action not allowed and can't split */ ++ else ++#endif ++ { ++ goto p_error; ++ } ++ } ++ ++ /* Hal Q is full, send again. This should never happen */ ++ if(status == MV_NO_RESOURCE) { ++ printk("%s,%d: cesa no more resources \n", __FILE__, __LINE__); ++ if(cesa_ocf_cmd) ++ kfree(cesa_ocf_cmd); ++ if(cesa_ocf_cmd_wa) ++ kfree(cesa_ocf_cmd_wa); ++ return ERESTART; ++ } ++ else if((status != MV_NO_MORE) && (status != MV_OK)) { ++ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); ++ goto p_error; ++ } ++ ++ ++#ifdef CESA_OCF_POLLING ++ cesa_interrupt_polling(); ++#endif ++ cesaTestTraceAdd(5); ++ ++ return 0; ++p_error: ++ crp->crp_etype = EINVAL; ++ if(cesa_ocf_cmd) ++ kfree(cesa_ocf_cmd); ++ if(cesa_ocf_cmd_wa) ++ kfree(cesa_ocf_cmd_wa); ++ return EINVAL; ++} ++ ++/* ++ * cesa callback. ++ */ ++static void ++cesa_callback(unsigned long dummy) ++{ ++ struct cesa_ocf_process *cesa_ocf_cmd = NULL; ++ struct cryptop *crp = NULL; ++ MV_CESA_RESULT result[MV_CESA_MAX_CHAN]; ++ int res_idx = 0,i; ++ MV_STATUS status; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++#ifdef CESA_OCF_TASKLET ++ disable_irq(cesa_device.irq); ++#endif ++ while(MV_TRUE) { ++ ++ /* Get Ready requests */ ++ spin_lock(&cesa_lock); ++ status = mvCesaReadyGet(&result[res_idx]); ++ spin_unlock(&cesa_lock); ++ ++ cesaTestTraceAdd(2); ++ ++ if(status != MV_OK) { ++#ifdef CESA_OCF_POLLING ++ if(status == MV_BUSY) { /* Fragment */ ++ cesa_interrupt_polling(); ++ return; ++ } ++#endif ++ break; ++ } ++ res_idx++; ++ break; ++ } ++ ++ for(i = 0; i < res_idx; i++) { ++ ++ if(!result[i].pReqPrv) { ++ printk("%s,%d: warning private is NULL\n", __FILE__, __LINE__); ++ break; ++ } ++ ++ cesa_ocf_cmd = result[i].pReqPrv; ++ crp = cesa_ocf_cmd->crp; ++ ++ // ignore HMAC error. ++ //if(result->retCode) ++ // crp->crp_etype = EIO; ++ ++#if defined(CESA_OCF_POLLING) ++ if(!cesa_ocf_cmd->need_cb){ ++ cesa_interrupt_polling(); ++ } ++#endif ++ if(cesa_ocf_cmd->need_cb) { ++ if(debug) { ++ mvCesaDebugMbuf("DST BUFFER", cesa_ocf_cmd->cesa_cmd.pDst, 0, cesa_ocf_cmd->cesa_cmd.pDst->mbufSize); ++ } ++ crypto_done(crp); ++ } ++ kfree(cesa_ocf_cmd); ++ } ++#ifdef CESA_OCF_TASKLET ++ enable_irq(cesa_device.irq); ++#endif ++ ++ cesaTestTraceAdd(3); ++ ++ return; ++} ++ ++#ifdef CESA_OCF_POLLING ++static void ++cesa_interrupt_polling(void) ++{ ++ u32 cause; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Read cause register */ ++ do { ++ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ cause &= MV_CESA_CAUSE_ACC_DMA_ALL_MASK; ++ ++ } while (cause == 0); ++ ++ /* clear interrupts */ ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++ ++ cesa_callback(0); ++ ++ return; ++} ++ ++#endif ++ ++/* ++ * cesa Interrupt polling routine. ++ */ ++static irqreturn_t ++cesa_interrupt_handler(int irq, void *arg) ++{ ++ u32 cause; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ cesaTestTraceAdd(0); ++ ++ /* Read cause register */ ++ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ ++ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) ++ { ++ /* Empty interrupt */ ++ dprintk("%s,%d: cesaTestReadyIsr: cause=0x%x\n", __FILE__, __LINE__, cause); ++ return IRQ_HANDLED; ++ } ++ ++ /* clear interrupts */ ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++ ++ cesaTestTraceAdd(1); ++#ifdef CESA_OCF_TASKLET ++ tasklet_hi_schedule(&cesa_ocf_tasklet); ++#else ++ cesa_callback(0); ++#endif ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Open a session. ++ */ ++static int ++/*cesa_ocf_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri)*/ ++cesa_ocf_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ u32 status = 0, i; ++ u32 count = 0, auth = 0, encrypt =0; ++ struct cesa_ocf_data *cesa_ocf_cur_ses; ++ MV_CESA_OPEN_SESSION cesa_session; ++ MV_CESA_OPEN_SESSION *cesa_ses = &cesa_session; ++ ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* leave first empty like in other implementations */ ++ for (i = 1; i < CESA_OCF_MAX_SES; i++) { ++ if (cesa_ocf_sessions[i] == NULL) ++ break; ++ } ++ ++ if(i >= CESA_OCF_MAX_SES) { ++ printk("%s,%d: no more sessions \n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ cesa_ocf_sessions[i] = (struct cesa_ocf_data *) kmalloc(sizeof(struct cesa_ocf_data), GFP_ATOMIC); ++ if (cesa_ocf_sessions[i] == NULL) { ++ cesa_ocf_freesession(NULL, i); ++ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ dprintk("%s,%d: new session %d \n", __FILE__, __LINE__, i); ++ ++ *sid = i; ++ cesa_ocf_cur_ses = cesa_ocf_sessions[i]; ++ memset(cesa_ocf_cur_ses, 0, sizeof(struct cesa_ocf_data)); ++ cesa_ocf_cur_ses->sid_encrypt = -1; ++ cesa_ocf_cur_ses->sid_decrypt = -1; ++ cesa_ocf_cur_ses->frag_wa_encrypt = -1; ++ cesa_ocf_cur_ses->frag_wa_decrypt = -1; ++ cesa_ocf_cur_ses->frag_wa_auth = -1; ++ ++ /* init the session */ ++ memset(cesa_ses, 0, sizeof(MV_CESA_OPEN_SESSION)); ++ count = 1; ++ while (cri) { ++ if(count > 2) { ++ printk("%s,%d: don't support more then 2 operations\n", __FILE__, __LINE__); ++ goto error; ++ } ++ switch (cri->cri_alg) { ++ case CRYPTO_AES_CBC: ++ dprintk("%s,%d: (%d) AES CBC \n", __FILE__, __LINE__, count); ++ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->ivlen = MV_CESA_AES_BLOCK_SIZE; ++ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_AES; ++ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); ++ dprintk("%s,%d: key length %d \n", __FILE__, __LINE__, cri->cri_klen/8); ++ cesa_ses->cryptoKeyLength = cri->cri_klen/8; ++ encrypt += count; ++ break; ++ case CRYPTO_3DES_CBC: ++ dprintk("%s,%d: (%d) 3DES CBC \n", __FILE__, __LINE__, count); ++ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->ivlen = MV_CESA_3DES_BLOCK_SIZE; ++ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_3DES; ++ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->cryptoKeyLength = cri->cri_klen/8; ++ encrypt += count; ++ break; ++ case CRYPTO_DES_CBC: ++ dprintk("%s,%d: (%d) DES CBC \n", __FILE__, __LINE__, count); ++ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->ivlen = MV_CESA_DES_BLOCK_SIZE; ++ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_DES; ++ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->cryptoKeyLength = cri->cri_klen/8; ++ encrypt += count; ++ break; ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ dprintk("%s,%d: (%d) %sMD5 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_MD5)? "H-":" "); ++ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MD5_DIGEST_SIZE : 12; ++ cesa_ses->macMode = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MAC_MD5 : MV_CESA_MAC_HMAC_MD5; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); ++ goto error; ++ } ++ cesa_ses->macKeyLength = cri->cri_klen/8; ++ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; ++ auth += count; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ dprintk("%s,%d: (%d) %sSHA1 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_SHA1)? "H-":" "); ++ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_SHA1_DIGEST_SIZE : 12; ++ cesa_ses->macMode = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_MAC_SHA1 : MV_CESA_MAC_HMAC_SHA1; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); ++ goto error; ++ } ++ cesa_ses->macKeyLength = cri->cri_klen/8; ++ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; ++ auth += count; ++ break; ++ default: ++ printk("%s,%d: unknown algo 0x%x\n", __FILE__, __LINE__, cri->cri_alg); ++ goto error; ++ } ++ cri = cri->cri_next; ++ count++; ++ } ++ ++ if((encrypt > 2) || (auth > 2)) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ /* create new sessions in HAL */ ++ if(encrypt) { ++ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; ++ /* encrypt session */ ++ if(auth == 1) { ++ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; ++ } ++ else if(auth == 2) { ++ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; ++ cesa_ocf_cur_ses->encrypt_tn_auth = 1; ++ } ++ else { ++ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; ++ } ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ /* decrypt session */ ++ if( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) { ++ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; ++ } ++ else if( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC ) { ++ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; ++ } ++ cesa_ses->direction = MV_CESA_DIR_DECODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_decrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ ++ /* preapre one action sessions for case we will need to split an action */ ++#ifdef CESA_OCF_SPLIT ++ if(( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) || ++ ( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC )) { ++ /* open one session for encode and one for decode */ ++ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_encrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ ++ cesa_ses->direction = MV_CESA_DIR_DECODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_decrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ /* open one session for auth */ ++ cesa_ses->operation = MV_CESA_MAC_ONLY; ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_auth); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ } ++#endif ++ } ++ else { /* only auth */ ++ cesa_ses->operation = MV_CESA_MAC_ONLY; ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ } ++ ++ return 0; ++error: ++ cesa_ocf_freesession(NULL, *sid); ++ return EINVAL; ++ ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++cesa_ocf_freesession(device_t dev, u_int64_t tid) ++{ ++ struct cesa_ocf_data *cesa_ocf_cur_ses; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ //unsigned long flags; ++ ++ dprintk("%s() %d \n", __FUNCTION__, sid); ++ if ( (sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL) ) { ++ printk("%s,%d: EINVAL can't free session %d \n", __FILE__, __LINE__, sid); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ /* release session from HAL */ ++ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; ++ if (cesa_ocf_cur_ses->sid_encrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->sid_encrypt); ++ } ++ if (cesa_ocf_cur_ses->sid_decrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->sid_decrypt); ++ } ++ if (cesa_ocf_cur_ses->frag_wa_encrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_encrypt); ++ } ++ if (cesa_ocf_cur_ses->frag_wa_decrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_decrypt); ++ } ++ if (cesa_ocf_cur_ses->frag_wa_auth != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_auth); ++ } ++ ++ kfree(cesa_ocf_cur_ses); ++ cesa_ocf_sessions[sid] = NULL; ++ ++ return 0; ++} ++ ++ ++/* TDMA Window setup */ ++ ++static void __init ++setup_tdma_mbus_windows(struct cesa_dev *dev) ++{ ++ int i; ++ ++ for (i = 0; i < 4; i++) { ++ writel(0, dev->reg + WINDOW_BASE(i)); ++ writel(0, dev->reg + WINDOW_CTRL(i)); ++ } ++ ++ for (i = 0; i < dev->plat_data->dram->num_cs; i++) { ++ struct mbus_dram_window *cs = dev->plat_data->dram->cs + i; ++ writel( ++ ((cs->size - 1) & 0xffff0000) | ++ (cs->mbus_attr << 8) | ++ (dev->plat_data->dram->mbus_dram_target_id << 4) | 1, ++ dev->reg + WINDOW_CTRL(i) ++ ); ++ writel(cs->base, dev->reg + WINDOW_BASE(i)); ++ } ++} ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++static int ++mv_cesa_ocf_init(struct platform_device *pdev) ++{ ++#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X) ++ if (MV_FALSE == mvSocUnitIsMappedToThisCpu(CESA)) ++ { ++ dprintk("CESA is not mapped to this CPU\n"); ++ return -ENODEV; ++ } ++#endif ++ ++ dprintk("%s\n", __FUNCTION__); ++ memset(&mv_cesa_dev, 0, sizeof(mv_cesa_dev)); ++ softc_device_init(&mv_cesa_dev, "MV CESA", 0, mv_cesa_methods); ++ cesa_ocf_id = crypto_get_driverid(softc_get_device(&mv_cesa_dev),CRYPTOCAP_F_HARDWARE); ++ ++ if (cesa_ocf_id < 0) ++ panic("MV CESA crypto device cannot initialize!"); ++ ++ dprintk("%s,%d: cesa ocf device id is %d \n", __FILE__, __LINE__, cesa_ocf_id); ++ ++ /* CESA unit is auto power on off */ ++#if 0 ++ if (MV_FALSE == mvCtrlPwrClckGet(CESA_UNIT_ID,0)) ++ { ++ printk("\nWarning CESA %d is Powered Off\n",0); ++ return EINVAL; ++ } ++#endif ++ ++ memset(&cesa_device, 0, sizeof(struct cesa_dev)); ++ /* Get the IRQ, and crypto memory regions */ ++ { ++ struct resource *res; ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); ++ ++ if (!res) ++ return -ENXIO; ++ ++ cesa_device.sram = ioremap(res->start, res->end - res->start + 1); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); ++ ++ if (!res) { ++ iounmap(cesa_device.sram); ++ return -ENXIO; ++ } ++ cesa_device.reg = ioremap(res->start, res->end - res->start + 1); ++ cesa_device.irq = platform_get_irq(pdev, 0); ++ cesa_device.plat_data = pdev->dev.platform_data; ++ setup_tdma_mbus_windows(&cesa_device); ++ ++ } ++ ++ ++ if( MV_OK != mvCesaInit(CESA_OCF_MAX_SES*5, CESA_Q_SIZE, cesa_device.reg, ++ NULL) ) { ++ printk("%s,%d: mvCesaInit Failed. \n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* clear and unmask Int */ ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++#ifndef CESA_OCF_POLLING ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); ++#endif ++#ifdef CESA_OCF_TASKLET ++ tasklet_init(&cesa_ocf_tasklet, cesa_callback, (unsigned int) 0); ++#endif ++ /* register interrupt */ ++ if( request_irq( cesa_device.irq, cesa_interrupt_handler, ++ (IRQF_DISABLED) , "cesa", &cesa_ocf_id) < 0) { ++ printk("%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, cesa_device.reg); ++ return EINVAL; ++ } ++ ++ ++ memset(cesa_ocf_sessions, 0, sizeof(struct cesa_ocf_data *) * CESA_OCF_MAX_SES); ++ ++#define REGISTER(alg) \ ++ crypto_register(cesa_ocf_id, alg, 0,0) ++ REGISTER(CRYPTO_AES_CBC); ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++ return 0; ++} ++ ++static void ++mv_cesa_ocf_exit(struct platform_device *pdev) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ crypto_unregister_all(cesa_ocf_id); ++ cesa_ocf_id = -1; ++ iounmap(cesa_device.reg); ++ iounmap(cesa_device.sram); ++ free_irq(cesa_device.irq, NULL); ++ ++ /* mask and clear Int */ ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ ++ ++ if( MV_OK != mvCesaFinish() ) { ++ printk("%s,%d: mvCesaFinish Failed. \n", __FILE__, __LINE__); ++ return; ++ } ++} ++ ++ ++void cesa_ocf_debug(void) ++{ ++ ++#ifdef CESA_OCF_TRACE_DEBUG ++ { ++ int i, j; ++ j = cesaTestTraceIdx; ++ mvOsPrintf("No Type rCause iCause Proc Isr Res Time pReady pProc pEmpty\n"); ++ for(i=0; i= _1G) ++ { ++ mvOsOutput("%3dGB ", size / _1G); ++ size %= _1G; ++ if(size) ++ mvOsOutput("+"); ++ } ++ if(size >= _1M ) ++ { ++ mvOsOutput("%3dMB ", size / _1M); ++ size %= _1M; ++ if(size) ++ mvOsOutput("+"); ++ } ++ if(size >= _1K) ++ { ++ mvOsOutput("%3dKB ", size / _1K); ++ size %= _1K; ++ if(size) ++ mvOsOutput("+"); ++ } ++ if(size > 0) ++ { ++ mvOsOutput("%3dB ", size); ++ } ++} ++ ++/******************************************************************************* ++* mvHexToBin - Convert hex to binary ++* ++* DESCRIPTION: ++* This function Convert hex to binary. ++* ++* INPUT: ++* pHexStr - hex buffer pointer. ++* size - Size to convert. ++* ++* OUTPUT: ++* pBin - Binary buffer pointer. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size) ++{ ++ int j, i; ++ char tmp[3]; ++ MV_U8 byte; ++ ++ for(j=0, i=0; j> 1; ++ result++; ++ } ++ return result; ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCommon.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,308 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++ ++#ifndef __INCmvCommonh ++#define __INCmvCommonh ++ ++#include "mvTypes.h" ++ ++/* Swap tool */ ++ ++/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ ++#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ ++ ((X&0xf0) >> 4) | \ ++ ((X&0xf00) << 4) | \ ++ ((X&0xf000) >> 4)) ++ ++/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ ++#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ ++ ((X&0xf0) >> 4) | \ ++ ((X&0xf00) << 4) | \ ++ ((X&0xf000) >> 4) | \ ++ ((X&0xf0000) << 4) | \ ++ ((X&0xf00000) >> 4) | \ ++ ((X&0xf000000) << 4) | \ ++ ((X&0xf0000000) >> 4)) ++ ++/* 16bit byte swap. For example 0x1122 -> 0x2211 */ ++#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) ++ ++/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ ++#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ ++ (((X)&0xff00)<<8) | \ ++ (((X)&0xff0000)>>8) | \ ++ (((X)&0xff000000)>>24)) ++ ++/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ ++#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ ++ (((X)&0xff00ULL)<<40) | \ ++ (((X)&0xff0000ULL)<<24) | \ ++ (((X)&0xff000000ULL)<<8) | \ ++ (((X)&0xff00000000ULL)>>8) | \ ++ (((X)&0xff0000000000ULL)>>24) | \ ++ (((X)&0xff000000000000ULL)>>40) | \ ++ (((X)&0xff00000000000000ULL)>>56))) ++ ++/* Endianess macros. */ ++#if defined(MV_CPU_LE) ++ #define MV_16BIT_LE(X) (X) ++ #define MV_32BIT_LE(X) (X) ++ #define MV_64BIT_LE(X) (X) ++ #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) ++ #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) ++ #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) ++#elif defined(MV_CPU_BE) ++ #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) ++ #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) ++ #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) ++ #define MV_16BIT_BE(X) (X) ++ #define MV_32BIT_BE(X) (X) ++ #define MV_64BIT_BE(X) (X) ++#else ++ #error "CPU endianess isn't defined!\n" ++#endif ++ ++ ++/* Bit field definitions */ ++#define NO_BIT 0x00000000 ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++ ++/* Handy sizes */ ++#define _1K 0x00000400 ++#define _2K 0x00000800 ++#define _4K 0x00001000 ++#define _8K 0x00002000 ++#define _16K 0x00004000 ++#define _32K 0x00008000 ++#define _64K 0x00010000 ++#define _128K 0x00020000 ++#define _256K 0x00040000 ++#define _512K 0x00080000 ++ ++#define _1M 0x00100000 ++#define _2M 0x00200000 ++#define _4M 0x00400000 ++#define _8M 0x00800000 ++#define _16M 0x01000000 ++#define _32M 0x02000000 ++#define _64M 0x04000000 ++#define _128M 0x08000000 ++#define _256M 0x10000000 ++#define _512M 0x20000000 ++ ++#define _1G 0x40000000 ++#define _2G 0x80000000 ++ ++/* Tclock and Sys clock define */ ++#define _100MHz 100000000 ++#define _125MHz 125000000 ++#define _133MHz 133333334 ++#define _150MHz 150000000 ++#define _160MHz 160000000 ++#define _166MHz 166666667 ++#define _175MHz 175000000 ++#define _178MHz 178000000 ++#define _183MHz 183333334 ++#define _187MHz 187000000 ++#define _192MHz 192000000 ++#define _194MHz 194000000 ++#define _200MHz 200000000 ++#define _233MHz 233333334 ++#define _250MHz 250000000 ++#define _266MHz 266666667 ++#define _300MHz 300000000 ++ ++/* For better address window table readability */ ++#define EN MV_TRUE ++#define DIS MV_FALSE ++#define N_A -1 /* Not applicable */ ++ ++/* Cache configuration options for memory (DRAM, SRAM, ... ) */ ++ ++/* Memory uncached, HW or SW cache coherency is not needed */ ++#define MV_UNCACHED 0 ++/* Memory cached, HW cache coherency supported in WriteThrough mode */ ++#define MV_CACHE_COHER_HW_WT 1 ++/* Memory cached, HW cache coherency supported in WriteBack mode */ ++#define MV_CACHE_COHER_HW_WB 2 ++/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ ++#define MV_CACHE_COHER_SW 3 ++ ++ ++/* Macro for testing aligment. Positive if number is NOT aligned */ ++#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) ++ ++/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ ++#define MV_ALIGN_UP(number, align) \ ++(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) ++ ++/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ ++#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) ++ ++/* This macro returns absolute value */ ++#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) ++ ++ ++/* Bit fields manipulation macros */ ++ ++/* An integer word which its 'x' bit is set */ ++#define MV_BIT_MASK(bitNum) (1 << (bitNum) ) ++ ++/* Checks wheter bit 'x' in integer word is set */ ++#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) ) ++ ++/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ ++#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) ) ++ ++/* Set bit 'x' in integer word (RMW) */ ++#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) ) ++ ++/* Invert bit 'x' in integer word (RMW) */ ++#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) ) ++ ++/* Get the min between 'a' or 'b' */ ++#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b)) ++ ++/* Get the max between 'a' or 'b' */ ++#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a)) ++ ++/* Temporary */ ++#define mvOsDivide(num, div) \ ++({ \ ++ int i=0, rem=(num); \ ++ \ ++ while(rem >= (div)) \ ++ { \ ++ rem -= (div); \ ++ i++; \ ++ } \ ++ (i); \ ++}) ++ ++/* Temporary */ ++#define mvOsReminder(num, div) \ ++({ \ ++ int rem = (num); \ ++ \ ++ while(rem >= (div)) \ ++ rem -= (div); \ ++ (rem); \ ++}) ++ ++#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ ++ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) ++ ++#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) ++ ++#ifndef MV_ASMLANGUAGE ++/* mvCommon API list */ ++ ++MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size); ++void mvAsciiToHex(const char* asciiStr, char* hexStr); ++void mvBinToHex(const MV_U8* bin, char* hexStr, int size); ++void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size); ++ ++MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex); ++MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr); ++void mvSizePrint(MV_U32); ++ ++MV_U32 mvLog2(MV_U32 num); ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#endif /* __INCmvCommonh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.4 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,326 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++ ++/* includes */ ++#include "mvOs.h" ++#include "mv802_3.h" ++#include "mvCommon.h" ++#include "mvDebug.h" ++ ++/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros ++ * mvDebug - map of bits (one for each module) bit=1 means enable ++ * debug code and messages for this module ++ * mvModuleDebug - array of 32 bits varables one for each module ++ */ ++MV_U32 mvDebug = 0; ++MV_U32 mvDebugModules[MV_MODULE_MAX]; ++ ++/* Init mvModuleDebug array to default values */ ++void mvDebugInit(void) ++{ ++ int bit; ++ ++ mvDebug = 0; ++ for(bit=0; bit 0) ++ { ++ mvOsPrintf("%08x: ", memAddr); ++ i = 0; ++ /* 32 bytes in the line */ ++ while(i < 32) ++ { ++ if(memAddr >= (MV_U32)addr) ++ { ++ switch(access) ++ { ++ case 1: ++ if( memAddr == CPU_PHY_MEM(memAddr) ) ++ { ++ mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); ++ } ++ else ++ { ++ mvOsPrintf("%02x ", *((MV_U8*)memAddr)); ++ } ++ break; ++ ++ case 2: ++ if( memAddr == CPU_PHY_MEM(memAddr) ) ++ { ++ mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); ++ } ++ else ++ { ++ mvOsPrintf("%04x ", *((MV_U16*)memAddr)); ++ } ++ break; ++ ++ case 4: ++ if( memAddr == CPU_PHY_MEM(memAddr) ) ++ { ++ mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); ++ } ++ else ++ { ++ mvOsPrintf("%08x ", *((MV_U32*)memAddr)); ++ } ++ break; ++ } ++ } ++ else ++ { ++ for(j=0; j<(access*2+1); j++) ++ mvOsPrintf(" "); ++ } ++ i += access; ++ memAddr += access; ++ size -= access; ++ if(size <= 0) ++ break; ++ } ++ mvOsPrintf("\n"); ++ } ++} ++ ++void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access) ++{ ++ if(pBufInfo == NULL) ++ { ++ mvOsPrintf("\n!!! pBufInfo = NULL\n"); ++ return; ++ } ++ mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", ++ (unsigned int)pBufInfo, ++ (unsigned int)pBufInfo->cmdSts, ++ (unsigned int)pBufInfo->pBuff, ++ (unsigned int)pBufInfo->bufSize); ++ mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", ++ (unsigned int)pBufInfo->pData, ++ (unsigned int)pBufInfo->byteCnt, ++ (unsigned int)pBufInfo->pNextBufInfo, ++ (unsigned int)pBufInfo->userInfo1, ++ (unsigned int)pBufInfo->userInfo2); ++ if(pBufInfo->pData != NULL) ++ { ++ if(size > pBufInfo->byteCnt) ++ size = pBufInfo->byteCnt; ++ mvDebugMemDump(pBufInfo->pData, size, access); ++ } ++} ++ ++void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access) ++{ ++ int frag, len; ++ ++ if(pPktInfo == NULL) ++ { ++ mvOsPrintf("\n!!! pPktInfo = NULL\n"); ++ return; ++ } ++ mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", ++ pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, ++ pPktInfo->pFrags, pPktInfo->osInfo); ++ ++ for(frag=0; fragnumFrags; frag++) ++ { ++ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", ++ frag, pPktInfo->pFrags[frag].bufVirtPtr, ++ pPktInfo->pFrags[frag].bufSize); ++ if(size > 0) ++ { ++ len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); ++ mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); ++ size -= len; ++ } ++ } ++ ++} ++ ++void mvDebugPrintIpAddr(MV_U32 ipAddr) ++{ ++ mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), ++ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); ++} ++ ++void mvDebugPrintMacAddr(const MV_U8* pMacAddr) ++{ ++ int i; ++ ++ mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); ++ for(i=1; ibegin = 0; ++ pTimeEntry->count = count; ++ pTimeEntry->end = 0; ++ pTimeEntry->left = pTimeEntry->count; ++ pTimeEntry->total = 0; ++ pTimeEntry->min = 0xFFFFFFFF; ++ pTimeEntry->max = 0x0; ++ strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1); ++ pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0'; ++} ++ ++/* Print out MV_DEBUG_TIMES entry */ ++void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle) ++{ ++ int num; ++ ++ if(isTitle == MV_TRUE) ++ mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); ++ ++ num = pTimeEntry->count-pTimeEntry->left; ++ if(num > 0) ++ { ++ mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", ++ pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num, ++ pTimeEntry->min, pTimeEntry->max); ++ } ++} ++ ++/* Update MV_DEBUG_TIMES entry */ ++void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry) ++{ ++ MV_U32 delta; ++ ++ if(pTimeEntry->left > 0) ++ { ++ if(pTimeEntry->end <= pTimeEntry->begin) ++ { ++ delta = pTimeEntry->begin - pTimeEntry->end; ++ } ++ else ++ { ++ delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin; ++ } ++ pTimeEntry->total += delta; ++ ++ if(delta < pTimeEntry->min) ++ pTimeEntry->min = delta; ++ ++ if(delta > pTimeEntry->max) ++ pTimeEntry->max = delta; ++ ++ pTimeEntry->left--; ++ } ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,178 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++ ++#ifndef __INCmvDebugh ++#define __INCmvDebugh ++ ++/* includes */ ++#include "mvTypes.h" ++ ++typedef enum ++{ ++ MV_MODULE_INVALID = -1, ++ MV_MODULE_ETH = 0, ++ MV_MODULE_IDMA, ++ MV_MODULE_XOR, ++ MV_MODULE_TWASI, ++ MV_MODULE_MGI, ++ MV_MODULE_USB, ++ MV_MODULE_CESA, ++ ++ MV_MODULE_MAX ++}MV_MODULE_ID; ++ ++/* Define generic flags useful for most of modules */ ++#define MV_DEBUG_FLAG_ALL (0) ++#define MV_DEBUG_FLAG_INIT (1 << 0) ++#define MV_DEBUG_FLAG_RX (1 << 1) ++#define MV_DEBUG_FLAG_TX (1 << 2) ++#define MV_DEBUG_FLAG_ERR (1 << 3) ++#define MV_DEBUG_FLAG_TRACE (1 << 4) ++#define MV_DEBUG_FLAG_DUMP (1 << 5) ++#define MV_DEBUG_FLAG_CACHE (1 << 6) ++#define MV_DEBUG_FLAG_IOCTL (1 << 7) ++#define MV_DEBUG_FLAG_STATS (1 << 8) ++ ++extern MV_U32 mvDebug; ++extern MV_U32 mvDebugModules[MV_MODULE_MAX]; ++ ++#ifdef MV_DEBUG ++# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg ++# define MV_DEBUG_CODE(module, flags, code) code ++#elif defined(MV_RT_DEBUG) ++# define MV_DEBUG_PRINT(module, flags, msg) \ ++ if( (mvDebug & (1<<(module))) && \ ++ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ ++ mvOsPrintf msg ++# define MV_DEBUG_CODE(module, flags, code) \ ++ if( (mvDebug & (1<<(module))) && \ ++ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ ++ code ++#else ++# define MV_DEBUG_PRINT(module, flags, msg) ++# define MV_DEBUG_CODE(module, flags, code) ++#endif ++ ++ ++ ++/* typedefs */ ++ ++/* time measurement structure used to check how much time pass between ++ * two points ++ */ ++typedef struct { ++ char name[20]; /* name of the entry */ ++ unsigned long begin; /* time measured on begin point */ ++ unsigned long end; /* time measured on end point */ ++ unsigned long total; /* Accumulated time */ ++ unsigned long left; /* The rest measurement actions */ ++ unsigned long count; /* Maximum measurement actions */ ++ unsigned long min; /* Minimum time from begin to end */ ++ unsigned long max; /* Maximum time from begin to end */ ++} MV_DEBUG_TIMES; ++ ++ ++/* mvDebug.h API list */ ++ ++/****** Error Recording ******/ ++ ++/* Dump memory in specific format: ++ * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 ++ */ ++void mvDebugMemDump(void* addr, int size, int access); ++ ++void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access); ++ ++void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access); ++ ++void mvDebugPrintIpAddr(MV_U32 ipAddr); ++ ++void mvDebugPrintMacAddr(const MV_U8* pMacAddr); ++ ++/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ ++ ++/* Reset MV_DEBUG_TIMES entry */ ++void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name); ++ ++/* Update MV_DEBUG_TIMES entry */ ++void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry); ++ ++/* Print out MV_DEBUG_TIMES entry */ ++void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle); ++ ++ ++/******** General ***********/ ++ ++/* Change value of mvDebugPrint global variable */ ++ ++void mvDebugInit(void); ++void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); ++void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); ++void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); ++ ++ ++#endif /* __INCmvDebug.h */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,225 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDeviceIdh ++#define __INCmvDeviceIdh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* defines */ ++#define MARVELL_VEN_ID 0x11ab ++ ++/* Disco-3 */ ++#define MV64460_DEV_ID 0x6480 ++#define MV64460B_DEV_ID 0x6485 ++#define MV64430_DEV_ID 0x6420 ++ ++/* Disco-5 */ ++#define MV64560_DEV_ID 0x6450 ++ ++/* Disco-6 */ ++#define MV64660_DEV_ID 0x6460 ++ ++/* Orion */ ++#define MV_1181_DEV_ID 0x1181 ++#define MV_5181_DEV_ID 0x5181 ++#define MV_5281_DEV_ID 0x5281 ++#define MV_5182_DEV_ID 0x5182 ++#define MV_8660_DEV_ID 0x8660 ++#define MV_5180_DEV_ID 0x5180 ++#define MV_5082_DEV_ID 0x5082 ++#define MV_1281_DEV_ID 0x1281 ++#define MV_6082_DEV_ID 0x6082 ++#define MV_6183_DEV_ID 0x6183 ++#define MV_6183L_DEV_ID 0x6083 ++ ++#define MV_5281_D0_REV 0x4 ++#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) ++#define MV_5281_D0_NAME "88F5281 D0" ++ ++#define MV_5281_D1_REV 0x5 ++#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) ++#define MV_5281_D1_NAME "88F5281 D1" ++ ++#define MV_5281_D2_REV 0x6 ++#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) ++#define MV_5281_D2_NAME "88F5281 D2" ++ ++ ++#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ ++#define MV_5181_A1_REV 0x1 /* for USB Er ..*/ ++#define MV_5181_B0_REV 0x2 ++#define MV_5181_B1_REV 0x3 ++#define MV_5182_A1_REV 0x1 ++#define MV_5180N_B1_REV 0x3 ++#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) ++ ++ ++ ++/* kw */ ++#define MV_6281_DEV_ID 0x6281 ++#define MV_6192_DEV_ID 0x6192 ++#define MV_6190_DEV_ID 0x6190 ++#define MV_6180_DEV_ID 0x6180 ++ ++#define MV_6281_A0_REV 0x2 ++#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) ++#define MV_6281_A0_NAME "88F6281 A0" ++ ++#define MV_6192_A0_REV 0x2 ++#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) ++#define MV_6192_A0_NAME "88F6192 A0" ++ ++#define MV_6190_A0_REV 0x2 ++#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) ++#define MV_6190_A0_NAME "88F6190 A0" ++ ++#define MV_6180_A0_REV 0x2 ++#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) ++#define MV_6180_A0_NAME "88F6180 A0" ++ ++#define MV_6281_A1_REV 0x3 ++#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) ++#define MV_6281_A1_NAME "88F6281 A1" ++ ++#define MV_6192_A1_REV 0x3 ++#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) ++#define MV_6192_A1_NAME "88F6192 A1" ++ ++#define MV_6190_A1_REV 0x3 ++#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) ++#define MV_6190_A1_NAME "88F6190 A1" ++ ++#define MV_6180_A1_REV 0x3 ++#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) ++#define MV_6180_A1_NAME "88F6180 A1" ++ ++#define MV_88F6XXX_A0_REV 0x2 ++#define MV_88F6XXX_A1_REV 0x3 ++/* Disco-Duo */ ++#define MV_78XX0_ZY_DEV_ID 0x6381 ++#define MV_78XX0_ZY_NAME "MV78X00" ++ ++#define MV_78XX0_Z0_REV 0x1 ++#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) ++#define MV_78XX0_Z0_NAME "78X00 Z0" ++ ++#define MV_78XX0_Y0_REV 0x2 ++#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) ++#define MV_78XX0_Y0_NAME "78X00 Y0" ++ ++#define MV_78XX0_DEV_ID 0x7800 ++#define MV_78XX0_NAME "MV78X00" ++ ++#define MV_76100_DEV_ID 0x7610 ++#define MV_78200_DEV_ID 0x7820 ++#define MV_78100_DEV_ID 0x7810 ++#define MV_78XX0_A0_REV 0x1 ++#define MV_78XX0_A1_REV 0x2 ++ ++#define MV_76100_NAME "MV76100" ++#define MV_78100_NAME "MV78100" ++#define MV_78200_NAME "MV78200" ++ ++#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) ++#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) ++#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) ++ ++#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) ++#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) ++#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) ++ ++#define MV_76100_A0_NAME "MV76100 A0" ++#define MV_78100_A0_NAME "MV78100 A0" ++#define MV_78200_A0_NAME "MV78200 A0" ++#define MV_78XX0_A0_NAME "MV78XX0 A0" ++ ++#define MV_76100_A1_NAME "MV76100 A1" ++#define MV_78100_A1_NAME "MV78100 A1" ++#define MV_78200_A1_NAME "MV78200 A1" ++#define MV_78XX0_A1_NAME "MV78XX0 A1" ++ ++/*MV88F632X family*/ ++#define MV_6321_DEV_ID 0x6321 ++#define MV_6322_DEV_ID 0x6322 ++#define MV_6323_DEV_ID 0x6323 ++ ++#define MV_6321_NAME "88F6321" ++#define MV_6322_NAME "88F6322" ++#define MV_6323_NAME "88F6323" ++ ++#define MV_632X_A1_REV 0x2 ++ ++#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) ++#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) ++#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) ++ ++#define MV_6321_A1_NAME "88F6321 A1" ++#define MV_6322_A1_NAME "88F6322 A1" ++#define MV_6323_A1_NAME "88F6323 A1" ++ ++ ++#endif /* __INCmvDeviceIdh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,73 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvHalVerh ++#define __INCmvHalVerh ++ ++/* Defines */ ++#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7" ++#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4" ++ ++#endif /* __INCmvHalVerh */ +\ No newline at end of file +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,100 @@ ++/******************************************************************************* ++* Copyright 2003, Marvell Semiconductor Israel LTD. * ++* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * ++* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * ++* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * ++* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * ++* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * ++* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * ++* * ++* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * ++* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * ++* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * ++* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * ++******************************************************************************** ++* mvQueue.c ++* ++* FILENAME: $Workfile: mvStack.c $ ++* REVISION: $Revision: 1.1 $ ++* LAST UPDATE: $Modtime: $ ++* ++* DESCRIPTION: ++* This file implements simple Stack LIFO functionality. ++*******************************************************************************/ ++ ++/* includes */ ++#include "mvOs.h" ++#include "mvTypes.h" ++#include "mvDebug.h" ++#include "mvStack.h" ++ ++/* defines */ ++ ++ ++/* Public functions */ ++ ++ ++/* Purpose: Create new stack ++ * Inputs: ++ * - MV_U32 noOfElements - maximum number of elements in the stack. ++ * Each element 4 bytes size ++ * Return: void* - pointer to created stack. ++ */ ++void* mvStackCreate(int numOfElements) ++{ ++ MV_STACK* pStack; ++ MV_U32* pStackElements; ++ ++ pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK)); ++ pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32)); ++ if( (pStack == NULL) || (pStackElements == NULL) ) ++ { ++ mvOsPrintf("mvStack: Can't create new stack\n"); ++ return NULL; ++ } ++ memset(pStackElements, 0, numOfElements*sizeof(MV_U32)); ++ pStack->numOfElements = numOfElements; ++ pStack->stackIdx = 0; ++ pStack->stackElements = pStackElements; ++ ++ return pStack; ++} ++ ++/* Purpose: Delete existing stack ++ * Inputs: ++ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function ++ * ++ * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. ++ * MV_OK - Success. ++ */ ++MV_STATUS mvStackDelete(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ if( (pStack == NULL) || (pStack->stackElements == NULL) ) ++ return MV_NOT_FOUND; ++ ++ mvOsFree(pStack->stackElements); ++ mvOsFree(pStack); ++ ++ return MV_OK; ++} ++ ++ ++/* PrintOut status of the stack */ ++void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements) ++{ ++ int i; ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", ++ stackHndl, pStack->stackElements, pStack->numOfElements, ++ pStack->stackIdx); ++ if(isPrintElements == MV_TRUE) ++ { ++ for(i=0; istackIdx; i++) ++ { ++ mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); ++ } ++ } ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,140 @@ ++/******************************************************************************* ++* Copyright 2003, Marvell Semiconductor Israel LTD. * ++* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * ++* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * ++* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * ++* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * ++* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * ++* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * ++* * ++* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * ++* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * ++* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * ++* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * ++******************************************************************************** ++* mvStack.h - Header File for : ++* ++* FILENAME: $Workfile: mvStack.h $ ++* REVISION: $Revision: 1.1 $ ++* LAST UPDATE: $Modtime: $ ++* ++* DESCRIPTION: ++* This file defines simple Stack (LIFO) functionality. ++* ++*******************************************************************************/ ++ ++#ifndef __mvStack_h__ ++#define __mvStack_h__ ++ ++ ++/* includes */ ++#include "mvTypes.h" ++ ++ ++/* defines */ ++ ++ ++/* typedefs */ ++/* Data structure describes general purpose Stack */ ++typedef struct ++{ ++ int stackIdx; ++ int numOfElements; ++ MV_U32* stackElements; ++} MV_STACK; ++ ++static INLINE MV_BOOL mvStackIsFull(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ if(pStack->stackIdx == pStack->numOfElements) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ if(pStack->stackIdx == 0) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++/* Purpose: Push new element to stack ++ * Inputs: ++ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. ++ * - MV_U32 value - New element. ++ * ++ * Return: MV_STATUS MV_FULL - Failure. Stack is full. ++ * MV_OK - Success. Element is put to stack. ++ */ ++static INLINE void mvStackPush(void* stackHndl, MV_U32 value) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++#ifdef MV_RT_DEBUG ++ if(pStack->stackIdx == pStack->numOfElements) ++ { ++ mvOsPrintf("mvStackPush: Stack is FULL\n"); ++ return; ++ } ++#endif /* MV_RT_DEBUG */ ++ ++ pStack->stackElements[pStack->stackIdx] = value; ++ pStack->stackIdx++; ++} ++ ++/* Purpose: Pop element from the top of stack and copy it to "pValue" ++ * Inputs: ++ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. ++ * - MV_U32 value - Element in the top of stack. ++ * ++ * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. ++ * MV_OK - Success. Element is removed from the stack and ++ * copied to pValue argument ++ */ ++static INLINE MV_U32 mvStackPop(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++#ifdef MV_RT_DEBUG ++ if(pStack->stackIdx == 0) ++ { ++ mvOsPrintf("mvStackPop: Stack is EMPTY\n"); ++ return 0; ++ } ++#endif /* MV_RT_DEBUG */ ++ ++ pStack->stackIdx--; ++ return pStack->stackElements[pStack->stackIdx]; ++} ++ ++static INLINE int mvStackIndex(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ return pStack->stackIdx; ++} ++ ++static INLINE int mvStackFreeElements(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ return (pStack->numOfElements - pStack->stackIdx); ++} ++ ++/* mvStack.h API list */ ++ ++/* Create new Stack */ ++void* mvStackCreate(int numOfElements); ++ ++/* Delete existing stack */ ++MV_STATUS mvStackDelete(void* stackHndl); ++ ++/* Print status of the stack */ ++void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements); ++ ++#endif /* __mvStack_h__ */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvTypes.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,245 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvTypesh ++#define __INCmvTypesh ++ ++/* Defines */ ++ ++/* The following is a list of Marvell status */ ++#define MV_ERROR (-1) ++#define MV_OK (0x00) /* Operation succeeded */ ++#define MV_FAIL (0x01) /* Operation failed */ ++#define MV_BAD_VALUE (0x02) /* Illegal value (general) */ ++#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ ++#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ ++#define MV_BAD_PTR (0x05) /* Illegal pointer value */ ++#define MV_BAD_SIZE (0x06) /* Illegal size */ ++#define MV_BAD_STATE (0x07) /* Illegal state of state machine */ ++#define MV_SET_ERROR (0x08) /* Set operation failed */ ++#define MV_GET_ERROR (0x09) /* Get operation failed */ ++#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ ++#define MV_NOT_FOUND (0x0B) /* Item not found */ ++#define MV_NO_MORE (0x0C) /* No more items found */ ++#define MV_NO_SUCH (0x0D) /* No such item */ ++#define MV_TIMEOUT (0x0E) /* Time Out */ ++#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ ++#define MV_NOT_SUPPORTED (0x10) /* This request is not support */ ++#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */ ++#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ ++#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ ++#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ ++#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ ++#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ ++#define MV_HW_ERROR (0x17) /* Hardware error */ ++#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ ++#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ ++#define MV_NOT_READY (0x1A) /* The other side is not ready yet */ ++#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ ++#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ ++#define MV_NOT_STARTED (0x1D) /* Not started yet */ ++#define MV_BUSY (0x1E) /* Item is busy. */ ++#define MV_TERMINATE (0x1F) /* Item terminates it's work. */ ++#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ ++#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ ++#define MV_WRITE_PROTECT (0x22) /* Write protected */ ++ ++ ++#define MV_INVALID (int)(-1) ++ ++#define MV_FALSE 0 ++#define MV_TRUE (!(MV_FALSE)) ++ ++ ++#ifndef NULL ++#define NULL ((void*)0) ++#endif ++ ++ ++#ifndef MV_ASMLANGUAGE ++/* typedefs */ ++ ++typedef char MV_8; ++typedef unsigned char MV_U8; ++ ++typedef int MV_32; ++typedef unsigned int MV_U32; ++ ++typedef short MV_16; ++typedef unsigned short MV_U16; ++ ++#ifdef MV_PPC64 ++typedef long MV_64; ++typedef unsigned long MV_U64; ++#else ++typedef long long MV_64; ++typedef unsigned long long MV_U64; ++#endif ++ ++typedef long MV_LONG; /* 32/64 */ ++typedef unsigned long MV_ULONG; /* 32/64 */ ++ ++typedef int MV_STATUS; ++typedef int MV_BOOL; ++typedef void MV_VOID; ++typedef float MV_FLOAT; ++ ++typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ ++typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ ++typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/ ++typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ ++ ++typedef MV_U32 MV_KHZ; ++typedef MV_U32 MV_MHZ; ++typedef MV_U32 MV_HZ; ++ ++ ++/* This enumerator describes the set of commands that can be applied on */ ++/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ ++/* status (see MV_STATE enumerator) */ ++/* Start can be applied only when status is IDLE */ ++/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ ++/* Pause can be applied only when status is ACTIVE */ ++/* Restart can be applied only when status is PAUSED */ ++typedef enum _mvCommand ++{ ++ MV_START, /* Start */ ++ MV_STOP, /* Stop */ ++ MV_PAUSE, /* Pause */ ++ MV_RESTART /* Restart */ ++} MV_COMMAND; ++ ++/* This enumerator describes the set of state conditions. */ ++/* Moving from one state to other is stricted. */ ++typedef enum _mvState ++{ ++ MV_IDLE, ++ MV_ACTIVE, ++ MV_PAUSED, ++ MV_UNDEFINED_STATE ++} MV_STATE; ++ ++ ++/* This structure describes address space window. Window base can be */ ++/* 64 bit, window size up to 4GB */ ++typedef struct _mvAddrWin ++{ ++ MV_U32 baseLow; /* 32bit base low */ ++ MV_U32 baseHigh; /* 32bit base high */ ++ MV_U32 size; /* 32bit size */ ++}MV_ADDR_WIN; ++ ++/* This binary enumerator describes protection attribute status */ ++typedef enum _mvProtRight ++{ ++ ALLOWED, /* Protection attribute allowed */ ++ FORBIDDEN /* Protection attribute forbidden */ ++}MV_PROT_RIGHT; ++ ++/* Unified struct for Rx and Tx packet operations. The user is required to */ ++/* be familier only with Tx/Rx descriptor command status. */ ++typedef struct _bufInfo ++{ ++ MV_U32 cmdSts; /* Tx/Rx command status */ ++ MV_U16 byteCnt; /* Size of valid data in the buffer */ ++ MV_U16 bufSize; /* Total size of the buffer */ ++ MV_U8 *pBuff; /* Pointer to Buffer */ ++ MV_U8 *pData; /* Pointer to data in the Buffer */ ++ MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ ++ MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ ++ struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ ++} BUF_INFO; ++ ++/* This structure contains information describing one of buffers ++ * (fragments) they are built Ethernet packet. ++ */ ++typedef struct ++{ ++ MV_U8* bufVirtPtr; ++ MV_ULONG bufPhysAddr; ++ MV_U32 bufSize; ++ MV_U32 dataSize; ++ MV_U32 memHandle; ++ MV_32 bufAddrShift; ++} MV_BUF_INFO; ++ ++/* This structure contains information describing Ethernet packet. ++ * The packet can be divided for few buffers (fragments) ++ */ ++typedef struct ++{ ++ MV_ULONG osInfo; ++ MV_BUF_INFO *pFrags; ++ MV_U32 status; ++ MV_U16 pktSize; ++ MV_U16 numFrags; ++ MV_U32 ownerId; ++ MV_U32 fragIP; ++} MV_PKT_INFO; ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++#endif /* __INCmvTypesh */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,110 @@ ++#include ++#include ++#include ++#include "dbg-trace.h" ++ ++#define TRACE_ARR_LEN 800 ++#define STR_LEN 128 ++struct trace { ++ struct timeval tv; ++ char str[STR_LEN]; ++ unsigned int callback_val1; ++ unsigned int callback_val2; ++ char valid; ++}; ++static unsigned int (*trc_callback1) (unsigned char) = NULL; ++static unsigned int (*trc_callback2) (unsigned char) = NULL; ++static unsigned char trc_param1 = 0; ++static unsigned char trc_param2 = 0; ++struct trace *trc_arr; ++static int trc_index; ++static int trc_active = 0; ++ ++void TRC_START() ++{ ++ trc_active = 1; ++} ++ ++void TRC_STOP() ++{ ++ trc_active = 0; ++} ++ ++void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param) ++{ ++ printk("Marvell debug tracing is on\n"); ++ trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL); ++ if(trc_arr == NULL) ++ { ++ printk("Can't allocate Debug Trace buffer\n"); ++ return; ++ } ++ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); ++ trc_index = 0; ++ trc_callback1 = callback1; ++ trc_callback2 = callback2; ++ trc_param1 = callback1_param; ++ trc_param2 = callback2_param; ++} ++void TRC_REC(char *fmt,...) ++{ ++ va_list args; ++ struct trace *trc = &trc_arr[trc_index]; ++ ++ if(trc_active == 0) ++ return; ++ ++ do_gettimeofday(&trc->tv); ++ if(trc_callback1) ++ trc->callback_val1 = trc_callback1(trc_param1); ++ if(trc_callback2) ++ trc->callback_val2 = trc_callback2(trc_param2); ++ va_start(args, fmt); ++ vsprintf(trc->str,fmt,args); ++ va_end(args); ++ trc->valid = 1; ++ if((++trc_index) == TRACE_ARR_LEN) { ++ trc_index = 0; ++ } ++} ++void TRC_OUTPUT(void) ++{ ++ int i,j; ++ struct trace *p; ++ printk("\n\nTrace %d items\n",TRACE_ARR_LEN); ++ for(i=0,j=trc_index; ivalid) { ++ unsigned long uoffs; ++ struct trace *plast; ++ if(p == &trc_arr[0]) ++ plast = &trc_arr[TRACE_ARR_LEN-1]; ++ else ++ plast = p-1; ++ if(p->tv.tv_sec == ((plast)->tv.tv_sec)) ++ uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec)); ++ else ++ uoffs = (1000000 - ((plast)->tv.tv_usec)) + ++ ((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) + ++ p->tv.tv_usec; ++ printk("%03d: [+%ld usec]", j, (unsigned long)uoffs); ++ if(trc_callback1) ++ printk("[%u]",p->callback_val1); ++ if(trc_callback2) ++ printk("[%u]",p->callback_val2); ++ printk(": %s",p->str); ++ } ++ p->valid = 0; ++ } ++ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); ++ trc_index = 0; ++} ++void TRC_RELEASE(void) ++{ ++ kfree(trc_arr); ++ trc_index = 0; ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,24 @@ ++ ++#ifndef _MV_DBG_TRCE_H_ ++#define _MV_DBG_TRCE_H_ ++ ++#ifdef CONFIG_MV_DBG_TRACE ++void TRC_INIT(void *callback1, void *callback2, ++ unsigned char callback1_param, unsigned char callback2_param); ++void TRC_REC(char *fmt,...); ++void TRC_OUTPUT(void); ++void TRC_RELEASE(void); ++void TRC_START(void); ++void TRC_STOP(void); ++ ++#else ++#define TRC_INIT(x1,x2,x3,x4) ++#define TRC_REC(X...) ++#define TRC_OUTPUT() ++#define TRC_RELEASE() ++#define TRC_START() ++#define TRC_STOP() ++#endif ++ ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,2513 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "boardEnv/mvBoardEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "cpu/mvCpu.h" ++#include "cntmr/mvCntmr.h" ++#include "gpp/mvGpp.h" ++#include "twsi/mvTwsi.h" ++#include "pex/mvPex.h" ++#include "device/mvDevice.h" ++#include "eth/gbe/mvEthRegs.h" ++ ++/* defines */ ++/* #define MV_DEBUG */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++extern MV_CPU_ARM_CLK _cpuARMDDRCLK[]; ++ ++#define CODE_IN_ROM MV_FALSE ++#define CODE_IN_RAM MV_TRUE ++ ++extern MV_BOARD_INFO* boardInfoTbl[]; ++#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] ++ ++/* Locals */ ++static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++ ++MV_U32 tClkRate = -1; ++ ++ ++/******************************************************************************* ++* mvBoardEnvInit - Init board ++* ++* DESCRIPTION: ++* In this function the board environment take care of device bank ++* initialization. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvBoardEnvInit(MV_VOID) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); ++ return; ++ ++ } ++ ++ /* Set GPP Out value */ ++ MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); ++ MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh); ++ ++ /* set GPP polarity */ ++ mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); ++ mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); ++ ++ /* Workaround for Erratum FE-MISC-70*/ ++ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV) ++ { ++ BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd; ++ BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002; ++ } /*End of WA*/ ++ ++ /* Set GPP Out Enable*/ ++ mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); ++ mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); ++ ++ /* Nand CE */ ++ MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT); ++} ++ ++/******************************************************************************* ++* mvBoardModelGet - Get Board model ++* ++* DESCRIPTION: ++* This function returns 16bit describing board model. ++* Board model is constructed of one byte major and minor numbers in the ++* following manner: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* String describing board model. ++* ++*******************************************************************************/ ++MV_U16 mvBoardModelGet(MV_VOID) ++{ ++ return (mvBoardIdGet() >> 16); ++} ++ ++/******************************************************************************* ++* mbBoardRevlGet - Get Board revision ++* ++* DESCRIPTION: ++* This function returns a 32bit describing the board revision. ++* Board revision is constructed of 4bytes. 2bytes describes major number ++* and the other 2bytes describes minor munber. ++* For example for board revision 3.4 the function will return ++* 0x00030004. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* String describing board model. ++* ++*******************************************************************************/ ++MV_U16 mvBoardRevGet(MV_VOID) ++{ ++ return (mvBoardIdGet() & 0xFFFF); ++} ++ ++/******************************************************************************* ++* mvBoardNameGet - Get Board name ++* ++* DESCRIPTION: ++* This function returns a string describing the board model and revision. ++* String is extracted from board I2C EEPROM. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. ++* ++* RETURN: ++* ++* MV_ERROR if informantion can not be read. ++*******************************************************************************/ ++MV_STATUS mvBoardNameGet(char *pNameBuff) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsSPrintf (pNameBuff, "Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardIsPortInSgmii - ++* ++* DESCRIPTION: ++* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE ++* For all other options. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE - port in SGMII. ++* MV_FALSE - other. ++* ++*******************************************************************************/ ++MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) ++{ ++ MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; ++ ++ if(ethPortNum >= BOARD_ETH_PORT_NUM) ++ { ++ mvOsPrintf ("Invalid portNo=%d\n", ethPortNum); ++ return MV_FALSE; ++ } ++ return ethPortSgmiiSupport[ethPortNum]; ++} ++ ++/******************************************************************************* ++* mvBoardIsPortInGmii - ++* ++* DESCRIPTION: ++* This routine returns MV_TRUE for port number works in GMII or MV_FALSE ++* For all other options. ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE - port in GMII. ++* MV_FALSE - other. ++* ++*******************************************************************************/ ++MV_BOOL mvBoardIsPortInGmii(MV_VOID) ++{ ++ MV_U32 devClassId, devClass = 0; ++ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) ++ { ++ /* Get MPP module ID */ ++ devClassId = mvBoarModuleTypeGet(devClass); ++ if (MV_BOARD_MODULE_GMII_ID == devClassId) ++ return MV_TRUE; ++ } ++ else if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++/******************************************************************************* ++* mvBoardPhyAddrGet - Get the phy address ++* ++* DESCRIPTION: ++* This routine returns the Phy address of a given ethernet port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing Phy address, -1 if the port number is wrong. ++* ++*******************************************************************************/ ++MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; ++} ++ ++/******************************************************************************* ++* mvBoardMacSpeedGet - Get the Mac speed ++* ++* DESCRIPTION: ++* This routine returns the Mac speed if pre define of a given ethernet port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. ++* ++*******************************************************************************/ ++MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; ++} ++ ++/******************************************************************************* ++* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication ++* ++* DESCRIPTION: ++* This routine returns the IRQ number for the link status indication. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the number of the IRQ for the link status indication, -1 if the port ++* number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq; ++} ++ ++/******************************************************************************* ++* mvBoardSwitchPortGet - Get the mapping between the board connector and the ++* Ethernet Switch port ++* ++* DESCRIPTION: ++* This routine returns the matching Switch port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* boardPortNum - logical number of the connector on the board ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the matching Switch port, -1 if the port number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) ++ { ++ mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum]; ++} ++ ++/******************************************************************************* ++* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port ++* ++* DESCRIPTION: ++* This routine returns the Switch CPU port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the Switch CPU port, -1 if the port number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort; ++} ++ ++/******************************************************************************* ++* mvBoardIsSwitchConnected - Get switch connection status ++* DESCRIPTION: ++* This routine returns port's connection status ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 1 - if ethPortNum is connected to switch, 0 otherwise ++* ++*******************************************************************************/ ++MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) ++ { ++ mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum); ++ return MV_ERROR; ++ } ++ ++ if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo)) ++ return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum); ++ else ++ return 0; ++} ++/******************************************************************************* ++* mvBoardSmiScanModeGet - Get Switch SMI scan mode ++* ++* DESCRIPTION: ++* This routine returns Switch SMI scan mode. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode; ++} ++/******************************************************************************* ++* mvBoardSpecInitGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, ++* otherwise return MV_FALSE. ++* ++* ++*******************************************************************************/ ++ ++MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) ++{ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvBoardTclkGet - Get the board Tclk (Controller clock) ++* ++* DESCRIPTION: ++* This routine extract the controller core clock. ++* This function uses the controller counters to make identification. ++* Note: In order to avoid interference, make sure task context switch ++* and interrupts will not occure during this function operation ++* ++* INPUT: ++* countNum - Counter number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit clock cycles in Hertz. ++* ++*******************************************************************************/ ++MV_U32 mvBoardTclkGet(MV_VOID) ++{ ++ if(mvCtrlModelGet()==MV_6281_DEV_ID) ++ { ++#if defined(TCLK_AUTO_DETECT) ++ MV_U32 tmpTClkRate = MV_BOARD_TCLK_166MHZ; ++ ++ tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ tmpTClkRate &= MSAR_TCLCK_MASK; ++ ++ switch (tmpTClkRate) ++ { ++ case MSAR_TCLCK_166: ++ return MV_BOARD_TCLK_166MHZ; ++ break; ++ case MSAR_TCLCK_200: ++ return MV_BOARD_TCLK_200MHZ; ++ break; ++ } ++#else ++ return MV_BOARD_TCLK_200MHZ; ++#endif ++ } ++ ++ return MV_BOARD_TCLK_166MHZ; ++ ++} ++/******************************************************************************* ++* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) ++* ++* DESCRIPTION: ++* This routine extract the CPU bus clock. ++* ++* INPUT: ++* countNum - Counter number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit clock cycles in Hertz. ++* ++*******************************************************************************/ ++static MV_U32 mvBoard6180SysClkGet(MV_VOID) ++{ ++ MV_U32 sysClkRate=0; ++ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; ++ ++ sysClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ sysClkRate = sysClkRate & MSAR_CPUCLCK_MASK_6180; ++ sysClkRate = sysClkRate >> MSAR_CPUCLCK_OFFS_6180; ++ ++ sysClkRate = _cpu6180_ddr_l2_CLK[sysClkRate].ddrClk; ++ ++ return sysClkRate; ++ ++} ++ ++MV_U32 mvBoardSysClkGet(MV_VOID) ++{ ++#ifdef SYSCLK_AUTO_DETECT ++ MV_U32 sysClkRate, tmp, pClkRate, indexDdrRtio; ++ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; ++ MV_U32 ddrRtio[][2] = MV_DDR_CLCK_RTIO_TBL; ++ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return mvBoard6180SysClkGet(); ++ ++ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ pClkRate = MSAR_CPUCLCK_EXTRACT(tmp); ++ pClkRate = cpuCLK[pClkRate]; ++ ++ indexDdrRtio = tmp & MSAR_DDRCLCK_RTIO_MASK; ++ indexDdrRtio = indexDdrRtio >> MSAR_DDRCLCK_RTIO_OFFS; ++ if(ddrRtio[indexDdrRtio][0] != 0) ++ sysClkRate = ((pClkRate * ddrRtio[indexDdrRtio][1]) / ddrRtio[indexDdrRtio][0]); ++ else ++ sysClkRate = 0; ++ return sysClkRate; ++#else ++ return MV_BOARD_DEFAULT_SYSCLK; ++#endif ++} ++ ++ ++/******************************************************************************* ++* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number ++* ++* DESCRIPTION: ++* Multi-ported PCI Express bridges that is implemented on the board ++* collapse interrupts across multiple conventional PCI/PCI-X buses. ++* A dual-headed PCI Express bridge would map (or "swizzle") the ++* interrupts per the following table (in accordance with the respective ++* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD# ++* signals from its two logical PCI/PCI-X bridges, collapse the ++* INTA#-INTD# signals from any internal sources, and convert the ++* signals to in-band PCI Express messages. 10 ++* This function returns the upstream interrupt as it was converted by ++* the bridge, according to board configuration and the following table: ++* PCI dev num ++* Interrupt pin 7, 8, 9 ++* A -> A D C ++* B -> B A D ++* C -> C B A ++* D -> D C B ++* ++* ++* INPUT: ++* devNum - PCI/PCIX device number. ++* intPin - PCI Int pin ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Int pin connected to the Interrupt controller ++* ++*******************************************************************************/ ++MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin) ++{ ++ MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 ); ++ ++ if (realIntPin == 0) return 4; ++ else return realIntPin; ++ ++} ++ ++/******************************************************************************* ++* mvBoardDebugLedNumGet - Get number of debug Leds ++* ++* DESCRIPTION: ++* INPUT: ++* boardId ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) ++{ ++ return BOARD_INFO(boardId)->activeLedsNumber; ++} ++ ++/******************************************************************************* ++* mvBoardDebugLeg - Set the board debug Leds ++* ++* DESCRIPTION: turn on/off status leds. ++* Note: assume MPP leds are part of group 0 only. ++* ++* INPUT: ++* hexNum - Number to be displied in hex by Leds. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvBoardDebugLed(MV_U32 hexNum) ++{ ++ MV_U32 val = 0,totalMask, currentBitMask = 1,i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (BOARD_INFO(boardId)->pLedGppPin == NULL) ++ return; ++ ++ totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1; ++ hexNum &= totalMask; ++ totalMask = 0; ++ ++ for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++) ++ { ++ if (hexNum & currentBitMask) ++ { ++ val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); ++ } ++ ++ totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); ++ ++ currentBitMask = (currentBitMask << 1); ++ } ++ ++ if (BOARD_INFO(boardId)->ledsPolarity) ++ { ++ mvGppValueSet(0, totalMask, val); ++ } ++ else ++ { ++ mvGppValueSet(0, totalMask, ~val); ++ } ++} ++ ++ ++/******************************************************************************* ++* mvBoarGpioPinGet - mvBoarGpioPinGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* class - MV_BOARD_GPP_CLASS enum. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index) ++{ ++ MV_U32 boardId, i; ++ MV_U32 indexFound = 0; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) ++ if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) { ++ if (indexFound == index) ++ return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; ++ else ++ indexFound++; ++ ++ } ++ ++ return MV_ERROR; ++} ++ ++ ++/******************************************************************************* ++* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardRTCGpioPinGet(MV_VOID) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_RTC, 0); ++} ++ ++ ++/******************************************************************************* ++* mvBoardReset - mvBoardReset ++* ++* DESCRIPTION: ++* Reset the board ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None ++* ++*******************************************************************************/ ++MV_VOID mvBoardReset(MV_VOID) ++{ ++ MV_32 resetPin; ++ ++ /* Get gpp reset pin if define */ ++ resetPin = mvBoardResetGpioPinGet(); ++ if (resetPin != MV_ERROR) ++ { ++ MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); ++ MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); ++ ++ } ++ else ++ { ++ /* No gpp reset pin was found, try to reset ussing ++ system reset out */ ++ MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2); ++ MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); ++ } ++} ++ ++/******************************************************************************* ++* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardResetGpioPinGet(MV_VOID) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); ++} ++/******************************************************************************* ++* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet ++* ++* DESCRIPTION: ++* used for hotswap detection ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardSDIOGpioPinGet(MV_VOID) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_SDIO_DETECT, 0); ++} ++ ++/******************************************************************************* ++* mvBoardUSBVbusGpioPinGet - return Vbus input GPP ++* ++* DESCRIPTION: ++* ++* INPUT: ++* int devNo. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); ++} ++ ++/******************************************************************************* ++* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP ++* ++* DESCRIPTION: ++* ++* INPUT: ++* int devNo. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); ++} ++ ++ ++/******************************************************************************* ++* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins ++* ++* DESCRIPTION: ++* This function returns a 32-bit mask of GPP pins that connected to ++* interrupt generating sources on board. ++* For example if UART channel A is hardwired to GPP pin 8 and ++* UART channel B is hardwired to GPP pin 4 the fuinction will return ++* the value 0x000000110 ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* See description. The function return -1 if board is not identified. ++* ++*******************************************************************************/ ++MV_32 mvBoardGpioIntMaskLowGet(MV_VOID) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return BOARD_INFO(boardId)->intsGppMaskLow; ++} ++MV_32 mvBoardGpioIntMaskHighGet(MV_VOID) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return BOARD_INFO(boardId)->intsGppMaskHigh; ++} ++ ++ ++/******************************************************************************* ++* mvBoardMppGet - Get board dependent MPP register value ++* ++* DESCRIPTION: ++* MPP settings are derived from board design. ++* MPP group consist of 8 MPPs. An MPP group represent MPP ++* control register. ++* This function retrieves board dependend MPP register value. ++* ++* INPUT: ++* mppGroupNum - MPP group number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit value describing MPP control register value. ++* ++*******************************************************************************/ ++MV_32 mvBoardMppGet(MV_U32 mppGroupNum) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum]; ++} ++ ++ ++/******************************************************************************* ++* mvBoardMppGroupId - If MPP group type is AUTO then identify it using twsi ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppGroupIdUpdate(MV_VOID) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MODULE_ID_CLASS devClassId; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U32 maxMppGrp = 1; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ /* If MPP group can be defined by the module connected to it */ ++ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) ++ { ++ /* Get MPP module ID */ ++ devClassId = mvBoarModuleTypeGet(devClass); ++ if (MV_ERROR != devClassId) ++ { ++ switch(devClassId) ++ { ++ case MV_BOARD_MODULE_TDM_ID: ++ case MV_BOARD_MODULE_TDM_5CHAN_ID: ++ mppGroupType = MV_BOARD_TDM; ++ break; ++ case MV_BOARD_MODULE_AUDIO_ID: ++ mppGroupType = MV_BOARD_AUDIO; ++ break; ++ case MV_BOARD_MODULE_RGMII_ID: ++ mppGroupType = MV_BOARD_RGMII; ++ break; ++ case MV_BOARD_MODULE_GMII_ID: ++ mppGroupType = MV_BOARD_GMII; ++ break; ++ case MV_BOARD_MODULE_TS_ID: ++ mppGroupType = MV_BOARD_TS; ++ break; ++ case MV_BOARD_MODULE_MII_ID: ++ mppGroupType = MV_BOARD_MII; ++ break; ++ default: ++ mppGroupType = MV_BOARD_OTHER; ++ break; ++ } ++ } ++ else ++ /* The module bay is empty */ ++ mppGroupType = MV_BOARD_OTHER; ++ ++ /* Update MPP group type */ ++ mvBoardMppGroupTypeSet(devClass, mppGroupType); ++ } ++ ++ /* Update MPP output voltage for RGMII 1.8V. Set port to GMII for GMII module */ ++ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_RGMII)) ++ MV_REG_BIT_SET(MPP_OUTPUT_DRIVE_REG,MPP_1_8_RGMII1_OUTPUT_DRIVE | MPP_1_8_RGMII0_OUTPUT_DRIVE); ++ else ++ { ++ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII)) ++ { ++ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); ++ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(0),BIT3); ++ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); ++ } ++ else if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_MII)) ++ { ++ /* Assumption that the MDC & MDIO should be 3.3V */ ++ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); ++ /* Assumption that only ETH1 can be MII when using modules on DB */ ++ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); ++ } ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvBoardMppGroupTypeGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) ++ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1; ++ else ++ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2; ++} ++ ++/******************************************************************************* ++* mvBoardMppGroupTypeSet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. ++* mppGroupType - MPP group type for MPP[35:20] or for MPP[49:36]. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); ++ } ++ ++ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) ++ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1 = mppGroupType; ++ else ++ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2 = mppGroupType; ++ ++} ++ ++/******************************************************************************* ++* mvBoardMppMuxSet - Update MPP mux ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppMuxSet(MV_VOID) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U8 muxVal = 0xf; ++ MV_U32 maxMppGrp = 1; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ mppGroupType = mvBoardMppGroupTypeGet(devClass); ++ ++ switch(mppGroupType) ++ { ++ case MV_BOARD_TDM: ++ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); ++ break; ++ case MV_BOARD_AUDIO: ++ muxVal &= ~(devClass ? 0x7 : 0x0); /*old Z0 value 0xd:0x0*/ ++ break; ++ case MV_BOARD_TS: ++ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); ++ break; ++ default: ++ muxVal |= (devClass ? 0xf : 0); ++ break; ++ } ++ } ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); ++ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 2; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 6; ++ muxVal = 0; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ ++} ++ ++/******************************************************************************* ++* mvBoardTdmMppSet - set MPPs in TDM module ++* ++* DESCRIPTION: ++* ++* INPUT: type of second telephony device ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardTdmMppSet(MV_32 chType) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U8 muxVal = 1; ++ MV_U8 muxValMask = 1; ++ MV_U8 twsiVal; ++ MV_U32 maxMppGrp = 1; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ mppGroupType = mvBoardMppGroupTypeGet(devClass); ++ if(mppGroupType == MV_BOARD_TDM) ++ break; ++ } ++ ++ if(devClass == maxMppGrp) ++ return; /* TDM module not found */ ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if(mvBoardIdGet() == RD_88F6281A_ID) ++ { ++ muxVal = 0xc; ++ muxValMask = 0xf3; ++ } ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxValMask) | muxVal; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp out val fail\n"); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ muxVal = 0xfe; ++ if(mvBoardIdGet() == RD_88F6281A_ID) ++ muxVal = 0xf3; ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxVal); ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp change to out fail\n"); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ /* reset the line to 0 */ ++ twsiSlave.offset = 3; ++ muxVal = 0; ++ muxValMask = 1; ++ ++ if(mvBoardIdGet() == RD_88F6281A_ID) { ++ muxVal = 0x0; ++ muxValMask = 0xf3; ++ } ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxValMask) | muxVal; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp out val fail\n"); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ mvOsDelay(20); ++ ++ /* set the line to 1 */ ++ twsiSlave.offset = 3; ++ muxVal = 1; ++ muxValMask = 1; ++ ++ if(mvBoardIdGet() == RD_88F6281A_ID) ++ { ++ muxVal = 0xc; ++ muxValMask = 0xf3; ++ if(chType) /* FXS - issue reset properly */ ++ { ++ MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), MV_GPP12); ++ mvOsDelay(50); ++ MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), MV_GPP12); ++ } ++ else /* FXO - issue reset via TDM_CODEC_RST*/ ++ { ++ /* change MPP44 type to TDM_CODEC_RST(0x2) */ ++ MV_REG_WRITE(MPP_CONTROL_REG5, ((MV_REG_READ(MPP_CONTROL_REG5) & 0xFFF0FFFF) | BIT17)); ++ } ++ } ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxValMask) | muxVal; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp out val fail\n"); ++ return; ++ } ++ ++ /* TBD - 5 channels */ ++#if defined(MV_TDM_5CHANNELS) ++ /* change MPP38 type to GPIO(0x0) & polarity for TDM_STROBE */ ++ MV_REG_WRITE(MPP_CONTROL_REG4, (MV_REG_READ(MPP_CONTROL_REG4) & 0xF0FFFFFF)); ++ mvGppPolaritySet(1, MV_GPP6, 0); ++ ++ twsiSlave.offset = 6; ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(2); ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & ~BIT2); ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp change to out fail\n"); ++ return; ++ } ++ ++ ++ twsiSlave.offset = 2; ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & ~BIT2); ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp change to out fail\n"); ++ return; ++ } ++#endif ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ ++} ++/******************************************************************************* ++* mvBoardVoiceConnModeGet - return SLIC/DAA connection & interrupt modes ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++ ++MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode) ++{ ++ switch(mvBoardIdGet()) ++ { ++ case RD_88F6281A_ID: ++ *connMode = DAISY_CHAIN_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ case DB_88F6281A_BP_ID: ++ *connMode = DUAL_CHIP_SELECT_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ case RD_88F6192A_ID: ++ *connMode = DUAL_CHIP_SELECT_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ case DB_88F6192A_BP_ID: ++ *connMode = DUAL_CHIP_SELECT_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ default: ++ *connMode = *irqMode = -1; ++ mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet()); ++ } ++ return; ++ ++} ++ ++/******************************************************************************* ++* mvBoardMppModuleTypePrint - print module detect ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppModuleTypePrint(MV_VOID) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U32 maxMppGrp = 1; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ mppGroupType = mvBoardMppGroupTypeGet(devClass); ++ ++ switch(mppGroupType) ++ { ++ case MV_BOARD_TDM: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is TDM\n", devClass); ++ break; ++ case MV_BOARD_AUDIO: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is AUDIO\n", devClass); ++ break; ++ case MV_BOARD_RGMII: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is RGMII\n", devClass); ++ break; ++ case MV_BOARD_GMII: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is GMII\n", devClass); ++ break; ++ case MV_BOARD_TS: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is TS\n", devClass); ++ break; ++ default: ++ break; ++ } ++ } ++} ++ ++/* Board devices API managments */ ++ ++/******************************************************************************* ++* mvBoardGetDeviceNumber - Get number of device of some type on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* number of those devices else the function returns 0 ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_U32 foundIndex=0,devNum; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); ++ return 0xFFFFFFFF; ++ ++ } ++ ++ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) ++ { ++ if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) ++ { ++ foundIndex++; ++ } ++ } ++ ++ return foundIndex; ++ ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* Base address else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ { ++ return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); ++ ++ } ++ ++ return 0xFFFFFFFF; ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* Bus width else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ { ++ return 8; ++ } ++ ++ return 0xFFFFFFFF; ++ ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceWidth - Get dev width of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* dev width else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("Board unknown.\n"); ++ return 0xFFFFFFFF; ++ } ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ return devEntry->devWidth; ++ ++ return MV_ERROR; ++ ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* window size else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("Board unknown.\n"); ++ return 0xFFFFFFFF; ++ } ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ { ++ return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); ++ } ++ ++ return 0xFFFFFFFF; ++} ++ ++ ++/******************************************************************************* ++* boardGetDevEntry - returns the entry pointer of a device on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* dev number else the function returns 0x0 ++* ++* ++*******************************************************************************/ ++static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_U32 foundIndex=0,devIndex; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("boardGetDevEntry: Board unknown.\n"); ++ return NULL; ++ ++ } ++ ++ for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) ++ { ++ /* TBR */ ++ /*if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX) ++ continue;*/ ++ ++ if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) ++ { ++ if (foundIndex == devNum) ++ { ++ return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); ++ } ++ foundIndex++; ++ } ++ } ++ ++ /* device not found */ ++ return NULL; ++} ++ ++/* Get device CS number */ ++ ++MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("Board unknown.\n"); ++ return 0xFFFFFFFF; ++ ++ } ++ ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ return devEntry->deviceCS; ++ ++ return 0xFFFFFFFF; ++ ++} ++ ++/******************************************************************************* ++* mvBoardRtcTwsiAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardRtcTwsiAddrTypeGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardRtcTwsiAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardRtcTwsiAddrGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ return (0xFF); ++} ++ ++/******************************************************************************* ++* mvBoardA2DTwsiAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardA2DTwsiAddrTypeGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardA2DTwsiAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardA2DTwsiAddrGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ return (0xFF); ++} ++ ++/******************************************************************************* ++* mvBoardTwsiExpAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ else ++ indexFound++; ++ } ++ ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardTwsiExpAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ else ++ indexFound++; ++ } ++ ++ return (0xFF); ++} ++ ++ ++/******************************************************************************* ++* mvBoardTwsiSatRAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ else ++ indexFound++; ++ } ++ ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardTwsiSatRAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ else ++ indexFound++; ++ } ++ ++ return (0xFF); ++} ++ ++/******************************************************************************* ++* mvBoardNandWidthGet - ++* ++* DESCRIPTION: Get the width of the first NAND device in byte. ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: 1, 2, 4 or MV_ERROR ++* ++* ++*******************************************************************************/ ++/* */ ++MV_32 mvBoardNandWidthGet(void) ++{ ++ MV_U32 devNum; ++ MV_U32 devWidth; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) ++ { ++ devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); ++ if (devWidth != MV_ERROR) ++ return (devWidth / 8); ++ } ++ ++ /* NAND wasn't found */ ++ return MV_ERROR; ++} ++ ++MV_U32 gBoardId = -1; ++ ++/******************************************************************************* ++* mvBoardIdGet - Get Board model ++* ++* DESCRIPTION: ++* This function returns board ID. ++* Board ID is 32bit word constructed of board model (16bit) and ++* board revision (16bit) in the following way: 0xMMMMRRRR. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit board ID number, '-1' if board is undefined. ++* ++*******************************************************************************/ ++MV_U32 mvBoardIdGet(MV_VOID) ++{ ++ MV_U32 tmpBoardId = -1; ++ ++ if(gBoardId == -1) ++ { ++ #if defined(DB_88F6281A) ++ tmpBoardId = DB_88F6281A_BP_ID; ++ #elif defined(RD_88F6281A) ++ tmpBoardId = RD_88F6281A_ID; ++ #elif defined(DB_88F6192A) ++ tmpBoardId = DB_88F6192A_BP_ID; ++ #elif defined(DB_88F6190A) ++ tmpBoardId = DB_88F6190A_BP_ID; ++ #elif defined(RD_88F6192A) ++ tmpBoardId = RD_88F6192A_ID; ++ #elif defined(RD_88F6190A) ++ tmpBoardId = RD_88F6190A_ID; ++ #elif defined(DB_88F6180A) ++ tmpBoardId = DB_88F6180A_BP_ID; ++ #elif defined(RD_88F6281A_PCAC) ++ tmpBoardId = RD_88F6281A_PCAC_ID; ++ #elif defined(RD_88F6281A_SHEEVA_PLUG) ++ tmpBoardId = SHEEVA_PLUG_ID; ++ #elif defined(DB_CUSTOMER) ++ tmpBoardId = DB_CUSTOMER_ID; ++ #endif ++ gBoardId = tmpBoardId; ++ } ++ ++ return gBoardId; ++} ++ ++ ++/******************************************************************************* ++* mvBoarModuleTypeGet - mvBoarModuleTypeGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group num - MV_BOARD_MPP_GROUP_CLASS enum ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* module num - MV_BOARD_MODULE_CLASS enum ++* ++*******************************************************************************/ ++MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass) ++{ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ MV_U8 data; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: Read MPP module ID\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); ++ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(devClass); ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ ++ ++ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) ++ { ++ DB(mvOsPrintf("Board: Read MPP module ID fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: Read MPP module ID succeded\n")); ++ ++ return data; ++} ++ ++/******************************************************************************* ++* mvBoarTwsiSatRGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* device num - one of three devices ++* reg num - 0 or 1 ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* reg value ++* ++*******************************************************************************/ ++MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) ++{ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ MV_U8 data; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: Read S@R device read\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); ++ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); ++ twsiSlave.validOffset = MV_TRUE; ++ /* Use offset as command */ ++ twsiSlave.offset = regNum; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) ++ { ++ DB(mvOsPrintf("Board: Read S@R fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: Read S@R succeded\n")); ++ ++ return data; ++} ++ ++/******************************************************************************* ++* mvBoarTwsiSatRSet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devNum - one of three devices ++* regNum - 0 or 1 ++* regVal - value ++* ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* reg value ++* ++*******************************************************************************/ ++MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) ++{ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); ++ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); ++ twsiSlave.validOffset = MV_TRUE; ++ DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", twsiSlave.slaveAddr.address,\ ++ twsiSlave.slaveAddr.type, regVal)); ++ /* Use offset as command */ ++ twsiSlave.offset = regNum; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, ®Val, 1) ) ++ { ++ DB(mvOsPrintf("Board: Write S@R fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: Write S@R succeded\n")); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardSlicGpioPinGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) ++{ ++ MV_U32 boardId; ++ boardId = mvBoardIdGet(); ++ ++ switch (boardId) ++ { ++ case DB_88F6281A_BP_ID: ++ case RD_88F6281A_ID: ++ default: ++ return MV_ERROR; ++ break; ++ ++ } ++} ++ ++/******************************************************************************* ++* mvBoardFanPowerControl - Turn on/off the fan power control on the RD-6281A ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mode - MV_TRUE = on ; MV_FALSE = off ++* ++* OUTPUT: ++* MV_STATUS - MV_OK , MV_ERROR. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvBoardFanPowerControl(MV_BOOL mode) ++{ ++ ++ MV_U8 val = 1, twsiVal; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ if(mvBoardIdGet() != RD_88F6281A_ID) ++ return MV_ERROR; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if(mode == MV_TRUE) ++ val = 0x1; ++ else ++ val = 0; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfe) | val; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfe); ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardHDDPowerControl - Turn on/off the HDD power control on the RD-6281A ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mode - MV_TRUE = on ; MV_FALSE = off ++* ++* OUTPUT: ++* MV_STATUS - MV_OK , MV_ERROR. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode) ++{ ++ ++ MV_U8 val = 1, twsiVal; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ if(mvBoardIdGet() != RD_88F6281A_ID) ++ return MV_ERROR; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if(mode == MV_TRUE) ++ val = 0x2; ++ else ++ val = 0; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfd) | val; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfd); ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardSDioWPControl - Turn on/off the SDIO WP on the RD-6281A ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mode - MV_TRUE = on ; MV_FALSE = off ++* ++* OUTPUT: ++* MV_STATUS - MV_OK , MV_ERROR. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvBoardSDioWPControl(MV_BOOL mode) ++{ ++ ++ MV_U8 val = 1, twsiVal; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ if(mvBoardIdGet() != RD_88F6281A_ID) ++ return MV_ERROR; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(0); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if(mode == MV_TRUE) ++ val = 0x10; ++ else ++ val = 0; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xef) | val; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xef); ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ return MV_OK; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,376 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCmvBoardEnvLibh ++#define __INCmvBoardEnvLibh ++ ++/* defines */ ++/* The below constant macros defines the board I2C EEPROM data offsets */ ++ ++ ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "mvSysHwConfig.h" ++#include "boardEnv/mvBoardEnvSpec.h" ++ ++ ++/* DUART stuff for Tclk detection only */ ++#define DUART_BAUD_RATE 115200 ++#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ ++ ++/* Voice devices assembly modes */ ++#define DAISY_CHAIN_MODE 1 ++#define DUAL_CHIP_SELECT_MODE 0 ++#define INTERRUPT_TO_MPP 1 ++#define INTERRUPT_TO_TDM 0 ++ ++ ++#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS ++#define BOARD_ETH_SWITCH_PORT_NUM 5 ++ ++#define MV_BOARD_MAX_USB_IF 1 ++#define MV_BOARD_MAX_MPP 7 ++#define MV_BOARD_NAME_LEN 0x20 ++ ++typedef struct _boardData ++{ ++ MV_U32 magic; ++ MV_U16 boardId; ++ MV_U8 boardVer; ++ MV_U8 boardRev; ++ MV_U32 reserved1; ++ MV_U32 reserved2; ++ ++}BOARD_DATA; ++ ++typedef enum _devBoardMppGroupClass ++{ ++ MV_BOARD_MPP_GROUP_1, ++ MV_BOARD_MPP_GROUP_2, ++ MV_BOARD_MAX_MPP_GROUP ++}MV_BOARD_MPP_GROUP_CLASS; ++ ++typedef enum _devBoardMppTypeClass ++{ ++ MV_BOARD_AUTO, ++ MV_BOARD_TDM, ++ MV_BOARD_AUDIO, ++ MV_BOARD_RGMII, ++ MV_BOARD_GMII, ++ MV_BOARD_TS, ++ MV_BOARD_MII, ++ MV_BOARD_OTHER ++}MV_BOARD_MPP_TYPE_CLASS; ++ ++typedef enum _devBoardModuleIdClass ++{ ++ MV_BOARD_MODULE_TDM_ID = 1, ++ MV_BOARD_MODULE_AUDIO_ID, ++ MV_BOARD_MODULE_RGMII_ID, ++ MV_BOARD_MODULE_GMII_ID, ++ MV_BOARD_MODULE_TS_ID, ++ MV_BOARD_MODULE_MII_ID, ++ MV_BOARD_MODULE_TDM_5CHAN_ID, ++ MV_BOARD_MODULE_OTHER_ID ++}MV_BOARD_MODULE_ID_CLASS; ++ ++typedef struct _boardMppTypeInfo ++{ ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup1; ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2; ++ ++}MV_BOARD_MPP_TYPE_INFO; ++ ++ ++typedef enum _devBoardClass ++{ ++ BOARD_DEV_NOR_FLASH, ++ BOARD_DEV_NAND_FLASH, ++ BOARD_DEV_SEVEN_SEG, ++ BOARD_DEV_FPGA, ++ BOARD_DEV_SRAM, ++ BOARD_DEV_SPI_FLASH, ++ BOARD_DEV_OTHER, ++}MV_BOARD_DEV_CLASS; ++ ++typedef enum _devTwsiBoardClass ++{ ++ BOARD_TWSI_RTC, ++ BOARD_DEV_TWSI_EXP, ++ BOARD_DEV_TWSI_SATR, ++ BOARD_TWSI_AUDIO_DEC, ++ BOARD_TWSI_OTHER ++}MV_BOARD_TWSI_CLASS; ++ ++typedef enum _devGppBoardClass ++{ ++ BOARD_GPP_RTC, ++ BOARD_GPP_MV_SWITCH, ++ BOARD_GPP_USB_VBUS, ++ BOARD_GPP_USB_VBUS_EN, ++ BOARD_GPP_USB_OC, ++ BOARD_GPP_USB_HOST_DEVICE, ++ BOARD_GPP_REF_CLCK, ++ BOARD_GPP_VOIP_SLIC, ++ BOARD_GPP_LIFELINE, ++ BOARD_GPP_BUTTON, ++ BOARD_GPP_TS_BUTTON_C, ++ BOARD_GPP_TS_BUTTON_U, ++ BOARD_GPP_TS_BUTTON_D, ++ BOARD_GPP_TS_BUTTON_L, ++ BOARD_GPP_TS_BUTTON_R, ++ BOARD_GPP_POWER_BUTTON, ++ BOARD_GPP_RESTOR_BUTTON, ++ BOARD_GPP_WPS_BUTTON, ++ BOARD_GPP_HDD0_POWER, ++ BOARD_GPP_HDD1_POWER, ++ BOARD_GPP_FAN_POWER, ++ BOARD_GPP_RESET, ++ BOARD_GPP_POWER_ON_LED, ++ BOARD_GPP_HDD_POWER, ++ BOARD_GPP_SDIO_POWER, ++ BOARD_GPP_SDIO_DETECT, ++ BOARD_GPP_SDIO_WP, ++ BOARD_GPP_SWITCH_PHY_INT, ++ BOARD_GPP_TSU_DIRCTION, ++ BOARD_GPP_OTHER ++}MV_BOARD_GPP_CLASS; ++ ++ ++typedef struct _devCsInfo ++{ ++ MV_U8 deviceCS; ++ MV_U32 params; ++ MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ ++ MV_U8 devWidth; ++ ++}MV_DEV_CS_INFO; ++ ++ ++#define MV_BOARD_PHY_FORCE_10MB 0x0 ++#define MV_BOARD_PHY_FORCE_100MB 0x1 ++#define MV_BOARD_PHY_FORCE_1000MB 0x2 ++#define MV_BOARD_PHY_SPEED_AUTO 0x3 ++ ++typedef struct _boardSwitchInfo ++{ ++ MV_32 linkStatusIrq; ++ MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM]; ++ MV_32 qdCpuPort; ++ MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */ ++ MV_32 switchOnPort; ++ ++}MV_BOARD_SWITCH_INFO; ++ ++typedef struct _boardLedInfo ++{ ++ MV_U8 activeLedsNumber; ++ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ ++ MV_U8* gppPinNum; /* Pointer to GPP values */ ++ ++}MV_BOARD_LED_INFO; ++ ++typedef struct _boardGppInfo ++{ ++ MV_BOARD_GPP_CLASS devClass; ++ MV_U8 gppPinNum; ++ ++}MV_BOARD_GPP_INFO; ++ ++ ++typedef struct _boardTwsiInfo ++{ ++ MV_BOARD_TWSI_CLASS devClass; ++ MV_U8 twsiDevAddr; ++ MV_U8 twsiDevAddrType; ++ ++}MV_BOARD_TWSI_INFO; ++ ++ ++typedef enum _boardMacSpeed ++{ ++ BOARD_MAC_SPEED_10M, ++ BOARD_MAC_SPEED_100M, ++ BOARD_MAC_SPEED_1000M, ++ BOARD_MAC_SPEED_AUTO, ++ ++}MV_BOARD_MAC_SPEED; ++ ++typedef struct _boardMacInfo ++{ ++ MV_BOARD_MAC_SPEED boardMacSpeed; ++ MV_U8 boardEthSmiAddr; ++ ++}MV_BOARD_MAC_INFO; ++ ++typedef struct _boardMppInfo ++{ ++ MV_U32 mppGroup[MV_BOARD_MAX_MPP]; ++ ++}MV_BOARD_MPP_INFO; ++ ++typedef struct _boardInfo ++{ ++ char boardName[MV_BOARD_NAME_LEN]; ++ MV_U8 numBoardMppTypeValue; ++ MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue; ++ MV_U8 numBoardMppConfigValue; ++ MV_BOARD_MPP_INFO* pBoardMppConfigValue; ++ MV_U32 intsGppMaskLow; ++ MV_U32 intsGppMaskHigh; ++ MV_U8 numBoardDeviceIf; ++ MV_DEV_CS_INFO* pDevCsInfo; ++ MV_U8 numBoardTwsiDev; ++ MV_BOARD_TWSI_INFO* pBoardTwsiDev; ++ MV_U8 numBoardMacInfo; ++ MV_BOARD_MAC_INFO* pBoardMacInfo; ++ MV_U8 numBoardGppInfo; ++ MV_BOARD_GPP_INFO* pBoardGppInfo; ++ MV_U8 activeLedsNumber; ++ MV_U8* pLedGppPin; ++ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ ++ /* GPP values */ ++ MV_U32 gppOutEnValLow; ++ MV_U32 gppOutEnValHigh; ++ MV_U32 gppOutValLow; ++ MV_U32 gppOutValHigh; ++ MV_U32 gppPolarityValLow; ++ MV_U32 gppPolarityValHigh; ++ ++ /* Switch Configuration */ ++ MV_BOARD_SWITCH_INFO* pSwitchInfo; ++}MV_BOARD_INFO; ++ ++ ++ ++MV_VOID mvBoardEnvInit(MV_VOID); ++MV_U32 mvBoardIdGet(MV_VOID); ++MV_U16 mvBoardModelGet(MV_VOID); ++MV_U16 mvBoardRevGet(MV_VOID); ++MV_STATUS mvBoardNameGet(char *pNameBuff); ++MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); ++MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); ++MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum); ++MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum); ++MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum); ++MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum); ++MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum); ++MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); ++MV_BOOL mvBoardIsPortInGmii(MV_VOID); ++MV_U32 mvBoardTclkGet(MV_VOID); ++MV_U32 mvBoardSysClkGet(MV_VOID); ++MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); ++MV_VOID mvBoardDebugLed(MV_U32 hexNum); ++MV_32 mvBoardMppGet(MV_U32 mppGroupNum); ++ ++MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); ++MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); ++ ++MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID); ++MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID); ++ ++MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index); ++MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index); ++MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index); ++MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index); ++MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass); ++MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass); ++MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType); ++MV_VOID mvBoardMppGroupIdUpdate(MV_VOID); ++MV_VOID mvBoardMppMuxSet(MV_VOID); ++MV_VOID mvBoardTdmMppSet(MV_32 chType); ++MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode); ++ ++MV_VOID mvBoardMppModuleTypePrint(MV_VOID); ++MV_VOID mvBoardReset(MV_VOID); ++MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); ++MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); ++MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); ++/* Board devices API managments */ ++MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++ ++/* Gpio Pin Connections API */ ++MV_32 mvBoardUSBVbusGpioPinGet(int devId); ++MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); ++MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin); ++ ++MV_32 mvBoardResetGpioPinGet(MV_VOID); ++MV_32 mvBoardRTCGpioPinGet(MV_VOID); ++MV_32 mvBoardGpioIntMaskLowGet(MV_VOID); ++MV_32 mvBoardGpioIntMaskHighGet(MV_VOID); ++MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); ++ ++MV_32 mvBoardSDIOGpioPinGet(MV_VOID); ++MV_STATUS mvBoardSDioWPControl(MV_BOOL mode); ++MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); ++ ++MV_32 mvBoardNandWidthGet(void); ++MV_STATUS mvBoardFanPowerControl(MV_BOOL mode); ++MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode); ++#endif /* __INCmvBoardEnvLibh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,848 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "mvCommon.h" ++#include "mvBoardEnvLib.h" ++#include "mvBoardEnvSpec.h" ++#include "twsi/mvTwsi.h" ++ ++#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0 ++#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7 ++#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2 ++#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3 ++#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 ++#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0 ++ ++ ++MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, ++ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ { ++ {BOARD_MAC_SPEED_AUTO, 0x8}, ++ {BOARD_MAC_SPEED_AUTO, 0x9} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_AUTO, MV_BOARD_AUTO} ++ }; ++ ++MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ {BOARD_GPP_TSU_DIRCTION, 33} ++ /*muxed with TDM/Audio module via IOexpender ++ {BOARD_GPP_SDIO_DETECT, 38}, ++ {BOARD_GPP_USB_VBUS, 49}*/ ++ }; ++ ++MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] = ++ {{{ ++ DB_88F6281A_MPP0_7, ++ DB_88F6281A_MPP8_15, ++ DB_88F6281A_MPP16_23, ++ DB_88F6281A_MPP24_31, ++ DB_88F6281A_MPP32_39, ++ DB_88F6281A_MPP40_47, ++ DB_88F6281A_MPP48_55 ++ }}}; ++ ++ ++MV_BOARD_INFO db88f6281AInfo = { ++ "DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6281AInfoBoardMppTypeInfo, ++ DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6281AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6281AInfoBoardDeCsInfo, ++ DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6281AInfoBoardTwsiDev, ++ DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6281AInfoBoardMacInfo, ++ DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ db88f6281AInfoBoardGppInfo, ++ DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6281A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6281A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ BIT6, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++ ++#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0 ++#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2 ++#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2 ++#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5 ++#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_1000M, 0xa}, ++ {BOARD_MAC_SPEED_AUTO, 0xb} ++ }; ++ ++MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] = ++ /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, ++ MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */ ++ {{38, {0, 1, 2, 3, -1}, 5, 2, 0}, ++ {-1, {-1}, -1, -1, -1}}; ++ ++MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */ ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_RGMII, MV_BOARD_TDM} ++ }; ++ ++MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ {{BOARD_GPP_SDIO_DETECT, 28}, ++ {BOARD_GPP_USB_OC, 29}, ++ {BOARD_GPP_WPS_BUTTON, 35}, ++ {BOARD_GPP_MV_SWITCH, 38}, ++ {BOARD_GPP_USB_VBUS, 49} ++ }; ++ ++MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] = ++ {{{ ++ RD_88F6281A_MPP0_7, ++ RD_88F6281A_MPP8_15, ++ RD_88F6281A_MPP16_23, ++ RD_88F6281A_MPP24_31, ++ RD_88F6281A_MPP32_39, ++ RD_88F6281A_MPP40_47, ++ RD_88F6281A_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO rd88f6281AInfo = { ++ "RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6281AInfoBoardMppTypeInfo, ++ RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6281AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6281AInfoBoardDeCsInfo, ++ RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ rd88f6281AInfoBoardTwsiDev, ++ RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6281AInfoBoardMacInfo, ++ RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ rd88f6281AInfoBoardGppInfo, ++ RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ RD_88F6281A_OE_LOW, /* gppOutEnLow */ ++ RD_88F6281A_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ BIT6, /* gppPolarityValHigh */ ++ rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */ ++}; ++ ++ ++#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0 ++#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7 ++#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2 ++#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3 ++#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, ++ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ { ++ {BOARD_MAC_SPEED_AUTO, 0x8}, ++ {BOARD_MAC_SPEED_AUTO, 0x9} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_AUTO, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ {BOARD_GPP_SDIO_WP, 20}, ++ {BOARD_GPP_USB_VBUS, 22}, ++ {BOARD_GPP_SDIO_DETECT, 23}, ++ }; ++ ++MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] = ++ {{{ ++ DB_88F6192A_MPP0_7, ++ DB_88F6192A_MPP8_15, ++ DB_88F6192A_MPP16_23, ++ DB_88F6192A_MPP24_31, ++ DB_88F6192A_MPP32_35 ++ }}}; ++ ++MV_BOARD_INFO db88f6192AInfo = { ++ "DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6192AInfoBoardMppTypeInfo, ++ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6192AInfoBoardDeCsInfo, ++ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6192AInfoBoardTwsiDev, ++ DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6192AInfoBoardMacInfo, ++ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ db88f6192AInfoBoardGppInfo, ++ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6192A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1 ++ ++MV_BOARD_INFO db88f6190AInfo = { ++ "DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6192AInfoBoardMppTypeInfo, ++ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6192AInfoBoardDeCsInfo, ++ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6192AInfoBoardTwsiDev, ++ DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6192AInfoBoardMacInfo, ++ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ db88f6192AInfoBoardGppInfo, ++ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6192A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0 ++#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0 ++#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1 ++#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE ++#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 ++#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3 ++ ++MV_U8 rd88f6192AInfoBoardDebugLedIf[] = ++ {17, 28, 29}; ++ ++MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x8} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++ ++MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ {BOARD_GPP_USB_VBUS_EN, 10}, ++ {BOARD_GPP_USB_HOST_DEVICE, 11}, ++ {BOARD_GPP_RESET, 14}, ++ {BOARD_GPP_POWER_ON_LED, 15}, ++ {BOARD_GPP_HDD_POWER, 16}, ++ {BOARD_GPP_WPS_BUTTON, 24}, ++ {BOARD_GPP_TS_BUTTON_C, 25}, ++ {BOARD_GPP_USB_VBUS, 26}, ++ {BOARD_GPP_USB_OC, 27}, ++ {BOARD_GPP_TS_BUTTON_U, 30}, ++ {BOARD_GPP_TS_BUTTON_R, 31}, ++ {BOARD_GPP_TS_BUTTON_L, 32}, ++ {BOARD_GPP_TS_BUTTON_D, 34}, ++ {BOARD_GPP_FAN_POWER, 35} ++ }; ++ ++MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] = ++ {{{ ++ RD_88F6192A_MPP0_7, ++ RD_88F6192A_MPP8_15, ++ RD_88F6192A_MPP16_23, ++ RD_88F6192A_MPP24_31, ++ RD_88F6192A_MPP32_35 ++ }}}; ++ ++MV_BOARD_INFO rd88f6192AInfo = { ++ "RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6192AInfoBoardMppTypeInfo, ++ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6192AInfoBoardDeCsInfo, ++ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ NULL, ++ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6192AInfoBoardMacInfo, ++ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ rd88f6192AInfoBoardGppInfo, ++ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ rd88f6192AInfoBoardDebugLedIf, ++ 0, /* ledsPolarity */ ++ RD_88F6192A_OE_LOW, /* gppOutEnLow */ ++ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++MV_BOARD_INFO rd88f6190AInfo = { ++ "RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6192AInfoBoardMppTypeInfo, ++ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6192AInfoBoardDeCsInfo, ++ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ NULL, ++ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6192AInfoBoardMacInfo, ++ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ rd88f6192AInfoBoardGppInfo, ++ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ rd88f6192AInfoBoardDebugLedIf, ++ 0, /* ledsPolarity */ ++ RD_88F6192A_OE_LOW, /* gppOutEnLow */ ++ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0 ++#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5 ++#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1 ++#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0 ++#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2 ++#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1 ++#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, ++ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x8} ++ }; ++ ++MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ /* Muxed with TDM/Audio module via IOexpender ++ {BOARD_GPP_USB_VBUS, 6} */ ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_OTHER, MV_BOARD_AUTO} ++ }; ++ ++MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] = ++ {{{ ++ DB_88F6180A_MPP0_7, ++ DB_88F6180A_MPP8_15, ++ DB_88F6180A_MPP16_23, ++ DB_88F6180A_MPP24_31, ++ DB_88F6180A_MPP32_39, ++ DB_88F6180A_MPP40_44 ++ }}}; ++ ++MV_BOARD_INFO db88f6180AInfo = { ++ "DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6180AInfoBoardMppTypeInfo, ++ DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6180AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6180AInfoBoardDeCsInfo, ++ DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6180AInfoBoardTwsiDev, ++ DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6180AInfoBoardMacInfo, ++ DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ NULL, ++ DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6180A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6180A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++ ++#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0 ++#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1 ++#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1 ++#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0 ++#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4 ++ ++MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] = ++ {38, 39, 40, 41}; ++ ++MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x8} ++ }; ++ ++MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] = ++ {{{ ++ RD_88F6281A_PCAC_MPP0_7, ++ RD_88F6281A_PCAC_MPP8_15, ++ RD_88F6281A_PCAC_MPP16_23, ++ RD_88F6281A_PCAC_MPP24_31, ++ RD_88F6281A_PCAC_MPP32_39, ++ RD_88F6281A_PCAC_MPP40_47, ++ RD_88F6281A_PCAC_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO rd88f6281APcacInfo = { ++ "RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6281APcacInfoBoardMppTypeInfo, ++ RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6281APcacInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6281APcacInfoBoardDeCsInfo, ++ RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ rd88f6281APcacInfoBoardTwsiDev, ++ RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6281APcacInfoBoardMacInfo, ++ RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ 0, ++ RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */ ++ RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++ ++/* 6281 Sheeva Plug*/ ++ ++#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0 ++#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0 ++#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1 ++#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0 ++#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1 ++#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1 ++#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1 ++#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1 ++ ++MV_U8 sheevaPlugInfoBoardDebugLedIf[] = ++ {49}; ++ ++MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x0}}; ++ ++MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; ++ ++MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++ ++MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] = ++ {{{ ++ RD_SHEEVA_PLUG_MPP0_7, ++ RD_SHEEVA_PLUG_MPP8_15, ++ RD_SHEEVA_PLUG_MPP16_23, ++ RD_SHEEVA_PLUG_MPP24_31, ++ RD_SHEEVA_PLUG_MPP32_39, ++ RD_SHEEVA_PLUG_MPP40_47, ++ RD_SHEEVA_PLUG_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO sheevaPlugInfo = { ++ "SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */ ++ SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ ++ sheevaPlugInfoBoardMppTypeInfo, ++ SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ sheevaPlugInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ sheevaPlugInfoBoardDeCsInfo, ++ SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ sheevaPlugInfoBoardTwsiDev, ++ SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ sheevaPlugInfoBoardMacInfo, ++ SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ 0, ++ SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ sheevaPlugInfoBoardDebugLedIf, ++ 0, /* ledsPolarity */ ++ RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */ ++ RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */ ++ RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */ ++ RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++/* Customer specific board place holder*/ ++ ++#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0 ++#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0 ++#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0 ++#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0 ++#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0 ++#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 ++#else ++ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 ++#endif ++#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_U8 dbCustomerInfoBoardDebugLedIf[] = ++ {0}; ++ ++MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x0}}; ++ ++MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; ++ ++MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] = ++ {{{ ++ DB_CUSTOMER_MPP0_7, ++ DB_CUSTOMER_MPP8_15, ++ DB_CUSTOMER_MPP16_23, ++ DB_CUSTOMER_MPP24_31, ++ DB_CUSTOMER_MPP32_39, ++ DB_CUSTOMER_MPP40_47, ++ DB_CUSTOMER_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO dbCustomerInfo = { ++ "DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ ++ dbCustomerInfoBoardMppTypeInfo, ++ DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ dbCustomerInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ dbCustomerInfoBoardDeCsInfo, ++ DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ dbCustomerInfoBoardTwsiDev, ++ DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ dbCustomerInfoBoardMacInfo, ++ DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ 0, ++ DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_CUSTOMER_OE_LOW, /* gppOutEnLow */ ++ DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */ ++ DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */ ++ DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++MV_BOARD_INFO* boardInfoTbl[] = { ++ &db88f6281AInfo, ++ &rd88f6281AInfo, ++ &db88f6192AInfo, ++ &rd88f6192AInfo, ++ &db88f6180AInfo, ++ &db88f6190AInfo, ++ &rd88f6190AInfo, ++ &rd88f6281APcacInfo, ++ &dbCustomerInfo, ++ &sheevaPlugInfo ++ }; ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,262 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvBoardEnvSpech ++#define __INCmvBoardEnvSpech ++ ++#include "mvSysHwConfig.h" ++ ++ ++/* For future use */ ++#define BD_ID_DATA_START_OFFS 0x0 ++#define BD_DETECT_SEQ_OFFS 0x0 ++#define BD_SYS_NUM_OFFS 0x4 ++#define BD_NAME_OFFS 0x8 ++ ++/* I2C bus addresses */ ++#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ ++#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_DIMM0_I2C_ADDR 0x56 ++#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_DIMM1_I2C_ADDR 0x54 ++#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_EEPROM_I2C_ADDR 0x51 ++#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50 ++#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2 ++#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 ++ ++#define BOOT_FLASH_INDEX 0 ++#define MAIN_FLASH_INDEX 1 ++ ++#define BOARD_ETH_START_PORT_NUM 0 ++ ++/* Supported clocks */ ++#define MV_BOARD_TCLK_100MHZ 100000000 ++#define MV_BOARD_TCLK_125MHZ 125000000 ++#define MV_BOARD_TCLK_133MHZ 133333333 ++#define MV_BOARD_TCLK_150MHZ 150000000 ++#define MV_BOARD_TCLK_166MHZ 166666667 ++#define MV_BOARD_TCLK_200MHZ 200000000 ++ ++#define MV_BOARD_SYSCLK_100MHZ 100000000 ++#define MV_BOARD_SYSCLK_125MHZ 125000000 ++#define MV_BOARD_SYSCLK_133MHZ 133333333 ++#define MV_BOARD_SYSCLK_150MHZ 150000000 ++#define MV_BOARD_SYSCLK_166MHZ 166666667 ++#define MV_BOARD_SYSCLK_200MHZ 200000000 ++#define MV_BOARD_SYSCLK_233MHZ 233333333 ++#define MV_BOARD_SYSCLK_250MHZ 250000000 ++#define MV_BOARD_SYSCLK_267MHZ 266666667 ++#define MV_BOARD_SYSCLK_300MHZ 300000000 ++#define MV_BOARD_SYSCLK_333MHZ 333333334 ++#define MV_BOARD_SYSCLK_400MHZ 400000000 ++ ++#define MV_BOARD_REFCLK_25MHZ 25000000 ++ ++/* Board specific */ ++/* =============================== */ ++ ++/* boards ID numbers */ ++ ++#define BOARD_ID_BASE 0x0 ++ ++/* New board ID numbers */ ++#define DB_88F6281A_BP_ID (BOARD_ID_BASE) ++#define DB_88F6281_BP_MLL_ID 1680 ++#define RD_88F6281A_ID (BOARD_ID_BASE+0x1) ++#define RD_88F6281_MLL_ID 1682 ++#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2) ++#define RD_88F6192A_ID (BOARD_ID_BASE+0x3) ++#define RD_88F6192_MLL_ID 1681 ++#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4) ++#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5) ++#define RD_88F6190A_ID (BOARD_ID_BASE+0x6) ++#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7) ++#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8) ++#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9) ++#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1) ++ ++/* DB-88F6281A-BP */ ++#if defined(MV_NAND) ++ #define DB_88F6281A_MPP0_7 0x21111111 ++#else ++ #define DB_88F6281A_MPP0_7 0x21112220 ++#endif ++#define DB_88F6281A_MPP8_15 0x11113311 ++#define DB_88F6281A_MPP16_23 0x00551111 ++#define DB_88F6281A_MPP24_31 0x00000000 ++#define DB_88F6281A_MPP32_39 0x00000000 ++#define DB_88F6281A_MPP40_47 0x00000000 ++#define DB_88F6281A_MPP48_55 0x00000000 ++#define DB_88F6281A_OE_LOW 0x0 ++#if defined(MV_TDM_5CHANNELS) ++ #define DB_88F6281A_OE_HIGH (BIT6) ++#else ++#define DB_88F6281A_OE_HIGH 0x0 ++#endif ++#define DB_88F6281A_OE_VAL_LOW 0x0 ++#define DB_88F6281A_OE_VAL_HIGH 0x0 ++ ++/* RD-88F6281A */ ++#if defined(MV_NAND) ++ #define RD_88F6281A_MPP0_7 0x21111111 ++#else ++ #define RD_88F6281A_MPP0_7 0x21112220 ++#endif ++#define RD_88F6281A_MPP8_15 0x11113311 ++#define RD_88F6281A_MPP16_23 0x33331111 ++#define RD_88F6281A_MPP24_31 0x33003333 ++#define RD_88F6281A_MPP32_39 0x20440533 ++#define RD_88F6281A_MPP40_47 0x22202222 ++#define RD_88F6281A_MPP48_55 0x00000002 ++#define RD_88F6281A_OE_LOW (BIT28 | BIT29) ++#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17) ++#define RD_88F6281A_OE_VAL_LOW 0x0 ++#define RD_88F6281A_OE_VAL_HIGH 0x0 ++ ++/* DB-88F6192A-BP */ ++#if defined(MV_NAND) ++ #define DB_88F6192A_MPP0_7 0x21111111 ++#else ++ #define DB_88F6192A_MPP0_7 0x21112220 ++#endif ++#define DB_88F6192A_MPP8_15 0x11113311 ++#define DB_88F6192A_MPP16_23 0x00501111 ++#define DB_88F6192A_MPP24_31 0x00000000 ++#define DB_88F6192A_MPP32_35 0x00000000 ++#define DB_88F6192A_OE_LOW (BIT22 | BIT23) ++#define DB_88F6192A_OE_HIGH 0x0 ++#define DB_88F6192A_OE_VAL_LOW 0x0 ++#define DB_88F6192A_OE_VAL_HIGH 0x0 ++ ++/* RD-88F6192A */ ++#define RD_88F6192A_MPP0_7 0x01222222 ++#define RD_88F6192A_MPP8_15 0x00000011 ++#define RD_88F6192A_MPP16_23 0x05550000 ++#define RD_88F6192A_MPP24_31 0x0 ++#define RD_88F6192A_MPP32_35 0x0 ++#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31) ++#define RD_88F6192A_OE_HIGH (BIT0 | BIT2) ++#define RD_88F6192A_OE_VAL_LOW 0x18400 ++#define RD_88F6192A_OE_VAL_HIGH 0x8 ++ ++/* DB-88F6180A-BP */ ++#if defined(MV_NAND) ++ #define DB_88F6180A_MPP0_7 0x21111111 ++#else ++ #define DB_88F6180A_MPP0_7 0x01112222 ++#endif ++#define DB_88F6180A_MPP8_15 0x11113311 ++#define DB_88F6180A_MPP16_23 0x00001111 ++#define DB_88F6180A_MPP24_31 0x0 ++#define DB_88F6180A_MPP32_39 0x4444c000 ++#define DB_88F6180A_MPP40_44 0x00044444 ++#define DB_88F6180A_OE_LOW 0x0 ++#define DB_88F6180A_OE_HIGH 0x0 ++#define DB_88F6180A_OE_VAL_LOW 0x0 ++#define DB_88F6180A_OE_VAL_HIGH 0x0 ++ ++/* RD-88F6281A_PCAC */ ++#define RD_88F6281A_PCAC_MPP0_7 0x21111111 ++#define RD_88F6281A_PCAC_MPP8_15 0x00003311 ++#define RD_88F6281A_PCAC_MPP16_23 0x00001100 ++#define RD_88F6281A_PCAC_MPP24_31 0x00000000 ++#define RD_88F6281A_PCAC_MPP32_39 0x00000000 ++#define RD_88F6281A_PCAC_MPP40_47 0x00000000 ++#define RD_88F6281A_PCAC_MPP48_55 0x00000000 ++#define RD_88F6281A_PCAC_OE_LOW 0x0 ++#define RD_88F6281A_PCAC_OE_HIGH 0x0 ++#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0 ++#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0 ++ ++/* SHEEVA PLUG */ ++#define RD_SHEEVA_PLUG_MPP0_7 0x01111111 ++#define RD_SHEEVA_PLUG_MPP8_15 0x11113322 ++#define RD_SHEEVA_PLUG_MPP16_23 0x00001111 ++#define RD_SHEEVA_PLUG_MPP24_31 0x00100000 ++#define RD_SHEEVA_PLUG_MPP32_39 0x00000000 ++#define RD_SHEEVA_PLUG_MPP40_47 0x00000000 ++#define RD_SHEEVA_PLUG_MPP48_55 0x00000000 ++#define RD_SHEEVA_PLUG_OE_LOW 0x0 ++#define RD_SHEEVA_PLUG_OE_HIGH 0x0 ++#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29) ++#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14) ++ ++/* DB-CUSTOMER */ ++#define DB_CUSTOMER_MPP0_7 0x21111111 ++#define DB_CUSTOMER_MPP8_15 0x00003311 ++#define DB_CUSTOMER_MPP16_23 0x00001100 ++#define DB_CUSTOMER_MPP24_31 0x00000000 ++#define DB_CUSTOMER_MPP32_39 0x00000000 ++#define DB_CUSTOMER_MPP40_47 0x00000000 ++#define DB_CUSTOMER_MPP48_55 0x00000000 ++#define DB_CUSTOMER_OE_LOW 0x0 ++#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9))) ++#define DB_CUSTOMER_OE_VAL_LOW 0x0 ++#define DB_CUSTOMER_OE_VAL_HIGH 0x0 ++ ++#endif /* __INCmvBoardEnvSpech */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,320 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "cpu/mvCpu.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvRegs.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* locals */ ++ ++/******************************************************************************* ++* mvCpuPclkGet - Get the CPU pClk (pipe clock) ++* ++* DESCRIPTION: ++* This routine extract the CPU core clock. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit clock cycles in MHertz. ++* ++*******************************************************************************/ ++/* 6180 have different clk reset sampling */ ++ ++static MV_U32 mvCpu6180PclkGet(MV_VOID) ++{ ++ MV_U32 tmpPClkRate=0; ++ MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; ++ ++ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180; ++ tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180; ++ ++ tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk; ++ ++ return tmpPClkRate; ++} ++ ++ ++MV_U32 mvCpuPclkGet(MV_VOID) ++{ ++#if defined(PCLCK_AUTO_DETECT) ++ MV_U32 tmpPClkRate=0; ++ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; ++ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return mvCpu6180PclkGet(); ++ ++ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate); ++ tmpPClkRate = cpuCLK[tmpPClkRate]; ++ ++ return tmpPClkRate; ++#else ++ return MV_DEFAULT_PCLK ++#endif ++} ++ ++/******************************************************************************* ++* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) ++* ++* DESCRIPTION: ++* This routine extract the CPU L2 clock. ++* ++* RETURN: ++* 32bit clock cycles in Hertz. ++* ++*******************************************************************************/ ++static MV_U32 mvCpu6180L2ClkGet(MV_VOID) ++{ ++ MV_U32 L2ClkRate=0; ++ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; ++ ++ L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180; ++ L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180; ++ ++ L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk; ++ ++ return L2ClkRate; ++ ++} ++ ++MV_U32 mvCpuL2ClkGet(MV_VOID) ++{ ++#ifdef L2CLK_AUTO_DETECT ++ MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio; ++ MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL; ++ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return mvCpu6180L2ClkGet(); ++ ++ pClkRate = mvCpuPclkGet(); ++ ++ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp); ++ ++ L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]); ++ ++ return L2ClkRate; ++#else ++ return MV_BOARD_DEFAULT_L2CLK; ++#endif ++} ++ ++ ++/******************************************************************************* ++* mvCpuNameGet - Get CPU name ++* ++* DESCRIPTION: ++* This function returns a string describing the CPU model and revision. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. ++* ++* RETURN: ++* None. ++*******************************************************************************/ ++MV_VOID mvCpuNameGet(char *pNameBuff) ++{ ++ MV_U32 cpuModel; ++ ++ cpuModel = mvOsCpuPartGet(); ++ ++ /* The CPU module is indicated in the Processor Version Register (PVR) */ ++ switch(cpuModel) ++ { ++ case CPU_PART_MRVL131: ++ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet()); ++ break; ++ case CPU_PART_ARM926: ++ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); ++ break; ++ case CPU_PART_ARM946: ++ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); ++ break; ++ default: ++ mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); ++ break; ++ } /* switch */ ++ ++ return; ++} ++ ++ ++#define MV_PROC_STR_SIZE 50 ++ ++static void mvCpuIfGetL2EccMode(MV_8 *buf) ++{ ++ MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG); ++ if (regVal & BIT2) ++ mvOsSPrintf(buf, "L2 ECC Enabled"); ++ else ++ mvOsSPrintf(buf, "L2 ECC Disabled"); ++} ++ ++static void mvCpuIfGetL2Mode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT22) ++ mvOsSPrintf(buf, "L2 Enabled"); ++ else ++ mvOsSPrintf(buf, "L2 Disabled"); ++} ++ ++static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT24) ++ mvOsSPrintf(buf, "L2 Prefetch Disabled"); ++ else ++ mvOsSPrintf(buf, "L2 Prefetch Enabled"); ++} ++ ++static void mvCpuIfGetWriteAllocMode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT28) ++ mvOsSPrintf(buf, "Write Allocate Enabled"); ++ else ++ mvOsSPrintf(buf, "Write Allocate Disabled"); ++} ++ ++static void mvCpuIfGetCpuStreamMode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT29) ++ mvOsSPrintf(buf, "CPU Streaming Enabled"); ++ else ++ mvOsSPrintf(buf, "CPU Streaming Disabled"); ++} ++ ++static void mvCpuIfPrintCpuRegs(void) ++{ ++ MV_U32 regVal = 0; ++ ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); ++ ++ __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ ++ mvOsPrintf("Control Reg = 0x%x\n",regVal); ++ ++ __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ ++ mvOsPrintf("ID Code Reg = 0x%x\n",regVal); ++ ++ __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ ++ mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); ++ ++} ++ ++MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) ++{ ++ MV_U32 count = 0; ++ ++ MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; ++ MV_8 L2_En_str[MV_PROC_STR_SIZE]; ++ MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; ++ MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; ++ MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; ++ ++ mvCpuIfGetL2Mode(L2_En_str); ++ mvCpuIfGetL2EccMode(L2_ECC_str); ++ mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); ++ mvCpuIfGetWriteAllocMode(Write_Alloc_str); ++ mvCpuIfGetCpuStreamMode(Cpu_Stream_str); ++ mvCpuIfPrintCpuRegs(); ++ ++ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); ++ return count; ++} ++ ++MV_U32 whoAmI(MV_VOID) ++{ ++ return 0; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,99 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCpuh ++#define __INCmvCpuh ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++/* defines */ ++#define CPU_PART_MRVL131 0x131 ++#define CPU_PART_ARM926 0x926 ++#define CPU_PART_ARM946 0x946 ++#define MV_CPU_ARM_CLK_ELM_SIZE 12 ++#define MV_CPU_ARM_CLK_RATIO_OFF 8 ++#define MV_CPU_ARM_CLK_DDR_OFF 4 ++ ++#ifndef MV_ASMLANGUAGE ++typedef struct _mvCpuArmClk ++{ ++ MV_U32 cpuClk; /* CPU clock in MHz */ ++ MV_U32 ddrClk; /* DDR clock in MHz */ ++ MV_U32 l2Clk; /* CPU DDR clock ratio */ ++ ++}MV_CPU_ARM_CLK; ++ ++MV_U32 mvCpuPclkGet(MV_VOID); ++MV_VOID mvCpuNameGet(char *pNameBuff); ++MV_U32 mvCpuL2ClkGet(MV_VOID); ++MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); ++MV_U32 whoAmI(MV_VOID); ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#endif /* __INCmvCpuh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,296 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvCtrlEnvAddrDec.h - Marvell controller address decode library ++* ++* DESCRIPTION: ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++#include "ctrlEnv/sys/mvAhbToMbusRegs.h" ++#include "ddr2/mvDramIfRegs.h" ++#include "pex/mvPexRegs.h" ++ ++#define MV_DEBUG ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* Default Attributes array */ ++MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; ++extern MV_TARGET *sampleAtResetTargetArray; ++/* Dram\AHBToMbus\PEX share regsiter */ ++ ++#define CTRL_DEC_BASE_OFFS 16 ++#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) ++#define CTRL_DEC_BASE_ALIGNMENT 0x10000 ++ ++#define CTRL_DEC_SIZE_OFFS 16 ++#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) ++#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 ++ ++#define CTRL_DEC_WIN_EN BIT0 ++ ++ ++ ++/******************************************************************************* ++* mvCtrlAddrDecToReg - Get address decode register format values ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) ++{ ++ ++ MV_U32 baseToReg=0 , sizeToReg=0; ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; ++ pAddrDecRegs->baseReg |= baseToReg; ++ ++ /* Get size register value according to window size */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ return MV_BAD_PARAM; ++ } ++ ++ /* set size */ ++ pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; ++ pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); ++ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCtrlRegToAddrDec - Extract address decode struct from registers. ++* ++* DESCRIPTION: ++* This function extract address decode struct from address decode ++* registers given as parameters. ++* ++* INPUT: ++* pAddrDecRegs - Address decode register struct. ++* ++* OUTPUT: ++* pAddrDecWin - Target window data structure. ++* ++* RETURN: ++* MV_BAD_PARAM if address decode registers data is invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) ++{ ++ MV_U32 sizeRegVal; ++ ++ sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> ++ CTRL_DEC_SIZE_OFFS; ++ ++ pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ ++ /* Extract base address */ ++ /* Base register [31:16] ==> baseLow[31:16] */ ++ pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; ++ ++ pAddrDecWin->baseHigh = 0; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCtrlAttribGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++ ++MV_STATUS mvCtrlAttribGet(MV_TARGET target, ++ MV_TARGET_ATTRIB *targetAttrib) ++{ ++ ++ targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; ++ targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCtrlGetAttrib - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) ++{ ++ MV_TARGET target; ++ MV_TARGET x; ++ for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) ++ { ++ x = MV_CHANGE_BOOT_CS(target); ++ if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && ++ (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) ++ { ++ /* found it */ ++ break; ++ } ++ } ++ ++ return target; ++} ++ ++MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, ++ MV_DEC_WIN_PARAMS *pWinParam) ++{ ++ MV_U32 baseToReg=0, sizeToReg=0; ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK; ++ pWinParam->baseAddr |= baseToReg; ++ ++ /* Get size register value according to window size */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n"); ++ return MV_BAD_PARAM; ++ } ++ pWinParam->size = sizeToReg; ++ ++ pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib; ++ pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId; ++ ++ return MV_OK; ++} ++ ++MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, ++ MV_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; ++ ++ /* Upper 32bit address base is supported under PCI High Address remap */ ++ pAddrDecWin->addrWin.baseHigh = 0; ++ ++ /* Prepare sizeReg to ctrlRegToSize function */ ++ pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); ++ return MV_BAD_PARAM; ++ } ++ targetAttrib.targetId = pWinParam->targetId; ++ targetAttrib.attrib = pWinParam->attrib; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ return MV_OK; ++} ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,203 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCtrlEnvAddrDech ++#define __INCmvCtrlEnvAddrDech ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvRegs.h" ++ ++ ++/* defines */ ++/* DUnit attributes */ ++#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 ++#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 ++#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) ++ ++#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 ++#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 ++#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) ++ ++#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 ++#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 ++#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) ++ ++#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 ++#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 ++#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) ++ ++/* RUnit (Device) attributes */ ++#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 ++#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 ++#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) ++ ++#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 ++#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 ++#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) ++ ++#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 ++#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 ++#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) ++ ++#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 ++#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 ++#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) ++ ++/* LMaster (PCI) attributes */ ++#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 ++#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 ++#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) ++#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) ++ ++ ++#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 ++#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 ++#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) ++#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) ++ ++#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 ++ ++#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 ++#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 ++#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) ++#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) ++ ++#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 ++#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 ++#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) ++ ++#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 ++#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 ++#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) ++ ++/* PEX Attributes */ ++#define ATMWCR_WIN_PEX_TYPE_OFFS 3 ++#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 ++#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) ++#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) ++ ++/* typedefs */ ++ ++/* Unsupported attributes for address decode: */ ++/* 2) PCI0/1_REQ64n control */ ++ ++typedef struct _mvDecRegs ++{ ++ MV_U32 baseReg; ++ MV_U32 baseRegHigh; ++ MV_U32 sizeReg; ++ ++}MV_DEC_REGS; ++ ++typedef struct _mvTargetAttrib ++{ ++ MV_U8 attrib; /* chip select attributes */ ++ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ ++ ++}MV_TARGET_ATTRIB; ++ ++ ++/* This structure describes address decode window */ ++typedef struct _mvDecWin ++{ ++ MV_TARGET target; /* Target for addr decode window */ ++ MV_ADDR_WIN addrWin; /* Address window of target */ ++ MV_BOOL enable; /* Window enable/disable */ ++}MV_DEC_WIN; ++ ++typedef struct _mvDecWinParams ++{ ++ MV_TARGET_ID targetId; /* Target ID field */ ++ MV_U8 attrib; /* Attribute field */ ++ MV_U32 baseAddr; /* Base address in register format */ ++ MV_U32 size; /* Size in register format */ ++}MV_DEC_WIN_PARAMS; ++ ++ ++/* mvCtrlEnvAddrDec API list */ ++ ++MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, ++ MV_DEC_REGS *pAddrDecRegs); ++ ++MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, ++ MV_ADDR_WIN *pAddrDecWin); ++ ++MV_STATUS mvCtrlAttribGet(MV_TARGET target, ++ MV_TARGET_ATTRIB *targetAttrib); ++ ++MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); ++ ++ ++MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, ++ MV_DEC_WIN_PARAMS *pWinParam); ++ ++MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, ++ MV_DEC_WIN *pAddrDecWin); ++ ++ ++ ++ ++#endif /* __INCmvCtrlEnvAddrDech */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,98 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCtrlEnvAsmh ++#define __INCmvCtrlEnvAsmh ++#include "pex/mvPexRegs.h" ++ ++#define CHIP_BOND_REG 0x10034 ++#define PCKG_OPT_MASK_AS #3 ++#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK ++ ++/* Read device ID into toReg bits 15:0 from 0xd0000000 */ ++/* defines */ ++#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ ++ MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ ++ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ ++ ++/* Read device ID into toReg bits 15:0 from 0xf1000000*/ ++#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ ++ MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ ++ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ ++ ++/* Read Revision into toReg bits 7:0 0xd0000000*/ ++#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ ++ /* Read device revision */ \ ++ MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ ++ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ ++ ++/* Read Revision into toReg bits 7:0 0xf1000000*/ ++#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ ++ /* Read device revision */ \ ++ MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ ++ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ ++ ++ ++#endif /* __INCmvCtrlEnvAsmh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1825 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "mvCommon.h" ++#include "mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++#if defined(MV_INCLUDE_PEX) ++#include "pex/mvPex.h" ++#include "ctrlEnv/sys/mvSysPex.h" ++#endif ++ ++#if defined(MV_INCLUDE_GIG_ETH) ++#include "ctrlEnv/sys/mvSysGbe.h" ++#endif ++ ++#if defined(MV_INCLUDE_XOR) ++#include "ctrlEnv/sys/mvSysXor.h" ++#endif ++ ++#if defined(MV_INCLUDE_SATA) ++#include "ctrlEnv/sys/mvSysSata.h" ++#endif ++ ++#if defined(MV_INCLUDE_USB) ++#include "ctrlEnv/sys/mvSysUsb.h" ++#endif ++ ++#if defined(MV_INCLUDE_AUDIO) ++#include "ctrlEnv/sys/mvSysAudio.h" ++#endif ++ ++#if defined(MV_INCLUDE_CESA) ++#include "ctrlEnv/sys/mvSysCesa.h" ++#endif ++ ++#if defined(MV_INCLUDE_TS) ++#include "ctrlEnv/sys/mvSysTs.h" ++#endif ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/******************************************************************************* ++* mvCtrlEnvInit - Initialize Marvell controller environment. ++* ++* DESCRIPTION: ++* This function get environment information and initialize controller ++* internal/external environment. For example ++* 1) MPP settings according to board MPP macros. ++* NOTE: It is the user responsibility to shut down all DMA channels ++* in device and disable controller sub units interrupts during ++* boot process. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvCtrlEnvInit(MV_VOID) ++{ ++ MV_U32 mppGroup; ++ MV_U32 devId; ++ MV_U32 boardId; ++ MV_U32 i; ++ MV_U32 maxMppGrp = 1; ++ MV_U32 mppVal = 0; ++ MV_U32 bootVal = 0; ++ MV_U32 mppGroupType = 0; ++ MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE; ++ MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE; ++ ++ devId = mvCtrlModelGet(); ++ boardId= mvBoardIdGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_GROUP; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_GROUP; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_GROUP; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_GROUP; ++ break; ++ } ++ ++ /* MPP Init */ ++ /* We split mpp init to 3 phases: ++ * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write ++ * in phase 2. ++ * 2. We detect the mpp group type and according the mpp values [35:20]. ++ * 3. We detect the mpp group type and according the mpp values [49:36]. ++ */ ++ /* Mpp phase 1 mpp[19:0] */ ++ /* Read MPP group from board level and assign to MPP register */ ++ for (mppGroup = 0; mppGroup < 3; mppGroup++) ++ { ++ mppVal = mvBoardMppGet(mppGroup); ++ if (mppGroup == 0) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ if (mvCtrlIsBootFromSPI()) ++ { ++ mppVal &= ~0xffff; ++ bootVal &= 0xffff; ++ mppVal |= bootVal; ++ } ++ else if (mvCtrlIsBootFromSPIUseNAND()) ++ { ++ mppVal &= ~0xf0000000; ++ bootVal &= 0xf0000000; ++ mppVal |= bootVal; ++ } ++ else if (mvCtrlIsBootFromNAND()) ++ { ++ mppVal &= ~0xffffff; ++ bootVal &= 0xffffff; ++ mppVal |= bootVal; ++ } ++ } ++ ++ if (mppGroup == 2) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ if (mvCtrlIsBootFromNAND()) ++ { ++ mppVal &= ~0xff00; ++ bootVal &= 0xff00; ++ mppVal |= bootVal; ++ } ++ } ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); ++ } ++ ++ /* Identify MPPs group */ ++ mvBoardMppGroupIdUpdate(); ++ ++ /* Update MPPs mux relevent only on Marvell DB */ ++ if ((boardId == DB_88F6281A_BP_ID) || ++ (boardId == DB_88F6180A_BP_ID)) ++ mvBoardMppMuxSet(); ++ ++ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1); ++ ++ /* Mpp phase 2 */ ++ /* Read MPP group from board level and assign to MPP register */ ++ if (devId != MV_6180_DEV_ID) ++ { ++ i = 0; ++ for (mppGroup = 2; mppGroup < 5; mppGroup++) ++ { ++ if ((mppGroupType == MV_BOARD_OTHER) || ++ (boardId == RD_88F6281A_ID) || ++ (boardId == RD_88F6192A_ID) || ++ (boardId == RD_88F6190A_ID) || ++ (boardId == RD_88F6281A_PCAC_ID) || ++ (boardId == SHEEVA_PLUG_ID)) ++ mppVal = mvBoardMppGet(mppGroup); ++ else ++ { ++ mppVal = mppGroup1[mppGroupType][i]; ++ i++; ++ } ++ ++ /* Group 2 is shared mpp[23:16] */ ++ if (mppGroup == 2) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ mppVal &= ~0xffff; ++ bootVal &= 0xffff; ++ mppVal |= bootVal; ++ } ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); ++ } ++ } ++ ++ if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID)) ++ return MV_OK; ++ ++ /* Mpp phase 3 */ ++ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2); ++ /* Read MPP group from board level and assign to MPP register */ ++ i = 0; ++ for (mppGroup = 4; mppGroup < 7; mppGroup++) ++ { ++ if ((mppGroupType == MV_BOARD_OTHER) || ++ (boardId == RD_88F6281A_ID) || ++ (boardId == RD_88F6281A_PCAC_ID) || ++ (boardId == SHEEVA_PLUG_ID)) ++ mppVal = mvBoardMppGet(mppGroup); ++ else ++ { ++ mppVal = mppGroup2[mppGroupType][i]; ++ i++; ++ } ++ ++ /* Group 4 is shared mpp[35:32] */ ++ if (mppGroup == 4) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ mppVal &= ~0xffff; ++ bootVal &= 0xffff; ++ mppVal |= bootVal; ++ } ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); ++ } ++ /* Update SSCG configuration register*/ ++ if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6192A_BP_ID || ++ mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID) ++ MV_REG_WRITE(0x100d8, 0x53); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCtrlMppRegGet - return reg address of mpp group ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mppGroup - MPP group. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 - Register address. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) ++{ ++ MV_U32 ret; ++ ++ switch(mppGroup){ ++ case (0): ret = MPP_CONTROL_REG0; ++ break; ++ case (1): ret = MPP_CONTROL_REG1; ++ break; ++ case (2): ret = MPP_CONTROL_REG2; ++ break; ++ case (3): ret = MPP_CONTROL_REG3; ++ break; ++ case (4): ret = MPP_CONTROL_REG4; ++ break; ++ case (5): ret = MPP_CONTROL_REG5; ++ break; ++ case (6): ret = MPP_CONTROL_REG6; ++ break; ++ default: ret = MPP_CONTROL_REG0; ++ break; ++ } ++ return ret; ++} ++#if defined(MV_INCLUDE_PEX) ++/******************************************************************************* ++* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. ++* ++* DESCRIPTION: ++* This function returns Marvell controller number of PEX interfaces. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Marvell controller number of PEX interfaces. If controller ++* ID is undefined the function returns '0'. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlPexMaxIfGet(MV_VOID) ++{ ++ ++ return MV_PEX_MAX_IF; ++} ++#endif ++ ++#if defined(MV_INCLUDE_GIG_ETH) ++/******************************************************************************* ++* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. ++* ++* DESCRIPTION: ++* This function returns Marvell controller number of etherent port. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Marvell controller number of etherent port. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlEthMaxPortGet(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_ETH_MAX_PORTS; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_ETH_MAX_PORTS; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_ETH_MAX_PORTS; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_ETH_MAX_PORTS; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_XOR) ++/******************************************************************************* ++* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. ++* ++* DESCRIPTION: ++* This function returns Marvell controller number of XOR channels. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Marvell controller number of XOR channels. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlXorMaxChanGet(MV_VOID) ++{ ++ return MV_XOR_MAX_CHAN; ++} ++#endif ++ ++#if defined(MV_INCLUDE_USB) ++/******************************************************************************* ++* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* returns number of Marvell USB controllers. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlUsbMaxGet(void) ++{ ++ return MV_USB_MAX_PORTS; ++} ++#endif ++ ++ ++#if defined(MV_INCLUDE_NAND) ++/******************************************************************************* ++* mvCtrlNandSupport - Return if this controller has integrated NAND flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if NAND is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlNandSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_NAND; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_NAND; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_NAND; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_NAND; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_SDIO) ++/******************************************************************************* ++* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if SDIO is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlSdioSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_SDIO; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_SDIO; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_SDIO; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_SDIO; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_TS) ++/******************************************************************************* ++* mvCtrlTsSupport - Return if this controller has integrated TS flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if TS is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlTsSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_TS; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_TS; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_TS; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_TS; ++ break; ++ } ++ return 0; ++} ++#endif ++ ++#if defined(MV_INCLUDE_AUDIO) ++/******************************************************************************* ++* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if AUDIO is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlAudioSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_AUDIO; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_AUDIO; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_AUDIO; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_AUDIO; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_TDM) ++/******************************************************************************* ++* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if TDM is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlTdmSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_TDM; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_TDM; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_TDM; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_TDM; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++/******************************************************************************* ++* mvCtrlModelGet - Get Marvell controller device model (Id) ++* ++* DESCRIPTION: ++* This function returns 16bit describing the device model (ID) as defined ++* in PCI Device and Vendor ID configuration register offset 0x0. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 16bit desscribing Marvell controller ID ++* ++*******************************************************************************/ ++MV_U16 mvCtrlModelGet(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = MV_REG_READ(CHIP_BOND_REG); ++ devId &= PCKG_OPT_MASK; ++ ++ switch(devId){ ++ case 2: ++ return MV_6281_DEV_ID; ++ break; ++ case 1: ++ if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) ++ == MV_6190_DEV_ID) ++ return MV_6190_DEV_ID; ++ else ++ return MV_6192_DEV_ID; ++ break; ++ case 0: ++ return MV_6180_DEV_ID; ++ break; ++ } ++ ++ return 0; ++} ++/******************************************************************************* ++* mvCtrlRevGet - Get Marvell controller device revision number ++* ++* DESCRIPTION: ++* This function returns 8bit describing the device revision as defined ++* in PCI Express Class Code and Revision ID Register. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 8bit desscribing Marvell controller revision number ++* ++*******************************************************************************/ ++MV_U8 mvCtrlRevGet(MV_VOID) ++{ ++ MV_U8 revNum; ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++ /* Check pex power state */ ++ MV_U32 pexPower; ++ pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); ++ if (pexPower == MV_FALSE) ++ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); ++#endif ++ revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID)); ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++ /* Return to power off state */ ++ if (pexPower == MV_FALSE) ++ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); ++#endif ++ return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); ++} ++ ++/******************************************************************************* ++* mvCtrlNameGet - Get Marvell controller name ++* ++* DESCRIPTION: ++* This function returns a string describing the device model and revision. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. ++* ++* RETURN: ++* ++* MV_ERROR if informantion can not be read. ++*******************************************************************************/ ++MV_STATUS mvCtrlNameGet(char *pNameBuff) ++{ ++ mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, ++ mvCtrlModelGet(), mvCtrlRevGet()); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision ++* ++* DESCRIPTION: ++* This function returns 32bit value describing both Device ID and Revision ++* as defined in PCI Express Device and Vendor ID Register and device revision ++* as defined in PCI Express Class Code and Revision ID Register. ++ ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing both controller device ID and revision number ++* ++*******************************************************************************/ ++MV_U32 mvCtrlModelRevGet(MV_VOID) ++{ ++ return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); ++} ++ ++/******************************************************************************* ++* mvCtrlModelRevNameGet - Get Marvell controller name ++* ++* DESCRIPTION: ++* This function returns a string describing the device model and revision. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. ++* ++* RETURN: ++* ++* MV_ERROR if informantion can not be read. ++*******************************************************************************/ ++ ++MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) ++{ ++ ++ switch (mvCtrlModelRevGet()) ++ { ++ case MV_6281_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME); ++ break; ++ case MV_6192_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME); ++ break; ++ case MV_6180_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME); ++ break; ++ case MV_6190_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME); ++ break; ++ case MV_6281_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME); ++ break; ++ case MV_6192_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME); ++ break; ++ case MV_6180_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME); ++ break; ++ case MV_6190_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME); ++ break; ++ default: ++ mvCtrlNameGet(pNameBuff); ++ break; ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* ctrlWinOverlapTest - Test address windows for overlaping. ++* ++* DESCRIPTION: ++* This function checks the given two address windows for overlaping. ++* ++* INPUT: ++* pAddrWin1 - Address window 1. ++* pAddrWin2 - Address window 2. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* MV_TRUE if address window overlaps, MV_FALSE otherwise. ++*******************************************************************************/ ++MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) ++{ ++ MV_U32 winBase1, winBase2; ++ MV_U32 winTop1, winTop2; ++ ++ /* check if we have overflow than 4G*/ ++ if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)|| ++ ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1)) ++ { ++ return MV_TRUE; ++ } ++ ++ winBase1 = pAddrWin1->baseLow; ++ winBase2 = pAddrWin2->baseLow; ++ winTop1 = winBase1 + pAddrWin1->size-1; ++ winTop2 = winBase2 + pAddrWin2->size-1; ++ ++ ++ if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) || ++ ((winBase1 <= winBase2) && (winBase2 <= winTop1))) ++ { ++ return MV_TRUE; ++ } ++ else ++ { ++ return MV_FALSE; ++ } ++} ++ ++/******************************************************************************* ++* ctrlWinWithinWinTest - Test address windows for overlaping. ++* ++* DESCRIPTION: ++* This function checks the given win1 boundries is within ++* win2 boundries. ++* ++* INPUT: ++* pAddrWin1 - Address window 1. ++* pAddrWin2 - Address window 2. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. ++*******************************************************************************/ ++MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) ++{ ++ MV_U32 winBase1, winBase2; ++ MV_U32 winTop1, winTop2; ++ ++ winBase1 = pAddrWin1->baseLow; ++ winBase2 = pAddrWin2->baseLow; ++ winTop1 = winBase1 + pAddrWin1->size -1; ++ winTop2 = winBase2 + pAddrWin2->size -1; ++ ++ if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || ++ ((winTop1 >= winBase2) && (winTop1 <= winTop2))) ++ { ++ return MV_TRUE; ++ } ++ else ++ { ++ return MV_FALSE; ++ } ++} ++ ++static const char* cntrlName[] = TARGETS_NAME_ARRAY; ++ ++/******************************************************************************* ++* mvCtrlTargetNameGet - Get Marvell controller target name ++* ++* DESCRIPTION: ++* This function convert the trget enumeration to string. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Target name (const MV_8 *) ++*******************************************************************************/ ++const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) ++{ ++ ++ if (target >= MAX_TARGETS) ++ { ++ return "target unknown"; ++ } ++ ++ return cntrlName[target]; ++} ++ ++/******************************************************************************* ++* mvCtrlAddrDecShow - Print the Controller units address decode map. ++* ++* DESCRIPTION: ++* This function the Controller units address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvCtrlAddrDecShow(MV_VOID) ++{ ++ mvCpuIfAddDecShow(); ++ mvAhbToMbusAddDecShow(); ++#if defined(MV_INCLUDE_PEX) ++ mvPexAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_USB) ++ mvUsbAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ mvEthAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_XOR) ++ mvXorAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_SATA) ++ mvSataAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ mvAudioAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_TS) ++ mvTsuAddrDecShow(); ++#endif ++} ++ ++/******************************************************************************* ++* ctrlSizeToReg - Extract size value for register assignment. ++* ++* DESCRIPTION: ++* Address decode size parameter must be programed from LSB to MSB as ++* sequence of 1's followed by sequence of 0's. The number of 1's ++* specifies the size of the window in 64 KB granularity (e.g. a ++* value of 0x00ff specifies 256x64k = 16 MB). ++* This function extract the size value from the size parameter according ++* to given aligment paramter. For example for size 0x1000000 (16MB) and ++* aligment 0x10000 (64KB) the function will return 0x00FF. ++* ++* INPUT: ++* size - Size. ++* alignment - Size alignment. Note that alignment must be power of 2! ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing size register value correspond to size parameter. ++* If value is '-1' size parameter or aligment are invalid. ++*******************************************************************************/ ++MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) ++{ ++ MV_U32 retVal; ++ ++ /* Check size parameter alignment */ ++ if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); ++ return -1; ++ } ++ ++ /* Take out the "alignment" portion out of the size parameter */ ++ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ ++ /* and size is 0x1000000 (16MB) for example */ ++ while(alignment & 1) /* Check that alignmet LSB is set */ ++ { ++ size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ ++ alignment = (alignment >> 1); ++ } ++ ++ /* If after the alignment first '0' was met we still have '1' in */ ++ /* it then aligment is invalid (not power of 2) */ ++ if (alignment) ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", ++ (MV_U32)alignment)); ++ return -1; ++ } ++ ++ /* Now the size is shifted right according to aligment: 0x0100 */ ++ size--; /* Now the size is a sequance of '1': 0x00ff */ ++ ++ retVal = size ; ++ ++ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ ++ while(size & 1) /* Check that LSB is set */ ++ { ++ size = (size >> 1); /* If LSB is set, move one bit to the right */ ++ } ++ ++ if (size) /* Sequance of 1's is over. Check that we have no other 1's */ ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", ++ size)); ++ return -1; ++ } ++ ++ return retVal; ++ ++} ++ ++/******************************************************************************* ++* ctrlRegToSize - Extract size value from register value. ++* ++* DESCRIPTION: ++* This function extract a size value from the register size parameter ++* according to given aligment paramter. For example for register size ++* value 0xff and aligment 0x10000 the function will return 0x01000000. ++* ++* INPUT: ++* regSize - Size as in register format. See ctrlSizeToReg. ++* alignment - Size alignment. Note that alignment must be power of 2! ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing size. ++* If value is '-1' size parameter or aligment are invalid. ++*******************************************************************************/ ++MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) ++{ ++ MV_U32 temp; ++ ++ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ ++ temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ ++ ++ while(temp & 1) /* Check that LSB is set */ ++ { ++ temp = (temp >> 1); /* If LSB is set, move one bit to the right */ ++ } ++ ++ if (temp) /* Sequance of 1's is over. Check that we have no other 1's */ ++ { ++ DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", ++ regSize)); ++ return -1; ++ } ++ ++ ++ /* Check that aligment is a power of two */ ++ temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ ++ ++ while(temp & 1) /* Check that alignmet LSB is set */ ++ { ++ temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ ++ } ++ ++ /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ ++ /* then 'temp' is invalid (not power of 2) */ ++ if (temp) ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", ++ alignment)); ++ return -1; ++ } ++ ++ regSize++; /* Now the size is 0x0100 */ ++ ++ /* Add in the "alignment" portion to the register size parameter */ ++ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ ++ ++ while(alignment & 1) /* Check that alignmet LSB is set */ ++ { ++ regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ ++ alignment = (alignment >> 1); ++ } ++ ++ return regSize; ++} ++ ++ ++/******************************************************************************* ++* ctrlSizeRegRoundUp - Round up given size ++* ++* DESCRIPTION: ++* This function round up a given size to a size that fits the ++* restrictions of size format given an aligment parameter. ++* to given aligment paramter. For example for size parameter 0xa1000 and ++* aligment 0x1000 the function will return 0xFF000. ++* ++* INPUT: ++* size - Size. ++* alignment - Size alignment. Note that alignment must be power of 2! ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing size value correspond to size in register. ++*******************************************************************************/ ++MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) ++{ ++ MV_U32 msbBit = 0; ++ MV_U32 retSize; ++ ++ /* Check if size parameter is already comply with restriction */ ++ if (!(-1 == ctrlSizeToReg(size, alignment))) ++ { ++ return size; ++ } ++ ++ while(size) ++ { ++ size = (size >> 1); ++ msbBit++; ++ } ++ ++ retSize = (1 << msbBit); ++ ++ if (retSize < alignment) ++ { ++ return alignment; ++ } ++ else ++ { ++ return retSize; ++ } ++} ++/******************************************************************************* ++* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button ++* was pressed and clear counter ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: number of milliseconds the reset button was pressed ++*******************************************************************************/ ++MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID) ++{ ++ static volatile MV_U32 Count = 0; ++ ++ if(!Count) { ++ Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK); ++ Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000)); ++ /* clear counter for next boot */ ++ MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK); ++ } ++ ++ DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count)); ++ ++ return Count; ++} ++ ++MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) ++{ ++ MV_U32 satr = 0; ++ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ { ++ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++ } ++ satr = satr & MSAR_BOOT_MODE_MASK; ++ if (satr == MSAR_BOOT_SPI_WITH_BOOTROM) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++} ++ ++MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID) ++{ ++ MV_U32 satr = 0; ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return MV_FALSE; ++ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ satr = satr & MSAR_BOOT_MODE_MASK; ++ ++ if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++} ++ ++MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) ++{ ++ MV_U32 satr = 0; ++ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ { ++ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++ } ++ satr = satr & MSAR_BOOT_MODE_MASK; ++ if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM)) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++} ++ ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++/******************************************************************************* ++* mvCtrlPwrSaveOn - Set Power save mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrSaveOn(MV_VOID) ++{ ++ unsigned long old,temp; ++ /* Disable int */ ++ __asm__ __volatile__("mrs %0, cpsr\n" ++ "orr %1, %0, #0xc0\n" ++ "msr cpsr_c, %1" ++ : "=r" (old), "=r" (temp) ++ : ++ : "memory"); ++ ++ /* Set SoC in power save */ ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11); ++ /* Wait for int */ ++ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); ++ ++ /* Enabled int */ ++ __asm__ __volatile__("msr cpsr_c, %0" ++ : ++ : "r" (old) ++ : "memory"); ++} ++ ++ ++ ++/******************************************************************************* ++* mvCtrlPwrSaveOff - Go out of power save mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrSaveOff(MV_VOID) ++{ ++ unsigned long old,temp; ++ /* Disable int */ ++ __asm__ __volatile__("mrs %0, cpsr\n" ++ "orr %1, %0, #0xc0\n" ++ "msr cpsr_c, %1" ++ : "=r" (old), "=r" (temp) ++ : ++ : "memory"); ++ ++ /* Set SoC in power save */ ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11); ++ /* Wait for int */ ++ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); ++ ++ /* Enabled int */ ++ __asm__ __volatile__("msr cpsr_c, %0" ++ : ++ : "r" (old) ++ : "memory"); ++} ++ ++/******************************************************************************* ++* mvCtrlPwrClckSet - Set Power State for specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) ++{ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_INTEG_SATA) ++ case SATA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_TS) ++ case TS_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_SDIO) ++ case SDIO_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_TDM) ++ case TDM_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++ ++ default: ++ ++ break; ++ ++ } ++} ++ ++/******************************************************************************* ++* mvCtrlPwrClckGet - Get Power State of specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) ++{ ++ MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); ++ MV_BOOL state = MV_TRUE; ++ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_SATA) ++ case SATA_UNIT_ID: ++ if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_TS) ++ case TS_UNIT_ID: ++ if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_SDIO) ++ case SDIO_UNIT_ID: ++ if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_TDM) ++ case TDM_UNIT_ID: ++ if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++ ++ default: ++ state = MV_TRUE; ++ break; ++ } ++ ++ ++ return state; ++} ++/******************************************************************************* ++* mvCtrlPwrMemSet - Set Power State for memory on specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) ++{ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_INTEG_SATA) ++ case SATA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_XOR) ++ case XOR_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); ++ } ++ break; ++#endif ++ default: ++ ++ break; ++ ++ } ++} ++ ++/******************************************************************************* ++* mvCtrlPwrMemGet - Get Power State of memory on specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) ++{ ++ MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG); ++ MV_BOOL state = MV_TRUE; ++ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if ((reg & PMC_PEXSTOPMEM_MASK) == PMC_PEXSTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_SATA) ++ case SATA_UNIT_ID: ++ if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_XOR) ++ case XOR_UNIT_ID: ++ if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++ ++ default: ++ state = MV_TRUE; ++ break; ++ } ++ ++ ++ return state; ++} ++#else ++MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} ++MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} ++#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ ++ ++ ++/******************************************************************************* ++* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_VOID mvMPPConfigToSPI(MV_VOID) ++{ ++ MV_U32 mppVal = 0; ++ MV_U32 bootVal = 0; ++ ++ if(!mvCtrlIsBootFromSPIUseNAND()) ++ return; ++ mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */ ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); ++ bootVal &= 0xffff000f; ++ mppVal |= bootVal; ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); ++} ++ ++ ++/******************************************************************************* ++* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_VOID mvMPPConfigToDefault(MV_VOID) ++{ ++ MV_U32 mppVal = 0; ++ MV_U32 bootVal = 0; ++ ++ if(!mvCtrlIsBootFromSPIUseNAND()) ++ return; ++ mppVal = mvBoardMppGet(0); ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); ++ mppVal &= ~0xffff000f; ++ bootVal &= 0xffff000f; ++ mppVal |= bootVal; ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,185 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCtrlEnvLibh ++#define __INCmvCtrlEnvLibh ++ ++/* includes */ ++#include "mvSysHwConfig.h" ++#include "mvCommon.h" ++#include "mvTypes.h" ++#include "mvOs.h" ++#include "boardEnv/mvBoardEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/mvCtrlEnvRegs.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++ ++/* typedefs */ ++ ++/* This enumerator describes the possible HW cache coherency policies the */ ++/* controllers supports. */ ++typedef enum _mvCachePolicy ++{ ++ NO_COHERENCY, /* No HW cache coherency support */ ++ WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ ++ WB_COHERENCY /* HW cache coherency supported in Write Back policy */ ++}MV_CACHE_POLICY; ++ ++ ++/* The swapping is referred to a 64-bit words (as this is the controller */ ++/* internal data path width). This enumerator describes the possible */ ++/* data swap types. Below is an example of the data 0x0011223344556677 */ ++typedef enum _mvSwapType ++{ ++ MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ ++ MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ ++ MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ ++ MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ ++ SWAP_TYPE_MAX /* Delimiter for this enumerator */ ++}MV_SWAP_TYPE; ++ ++/* This structure describes access rights for Access protection windows */ ++/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ ++/* Note that the permission enumerator coresponds to its register format. */ ++/* For example, Read only premission is presented as "1" in register field. */ ++typedef enum _mvAccessRights ++{ ++ NO_ACCESS_ALLOWED = 0, /* No access allowed */ ++ READ_ONLY = 1, /* Read only permission */ ++ ACC_RESERVED = 2, /* Reserved access right */ ++ FULL_ACCESS = 3, /* Read and Write permission */ ++ MAX_ACC_RIGHTS ++}MV_ACCESS_RIGHTS; ++ ++ ++/* mcspLib.h API list */ ++ ++MV_STATUS mvCtrlEnvInit(MV_VOID); ++MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); ++ ++#if defined(MV_INCLUDE_PEX) ++MV_U32 mvCtrlPexMaxIfGet(MV_VOID); ++#else ++#define mvCtrlPexMaxIfGet() (0) ++#endif ++ ++#define mvCtrlPciIfMaxIfGet() (0) ++ ++#if defined(MV_INCLUDE_GIG_ETH) ++MV_U32 mvCtrlEthMaxPortGet(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_XOR) ++MV_U32 mvCtrlXorMaxChanGet(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_USB) ++MV_U32 mvCtrlUsbMaxGet(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_NAND) ++MV_U32 mvCtrlNandSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_SDIO) ++MV_U32 mvCtrlSdioSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_TS) ++MV_U32 mvCtrlTsSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++MV_U32 mvCtrlAudioSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_TDM) ++MV_U32 mvCtrlTdmSupport(MV_VOID); ++#endif ++ ++MV_U16 mvCtrlModelGet(MV_VOID); ++MV_U8 mvCtrlRevGet(MV_VOID); ++MV_STATUS mvCtrlNameGet(char *pNameBuff); ++MV_U32 mvCtrlModelRevGet(MV_VOID); ++MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); ++MV_VOID mvCtrlAddrDecShow(MV_VOID); ++const MV_8* mvCtrlTargetNameGet(MV_TARGET target); ++MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); ++MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); ++MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); ++MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); ++MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); ++MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); ++ ++MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); ++MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); ++MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); ++MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); ++MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID); ++MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++MV_VOID mvCtrlPwrSaveOn(MV_VOID); ++MV_VOID mvCtrlPwrSaveOff(MV_VOID); ++#endif ++MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); ++MV_VOID mvMPPConfigToSPI(MV_VOID); ++MV_VOID mvMPPConfigToDefault(MV_VOID); ++ ++ ++#endif /* __INCmvCtrlEnvLibh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,419 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvCtrlEnvRegsh ++#define __INCmvCtrlEnvRegsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* CV Support */ ++#define PEX0_MEM0 PEX0_MEM ++#define PCI0_MEM0 PEX0_MEM ++ ++/* Controller revision info */ ++#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 ++#define PCCRIR_REVID_OFFS 0 /* Revision ID */ ++#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) ++ ++/* Controler environment registers offsets */ ++ ++/* Power Managment Control */ ++#define POWER_MNG_MEM_CTRL_REG 0x20118 ++ ++#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0) ++#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port)) ++#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) ++#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) ++ ++#define PMC_PEXSTOPMEM_OFFS 1 ++#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS) ++#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS) ++#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS) ++ ++#define PMC_USBSTOPMEM_OFFS 2 ++#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS) ++#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS) ++#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS) ++ ++#define PMC_DUNITSTOPMEM_OFFS 3 ++#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS) ++#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) ++#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) ++ ++#define PMC_RUNITSTOPMEM_OFFS 4 ++#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS) ++#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS) ++#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS) ++ ++#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2)) ++#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port)) ++#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) ++#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) ++ ++#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5)) ++#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port)) ++#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) ++#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port)) ++ ++#define PMC_SESTOPMEM_OFFS 8 ++#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS) ++#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS) ++#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS) ++ ++#define PMC_AUDIOSTOPMEM_OFFS 9 ++#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS) ++#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS) ++#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS) ++ ++#define POWER_MNG_CTRL_REG 0x2011C ++ ++#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0) ++#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) ++#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) ++#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) ++ ++#define PMC_PEXPHYSTOPCLOCK_OFFS 1 ++#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS) ++#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS) ++#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS) ++ ++#define PMC_PEXSTOPCLOCK_OFFS 2 ++#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) ++#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS) ++#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS) ++ ++#define PMC_USBSTOPCLOCK_OFFS 3 ++#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) ++#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS) ++#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS) ++ ++#define PMC_SDIOSTOPCLOCK_OFFS 4 ++#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) ++#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) ++#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) ++ ++#define PMC_TSSTOPCLOCK_OFFS 5 ++#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS) ++#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS) ++#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS) ++ ++#define PMC_AUDIOSTOPCLOCK_OFFS 9 ++#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS) ++#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS) ++#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS) ++ ++#define PMC_POWERSAVE_OFFS 11 ++#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS) ++#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS) ++#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS) ++ ++ ++ ++ ++#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port)) ++#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) ++#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) ++#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port)) ++ ++#define PMC_SESTOPCLOCK_OFFS 17 ++#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) ++#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS) ++#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS) ++ ++#define PMC_TDMSTOPCLOCK_OFFS 20 ++#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) ++#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) ++#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) ++ ++ ++/* Controler environment registers offsets */ ++#define MPP_CONTROL_REG0 0x10000 ++#define MPP_CONTROL_REG1 0x10004 ++#define MPP_CONTROL_REG2 0x10008 ++#define MPP_CONTROL_REG3 0x1000C ++#define MPP_CONTROL_REG4 0x10010 ++#define MPP_CONTROL_REG5 0x10014 ++#define MPP_CONTROL_REG6 0x10018 ++#define MPP_SAMPLE_AT_RESET 0x10030 ++#define CHIP_BOND_REG 0x10034 ++#define SYSRST_LENGTH_COUNTER_REG 0x10050 ++#define SLCR_COUNT_OFFS 0 ++#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) ++#define SLCR_CLR_OFFS 31 ++#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) ++#define PCKG_OPT_MASK 0x3 ++#define MPP_OUTPUT_DRIVE_REG 0x100E0 ++#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7 ++#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) ++#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) ++#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15 ++#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) ++#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) ++ ++#define MSAR_BOOT_MODE_OFFS 12 ++#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS) ++#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS) ++#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS) ++#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS) ++ ++#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \ ++ ((X & 0x2) << 1)) ++#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1 ++#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5 ++ ++#define MSAR_TCLCK_OFFS 21 ++#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) ++#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) ++#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS) ++ ++ ++#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \ ++ ((X & 0x18) >> 1)) ++ ++#define MSAR_CPUCLCK_OFFS_6180 2 ++#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180) ++ ++#define MSAR_DDRCLCK_RTIO_OFFS 5 ++#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS) ++ ++#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17)) ++ ++#ifndef MV_ASMLANGUAGE ++/* CPU clock for 6281,6192 0->Resereved */ ++#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \ ++ 600000000, 0, 800000000, 1000000000, \ ++ 0, 1200000000, 0, 0, \ ++ 1500000000, 0, 0, 0} ++ ++/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */ ++#define MV_DDR_CLCK_RTIO_TBL {\ ++ {0, 0}, {0, 0}, {2, 1}, {0, 0}, \ ++ {3, 1}, {0, 0}, {4, 1}, {9, 2}, \ ++ {5, 1}, {6, 1}, {0, 0}, {0, 0}, \ ++ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ ++} ++ ++/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */ ++#define MV_L2_CLCK_RTIO_TBL {\ ++ {0, 0}, {2, 1}, {0, 0}, {3, 1}, \ ++ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ ++} ++ ++/* 6180 have different clk reset sampling */ ++/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */ ++#define MV_CPU6180_DDR_L2_CLCK_TBL { \ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {600000000, 200000000, 300000000 },\ ++ {800000000, 200000000, 400000000 },\ ++ {0, 0, 0 }\ ++} ++ ++ ++ ++/* These macros help units to identify a target Mbus Arbiter group */ ++#define MV_TARGET_IS_DRAM(target) \ ++ ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) ++ ++#define MV_TARGET_IS_PEX0(target) \ ++ ((target >= PEX0_MEM) && (target <= PEX0_IO)) ++ ++#define MV_TARGET_IS_PEX1(target) 0 ++ ++#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) ++ ++#define MV_TARGET_IS_DEVICE(target) \ ++ ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) ++ ++#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 ++ ++#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \ ++ (mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \ ++ (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ ++ & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) ++ ++ ++#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\ ++ sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \ ++ MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \ ++ ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\ ++ >> MSAR_BOOT_MODE_OFFS)]:(target)) ++ ++#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ ++ ++#define BOOT_TARGETS_NAME_ARRAY { \ ++ TBL_TERM, \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ TBL_TERM \ ++} ++ ++#define BOOT_TARGETS_NAME_ARRAY_6180 { \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ TBL_TERM, \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ TBL_TERM \ ++} ++ ++ ++/* For old competability */ ++#define DEVICE_CS0 NFLASH_CS ++#define DEVICE_CS1 SPI_CS ++#define DEVICE_CS2 BOOT_ROM_CS ++#define DEVICE_CS3 DEV_BOOCS ++#define MV_BOOTDEVICE_INDEX 0 ++ ++#define START_DEV_CS DEV_CS0 ++#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) ++ ++#define PCI_IF0_MEM0 PEX0_MEM ++#define PCI_IF0_IO PEX0_IO ++ ++ ++/* This enumerator defines the Marvell controller target ID */ ++typedef enum _mvTargetId ++{ ++ DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ ++ DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */ ++ PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ ++ CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */ ++ SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */ ++ MAX_TARGETS_ID ++}MV_TARGET_ID; ++ ++ ++/* This enumerator described the possible Controller paripheral targets. */ ++/* Controller peripherals are designated memory/IO address spaces that the */ ++/* controller can access. They are also refered as "targets" */ ++typedef enum _mvTarget ++{ ++ TBL_TERM = -1, /* none valid target, used as targets list terminator*/ ++ SDRAM_CS0, /* SDRAM chip select 0 */ ++ SDRAM_CS1, /* SDRAM chip select 1 */ ++ SDRAM_CS2, /* SDRAM chip select 2 */ ++ SDRAM_CS3, /* SDRAM chip select 3 */ ++ PEX0_MEM, /* PCI Express 0 Memory */ ++ PEX0_IO, /* PCI Express 0 IO */ ++ INTER_REGS, /* Internal registers */ ++ NFLASH_CS, /* NFLASH_CS */ ++ SPI_CS, /* SPI_CS */ ++ BOOT_ROM_CS, /* BOOT_ROM_CS */ ++ DEV_BOOCS, /* DEV_BOOCS */ ++ CRYPT_ENG, /* Crypto Engine */ ++#ifdef MV_INCLUDE_SAGE ++ SAGE_UNIT, /* SAGE Unit */ ++#endif ++ MAX_TARGETS ++ ++}MV_TARGET; ++ ++#define TARGETS_DEF_ARRAY { \ ++ {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ ++ {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ ++ {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ ++ {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ ++ {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \ ++ {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \ ++ {0xFF, 0xFF }, /* INTER_REGS */ \ ++ {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \ ++ {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \ ++ {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ ++ {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \ ++ {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \ ++ {0x00, SAGE_TARGET_ID } \ ++} ++ ++ ++#define TARGETS_NAME_ARRAY { \ ++ "SDRAM_CS0", /* SDRAM_CS0 */ \ ++ "SDRAM_CS1", /* SDRAM_CS1 */ \ ++ "SDRAM_CS2", /* SDRAM_CS2 */ \ ++ "SDRAM_CS3", /* SDRAM_CS3 */ \ ++ "PEX0_MEM", /* PEX0_MEM */ \ ++ "PEX0_IO", /* PEX0_IO */ \ ++ "INTER_REGS", /* INTER_REGS */ \ ++ "NFLASH_CS", /* NFLASH_CS */ \ ++ "SPI_CS", /* SPI_CS */ \ ++ "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ ++ "DEV_BOOTCS", /* DEV_BOOCS */ \ ++ "CRYPT_ENG", /* CRYPT_ENG */ \ ++ "SAGE_UNIT" /* SAGE_UNIT */ \ ++} ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,257 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvCtrlEnvSpech ++#define __INCmvCtrlEnvSpech ++ ++#include "mvDeviceId.h" ++#include "mvSysHwConfig.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#define MV_ARM_SOC ++#define SOC_NAME_PREFIX "MV88F" ++ ++ ++/* units base and port numbers */ ++#ifdef MV_ASMLANGUAGE ++#define XOR_UNIT_BASE(unit) 0x60800 ++#else ++#define MV_XOR_REG_BASE 0x60000 ++#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800) ++#endif ++ ++#define TDM_REG_BASE 0xD0000 ++#define USB_REG_BASE(dev) 0x50000 ++#define AUDIO_REG_BASE 0xA0000 ++#define SATA_REG_BASE 0x80000 ++#define MV_CESA_REG_BASE 0x3D000 ++#define MV_CESA_TDMA_REG_BASE 0x30000 ++#define MV_SDIO_REG_BASE 0x90000 ++#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000) ++#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) ++#define DRAM_BASE 0x0 ++#define CNTMR_BASE 0x20300 ++#define TWSI_SLAVE_BASE(chanNum) 0x11000 ++#define PEX_IF_BASE(pexIf) 0x40000 ++#define MPP_REG_BASE 0x10000 ++#define TSU_GLOBAL_REG_BASE 0xB4000 ++#define MAX_AHB_TO_MBUS_REG_BASE 0x20000 ++ ++#define INTER_REGS_SIZE _1M ++/* This define describes the TWSI interrupt bit and location */ ++#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200 ++#define TWSI0_CPU_MAIN_INT_BIT (1<<29) ++#define TWSI_SPEED 100000 ++ ++#define MV_GPP_MAX_GROUP 2 ++#define MV_CNTMR_MAX_COUNTER 2 ++#define MV_UART_MAX_CHAN 2 ++#define MV_XOR_MAX_UNIT 2 ++#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ ++#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ ++#define MV_SATA_MAX_CHAN 2 ++ ++#define MV_6281_MPP_MAX_MODULE 2 ++#define MV_6192_MPP_MAX_MODULE 1 ++#define MV_6190_MPP_MAX_MODULE 1 ++#define MV_6180_MPP_MAX_MODULE 2 ++#define MV_6281_MPP_MAX_GROUP 7 ++#define MV_6192_MPP_MAX_GROUP 4 ++#define MV_6190_MPP_MAX_GROUP 4 ++#define MV_6180_MPP_MAX_GROUP 3 ++ ++#define MV_DRAM_MAX_CS 4 ++ ++/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ ++#define MV_PCI_MAX_IF 0 ++#define MV_PCI_START_IF 0 ++ ++/* This define describes the maximum number of supported PEX Interfaces */ ++#define MV_INCLUDE_PEX0 ++#define MV_DISABLE_PEX_DEVICE_BAR ++#define MV_PEX_MAX_IF 1 ++#define MV_PEX_START_IF MV_PCI_MAX_IF ++ ++/* This define describes the maximum number of supported PCI Interfaces */ ++#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) ++ ++#define MV_ETH_MAX_PORTS 2 ++#define MV_6281_ETH_MAX_PORTS 2 ++#define MV_6192_ETH_MAX_PORTS 2 ++#define MV_6190_ETH_MAX_PORTS 1 ++#define MV_6180_ETH_MAX_PORTS 1 ++ ++#define MV_IDMA_MAX_CHAN 0 ++ ++#define MV_USB_MAX_PORTS 1 ++ ++#define MV_USB_VERSION 1 ++ ++ ++#define MV_6281_NAND 1 ++#define MV_6192_NAND 1 ++#define MV_6190_NAND 1 ++#define MV_6180_NAND 0 ++ ++#define MV_6281_SDIO 1 ++#define MV_6192_SDIO 1 ++#define MV_6190_SDIO 1 ++#define MV_6180_SDIO 1 ++ ++#define MV_6281_TS 1 ++#define MV_6192_TS 1 ++#define MV_6190_TS 0 ++#define MV_6180_TS 0 ++ ++#define MV_6281_AUDIO 1 ++#define MV_6192_AUDIO 1 ++#define MV_6190_AUDIO 0 ++#define MV_6180_AUDIO 1 ++ ++#define MV_6281_TDM 1 ++#define MV_6192_TDM 1 ++#define MV_6190_TDM 0 ++#define MV_6180_TDM 0 ++ ++#define MV_DEVICE_MAX_CS 4 ++ ++/* Others */ ++#define PEX_HOST_BUS_NUM(pciIf) (pciIf) ++#define PEX_HOST_DEV_NUM(pciIf) 0 ++ ++#define PCI_IO(pciIf) (PEX0_IO) ++#define PCI_MEM(pciIf, memNum) (PEX0_MEM0) ++/* CESA version #2: One channel, 2KB SRAM, TDMA */ ++#if defined(MV_CESA_CHAIN_MODE_SUPPORT) ++ #define MV_CESA_VERSION 3 ++#else ++#define MV_CESA_VERSION 2 ++#endif ++#define MV_CESA_SRAM_SIZE 2*1024 ++/* This define describes the maximum number of supported Ethernet ports */ ++#define MV_ETH_VERSION 4 ++#define MV_ETH_MAX_RXQ 8 ++#define MV_ETH_MAX_TXQ 8 ++#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE } ++/* This define describes the the support of USB */ ++#define MV_USB_VERSION 1 ++ ++#define MV_INCLUDE_SDRAM_CS0 ++#define MV_INCLUDE_SDRAM_CS1 ++#define MV_INCLUDE_SDRAM_CS2 ++#define MV_INCLUDE_SDRAM_CS3 ++ ++#define MV_INCLUDE_DEVICE_CS0 ++#define MV_INCLUDE_DEVICE_CS1 ++#define MV_INCLUDE_DEVICE_CS2 ++#define MV_INCLUDE_DEVICE_CS3 ++ ++#define MPP_GROUP_1_TYPE {\ ++ {0, 0, 0}, /* Reserved for AUTO */ \ ++ {0x22220000, 0x22222222, 0x2222}, /* TDM */ \ ++ {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \ ++ {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \ ++ {0x33330000, 0x03333333, 0x0033}, /* GMII */ \ ++ {0x11110000, 0x11111111, 0x0001}, /* TS */ \ ++ {0x33330000, 0x33333333, 0x3333} /* MII */ \ ++} ++ ++#define MPP_GROUP_2_TYPE {\ ++ {0, 0, 0}, /* Reserved for AUTO */ \ ++ {0x22220000, 0x22222222, 0x22}, /* TDM */ \ ++ {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \ ++ {0, 0, 0}, /* N_A */ \ ++ {0, 0, 0}, /* N_A */ \ ++ {0x11110000, 0x11111111, 0x01} /* TS */ \ ++} ++ ++#ifndef MV_ASMLANGUAGE ++ ++/* This enumerator defines the Marvell Units ID */ ++typedef enum _mvUnitId ++{ ++ DRAM_UNIT_ID, ++ PEX_UNIT_ID, ++ ETH_GIG_UNIT_ID, ++ USB_UNIT_ID, ++ IDMA_UNIT_ID, ++ XOR_UNIT_ID, ++ SATA_UNIT_ID, ++ TDM_UNIT_ID, ++ UART_UNIT_ID, ++ CESA_UNIT_ID, ++ SPI_UNIT_ID, ++ AUDIO_UNIT_ID, ++ SDIO_UNIT_ID, ++ TS_UNIT_ID, ++ MAX_UNITS_ID ++ ++}MV_UNIT_ID; ++ ++#endif ++ ++#endif /* __INCmvCtrlEnvSpech */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1048 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "ctrlEnv/sys/mvAhbToMbus.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++#undef MV_DEBUG ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* typedefs */ ++ ++ ++/* CPU address remap registers offsets are inconsecutive. This struct */ ++/* describes address remap register offsets */ ++typedef struct _ahbToMbusRemapRegOffs ++{ ++ MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ ++ MV_U32 highRegOffs; /* High 32 bit remap register offset */ ++}AHB_TO_MBUS_REMAP_REG_OFFS; ++ ++/* locals */ ++static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum, ++ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); ++ ++/******************************************************************************* ++* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK laways. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusInit(void) ++{ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window ++* ++* DESCRIPTION: ++* This function sets ++* address window, also known as address decode window. ++* A new address decode window is set for specified winNum address window. ++* If address decode window parameter structure enables the window, ++* the routine will also enable the winNum window, allowing CPU to access ++* the winNum window. ++* ++* INPUT: ++* winNum - Windows number. ++* pAddrDecWin - CPU winNum window data structure. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of ++* address window overlapps with other active CPU winNum window or ++* trying to assign 36bit base address while CPU does not support that. ++* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttribs; ++ MV_DEC_REGS decRegs; ++ ++ /* Parameter checking */ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ ++ /* read base register*/ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); ++ } ++ else ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ /* read control register*/ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); ++ } ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* enable\Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ decRegs.sizeReg |= ATMWCR_WIN_ENABLE; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; ++ decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; ++ /* set target ID */ ++ decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; ++ decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; ++ ++#if !defined(MV_RUN_FROM_FLASH) ++ /* To be on the safe side we disable the window before writing the */ ++ /* new values. */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ mvAhbToMbusWinEnable(winNum,MV_FALSE); ++ } ++#endif ++ ++ /* 3) Write to address decode Base Address Register */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); ++ } ++ else ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); ++ } ++ ++ ++ /* Internal register space have no size */ ++ /* register. Do not perform size register assigment for those targets */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window ++* ++* DESCRIPTION: ++* Get the CPU peripheral winNum address window. ++* ++* INPUT: ++* winNum - Peripheral winNum enumerator ++* ++* OUTPUT: ++* pAddrDecWin - CPU winNum window information data structure. ++* ++* RETURN: ++* MV_OK if winNum exist, MV_ERROR otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ ++ /* Parameter checking */ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ ++ /* Internal register space size have no size register*/ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); ++ } ++ else ++ { ++ decRegs.sizeReg = 0; ++ } ++ ++ ++ /* Read base and size */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); ++ } ++ else ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); ++ } ++ ++ ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ pAddrDecWin->addrWin.size = INTER_REGS_SIZE; ++ pAddrDecWin->target = INTER_REGS; ++ pAddrDecWin->enable = MV_TRUE; ++ ++ return MV_OK; ++ } ++ ++ ++ if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ ++ } ++ ++ ++ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> ++ ATMWCR_WIN_ATTR_OFFS; ++ targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> ++ ATMWCR_WIN_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinTargetGet - Get Window number associated with target ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ if (INTER_REGS == target) ++ { ++ return MV_AHB_TO_MBUS_INTREG_WIN; ++ } ++ ++ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) ++ { ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ continue; ++ ++ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); ++ return 0xffffffff; ++ ++ } ++ ++ if (decWin.enable == MV_TRUE) ++ { ++ if (decWin.target == target) ++ { ++ return winNum; ++ } ++ ++ } ++ ++ } ++ ++ return 0xFFFFFFFF; ++ ++ ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinAvailGet - Get First Available window number. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) ++ { ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ continue; ++ ++ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); ++ return 0xffffffff; ++ ++ } ++ ++ if (decWin.enable == MV_FALSE) ++ { ++ return winNum; ++ } ++ ++ } ++ ++ return 0xFFFFFFFF; ++} ++ ++ ++/******************************************************************************* ++* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window ++* ++* DESCRIPTION: ++* This function enable/disable a CPU address decode window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling CPU accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - Peripheral winNum enumerator. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if protection window number was wrong, or the window ++* overlapps other winNum window. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) ++{ ++ ++ /* Parameter checking */ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ /* Internal registers bar can't be disable or enabled */ ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ return (enable ? MV_OK : MV_ERROR); ++ } ++ ++ if (enable == MV_TRUE) ++ { ++ /* enable the window */ ++ MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); ++ } ++ else ++ { /* Disable address decode winNum window */ ++ MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvAhbToMbusWinRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* After a CPU address hits one of PCI address decode windows there is an ++* option to remap the address to a different one. For example, CPU ++* executes a read from PCI winNum window address 0x1200.0000. This ++* can be modified so the address on the PCI bus would be 0x1400.0000 ++* Using the PCI address remap mechanism. ++* ++* INPUT: ++* winNum - Peripheral winNum enumerator. Must be a PCI winNum. ++* pAddrDecWin - CPU winNum window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 baseAddr; ++ AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; ++ ++ MV_U32 effectiveBaseAddress=0, ++ baseAddrValue=0,windowSizeValue=0; ++ ++ ++ /* Get registers offsets of given winNum */ ++ if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) ++ { ++ return 0xffffffff; ++ } ++ ++ /* 1) Set address remap low */ ++ baseAddr = pAddrWin->baseLow; ++ ++ /* Check base address aligment */ ++ /* ++ if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) ++ { ++ mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", ++ baseAddr); ++ return MV_ERROR; ++ } ++ */ ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; ++ ++ MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); ++ ++ MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); ++ ++ ++ baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); ++ windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); ++ ++ baseAddrValue &= ATMWBR_BASE_MASK; ++ windowSizeValue &=ATMWCR_WIN_SIZE_MASK; ++ ++ /* Start calculating the effective Base Address */ ++ effectiveBaseAddress = baseAddrValue ; ++ ++ /* The effective base address will be combined from the chopped (if any) ++ remap value (according to the size value and remap mechanism) and the ++ window's base address */ ++ effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); ++ /* If the effectiveBaseAddress exceed the window boundaries return an ++ invalid value. */ ++ ++ if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) ++ { ++ mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); ++ return 0xffffffff; ++ } ++ ++ return effectiveBaseAddress; ++ ++ ++} ++/******************************************************************************* ++* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets ++* ++* DESCRIPTION: ++* ++* INPUT: ++* target1 - CPU Interface target 1 ++* target2 - CPU Interface target 2 ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if targets are illigal, or if one of the targets is not ++* associated to a valid window . ++* MV_OK otherwise. ++* ++*******************************************************************************/ ++ ++ ++MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2) ++{ ++ MV_U32 winNum1,winNum2; ++ MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; ++ AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; ++ MV_U32 remapBaseLow1=0,remapBaseLow2=0; ++ MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; ++ ++ ++ /* Check parameters */ ++ if (target1 >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); ++ return MV_ERROR; ++ } ++ ++ if (target2 >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); ++ return MV_ERROR; ++ } ++ ++ ++ /* get window associated with this target */ ++ winNum1 = mvAhbToMbusWinTargetGet(target1); ++ ++ if (winNum1 == 0xffffffff) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", ++ target1,winNum1); ++ return MV_ERROR; ++ ++ } ++ ++ /* get window associated with this target */ ++ winNum2 = mvAhbToMbusWinTargetGet(target2); ++ ++ if (winNum2 == 0xffffffff) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", ++ target2,winNum2); ++ return MV_ERROR; ++ ++ } ++ ++ /* now Get original values of both Windows */ ++ if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", ++ winNum1); ++ return MV_ERROR; ++ ++ } ++ if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", ++ winNum2); ++ return MV_ERROR; ++ ++ } ++ ++ ++ /* disable both windows */ ++ if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", ++ winNum1); ++ return MV_ERROR; ++ ++ } ++ if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", ++ winNum2); ++ return MV_ERROR; ++ ++ } ++ ++ ++ /* now swap targets */ ++ ++ /* first save winDec2 values */ ++ winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; ++ winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; ++ winDecTemp.addrWin.size = winDec2.addrWin.size; ++ winDecTemp.enable = winDec2.enable; ++ winDecTemp.target = winDec2.target; ++ ++ /* winDec2 = winDec1 */ ++ winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; ++ winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; ++ winDec2.addrWin.size = winDec1.addrWin.size; ++ winDec2.enable = winDec1.enable; ++ winDec2.target = winDec1.target; ++ ++ ++ /* winDec1 = winDecTemp */ ++ winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; ++ winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; ++ winDec1.addrWin.size = winDecTemp.addrWin.size; ++ winDec1.enable = winDecTemp.enable; ++ winDec1.target = winDecTemp.target; ++ ++ ++ /* now set the new values */ ++ ++ ++ mvAhbToMbusWinSet(winNum1,&winDec1); ++ mvAhbToMbusWinSet(winNum2,&winDec2); ++ ++ ++ ++ ++ ++ /* now we will treat the remap windows if exist */ ++ ++ ++ /* now check if one or both windows has a remap window ++ as well after the swap ! */ ++ ++ /* if a window had a remap value differnt than the base value ++ before the swap , then after the swap the remap value will be ++ equal to the base value unless both windows has a remap windows*/ ++ ++ /* first get old values */ ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) ++ { ++ remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); ++ remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); ++ ++ } ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) ++ { ++ remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); ++ remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); ++ ++ ++ } ++ ++ /* now do the swap */ ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) ++ { ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) ++ { ++ /* Two windows has a remap !!! so swap */ ++ ++ MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); ++ MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); ++ ++ MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); ++ MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); ++ ++ ++ ++ } ++ else ++ { ++ /* remap == base */ ++ MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); ++ MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); ++ ++ } ++ ++ } ++ else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) ++ { ++ /* remap == base */ ++ MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); ++ MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); ++ ++ } ++ ++ ++ ++ return MV_OK; ++ ++ ++} ++ ++ ++ ++#if defined(MV_88F1181) ++ ++/******************************************************************************* ++* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration. ++* ++* DESCRIPTION: ++* This function sets CPU Mbus Arbiter ++* ++* INPUT: ++* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At ++* each clock cycle, the crossbar arbiter samples all ++* requests and gives the bus to the next agent according ++* to the "pizza". ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if paramers to function invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray) ++{ ++ MV_U32 sliceNum; ++ MV_U32 xbarCtrl = 0; ++ MV_MBUS_ARB_TARGET xbarTarget; ++ ++ /* 1) Set crossbar control low register */ ++ for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++) ++ { ++ xbarTarget = pPizzaArbArray[sliceNum]; ++ ++ /* sliceNum parameter check */ ++ if (xbarTarget > MAX_MBUS_ARB_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", ++ xbarTarget); ++ return MV_ERROR; ++ } ++ xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum)); ++ } ++ /* Write to crossbar control low register */ ++ MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl); ++ ++ xbarCtrl = 0; ++ ++ /* 2) Set crossbar control high register */ ++ for (sliceNum = MRLR_SLICE_NUM; ++ sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM; ++ sliceNum++) ++ { ++ ++ xbarTarget = pPizzaArbArray[sliceNum]; ++ ++ /* sliceNum parameter check */ ++ if (xbarTarget > MAX_MBUS_ARB_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", ++ xbarTarget); ++ return MV_ERROR; ++ } ++ xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum)); ++ } ++ /* Write to crossbar control high register */ ++ MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvMbusArbCtrlSet - Set MBus Arbiter control register ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ctrl - pointer to MV_MBUS_ARB_CTRL register ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if paramers to function invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl) ++{ ++ ++ if (ctrl->highPrio == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); ++ } ++ else ++ { ++ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); ++ } ++ ++ if (ctrl->fixedRoundRobin == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); ++ } ++ else ++ { ++ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); ++ } ++ ++ if (ctrl->starvEn == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); ++ } ++ else ++ { ++ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvMbusArbCtrlGet - Get MBus Arbiter control register ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ctrl - pointer to MV_MBUS_ARB_CTRL register ++* ++* OUTPUT: ++* ctrl - pointer to MV_MBUS_ARB_CTRL register ++* ++* RETURN: ++* MV_ERROR if paramers to function invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl) ++{ ++ ++ MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG); ++ ++ if (ctrlReg & MACR_ARB_ARM_TOP) ++ { ++ ctrl->highPrio = MV_TRUE; ++ } ++ else ++ { ++ ctrl->highPrio = MV_FALSE; ++ } ++ ++ if (ctrlReg & MACR_ARB_TARGET_FIXED) ++ { ++ ctrl->fixedRoundRobin = MV_TRUE; ++ } ++ else ++ { ++ ctrl->fixedRoundRobin = MV_FALSE; ++ } ++ ++ if (ctrlReg & MACR_ARB_REQ_CTRL_EN) ++ { ++ ctrl->starvEn = MV_TRUE; ++ } ++ else ++ { ++ ctrl->starvEn = MV_FALSE; ++ } ++ ++ ++ return MV_OK; ++} ++ ++#endif /* #if defined(MV_88F1181) */ ++ ++ ++ ++/******************************************************************************* ++* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets ++* ++* DESCRIPTION: ++* CPU to PCI address remap registers offsets are inconsecutive. ++* This function returns PCI address remap registers offsets. ++* ++* INPUT: ++* winNum - Address decode window number. See MV_U32 enumerator. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if winNum is not a PCI one. ++* ++*******************************************************************************/ ++static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, ++ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) ++{ ++ switch (winNum) ++ { ++ case 0: ++ case 1: ++ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); ++ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); ++ break; ++ case 2: ++ case 3: ++ if((mvCtrlModelGet() == MV_5281_DEV_ID) || ++ (mvCtrlModelGet() == MV_1281_DEV_ID) || ++ (mvCtrlModelGet() == MV_6183_DEV_ID) || ++ (mvCtrlModelGet() == MV_6183L_DEV_ID)) ++ { ++ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); ++ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); ++ break; ++ } ++ else ++ { ++ pRemapRegs->lowRegOffs = 0; ++ pRemapRegs->highRegOffs = 0; ++ ++ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", ++ winNum)); ++ return MV_NO_SUCH; ++ } ++ default: ++ { ++ pRemapRegs->lowRegOffs = 0; ++ pRemapRegs->highRegOffs = 0; ++ ++ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", ++ winNum)); ++ return MV_NO_SUCH; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. ++* ++* DESCRIPTION: ++* This function print the CPU address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvAhbToMbusAddDecShow(MV_VOID) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN win; ++ MV_U32 winNum; ++ mvOsOutput( "\n" ); ++ mvOsOutput( "AHB To MBUS Bridge:\n" ); ++ mvOsOutput( "-------------------\n" ); ++ ++ for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) ++ { ++ memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", winNum ); ++ ++ if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,130 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvAhbToMbush ++#define __INCmvAhbToMbush ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvAhbToMbusRegs.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++/* defines */ ++ ++#if defined(MV_88F1181) ++/* This enumerator defines the Marvell controller possible MBUS arbiter */ ++/* target ports. It is used to define crossbar priority scheame (pizza) */ ++typedef enum _mvMBusArbTargetId ++{ ++ DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */ ++ TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */ ++ ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */ ++ PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */ ++ PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */ ++ MAX_MBUS_ARB_TARGETS ++}MV_MBUS_ARB_TARGET; ++ ++typedef struct _mvMBusArbCtrl ++{ ++ MV_BOOL starvEn; ++ MV_BOOL highPrio; ++ MV_BOOL fixedRoundRobin; ++ ++}MV_MBUS_ARB_CTRL; ++ ++#endif /* #if defined(MV_88F1181) */ ++ ++typedef struct _mvAhbtoMbusDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_AHB_TO_MBUS_DEC_WIN; ++ ++/* mvAhbToMbus.h API list */ ++ ++MV_STATUS mvAhbToMbusInit(MV_VOID); ++MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); ++MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); ++MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable); ++MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); ++MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); ++MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); ++MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2); ++ ++#if defined(MV_88F1181) ++ ++MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray); ++MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl); ++MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl); ++ ++#endif /* #if defined(MV_88F1181) */ ++ ++ ++MV_VOID mvAhbToMbusAddDecShow(MV_VOID); ++ ++ ++#endif /* __INCmvAhbToMbush */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,143 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvAhbToMbusRegsh ++#define __INCmvAhbToMbusRegsh ++ ++/******************************/ ++/* ARM Address Map Registers */ ++/******************************/ ++ ++#define MAX_AHB_TO_MBUS_WINS 9 ++#define MV_AHB_TO_MBUS_INTREG_WIN 8 ++ ++ ++#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080 ++ ++/* Window Control Register */ ++/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ ++#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ ++ ++#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated ++ with this window*/ ++#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) ++ ++#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes ++ Associated with this window */ ++#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) ++ ++ ++/* ++Used with the Base register to set the address window size and location ++Must be programed from LSB to MSB as sequence of 1’s followed ++by sequence of 0’s. The number of 1’s specifies the size of the window ++in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). ++ ++NOTE: A value of 0x0 specifies 64KB size. ++*/ ++#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ ++#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) ++#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 ++ ++/* Window Base Register */ ++/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ ++ ++/* ++Used with the size field to set the address window size and location. ++Corresponds to transaction address[31:16] ++*/ ++#define ATMWBR_BASE_OFFS 16 /* Base Address */ ++#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) ++#define ATMWBR_BASE_ALIGNMENT 0x10000 ++ ++/* Window Remap Low Register */ ++/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ ++ ++/* ++Used with the size field to specifies address bits[31:0] to be driven to ++the target interface.: ++target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) ++*/ ++#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ ++#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) ++#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 ++ ++/* Window Remap High Register */ ++/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ ++ ++/* ++Specifies address bits[63:32] to be driven to the target interface. ++target_addr[63:32] = (RemapHigh[31:0] ++*/ ++#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ ++#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) ++ ++ ++#endif /* __INCmvAhbToMbusRegsh */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1036 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/sys/mvAhbToMbusRegs.h" ++#include "cpu/mvCpu.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "mvSysHwConfig.h" ++#include "mvSysDram.h" ++ ++/*#define MV_DEBUG*/ ++/* defines */ ++ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* locals */ ++/* static functions */ ++static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); ++ ++MV_TARGET * sampleAtResetTargetArray; ++MV_TARGET sampleAtResetTargetArrayP[] = BOOT_TARGETS_NAME_ARRAY; ++MV_TARGET sampleAtResetTargetArray6180P[] = BOOT_TARGETS_NAME_ARRAY_6180; ++/******************************************************************************* ++* mvCpuIfInit - Initialize Controller CPU interface ++* ++* DESCRIPTION: ++* This function initialize Controller CPU interface: ++* 1. Set CPU interface configuration registers. ++* 2. Set CPU master Pizza arbiter control according to static ++* configuration described in configuration file. ++* 3. Opens CPU address decode windows. DRAM windows are assumed to be ++* already set (auto detection). ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) ++{ ++ MV_U32 regVal; ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; ++ ++ if (cpuAddrWinMap == NULL) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); ++ return MV_ERROR; ++ } ++ ++ /*Initialize the boot target array according to device type*/ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ sampleAtResetTargetArray = sampleAtResetTargetArray6180P; ++ else ++ sampleAtResetTargetArray = sampleAtResetTargetArrayP; ++ ++ /* Set ARM Configuration register */ ++ regVal = MV_REG_READ(CPU_CONFIG_REG); ++ regVal &= ~CPU_CONFIG_DEFAULT_MASK; ++ regVal |= CPU_CONFIG_DEFAULT; ++ MV_REG_WRITE(CPU_CONFIG_REG,regVal); ++ ++ /* First disable all CPU target windows */ ++ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) ++ { ++ if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) ++ { ++ continue; ++ } ++ ++#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PCI(target)) ++ { ++ continue; ++ } ++#endif ++ ++#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PEX(target)) ++ { ++ continue; ++ } ++#endif ++#if defined(MV_RUN_FROM_FLASH) ++ /* Don't disable the boot device. */ ++ if (target == DEV_BOOCS) ++ { ++ continue; ++ } ++#endif /* MV_RUN_FROM_FLASH */ ++ mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE); ++ } ++ ++#if defined(MV_RUN_FROM_FLASH) ++ /* Resize the bootcs windows before other windows, because this */ ++ /* window is enabled and will cause an overlap if not resized. */ ++ target = DEV_BOOCS; ++ ++ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); ++ return MV_ERROR; ++ } ++ ++ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; ++ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; ++ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", ++ cpuAddrWinMap[target].winNum)); ++ } ++ ++#endif /* MV_RUN_FROM_FLASH */ ++ ++ /* Go through all targets in user table until table terminator */ ++ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) ++ { ++ ++#if defined(MV_RUN_FROM_FLASH) ++ if (target == DEV_BOOCS) ++ { ++ continue; ++ } ++#endif /* MV_RUN_FROM_FLASH */ ++ ++ /* if DRAM auto sizing is used do not initialized DRAM target windows, */ ++ /* assuming this already has been done earlier. */ ++#ifdef MV_DRAM_AUTO_SIZE ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ continue; ++ } ++#endif ++ ++#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PCI(target)) ++ { ++ continue; ++ } ++#endif ++ ++#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PEX(target)) ++ { ++ continue; ++ } ++#endif ++ /* If the target attribute is the same as the boot device attribute */ ++ /* then it's stays disable */ ++ if (MV_TARGET_IS_AS_BOOT(target)) ++ { ++ continue; ++ } ++ ++ if((0 == cpuAddrWinMap[target].addrWin.size) || ++ (DIS == cpuAddrWinMap[target].enable)) ++ ++ { ++ if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); ++ return MV_ERROR; ++ } ++ ++ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; ++ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; ++ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", ++ cpuAddrWinMap[target].winNum)); ++ } ++ ++ ++ } ++ } ++ ++ return MV_OK; ++ ++ ++} ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window ++* ++* DESCRIPTION: ++* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) ++* address window, also known as address decode window. ++* A new address decode window is set for specified target address window. ++* If address decode window parameter structure enables the window, ++* the routine will also enable the target window, allowing CPU to access ++* the target window. ++* ++* INPUT: ++* target - Peripheral target enumerator. ++* pAddrDecWin - CPU target window data structure. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_OK if CPU target window was set correctly, MV_ERROR in case of ++* address window overlapps with other active CPU target window or ++* trying to assign 36bit base address while CPU does not support that. ++* The function returns MV_NOT_SUPPORTED, if the target is unsupported. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_U32 existingWinNum; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* 2) Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ /* copy relevant data to MV_DRAM_DEC_WIN structure */ ++ addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; ++ addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; ++ addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; ++ addrDecWin.enable = pAddrDecWin->enable; ++ ++ ++ if (mvDramIfWinSet(target,&addrDecWin) != MV_OK); ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ ++ decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; ++ decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; ++ decWin.addrWin.size = pAddrDecWin->addrWin.size; ++ decWin.enable = pAddrDecWin->enable; ++ decWin.target = target; ++ ++ existingWinNum = mvAhbToMbusWinTargetGet(target); ++ ++ /* check if there is already another Window configured ++ for this target */ ++ if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&& ++ (existingWinNum != pAddrDecWin->winNum)) ++ { ++ /* if we want to enable the new winow number ++ passed by the user , then the old one should ++ be disabled */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ /* be sure it is disabled */ ++ mvAhbToMbusWinEnable(existingWinNum , MV_FALSE); ++ } ++ } ++ ++ if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); ++ return MV_ERROR; ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window ++* ++* DESCRIPTION: ++* Get the CPU peripheral target address window. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* pAddrDecWin - CPU target window information data structure. ++* ++* RETURN: ++* MV_OK if target exist, MV_ERROR otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) ++{ ++ ++ MV_U32 winNum=0xffffffff; ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ if (mvDramIfWinGet(target,&addrDecWin) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", ++ target); ++ return MV_ERROR; ++ } ++ ++ /* copy relevant data to MV_CPU_DEC_WIN structure */ ++ pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; ++ pAddrDecWin->enable = addrDecWin.enable; ++ pAddrDecWin->winNum = 0xffffffff; ++ ++ } ++ else ++ { ++ /* get the Window number associated with this target */ ++ ++ winNum = mvAhbToMbusWinTargetGet(target); ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ return MV_NO_SUCH; ++ ++ } ++ ++ if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK) ++ { ++ mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", ++ __FUNCTION__, winNum); ++ return MV_ERROR; ++ ++ } ++ ++ /* copy relevant data to MV_CPU_DEC_WIN structure */ ++ pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; ++ pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; ++ pAddrDecWin->addrWin.size = decWin.addrWin.size; ++ pAddrDecWin->enable = decWin.enable; ++ pAddrDecWin->winNum = winNum; ++ ++ } ++ ++ ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window ++* ++* DESCRIPTION: ++* This function enable/disable a CPU address decode window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling CPU accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* target - Peripheral target enumerator. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if protection window number was wrong, or the window ++* overlapps other target window. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable) ++{ ++ MV_U32 winNum, temp; ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* get the window and check if it exist */ ++ temp = mvCpuIfTargetWinGet(target, &addrDecWin); ++ if (MV_NO_SUCH == temp) ++ { ++ return (enable? MV_ERROR: MV_OK); ++ } ++ else if( MV_OK != temp) ++ { ++ mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); ++ return MV_ERROR; ++ } ++ ++ ++ /* check overlap */ ++ ++ if (MV_TRUE == enable) ++ { ++ if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); ++ return MV_ERROR; ++ } ++ ++ } ++ ++ ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ if (mvDramIfWinEnable(target , enable) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); ++ return MV_ERROR; ++ ++ } ++ ++ } ++ else ++ { ++ /* get the Window number associated with this target */ ++ ++ winNum = mvAhbToMbusWinTargetGet(target); ++ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ return (enable? MV_ERROR: MV_OK); ++ } ++ ++ if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", ++ winNum); ++ return MV_ERROR; ++ ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetWinSizeGet - Get CPU target address window size ++* ++* DESCRIPTION: ++* Get the size of CPU-to-peripheral target window. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit size. Function also returns '0' if window is closed. ++* Function returns 0xFFFFFFFF in case of an error. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) ++{ ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); ++ return 0; ++ } ++ ++ /* Get the winNum window */ ++ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", ++ target); ++ return 0; ++ } ++ ++ /* Check if window is enabled */ ++ if (addrDecWin.enable == MV_TRUE) ++ { ++ return (addrDecWin.addrWin.size); ++ } ++ else ++ { ++ return 0; /* Window disabled. return 0 */ ++ } ++} ++ ++/******************************************************************************* ++* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low ++* ++* DESCRIPTION: ++* CPU-to-peripheral target address window base is constructed of ++* two parts: Low and high. ++* This function gets the CPU peripheral target low base address. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit low base address. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) ++{ ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ /* Get the target window */ ++ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", ++ target); ++ return 0xffffffff; ++ } ++ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ return 0xffffffff; ++ } ++ return (addrDecWin.addrWin.baseLow); ++} ++ ++/******************************************************************************* ++* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high ++* ++* DESCRIPTION: ++* CPU-to-peripheral target address window base is constructed of ++* two parts: Low and high. ++* This function gets the CPU peripheral target high base address. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit high base address. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) ++{ ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ /* Get the target window */ ++ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", ++ target); ++ return 0xffffffff; ++ } ++ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ return 0; ++ } ++ ++ return (addrDecWin.addrWin.baseHigh); ++} ++ ++#if defined(MV_INCLUDE_PEX) ++/******************************************************************************* ++* mvCpuIfPexRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* pexTarget - Peripheral target enumerator. Must be a PEX target. ++* pAddrDecWin - CPU target window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if target is not a PEX one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) ++{ ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ ++ if (mvCtrlPexMaxIfGet() > 1) ++ { ++ if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget))) ++ { ++ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); ++ return 0xffffffff; ++ } ++ ++ } ++ else ++ { ++ if (!MV_TARGET_IS_PEX0(pexTarget)) ++ { ++ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); ++ return 0xffffffff; ++ } ++ ++ } ++ ++ /* get the Window number associated with this target */ ++ winNum = mvAhbToMbusWinTargetGet(pexTarget); ++ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); ++ return 0xffffffff; ++ ++ } ++ ++ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); ++} ++ ++#endif ++ ++#if defined(MV_INCLUDE_PCI) ++/******************************************************************************* ++* mvCpuIfPciRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* pciTarget - Peripheral target enumerator. Must be a PCI target. ++* pAddrDecWin - CPU target window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if target is not a PCI one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin) ++{ ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_PCI(pciTarget)) ++ { ++ mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget); ++ return 0xffffffff; ++ } ++ ++ /* get the Window number associated with this target */ ++ winNum = mvAhbToMbusWinTargetGet(pciTarget); ++ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n"); ++ return 0xffffffff; ++ ++ } ++ ++ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); ++} ++#endif /* MV_INCLUDE_PCI */ ++ ++ ++/******************************************************************************* ++* mvCpuIfPciIfRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* pciTarget - Peripheral target enumerator. Must be a PCI target. ++* pAddrDecWin - CPU target window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if target is not a PCI one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) ++{ ++#if defined(MV_INCLUDE_PEX) ++ if (MV_TARGET_IS_PEX(pciIfTarget)) ++ { ++ return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); ++ } ++#endif ++#if defined(MV_INCLUDE_PCI) ++ ++ if (MV_TARGET_IS_PCI(pciIfTarget)) ++ { ++ return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin); ++ } ++#endif ++ return 0; ++} ++ ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address ++* ++* DESCRIPTION: ++* ++* INPUT: ++* baseAddress - base address to be checked ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the target number that baseAddress belongs to or MAX_TARGETS is not ++* found ++* ++*******************************************************************************/ ++ ++MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) ++{ ++ MV_CPU_DEC_WIN win; ++ MV_U32 target; ++ ++ for( target = 0; target < MAX_TARGETS; target++ ) ++ { ++ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ if ((baseAddress >= win.addrWin.baseLow) && ++ (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break; ++ } ++ } ++ else return MAX_TARGETS; ++ ++ } ++ ++ return target; ++} ++/******************************************************************************* ++* cpuTargetWinOverlap - Detect CPU address decode windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case CPU address decode ++* windows overlapps. ++* This function detects CPU address decode windows overlapping of a ++* specified target. The function does not check the target itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* target - Peripheral target enumerator. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlaps current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 targetNum; ++ MV_CPU_DEC_WIN addrDecWin; ++ MV_STATUS status; ++ ++ ++ for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) ++ { ++#if defined(MV_RUN_FROM_FLASH) ++ if(MV_TARGET_IS_AS_BOOT(target)) ++ { ++ if (MV_CHANGE_BOOT_CS(targetNum) == target) ++ continue; ++ } ++#endif /* MV_RUN_FROM_FLASH */ ++ ++ /* don't check our target or illegal targets */ ++ if (targetNum == target) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); ++ if(MV_NO_SUCH == status) ++ { ++ continue; ++ } ++ if(MV_OK != status) ++ { ++ DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); ++ return MV_TRUE; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ DB(mvOsPrintf( ++ "cpuTargetWinOverlap: Required target %d overlap current %d\n", ++ target, targetNum)); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++ ++} ++ ++/******************************************************************************* ++* mvCpuIfAddDecShow - Print the CPU address decode map. ++* ++* DESCRIPTION: ++* This function print the CPU address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvCpuIfAddDecShow(MV_VOID) ++{ ++ MV_CPU_DEC_WIN win; ++ MV_U32 target; ++ mvOsOutput( "\n" ); ++ mvOsOutput( "CPU Interface\n" ); ++ mvOsOutput( "-------------\n" ); ++ ++ for( target = 0; target < MAX_TARGETS; target++ ) ++ { ++ ++ memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); ++ ++ mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); ++ mvOsOutput( "...." ); ++ ++ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "base %08x, ", win.addrWin.baseLow ); ++ mvSizePrint( win.addrWin.size ); ++ mvOsOutput( "\n" ); ++ ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH ) ++ { ++ mvOsOutput( "no such\n" ); ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvCpuIfEnablePex - Enable PCI Express. ++* ++* DESCRIPTION: ++* This function Enable PCI Express. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* pexType - MV_PEX_ROOT_COMPLEX - root complex device ++* MV_PEX_END_POINT - end point device ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++#if defined(MV_INCLUDE_PEX) ++MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType) ++{ ++ /* Set pex mode incase S@R not exist */ ++ if( pexType == MV_PEX_END_POINT) ++ { ++ MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); ++ /* Change pex mode in capability reg */ ++ MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22); ++ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20); ++ ++ } ++ else ++ { ++ MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); ++ } ++ ++ /* CPU config register Pex enable */ ++ MV_REG_BIT_SET(CPU_CTRL_STAT_REG,CCSR_PCI_ACCESS_MASK); ++} ++#endif ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,120 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCpuIfh ++#define __INCmvCpuIfh ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++#include "ctrlEnv/sys/mvAhbToMbus.h" ++#include "ddr2/mvDramIf.h" ++#include "ctrlEnv/sys/mvSysDram.h" ++#if defined(MV_INCLUDE_PEX) ++#include "pex/mvPex.h" ++#endif ++ ++/* defines */ ++ ++/* typedefs */ ++/* This structure describes CPU interface address decode window */ ++typedef struct _mvCpuIfDecWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_CPU_DEC_WIN; ++ ++ ++ ++/* mvCpuIfLib.h API list */ ++ ++/* mvCpuIfLib.h API list */ ++ ++MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); ++MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); ++MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); ++MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); ++MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); ++MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); ++MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); ++MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); ++#if defined(MV_INCLUDE_PEX) ++MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); ++MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType); ++#endif ++#if defined(MV_INCLUDE_PCI) ++MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); ++#endif ++MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); ++ ++MV_VOID mvCpuIfAddDecShow(MV_VOID); ++ ++#if defined(MV88F6281) ++MV_STATUS mvCpuIfBridgeReorderWAInit(void); ++#endif ++ ++#endif /* __INCmvCpuIfh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,163 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#define MV_ASMLANGUAGE ++#include "mvOsAsm.h" ++#include "mvDeviceId.h" ++#include "mvCtrlEnvRegs.h" ++#include "mvCpuIfRegs.h" ++#include "mvCtrlEnvAsm.h" ++ ++ ++/******************************************************************************* ++* mvCpuIfPreInit - Make early initialization of CPU interface. ++* ++* DESCRIPTION: ++* The function will initialize the CPU interface parameters that must ++* be initialize before any BUS activity towards the DDR interface, ++* which means it must be executed from ROM. Because of that, the function ++* is implemented in assembly code. ++* The function configure the following CPU config register parameters: ++* 1) CPU2MbusLTickDrv ++* 2) CPU2MbusLTickSample. ++* NOTE: This function must be called AFTER the internal register ++* base is modified to INTER_REGS_BASE. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++* r11 holds return function address. ++*******************************************************************************/ ++#define MV88F6281_PCKG_OPT 2 ++#define MV88F6192_PCKG_OPT 1 ++#define MV88F6180_PCKG_OPT 0 ++ ++ .globl _mvCpuIfPreInit ++_mvCpuIfPreInit: ++ ++ mov r11, LR /* Save link register */ ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r4, r5); ++ ++ /* goto calcConfigReg if device is 6281 */ ++ ldr r5, =MV88F6281_PCKG_OPT ++ cmp r4, r5 ++ beq calcConfigReg ++ ++ /* goto calcConfigReg if device is 6192/6190 */ ++ ldr r5, =MV88F6192_PCKG_OPT ++ cmp r4, r5 ++ beq calcConfigReg ++ ++ /* Else 6180 */ ++ /* Get the "sample on reset" register */ ++ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) ++ ldr r5, =MSAR_CPUCLCK_MASK_6180 ++ and r5, r4, r5 ++ mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180 ++ ++ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 ++ cmp r5, #CPU_2_DDR_CLK_1x3_1 ++ beq setConfigReg ++ ++ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 ++ cmp r5, #CPU_2_DDR_CLK_1x4_1 ++ beq setConfigReg ++ b setConfigReg ++ ++calcConfigReg: ++ /* Get the "sample on reset" register */ ++ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) ++ ldr r5, =MSAR_DDRCLCK_RTIO_MASK ++ and r5, r4, r5 ++ mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS ++ ++ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 ++ cmp r5, #CPU_2_DDR_CLK_1x3 ++ beq setConfigReg ++ ++ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 ++ cmp r5, #CPU_2_DDR_CLK_1x4 ++ beq setConfigReg ++ ++ /* Else */ ++ ldr r4, =0 ++ ++setConfigReg: ++ /* Read CPU Config register */ ++ MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG) ++ ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK) ++ and r7, r7, r5 /* Clear register fields */ ++ orr r7, r7, r4 /* Set the values according to the findings */ ++ MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG) ++ ++done: ++ mov PC, r11 /* r11 is saved link register */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,304 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCpuIfRegsh ++#define __INCmvCpuIfRegsh ++ ++/****************************************/ ++/* ARM Control and Status Registers Map */ ++/****************************************/ ++ ++#define CPU_CONFIG_REG 0x20100 ++#define CPU_CTRL_STAT_REG 0x20104 ++#define CPU_RSTOUTN_MASK_REG 0x20108 ++#define CPU_SYS_SOFT_RST_REG 0x2010C ++#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110 ++#define CPU_AHB_MBUS_MASK_INT_REG 0x20114 ++#define CPU_FTDLL_CONFIG_REG 0x20120 ++#define CPU_L2_CONFIG_REG 0x20128 ++ ++ ++ ++/* ARM Configuration register */ ++/* CPU_CONFIG_REG (CCR) */ ++ ++ ++/* Reset vector location */ ++#define CCR_VEC_INIT_LOC_OFFS 1 ++#define CCR_VEC_INIT_LOC_MASK BIT1 ++/* reset at 0x00000000 */ ++#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) ++/* reset at 0xFFFF0000 */ ++#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) ++ ++ ++#define CCR_AHB_ERROR_PROP_OFFS 2 ++#define CCR_AHB_ERROR_PROP_MASK BIT2 ++/* Erros are not propogated to AHB */ ++#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) ++/* Erros are propogated to AHB */ ++#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) ++ ++ ++#define CCR_ENDIAN_INIT_OFFS 3 ++#define CCR_ENDIAN_INIT_MASK BIT3 ++#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) ++#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) ++ ++ ++#define CCR_INCR_EN_OFFS 4 ++#define CCR_INCR_EN_MASK BIT4 ++#define CCR_INCR_EN BIT4 ++ ++ ++#define CCR_NCB_BLOCKING_OFFS 5 ++#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS) ++#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS) ++#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS) ++ ++#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8 ++#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) ++#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12 ++#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS) ++#define CCR_ICACH_PREF_BUF_ENABLE BIT16 ++#define CCR_DCACH_PREF_BUF_ENABLE BIT17 ++ ++/* Ratio options for CPU to DDR for 6281/6192/6190 */ ++#define CPU_2_DDR_CLK_1x3 4 ++#define CPU_2_DDR_CLK_1x4 6 ++ ++/* Ratio options for CPU to DDR for 6281 only */ ++#define CPU_2_DDR_CLK_2x9 7 ++#define CPU_2_DDR_CLK_1x5 8 ++#define CPU_2_DDR_CLK_1x6 9 ++ ++/* Ratio options for CPU to DDR for 6180 only */ ++#define CPU_2_DDR_CLK_1x3_1 0x5 ++#define CPU_2_DDR_CLK_1x4_1 0x6 ++ ++/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ ++/* CPU to Mbus-L Tick Sample fields in CPU config register */ ++ ++#define TICK_DRV_1x1 0 ++#define TICK_DRV_1x2 0 ++#define TICK_DRV_1x3 1 ++#define TICK_DRV_1x4 2 ++#define TICK_SMPL_1x1 0 ++#define TICK_SMPL_1x2 1 ++#define TICK_SMPL_1x3 0 ++#define TICK_SMPL_1x4 0 ++ ++#define CPU_2_MBUSL_DDR_CLK_1x2 \ ++ ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ ++ (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) ++#define CPU_2_MBUSL_DDR_CLK_1x3 \ ++ ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ ++ (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) ++#define CPU_2_MBUSL_DDR_CLK_1x4 \ ++ ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ ++ (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) ++ ++/* ARM Control and Status register */ ++/* CPU_CTRL_STAT_REG (CCSR) */ ++ ++ ++/* ++This is used to block PCI express\PCI from access Socrates/Feroceon GP ++while ARM boot is still in progress ++*/ ++ ++#define CCSR_PCI_ACCESS_OFFS 0 ++#define CCSR_PCI_ACCESS_MASK BIT0 ++#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS) ++#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS) ++ ++#define CCSR_ARM_RESET BIT1 ++#define CCSR_SELF_INT BIT2 ++#define CCSR_BIG_ENDIAN BIT15 ++ ++ ++/* RSTOUTn Mask Register */ ++/* CPU_RSTOUTN_MASK_REG (CRMR) */ ++ ++#define CRMR_PEX_RST_OUT_OFFS 0 ++#define CRMR_PEX_RST_OUT_MASK BIT0 ++#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS) ++#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS) ++ ++#define CRMR_WD_RST_OUT_OFFS 1 ++#define CRMR_WD_RST_OUT_MASK BIT1 ++#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS) ++#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS) ++ ++#define CRMR_SOFT_RST_OUT_OFFS 2 ++#define CRMR_SOFT_RST_OUT_MASK BIT2 ++#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) ++#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS) ++ ++/* System Software Reset Register */ ++/* CPU_SYS_SOFT_RST_REG (CSSRR) */ ++ ++#define CSSRR_SYSTEM_SOFT_RST BIT0 ++ ++/* AHB to Mbus Bridge Interrupt Cause Register*/ ++/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ ++ ++#define CAMCIR_ARM_SELF_INT BIT0 ++#define CAMCIR_ARM_TIMER0_INT_REQ BIT1 ++#define CAMCIR_ARM_TIMER1_INT_REQ BIT2 ++#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3 ++ ++ ++/* AHB to Mbus Bridge Interrupt Mask Register*/ ++/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ ++ ++#define CAMCIR_ARM_SELF_INT_OFFS 0 ++#define CAMCIR_ARM_SELF_INT_MASK BIT0 ++#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS) ++#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS) ++ ++ ++#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1 ++#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 ++#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) ++#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) ++ ++#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2 ++#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 ++#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) ++#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) ++ ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) ++ ++/* CPU FTDLL Config register (CFCR) fields */ ++#define CFCR_FTDLL_ICACHE_TAG_OFFS 0 ++#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS) ++#define CFCR_FTDLL_DCACHE_TAG_OFFS 8 ++#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS) ++#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15) ++/* For Orion 2 D2 only */ ++#define CFCR_MRVL_CPU_ID_OFFS 16 ++#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS) ++#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS) ++#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS) ++#define CFCR_VFP_SUB_ARC_NUM_OFFS 7 ++#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) ++#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS) ++#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) ++ ++/* CPU_L2_CONFIG_REG fields */ ++#ifdef MV_CPU_LE ++#define CL2CR_L2_ECC_EN_OFFS 2 ++#define CL2CR_L2_WT_MODE_OFFS 4 ++#else ++#define CL2CR_L2_ECC_EN_OFFS 26 ++#define CL2CR_L2_WT_MODE_OFFS 28 ++#endif ++ ++#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS) ++#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS) ++ ++/*******************************************/ ++/* Main Interrupt Controller Registers Map */ ++/*******************************************/ ++ ++#define CPU_MAIN_INT_CAUSE_REG 0x20200 ++#define CPU_MAIN_IRQ_MASK_REG 0x20204 ++#define CPU_MAIN_FIQ_MASK_REG 0x20208 ++#define CPU_ENPOINT_MASK_REG 0x2020C ++#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210 ++#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214 ++#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218 ++#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C ++ ++ ++/*******************************************/ ++/* ARM Doorbell Registers Map */ ++/*******************************************/ ++ ++#define CPU_HOST_TO_ARM_DRBL_REG 0x20400 ++#define CPU_HOST_TO_ARM_MASK_REG 0x20404 ++#define CPU_ARM_TO_HOST_DRBL_REG 0x20408 ++#define CPU_ARM_TO_HOST_MASK_REG 0x2040C ++ ++ ++ ++/* CPU control register map */ ++/* Set bits means value is about to change according to new value */ ++#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK) ++ ++#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) ++ ++/* CPU Control and status defaults */ ++#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) ++ ++ ++#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) ++ ++#endif /* __INCmvCpuIfRegsh */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,324 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "mvSysAudio.h" ++ ++/******************************************************************************* ++* mvAudioWinSet - Set AUDIO target address window ++* ++* DESCRIPTION: ++* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0) ++* address window, also known as address decode window. ++* After setting this target window, the AUDIO will be able to access the ++* target within the address window. ++* ++* INPUT: ++* winNum - AUDIO target address decode window number. ++* pAddrDecWin - AUDIO target window data structure. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if address window overlapps with other address decode windows. ++* MV_BAD_PARAM if base address is invalid parameter or target is ++* unknown. ++* ++*******************************************************************************/ ++MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttribs; ++ MV_DEC_REGS decRegs; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = 0; ++ decRegs.sizeReg = 0; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK; ++ decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET); ++ ++ /* set target ID */ ++ decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK; ++ decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET); ++ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg); ++ MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAudioWinGet - Get AUDIO peripheral target address window. ++* ++* DESCRIPTION: ++* Get AUDIO peripheral target address window. ++* ++* INPUT: ++* winNum - AUDIO target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - AUDIO target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s : ERR. Invalid winNum %d\n", ++ __FUNCTION__, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) ); ++ decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) ); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) ++ { ++ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >> ++ MV_AUDIO_WIN_ATTR_OFFSET; ++ targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >> ++ MV_AUDIO_WIN_TARGET_OFFSET; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++/******************************************************************************* ++* mvAudioAddrDecShow - Print the AUDIO address decode map. ++* ++* DESCRIPTION: ++* This function print the AUDIO address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvAudioAddrDecShow(MV_VOID) ++{ ++ ++ MV_AUDIO_DEC_WIN win; ++ int i; ++ ++ if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) ++ return; ++ ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "AUDIO:\n" ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvAudioWinGet( i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ ++ ++/******************************************************************************* ++* mvAudioWinInit - Initialize the integrated AUDIO target address window. ++* ++* DESCRIPTION: ++* Initialize the AUDIO peripheral target address window. ++* ++* INPUT: ++* ++* ++* OUTPUT: ++* ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvAudioInit(MV_VOID) ++{ ++ int winNum; ++ MV_AUDIO_DEC_WIN audioWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_U32 status; ++ ++ mvAudioHalInit(); ++ ++ /* Initiate Audio address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum)); ++ regVal &= ~MV_AUDIO_WIN_ENABLE_MASK; ++ MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal); ++ } ++ ++ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ ++ /* We will set the Window to DRAM_CS0 in default */ ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(SDRAM_CS0, ++ &cpuAddrDecWin); ++ ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ audioWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ audioWin.enable = MV_TRUE; ++ audioWin.target = SDRAM_CS0; ++ ++ if(MV_OK != mvAudioWinSet(winNum, &audioWin)) ++ { ++ return MV_ERROR; ++ } ++ } ++ } ++ ++ return MV_OK; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,123 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCMVSysAudioH ++#define __INCMVSysAudioH ++ ++#include "mvCommon.h" ++#include "audio/mvAudio.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++/***********************************/ ++/* Audio Address Decoding registers*/ ++/***********************************/ ++ ++#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2 ++#define MV_AUDIO_RECORD_WIN_NUM 0 ++#define MV_AUDIO_PLAYBACK_WIN_NUM 1 ++ ++#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3)) ++#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3)) ++ ++#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM) ++#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM) ++#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM) ++#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM) ++ ++ ++/* BITs in Windows 0-3 Control and Base Registers */ ++#define MV_AUDIO_WIN_ENABLE_BIT 0 ++#define MV_AUDIO_WIN_ENABLE_MASK (1<= 2) ++MV_TARGET tdmaAddrDecPrioTable[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_MEM, ++#endif ++ ++ TBL_TERM ++}; ++ ++/******************************************************************************* ++* mvCesaWinGet - Get TDMA target address window. ++* ++* DESCRIPTION: ++* Get TDMA target address window. ++* ++* INPUT: ++* winNum - TDMA target address decode window number. ++* ++* OUTPUT: ++* pDecWin - TDMA target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) ++{ ++ MV_DEC_WIN_PARAMS winParam; ++ MV_U32 sizeReg, baseReg; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) ++ { ++ mvOsPrintf("%s : ERR. Invalid winNum %d\n", ++ __FUNCTION__, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); ++ sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); ++ ++ /* Check if window is enabled */ ++ if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) ++ { ++ pDecWin->enable = MV_TRUE; ++ ++ /* Extract window parameters from registers */ ++ winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; ++ winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; ++ winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; ++ winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); ++ ++ /* Translate the decode window parameters to address decode struct */ ++ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) ++ { ++ mvOsPrintf("Failed to translate register parameters to CESA address" \ ++ " decode window structure\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ pDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case TDMA address decode ++* windows overlapps. ++* This function detects TDMA address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE - if the given address window overlap current address ++* decode map, ++* MV_FALSE - otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_DEC_WIN addrDecWin; ++ ++ for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) ++ { ++ mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pDecWin->target), ++ pDecWin->addrWin.baseLow, ++ pDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* set Size, Attributes and TargetID */ ++ sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | ++ ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | ++ ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); ++ ++ if (pDecWin->enable == MV_TRUE) ++ { ++ sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; ++ } ++ ++ /* Update Base value */ ++ baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); ++ ++ MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); ++ MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); ++ ++ return MV_OK; ++} ++ ++ ++static MV_STATUS mvCesaTdmaAddrDecInit (void) ++{ ++ MV_U32 winNum; ++ MV_STATUS status; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_DEC_WIN cesaWin; ++ MV_U32 winPrioIndex = 0; ++ ++ /* First disable all address decode windows */ ++ for(winNum=0; winNum= 2 */ ++ ++ ++ ++ ++MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) ++{ ++ MV_U32 cesaCryptEngBase; ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) ++ { ++ mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n", ++ sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); ++ return MV_FAIL; ++ } ++#if 0 ++ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) ++ cesaCryptEngBase = addrDecWin.addrWin.baseLow; ++ else ++ { ++ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++#else ++ cesaCryptEngBase = (MV_U32)pSramBase; ++#endif ++ ++#if 0 /* Already done in the platform init */ ++#if (MV_CESA_VERSION >= 2) ++ mvCesaTdmaAddrDecInit(); ++#endif /* MV_CESA_VERSION >= 2 */ ++#endif ++ return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, ++ osHandle); ++ ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,100 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvSysCesa_h__ ++#define __mvSysCesa_h__ ++ ++ ++#include "mvCommon.h" ++#include "cesa/mvCesa.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++/***************************** TDMA Registers *************************************/ ++ ++#define MV_CESA_TDMA_ADDR_DEC_WIN 4 ++ ++#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) ++ ++#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) ++ ++#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 ++#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) ++ ++#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 ++#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) ++ ++#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 ++#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) ++ ++#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 ++#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) ++ ++#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 ++#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) ++ ++ ++MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,348 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++ ++#include "ddr2/mvDramIf.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/sys/mvSysDram.h" ++ ++/* #define MV_DEBUG */ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); ++ ++/******************************************************************************* ++* mvDramIfWinSet - Set DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function sets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* pAddrDecWin - SDRAM address window structure. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg=0,sizeReg=0; ++ MV_U32 baseToReg=0 , sizeToReg=0; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlaps with current enabled windows */ ++ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ ++ "\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ target, ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ /* read base register*/ ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); ++ ++ /* read size register */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ baseReg &= ~SCBAR_BASE_MASK; ++ baseReg |= baseToReg; ++ ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* set size */ ++ sizeReg &= ~SCSR_SIZE_MASK; ++ /* Size is located at upper 16 bits */ ++ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); ++ ++ /* enable/Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ sizeReg |= SCSR_WIN_EN; ++ } ++ else ++ { ++ sizeReg &= ~SCSR_WIN_EN; ++ } ++ ++ /* 3) Write to address decode Base Address Register */ ++ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinGet - Get DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function gets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* pAddrDecWin - SDRAM address window structure. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg,sizeReg; ++ MV_U32 sizeRegVal; ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Read base and size registers */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); ++ ++ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; ++ ++ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, ++ SCSR_SIZE_ALIGNMENT); ++ ++ /* Check if ctrlRegToSize returned OK */ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Extract base address */ ++ /* Base register [31:16] ==> baseLow[31:16] */ ++ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; ++ ++ pAddrDecWin->addrWin.baseHigh = 0; ++ ++ ++ if (sizeReg & SCSR_WIN_EN) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinEnable - Enable/Disable SDRAM address decode window ++* ++* DESCRIPTION: ++* This function enable/Disable SDRAM address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR in case function parameter are invalid, MV_OK otherewise. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { /* First check for overlap with other enabled windows */ ++ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", ++ target); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode winNum window */ ++ MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", ++ target); ++ return MV_ERROR; ++ } ++ } ++ else ++ { /* Disable address decode winNum window */ ++ MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window ++* ++* DESCRIPTION: ++* This function scan each SDRAM address decode window to test if it ++* overlapps the given address windoow ++* ++* INPUT: ++* target - SDRAM target where the function skips checking. ++* pAddrDecWin - The tested address window for overlapping with ++* SDRAM windows. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlaps any enabled address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_TARGET targetNum; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) ++ { ++ /* don't check our winNum or illegal targets */ ++ if (targetNum == target) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf( ++ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", ++ target, targetNum); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,80 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __sysDram ++#define __sysDram ++ ++/* This structure describes CPU interface address decode window */ ++typedef struct _mvDramIfDecWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++}MV_DRAM_DEC_WIN; ++ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,658 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "ctrlEnv/sys/mvSysGbe.h" ++ ++ ++ ++typedef struct _mvEthDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_ETH_DEC_WIN; ++ ++MV_TARGET ethAddrDecPrioTap[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS0) ++ DEVICE_CS0, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS1) ++ DEVICE_CS1, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS2) ++ DEVICE_CS2, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS3) ++ DEVICE_CS3, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_IO, ++#endif ++ TBL_TERM ++}; ++ ++static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); ++static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); ++static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); ++ ++ ++/******************************************************************************* ++* mvEthWinInit - Initialize ETH address decode windows ++* ++* DESCRIPTION: ++* This function initialize ETH window decode unit. It set the ++* default address decode windows of the unit. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if setting fail. ++*******************************************************************************/ ++/* Configure EthDrv memory map registes. */ ++MV_STATUS mvEthWinInit (int port) ++{ ++ MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; ++ MV_ETH_DEC_WIN ethWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ static MV_U32 accessProtReg = 0; ++ ++#if (MV_ETH_VERSION <= 1) ++ static MV_BOOL isFirst = MV_TRUE; ++ ++ if(isFirst == MV_FALSE) ++ { ++ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); ++ return MV_OK; ++ } ++ isFirst = MV_FALSE; ++#endif /* MV_GIGA_ETH_VERSION */ ++ ++ /* Initiate Ethernet address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum=0; winNum= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ ++ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); ++ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; ++ decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; ++ /* set target ID */ ++ decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; ++ decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; ++ ++ /* for the safe side we disable the window before writing the new ++ values */ ++ mvEthWinEnable(port, winNum, MV_FALSE); ++ MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); ++ ++ /* Enable address decode target window */ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ mvEthWinEnable(port, winNum, MV_TRUE); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvETHWinGet - Get dma peripheral target address window. ++* ++* DESCRIPTION: ++* Get ETH peripheral target address window. ++* ++* INPUT: ++* winNum - ETH to target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - ETH target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); ++ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; ++ targetAttrib.targetId = ++ (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthWinEnable - Enable/disable a ETH to target address window ++* ++* DESCRIPTION: ++* This function enable/disable a ETH to target address window. ++* According to parameter 'enable' the routine will enable the ++* window, thus enabling ETH accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - ETH to target address decode window number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if decode window number was wrong or enabled window overlapps. ++* ++*******************************************************************************/ ++MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) ++{ ++ MV_ETH_DEC_WIN addrDecWin; ++ ++ /* Parameter checking */ ++ if (winNum >= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { /* First check for overlap with other enabled windows */ ++ /* Get current window */ ++ if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) ++ { ++ mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode target window */ ++ MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { /* Disable address decode target window */ ++ MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthWinTargetGet - Get Window number associated with target ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* window number ++* ++*******************************************************************************/ ++MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) ++{ ++ MV_ETH_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ for (winNum=0; winNum= mvCtrlEthMaxPortGet()) ++ { ++ mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); ++ return MV_ERROR; ++ } ++ ++ if (winNum >= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) ++ { ++ mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); ++ return MV_ERROR; ++ } ++ /* Read current protection register */ ++ protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); ++ ++ /* Clear protection window field */ ++ protReg &= ~(ETH_PROT_WIN_MASK(winNum)); ++ ++ /* Set new protection field value */ ++ protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); ++ ++ /* Write protection register back */ ++ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* ethWinOverlapDetect - Detect ETH address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case ETH address decode ++* windows overlapps. ++* This function detects ETH address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 baseAddrEnableReg; ++ MV_U32 winNumIndex; ++ MV_ETH_DEC_WIN addrDecWin; ++ ++ /* Read base address enable register. Do not check disabled windows */ ++ baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); ++ ++ for (winNumIndex=0; winNumIndex= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Enabled CPU access to PCI-Express */ ++ mvCpuIfEnablePex(pexIf, pexType); ++ ++ /* Start with bars */ ++ /* First disable all PEX bars*/ ++ for (bar = 0; bar < PEX_MAX_BARS; bar++) ++ { ++ if (PEX_INTER_REGS_BAR != bar) ++ { ++ if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) ++ { ++ mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar); ++ return MV_ERROR; ++ } ++ ++ } ++ ++ } ++ ++ /* and disable all PEX target windows */ ++ for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) ++ { ++ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) ++ { ++ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", ++ winNum); ++ return MV_ERROR; ++ ++ } ++ } ++ ++ /* Now, go through all bars*/ ++ ++ ++ ++/******************************************************************************/ ++/* Internal registers bar */ ++/******************************************************************************/ ++ bar = PEX_INTER_REGS_BAR; ++ ++ /* we only open the bar , no need to open windows for this bar */ ++ ++ /* first get the CS attribute from the CPU Interface */ ++ if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); ++ return MV_ERROR; ++ } ++ ++ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pexBar.addrWin.size = addrDecWin.addrWin.size; ++ pexBar.enable = MV_TRUE; ++ ++ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); ++ return MV_ERROR; ++ } ++ ++/******************************************************************************/ ++/* DRAM bar */ ++/******************************************************************************/ ++ ++ bar = PEX_DRAM_BAR; ++ ++ pexBar.addrWin.size = 0; ++ ++ for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ ) ++ { ++ ++ status = mvCpuIfTargetWinGet(target,&addrDecWin); ++ ++ if((MV_NO_SUCH == status)&&(target != SDRAM_CS0)) ++ { ++ continue; ++ } ++ ++ /* first get attributes from CPU If */ ++ if (MV_OK != status) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); ++ return MV_ERROR; ++ } ++ if (addrDecWin.enable == MV_TRUE) ++ { ++ /* the base is the base of DRAM CS0 always */ ++ if (SDRAM_CS0 == target ) ++ { ++ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ ++ } ++ ++ /* increment the bar size to be the sum of the size of all ++ DRAM chips selecs */ ++ pexBar.addrWin.size += addrDecWin.addrWin.size; ++ ++ /* set a Pex window for this target ! ++ DRAM CS always will have a Pex Window , and is not a ++ part of the priority table */ ++ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pexWin.addrWin.size = addrDecWin.addrWin.size; ++ ++ /* we disable the windows at first because we are not ++ sure that it is witihin bar boundries */ ++ pexWin.enable =MV_FALSE; ++ pexWin.target = target; ++ pexWin.targetBar = bar; ++ ++ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); ++ return MV_ERROR; ++ } ++ } ++ } ++ ++ /* check if the size of the bar is illeggal */ ++ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) ++ { ++ /* try to get a good size */ ++ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, ++ PXBCR_BAR_SIZE_ALIGNMENT); ++ } ++ ++ /* check if the size and base are valid */ ++ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) ++ { ++ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); ++ mvOsPrintf("it will be disabled\n"); ++ mvOsPrintf("please check Pex and CPU windows configuration\n"); ++ } ++ else ++ { ++ pexBar.enable = MV_TRUE; ++ ++ /* configure the bar */ ++ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); ++ return MV_ERROR; ++ } ++ ++ /* after the bar was configured then we enable the Pex windows*/ ++ for (winNum = 0;winNum < pexCurrWin ;winNum++) ++ { ++ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) ++ { ++ mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ } ++ } ++ ++/******************************************************************************/ ++/* DEVICE bar */ ++/******************************************************************************/ ++ ++/* Open the Device BAR for non linux only */ ++#ifndef MV_DISABLE_PEX_DEVICE_BAR ++ ++ /* then device bar*/ ++ bar = PEX_DEVICE_BAR; ++ ++ /* save the starting window */ ++ pexStartWindow = pexCurrWin; ++ pexBar.addrWin.size = 0; ++ pexBar.addrWin.baseLow = 0xffffffff; ++ pexBar.addrWin.baseHigh = 0; ++ maxBase = 0; ++ ++ for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ ) ++ { ++ status = mvCpuIfTargetWinGet(target,&addrDecWin); ++ ++ if (MV_NO_SUCH == status) ++ { ++ continue; ++ } ++ ++ if (MV_OK != status) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); ++ return MV_ERROR; ++ } ++ ++ if (addrDecWin.enable == MV_TRUE) ++ { ++ /* get the minimum base */ ++ if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) ++ { ++ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ } ++ ++ /* get the maximum base */ ++ if (addrDecWin.addrWin.baseLow > maxBase) ++ { ++ maxBase = addrDecWin.addrWin.baseLow; ++ sizeOfMaxBase = addrDecWin.addrWin.size; ++ } ++ ++ /* search in the priority table for this target */ ++ for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; ++ winIndex++) ++ { ++ if (pexDevBarPrioTable[winIndex] != target) ++ { ++ continue; ++ } ++ else if (pexDevBarPrioTable[winIndex] == target) ++ { ++ /*found it */ ++ ++ /* if the index of this target in the prio table is valid ++ then we set the Pex window for this target, a valid index is ++ an index that is lower than the number of the windows that ++ was not configured yet */ ++ ++ /* we subtract 2 always because the default and expantion ++ rom windows are always configured */ ++ if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2) ++ { ++ /* set a Pex window for this target ! */ ++ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pexWin.addrWin.size = addrDecWin.addrWin.size; ++ ++ /* we disable the windows at first because we are not ++ sure that it is witihin bar boundries */ ++ pexWin.enable = MV_FALSE; ++ pexWin.target = target; ++ pexWin.targetBar = bar; ++ ++ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, ++ &pexWin)) ++ { ++ mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); ++ return MV_ERROR; ++ } ++ } ++ } ++ } ++ } ++ } ++ ++ pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; ++ pexBar.enable = MV_TRUE; ++ ++ /* check if the size of the bar is illegal */ ++ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) ++ { ++ /* try to get a good size */ ++ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, ++ PXBCR_BAR_SIZE_ALIGNMENT); ++ } ++ ++ /* check if the size and base are valid */ ++ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) ++ { ++ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); ++ mvOsPrintf("it will be disabled\n"); ++ mvOsPrintf("please check Pex and CPU windows configuration\n"); ++ } ++ else ++ { ++ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); ++ return MV_ERROR; ++ } ++ ++ /* now enable the windows */ ++ for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) ++ { ++ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) ++ { ++ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", ++ winNum); ++ return MV_ERROR; ++ } ++ } ++ } ++ ++#endif ++ ++ return mvPexHalInit(pexIf, pexType); ++ ++} ++ ++/******************************************************************************* ++* mvPexTargetWinSet - Set PEX to peripheral target address window BAR ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_OK if PEX BAR target window was set correctly, ++* MV_BAD_PARAM on bad params ++* MV_ERROR otherwise ++* (e.g. address window overlapps with other active PEX target window). ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin) ++{ ++ ++ MV_DEC_REGS decRegs; ++ PEX_WIN_REG_INFO winRegInfo; ++ MV_TARGET_ATTRIB targetAttribs; ++ ++ /* Parameter checking */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (winNum >= PEX_MAX_TARGET_WIN) ++ { ++ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* get the pex Window registers offsets */ ++ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); ++ ++ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ ++ /* 2) Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* 2) Check if the requested window overlaps with current windows */ ++ if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", ++ winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ } ++ ++ ++ ++ /* read base register*/ ++ ++ if (winRegInfo.baseLowRegOffs) ++ { ++ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); ++ } ++ else ++ { ++ decRegs.baseReg = 0; ++ } ++ ++ if (winRegInfo.sizeRegOffs) ++ { ++ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); ++ } ++ else ++ { ++ decRegs.sizeReg =0; ++ } ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* enable\Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ decRegs.sizeReg |= PXWCR_WIN_EN; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~PXWCR_WIN_EN; ++ } ++ ++ ++ /* clear bit location */ ++ decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; ++ ++ /* set bar Mapping */ ++ if (pAddrDecWin->targetBar == 1) ++ { ++ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; ++ } ++ else if (pAddrDecWin->targetBar == 2) ++ { ++ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK; ++ decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS; ++ /* set target ID */ ++ decRegs.sizeReg &= ~PXWCR_TARGET_MASK; ++ decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS; ++ ++ ++ /* 3) Write to address decode Base Address Register */ ++ ++ if (winRegInfo.baseLowRegOffs) ++ { ++ MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg); ++ } ++ ++ /* write size reg */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ if ((MV_PEX_WIN_DEFAULT == winNum)|| ++ (MV_PEX_WIN_EXP_ROM == winNum)) ++ { ++ /* clear size because there is no size field*/ ++ decRegs.sizeReg &= ~PXWCR_SIZE_MASK; ++ ++ /* clear enable because there is no enable field*/ ++ decRegs.sizeReg &= ~PXWCR_WIN_EN; ++ ++ } ++ ++ MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg); ++ } ++ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexTargetWinGet - Get PEX to peripheral target address window ++* ++* DESCRIPTION: ++* Get the PEX to peripheral target address window BAR. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - BAR to be accessed by slave. ++* ++* OUTPUT: ++* pAddrBarWin - PEX target window information data structure. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttrib; ++ MV_DEC_REGS decRegs; ++ ++ PEX_WIN_REG_INFO winRegInfo; ++ ++ /* Parameter checking */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (winNum >= PEX_MAX_TARGET_WIN) ++ { ++ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* get the pex Window registers offsets */ ++ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); ++ ++ /* read base register*/ ++ if (winRegInfo.baseLowRegOffs) ++ { ++ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); ++ } ++ else ++ { ++ decRegs.baseReg = 0; ++ } ++ ++ /* read size reg */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); ++ } ++ else ++ { ++ decRegs.sizeReg =0; ++ } ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ ++ } ++ ++ if (decRegs.sizeReg & PXWCR_WIN_EN) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ ++ } ++ ++ ++ #if 0 ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ return MV_ERROR; ++ } ++ #endif ++ ++ ++ /* get target bar */ ++ if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 ) ++ { ++ pAddrDecWin->targetBar = 1; ++ } ++ else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == ++ PXWCR_WIN_BAR_MAP_BAR2 ) ++ { ++ pAddrDecWin->targetBar = 2; ++ } ++ ++ /* attrib and targetId */ ++ pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >> ++ PXWCR_ATTRIB_OFFS; ++ pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >> ++ PXWCR_TARGET_OFFS; ++ ++ targetAttrib.attrib = pAddrDecWin->attrib; ++ targetAttrib.targetId = pAddrDecWin->targetId; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ return MV_OK; ++ ++} ++ ++ ++/******************************************************************************* ++* mvPexTargetWinEnable - Enable/disable a PEX BAR window ++* ++* DESCRIPTION: ++* This function enable/disable a PEX BAR window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling PEX accesses for that BAR (before enabling the ++* window it is tested for overlapping). Otherwise, the window will ++* be disabled. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - BAR to be accessed by slave. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) ++{ ++ PEX_WIN_REG_INFO winRegInfo; ++ MV_PEX_DEC_WIN addrDecWin; ++ ++ /* Parameter checking */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (winNum >= PEX_MAX_TARGET_WIN) ++ { ++ mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ ++ /* get the pex Window registers offsets */ ++ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); ++ ++ ++ /* if the address windows is disabled , we only disable the appropriare ++ pex window and ignore other settings */ ++ ++ if (MV_FALSE == enable) ++ { ++ ++ /* this is not relevant to default and expantion rom ++ windows */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ if ((MV_PEX_WIN_DEFAULT != winNum)&& ++ (MV_PEX_WIN_EXP_ROM != winNum)) ++ { ++ MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); ++ } ++ } ++ ++ } ++ else ++ { ++ if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", ++ winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ /* this is not relevant to default and expantion rom ++ windows */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ if ((MV_PEX_WIN_DEFAULT != winNum)&& ++ (MV_PEX_WIN_EXP_ROM != winNum)) ++ { ++ MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); ++ } ++ } ++ ++ ++ } ++ ++ return MV_OK; ++ ++} ++ ++ ++ ++/******************************************************************************* ++* mvPexTargetWinRemap - Set PEX to target address window remap. ++* ++* DESCRIPTION: ++* The PEX interface supports remap of the BAR original address window. ++* For each BAR it is possible to define a remap address. For example ++* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified ++* according to remap register but will also be targeted to the ++* SDRAM CS[0]. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - Peripheral target enumerator accessed by slave. ++* pAddrWin - Address window to be checked. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_REMAP_WIN *pAddrWin) ++{ ++ ++ PEX_WIN_REG_INFO winRegInfo; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", ++ pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (MV_PEX_WIN_DEFAULT == winNum) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", ++ winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ ++ "\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ pexIf, ++ winNum, ++ pAddrWin->addrWin.baseLow, ++ pAddrWin->addrWin.size); ++ ++ return MV_ERROR; ++ } ++ ++ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); ++ ++ /* Set remap low register value */ ++ MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); ++ ++ /* Skip base high settings if the BAR has only base low (32-bit) */ ++ if (0 != winRegInfo.remapHighRegOffs) ++ { ++ MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); ++ } ++ ++ ++ if (pAddrWin->enable == MV_TRUE) ++ { ++ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPexTargetWinRemapEnable - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, ++ MV_BOOL enable) ++{ ++ PEX_WIN_REG_INFO winRegInfo; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", ++ pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (MV_PEX_WIN_DEFAULT == winNum) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", ++ winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ ++ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); ++ ++ if (enable == MV_TRUE) ++ { ++ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexBarSet - Set PEX bar address and size ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexBarSet(MV_U32 pexIf, ++ MV_U32 barNum, ++ MV_PEX_BAR *pAddrWin) ++{ ++ MV_U32 regBaseLow; ++ MV_U32 regSize,sizeToReg; ++ ++ ++ /* check parameters */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if(barNum >= PEX_MAX_BARS) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ if (pAddrWin->addrWin.size == 0) ++ { ++ mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" ); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ /* Check if the window complies with PEX spec */ ++ if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, ++ pAddrWin->addrWin.size)) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* 2) Check if the requested bar overlaps with current bars */ ++ if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Get size register value according to window size */ ++ sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); ++ ++ /* Read bar size */ ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ ++ { ++ regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ regSize &= ~PXBCR_BAR_SIZE_MASK; ++ regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; ++ ++ MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); ++ ++ } ++ ++ /* set size */ ++ ++ ++ ++ /* Read base address low */ ++ regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, ++ PEX_MV_BAR_BASE(barNum))); ++ ++ /* clear current base */ ++ if (PEX_INTER_REGS_BAR == barNum) ++ { ++ regBaseLow &= ~PXBIR_BASE_MASK; ++ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); ++ } ++ else ++ { ++ regBaseLow &= ~PXBR_BASE_MASK; ++ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); ++ } ++ ++ /* if we had a previous value that contain the bar type (MeM\IO), we want to ++ restore it */ ++ regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; ++ ++ ++ ++ /* write base low */ ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), ++ regBaseLow); ++ ++ if (pAddrWin->addrWin.baseHigh != 0) ++ { ++ /* Read base address high */ ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), ++ pAddrWin->addrWin.baseHigh); ++ ++ } ++ ++ /* lastly enable the Bar */ ++ if (pAddrWin->enable == MV_TRUE) ++ { ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers ++ are enabled always */ ++ { ++ MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); ++ } ++ } ++ else if (MV_FALSE == pAddrWin->enable) ++ { ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers ++ are enabled always */ ++ { ++ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); ++ } ++ ++ } ++ ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexBarGet - Get PEX bar address and size ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++MV_STATUS mvPexBarGet(MV_U32 pexIf, ++ MV_U32 barNum, ++ MV_PEX_BAR *pAddrWin) ++{ ++ /* check parameters */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if(barNum >= PEX_MAX_BARS) ++ { ++ mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* read base low */ ++ pAddrWin->addrWin.baseLow = ++ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); ++ ++ ++ if (PEX_INTER_REGS_BAR == barNum) ++ { ++ pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; ++ } ++ else ++ { ++ pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; ++ } ++ ++ ++ /* read base high */ ++ pAddrWin->addrWin.baseHigh = ++ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); ++ ++ ++ /* Read bar size */ ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ ++ { ++ pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); ++ ++ /* check if enable or not */ ++ if (pAddrWin->addrWin.size & PXBCR_BAR_EN) ++ { ++ pAddrWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrWin->enable = MV_FALSE; ++ } ++ ++ /* now get the size */ ++ pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; ++ pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; ++ ++ pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, ++ PXBCR_BAR_SIZE_ALIGNMENT); ++ ++ } ++ else /* PEX_INTER_REGS_BAR */ ++ { ++ pAddrWin->addrWin.size = INTER_REGS_SIZE; ++ pAddrWin->enable = MV_TRUE; ++ } ++ ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPexBarEnable - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++ ++MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) ++{ ++ ++ MV_PEX_BAR pexBar; ++ ++ /* check parameters */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ if(barNum >= PEX_MAX_BARS) ++ { ++ mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ if (PEX_INTER_REGS_BAR == barNum) ++ { ++ if (MV_TRUE == enable) ++ { ++ return MV_OK; ++ } ++ else ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ ++ if (MV_FALSE == enable) ++ { ++ /* disable bar and quit */ ++ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); ++ return MV_OK; ++ } ++ ++ /* else */ ++ ++ if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) ++ { ++ mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); ++ return MV_ERROR; ++ ++ } ++ ++ if (MV_TRUE == pexBar.enable) ++ { ++ /* it is already enabled !!! */ ++ return MV_OK; ++ } ++ ++ /* else enable the bar*/ ++ ++ pexBar.enable = MV_TRUE; ++ ++ if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) ++ { ++ mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* pexWinOverlapDetect - Detect address windows overlapping ++* ++* DESCRIPTION: ++* This function detects address window overlapping of a given address ++* window in PEX BARs. ++* ++* INPUT: ++* pAddrWin - Address window to be checked. ++* bar - BAR to be accessed by slave. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, ++ MV_U32 winNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 win; ++ MV_PEX_DEC_WIN addrDecWin; ++ ++ ++ for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++) ++ { ++ /* don't check our target or illegal targets */ ++ if (winNum == win) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) ++ { ++ mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", ++ win); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", ++ winNum, win); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* pexIsWinWithinBar - Detect if address is within PEX bar boundries ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 bar; ++ MV_PEX_BAR addrDecWin; ++ ++ for(bar = 0; bar < PEX_MAX_BARS; bar++) ++ { ++ ++ /* Get window parameters */ ++ if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) ++ { ++ mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled bars */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ ++ if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++ ++} ++ ++/******************************************************************************* ++* pexBarOverlapDetect - Detect address windows overlapping ++* ++* DESCRIPTION: ++* This function detects address window overlapping of a given address ++* window in PEX BARs. ++* ++* INPUT: ++* pAddrWin - Address window to be checked. ++* bar - BAR to be accessed by slave. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, ++ MV_U32 barNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 bar; ++ MV_PEX_BAR barDecWin; ++ ++ ++ for(bar = 0; bar < PEX_MAX_BARS; bar++) ++ { ++ /* don't check our target or illegal targets */ ++ if (barNum == bar) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) ++ { ++ mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* don'nt check disabled bars */ ++ if (barDecWin.enable == MV_FALSE) ++ { ++ continue; ++ } ++ ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) ++ { ++ mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", ++ barNum, bar); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* pexBarIsValid - Check if the given address window is valid ++* ++* DESCRIPTION: ++* PEX spec restrict BAR base to be aligned to BAR size. ++* This function checks if the given address window is valid. ++* ++* INPUT: ++* baseLow - 32bit low base address. ++* size - Window size. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the address window is valid, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) ++{ ++ ++ /* PCI spec restrict BAR base to be aligned to BAR size */ ++ if(MV_IS_NOT_ALIGN(baseLow, size)) ++ { ++ return MV_ERROR; ++ } ++ else ++ { ++ return MV_TRUE; ++ } ++ ++ return MV_TRUE; ++} ++ ++/******************************************************************************* ++* pexBarRegInfoGet - Get BAR register information ++* ++* DESCRIPTION: ++* PEX BARs registers offsets are inconsecutive. ++* This function gets a PEX BAR register information like register offsets ++* and function location of the BAR. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - The PEX BAR in question. ++* ++* OUTPUT: ++* pBarRegInfo - BAR register info struct. ++* ++* RETURN: ++* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK ++* ++*******************************************************************************/ ++static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, ++ MV_U32 winNum, ++ PEX_WIN_REG_INFO *pWinRegInfo) ++{ ++ ++ if ((winNum >= 0)&&(winNum <=3)) ++ { ++ pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum); ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum); ++ pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum); ++ pWinRegInfo->remapHighRegOffs = 0; ++ } ++ else if ((winNum >= 4)&&(winNum <=5)) ++ { ++ pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum); ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum); ++ pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum); ++ pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum); ++ ++ } ++ else if (MV_PEX_WIN_DEFAULT == winNum) ++ { ++ pWinRegInfo->baseLowRegOffs = 0; ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); ++ pWinRegInfo->remapLowRegOffs = 0; ++ pWinRegInfo->remapHighRegOffs = 0; ++ } ++ else if (MV_PEX_WIN_EXP_ROM == winNum) ++ { ++ pWinRegInfo->baseLowRegOffs = 0; ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); ++ pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); ++ pWinRegInfo->remapHighRegOffs = 0; ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* pexBarNameGet - Get the string name of PEX BAR. ++* ++* DESCRIPTION: ++* This function get the string name of PEX BAR. ++* ++* INPUT: ++* bar - PEX bar number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* pointer to the string name of PEX BAR. ++* ++*******************************************************************************/ ++const MV_8* pexBarNameGet( MV_U32 bar ) ++{ ++ switch( bar ) ++ { ++ case PEX_INTER_REGS_BAR: ++ return "Internal Regs Bar0...."; ++ case PEX_DRAM_BAR: ++ return "DRAM Bar1............."; ++ case PEX_DEVICE_BAR: ++ return "Devices Bar2.........."; ++ default: ++ return "Bar unknown"; ++ } ++} ++/******************************************************************************* ++* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). ++* ++* DESCRIPTION: ++* This function print the PEX address decode map (BARs and windows). ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvPexAddrDecShow(MV_VOID) ++{ ++ MV_PEX_BAR pexBar; ++ MV_PEX_DEC_WIN win; ++ MV_U32 pexIf; ++ MV_U32 bar,winNum; ++ ++ for( pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++ ) ++ { ++ if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue; ++ mvOsOutput( "\n" ); ++ mvOsOutput( "PEX%d:\n", pexIf ); ++ mvOsOutput( "-----\n" ); ++ ++ mvOsOutput( "\nPex Bars \n\n"); ++ ++ for( bar = 0; bar < PEX_MAX_BARS; bar++ ) ++ { ++ memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); ++ ++ mvOsOutput( "%s ", pexBarNameGet(bar) ); ++ ++ if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) ++ { ++ if( pexBar.enable ) ++ { ++ mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow ); ++ mvSizePrint( pexBar.addrWin.size ); ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ mvOsOutput( "\nPex Decode Windows\n\n"); ++ ++ for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) ++ { ++ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", winNum ); ++ ++ if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) ++ { ++ if (win.enable) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ ++ ++ } ++ } ++ ++ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); ++ ++ mvOsOutput( "default win - " ); ++ ++ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) ++ { ++ mvOsOutput( "%s ", ++ mvCtrlTargetNameGet(win.target) ); ++ mvOsOutput( "\n" ); ++ } ++ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); ++ ++ mvOsOutput( "Expansion ROM - " ); ++ ++ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) ++ { ++ mvOsOutput( "%s ", ++ mvCtrlTargetNameGet(win.target) ); ++ mvOsOutput( "\n" ); ++ } ++ ++ } ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,348 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCSysPEXH ++#define __INCSysPEXH ++ ++#include "mvCommon.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++/* 4KB granularity */ ++#define MINIMUM_WINDOW_SIZE 0x1000 ++#define MINIMUM_BAR_SIZE 0x1000 ++#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 ++#define BAR_SIZE_OFFS 12 ++#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) ++ ++ ++ ++#define MV_PEX_WIN_DEFAULT 6 ++#define MV_PEX_WIN_EXP_ROM 7 ++#define PEX_MAX_TARGET_WIN 8 ++ ++ ++#define PEX_MAX_BARS 3 ++#define PEX_INTER_REGS_BAR 0 ++#define PEX_DRAM_BAR 1 ++#define PEX_DEVICE_BAR 2 ++ ++/*************************************/ ++/* PCI Express BAR Control Registers */ ++/*************************************/ ++#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000) ++#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000) ++ ++ ++/* PCI Express BAR Control Register */ ++/* PEX_BAR_CTRL_REG (PXBCR) */ ++ ++#define PXBCR_BAR_EN BIT0 ++#define PXBCR_BAR_SIZE_OFFS 16 ++#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) ++#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 ++ ++ ++ ++/* PCI Express Expansion ROM BAR Control Register */ ++/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ ++ ++#define PXERBCR_EXPROM_EN BIT0 ++#define PXERBCR_EXPROMSZ_OFFS 19 ++#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) ++ ++/************************************************/ ++/* PCI Express Address Window Control Registers */ ++/************************************************/ ++#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \ ++ (0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000) ++#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \ ++ (0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000) ++#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \ ++ (0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \ ++ (0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \ ++ (0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \ ++ (0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \ ++ (0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++ ++#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000) ++#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000) ++#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000) ++ ++/* PCI Express Window Control Register */ ++/* PEX_WIN_CTRL_REG (PXWCR) */ ++ ++#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ ++ ++#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ ++#define PXWCR_WIN_BAR_MAP_MASK BIT1 ++#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) ++#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) ++ ++#define PXWCR_TARGET_OFFS 4 /*Unit ID */ ++#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) ++ ++#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ ++#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) ++ ++#define PXWCR_SIZE_OFFS 16 /* size */ ++#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) ++#define PXWCR_SIZE_ALIGNMENT 0x10000 ++ ++/* PCI Express Window Base Register */ ++/* PEX_WIN_BASE_REG (PXWBR)*/ ++ ++#define PXWBR_BASE_OFFS 16 /* address[31:16] */ ++#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) ++#define PXWBR_BASE_ALIGNMENT 0x10000 ++ ++/* PCI Express Window Remap Register */ ++/* PEX_WIN_REMAP_REG (PXWRR)*/ ++ ++#define PXWRR_REMAP_EN BIT0 ++#define PXWRR_REMAP_OFFS 16 ++#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) ++#define PXWRR_REMAP_ALIGNMENT 0x10000 ++ ++/* PCI Express Window Remap (High) Register */ ++/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ ++ ++#define PXWRHR_REMAP_HIGH_OFFS 0 ++#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) ++ ++/* PCI Express Default Window Control Register */ ++/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ ++ ++#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ ++#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) ++#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ ++#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) ++ ++/* PCI Express Expansion ROM Window Control Register */ ++/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ ++ ++#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ ++#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) ++#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ ++#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) ++ ++/* PCI Express Expansion ROM Window Remap Register */ ++/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ ++ ++#define PXWERRR_REMAP_EN BIT0 ++#define PXWERRR_REMAP_OFFS 16 ++#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) ++#define PXWERRR_REMAP_ALIGNMENT 0x10000 ++ ++ ++ ++/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/ ++/* PCI Express BAR0 Internal Register*/ ++/*PEX BAR0_INTER_REG (PXBIR)*/ ++ ++#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ ++ ++#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ ++#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) ++#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) ++#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) ++ ++#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ ++ ++#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ ++#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) ++#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) ++ ++ ++/* PCI Express BAR0 Internal (High) Register*/ ++/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/ ++ ++#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ ++#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) ++ ++ ++#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ ++#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB ++#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB ++#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB ++ ++ ++/* PCI Express BAR1 Register */ ++/* PCI Express BAR2 Register*/ ++/*PEX BAR1_REG (PXBR)*/ ++/*PEX BAR2_REG (PXBR)*/ ++ ++#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ ++ ++#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ ++#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) ++#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) ++#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) ++ ++#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ ++ ++#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ ++#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) ++#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) ++ ++ ++/* PCI Express BAR1 (High) Register*/ ++/* PCI Express BAR2 (High) Register*/ ++/*PEX BAR1_REG_HIGH (PXBRH)*/ ++/*PEX BAR2_REG_HIGH (PXBRH)*/ ++ ++#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ ++#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) ++ ++/* PCI Express Expansion ROM BAR Register*/ ++/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/ ++ ++#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ ++ ++#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) ++ ++#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) ++ ++#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) ++ ++#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) ++ ++/* PEX Bar attributes */ ++typedef struct _mvPexBar ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_PEX_BAR; ++ ++/* PEX Remap Window attributes */ ++typedef struct _mvPexRemapWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_PEX_REMAP_WIN; ++ ++/* PEX Remap Window attributes */ ++typedef struct _mvPexDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_U32 targetBar; ++ MV_U8 attrib; /* chip select attributes */ ++ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_PEX_DEC_WIN; ++ ++/* Global Functions prototypes */ ++/* mvPexHalInit - Initialize PEX interfaces*/ ++MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); ++ ++ ++/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ ++MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin); ++ ++/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ ++MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin); ++ ++/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ ++MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable); ++ ++/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ ++MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_REMAP_WIN *pAddrWin); ++ ++/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ ++MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, ++ MV_BOOL enable); ++ ++/* mvPexBarSet - Set PEX bar address and size */ ++MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); ++ ++/* mvPexBarGet - Get PEX bar address and size */ ++MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); ++ ++/* mvPexBarEnable - enable\disable a PEX bar*/ ++MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); ++ ++/* mvPexAddrDecShow - Display address decode windows attributes */ ++MV_VOID mvPexAddrDecShow(MV_VOID); ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,430 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "mvTypes.h" ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "cpu/mvCpu.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "sata/CoreDriver/mvRegs.h" ++#include "ctrlEnv/sys/mvSysSata.h" ++ ++MV_TARGET sataAddrDecPrioTab[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_MEM, ++#endif ++ TBL_TERM ++}; ++ ++ ++/******************************************************************************* ++* sataWinOverlapDetect - Detect SATA address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case SATA address decode ++* windows overlapps. ++* This function detects SATA address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_SATA_DEC_WIN addrDecWin; ++ ++ for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = 0; ++ decRegs.sizeReg = 0; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; ++ decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); ++ ++ /* set target ID */ ++ decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; ++ decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); ++ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); ++ MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSataWinGet - Get SATA peripheral target address window. ++* ++* DESCRIPTION: ++* Get SATA peripheral target address window. ++* ++* INPUT: ++* winNum - SATA target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - SATA target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", ++ __FUNCTION__, dev, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); ++ decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) ++ { ++ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> ++ MV_SATA_WIN_ATTR_OFFSET; ++ targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> ++ MV_SATA_WIN_TARGET_OFFSET; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++/******************************************************************************* ++* mvSataAddrDecShow - Print the SATA address decode map. ++* ++* DESCRIPTION: ++* This function print the SATA address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvSataAddrDecShow(MV_VOID) ++{ ++ ++ MV_SATA_DEC_WIN win; ++ int i,j; ++ ++ ++ ++ for( j = 0; j < MV_SATA_MAX_CHAN; j++ ) ++ { ++ if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j)) ++ return; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "SATA %d:\n", j ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvSataWinGet(j, i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ } ++} ++ ++ ++/******************************************************************************* ++* mvSataWinInit - Initialize the integrated SATA target address window. ++* ++* DESCRIPTION: ++* Initialize the SATA peripheral target address window. ++* ++* INPUT: ++* ++* ++* OUTPUT: ++* ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSataWinInit(MV_VOID) ++{ ++ int winNum; ++ MV_SATA_DEC_WIN sataWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_U32 status, winPrioIndex = 0; ++ ++ /* Initiate Sata address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); ++ regVal &= ~MV_SATA_WIN_ENABLE_MASK; ++ MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); ++ } ++ ++ winNum = 0; ++ while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && ++ (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) ++ { ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], ++ &cpuAddrDecWin); ++ ++ if(MV_NO_SUCH == status) ++ { ++ winPrioIndex++; ++ continue; ++ } ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ sataWin.enable = MV_TRUE; ++ sataWin.target = sataAddrDecPrioTab[winPrioIndex]; ++ ++ if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) ++ { ++ return MV_ERROR; ++ } ++ winNum++; ++ } ++ winPrioIndex++; ++ } ++ return MV_OK; ++} ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,128 @@ ++ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCMVSysSataAddrDech ++#define __INCMVSysSataAddrDech ++ ++#include "mvCommon.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++typedef struct _mvSataDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++} MV_SATA_DEC_WIN; ++ ++ ++#define MV_SATA_MAX_ADDR_DECODE_WIN 4 ++ ++#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) ++#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) ++ ++/* BITs in Bridge Interrupt Cause and Mask registers */ ++#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 ++#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= MV_SDMMC_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = 0; ++ decRegs.sizeReg = 0; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK; ++ decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET); ++ ++ /* set target ID */ ++ decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK; ++ decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET); ++ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); ++ MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSdmmcWinGet - Get SDMMC peripheral target address window. ++* ++* DESCRIPTION: ++* Get SDMMC peripheral target address window. ++* ++* INPUT: ++* winNum - SDMMC target address decode window number. ++*d ++* OUTPUT: ++* pAddrDecWin - SDMMC target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", ++ __FUNCTION__, dev, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) ); ++ decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) ); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) ++ { ++ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >> ++ MV_SDMMC_WIN_ATTR_OFFSET; ++ targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >> ++ MV_SDMMC_WIN_TARGET_OFFSET; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++/******************************************************************************* ++* mvSdmmcAddrDecShow - Print the SDMMC address decode map. ++* ++* DESCRIPTION: ++* This function print the SDMMC address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvSdmmcAddrDecShow(MV_VOID) ++{ ++ ++ MV_SDMMC_DEC_WIN win; ++ int i,j=0; ++ ++ ++ ++ if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0)) ++ return; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "SDMMC %d:\n", j ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvSdmmcWinGet(j, i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ ++ ++/******************************************************************************* ++* mvSdmmcWinInit - Initialize the integrated SDMMC target address window. ++* ++* DESCRIPTION: ++* Initialize the SDMMC peripheral target address window. ++* ++* INPUT: ++* ++* ++* OUTPUT: ++* ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSdmmcWinInit(MV_VOID) ++{ ++ int winNum; ++ MV_SDMMC_DEC_WIN sdmmcWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_U32 status, winPrioIndex = 0; ++ ++ /* Initiate Sdmmc address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum)); ++ regVal &= ~MV_SDMMC_WIN_ENABLE_MASK; ++ MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal); ++ } ++ ++ winNum = 0; ++ while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) && ++ (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) ) ++ { ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex], ++ &cpuAddrDecWin); ++ ++ if(MV_NO_SUCH == status) ++ { ++ winPrioIndex++; ++ continue; ++ } ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ sdmmcWin.enable = MV_TRUE; ++ sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex]; ++ ++ if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin)) ++ { ++ return MV_ERROR; ++ } ++ winNum++; ++ } ++ winPrioIndex++; ++ } ++ return MV_OK; ++} ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,125 @@ ++ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCMVSysSdmmcAddrDech ++#define __INCMVSysSdmmcAddrDech ++ ++#include "mvCommon.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++typedef struct _mvSdmmcDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++} MV_SDMMC_DEC_WIN; ++ ++ ++#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4 ++ ++#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3)) ++#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3)) ++ ++ ++/* BITs in Windows 0-3 Control and Base Registers */ ++#define MV_SDMMC_WIN_ENABLE_BIT 0 ++#define MV_SDMMC_WIN_ENABLE_MASK (1<= TDM_MBUS_MAX_WIN) ++ { ++ mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* for the safe side we disable the window before writing the new ++ values */ ++ mvTdmWinEnable(winNum, MV_FALSE); ++ ++ ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); ++ ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); ++ ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK); ++ ++ /* Write to address base and control registers */ ++ MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); ++ MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); ++ /* Enable address decode target window */ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ mvTdmWinEnable(winNum, MV_TRUE); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTdmWinGet - Get peripheral target address window. ++* ++* DESCRIPTION: ++* Get TDM peripheral target address window. ++* ++* INPUT: ++* winNum - TDM to target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - TDM target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++ ++MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) ++{ ++ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= TDM_MBUS_MAX_WIN) ++ { ++ mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; ++ targetAttrib.targetId = ++ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTdmWinEnable - Enable/disable a TDM to target address window ++* ++* DESCRIPTION: ++* This function enable/disable a TDM to target address window. ++* According to parameter 'enable' the routine will enable the ++* window, thus enabling TDM accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - TDM to target address decode window number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if decode window number was wrong or enabled window overlapps. ++* ++*******************************************************************************/ ++MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) ++{ ++ MV_TDM_DEC_WIN addrDecWin; ++ ++ if (MV_TRUE == enable) ++ { ++ if (winNum >= TDM_MBUS_MAX_WIN) ++ { ++ mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ /* First check for overlap with other enabled windows */ ++ /* Get current window */ ++ if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) ++ { ++ mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode target window */ ++ MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); ++ } ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* tdmWinOverlapDetect - Detect TDM address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviour is expected in case TDM address decode ++* windows overlapps. ++* This function detects TDM address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_TDM_DEC_WIN addrDecWin; ++ ++ for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) ++ { ++ /* Do not check window itself */ ++ if (winNumIndex == winNum) ++ { ++ continue; ++ } ++ /* Do not check disabled windows */ ++ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) ++ { ++ /* Get window parameters */ ++ if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) ++ { ++ DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); ++ return MV_ERROR; ++ } ++ ++ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) ++ { ++ return MV_TRUE; ++ } ++ } ++ } ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvTdmAddrDecShow - Print the TDM address decode map. ++* ++* DESCRIPTION: ++* This function print the TDM address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvTdmAddrDecShow(MV_VOID) ++{ ++ MV_TDM_DEC_WIN win; ++ int i; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "TDM:\n" ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if (mvTdmWinGet(i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); ++ mvOsOutput( "...." ); ++ mvSizePrint( win.addrWin.size ); ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,106 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSysTdmh ++#define __INCmvSysTdmh ++ ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++typedef struct _mvTdmDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++} MV_TDM_DEC_WIN; ++ ++MV_STATUS mvTdmWinInit(MV_VOID); ++MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable); ++MV_VOID mvTdmAddrDecShow(MV_VOID); ++ ++ ++#define TDM_MBUS_MAX_WIN 4 ++#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4)) ++#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) ++ ++/* TDM_WIN_CTRL_REG bits */ ++#define TDM_WIN_ENABLE_OFFS 0 ++#define TDM_WIN_ENABLE_MASK (1<= TSU_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target " ++ "%s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); ++ ++ if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK; ++ decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS; ++ /* set target ID */ ++ decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK; ++ decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS; ++ ++ /* for the safe side we disable the window before writing the new */ ++ /* values */ ++ mvTsuWinEnable(winNum, MV_FALSE); ++ MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg); ++ ++ /* Enable address decode target window */ ++ if(pAddrDecWin->enable == MV_TRUE) ++ { ++ mvTsuWinEnable(winNum,MV_TRUE); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvTsuWinGet ++* ++* DESCRIPTION: ++* Get TSU peripheral target address window. ++* ++* INPUT: ++* winNum - TSU to target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - TSU target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if(winNum >= TSU_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); ++ ++ if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS; ++ targetAttrib.targetId = ++ (decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK)) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvTsuWinEnable ++* ++* DESCRIPTION: ++* This function enable/disable a TSU to target address window. ++* According to parameter 'enable' the routine will enable the ++* window, thus enabling TSU accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - TSU to target address decode window number. ++* enable - Enable / disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if decode window number was wrong or enabled window overlapps. ++* ++*******************************************************************************/ ++MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable) ++{ ++ MV_TSU_DEC_WIN addrDecWin; ++ ++ /* Parameter checking */ ++ if(winNum >= TSU_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ if(enable == MV_TRUE) ++ { ++ /* First check for overlap with other enabled windows */ ++ /* Get current window. */ ++ if(MV_OK != mvTsuWinGet(winNum,&addrDecWin)) ++ { ++ mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n"); ++ return MV_ERROR; ++ } ++ /* Check for overlapping. */ ++ if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode target window */ ++ MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum), ++ TSU_WIN_CTRL_EN_MASK); ++ } ++ else ++ { ++ /* Overlap detected */ ++ mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ /* Disable address decode target window */ ++ MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum), ++ TSU_WIN_CTRL_EN_MASK); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTsuWinTargetGet ++* ++* DESCRIPTION: ++* Get Window number associated with target ++* ++* INPUT: ++* target - Target ID to get the window number for. ++* OUTPUT: ++* ++* RETURN: ++* window number or 0xFFFFFFFF on error. ++* ++*******************************************************************************/ ++MV_U32 mvTsuWinTargetGet(MV_TARGET target) ++{ ++ MV_TSU_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if(target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++) ++ { ++ if(mvTsuWinGet(winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvTsuWinGet: window returned error\n"); ++ return 0xffffffff; ++ } ++ ++ if (decWin.enable == MV_TRUE) ++ { ++ if(decWin.target == target) ++ { ++ return winNum; ++ } ++ } ++ } ++ return 0xFFFFFFFF; ++} ++ ++ ++/******************************************************************************* ++* tsuWinOverlapDetect ++* ++* DESCRIPTION: ++* Detect TSU address windows overlapping ++* An unpredicted behaviur is expected in case TSU address decode ++* windows overlapps. ++* This function detects TSU address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 ctrlReg; ++ MV_U32 winNumIndex; ++ MV_TSU_DEC_WIN addrDecWin; ++ ++ for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++) ++ { ++ /* Do not check window itself */ ++ if(winNumIndex == winNum) ++ { ++ continue; ++ } ++ ++ /* Do not check disabled windows */ ++ ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex)); ++ if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin)) ++ { ++ mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) ++ { ++ return MV_TRUE; ++ } ++ } ++ return MV_FALSE; ++} ++ ++ ++/******************************************************************************* ++* mvTsuAddrDecShow ++* ++* DESCRIPTION: ++* Print the TSU address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++void mvTsuAddrDecShow(void) ++{ ++ MV_TSU_DEC_WIN win; ++ int i; ++ ++ if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0)) ++ return; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "TSU:\n"); ++ mvOsOutput( "----\n" ); ++ ++ for(i = 0; i < TSU_MAX_DECODE_WIN; i++) ++ { ++ memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN)); ++ mvOsOutput( "win%d - ", i ); ++ ++ if(mvTsuWinGet(i, &win ) == MV_OK ) ++ { ++ if(win.enable == MV_TRUE) ++ { ++ mvOsOutput("%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), ++ win.addrWin.baseLow); ++ mvOsOutput( "...." ); ++ mvSizePrint(win.addrWin.size ); ++ mvOsOutput( "\n" ); ++ } ++ else ++ { ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ } ++ return; ++} ++ ++ ++/******************************************************************************* ++* mvTsuInit ++* ++* DESCRIPTION: ++* Initialize the TSU unit, and get unit out of reset. ++* ++* INPUT: ++* coreClock - The core clock at which the TSU should operate. ++* mode - The mode on configure the unit into (serial/parallel). ++* memHandle - Memory handle used for memory allocations. ++* OUTPUT: ++* None. ++* RETURN: ++* MV_OK - on success, ++* ++*******************************************************************************/ ++MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, ++ void *osHandle) ++{ ++ MV_STATUS status; ++ ++ status = mvTsuWinInit(); ++ if(status == MV_OK) ++ status = mvTsuHalInit(coreClock,mode,osHandle); ++ ++ return status; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,110 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSysTsh ++#define __INCmvSysTsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* includes */ ++#include "ts/mvTsu.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++#define TSU_MAX_DECODE_WIN 4 ++ ++ ++/*******************************************/ ++/* TSU Windows Registers */ ++/*******************************************/ ++#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win) ++#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win) ++ ++/* TSU windows control register. */ ++#define TSU_WIN_CTRL_EN_MASK (0x1 << 0) ++#define TSU_WIN_CTRL_TARGET_OFFS 4 ++#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS) ++#define TSU_WIN_CTRL_ATTR_OFFS 8 ++#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS) ++#define TSU_WIN_CTRL_SIZE_OFFS 16 ++#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS) ++ ++/* TSU windows base register. */ ++#define TSU_WIN_BASE_OFFS 16 ++#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS) ++ ++MV_STATUS mvTsuWinInit(void); ++ ++void mvTsuAddrDecShow(void); ++MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, ++ void *osHandle); ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvTsh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,497 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "ctrlEnv/sys/mvSysUsb.h" ++ ++MV_TARGET usbAddrDecPrioTab[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA) ++ CRYPT_ENG, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_MEM, ++#endif ++ TBL_TERM ++}; ++ ++ ++ ++MV_STATUS mvUsbInit(int dev, MV_BOOL isHost) ++{ ++ MV_STATUS status; ++ ++ status = mvUsbWinInit(dev); ++ if(status != MV_OK) ++ return status; ++ ++ return mvUsbHalInit(dev, isHost); ++} ++ ++ ++/******************************************************************************* ++* usbWinOverlapDetect - Detect USB address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case USB address decode ++* windows overlapps. ++* This function detects USB address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_DEC_WIN addrDecWin; ++ ++ for(winNumIndex=0; winNumIndex= MV_USB_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pDecWin->target), ++ pDecWin->addrWin.baseLow, ++ pDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* set Size, Attributes and TargetID */ ++ sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | ++ ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | ++ ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); ++ ++#if defined(MV645xx) || defined(MV646xx) ++ /* If window is DRAM with HW cache coherency, make sure bit2 is set */ ++ sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; ++ ++ if((MV_TARGET_IS_DRAM(pDecWin->target)) && ++ (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) ++ { ++ sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; ++ } ++ else ++ { ++ sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; ++ } ++#endif /* MV645xx || MV646xx */ ++ ++ if (pDecWin->enable == MV_TRUE) ++ { ++ sizeReg |= MV_USB_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ sizeReg &= ~MV_USB_WIN_ENABLE_MASK; ++ } ++ ++ /* Update Base value */ ++ baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); ++ ++ MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); ++ MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvUsbWinGet - Get USB peripheral target address window. ++* ++* DESCRIPTION: ++* Get USB peripheral target address window. ++* ++* INPUT: ++* winNum - USB target address decode window number. ++* ++* OUTPUT: ++* pDecWin - USB target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) ++{ ++ MV_DEC_WIN_PARAMS winParam; ++ MV_U32 sizeReg, baseReg; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", ++ __FUNCTION__, dev, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); ++ sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); ++ ++ /* Check if window is enabled */ ++ if(sizeReg & MV_USB_WIN_ENABLE_MASK) ++ { ++ pDecWin->enable = MV_TRUE; ++ ++ /* Extract window parameters from registers */ ++ winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; ++ winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; ++ winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; ++ winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); ++ ++ /* Translate the decode window parameters to address decode struct */ ++ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) ++ { ++ mvOsPrintf("Failed to translate register parameters to USB address" \ ++ " decode window structure\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ pDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvUsbWinInit - ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvUsbWinInit(int dev) ++{ ++ MV_STATUS status; ++ MV_DEC_WIN usbWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ int winNum; ++ MV_U32 winPrioIndex = 0; ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); ++ } ++ ++ /* Go through all windows in user table until table terminator */ ++ winNum = 0; ++ while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && ++ (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) ++ { ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], ++ &cpuAddrDecWin); ++ ++ if(MV_NO_SUCH == status) ++ { ++ winPrioIndex++; ++ continue; ++ } ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ usbWin.enable = MV_TRUE; ++ usbWin.target = usbAddrDecPrioTab[winPrioIndex]; ++ ++#if defined(MV645xx) || defined(MV646xx) ++ /* Get the default attributes for that target window */ ++ mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); ++#endif /* MV645xx || MV646xx */ ++ ++ if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) ++ { ++ return MV_ERROR; ++ } ++ winNum++; ++ } ++ winPrioIndex++; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvUsbAddrDecShow - Print the USB address decode map. ++* ++* DESCRIPTION: ++* This function print the USB address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvUsbAddrDecShow(MV_VOID) ++{ ++ MV_DEC_WIN addrDecWin; ++ int i, winNum; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "USB:\n" ); ++ mvOsOutput( "----\n" ); ++ ++ for(i=0; i= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); ++ return MV_BAD_PARAM; ++ } ++ if (pAddrDecWin == NULL) ++ { ++ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); ++ return MV_BAD_PTR; ++ } ++ /* Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); ++ return MV_ERROR; ++ } ++ ++ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); ++ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); ++ ++ /* Get Base Address and size registers values */ ++ if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; ++ xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; ++ /* set target ID */ ++ xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; ++ xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; ++ ++ ++ /* Write to address decode Base Address Register */ ++ MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); ++ ++ /* Write to Size Register */ ++ MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ if (pAddrDecWin->enable) ++ { ++ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorTargetWinGet - Get xor peripheral target address window. ++* ++* DESCRIPTION: ++* Get xor peripheral target address window. ++* ++* INPUT: ++* winNum - One of the possible XOR memory decode windows. ++* ++* OUTPUT: ++* base - Window base address. ++* size - Window size. ++* enable - window enable/disable. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS xorDecRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ MV_U32 chan=0,chanWinEn; ++ ++ /* Parameter checking */ ++ if (winNum >= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); ++ return MV_ERROR; ++ } ++ ++ if (NULL == pAddrDecWin) ++ { ++ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); ++ return MV_BAD_PTR; ++ } ++ ++ chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */ ++ { ++ /* Check if enable bit is equal for all channels */ ++ if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & ++ XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) ++ { ++ mvOsPrintf("%s: ERR. Window enable field must be equal in " ++ "all channels(chan=%d)\n",__FUNCTION__, chan); ++ return MV_ERROR; ++ } ++ } ++ ++ ++ ++ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); ++ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; ++ targetAttrib.targetId = ++ (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; ++ ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ if(chanWinEn) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else pAddrDecWin->enable = MV_FALSE; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorTargetWinEnable - Enable/disable a Xor address decode window ++* ++* DESCRIPTION: ++* This function enable/disable a XOR address decode window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling XOR accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - Decode window number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) ++{ ++ MV_XOR_DEC_WIN addrDecWin; ++ MV_U32 chan; ++ ++ /* Parameter checking */ ++ if (winNum >= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { ++ /* Get current window */ ++ if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); ++ return MV_ERROR; ++ } ++ ++ /* Check for overlapping */ ++ if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) ++ { ++ /* Overlap detected */ ++ DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); ++ return MV_ERROR; ++ } ++ ++ /* No Overlap. Enable address decode target window */ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ ++ } ++ else ++ { ++ /* Disable address decode target window */ ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorSetProtWinSet - Configure access attributes of a XOR engine ++* to one of the XOR memory windows. ++* ++* DESCRIPTION: ++* Each engine can be configured with access attributes for each of the ++* memory spaces. This function sets access attributes ++* to a given window for the given engine ++* ++* INPUTS: ++* chan - One of the possible engines. ++* winNum - One of the possible XOR memory spaces. ++* access - Protection access rights. ++* write - Write rights. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, ++ MV_BOOL write) ++{ ++ MV_U32 temp; ++ ++ /* Parameter checking */ ++ if (chan >= MV_XOR_MAX_CHAN_PER_UNIT) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); ++ return MV_BAD_PARAM; ++ } ++ if (winNum >= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); ++ return MV_BAD_PARAM; ++ } ++ ++ temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & ++ (~XEXWCR_WIN_ACC_MASK(winNum)); ++ ++ /* if access is disable */ ++ if (!access) ++ { ++ /* disable access */ ++ temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); ++ } ++ /* if access is enable */ ++ else ++ { ++ /* if write is enable */ ++ if (write) ++ { ++ /* enable write */ ++ temp |= XEXWCR_WIN_ACC_RW(winNum); ++ } ++ /* if write is disable */ ++ else ++ { ++ /* disable write */ ++ temp |= XEXWCR_WIN_ACC_RO(winNum); ++ } ++ } ++ MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorPciRemap - Set XOR remap register for PCI address windows. ++* ++* DESCRIPTION: ++* only Windows 0-3 can be remapped. ++* ++* INPUT: ++* winNum - window number ++* pAddrDecWin - pointer to address space window structure ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) ++{ ++ /* Parameter checking */ ++ if (winNum >= XOR_MAX_REMAP_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); ++ return MV_BAD_PARAM; ++ } ++ ++ MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* xorWinOverlapDetect - Detect XOR address windows overlaping ++* ++* DESCRIPTION: ++* An unpredicted behaviour is expected in case XOR address decode ++* windows overlaps. ++* This function detects XOR address decode windows overlaping of a ++* specified window. The function does not check the window itself for ++* overlaping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 baseAddrEnableReg; ++ MV_U32 winNumIndex,chan; ++ MV_XOR_DEC_WIN addrDecWin; ++ ++ if (pAddrWin == NULL) ++ { ++ DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); ++ return MV_BAD_PTR; ++ } ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ /* Read base address enable register. Do not check disabled windows */ ++ baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); ++ ++ for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) ++ { ++ /* Do not check window itself */ ++ if (winNumIndex == winNum) ++ { ++ continue; ++ } ++ ++ /* Do not check disabled windows */ ++ if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); ++ return MV_ERROR; ++ } ++ ++ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) ++ { ++ return MV_TRUE; ++ } ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) ++{ ++ MV_XOR_DEC_WIN win; ++ int i; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "XOR %d:\n", unit ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvXorAddrDecShow - Print the XOR address decode map. ++* ++* DESCRIPTION: ++* This function print the XOR address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvXorAddrDecShow(MV_VOID) ++{ ++ int i; ++ ++ for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) ++ mvXorAddrDecShowUnit(i); ++ ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,140 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCMVSysXorh ++#define __INCMVSysXorh ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ ++#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ ++ ++/* XOR Engine Address Decoding Register Map */ ++#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) ++#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) ++#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) ++#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) ++ ++/* XOR Engine [0..1] Window Control Registers (XExWCR) */ ++#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) ++#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) ++#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) ++#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) ++ ++#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) ++#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++ ++/* XOR Engine Base Address Registers (XEBARx) */ ++#define XEBARX_TARGET_OFFS (0) ++#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) ++#define XEBARX_ATTR_OFFS (8) ++#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) ++#define XEBARX_BASE_OFFS (16) ++#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) ++ ++/* XOR Engine Size Mask Registers (XESMRx) */ ++#define XESMRX_SIZE_MASK_OFFS (16) ++#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) ++ ++/* XOR Engine High Address Remap Register (XEHARRx1) */ ++#define XEHARRX_REMAP_OFFS (0) ++#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) ++ ++typedef struct _mvXorDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_XOR_DEC_WIN; ++ ++MV_STATUS mvXorInit (MV_VOID); ++MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, ++ MV_XOR_DEC_WIN *pAddrDecWin); ++MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, ++ MV_XOR_DEC_WIN *pAddrDecWin); ++MV_STATUS mvXorTargetWinEnable(MV_U32 unit, ++ MV_U32 winNum, MV_BOOL enable); ++MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, ++ MV_BOOL write); ++MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); ++ ++MV_VOID mvXorAddrDecShow(MV_VOID); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,75 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "device/mvDevice.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,74 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDeviceH ++#define __INCmvDeviceH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "device/mvDeviceRegs.h" ++ ++ ++#endif /* #ifndef __INCmvDeviceH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,101 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDeviceRegsH ++#define __INCmvDeviceRegsH ++ ++#ifndef MV_ASMLANGUAGE ++#include "ctrlEnv/mvCtrlEnvLib.h" ++/* This enumerator describes the Marvell controller possible devices that */ ++/* can be connected to its device interface. */ ++typedef enum _mvDevice ++{ ++#if defined(MV_INCLUDE_DEVICE_CS0) ++ DEV_CS0 = 0, /* Device connected to dev CS[0] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS1) ++ DEV_CS1 = 1, /* Device connected to dev CS[1] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS2) ++ DEV_CS2 = 2, /* Device connected to dev CS[2] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS3) ++ DEV_CS3 = 3, /* Device connected to dev CS[2] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS4) ++ DEV_CS4 = 4, /* Device connected to BOOT dev */ ++#endif ++ MV_DEV_MAX_CS = MV_DEVICE_MAX_CS ++}MV_DEVICE; ++ ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#define NAND_CTRL_REG 0x10470 ++ ++#define NAND_ACTCEBOOT_BIT BIT1 ++ ++ ++#endif /* #ifndef __INCmvDeviceRegsH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.5 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,211 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++/******************************************************************************* ++* mvOsCpuArchLib.c - Marvell CPU architecture library ++* ++* DESCRIPTION: ++* This library introduce Marvell API for OS dependent CPU architecture ++* APIs. This library introduce single CPU architecture services APKI ++* cross OS. ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#include ++#include "mvOs.h" ++ ++static MV_U32 read_p15_c0 (void); ++ ++/* defines */ ++#define ARM_ID_REVISION_OFFS 0 ++#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS) ++ ++#define ARM_ID_PART_NUM_OFFS 4 ++#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS) ++ ++#define ARM_ID_ARCH_OFFS 16 ++#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS) ++ ++#define ARM_ID_VAR_OFFS 20 ++#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS) ++ ++#define ARM_ID_ASCII_OFFS 24 ++#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS) ++ ++ ++ ++void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, ++ MV_U32 *memHandle) ++{ ++ void *p = kmalloc( size, GFP_KERNEL ); ++ *pPhyAddr = pci_map_single( osHandle, p, 0, PCI_DMA_BIDIRECTIONAL ); ++ return p; ++} ++void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, ++ MV_U32 *memHandle) ++{ ++ return pci_alloc_consistent( osHandle, size, (dma_addr_t *)pPhyAddr ); ++} ++ ++void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, ++ MV_U32 memHandle) ++{ ++ return pci_free_consistent( osHandle, size, pVirtAddr, (dma_addr_t)phyAddr ); ++} ++ ++void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, ++ MV_U32 memHandle ) ++{ ++ return kfree( pVirtAddr ); ++} ++ ++int mvOsRand(void) ++{ ++ int rand; ++ get_random_bytes(&rand, sizeof(rand) ); ++ return rand; ++} ++ ++/******************************************************************************* ++* mvOsCpuVerGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Revision ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuRevGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuPartGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Part number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuPartGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuArchGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Architicture number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuArchGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuVarGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Variant number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuVarGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuAsciiGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Variant number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuAsciiGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS); ++} ++ ++ ++ ++/* ++static unsigned long read_p15_c0 (void) ++*/ ++/* read co-processor 15, register #0 (ID register) */ ++static MV_U32 read_p15_c0 (void) ++{ ++ MV_U32 value; ++ ++ __asm__ __volatile__( ++ "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" ++ : "=r" (value) ++ : ++ : "memory"); ++ ++ return value; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,423 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++#ifndef _MV_OS_LNX_H_ ++#define _MV_OS_LNX_H_ ++ ++ ++#ifdef __KERNEL__ ++/* for kernel space */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "dbg-trace.h" ++ ++extern void mv_early_printk(char *fmt,...); ++ ++#define MV_ASM __asm__ __volatile__ ++#define INLINE inline ++#define MV_TRC_REC TRC_REC ++#define mvOsPrintf printk ++#define mvOsEarlyPrintf mv_early_printk ++#define mvOsOutput printk ++#define mvOsSPrintf sprintf ++#define mvOsMalloc(_size_) kmalloc(_size_,GFP_ATOMIC) ++#define mvOsFree kfree ++#define mvOsMemcpy memcpy ++#define mvOsSleep(_mils_) mdelay(_mils_) ++#define mvOsTaskLock() ++#define mvOsTaskUnlock() ++#define strtol simple_strtoul ++#define mvOsDelay(x) mdelay(x) ++#define mvOsUDelay(x) udelay(x) ++#define mvCopyFromOs copy_from_user ++#define mvCopyToOs copy_to_user ++ ++ ++#include "mvTypes.h" ++#include "mvCommon.h" ++ ++#ifdef MV_NDEBUG ++#define mvOsAssert(cond) ++#else ++#define mvOsAssert(cond) { do { if(!(cond)) { BUG(); } }while(0); } ++#endif /* MV_NDEBUG */ ++ ++#else /* __KERNEL__ */ ++ ++/* for user space applications */ ++#include ++#include ++#include ++#include ++ ++#define INLINE inline ++#define mvOsPrintf printf ++#define mvOsOutput printf ++#define mvOsMalloc(_size_) malloc(_size_) ++#define mvOsFree free ++#define mvOsAssert(cond) assert(cond) ++ ++#endif /* __KERNEL__ */ ++#define mvOsIoVirtToPhy(pDev, pVirtAddr) \ ++ pci_map_single( (pDev), (pVirtAddr), 0, PCI_DMA_BIDIRECTIONAL ) ++ ++#define mvOsCacheClear(pDev, p, size ) \ ++ pci_map_single( (pDev), (p), (size), PCI_DMA_BIDIRECTIONAL) ++ ++#define mvOsCacheFlush(pDev, p, size ) \ ++ pci_map_single( (pDev), (p), (size), PCI_DMA_TODEVICE) ++ ++#define mvOsCacheInvalidate(pDev, p, size) \ ++ pci_map_single( (pDev), (p), (size), PCI_DMA_FROMDEVICE ) ++ ++#define mvOsCacheUnmap(pDev, phys, size) \ ++ pci_unmap_single( (pDev), (dma_addr_t)(phys), (size), PCI_DMA_FROMDEVICE ) ++ ++ ++#define CPU_PHY_MEM(x) (MV_U32)x ++#define CPU_MEMIO_CACHED_ADDR(x) (void*)x ++#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x ++ ++ ++/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */ ++#define MV_MEMIO32_WRITE(addr, data) \ ++ ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data))) ++ ++#define MV_MEMIO32_READ(addr) \ ++ ((*((volatile unsigned int*)(addr)))) ++ ++#define MV_MEMIO16_WRITE(addr, data) \ ++ ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data))) ++ ++#define MV_MEMIO16_READ(addr) \ ++ ((*((volatile unsigned short*)(addr)))) ++ ++#define MV_MEMIO8_WRITE(addr, data) \ ++ ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data))) ++ ++#define MV_MEMIO8_READ(addr) \ ++ ((*((volatile unsigned char*)(addr)))) ++ ++ ++/* No Fast Swap implementation (in assembler) for ARM */ ++#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val) ++#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val) ++#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val) ++#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val) ++ ++/* 32 and 16 bit read/write in big/little endian mode */ ++ ++/* 16bit write in little endian mode */ ++#define MV_MEMIO_LE16_WRITE(addr, data) \ ++ MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data)) ++ ++/* 16bit read in little endian mode */ ++static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr) ++{ ++ MV_U16 data; ++ ++ data= (MV_U16)MV_MEMIO16_READ(addr); ++ ++ return (MV_U16)MV_16BIT_LE_FAST(data); ++} ++ ++/* 32bit write in little endian mode */ ++#define MV_MEMIO_LE32_WRITE(addr, data) \ ++ MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data)) ++ ++/* 32bit read in little endian mode */ ++static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr) ++{ ++ MV_U32 data; ++ ++ data= (MV_U32)MV_MEMIO32_READ(addr); ++ ++ return (MV_U32)MV_32BIT_LE_FAST(data); ++} ++ ++static __inline void mvOsBCopy(char* srcAddr, char* dstAddr, int byteCount) ++{ ++ while(byteCount != 0) ++ { ++ *dstAddr = *srcAddr; ++ dstAddr++; ++ srcAddr++; ++ byteCount--; ++ } ++} ++ ++static INLINE MV_U64 mvOsDivMod64(MV_U64 divided, MV_U64 divisor, MV_U64* modulu) ++{ ++ MV_U64 division = 0; ++ ++ if(divisor == 1) ++ return divided; ++ ++ while(divided >= divisor) ++ { ++ division++; ++ divided -= divisor; ++ } ++ if (modulu != NULL) ++ *modulu = divided; ++ ++ return division; ++} ++ ++#if defined(MV_BRIDGE_SYNC_REORDER) ++extern MV_U32 *mvUncachedParam; ++ ++static __inline void mvOsBridgeReorderWA(void) ++{ ++ volatile MV_U32 val = 0; ++ ++ val = mvUncachedParam[0]; ++} ++#endif ++ ++ ++/* Flash APIs */ ++#define MV_FL_8_READ MV_MEMIO8_READ ++#define MV_FL_16_READ MV_MEMIO_LE16_READ ++#define MV_FL_32_READ MV_MEMIO_LE32_READ ++#define MV_FL_8_DATA_READ MV_MEMIO8_READ ++#define MV_FL_16_DATA_READ MV_MEMIO16_READ ++#define MV_FL_32_DATA_READ MV_MEMIO32_READ ++#define MV_FL_8_WRITE MV_MEMIO8_WRITE ++#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE ++#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE ++#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE ++#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE ++#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE ++ ++ ++/* CPU cache information */ ++#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ ++#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ ++ ++#ifdef CONFIG_L2_CACHE_ENABLE ++/* Data cache flush one line */ ++#define mvOsCacheLineFlushInv(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c10, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ ++} ++ ++#else ++ ++/* Data cache flush one line */ ++#define mvOsCacheLineFlushInv(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ ++} ++#endif ++ ++#ifdef CONFIG_L2_CACHE_ENABLE ++#define mvOsCacheLineInv(handle,addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ ++ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c11, 1" : : "r" (addr)); \ ++} ++#else ++#define mvOsCacheLineInv(handle,addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ ++} ++#endif ++ ++#ifdef CONFIG_L2_CACHE_ENABLE ++/* Data cache flush one line */ ++#define mvOsCacheLineFlush(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c9, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ ++} ++ ++#else ++/* Data cache flush one line */ ++#define mvOsCacheLineFlush(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ ++} ++#endif ++ ++static __inline void mvOsPrefetch(const void *ptr) ++{ ++#ifdef CONFIG_USE_DSP ++ __asm__ __volatile__( ++ "pld\t%0" ++ : ++ : "o" (*(char *)ptr) ++ : "cc"); ++#else ++ return; ++#endif ++} ++ ++ ++/* Flush CPU pipe */ ++#define CPU_PIPE_FLUSH ++ ++ ++ ++ ++ ++/* register manipulations */ ++ ++/****************************************************************************** ++* This debug function enable the write of each register that u-boot access to ++* to an array in the DRAM, the function record only MV_REG_WRITE access. ++* The function could not be operate when booting from flash. ++* In order to print the array we use the printreg command. ++******************************************************************************/ ++/* #define REG_DEBUG */ ++#if defined(REG_DEBUG) ++extern int reg_arry[2048][2]; ++extern int reg_arry_index; ++#endif ++ ++/* Marvell controller register read/write macros */ ++#define MV_REG_VALUE(offset) \ ++ (MV_MEMIO32_READ((INTER_REGS_BASE | (offset)))) ++ ++#define MV_REG_READ(offset) \ ++ (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset))) ++ ++#if defined(REG_DEBUG) ++#define MV_REG_WRITE(offset, val) \ ++ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (val);\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_WRITE(offset, val) \ ++ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); ++#endif ++ ++#define MV_REG_BYTE_READ(offset) \ ++ (MV_MEMIO8_READ((INTER_REGS_BASE | (offset)))) ++ ++#if defined(REG_DEBUG) ++#define MV_REG_BYTE_WRITE(offset, val) \ ++ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (val);\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_BYTE_WRITE(offset, val) \ ++ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)) ++#endif ++ ++#if defined(REG_DEBUG) ++#define MV_REG_BIT_SET(offset, bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ ++ MV_32BIT_LE_FAST(bitMask)))); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_BIT_SET(offset, bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ ++ MV_32BIT_LE_FAST(bitMask)))) ++#endif ++ ++#if defined(REG_DEBUG) ++#define MV_REG_BIT_RESET(offset,bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ ++ MV_32BIT_LE_FAST(~bitMask)))); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_BIT_RESET(offset,bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ ++ MV_32BIT_LE_FAST(~bitMask)))) ++#endif ++ ++ ++ ++/* ARM architecture APIs */ ++MV_U32 mvOsCpuRevGet (MV_VOID); ++MV_U32 mvOsCpuPartGet (MV_VOID); ++MV_U32 mvOsCpuArchGet (MV_VOID); ++MV_U32 mvOsCpuVarGet (MV_VOID); ++MV_U32 mvOsCpuAsciiGet (MV_VOID); ++ ++/* Other APIs */ ++void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle); ++void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle ); ++void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); ++void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); ++int mvOsRand(void); ++ ++#endif /* _MV_OS_LNX_H_ */ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,158 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++/******************************************************************************* ++* mvOsLinux.h - O.S. interface header file for Linux ++* ++* DESCRIPTION: ++* This header file contains OS dependent definition under Linux ++* ++* DEPENDENCIES: ++* Linux kernel header files. ++* ++* FILE REVISION NUMBER: ++* $Revision: 1.1 $ ++*******************************************************************************/ ++ ++#ifndef __INCmvOsLinuxh ++#define __INCmvOsLinuxh ++ ++/* Includes */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include "mvOs.h" ++ ++ ++/* Definitions */ ++#define MV_DEFAULT_QUEUE_DEPTH 2 ++#define MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION ++#define MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN ++ ++#ifdef CONFIG_MV88F6082 ++ #define MV_SATA_OVERRIDE_SW_QUEUE_SIZE ++ #define MV_SATA_REQUESTED_SW_QUEUE_SIZE 2 ++ #undef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN ++#endif ++ ++/* System dependent macro for flushing CPU write cache */ ++#if defined (MV_BRIDGE_SYNC_REORDER) ++#define MV_CPU_WRITE_BUFFER_FLUSH() do { \ ++ wmb(); \ ++ mvOsBridgeReorderWA(); \ ++ } while (0) ++#else ++#define MV_CPU_WRITE_BUFFER_FLUSH() wmb() ++#endif /* CONFIG_MV78XX0 */ ++ ++/* System dependent little endian from / to CPU conversions */ ++#define MV_CPU_TO_LE16(x) cpu_to_le16(x) ++#define MV_CPU_TO_LE32(x) cpu_to_le32(x) ++ ++#define MV_LE16_TO_CPU(x) le16_to_cpu(x) ++#define MV_LE32_TO_CPU(x) le32_to_cpu(x) ++ ++#ifdef __BIG_ENDIAN_BITFIELD ++#define MV_BIG_ENDIAN_BITFIELD ++#endif ++ ++/* System dependent register read / write in byte/word/dword variants */ ++#define MV_REG_WRITE_BYTE(base, offset, val) writeb(val, base + offset) ++#define MV_REG_WRITE_WORD(base, offset, val) writew(val, base + offset) ++#define MV_REG_WRITE_DWORD(base, offset, val) writel(val, base + offset) ++#define MV_REG_READ_BYTE(base, offset) readb(base + offset) ++#define MV_REG_READ_WORD(base, offset) readw(base + offset) ++#define MV_REG_READ_DWORD(base, offset) readl(base + offset) ++ ++ ++/* Typedefs */ ++ ++/* System dependant typedefs */ ++typedef void *MV_VOID_PTR; ++typedef u32 *MV_U32_PTR; ++typedef u16 *MV_U16_PTR; ++typedef u8 *MV_U8_PTR; ++typedef char *MV_CHAR_PTR; ++typedef void *MV_BUS_ADDR_T; ++typedef unsigned long MV_CPU_FLAGS; ++ ++ ++/* Structures */ ++/* System dependent structure */ ++typedef struct mvOsSemaphore ++{ ++ int notUsed; ++} MV_OS_SEMAPHORE; ++ ++ ++/* Functions (User implemented)*/ ++ ++/* Semaphore init, take and release */ ++#define mvOsSemInit(x) MV_TRUE ++#define mvOsSemTake(x) ++#define mvOsSemRelease(x) ++ ++/* Interrupt masking and unmasking functions */ ++MV_CPU_FLAGS mvOsSaveFlagsAndMaskCPUInterrupts(MV_VOID); ++MV_VOID mvOsRestoreFlags(MV_CPU_FLAGS); ++ ++/* Delay function in micro seconds resolution */ ++void mvMicroSecondsDelay(MV_VOID_PTR, MV_U32); ++ ++/* Typedefs */ ++typedef enum mvBoolean ++{ ++ MV_SFALSE, MV_STRUE ++} MV_BOOLEAN; ++ ++/* System logging function */ ++#include "mvLog.h" ++/* Enable READ/WRITE Long SCSI command only when driver is compiled for debugging */ ++#ifdef MV_LOGGER ++#define MV_SATA_SUPPORT_READ_WRITE_LONG ++#endif ++ ++#define MV_IAL_LOG_ID 3 ++ ++#endif /* __INCmvOsLinuxh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,375 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++ ++*******************************************************************************/ ++/******************************************************************************* ++* mvSysHwCfg.h - Marvell system HW configuration file ++* ++* DESCRIPTION: ++* None. ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++#ifndef __INCmvSysHwConfigh ++#define __INCmvSysHwConfigh ++ ++#include "../../../../include/linux/autoconf.h" ++ ++#define CONFIG_MARVELL 1 ++ ++/* includes */ ++#define _1K 0x00000400 ++#define _4K 0x00001000 ++#define _8K 0x00002000 ++#define _16K 0x00004000 ++#define _32K 0x00008000 ++#define _64K 0x00010000 ++#define _128K 0x00020000 ++#define _256K 0x00040000 ++#define _512K 0x00080000 ++ ++#define _1M 0x00100000 ++#define _2M 0x00200000 ++#define _4M 0x00400000 ++#define _8M 0x00800000 ++#define _16M 0x01000000 ++#define _32M 0x02000000 ++#define _64M 0x04000000 ++#define _128M 0x08000000 ++#define _256M 0x10000000 ++#define _512M 0x20000000 ++ ++#define _1G 0x40000000 ++#define _2G 0x80000000 ++ ++/****************************************/ ++/* Soc supporeted Units definitions */ ++/****************************************/ ++ ++#ifdef CONFIG_MV_INCLUDE_PEX ++#define MV_INCLUDE_PEX ++#endif ++#ifdef CONFIG_MV_INCLUDE_TWSI ++#define MV_INCLUDE_TWSI ++#endif ++#ifdef CONFIG_MV_INCLUDE_CESA ++#define MV_INCLUDE_CESA ++#endif ++#ifdef CONFIG_MV_INCLUDE_GIG_ETH ++#define MV_INCLUDE_GIG_ETH ++#endif ++#ifdef CONFIG_MV_INCLUDE_INTEG_SATA ++#define MV_INCLUDE_INTEG_SATA ++#define MV_INCLUDE_SATA ++#endif ++#ifdef CONFIG_MV_INCLUDE_USB ++#define MV_INCLUDE_USB ++#define MV_USB_VOLTAGE_FIX ++#endif ++#ifdef CONFIG_MV_INCLUDE_NAND ++#define MV_INCLUDE_NAND ++#endif ++#ifdef CONFIG_MV_INCLUDE_TDM ++#define MV_INCLUDE_TDM ++#endif ++#ifdef CONFIG_MV_INCLUDE_XOR ++#define MV_INCLUDE_XOR ++#endif ++#ifdef CONFIG_MV_INCLUDE_TWSI ++#define MV_INCLUDE_TWSI ++#endif ++#ifdef CONFIG_MV_INCLUDE_UART ++#define MV_INCLUDE_UART ++#endif ++#ifdef CONFIG_MV_INCLUDE_SPI ++#define MV_INCLUDE_SPI ++#endif ++#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD ++#define MV_INCLUDE_SFLASH_MTD ++#endif ++#ifdef CONFIG_MV_INCLUDE_AUDIO ++#define MV_INCLUDE_AUDIO ++#endif ++#ifdef CONFIG_MV_INCLUDE_TS ++#define MV_INCLUDE_TS ++#endif ++#ifdef CONFIG_MV_INCLUDE_SDIO ++#define MV_INCLUDE_SDIO ++#endif ++ ++ ++/* NAND flash stuff */ ++#ifdef CONFIG_MV_NAND_BOOT ++#define MV_NAND_BOOT ++#endif ++#ifdef CONFIG_MV_NAND ++#define MV_NAND ++#endif ++ ++/* SPI flash stuff */ ++#ifdef CONFIG_MV_SPI_BOOT ++#define MV_SPI_BOOT ++#endif ++ ++ ++/****************************************************************/ ++/************* General configuration ********************/ ++/****************************************************************/ ++ ++/* Enable Clock Power Control */ ++#define MV_INCLUDE_CLK_PWR_CNTRL ++ ++/* Disable the DEVICE BAR in the PEX */ ++#define MV_DISABLE_PEX_DEVICE_BAR ++ ++/* Allow the usage of early printings during initialization */ ++#define MV_INCLUDE_EARLY_PRINTK ++ ++/****************************************************************/ ++/************* NFP configuration ********************************/ ++/****************************************************************/ ++#define MV_NFP_SEC_Q_SIZE 64 ++#define MV_NFP_SEC_REQ_Q_SIZE 1000 ++ ++ ++ ++/****************************************************************/ ++/************* CESA configuration ********************/ ++/****************************************************************/ ++ ++#ifdef MV_INCLUDE_CESA ++ ++#define MV_CESA_MAX_CHAN 4 ++ ++/* Use 2K of SRAM */ ++#define MV_CESA_MAX_BUF_SIZE 1600 ++ ++#endif /* MV_INCLUDE_CESA */ ++ ++#if defined(CONFIG_MV_INCLUDE_GIG_ETH) ++ ++#ifdef CONFIG_MV_NFP_STATS ++#define MV_FP_STATISTICS ++#else ++#undef MV_FP_STATISTICS ++#endif ++/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */ ++#define MV_ETH_SKB_REUSE_DEFAULT 1 ++/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ ++#define MV_ETH_TX_EN_DEFAULT 0 ++ ++/* un-comment if you want to perform tx_done from within the poll function */ ++/* #define ETH_TX_DONE_ISR */ ++ ++/* put descriptors in uncached memory */ ++/* #define ETH_DESCR_UNCACHED */ ++ ++/* Descriptors location: DRAM/internal-SRAM */ ++#define ETH_DESCR_IN_SDRAM ++#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ ++ ++#if defined(ETH_DESCR_IN_SRAM) ++#if defined(ETH_DESCR_UNCACHED) ++ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" ++#else ++ #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" ++#endif ++#elif defined(ETH_DESCR_IN_SDRAM) ++#if defined(ETH_DESCR_UNCACHED) ++ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" ++#else ++ #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" ++#endif ++#else ++ #error "Ethernet descriptors location undefined" ++#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ ++ ++/* SW Sync-Barrier: not relevant for 88fxx81*/ ++/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ ++/* In RX the CPU theoretically might see himself as the descriptor owner, */ ++/* although the buffer hadn't been written to DRAM yet. Performance cost. */ ++/* #define INCLUDE_SYNC_BARR */ ++ ++/* Buffers cache coherency method (buffers in DRAM) */ ++#ifndef MV_CACHE_COHER_SW ++/* Taken from mvCommon.h */ ++/* Memory uncached, HW or SW cache coherency is not needed */ ++#define MV_UNCACHED 0 ++/* Memory cached, HW cache coherency supported in WriteThrough mode */ ++#define MV_CACHE_COHER_HW_WT 1 ++/* Memory cached, HW cache coherency supported in WriteBack mode */ ++#define MV_CACHE_COHER_HW_WB 2 ++/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ ++#define MV_CACHE_COHER_SW 3 ++ ++#endif ++ ++/* DRAM cache coherency configuration */ ++#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW ++ ++ ++#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ ++ ++#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) ++ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" ++#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ++ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" ++#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) ++ #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" ++#elif (ETHER_DRAM_COHER == MV_UNCACHED) ++# define ETH_SDRAM_CONFIG_STR "DRAM uncached" ++#else ++ #error "Ethernet-DRAM undefined" ++#endif /* ETHER_DRAM_COHER */ ++ ++ ++/****************************************************************/ ++/************* Ethernet driver configuration ********************/ ++/****************************************************************/ ++ ++/* port's default queueus */ ++#define ETH_DEF_TXQ 0 ++#define ETH_DEF_RXQ 0 ++ ++#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM ++#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM ++ ++/* interrupt coalescing setting */ ++#define ETH_TX_COAL 200 ++#define ETH_RX_COAL 200 ++ ++/* Checksum offloading */ ++#define TX_CSUM_OFFLOAD ++#define RX_CSUM_OFFLOAD ++ ++#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ ++ ++/****************************************************************/ ++/*************** Telephony configuration ************************/ ++/****************************************************************/ ++#if defined(CONFIG_MV_TDM_LINEAR_MODE) ++ #define MV_TDM_LINEAR_MODE ++#elif defined(CONFIG_MV_TDM_ULAW_MODE) ++ #define MV_TDM_ULAW_MODE ++#endif ++ ++#if defined(CONFIG_MV_TDM_5CHANNELS) ++ #define MV_TDM_5CHANNELS ++#endif ++ ++#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) ++ #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE ++#endif ++ ++/* We use the following registers to store DRAM interface pre configuration */ ++/* auto-detection results */ ++/* IMPORTANT: We are using mask register for that purpose. Before writing */ ++/* to units mask register, make sure main maks register is set to disable */ ++/* all interrupts. */ ++#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ ++#define DRAM_BUF_REG1 0x30820 /* sdram config */ ++#define DRAM_BUF_REG2 0x30830 /* sdram mode */ ++#define DRAM_BUF_REG3 0x308c4 /* dunit control low */ ++#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ ++#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ ++#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ ++#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ ++#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ ++#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ ++#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ ++#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ ++#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */ ++#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */ ++#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */ ++ ++/* Following the pre-configuration registers default values restored after */ ++/* auto-detection is done */ ++#define DRAM_BUF_REG_DV 0 ++ ++/* System Mapping */ ++#define SDRAM_CS0_BASE 0x00000000 ++#define SDRAM_CS0_SIZE _256M ++ ++#define SDRAM_CS1_BASE 0x10000000 ++#define SDRAM_CS1_SIZE _256M ++ ++#define SDRAM_CS2_BASE 0x20000000 ++#define SDRAM_CS2_SIZE _256M ++ ++#define SDRAM_CS3_BASE 0x30000000 ++#define SDRAM_CS3_SIZE _256M ++ ++/* PEX */ ++#define PEX0_MEM_BASE 0xe8000000 ++#define PEX0_MEM_SIZE _128M ++ ++#define PEX0_IO_BASE 0xf2000000 ++#define PEX0_IO_SIZE _1M ++ ++/* Device Chip Selects */ ++#define NFLASH_CS_BASE 0xfa000000 ++#define NFLASH_CS_SIZE _2M ++ ++#define SPI_CS_BASE 0xf4000000 ++#define SPI_CS_SIZE _16M ++ ++#define CRYPT_ENG_BASE 0xf0000000 ++#define CRYPT_ENG_SIZE _2M ++ ++#define BOOTDEV_CS_BASE 0xff800000 ++#define BOOTDEV_CS_SIZE _8M ++ ++/* CS2 - BOOTROM */ ++#define DEVICE_CS2_BASE 0xff900000 ++#define DEVICE_CS2_SIZE _1M ++ ++/* PEX Work arround */ ++/* the target we will use for the workarround */ ++#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM ++/*a flag that indicates if we are going to use the ++size and base of the target we using for the workarround ++window */ ++#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 ++/* if the above flag is 0 then the following values ++will be used for the workarround window base and size, ++otherwise the following defines will be ignored */ ++#define PEX_CONFIG_RW_WA_BASE 0xF3000000 ++#define PEX_CONFIG_RW_WA_SIZE _16M ++ ++/* Internal registers: size is defined in Controllerenvironment */ ++#define INTER_REGS_BASE 0xFEE00000 ++ ++/* DRAM detection stuff */ ++#define MV_DRAM_AUTO_SIZE ++ ++/* Board clock detection */ ++#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ ++#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ ++#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ ++#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */ ++ ++/* PEX-PCI\PCI-PCI Bridge*/ ++#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/ ++ ++ ++ ++#endif /* __INCmvSysHwConfigh */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,376 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvCntmr.h" ++#include "cpu/mvCpu.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++extern unsigned int whoAmI(void); ++ ++/******************************************************************************* ++* mvCntmrLoad - ++* ++* DESCRIPTION: ++* Load an init Value to a given counter/timer ++* ++* INPUT: ++* countNum - counter number ++* value - value to be loaded ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value) ++{ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ mvOsPrintf(("mvCntmrLoad: Err. Illigal counter number \n")); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ MV_REG_WRITE(CNTMR_RELOAD_REG(countNum),value); ++ MV_REG_WRITE(CNTMR_VAL_REG(countNum),value); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrRead - ++* ++* DESCRIPTION: ++* Returns the value of the given Counter/Timer ++* ++* INPUT: ++* countNum - counter number ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 counter value ++*******************************************************************************/ ++MV_U32 mvCntmrRead(MV_U32 countNum) ++{ ++ return MV_REG_READ(CNTMR_VAL_REG(countNum)); ++} ++ ++/******************************************************************************* ++* mvCntmrWrite - ++* ++* DESCRIPTION: ++* Returns the value of the given Counter/Timer ++* ++* INPUT: ++* countNum - counter number ++* countVal - value to write ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None ++*******************************************************************************/ ++void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal) ++{ ++ MV_REG_WRITE(CNTMR_VAL_REG(countNum),countVal); ++} ++ ++/******************************************************************************* ++* mvCntmrCtrlSet - ++* ++* DESCRIPTION: ++* Set the Control to a given counter/timer ++* ++* INPUT: ++* countNum - counter number ++* pCtrl - pointer to MV_CNTMR_CTRL structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ DB(mvOsPrintf(("mvCntmrCtrlSet: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ ++ if (pCtrl->enable) /* enable counter\timer */ ++ { ++ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); ++ } ++ else /* disable counter\timer */ ++ { ++ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); ++ } ++ ++ if ( pCtrl->autoEnable ) /* Auto mode */ ++ { ++ cntmrCtrl |= CTCR_ARM_TIMER_AUTO_EN(countNum); ++ ++ } ++ else /* no auto mode */ ++ { ++ cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(countNum); ++ } ++ ++ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCntmrCtrlGet - ++* ++* DESCRIPTION: ++* Get the Control value of a given counter/timer ++* ++* INPUT: ++* countNum - counter number ++* pCtrl - pointer to MV_CNTMR_CTRL structure ++* ++* OUTPUT: ++* Counter\Timer control value ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ DB(mvOsPrintf(("mvCntmrCtrlGet: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ /* enable counter\timer */ ++ if (cntmrCtrl & CTCR_ARM_TIMER_EN(countNum)) ++ { ++ pCtrl->enable = MV_TRUE; ++ } ++ else ++ { ++ pCtrl->enable = MV_FALSE; ++ } ++ ++ /* counter mode */ ++ if (cntmrCtrl & CTCR_ARM_TIMER_AUTO_EN(countNum)) ++ { ++ pCtrl->autoEnable = MV_TRUE; ++ } ++ else ++ { ++ pCtrl->autoEnable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrEnable - ++* ++* DESCRIPTION: ++* Set the Enable-Bit to logic '1' ==> starting the counter ++* ++* INPUT: ++* countNum - counter number ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrEnable(MV_U32 countNum) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ DB(mvOsPrintf(("mvCntmrEnable: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ /* enable counter\timer */ ++ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); ++ ++ ++ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrDisable - ++* ++* DESCRIPTION: ++* Stop the counter/timer running, and returns its Value ++* ++* INPUT: ++* countNum - counter number ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 counter\timer value ++*******************************************************************************/ ++MV_STATUS mvCntmrDisable(MV_U32 countNum) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ DB(mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ /* disable counter\timer */ ++ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); ++ ++ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrStart - ++* ++* DESCRIPTION: ++* Combined all the sub-operations above to one function: Load,setMode,Enable ++* ++* INPUT: ++* countNum - counter number ++* value - value of the counter\timer to be set ++* pCtrl - pointer to MV_CNTMR_CTRL structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, ++ MV_CNTMR_CTRL *pCtrl) ++{ ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n")); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* load value onto counter\timer */ ++ mvCntmrLoad(countNum,value); ++ ++ /* set the counter to load in the first time */ ++ mvCntmrWrite(countNum,value); ++ ++ /* set control for timer \ cunter and enable */ ++ mvCntmrCtrlSet(countNum,pCtrl); ++ ++ return MV_OK; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,121 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvTmrWtdgh ++#define __INCmvTmrWtdgh ++ ++/* includes */ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "cntmr/mvCntmrRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++ ++/* This enumerator describe counters\watchdog numbers */ ++typedef enum _mvCntmrID ++{ ++ TIMER0 = 0, ++ TIMER1, ++ WATCHDOG, ++ TIMER2, ++ TIMER3, ++}MV_CNTMR_ID; ++ ++ ++/* Counter / Timer control structure */ ++typedef struct _mvCntmrCtrl ++{ ++ MV_BOOL enable; /* enable */ ++ MV_BOOL autoEnable; /* counter/Timer */ ++}MV_CNTMR_CTRL; ++ ++ ++/* Functions */ ++ ++/* Load an init Value to a given counter/timer */ ++MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value); ++ ++/* Returns the value of the given Counter/Timer */ ++MV_U32 mvCntmrRead(MV_U32 countNum); ++ ++/* Write a value of the given Counter/Timer */ ++void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal); ++ ++/* Set the Control to a given counter/timer */ ++MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); ++ ++/* Get the value of a given counter/timer */ ++MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); ++ ++/* Set the Enable-Bit to logic '1' ==> starting the counter. */ ++MV_STATUS mvCntmrEnable(MV_U32 countNum); ++ ++/* Stop the counter/timer running, and returns its Value. */ ++MV_STATUS mvCntmrDisable(MV_U32 countNum); ++ ++/* Combined all the sub-operations above to one function: Load,setMode,Enable */ ++MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, ++ MV_CNTMR_CTRL *pCtrl); ++ ++#endif /* __INCmvTmrWtdgh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,121 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvTmrwtdgRegsh ++#define __INCmvTmrwtdgRegsh ++ ++/*******************************************/ ++/* ARM Timers Registers Map */ ++/*******************************************/ ++ ++#define CNTMR_RELOAD_REG(tmrNum) (CNTMR_BASE + 0x10 + (tmrNum)*8 + \ ++ (((tmrNum) <= 3)?0:8)) ++#define CNTMR_VAL_REG(tmrNum) (CNTMR_BASE + 0x14 + (tmrNum)*8 + \ ++ (((tmrNum) <= 3)?0:8)) ++#define CNTMR_CTRL_REG (CNTMR_BASE) ++ ++/*For MV78XX0*/ ++#define CNTMR_CAUSE_REG (CPU_AHB_MBUS_CAUSE_INT_REG(whoAmI())) ++#define CNTMR_MASK_REG (CPU_AHB_MBUS_MASK_INT_REG(whoAmI())) ++ ++/* ARM Timers Registers Map */ ++/*******************************************/ ++ ++ ++/* ARM Timers Control Register */ ++/* CPU_TIMERS_CTRL_REG (CTCR) */ ++ ++#define TIMER0_NUM 0 ++#define TIMER1_NUM 1 ++#define WATCHDOG_NUM 2 ++#define TIMER2_NUM 3 ++#define TIMER3_NUM 4 ++ ++#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) ++#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) ++#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) ++#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) ++ ++#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) ++#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1 ++#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) ++#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) ++ ++ ++/* ARM Timer\Watchdog Reload Register */ ++/* CNTMR_RELOAD_REG (TRR) */ ++ ++#define TRG_ARM_TIMER_REL_OFFS 0 ++#define TRG_ARM_TIMER_REL_MASK 0xffffffff ++ ++/* ARM Timer\Watchdog Register */ ++/* CNTMR_VAL_REG (TVRG) */ ++ ++#define TVR_ARM_TIMER_OFFS 0 ++#define TVR_ARM_TIMER_MASK 0xffffffff ++#define TVR_ARM_TIMER_MAX 0xffffffff ++ ++ ++ ++#endif /* __INCmvTmrwtdgRegsh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.3 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,207 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include "mvOs.h" ++#include "mvCpuCntrs.h" ++ ++ ++const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] = ++{ ++ /*0*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS, ++ MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY, ++ MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, ++ }, ++ /*1*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS, ++ MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, ++ }, ++ /*2*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS, ++ MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, ++ }, ++ /*3*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS, ++ MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS, ++ MV_CPU_CNTRS_INVALID, ++ } ++}; ++ ++MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; ++ ++MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128]; ++ ++void mvCpuCntrsReset(void) ++{ ++ MV_U32 reg = 0; ++ ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg)); ++} ++ ++void program_counter(int counter, int op) ++{ ++ MV_U32 reg = (1 << op) | 0x1; /*enable*/ ++ ++ switch(counter) ++ { ++ case 0: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg)); ++ return; ++ ++ case 1: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg)); ++ return; ++ ++ case 2: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg)); ++ return; ++ ++ case 3: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg)); ++ return; ++ ++ default: ++ mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); ++ } ++ return; ++} ++ ++void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++ for(i=0; icounters_sum[i] = 0; ++ } ++ pEvent->num_of_measurements = 0; ++} ++ ++ ++MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold) ++{ ++ int i; ++ MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT)); ++ ++ if(event) ++ { ++ strncpy(event->name, name, sizeof(event->name)); ++ event->num_of_measurements = 0; ++ event->avg_sample_count = print_threshold; ++ for(i=0; icounters_before[i] = 0; ++ event->counters_after[i] = 0; ++ event->counters_sum[i] = 0; ++ } ++ } ++ return event; ++} ++ ++void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event) ++{ ++ if(event != NULL) ++ mvOsFree(event); ++} ++ ++ ++MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, ++ char* name, MV_U32 overhead) ++{ ++ int i; ++ ++ /* Find required operations */ ++ for(i=0; inum_of_measurements < pEvent->avg_sample_count) ++ return; ++ ++ mvOsPrintf("%16s: ", pEvent->name); ++ for(i=0; icounters_sum[i], ++ pEvent->num_of_measurements, NULL); ++ if(counters_avg >= mvCpuCntrsTbl[i].overhead) ++ counters_avg -= mvCpuCntrsTbl[i].overhead; ++ else ++ counters_avg = 0; ++ ++ mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg); ++ } ++ mvOsPrintf("\n"); ++ mvCpuCntrsEventClear(pEvent); ++ mvCpuCntrsReset(); ++} ++ ++void mvCpuCntrsStatus(void) ++{ ++ int i; ++ ++ for(i=0; icounters_before[i] = mvCpuCntrsRead(i); ++#else ++ pEvent->counters_before[1] = mvCpuCntrsRead(1); ++ pEvent->counters_before[3] = mvCpuCntrsRead(3); ++ pEvent->counters_before[0] = mvCpuCntrsRead(0); ++ pEvent->counters_before[2] = mvCpuCntrsRead(2); ++#endif ++} ++ ++static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++#if 0 ++ /* order is important - we want to measure the cycle count first here! */ ++ for(i=0; icounters_after[i] = mvCpuCntrsRead(i); ++#else ++ pEvent->counters_after[2] = mvCpuCntrsRead(2); ++ pEvent->counters_after[0] = mvCpuCntrsRead(0); ++ pEvent->counters_after[3] = mvCpuCntrsRead(3); ++ pEvent->counters_after[1] = mvCpuCntrsRead(1); ++#endif ++ ++ for(i=0; icounters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); ++ } ++ pEvent->num_of_measurements++; ++} ++ ++ ++#ifdef CONFIG_MV_CPU_PERF_CNTRS ++ ++#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter) ++ ++#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event) ++ ++#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event) ++ ++#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event) ++ ++#else ++ ++#define MV_CPU_CNTRS_READ(counter) ++#define MV_CPU_CNTRS_START(event) ++#define MV_CPU_CNTRS_STOP(event) ++#define MV_CPU_CNTRS_SHOW(event) ++ ++#endif /* CONFIG_MV_CPU_PERF_CNTRS */ ++ ++ ++#endif /* __mvCpuCntrs_h__ */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,143 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include "mvOs.h" ++#include "mvCpuL2Cntrs.h" ++ ++ ++ ++MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM]; ++ ++MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128]; ++ ++void mvCpuL2CntrsReset(void) ++{ ++ MV_U32 reg = 0; ++ ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg)); ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg)); ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg)); ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg)); ++} ++ ++static void mvCpuL2CntrConfig(int counter, int op) ++{ ++ MV_U32 reg = (1 << op) | 0x1; /*enable*/ ++ ++ switch(counter) ++ { ++ case 0: ++ MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg)); ++ return; ++ ++ case 1: ++ MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg)); ++ return; ++ ++ default: ++ mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter); ++ } ++ return; ++} ++ ++void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++ for(i=0; icounters_sum[i] = 0; ++ } ++ pEvent->num_of_measurements = 0; ++} ++ ++ ++MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold) ++{ ++ int i; ++ MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT)); ++ ++ if(event) ++ { ++ strncpy(event->name, name, sizeof(event->name)); ++ event->num_of_measurements = 0; ++ event->avg_sample_count = print_threshold; ++ for(i=0; icounters_before[i] = 0; ++ event->counters_after[i] = 0; ++ event->counters_sum[i] = 0; ++ } ++ } ++ return event; ++} ++ ++void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event) ++{ ++ if(event != NULL) ++ mvOsFree(event); ++} ++ ++ ++MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, ++ char* name, MV_U32 overhead) ++{ ++ strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name)); ++ mvCpuL2CntrsTbl[counter].operation = op; ++ mvCpuL2CntrsTbl[counter].opIdx = op; ++ mvCpuL2CntrsTbl[counter].overhead = overhead; ++ mvCpuL2CntrConfig(counter, op); ++ mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n", ++ counter, op, overhead); ++ return MV_OK; ++} ++ ++void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ MV_U64 counters_avg; ++ ++ if(pEvent->num_of_measurements < pEvent->avg_sample_count) ++ return; ++ ++ mvOsPrintf("%16s: ", pEvent->name); ++ for(i=0; icounters_sum[i], ++ pEvent->num_of_measurements, NULL); ++ ++ if(counters_avg >= mvCpuL2CntrsTbl[i].overhead) ++ counters_avg -= mvCpuL2CntrsTbl[i].overhead; ++ else ++ counters_avg = 0; ++ ++ mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg); ++ } ++ mvOsPrintf("\n"); ++ mvCpuL2CntrsEventClear(pEvent); ++ mvCpuL2CntrsReset(); ++} ++ ++void mvCpuL2CntrsStatus(void) ++{ ++ int i; ++ ++ for(i=0; icounters_before[i] = mvCpuL2CntrsRead(i); ++} ++ ++static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++ for(i=0; icounters_after[i] = mvCpuL2CntrsRead(i); ++ pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); ++ } ++ pEvent->num_of_measurements++; ++} ++ ++ ++#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS ++ ++#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter) ++ ++#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event) ++ ++#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event) ++ ++#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event) ++ ++#else ++ ++#define MV_CPU_L2_CNTRS_READ(counter) ++#define MV_CPU_L2_CNTRS_START(event) ++#define MV_CPU_L2_CNTRS_STOP(event) ++#define MV_CPU_L2_CNTRS_SHOW(event) ++ ++#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */ ++ ++ ++#endif /* __mvCpuL2Cntrs_h__ */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.3 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1479 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "ddr1_2/mvDram.h" ++#include "boardEnv/mvBoardEnvLib.h" ++ ++#undef MV_DEBUG ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, ++ MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 cas2ps(MV_U8 spd_byte); ++/******************************************************************************* ++* mvDramBankGet - Get the DRAM bank paramters. ++* ++* DESCRIPTION: ++* This function retrieves DRAM bank parameters as described in ++* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board ++* has its DRAM on DIMMs it will use its EEPROM to extract SPD data ++* from it. Otherwise, if the DRAM is soldered on board, the function ++* should insert its bank information into MV_DRAM_BANK_INFO struct. ++* ++* INPUT: ++* bankNum - Board DRAM bank number. ++* ++* OUTPUT: ++* pBankInfo - DRAM bank information struct. ++* ++* RETURN: ++* MV_FAIL - Bank parameters could not be read. ++* ++*******************************************************************************/ ++MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_DIMM_INFO dimmInfo; ++ ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); ++ /* zero pBankInfo structure */ ++ memset(pBankInfo, 0, sizeof(*pBankInfo)); ++ ++ if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); ++ return MV_FAIL; ++ } ++ if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); ++ return MV_FAIL; ++ } ++ ++ /* convert Dimm info to Bank info */ ++ cpyDimm2BankInfo(&dimmInfo, pBankInfo); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. ++* ++* DESCRIPTION: ++* Convert a Dimm info struct into a bank info struct. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* pBankInfo - DRAM bank information struct. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, ++ MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ pBankInfo->memoryType = pDimmInfo->memoryType; ++ ++ /* DIMM dimensions */ ++ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; ++ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; ++ pBankInfo->dataWidth = pDimmInfo->dataWidth; ++ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; ++ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; ++ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; ++ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; ++ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; ++ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; ++ ++ /* DIMM timing parameters */ ++ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; ++ ++ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; ++ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; ++ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; ++ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; ++ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; ++ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; ++ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; ++ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; ++ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; ++ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / ++ pDimmInfo->numOfModuleBanks; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ ++ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || ++ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) ++ { ++ if (pDimmInfo->dimmAttributes & BIT1) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ ++ { ++ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ ++ return; ++} ++ ++/******************************************************************************* ++* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdCpy(MV_VOID) ++{ ++ MV_U32 i; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, ++ &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the DIMM 1 SPD */ ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ twsiSlave.offset = i; ++ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, ++ &twsiSlave, &data[i], 1) ) ++ { ++ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); ++ return MV_FAIL; ++ } ++ mvOsDelay(5); ++ } ++ ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdGet - Get the SPD parameters. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters into given struct parameter. ++* ++* INPUT: ++* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. ++* ++* OUTPUT: ++* pDimmInfo - DIMM information structure. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) ++{ ++ MV_U32 i; ++ MV_U32 density = 1; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = (dimmNum == 0) ? ++ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, ++ &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the dimmInfo structure*/ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ pDimmInfo->spdRawData[i] = data[i]; ++ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); ++ } ++ ++ DB(mvOsPrintf("DRAM SPD Information:\n")); ++ ++ /* Memory type (DDR / SDRAM) */ ++ switch (data[DIMM_MEM_TYPE]) ++ { ++ case (DIMM_MEM_TYPE_SDRAM): ++ pDimmInfo->memoryType = MEM_TYPE_SDRAM; ++ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR1): ++ pDimmInfo->memoryType = MEM_TYPE_DDR1; ++ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR2): ++ pDimmInfo->memoryType = MEM_TYPE_DDR2; ++ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); ++ break; ++ default: ++ mvOsPrintf("ERROR: Undefined memory type!\n"); ++ return MV_ERROR; ++ } ++ ++ ++ /* Number Of Row Addresses */ ++ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; ++ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); ++ ++ /* Number Of Column Addresses */ ++ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; ++ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); ++ ++ /* Number Of Module Banks */ ++ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", ++ pDimmInfo->numOfModuleBanks)); ++ ++ /* Number of module banks encoded differently for DDR2 */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; ++ ++ /* Data Width */ ++ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); ++ ++ /* Minimum Cycle Time At Max CasLatancy */ ++ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); ++ ++ /* Error Check Type */ ++ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; ++ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", ++ pDimmInfo->errorCheckType)); ++ ++ /* Refresh Interval */ ++ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; ++ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", ++ pDimmInfo->refreshInterval)); ++ ++ /* Sdram Width */ ++ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; ++ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); ++ ++ /* Error Check Data Width */ ++ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", ++ pDimmInfo->errorCheckDataWidth)); ++ ++ /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; ++ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", ++ pDimmInfo->burstLengthSupported)); ++ ++ /* Number Of Banks On Each Device */ ++ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", ++ pDimmInfo->numOfBanksOnEachDevice)); ++ ++ /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; ++ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", ++ pDimmInfo->suportedCasLatencies)); ++ ++ /* For DDR2 only, get the DIMM type information */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ { ++ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; ++ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", ++ pDimmInfo->dimmTypeInfo)); ++ } ++ ++ /* SDRAM Modules Attributes */ ++ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; ++ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", ++ pDimmInfo->dimmAttributes)); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); ++ ++ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; ++ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", ++ pDimmInfo->minRowPrechargeTime)); ++ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; ++ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", ++ pDimmInfo->minRowActiveToRowActive)); ++ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; ++ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", ++ pDimmInfo->minRasToCasDelay)); ++ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; ++ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", ++ pDimmInfo->minRasPulseWidth)); ++ ++ /* DIMM Bank Density */ ++ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; ++ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", ++ pDimmInfo->dimmBankDensity)); ++ ++ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ ++ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; ++ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", ++ pDimmInfo->minWriteRecoveryTime)); ++ ++ /* Only DDR2 includes Internal Write To Read Command Delay field. */ ++ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", ++ pDimmInfo->minWriteToReadCmdDelay)); ++ ++ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ ++ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", ++ pDimmInfo->minReadToPrechCmdDelay)); ++ ++ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ ++ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; ++ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", ++ pDimmInfo->minRefreshToActiveCmd)); ++ ++ /* calculating the sdram density. Representing device density from */ ++ /* bit 20 to allow representation of 4GB and above. */ ++ /* For example, if density is 512Mbit 0x20000000, will be represent in */ ++ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ ++ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ ++ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); ++ pDimmInfo->deviceDensity = density * ++ pDimmInfo->numOfBanksOnEachDevice * ++ pDimmInfo->sdramWidth; ++ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); ++ ++ /* Number of devices includeing Error correction */ ++ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * ++ pDimmInfo->numOfModuleBanks; ++ DB(mvOsPrintf("DRAM numberOfDevices %d\n", ++ pDimmInfo->numberOfDevices)); ++ ++ pDimmInfo->size = 0; ++ ++ /* Note that pDimmInfo->size is in MB units */ ++ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 8; /* Equal to 8MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 4096; /* Equal to 4GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 8192; /* Equal to 8GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 16384; /* Equal to 16GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ ++ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; ++ ++ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdPrint - Print the SPD parameters. ++* ++* DESCRIPTION: ++* Print the Dimm SPD parameters. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID dimmSpdPrint(MV_U32 dimmNum) ++{ ++ MV_DIMM_INFO dimmInfo; ++ MV_U32 i, temp = 0; ++ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; ++ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; ++ MV_U32 busClkPs; ++ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, ++ temp_buf[40], *spdRawData; ++ ++ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ ++ ++ spdRawData = dimmInfo.spdRawData; ++ ++ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) ++ { ++ mvOsOutput("ERROR: Could not read SPD information!\n"); ++ return; ++ } ++ ++ /* find Manufactura of Dimm Module */ ++ mvOsOutput("\nManufacturer's JEDEC ID Code: "); ++ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) ++ { ++ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); ++ } ++ mvOsOutput("\n"); ++ ++ /* Manufacturer's Specific Data */ ++ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; ++ } ++ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); ++ ++ /* Module Part Number */ ++ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; ++ } ++ mvOsOutput("Module Part Number: %s\n", temp_buf); ++ ++ /* Module Serial Number */ ++ for(i = 0; i < sizeof(MV_U32); i++) ++ { ++ temp |= spdRawData[95+i] << 8*i; ++ } ++ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, ++ (long)temp); ++ ++ /* find Manufac-Data of Dimm Module */ ++ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", ++ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), ++ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); ++ /* find modul_revision of Dimm Module */ ++ mvOsOutput("Module Revision: %d.%d\n", ++ spdRawData[91], spdRawData[92]); ++ ++ /* find manufac_place of Dimm Module */ ++ mvOsOutput("manufac_place: %d\n", spdRawData[72]); ++ ++ /* go over the first 35 I2C data bytes */ ++ for(i = 2 ; i <= 35 ; i++) ++ switch(i) ++ { ++ case 2: /* Memory type (DDR1/2 / SDRAM) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ mvOsOutput("Dram Type is: SDRAM\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ mvOsOutput("Dram Type is: SDRAM DDR1\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ mvOsOutput("Dram Type is: SDRAM DDR2\n"); ++ else ++ mvOsOutput("Dram Type unknown\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 3: /* Number Of Row Addresses */ ++ mvOsOutput("Module Number of row addresses: %d\n", ++ dimmInfo.numOfRowAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 4: /* Number Of Column Addresses */ ++ mvOsOutput("Module Number of col addresses: %d\n", ++ dimmInfo.numOfColAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 5: /* Number Of Module Banks */ ++ mvOsOutput("Number of Banks on Mod.: %d\n", ++ dimmInfo.numOfModuleBanks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 6: /* Data Width */ ++ mvOsOutput("Module Data Width: %d bit\n", ++ dimmInfo.dataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 8: /* Voltage Interface */ ++ switch(spdRawData[i]) ++ { ++ case 0x0: ++ mvOsOutput("Module is TTL_5V_TOLERANT\n"); ++ break; ++ case 0x1: ++ mvOsOutput("Module is LVTTL\n"); ++ break; ++ case 0x2: ++ mvOsOutput("Module is HSTL_1_5V\n"); ++ break; ++ case 0x3: ++ mvOsOutput("Module is SSTL_3_3V\n"); ++ break; ++ case 0x4: ++ mvOsOutput("Module is SSTL_2_5V\n"); ++ break; ++ case 0x5: ++ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) ++ { ++ mvOsOutput("Module is SSTL_1_8V\n"); ++ break; ++ } ++ default: ++ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); ++ break; ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 9: /* Minimum Cycle Time At Max CasLatancy */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 10: /* Clock To Data Out */ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 11: /* Error Check Type */ ++ mvOsOutput("Error Check Type (0=NONE): %d\n", ++ dimmInfo.errorCheckType); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 12: /* Refresh Interval */ ++ mvOsOutput("Refresh Rate: %x\n", ++ dimmInfo.refreshInterval); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 13: /* Sdram Width */ ++ mvOsOutput("Sdram Width: %d bits\n", ++ dimmInfo.sdramWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 14: /* Error Check Data Width */ ++ mvOsOutput("Error Check Data Width: %d bits\n", ++ dimmInfo.errorCheckDataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 15: /* Minimum Clock Delay is unsupported */ ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ mvOsOutput("Minimum Clk Delay back to back: %d\n", ++ spdRawData[i]); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 16: /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ mvOsOutput("Burst Length Supported: "); ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ if (dimmInfo.burstLengthSupported & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.burstLengthSupported & BIT1) ++ mvOsOutput("2, "); ++ } ++ if (dimmInfo.burstLengthSupported & BIT2) ++ mvOsOutput("4, "); ++ if (dimmInfo.burstLengthSupported & BIT3) ++ mvOsOutput("8, "); ++ ++ mvOsOutput(" Bit \n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 17: /* Number Of Banks On Each Device */ ++ mvOsOutput("Number Of Banks On Each Chip: %d\n", ++ dimmInfo.numOfBanksOnEachDevice); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 18: /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ mvOsOutput("Suported Cas Latencies: (CL) "); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ for (k = 0; k <=7; k++) ++ { ++ if (dimmInfo.suportedCasLatencies & (1 << k)) ++ mvOsOutput("%d, ", k+1); ++ } ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.suportedCasLatencies & BIT1) ++ mvOsOutput("1.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("2.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("3.5, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("4, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("5, "); ++ } ++ else ++ mvOsOutput("?.?, "); ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 20: /* DDR2 DIMM type info */ ++ if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) ++ mvOsOutput("Registered DIMM (RDIMM)\n"); ++ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) ++ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); ++ else ++ mvOsOutput("Unknown DIMM type.\n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 21: /* SDRAM Modules Attributes */ ++ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" Bufferd DQMB Input: Yes \n"); ++ else ++ mvOsOutput(" Bufferd DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" Registered DQMB Inputs: Yes \n"); ++ else ++ mvOsOutput(" Registered DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" redundant Row Addressing: Yes \n"); ++ else ++ mvOsOutput(" redundant Row Addressing: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch On-Card Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", ++ (dimmInfo.dimmAttributes & 0x3) + 1); ++ ++ mvOsOutput(" Number of PLLs on the DIMM: %d\n", ++ ((dimmInfo.dimmAttributes) >> 2) & 0x3); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" Analysis probe installed: Yes \n"); ++ else ++ mvOsOutput(" Analysis probe installed: No \n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 22: /* Suported AutoPreCharge */ ++ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Early Ras Precharge: Yes \n"); ++ else ++ mvOsOutput(" Early Ras Precharge: No \n"); ++ ++ if ( spdRawData[i] & BIT1 ) ++ mvOsOutput(" AutoPreCharge: Yes \n"); ++ else ++ mvOsOutput(" AutoPreCharge: No \n"); ++ ++ if ( spdRawData[i] & BIT2 ) ++ mvOsOutput(" Precharge All: Yes \n"); ++ else ++ mvOsOutput(" Precharge All: No \n"); ++ ++ if ( spdRawData[i] & BIT3 ) ++ mvOsOutput(" Write 1/ReadBurst: Yes \n"); ++ else ++ mvOsOutput(" Write 1/ReadBurst: No \n"); ++ ++ if ( spdRawData[i] & BIT4 ) ++ mvOsOutput(" lower VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" lower VCC tolerance: 10%%\n"); ++ ++ if ( spdRawData[i] & BIT5 ) ++ mvOsOutput(" upper VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" upper VCC tolerance: 10%%\n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ ++ if ( !(spdRawData[i] & BIT4) ) ++ mvOsOutput(" lower VCC tolerance: 0.2V\n"); ++ ++ if ( !(spdRawData[i] & BIT5) ) ++ mvOsOutput(" upper VCC tolerance: 0.2V\n"); ++ ++ if ( spdRawData[i] & BIT6 ) ++ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); ++ else ++ mvOsOutput(" Concurrent Auto Preharge: No \n"); ++ ++ if ( spdRawData[i] & BIT7 ) ++ mvOsOutput(" Supports Fast AP: Yes \n"); ++ else ++ mvOsOutput(" Supports Fast AP: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 23: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ ++ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 25: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ } ++ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = 0; ++ rightOfPoint = time_tmp; ++ } ++ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 27: /* Minimum Row Precharge Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ ++ trp_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 28: /* Minimum Row Active to Row Active Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " ++ "%d.%d = in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 29: /* Minimum Ras-To-Cas Delay */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; ++ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 30: /* Minimum Ras Pulse Width */ ++ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " ++ "in Clk cycles %d\n", spdRawData[i], tras_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 31: /* Module Bank Density */ ++ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("8MB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("4GB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("8GB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("16GB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 32: /* Address And Command Setup Time (measured in ns/1000) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 33: /* Address And Command Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 34: /* Data Input Setup Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 35: /* Data Input Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 36: /* Relevant for DDR2 only: Write Recovery Time */ ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; ++ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ } ++ ++} ++ ++ ++/* ++ * translate ns.ns/10 coding of SPD timing values ++ * into ps unit values ++ */ ++/******************************************************************************* ++* cas2ps - Translate x.y ns parameter to pico-seconds values ++* ++* DESCRIPTION: ++* This function translates x.y nano seconds to its value in pico seconds. ++* For example 3.75ns will return 3750. ++* ++* INPUT: ++* spd_byte - DIMM SPD byte. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* value in pico seconds. ++* ++*******************************************************************************/ ++static MV_U32 cas2ps(MV_U8 spd_byte) ++{ ++ MV_U32 ns, ns10; ++ ++ /* isolate upper nibble */ ++ ns = (spd_byte >> 4) & 0x0F; ++ /* isolate lower nibble */ ++ ns10 = (spd_byte & 0x0F); ++ ++ if( ns10 < 10 ) { ++ ns10 *= 10; ++ } ++ else if( ns10 == 10 ) ++ ns10 = 25; ++ else if( ns10 == 11 ) ++ ns10 = 33; ++ else if( ns10 == 12 ) ++ ns10 = 66; ++ else if( ns10 == 13 ) ++ ns10 = 75; ++ else ++ { ++ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); ++ } ++ ++ return (ns*1000 + ns10*10); ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,191 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDram ++#define __INCmvDram ++ ++#include "ddr1_2/mvDramIf.h" ++#include "twsi/mvTwsi.h" ++ ++#define MAX_DIMM_NUM 2 ++#define SPD_SIZE 128 ++ ++/* Dimm spd offsets */ ++#define DIMM_MEM_TYPE 2 ++#define DIMM_ROW_NUM 3 ++#define DIMM_COL_NUM 4 ++#define DIMM_MODULE_BANK_NUM 5 ++#define DIMM_DATA_WIDTH 6 ++#define DIMM_VOLT_IF 8 ++#define DIMM_MIN_CC_AT_MAX_CAS 9 ++#define DIMM_ERR_CHECK_TYPE 11 ++#define DIMM_REFRESH_INTERVAL 12 ++#define DIMM_SDRAM_WIDTH 13 ++#define DIMM_ERR_CHECK_DATA_WIDTH 14 ++#define DIMM_MIN_CLK_DEL 15 ++#define DIMM_BURST_LEN_SUP 16 ++#define DIMM_DEV_BANK_NUM 17 ++#define DIMM_SUP_CAL 18 ++#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ ++#define DIMM_BUF_ADDR_CONT_IN 21 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 ++#define DIMM_MIN_ROW_PRECHARGE_TIME 27 ++#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 ++#define DIMM_MIN_RAS_TO_CAS_DELAY 29 ++#define DIMM_MIN_RAS_PULSE_WIDTH 30 ++#define DIMM_BANK_DENSITY 31 ++#define DIMM_MIN_WRITE_RECOVERY_TIME 36 ++#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 ++#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 ++#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 ++ ++/* Dimm Memory Type values */ ++#define DIMM_MEM_TYPE_SDRAM 0x4 ++#define DIMM_MEM_TYPE_DDR1 0x7 ++#define DIMM_MEM_TYPE_DDR2 0x8 ++ ++#define DIMM_MODULE_MANU_OFFS 64 ++#define DIMM_MODULE_MANU_SIZE 8 ++#define DIMM_MODULE_VEN_OFFS 73 ++#define DIMM_MODULE_VEN_SIZE 25 ++#define DIMM_MODULE_ID_OFFS 99 ++#define DIMM_MODULE_ID_SIZE 18 ++ ++/* enumeration for voltage levels. */ ++typedef enum _mvDimmVoltageIf ++{ ++ TTL_5V_TOLERANT, ++ LVTTL, ++ HSTL_1_5V, ++ SSTL_3_3V, ++ SSTL_2_5V, ++ VOLTAGE_UNKNOWN, ++} MV_DIMM_VOLTAGE_IF; ++ ++ ++/* enumaration for SDRAM CAS Latencies. */ ++typedef enum _mvDimmSdramCas ++{ ++ SD_CL_1 =1, ++ SD_CL_2, ++ SD_CL_3, ++ SD_CL_4, ++ SD_CL_5, ++ SD_CL_6, ++ SD_CL_7, ++ SD_FAULT ++}MV_DIMM_SDRAM_CAS; ++ ++ ++/* DIMM information structure */ ++typedef struct _mvDimmInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ ++ ++ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 numOfModuleBanks; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ MV_U32 dimmBankDensity; ++ MV_U32 dimmTypeInfo; /* DDR2 only */ ++ MV_U32 dimmAttributes; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ ++ MV_U32 numberOfDevices; ++ ++} MV_DIMM_INFO; ++ ++ ++MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); ++MV_VOID dimmSpdPrint(MV_U32 dimmNum); ++MV_STATUS dimmSpdCpy(MV_VOID); ++ ++#endif /* __INCmvDram */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1599 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "ddr1_2/mvDramIf.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++ ++ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++/* DRAM bank presence encoding */ ++#define BANK_PRESENT_CS0 0x1 ++#define BANK_PRESENT_CS0_CS1 0x3 ++#define BANK_PRESENT_CS0_CS2 0x5 ++#define BANK_PRESENT_CS0_CS1_CS2 0x7 ++#define BANK_PRESENT_CS0_CS2_CS3 0xd ++#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf ++ ++/* locals */ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); ++#if defined(MV_INC_BOARD_DDIM) ++static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas); ++static MV_U32 sdramModeRegCalc(MV_U32 minCas); ++static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); ++static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, ++ MV_U32 forcedCl); ++static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 minCas, MV_U32 busClk); ++static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 busClk); ++ ++/******************************************************************************* ++* mvDramIfDetect - Prepare DRAM interface configuration values. ++* ++* DESCRIPTION: ++* This function implements the full DRAM detection and timing ++* configuration for best system performance. ++* Since this routine runs from a ROM device (Boot Flash), its stack ++* resides on RAM, that might be the system DRAM. Changing DRAM ++* configuration values while keeping vital data in DRAM is risky. That ++* is why the function does not preform the configuration setting but ++* prepare those in predefined 32bit registers (in this case IDMA ++* registers are used) for other routine to perform the settings. ++* The function will call for board DRAM SPD information for each DRAM ++* chip select. The function will then analyze those SPD parameters of ++* all DRAM banks in order to decide on DRAM configuration compatible ++* for all DRAM banks. ++* The function will set the CPU DRAM address decode registers. ++* Note: This routine prepares values that will overide configuration of ++* mvDramBasicAsmInit(). ++* ++* INPUT: ++* forcedCl - Forced CAL Latency. If equal to zero, do not force. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfDetect(MV_U32 forcedCl) ++{ ++ MV_U32 retVal = MV_OK; /* return value */ ++ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; ++ MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW; ++ MV_U8 minCas; ++ MV_DRAM_DEC_WIN dramDecWin; ++ ++ dramDecWin.addrWin.baseHigh = 0; ++ ++ busClk = mvBoardSysClkGet(); ++ ++ if (0 == busClk) ++ { ++ mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); ++ return MV_ERROR; ++ } ++ ++ /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */ ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++) ++ mvCpuIfTargetWinEnable(i, MV_FALSE); ++#endif ++ ++ /* we will use bank 0 as the representative of the all the DRAM banks, */ ++ /* since bank 0 must exist. */ ++ for(i = 0; i < MV_DRAM_MAX_CS; i++) ++ { ++ /* if Bank exist */ ++ if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) ++ { ++ /* check it isn't SDRAM */ ++ if(bankInfo[i].memoryType == MEM_TYPE_SDRAM) ++ { ++ mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n"); ++ return MV_ERROR; ++ } ++ /* All banks must support registry in order to activate it */ ++ if(bankInfo[i].registeredAddrAndControlInputs != ++ bankInfo[0].registeredAddrAndControlInputs) ++ { ++ mvOsPrintf("Dram: ERR. different Registered settings !!!\n"); ++ return MV_ERROR; ++ } ++ ++ /* Init the CPU window decode */ ++ /* Note that the size in Bank info is in MB units */ ++ /* Note that the Dimm width might be different then the device DRAM width */ ++ temp = MV_REG_READ(SDRAM_CONFIG_REG); ++ ++ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32; ++ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); ++ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); ++ ++ /* We can not change DRAM window settings while excecuting */ ++ /* code from it. That is why we skip the DRAM CS[0], saving */ ++ /* it to the ROM configuration routine */ ++ if(i == SDRAM_CS0) ++ { ++ MV_U32 sizeToReg; ++ ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" ++ ,i); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Size is located at upper 16 bits */ ++ sizeToReg <<= SCSR_SIZE_OFFS; ++ ++ /* enable it */ ++ sizeToReg |= SCSR_WIN_EN; ++ ++ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); ++ } ++ else ++ { ++ dramDecWin.addrWin.baseLow = base; ++ dramDecWin.addrWin.size = size; ++ dramDecWin.enable = MV_TRUE; ++ ++ if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin)) ++ { ++ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", ++ SDRAM_CS0 + i); ++ return MV_ERROR; ++ } ++ } ++ ++ base += size; ++ ++ /* update the suportedCasLatencies mask */ ++ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; ++ ++ } ++ else ++ { ++ if( i == 0 ) /* bank 0 doesn't exist */ ++ { ++ mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n"); ++ return MV_ERROR; ++ } ++ else ++ { ++ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); ++ bankInfo[i].size = 0; /* Mark this bank as non exist */ ++ } ++ } ++ } ++ ++ /* calculate minimum CAS */ ++ minCas = minCasCalc(&bankInfo[0], busClk, forcedCl); ++ if (0 == minCas) ++ { ++ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", ++ (busClk / 1000000)); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ minCas = DDR2_CL_4; /* Continue with this CAS */ ++ mvOsPrintf("Set default CAS latency 4\n"); ++ } ++ else ++ { ++ minCas = DDR1_CL_3; /* Continue with this CAS */ ++ mvOsPrintf("Set default CAS latency 3\n"); ++ } ++ } ++ ++ /* calc SDRAM_CONFIG_REG and save it to temp register */ ++ temp = sdramConfigRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG1, temp); ++ ++ /* calc SDRAM_MODE_REG and save it to temp register */ ++ temp = sdramModeRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG2, temp); ++ ++ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ ++ temp = sdramExtModeRegCalc(&bankInfo[0]); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG10, temp); ++ ++ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ ++ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG3, temp); ++ ++ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ ++ temp = sdramAddrCtrlRegCalc(&bankInfo[0]); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG4, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ ++ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG5, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ ++ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG6, temp); ++ ++ /* Config DDR2 On Die Termination (ODT) registers */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ sdramDDr2OdtConfig(bankInfo); ++ } ++ ++ /* Note that DDR SDRAM Address/Control and Data pad calibration */ ++ /* settings is done in mvSdramIfConfig.s */ ++ ++ return retVal; ++} ++ ++/******************************************************************************* ++* minCasCalc - Calculate the Minimum CAS latency which can be used. ++* ++* DESCRIPTION: ++* Calculate the minimum CAS latency that can be used, base on the DRAM ++* parameters and the SDRAM bus Clock freq. ++* ++* INPUT: ++* busClk - the DRAM bus Clock. ++* pBankInfo - bank info parameters. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* The minimum CAS Latency. The function returns 0 if max CAS latency ++* supported by banks is incompatible with system bus clock frequancy. ++* ++*******************************************************************************/ ++static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, ++ MV_U32 forcedCl) ++{ ++ MV_U32 count = 1, j; ++ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ ++ MV_U32 startBit, stopBit; ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ ++ /* If we are asked to use the forced CAL */ ++ if (forcedCl) ++ { ++ mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), ++ (forcedCl % 10)); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ if (forcedCl == 30) ++ pBankInfo->suportedCasLatencies = 0x08; ++ else if (forcedCl == 40) ++ pBankInfo->suportedCasLatencies = 0x10; ++ else ++ { ++ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", ++ (forcedCl / 10), (forcedCl % 10)); ++ pBankInfo->suportedCasLatencies = 0x10; ++ } ++ } ++ else ++ { ++ if (forcedCl == 15) ++ pBankInfo->suportedCasLatencies = 0x02; ++ else if (forcedCl == 20) ++ pBankInfo->suportedCasLatencies = 0x04; ++ else if (forcedCl == 25) ++ pBankInfo->suportedCasLatencies = 0x08; ++ else if (forcedCl == 30) ++ pBankInfo->suportedCasLatencies = 0x10; ++ else if (forcedCl == 40) ++ pBankInfo->suportedCasLatencies = 0x40; ++ else ++ { ++ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n", ++ (forcedCl / 10), (forcedCl % 10)); ++ pBankInfo->suportedCasLatencies = 0x10; ++ } ++ } ++ ++ return pBankInfo->suportedCasLatencies; ++ } ++ ++ /* go over the supported cas mask from Max Cas down and check if the */ ++ /* SysClk stands in its time requirments. */ ++ ++ ++ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", ++ pBankInfo->suportedCasLatencies,busClkPs )); ++ for(j = 7; j > 0; j--) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ /* Reset the bits for CL incompatible for the sysClk */ ++ switch (count) ++ { ++ case 1: ++ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 2: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 3: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ default: ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ break; ++ } ++ } ++ } ++ ++ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", ++ pBankInfo->suportedCasLatencies )); ++ ++ /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */ ++ /* SDRAM DDR2 controller supports CL 3 to 5 */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ ++ stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */ ++ } ++ else ++ { ++ startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */ ++ stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */ ++ } ++ ++ for(j = startBit; j <= stopBit ; j++) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); ++ return (BIT0 << j); ++ } ++ } ++ ++ return 0; ++} ++ ++/******************************************************************************* ++* sdramConfigRegCalc - Calculate sdram config register ++* ++* DESCRIPTION: Calculate sdram config register optimized value based ++* on the bank info parameters. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram config reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 sdramConfig = 0; ++ MV_U32 refreshPeriod; ++ ++ busClk /= 1000000; /* we work with busClk in MHz */ ++ ++ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); ++ ++ /* figure out the memory refresh internal */ ++ switch (pBankInfo->refreshInterval & 0xf) ++ { ++ case 0x0: /* refresh period is 15.625 usec */ ++ refreshPeriod = 15625; ++ break; ++ case 0x1: /* refresh period is 3.9 usec */ ++ refreshPeriod = 3900; ++ break; ++ case 0x2: /* refresh period is 7.8 usec */ ++ refreshPeriod = 7800; ++ break; ++ case 0x3: /* refresh period is 31.3 usec */ ++ refreshPeriod = 31300; ++ break; ++ case 0x4: /* refresh period is 62.5 usec */ ++ refreshPeriod = 62500; ++ break; ++ case 0x5: /* refresh period is 125 usec */ ++ refreshPeriod = 125000; ++ break; ++ default: /* refresh period undefined */ ++ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); ++ return -1; ++ } ++ ++ /* Now the refreshPeriod is in register format value */ ++ refreshPeriod = (busClk * refreshPeriod) / 1000; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", ++ refreshPeriod)); ++ ++ /* make sure the refresh value is only 14 bits */ ++ if(refreshPeriod > SDRAM_REFRESH_MAX) ++ { ++ refreshPeriod = SDRAM_REFRESH_MAX; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", ++ refreshPeriod)); ++ } ++ ++ /* Clear the refresh field */ ++ sdramConfig &= ~SDRAM_REFRESH_MASK; ++ ++ /* Set new value to refresh field */ ++ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); ++ ++ /* registered DRAM ? */ ++ if ( pBankInfo->registeredAddrAndControlInputs ) ++ { ++ /* it's registered DRAM, so set the reg. DRAM bit */ ++ sdramConfig |= SDRAM_REGISTERED; ++ mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); ++ } ++ ++ /* set DDR SDRAM devices configuration */ ++ sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */ ++ ++ switch (pBankInfo->sdramWidth) ++ { ++ case 8: /* memory is x8 */ ++ sdramConfig |= SDRAM_DCFG_X8_DEV; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n")); ++ break; ++ case 16: ++ sdramConfig |= SDRAM_DCFG_X16_DEV; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n")); ++ break; ++ default: /* memory width unsupported */ ++ mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n"); ++ return -1; ++ } ++ ++ /* Set static default settings */ ++ sdramConfig |= SDRAM_CONFIG_DV; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", ++ sdramConfig)); ++ ++ return sdramConfig; ++} ++ ++/******************************************************************************* ++* sdramModeRegCalc - Calculate sdram mode register ++* ++* DESCRIPTION: Calculate sdram mode register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramModeRegCalc(MV_U32 minCas) ++{ ++ MV_U32 sdramMode; ++ ++ sdramMode = MV_REG_READ(SDRAM_MODE_REG); ++ ++ /* Clear CAS Latency field */ ++ sdramMode &= ~SDRAM_CL_MASK; ++ ++ mvOsPrintf("DRAM CAS Latency "); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ switch (minCas) ++ { ++ case DDR2_CL_3: ++ sdramMode |= SDRAM_DDR2_CL_3; ++ mvOsPrintf("3.\n"); ++ break; ++ case DDR2_CL_4: ++ sdramMode |= SDRAM_DDR2_CL_4; ++ mvOsPrintf("4.\n"); ++ break; ++ case DDR2_CL_5: ++ sdramMode |= SDRAM_DDR2_CL_5; ++ mvOsPrintf("5.\n"); ++ break; ++ default: ++ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); ++ return -1; ++ } ++ sdramMode |= DDR2_MODE_REG_DV; ++ } ++ else /* DDR1 */ ++ { ++ switch (minCas) ++ { ++ case DDR1_CL_1_5: ++ sdramMode |= SDRAM_DDR1_CL_1_5; ++ mvOsPrintf("1.5\n"); ++ break; ++ case DDR1_CL_2: ++ sdramMode |= SDRAM_DDR1_CL_2; ++ mvOsPrintf("2\n"); ++ break; ++ case DDR1_CL_2_5: ++ sdramMode |= SDRAM_DDR1_CL_2_5; ++ mvOsPrintf("2.5\n"); ++ break; ++ case DDR1_CL_3: ++ sdramMode |= SDRAM_DDR1_CL_3; ++ mvOsPrintf("3\n"); ++ break; ++ case DDR1_CL_4: ++ sdramMode |= SDRAM_DDR1_CL_4; ++ mvOsPrintf("4\n"); ++ break; ++ default: ++ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); ++ return -1; ++ } ++ sdramMode |= DDR1_MODE_REG_DV; ++ } ++ ++ DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode )); ++ ++ return sdramMode; ++} ++ ++/******************************************************************************* ++* sdramExtModeRegCalc - Calculate sdram Extended mode register ++* ++* DESCRIPTION: ++* Return sdram Extended mode register value based ++* on the bank info parameters and bank presence. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram Extended mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 populateBanks = 0; ++ int bankNum; ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ return DDR_SDRAM_EXT_MODE_CS0_DV; ++ ++ case(BANK_PRESENT_CS0_CS1): ++ return DDR_SDRAM_EXT_MODE_CS0_DV; ++ ++ case(BANK_PRESENT_CS0_CS2): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ default: ++ mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++/******************************************************************************* ++* dunitCtrlLowRegCalc - Calculate sdram dunit control low register ++* ++* DESCRIPTION: Calculate sdram dunit control low register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram dunit control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas) ++{ ++ MV_U32 dunitCtrlLow; ++ ++ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); ++ ++ /* Clear StBurstDel field */ ++ dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK; ++ ++#ifdef MV_88W8660 ++ /* Clear address/control output timing field */ ++ dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE; ++#endif /* MV_88W8660 */ ++ ++ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); ++ ++ /* For proper sample of read data set the Dunit Control register's */ ++ /* stBurstDel bits [27:24] */ ++ /********-********-********-********-********-********* ++ * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 * ++ *********-********-********-********-********-********* ++Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD * ++ *********-********-********-********-********-********* ++Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD * ++ *********-********-********-********-********-*********/ ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ switch (minCas) ++ { ++ case DDR2_CL_3: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR2_CL_4: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ default: ++ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", ++ minCas); ++ return -1; ++ } ++ } ++ else /* DDR1 */ ++ { ++ switch (minCas) ++ { ++ case DDR1_CL_1_5: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_2: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_2_5: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_3: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_4: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ default: ++ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", ++ minCas); ++ return -1; ++ } ++ ++ } ++ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); ++ ++ return dunitCtrlLow; ++} ++ ++/******************************************************************************* ++* sdramAddrCtrlRegCalc - Calculate sdram address control register ++* ++* DESCRIPTION: Calculate sdram address control register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram address control reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 addrCtrl = 0; ++ ++ /* Set Address Control register static configuration bits */ ++ addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG); ++ ++ /* Set address control default value */ ++ addrCtrl |= SDRAM_ADDR_CTRL_DV; ++ ++ /* Clear DSize field */ ++ addrCtrl &= ~SDRAM_DSIZE_MASK; ++ ++ /* Note that density is in MB units */ ++ switch (pBankInfo->deviceDensity) ++ { ++ case 128: /* 128 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 128Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_128Mb; ++ break; ++ case 256: /* 256 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_256Mb; ++ break; ++ case 512: /* 512 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_512Mb; ++ break; ++ default: ++ mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", ++ pBankInfo->deviceDensity); ++ return -1; ++ } ++ ++ /* SDRAM address control */ ++ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); ++ ++ return addrCtrl; ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control low register ++* optimized value based on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timinf control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 minCas, MV_U32 busClk) ++{ ++ MV_U32 tRp = 0; ++ MV_U32 tRrd = 0; ++ MV_U32 tRcd = 0; ++ MV_U32 tRas = 0; ++ MV_U32 tWr = 0; ++ MV_U32 tWtr = 0; ++ MV_U32 tRtp = 0; ++ ++ MV_U32 bankNum; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); ++ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); ++ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); ++ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ ++ /* by shifting the data two bits right. */ ++ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ ++ tRrd = tRrd >> 2; ++ tRcd = tRcd >> 2; ++ ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); ++ /* Micron work around for 133MHz */ ++ if (busClk == 133) ++ tRp += 1; ++ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); ++ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRrd = 2 */ ++ if (tRrd < 2) ++ tRrd = 2; ++ DB(mvOsPrintf("tRrd = %d ", tRrd)); ++ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRcd = %d ", tRcd)); ++ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRas = %d ", tRas)); ++ ++ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); ++ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); ++ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ ++ /* part by shifting the data two bits right. */ ++ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ ++ tWtr = tWtr >> 2; ++ tRtp = tRtp >> 2; ++ ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tWr = %d ", tWr)); ++ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tWtr = 2 */ ++ if (tWtr < 2) ++ tWtr = 2; ++ DB(mvOsPrintf("tWtr = %d ", tWtr)); ++ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRtp = 2 */ ++ if (tRtp < 2) ++ tRtp = 2; ++ DB(mvOsPrintf("tRtp = %d ", tRtp)); ++ } ++ else ++ { ++ tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0); ++ ++ if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas))) ++ { ++ tWtr = 2; ++ } ++ else ++ { ++ tWtr = 1; ++ } ++ ++ tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */ ++ } ++ ++ DB(mvOsPrintf("tWtr = %d\n", tWtr)); ++ ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ return (((tRp - 1) << SDRAM_TRP_OFFS) | ++ ((tRrd - 1) << SDRAM_TRRD_OFFS) | ++ ((tRcd - 1) << SDRAM_TRCD_OFFS) | ++ ((tRas - 1) << SDRAM_TRAS_OFFS) | ++ ((tWr - 1) << SDRAM_TWR_OFFS) | ++ ((tWtr - 1) << SDRAM_TWTR_OFFS) | ++ ((tRtp - 1) << SDRAM_TRTP_OFFS)); ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control high register ++* optimized value based on the bank info parameters and the bus clock. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timinf control high reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 busClk) ++{ ++ MV_U32 tRfc; ++ MV_U32 timeNs = 0; ++ int bankNum; ++ MV_U32 sdramTw2wCyc = 0; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* tRfc is different for DDR1 and DDR2. */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ MV_U32 bankNum; ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); ++ } ++ else ++ { ++ if (pBankInfo[0].deviceDensity == _1G) ++ { ++ timeNs = SDRAM_TRFC_1G; ++ } ++ else ++ { ++ if (200 == busClk) ++ { ++ timeNs = SDRAM_TRFC_64_512M_AT_200MHZ; ++ } ++ else ++ { ++ timeNs = SDRAM_TRFC_64_512M; ++ } ++ } ++ } ++ ++ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); ++ ++ DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc)); ++ ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ sdramTw2wCyc++; ++ } ++ ++ /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */ ++ if (sdramTw2wCyc > 1) ++ sdramTw2wCyc = 1; ++ else ++ sdramTw2wCyc = 0; ++ ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) | ++ ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) | ++ ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) | ++ (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) | ++ (sdramTw2wCyc << SDRAM_TW2W_OFFS)); ++ ++} ++ ++/******************************************************************************* ++* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. ++* ++* DESCRIPTION: ++* This function config DDR2 On Die Termination (ODT) registers. ++* ODT configuration is done according to DIMM presence: ++* ++* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode ++* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 ++* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 ++* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* ++* INPUT: ++* pBankInfo - bank info parameters. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* None ++*******************************************************************************/ ++static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 populateBanks = 0; ++ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; ++ int bankNum; ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS1): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ default: ++ mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"); ++ return; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); ++ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); ++ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); ++ return; ++} ++#endif /* defined(MV_INC_BOARD_DDIM) */ ++ ++/******************************************************************************* ++* mvDramIfWinSet - Set DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function sets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* pAddrDecWin - SDRAM address window structure. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg=0,sizeReg=0; ++ MV_U32 baseToReg=0 , sizeToReg=0; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlaps with current enabled windows */ ++ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ ++ "\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ target, ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ /* read base register*/ ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); ++ ++ /* read size register */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ baseReg &= ~SCBAR_BASE_MASK; ++ baseReg |= baseToReg; ++ ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* set size */ ++ sizeReg &= ~SCSR_SIZE_MASK; ++ /* Size is located at upper 16 bits */ ++ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); ++ ++ /* enable/Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ sizeReg |= SCSR_WIN_EN; ++ } ++ else ++ { ++ sizeReg &= ~SCSR_WIN_EN; ++ } ++ ++ /* 3) Write to address decode Base Address Register */ ++ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg); ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinGet - Get DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function gets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* pAddrDecWin - SDRAM address window structure. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg,sizeReg; ++ MV_U32 sizeRegVal; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Read base and size registers */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); ++ ++ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; ++ ++ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, ++ SCSR_SIZE_ALIGNMENT); ++ ++ /* Check if ctrlRegToSize returned OK */ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Extract base address */ ++ /* Base register [31:16] ==> baseLow[31:16] */ ++ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; ++ ++ pAddrDecWin->addrWin.baseHigh = 0; ++ ++ ++ if (sizeReg & SCSR_WIN_EN) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinEnable - Enable/Disable SDRAM address decode window ++* ++* DESCRIPTION: ++* This function enable/Disable SDRAM address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR in case function parameter are invalid, MV_OK otherewise. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { /* First check for overlap with other enabled windows */ ++ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", ++ target); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode winNum window */ ++ MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", ++ target); ++ return MV_ERROR; ++ } ++ } ++ else ++ { /* Disable address decode winNum window */ ++ MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window ++* ++* DESCRIPTION: ++* This function scan each SDRAM address decode window to test if it ++* overlapps the given address windoow ++* ++* INPUT: ++* target - SDRAM target where the function skips checking. ++* pAddrDecWin - The tested address window for overlapping with ++* SDRAM windows. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlaps any enabled address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_TARGET targetNum; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) ++ { ++ /* don't check our winNum or illegal targets */ ++ if (targetNum == target) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf( ++ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", ++ target, targetNum); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvDramIfBankSizeGet - Get DRAM interface bank size. ++* ++* DESCRIPTION: ++* This function returns the size of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled the function return '0'. In case ++* or paramter is invalid, the function returns -1. ++* ++*******************************************************************************/ ++MV_32 mvDramIfBankSizeGet(MV_U32 bankNum) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(bankNum)) ++ { ++ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); ++ return -1; ++ } ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return -1; ++ } ++ ++ if (MV_TRUE == addrDecWin.enable) ++ { ++ return addrDecWin.addrWin.size; ++ } ++ else ++ { ++ return 0; ++ } ++} ++ ++ ++/******************************************************************************* ++* mvDramIfSizeGet - Get DRAM interface total size. ++* ++* DESCRIPTION: ++* This function get the DRAM total size. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM total size. In case or paramter is invalid, the function ++* returns -1. ++* ++*******************************************************************************/ ++MV_32 mvDramIfSizeGet(MV_VOID) ++{ ++ MV_U32 totalSize = 0, bankSize = 0, bankNum; ++ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ bankSize = mvDramIfBankSizeGet(bankNum); ++ ++ if (-1 == bankSize) ++ { ++ mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum); ++ return -1; ++ } ++ else ++ { ++ totalSize += bankSize; ++ } ++ } ++ ++ DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize)); ++ ++ return totalSize; ++} ++ ++/******************************************************************************* ++* mvDramIfBankBaseGet - Get DRAM interface bank base. ++* ++* DESCRIPTION: ++* This function returns the 32 bit base address of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled or paramter is invalid, the ++* function returns -1. ++* ++*******************************************************************************/ ++MV_32 mvDramIfBankBaseGet(MV_U32 bankNum) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(bankNum)) ++ { ++ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); ++ return -1; ++ } ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return -1; ++ } ++ ++ if (MV_TRUE == addrDecWin.enable) ++ { ++ return addrDecWin.addrWin.baseLow; ++ } ++ else ++ { ++ return -1; ++ } ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,179 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfh ++#define __INCmvDramIfh ++ ++/* includes */ ++#include "ddr1_2/mvDramIfRegs.h" ++#include "ddr1_2/mvDramIfConfig.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* defines */ ++/* DRAM Timing parameters */ ++#define SDRAM_TWR 15 /* ns tWr */ ++#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ ++#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ ++#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ ++#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ ++#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */ ++ ++/* typedefs */ ++ ++/* enumeration for memory types */ ++typedef enum _mvMemoryType ++{ ++ MEM_TYPE_SDRAM, ++ MEM_TYPE_DDR1, ++ MEM_TYPE_DDR2 ++}MV_MEMORY_TYPE; ++ ++/* enumeration for DDR1 supported CAS Latencies */ ++typedef enum _mvDimmDdr1Cas ++{ ++ DDR1_CL_1_5 = 0x02, ++ DDR1_CL_2 = 0x04, ++ DDR1_CL_2_5 = 0x08, ++ DDR1_CL_3 = 0x10, ++ DDR1_CL_4 = 0x40, ++ DDR1_CL_FAULT ++} MV_DIMM_DDR1_CAS; ++ ++/* enumeration for DDR2 supported CAS Latencies */ ++typedef enum _mvDimmDdr2Cas ++{ ++ DDR2_CL_3 = 0x08, ++ DDR2_CL_4 = 0x10, ++ DDR2_CL_5 = 0x20, ++ DDR2_CL_FAULT ++} MV_DIMM_DDR2_CAS; ++ ++ ++typedef struct _mvDramBankInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ ++ MV_U32 numberOfDevices; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ MV_BOOL registeredAddrAndControlInputs; ++ ++}MV_DRAM_BANK_INFO; ++ ++/* This structure describes CPU interface address decode window */ ++typedef struct _mvDramIfDecWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++}MV_DRAM_DEC_WIN; ++ ++#include "ddr1_2/mvDram.h" ++ ++/* mvDramIf.h API list */ ++MV_VOID mvDramIfBasicAsmInit(MV_VOID); ++MV_STATUS mvDramIfDetect(MV_U32 forcedCl); ++MV_VOID _mvDramIfConfig(MV_VOID); ++ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); ++MV_32 mvDramIfBankSizeGet(MV_U32 bankNum); ++MV_32 mvDramIfBankBaseGet(MV_U32 bankNum); ++MV_32 mvDramIfSizeGet(MV_VOID); ++ ++#if 0 ++MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray); ++MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable); ++#endif ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,988 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#define MV_ASMLANGUAGE ++#include "mvSysHwConfig.h" ++#include "mvOsAsm.h" ++#include "mvBoardEnvSpec.h" ++#include "mvCpuIfRegs.h" ++#include "mvDramIfConfig.h" ++#include "mvDramIfRegs.h" ++#include "pex/mvPexRegs.h" ++#include "pci/mvPciRegs.h" ++#include "mvCtrlEnvSpec.h" ++#include "mvCtrlEnvAsm.h" ++#include "cpu/mvCpuArm.h" ++#include "mvCommon.h" ++ ++/* defines */ ++ ++#if !defined(MV_INC_BOARD_DDIM) ++.globl dramBoot1 ++dramBoot1: ++ .word 0 ++ ++/****************************************************************************** ++* ++* ++* ++* ++*******************************************************************************/ ++#if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG) ++ ++/* PEX_PCI and PRPMC boards 256 MB*/ ++#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 ++#define STATIC_SDRAM_CONFIG 0x03248400 ++#define STATIC_SDRAM_MODE 0x62 ++#define STATIC_DUNIT_CTRL_LOW 0x4041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x0 ++ ++#elif defined(DB_FPGA) ++ ++/* FPGA DC boards 256 MB*/ ++#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 ++#define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */ ++#define STATIC_SDRAM_MODE 0x22 ++#define STATIC_DUNIT_CTRL_LOW 0x03041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x1 ++ ++#elif defined(RD_88F6183GP) || defined(DB_CUSTOMER) ++ ++/* Customer 1 DDR2 2 devices 512Mbit by 16 bit */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 ++#define STATIC_SDRAM_CONFIG 0x03158400 ++#define STATIC_SDRAM_MODE 0x452 ++#define STATIC_DUNIT_CTRL_LOW 0x06041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 ++#define STATIC_SDRAM_EXT_MODE 0x00000440 ++ ++ ++#elif defined(RD_88F6183AP) ++ ++/* DDR2 1 devices 512Mbit by 16 bit */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 ++#define STATIC_SDRAM_CONFIG 0x1f154400 ++#define STATIC_SDRAM_MODE 0x432 ++#define STATIC_DUNIT_CTRL_LOW 0x04041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 ++#define STATIC_SDRAM_EXT_MODE 0x00000440 ++ ++/* 6082L MARVELL DIMM */ ++#elif defined(DB_88F6082LBP) ++#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 ++#define STATIC_SDRAM_CONFIG 0x7f158400 ++#define STATIC_SDRAM_MODE 0x432 ++#define STATIC_DUNIT_CTRL_LOW 0x04041040 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000501 ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01 ++#define STATIC_SDRAM_EXT_MODE 0x00000440 ++ ++#elif defined(RD_88W8660_AP82S) ++ ++/* Shark RD */ ++ ++#if defined(MV_DRAM_32M) ++#define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000010 ++#elif defined(MV_DRAM_16M) ++ ++#define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000000 ++ ++#else ++#error "NO DDR size selected" ++#endif ++ ++#define STATIC_SDRAM_CONFIG 0x03144400 ++#define STATIC_SDRAM_MODE 0x62 ++#define STATIC_DUNIT_CTRL_LOW 0x4041000 ++ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x0 ++ ++#elif defined(RD_88W8660) ++ ++/* Shark RD */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 ++#define STATIC_SDRAM_CONFIG 0x03144400 ++#define STATIC_SDRAM_MODE 0x62 ++#define STATIC_DUNIT_CTRL_LOW 0x4041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000010 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x0 ++ ++#else /* NAS */ ++ ++ ++#if defined(RD_88F5182) ++ ++#if defined(MV_88F5082) ++#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x20 ++#else ++#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x20 ++#endif ++ ++#elif defined(RD_88F5182_3) ++ ++#if defined(MV_88F5082) ++#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x20 ++#else ++#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x20 ++#endif ++ ++#else ++ ++#define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x0 ++ ++#endif ++ ++#if defined(MV_88F5082) ++#define STATIC_SDRAM_CONFIG 0x3144400 ++#else ++#define STATIC_SDRAM_CONFIG 0x3148400 ++#endif ++#define STATIC_SDRAM_MODE 0x62 ++#define STATIC_DUNIT_CTRL_LOW 0x4041000 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x40c ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x0 ++ ++#endif ++ ++ .globl _mvDramIfStaticInit ++_mvDramIfStaticInit: ++ ++ mov r11, LR /* Save link register */ ++ mov r10, r2 ++ ++ /* If we boot from NAND jump to DRAM sddress */ ++ ++ mov r5, #1 ++ ldr r6, =dramBoot1 ++ str r5, [r6] /* We started executing from DRAM */ ++ ++ ldr r6, dramBoot1 ++ cmp r6, #0 ++ bne 1f ++ ++ ++ /* set all dram windows to 0 */ ++ mov r6, #0 ++ MV_REG_WRITE_ASM(r6, r5, 0x1504) ++ MV_REG_WRITE_ASM(r6, r5, 0x150c) ++ MV_REG_WRITE_ASM(r6, r5, 0x1514) ++ MV_REG_WRITE_ASM(r6, r5, 0x151c) ++ ++ /* set all dram configuration in temp registers */ ++ ldr r6, = STATIC_SDRAM0_BANK0_SIZE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) ++ ldr r6, = STATIC_SDRAM_CONFIG ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) ++ ldr r6, = STATIC_SDRAM_MODE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) ++ ldr r6, = STATIC_DUNIT_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) ++ ldr r6, = STATIC_SDRAM_ADDR_CTRL ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) ++ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) ++ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) ++ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) ++ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) ++ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) ++ ldr r6, = STATIC_SDRAM_EXT_MODE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) ++ ++ mov sp, #0 ++ bl _mvDramIfConfig ++1: ++ mov r2, r10 ++ mov PC, r11 /* r11 is saved link register */ ++ ++#else /* #if !defined(MV_INC_BOARD_DDIM) */ ++ ++.globl dramBoot1 ++dramBoot1: ++ .word 0 ++ ++/******************************************************************************* ++* mvDramIfBasicInit - Basic initialization of DRAM interface ++* ++* DESCRIPTION: ++* The function will initialize the DRAM for basic usage. The function ++* will use the TWSI assembly API to extract DIMM parameters according ++* to which DRAM interface will be initialized. ++* The function referes to the following DRAM parameters: ++* 1) DIMM is registered or not. ++* 2) DIMM width detection. ++* 3) DIMM density. ++* ++* INPUT: ++* r3 - required size for initial DRAM. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++* Note: ++* r4 holds I2C EEPROM address ++* r5 holds SDRAM register base address ++* r7 holds returned values ++* r8 holds SDRAM various configuration registers value. ++* r11 holds return function address. ++*******************************************************************************/ ++/* Setting the offsets of the I2C registers */ ++#define NUM_OF_ROWS_OFFSET 3 ++#define NUM_OF_COLS_OFFSET 4 ++#define NUM_OF_RANKS 5 ++#define SDRAM_WIDTH_OFFSET 13 ++#define NUM_OF_BANKS_OFFSET 17 ++#define SUPPORTED_CL_OFFSET 18 ++#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ ++#define SDRAM_MODULES_ATTR_OFFSET 21 ++ ++#define DRAM_DEV_DENSITY_128M 0x080 ++#define DRAM_DEV_DENSITY_256M 0x100 ++#define DRAM_DEV_DENSITY_512M 0x200 ++ .globl _mvDramIfBasicInit ++ .extern _i2cInit ++ ++_mvDramIfBasicInit: ++ ++ mov r11, LR /* Save link register */ ++ ++ mov r5, #1 ++ ldr r8, =dramBoot1 ++ str r5, [r8] /* We started executing from DRAM */ ++ ++ /* If we boot from NAND jump to DRAM sddress */ ++ ldr r8, dramBoot1 ++ cmp r8, #0 ++ movne pc, r11 ++ ++ ++ ++ bl _i2cInit /* Initialize TWSI master */ ++ ++ /* Get default SDRAM Config values */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ bic r8, r8, #SDRAM_DCFG_MASK ++ ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r4, r5); ++ ++ /* Return if OrionN */ ++ ldr r5, =MV_5180_DEV_ID ++ cmp r4, r5 ++ beq cat_through_end ++ ++ /* Return if Orion1 */ ++ ldr r5, =MV_5181_DEV_ID ++ cmp r4, r5 ++ beq cat_through_end ++ ++ /* Return if Nas */ ++ ldr r5, =MV_5182_DEV_ID ++ cmp r4, r5 ++ beq cat_through_end ++ ++ /* Return if Shark */ ++ ldr r5, =MV_8660_DEV_ID ++ cmp r4, r5 ++ beq cat_through_end ++ ++ /* goto calcConfigReg if bigger than Orion2*/ ++ ldr r5, =MV_5281_DEV_ID ++ cmp r4, r5 ++ bne cat_through ++ ++cat_through: ++ /* set cat through - for better performance - in orion2 b0 and higher*/ ++ orr r8, r8, #SDRAM_CATTHR_EN ++ ++cat_through_end: ++ ++ ++ /* Get registered/non registered info from DIMM */ ++ bl _is_Registered ++ beq nonRegistered ++ ++setRegistered: ++ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ ++ ++nonRegistered: ++ /* Get SDRAM width */ ++ bl _get_width ++ ++ orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */ ++ cmp r7, #16 ++ beq setConfigReg ++ ++ orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */ ++ cmp r7, #8 ++ beq setConfigReg ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++setConfigReg: ++ mov r8, r6 ++ ldr r6, =SDRAM_CONFIG_DV ++ orr r8, r8, r6 /* Add default settings */ ++ mov r6, r8 /* Do not swap r8 content */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG) ++ ++ /* Set maximum CL supported by DIMM */ ++ bl _get_CAL ++ ++ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ ++ clz r6, r7 ++ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ ++ ++ /* Check the DDR version */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ bne casDdr2 ++ ++casDdr1: ++ ldr r7, =3 /* stBurstDel field value */ ++ ldr r8, =0x52 /* Assuming MAX CL = 1.5 */ ++ cmp r6, #1 /* If CL = 1.5 break */ ++ beq setModeReg ++ ++ ldr r7, =3 /* stBurstDel field value */ ++ ldr r8, =0x22 /* Assuming MAX CL = 2 */ ++ cmp r6, #2 /* If CL = 2 break */ ++ beq setModeReg ++ ++ ldr r7, =4 /* stBurstDel field value */ ++ ldr r8, =0x62 /* Assuming MAX CL = 2.5 */ ++ cmp r6, #3 /* If CL = 2.5 break */ ++ beq setModeReg ++ ++ ldr r7, =4 /* stBurstDel field value */ ++ ldr r8, =0x32 /* Assuming MAX CL = 3 */ ++ cmp r6, #4 /* If CL = 3 break */ ++ beq setModeReg ++ ++ ldr r7, =5 /* stBurstDel field value */ ++ ldr r8, =0x42 /* Assuming MAX CL = 4 */ ++ cmp r6, #6 /* If CL = 4 break */ ++ b setModeReg ++ ++ b exit_ddrAutoConfig /* This is an error !! */ ++ ++casDdr2: ++ ldr r7, =4 /* stBurstDel field value */ ++ ldr r8, =0x32 /* Assuming MAX CL = 3 */ ++ cmp r6, #3 /* If CL = 3 break */ ++ beq casDdr2Cont ++ ++ ldr r7, =5 /* stBurstDel field value */ ++ ldr r8, =0x42 /* Assuming MAX CL = 4 */ ++ cmp r6, #4 /* If CL = 4 break */ ++ beq casDdr2Cont ++ ++ /* CL 5 currently unsupported. We use CL 4 instead */ ++ ldr r7, =5 /* stBurstDel field value */ ++ ldr r8, =0x42 /* Assuming MAX CL = 5 */ ++ cmp r6, #5 /* If CL = 5 break */ ++ beq casDdr2Cont ++ ++ b exit_ddrAutoConfig /* This is an error !! */ ++casDdr2Cont: ++ /* Write recovery for auto-precharge relevant only in DDR2 */ ++ orr r8, r8, #0x400 /* Default value */ ++ ++setModeReg: ++ /* The CPU must not attempt to change the SDRAM Mode register setting */ ++ /* prior to DRAM controller completion of the DRAM initialization */ ++ /* sequence. To guarantee this restriction, it is recommended that */ ++ /* the CPU sets the SDRAM Operation register to NOP command, performs */ ++ /* read polling until the register is back in Normal operation value, */ ++ /* and then sets SDRAM Mode register to it's new value. */ ++ ++ /* write 'nop' to SDRAM operation */ ++ mov r6, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll1: ++ ldr r6, [r5] ++ cmp r6, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll1 ++ ++ /* Now its safe to write new value to SDRAM Mode register */ ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG) ++ ++ /* Make the Dunit write the DRAM its new mode */ ++ mov r6, #0x3 /* Mode Register Set command */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll2: ++ ldr r6, [r5] ++ cmp r6, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll2 ++ ++ /* Set Dunit control register according to max CL detected */ ++ /* If we use registered DIMM, add 1 to stBurstDel */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG) ++ tst r6, #SDRAM_REGISTERED ++ beq setDunitReg ++ add r7, r7, #1 ++ ++setDunitReg: ++ ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV ++ orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++ ++ ++ /* DIMM density configuration*/ ++ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ ++Density: ++ bl _getDensity ++ mov r8, r7 ++ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ ++ /* For example 0x10000000 --> 0x1000 */ ++ ++ mov r6, #0x00 ++ cmp r8, #DRAM_DEV_DENSITY_128M ++ beq densCont ++ ++ mov r6, #0x10 ++ cmp r8, #DRAM_DEV_DENSITY_256M ++ beq densCont ++ ++ mov r6, #0x20 ++ cmp r8, #DRAM_DEV_DENSITY_512M ++ beq densCont ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++densCont: ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG) ++ ++ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ tst r8, #SDRAM_DTYPE_DDR2 ++ beq _extModeODTEnd ++ ++ ++ /* Set DDR Extended Mode register for working with CS[0] */ ++ /* write 'nop' to SDRAM operation */ ++ mov r6, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll3: ++ ldr r6, [r5] ++ cmp r6, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll3 ++ ++ /* Now its safe to write new value to SDRAM Extended Mode register */ ++ ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG) ++ ++ /* Make the Dunit write the DRAM its new extended mode */ ++ mov r6, #0x4 /* Extended Mode Register Set command */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll4: ++ ldr r6, [r5] ++ cmp r6, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll4 ++ ++ /* ODT configuration is done for single bank CS[0] only */ ++ /* Config DDR2 On Die Termination (ODT) registers */ ++ ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV ++ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG) ++ ++ ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV ++ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) ++ ++ ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV ++ MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG) ++ ++ ++ /* we will check what device we are running and perform ++ Initialization according to device value */ ++ ++_extModeODTEnd: ++ ++ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ ++ /* Does Not Work for Address/Control and Data Pads. */ ++ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r6, r5); ++ /* Read device revision */ ++ MV_CTRL_REV_GET_ASM(r8, r5); ++ ++ /* Continue if OrionN */ ++ ldr r5, =MV_5180_DEV_ID ++ cmp r6, r5 ++ bne 1f ++ b glMem2End ++1: ++ ++ /* Continue if Orion1 and device revision B1 */ ++ ldr r5, =MV_5181_DEV_ID ++ cmp r6, r5 ++ bne 1f ++ ++ cmp r8, #MV_5181_B1_REV ++ bge glMem2End ++ b glMem2Start ++1: ++ ++ /* Orion NAS */ ++ ldr r5, =MV_5182_DEV_ID ++ cmp r6, r5 ++ beq glMem2Start ++ ++ /* Orion Shark */ ++ ldr r5, =MV_8660_DEV_ID ++ cmp r6, r5 ++ beq glMem2Start ++ ++ b glMem2End ++ ++glMem2Start: ++ ++ /* DDR SDRAM Address/Control Pads Calibration */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ /* Set Bit [31] to make the register writable */ ++ orr r8, r6, #SDRAM_WR_EN ++ ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ ++ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ ++ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ ++ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ ++ ++ /* Get the final N locked value of driving strength [22:17] */ ++ mov r5, r6 ++ mov r5, r5, LSL #9 ++ mov r5, r5, LSR #26 /* r5[5:0] = r6[22:17] */ ++ orr r5, r5, r5, LSL #6 /* r5[11:6] = r5[5:0] */ ++ ++ /* Write to both bits [5:0] and bits [11:6] */ ++ orr r6, r6, r5 ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ ++ /* DDR SDRAM Data Pads Calibration */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++ /* Set Bit [31] to make the register writable */ ++ orr r8, r6, #SDRAM_WR_EN ++ ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ ++ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ ++ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ ++ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ ++ ++ /* Get the final N locked value of driving strength [22:17] */ ++ mov r5, r6 ++ mov r5, r5, LSL #9 ++ mov r5, r5, LSR #26 ++ orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17] */ ++ ++ /* Write to both bits [5:0] and bits [11:6] */ ++ orr r6, r6, r5 ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++glMem2End: ++ /* Implement Guideline (GL# MEM-3) Drive Strength Value */ ++ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ ++ ++ /* Get SDRAM Config value */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ ++ /* Get DIMM type */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ beq ddr1StrengthVal ++ ++ddr2StrengthVal: ++ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV ++ ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV ++ b setDrvStrength ++ddr1StrengthVal: ++ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV ++ ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV ++ ++setDrvStrength: ++ /* DDR SDRAM Address/Control Pads Calibration */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ HTOLL(r6,r5) ++ ++ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ ++ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK ++ orr r6, r4, r6 /* Set default value for DDR */ ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ ++ /* DDR SDRAM Data Pads Calibration */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ HTOLL(r6,r5) ++ ++ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ ++ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK ++ orr r6, r8, r6 /* Set default value for DDR */ ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++ ++ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ ++ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ ++ /* Get the "sample on reset" register for the DDR frequancy */ ++ ++#if defined(MV_RUN_FROM_FLASH) ++ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ ++ ldr r7, = _cpuARMDDRCLK ++ ldr r4, =_start ++ ldr r4, [r4] ++ sub r7, r7, r4 ++ ldr r4, = Lrom_start_of_data ++ ldr r4, [r4] ++ add r7, r4, r7 ++#else ++ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ ++ ldr r7, = _cpuARMDDRCLK ++ ldr r4, =_start ++ sub r7, r7, r4 ++ add r7, r7, #CFG_MONITOR_BASE ++#endif ++ /* Get the "sample on reset" register for the DDR frequancy */ ++ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) ++ ldr r5, =MSAR_ARMDDRCLCK_MASK ++ and r5, r4, r5 ++#if 0 /* YOTAM TO BE FIX */ ++ mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS ++#endif ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r6, r8); ++ ++ /* Continue if TC90 */ ++ ldr r8, =MV_1281_DEV_ID ++ cmp r6, r6 ++ beq armClkMsb ++ ++ /* Continue if Orion2 */ ++ ldr r8, =MV_5281_DEV_ID ++ cmp r6, r8 ++#if 0 /* YOTAM TO BE FIX */ ++ bne 1f ++#endif ++ ++armClkMsb: ++#if 0 /* YOTAM TO BE FIX */ ++ tst r4, #MSAR_ARMDDRCLCK_H_MASK ++ beq 1f ++ orr r5, r5, #BIT4 ++1: ++ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE ++ mul r5, r4, r5 ++ add r7, r7, r5 ++ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF ++ ldr r5, [r7] ++#endif ++ ++ /* Get SDRAM Config value */ ++ MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG) ++ ++ /* Get DIMM type */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ beq ddr1FtdllVal ++ ++ddr2FtdllVal: ++ ldr r4, =FTDLL_DDR2_250MHZ ++ ldr r7, =_250MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_200MHZ ++ ldr r7, =_200MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_166MHZ ++ ldr r7, =_166MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_133MHZ ++ b setFtdllReg ++ ++ddr1FtdllVal: ++ ldr r4, =FTDLL_DDR1_200MHZ ++ ldr r7, =_200MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR1_166MHZ ++ ldr r7, =_166MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR1_133MHZ ++ ldr r7, =_133MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =0 ++ ++setFtdllReg: ++ ++#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) ++ MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) ++ orr r8, r8, r4 ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) ++ bic r8, r8, #1 ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) ++#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/ ++ ++ ++setTimingReg: ++ /* Set default Timing parameters */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ tst r8, #SDRAM_DTYPE_DDR2 ++ bne ddr2TimeParam ++ ++ddr1TimeParam: ++ ldr r6, =DDR1_TIMING_LOW_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) ++ ldr r6, =DDR1_TIMING_HIGH_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) ++ b timeParamDone ++ ++ddr2TimeParam: ++ ldr r6, =DDR2_TIMING_LOW_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) ++ ldr r6, =DDR2_TIMING_HIGH_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) ++ ++timeParamDone: ++ /* Open CS[0] window to requested size and enable it. Disable other */ ++ /* windows */ ++ ldr r6, =SCBAR_BASE_MASK ++ sub r3, r3, #1 ++ and r3, r3, r6 ++ orr r3, r3, #1 /* Enable bank */ ++ MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0)) ++ ldr r6, =0 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1)) ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2)) ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3)) ++ ++exit_ddrAutoConfig: ++ mov PC, r11 /* r11 is saved link register */ ++ ++ ++/***************************************************************************************/ ++/* r4 holds I2C EEPROM address ++ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value ++ * r8 holds SDRAM various configuration registers value. ++ * r13 holds Link register ++ */ ++/**************************/ ++_getDensity: ++ mov r13, LR /* Save link register */ ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ ++ bl _i2cRead ++ mov r8, r7 /* r8 save number of rows */ ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ ++ bl _i2cRead ++ add r8, r8, r7 /* r8 = number of rows + number of col */ ++ ++ mov r7, #0x1 ++ mov r8, r7, LSL r8 /* r8 = (1 << r8) */ ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ ++ bl _i2cRead ++ mul r8, r7, r8 ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ ++ bl _i2cRead ++ mul r7, r8, r7 ++ ++ mov PC, r13 ++ ++/**************************/ ++_get_width: ++ mov r13, LR /* Save link register */ ++ ++ /* Get SDRAM width (SPD offset 13) */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SDRAM_WIDTH_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ mov PC, r13 ++ ++/**************************/ ++_get_CAL: ++ mov r13, LR /* Save link register */ ++ ++ /* Set maximum CL supported by DIMM */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ ++ bl _i2cRead ++ ++ mov PC, r13 ++ ++/**************************/ ++/* R8 - sdram configuration register. ++ * Return value in flag if no-registered then Z-flag is set ++ */ ++_is_Registered: ++ mov r13, LR /* Save link register */ ++ ++ /* Get registered/non registered info from DIMM */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ bne regDdr2 ++ ++regDdr1: ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SDRAM_MODULES_ATTR_OFFSET ++ bl _i2cRead /* result in r7 */ ++ tst r7, #0x2 ++ b exit ++regDdr2: ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #DIMM_TYPE_INFO_OFFSET ++ bl _i2cRead /* result in r7 */ ++ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ ++ /* or Mini-RDIMM (0x10) */ ++exit: ++ mov PC, r13 ++ ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,668 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvDramIfBasicAsm.s ++* ++* DESCRIPTION: ++* Memory full detection and best timing configuration is done in ++* C code. C runtime environment requires a stack. This module API ++* initialize DRAM interface chip select 0 for basic functionality for ++* the use of stack. ++* The module API assumes DRAM information is stored in I2C EEPROM reside ++* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM ++* internal data structure is assumed to be orgenzied in common DRAM ++* vendor SPD structure. ++* NOTE: DFCDL values are assumed to be already initialized prior to ++* this module API activity. ++* ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#define MV_ASMLANGUAGE ++#include "mvOsAsm.h" ++#include "mvSysHwConfig.h" ++#include "mvDramIfRegs.h" ++#include "mvDramIfConfig.h" ++#include "mvCpuIfRegs.h" ++#include "pex/mvPexRegs.h" ++#include "pci/mvPciRegs.h" ++#include "mvCtrlEnvSpec.h" ++#include "mvCtrlEnvAsm.h" ++#include "cpu/mvCpuArm.h" ++#include "mvCommon.h" ++ ++/* defines */ ++ ++/* locals */ ++.data ++.globl _mvDramIfConfig ++ ++.text ++ ++/******************************************************************************* ++* _mvDramIfConfig - Basic DRAM interface initialization. ++* ++* DESCRIPTION: ++* The function will initialize the following DRAM parameters using the ++* values prepared by mvDramIfDetect routine. Values are located ++* in predefined registers. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++ ++_mvDramIfConfig: ++ ++ /* Save register on stack */ ++ cmp sp, #0 ++ beq no_stack_s ++save_on_stack: ++ stmdb sp!, {r1, r2, r3, r4, r7, r11} ++no_stack_s: ++ ++ /* 1) Write to SDRAM coniguration register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) ++ str r4, [r1] ++ ++ /* 2) Write Dunit control low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) ++ str r4, [r1] ++ ++ /* 3) Write SDRAM address control register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) ++ str r4, [r1] ++ ++ /* 4) Write SDRAM bank 0 size register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0)) ++ str r4, [r1] ++ ++ /* 5) Write SDRAM open pages control register */ ++ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) ++ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV ++ str r4, [r1] ++ ++ /* 6) Write SDRAM timing Low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) ++ str r4, [r1] ++ ++ /* 7) Write SDRAM timing High register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) ++ str r4, [r1] ++ ++ /* 8) Write SDRAM mode register */ ++ /* The CPU must not attempt to change the SDRAM Mode register setting */ ++ /* prior to DRAM controller completion of the DRAM initialization */ ++ /* sequence. To guarantee this restriction, it is recommended that */ ++ /* the CPU sets the SDRAM Operation register to NOP command, performs */ ++ /* read polling until the register is back in Normal operation value, */ ++ /* and then sets SDRAM Mode register to it’s new value. */ ++ ++ /* 8.1 write 'nop' to SDRAM operation */ ++ mov r4, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) ++ ++ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll1: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll1 ++ ++ /* 8.3 Now its safe to write new value to SDRAM Mode register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) ++ str r4, [r1] ++ ++ /* 8.4 Make the Dunit write the DRAM its new mode */ ++ mov r4, #0x3 /* Mode Register Set command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll2: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll2 ++ ++#ifndef DB_FPGA ++ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ ++ MV_REG_READ_ASM (r4, r1, SDRAM_CONFIG_REG) ++ tst r4, #SDRAM_DTYPE_DDR2 ++ beq _extModeODTEnd ++#endif /* DB_FPGA */ ++ ++ /* 9) Write SDRAM Extended mode register This operation should be */ ++ /* done for each memory bank */ ++ /* write 'nop' to SDRAM operation */ ++ mov r4, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll3: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll3 ++ ++ /* Now its safe to write new value to SDRAM Extended Mode register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) ++ str r4, [r1] ++ ++ /* Go over each of the Banks */ ++ ldr r3, =0 /* r3 = DRAM bank Num */ ++ ++extModeLoop: ++ /* Set the SDRAM Operation Control to each of the DRAM banks */ ++ mov r2, r3 /* Do not swap the bank counter value */ ++ MV_REG_WRITE_ASM (r2, r1, SDRAM_OPERATION_CTRL_REG) ++ ++ /* Make the Dunit write the DRAM its new mode */ ++ mov r4, #0x4 /* Extended Mode Register Set command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll4: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll4 ++#ifndef DB_FPGA ++ add r3, r3, #1 ++ cmp r3, #4 /* 4 = Number of banks */ ++ bne extModeLoop ++ ++extModeEnd: ++ /* Config DDR2 On Die Termination (ODT) registers */ ++ /* Write SDRAM DDR2 ODT control low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) ++ str r4, [r1] ++ ++ /* Write SDRAM DDR2 ODT control high register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) ++ str r4, [r1] ++ ++ /* Write SDRAM DDR2 Dunit ODT control register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) ++ str r4, [r1] ++ ++#endif /* DB_FPGA */ ++_extModeODTEnd: ++#ifndef DB_FPGA ++ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ ++ /* Does Not Work for Address/Control and Data Pads. */ ++ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r3, r1); ++ /* Read device revision */ ++ MV_CTRL_REV_GET_ASM(r2, r1); ++ ++ /* Continue if OrionN */ ++ ldr r1, =MV_5180_DEV_ID ++ cmp r3, r1 ++ bne 1f ++ b glMem2End ++1: ++ /* Continue if Orion1 and device revision B1 */ ++ ldr r1, =MV_5181_DEV_ID ++ cmp r3, r1 ++ bne 1f ++ ++ cmp r2, #MV_5181_B1_REV ++ bge glMem2End ++ b glMem2Start ++1: ++ ++ /* Orion NAS */ ++ ldr r1, =MV_5182_DEV_ID ++ cmp r3, r1 ++ beq glMem2Start ++ ++ /* Orion NAS */ ++ ldr r1, =MV_5082_DEV_ID ++ cmp r3, r1 ++ beq glMem2Start ++ ++ /* Orion Shark */ ++ ldr r1, =MV_8660_DEV_ID ++ cmp r3, r1 ++ beq glMem2Start ++ ++ b glMem2End ++ ++glMem2Start: ++ ++ /* DDR SDRAM Address/Control Pads Calibration */ ++ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ /* Set Bit [31] to make the register writable */ ++ orr r2, r3, #SDRAM_WR_EN ++ ++ MV_REG_WRITE_ASM (r2, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ ++ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ ++ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ ++ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ ++ ++ /* Get the final N locked value of driving strength [22:17] */ ++ mov r1, r3 ++ mov r1, r1, LSL #9 ++ mov r1, r1, LSR #26 /* r1[5:0] = r3[22:17] */ ++ orr r1, r1, r1, LSL #6 /* r1[11:6] = r1[5:0] */ ++ ++ /* Write to both bits [5:0] and bits [11:6] */ ++ orr r3, r3, r1 ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ ++ /* DDR SDRAM Data Pads Calibration */ ++ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++ /* Set Bit [31] to make the register writable */ ++ orr r2, r3, #SDRAM_WR_EN ++ ++ MV_REG_WRITE_ASM (r2, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ ++ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ ++ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ ++ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ ++ ++ /* Get the final N locked value of driving strength [22:17] */ ++ mov r1, r3 ++ mov r1, r1, LSL #9 ++ mov r1, r1, LSR #26 ++ orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17] */ ++ ++ /* Write to both bits [5:0] and bits [11:6] */ ++ orr r3, r3, r1 ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++glMem2End: ++ ++ ++ /* Implement Guideline (GL# MEM-3) Drive Strength Value */ ++ /* Relevant for: 88F5181-A1/B0/B1, 88F5281-A0/B0/C/D, 88F5182, */ ++ /* 88F5082, 88F5181L, 88F6082/L, 88F6183, 88F6183L */ ++ ++ /* Get SDRAM Config value */ ++ MV_REG_READ_ASM (r2, r1, SDRAM_CONFIG_REG) ++ ++ /* Get DIMM type */ ++ tst r2, #SDRAM_DTYPE_DDR2 ++ beq ddr1StrengthVal ++ ++ddr2StrengthVal: ++ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV ++ ldr r2, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV ++ b setDrvStrength ++ddr1StrengthVal: ++ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV ++ ldr r2, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV ++ ++setDrvStrength: ++ /* DDR SDRAM Address/Control Pads Calibration */ ++ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ HTOLL(r3,r1) ++ ++ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ ++ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK ++ orr r3, r4, r3 /* Set default value for DDR */ ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ ++ /* DDR SDRAM Data Pads Calibration */ ++ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ HTOLL(r3,r1) ++ ++ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ ++ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK ++ orr r3, r2, r3 /* Set default value for DDR */ ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) ++ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ ++ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0/C/D, 88F5182 */ ++ /* 88F5082, 88F5181L, 88F6082/L */ ++ ++ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ ++ ldr r7, = _cpuARMDDRCLK ++ ldr r4, =_start ++ sub r7, r7, r4 ++ add r7, r7, #CFG_MONITOR_BASE ++ ++ /* Get the "sample on reset" register for the DDR frequancy */ ++ MV_REG_READ_ASM (r4, r1, MPP_SAMPLE_AT_RESET) ++ ldr r1, =MSAR_ARMDDRCLCK_MASK ++ and r1, r4, r1 ++#if 0 /* YOTAM TO BE FIX */ ++ mov r1, r1, LSR #MSAR_ARMDDRCLCK_OFFS ++#endif ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r3, r2); ++ ++ /* Continue if TC90 */ ++ ldr r2, =MV_1281_DEV_ID ++ cmp r3, r2 ++ beq armClkMsb ++ ++ /* Continue if Orion2 */ ++ ldr r2, =MV_5281_DEV_ID ++ cmp r3, r2 ++#if 0 /* YOTAM TO BE FIX */ ++ bne 1f ++#endif ++ ++armClkMsb: ++#if 0 /* YOTAM TO BE FIX */ ++ tst r4, #MSAR_ARMDDRCLCK_H_MASK ++ beq 1f ++ orr r1, r1, #BIT4 ++1: ++ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE ++ mul r1, r4, r1 ++ add r7, r7, r1 ++ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF ++ ldr r1, [r7] ++#endif ++ ++ /* Get SDRAM Config value */ ++ MV_REG_READ_ASM (r2, r4, SDRAM_CONFIG_REG) ++ ++ /* Get DIMM type */ ++ tst r2, #SDRAM_DTYPE_DDR2 ++ beq ddr1FtdllVal ++ ++ddr2FtdllVal: ++ ldr r2, =MV_5281_DEV_ID ++ cmp r3, r2 ++ bne 2f ++ MV_CTRL_REV_GET_ASM(r3, r2) ++ cmp r3, #MV_5281_D0_REV ++ beq orin2_d0_ddr2_ftdll_val ++ cmp r3, #MV_5281_D1_REV ++ beq orin2_d1_ddr2_ftdll_val ++ cmp r3, #MV_5281_D2_REV ++ beq orin2_d1_ddr2_ftdll_val ++ b ddr2_default_val ++ ++/* Set Orion 2 D1 ftdll values for DDR2 */ ++orin2_d1_ddr2_ftdll_val: ++ ldr r4, =FTDLL_DDR2_250MHZ_5281_D1 ++ ldr r7, =_250MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_200MHZ_5281_D1 ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ b ddr2_default_val ++ ++/* Set Orion 2 D0 ftdll values for DDR2 */ ++orin2_d0_ddr2_ftdll_val: ++ ldr r4, =FTDLL_DDR2_250MHZ_5281_D0 ++ ldr r7, =_250MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_200MHZ_5281_D0 ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ b ddr2_default_val ++2: ++ ldr r2, =MV_5182_DEV_ID ++ cmp r3, r2 ++ bne 3f ++ ++/* Set Orion nas ftdll values for DDR2 */ ++orin_nas_ftdll_val: ++ ldr r4, =FTDLL_DDR2_166MHZ_5182 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ++/* default values for all other devices */ ++3: ++ddr2_default_val: ++ ldr r4, =FTDLL_DDR2_250MHZ ++ ldr r7, =_250MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_200MHZ ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_166MHZ ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_133MHZ ++ ldr r7, =_133MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =0 ++ b setFtdllReg ++ ++ddr1FtdllVal: ++ ldr r2, =MV_5281_DEV_ID ++ cmp r3, r2 ++ bne 2f ++ MV_CTRL_REV_GET_ASM(r3, r2) ++ cmp r3, #MV_5281_D0_REV ++ bge orin2_ddr1_ftdll_val ++ b ddr1_default_val ++ ++/* Set Orion 2 D0 and above ftdll values for DDR1 */ ++orin2_ddr1_ftdll_val: ++ ldr r4, =FTDLL_DDR1_200MHZ_5281_D0 ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR1_166MHZ_5281_D0 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ b ddr1_default_val ++2: ++ ldr r2, =MV_5181_DEV_ID ++ cmp r3, r2 ++ bne 3f ++ MV_CTRL_REV_GET_ASM(r3, r2) ++ cmp r3, #MV_5181_B1_REV ++ bge orin1_ddr1_ftdll_val ++ b ddr1_default_val ++ ++/* Set Orion 1 ftdll values for DDR1 */ ++orin1_ddr1_ftdll_val: ++ ldr r4, =FTDLL_DDR1_166MHZ_5181_B1 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++3: ++ddr1_default_val: ++ ldr r4, =FTDLL_DDR1_133MHZ ++ ldr r7, =_133MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ++ ldr r4, =FTDLL_DDR1_166MHZ ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ++ ldr r4, =FTDLL_DDR1_200MHZ ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ++ ldr r4, =0 ++ ++setFtdllReg: ++ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) ++ HTOLL(r4,r1) ++ bic r4, r4, #1 ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) ++ ++#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) */ ++#endif /* DB_FPGA */ ++ ++restoreTmpRegs: ++ /* Restore the registers we used to save the DDR detect values */ ++ ++ ldr r4, =DRAM_BUF_REG0_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG0) ++ ++ ldr r4, =DRAM_BUF_REG1_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG1) ++ ++ ldr r4, =DRAM_BUF_REG2_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG2) ++ ++ ldr r4, =DRAM_BUF_REG3_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG3) ++ ++ ldr r4, =DRAM_BUF_REG4_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG4) ++ ++ ldr r4, =DRAM_BUF_REG5_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG5) ++ ++ ldr r4, =DRAM_BUF_REG6_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG6) ++ ++ ldr r4, =DRAM_BUF_REG7_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG7) ++ ++ ldr r4, =DRAM_BUF_REG8_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG8) ++ ++ ldr r4, =DRAM_BUF_REG9_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG9) ++ ++ ldr r4, =DRAM_BUF_REG10_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG10) ++ ++ ++ /* Restore registers */ ++ /* Save register on stack */ ++ cmp sp, #0 ++ beq no_stack_l ++load_from_stack: ++ ldmia sp!, {r1, r2, r3, r4, r7, r11} ++no_stack_l: ++ ++ mov pc, lr ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,192 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfConfigh ++#define __INCmvDramIfConfigh ++ ++/* includes */ ++ ++/* defines */ ++ ++/* registers defaults values */ ++ ++#define SDRAM_CONFIG_DV \ ++ (SDRAM_PERR_WRITE | \ ++ SDRAM_SRMODE | \ ++ SDRAM_SRCLK_GATED) ++ ++#define SDRAM_DUNIT_CTRL_LOW_DV \ ++ (SDRAM_CTRL_POS_RISE | \ ++ SDRAM_CLK1DRV_NORMAL | \ ++ SDRAM_LOCKEN_ENABLE) ++ ++#define SDRAM_ADDR_CTRL_DV 0 ++ ++#define SDRAM_TIMING_CTRL_LOW_REG_DV \ ++ ((0x2 << SDRAM_TRCD_OFFS) | \ ++ (0x2 << SDRAM_TRP_OFFS) | \ ++ (0x1 << SDRAM_TWR_OFFS) | \ ++ (0x0 << SDRAM_TWTR_OFFS) | \ ++ (0x5 << SDRAM_TRAS_OFFS) | \ ++ (0x1 << SDRAM_TRRD_OFFS)) ++/* TRFC 0x27, TW2W 0x1 */ ++#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\ ++ ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\ ++ ( 0x1 << SDRAM_TW2W_OFFS)) ++ ++#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN ++ ++/* DDR2 ODT default register values */ ++ ++/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ ++/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++ ++#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000 ++#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F ++#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440 ++ ++#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C ++#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F ++#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404 ++ ++ ++/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ ++#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ ++ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++ ++#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \ ++ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++/* DDR SDRAM Mode Register default value */ ++#define DDR1_MODE_REG_DV 0x00000000 ++#define DDR2_MODE_REG_DV 0x00000400 ++ ++/* DDR SDRAM Timing parameter default values */ ++#define DDR1_TIMING_LOW_DV 0x11602220 ++#define DDR1_TIMING_HIGH_DV 0x0000000d ++ ++#define DDR2_TIMING_LOW_DV 0x11812220 ++#define DDR2_TIMING_HIGH_DV 0x0000030f ++ ++/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */ ++#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \ ++ (0x7F<< 12) | \ ++ (0x1 << 22)) ++ ++#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ ++ ++#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \ ++ (0x1 << 12) | \ ++ (0x3 << 14) | \ ++ (0x1 << 18) | \ ++ (0x1 << 22)) ++ ++ ++#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \ ++ (0x1 << 12) | \ ++ (0x1 << 14) | \ ++ (0x1 << 16) | \ ++ (0x1 << 19) | \ ++ (0xF << 20)) ++ ++#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ ++ ++#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \ ++ (0x1 << 12) | \ ++ (0x1 << 14) | \ ++ (0x1 << 16) | \ ++ (0x1 << 19) | \ ++ (0xF << 20)) ++ ++#define FTDLL_DDR2_250MHZ 0x445001 ++ ++/* Orion 1 B1 and above */ ++#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001 ++ ++/* Orion nas */ ++#define FTDLL_DDR2_166MHZ_5182 0x597001 ++ ++/* Orion 2 D0 and above */ ++#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001 ++#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001 ++#define FTDLL_DDR2_166MHZ_5281_D0 0x485001 ++#define FTDLL_DDR2_200MHZ_5281_D0 0x485001 ++#define FTDLL_DDR2_250MHZ_5281_D0 0x445001 ++#define FTDLL_DDR2_200MHZ_5281_D1 0x995001 ++#define FTDLL_DDR2_250MHZ_5281_D1 0x984801 ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,306 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDramIfRegsh ++#define __INCmvDramIfRegsh ++ ++ ++/* DDR SDRAM Controller Address Decode Registers */ ++/* SDRAM CSn Base Address Register (SCBAR) */ ++#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) ++#define SCBAR_BASE_OFFS 16 ++#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) ++#define SCBAR_BASE_ALIGNMENT 0x10000 ++ ++/* SDRAM CSn Size Register (SCSR) */ ++#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) ++#define SCSR_WIN_EN BIT0 ++#define SCSR_SIZE_OFFS 16 ++#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) ++#define SCSR_SIZE_ALIGNMENT 0x10000 ++ ++/* configuration register */ ++#define SDRAM_CONFIG_REG 0x1400 ++#define SDRAM_REFRESH_OFFS 0 ++#define SDRAM_REFRESH_MAX 0x3000 ++#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) ++#define SDRAM_DWIDTH_OFFS 14 ++#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DTYPE_OFFS 16 ++#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) ++#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) ++#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) ++#define SDRAM_REGISTERED (1 << 17) ++#define SDRAM_PERR_OFFS 18 ++#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) ++#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) ++#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) ++#define SDRAM_DCFG_OFFS 20 ++#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) ++#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) ++#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) ++#define SDRAM_SRMODE (1 << 24) ++#define SDRAM_SRCLK_OFFS 25 ++#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_CATTH_OFFS 26 ++#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) ++ ++ ++/* dunit control register */ ++#define SDRAM_DUNIT_CTRL_REG 0x1404 ++#define SDRAM_CTRL_POS_OFFS 6 ++#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CLK1DRV_OFFS 12 ++#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_LOCKEN_OFFS 18 ++#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) ++#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) ++#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) ++#define SDRAM_ST_BURST_DEL_OFFS 24 ++#define SDRAM_ST_BURST_DEL_MAX 0xf ++#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX< busClkPs) ++ { ++ mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); ++ return MV_ERROR; ++ } ++ ++ /* All banks must support registry in order to activate it */ ++ if(bankInfo[i].registeredAddrAndControlInputs != ++ bankInfo[0].registeredAddrAndControlInputs) ++ { ++ mvOsOutput("Dram: ERR. different Registered settings !!!\n"); ++ return MV_ERROR; ++ } ++ ++ /* All banks must support same ECC mode */ ++ if(bankInfo[i].errorCheckType != ++ bankInfo[0].errorCheckType) ++ { ++ mvOsOutput("Dram: ERR. different ECC settings !!!\n"); ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ if( i == 0 ) /* bank 0 doesn't exist */ ++ { ++ mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); ++ return MV_ERROR; ++ } ++ else ++ { ++ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); ++ bankInfo[i].size = 0; /* Mark this bank as non exist */ ++ } ++ } ++ } ++ ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) ++ { ++ MV_DRAM_CS_order[0] = SDRAM_CS2; ++ MV_DRAM_CS_order[1] = SDRAM_CS3; ++ MV_DRAM_CS_order[2] = SDRAM_CS0; ++ MV_DRAM_CS_order[3] = SDRAM_CS1; ++ DRAM_CS_Order[0] = SDRAM_CS2; ++ DRAM_CS_Order[1] = SDRAM_CS3; ++ DRAM_CS_Order[2] = SDRAM_CS0; ++ DRAM_CS_Order[3] = SDRAM_CS1; ++ ++ } ++ else ++#endif ++ { ++ MV_DRAM_CS_order[0] = SDRAM_CS0; ++ MV_DRAM_CS_order[1] = SDRAM_CS1; ++ DRAM_CS_Order[0] = SDRAM_CS0; ++ DRAM_CS_Order[1] = SDRAM_CS1; ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ MV_DRAM_CS_order[2] = SDRAM_CS2; ++ MV_DRAM_CS_order[3] = SDRAM_CS3; ++ DRAM_CS_Order[2] = SDRAM_CS2; ++ DRAM_CS_Order[3] = SDRAM_CS3; ++#endif ++ } ++ ++ for(j = 0; j < MV_DRAM_MAX_CS; j++) ++ { ++ i = MV_DRAM_CS_order[j]; ++ ++ if (0 == bankInfo[i].size) ++ continue; ++ ++ /* Init the CPU window decode */ ++ /* Note that the Dimm width might be different then the device DRAM width */ ++#ifdef MV78XX0 ++ temp = MV_REG_READ(SDRAM_CONFIG_REG); ++ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; ++#else ++ deviceW = 16 /* KW family */; ++#endif ++ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); ++ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); ++ ++ /* We can not change DRAM window settings while excecuting */ ++ /* code from it. That is why we skip the DRAM CS[0], saving */ ++ /* it to the ROM configuration routine */ ++ ++ numOfAllDevices += bankInfo[i].numberOfDevices; ++ if (i == MV_DRAM_CS_order[0]) ++ { ++ MV_U32 sizeToReg; ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" ++ ,i); ++ return MV_BAD_PARAM; ++ } ++ ++ DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) ++ sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); ++ sizeToReg |= SCSR_WIN_EN; ++ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); ++ } ++ else ++ { ++ dramDecWin.addrWin.baseLow = base; ++ dramDecWin.addrWin.size = size; ++ dramDecWin.enable = MV_TRUE; ++ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); ++ ++ /* Check if the DRAM size is more then 3GByte */ ++ if (base < 0xC0000000) ++ { ++ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); ++ if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin)) ++ { ++ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); ++ return MV_ERROR; ++ } ++ } ++ } ++ ++ base += size; ++ ++ /* update the suportedCasLatencies mask */ ++ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; ++ } ++ ++ /* calculate minimum CAS */ ++ minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); ++ if (0 == minCas) ++ { ++ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", ++ (busClk / 1000000)); ++ ++ minCas = DDR2_CL_4; /* Continue with this CAS */ ++ mvOsOutput("Set default CAS latency 4\n"); ++ } ++ ++ /* calc SDRAM_CONFIG_REG and save it to temp register */ ++ temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ ++ /* check if ECC is enabled by the user */ ++ if(eccDisable) ++ { ++ /* turn off ECC*/ ++ temp &= ~BIT18; ++ } ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG1, temp); ++ ++ /* calc SDRAM_MODE_REG and save it to temp register */ ++ temp = sdramModeRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG2, temp); ++ ++ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ ++ temp = sdramExtModeRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG10, temp); ++ ++ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ ++ TTMode = MV_FALSE; ++ DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) ++ if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) ++ { ++ if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || ++ (numOfAllDevices > 18) ) ++ { ++ mvOsOutput("Enable 2T "); ++ TTMode = MV_TRUE; ++ } ++ } ++ ++ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG3, temp); ++ ++ /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ ++ temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) ++ /* check if ECC is enabled by the user */ ++ if(eccDisable) ++ { ++ /* turn off sample stage if no ecc */ ++ temp &= ~SDRAM__D2P_EN;; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG13, temp); ++ ++ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ ++ temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG4, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ ++ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG5, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ ++ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG6, temp); ++ ++ sdramDDr2OdtConfig(bankInfo); ++ ++ /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ ++ temp = sdramDdr2TimeLoRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG11, temp); ++ ++ /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ ++ temp = sdramDdr2TimeHiRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG12, temp); ++#endif ++ ++ /* Note that DDR SDRAM Address/Control and Data pad calibration */ ++ /* settings is done in mvSdramIfConfig.s */ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvDramIfBankBaseGet - Get DRAM interface bank base. ++* ++* DESCRIPTION: ++* This function returns the 32 bit base address of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled or paramter is invalid, the ++* function returns -1. ++* ++*******************************************************************************/ ++MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) ++{ ++ DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", ++ bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum))); ++ return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum); ++} ++ ++/******************************************************************************* ++* mvDramIfBankSizeGet - Get DRAM interface bank size. ++* ++* DESCRIPTION: ++* This function returns the size of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled the function return '0'. In case ++* or paramter is invalid, the function returns -1. ++* ++*******************************************************************************/ ++MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) ++{ ++ DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", ++ bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum))); ++ return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum); ++} ++ ++ ++/******************************************************************************* ++* mvDramIfSizeGet - Get DRAM interface total size. ++* ++* DESCRIPTION: ++* This function get the DRAM total size. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM total size. In case or paramter is invalid, the function ++* returns -1. ++* ++*******************************************************************************/ ++MV_U32 mvDramIfSizeGet(MV_VOID) ++{ ++ MV_U32 size = 0, i; ++ ++ for(i = 0; i < MV_DRAM_MAX_CS; i++) ++ size += mvDramIfBankSizeGet(i); ++ ++ DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); ++ return size; ++} ++ ++/******************************************************************************* ++* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. ++* ++* DESCRIPTION: ++* The ECC single bit error threshold is the number of single bit ++* errors to happen before the Dunit generates an interrupt. ++* This function set single bit ECC threshold. ++* ++* INPUT: ++* threshold - threshold. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) ++{ ++ MV_U32 regVal; ++ ++ if (threshold > SECR_THRECC_MAX) ++ { ++ return MV_BAD_PARAM; ++ } ++ ++ regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); ++ regVal &= ~SECR_THRECC_MASK; ++ regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); ++ MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); ++ ++ return MV_OK; ++} ++ ++#ifndef MV_STATIC_DRAM_ON_BOARD ++/******************************************************************************* ++* minCasCalc - Calculate the Minimum CAS latency which can be used. ++* ++* DESCRIPTION: ++* Calculate the minimum CAS latency that can be used, base on the DRAM ++* parameters and the SDRAM bus Clock freq. ++* ++* INPUT: ++* busClk - the DRAM bus Clock. ++* pBankInfo - bank info parameters. ++* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* The minimum CAS Latency. The function returns 0 if max CAS latency ++* supported by banks is incompatible with system bus clock frequancy. ++* ++*******************************************************************************/ ++ ++static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) ++{ ++ MV_U32 count = 1, j; ++ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ ++ MV_U32 startBit, stopBit; ++ MV_U32 minCas0 = 0, minCas2 = 0; ++ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * ++ Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * ++ *********************************************************/ ++ ++ ++ /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ ++ if (forcedCl) ++ { ++ mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); ++ ++ if (forcedCl == 30) ++ pBankInfo->suportedCasLatencies = 0x08; ++ else if (forcedCl == 40) ++ pBankInfo->suportedCasLatencies = 0x10; ++ else if (forcedCl == 50) ++ pBankInfo->suportedCasLatencies = 0x20; ++ else if (forcedCl == 60) ++ pBankInfo->suportedCasLatencies = 0x40; ++ else ++ { ++ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", ++ (forcedCl / 10), (forcedCl % 10)); ++ pBankInfo->suportedCasLatencies = 0x10; ++ } ++ ++ return pBankInfo->suportedCasLatencies; ++ } ++ ++ /* go over the supported cas mask from Max Cas down and check if the */ ++ /* SysClk stands in its time requirments. */ ++ ++ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", ++ pBankInfo->suportedCasLatencies,busClkPs )); ++ count = 1; ++ for(j = 7; j > 0; j--) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ /* Reset the bits for CL incompatible for the sysClk */ ++ switch (count) ++ { ++ case 1: ++ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 2: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 3: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ default: ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ break; ++ } ++ } ++ } ++ ++ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", ++ pBankInfo->suportedCasLatencies )); ++ ++ count = 1; ++ DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", ++ pBankInfo2->suportedCasLatencies,busClkPs )); ++ for(j = 7; j > 0; j--) ++ { ++ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) ++ { ++ /* Reset the bits for CL incompatible for the sysClk */ ++ switch (count) ++ { ++ case 1: ++ if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 2: ++ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 3: ++ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ default: ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ break; ++ } ++ } ++ } ++ ++ DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", ++ pBankInfo2->suportedCasLatencies )); ++ ++ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ ++ stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ ++ ++ for(j = startBit; j <= stopBit ; j++) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); ++ minCas0 = (BIT0 << j); ++ break; ++ } ++ } ++ ++ for(j = startBit; j <= stopBit ; j++) ++ { ++ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) ++ { ++ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); ++ minCas2 = (BIT0 << j); ++ break; ++ } ++ } ++ ++ if (minCas2 > minCas0) ++ return minCas2; ++ else ++ return minCas0; ++ ++ return 0; ++} ++ ++/******************************************************************************* ++* sdramConfigRegCalc - Calculate sdram config register ++* ++* DESCRIPTION: Calculate sdram config register optimized value based ++* on the bank info parameters. ++* ++* INPUT: ++* busClk - the DRAM bus Clock. ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram config reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) ++{ ++ MV_U32 sdramConfig = 0; ++ MV_U32 refreshPeriod; ++ ++ busClk /= 1000000; /* we work with busClk in MHz */ ++ ++ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); ++ ++ /* figure out the memory refresh internal */ ++ switch (pBankInfo->refreshInterval & 0xf) ++ { ++ case 0x0: /* refresh period is 15.625 usec */ ++ refreshPeriod = 15625; ++ break; ++ case 0x1: /* refresh period is 3.9 usec */ ++ refreshPeriod = 3900; ++ break; ++ case 0x2: /* refresh period is 7.8 usec */ ++ refreshPeriod = 7800; ++ break; ++ case 0x3: /* refresh period is 31.3 usec */ ++ refreshPeriod = 31300; ++ break; ++ case 0x4: /* refresh period is 62.5 usec */ ++ refreshPeriod = 62500; ++ break; ++ case 0x5: /* refresh period is 125 usec */ ++ refreshPeriod = 125000; ++ break; ++ default: /* refresh period undefined */ ++ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); ++ return -1; ++ } ++ ++ /* Now the refreshPeriod is in register format value */ ++ refreshPeriod = (busClk * refreshPeriod) / 1000; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", ++ refreshPeriod)); ++ ++ /* make sure the refresh value is only 14 bits */ ++ if(refreshPeriod > SDRAM_REFRESH_MAX) ++ { ++ refreshPeriod = SDRAM_REFRESH_MAX; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", ++ refreshPeriod)); ++ } ++ ++ /* Clear the refresh field */ ++ sdramConfig &= ~SDRAM_REFRESH_MASK; ++ ++ /* Set new value to refresh field */ ++ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); ++ ++ /* registered DRAM ? */ ++ if ( pBankInfo->registeredAddrAndControlInputs ) ++ { ++ /* it's registered DRAM, so set the reg. DRAM bit */ ++ sdramConfig |= SDRAM_REGISTERED; ++ DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) ++ } ++ ++ /* ECC and IERR support */ ++ sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ ++ sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ ++ ++ if ( pBankInfo->errorCheckType ) ++ { ++ sdramConfig |= SDRAM_ECC_EN; ++ sdramConfig |= SDRAM_IERR_REPORTE; ++ DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); ++ } ++ else ++ { ++ sdramConfig |= SDRAM_ECC_DIS; ++ sdramConfig |= SDRAM_IERR_IGNORE; ++ DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); ++ } ++ /* Set static default settings */ ++ sdramConfig |= SDRAM_CONFIG_DV; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", ++ sdramConfig)); ++ ++ return sdramConfig; ++} ++ ++/******************************************************************************* ++* sdramModeRegCalc - Calculate sdram mode register ++* ++* DESCRIPTION: Calculate sdram mode register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramModeRegCalc(MV_U32 minCas) ++{ ++ MV_U32 sdramMode; ++ ++ sdramMode = MV_REG_READ(SDRAM_MODE_REG); ++ ++ /* Clear CAS Latency field */ ++ sdramMode &= ~SDRAM_CL_MASK; ++ ++ DB(mvOsPrintf("DRAM CAS Latency ");) ++ ++ switch (minCas) ++ { ++ case DDR2_CL_3: ++ sdramMode |= SDRAM_DDR2_CL_3; ++ DB(mvOsPrintf("3.\n");) ++ break; ++ case DDR2_CL_4: ++ sdramMode |= SDRAM_DDR2_CL_4; ++ DB(mvOsPrintf("4.\n");) ++ break; ++ case DDR2_CL_5: ++ sdramMode |= SDRAM_DDR2_CL_5; ++ DB(mvOsPrintf("5.\n");) ++ break; ++ case DDR2_CL_6: ++ sdramMode |= SDRAM_DDR2_CL_6; ++ DB(mvOsPrintf("6.\n");) ++ break; ++ default: ++ mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); ++ return -1; ++ } ++ ++ DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); ++ ++ return sdramMode; ++} ++/******************************************************************************* ++* sdramExtModeRegCalc - Calculate sdram Extended mode register ++* ++* DESCRIPTION: ++* Return sdram Extended mode register value based ++* on the bank info parameters and bank presence. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - DRAM frequency ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram Extended mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 populateBanks = 0; ++ int bankNum; ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ case(BANK_PRESENT_CS0_CS1): ++ return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; ++ ++ case(BANK_PRESENT_CS0_CS2): ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ if (busClk >= MV_BOARD_SYSCLK_267MHZ) ++ return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; ++ else ++ return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; ++ ++ default: ++ mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++/******************************************************************************* ++* dunitCtrlLowRegCalc - Calculate sdram dunit control low register ++* ++* DESCRIPTION: Calculate sdram dunit control low register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram dunit control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) ++{ ++ MV_U32 dunitCtrlLow, cl; ++ MV_U32 sbOutR[4]={3,5,7,9} ; ++ MV_U32 sbOutU[4]={1,3,5,7} ; ++ ++ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); ++ ++ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); ++ ++ /* Clear StBurstOutDel field */ ++ dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; ++ ++ /* Clear StBurstInDel field */ ++ dunitCtrlLow &= ~SDRAM_SB_IN_MASK; ++ ++ /* Clear CtrlPos field */ ++ dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; ++ ++ /* Clear 2T field */ ++ dunitCtrlLow &= ~SDRAM_2T_MASK; ++ if (TTMode == MV_TRUE) ++ { ++ dunitCtrlLow |= SDRAM_2T_MODE; ++ } ++ ++ /* For proper sample of read data set the Dunit Control register's */ ++ /* stBurstInDel bits [27:24] */ ++ /* 200MHz - 267MHz None reg = CL + 1 */ ++ /* 200MHz - 267MHz reg = CL + 2 */ ++ /* > 267MHz None reg = CL + 2 */ ++ /* > 267MHz reg = CL + 3 */ ++ ++ /* For proper sample of read data set the Dunit Control register's */ ++ /* stBurstOutDel bits [23:20] */ ++ /********-********-********-********- ++ * CL=3 | CL=4 | CL=5 | CL=6 | ++ *********-********-********-********- ++ Not Reg. * 0001 | 0011 | 0101 | 0111 | ++ *********-********-********-********- ++ Registered * 0011 | 0101 | 0111 | 1001 | ++ *********-********-********-********/ ++ ++ /* Set Dunit Control low default value */ ++ dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; ++ ++ switch (minCas) ++ { ++ case DDR2_CL_3: cl = 3; break; ++ case DDR2_CL_4: cl = 4; break; ++ case DDR2_CL_5: cl = 5; break; ++ case DDR2_CL_6: cl = 6; break; ++ default: ++ mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); ++ return -1; ++ } ++ ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ { ++ dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; ++ } ++ else ++ { ++ dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; ++ } ++ ++ DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); ++ ++ if (busClk <= MV_BOARD_SYSCLK_267MHZ) ++ { ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ cl = cl + 2; ++ else ++ cl = cl + 1; ++ } ++ else ++ { ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ cl = cl + 3; ++ else ++ cl = cl + 2; ++ } ++ ++ DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); ++ dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; ++ ++ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); ++ ++ return dunitCtrlLow; ++} ++ ++/******************************************************************************* ++* dunitCtrlHighRegCalc - Calculate sdram dunit control high register ++* ++* DESCRIPTION: Calculate sdram dunit control high register optimized value based ++* on the bus clock. ++* ++* INPUT: ++* busClk - DRAM frequency. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram dunit control high reg value. ++* ++*******************************************************************************/ ++static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 dunitCtrlHigh; ++ dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); ++ if(busClk > MV_BOARD_SYSCLK_300MHZ) ++ dunitCtrlHigh |= SDRAM__P2D_EN; ++ else ++ dunitCtrlHigh &= ~SDRAM__P2D_EN; ++ ++ if(busClk > MV_BOARD_SYSCLK_267MHZ) ++ dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); ++ ++ /* If ECC support we turn on D2P sample */ ++ dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ ++ if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) ++ dunitCtrlHigh |= SDRAM__D2P_EN; ++ ++ return dunitCtrlHigh; ++} ++ ++/******************************************************************************* ++* sdramAddrCtrlRegCalc - Calculate sdram address control register ++* ++* DESCRIPTION: Calculate sdram address control register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram address control reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) ++{ ++ MV_U32 addrCtrl = 0; ++ ++ if (pBankInfoDIMM1->size) ++ { ++ switch (pBankInfoDIMM1->sdramWidth) ++ { ++ case 4: /* memory is x4 */ ++ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); ++ return -1; ++ break; ++ case 8: /* memory is x8 */ ++ addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); ++ break; ++ case 16: ++ addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); ++ break; ++ default: /* memory width unsupported */ ++ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); ++ return -1; ++ } ++ } ++ ++ switch (pBankInfo->sdramWidth) ++ { ++ case 4: /* memory is x4 */ ++ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); ++ return -1; ++ break; ++ case 8: /* memory is x8 */ ++ addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); ++ break; ++ case 16: ++ addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); ++ break; ++ default: /* memory width unsupported */ ++ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); ++ return -1; ++ } ++ ++ /* Note that density is in MB units */ ++ switch (pBankInfo->deviceDensity) ++ { ++ case 256: /* 256 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); ++ break; ++ case 512: /* 512 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); ++ break; ++ case 1024: /* 1 Gbit */ ++ DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); ++ break; ++ case 2048: /* 2 Gbit */ ++ DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); ++ break; ++ default: ++ mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", ++ pBankInfo->deviceDensity); ++ return -1; ++ } ++ ++ if (pBankInfoDIMM1->size) ++ { ++ switch (pBankInfoDIMM1->deviceDensity) ++ { ++ case 256: /* 256 Mbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); ++ break; ++ case 512: /* 512 Mbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); ++ break; ++ case 1024: /* 1 Gbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); ++ break; ++ case 2048: /* 2 Gbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); ++ break; ++ default: ++ mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", ++ pBankInfoDIMM1->deviceDensity); ++ return -1; ++ } ++ } ++ /* SDRAM address control */ ++ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); ++ ++ return addrCtrl; ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control low register ++* optimized value based on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* minCas - minimum CAS supported. ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timing control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) ++{ ++ MV_U32 tRp = 0; ++ MV_U32 tRrd = 0; ++ MV_U32 tRcd = 0; ++ MV_U32 tRas = 0; ++ MV_U32 tWr = 0; ++ MV_U32 tWtr = 0; ++ MV_U32 tRtp = 0; ++ MV_U32 timeCtrlLow = 0; ++ ++ MV_U32 bankNum; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); ++ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); ++ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); ++ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ ++ /* by shifting the data two bits right. */ ++ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ ++ tRrd = tRrd >> 2; ++ tRcd = tRcd >> 2; ++ ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); ++ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRrd = 2 */ ++ if (tRrd < 2) ++ tRrd = 2; ++ DB(mvOsPrintf("tRrd = %d ", tRrd)); ++ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRcd = %d ", tRcd)); ++ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRas = %d ", tRas)); ++ ++ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); ++ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); ++ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ ++ /* part by shifting the data two bits right. */ ++ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ ++ tWtr = tWtr >> 2; ++ tRtp = tRtp >> 2; ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tWr = %d ", tWr)); ++ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tWtr = 2 */ ++ if (tWtr < 2) ++ tWtr = 2; ++ DB(mvOsPrintf("tWtr = %d ", tWtr)); ++ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRtp = 2 */ ++ if (tRtp < 2) ++ tRtp = 2; ++ DB(mvOsPrintf("tRtp = %d ", tRtp)); ++ ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | ++ ((tRrd - 1) << SDRAM_TRRD_OFFS) | ++ ((tRcd - 1) << SDRAM_TRCD_OFFS) | ++ (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| ++ ((tWr - 1) << SDRAM_TWR_OFFS) | ++ ((tWtr - 1) << SDRAM_TWTR_OFFS) | ++ ((tRtp - 1) << SDRAM_TRTP_OFFS)); ++ ++ /* Check extended tRas bit */ ++ if ((tRas - 1) & BIT4) ++ timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); ++ ++ return timeCtrlLow; ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control high register ++* optimized value based on the bank info parameters and the bus clock. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timing control high reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 tRfc; ++ MV_U32 timingHigh; ++ MV_U32 timeNs = 0; ++ MV_U32 bankNum; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* Set DDR timing high register static configuration bits */ ++ timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); ++ ++ /* Set DDR timing high register default value */ ++ timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; ++ ++ /* Clear tRfc field */ ++ timingHigh &= ~SDRAM_TRFC_MASK; ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); ++ DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", ++ pBankInfo[bankNum].minRefreshToActiveCmd)); ++ } ++ if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) ++ { ++ timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; ++ } ++ ++ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); ++ timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); ++ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); ++ ++ /* SDRAM timing high */ ++ DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); ++ ++ return timingHigh; ++} ++/******************************************************************************* ++* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. ++* ++* DESCRIPTION: ++* This function config DDR2 On Die Termination (ODT) registers. ++* ++* INPUT: ++* pBankInfo - bank info parameters. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* None ++*******************************************************************************/ ++static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 populateBanks = 0; ++ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; ++ int bankNum; ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ case(BANK_PRESENT_CS0_CS1): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2): ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; ++ break; ++ default: ++ DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); ++ return; ++ } ++ /* DDR2 SDRAM ODT ctrl low */ ++ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); ++ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); ++ ++ /* DDR2 SDRAM ODT ctrl high */ ++ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); ++ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); ++ ++ /* DDR2 DUNIT ODT ctrl */ ++ if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || ++ (mvCtrlModelGet() == MV_76100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78200_DEV_ID) ) ++ dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ ++ ++ DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); ++ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); ++ return; ++} ++/******************************************************************************* ++* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. ++* ++* DESCRIPTION: ++* This function config DDR2 DRAM Timing low registers. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* DDR2 sdram timing low reg value. ++*******************************************************************************/ ++static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) ++{ ++ MV_U8 cl = -1; ++ MV_U32 ddr2TimeLoReg; ++ ++ /* read and clear the feilds we are going to set */ ++ ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); ++ ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | ++ SD2TLR_TODT_OFF_RD_MASK | ++ SD2TLR_TODT_ON_CTRL_RD_MASK | ++ SD2TLR_TODT_OFF_CTRL_RD_MASK); ++ ++ if( minCas == DDR2_CL_3 ) ++ { ++ cl = 3; ++ } ++ else if( minCas == DDR2_CL_4 ) ++ { ++ cl = 4; ++ } ++ else if( minCas == DDR2_CL_5 ) ++ { ++ cl = 5; ++ } ++ else if( minCas == DDR2_CL_6 ) ++ { ++ cl = 6; ++ } ++ else ++ { ++ DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", ++ minCas)); ++ cl = 4; ++ } ++ ++ ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); ++ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); ++ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); ++ ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); ++ ++ /* DDR2 SDRAM timing low */ ++ DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); ++ ++ return ddr2TimeLoReg; ++} ++ ++/******************************************************************************* ++* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. ++* ++* DESCRIPTION: ++* This function config DDR2 DRAM Timing high registers. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* DDR2 sdram timing high reg value. ++*******************************************************************************/ ++static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) ++{ ++ MV_U8 cl = -1; ++ MV_U32 ddr2TimeHiReg; ++ ++ /* read and clear the feilds we are going to set */ ++ ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); ++ ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | ++ SD2THR_TODT_OFF_WR_MASK | ++ SD2THR_TODT_ON_CTRL_WR_MASK | ++ SD2THR_TODT_OFF_CTRL_WR_MASK); ++ ++ if( minCas == DDR2_CL_3 ) ++ { ++ cl = 3; ++ } ++ else if( minCas == DDR2_CL_4 ) ++ { ++ cl = 4; ++ } ++ else if( minCas == DDR2_CL_5 ) ++ { ++ cl = 5; ++ } ++ else if( minCas == DDR2_CL_6 ) ++ { ++ cl = 6; ++ } ++ else ++ { ++ mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", ++ minCas); ++ cl = 4; ++ } ++ ++ ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); ++ ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); ++ ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); ++ ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); ++ ++ /* DDR2 SDRAM timin high */ ++ DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); ++ ++ return ddr2TimeHiReg; ++} ++#endif ++ ++/******************************************************************************* ++* mvDramIfCalGet - Get CAS Latency ++* ++* DESCRIPTION: ++* This function get the CAS Latency. ++* ++* INPUT: ++* None ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* CAS latency times 10 (to avoid using floating point). ++* ++*******************************************************************************/ ++MV_U32 mvDramIfCalGet(void) ++{ ++ MV_U32 sdramCasLat, casLatMask; ++ ++ casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); ++ ++ switch (casLatMask) ++ { ++ case SDRAM_DDR2_CL_3: ++ sdramCasLat = 30; ++ break; ++ case SDRAM_DDR2_CL_4: ++ sdramCasLat = 40; ++ break; ++ case SDRAM_DDR2_CL_5: ++ sdramCasLat = 50; ++ break; ++ case SDRAM_DDR2_CL_6: ++ sdramCasLat = 60; ++ break; ++ default: ++ mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); ++ return -1; ++ } ++ ++ return sdramCasLat; ++} ++ ++ ++/******************************************************************************* ++* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - ++* ++* DESCRIPTION: ++* add support in power management. ++* ++* ++* INPUT: ++* None ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* None ++* ++*******************************************************************************/ ++ ++MV_VOID mvDramIfSelfRefreshSet() ++{ ++ MV_U32 operReg; ++ ++ operReg = MV_REG_READ(SDRAM_OPERATION_REG); ++ MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); ++ /* Read until register is reset to 0 */ ++ while(MV_REG_READ(SDRAM_OPERATION_REG)); ++} ++/******************************************************************************* ++* mvDramIfDimGetSPDversion - return DIMM SPD version. ++* ++* DESCRIPTION: ++* This function prints the DRAM controller information. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) ++{ ++ MV_DIMM_INFO dimmInfo; ++ if (bankNum >= MV_DRAM_MAX_CS ) ++ { ++ DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); ++ return ; ++ } ++ memset(&dimmInfo,0,sizeof(dimmInfo)); ++ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); ++ return ; ++ } ++ *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; ++ *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; ++} ++/******************************************************************************* ++* mvDramIfShow - Show DRAM controller information. ++* ++* DESCRIPTION: ++* This function prints the DRAM controller information. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++void mvDramIfShow(void) ++{ ++ int i, sdramCasLat, sdramCsSize; ++ MV_U32 Major=0, Minor=0; ++ ++ mvOsOutput("DRAM Controller info:\n"); ++ ++ mvOsOutput("Total DRAM "); ++ mvSizePrint(mvDramIfSizeGet()); ++ mvOsOutput("\n"); ++ ++ for(i = 0; i < MV_DRAM_MAX_CS; i++) ++ { ++ sdramCsSize = mvDramIfBankSizeGet(i); ++ if (sdramCsSize) ++ { ++ if (0 == (i & 1)) ++ { ++ mvDramIfDimGetSPDversion(&Major, &Minor,i); ++ mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); ++ } ++ mvOsOutput("\tDRAM CS[%d] ", i); ++ mvSizePrint(sdramCsSize); ++ mvOsOutput("\n"); ++ } ++ } ++ sdramCasLat = mvDramIfCalGet(); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) ++ { ++ mvOsOutput("ECC enabled, "); ++ } ++ else ++ { ++ mvOsOutput("ECC Disabled, "); ++ } ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) ++ { ++ mvOsOutput("Registered DIMM\n"); ++ } ++ else ++ { ++ mvOsOutput("Non registered DIMM\n"); ++ } ++ ++ mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); ++} ++/******************************************************************************* ++* mvDramIfGetFirstCS - find the DRAM bank on the lower address ++* ++* ++* DESCRIPTION: ++* This function return the fisrt CS on address 0 ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* SDRAM_CS0 or SDRAM_CS2 ++* ++*******************************************************************************/ ++MV_U32 mvDramIfGetFirstCS(void) ++{ ++ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; ++ ++ if (DRAM_CS_Order[0] == N_A) ++ { ++ mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); ++#endif ++ ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) ++ { ++ DRAM_CS_Order[0] = SDRAM_CS2; ++ DRAM_CS_Order[1] = SDRAM_CS3; ++ DRAM_CS_Order[2] = SDRAM_CS0; ++ DRAM_CS_Order[3] = SDRAM_CS1; ++ ++ return SDRAM_CS2; ++ } ++#endif ++ DRAM_CS_Order[0] = SDRAM_CS0; ++ DRAM_CS_Order[1] = SDRAM_CS1; ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ DRAM_CS_Order[2] = SDRAM_CS2; ++ DRAM_CS_Order[3] = SDRAM_CS3; ++#endif ++ return SDRAM_CS0; ++ } ++ return DRAM_CS_Order[0]; ++} ++/******************************************************************************* ++* mvDramIfGetCSorder - ++* ++* ++* DESCRIPTION: ++* This function return the fisrt CS on address 0 ++* ++* INPUT: ++* CS number. ++* ++* OUTPUT: ++* CS order. ++* ++* RETURN: ++* SDRAM_CS0 or SDRAM_CS2 ++* ++* NOTE: mvDramIfGetFirstCS must be caled before this subroutine ++*******************************************************************************/ ++MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) ++{ ++ return DRAM_CS_Order[csOrder]; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,172 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfh ++#define __INCmvDramIfh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* includes */ ++#include "ddr2/mvDramIfRegs.h" ++#include "ddr2/mvDramIfConfig.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* defines */ ++/* DRAM Timing parameters */ ++#define SDRAM_TWR 15 /* ns tWr */ ++#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ ++#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ ++#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ ++#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ ++ ++#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ ++#define ECC_DISABLE 1 /* Force ECC to Disable */ ++#define ECC_ENABLE 0 /* Force ECC to ENABLE */ ++/* typedefs */ ++ ++/* enumeration for memory types */ ++typedef enum _mvMemoryType ++{ ++ MEM_TYPE_SDRAM, ++ MEM_TYPE_DDR1, ++ MEM_TYPE_DDR2 ++}MV_MEMORY_TYPE; ++ ++/* enumeration for DDR2 supported CAS Latencies */ ++typedef enum _mvDimmDdr2Cas ++{ ++ DDR2_CL_3 = 0x08, ++ DDR2_CL_4 = 0x10, ++ DDR2_CL_5 = 0x20, ++ DDR2_CL_6 = 0x40, ++ DDR2_CL_FAULT ++} MV_DIMM_DDR2_CAS; ++ ++ ++typedef struct _mvDramBankInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ ++ MV_U32 numberOfDevices; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ MV_BOOL registeredAddrAndControlInputs; ++ MV_BOOL registeredDQMBinputs; ++ ++}MV_DRAM_BANK_INFO; ++ ++#include "ddr2/spd/mvSpd.h" ++ ++/* mvDramIf.h API list */ ++MV_VOID mvDramIfBasicAsmInit(MV_VOID); ++MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); ++MV_VOID _mvDramIfConfig(int entryNum); ++ ++MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); ++MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); ++MV_U32 mvDramIfSizeGet(MV_VOID); ++MV_U32 mvDramIfCalGet(void); ++MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); ++MV_VOID mvDramIfSelfRefreshSet(void); ++void mvDramIfShow(void); ++MV_U32 mvDramIfGetFirstCS(void); ++MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); ++MV_U32 mvDramCsSizeGet(MV_U32 csNum); ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,986 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#define _ASMLANGUAGE ++#define MV_ASMLANGUAGE ++#include "mvSysHwConfig.h" ++#include "mvOsAsm.h" ++#include "boardEnv/mvBoardEnvSpec.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++#include "mvDramIfConfig.h" ++#include "mvDramIfRegs.h" ++#include "pex/mvPexRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/mvCtrlEnvAsm.h" ++#include "mvCommon.h" ++ ++/* defines */ ++ ++#if defined(MV_STATIC_DRAM_ON_BOARD) ++.globl dramBoot1 ++dramBoot1: ++ .word 0 ++ ++/****************************************************************************** ++* ++* ++* ++* ++*******************************************************************************/ ++#if defined(DB_MV78XX0) || defined(DB_MV88F632X) ++/* DDR2 boards 512MB 333MHz */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++ ++#elif defined(RD_MV78XX0_AMC) ++/* On board DDR2 512MB 400MHz CL5 */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++ ++#elif defined(RD_MV78XX0_H3C) ++/* DDR2 boards 512MB 333MHz */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++ ++#elif defined(RD_MV78XX0_PCAC) ++/* DDR2 boards 256MB 200MHz */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++ ++#else ++/* DDR2 MV88F6281 boards 256MB 400MHz */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++#endif /* MV78XX0 */ ++ ++ .globl _mvDramIfStaticInit ++_mvDramIfStaticInit: ++ ++ mov r11, LR /* Save link register */ ++ mov r10, r2 ++ ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++ orr r6, r6, #BIT4 /* Enable 2T mode */ ++ bic r6, r6, #BIT6 /* clear ctrlPos */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++#endif ++ ++ /*DDR SDRAM Initialization Control */ ++ ldr r6, =DSICR_INIT_EN ++ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) ++2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) ++ and r6, r6, #DSICR_INIT_EN ++ cmp r6, #0 ++ bne 2b ++ ++ /* If we boot from NAND jump to DRAM address */ ++ mov r5, #1 ++ ldr r6, =dramBoot1 ++ str r5, [r6] /* We started executing from DRAM */ ++ ++ ldr r6, dramBoot1 ++ cmp r6, #0 ++ bne 1f ++ ++ /* set all dram windows to 0 */ ++ mov r6, #0 ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1)) ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2)) ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3)) ++ ldr r6, = STATIC_SDRAM0_BANK0_SIZE ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) ++ ++ ++ /* set all dram configuration in temp registers */ ++ ldr r6, = STATIC_SDRAM0_BANK0_SIZE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) ++ ldr r6, = STATIC_SDRAM_CONFIG ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) ++ ldr r6, = STATIC_SDRAM_MODE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) ++ ldr r6, = STATIC_DUNIT_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) ++ ldr r6, = STATIC_SDRAM_ADDR_CTRL ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) ++ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) ++ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) ++ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) ++ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) ++ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) ++ ldr r6, = STATIC_SDRAM_EXT_MODE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) ++ ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11) ++ ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12) ++#ifndef MV_NAND_BOOT ++ ldr r6, = STATIC_DUNIT_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13) ++#endif ++ ++ ldr sp,=0 ++ bl _mvDramIfConfig ++ ldr r0, =0 ++#ifdef MV78XX0 ++ bl _mvDramIfEccMemInit ++#endif ++1: ++ mov r2, r10 ++ mov PC, r11 /* r11 is saved link register */ ++ ++#else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */ ++ ++.globl dramBoot1 ++dramBoot1: ++ .word 0 ++ ++/******************************************************************************* ++* mvDramIfBasicInit - Basic initialization of DRAM interface ++* ++* DESCRIPTION: ++* The function will initialize the DRAM for basic usage. The function ++* will use the TWSI assembly API to extract DIMM parameters according ++* to which DRAM interface will be initialized. ++* The function referes to the following DRAM parameters: ++* 1) DIMM is registered or not. ++* 2) DIMM width detection. ++* 3) DIMM density. ++* ++* INPUT: ++* r3 - required size for initial DRAM. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++* Note: ++* r4 holds I2C EEPROM address ++* r5 holds SDRAM register base address ++* r7 holds returned values ++* r8 holds SDRAM various configuration registers value. ++* r11 holds return function address. ++*******************************************************************************/ ++/* Setting the offsets of the I2C registers */ ++#define DIMM_TYPE_OFFSET 2 ++#define NUM_OF_ROWS_OFFSET 3 ++#define NUM_OF_COLS_OFFSET 4 ++#define NUM_OF_RANKS 5 ++#define DIMM_CONFIG_TYPE 11 ++#define SDRAM_WIDTH_OFFSET 13 ++#define NUM_OF_BANKS_OFFSET 17 ++#define SUPPORTED_CL_OFFSET 18 ++#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ ++#define SDRAM_MODULES_ATTR_OFFSET 21 ++#define RANK_SIZE_OFFSET 31 ++ ++#define DRAM_DEV_DENSITY_128M 128 ++#define DRAM_DEV_DENSITY_256M 256 ++#define DRAM_DEV_DENSITY_512M 512 ++#define DRAM_DEV_DENSITY_1G 1024 ++#define DRAM_DEV_DENSITY_2G 2048 ++ ++#define DRAM_RANK_DENSITY_128M 0x20 ++#define DRAM_RANK_DENSITY_256M 0x40 ++#define DRAM_RANK_DENSITY_512M 0x80 ++#define DRAM_RANK_DENSITY_1G 0x1 ++#define DRAM_RANK_DENSITY_2G 0x2 ++ ++ .globl _mvDramIfBasicInit ++ .extern _i2cInit ++_mvDramIfBasicInit: ++ ++ mov r11, LR /* Save link register */ ++ ++ /* Set Dunit high control register */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) ++ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ ++ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ ++#ifdef MV78XX0 ++ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ ++ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ ++ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ ++#endif ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) ++ ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++ orr r6, r6, #BIT4 /* Enable 2T mode */ ++ bic r6, r6, #BIT6 /* clear ctrlPos */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++#endif ++ ++ /*DDR SDRAM Initialization Control */ ++ ldr r6, =DSICR_INIT_EN ++ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) ++2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) ++ and r6, r6, #DSICR_INIT_EN ++ cmp r6, #0 ++ bne 2b ++ ++ mov r5, #1 ++ ldr r8, =dramBoot1 ++ str r5, [r8] /* We started executing from DRAM */ ++ ++ /* If we boot from NAND jump to DRAM address */ ++ ldr r8, dramBoot1 ++ cmp r8, #0 ++ movne pc, r11 ++ ++ bl _i2cInit /* Initialize TWSI master */ ++ ++ /* Check if we have more then 1 dimm */ ++ ldr r6, =0 ++ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) ++#ifdef MV78XX0 ++ bl _is_Second_Dimm_Exist ++ beq single_dimm ++ ldr r6, =1 ++ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) ++single_dimm: ++ bl _i2cInit /* Initialize TWSI master */ ++#endif ++ ++ /* Get default SDRAM Config values */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ ++ /* Get registered/non registered info from DIMM */ ++ bl _is_Registered ++ beq nonRegistered ++ ++setRegistered: ++ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ ++nonRegistered: ++#ifdef MV78XX0 ++ /* Get ECC/non ECC info from DIMM */ ++ bl _is_Ecc ++ beq setConfigReg ++ ++setEcc: ++ orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */ ++#endif ++setConfigReg: ++ MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1) ++ ++ /* Set maximum CL supported by DIMM */ ++ bl _get_CAL ++ ++ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ ++ clz r6, r7 ++ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ ++ ++casDdr2: ++ ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */ ++ ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/ ++ ldr r8, =0x32 /* Assuming MAX CL = 3 */ ++ cmp r6, #3 /* If CL = 3 break */ ++ beq casDdr2Cont ++ ++ ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */ ++ ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/ ++ ldr r8, =0x42 /* Assuming MAX CL = 4 */ ++ cmp r6, #4 /* If CL = 4 break */ ++ beq casDdr2Cont ++ ++ ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */ ++ ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/ ++ ldr r8, =0x52 /* Assuming MAX CL = 5 */ ++ cmp r6, #5 /* If CL = 5 break */ ++ beq casDdr2Cont ++ ++ ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */ ++ ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/ ++ ldr r8, =0x62 /* Assuming MAX CL = 6 */ ++ cmp r6, #6 /* If CL = 5 break */ ++ beq casDdr2Cont ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig /* This is an error !! */ ++casDdr2Cont: ++ ++ /* Get default SDRAM Mode values */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG) ++ bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */ ++ orr r6, r6, r8 ++ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2) ++ ++ /* Set Dunit control register according to max CL detected */ ++ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1) ++ tst r6, #SDRAM_REGISTERED ++ beq setDunitReg ++ mov r7, r3 ++ ++setDunitReg: ++#ifdef MV78XX0 ++ /* Set SDRAM Extended Mode register for double DIMM */ ++ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ ++ ++ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) ++ ldr r5, =MSAR_SYSCLCK_MASK ++ and r4, r4, r5 ++ ldr r5, =MSAR_SYSCLCK_333 ++ cmp r4, r5 ++ ble Clock333 ++ add r7, r7, #0x10 ++Clock333: ++#endif ++ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++ bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */ ++ orr r6, r6, #BIT4 /* Enable 2T mode */ ++ bic r6, r6, #BIT6 /* clear ctrlPos */ ++ orr r6, r6, r7, LSL #20 ++ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3) ++ ++ /* Set Dunit high control register */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) ++ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ ++ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ ++#ifdef MV78XX0 ++ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ ++ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ ++ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ ++#endif ++ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13) ++ ++ /* DIMM density configuration*/ ++ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ ++Density: ++ /* Get bank 0 and 1 density */ ++ ldr r6, =0 ++ bl _getDensity ++ ++ mov r8, r7 ++ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ ++ /* For example 0x10000000 --> 0x1000 */ ++ ++ mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1)) ++ cmp r8, #DRAM_DEV_DENSITY_256M ++ beq get_bank_2_density ++ ++ mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1)) ++ cmp r8, #DRAM_DEV_DENSITY_512M ++ beq get_bank_2_density ++ ++ mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1)) ++ cmp r8, #DRAM_DEV_DENSITY_1G ++ beq get_bank_2_density ++ ++ mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1)) ++ cmp r8, #DRAM_DEV_DENSITY_2G ++ beq get_bank_2_density ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++get_bank_2_density: ++ /* Check for second dimm */ ++ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) ++ cmp r6, #1 ++ bne get_width ++ ++ /* Get bank 2 and 3 density */ ++ ldr r6, =2 ++ bl _getDensity ++ ++ mov r8, r7 ++ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ ++ /* For example 0x10000000 --> 0x1000 */ ++ ++ orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3)) ++ cmp r8, #DRAM_DEV_DENSITY_256M ++ beq get_width ++ ++ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) ++ orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3)) ++ cmp r8, #DRAM_DEV_DENSITY_512M ++ beq get_width ++ ++ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) ++ orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3)) ++ cmp r8, #DRAM_DEV_DENSITY_1G ++ beq get_width ++ ++ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) ++ orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3)) ++ cmp r8, #DRAM_DEV_DENSITY_2G ++ beq get_width ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++ /* Get SDRAM width */ ++get_width: ++ /* Get bank 0 and 1 width */ ++ ldr r6, =0 ++ bl _get_width ++ ++ cmp r7, #8 /* x8 devices */ ++ beq get_bank_2_width ++ ++ orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */ ++ cmp r7, #16 ++ beq get_bank_2_width ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++get_bank_2_width: ++ /* Check for second dimm */ ++ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) ++ cmp r6, #1 ++ bne densCont ++ ++ /* Get bank 2 and 3 width */ ++ ldr r6, =2 ++ bl _get_width ++ ++ cmp r7, #8 /* x8 devices */ ++ beq densCont ++ ++ orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */ ++ cmp r7, #16 ++ beq densCont ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++densCont: ++ MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4) ++ ++ /* Set SDRAM timing control low register */ ++ ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT ++ /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */ ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5) ++ ++ /* Set SDRAM timing control high register */ ++ ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT ++ ++ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) ++ ldr r5, =MSAR_SYSCLCK_MASK ++ and r4, r4, r5 ++ ldr r5, =MSAR_SYSCLCK_333 ++ cmp r4, r5 ++ blt timingHighClock333 ++ orr r6, r6, #BIT9 ++ ++timingHighClock333: ++ /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */ ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) ++ ++ /* Check for second dimm */ ++ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) ++ cmp r6, #1 ++ bne single_dimm_odt ++ ++ /* Set SDRAM ODT control low register for double DIMM*/ ++ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) ++ ++ /* Set DUNIT ODT control register for double DIMM */ ++ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) ++ ++#ifdef MV78XX0 ++ /* Set SDRAM Extended Mode register for double DIMM */ ++ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ ++ ++ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) ++ ldr r5, =MSAR_SYSCLCK_MASK ++ and r4, r4, r5 ++ ldr r5, =MSAR_SYSCLCK_267 ++ cmp r4, r5 ++ beq slow_dram_clock_rtt ++ ldr r5, =MSAR_SYSCLCK_300 ++ cmp r4, r5 ++ beq slow_dram_clock_rtt ++ ldr r5, =MSAR_SYSCLCK_333 ++ cmp r4, r5 ++ beq fast_dram_clock_rtt ++ ldr r5, =MSAR_SYSCLCK_400 ++ cmp r4, r5 ++ beq fast_dram_clock_rtt ++ ++ b slow_dram_clock_rtt ++ ++fast_dram_clock_rtt: ++ ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) ++ b odt_config_end ++#endif ++slow_dram_clock_rtt: ++ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) ++ b odt_config_end ++ ++single_dimm_odt: ++ /* Set SDRAM ODT control low register */ ++ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) ++ ++ /* Set DUNIT ODT control register */ ++ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) ++ ++ /* Set SDRAM Extended Mode register */ ++ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) ++ ++odt_config_end: ++ /* SDRAM ODT control high register is left as default */ ++ MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8) ++ ++ /*Read CL and set the DDR2 registers accordingly */ ++ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2) ++ and r6, r6, #SDRAM_CL_MASK ++ mov r4, r6 ++ orr r4, r4, r6, LSL #4 ++ orr r4, r4, r6, LSL #8 ++ orr r4, r4, r6, LSL #12 ++ mov r5, #0x30000 ++ add r4, r4, r5 ++ sub r4, r4, #0x30 ++ /* Set SDRAM Ddr2 Timing Low register */ ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11) ++ ++ /* Set SDRAM Ddr2 Timing High register */ ++ mov r4, r4, LSR #4 ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12) ++ ++timeParamDone: ++ /* Close all windows */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) ++ ++ /* Set sdram bank 0 size and enable it */ ++ ldr r6, =0 ++ bl _mvDramIfGetDimmSizeFromSpd ++#ifdef MV78XX0 ++ /* Check DRAM width */ ++ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) ++ ldr r5, =SDRAM_DWIDTH_MASK ++ and r4, r4, r5 ++ ldr r5, =SDRAM_DWIDTH_64BIT ++ cmp r4, r5 ++ beq dram_64bit_width ++ /* Utilize only 32bit width */ ++ mov r8, r8, LSR #1 ++#else ++ /* Utilize only 16bit width */ ++ mov r8, r8, LSR #2 ++#endif ++dram_64bit_width: ++ /* Update first dimm size return value R8 */ ++ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0)) ++ ldr r6, =~SCSR_SIZE_MASK ++ and r5, r5, r6 ++ orr r5, r5, r8 ++ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0)) ++ ++ /* Clear bank 2 size */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ ++ /* Check for second dimm */ ++ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) ++ cmp r6, #1 ++ bne defualt_order ++ ++ /* Set sdram bank 2 size */ ++ ldr r6, =2 ++ bl _mvDramIfGetDimmSizeFromSpd ++#ifdef MV78XX0 ++ /* Check DRAM width */ ++ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) ++ ldr r5, =SDRAM_DWIDTH_MASK ++ and r4, r4, r5 ++ ldr r5, =SDRAM_DWIDTH_64BIT ++ cmp r4, r5 ++ beq dram_64bit_width2 ++ /* Utilize only 32bit width */ ++ mov r8, r8, LSR #1 ++#else ++ /* Utilize only 16bit width */ ++ mov r8, r8, LSR #2 ++#endif ++dram_64bit_width2: ++ /* Update first dimm size return value R8 */ ++ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2)) ++ ldr r6, =~SCSR_SIZE_MASK ++ and r5, r5, r6 ++ orr r5, r5, r8 ++ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2)) ++ ++ /* Close windows 1 and 3 */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) ++ ++ /* Check dimm size for setting dram bank order */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2)) ++ and r6, r6,#SCSR_SIZE_MASK ++ and r4, r4,#SCSR_SIZE_MASK ++ cmp r6, r4 ++ bge defualt_order ++ ++ /* Bank 2 is biger then bank 0 */ ++ ldr r6,=0 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2)) ++ ++ /* Open win 2 */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ orr r6, r6,#1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ ++ ldr sp,=0 ++ bl _mvDramIfConfig ++#ifdef MV78XX0 ++ /* Init ECC on CS 2 */ ++ ldr r0, =2 ++ bl _mvDramIfEccMemInit ++#endif ++ mov PC, r11 /* r11 is saved link register */ ++ ++defualt_order: ++ ++ /* Open win 0 */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ orr r6, r6,#1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ ++ ldr sp,=0 ++ bl _mvDramIfConfig ++#ifdef MV78XX0 ++ /* Init ECC on CS 0 */ ++ ldr r0, =0 ++ bl _mvDramIfEccMemInit ++#endif ++exit_ddrAutoConfig: ++ mov PC, r11 /* r11 is saved link register */ ++ ++ ++/***************************************************************************************/ ++/* r4 holds I2C EEPROM address ++ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value ++ * r8 holds SDRAM various configuration registers value. ++ * r13 holds Link register ++ */ ++/**************************/ ++_getDensity: ++ mov r13, LR /* Save link register */ ++ ++ /* Read SPD rank size from DIMM0 */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ ++ cmp r6, #0 ++ beq 1f ++ ++ /* Read SPD rank size from DIMM1 */ ++ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ ++ ++1: ++ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ ++ bl _i2cRead ++ mov r8, r7 /* r8 save number of rows */ ++ ++ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ ++ bl _i2cRead ++ add r8, r8, r7 /* r8 = number of rows + number of col */ ++ ++ mov r7, #0x1 ++ mov r8, r7, LSL r8 /* r8 = (1 << r8) */ ++ ++ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ ++ bl _i2cRead ++ mul r8, r7, r8 ++ ++ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ ++ bl _i2cRead ++ mul r7, r8, r7 ++ ++ mov PC, r13 ++ ++/**************************/ ++_get_width: ++ mov r13, LR /* Save link register */ ++ ++ /* Read SPD rank size from DIMM0 */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ ++ cmp r6, #0 ++ beq 1f ++ ++ /* Read SPD rank size from DIMM1 */ ++ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ ++ ++1: ++ /* Get SDRAM width (SPD offset 13) */ ++ mov r7, #SDRAM_WIDTH_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ mov PC, r13 ++ ++/**************************/ ++_get_CAL: ++ mov r13, LR /* Save link register */ ++ ++ /* Set maximum CL supported by DIMM */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ ++ bl _i2cRead ++ ++ mov PC, r13 ++ ++/**************************/ ++/* R8 - sdram configuration register. ++ * Return value in flag if no-registered then Z-flag is set ++ */ ++_is_Registered: ++ mov r13, LR /* Save link register */ ++#if defined(MV645xx) ++ /* Get registered/non registered info from DIMM */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ bne regDdr2 ++ ++regDdr1: ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SDRAM_MODULES_ATTR_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ tst r7, #0x2 ++ b exit ++#endif ++regDdr2: ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #DIMM_TYPE_INFO_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ ++ /* or Mini-RDIMM (0x10) */ ++exit: ++ mov PC, r13 ++ ++ ++/**************************/ ++/* Return value in flag if no-Ecc then Z-flag is set */ ++_is_Ecc: ++ mov r13, LR /* Save link register */ ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #DIMM_CONFIG_TYPE ++ bl _i2cRead /* result in r7 */ ++ ++ tst r7, #0x2 /* bit 1 -> Data ECC */ ++ mov PC, r13 ++ ++/**************************/ ++/* Return value in flag if no second DIMM then Z-flag is set */ ++_is_Second_Dimm_Exist: ++ mov r13, LR /* Save link register */ ++ ++ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #DIMM_TYPE_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ tst r7, #0x8 /* bit3 is '1' -> DDR 2 */ ++ mov PC, r13 ++ ++/******************************************************************************* ++* _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size ++* ++* DESCRIPTION: ++* The function will read the bank 0 dram size(SPD version 1.0 and above ) ++* ++* INPUT: ++* r6 - dram bank number. ++* ++* OUTPUT: ++* none ++*/ ++_mvDramIfGetDimmSizeFromSpd: ++ ++ mov r13, LR /* Save link register */ ++ ++ /* Read SPD rank size from DIMM0 */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ ++ cmp r6, #0 ++ beq 1f ++ ++ /* Read SPD rank size from DIMM1 */ ++ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ ++ ++1: ++ mov r7, #RANK_SIZE_OFFSET /* offset 31 */ ++ bl _i2cRead ++ ++pass_read: ++ ldr r8, =(0x7 << SCSR_SIZE_OFFS) ++ cmp r7, #DRAM_RANK_DENSITY_128M ++ beq endDimmSize ++ ++ ldr r8, =(0xf << SCSR_SIZE_OFFS) ++ cmp r7, #DRAM_RANK_DENSITY_256M ++ beq endDimmSize ++ ++ ldr r8, =(0x1f << SCSR_SIZE_OFFS) ++ cmp r7, #DRAM_RANK_DENSITY_512M ++ beq endDimmSize ++ ++ ldr r8, =(0x3f << SCSR_SIZE_OFFS) ++ cmp r7, #DRAM_RANK_DENSITY_1G ++ beq endDimmSize ++ ++ ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */ ++endDimmSize: ++ mov PC, r13 ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,528 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvDramIfBasicAsm.s ++* ++* DESCRIPTION: ++* Memory full detection and best timing configuration is done in ++* C code. C runtime environment requires a stack. This module API ++* initialize DRAM interface chip select 0 for basic functionality for ++* the use of stack. ++* The module API assumes DRAM information is stored in I2C EEPROM reside ++* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM ++* internal data structure is assumed to be orgenzied in common DRAM ++* vendor SPD structure. ++* NOTE: DFCDL values are assumed to be already initialized prior to ++* this module API activity. ++* ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#define _ASMLANGUAGE ++#define MV_ASMLANGUAGE ++#include "mvOsAsm.h" ++#include "mvSysHwConfig.h" ++#include "mvDramIfRegs.h" ++#include "mvDramIfConfig.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++#include "pex/mvPexRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "mvCommon.h" ++ ++/* defines */ ++ ++/* locals */ ++.data ++.globl _mvDramIfConfig ++.text ++.globl _mvDramIfMemInit ++ ++/******************************************************************************* ++* _mvDramIfConfig - Basic DRAM interface initialization. ++* ++* DESCRIPTION: ++* The function will initialize the following DRAM parameters using the ++* values prepared by mvDramIfDetect routine. Values are located ++* in predefined registers. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++ ++_mvDramIfConfig: ++ ++ /* Save register on stack */ ++ cmp sp, #0 ++ beq no_stack_s ++save_on_stack: ++ stmdb sp!, {r1, r2, r3, r4} ++no_stack_s: ++ ++ /* Dunit FTDLL Configuration Register */ ++ /* 0) Write to SDRAM FTDLL coniguration register */ ++ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT; ++ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG) ++ str r4, [r1] ++ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT; ++ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG) ++ str r4, [r1] ++ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP; ++ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG) ++ str r4, [r1] ++ ++ /* 1) Write to SDRAM coniguration register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) ++ str r4, [r1] ++ ++ /* 2) Write Dunit control low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) ++ str r4, [r1] ++ ++ /* 2) Write Dunit control high register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG) ++ str r4, [r1] ++ ++ /* 3) Write SDRAM address control register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) ++ str r4, [r1] ++#if defined(MV_STATIC_DRAM_ON_BOARD) ++ /* 4) Write SDRAM bank 0 size register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0)) ++ str r4, [r1] ++#endif ++ ++ /* 5) Write SDRAM open pages control register */ ++ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) ++ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV ++ str r4, [r1] ++ ++ /* 6) Write SDRAM timing Low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) ++ str r4, [r1] ++ ++ /* 7) Write SDRAM timing High register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) ++ str r4, [r1] ++ ++ /* Config DDR2 On Die Termination (ODT) registers */ ++ /* Write SDRAM DDR2 ODT control low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) ++ str r4, [r1] ++ ++ /* Write SDRAM DDR2 ODT control high register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) ++ str r4, [r1] ++ ++ /* Write SDRAM DDR2 Dunit ODT control register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) ++ str r4, [r1] ++ ++ /* Write DDR2 SDRAM timing Low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG) ++ str r4, [r1] ++ ++ /* Write DDR2 SDRAM timing High register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG) ++ str r4, [r1] ++ ++ /* 8) Write SDRAM mode register */ ++ /* The CPU must not attempt to change the SDRAM Mode register setting */ ++ /* prior to DRAM controller completion of the DRAM initialization */ ++ /* sequence. To guarantee this restriction, it is recommended that */ ++ /* the CPU sets the SDRAM Operation register to NOP command, performs */ ++ /* read polling until the register is back in Normal operation value, */ ++ /* and then sets SDRAM Mode register to its new value. */ ++ ++ /* 8.1 write 'nop' to SDRAM operation */ ++ mov r4, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) ++ ++ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll1: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll1 ++ ++ /* 8.3 Now its safe to write new value to SDRAM Mode register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) ++ str r4, [r1] ++ ++ /* 8.4 Make the Dunit write the DRAM its new mode */ ++ mov r4, #0x3 /* Mode Register Set command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll2: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll2 ++ ++ /* Now its safe to write new value to SDRAM Extended Mode regist */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) ++ str r4, [r1] ++ ++ /* 9) Write SDRAM Extended mode register This operation should be */ ++ /* done for each memory bank */ ++ /* write 'nop' to SDRAM operation */ ++ mov r4, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll3: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll3 ++ /* Go over each of the Banks */ ++ ldr r3, =0 /* r3 = DRAM bank Num */ ++ ++extModeLoop: ++ /* Set the SDRAM Operation Control to each of the DRAM banks */ ++ mov r4, r3 /* Do not swap the bank counter value */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG) ++ ++ /* Make the Dunit write the DRAM its new mode */ ++ mov r4, #0x4 /* Extended Mode Register Set command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll4: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll4 ++ ++ add r3, r3, #1 ++ cmp r3, #4 /* 4 = Number of banks */ ++ bne extModeLoop ++ ++extModeEnd: ++cmp sp, #0 ++ beq no_stack_l ++ mov r1, LR /* Save link register */ ++#if defined(MV78XX0) ++ bl _mvDramIfMemInit ++#endif ++ mov LR,r1 /* restore link register */ ++load_from_stack: ++ /* Restore registers */ ++ ldmia sp!, {r1, r2, r3, r4} ++no_stack_l: ++ ++ mov pc, lr ++ ++ ++/******************************************************************************* ++* _mvDramIfEccMemInit - Basic DRAM ECC initialization. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */ ++#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */ ++#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */ ++/* XOR engine register offsets macros */ ++#define XOR_CONFIG_REG(chan) (XOR_UNIT_BASE(0) + 0x10 + ((chan) * 4)) ++#define XOR_ACTIVATION_REG(chan) (XOR_UNIT_BASE(0) + 0x20 + ((chan) * 4)) ++#define XOR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x30) ++#define XOR_ERROR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x50) ++#define XOR_ERROR_ADDR_REG (XOR_UNIT_BASE(0) + 0x60) ++#define XOR_INIT_VAL_LOW_REG (XOR_UNIT_BASE(0) + 0x2E0) ++#define XOR_INIT_VAL_HIGH_REG (XOR_UNIT_BASE(0) + 0x2E4) ++#define XOR_DST_PTR_REG(chan) (XOR_UNIT_BASE(0) + 0x2B0 + ((chan) * 4)) ++#define XOR_BLOCK_SIZE_REG(chan) (XOR_UNIT_BASE(0) + 0x2C0 + ((chan) * 4)) ++ ++/* XOR Engine Address Decoding Register Map */ ++#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) ++#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) ++#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) ++ ++.globl _mvDramIfEccMemInit ++/******************************************************************************* ++* _mvDramIfEccMemInit - mem init for dram cs ++* ++* DESCRIPTION: ++* This function will clean the cs by ussing the XOR mem init. ++* ++* INPUT: ++* r0 - dram bank number. ++* ++* OUTPUT: ++* none ++*/ ++_mvDramIfEccMemInit: ++ ++ /* Save register on stack */ ++ cmp sp, #0 ++ beq no_stack_s1 ++save_on_stack1: ++ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} ++no_stack_s1: ++ ++ ldr r1, = 0 ++ ++ /* Disable all XOR address decode windows to avoid possible overlap */ ++ MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))) ++ ++ /* Init r5 to first XOR_SIZE_MASK_REG */ ++ mov r5, r0, LSL #3 ++ add r5, r5,#0x1500 ++ add r5, r5,#0x04 ++ add r5, r5,#(INTER_REGS_BASE) ++ ldr r6, [r5] ++ HTOLL(r6,r5) ++ MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) ++ ++ mov r5, r0, LSL #3 ++ add r5, r5,#0x1500 ++ add r5, r5,#(INTER_REGS_BASE) ++ ldr r6, [r5] ++ /* Update destination & size */ ++ MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0)) ++ HTOLL(r6,r5) ++ /* Init r6 to first XOR_BASE_ADDR_REG */ ++ ldr r4, = 0xf ++ ldr r5, = 0x1 ++ mov r5, r5, LSL r0 ++ bic r4, r4, r5 ++ mov r4, r4, LSL #8 ++ ++ orr r6, r6, r4 ++ MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) ++ ++ ldr r6, = 0xff0001 ++ MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)) ++ ++ /* Configure XOR engine for memory init function. */ ++ MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) ++ and r6, r6, #~0x7 /* Clear operation mode field */ ++ orr r6, r6, #0x4 /* Set operation to memory init */ ++ MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) ++ ++ /* Set initVal in the XOR Engine Initial Value Registers */ ++ ldr r6, = 0xfeedfeed ++ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG) ++ ldr r6, = 0xfeedfeed ++ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG) ++ ++ /* Set block size using DRAM bank size */ ++ ++ mov r5, r0, LSL #3 ++ add r5, r5,#0x1500 ++ add r5, r5,#0x04 ++ add r5, r5,#(INTER_REGS_BASE) ++ ++ ldr r6, [r5] ++ HTOLL(r6,r5) ++ and r6, r6, #SCSR_SIZE_MASK ++ mov r5, r6, LSR #SCSR_SIZE_OFFS ++ add r5, r5, #1 ++ mov r6, r5, LSL #SCSR_SIZE_OFFS ++ MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0)) ++ ++ /* Clean interrupt cause*/ ++ MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG) ++ ++ /* Clean error interrupt cause*/ ++ MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG) ++ MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG) ++ ++ /* Start transfer */ ++ MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) ++ orr r6, r6, #0x1 /* Preform start command */ ++ MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) ++ ++ /* Wait for engine to finish */ ++waitForComplete: ++ MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG) ++ and r6, r6, #2 ++ cmp r6, #0 ++ beq waitForComplete ++ ++ /* Clear all error report registers */ ++ MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG) ++ MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG) ++ ++ MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG) ++ ++ cmp sp, #0 ++ beq no_stack_l1 ++load_from_stack1: ++ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} ++no_stack_l1: ++ mov pc, lr ++ ++ ++/******************************************************************************* ++* mvDramIfMemInit - Use XOR to clear all memory. ++* ++* DESCRIPTION: ++* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern. ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++#if defined(MV78XX0) ++ ++_mvDramIfMemInit: ++ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} ++ mov r6, LR /* Save link register */ ++ /* Check if dram bank 0 has to be init for ECC */ ++ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0)) ++ and r3, r0, #SCSR_WIN_EN ++ cmp r3, #0 ++ beq no_bank_0 ++ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0)) ++ cmp r0, #0 ++ beq no_bank_0 ++ mov r0,#0 ++ bl _mvDramIfEccMemInit ++ ++no_bank_0: ++ /* Check if dram bank 1 has to be init for ECC */ ++ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1)) ++ and r0, r0, #SCSR_WIN_EN ++ cmp r0, #0 ++ beq no_bank_1 ++ mov r0,#1 ++ bl _mvDramIfEccMemInit ++no_bank_1: ++ /* Check if dram bank 2 has to be init for ECC */ ++ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2)) ++ and r0, r0, #SCSR_WIN_EN ++ cmp r0, #0 ++ beq no_bank_2 ++ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2)) ++ cmp r0, #0 ++ beq no_bank_2 ++ mov r0,#2 ++ bl _mvDramIfEccMemInit ++ ++no_bank_2: ++ /* Check if dram bank 3 has to be init for ECC */ ++ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3)) ++ and r0, r0, #SCSR_WIN_EN ++ cmp r0, #0 ++ beq no_bank_3 ++ mov r0,#3 ++ bl _mvDramIfEccMemInit ++no_bank_3: ++ mov LR ,r6 /* restore link register */ ++ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} ++ mov pc, lr ++#endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,157 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfConfigh ++#define __INCmvDramIfConfigh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* includes */ ++ ++/* defines */ ++ ++/* registers defaults values */ ++ ++#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) ++ ++#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ ++ (SDRAM_SRCLK_KEPT | \ ++ SDRAM_CLK1DRV_NORMAL | \ ++ (BIT28 | BIT29)) ++ ++#define SDRAM_ADDR_CTRL_DV 2 ++ ++#define SDRAM_TIMING_CTRL_LOW_REG_DV \ ++ ((0x2 << SDRAM_TRCD_OFFS) | \ ++ (0x2 << SDRAM_TRP_OFFS) | \ ++ (0x1 << SDRAM_TWR_OFFS) | \ ++ (0x0 << SDRAM_TWTR_OFFS) | \ ++ (0x5 << SDRAM_TRAS_OFFS) | \ ++ (0x1 << SDRAM_TRRD_OFFS)) ++ ++/* Note: value of 0 in register means one cycle, 1 means two and so on */ ++#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ ++ ((0x0 << SDRAM_TR2R_OFFS) | \ ++ (0x0 << SDRAM_TR2W_W2R_OFFS) | \ ++ (0x1 << SDRAM_TW2W_OFFS)) ++ ++#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN ++ ++/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ ++/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++ ++#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 ++#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F ++#ifdef MV78XX0 ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 ++#else ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 ++#endif ++ ++#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C ++#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F ++#ifdef MV78XX0 ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 ++#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 ++#else ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 ++#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 ++#endif ++ ++/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ ++#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++/* DDR SDRAM Mode Register default value */ ++#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) ++/* DDR SDRAM Timing parameter default values */ ++#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 ++#define SDRAM_TRFC_DEFAULT_VALUE 0x34 ++#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE ++#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) ++ ++#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) ++ ++#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 ++#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 ++#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,423 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDramIfRegsh ++#define __INCmvDramIfRegsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* DDR SDRAM Controller Address Decode Registers */ ++ /* SDRAM CSn Base Address Register (SCBAR) */ ++#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) ++#define SCBAR_BASE_OFFS 16 ++#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) ++#define SCBAR_BASE_ALIGNMENT 0x10000 ++ ++/* SDRAM CSn Size Register (SCSR) */ ++#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) ++#define SCSR_SIZE_OFFS 24 ++#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) ++#define SCSR_SIZE_ALIGNMENT 0x1000000 ++#define SCSR_WIN_EN BIT0 ++ ++/* configuration register */ ++#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400) ++#define SDRAM_REFRESH_OFFS 0 ++#define SDRAM_REFRESH_MAX 0x3FFF ++#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) ++#define SDRAM_DWIDTH_OFFS 15 ++#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_REGISTERED (1 << 17) ++#define SDRAM_ECC_OFFS 18 ++#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) ++#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) ++#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) ++#define SDRAM_IERR_OFFS 19 ++#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) ++#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) ++#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) ++#define SDRAM_SRMODE_OFFS 24 ++#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) ++#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) ++#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) ++ ++/* dunit control low register */ ++#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404) ++#define SDRAM_2T_OFFS 4 ++#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) ++#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) ++ ++#define SDRAM_SRCLK_OFFS 5 ++#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_CTRL_POS_OFFS 6 ++#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CLK1DRV_OFFS 12 ++#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK2DRV_OFFS 13 ++#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) ++#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) ++#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) ++#define SDRAM_SB_OUT_DEL_OFFS 20 ++#define SDRAM_SB_OUT_DEL_MAX 0xf ++#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS )) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ memset(pBankInfo, 0, sizeof(*pBankInfo)); ++ ++ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); ++ return MV_FAIL; ++ } ++ if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); ++ return MV_FAIL; ++ } ++ /* convert Dimm info to Bank info */ ++ cpyDimm2BankInfo(&dimmInfo, pBankInfo); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. ++* ++* DESCRIPTION: ++* Convert a Dimm info struct into a bank info struct. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* pBankInfo - DRAM bank information struct. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, ++ MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ pBankInfo->memoryType = pDimmInfo->memoryType; ++ ++ /* DIMM dimensions */ ++ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; ++ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; ++ pBankInfo->dataWidth = pDimmInfo->dataWidth; ++ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; ++ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; ++ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; ++ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; ++ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; ++ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; ++ ++ /* DIMM timing parameters */ ++ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; ++ ++ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; ++ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; ++ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; ++ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; ++ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; ++ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; ++ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; ++ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; ++ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; ++ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / ++ pDimmInfo->numOfModuleBanks; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ ++ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || ++ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) ++ { ++ if (pDimmInfo->dimmAttributes & BIT1) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ ++ { ++ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ ++ return; ++} ++/******************************************************************************* ++* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdCpy(MV_VOID) ++{ ++ MV_U32 i; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the DIMM 1 SPD */ ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ twsiSlave.offset = i; ++ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) ) ++ { ++ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); ++ return MV_FAIL; ++ } ++ mvOsDelay(5); ++ } ++ ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdGet - Get the SPD parameters. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters into given struct parameter. ++* ++* INPUT: ++* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. ++* ++* OUTPUT: ++* pDimmInfo - DIMM information structure. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) ++{ ++ MV_U32 i; ++ MV_U32 density = 1; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = (dimmNum == 0) ? ++ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the dimmInfo structure*/ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ pDimmInfo->spdRawData[i] = data[i]; ++ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); ++ } ++ ++ DB(mvOsPrintf("DRAM SPD Information:\n")); ++ ++ /* Memory type (DDR / SDRAM) */ ++ switch (data[DIMM_MEM_TYPE]) ++ { ++ case (DIMM_MEM_TYPE_SDRAM): ++ pDimmInfo->memoryType = MEM_TYPE_SDRAM; ++ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR1): ++ pDimmInfo->memoryType = MEM_TYPE_DDR1; ++ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR2): ++ pDimmInfo->memoryType = MEM_TYPE_DDR2; ++ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); ++ break; ++ default: ++ mvOsPrintf("ERROR: Undefined memory type!\n"); ++ return MV_ERROR; ++ } ++ ++ ++ /* Number Of Row Addresses */ ++ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; ++ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); ++ ++ /* Number Of Column Addresses */ ++ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; ++ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); ++ ++ /* Number Of Module Banks */ ++ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", ++ pDimmInfo->numOfModuleBanks)); ++ ++ /* Number of module banks encoded differently for DDR2 */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; ++ ++ /* Data Width */ ++ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); ++ ++ /* Minimum Cycle Time At Max CasLatancy */ ++ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); ++ ++ /* Error Check Type */ ++ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; ++ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", ++ pDimmInfo->errorCheckType)); ++ ++ /* Refresh Interval */ ++ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; ++ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", ++ pDimmInfo->refreshInterval)); ++ ++ /* Sdram Width */ ++ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; ++ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); ++ ++ /* Error Check Data Width */ ++ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", ++ pDimmInfo->errorCheckDataWidth)); ++ ++ /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; ++ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", ++ pDimmInfo->burstLengthSupported)); ++ ++ /* Number Of Banks On Each Device */ ++ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", ++ pDimmInfo->numOfBanksOnEachDevice)); ++ ++ /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; ++ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", ++ pDimmInfo->suportedCasLatencies)); ++ ++ /* For DDR2 only, get the DIMM type information */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ { ++ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; ++ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", ++ pDimmInfo->dimmTypeInfo)); ++ } ++ ++ /* SDRAM Modules Attributes */ ++ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; ++ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", ++ pDimmInfo->dimmAttributes)); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); ++ ++ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; ++ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", ++ pDimmInfo->minRowPrechargeTime)); ++ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; ++ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", ++ pDimmInfo->minRowActiveToRowActive)); ++ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; ++ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", ++ pDimmInfo->minRasToCasDelay)); ++ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; ++ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", ++ pDimmInfo->minRasPulseWidth)); ++ ++ /* DIMM Bank Density */ ++ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; ++ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", ++ pDimmInfo->dimmBankDensity)); ++ ++ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ ++ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; ++ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", ++ pDimmInfo->minWriteRecoveryTime)); ++ ++ /* Only DDR2 includes Internal Write To Read Command Delay field. */ ++ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", ++ pDimmInfo->minWriteToReadCmdDelay)); ++ ++ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ ++ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", ++ pDimmInfo->minReadToPrechCmdDelay)); ++ ++ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ ++ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; ++ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", ++ pDimmInfo->minRefreshToActiveCmd)); ++ ++ /* calculating the sdram density. Representing device density from */ ++ /* bit 20 to allow representation of 4GB and above. */ ++ /* For example, if density is 512Mbit 0x20000000, will be represent in */ ++ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ ++ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ ++ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); ++ pDimmInfo->deviceDensity = density * ++ pDimmInfo->numOfBanksOnEachDevice * ++ pDimmInfo->sdramWidth; ++ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); ++ ++ /* Number of devices includeing Error correction */ ++ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * ++ pDimmInfo->numOfModuleBanks; ++ DB(mvOsPrintf("DRAM numberOfDevices %d\n", ++ pDimmInfo->numberOfDevices)); ++ ++ pDimmInfo->size = 0; ++ ++ /* Note that pDimmInfo->size is in MB units */ ++ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 8; /* Equal to 8MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 4096; /* Equal to 4GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 8192; /* Equal to 8GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 16384; /* Equal to 16GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ ++ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; ++ ++ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdPrint - Print the SPD parameters. ++* ++* DESCRIPTION: ++* Print the Dimm SPD parameters. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID dimmSpdPrint(MV_U32 dimmNum) ++{ ++ MV_DIMM_INFO dimmInfo; ++ MV_U32 i, temp = 0; ++ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; ++ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; ++ MV_U32 busClkPs; ++ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, ++ temp_buf[40], *spdRawData; ++ ++ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ ++ ++ spdRawData = dimmInfo.spdRawData; ++ ++ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) ++ { ++ mvOsOutput("ERROR: Could not read SPD information!\n"); ++ return; ++ } ++ ++ /* find Manufactura of Dimm Module */ ++ mvOsOutput("\nManufacturer's JEDEC ID Code: "); ++ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) ++ { ++ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); ++ } ++ mvOsOutput("\n"); ++ ++ /* Manufacturer's Specific Data */ ++ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; ++ } ++ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); ++ ++ /* Module Part Number */ ++ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; ++ } ++ mvOsOutput("Module Part Number: %s\n", temp_buf); ++ ++ /* Module Serial Number */ ++ for(i = 0; i < sizeof(MV_U32); i++) ++ { ++ temp |= spdRawData[95+i] << 8*i; ++ } ++ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, ++ (long)temp); ++ ++ /* find Manufac-Data of Dimm Module */ ++ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", ++ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), ++ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); ++ /* find modul_revision of Dimm Module */ ++ mvOsOutput("Module Revision: %d.%d\n", ++ spdRawData[62]/10, spdRawData[62]%10); ++ ++ /* find manufac_place of Dimm Module */ ++ mvOsOutput("manufac_place: %d\n", spdRawData[72]); ++ ++ /* go over the first 35 I2C data bytes */ ++ for(i = 2 ; i <= 35 ; i++) ++ switch(i) ++ { ++ case 2: /* Memory type (DDR1/2 / SDRAM) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ mvOsOutput("Dram Type is: SDRAM\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ mvOsOutput("Dram Type is: SDRAM DDR1\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ mvOsOutput("Dram Type is: SDRAM DDR2\n"); ++ else ++ mvOsOutput("Dram Type unknown\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 3: /* Number Of Row Addresses */ ++ mvOsOutput("Module Number of row addresses: %d\n", ++ dimmInfo.numOfRowAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 4: /* Number Of Column Addresses */ ++ mvOsOutput("Module Number of col addresses: %d\n", ++ dimmInfo.numOfColAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 5: /* Number Of Module Banks */ ++ mvOsOutput("Number of Banks on Mod.: %d\n", ++ dimmInfo.numOfModuleBanks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 6: /* Data Width */ ++ mvOsOutput("Module Data Width: %d bit\n", ++ dimmInfo.dataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 8: /* Voltage Interface */ ++ switch(spdRawData[i]) ++ { ++ case 0x0: ++ mvOsOutput("Module is TTL_5V_TOLERANT\n"); ++ break; ++ case 0x1: ++ mvOsOutput("Module is LVTTL\n"); ++ break; ++ case 0x2: ++ mvOsOutput("Module is HSTL_1_5V\n"); ++ break; ++ case 0x3: ++ mvOsOutput("Module is SSTL_3_3V\n"); ++ break; ++ case 0x4: ++ mvOsOutput("Module is SSTL_2_5V\n"); ++ break; ++ case 0x5: ++ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) ++ { ++ mvOsOutput("Module is SSTL_1_8V\n"); ++ break; ++ } ++ default: ++ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); ++ break; ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 9: /* Minimum Cycle Time At Max CasLatancy */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 10: /* Clock To Data Out */ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 11: /* Error Check Type */ ++ mvOsOutput("Error Check Type (0=NONE): %d\n", ++ dimmInfo.errorCheckType); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 12: /* Refresh Interval */ ++ mvOsOutput("Refresh Rate: %x\n", ++ dimmInfo.refreshInterval); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 13: /* Sdram Width */ ++ mvOsOutput("Sdram Width: %d bits\n", ++ dimmInfo.sdramWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 14: /* Error Check Data Width */ ++ mvOsOutput("Error Check Data Width: %d bits\n", ++ dimmInfo.errorCheckDataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 15: /* Minimum Clock Delay is unsupported */ ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ mvOsOutput("Minimum Clk Delay back to back: %d\n", ++ spdRawData[i]); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 16: /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ mvOsOutput("Burst Length Supported: "); ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ if (dimmInfo.burstLengthSupported & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.burstLengthSupported & BIT1) ++ mvOsOutput("2, "); ++ } ++ if (dimmInfo.burstLengthSupported & BIT2) ++ mvOsOutput("4, "); ++ if (dimmInfo.burstLengthSupported & BIT3) ++ mvOsOutput("8, "); ++ ++ mvOsOutput(" Bit \n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 17: /* Number Of Banks On Each Device */ ++ mvOsOutput("Number Of Banks On Each Chip: %d\n", ++ dimmInfo.numOfBanksOnEachDevice); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 18: /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ mvOsOutput("Suported Cas Latencies: (CL) "); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ for (k = 0; k <=7; k++) ++ { ++ if (dimmInfo.suportedCasLatencies & (1 << k)) ++ mvOsOutput("%d, ", k+1); ++ } ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.suportedCasLatencies & BIT1) ++ mvOsOutput("1.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("2.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("3.5, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("4, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("5, "); ++ } ++ else ++ mvOsOutput("?.?, "); ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 20: /* DDR2 DIMM type info */ ++ if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) ++ mvOsOutput("Registered DIMM (RDIMM)\n"); ++ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) ++ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); ++ else ++ mvOsOutput("Unknown DIMM type.\n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 21: /* SDRAM Modules Attributes */ ++ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" Bufferd DQMB Input: Yes \n"); ++ else ++ mvOsOutput(" Bufferd DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" Registered DQMB Inputs: Yes \n"); ++ else ++ mvOsOutput(" Registered DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" redundant Row Addressing: Yes \n"); ++ else ++ mvOsOutput(" redundant Row Addressing: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch On-Card Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", ++ (dimmInfo.dimmAttributes & 0x3) + 1); ++ ++ mvOsOutput(" Number of PLLs on the DIMM: %d\n", ++ ((dimmInfo.dimmAttributes) >> 2) & 0x3); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" Analysis probe installed: Yes \n"); ++ else ++ mvOsOutput(" Analysis probe installed: No \n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 22: /* Suported AutoPreCharge */ ++ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Early Ras Precharge: Yes \n"); ++ else ++ mvOsOutput(" Early Ras Precharge: No \n"); ++ ++ if ( spdRawData[i] & BIT1 ) ++ mvOsOutput(" AutoPreCharge: Yes \n"); ++ else ++ mvOsOutput(" AutoPreCharge: No \n"); ++ ++ if ( spdRawData[i] & BIT2 ) ++ mvOsOutput(" Precharge All: Yes \n"); ++ else ++ mvOsOutput(" Precharge All: No \n"); ++ ++ if ( spdRawData[i] & BIT3 ) ++ mvOsOutput(" Write 1/ReadBurst: Yes \n"); ++ else ++ mvOsOutput(" Write 1/ReadBurst: No \n"); ++ ++ if ( spdRawData[i] & BIT4 ) ++ mvOsOutput(" lower VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" lower VCC tolerance: 10%%\n"); ++ ++ if ( spdRawData[i] & BIT5 ) ++ mvOsOutput(" upper VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" upper VCC tolerance: 10%%\n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ ++ if ( !(spdRawData[i] & BIT4) ) ++ mvOsOutput(" lower VCC tolerance: 0.2V\n"); ++ ++ if ( !(spdRawData[i] & BIT5) ) ++ mvOsOutput(" upper VCC tolerance: 0.2V\n"); ++ ++ if ( spdRawData[i] & BIT6 ) ++ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); ++ else ++ mvOsOutput(" Concurrent Auto Preharge: No \n"); ++ ++ if ( spdRawData[i] & BIT7 ) ++ mvOsOutput(" Supports Fast AP: Yes \n"); ++ else ++ mvOsOutput(" Supports Fast AP: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 23: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ ++ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 25: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ } ++ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = 0; ++ rightOfPoint = time_tmp; ++ } ++ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 27: /* Minimum Row Precharge Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ ++ trp_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 28: /* Minimum Row Active to Row Active Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " ++ "%d.%d = in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 29: /* Minimum Ras-To-Cas Delay */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; ++ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 30: /* Minimum Ras Pulse Width */ ++ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " ++ "in Clk cycles %d\n", spdRawData[i], tras_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 31: /* Module Bank Density */ ++ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("8MB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("4GB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("8GB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("16GB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 32: /* Address And Command Setup Time (measured in ns/1000) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 33: /* Address And Command Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 34: /* Data Input Setup Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 35: /* Data Input Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 36: /* Relevant for DDR2 only: Write Recovery Time */ ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; ++ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ } ++ ++} ++ ++ ++/* ++ * translate ns.ns/10 coding of SPD timing values ++ * into ps unit values ++ */ ++/******************************************************************************* ++* cas2ps - Translate x.y ns parameter to pico-seconds values ++* ++* DESCRIPTION: ++* This function translates x.y nano seconds to its value in pico seconds. ++* For example 3.75ns will return 3750. ++* ++* INPUT: ++* spd_byte - DIMM SPD byte. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* value in pico seconds. ++* ++*******************************************************************************/ ++static MV_U32 cas2ps(MV_U8 spd_byte) ++{ ++ MV_U32 ns, ns10; ++ ++ /* isolate upper nibble */ ++ ns = (spd_byte >> 4) & 0x0F; ++ /* isolate lower nibble */ ++ ns10 = (spd_byte & 0x0F); ++ ++ if( ns10 < 10 ) { ++ ns10 *= 10; ++ } ++ else if( ns10 == 10 ) ++ ns10 = 25; ++ else if( ns10 == 11 ) ++ ns10 = 33; ++ else if( ns10 == 12 ) ++ ns10 = 66; ++ else if( ns10 == 13 ) ++ ns10 = 75; ++ else ++ { ++ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); ++ } ++ ++ return (ns*1000 + ns10*10); ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,192 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDram ++#define __INCmvDram ++ ++#include "ddr2/mvDramIf.h" ++#include "twsi/mvTwsi.h" ++ ++#define MAX_DIMM_NUM 2 ++#define SPD_SIZE 128 ++ ++/* Dimm spd offsets */ ++#define DIMM_MEM_TYPE 2 ++#define DIMM_ROW_NUM 3 ++#define DIMM_COL_NUM 4 ++#define DIMM_MODULE_BANK_NUM 5 ++#define DIMM_DATA_WIDTH 6 ++#define DIMM_VOLT_IF 8 ++#define DIMM_MIN_CC_AT_MAX_CAS 9 ++#define DIMM_ERR_CHECK_TYPE 11 ++#define DIMM_REFRESH_INTERVAL 12 ++#define DIMM_SDRAM_WIDTH 13 ++#define DIMM_ERR_CHECK_DATA_WIDTH 14 ++#define DIMM_MIN_CLK_DEL 15 ++#define DIMM_BURST_LEN_SUP 16 ++#define DIMM_DEV_BANK_NUM 17 ++#define DIMM_SUP_CAL 18 ++#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ ++#define DIMM_BUF_ADDR_CONT_IN 21 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 ++#define DIMM_MIN_ROW_PRECHARGE_TIME 27 ++#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 ++#define DIMM_MIN_RAS_TO_CAS_DELAY 29 ++#define DIMM_MIN_RAS_PULSE_WIDTH 30 ++#define DIMM_BANK_DENSITY 31 ++#define DIMM_MIN_WRITE_RECOVERY_TIME 36 ++#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 ++#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 ++#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 ++#define DIMM_SPD_VERSION 62 ++ ++/* Dimm Memory Type values */ ++#define DIMM_MEM_TYPE_SDRAM 0x4 ++#define DIMM_MEM_TYPE_DDR1 0x7 ++#define DIMM_MEM_TYPE_DDR2 0x8 ++ ++#define DIMM_MODULE_MANU_OFFS 64 ++#define DIMM_MODULE_MANU_SIZE 8 ++#define DIMM_MODULE_VEN_OFFS 73 ++#define DIMM_MODULE_VEN_SIZE 25 ++#define DIMM_MODULE_ID_OFFS 99 ++#define DIMM_MODULE_ID_SIZE 18 ++ ++/* enumeration for voltage levels. */ ++typedef enum _mvDimmVoltageIf ++{ ++ TTL_5V_TOLERANT, ++ LVTTL, ++ HSTL_1_5V, ++ SSTL_3_3V, ++ SSTL_2_5V, ++ VOLTAGE_UNKNOWN, ++} MV_DIMM_VOLTAGE_IF; ++ ++ ++/* enumaration for SDRAM CAS Latencies. */ ++typedef enum _mvDimmSdramCas ++{ ++ SD_CL_1 =1, ++ SD_CL_2, ++ SD_CL_3, ++ SD_CL_4, ++ SD_CL_5, ++ SD_CL_6, ++ SD_CL_7, ++ SD_FAULT ++}MV_DIMM_SDRAM_CAS; ++ ++ ++/* DIMM information structure */ ++typedef struct _mvDimmInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ ++ ++ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 numOfModuleBanks; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ MV_U32 dimmBankDensity; ++ MV_U32 dimmTypeInfo; /* DDR2 only */ ++ MV_U32 dimmAttributes; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ ++ MV_U32 numberOfDevices; ++ ++} MV_DIMM_INFO; ++ ++ ++MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); ++MV_VOID dimmSpdPrint(MV_U32 dimmNum); ++MV_STATUS dimmSpdCpy(MV_VOID); ++ ++#endif /* __INCmvDram */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,2952 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvEth.c - Marvell's Gigabit Ethernet controller low level driver ++* ++* DESCRIPTION: ++* This file introduce OS independent APIs to Marvell's Gigabit Ethernet ++* controller. This Gigabit Ethernet Controller driver API controls ++* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). ++* 2) Data flow (i.e. port Send, Receive etc'). ++* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) ++* 4) MIB counters support (ethReadMibCounter) ++* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) ++* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. ++* This struct includes configuration information as well as driver ++* internal data needed for its operations. ++* ++* Supported Features: ++* - OS independent. All required OS services are implemented via external ++* OS dependent components (like osLayer or ethOsg) ++* - The user is free from Rx/Tx queue managing. ++* - Simple Gigabit Ethernet port operation API. ++* - Simple Gigabit Ethernet port data flow API. ++* - Data flow and operation API support per queue functionality. ++* - Support cached descriptors for better performance. ++* - PHY access and control API. ++* - Port Configuration API. ++* - Full control over Special and Other Multicast MAC tables. ++* ++*******************************************************************************/ ++/* includes */ ++#include "mvTypes.h" ++#include "mv802_3.h" ++#include "mvDebug.h" ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "eth-phy/mvEthPhy.h" ++#include "eth/mvEth.h" ++#include "eth/gbe/mvEthGbe.h" ++#include "cpu/mvCpu.h" ++ ++#ifdef INCLUDE_SYNC_BARR ++#include "sys/mvCpuIf.h" ++#endif ++ ++#ifdef MV_RT_DEBUG ++# define ETH_DEBUG ++#endif ++ ++ ++/* locals */ ++MV_BOOL ethDescInSram; ++MV_BOOL ethDescSwCoher; ++ ++/* This array holds the control structure of each port */ ++ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS]; ++ ++/* Ethernet Port Local routines */ ++ ++static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); ++ ++static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); ++ ++static void ethSetUcastTable(int portNo, int queue); ++ ++static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue); ++static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); ++static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); ++ ++static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf); ++static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size, ++ MV_ULONG* pPhysAddr, MV_U32 *memHandle); ++ ++static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); ++ ++static void mvEthPortSgmiiConfig(int port); ++ ++ ++ ++/******************************************************************************/ ++/* EthDrv Initialization functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthHalInit - Initialize the Giga Ethernet unit ++* ++* DESCRIPTION: ++* This function initialize the Giga Ethernet unit. ++* 1) Configure Address decode windows of the unit ++* 2) Set registers to HW default values. ++* 3) Clear and Disable interrupts ++* ++* INPUT: NONE ++* ++* RETURN: NONE ++* ++* NOTE: this function is called once in the boot process. ++*******************************************************************************/ ++void mvEthHalInit(void) ++{ ++ int port; ++ ++ /* Init static data structures */ ++ for (port=0; port 0) ++ { ++ isSram = MV_TRUE; ++ #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) ++ isSwCoher = MV_TRUE; ++ #else ++ isSwCoher = MV_FALSE; ++ #endif ++ } ++#endif /* ETH_DESCR_IN_SRAM */ ++ ++ if(pIsSram != NULL) ++ *pIsSram = isSram; ++ ++ if(pIsSwCoher != NULL) ++ *pIsSwCoher = isSwCoher; ++} ++ ++ ++ ++/******************************************************************************/ ++/* Port Initialization functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthPortInit - Initialize the Ethernet port driver ++* ++* DESCRIPTION: ++* This function initialize the ethernet port. ++* 1) Allocate and initialize internal port Control structure. ++* 2) Create RX and TX descriptor rings for default RX and TX queues ++* 3) Disable RX and TX operations, clear cause registers and ++* mask all interrupts. ++* 4) Set all registers to default values and clean all MAC tables. ++* ++* INPUT: ++* int portNo - Ethernet port number ++* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure ++* ++* RETURN: ++* void* - ethernet port handler, that should be passed to the most other ++* functions dealing with this port. ++* ++* NOTE: This function is called once per port when loading the eth module. ++*******************************************************************************/ ++void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit) ++{ ++ int queue, descSize; ++ ETH_PORT_CTRL* pPortCtrl; ++ ++ /* Check validity of parameters */ ++ if( (portNo >= (int)mvCtrlEthMaxPortGet()) || ++ (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) || ++ (pEthPortInit->maxRxPktSize < 1518) ) ++ { ++ mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); ++ return NULL; ++ } ++ if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) ++ { ++ mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", ++ portNo, pEthPortInit->rxDefQ); ++ return NULL; ++ } ++ ++ pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) ); ++ if(pPortCtrl == NULL) ++ { ++ mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", ++ (int)sizeof(ETH_PORT_CTRL), portNo); ++ return NULL; ++ } ++ ++ memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) ); ++ ethPortCtrl[portNo] = pPortCtrl; ++ ++ pPortCtrl->portState = MV_UNDEFINED_STATE; ++ ++ pPortCtrl->portNo = portNo; ++ ++ pPortCtrl->osHandle = pEthPortInit->osHandle; ++ ++ /* Copy Configuration parameters */ ++ pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; ++ pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; ++ pPortCtrl->portConfig.ejpMode = 0; ++ ++ for( queue=0; queuerxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; ++ } ++ for( queue=0; queuetxQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; ++ } ++ ++ mvEthPortDisable(pPortCtrl); ++ ++ /* Set the board information regarding PHY address */ ++ mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) ); ++ ++ /* Create all requested RX queues */ ++ for(queue=0; queuerxQueueConfig[queue].descrNum == 0) ++ continue; ++ ++ /* Allocate memory for RX descriptors */ ++ descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = ++ ethAllocDescrMemory(pPortCtrl, descSize, ++ &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, ++ &pPortCtrl->rxQueue[queue].descBuf.memHandle); ++ pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; ++ if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", ++ pPortCtrl->portNo, queue, descSize, ++ ethDescInSram ? "SRAM" : "DRAM", ++ pPortCtrl->rxQueueConfig[queue].descrNum); ++ return NULL; ++ } ++ ++ ethInitRxDescRing(pPortCtrl, queue); ++ } ++ /* Create TX queues */ ++ for(queue=0; queuetxQueueConfig[queue].descrNum == 0) ++ continue; ++ ++ /* Allocate memory for TX descriptors */ ++ descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = ++ ethAllocDescrMemory(pPortCtrl, descSize, ++ &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, ++ &pPortCtrl->txQueue[queue].descBuf.memHandle); ++ pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; ++ if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", ++ pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", ++ pPortCtrl->txQueueConfig[queue].descrNum); ++ return NULL; ++ } ++ ++ ethInitTxDescRing(pPortCtrl, queue); ++ } ++ mvEthDefaultsSet(pPortCtrl); ++ ++ pPortCtrl->portState = MV_IDLE; ++ return pPortCtrl; ++} ++ ++/******************************************************************************* ++* ethPortFinish - Finish the Ethernet port driver ++* ++* DESCRIPTION: ++* This function finish the ethernet port. ++* 1) Down ethernet port if needed. ++* 2) Delete RX and TX descriptor rings for all created RX and TX queues ++* 3) Free internal port Control structure. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: NONE. ++* ++*******************************************************************************/ ++void mvEthPortFinish(void* pPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ int queue, portNo = pPortCtrl->portNo; ++ ++ if(pPortCtrl->portState == MV_ACTIVE) ++ { ++ mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", ++ portNo); ++ mvEthPortDisable(pPortHndl); ++ } ++ ++ /* Free all allocated RX queues */ ++ for(queue=0; queuerxQueue[queue].descBuf); ++ } ++ ++ /* Free all allocated TX queues */ ++ for(queue=0; queuetxQueue[queue].descBuf); ++ } ++ ++ /* Free port control structure */ ++ mvOsFree(pPortCtrl); ++ ++ ethPortCtrl[portNo] = NULL; ++} ++ ++/******************************************************************************* ++* mvEthDefaultsSet - Set defaults to the ethernet port ++* ++* DESCRIPTION: ++* This function set default values to the ethernet port. ++* 1) Clear Cause registers and Mask all interrupts ++* 2) Clear all MAC tables ++* 3) Set defaults to all registers ++* 4) Reset all created RX and TX descriptors ring ++* 5) Reset PHY ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure ++* NOTE: ++* This function update all the port configuration except those set ++* Initialy by the OsGlue by MV_ETH_PORT_INIT. ++* This function can be called after portDown to return the port setting ++* to defaults. ++*******************************************************************************/ ++MV_STATUS mvEthDefaultsSet(void* pPortHndl) ++{ ++ int ethPortNo, queue; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ MV_U32 txPrio; ++ MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; ++ MV_BOARD_MAC_SPEED boardMacCfg; ++ ++ ethPortNo = pPortCtrl->portNo; ++ ++ /* Clear Cause registers */ ++ MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0); ++ MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0); ++ ++ /* Mask all interrupts */ ++ MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0); ++ MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0); ++ ++ portCfgReg = PORT_CONFIG_VALUE; ++ portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; ++ ++ boardMacCfg = mvBoardMacSpeedGet(ethPortNo); ++ ++ if(boardMacCfg == BOARD_MAC_SPEED_100M) ++ { ++ portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; ++ } ++ else if(boardMacCfg == BOARD_MAC_SPEED_1000M) ++ { ++ portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; ++ } ++ else ++ { ++ portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; ++ } ++ ++ /* build PORT_SDMA_CONFIG_REG */ ++ portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); ++ portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); ++ ++#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \ ++ (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ) ++ /* some devices have restricted RX burst size when using HW coherency */ ++ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); ++#else ++ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); ++#endif ++ ++#if defined(MV_CPU_BE) ++ /* big endian */ ++# if defined(MV_ARM) ++ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | ++ ETH_TX_NO_DATA_SWAP_MASK | ++ ETH_DESC_SWAP_MASK); ++# elif defined(MV_PPC) ++ portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | ++ ETH_TX_DATA_SWAP_MASK | ++ ETH_NO_DESC_SWAP_MASK); ++# else ++# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" ++# endif /* MV_ARM / MV_PPC */ ++ ++#else /* MV_CPU_LE */ ++ /* little endian */ ++ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | ++ ETH_TX_NO_DATA_SWAP_MASK | ++ ETH_NO_DESC_SWAP_MASK); ++#endif /* MV_CPU_BE / MV_CPU_LE */ ++ ++ pPortCtrl->portRxQueueCmdReg = 0; ++ pPortCtrl->portTxQueueCmdReg = 0; ++ ++#if (MV_ETH_VERSION >= 4) ++ if(pPortCtrl->portConfig.ejpMode == MV_TRUE) ++ { ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK); ++ } ++ else ++ { ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0) ++ } ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++ ethSetUcastTable(ethPortNo, -1); ++ mvEthSetSpecialMcastTable(ethPortNo, -1); ++ mvEthSetOtherMcastTable(ethPortNo, -1); ++ ++ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; ++ ++ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); ++ ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); ++ ++ /* Update value of PortConfig register accordingly with all RxQueue types */ ++ pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; ++ pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; ++ pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; ++ pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; ++ ++ portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); ++ ++ /* Assignment of Tx CTRP of given queue */ ++ txPrio = 0; ++ ++ for(queue=0; queuetxQueue[queue]; ++ ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ ethResetTxDescRing(pPortCtrl, queue); ++ ++ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), ++ 0x3fffffff); ++ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), ++ 0x03ffffff); ++ } ++ else ++ { ++ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); ++ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); ++ } ++ } ++ ++ /* Assignment of Rx CRDP of given queue */ ++ for(queue=0; queueportNo; ++ ++ if( (pPortCtrl->portState != MV_ACTIVE) && ++ (pPortCtrl->portState != MV_PAUSED) ) ++ { ++ mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", ++ ethPortNo, pPortCtrl->portState); ++ return MV_BAD_STATE; ++ } ++ ++ ethPortNo = pPortCtrl->portNo; ++ ++ /* Enable port RX. */ ++ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); ++ ++ /* Enable port TX. */ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; ++ ++ pPortCtrl->portState = MV_ACTIVE; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* ethPortDown - Stop the Ethernet port activity. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure. ++* ++* NOTE : used for port link down. ++*******************************************************************************/ ++MV_STATUS mvEthPortDown(void* pEthPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ int ethPortNum = pPortCtrl->portNo; ++ unsigned int regData; ++ volatile int uDelay, mDelay; ++ ++ /* Stop Rx port activity. Check port Rx activity. */ ++ regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; ++ if(regData != 0) ++ { ++ /* Issue stop command for active channels only */ ++ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); ++ } ++ ++ /* Stop Tx port activity. Check port Tx activity. */ ++ regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; ++ if(regData != 0) ++ { ++ /* Issue stop command for active channels only */ ++ MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), ++ (regData << ETH_TXQ_DISABLE_OFFSET) ); ++ } ++ ++ /* Force link down */ ++/* ++ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); ++ regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); ++*/ ++ /* Wait for all Rx activity to terminate. */ ++ mDelay = 0; ++ do ++ { ++ if(mDelay >= RX_DISABLE_TIMEOUT_MSEC) ++ { ++ mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", ++ ethPortNum, regData); ++ break; ++ } ++ mvOsDelay(1); ++ mDelay++; ++ ++ /* Check port RX Command register that all Rx queues are stopped */ ++ regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); ++ } ++ while(regData & 0xFF); ++ ++ /* Wait for all Tx activity to terminate. */ ++ mDelay = 0; ++ do ++ { ++ if(mDelay >= TX_DISABLE_TIMEOUT_MSEC) ++ { ++ mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", ++ ethPortNum, regData); ++ break; ++ } ++ mvOsDelay(1); ++ mDelay++; ++ ++ /* Check port TX Command register that all Tx queues are stopped */ ++ regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); ++ } ++ while(regData & 0xFF); ++ ++ /* Double check to Verify that TX FIFO is Empty */ ++ mDelay = 0; ++ while(MV_TRUE) ++ { ++ do ++ { ++ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) ++ { ++ mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", ++ ethPortNum, regData); ++ break; ++ } ++ mvOsDelay(1); ++ mDelay++; ++ ++ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); ++ } ++ while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || ++ ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) ); ++ ++ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) ++ break; ++ ++ /* Double check */ ++ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); ++ if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && ++ ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) ) ++ { ++ break; ++ } ++ else ++ mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", ++ ethPortNum, mDelay, regData); ++ } ++ ++ /* Do NOT force link down */ ++/* ++ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); ++ regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); ++*/ ++ /* Wait about 2500 tclk cycles */ ++ uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000)); ++ mvOsUDelay(uDelay); ++ ++ pPortCtrl->portState = MV_PAUSED; ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* ethPortEnable - Enable the Ethernet port and Start RX and TX. ++* ++* DESCRIPTION: ++* This routine enable the Ethernet port and Rx and Tx activity: ++* ++* Note: Each Rx and Tx queue descriptor's list must be initialized prior ++* to calling this function (use etherInitTxDescRing for Tx queues and ++* etherInitRxDescRing for Rx queues). ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure. ++* ++* NOTE: main usage is to enable the port after ifconfig up. ++*******************************************************************************/ ++MV_STATUS mvEthPortEnable(void* pEthPortHndl) ++{ ++ int ethPortNo; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ MV_U32 portSerialCtrlReg; ++ ++ ethPortNo = pPortCtrl->portNo; ++ ++ /* Enable port */ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); ++ portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); ++ ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); ++ ++ mvEthMibCountersClear(pEthPortHndl); ++ ++ pPortCtrl->portState = MV_PAUSED; ++ ++ /* If Link is UP, Start RX and TX traffic */ ++ if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK) ++ return( mvEthPortUp(pEthPortHndl) ); ++ ++ return MV_NOT_READY; ++} ++ ++ ++/******************************************************************************* ++* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure. ++* ++* NOTE: main usage is to disable the port after ifconfig down. ++*******************************************************************************/ ++MV_STATUS mvEthPortDisable(void* pEthPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ int ethPortNum = pPortCtrl->portNo; ++ unsigned int regData; ++ volatile int mvDelay; ++ ++ if(pPortCtrl->portState == MV_ACTIVE) ++ { ++ /* Stop RX and TX activities */ ++ mvEthPortDown(pEthPortHndl); ++ } ++ ++ /* Reset the Enable bit in the Serial Control Register */ ++ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); ++ regData &= ~(ETH_PORT_ENABLE_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); ++ ++ /* Wait about 2500 tclk cycles */ ++ mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet())); ++ for(mvDelay; mvDelay>0; mvDelay--); ++ ++ pPortCtrl->portState = MV_IDLE; ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. ++* ++* DESCRIPTION: ++* This routine used to free buffers attached to the Tx ring and should ++* be called only when Giga Ethernet port is Down ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of TX queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. ++* ++* RETURN: ++* MV_EMPTY - There is no more buffers in this queue. ++* MV_OK - Buffer detached from the queue and pPktInfo structure ++* filled with relevant information. ++* ++*******************************************************************************/ ++MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ MV_PKT_INFO* pPktInfo; ++ ETH_TX_DESC* pTxDesc; ++ int port = pPortCtrl->portNo; ++ ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || ++ (pQueueCtrl->resource == 0) ) ++ { ++ /* Free next descriptor */ ++ pQueueCtrl->resource++; ++ pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr; ++ ++ /* pPktInfo is available only in descriptors which are last descriptors */ ++ pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo; ++ if (pPktInfo) ++ pPktInfo->status = pTxDesc->cmdSts; ++ ++ pTxDesc->cmdSts = 0x0; ++ pTxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); ++ ++ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); ++ ++ if (pPktInfo) ++ if (pPktInfo->status & ETH_TX_LAST_DESC_MASK) ++ return pPktInfo; ++ } ++ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ return NULL; ++} ++ ++ ++ ++/******************************************************************************* ++* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. ++* ++* DESCRIPTION: ++* This routine used to free buffers attached to the Rx ring and should ++* be called only when Giga Ethernet port is Down ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int rxQueue - Number of Rx queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to received packet. ++* ++* RETURN: ++* MV_EMPTY - There is no more buffers in this queue. ++* MV_OK - Buffer detached from the queue and pBufInfo structure ++* filled with relevant information. ++* ++*******************************************************************************/ ++MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_RX_DESC* pRxDesc; ++ MV_PKT_INFO* pPktInfo; ++ int port = pPortCtrl->portNo; ++ ++ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; ++ ++ if(pQueueCtrl->resource == 0) ++ { ++ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ ++ return NULL; ++ } ++ /* Free next descriptor */ ++ pQueueCtrl->resource--; ++ pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr; ++ pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo; ++ ++ pPktInfo->status = pRxDesc->cmdSts; ++ pRxDesc->cmdSts = 0x0; ++ pRxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); ++ ++ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); ++ return pPktInfo; ++} ++ ++ ++/******************************************************************************/ ++/* Port Configuration functions */ ++/******************************************************************************/ ++/******************************************************************************* ++* mvEthMruGet - Get MRU configuration for Max Rx packet size. ++* ++* INPUT: ++* MV_U32 maxRxPktSize - max packet size. ++* ++* RETURN: MV_U32 - MRU configuration. ++* ++*******************************************************************************/ ++static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) ++{ ++ MV_U32 portSerialCtrlReg = 0; ++ ++ if(maxRxPktSize > 9192) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; ++ else if(maxRxPktSize > 9022) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; ++ else if(maxRxPktSize > 1552) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; ++ else if(maxRxPktSize > 1522) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; ++ else if(maxRxPktSize > 1518) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; ++ else ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; ++ ++ return portSerialCtrlReg; ++} ++ ++/******************************************************************************* ++* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path ++* ++* DESCRIPTION: ++* This routine sets the RX coalescing interrupt mechanism parameter. ++* This parameter is a timeout counter, that counts in 64 tClk ++* chunks, that when timeout event occurs a maskable interrupt occurs. ++* The parameter is calculated using the tCLK frequency of the ++* MV-64xxx chip, and the required number is in micro seconds. ++* ++* INPUT: ++* void* pPortHndl - Ethernet Port handler. ++* MV_U32 uSec - Number of micro seconds between ++* RX interrupts ++* ++* RETURN: ++* None. ++* ++* COMMENT: ++* 1 sec - TCLK_RATE clocks ++* 1 uSec - TCLK_RATE / 1,000,000 clocks ++* ++* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); ++ MV_U32 portSdmaCfgReg; ++ ++ portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); ++ portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; ++ ++ portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); ++ ++#if (MV_ETH_VERSION >= 2) ++ /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ ++ if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) ++ portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; ++#endif /* MV_ETH_VERSION >= 2 */ ++ ++ MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); ++ return coal; ++} ++ ++/******************************************************************************* ++* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path ++* ++* DESCRIPTION: ++* This routine sets the TX coalescing interrupt mechanism parameter. ++* This parameter is a timeout counter, that counts in 64 tClk ++* chunks, that when timeout event occurs a maskable interrupt ++* occurs. ++* The parameter is calculated using the tCLK frequency of the ++* MV-64xxx chip, and the required number is in micro seconds. ++* ++* INPUT: ++* void* pPortHndl - Ethernet Port handler. ++* MV_U32 uSec - Number of micro seconds between ++* RX interrupts ++* ++* RETURN: ++* None. ++* ++* COMMENT: ++* 1 sec - TCLK_RATE clocks ++* 1 uSec - TCLK_RATE / 1,000,000 clocks ++* ++* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) ++* ++*******************************************************************************/ ++MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); ++ MV_U32 regVal; ++ ++ regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); ++ regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; ++ regVal |= ETH_TX_INTR_COAL_MASK(coal); ++ ++ /* Set TX Coalescing mechanism */ ++ MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); ++ return coal; ++} ++ ++/******************************************************************************* ++* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds ++* ++* DESCRIPTION: ++* This routine gets the RX and TX coalescing interrupt values. ++* The parameter is calculated using the tCLK frequency of the ++* MV-64xxx chip, and the returned numbers are in micro seconds. ++* ++* INPUTs: ++* void* pPortHndl - Ethernet Port handler. ++* ++* OUTPUTs: ++* MV_U32* pRxCoal - Number of micro seconds between RX interrupts ++* MV_U32* pTxCoal - Number of micro seconds between TX interrupts ++* ++* RETURN: ++* MV_STATUS MV_OK - success ++* Others - failure. ++* ++* COMMENT: ++* 1 sec - TCLK_RATE clocks ++* 1 uSec - TCLK_RATE / 1,000,000 clocks ++* ++* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) ++* ++*******************************************************************************/ ++MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal) ++{ ++ MV_U32 regVal, coal, usec; ++ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ /* get TX Coalescing */ ++ regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); ++ coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); ++ ++ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); ++ if(pTxCoal != NULL) ++ *pTxCoal = usec; ++ ++ /* Get RX Coalescing */ ++ regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); ++ coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); ++ ++#if (MV_ETH_VERSION >= 2) ++ if(regVal & ETH_RX_INTR_COAL_MSB_MASK) ++ { ++ /* Add MSB */ ++ coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); ++ } ++#endif /* MV_ETH_VERSION >= 2 */ ++ ++ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); ++ if(pRxCoal != NULL) ++ *pRxCoal = usec; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMaxRxSizeSet - ++* ++* DESCRIPTION: ++* Change maximum receive size of the port. This configuration will take place ++* after next call of ethPortSetDefaults() function. ++* ++* INPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ MV_U32 portSerialCtrlReg; ++ ++ if((maxRxSize < 1518) || (maxRxSize & ~ETH_RX_BUFFER_MASK)) ++ return MV_BAD_PARAM; ++ ++ pPortCtrl->portConfig.maxRxPktSize = maxRxSize; ++ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); ++ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; ++ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************/ ++/* MAC Filtering functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port ++* ++* DESCRIPTION: ++* This routine used to free buffers attached to the Rx ring and should ++* be called only when Giga Ethernet port is Down ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* MV_BOOL isPromisc - Promiscous mode ++* MV_TRUE - accept all Broadcast, Multicast ++* and Unicast packets ++* MV_FALSE - accept all Broadcast, ++* specially added Multicast and ++* single Unicast packets ++* ++* RETURN: MV_STATUS MV_OK - Success, Other - Failure ++* ++*******************************************************************************/ ++MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ int queue; ++ MV_U32 portCfgReg; ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ /* Set / Clear UPM bit in port configuration register */ ++ if(isPromisc) ++ { ++ /* Accept all multicast packets to RX default queue */ ++ queue = pPortCtrl->portConfig.rxDefQ; ++ portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; ++ memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); ++ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF); ++ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF); ++ } ++ else ++ { ++ /* Reject all Multicast addresses */ ++ queue = -1; ++ portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; ++ /* Clear all mcastCount */ ++ memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); ++ } ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ /* Set Special Multicast and Other Multicast tables */ ++ mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); ++ mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); ++ ethSetUcastTable(pPortCtrl->portNo, queue); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMacAddrSet - This function Set the port Unicast address. ++* ++* DESCRIPTION: ++* This function Set the port Ethernet MAC address. This address ++* will be used to send Pause frames if enabled. Packets with this ++* address will be accepted and dispatched to default RX queue ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler. ++* char* pAddr - Address to be set ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Other - Faulure ++* ++*******************************************************************************/ ++MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ unsigned int macH; ++ unsigned int macL; ++ ++ if(queue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); ++ return MV_BAD_PARAM; ++ } ++ ++ if(queue != -1) ++ { ++ macL = (pAddr[4] << 8) | (pAddr[5]); ++ macH = (pAddr[0] << 24)| (pAddr[1] << 16) | ++ (pAddr[2] << 8) | (pAddr[3] << 0); ++ ++ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); ++ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); ++ } ++ ++ /* Accept frames of this address */ ++ ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMacAddrGet - This function returns the port Unicast address. ++* ++* DESCRIPTION: ++* This function returns the port Ethernet MAC address. ++* ++* INPUT: ++* int portNo - Ethernet port number. ++* char* pAddr - Pointer where address will be written to ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Other - Faulure ++* ++*******************************************************************************/ ++MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) ++{ ++ unsigned int macH; ++ unsigned int macL; ++ ++ if(pAddr == NULL) ++ { ++ mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); ++ return MV_BAD_PARAM; ++ } ++ ++ macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); ++ macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); ++ pAddr[0] = (macH >> 24) & 0xff; ++ pAddr[1] = (macH >> 16) & 0xff; ++ pAddr[2] = (macH >> 8) & 0xff; ++ pAddr[3] = macH & 0xff; ++ pAddr[4] = (macL >> 8) & 0xff; ++ pAddr[5] = macL & 0xff; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* MV_U8* pAddr - Address to calculate CRC-8 ++* ++* RETURN: MV_U8 - CRC-8 of this MAC address ++* ++*******************************************************************************/ ++MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr) ++{ ++ unsigned int macH; ++ unsigned int macL; ++ int macArray[48]; ++ int crc[8]; ++ int i; ++ unsigned char crcResult = 0; ++ ++ /* Calculate CRC-8 out of the given address */ ++ macH = (pAddr[0] << 8) | (pAddr[1]); ++ macL = (pAddr[2] << 24)| (pAddr[3] << 16) | ++ (pAddr[4] << 8) | (pAddr[5] << 0); ++ ++ for(i=0; i<32; i++) ++ macArray[i] = (macL >> i) & 0x1; ++ ++ for(i=32; i<48; i++) ++ macArray[i] = (macH >> (i - 32)) & 0x1; ++ ++ crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ ++ macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ ++ macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ ++ macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ ++ macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; ++ ++ crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ ++ macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ ++ macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ ++ macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ ++ macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ ++ macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ ++ macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; ++ ++ crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ ++ macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ ++ macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ ++ macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ ++ macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ ++ macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; ++ ++ crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ ++ macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ ++ macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ ++ macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ ++ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ ++ macArray[3] ^ macArray[2] ^ macArray[1]; ++ ++ crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ ++ macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ ++ macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ ++ macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ ++ macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ ++ macArray[3] ^ macArray[2]; ++ ++ crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ ++ macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ ++ macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ ++ macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ ++ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ ++ macArray[4] ^ macArray[3]; ++ ++ crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ ++ macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ ++ macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ ++ macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ ++ macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ ++ macArray[4]; ++ ++ crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ ++ macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ ++ macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ ++ macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ ++ macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; ++ ++ for(i=0; i<8; i++) ++ crcResult = crcResult | (crc[i] << i); ++ ++ return crcResult; ++} ++/******************************************************************************* ++* mvEthMcastAddrSet - Multicast address settings. ++* ++* DESCRIPTION: ++* This API controls the MV device MAC multicast support. ++* The MV device supports multicast using two tables: ++* 1) Special Multicast Table for MAC addresses of the form ++* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). ++* The MAC DA[7:0] bits are used as a pointer to the Special Multicast ++* Table entries in the DA-Filter table. ++* In this case, the function calls ethPortSmcAddr() routine to set the ++* Special Multicast Table. ++* 2) Other Multicast Table for multicast of another type. A CRC-8bit ++* is used as an index to the Other Multicast Table entries in the ++* DA-Filter table. ++* In this case, the function calculates the CRC-8bit value and calls ++* ethPortOmcAddr() routine to set the Other Multicast Table. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler. ++* MV_U8* pAddr - Address to be set ++* int queue - RX queue to capture all packets with this ++* Multicast MAC address. ++* -1 means delete this Multicast address. ++* ++* RETURN: MV_STATUS ++* MV_TRUE - Success, Other - Failure ++* ++*******************************************************************************/ ++MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ unsigned char crcResult = 0; ++ ++ if(queue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", ++ pPortCtrl->portNo, queue); ++ return MV_BAD_PARAM; ++ } ++ ++ if((pAddr[0] == 0x01) && ++ (pAddr[1] == 0x00) && ++ (pAddr[2] == 0x5E) && ++ (pAddr[3] == 0x00) && ++ (pAddr[4] == 0x00)) ++ { ++ ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); ++ } ++ else ++ { ++ crcResult = mvEthMcastCrc8Get(pAddr); ++ ++ /* Check Add counter for this CRC value */ ++ if(queue == -1) ++ { ++ if(pPortCtrl->mcastCount[crcResult] == 0) ++ { ++ mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", ++ pPortCtrl->portNo, (unsigned)crcResult); ++ return MV_NO_SUCH; ++ } ++ ++ pPortCtrl->mcastCount[crcResult]--; ++ if(pPortCtrl->mcastCount[crcResult] != 0) ++ { ++ mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", ++ pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], ++ (unsigned)crcResult); ++ return MV_NO_CHANGE; ++ } ++ } ++ else ++ { ++ pPortCtrl->mcastCount[crcResult]++; ++ if(pPortCtrl->mcastCount[crcResult] > 1) ++ { ++ mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", ++ pPortCtrl->portNo, (unsigned)crcResult); ++ return MV_NO_CHANGE; ++ } ++ } ++ ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* ethSetUcastTable - Unicast address settings. ++* ++* DESCRIPTION: ++* Set all entries in the Unicast MAC Table queue==-1 means reject all ++* INPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++static void ethSetUcastTable(int portNo, int queue) ++{ ++ int offset; ++ MV_U32 regValue; ++ ++ if(queue == -1) ++ { ++ regValue = 0; ++ } ++ else ++ { ++ regValue = (((0x01 | (queue<<1)) << 0) | ++ ((0x01 | (queue<<1)) << 8) | ++ ((0x01 | (queue<<1)) << 16) | ++ ((0x01 | (queue<<1)) << 24)); ++ } ++ ++ for (offset=0; offset<=0xC; offset+=4) ++ MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); ++} ++ ++/******************************************************************************* ++* mvEthSetSpecialMcastTable - Special Multicast address settings. ++* ++* DESCRIPTION: ++* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all ++* INPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) ++{ ++ int offset; ++ MV_U32 regValue; ++ ++ if(queue == -1) ++ { ++ regValue = 0; ++ } ++ else ++ { ++ regValue = (((0x01 | (queue<<1)) << 0) | ++ ((0x01 | (queue<<1)) << 8) | ++ ((0x01 | (queue<<1)) << 16) | ++ ((0x01 | (queue<<1)) << 24)); ++ } ++ ++ for (offset=0; offset<=0xFC; offset+=4) ++ { ++ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + ++ offset), regValue); ++ } ++} ++ ++/******************************************************************************* ++* mvEthSetOtherMcastTable - Other Multicast address settings. ++* ++* DESCRIPTION: ++* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all ++* INPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) ++{ ++ int offset; ++ MV_U32 regValue; ++ ++ if(queue == -1) ++ { ++ regValue = 0; ++ } ++ else ++ { ++ regValue = (((0x01 | (queue<<1)) << 0) | ++ ((0x01 | (queue<<1)) << 8) | ++ ((0x01 | (queue<<1)) << 16) | ++ ((0x01 | (queue<<1)) << 24)); ++ } ++ ++ for (offset=0; offset<=0xFC; offset+=4) ++ { ++ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + ++ offset), regValue); ++ } ++} ++ ++/******************************************************************************* ++* ethSetUcastAddr - This function Set the port unicast address table ++* ++* DESCRIPTION: ++* This function locates the proper entry in the Unicast table for the ++* specified MAC nibble and sets its properties according to function ++* parameters. ++* ++* INPUT: ++* int ethPortNum - Port number. ++* MV_U8 lastNibble - Unicast MAC Address last nibble. ++* int queue - Rx queue number for this MAC address. ++* value "-1" means remove address ++* ++* OUTPUT: ++* This function add/removes MAC addresses from the port unicast address ++* table. ++* ++* RETURN: ++* MV_TRUE is output succeeded. ++* MV_FALSE if option parameter is invalid. ++* ++*******************************************************************************/ ++static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) ++{ ++ unsigned int unicastReg; ++ unsigned int tblOffset; ++ unsigned int regOffset; ++ ++ /* Locate the Unicast table entry */ ++ lastNibble = (0xf & lastNibble); ++ tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/ ++ regOffset = lastNibble % 4; /* Entry offset within the above register */ ++ ++ ++ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) + ++ tblOffset)); ++ ++ ++ if(queue == -1) ++ { ++ /* Clear accepts frame bit at specified unicast DA table entry */ ++ unicastReg &= ~(0xFF << (8*regOffset)); ++ } ++ else ++ { ++ unicastReg &= ~(0xFF << (8*regOffset)); ++ unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset)); ++ } ++ MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), ++ unicastReg); ++ ++ return MV_TRUE; ++} ++ ++/******************************************************************************* ++* ethSetSpecialMcastAddr - Special Multicast address settings. ++* ++* DESCRIPTION: ++* This routine controls the MV device special MAC multicast support. ++* The Special Multicast Table for MAC addresses supports MAC of the form ++* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). ++* The MAC DA[7:0] bits are used as a pointer to the Special Multicast ++* Table entries in the DA-Filter table. ++* This function set the Special Multicast Table appropriate entry ++* according to the argument given. ++* ++* INPUT: ++* int ethPortNum Port number. ++* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). ++* int queue Rx queue number for this MAC address. ++* int option 0 = Add, 1 = remove address. ++* ++* OUTPUT: ++* See description. ++* ++* RETURN: ++* MV_TRUE is output succeeded. ++* MV_FALSE if option parameter is invalid. ++* ++*******************************************************************************/ ++static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) ++{ ++ unsigned int smcTableReg; ++ unsigned int tblOffset; ++ unsigned int regOffset; ++ ++ /* Locate the SMC table entry */ ++ tblOffset = (lastByte / 4); /* Register offset from SMC table base */ ++ regOffset = lastByte % 4; /* Entry offset within the above register */ ++ ++ smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4)); ++ ++ if(queue == -1) ++ { ++ /* Clear accepts frame bit at specified Special DA table entry */ ++ smcTableReg &= ~(0xFF << (8 * regOffset)); ++ } ++ else ++ { ++ smcTableReg &= ~(0xFF << (8 * regOffset)); ++ smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); ++ } ++ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + ++ tblOffset*4), smcTableReg); ++ ++ return MV_TRUE; ++} ++ ++/******************************************************************************* ++* ethSetOtherMcastAddr - Multicast address settings. ++* ++* DESCRIPTION: ++* This routine controls the MV device Other MAC multicast support. ++* The Other Multicast Table is used for multicast of another type. ++* A CRC-8bit is used as an index to the Other Multicast Table entries ++* in the DA-Filter table. ++* The function gets the CRC-8bit value from the calling routine and ++* set the Other Multicast Table appropriate entry according to the ++* CRC-8 argument given. ++* ++* INPUT: ++* int ethPortNum Port number. ++* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). ++* int queue Rx queue number for this MAC address. ++* ++* OUTPUT: ++* See description. ++* ++* RETURN: ++* MV_TRUE is output succeeded. ++* MV_FALSE if option parameter is invalid. ++* ++*******************************************************************************/ ++static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) ++{ ++ unsigned int omcTableReg; ++ unsigned int tblOffset; ++ unsigned int regOffset; ++ ++ /* Locate the OMC table entry */ ++ tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ ++ regOffset = crc8 % 4; /* Entry offset within the above register */ ++ ++ omcTableReg = MV_REG_READ( ++ (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); ++ ++ if(queue == -1) ++ { ++ /* Clear accepts frame bit at specified Other DA table entry */ ++ omcTableReg &= ~(0xFF << (8 * regOffset)); ++ } ++ else ++ { ++ omcTableReg &= ~(0xFF << (8 * regOffset)); ++ omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); ++ } ++ ++ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), ++ omcTableReg); ++ ++ return MV_TRUE; ++} ++ ++ ++/******************************************************************************/ ++/* MIB Counters functions */ ++/******************************************************************************/ ++ ++ ++/******************************************************************************* ++* mvEthMibCounterRead - Read a MIB counter ++* ++* DESCRIPTION: ++* This function reads a MIB counter of a specific ethernet port. ++* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or ++* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, ++* so pHigh32 pointer should not be NULL in this case. ++* ++* INPUT: ++* int ethPortNum - Ethernet Port number. ++* unsigned int mibOffset - MIB counter offset. ++* ++* OUTPUT: ++* MV_U32* pHigh32 - pointer to place where 32 most significant bits ++* of the counter will be stored. ++* ++* RETURN: ++* 32 low sgnificant bits of MIB counter value. ++* ++*******************************************************************************/ ++MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset, ++ MV_U32* pHigh32) ++{ ++ int portNo; ++ MV_U32 valLow32, valHigh32; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ ++ portNo = pPortCtrl->portNo; ++ ++ valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); ++ ++ /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ ++ /* of a 64-bit MIB Counter. */ ++ if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || ++ (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) ) ++ { ++ valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); ++ if(pHigh32 != NULL) ++ *pHigh32 = valHigh32; ++ } ++ return valLow32; ++} ++ ++/******************************************************************************* ++* mvEthMibCountersClear - Clear all MIB counters ++* ++* DESCRIPTION: ++* This function clears all MIB counters ++* ++* INPUT: ++* int ethPortNum - Ethernet Port number. ++* ++* ++* RETURN: void ++* ++*******************************************************************************/ ++void mvEthMibCountersClear(void* pPortHandle) ++{ ++ int i, portNo; ++ unsigned int dummy; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ ++ portNo = pPortCtrl->portNo; ++ ++ /* Perform dummy reads from MIB counters */ ++ for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i 0xFF) ++ { ++ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); ++ return -1; ++ } ++ regIdx = mvOsDivide(tos>>2, 10); ++ regOffs = mvOsReminder(tos>>2, 10); ++ ++ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); ++ rxq = (regValue >> (regOffs*3)); ++ rxq &= 0x7; ++ ++ return rxq; ++} ++ ++/******************************************************************************* ++* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int tos - TOS value in the IP header of the packet ++* int rxq - RX Queue for packets with the configured TOS value ++* Negative value (-1) means no special processing for these packets, ++* so they will be processed as regular packets. ++* ++* RETURN: MV_STATUS ++*******************************************************************************/ ++MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq) ++{ ++ MV_U32 regValue; ++ int regIdx, regOffs; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ ++ if( (rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM) ) ++ { ++ mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq); ++ return MV_BAD_PARAM; ++ } ++ if(tos > 0xFF) ++ { ++ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); ++ return MV_BAD_PARAM; ++ } ++ regIdx = mvOsDivide(tos>>2, 10); ++ regOffs = mvOsReminder(tos>>2, 10); ++ ++ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); ++ regValue &= ~(0x7 << (regOffs*3)); ++ regValue |= (rxq << (regOffs*3)); ++ ++ MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with ++* special priority bits [0-2] ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int bpduQueue - Special queue to capture VLAN tagged packets with special ++* priority. ++* Negative value (-1) means no special processing for these packets, ++* so they will be processed as regular packets. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 vlanPrioReg; ++ ++ if(vlanPrioQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); ++ return MV_BAD_PARAM; ++ } ++ if(vlanPrio >= 8) ++ { ++ mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); ++ return MV_BAD_PARAM; ++ } ++ ++ vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); ++ vlanPrioReg &= ~(0x7 << (vlanPrio*3)); ++ vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3)); ++ MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. ++* ++* DESCRIPTION: ++* This function defines processing of BPDU packets. ++* BPDU packets can be accepted and captured to one of RX queues ++* or can be processing as regular Multicast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int bpduQueue - Special queue to capture BPDU packets (DA is equal to ++* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, ++* except for the Flow-Control Pause packets). ++* Negative value (-1) means no special processing for BPDU, ++* packets so they will be processed as regular Multicast packets. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ MV_U32 portCfgExtReg; ++ ++ if(bpduQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); ++ return MV_BAD_PARAM; ++ } ++ ++ portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ if(bpduQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxBpduQ = bpduQueue; ++ ++ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxBpduQ = -1; ++ /* no special processing for BPDU packets */ ++ portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthArpRxQueue - Configure RX queue to capture ARP packets. ++* ++* DESCRIPTION: ++* This function defines processing of ARP (type=0x0806) packets. ++* ARP packets can be accepted and captured to one of RX queues ++* or can be processed as other Broadcast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int arpQueue - Special queue to capture ARP packets (type=0x806). ++* Negative value (-1) means discard ARP packets ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ ++ if(arpQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); ++ return MV_BAD_PARAM; ++ } ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ ++ if(arpQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxArpQ = arpQueue; ++ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); ++ ++ portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxArpQ = -1; ++ portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. ++* ++* DESCRIPTION: ++* This function defines processing of TCP packets. ++* TCP packets can be accepted and captured to one of RX queues ++* or can be processed as regular Unicast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int tcpQueue - Special queue to capture TCP packets. Value "-1" ++* means no special processing for TCP packets, ++* so they will be processed as regular ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ ++ if(tcpQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); ++ return MV_BAD_PARAM; ++ } ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ ++ if(tcpQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxTcpQ = tcpQueue; ++ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); ++ ++ portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxTcpQ = -1; ++ portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. ++* ++* DESCRIPTION: ++* This function defines processing of UDP packets. ++* TCP packets can be accepted and captured to one of RX queues ++* or can be processed as regular Unicast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int udpQueue - Special queue to capture UDP packets. Value "-1" ++* means no special processing for UDP packets, ++* so they will be processed as regular ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ ++ if(udpQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); ++ return MV_BAD_PARAM; ++ } ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ ++ if(udpQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxUdpQ = udpQueue; ++ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); ++ ++ portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxUdpQ = -1; ++ portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************/ ++/* Speed, Duplex, FlowControl routines */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. ++* ++* DESCRIPTION: ++* This function configure the port to work with desirable Duplex and Speed. ++* Changing of these parameters are allowed only when port is disabled. ++* This function disable the port if was enabled, change duplex and speed ++* and, enable the port back if needed. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* ETH_PORT_SPEED speed - Speed of the port. ++* ETH_PORT_SPEED duplex - Duplex of the port. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_OUT_OF_RANGE - Failed. Port is out of valid range ++* MV_NOT_FOUND - Failed. Port is not initialized. ++* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. ++* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) ++* is not valid ++* ++*******************************************************************************/ ++MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed, ++ MV_ETH_PORT_DUPLEX duplex) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ MV_U32 portSerialCtrlReg; ++ ++ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) ) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ /* Check validity */ ++ if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) ) ++ return MV_BAD_PARAM; ++ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); ++ /* Set Speed */ ++ switch(speed) ++ { ++ case MV_ETH_SPEED_AN: ++ portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ break; ++ ++ case MV_ETH_SPEED_10: ++ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; ++ portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; ++ break; ++ ++ case MV_ETH_SPEED_100: ++ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; ++ portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; ++ break; ++ ++ case MV_ETH_SPEED_1000: ++ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; ++ break; ++ ++ default: ++ mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); ++ return MV_BAD_VALUE; ++ } ++ /* Set duplex */ ++ switch(duplex) ++ { ++ case MV_ETH_DUPLEX_AN: ++ portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; ++ break; ++ ++ case MV_ETH_DUPLEX_HALF: ++ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; ++ break; ++ ++ case MV_ETH_DUPLEX_FULL: ++ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; ++ break; ++ ++ default: ++ mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); ++ return MV_BAD_VALUE; ++ } ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthFlowCtrlSet - Set Flow Control of the port. ++* ++* DESCRIPTION: ++* This function configure the port to work with desirable Duplex and ++* Speed. Changing of these parameters are allowed only when port is ++* disabled. This function disable the port if was enabled, change ++* duplex and speed and, enable the port back if needed. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* MV_ETH_PORT_FC flowControl - Flow control of the port. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_OUT_OF_RANGE - Failed. Port is out of valid range ++* MV_NOT_FOUND - Failed. Port is not initialized. ++* MV_BAD_VALUE - Value flowControl parameters is not valid ++* ++*******************************************************************************/ ++MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ MV_U32 portSerialCtrlReg; ++ ++ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) ) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); ++ switch(flowControl) ++ { ++ case MV_ETH_FC_AN_ADV_DIS: ++ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; ++ break; ++ ++ case MV_ETH_FC_AN_ADV_SYM: ++ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; ++ break; ++ ++ case MV_ETH_FC_DISABLE: ++ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; ++ break; ++ ++ case MV_ETH_FC_ENABLE: ++ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; ++ break; ++ ++ default: ++ mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); ++ return MV_BAD_VALUE; ++ } ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthHeaderModeSet - Set port header mode. ++* ++* DESCRIPTION: ++* This function configures the port to work in Marvell-Header mode. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_NOT_SUPPORTED- Feature not supported. ++* MV_OUT_OF_RANGE - Failed. Port is out of valid range ++* MV_NOT_FOUND - Failed. Port is not initialized. ++* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. ++* ++*******************************************************************************/ ++MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ MV_U32 mvHeaderReg; ++ MV_U32 numRxQ = MV_ETH_RX_Q_NUM; ++ ++ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); ++ /* Disable header mode. */ ++ mvHeaderReg &= ~ETH_MVHDR_EN_MASK; ++ ++ if(headerMode != MV_ETH_DISABLE_HEADER_MODE) ++ { ++ /* Enable Header mode. */ ++ mvHeaderReg |= ETH_MVHDR_EN_MASK; ++ ++ /* Clear DA-Prefix & MHMask fields.*/ ++ mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); ++ ++ if(numRxQ > 1) ++ { ++ switch (headerMode) ++ { ++ case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): ++ mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; ++ break; ++ case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): ++ mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; ++ break; ++ case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): ++ mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; ++ break; ++ default: ++ break; ++ } ++ ++ switch (numRxQ) ++ { ++ case (4): ++ mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; ++ break; ++ case (8): ++ mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; ++ break; ++ default: ++ break; ++ } ++ } ++ } ++ ++ MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); ++ ++ return MV_OK; ++} ++ ++#if (MV_ETH_VERSION >= 4) ++/******************************************************************************* ++* mvEthEjpModeSet - Enable / Disable EJP policy for TX. ++* ++* DESCRIPTION: ++* This function ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* MV_BOOL TRUE - enable EJP mode ++* FALSE - disable EJP mode ++* ++* OUTPUT: MV_STATUS ++* MV_OK - Success ++* Other - Failure ++* ++* RETURN: None. ++* ++*******************************************************************************/ ++MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ ++ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ pPortCtrl->portConfig.ejpMode = mode; ++ if(mode) ++ { ++ /* EJP enabled */ ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK); ++ } ++ else ++ { ++ /* EJP disabled */ ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0); ++ } ++ mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n", ++ port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port), ++ MV_REG_READ(ETH_TXQ_CMD_1_REG(port))); ++ ++ return MV_OK; ++} ++#endif /* MV_ETH_VERSION >= 4 */ ++ ++/******************************************************************************* ++* mvEthStatusGet - Get major properties of the port . ++* ++* DESCRIPTION: ++* This function get major properties of the port (link, speed, duplex, ++* flowControl, etc) and return them using the single structure. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* ++* OUTPUT: ++* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status ++* will be placed. ++* ++* RETURN: None. ++* ++*******************************************************************************/ ++void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ ++ MV_U32 regValue; ++ ++ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); ++ ++ if(regValue & ETH_GMII_SPEED_1000_MASK) ++ pStatus->speed = MV_ETH_SPEED_1000; ++ else if(regValue & ETH_MII_SPEED_100_MASK) ++ pStatus->speed = MV_ETH_SPEED_100; ++ else ++ pStatus->speed = MV_ETH_SPEED_10; ++ ++ if(regValue & ETH_LINK_UP_MASK) ++ pStatus->isLinkUp = MV_TRUE; ++ else ++ pStatus->isLinkUp = MV_FALSE; ++ ++ if(regValue & ETH_FULL_DUPLEX_MASK) ++ pStatus->duplex = MV_ETH_DUPLEX_FULL; ++ else ++ pStatus->duplex = MV_ETH_DUPLEX_HALF; ++ ++ ++ if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ++ pStatus->flowControl = MV_ETH_FC_ENABLE; ++ else ++ pStatus->flowControl = MV_ETH_FC_DISABLE; ++} ++ ++ ++/******************************************************************************/ ++/* PHY Control Functions */ ++/******************************************************************************/ ++ ++ ++/******************************************************************************* ++* mvEthPhyAddrSet - Set the ethernet port PHY address. ++* ++* DESCRIPTION: ++* This routine set the ethernet port PHY address according to given ++* parameter. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int phyAddr - PHY address ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++void mvEthPhyAddrSet(void* pPortHandle, int phyAddr) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ unsigned int regData; ++ ++ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); ++ ++ regData &= ~ETH_PHY_ADDR_MASK; ++ regData |= phyAddr; ++ ++ MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); ++ ++ return; ++} ++ ++/******************************************************************************* ++* mvEthPhyAddrGet - Get the ethernet port PHY address. ++* ++* DESCRIPTION: ++* This routine returns the given ethernet port PHY address. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* ++* ++* RETURN: int - PHY address. ++* ++*******************************************************************************/ ++int mvEthPhyAddrGet(void* pPortHandle) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ unsigned int regData; ++ ++ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); ++ ++ return ((regData >> (5 * port)) & 0x1f); ++} ++ ++/******************************************************************************/ ++/* Descriptor handling Functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. ++* ++* DESCRIPTION: ++* This function prepares a Rx chained list of descriptors and packet ++* buffers in a form of a ring. The routine must be called after port ++* initialization routine and before port start routine. ++* The Ethernet SDMA engine uses CPU bus addresses to access the various ++* devices in the system (i.e. DRAM). This function uses the ethernet ++* struct 'virtual to physical' routine (set by the user) to set the ring ++* with physical addresses. ++* ++* INPUT: ++* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. ++* int rxQueue Number of Rx queue. ++* int rxDescNum Number of Rx descriptors ++* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. ++* ++* OUTPUT: ++* The routine updates the Ethernet port control struct with information ++* regarding the Rx descriptors and buffers. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) ++{ ++ ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; ++ int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; ++ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; ++ ++ /* Make sure descriptor address is cache line size aligned */ ++ pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pRxDesc = (ETH_RX_DESC*)pRxDescBase; ++ pRxPrevDesc = pRxDesc; ++ ++ /* initialize the Rx descriptors ring */ ++ for (ix=0; ixbufSize = 0x0; ++ pRxDesc->byteCnt = 0x0; ++ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pRxDesc->bufPtr = 0x0; ++ pRxDesc->returnInfo = 0x0; ++ pRxPrevDesc = pRxDesc; ++ if(ix == (rxDescNum-1)) ++ { ++ /* Closing Rx descriptors ring */ ++ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase); ++ } ++ else ++ { ++ pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); ++ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc); ++ } ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); ++ } ++ ++ pQueueCtrl->pCurrentDescr = pRxDescBase; ++ pQueueCtrl->pUsedDescr = pRxDescBase; ++ ++ pQueueCtrl->pFirstDescr = pRxDescBase; ++ pQueueCtrl->pLastDescr = pRxDesc; ++ pQueueCtrl->resource = 0; ++} ++ ++void ethResetRxDescRing(void* pPortHndl, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue]; ++ ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; ++ ++ pQueueCtrl->resource = 0; ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ while(MV_TRUE) ++ { ++ pRxDesc->bufSize = 0x0; ++ pRxDesc->byteCnt = 0x0; ++ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pRxDesc->bufPtr = 0x0; ++ pRxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); ++ if( (void*)pRxDesc == pQueueCtrl->pLastDescr) ++ break; ++ pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); ++ } ++ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; ++ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; ++ ++ /* Update RX Command register */ ++ pPortCtrl->portRxQueueCmdReg |= (1 << queue); ++ ++ /* update HW */ ++ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ } ++ else ++ { ++ /* Update RX Command register */ ++ pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); ++ ++ /* update HW */ ++ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); ++ } ++} ++ ++/******************************************************************************* ++* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. ++* ++* DESCRIPTION: ++* This function prepares a Tx chained list of descriptors and packet ++* buffers in a form of a ring. The routine must be called after port ++* initialization routine and before port start routine. ++* The Ethernet SDMA engine uses CPU bus addresses to access the various ++* devices in the system (i.e. DRAM). This function uses the ethernet ++* struct 'virtual to physical' routine (set by the user) to set the ring ++* with physical addresses. ++* ++* INPUT: ++* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. ++* int txQueue Number of Tx queue. ++* int txDescNum Number of Tx descriptors ++* int txBuffSize Size of Tx buffer ++* MV_U8* pTxDescBase Tx descriptors memory area base addr. ++* ++* OUTPUT: ++* The routine updates the Ethernet port control struct with information ++* regarding the Tx descriptors and buffers. ++* ++* RETURN: None. ++* ++*******************************************************************************/ ++static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) ++{ ++ ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; ++ int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; ++ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; ++ ++ /* Make sure descriptor address is cache line size aligned */ ++ pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pTxDesc = (ETH_TX_DESC*)pTxDescBase; ++ pTxPrevDesc = pTxDesc; ++ ++ /* initialize the Tx descriptors ring */ ++ for (ix=0; ixbyteCnt = 0x0000; ++ pTxDesc->L4iChk = 0x0000; ++ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pTxDesc->bufPtr = 0x0; ++ pTxDesc->returnInfo = 0x0; ++ ++ pTxPrevDesc = pTxDesc; ++ ++ if(ix == (txDescNum-1)) ++ { ++ /* Closing Tx descriptors ring */ ++ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase); ++ } ++ else ++ { ++ pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); ++ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc); ++ } ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); ++ } ++ ++ pQueueCtrl->pCurrentDescr = pTxDescBase; ++ pQueueCtrl->pUsedDescr = pTxDescBase; ++ ++ pQueueCtrl->pFirstDescr = pTxDescBase; ++ pQueueCtrl->pLastDescr = pTxDesc; ++ /* Leave one TX descriptor out of use */ ++ pQueueCtrl->resource = txDescNum - 1; ++} ++ ++void ethResetTxDescRing(void* pPortHndl, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue]; ++ ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; ++ ++ pQueueCtrl->resource = 0; ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ while(MV_TRUE) ++ { ++ pTxDesc->byteCnt = 0x0000; ++ pTxDesc->L4iChk = 0x0000; ++ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pTxDesc->bufPtr = 0x0; ++ pTxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); ++ pQueueCtrl->resource++; ++ if( (void*)pTxDesc == pQueueCtrl->pLastDescr) ++ break; ++ pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); ++ } ++ /* Leave one TX descriptor out of use */ ++ pQueueCtrl->resource--; ++ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; ++ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; ++ ++ /* Update TX Command register */ ++ pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); ++ /* update HW */ ++ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ } ++ else ++ { ++ /* Update TX Command register */ ++ pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); ++ /* update HW */ ++ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 ); ++ } ++} ++ ++/******************************************************************************* ++* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. ++* ++* DESCRIPTION: ++* This function allocates memory for RX and TX descriptors. ++* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. ++* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. ++* ++* INPUT: ++* int size - size of memory should be allocated. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize, ++ MV_ULONG* pPhysAddr, MV_U32 *memHandle) ++{ ++ MV_U8* pVirt; ++ ++#if defined(ETH_DESCR_IN_SRAM) ++ if(ethDescInSram == MV_TRUE) ++ pVirt = (char*)mvSramMalloc(descSize, pPhysAddr); ++ else ++#endif /* ETH_DESCR_IN_SRAM */ ++ { ++#ifdef ETH_DESCR_UNCACHED ++ pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, ++ pPhysAddr,memHandle); ++#else ++ pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, ++ pPhysAddr, memHandle); ++#endif /* ETH_DESCR_UNCACHED */ ++ } ++ memset(pVirt, 0, descSize); ++ ++ return pVirt; ++} ++ ++/******************************************************************************* ++* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. ++* ++* DESCRIPTION: ++* This function frees memory allocated for RX and TX descriptors. ++* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. ++* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. ++* ++* INPUT: ++* void* pVirtAddr - virtual pointer to memory allocated for RX and TX ++* desriptors. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf) ++{ ++ if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) ) ++ return; ++ ++#if defined(ETH_DESCR_IN_SRAM) ++ if( ethDescInSram ) ++ { ++ mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); ++ return; ++ } ++#endif /* ETH_DESCR_IN_SRAM */ ++ ++#ifdef ETH_DESCR_UNCACHED ++ mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, ++ pDescBuf->bufVirtPtr,pDescBuf->memHandle); ++#else ++ mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, ++ pDescBuf->bufVirtPtr,pDescBuf->memHandle); ++#endif /* ETH_DESCR_UNCACHED */ ++} ++ ++/******************************************************************************/ ++/* Other Functions */ ++/******************************************************************************/ ++ ++void mvEthPortPowerUp(int port) ++{ ++ MV_U32 regVal; ++ ++ /* MAC Cause register should be cleared */ ++ MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); ++ ++ if (mvBoardIsPortInSgmii(port)) ++ mvEthPortSgmiiConfig(port); ++ ++ /* Cancel Port Reset */ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); ++ regVal &= (~ETH_PORT_RESET_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); ++ while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0); ++} ++ ++void mvEthPortPowerDown(int port) ++{ ++ MV_U32 regVal; ++ ++ /* Port must be DISABLED */ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); ++ if( (regVal & ETH_PORT_ENABLE_MASK) != 0) ++ { ++ mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", ++ port, regVal); ++ return; ++ } ++ ++ /* Port Reset (Read after write the register as a precaution) */ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); ++ while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0); ++} ++ ++static void mvEthPortSgmiiConfig(int port) ++{ ++ MV_U32 regVal; ++ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); ++ ++ regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); ++ regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); ++ ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); ++} ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,748 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthDebug.c - Source file for user friendly debug functions ++* ++* DESCRIPTION: ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvCommon.h" ++#include "mvTypes.h" ++#include "mv802_3.h" ++#include "mvDebug.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "eth-phy/mvEthPhy.h" ++#include "eth/mvEth.h" ++#include "eth/gbe/mvEthDebug.h" ++ ++/* #define mvOsPrintf printf */ ++ ++void mvEthPortShow(void* pHndl); ++void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); ++ ++/******************************************************************************/ ++/* Debug functions */ ++/******************************************************************************/ ++void ethRxCoal(int port, int usec) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthRxCoalSet(pHndl, usec); ++ } ++} ++ ++void ethTxCoal(int port, int usec) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthTxCoalSet(pHndl, usec); ++ } ++} ++ ++#if (MV_ETH_VERSION >= 4) ++void ethEjpModeSet(int port, int mode) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthEjpModeSet(pHndl, mode); ++ } ++} ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++void ethBpduRxQ(int port, int bpduQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthBpduRxQueue(pHndl, bpduQueue); ++ } ++} ++ ++void ethArpRxQ(int port, int arpQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthArpRxQueue(pHndl, arpQueue); ++ } ++} ++ ++void ethTcpRxQ(int port, int tcpQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthTcpRxQueue(pHndl, tcpQueue); ++ } ++} ++ ++void ethUdpRxQ(int port, int udpQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthUdpRxQueue(pHndl, udpQueue); ++ } ++} ++ ++void ethTxPolicyRegs(int port) ++{ ++ int queue; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); ++ ++ if(pPortCtrl == NULL) ++ { ++ return; ++ } ++ mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", ++ port, pPortCtrl->portConfig.ejpMode); ++ for(queue=0; queuetxQueueConfig[queue].descrNum > 0) ++ mvOsPrintf("%d, ", queue); ++ } ++ mvOsPrintf("\n"); ++ ++ mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); ++ ++ mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", ++ ETH_TX_QUEUE_COMMAND_REG(port), ++ MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", ++ ETH_TX_FIXED_PRIO_CFG_REG(port), ++ MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", ++ ETH_TX_TOKEN_RATE_CFG_REG(port), ++ MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) ); ++ ++ mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", ++ ETH_MAX_TRANSMIT_UNIT_REG(port), ++ MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", ++ ETH_TX_TOKEN_BUCKET_SIZE_REG(port), ++ MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", ++ ETH_TX_TOKEN_BUCKET_COUNT_REG(port), ++ MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) ); ++ ++ for(queue=0; queue> 24) & 0xff), ((macH >> 16) & 0xff), ++ ((macH >> 8) & 0xff), (macH & 0xff), ++ ((macL >> 8) & 0xff), (macL & 0xff) ); ++ ++ for (i=0; i<4; i++) ++ { ++ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4)); ++ for(j=0; j<4; j++) ++ { ++ MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF; ++ ++ mvOsPrintf("%X: %8s, Q = %d\n", i*4+j, ++ (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); ++ } ++ } ++} ++ ++void ethMcastAdd(int port, char* macStr, int queue) ++{ ++ void* pHndl; ++ MV_U8 macAddr[MV_MAC_ADDR_SIZE]; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvMacStrToHex(macStr, macAddr); ++ mvEthMcastAddrSet(pHndl, macAddr, queue); ++ } ++} ++ ++void ethPortMcast(int port) ++{ ++ int tblIdx, regIdx; ++ MV_U32 regVal; ++ ++ mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", ++ port); ++ ++ for(tblIdx=0; tblIdx<(256/4); tblIdx++) ++ { ++ regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4)); ++ for(regIdx=0; regIdx<4; regIdx++) ++ { ++ if((regVal & (0x01 << (regIdx*8))) != 0) ++ { ++ mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", ++ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); ++ } ++ } ++ } ++ mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); ++ for(tblIdx=0; tblIdx<(256/4); tblIdx++) ++ { ++ regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4)); ++ for(regIdx=0; regIdx<4; regIdx++) ++ { ++ if((regVal & (0x01 << (regIdx*8))) != 0) ++ { ++ mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", ++ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); ++ } ++ } ++ } ++} ++ ++ ++/* Print status of Ethernet port */ ++void mvEthPortShow(void* pHndl) ++{ ++ MV_U32 regValue, rxCoal, txCoal; ++ int speed, queue, port; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl; ++ ++ port = pPortCtrl->portNo; ++ ++ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); ++ ++ mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", ++ port, ETH_PORT_STATUS_REG(port), regValue); ++ ++ mvOsPrintf("descInSram=%d, descSwCoher=%d\n", ++ ethDescInSram, ethDescSwCoher); ++ ++ if(regValue & ETH_GMII_SPEED_1000_MASK) ++ speed = 1000; ++ else if(regValue & ETH_MII_SPEED_100_MASK) ++ speed = 100; ++ else ++ speed = 10; ++ ++ mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); ++ ++ /* Link, Speed, Duplex, FlowControl */ ++ mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", ++ (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", ++ speed, ++ (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", ++ (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); ++ ++ mvOsPrintf("\n"); ++ ++ mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", ++ rxCoal, txCoal); ++ ++ mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", ++ pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, ++ pPortCtrl->portConfig.rxBpduQ, ++ pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); ++ ++ /* Print all RX and TX queues */ ++ for(queue=0; queuerxQueue[queue].pFirstDescr, ++ mvEthRxResourceGet(pPortCtrl, queue) ); ++ } ++ mvOsPrintf("\n"); ++ for(queue=0; queuetxQueue[queue].pFirstDescr, ++ mvEthTxResourceGet(pPortCtrl, queue) ); ++ } ++} ++ ++/* Print RX and TX queue of the Ethernet port */ ++void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode) ++{ ++ ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl; ++ ETH_QUEUE_CTRL *pQueueCtrl; ++ MV_U32 regValue; ++ ETH_RX_DESC *pRxDescr; ++ ETH_TX_DESC *pTxDescr; ++ int i, port = pPortCtrl->portNo; ++ ++ if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) ) ++ { ++ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); ++ mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); ++ ++ mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", ++ ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), ++ MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); ++ ++ ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", ++ (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr, ++ pQueueCtrl->resource); ++ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", ++ (MV_ULONG)pQueueCtrl->pCurrentDescr, ++ (MV_ULONG)pQueueCtrl->pUsedDescr); ++ ++ if(mode == 1) ++ { ++ pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; ++ i = 0; ++ do ++ { ++ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", ++ i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr), ++ pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize, ++ (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo, ++ ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo); ++ ++ ETH_DESCR_INV(pPortCtrl, pRxDescr); ++ pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); ++ i++; ++ } while (pRxDescr != pQueueCtrl->pFirstDescr); ++ } ++ } ++ else ++ mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); ++ } ++ ++ if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) ) ++ { ++ pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); ++ mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); ++ ++ regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); ++ mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", ++ ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); ++ ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", ++ (MV_ULONG)pQueueCtrl->pFirstDescr, ++ (MV_ULONG)pQueueCtrl->pLastDescr, ++ pQueueCtrl->resource); ++ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", ++ (MV_ULONG)pQueueCtrl->pCurrentDescr, ++ (MV_ULONG)pQueueCtrl->pUsedDescr); ++ ++ if(mode == 1) ++ { ++ pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; ++ i = 0; ++ do ++ { ++ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", ++ i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr), ++ pTxDescr->cmdSts, pTxDescr->byteCnt, ++ (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo, ++ pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0); ++ ++ ETH_DESCR_INV(pPortCtrl, pTxDescr); ++ pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); ++ i++; ++ } while (pTxDescr != pQueueCtrl->pFirstDescr); ++ } ++ } ++ else ++ mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); ++ } ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,146 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __MV_ETH_DEBUG_H__ ++#define __MV_ETH_DEBUG_H__ ++ ++#if 0 ++/* ++ ** Externs ++ */ ++void ethBpduRxQ(int port, int bpduQueue); ++void ethArpRxQ(int port, int bpduQueue); ++void ethTcpRxQ(int port, int bpduQueue); ++void ethUdpRxQ(int port, int bpduQueue); ++void ethMcastAdd(int port, char* macStr, int queue); ++ ++#ifdef INCLUDE_MULTI_QUEUE ++void ethRxPolicy( int port); ++void ethTxPolicy( int port); ++void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); ++void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); ++void ethRxPolQ(int port, int rxQueue, int rxQuota); ++#endif /* INCLUDE_MULTI_QUEUE */ ++ ++void print_egiga_stat(void *sc, unsigned int port); ++void ethPortStatus (int port); ++void ethPortQueues( int port, int rxQueue, int txQueue, int mode); ++void ethPortMcast(int port); ++void ethPortRegs(int port); ++void ethPortCounters(int port); ++void ethPortRmonCounters(int port); ++void ethRxCoal(int port, int usec); ++void ethTxCoal(int port, int usec); ++ ++void ethRegs(int port); ++void ethClearCounters(int port); ++void ethUcastSet(int port, char* macStr, int queue); ++void ethPortUcastShow(int port); ++ ++#ifdef CONFIG_MV_ETH_HEADER ++void run_com_header(const char *buffer); ++#endif ++ ++#ifdef INCLUDE_MULTI_QUEUE ++void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); ++void ethRxPolQ(int port, int queue, int quota); ++void ethRxPolicy(int port); ++void ethTxPolDef(int port, int txQ, char* headerHexStr); ++void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); ++void ethTxPolicy(int port); ++#endif /* INCLUDE_MULTI_QUEUE */ ++ ++#if (MV_ETH_VERSION >= 4) ++void ethEjpModeSet(int port, int mode) ++#endif ++#endif /* 0 */ ++ ++ ++ ++ ++void ethRxCoal(int port, int usec); ++void ethTxCoal(int port, int usec); ++#if (MV_ETH_VERSION >= 4) ++void ethEjpModeSet(int port, int mode); ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++void ethBpduRxQ(int port, int bpduQueue); ++void ethArpRxQ(int port, int arpQueue); ++void ethTcpRxQ(int port, int tcpQueue); ++void ethUdpRxQ(int port, int udpQueue); ++void ethTxPolicyRegs(int port); ++void ethPortRegs(int port); ++void ethRegs(int port); ++void ethClearCounters(int port); ++void ethPortCounters(int port); ++void ethPortRmonCounters(int port); ++void ethPortStatus(int port); ++void ethPortQueues(int port, int rxQueue, int txQueue, int mode); ++void ethUcastSet(int port, char* macStr, int queue); ++void ethPortUcastShow(int port); ++void ethMcastAdd(int port, char* macStr, int queue); ++void ethPortMcast(int port); ++void mvEthPortShow(void* pHndl); ++void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,751 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller ++* ++* DESCRIPTION: ++* This header file contains macros typedefs and function declaration specific to ++* the Marvell Gigabit Ethernet Controller. ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++#ifndef __mvEthGbe_h__ ++#define __mvEthGbe_h__ ++ ++extern MV_BOOL ethDescInSram; ++extern MV_BOOL ethDescSwCoher; ++extern ETH_PORT_CTRL* ethPortCtrl[]; ++ ++static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc) ++{ ++#if defined (ETH_DESCR_IN_SRAM) ++ if( ethDescInSram ) ++ return mvSramVirtToPhy(pDesc); ++ else ++#endif /* ETH_DESCR_IN_SRAM */ ++ return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); ++} ++/* Return port handler */ ++#define mvEthPortHndlGet(port) ethPortCtrl[port] ++ ++/* Used as WA for HW/SW race on TX */ ++static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep) ++{ ++ int deep = 0; ++ MV_U32 txCurrReg, txEnReg; ++ ETH_TX_DESC* pTxLastDesc; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); ++ if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) ++ { ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; ++ return 0; ++ } ++ ++ pQueueCtrl = &pPortCtrl->txQueue[queue]; ++ pTxLastDesc = pQueueCtrl->pCurrentDescr; ++ txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); ++ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) ++ { ++ /* All descriptors are processed, no chance for race */ ++ return 0; ++ } ++ ++ /* Check distance betwee HW and SW location: */ ++ /* If distance between HW and SW pointers is less than max_deep descriptors */ ++ /* Race condition is possible, so wait end of TX and restart TXQ */ ++ while(deep < max_deep) ++ { ++ pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); ++ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) ++ { ++ int count = 0; ++ ++ while( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0) ++ { ++ count++; ++ if(count > 10000) ++ { ++ mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", ++ MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) ); ++ break; ++ } ++ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); ++ } ++ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; ++ return count; ++ } ++ deep++; ++ } ++ /* Distance between HW and SW pointers is more than max_deep descriptors, */ ++ /* So NO race condition - do nothing */ ++ return -1; ++} ++ ++ ++/* defines */ ++#define ETH_CSUM_MIN_BYTE_COUNT 72 ++ ++/* Tailgate and Kirwood have only 2K TX FIFO */ ++#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) ++#define ETH_CSUM_MAX_BYTE_COUNT 1600 ++#else ++#define ETH_CSUM_MAX_BYTE_COUNT 9*1024 ++#endif /* MV_ETH_VERSION */ ++ ++#define ETH_MV_HEADER_SIZE 2 ++#define ETH_MV_TX_EN ++ ++/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ ++#define MIN_TX_BUFF_LOAD 8 ++#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) ++ ++/* Default port configuration value */ ++#define PORT_CONFIG_VALUE \ ++ ETH_DEF_RX_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ ++ ETH_RX_CHECKSUM_WITH_PSEUDO_HDR ++ ++/* Default port extend configuration value */ ++#define PORT_CONFIG_EXTEND_VALUE 0 ++ ++#define PORT_SERIAL_CONTROL_VALUE \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE | \ ++ ETH_SET_FULL_DUPLEX_MASK ++ ++#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ ++ ETH_FORCE_LINK_PASS_MASK | \ ++ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ ++ ETH_SET_FULL_DUPLEX_MASK | \ ++ ETH_SET_MII_SPEED_100_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE ++ ++ ++#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ ++ ETH_FORCE_LINK_PASS_MASK | \ ++ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ ++ ETH_SET_FULL_DUPLEX_MASK | \ ++ ETH_SET_GMII_SPEED_1000_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE ++ ++#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_IN_BAND_AN_EN_MASK | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE ++ ++/* Function headers: */ ++MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); ++MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue); ++MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue); ++MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue); ++MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); ++MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); ++MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); ++/* Interrupt Coalesting functions */ ++MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec); ++MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec); ++MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal); ++ ++/******************************************************************************/ ++/* Data Flow functions */ ++/******************************************************************************/ ++static INLINE void mvEthPortTxRestart(void* pPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; ++} ++ ++/* Get number of Free resources in specific TX queue */ ++static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ return (pPortCtrl->txQueue[txQueue].resource); ++} ++ ++/* Get number of Free resources in specific RX queue */ ++static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ return (pPortCtrl->rxQueue[rxQueue].resource); ++} ++ ++static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ if(pPortCtrl->txQueue[txQueue].resource == 0) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++/* Get number of Free resources in specific RX queue */ ++static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; ++ ++ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && ++ (pQueueCtrl->resource != 0) ) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && ++ (pQueueCtrl->resource != 0) ) ++ { ++ return MV_TRUE; ++ } ++ return MV_FALSE; ++} ++ ++/* Get number of Free resources in specific RX queue */ ++static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ if(pPortCtrl->rxQueue[rxQueue].resource == 0) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvEthPortTx - Send an Ethernet packet ++* ++* DESCRIPTION: ++* This routine send a given packet described by pPktInfo parameter. ++* Single buffer only. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of Tx queue. ++* MV_PKT_INFO *pPktInfo - User packet to send. ++* ++* RETURN: ++* MV_NO_RESOURCE - No enough resources to send this packet. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - Packet send successfully. ++* ++*******************************************************************************/ ++static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) ++{ ++ ETH_TX_DESC* pTxCurrDesc; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ int portNo; ++ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; ++ ++#ifdef ETH_DEBUG ++ if(pPortCtrl->portState != MV_ACTIVE) ++ return MV_BAD_STATE; ++#endif /* ETH_DEBUG */ ++ ++ portNo = pPortCtrl->portNo; ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ /* Get the Tx Desc ring indexes */ ++ pTxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ /* Check if there is enough resources to send the packet */ ++ if(pQueueCtrl->resource == 0) ++ return MV_NO_RESOURCE; ++ ++ pTxCurrDesc->byteCnt = pBufInfo->dataSize; ++ ++ /* Flash Buffer */ ++ if(pPktInfo->pktSize != 0) ++ { ++#ifdef MV_NETBSD ++ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; ++ ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); ++#else ++ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); ++#endif ++ pPktInfo->pktSize = 0; ++ } ++ else ++ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; ++ ++ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; ++ ++ /* There is only one buffer in the packet */ ++ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ ++ pTxCurrDesc->cmdSts = pPktInfo->status | ++ ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_GENERATE_CRC_MASK | ++ ETH_TX_ENABLE_INTERRUPT_MASK | ++ ETH_TX_ZERO_PADDING_MASK | ++ ETH_TX_FIRST_DESC_MASK | ++ ETH_TX_LAST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ ++ pQueueCtrl->resource--; ++ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); ++ ++ /* Apply send command */ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthPortSgTx - Send an Ethernet packet ++* ++* DESCRIPTION: ++* This routine send a given packet described by pBufInfo parameter. It ++* supports transmitting of a packet spaned over multiple buffers. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of Tx queue. ++* MV_PKT_INFO *pPktInfo - User packet to send. ++* ++* RETURN: ++* MV_NO_RESOURCE - No enough resources to send this packet. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - Packet send successfully. ++* ++*******************************************************************************/ ++static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) ++{ ++ ETH_TX_DESC* pTxFirstDesc; ++ ETH_TX_DESC* pTxCurrDesc; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ int portNo, bufCount; ++ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; ++ MV_U8* pTxBuf; ++ ++#ifdef ETH_DEBUG ++ if(pPortCtrl->portState != MV_ACTIVE) ++ return MV_BAD_STATE; ++#endif /* ETH_DEBUG */ ++ ++ portNo = pPortCtrl->portNo; ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ /* Get the Tx Desc ring indexes */ ++ pTxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ /* Check if there is enough resources to send the packet */ ++ if(pQueueCtrl->resource < pPktInfo->numFrags) ++ return MV_NO_RESOURCE; ++ ++ /* Remember first desc */ ++ pTxFirstDesc = pTxCurrDesc; ++ ++ bufCount = 0; ++ while(MV_TRUE) ++ { ++ if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) ++ { ++ /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ ++ /* to 64-bit boundary. Two options here: */ ++ /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ ++ /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ ++ /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ ++ pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC; ++ mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); ++ pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); ++ } ++ else ++ { ++ /* Flash Buffer */ ++#ifdef MV_NETBSD ++ pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr; ++ ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); ++#else ++ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); ++#endif ++ } ++ ++ pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; ++ bufCount++; ++ ++ if(bufCount >= pPktInfo->numFrags) ++ break; ++ ++ if(bufCount > 1) ++ { ++ /* There is middle buffer of the packet Not First and Not Last */ ++ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ } ++ /* Go to next descriptor and next buffer */ ++ pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); ++ } ++ /* Set last desc with DMA ownership and interrupt enable. */ ++ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; ++ if(bufCount == 1) ++ { ++ /* There is only one buffer in the packet */ ++ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ ++ pTxCurrDesc->cmdSts = pPktInfo->status | ++ ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_GENERATE_CRC_MASK | ++ ETH_TX_ENABLE_INTERRUPT_MASK | ++ ETH_TX_ZERO_PADDING_MASK | ++ ETH_TX_FIRST_DESC_MASK | ++ ETH_TX_LAST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ } ++ else ++ { ++ /* Last but not First */ ++ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_ENABLE_INTERRUPT_MASK | ++ ETH_TX_ZERO_PADDING_MASK | ++ ETH_TX_LAST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ ++ /* Update First when more than one buffer in the packet */ ++ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ ++ pTxFirstDesc->cmdSts = pPktInfo->status | ++ ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_GENERATE_CRC_MASK | ++ ETH_TX_FIRST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); ++ } ++ /* Update txQueue state */ ++ pQueueCtrl->resource -= bufCount; ++ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); ++ ++ /* Apply send command */ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthPortTxDone - Free all used Tx descriptors and mBlks. ++* ++* DESCRIPTION: ++* This routine returns the transmitted packet information to the caller. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of Tx queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. ++* ++* RETURN: ++* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. ++* MV_EMPTY - No transmitted packets to return. TX Queue is empty. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - There is transmitted packet in the queue, ++* 'pPktInfo' filled with relevant information. ++* ++*******************************************************************************/ ++static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue) ++{ ++ ETH_TX_DESC* pTxCurrDesc; ++ ETH_TX_DESC* pTxUsedDesc; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ MV_PKT_INFO* pPktInfo; ++ MV_U32 commandStatus; ++ ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ pTxUsedDesc = pQueueCtrl->pUsedDescr; ++ pTxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ while(MV_TRUE) ++ { ++ /* No more used descriptors */ ++ commandStatus = pTxUsedDesc->cmdSts; ++ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) ++ { ++ ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); ++ return NULL; ++ } ++ if( (pTxUsedDesc == pTxCurrDesc) && ++ (pQueueCtrl->resource != 0) ) ++ { ++ return NULL; ++ } ++ pQueueCtrl->resource++; ++ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); ++ if(commandStatus & (ETH_TX_LAST_DESC_MASK)) ++ { ++ pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo; ++ pPktInfo->status = commandStatus; ++ return pPktInfo; ++ } ++ pTxUsedDesc = pQueueCtrl->pUsedDescr; ++ } ++} ++ ++/******************************************************************************* ++* mvEthPortRx - Get new received packets from Rx queue. ++* ++* DESCRIPTION: ++* This routine returns the received data to the caller. There is no ++* data copying during routine operation. All information is returned ++* using pointer to packet information struct passed from the caller. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int rxQueue - Number of Rx queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to received packet. ++* ++* RETURN: ++* MV_NO_RESOURCE - No free resources in RX queue. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - New packet received and 'pBufInfo' structure filled ++* with relevant information. ++* ++*******************************************************************************/ ++static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue) ++{ ++ ETH_RX_DESC *pRxCurrDesc; ++ MV_U32 commandStatus; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ MV_PKT_INFO* pPktInfo; ++ ++ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); ++ ++ /* Check resources */ ++ if(pQueueCtrl->resource == 0) ++ { ++ mvOsPrintf("ethPortRx: no more resources\n"); ++ return NULL; ++ } ++ while(MV_TRUE) ++ { ++ /* Get the Rx Desc ring 'curr and 'used' indexes */ ++ pRxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ commandStatus = pRxCurrDesc->cmdSts; ++ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) ++ { ++ /* Nothing to receive... */ ++ ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); ++ return NULL; ++ } ++ ++ /* Valid RX only if FIRST and LAST bits are set */ ++ if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == ++ (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) ) ++ { ++ pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo; ++ pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; ++ pPktInfo->status = commandStatus; ++ pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; ++ ++ pQueueCtrl->resource--; ++ /* Update 'curr' in data structure */ ++ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); ++ ++#ifdef INCLUDE_SYNC_BARR ++ mvCpuIfSyncBarr(DRAM_TARGET); ++#endif ++ return pPktInfo; ++ } ++ else ++ { ++ ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr; ++ ++#ifdef ETH_DEBUG ++ mvOsPrintf("ethDrv: Unexpected Jumbo frame: " ++ "status=0x%08x, byteCnt=%d, pData=0x%x\n", ++ commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); ++#endif /* ETH_DEBUG */ ++ ++ /* move buffer from pCurrentDescr position to pUsedDescr position */ ++ pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; ++ pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; ++ pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; ++ ++ /* Return the descriptor to DMA ownership */ ++ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ++ ETH_RX_ENABLE_INTERRUPT_MASK; ++ ++ /* Flush descriptor and CPU pipe */ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); ++ ++ /* Move the used descriptor pointer to the next descriptor */ ++ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); ++ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. ++* ++* DESCRIPTION: ++* This routine returns a Rx buffer back to the Rx ring. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int rxQueue - Number of Rx queue. ++* MV_PKT_INFO *pPktInfo - Pointer to received packet. ++* ++* RETURN: ++* MV_ERROR - Unexpected Fatal error. ++* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be ++* returned to this queue. ++* MV_FULL - Buffer returned successfully and RX queue became full. ++* More buffers should not be returned at the time. ++* MV_OK - Buffer returned successfully and there are more free ++* places in the queue. ++* ++*******************************************************************************/ ++static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo) ++{ ++ ETH_RX_DESC* pRxUsedDesc; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ++ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; ++ ++ /* Get 'used' Rx descriptor */ ++ pRxUsedDesc = pQueueCtrl->pUsedDescr; ++ ++ /* Check that ring is not FULL */ ++ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && ++ (pQueueCtrl->resource != 0) ) ++ { ++ mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", ++ __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource, ++ pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; ++ pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo; ++ pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; ++ ++ /* Invalidate data buffer accordingly with pktSize */ ++ if(pPktInfo->pktSize != 0) ++ { ++ ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); ++ pPktInfo->pktSize = 0; ++ } ++ ++ /* Return the descriptor to DMA ownership */ ++ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; ++ ++ /* Flush descriptor and CPU pipe */ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); ++ ++ pQueueCtrl->resource++; ++ ++ /* Move the used descriptor pointer to the next descriptor */ ++ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); ++ ++ /* If ring became Full return MV_FULL */ ++ if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) ++ return MV_FULL; ++ ++ return MV_OK; ++} ++ ++ ++#endif /* __mvEthGbe_h__ */ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,700 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvEthRegsh ++#define __INCmvEthRegsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++/****************************************/ ++/* Ethernet Unit Registers */ ++/****************************************/ ++#define ETH_REG_BASE MV_ETH_REG_BASE ++ ++#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000) ++#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004) ++#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008) ++#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c) ++#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014) ++#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080) ++#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084) ++ ++ ++#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094) ++#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098) ++#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0) ++ ++#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400) ++#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404) ++#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408) ++#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c) ++#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410) ++#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414) ++#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418) ++#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c) ++#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2)) ++#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c) ++#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440) ++#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444) ++ ++#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680) ++#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448) ++ ++#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c) ++#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450) ++#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454) ++#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458) ++#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c) ++#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460) ++#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464) ++#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468) ++#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c) ++#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474) ++#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c) ++#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484) ++#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488) ++#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494) ++#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc) ++#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0) ++#define ETH_TX_QUEUE_COMMAND1_REG(port) (ETH_REG_BASE(port) + 0x4e4) ++#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8) ++#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec) ++#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780) ++#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4)) ++#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4)) ++#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4)) ++#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4)) ++#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2)) ++ ++#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4)) ++#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4)) ++#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4)) ++ ++#if (MV_ETH_VERSION >= 4) ++#define ETH_TXQ_CMD_1_REG(port) (ETH_REG_BASE(port) + 0x4E4) ++#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8) ++#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8) ++#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0) ++#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4) ++#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8) ++#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0) ++#endif /* MV_ETH_VERSION >= 4 */ ++ ++#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000) ++#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400) ++#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500) ++#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600) ++ ++/* Phy address register definitions */ ++#define ETH_PHY_ADDR_OFFS 0 ++#define ETH_PHY_ADDR_MASK (0x1f <= 4) ++#define ETH_TX_EJP_RESET_BIT 0 ++#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT) ++ ++#define ETH_TX_EJP_ENABLE_BIT 2 ++#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) ++ ++#define ETH_TX_LEGACY_WRR_BIT 3 ++#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++/***** BITs of Ethernet Port Status reg (PSR) *****/ ++#define ETH_LINK_UP_BIT 1 ++#define ETH_LINK_UP_MASK (1<= 4) ++MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode); ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus); ++ ++/* Marvell Header control */ ++MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); ++ ++/* PHY routines */ ++void mvEthPhyAddrSet(void* pPortHandle, int phyAddr); ++int mvEthPhyAddrGet(void* pPortHandle); ++ ++/* Power management routines */ ++void mvEthPortPowerDown(int port); ++void mvEthPortPowerUp(int port); ++ ++/******************** ETH PRIVATE ************************/ ++ ++/*#define UNCACHED_TX_BUFFERS*/ ++/*#define UNCACHED_RX_BUFFERS*/ ++ ++ ++/* Port attributes */ ++/* Size of a Tx/Rx descriptor used in chain list data structure */ ++#define ETH_RX_DESC_ALIGNED_SIZE 32 ++#define ETH_TX_DESC_ALIGNED_SIZE 32 ++ ++#define TX_DISABLE_TIMEOUT_MSEC 1000 ++#define RX_DISABLE_TIMEOUT_MSEC 1000 ++#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 ++#define PORT_DISABLE_WAIT_TCLOCKS 5000 ++ ++/* Macros that save access to desc in order to find next desc pointer */ ++#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \ ++ ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \ ++ (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \ ++ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) ++ ++#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ ++ ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ ++ (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \ ++ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) ++ ++#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ ++ ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ ++ (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \ ++ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) ++ ++#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ ++ ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ ++ (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \ ++ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) ++ ++ ++/* Queue specific information */ ++typedef struct ++{ ++ void* pFirstDescr; ++ void* pLastDescr; ++ void* pCurrentDescr; ++ void* pUsedDescr; ++ int resource; ++ MV_BUF_INFO descBuf; ++} ETH_QUEUE_CTRL; ++ ++ ++/* Ethernet port specific infomation */ ++typedef struct _ethPortCtrl ++{ ++ int portNo; ++ ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ ++ ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ ++ ++ MV_ETH_PORT_CFG portConfig; ++ MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; ++ MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; ++ ++ /* Register images - For DP */ ++ MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ ++ MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ ++ ++ MV_STATE portState; ++ ++ MV_U8 mcastCount[256]; ++ MV_U32* hashPtr; ++ void *osHandle; ++} ETH_PORT_CTRL; ++ ++/************** MACROs ****************/ ++ ++/* MACROs to Flush / Invalidate TX / RX Buffers */ ++#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) ++# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ ++ mvOsCacheClear(NULL, (pAddr), (size)); \ ++ /*CPU_PIPE_FLUSH;*/ ++#else ++# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ ++ mvOsIoVirtToPhy(NULL, (pAddr)); ++#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ ++ ++#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) ) ++# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ ++ mvOsCacheInvalidate (NULL, (pAddr), (size)); \ ++ /*CPU_PIPE_FLUSH;*/ ++#else ++# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) ++#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ ++ ++#ifdef ETH_DESCR_UNCACHED ++ ++#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) ++#define ETH_DESCR_INV(pPortCtrl, pDescr) ++ ++#else ++ ++#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ ++ mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) ++ ++#define ETH_DESCR_INV(pPortCtrl, pDescr) \ ++ mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) ++ ++#endif /* ETH_DESCR_UNCACHED */ ++ ++#include "eth/gbe/mvEthGbe.h" ++ ++#endif /* __mvEth_h__ */ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.4 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,362 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "gpp/mvGpp.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value); ++ ++/******************************************************************************* ++* mvGppTypeSet - Enable a GPP (OUT) pin ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the type ++* of corresponding GPP will be set. Other GPPs are ignored. ++* value - 32bit value that describes GPP type per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 to input and GPP15 to output. ++* mvGppTypeSet(0, (GPP8 | GPP15), ++* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value); ++ ++ /* Workaround for Erratum FE-MISC-70*/ ++ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) ++ { ++ mask &= 0x2; ++ gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value); ++ } /*End of WA*/ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the type ++* of corresponding GPP will be set. Other GPPs are ignored. ++* value - 32bit value that describes GPP blink per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 to be static and GPP15 to be blinking. ++* mvGppBlinkEn(0, (GPP8 | GPP15), ++* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value); ++ ++ return MV_OK; ++ ++} ++/******************************************************************************* ++* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the type ++* of corresponding GPP will be set. Other GPPs are ignored. ++* value - 32bit value that describes GPP polarity per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 to the actual pin value and GPP15 to be inverted. ++* mvGppPolaritySet(0, (GPP8 | GPP15), ++* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* returned value is valid for it. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Get GPP8 and GPP15 value. ++* mvGppPolarityGet(0, (GPP8 | GPP15)); ++* ++* RETURN: ++* 32bit value that describes GPP polatity mode per pin. ++* ++*******************************************************************************/ ++MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask) ++{ ++ MV_U32 regVal; ++ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n")); ++ return MV_ERROR; ++ } ++ regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group)); ++ ++ return (regVal & mask); ++} ++ ++/******************************************************************************* ++* mvGppValueGet - Get a GPP Pin list value. ++* ++* DESCRIPTION: ++* This function get GPP value. ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* returned value is valid for it. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Get GPP8 and GPP15 value. ++* mvGppValueGet(0, (GPP8 | GPP15)); ++* ++* RETURN: ++* 32bit value that describes GPP activity mode per pin. ++* ++*******************************************************************************/ ++MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask) ++{ ++ MV_U32 gppData; ++ ++ gppData = MV_REG_READ(GPP_DATA_IN_REG(group)); ++ ++ gppData &= mask; ++ ++ return gppData; ++ ++} ++ ++/******************************************************************************* ++* mvGppValueSet - Set a GPP Pin list value. ++* ++* DESCRIPTION: ++* This function set value for given GPP pin list. ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* value of corresponding GPP will be set accordingly. Other GPP ++* are not affected. ++* value - 32bit value that describes GPP value per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 value of '0' and GPP15 value of '1'. ++* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ MV_U32 outEnable, tmp; ++ MV_U32 i; ++ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ /* verify that the gpp pin is configured as output */ ++ /* Note that in the register out enabled -> bit = '0'. */ ++ outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group)); ++ ++ /* Workaround for Erratum FE-MISC-70*/ ++ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) ++ { ++ tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0)); ++ outEnable &= 0xfffffffd; ++ outEnable |= (tmp & 0x2); ++ } /*End of WA*/ ++ ++ for (i = 0 ; i < 32 ;i++) ++ { ++ if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i))) ++ { ++ mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\ ++ "value to GPP %d in input mode.\n", i); ++ return MV_ERROR; ++ } ++ } ++ ++ gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value); ++ ++ return MV_OK; ++ ++} ++/******************************************************************************* ++* gppRegSet - Set a specific GPP pin on a specific GPP register ++* ++* DESCRIPTION: ++* This function set a specific GPP pin on a specific GPP register ++* ++* INPUT: ++* regOffs - GPP Register offset ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* value of corresponding GPP will be set accordingly. Other GPP ++* are not affected. ++* value - 32bit value that describes GPP value per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 value of '0' and GPP15 value of '1'. ++* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value) ++{ ++ MV_U32 gppData; ++ ++ gppData = MV_REG_READ(regOffs); ++ ++ gppData &= ~mask; ++ ++ gppData |= (value & mask); ++ ++ MV_REG_WRITE(regOffs, gppData); ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,118 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvGppH ++#define __INCmvGppH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "gpp/mvGppRegs.h" ++ ++/* These macros describes the GPP type. Each of the GPPs pins can */ ++/* be assigned to act as a general purpose input or output pin. */ ++#define MV_GPP_IN 0xFFFFFFFF /* GPP input */ ++#define MV_GPP_OUT 0 /* GPP output */ ++ ++ ++/* These macros describes the GPP Out Enable. */ ++#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled*/ ++#define MV_GPP_OUT_EN 0 /* Out pin enabled*/ ++ ++/* These macros describes the GPP Out Blinking. */ ++/* When set and the corresponding bit in GPIO Data Out Enable Control */ ++/* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */ ++/* 2^24 TCLK clocks). */ ++#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking*/ ++#define MV_GPP_OUT_STATIC 0 /* Out pin static*/ ++ ++ ++/* These macros describes the GPP Polarity. */ ++/* When set to 1 GPIO Data In Register reflects the inverted value of the */ ++/* corresponding pin. */ ++ ++#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got*/ ++#define MV_GPP_IN_ORIGIN 0 /* original value is got*/ ++ ++/* mvGppTypeSet - Set PP pin mode (IN or OUT) */ ++MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++/* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */ ++MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++/* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */ ++MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++/* mvGppPolarityGet - Get the Polarity of a GPP Pin */ ++MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask); ++ ++/* mvGppValueGet - Get a GPP Pin list value.*/ ++MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); ++ ++ ++/* mvGppValueSet - Set a GPP Pin list value. */ ++MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++#endif /* #ifndef __INCmvGppH */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,116 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvGppRegsH ++#define __INCmvGppRegsH ++ ++#define MV_GPP0 BIT0 ++#define MV_GPP1 BIT1 ++#define MV_GPP2 BIT2 ++#define MV_GPP3 BIT3 ++#define MV_GPP4 BIT4 ++#define MV_GPP5 BIT5 ++#define MV_GPP6 BIT6 ++#define MV_GPP7 BIT7 ++#define MV_GPP8 BIT8 ++#define MV_GPP9 BIT9 ++#define MV_GPP10 BIT10 ++#define MV_GPP11 BIT11 ++#define MV_GPP12 BIT12 ++#define MV_GPP13 BIT13 ++#define MV_GPP14 BIT14 ++#define MV_GPP15 BIT15 ++#define MV_GPP16 BIT16 ++#define MV_GPP17 BIT17 ++#define MV_GPP18 BIT18 ++#define MV_GPP19 BIT19 ++#define MV_GPP20 BIT20 ++#define MV_GPP21 BIT21 ++#define MV_GPP22 BIT22 ++#define MV_GPP23 BIT23 ++#define MV_GPP24 BIT24 ++#define MV_GPP25 BIT25 ++#define MV_GPP26 BIT26 ++#define MV_GPP27 BIT27 ++#define MV_GPP28 BIT28 ++#define MV_GPP29 BIT29 ++#define MV_GPP30 BIT30 ++#define MV_GPP31 BIT31 ++ ++ ++/* registers offsets */ ++ ++#define GPP_DATA_OUT_REG(grp) ((grp == 0) ? 0x10100 : 0x10140) ++#define GPP_DATA_OUT_EN_REG(grp) ((grp == 0) ? 0x10104 : 0x10144) ++#define GPP_BLINK_EN_REG(grp) ((grp == 0) ? 0x10108 : 0x10148) ++#define GPP_DATA_IN_POL_REG(grp) ((grp == 0) ? 0x1010C : 0x1014c) ++#define GPP_DATA_IN_REG(grp) ((grp == 0) ? 0x10110 : 0x10150) ++#define GPP_INT_CAUSE_REG(grp) ((grp == 0) ? 0x10114 : 0x10154) ++#define GPP_INT_MASK_REG(grp) ((grp == 0) ? 0x10118 : 0x10158) ++#define GPP_INT_LVL_REG(grp) ((grp == 0) ? 0x1011c : 0x1015c) ++ ++#define GPP_DATA_OUT_SET_REG 0x10120 ++#define GPP_DATA_OUT_CLEAR_REG 0x10124 ++ ++#endif /* #ifndef __INCmvGppRegsH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.2 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1047 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "pci/mvPci.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++ ++ ++MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod) ++{ ++ if (MV_PCI_MOD_HOST == pciIfmod) ++ { ++ ++ mvPciLocalBusNumSet(pciIf, PCI_HOST_BUS_NUM(pciIf)); ++ mvPciLocalDevNumSet(pciIf, PCI_HOST_DEV_NUM(pciIf)); ++ ++ /* Local device master Enable */ ++ mvPciMasterEnable(pciIf, MV_TRUE); ++ ++ /* Local device slave Enable */ ++ mvPciSlaveEnable(pciIf, mvPciLocalBusNumGet(pciIf), ++ mvPciLocalDevNumGet(pciIf), MV_TRUE); ++ } ++ /* enable CPU-2-PCI ordering */ ++ MV_REG_BIT_SET(PCI_CMD_REG(0), PCR_CPU_TO_PCI_ORDER_EN); ++} ++ ++/******************************************************************************* ++* mvPciCommandSet - Set PCI comman register value. ++* ++* DESCRIPTION: ++* This function sets a given PCI interface with its command register ++* value. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* command - 32bit value to be written to comamnd register. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if pciIf is not in range otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command) ++{ ++ MV_U32 locBusNum, locDevNum, regVal; ++ ++ locBusNum = mvPciLocalBusNumGet(pciIf); ++ locDevNum = mvPciLocalDevNumGet(pciIf); ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Set command register */ ++ MV_REG_WRITE(PCI_CMD_REG(pciIf), command); ++ ++ /* Upodate device max outstanding split tarnsaction */ ++ if ((command & PCR_CPU_TO_PCI_ORDER_EN) && ++ (command & PCR_PCI_TO_CPU_ORDER_EN)) ++ { ++ /* Read PCI-X command register */ ++ regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND); ++ ++ /* clear bits 22:20 */ ++ regVal &= 0xff8fffff; ++ ++ /* set reset value */ ++ regVal |= (0x3 << 20); ++ ++ /* Write back the value */ ++ mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal); ++ } ++ ++ return MV_OK; ++ ++ ++} ++ ++ ++/******************************************************************************* ++* mvPciModeGet - Get PCI interface mode. ++* ++* DESCRIPTION: ++* This function returns the given PCI interface mode. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* ++* OUTPUT: ++* pPciMode - Pointer to PCI mode structure. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode) ++{ ++ MV_U32 pciMode; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (NULL == pPciMode) ++ { ++ mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n"); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Read pci mode register */ ++ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); ++ ++ switch (pciMode & PMR_PCI_MODE_MASK) ++ { ++ case PMR_PCI_MODE_CONV: ++ pPciMode->pciType = MV_PCI_CONV; ++ ++ if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN) ++ { ++ pPciMode->pciSpeed = 66000000; /* 66MHZ */ ++ } ++ else ++ { ++ pPciMode->pciSpeed = 33000000; /* 33MHZ */ ++ } ++ ++ break; ++ ++ case PMR_PCI_MODE_PCIX_66MHZ: ++ pPciMode->pciType = MV_PCIX; ++ pPciMode->pciSpeed = 66000000; /* 66MHZ */ ++ break; ++ ++ case PMR_PCI_MODE_PCIX_100MHZ: ++ pPciMode->pciType = MV_PCIX; ++ pPciMode->pciSpeed = 100000000; /* 100MHZ */ ++ break; ++ ++ case PMR_PCI_MODE_PCIX_133MHZ: ++ pPciMode->pciType = MV_PCIX; ++ pPciMode->pciSpeed = 133000000; /* 133MHZ */ ++ break; ++ ++ default: ++ { ++ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); ++ return MV_ERROR; ++ } ++ } ++ ++ switch (pciMode & PMR_PCI_64_MASK) ++ { ++ case PMR_PCI_64_64BIT: ++ pPciMode->pciWidth = MV_PCI_64; ++ break; ++ ++ case PMR_PCI_64_32BIT: ++ pPciMode->pciWidth = MV_PCI_32; ++ break; ++ ++ default: ++ { ++ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); ++ return MV_ERROR; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciRetrySet - Set PCI retry counters ++* ++* DESCRIPTION: ++* This function specifies the number of times the PCI controller ++* retries a transaction before it quits. ++* Applies to the PCI Master when acting as a requester. ++* Applies to the PCI slave when acting as a completer (PCI-X mode). ++* A 0x00 value means a "retry forever". ++* ++* INPUT: ++* pciIf - PCI interface number. ++* counter - Number of times PCI controller retry. Use counter value ++* up to PRR_RETRY_CNTR_MAX. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter) ++{ ++ MV_U32 pciRetry; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (counter >= PRR_RETRY_CNTR_MAX) ++ { ++ mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* Reading PCI retry register */ ++ pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf)); ++ ++ pciRetry &= ~PRR_RETRY_CNTR_MASK; ++ ++ pciRetry |= (counter << PRR_RETRY_CNTR_OFFS); ++ ++ /* write new value */ ++ MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciDiscardTimerSet - Set PCI discard timer ++* ++* DESCRIPTION: ++* This function set PCI discard timer. ++* In conventional PCI mode: ++* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed ++* read buffers (non-completed delayed read) before invalidate the buffer. ++* Set to '0' to disable the timer. The PCI slave waits for delayed ++* read completion forever. ++* In PCI-X mode: ++* Specifies the number of PCLK cycles the PCI master waits for split ++* completion transaction, before it invalidates the pre-allocated read ++* buffer. ++* Set to '0' to disable the timer. The PCI master waits for split ++* completion forever. ++* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK, ++* unless using the "wait for ever" setting 0x0. ++* NOTE: Must not be updated while there are pending read requests. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* pClkCycles - Number of PCI clock cycles. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles) ++{ ++ MV_U32 pciDiscardTimer; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (pClkCycles >= PDTR_TIMER_MIN) ++ { ++ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n", ++ pClkCycles); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* Read PCI Discard Timer */ ++ pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf)); ++ ++ pciDiscardTimer &= ~PDTR_TIMER_MASK; ++ ++ pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS); ++ ++ /* Write new value */ ++ MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer); ++ ++ return MV_OK; ++ ++} ++ ++/* PCI Arbiter routines */ ++ ++/******************************************************************************* ++* mvPciArbEnable - PCI arbiter enable/disable ++* ++* DESCRIPTION: ++* This fuction enable/disables a given PCI interface arbiter. ++* NOTE: Arbiter setting can not be changed while in work. It should only ++* be set once. ++* INPUT: ++* pciIf - PCI interface number. ++* enable - Enable/disable parameter. If enable = MV_TRUE then enable. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable) ++{ ++ MV_U32 regVal; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_ERROR; ++ } ++ ++ /* Set PCI Arbiter Control register according to default configuration */ ++ regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); ++ ++ /* Make sure arbiter disabled before changing its values */ ++ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); ++ ++ regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK; ++ ++ regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */ ++ ++ if (MV_TRUE == enable) ++ { ++ regVal |= PACR_ARB_ENABLE; ++ } ++ else ++ { ++ regVal &= ~PACR_ARB_ENABLE; ++ } ++ ++ /* Write to register */ ++ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciArbParkDis - Disable arbiter parking on agent ++* ++* DESCRIPTION: ++* This function disables the PCI arbiter from parking on the given agent ++* list. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* pciAgentMask - When a bit in the mask is set to '1', parking on ++* the associated PCI master is disabled. Mask bit ++* refers to bit 0 - 6. For example disable parking on PCI ++* agent 3 set pciAgentMask 0x4 (bit 3 is set). ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask) ++{ ++ MV_U32 pciArbiterCtrl; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_ERROR; ++ } ++ ++ /* Reading Arbiter Control register */ ++ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); ++ ++ /* Arbiter must be disabled before changing parking */ ++ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); ++ ++ /* do the change */ ++ pciArbiterCtrl &= ~PACR_PARK_DIS_MASK; ++ pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS); ++ ++ /* writing new value ( if th earbiter was enabled before the change */ ++ /* here it will be reenabled */ ++ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciArbBrokDetectSet - Set PCI arbiter broken detection ++* ++* DESCRIPTION: ++* This function sets the maximum number of cycles that the arbiter ++* waits for a PCI master to respond to its grant assertion. If a ++* PCI agent fails to respond within this time, the PCI arbiter aborts ++* the transaction and performs a new arbitration cycle. ++* NOTE: Value must be greater than '1' for conventional PCI and ++* greater than '5' for PCI-X. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken ++* master detection is disabled. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles) ++{ ++ MV_U32 pciArbiterCtrl; ++ MV_U32 pciMode; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Checking PCI mode and if pClkCycles is legal value */ ++ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); ++ pciMode &= PMR_PCI_MODE_MASK; ++ ++ if (PMR_PCI_MODE_CONV == pciMode) ++ { ++ if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN) ++ return MV_ERROR; ++ } ++ else ++ { ++ if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN) ++ return MV_ERROR; ++ } ++ ++ pClkCycles <<= PACR_BROKEN_VAL_OFFS; ++ ++ /* Reading Arbiter Control register */ ++ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); ++ pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK; ++ pciArbiterCtrl |= pClkCycles; ++ ++ /* Arbiter must be disabled before changing broken detection */ ++ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); ++ ++ /* writing new value ( if th earbiter was enabled before the change */ ++ /* here it will be reenabled */ ++ ++ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); ++ ++ return MV_OK; ++} ++ ++/* PCI configuration space read write */ ++ ++/******************************************************************************* ++* mvPciConfigRead - Read from configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit read from PCI configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to read from local bus segment, use ++* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pciIf - PCI interface number. ++* bus - PCI segment bus number. ++* dev - PCI device number. ++* func - Function number. ++* regOffs - Register offset. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit register data, 0xffffffff on error ++* ++*******************************************************************************/ ++MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++ MV_U32 pciData = 0; ++ ++ /* Parameter checking */ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ if (dev >= MAX_PCI_DEVICES) ++ { ++ DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (func >= MAX_PCI_FUNCS) ++ { ++ DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (bus >= MAX_PCI_BUSSES) ++ { ++ DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus)); ++ return MV_ERROR; ++ } ++ ++ ++ /* Creating PCI address to be passed */ ++ pciData |= (bus << PCAR_BUS_NUM_OFFS); ++ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); ++ pciData |= (func << PCAR_FUNC_NUM_OFFS); ++ pciData |= (regOff & PCAR_REG_NUM_MASK); ++ ++ pciData |= PCAR_CONFIG_EN; ++ ++ /* Write the address to the PCI configuration address register */ ++ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); ++ ++ /* In order to let the PCI controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) ++ { ++ return MV_ERROR; ++ } ++ /* Read the Data returned in the PCI Data register */ ++ pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf)); ++ ++ return pciData; ++} ++ ++/******************************************************************************* ++* mvPciConfigWrite - Write to configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit write to PCI configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to write to local bus segment, use ++* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pciIf - PCI interface number. ++* bus - PCI segment bus number. ++* dev - PCI device number. ++* func - Function number. ++* regOffs - Register offset. ++* data - 32bit data. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++ MV_U32 pciData = 0; ++ ++ /* Parameter checking */ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ if (dev >= MAX_PCI_DEVICES) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev); ++ return MV_BAD_PARAM; ++ } ++ ++ if (func >= MAX_PCI_FUNCS) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func); ++ return MV_ERROR; ++ } ++ ++ if (bus >= MAX_PCI_BUSSES) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus); ++ return MV_ERROR; ++ } ++ ++ /* Creating PCI address to be passed */ ++ pciData |= (bus << PCAR_BUS_NUM_OFFS); ++ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); ++ pciData |= (func << PCAR_FUNC_NUM_OFFS); ++ pciData |= (regOff & PCAR_REG_NUM_MASK); ++ ++ pciData |= PCAR_CONFIG_EN; ++ ++ /* Write the address to the PCI configuration address register */ ++ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); ++ ++ /* In order to let the PCI controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) ++ { ++ return MV_ERROR; ++ } ++ ++ /* Write the Data passed to the PCI Data register */ ++ MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciMasterEnable - Enable/disale PCI interface master transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PCI command status ++* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI ++* master is allowed to gain ownership on the bus, otherwise it is ++* incapable to do so. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable) ++{ ++ MV_U32 pciCommandStatus; ++ MV_U32 RegOffs; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_ERROR; ++ } ++ ++ localBus = mvPciLocalBusNumGet(pciIf); ++ localDev = mvPciLocalDevNumGet(pciIf); ++ ++ RegOffs = PCI_STATUS_AND_COMMAND; ++ ++ pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs); ++ ++ if (MV_TRUE == enable) ++ { ++ pciCommandStatus |= PSCR_MASTER_EN; ++ } ++ else ++ { ++ pciCommandStatus &= ~PSCR_MASTER_EN; ++ } ++ ++ mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PCI command status ++* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, ++* the PCI slave is allowed to respond to PCI IO space access (bit 0) ++* and PCI memory space access (bit 1). ++* ++* INPUT: ++* pciIf - PCI interface number. ++* dev - PCI device number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) ++{ ++ MV_U32 pciCommandStatus; ++ MV_U32 RegOffs; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (dev >= MAX_PCI_DEVICES) ++ { ++ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ RegOffs = PCI_STATUS_AND_COMMAND; ++ ++ pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs); ++ ++ if (MV_TRUE == enable) ++ { ++ pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN); ++ } ++ else ++ { ++ pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN); ++ } ++ ++ mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciLocalBusNumSet - Set PCI interface local bus number. ++* ++* DESCRIPTION: ++* This function sets given PCI interface its local bus number. ++* Note: In case the PCI interface is PCI-X, the information is read-only. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* busNum - Bus number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PCI interface is PCI-X. ++* MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) ++{ ++ MV_U32 pciP2PConfig; ++ MV_PCI_MODE pciMode; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (busNum >= MAX_PCI_BUSSES) ++ { ++ mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum); ++ return MV_ERROR; ++ ++ } ++ ++ localBus = mvPciLocalBusNumGet(pciIf); ++ localDev = mvPciLocalDevNumGet(pciIf); ++ ++ ++ /* PCI interface mode */ ++ mvPciModeGet(pciIf, &pciMode); ++ ++ /* if PCI type is PCI-X then it is not allowed to change the dev number */ ++ if (MV_PCIX == pciMode.pciType) ++ { ++ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); ++ ++ pciP2PConfig &= ~PXS_BN_MASK; ++ ++ pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK; ++ ++ mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); ++ ++ } ++ else ++ { ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ ++ pciP2PConfig &= ~PPCR_BUS_NUM_MASK; ++ ++ pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK; ++ ++ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); ++ ++ } ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciLocalBusNumGet - Get PCI interface local bus number. ++* ++* DESCRIPTION: ++* This function gets the local bus number of a given PCI interface. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local bus number.0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf) ++{ ++ MV_U32 pciP2PConfig; ++ ++ /* Parameter checking */ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ pciP2PConfig &= PPCR_BUS_NUM_MASK; ++ return (pciP2PConfig >> PPCR_BUS_NUM_OFFS); ++} ++ ++ ++/******************************************************************************* ++* mvPciLocalDevNumSet - Set PCI interface local device number. ++* ++* DESCRIPTION: ++* This function sets given PCI interface its local device number. ++* Note: In case the PCI interface is PCI-X, the information is read-only. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* devNum - Device number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) ++{ ++ MV_U32 pciP2PConfig; ++ MV_PCI_MODE pciMode; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (devNum >= MAX_PCI_DEVICES) ++ { ++ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", ++ devNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ localBus = mvPciLocalBusNumGet(pciIf); ++ localDev = mvPciLocalDevNumGet(pciIf); ++ ++ /* PCI interface mode */ ++ mvPciModeGet(pciIf, &pciMode); ++ ++ /* if PCI type is PCIX then it is not allowed to change the dev number */ ++ if (MV_PCIX == pciMode.pciType) ++ { ++ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); ++ ++ pciP2PConfig &= ~PXS_DN_MASK; ++ ++ pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK; ++ ++ mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); ++ } ++ else ++ { ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ ++ pciP2PConfig &= ~PPCR_DEV_NUM_MASK; ++ ++ pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK; ++ ++ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciLocalDevNumGet - Get PCI interface local device number. ++* ++* DESCRIPTION: ++* This function gets the local device number of a given PCI interface. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local device number. 0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf) ++{ ++ MV_U32 pciP2PConfig; ++ ++ /* Parameter checking */ ++ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ ++ pciP2PConfig &= PPCR_DEV_NUM_MASK; ++ ++ return (pciP2PConfig >> PPCR_DEV_NUM_OFFS); ++} ++ ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,185 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCPCIH ++#define __INCPCIH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "pci/mvPciRegs.h" ++ ++ ++/* NOTE not supported in this driver: ++ ++ Built In Self Test (BIST) ++ Vital Product Data (VPD) ++ Message Signaled Interrupt (MSI) ++ Power Management ++ Compact PCI Hot Swap ++ Header retarget ++ ++Registers not supported: ++1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0) ++2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C) ++*/ ++ ++/* defines */ ++/* The number of supported PCI interfaces depend on Marvell controller */ ++/* device number. This device number ID is located on the PCI unit */ ++/* configuration header. This creates a loop where calling PCI */ ++/* configuration read/write routine results a call to get PCI configuration */ ++/* information etc. This macro defines a default PCI interface. This PCI */ ++/* interface is sure to exist. */ ++#define PCI_DEFAULT_IF 0 ++ ++ ++/* typedefs */ ++/* The Marvell controller supports both conventional PCI and PCI-X. */ ++/* This enumeration describes the PCI type. */ ++typedef enum _mvPciType ++{ ++ MV_PCI_CONV, /* Conventional PCI */ ++ MV_PCIX /* PCI-X */ ++}MV_PCI_TYPE; ++ ++typedef enum _mvPciMod ++{ ++ MV_PCI_MOD_HOST, ++ MV_PCI_MOD_DEVICE ++}MV_PCI_MOD; ++ ++ ++/* The Marvell controller supports both PCI width of 32 and 64 bit. */ ++/* This enumerator describes PCI width */ ++typedef enum _mvPciWidth ++{ ++ MV_PCI_32, /* PCI width 32bit */ ++ MV_PCI_64 /* PCI width 64bit */ ++}MV_PCI_WIDTH; ++ ++/* This structure describes the PCI unit configured type, speed and width. */ ++typedef struct _mvPciMode ++{ ++ MV_PCI_TYPE pciType; /* PCI type */ ++ MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */ ++ MV_PCI_WIDTH pciWidth; /* PCI bus width */ ++}MV_PCI_MODE; ++ ++/* mvPciInit - Initialize PCI interfaces*/ ++MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); ++ ++/* mvPciCommandSet - Set PCI comman register value.*/ ++MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command); ++ ++/* mvPciModeGet - Get PCI interface mode.*/ ++MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode); ++ ++/* mvPciRetrySet - Set PCI retry counters*/ ++MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter); ++ ++/* mvPciDiscardTimerSet - Set PCI discard timer*/ ++MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles); ++ ++/* mvPciArbEnable - PCI arbiter enable/disable*/ ++MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable); ++ ++/* mvPciArbParkDis - Disable arbiter parking on agent */ ++MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask); ++ ++/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */ ++MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles); ++ ++/* mvPciConfigRead - Read from configuration space */ ++MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPciConfigWrite - Write to configuration space */ ++MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/ ++MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable); ++ ++/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/ ++MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable); ++ ++/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/ ++MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); ++ ++/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/ ++MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf); ++ ++/* mvPciLocalDevNumSet - Set PCI interface local device number.*/ ++MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); ++ ++/* mvPciLocalDevNumGet - Get PCI interface local device number.*/ ++MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf); ++ ++ ++#endif /* #ifndef __INCPCIH */ ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,411 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPCIREGSH ++#define __INCPCIREGSH ++ ++ ++#include "pci-if/mvPciIfRegs.h" ++/* defines */ ++#define MAX_PCI_DEVICES 32 ++#define MAX_PCI_FUNCS 8 ++#define MAX_PCI_BUSSES 128 ++ ++/* enumerators */ ++ ++/* This enumerator described the possible PCI slave targets. */ ++/* PCI slave targets are designated memory/IO address spaces that the */ ++/* PCI slave targets can access. They are also refered as "targets" */ ++/* this enumeratoe order is determined by the content of : ++ PCI_BASE_ADDR_ENABLE_REG */ ++ ++ ++/* registers offsetes defines */ ++ ++ ++ ++/*************************/ ++/* PCI control registers */ ++/*************************/ ++/* maen : should add new registers */ ++#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) ++#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) ++#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) ++#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) ++#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) ++#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) ++#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ ++ (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) ++#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ ++ (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) ++#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ ++ (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) ++ ++#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) ++ ++/* PCI Dll Control (PDC)*/ ++#define PDC_DLL_EN BIT0 ++ ++ ++/* PCI Command Register (PCR) */ ++#define PCR_MASTER_BYTE_SWAP_EN BIT0 ++#define PCR_MASTER_WR_COMBINE_EN BIT4 ++#define PCR_MASTER_RD_COMBINE_EN BIT5 ++#define PCR_MASTER_WR_TRIG_WHOLE BIT6 ++#define PCR_MASTER_RD_TRIG_WHOLE BIT7 ++#define PCR_MASTER_MEM_RD_LINE_EN BIT8 ++#define PCR_MASTER_MEM_RD_MULT_EN BIT9 ++#define PCR_MASTER_WORD_SWAP_EN BIT10 ++#define PCR_SLAVE_WORD_SWAP_EN BIT11 ++#define PCR_NS_ACCORDING_RCV_TRANS BIT14 ++#define PCR_MASTER_PCIX_REQ64N_EN BIT15 ++#define PCR_SLAVE_BYTE_SWAP_EN BIT16 ++#define PCR_MASTER_DAC_EN BIT17 ++#define PCR_MASTER_M64_ALLIGN BIT18 ++#define PCR_ERRORS_PROPAGATION_EN BIT19 ++#define PCR_SLAVE_SWAP_ENABLE BIT20 ++#define PCR_MASTER_SWAP_ENABLE BIT21 ++#define PCR_MASTER_INT_SWAP_EN BIT22 ++#define PCR_LOOP_BACK_ENABLE BIT23 ++#define PCR_SLAVE_INTREG_SWAP_OFFS 24 ++#define PCR_SLAVE_INTREG_SWAP_MASK 0x3 ++#define PCR_SLAVE_INTREG_BYTE_SWAP \ ++ (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_SLAVE_INTREG_NO_SWAP \ ++ (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_SLAVE_INTREG_BYTE_WORD \ ++ (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_SLAVE_INTREG_WORD_SWAP \ ++ (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_RESET_REASSERTION_EN BIT26 ++#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 ++#define PCR_CPU_TO_PCI_ORDER_EN BIT29 ++#define PCR_PCI_TO_CPU_ORDER_EN BIT30 ++ ++/* PCI Mode Register (PMR) */ ++#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ ++#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) ++#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) ++ ++#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ ++#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) ++#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) ++#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) ++ ++#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ ++#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) ++ ++#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ ++ ++#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ ++#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) ++#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) ++ ++ ++/* PCI Retry Register (PRR) */ ++#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ ++#define PRR_RETRY_CNTR_MAX 0xff ++#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) ++ ++ ++/* PCI Discard Timer Register (PDTR) */ ++#define PDTR_TIMER_OFFS 0 /* Timer */ ++#define PDTR_TIMER_MAX 0xffff ++#define PDTR_TIMER_MIN 0x7F ++#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) ++ ++ ++/* PCI Arbiter Control Register (PACR) */ ++#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ ++ ++#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ ++#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) ++#define PACR_BROKEN_VAL_CONV_MIN 0x2 ++#define PACR_BROKEN_VAL_PCIX_MIN 0x6 ++ ++#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ ++#define PACR_PARK_DIS_MAX_AGENT 0x3f ++#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<= MV_PCI_START_IF)&&(pciIf < MV_PCI_MAX_IF + MV_PCI_START_IF)) ++ { ++ return PCI_IF_TYPE_CONVEN_PCIX; ++ } ++ else if ((pciIf >= MV_PEX_START_IF) && ++ (pciIf < MV_PEX_MAX_IF + MV_PEX_START_IF)) ++ { ++ return PCI_IF_TYPE_PEX; ++ ++ } ++ else ++ { ++ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); ++ } ++ ++ return 0xffffffff; ++ ++} ++ ++/******************************************************************************* ++* mvPciIfTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++ ++MV_U32 mvPciRealIfNumGet(MV_U32 pciIf) ++{ ++ ++ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); ++ ++ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) ++ { ++ return (pciIf - MV_PCI_START_IF); ++ } ++ else if (PCI_IF_TYPE_PEX == pciIfType) ++ { ++ return (pciIf - MV_PEX_START_IF); ++ ++ } ++ else ++ { ++ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); ++ } ++ ++ return 0xffffffff; ++ ++} ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,134 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPCIIFH ++#define __INCPCIIFH ++ ++#include "mvSysHwConfig.h" ++#include "pci-if/mvPciIfRegs.h" ++#if defined(MV_INCLUDE_PEX) ++#include "pex/mvPex.h" ++#endif ++#if defined(MV_INCLUDE_PCI) ++#include "pci/mvPci.h" ++#endif ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++typedef enum _mvPCIIfType ++{ ++ PCI_IF_TYPE_CONVEN_PCIX, ++ PCI_IF_TYPE_PEX ++ ++}PCI_IF_TYPE; ++ ++typedef enum _mvPCIIfMode ++{ ++ PCI_IF_MODE_HOST, ++ PCI_IF_MODE_DEVICE ++}PCI_IF_MODE; ++ ++ ++/* Global Functions prototypes */ ++ ++/* mvPciIfInit - Initialize PCI interfaces*/ ++MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode); ++ ++/* mvPciIfConfigRead - Read from configuration space */ ++MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPciIfConfigWrite - Write to configuration space */ ++MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/ ++MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable); ++ ++/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/ ++MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, ++ MV_BOOL enable); ++ ++/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/ ++MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); ++ ++/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/ ++MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf); ++ ++/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/ ++MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); ++ ++/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/ ++MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf); ++ ++/* mvPciIfTypeGet - Get PCI If type*/ ++PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf); ++ ++MV_U32 mvPciRealIfNumGet(MV_U32 pciIf); ++ ++/* mvPciIfAddrDecShow - Display address decode windows attributes */ ++MV_VOID mvPciIfAddrDecShow(MV_VOID); ++ ++#endif /* #ifndef __INCPCIIFH */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,245 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPCIIFREGSH ++#define __INCPCIIFREGSH ++ ++ ++/* defines */ ++#define MAX_PCI_DEVICES 32 ++#define MAX_PCI_FUNCS 8 ++#define MAX_PCI_BUSSES 128 ++ ++/***************************************/ ++/* PCI Configuration registers */ ++/***************************************/ ++ ++/*********************************************/ ++/* PCI Configuration, Function 0, Registers */ ++/*********************************************/ ++ ++ ++/* Standard registers */ ++#define PCI_DEVICE_AND_VENDOR_ID 0x000 ++#define PCI_STATUS_AND_COMMAND 0x004 ++#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 ++#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C ++#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) ++#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C ++#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 ++#define PCI_CAPABILTY_LIST_POINTER 0x034 ++#define PCI_INTERRUPT_PIN_AND_LINE 0x03C ++ ++ ++/* PCI Device and Vendor ID Register (PDVIR) */ ++#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */ ++#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS) ++ ++#define PDVIR_DEV_ID_OFFS 16 /* Device ID */ ++#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS) ++ ++/* PCI Status and Command Register (PSCR) */ ++#define PSCR_IO_EN BIT0 /* IO Enable */ ++#define PSCR_MEM_EN BIT1 /* Memory Enable */ ++#define PSCR_MASTER_EN BIT2 /* Master Enable */ ++#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */ ++#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */ ++#define PSCR_VGA BIT5 /* VGA Palette Snoops */ ++#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */ ++#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En)*/ ++#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */ ++#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions*/ ++#define PSCR_CAP_LIST BIT20 /* Capability List Support */ ++#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */ ++#define PSCR_UDF_EN BIT22 /* User definable features */ ++#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */ ++#define PSCR_DATA_PERR BIT24 /* Data Parity reported */ ++ ++#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */ ++#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS) ++#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS) ++#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS) ++#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS) ++ ++#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */ ++#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */ ++#define PSCR_MABORT BIT29 /* Recieved Master Abort */ ++#define PSCR_SYSERR BIT30 /* Signalled system error */ ++#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */ ++ ++/* PCI configuration register offset=0x08 fields ++ (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */ ++ ++#define PCCRIR_REVID_OFFS 0 /* Revision ID */ ++#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) ++ ++#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */ ++#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS) ++ ++#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F*/ ++#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS) ++ ++#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class*/ ++#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS) ++ ++#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class*/ ++#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS) ++ ++/* PCI configuration register offset=0x0C fields ++ (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */ ++ ++#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */ ++#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS) ++ ++#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */ ++#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS) ++ ++#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ ++#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS) ++ ++#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */ ++ ++#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */ ++#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS) ++#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS) ++#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS) ++ ++ ++#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */ ++#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS) ++ ++#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */ ++#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */ ++ ++ ++/* PCI Bar Base Low Register (PBBLR) */ ++#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */ ++ ++#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */ ++#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS) ++#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS) ++#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS) ++ ++#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */ ++ ++ ++#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to ++ address bits [31:4] */ ++#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS) ++ ++#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to ++ address bits [31:2] */ ++#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS) ++ ++ ++#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */ ++#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS) ++#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS) ++ ++ ++/* PCI Bar Base High Fegister (PBBHR) */ ++#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */ ++#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) ++ ++ ++/* PCI configuration register offset=0x2C fields ++ (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */ ++ ++#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ ++#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS) ++ ++#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */ ++#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS) ++ ++/* PCI configuration register offset=0x30 fields ++ (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */ ++ ++#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ ++ ++#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */ ++#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS) ++ ++/* PCI configuration register offset=0x34 fields ++ (PCI_CAPABILTY_LIST_POINTER)(PCLP) */ ++ ++#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */ ++#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS) ++ ++/* PCI configuration register offset=0x3C fields ++ (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */ ++ ++#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ ++#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS) ++ ++#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ ++#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS) ++ ++#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */ ++#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS) ++ ++#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */ ++#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS) ++ ++#endif /* #ifndef __INCPCIIFREGSH */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1006 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/* includes */ ++#include "mvPciUtils.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* #define MV_DEBUG */ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++ #define mvOsPrintf printf ++#else ++ #define DB(x) ++#endif ++ ++/* ++This module only support scanning of Header type 00h of pci devices ++There is no suppotr for Header type 01h of pci devices ( PCI bridges ) ++*/ ++ ++ ++static MV_STATUS pciDetectDevice(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent); ++ ++static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent); ++ ++ ++ ++ ++ ++ ++/******************************************************************************* ++* mvPciScan - Scan a PCI interface bus ++* ++* DESCRIPTION: ++* Performs a full scan on a PCI interface and returns all possible details ++* on the agents found on the bus. ++* ++* INPUT: ++* pciIf - PCI Interface ++* pPciAgents - Pointer to an Array of the pci agents to be detected ++* pPciAgentsNum - pPciAgents array maximum number of elements ++* ++* OUTPUT: ++* pPciAgents - Array of the pci agents detected on the bus ++* pPciAgentsNum - Number of pci agents detected on the bus ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++MV_STATUS mvPciScan(MV_U32 pciIf, ++ MV_PCI_DEVICE *pPciAgents, ++ MV_U32 *pPciAgentsNum) ++{ ++ ++ MV_U32 devIndex,funcIndex=0,busIndex=0,detectedDevNum=0; ++ MV_U32 localBus=mvPciIfLocalBusNumGet(pciIf); ++ MV_PCI_DEVICE *pPciDevice; ++ MV_PCI_DEVICE *pMainDevice; ++ ++ DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf)); ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPexMaxIfGet()) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf)); ++ return MV_BAD_PARAM; ++ } ++ if (NULL == pPciAgents) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n")); ++ return MV_BAD_PARAM; ++ } ++ if (NULL == pPciAgentsNum) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf)); ++ /* Master enable the MV PCI master */ ++ if (MV_OK != mvPciIfMasterEnable(pciIf,MV_TRUE)) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n")); ++ return MV_ERROR; ++ ++ } ++ ++ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf)); ++ ++ /* go through all busses */ ++ for (busIndex=localBus ; busIndex < MAX_PCI_BUSSES ; busIndex++) ++ { ++ /* go through all possible devices on the local bus */ ++ for (devIndex=0 ; devIndex < MAX_PCI_DEVICES ; devIndex++) ++ { ++ /* always start with function equal to zero */ ++ funcIndex=0; ++ ++ pPciDevice=&pPciAgents[detectedDevNum]; ++ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex)); ++ ++ if (MV_ERROR == pciDetectDevice(pciIf, ++ busIndex, ++ devIndex, ++ funcIndex, ++ pPciDevice)) ++ { ++ /* no device detected , try the next address */ ++ continue; ++ } ++ ++ /* We are here ! means we have detected a device*/ ++ /* always we start with only one function per device */ ++ pMainDevice = pPciDevice; ++ pPciDevice->funtionsNum = 1; ++ ++ ++ /* move on */ ++ detectedDevNum++; ++ ++ ++ /* check if we have no more room for a new device */ ++ if (detectedDevNum == *pPciAgentsNum) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n")); ++ return MV_ERROR; ++ } ++ ++ /* check the detected device if it is a multi functional device then ++ scan all device functions*/ ++ if (pPciDevice->isMultiFunction == MV_TRUE) ++ { ++ /* start with function number 1 because we have already detected ++ function 0 */ ++ for (funcIndex=1; funcIndexfuntionsNum++; ++ detectedDevNum++; ++ ++ /* check if we have no more room for a new device */ ++ if (detectedDevNum == *pPciAgentsNum) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. Array too small\n")); ++ return MV_ERROR; ++ } ++ ++ ++ } ++ } ++ ++ } ++ ++ } ++ ++ /* return the number of devices actually detected on the bus ! */ ++ *pPciAgentsNum = detectedDevNum; ++ ++ return MV_OK; ++ ++} ++ ++ ++/******************************************************************************* ++* pciDetectDevice - Detect a pci device parameters ++* ++* DESCRIPTION: ++* This function detect if a pci agent exist on certain address ! ++* and if exists then it fills all possible information on the ++* agent ++* ++* INPUT: ++* pciIf - PCI Interface ++* bus - Bus number ++* dev - Device number ++* func - Function number ++* ++* ++* ++* OUTPUT: ++* pPciAgent - pointer to the pci agent filled with its information ++* ++* RETURN: ++* MV_ERROR if no device , MV_OK otherwise ++* ++*******************************************************************************/ ++ ++static MV_STATUS pciDetectDevice(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent) ++{ ++ MV_U32 pciData; ++ ++ /* no Parameters checking ! because it is static function and it is assumed ++ that all parameters were checked in the calling function */ ++ ++ ++ /* Try read the PCI Vendor ID and Device ID */ ++ ++ /* We will scan only ourselves and the PCI slots that exist on the ++ board, because we may have a case that we have one slot that has ++ a Cardbus connector, and because CardBus answers all IDsels we want ++ to scan only this slot and ourseleves. ++ ++ */ ++ #if defined(MV_INCLUDE_PCI) ++ if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) && ++ (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && ++ (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) && ++ (DB_88F5181_DDR1_MNG != mvBoardIdGet())) ++ { ++ ++ if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE) ++ { ++ return MV_ERROR; ++ } ++ } ++ #endif /* defined(MV_INCLUDE_PCI) */ ++ ++ pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID); ++ ++ if (PCI_ERROR_CODE == pciData) ++ { ++ /* no device exist */ ++ return MV_ERROR; ++ } ++ ++ /* we are here ! means a device is detected */ ++ ++ /* fill basic information */ ++ pPciAgent->busNumber=bus; ++ pPciAgent->deviceNum=dev; ++ pPciAgent->function=func; ++ ++ /* Fill the PCI Vendor ID and Device ID */ ++ ++ pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS; ++ pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS; ++ ++ /* Read Status and command */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_STATUS_AND_COMMAND); ++ ++ ++ /* Fill related Status and Command information*/ ++ ++ if (pciData & PSCR_TAR_FAST_BB) ++ { ++ pPciAgent->isFastB2BCapable = MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isFastB2BCapable = MV_FALSE; ++ } ++ ++ if (pciData & PSCR_CAP_LIST) ++ { ++ pPciAgent->isCapListSupport=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isCapListSupport=MV_FALSE; ++ } ++ ++ if (pciData & PSCR_66MHZ_EN) ++ { ++ pPciAgent->is66MHZCapable=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->is66MHZCapable=MV_FALSE; ++ } ++ ++ /* Read Class Code and Revision */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_CLASS_CODE_AND_REVISION_ID); ++ ++ ++ pPciAgent->baseClassCode = ++ (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; ++ ++ pPciAgent->subClassCode = ++ (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; ++ ++ pPciAgent->progIf = ++ (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS; ++ ++ pPciAgent->revisionID = ++ (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; ++ ++ /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE); ++ ++ ++ ++ pPciAgent->pciCacheLine= ++ (pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS; ++ pPciAgent->pciLatencyTimer= ++ (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS; ++ ++ switch (pciData & PBHTLTCLR_HEADER_MASK) ++ { ++ case PBHTLTCLR_HEADER_STANDARD: ++ ++ pPciAgent->pciHeader=MV_PCI_STANDARD; ++ break; ++ case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE: ++ ++ pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE; ++ break; ++ ++ } ++ ++ if (pciData & PBHTLTCLR_MULTI_FUNC) ++ { ++ pPciAgent->isMultiFunction=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isMultiFunction=MV_FALSE; ++ } ++ ++ if (pciData & PBHTLTCLR_BISTCAP) ++ { ++ pPciAgent->isBISTCapable=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isBISTCapable=MV_FALSE; ++ } ++ ++ ++ /* read this device pci bars */ ++ ++ pciDetectDeviceBars(pciIf, ++ bus,dev,func, ++ pPciAgent); ++ ++ ++ /* check if we are bridge*/ ++ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& ++ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) ++ { ++ ++ /* Read P2P_BUSSES_NUM */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_BUSSES_NUM); ++ ++ pPciAgent->p2pPrimBusNum = ++ (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS; ++ ++ pPciAgent->p2pSecBusNum = ++ (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS; ++ ++ pPciAgent->p2pSubBusNum = ++ (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS; ++ ++ pPciAgent->p2pSecLatencyTimer = ++ (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS; ++ ++ /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_IO_BASE_LIMIT_SEC_STATUS); ++ ++ pPciAgent->p2pSecStatus = ++ (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS; ++ ++ ++ pPciAgent->p2pIObase = ++ (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS; ++ ++ /* clear low address (should be zero)*/ ++ pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK; ++ ++ pPciAgent->p2pIOLimit = ++ (pciData & PIBLSS_IO_LIMIT_MASK); ++ ++ /* fill low address with 0xfff */ ++ pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK; ++ ++ ++ switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS) ++ { ++ case PIBLSS_ADD_CAP_16BIT: ++ ++ pPciAgent->bIO32 = MV_FALSE; ++ ++ break; ++ case PIBLSS_ADD_CAP_32BIT: ++ ++ pPciAgent->bIO32 = MV_TRUE; ++ ++ /* Read P2P_IO_BASE_LIMIT_UPPER_16 */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_IO_BASE_LIMIT_UPPER_16); ++ ++ pPciAgent->p2pIObase |= ++ (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS; ++ ++ ++ pPciAgent->p2pIOLimit |= ++ (pciData & PRBU_IO_UPP_LIMIT_MASK); ++ ++ break; ++ ++ } ++ ++ ++ /* Read P2P_MEM_BASE_LIMIT */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_MEM_BASE_LIMIT); ++ ++ pPciAgent->p2pMemBase = ++ (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS; ++ ++ /* clear low address */ ++ pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK; ++ ++ pPciAgent->p2pMemLimit = ++ (pciData & PMBL_MEM_LIMIT_MASK); ++ ++ /* add 0xfffff */ ++ pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK; ++ ++ ++ /* Read P2P_PREF_MEM_BASE_LIMIT */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_PREF_MEM_BASE_LIMIT); ++ ++ ++ pPciAgent->p2pPrefMemBase = ++ (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS; ++ ++ /* get high address only */ ++ pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK; ++ ++ ++ ++ pPciAgent->p2pPrefMemLimit = ++ (pciData & PRMBL_PREF_MEM_LIMIT_MASK); ++ ++ /* add 0xfffff */ ++ pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK; ++ ++ switch (pciData & PRMBL_ADD_CAP_MASK) ++ { ++ case PRMBL_ADD_CAP_32BIT: ++ ++ pPciAgent->bPrefMem64 = MV_FALSE; ++ ++ /* Read P2P_PREF_BASE_UPPER_32 */ ++ pPciAgent->p2pPrefBaseUpper32Bits = 0; ++ ++ /* Read P2P_PREF_LIMIT_UPPER_32 */ ++ pPciAgent->p2pPrefLimitUpper32Bits = 0; ++ ++ break; ++ case PRMBL_ADD_CAP_64BIT: ++ ++ pPciAgent->bPrefMem64 = MV_TRUE; ++ ++ /* Read P2P_PREF_BASE_UPPER_32 */ ++ pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_PREF_BASE_UPPER_32); ++ ++ /* Read P2P_PREF_LIMIT_UPPER_32 */ ++ pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_PREF_LIMIT_UPPER_32); ++ ++ break; ++ ++ } ++ ++ } ++ else /* no bridge */ ++ { ++ /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID); ++ ++ ++ pPciAgent->subSysVenID = ++ (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS; ++ pPciAgent->subSysID = ++ (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS; ++ ++ ++ /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_EXPANSION_ROM_BASE_ADDR_REG); ++ ++ ++ if (pciData & PERBAR_EXPROMEN) ++ { ++ pPciAgent->isExpRom = MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isExpRom = MV_FALSE; ++ } ++ ++ pPciAgent->expRomAddr = ++ (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS; ++ ++ } ++ ++ ++ if (MV_TRUE == pPciAgent->isCapListSupport) ++ { ++ /* Read PCI_CAPABILTY_LIST_POINTER */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_CAPABILTY_LIST_POINTER); ++ ++ pPciAgent->capListPointer = ++ (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS; ++ ++ } ++ ++ /* Read PCI_INTERRUPT_PIN_AND_LINE */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_INTERRUPT_PIN_AND_LINE); ++ ++ ++ pPciAgent->irqLine= ++ (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS; ++ ++ pPciAgent->intPin= ++ (MV_PCI_INT_PIN)(pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS; ++ ++ pPciAgent->minGrant= ++ (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS; ++ pPciAgent->maxLatency= ++ (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS; ++ ++ mvPciClassNameGet(pPciAgent->baseClassCode, ++ (MV_8 *)pPciAgent->type); ++ ++ return MV_OK; ++ ++ ++} ++ ++/******************************************************************************* ++* pciDetectDeviceBars - Detect a pci device bars ++* ++* DESCRIPTION: ++* This function detects all pci agent bars ++* ++* INPUT: ++* pciIf - PCI Interface ++* bus - Bus number ++* dev - Device number ++* func - Function number ++* ++* ++* ++* OUTPUT: ++* pPciAgent - pointer to the pci agent filled with its information ++* ++* RETURN: ++* detected bars number ++* ++*******************************************************************************/ ++static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent) ++{ ++ MV_U32 pciData,barIndex,detectedBar=0; ++ MV_U32 tmpBaseHigh=0,tmpBaseLow=0; ++ MV_U32 pciMaxBars=0; ++ ++ pPciAgent->barsNum=0; ++ ++ /* check if we are bridge*/ ++ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& ++ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) ++ { ++ pciMaxBars = 2; ++ } ++ else /* no bridge */ ++ { ++ pciMaxBars = 6; ++ } ++ ++ /* read this device pci bars */ ++ for (barIndex = 0 ; barIndex < pciMaxBars ; barIndex++ ) ++ { ++ /* Read PCI_MEMORY_BAR_BASE_ADDR */ ++ tmpBaseLow = pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ pPciAgent->pciBar[detectedBar].barOffset = ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex); ++ ++ /* check if the bar is 32bit or 64bit bar */ ++ switch (pciData & PBBLR_TYPE_MASK) ++ { ++ case PBBLR_TYPE_32BIT_ADDR: ++ pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR; ++ break; ++ case PBBLR_TYPE_64BIT_ADDR: ++ pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR; ++ break; ++ ++ } ++ ++ /* check if it is memory or IO bar */ ++ if (pciData & PBBLR_IOSPACE) ++ { ++ pPciAgent->pciBar[detectedBar].barMapping=PCI_IO_BAR; ++ } ++ else ++ { ++ pPciAgent->pciBar[detectedBar].barMapping=PCI_MEMORY_BAR; ++ } ++ ++ /* if it is memory bar then check if it is prefetchable */ ++ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) ++ { ++ if (pciData & PBBLR_PREFETCH_EN) ++ { ++ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE; ++ } ++ ++ pPciAgent->pciBar[detectedBar].barBaseLow = ++ pciData & PBBLR_MEM_BASE_MASK; ++ ++ ++ } ++ else /* IO Bar */ ++ { ++ pPciAgent->pciBar[detectedBar].barBaseLow = ++ pciData & PBBLR_IO_BASE_MASK; ++ ++ } ++ ++ pPciAgent->pciBar[detectedBar].barBaseHigh=0; ++ ++ if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) ++ { ++ barIndex++; ++ ++ tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ ++ } ++ ++ /* calculating full base address (64bit) */ ++ pPciAgent->pciBar[detectedBar].barBaseAddr = ++ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseHigh; ++ ++ pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32; ++ ++ pPciAgent->pciBar[detectedBar].barBaseAddr |= ++ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseLow; ++ ++ ++ ++ /* get the sizes of the the bar */ ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh=0; ++ ++ if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) && ++ (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)) ++ ++ { ++ /* write oxffffffff to the bar to get the size */ ++ /* start with sizelow ( original value was saved in tmpBaseLow ) */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), ++ 0xffffffff); ++ ++ /* read size */ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1)); ++ ++ ++ ++ /* restore original value */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), ++ tmpBaseLow); ++ ++ ++ /* now do the same for BaseHigh */ ++ ++ /* write oxffffffff to the bar to get the size */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ 0xffffffff); ++ ++ /* read size */ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ /* restore original value */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ tmpBaseHigh); ++ ++ if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow)&& ++ (0 == pPciAgent->pciBar[detectedBar].barSizeHigh)) ++ { ++ /* this bar is not applicable for this device, ++ ignore all previous settings and check the next bar*/ ++ ++ /* we though this was a 64bit bar , and it seems this ++ was wrong ! so decrement barIndex */ ++ barIndex--; ++ continue; ++ } ++ ++ /* calculate the full 64 bit size */ ++ ++ if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh) ++ { ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; ++ ++ } ++ else ++ { ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; ++ ++ } ++ ++ ++ ++ } ++ else /* 32bit bar */ ++ { ++ /* write oxffffffff to the bar to get the size */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ 0xffffffff); ++ ++ /* read size */ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ if (0 == pPciAgent->pciBar[detectedBar].barSizeLow) ++ { ++ /* this bar is not applicable for this device, ++ ignore all previous settings and check the next bar*/ ++ continue; ++ } ++ ++ ++ /* restore original value */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ tmpBaseLow); ++ ++ /* calculate size low */ ++ ++ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) ++ { ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; ++ } ++ else ++ { ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK; ++ } ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; ++ pPciAgent->pciBar[detectedBar].barSize = ++ (MV_U64)pPciAgent->pciBar[detectedBar].barSizeLow; ++ ++ ++ } ++ ++ /* we are here ! this means we have already detected a bar for ++ this device , now move on */ ++ ++ detectedBar++; ++ pPciAgent->barsNum++; ++ } ++ ++ return detectedBar; ++} ++ ++ ++/******************************************************************************* ++* mvPciClassNameGet - get PCI class name ++* ++* DESCRIPTION: ++* This function returns the PCI class name ++* ++* INPUT: ++* baseClassCode - Base Class Code. ++* ++* OUTPUT: ++* pType - the class name ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType) ++{ ++ ++ switch(baseClassCode) ++ { ++ case 0x0: ++ strcpy(pType,"Old generation device"); ++ break; ++ case 0x1: ++ strcpy(pType,"Mass storage controller"); ++ break; ++ case 0x2: ++ strcpy(pType,"Network controller"); ++ break; ++ case 0x3: ++ strcpy(pType,"Display controller"); ++ break; ++ case 0x4: ++ strcpy(pType,"Multimedia device"); ++ break; ++ case 0x5: ++ strcpy(pType,"Memory controller"); ++ break; ++ case 0x6: ++ strcpy(pType,"Bridge Device"); ++ break; ++ case 0x7: ++ strcpy(pType,"Simple Communication controllers"); ++ break; ++ case 0x8: ++ strcpy(pType,"Base system peripherals"); ++ break; ++ case 0x9: ++ strcpy(pType,"Input Devices"); ++ break; ++ case 0xa: ++ strcpy(pType,"Docking stations"); ++ break; ++ case 0xb: ++ strcpy(pType,"Processors"); ++ break; ++ case 0xc: ++ strcpy(pType,"Serial bus controllers"); ++ break; ++ case 0xd: ++ strcpy(pType,"Wireless controllers"); ++ break; ++ case 0xe: ++ strcpy(pType,"Intelligent I/O controllers"); ++ break; ++ case 0xf: ++ strcpy(pType,"Satellite communication controllers"); ++ break; ++ case 0x10: ++ strcpy(pType,"Encryption/Decryption controllers"); ++ break; ++ case 0x11: ++ strcpy(pType,"Data acquisition and signal processing controllers"); ++ break; ++ default: ++ strcpy(pType,"Unknown device"); ++ break; ++ } ++ ++ return MV_OK; ++ ++} ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,323 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvPciUtilsh ++#define __INCmvPciUtilsh ++ ++/* ++This module only support scanning of Header type 00h of pci devices ++There is no suppotr for Header type 01h of pci devices ( PCI bridges ) ++*/ ++ ++/* includes */ ++#include "mvSysHwConfig.h" ++#include "pci-if/mvPciIf.h" ++#include "pci/mvPciRegs.h" ++ ++ ++ ++/* PCI base address low bar mask */ ++#define PCI_ERROR_CODE 0xffffffff ++ ++#define PCI_BRIDGE_CLASS 0x6 ++#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 ++ ++ ++#define P2P_BUSSES_NUM 0x18 ++#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C ++#define P2P_MEM_BASE_LIMIT 0x20 ++#define P2P_PREF_MEM_BASE_LIMIT 0x24 ++#define P2P_PREF_BASE_UPPER_32 0x28 ++#define P2P_PREF_LIMIT_UPPER_32 0x2C ++#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 ++#define P2P_EXP_ROM 0x38 ++ ++/* P2P_BUSSES_NUM (PBM) */ ++ ++#define PBM_PRIME_BUS_NUM_OFFS 0 ++#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) ++ ++#define PBM_SEC_BUS_NUM_OFFS 8 ++#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) ++ ++#define PBM_SUB_BUS_NUM_OFFS 16 ++#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) ++ ++#define PBM_SEC_LAT_TMR_OFFS 24 ++#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) ++ ++/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ ++ ++#define PIBLSS_IO_BASE_OFFS 0 ++#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) ++ ++#define PIBLSS_ADD_CAP_OFFS 0 ++#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) ++#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) ++#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) ++ ++#define PIBLSS_LOW_ADDR_OFFS 0 ++#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) ++ ++#define PIBLSS_HIGH_ADDR_OFFS 12 ++#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) ++ ++#define PIBLSS_IO_LIMIT_OFFS 8 ++#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) ++ ++#define PIBLSS_SEC_STATUS_OFFS 16 ++#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) ++ ++ ++/* P2P_MEM_BASE_LIMIT (PMBL)*/ ++ ++#define PMBL_MEM_BASE_OFFS 0 ++#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) ++ ++#define PMBL_MEM_LIMIT_OFFS 16 ++#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) ++ ++ ++#define PMBL_LOW_ADDR_OFFS 0 ++#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) ++ ++#define PMBL_HIGH_ADDR_OFFS 20 ++#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) ++ ++ ++/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ ++ ++#define PRMBL_PREF_MEM_BASE_OFFS 0 ++#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) ++ ++#define PRMBL_PREF_MEM_LIMIT_OFFS 16 ++#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf); ++ return MV_ERROR; ++ } ++ } ++ ++ pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); ++ ++ switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) ++ { ++ case PXCR_DEV_TYPE_CTRL_CMPLX: ++ pexMode->pexType = MV_PEX_ROOT_COMPLEX; ++ break; ++ case PXCR_DEV_TYPE_CTRL_POINT: ++ pexMode->pexType = MV_PEX_END_POINT; ++ break; ++ ++ } ++ ++ /* Check if we have link */ ++ if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) ++ { ++ pexMode->pexLinkUp = MV_FALSE; ++ ++ /* If there is no link, the auto negotiation data is worthless */ ++ pexMode->pexWidth = MV_PEX_WITDH_INVALID; ++ } ++ else ++ { ++ pexMode->pexLinkUp = MV_TRUE; ++ ++ /* We have link. The link width is now valid */ ++ pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); ++ pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> ++ PXLCSR_NEG_LNK_WDTH_OFFS); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/* PEX configuration space read write */ ++ ++/******************************************************************************* ++* mvPexConfigRead - Read from configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit read from PEX configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to read from local bus segment, use ++* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bus - PEX segment bus number. ++* dev - PEX device number. ++* func - Function number. ++* regOffs - Register offset. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit register data, 0xffffffff on error ++* ++*******************************************************************************/ ++MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) ++ return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff); ++} ++ ++MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++#endif ++ MV_U32 pexData = 0; ++ MV_U32 localDev,localBus; ++ ++ /* Parameter checking */ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ if (dev >= MAX_PEX_DEVICES) ++ { ++ DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (func >= MAX_PEX_FUNCS) ++ { ++ DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (bus >= MAX_PEX_BUSSES) ++ { ++ DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); ++ return MV_ERROR; ++ } ++ ++ DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", ++ pexIf, bus, dev, func, regOff)); ++ ++ localDev = mvPexLocalDevNumGet(pexIf); ++ localBus = mvPexLocalBusNumGet(pexIf); ++ ++ /* Speed up the process. In case on no link, return MV_ERROR */ ++ if ((dev != localDev) || (bus != localBus)) ++ { ++ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ if ((pexData & PXSR_DL_DOWN)) ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ /* in PCI Express we have only one device number */ ++ /* and this number is the first number we encounter ++ else that the localDev*/ ++ /* spec pex define return on config read/write on any device */ ++ if (bus == localBus) ++ { ++ if (localDev == 0) ++ { ++ /* if local dev is 0 then the first number we encounter ++ after 0 is 1 */ ++ if ((dev != 1)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ /* if local dev is not 0 then the first number we encounter ++ is 0 */ ++ ++ if ((dev != 0)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ } ++ if(func != 0 ) /* i.e bridge */ ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ ++ /* Creating PEX address to be passed */ ++ pexData = (bus << PXCAR_BUS_NUM_OFFS); ++ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); ++ pexData |= (func << PXCAR_FUNC_NUM_OFFS); ++ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ ++ /* extended register space */ ++ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> ++ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); ++ ++ pexData |= PXCAR_CONFIG_EN; ++ ++ /* Write the address to the PEX configuration address register */ ++ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); ++ ++ DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData)); ++ ++ ++ /* In order to let the PEX controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) ++ { ++ return MV_ERROR; ++ } ++ ++ /* cleaning Master Abort */ ++ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), ++ PXSAC_MABORT); ++#if 0 ++ /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ ++ /* This guideline is relevant for all devices except of the following devices: ++ 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above ++ 88F6183 A0 and above, 88F6183L */ ++ if ( ( (dev != localDev) || (bus != localBus) ) && ++ ( ++ !(MV_5281_DEV_ID == mvCtrlModelGet())&& ++ !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&& ++ !(MV_1281_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6183_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6183L_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6281_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6192_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6190_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6180_DEV_ID == mvCtrlModelGet())&& ++ !(MV_78XX0_DEV_ID == mvCtrlModelGet()) ++ )) ++ { ++ ++ /* PCI-Express configuration read work-around */ ++ ++ /* we will use one of the Punit (AHBToMbus) windows to access the xbar ++ and read the data from there */ ++ /* ++ Need to configure the 2 free Punit (AHB to MBus bridge) ++ address decoding windows: ++ Configure the flash Window to handle Configuration space requests ++ for PEX0/1: ++ 1. write 0x7931/0x7941 to the flash window and the size, ++ 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn ++ 2. write base to flash window ++ ++ Configuration transactions from the CPU should write/read the data ++ to/from address of the form: ++ addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) ++ addr[27:24] = extended register number ++ addr[23:16] = bus number ++ addr[15:11] = device number ++ addr[10:8] = function number ++ addr[7:0] = register number ++ */ ++ ++ #include "ctrlEnv/sys/mvAhbToMbus.h" ++ { ++ MV_U32 winNum; ++ MV_AHB_TO_MBUS_DEC_WIN originWin; ++ MV_U32 pciAddr=0; ++ MV_U32 remapLow=0,remapHigh=0; ++ ++ /* ++ We will use DEV_CS2\Flash window for this workarround ++ */ ++ ++ winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); ++ ++ /* save remap values if exist */ ++ if ((1 == winNum)||(0 == winNum)) ++ { ++ remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); ++ remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); ++ ++ } ++ ++ ++ /* save the original window values */ ++ mvAhbToMbusWinGet(winNum,&originWin); ++ ++ if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) ++ { ++ /* set the window as xbar window */ ++ if (pexIf) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16)); ++ } ++ else ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16)); ++ } ++ ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), ++ originWin.addrWin.baseLow); ++ ++ /*pciAddr = originWin.addrWin.baseLow;*/ ++ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR( ++ (MV_U32)originWin.addrWin.baseLow); ++ ++ } ++ else ++ { ++ /* set the window as xbar window */ ++ if (pexIf) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); ++ } ++ else ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); ++ } ++ ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), ++ PEX_CONFIG_RW_WA_BASE); ++ ++ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); ++ } ++ ++ ++ /* remap should be as base */ ++ if ((1 == winNum)||(0 == winNum)) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr); ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0); ++ ++ } ++ ++ /* extended register space */ ++ pciAddr |= (bus << 16); ++ pciAddr |= (dev << 11); ++ pciAddr |= (func << 8); ++ pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ ++ ++ pexData = *(MV_U32*)pciAddr; ++ pexData = MV_32BIT_LE(pexData); /* Data always in LE */ ++ ++ /* restore the original window values */ ++ mvAhbToMbusWinSet(winNum,&originWin); ++ ++ /* restore original remap values*/ ++ if ((1 == winNum)||(0 == winNum)) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow); ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh); ++ ++ } ++ } ++ } ++ else ++#endif ++ { ++ /* Read the Data returned in the PEX Data register */ ++ pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); ++ ++ } ++ ++ DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData)); ++ ++ return pexData; ++ ++} ++ ++/******************************************************************************* ++* mvPexConfigWrite - Write to configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit write to PEX configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to write to local bus segment, use ++* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bus - PEX segment bus number. ++* dev - PEX device number. ++* func - Function number. ++* regOffs - Register offset. ++* data - 32bit data. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) ++ return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data); ++} ++ ++MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++#endif ++ MV_U32 pexData = 0; ++ MV_U32 localDev,localBus; ++ ++ /* Parameter checking */ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", ++ pexIf); ++ return MV_ERROR; ++ } ++ } ++ ++ if (dev >= MAX_PEX_DEVICES) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev); ++ return MV_BAD_PARAM; ++ } ++ ++ if (func >= MAX_PEX_FUNCS) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); ++ return MV_ERROR; ++ } ++ ++ if (bus >= MAX_PEX_BUSSES) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); ++ return MV_ERROR; ++ } ++ ++ ++ ++ localDev = mvPexLocalDevNumGet(pexIf); ++ localBus = mvPexLocalBusNumGet(pexIf); ++ ++ ++ /* in PCI Express we have only one device number other than ourselves*/ ++ /* and this number is the first number we encounter ++ else than the localDev that can be any valid dev number*/ ++ /* pex spec define return on config read/write on any device */ ++ if (bus == localBus) ++ { ++ ++ if (localDev == 0) ++ { ++ /* if local dev is 0 then the first number we encounter ++ after 0 is 1 */ ++ if ((dev != 1)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ /* if local dev is not 0 then the first number we encounter ++ is 0 */ ++ ++ if ((dev != 0)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ ++ } ++ ++ /* if we are not accessing ourselves , then check the link */ ++ if ((dev != localDev) || (bus != localBus) ) ++ { ++ /* workarround */ ++ /* when no link return MV_ERROR */ ++ ++ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ if ((pexData & PXSR_DL_DOWN)) ++ { ++ return MV_ERROR; ++ } ++ ++ } ++ ++ pexData =0; ++ ++ /* Creating PEX address to be passed */ ++ pexData |= (bus << PXCAR_BUS_NUM_OFFS); ++ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); ++ pexData |= (func << PXCAR_FUNC_NUM_OFFS); ++ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ ++ /* extended register space */ ++ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> ++ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); ++ pexData |= PXCAR_CONFIG_EN; ++ ++ DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", ++ pexIf,bus,func,dev,regOff,data,pexData) ); ++ ++ /* Write the address to the PEX configuration address register */ ++ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); ++ ++ /* Clear CPU pipe. Important where CPU can perform OOO execution */ ++ CPU_PIPE_FLUSH; ++ ++ /* In order to let the PEX controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) ++ { ++ return MV_ERROR; ++ } ++ ++ /* Write the Data passed to the PEX Data register */ ++ MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexMasterEnable - Enable/disale PEX interface master transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PEX command status ++* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX ++* master is allowed to gain ownership on the bus, otherwise it is ++* incapable to do so. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) ++{ ++ MV_U32 pexCommandStatus; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_ERROR; ++ } ++ ++ localBus = mvPexLocalBusNumGet(pexIf); ++ localDev = mvPexLocalDevNumGet(pexIf); ++ ++ pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, ++ PEX_STATUS_AND_COMMAND)); ++ ++ ++ if (MV_TRUE == enable) ++ { ++ pexCommandStatus |= PXSAC_MASTER_EN; ++ } ++ else ++ { ++ pexCommandStatus &= ~PXSAC_MASTER_EN; ++ } ++ ++ ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), ++ pexCommandStatus); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PEX command status ++* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, ++* the PEX slave is allowed to respond to PEX IO space access (bit 0) ++* and PEX memory space access (bit 1). ++* ++* INPUT: ++* pexIf - PEX interface number. ++* dev - PEX device number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable) ++{ ++ MV_U32 pexCommandStatus; ++ MV_U32 RegOffs; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (dev >= MAX_PEX_DEVICES) ++ { ++ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ ++ RegOffs = PEX_STATUS_AND_COMMAND; ++ ++ pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); ++ ++ if (MV_TRUE == enable) ++ { ++ pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); ++ } ++ else ++ { ++ pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); ++ } ++ ++ mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexLocalBusNumSet - Set PEX interface local bus number. ++* ++* DESCRIPTION: ++* This function sets given PEX interface its local bus number. ++* Note: In case the PEX interface is PEX-X, the information is read-only. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* busNum - Bus number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PEX interface is PEX-X. ++* MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) ++{ ++ MV_U32 pexStatus; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (busNum >= MAX_PEX_BUSSES) ++ { ++ mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); ++ return MV_ERROR; ++ ++ } ++ ++ localBus = mvPexLocalBusNumGet(pexIf); ++ localDev = mvPexLocalDevNumGet(pexIf); ++ ++ ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; ++ ++ pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; ++ ++ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexLocalBusNumGet - Get PEX interface local bus number. ++* ++* DESCRIPTION: ++* This function gets the local bus number of a given PEX interface. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local bus number.0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) ++{ ++ MV_U32 pexStatus; ++ ++ /* Parameter checking */ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= PXSR_PEX_BUS_NUM_MASK; ++ ++ return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); ++ ++} ++ ++ ++/******************************************************************************* ++* mvPexLocalDevNumSet - Set PEX interface local device number. ++* ++* DESCRIPTION: ++* This function sets given PEX interface its local device number. ++* Note: In case the PEX interface is PEX-X, the information is read-only. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* devNum - Device number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PEX interface is PEX-X. ++* MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) ++{ ++ MV_U32 pexStatus; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (devNum >= MAX_PEX_DEVICES) ++ { ++ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", ++ devNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ localBus = mvPexLocalBusNumGet(pexIf); ++ localDev = mvPexLocalDevNumGet(pexIf); ++ ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; ++ ++ pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; ++ ++ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); ++ ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPexLocalDevNumGet - Get PEX interface local device number. ++* ++* DESCRIPTION: ++* This function gets the local device number of a given PEX interface. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local device number. 0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) ++{ ++ MV_U32 pexStatus; ++ ++ /* Parameter checking */ ++ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", ++ pexIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= PXSR_PEX_DEV_NUM_MASK; ++ ++ return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); ++} ++ ++MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) ++{ ++ ++ MV_U32 regAddr; ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); ++ return; ++ } ++ regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); ++ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); ++ *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); ++} ++ ++ ++MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) ++{ ++ ++ MV_U32 regAddr; ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); ++ return; ++ } ++ regAddr = (((regOffset & 0x3fff) << 16) | value); ++ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); ++} ++ ++/******************************************************************************* ++* mvPexActiveStateLinkPMEnable ++* ++* DESCRIPTION: ++* Enable Active Link State Power Management ++* ++* INPUT: ++* pexIf - PEX interface number. ++* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_OK on success , MV_ERROR otherwise ++* ++*******************************************************************************/ ++MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) ++{ ++ MV_U32 reg; ++ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_ERROR; ++ } ++ ++ reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; ++ if(enable == MV_TRUE) ++ reg |= PXPMER_L1_ASPM_EN_MASK; ++ MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); ++ ++ /* Enable / Disable L0/1 entry */ ++ reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) ++ & ~PXLCSR_ASPM_CNT_MASK; ++ if(enable == MV_TRUE) ++ reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexForceX1 ++* ++* DESCRIPTION: ++* shut down lanes 1-3 if recognize that attached to an x1 end-point ++* INPUT: ++* pexIf - PEX interface number. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_OK on success , MV_ERROR otherwise ++* ++*******************************************************************************/ ++MV_U32 mvPexForceX1(MV_U32 pexIf) ++{ ++ MV_U32 regData = 0; ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ; ++ regData |= PXCR_CONF_LINK_X1; ++ ++ MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); ++ return MV_OK; ++} ++ ++MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) ++{ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_FALSE; ++ } ++ return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); ++} ++ ++ ++MV_VOID mvPexPowerDown(MV_U32 pexIf) ++{ ++ if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) || ++ (mvCtrlModelGet() == MV_76100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78200_DEV_ID) ) ++ { ++ mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); ++ } ++ else ++ { ++ MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087); ++ } ++} ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,168 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPEXH ++#define __INCPEXH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "pex/mvPexRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++ ++ ++/* NOTE not supported in this driver:*/ ++ ++ ++/* defines */ ++/* The number of supported PEX interfaces depend on Marvell controller */ ++/* device number. This device number ID is located on the PEX unit */ ++/* configuration header. This creates a loop where calling PEX */ ++/* configuration read/write routine results a call to get PEX configuration */ ++/* information etc. This macro defines a default PEX interface. This PEX */ ++/* interface is sure to exist. */ ++#define PEX_DEFAULT_IF 0 ++ ++ ++/* typedefs */ ++/* The Marvell controller supports both root complex and end point devices */ ++/* This enumeration describes the PEX type. */ ++typedef enum _mvPexType ++{ ++ MV_PEX_ROOT_COMPLEX, /* root complex device */ ++ MV_PEX_END_POINT /* end point device */ ++}MV_PEX_TYPE; ++ ++typedef enum _mvPexWidth ++{ ++ MV_PEX_WITDH_X1 = 1, ++ MV_PEX_WITDH_X2, ++ MV_PEX_WITDH_X3, ++ MV_PEX_WITDH_X4, ++ MV_PEX_WITDH_INVALID ++}MV_PEX_WIDTH; ++ ++/* PEX Bar attributes */ ++typedef struct _mvPexMode ++{ ++ MV_PEX_TYPE pexType; ++ MV_PEX_WIDTH pexWidth; ++ MV_BOOL pexLinkUp; ++}MV_PEX_MODE; ++ ++ ++ ++/* Global Functions prototypes */ ++/* mvPexInit - Initialize PEX interfaces*/ ++MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType); ++ ++/* mvPexModeGet - Get Pex If mode */ ++MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode); ++ ++/* mvPexConfigRead - Read from configuration space */ ++MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPexConfigWrite - Write to configuration space */ ++MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/ ++MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); ++ ++/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/ ++MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable); ++ ++/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/ ++MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); ++ ++/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/ ++MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); ++ ++/* mvPexLocalDevNumSet - Set PEX interface local device number.*/ ++MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); ++ ++/* mvPexLocalDevNumGet - Get PEX interface local device number.*/ ++MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); ++/* mvPexForceX1 - Force PEX interface to X1 mode. */ ++MV_U32 mvPexForceX1(MV_U32 pexIf); ++ ++/* mvPexIsPowerUp - Is PEX interface Power up? */ ++MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); ++ ++/* mvPexPowerDown - Power Down */ ++MV_VOID mvPexPowerDown(MV_U32 pexIf); ++ ++/* mvPexPowerUp - Power Up */ ++MV_VOID mvPexPowerUp(MV_U32 pexIf); ++ ++/* mvPexPhyRegRead - Pex phy read */ ++MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); ++ ++/* mvPexPhyRegWrite - Pex phy write */ ++MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); ++ ++MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); ++ ++#endif /* #ifndef __INCPEXH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,751 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPEXREGSH ++#define __INCPEXREGSH ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* defines */ ++#define MAX_PEX_DEVICES 32 ++#define MAX_PEX_FUNCS 8 ++#define MAX_PEX_BUSSES 256 ++ ++ ++ ++/*********************************************************/ ++/* PCI Express Configuration Cycles Generation Registers */ ++/*********************************************************/ ++ ++#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8) ++#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC) ++#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00) ++/* PCI Express Configuration Address Register */ ++/* PEX_CFG_ADDR_REG (PXCAR)*/ ++ ++#define PXCAR_REG_NUM_OFFS 2 ++#define PXCAR_REG_NUM_MAX 0x3F ++#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) ++#define PXCAR_FUNC_NUM_OFFS 8 ++#define PXCAR_FUNC_NUM_MAX 0x7 ++#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) ++#define PXCAR_DEVICE_NUM_OFFS 11 ++#define PXCAR_DEVICE_NUM_MAX 0x1F ++#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) ++#define PXCAR_BUS_NUM_OFFS 16 ++#define PXCAR_BUS_NUM_MAX 0xFF ++#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) ++#define PXCAR_EXT_REG_NUM_OFFS 24 ++#define PXCAR_EXT_REG_NUM_MAX 0xF ++ ++/* in pci express register address is now the legacy register address (8 bits) ++with the new extended register address (more 4 bits) , below is the mask of ++the upper 4 bits of the full register address */ ++ ++#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 ++#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) ++#define PXCAR_CONFIG_EN BIT31 ++ ++#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 ++#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) ++ ++/* The traditional PCI spec defined 6-bit field to describe register offset.*/ ++/* The new PCI Express extend the register offset by an extra 4-bits. */ ++/* The below macro assign 10-bit register offset into the apprpreate */ ++/* fields in the CFG_ADDR_REG */ ++#define PXCAR_REG_OFFS_SET(regOffs) \ ++ ( (regOff & PXCAR_REG_NUM_MASK) | \ ++ ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) ) ++ ++/***********************************/ ++/* PCI Express Interrupt registers */ ++/***********************************/ ++#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900) ++#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910) ++ ++#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ ++ /* of the PCI Express */ ++/* PCI Express Interrupt Cause */ ++/* PEX_INT_CAUSE_REG (PXICR)*/ ++/* PEX_INT_MASK_REG*/ ++/* ++NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets ++upon an error event occurrence. A write of 0 clears the bit. A write of 1 has ++no affect. Bits[24:27} are set and cleared upon reception of interrupt ++emulation messages. ++ ++Mask bit per cause bit. If a bit is set to 1, the corresponding event is ++enabled. Mask does not affect setting of the Interrupt Cause register bits; ++it only affects the assertion of the interrupt .*/ ++ ++ ++#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction ++ while master is disabled */ ++#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to ++ PCI Express internal register*/ ++#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ ++#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ ++#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ ++#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/ ++#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/ ++#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/ ++#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/ ++#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/ ++#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ ++ ++#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ ++#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/ ++#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/ ++#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/ ++#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/ ++#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/ ++#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/ ++#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/ ++#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/ ++#define PXICR_RCV_INTA BIT24 /* IntA status.*/ ++#define PXICR_RCV_INTB BIT25 /* IntB status.*/ ++#define PXICR_RCV_INTC BIT26 /* IntC status.*/ ++#define PXICR_RCV_INTD BIT27 /* IntD status.*/ ++#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ ++ ++ ++/********************************************/ ++/* PCI Express Control and Status Registers */ ++/********************************************/ ++#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00) ++#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04) ++#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10) ++#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18) ++#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20) ++#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30) ++#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40) ++#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0) ++ ++ ++#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50) ++/* PCI Express Control Register */ ++/* PEX_CTRL_REG (PXCR) */ ++ ++#define PXCR_CONF_LINK_OFFS 0 ++#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) ++#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) ++#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) ++#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/ ++#define PXCR_DEV_TYPE_CTRL_MASK BIT1 ++#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) ++#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) ++#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping ++ to Memory Space Enable */ ++ ++#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping ++ to Memory Space Enable*/ ++ ++#define PXCR_RSRV1_OFFS 5 ++#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) ++#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) ++ ++#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/ ++#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) ++ ++ ++#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/ ++#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) ++ ++#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/ ++#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ ++#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/ ++#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/ ++ ++/* PCI Express Status Register */ ++/* PEX_STATUS_REG (PXSR) */ ++ ++#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/ ++ ++#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ ++#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) ++ ++#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ ++#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) ++ ++#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/ ++#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/ ++#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/ ++#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/ ++ ++ ++/* PCI Express Completion Timeout Register */ ++/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/ ++ ++#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ ++#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) ++ ++/* PCI Express Power Management Extended Register */ ++/* PEX_PWR_MNG_EXT_REG (PXPMER) */ ++ ++#define PXPMER_L1_ASPM_EN_OFFS 1 ++#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) ++ ++/* PCI Express Flow Control Register */ ++/* PEX_FLOW_CTRL_REG (PXFCR)*/ ++ ++#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit ++ Initial Value.*/ ++#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) ++ ++ ++#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers ++ Flow Control Credit Initial Value*/ ++#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) ++ ++#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control ++ Credit Initial Value Infinite*/ ++ ++#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) ++ ++#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ ++#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) ++ ++/* PCI Express Acknowledge Timers (4X) Register */ ++/* PEX_ACK_TMR_4X_REG (PXAT4R) */ ++#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ ++#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) ++#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ ++#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) ++ ++/* PCI Express Acknowledge Timers (1X) Register */ ++/* PEX_ACK_TMR_1X_REG (PXAT1R) */ ++ ++#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout ++ Value for 1X Link*/ ++#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) ++ ++#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout ++ Value for 1X*/ ++#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) ++ ++ ++/* PCI Express TL Control Register */ ++/* PEX_TL_CTRL_REG (PXTCR) */ ++ ++#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/ ++#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) ++ ++/* PCI Express Debug MAC Control Register */ ++/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ ++ ++#define PXDMCR_LINKUP BIT4 ++ ++ ++ ++/**********************************************/ ++/* PCI Express Configuration Header Registers */ ++/**********************************************/ ++#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg)) ++ ++#define PEX_DEVICE_AND_VENDOR_ID 0x000 ++#define PEX_STATUS_AND_COMMAND 0x004 ++#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 ++#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C ++#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) ++#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) ++#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) ++#define PEX_BAR0_INTER_REG 0x010 ++#define PEX_BAR0_INTER_REG_HIGH 0x014 ++#define PEX_BAR1_REG 0x018 ++#define PEX_BAR1_REG_HIGH 0x01C ++#define PEX_BAR2_REG 0x020 ++#define PEX_BAR2_REG_HIGH 0x024 ++ ++#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C ++#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 ++#define PEX_CAPABILTY_LIST_POINTER 0x034 ++#define PEX_INTERRUPT_PIN_AND_LINE 0x03C ++ ++/* capability list */ ++#define PEX_POWER_MNG_CAPABILITY 0x040 ++#define PEX_POWER_MNG_STATUS_CONTROL 0x044 ++ ++#define PEX_MSI_MESSAGE_CONTROL 0x050 ++#define PEX_MSI_MESSAGE_ADDR 0x054 ++#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 ++#define PEX_MSI_MESSAGE_DATA 0x05C ++ ++#define PEX_CAPABILITY_REG 0x60 ++#define PEX_DEV_CAPABILITY_REG 0x64 ++#define PEX_DEV_CTRL_STAT_REG 0x68 ++#define PEX_LINK_CAPABILITY_REG 0x6C ++#define PEX_LINK_CTRL_STAT_REG 0x70 ++ ++#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 ++#define PEX_UNCORRECT_ERR_STAT_REG 0x104 ++#define PEX_UNCORRECT_ERR_MASK_REG 0x108 ++#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C ++#define PEX_CORRECT_ERR_STAT_REG 0x110 ++#define PEX_CORRECT_ERR_MASK_REG 0x114 ++#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 ++#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C ++#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 ++#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 ++#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 ++ ++ ++ ++/* PCI Express Device and Vendor ID Register*/ ++/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/ ++ ++#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ ++#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) ++ ++#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ ++#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) ++ ++ ++/* PCI Express Command and Status Register*/ ++/*PEX_STATUS_AND_COMMAND (PXSAC)*/ ++ ++#define PXSAC_IO_EN BIT0 /* IO Enable */ ++#define PXSAC_MEM_EN BIT1 /* Memory Enable */ ++#define PXSAC_MASTER_EN BIT2 /* Master Enable */ ++#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ ++#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ ++#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ ++#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ ++#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ ++#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ ++#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ ++#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ ++#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ ++#define PXSAC_SYSERR BIT30 /* Signalled system error */ ++#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ ++ ++ ++/* PCI Express Class Code and Revision ID Register*/ ++/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/ ++ ++#define PXCCARI_REVID_OFFS 0 /* Revision ID */ ++#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) ++ ++#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ ++#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) ++ ++#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/ ++#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) ++ ++#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/ ++#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) ++ ++#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/ ++#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) ++ ++ ++/* PCI Express BIST, Header Type and Cache Line Size Register*/ ++/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/ ++ ++#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ ++#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) ++ ++#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ ++#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) ++ ++#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ ++ ++#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ ++#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) ++#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) ++#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) ++ ++ ++#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ ++#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) ++ ++#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ ++#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ ++#define PXBHTLTCL_BISTCAP_OFFS 31 ++#define PXBHTLTCL_BISTCAP_MASK BIT31 ++#define PXBHTLTCL_BISTCAP_VAL 0 ++ ++ ++/* PCI Express Subsystem Device and Vendor ID */ ++/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/ ++ ++#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ ++#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) ++ ++#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ ++#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) ++ ++ ++/* PCI Express Capability List Pointer Register*/ ++/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/ ++ ++#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ ++#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) ++ ++/* PCI Express Interrupt Pin and Line Register */ ++/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/ ++ ++#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ ++#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) ++ ++#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ ++#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) ++ ++ ++/* PCI Express Power Management Capability Header Register*/ ++/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/ ++ ++#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ ++#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) ++ ++#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ ++#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) ++ ++#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/ ++#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) ++ ++#define PXPMC_DSI BIT21/* Device Specific Initialization */ ++ ++#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ ++#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) ++ ++#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/ ++ ++#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/ ++ ++#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/ ++#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) ++ ++/* PCI Express Power Management Control and Status Register*/ ++/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/ ++ ++#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ ++#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) ++ ++#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */ ++ ++#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/ ++#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) ++ ++#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ ++#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) ++ ++#define PXPMSC_PME_STAT BIT15/* PME Status */ ++ ++#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ ++#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) ++ ++ ++/* PCI Express MSI Message Control Register*/ ++/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/ ++ ++#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ ++#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) ++ ++#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ ++#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) ++ ++#define PXMMC_MSI_EN BIT18 /* MSI Enable */ ++ ++#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ ++#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) ++ ++#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ ++#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) ++ ++#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ ++ ++ ++/* PCI Express MSI Message Address Register*/ ++/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/ ++ ++#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to ++ Address[31:2] of the MSI MWr TLP*/ ++#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) ++ ++ ++/* PCI Express MSI Message Address (High) Register */ ++/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/ ++ ++#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to ++ Address[63:32] of the MSI MWr TLP*/ ++#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS ) ++ ++ ++/* PCI Express MSI Message Data Register*/ ++/*PEX_MSI_MESSAGE_DATA (PXMMD)*/ ++ ++#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ ++#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS ) ++ ++ ++/* PCI Express Capability Register*/ ++/*PEX_CAPABILITY_REG (PXCR)*/ ++ ++#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/ ++#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) ++ ++#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/ ++#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) ++ ++#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/ ++#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) ++ ++#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/ ++#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) ++ ++#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/ ++ ++#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/ ++#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) ++ ++ ++/* PCI Express Device Capabilities Register */ ++/*PEX_DEV_CAPABILITY_REG (PXDCR)*/ ++ ++#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/ ++#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) ++ ++#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/ ++#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++ ++#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/ ++#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) ++ ++ ++#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/ ++#define PXDCR_ATT_BUT_PRS_MASK BIT12 ++#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 ++ ++#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/ ++#define PXDCR_ATT_IND_PRS_MASK BIT13 ++#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 ++ ++#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/ ++#define PXDCR_PWR_IND_PRS_MASK BIT14 ++#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 ++ ++#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit ++ Value*/ ++#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) ++ ++#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit ++ Scale */ ++#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) ++ ++/* PCI Express Device Control Status Register */ ++/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/ ++ ++#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/ ++#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/ ++#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/ ++#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) ++ Reporting Enable*/ ++#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/ ++ ++#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/ ++#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) ++#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) ++#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/ ++ ++#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/ ++#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++ ++#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/ ++#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/ ++#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/ ++#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ ++#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/ ++ ++#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/ ++#define PXDCSR_TRANS_PEND_MASK BIT21 ++#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) ++ ++ ++/* PCI Express Link Capabilities Register*/ ++/*PEX_LINK_CAPABILITY_REG (PXLCR)*/ ++ ++#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/ ++#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) ++ ++#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/ ++#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) ++ ++#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/ ++#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) ++ ++#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/ ++#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) ++ ++#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ ++#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) ++ ++/* PCI Express Link Control Status Register */ ++/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/ ++ ++#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ ++#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) ++ ++#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ ++#define PXLCSR_RCB_MASK BIT3 ++#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) ++#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) ++ ++#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ ++#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ ++#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ ++#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ ++ ++#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ ++#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) ++ ++#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ ++#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) ++#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) ++ ++#define PXLCSR_LNK_TRN BIT27 /* Link Training */ ++ ++#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ ++#define PXLCSR_SLT_CLK_CFG_MASK BIT28 ++#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) ++#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) ++ ++/* PCI Express Advanced Error Report Header Register */ ++/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/ ++ ++/* PCI Express Uncorrectable Error Status Register*/ ++/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/ ++ ++/* PCI Express Uncorrectable Error Mask Register */ ++/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/ ++ ++/* PCI Express Uncorrectable Error Severity Register */ ++/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/ ++ ++/* PCI Express Correctable Error Status Register */ ++/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/ ++ ++/* PCI Express Correctable Error Mask Register */ ++/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/ ++ ++/* PCI Express Advanced Error Capability and Control Register*/ ++/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/ ++ ++/* PCI Express Header Log First DWORD Register*/ ++/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/ ++ ++/* PCI Express Header Log Second DWORD Register*/ ++/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/ ++ ++/* PCI Express Header Log Third DWORD Register*/ ++/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/ ++ ++/* PCI Express Header Log Fourth DWORD Register*/ ++/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* #ifndef __INCPEXREGSH */ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,313 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvPex.h" ++ ++//#define MV_DEBUG ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* locals */ ++typedef struct ++{ ++ MV_U32 data; ++ MV_U32 mask; ++}PEX_HEADER_DATA; ++ ++/* local function forwad decleration */ ++MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff); ++MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev); ++ ++ ++PEX_HEADER_DATA configHdr[16] = ++{ ++{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */ ++{0x00100007, 0x0000ffff}, /*[status register, command register] */ ++{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */ ++{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */ ++{0x00000000, 0x00000000}, /*[base address 0] */ ++{0x00000000, 0x00000000}, /*[base address 1] */ ++{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */ ++{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */ ++{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ ++{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ ++{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ ++{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */ ++{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ ++{0x00000000, 0x00000000}, /*[reserved, capability pointer] */ ++{0x00000000, 0x00000000}, /*[expansion ROM base address] */ ++{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ ++}; ++ ++ ++#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \ ++ (data & configHdr[offset/4].mask)) ++#define HEADER_READ(offset) configHdr[offset/4].data ++ ++/******************************************************************************* ++* mvVrtBrgPexInit - Initialize PEX interfaces ++* ++* DESCRIPTION: ++* ++* This function is responsible of intialization of the Pex Interface , It ++* configure the Pex Bars and Windows in the following manner: ++* ++* Assumptions : ++* Bar0 is always internal registers bar ++* Bar1 is always the DRAM bar ++* Bar2 is always the Device bar ++* ++* 1) Sets the Internal registers bar base by obtaining the base from ++* the CPU Interface ++* 2) Sets the DRAM bar base and size by getting the base and size from ++* the CPU Interface when the size is the sum of all enabled DRAM ++* chip selects and the base is the base of CS0 . ++* 3) Sets the Device bar base and size by getting these values from the ++* CPU Interface when the base is the base of the lowest base of the ++* Device chip selects, and the ++* ++* ++* INPUT: ++* ++* pexIf - PEX interface number. ++* ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM ++* ++*******************************************************************************/ ++MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf) ++{ ++ /* reset PEX tree to recover previous U-boot/Boot configurations */ ++ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); ++ ++ ++ resetPexConfig(pexIf, localBus, 1); ++ return MV_OK; ++} ++ ++ ++MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++ ++ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); ++ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); ++ MV_U32 val; ++ if(bus == localBus) ++ { ++ if(dev > 1) ++ { ++/* on the local device allow only device #0 & #1 */ ++ return 0xffffffff; ++ } ++ else ++ if (dev == localDev) ++ { ++ /* read the memory controller registers */ ++ return mvPexHwConfigRead (pexIf, bus, dev, func, regOff); ++ } ++ else ++ { ++ /* access the virtual brg header */ ++ return HEADER_READ(regOff); ++ } ++ } ++ else ++ if(bus == (localBus + 1)) ++ { ++ /* access the device behind the virtual bridge */ ++ if((dev == localDev) || (dev > 1)) ++ { ++ return 0xffffffff; ++ } ++ else ++ { ++ /* access the device behind the virtual bridge, in this case ++ * change the bus number to the local bus number in order to ++ * generate type 0 config cycle ++ */ ++ mvPexLocalBusNumSet(pexIf, bus); ++ mvPexLocalDevNumSet(pexIf, 1); ++ val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff); ++ mvPexLocalBusNumSet(pexIf, localBus); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return val; ++ } ++ } ++ /* for all other devices use the HW function to get the ++ * requested registers ++ */ ++ mvPexLocalDevNumSet(pexIf, 1); ++ val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return val; ++} ++ ++ ++MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); ++ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); ++ MV_STATUS status; ++ ++ if(bus == localBus) ++ { ++ if(dev > 1) ++ { ++ /* on the local device allow only device #0 & #1 */ ++ return MV_ERROR; ++ } ++ else ++ if (dev == localDev) ++ { ++ /* read the memory controller registers */ ++ return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); ++ } ++ else ++ { ++ /* access the virtual brg header */ ++ HEADER_WRITE(data, regOff); ++ return MV_OK; ++ } ++ } ++ else ++ if(bus == (localBus + 1)) ++ { ++ /* access the device behind the virtual bridge */ ++ if((dev == localDev) || (dev > 1)) ++ { ++ return MV_ERROR; ++ } ++ else ++ { ++ /* access the device behind the virtual bridge, in this case ++ * change the bus number to the local bus number in order to ++ * generate type 0 config cycle ++ */ ++ //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data); ++ mvPexLocalBusNumSet(pexIf, bus); ++ mvPexLocalDevNumSet(pexIf, 1); ++ status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data); ++ mvPexLocalBusNumSet(pexIf, localBus); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return status; ++ ++ } ++ } ++ /* for all other devices use the HW function to get the ++ * requested registers ++ */ ++ mvPexLocalDevNumSet(pexIf, 1); ++ status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return status; ++} ++ ++ ++ ++ ++void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev) ++{ ++ MV_U32 tData; ++ MV_U32 i; ++ ++ /* restore the PEX configuration to initialization state */ ++ /* in case PEX P2P call recursive and reset config */ ++ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0); ++ if(tData != 0xffffffff) ++ { ++ /* agent had been found - check whether P2P */ ++ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8); ++ if((tData & 0xffff0000) == 0x06040000) ++ {/* P2P */ ++ /* get the sec bus and the subordinate */ ++ MV_U32 secBus; ++ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18); ++ secBus = ((tData >> 8) & 0xff); ++ /* now scan on sec bus */ ++ for(i = 0;i < 0xff;i++) ++ { ++ resetPexConfig(pexIf, secBus, i); ++ } ++ /* now reset this device */ ++ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); ++ mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); ++ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); ++ } ++ } ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,82 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCVRTBRGPEXH ++#define __INCVRTBRGPEXH ++ ++ ++/* Global Functions prototypes */ ++/* mvPexInit - Initialize PEX interfaces*/ ++MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf); ++ ++/* mvPexConfigRead - Read from configuration space */ ++MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPexConfigWrite - Write to configuration space */ ++MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++ ++#endif /* #ifndef __INCPEXH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.3 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1522 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "mvOs.h" ++#include "sflash/mvSFlash.h" ++#include "sflash/mvSFlashSpec.h" ++#include "spi/mvSpi.h" ++#include "spi/mvSpiCmnd.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/*#define MV_DEBUG*/ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++/* Globals */ ++static MV_SFLASH_DEVICE_PARAMS sflash[] = { ++ /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ ++ { ++ MV_M25P_WREN_CMND_OPCD, ++ MV_M25P_WRDI_CMND_OPCD, ++ MV_M25P_RDID_CMND_OPCD, ++ MV_M25P_RDSR_CMND_OPCD, ++ MV_M25P_WRSR_CMND_OPCD, ++ MV_M25P_READ_CMND_OPCD, ++ MV_M25P_FAST_RD_CMND_OPCD, ++ MV_M25P_PP_CMND_OPCD, ++ MV_M25P_SE_CMND_OPCD, ++ MV_M25P_BE_CMND_OPCD, ++ MV_M25P_RES_CMND_OPCD, ++ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ ++ MV_M25P32_SECTOR_SIZE, ++ MV_M25P32_SECTOR_NUMBER, ++ MV_M25P_PAGE_SIZE, ++ "ST M25P32", ++ MV_M25PXXX_ST_MANF_ID, ++ MV_M25P32_DEVICE_ID, ++ MV_M25P32_MAX_SPI_FREQ, ++ MV_M25P32_MAX_FAST_SPI_FREQ, ++ MV_M25P32_FAST_READ_DUMMY_BYTES ++ }, ++ /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ ++ { ++ MV_M25P_WREN_CMND_OPCD, ++ MV_M25P_WRDI_CMND_OPCD, ++ MV_M25P_RDID_CMND_OPCD, ++ MV_M25P_RDSR_CMND_OPCD, ++ MV_M25P_WRSR_CMND_OPCD, ++ MV_M25P_READ_CMND_OPCD, ++ MV_M25P_FAST_RD_CMND_OPCD, ++ MV_M25P_PP_CMND_OPCD, ++ MV_M25P_SE_CMND_OPCD, ++ MV_M25P_BE_CMND_OPCD, ++ MV_M25P_RES_CMND_OPCD, ++ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ ++ MV_M25P64_SECTOR_SIZE, ++ MV_M25P64_SECTOR_NUMBER, ++ MV_M25P_PAGE_SIZE, ++ "ST M25P64", ++ MV_M25PXXX_ST_MANF_ID, ++ MV_M25P64_DEVICE_ID, ++ MV_M25P64_MAX_SPI_FREQ, ++ MV_M25P64_MAX_FAST_SPI_FREQ, ++ MV_M25P64_FAST_READ_DUMMY_BYTES ++ }, ++ /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ ++ { ++ MV_M25P_WREN_CMND_OPCD, ++ MV_M25P_WRDI_CMND_OPCD, ++ MV_M25P_RDID_CMND_OPCD, ++ MV_M25P_RDSR_CMND_OPCD, ++ MV_M25P_WRSR_CMND_OPCD, ++ MV_M25P_READ_CMND_OPCD, ++ MV_M25P_FAST_RD_CMND_OPCD, ++ MV_M25P_PP_CMND_OPCD, ++ MV_M25P_SE_CMND_OPCD, ++ MV_M25P_BE_CMND_OPCD, ++ MV_M25P_RES_CMND_OPCD, ++ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ ++ MV_M25P128_SECTOR_SIZE, ++ MV_M25P128_SECTOR_NUMBER, ++ MV_M25P_PAGE_SIZE, ++ "ST M25P128", ++ MV_M25PXXX_ST_MANF_ID, ++ MV_M25P128_DEVICE_ID, ++ MV_M25P128_MAX_SPI_FREQ, ++ MV_M25P128_MAX_FAST_SPI_FREQ, ++ MV_M25P128_FAST_READ_DUMMY_BYTES ++ }, ++ /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ ++ { ++ MV_MX25L_WREN_CMND_OPCD, ++ MV_MX25L_WRDI_CMND_OPCD, ++ MV_MX25L_RDID_CMND_OPCD, ++ MV_MX25L_RDSR_CMND_OPCD, ++ MV_MX25L_WRSR_CMND_OPCD, ++ MV_MX25L_READ_CMND_OPCD, ++ MV_MX25L_FAST_RD_CMND_OPCD, ++ MV_MX25L_PP_CMND_OPCD, ++ MV_MX25L_SE_CMND_OPCD, ++ MV_MX25L_BE_CMND_OPCD, ++ MV_MX25L_RES_CMND_OPCD, ++ MV_MX25L_DP_CMND_OPCD, ++ MV_MX25L6405_SECTOR_SIZE, ++ MV_MX25L6405_SECTOR_NUMBER, ++ MV_MXIC_PAGE_SIZE, ++ "MXIC MX25L6405", ++ MV_MXIC_MANF_ID, ++ MV_MX25L6405_DEVICE_ID, ++ MV_MX25L6405_MAX_SPI_FREQ, ++ MV_MX25L6405_MAX_FAST_SPI_FREQ, ++ MV_MX25L6405_FAST_READ_DUMMY_BYTES ++ }, ++ /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ ++ { ++ MV_S25FL_WREN_CMND_OPCD, ++ MV_S25FL_WRDI_CMND_OPCD, ++ MV_S25FL_RDID_CMND_OPCD, ++ MV_S25FL_RDSR_CMND_OPCD, ++ MV_S25FL_WRSR_CMND_OPCD, ++ MV_S25FL_READ_CMND_OPCD, ++ MV_S25FL_FAST_RD_CMND_OPCD, ++ MV_S25FL_PP_CMND_OPCD, ++ MV_S25FL_SE_CMND_OPCD, ++ MV_S25FL_BE_CMND_OPCD, ++ MV_S25FL_RES_CMND_OPCD, ++ MV_S25FL_DP_CMND_OPCD, ++ MV_S25FL128_SECTOR_SIZE, ++ MV_S25FL128_SECTOR_NUMBER, ++ MV_S25FL_PAGE_SIZE, ++ "SPANSION S25FL128", ++ MV_SPANSION_MANF_ID, ++ MV_S25FL128_DEVICE_ID, ++ MV_S25FL128_MAX_SPI_FREQ, ++ MV_M25P128_MAX_FAST_SPI_FREQ, ++ MV_M25P128_FAST_READ_DUMMY_BYTES ++ } ++}; ++ ++/* Static Functions */ ++static MV_STATUS mvWriteEnable (MV_SFLASH_INFO * pFlinfo); ++static MV_STATUS mvStatusRegGet (MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg); ++static MV_STATUS mvStatusRegSet (MV_SFLASH_INFO * pFlinfo, MV_U8 sr); ++static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo); ++static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, \ ++ MV_U8* pPageBuff, MV_U32 buffSize); ++static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, \ ++ MV_U8* manId, MV_U16* devId); ++ ++/******************************************************************************* ++* mvWriteEnable - serialize the write enable sequence ++* ++* DESCRIPTION: ++* transmit the sequence for write enable ++* ++********************************************************************************/ ++static MV_STATUS mvWriteEnable(MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_U8 cmd[MV_SFLASH_WREN_CMND_LENGTH]; ++ ++ ++ cmd[0] = sflash[pFlinfo->index].opcdWREN; ++ ++ return mvSpiWriteThenRead(cmd, MV_SFLASH_WREN_CMND_LENGTH, NULL, 0, 0); ++} ++ ++/******************************************************************************* ++* mvStatusRegGet - Retrieve the value of the status register ++* ++* DESCRIPTION: ++* perform the RDSR sequence to get the 8bit status register ++* ++********************************************************************************/ ++static MV_STATUS mvStatusRegGet(MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_RDSR_CMND_LENGTH]; ++ MV_U8 sr[MV_SFLASH_RDSR_REPLY_LENGTH]; ++ ++ ++ ++ ++ cmd[0] = sflash[pFlinfo->index].opcdRDSR; ++ ++ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDSR_CMND_LENGTH, sr, ++ MV_SFLASH_RDSR_REPLY_LENGTH,0)) != MV_OK) ++ return ret; ++ ++ *pStatReg = sr[0]; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared ++* ++* DESCRIPTION: ++* Block waiting for the WIP (write in progress) to be cleared ++* ++********************************************************************************/ ++static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U32 i; ++ MV_U8 stat; ++ ++ for (i=0; iindex].opcdWRSR; ++ cmd[1] = sr; ++ ++ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_WRSR_CMND_LENGTH, NULL, 0, 0)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) ++ return ret; ++ ++ mvOsDelay(1); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashPageWr - Write up to 256 Bytes in the same page ++* ++* DESCRIPTION: ++* Write a buffer up to the page size in length provided that the whole address ++* range is within the same page (alligned to page bounderies) ++* ++*******************************************************************************/ ++static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pPageBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_PP_CMND_LENGTH]; ++ ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invalid parameter device index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that we do not cross the page bounderies */ ++ if (((offset & (sflash[pFlinfo->index].pageSize - 1)) + buffSize) > ++ sflash[pFlinfo->index].pageSize) ++ { ++ DB(mvOsPrintf("%s WARNING: Page allignment problem!\n", __FUNCTION__);) ++ return MV_OUT_OF_RANGE; ++ } ++ ++ /* Issue the Write enable command prior the page program command */ ++ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) ++ return ret; ++ ++ cmd[0] = sflash[pFlinfo->index].opcdPP; ++ cmd[1] = ((offset >> 16) & 0xFF); ++ cmd[2] = ((offset >> 8) & 0xFF); ++ cmd[3] = (offset & 0xFF); ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_PP_CMND_LENGTH, pPageBuff, buffSize)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashWithDefaultsIdGet - Try to read the manufacturer and Device IDs from ++* the device using the default RDID opcode and the default WREN opcode. ++* ++* DESCRIPTION: ++* This is used to detect a generic device that uses the default opcodes ++* for the WREN and RDID. ++* ++********************************************************************************/ ++static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* manId, MV_U16* devId) ++{ ++ MV_STATUS ret; ++ MV_U8 cmdRDID[MV_SFLASH_RDID_CMND_LENGTH]; ++ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; ++ ++ ++ ++ /* Use the default RDID opcode to read the IDs */ ++ cmdRDID[0] = MV_SFLASH_DEFAULT_RDID_OPCD; /* unknown model try default */ ++ if ((ret = mvSpiWriteThenRead(cmdRDID, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) ++ return ret; ++ ++ *manId = id[0]; ++ *devId = 0; ++ *devId |= (id[1] << 8); ++ *devId |= id[2]; ++ ++ return MV_OK; ++} ++ ++/* ++##################################################################################### ++##################################################################################### ++*/ ++ ++/******************************************************************************* ++* mvSFlashInit - Initialize the serial flash device ++* ++* DESCRIPTION: ++* Perform the neccessary initialization and configuration ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* pFlinfo->baseAddr: base address in fast mode. ++* pFlinfo->index: Index of the flash in the sflash tabel. If the SPI ++* flash device does not support read Id command with ++* the standard opcode, then the user should supply this ++* as an input to skip the autodetection process!!!! ++* ++* OUTPUT: ++* pFlinfo: pointer to the Flash information structure after detection ++* pFlinfo->manufacturerId: Manufacturer ID ++* pFlinfo->deviceId: Device ID ++* pFlinfo->sectorSize: size of the sector (all sectors are the same). ++* pFlinfo->sectorNumber: number of sectors. ++* pFlinfo->pageSize: size of the page. ++* pFlinfo->index: Index of the detected flash in the sflash tabel ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 manf; ++ MV_U16 dev; ++ MV_U32 indx; ++ MV_BOOL detectFlag = MV_FALSE; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Initialize the SPI interface with low frequency to make sure that the read ID succeeds */ ++ if ((ret = mvSpiInit(MV_SFLASH_BASIC_SPI_FREQ)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to initialize the SPI interface!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ /* First try to read the Manufacturer and Device IDs */ ++ if ((ret = mvSFlashIdGet(pFlinfo, &manf, &dev)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to get the SFlash ID!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ /* loop over the whole table and look for the appropriate SFLASH */ ++ for (indx=0; indxmanufacturerId = manf; ++ pFlinfo->deviceId = dev; ++ pFlinfo->index = indx; ++ detectFlag = MV_TRUE; ++ } ++ } ++ ++ if(!detectFlag) ++ { ++ mvOsPrintf("%s ERROR: Unknown SPI flash device!\n", __FUNCTION__); ++ return MV_FAIL; ++ } ++ ++ /* fill the info based on the model detected */ ++ pFlinfo->sectorSize = sflash[pFlinfo->index].sectorSize; ++ pFlinfo->sectorNumber = sflash[pFlinfo->index].sectorNumber; ++ pFlinfo->pageSize = sflash[pFlinfo->index].pageSize; ++ ++ /* Set the SPI frequency to the MAX allowed for the device for best performance */ ++ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ /* As default lock the SR */ ++ if ((ret = mvSFlashStatRegLock(pFlinfo, MV_TRUE)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashSectorErase - Erasse a single sector of the serial flash ++* ++* DESCRIPTION: ++* Issue the erase sector command and address ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* secNumber: sector Number to erase (0 -> (sectorNumber-1)) ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_SE_CMND_LENGTH]; ++ ++ MV_U32 secAddr = (secNumber * pFlinfo->sectorSize); ++#if 0 ++ MV_U32 i; ++ MV_U32 * pW = (MV_U32*) (secAddr + pFlinfo->baseAddr); ++ MV_U32 erasedWord = 0xFFFFFFFF; ++ MV_U32 wordsPerSector = (pFlinfo->sectorSize / sizeof(MV_U32)); ++ MV_BOOL eraseNeeded = MV_FALSE; ++#endif ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that the sector number is valid */ ++ if (secNumber >= pFlinfo->sectorNumber) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter sector number!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* we don't want to access SPI in direct mode from in-direct API, ++ becasue of timing issue between CS asserts. */ ++#if 0 ++ /* First compare to FF and check if erase is needed */ ++ for (i=0; iindex].opcdSE; ++ cmd[1] = ((secAddr >> 16) & 0xFF); ++ cmd[2] = ((secAddr >> 8) & 0xFF); ++ cmd[3] = (secAddr & 0xFF); ++ ++ /* Issue the Write enable command prior the sector erase command */ ++ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_SE_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashChipErase - Erasse the whole serial flash ++* ++* DESCRIPTION: ++* Issue the bulk (chip) erase command ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_BE_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdBE; ++ ++ /* Issue the Write enable command prior the Bulk erase command */ ++ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_BE_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnChipEraseDone(pFlinfo)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashBlockRd - Read from the serial flash ++* ++* DESCRIPTION: ++* Issue the read command and address then perfom the needed read ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* offset: byte offset with the flash to start reading from ++* pReadBuff: pointer to the buffer to read the data in ++* buffSize: size of the buffer to read. ++* ++* OUTPUT: ++* pReadBuff: pointer to the buffer containing the read data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize) ++{ ++ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pReadBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdREAD; ++ cmd[1] = ((offset >> 16) & 0xFF); ++ cmd[2] = ((offset >> 8) & 0xFF); ++ cmd[3] = (offset & 0xFF); ++ ++ return mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, 0); ++} ++ ++/******************************************************************************* ++* mvSFlashFastBlockRd - Fast read from the serial flash ++* ++* DESCRIPTION: ++* Issue the fast read command and address then perfom the needed read ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* offset: byte offset with the flash to start reading from ++* pReadBuff: pointer to the buffer to read the data in ++* buffSize: size of the buffer to read. ++* ++* OUTPUT: ++* pReadBuff: pointer to the buffer containing the read data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize) ++{ ++ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; ++ MV_STATUS ret; ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pReadBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* Set the SPI frequency to the MAX allowed for fast-read operations */ ++ mvOsPrintf("Setting freq to %d.\n",sflash[pFlinfo->index].spiMaxFastFreq); ++ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFastFreq)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to set the SPI fast frequency!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdFSTRD; ++ cmd[1] = ((offset >> 16) & 0xFF); ++ cmd[2] = ((offset >> 8) & 0xFF); ++ cmd[3] = (offset & 0xFF); ++ ++ ++ ret = mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, ++ sflash[pFlinfo->index].spiFastRdDummyBytes); ++ ++ /* Reset the SPI frequency to the MAX allowed for the device for best performance */ ++ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++ ++/******************************************************************************* ++* mvSFlashBlockWr - Write a buffer with any size ++* ++* DESCRIPTION: ++* write regardless of the page boundaries and size limit per Page ++* program command ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* offset: byte offset within the flash region ++* pWriteBuff: pointer to the buffer holding the data to program ++* buffSize: size of the buffer to write ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pWriteBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 data2write = buffSize; ++ MV_U32 preAllOffset = (offset & MV_SFLASH_PAGE_ALLIGN_MASK(MV_M25P_PAGE_SIZE)); ++ MV_U32 preAllSz = (preAllOffset ? (MV_M25P_PAGE_SIZE - preAllOffset) : 0); ++ MV_U32 writeOffset = offset; ++ ++ /* check for NULL pointer */ ++#ifndef CONFIG_MARVELL ++ if(NULL == pWriteBuff) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++#endif ++ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that the buffer size does not exceed the flash size */ ++ if ((offset + buffSize) > mvSFlashSizeGet(pFlinfo)) ++ { ++ DB(mvOsPrintf("%s WARNING: Write exceeds flash size!\n", __FUNCTION__);) ++ return MV_OUT_OF_RANGE; ++ } ++ ++ /* check if the total block size is less than the first chunk remainder */ ++ if (data2write < preAllSz) ++ preAllSz = data2write; ++ ++ /* check if programing does not start at a 64byte alligned offset */ ++ if (preAllSz) ++ { ++ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, preAllSz)) != MV_OK) ++ return ret; ++ ++ /* increment pointers and counters */ ++ writeOffset += preAllSz; ++ data2write -= preAllSz; ++ pWriteBuff += preAllSz; ++ } ++ ++ /* program the data that fits in complete page chunks */ ++ while (data2write >= sflash[pFlinfo->index].pageSize) ++ { ++ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, sflash[pFlinfo->index].pageSize)) != MV_OK) ++ return ret; ++ ++ /* increment pointers and counters */ ++ writeOffset += sflash[pFlinfo->index].pageSize; ++ data2write -= sflash[pFlinfo->index].pageSize; ++ pWriteBuff += sflash[pFlinfo->index].pageSize; ++ } ++ ++ /* program the last partial chunk */ ++ if (data2write) ++ { ++ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, data2write)) != MV_OK) ++ return ret; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashIdGet - Get the manufacturer and device IDs. ++* ++* DESCRIPTION: ++* Get the Manufacturer and device IDs from the serial flash through ++* writing the RDID command then reading 3 bytes of data. In case that ++* this command was called for the first time in order to detect the ++* manufacturer and device IDs, then the default RDID opcode will be used ++* unless the device index is indicated by the user (in case the SPI flash ++* does not use the default RDID opcode). ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* pManId: pointer to the 8bit variable to hold the manufacturing ID ++* pDevId: pointer to the 16bit variable to hold the device ID ++* ++* OUTPUT: ++* pManId: pointer to the 8bit variable holding the manufacturing ID ++* pDevId: pointer to the 16bit variable holding the device ID ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_RDID_CMND_LENGTH]; ++ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; ++ ++ ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pManId == NULL) || (pDevId == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ return mvSFlashWithDefaultsIdGet(pFlinfo, pManId, pDevId); ++ else ++ cmd[0] = sflash[pFlinfo->index].opcdRDID; ++ ++ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) ++ return ret; ++ ++ *pManId = id[0]; ++ *pDevId = 0; ++ *pDevId |= (id[1] << 8); ++ *pDevId |= id[2]; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashWpRegionSet - Set the Write-Protected region ++* ++* DESCRIPTION: ++* Set the Write-Protected region ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* wpRegion: which region will be protected ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion) ++{ ++ MV_U8 wpMask; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the chip is an ST flash; then WP supports only 3 bits */ ++ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) ++ { ++ switch (wpRegion) ++ { ++ case MV_WP_NONE: ++ wpMask = MV_M25P_STATUS_BP_NONE; ++ break; ++ ++ case MV_WP_UPR_1OF128: ++ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ ++ case MV_WP_UPR_1OF64: ++ wpMask = MV_M25P_STATUS_BP_1_OF_64; ++ break; ++ ++ case MV_WP_UPR_1OF32: ++ wpMask = MV_M25P_STATUS_BP_1_OF_32; ++ break; ++ ++ case MV_WP_UPR_1OF16: ++ wpMask = MV_M25P_STATUS_BP_1_OF_16; ++ break; ++ ++ case MV_WP_UPR_1OF8: ++ wpMask = MV_M25P_STATUS_BP_1_OF_8; ++ break; ++ ++ case MV_WP_UPR_1OF4: ++ wpMask = MV_M25P_STATUS_BP_1_OF_4; ++ break; ++ ++ case MV_WP_UPR_1OF2: ++ wpMask = MV_M25P_STATUS_BP_1_OF_2; ++ break; ++ ++ case MV_WP_ALL: ++ wpMask = MV_M25P_STATUS_BP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ } ++ /* check if the manufacturer is MXIC then the WP is 4bits */ ++ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) ++ { ++ switch (wpRegion) ++ { ++ case MV_WP_NONE: ++ wpMask = MV_MX25L_STATUS_BP_NONE; ++ break; ++ ++ case MV_WP_UPR_1OF128: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_128; ++ break; ++ ++ case MV_WP_UPR_1OF64: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_64; ++ break; ++ ++ case MV_WP_UPR_1OF32: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_32; ++ break; ++ ++ case MV_WP_UPR_1OF16: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_16; ++ break; ++ ++ case MV_WP_UPR_1OF8: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_8; ++ break; ++ ++ case MV_WP_UPR_1OF4: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_4; ++ break; ++ ++ case MV_WP_UPR_1OF2: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_2; ++ break; ++ ++ case MV_WP_ALL: ++ wpMask = MV_MX25L_STATUS_BP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ } ++ /* check if the manufacturer is SPANSION then the WP is 4bits */ ++ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) ++ { ++ switch (wpRegion) ++ { ++ case MV_WP_NONE: ++ wpMask = MV_S25FL_STATUS_BP_NONE; ++ break; ++ ++ case MV_WP_UPR_1OF128: ++ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ ++ case MV_WP_UPR_1OF64: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_64; ++ break; ++ ++ case MV_WP_UPR_1OF32: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_32; ++ break; ++ ++ case MV_WP_UPR_1OF16: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_16; ++ break; ++ ++ case MV_WP_UPR_1OF8: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_8; ++ break; ++ ++ case MV_WP_UPR_1OF4: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_4; ++ break; ++ ++ case MV_WP_UPR_1OF2: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_2; ++ break; ++ ++ case MV_WP_ALL: ++ wpMask = MV_S25FL_STATUS_BP_ALL; ++ break; ++ ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ } ++ else ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* Verify that the SRWD bit is always set - register is s/w locked */ ++ wpMask |= MV_SFLASH_STATUS_REG_SRWD_MASK; ++ ++ return mvStatusRegSet(pFlinfo, wpMask); ++} ++ ++/******************************************************************************* ++* mvSFlashWpRegionGet - Get the Write-Protected region configured ++* ++* DESCRIPTION: ++* Get from the chip the Write-Protected region configured ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* pWpRegion: pointer to the variable to return the WP region in ++* ++* OUTPUT: ++* wpRegion: pointer to the variable holding the WP region configured ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion) ++{ ++ MV_STATUS ret; ++ MV_U8 reg; ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pWpRegion == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) ++ return ret; ++ ++ /* Check if the chip is an ST flash; then WP supports only 3 bits */ ++ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) ++ { ++ switch ((reg & MV_M25P_STATUS_REG_WP_MASK)) ++ { ++ case MV_M25P_STATUS_BP_NONE: ++ *pWpRegion = MV_WP_NONE; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_64: ++ *pWpRegion = MV_WP_UPR_1OF64; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_32: ++ *pWpRegion = MV_WP_UPR_1OF32; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_16: ++ *pWpRegion = MV_WP_UPR_1OF16; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_8: ++ *pWpRegion = MV_WP_UPR_1OF8; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_4: ++ *pWpRegion = MV_WP_UPR_1OF4; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_2: ++ *pWpRegion = MV_WP_UPR_1OF2; ++ break; ++ ++ case MV_M25P_STATUS_BP_ALL: ++ *pWpRegion = MV_WP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) ++ return MV_BAD_VALUE; ++ } ++ } ++ /* check if the manufacturer is MXIC then the WP is 4bits */ ++ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) ++ { ++ switch ((reg & MV_MX25L_STATUS_REG_WP_MASK)) ++ { ++ case MV_MX25L_STATUS_BP_NONE: ++ *pWpRegion = MV_WP_NONE; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_128: ++ *pWpRegion = MV_WP_UPR_1OF128; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_64: ++ *pWpRegion = MV_WP_UPR_1OF64; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_32: ++ *pWpRegion = MV_WP_UPR_1OF32; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_16: ++ *pWpRegion = MV_WP_UPR_1OF16; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_8: ++ *pWpRegion = MV_WP_UPR_1OF8; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_4: ++ *pWpRegion = MV_WP_UPR_1OF4; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_2: ++ *pWpRegion = MV_WP_UPR_1OF2; ++ break; ++ ++ case MV_MX25L_STATUS_BP_ALL: ++ *pWpRegion = MV_WP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) ++ return MV_BAD_VALUE; ++ } ++ } ++ /* Check if the chip is an SPANSION flash; then WP supports only 3 bits */ ++ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) ++ { ++ switch ((reg & MV_S25FL_STATUS_REG_WP_MASK)) ++ { ++ case MV_S25FL_STATUS_BP_NONE: ++ *pWpRegion = MV_WP_NONE; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_64: ++ *pWpRegion = MV_WP_UPR_1OF64; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_32: ++ *pWpRegion = MV_WP_UPR_1OF32; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_16: ++ *pWpRegion = MV_WP_UPR_1OF16; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_8: ++ *pWpRegion = MV_WP_UPR_1OF8; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_4: ++ *pWpRegion = MV_WP_UPR_1OF4; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_2: ++ *pWpRegion = MV_WP_UPR_1OF2; ++ break; ++ ++ case MV_S25FL_STATUS_BP_ALL: ++ *pWpRegion = MV_WP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) ++ return MV_BAD_VALUE; ++ } ++ } ++ else ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashStatRegLock - Lock the status register for writing - W/Vpp ++* pin should be low to take effect ++* ++* DESCRIPTION: ++* Lock the access to the Status Register for writing. This will ++* cause the flash to enter the hardware protection mode if the W/Vpp ++* is low. If the W/Vpp is hi, the chip will be in soft protection mode, but ++* the register will continue to be writable if WREN sequence was used. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* srLock: enable/disable (MV_TRUE/MV_FALSE) status registor lock mechanism ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock) ++{ ++ MV_STATUS ret; ++ MV_U8 reg; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) ++ return ret; ++ ++ if (srLock) ++ reg |= MV_SFLASH_STATUS_REG_SRWD_MASK; ++ else ++ reg &= ~MV_SFLASH_STATUS_REG_SRWD_MASK; ++ ++ return mvStatusRegSet(pFlinfo, reg); ++} ++ ++/******************************************************************************* ++* mvSFlashSizeGet - Get the size of the SPI flash ++* ++* DESCRIPTION: ++* based on the sector number and size of each sector calculate the total ++* size of the flash memory. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Size of the flash in bytes. ++* ++* ++*******************************************************************************/ ++MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo) ++{ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ return (pFlinfo->sectorSize * pFlinfo->sectorNumber); ++} ++ ++/******************************************************************************* ++* mvSFlashPowerSaveEnter - Cause the falsh device to go into power save mode ++* ++* DESCRIPTION: ++* Enter a special power save mode. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Size of the flash in bytes. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_DP_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that power save mode is supported in the specific device */ ++ if (sflash[pFlinfo->index].opcdPwrSave == MV_SFLASH_NO_SPECIFIC_OPCD) ++ { ++ DB(mvOsPrintf("%s WARNING: Power save not supported for this device!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdPwrSave; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_DP_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvSFlashPowerSaveExit - Cause the falsh device to exit the power save mode ++* ++* DESCRIPTION: ++* Exit the deep power save mode. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Size of the flash in bytes. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_RES_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that power save mode is supported in the specific device */ ++ if (sflash[pFlinfo->index].opcdRES == MV_SFLASH_NO_SPECIFIC_OPCD) ++ { ++ DB(mvOsPrintf("%s WARNING: Read Electronic Signature not supported for this device!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdRES; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_RES_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ /* add the delay needed for the device to wake up */ ++ mvOsDelay(MV_MXIC_DP_EXIT_DELAY); /* 30 ms */ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvSFlashModelGet - Retreive the string with the device manufacturer and model ++* ++* DESCRIPTION: ++* Retreive the string with the device manufacturer and model ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* pointer to the string indicating the device manufacturer and model ++* ++* ++*******************************************************************************/ ++const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo) ++{ ++ static const MV_8 * unknModel = (const MV_8 *)"Unknown"; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return unknModel; ++ } ++ ++ return sflash[pFlinfo->index].deviceModel; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,166 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSFlashH ++#define __INCmvSFlashH ++ ++#include "mvTypes.h" ++ ++/* MCAROS */ ++#define MV_SFLASH_PAGE_ALLIGN_MASK(pgSz) (pgSz-1) ++#define MV_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) ++ ++/* Constants */ ++#define MV_INVALID_DEVICE_NUMBER 0xFFFFFFFF ++/* 10 MHz is the minimum possible SPI frequency when tclk is set 200MHz*/ ++#define MV_SFLASH_BASIC_SPI_FREQ 10000000 ++/* enumerations */ ++typedef enum ++{ ++ MV_WP_NONE, /* Unprotect the whole chip */ ++ MV_WP_UPR_1OF128, /* Write protect the upper 1/128 part */ ++ MV_WP_UPR_1OF64, /* Write protect the upper 1/64 part */ ++ MV_WP_UPR_1OF32, /* Write protect the upper 1/32 part */ ++ MV_WP_UPR_1OF16, /* Write protect the upper 1/16 part */ ++ MV_WP_UPR_1OF8, /* Write protect the upper 1/8 part */ ++ MV_WP_UPR_1OF4, /* Write protect the upper 1/4 part */ ++ MV_WP_UPR_1OF2, /* Write protect the upper 1/2 part */ ++ MV_WP_ALL /* Write protect the whole chip */ ++} MV_SFLASH_WP_REGION; ++ ++/* Type Definitions */ ++typedef struct ++{ ++ MV_U8 opcdWREN; /* Write enable opcode */ ++ MV_U8 opcdWRDI; /* Write disable opcode */ ++ MV_U8 opcdRDID; /* Read ID opcode */ ++ MV_U8 opcdRDSR; /* Read Status Register opcode */ ++ MV_U8 opcdWRSR; /* Write Status register opcode */ ++ MV_U8 opcdREAD; /* Read opcode */ ++ MV_U8 opcdFSTRD; /* Fast Read opcode */ ++ MV_U8 opcdPP; /* Page program opcode */ ++ MV_U8 opcdSE; /* Sector erase opcode */ ++ MV_U8 opcdBE; /* Bulk erase opcode */ ++ MV_U8 opcdRES; /* Read electronic signature */ ++ MV_U8 opcdPwrSave; /* Go into power save mode */ ++ MV_U32 sectorSize; /* Size of each sector */ ++ MV_U32 sectorNumber; /* Number of sectors */ ++ MV_U32 pageSize; /* size of each page */ ++ const char * deviceModel; /* string with the device model */ ++ MV_U32 manufacturerId; /* The manufacturer ID */ ++ MV_U32 deviceId; /* Device ID */ ++ MV_U32 spiMaxFreq; /* The MAX frequency that can be used with the device */ ++ MV_U32 spiMaxFastFreq; /* The MAX frequency that can be used with the device for fast reads */ ++ MV_U32 spiFastRdDummyBytes; /* Number of dumy bytes to read before real data when working in fast read mode. */ ++} MV_SFLASH_DEVICE_PARAMS; ++ ++typedef struct ++{ ++ MV_U32 baseAddr; /* Flash Base Address used in fast mode */ ++ MV_U8 manufacturerId; /* Manufacturer ID */ ++ MV_U16 deviceId; /* Device ID */ ++ MV_U32 sectorSize; /* Size of each sector - all the same */ ++ MV_U32 sectorNumber; /* Number of sectors */ ++ MV_U32 pageSize; /* Page size - affect allignment */ ++ MV_U32 index; /* index of the device in the sflash table (internal parameter) */ ++} MV_SFLASH_INFO; ++ ++/* Function Prototypes */ ++/* Init */ ++MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo); ++ ++/* erase */ ++MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber); ++MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo); ++ ++/* Read */ ++MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize); ++MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize); ++ ++/* write regardless of the page boundaries and size limit per Page program command */ ++MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pWriteBuff, MV_U32 buffSize); ++/* Get IDs */ ++MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId); ++ ++/* Set and Get the Write Protection region - if the Status register is not locked */ ++MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion); ++MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion); ++ ++/* Lock the status register for writing - W/Vpp pin should be low to take effect */ ++MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock); ++ ++/* Get the regions sizes */ ++MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo); ++ ++/* Cause the falsh device to go into power save mode */ ++MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo); ++MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo); ++ ++/* Retreive the string with the device manufacturer and model */ ++const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo); ++ ++#endif /* __INCmvSFlashH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,233 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSFlashSpecH ++#define __INCmvSFlashSpecH ++ ++/* Constants */ ++#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ ++#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ ++#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ ++#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */ ++#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ ++#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */ ++#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ ++ ++/* Status Register Bit Masks */ ++#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */ ++#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */ ++#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */ ++#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET) ++#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET) ++ ++#define MV_SFLASH_MAX_WAIT_LOOP 1000000 ++#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 ++ ++#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ ++#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ ++#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00 ++ ++/********************************/ ++/* ST M25Pxxx Device Specific */ ++/********************************/ ++ ++/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ ++#define MV_M25PXXX_ST_MANF_ID 0x20 ++#define MV_M25P32_DEVICE_ID 0x2016 ++#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_M25P32_FAST_READ_DUMMY_BYTES 1 ++#define MV_M25P64_DEVICE_ID 0x2017 ++#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_M25P64_FAST_READ_DUMMY_BYTES 1 ++#define MV_M25P128_DEVICE_ID 0x2018 ++#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_M25P128_FAST_READ_DUMMY_BYTES 1 ++ ++ ++/* Sector Sizes and population per device model*/ ++#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */ ++#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */ ++#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */ ++#define MV_M25P32_SECTOR_NUMBER 64 ++#define MV_M25P64_SECTOR_NUMBER 128 ++#define MV_M25P128_SECTOR_NUMBER 64 ++#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */ ++ ++#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ ++#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ ++#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ ++#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */ ++#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */ ++#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ ++#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ ++#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */ ++#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ ++#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ ++#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ ++ ++/* Status Register Write Protect Bit Masks - 3bits */ ++#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++ ++/************************************/ ++/* MXIC MX25L6405 Device Specific */ ++/************************************/ ++ ++/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ ++#define MV_MXIC_MANF_ID 0xC2 ++#define MV_MX25L6405_DEVICE_ID 0x2017 ++#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1 ++#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ ++ ++/* Sector Sizes and population per device model*/ ++#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ ++#define MV_MX25L6405_SECTOR_NUMBER 128 ++#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */ ++ ++#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ ++#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ ++#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ ++#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */ ++#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */ ++#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ ++#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ ++#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ ++#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ ++#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ ++#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ ++#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ ++ ++/* Status Register Write Protect Bit Masks - 4bits */ ++#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++ ++/************************************/ ++/* SPANSION S25FL128P Device Specific */ ++/************************************/ ++ ++/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ ++#define MV_SPANSION_MANF_ID 0x01 ++#define MV_S25FL128_DEVICE_ID 0x2018 ++#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ ++#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ ++#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1 ++ ++/* Sector Sizes and population per device model*/ ++#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */ ++#define MV_S25FL128_SECTOR_NUMBER 64 ++#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */ ++ ++#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ ++#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ ++#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ ++#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */ ++#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */ ++#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ ++#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ ++#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ ++#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ ++#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ ++#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ ++#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ ++ ++/* Status Register Write Protect Bit Masks - 4bits */ ++#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++ ++#endif /* __INCmvSFlashSpecH */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.3 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,576 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "spi/mvSpi.h" ++#include "spi/mvSpiSpec.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* #define MV_DEBUG */ ++#ifdef MV_DEBUG ++#define DB(x) x ++#define mvOsPrintf printf ++#else ++#define DB(x) ++#endif ++ ++ ++/******************************************************************************* ++* mvSpi16bitDataTxRx - Transmt and receive data ++* ++* DESCRIPTION: ++* Tx data and block waiting for data to be transmitted ++* ++********************************************************************************/ ++static MV_STATUS mvSpi16bitDataTxRx (MV_U16 txData, MV_U16 * pRxData) ++{ ++ MV_U32 i; ++ MV_BOOL ready = MV_FALSE; ++ ++ /* First clear the bit in the interrupt cause register */ ++ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); ++ ++ /* Transmit data */ ++ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, MV_16BIT_LE(txData)); ++ ++ /* wait with timeout for memory ready */ ++ for (i=0; i> 8) & 0xFF); ++ ++#elif defined(MV_CPU_BE) ++ ++ /* perform the data write to the buffer in two stages with 8bit each */ ++ MV_U8 * bptr = (MV_U8 *)pRxData; ++ MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); ++ *bptr = ((data >> 8) & 0xFF); ++ ++bptr; ++ *bptr = (data & 0xFF); ++ ++#else ++ #error "CPU endianess isn't defined!\n" ++#endif ++ ++ } ++ else ++ *pRxData = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvSpi8bitDataTxRx - Transmt and receive data (8bits) ++* ++* DESCRIPTION: ++* Tx data and block waiting for data to be transmitted ++* ++********************************************************************************/ ++static MV_STATUS mvSpi8bitDataTxRx (MV_U8 txData, MV_U8 * pRxData) ++{ ++ MV_U32 i; ++ MV_BOOL ready = MV_FALSE; ++ ++ /* First clear the bit in the interrupt cause register */ ++ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); ++ ++ /* Transmit data */ ++ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, txData); ++ ++ /* wait with timeout for memory ready */ ++ for (i=0; i serialBaudRate) ++ continue; ++ ++ /* check for exact fit */ ++ if ((cpuClk / preScale[i]) == serialBaudRate) ++ { ++ bestPrescaleIndx = i; ++ break; ++ } ++ ++ /* check if this is better than the previous one */ ++ if ((serialBaudRate - (cpuClk / preScale[i])) < minBaudOffset) ++ { ++ minBaudOffset = (serialBaudRate - (cpuClk / preScale[i])); ++ bestPrescaleIndx = i; ++ } ++ } ++ ++ if (bestPrescaleIndx > 14) ++ { ++ mvOsPrintf("%s ERROR: SPI baud rate prescale error!\n", __FUNCTION__); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ /* configure the Prescale */ ++ tempReg = MV_REG_READ(MV_SPI_IF_CONFIG_REG); ++ tempReg = ((tempReg & ~MV_SPI_CLK_PRESCALE_MASK) | (bestPrescaleIndx + 0x12)); ++ MV_REG_WRITE(MV_SPI_IF_CONFIG_REG, tempReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSpiCsAssert - Assert the Chip Select pin indicating a new transfer ++* ++* DESCRIPTION: ++* Assert The chip select - used to select an external SPI device ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++********************************************************************************/ ++MV_VOID mvSpiCsAssert(MV_VOID) ++{ ++ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ ++ mvMPPConfigToSPI(); ++ mvOsUDelay(1); ++ MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); ++} ++ ++/******************************************************************************* ++* mvSpiCsDeassert - DeAssert the Chip Select pin indicating the end of a ++* SPI transfer sequence ++* ++* DESCRIPTION: ++* DeAssert the chip select pin ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++********************************************************************************/ ++MV_VOID mvSpiCsDeassert(MV_VOID) ++{ ++ MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); ++ ++ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ ++ mvMPPConfigToDefault(); ++} ++ ++/******************************************************************************* ++* mvSpiRead - Read a buffer over the SPI interface ++* ++* DESCRIPTION: ++* Receive (read) a buffer over the SPI interface in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. Chip select is not ++* handled at this level. ++* ++* INPUT: ++* pRxBuff: Pointer to the buffer to hold the received data ++* buffSize: length of the pRxBuff ++* ++* OUTPUT: ++* pRxBuff: Pointer to the buffer with the received data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 bytesLeft = buffSize; ++ MV_U16* rxPtr = (MV_U16*)pRxBuff; ++ ++ /* check for null parameters */ ++ if (pRxBuff == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check that the buffer pointer and the buffer size are 16bit aligned */ ++ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) ++ { ++ /* Verify that the SPI mode is in 16bit mode */ ++ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX as long we have complete 16bit chunks */ ++ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi16bitDataTxRx(MV_SPI_DUMMY_WRITE_16BITS, rxPtr)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ rxPtr++; ++ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; ++ } ++ ++ } ++ else ++ { ++ /* Verify that the SPI mode is in 8bit mode */ ++ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX in 8bit chanks */ ++ while (bytesLeft > 0) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi8bitDataTxRx(MV_SPI_DUMMY_WRITE_8BITS, pRxBuff)) != MV_OK) ++ return ret; ++ /* increment the pointers */ ++ pRxBuff++; ++ bytesLeft--; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSpiWrite - Transmit a buffer over the SPI interface ++* ++* DESCRIPTION: ++* Transmit a buffer over the SPI interface in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. No chip select ++* action is taken. ++* ++* INPUT: ++* pTxBuff: Pointer to the buffer holding the TX data ++* buffSize: length of the pTxBuff ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiWrite(MV_U8* pTxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 bytesLeft = buffSize; ++ MV_U16* txPtr = (MV_U16*)pTxBuff; ++ ++ /* check for null parameters */ ++ if (pTxBuff == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check that the buffer pointer and the buffer size are 16bit aligned */ ++ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0)) ++ { ++ /* Verify that the SPI mode is in 16bit mode */ ++ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX as long we have complete 16bit chunks */ ++ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi16bitDataTxRx(*txPtr, NULL)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ txPtr++; ++ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; ++ } ++ } ++ else ++ { ++ ++ /* Verify that the SPI mode is in 8bit mode */ ++ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX in 8bit chanks */ ++ while (bytesLeft > 0) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi8bitDataTxRx(*pTxBuff, NULL)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ pTxBuff++; ++ bytesLeft--; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvSpiReadWrite - Read and Write a buffer simultanuosely ++* ++* DESCRIPTION: ++* Transmit and receive a buffer over the SPI in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. The SPI chip ++* select is not handled implicitely. ++* ++* INPUT: ++* pRxBuff: Pointer to the buffer to write the RX info in ++* pTxBuff: Pointer to the buffer holding the TX info ++* buffSize: length of both the pTxBuff and pRxBuff ++* ++* OUTPUT: ++* pRxBuff: Pointer of the buffer holding the RX data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiReadWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 bytesLeft = buffSize; ++ MV_U16* txPtr = (MV_U16*)pTxBuff; ++ MV_U16* rxPtr = (MV_U16*)pRxBuff; ++ ++ /* check for null parameters */ ++ if ((pRxBuff == NULL) || (pTxBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check that the buffer pointer and the buffer size are 16bit aligned */ ++ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) ++ { ++ /* Verify that the SPI mode is in 16bit mode */ ++ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX as long we have complete 16bit chunks */ ++ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi16bitDataTxRx(*txPtr, rxPtr)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ txPtr++; ++ rxPtr++; ++ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; ++ } ++ } ++ else ++ { ++ /* Verify that the SPI mode is in 8bit mode */ ++ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX in 8bit chanks */ ++ while (bytesLeft > 0) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ( (ret = mvSpi8bitDataTxRx(*pTxBuff, pRxBuff) ) != MV_OK) ++ return ret; ++ pRxBuff++; ++ pTxBuff++; ++ bytesLeft--; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,94 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSpihH ++#define __INCmvSpihH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++/* Function Prototypes */ ++/* Init */ ++MV_STATUS mvSpiInit (MV_U32 serialBaudRate); ++ ++/* Set the Frequency of the Spi clock */ ++MV_STATUS mvSpiBaudRateSet(MV_U32 serialBaudRate); ++ ++/* Assert the SPI chip select */ ++MV_VOID mvSpiCsAssert (MV_VOID); ++ ++/* De-assert the SPI chip select */ ++MV_VOID mvSpiCsDeassert (MV_VOID); ++ ++/* Simultanuous Read and write */ ++MV_STATUS mvSpiReadWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); ++ ++/* serialize a buffer on the TX line - Rx is ignored */ ++MV_STATUS mvSpiWrite (MV_U8* pTxBuff, MV_U32 buffSize); ++ ++/* read from the RX line by writing dummy values to the TX line */ ++MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize); ++ ++#endif /* __INCmvSpihH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,249 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "spi/mvSpi.h" ++#include "spi/mvSpiSpec.h" ++ ++/*#define MV_DEBUG*/ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++ ++/******************************************************************************* ++* mvSpiReadAndWrite - Read and Write a buffer simultanuousely ++* ++* DESCRIPTION: ++* Transmit and receive a buffer over the SPI in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. ++* ++* INPUT: ++* pRxBuff: Pointer to the buffer to write the RX info in ++* pTxBuff: Pointer to the buffer holding the TX info ++* buffSize: length of both the pTxBuff and pRxBuff ++* ++* OUTPUT: ++* pRxBuff: Pointer of the buffer holding the RX data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiReadAndWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ ++ /* check for null parameters */ ++ if ((pRxBuff == NULL) || (pTxBuff == NULL) || (buffSize == 0)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* First assert the chip select */ ++ mvSpiCsAssert(); ++ ++ ret = mvSpiReadWrite(pRxBuff, pTxBuff, buffSize); ++ ++ /* Finally deassert the chip select */ ++ mvSpiCsDeassert(); ++ ++ return ret; ++} ++ ++/******************************************************************************* ++* mvSpiWriteThenWrite - Serialize a command followed by the data over the TX line ++* ++* DESCRIPTION: ++* Assert the chip select line. Transmit the command buffer followed by ++* the data buffer. Then deassert the CS line. ++* ++* INPUT: ++* pCmndBuff: Pointer to the command buffer to transmit ++* cmndSize: length of the command size ++* pTxDataBuff: Pointer to the data buffer to transmit ++* txDataSize: length of the data buffer ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, ++ MV_U32 txDataSize) ++{ ++ MV_STATUS ret = MV_OK, tempRet; ++ ++ /* check for null parameters */ ++#ifndef CONFIG_MARVELL ++ if(NULL == pTxDataBuff) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++#endif ++ ++ if (pCmndBuff == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* First assert the chip select */ ++ mvSpiCsAssert(); ++ ++ /* first write the command */ ++ if ((cmndSize) && (pCmndBuff != NULL)) ++ { ++ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Then write the data buffer */ ++#ifndef CONFIG_MARVELL ++ if (txDataSize) ++#else ++ if ((txDataSize) && (pTxDataBuff != NULL)) ++#endif ++ { ++ if ((tempRet = mvSpiWrite(pTxDataBuff, txDataSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Finally deassert the chip select */ ++ mvSpiCsDeassert(); ++ ++ return ret; ++} ++ ++/******************************************************************************* ++* mvSpiWriteThenRead - Serialize a command then read a data buffer ++* ++* DESCRIPTION: ++* Assert the chip select line. Transmit the command buffer then read ++* the data buffer. Then deassert the CS line. ++* ++* INPUT: ++* pCmndBuff: Pointer to the command buffer to transmit ++* cmndSize: length of the command size ++* pRxDataBuff: Pointer to the buffer to read the data in ++* txDataSize: length of the data buffer ++* ++* OUTPUT: ++* pRxDataBuff: Pointer to the buffer holding the data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, ++ MV_U32 rxDataSize,MV_U32 dummyBytesToRead) ++{ ++ MV_STATUS ret = MV_OK, tempRet; ++ MV_U8 dummyByte; ++ ++ /* check for null parameters */ ++ if ((pCmndBuff == NULL) && (pRxDataBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* First assert the chip select */ ++ mvSpiCsAssert(); ++ ++ /* first write the command */ ++ if ((cmndSize) && (pCmndBuff != NULL)) ++ { ++ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Read dummy bytes before real data. */ ++ while(dummyBytesToRead) ++ { ++ mvSpiRead(&dummyByte,1); ++ dummyBytesToRead--; ++ } ++ ++ /* Then write the data buffer */ ++ if ((rxDataSize) && (pRxDataBuff != NULL)) ++ { ++ if ((tempRet = mvSpiRead(pRxDataBuff, rxDataSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Finally deassert the chip select */ ++ mvSpiCsDeassert(); ++ ++ return ret; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,82 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSpiCmndhH ++#define __INCmvSpiCmndhH ++ ++#include "mvTypes.h" ++ ++/* Function Prototypes */ ++ ++/* Simultanuous Read and write */ ++MV_STATUS mvSpiReadAndWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); ++ ++/* write command - write a command and then write data */ ++MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, MV_U32 txDataSize); ++ ++/* read command - write a command and then read data by writing dummy data */ ++MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, ++ MV_U32 rxDataSize,MV_U32 dummyBytesToRead); ++ ++#endif /* __INCmvSpiCmndhH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,98 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSpiSpecH ++#define __INCmvSpiSpecH ++ ++/* Constants */ ++#define MV_SPI_WAIT_RDY_MAX_LOOP 100000 ++#define MV_SPI_16_BIT_CHUNK_SIZE 2 ++#define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF ++#define MV_SPI_DUMMY_WRITE_8BITS 0xFF ++ ++/* Marvell Flash Device Controller Registers */ ++#define MV_SPI_CTRLR_OFST 0x10600 ++#define MV_SPI_IF_CTRL_REG (MV_SPI_CTRLR_OFST + 0x00) ++#define MV_SPI_IF_CONFIG_REG (MV_SPI_CTRLR_OFST + 0x04) ++#define MV_SPI_DATA_OUT_REG (MV_SPI_CTRLR_OFST + 0x08) ++#define MV_SPI_DATA_IN_REG (MV_SPI_CTRLR_OFST + 0x0c) ++#define MV_SPI_INT_CAUSE_REG (MV_SPI_CTRLR_OFST + 0x10) ++#define MV_SPI_INT_CAUSE_MASK_REG (MV_SPI_CTRLR_OFST + 0x14) ++ ++/* Serial Memory Interface Control Register Masks */ ++#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */ ++#define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */ ++#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET) ++#define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET) ++ ++/* Serial Memory Interface Configuration Register Masks */ ++#define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */ ++#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */ ++#define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */ ++#define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET) ++#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET) ++#define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET) ++ ++#endif /* __INCmvSpiSpecH */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.5 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1023 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "mvTwsi.h" ++#include "mvTwsiSpec.h" ++#include "cpu/mvCpu.h" ++ ++ ++/*#define MV_DEBUG*/ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++static MV_VOID twsiIntFlgClr(MV_U8 chanNum); ++static MV_BOOL twsiMainIntGet(MV_U8 chanNum); ++static MV_VOID twsiAckBitSet(MV_U8 chanNum); ++static MV_U32 twsiStsGet(MV_U8 chanNum); ++static MV_VOID twsiReset(MV_U8 chanNum); ++static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); ++static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); ++static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); ++static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); ++static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset,MV_BOOL moreThen256); ++ ++ ++static MV_BOOL twsiTimeoutChk(MV_U32 timeout, const MV_8 *pString) ++{ ++ if(timeout >= TWSI_TIMEOUT_VALUE) ++ { ++ DB(mvOsPrintf("%s",pString)); ++ return MV_TRUE; ++ } ++ return MV_FALSE; ++ ++} ++/******************************************************************************* ++* mvTwsiStartBitSet - Set start bit on the bus ++* ++* DESCRIPTION: ++* This routine sets the start bit on the TWSI bus. ++* The routine first checks for interrupt flag condition, then it sets ++* the start bit in the TWSI Control register. ++* If the interrupt flag condition check previously was set, the function ++* will clear it. ++* The function then wait for the start bit to be cleared by the HW. ++* Then it waits for the interrupt flag to be set and eventually, the ++* TWSI status is checked to be 0x8 or 0x10(repeated start bit). ++* ++* INPUT: ++* chanNum - TWSI channel. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK is start bit was set successfuly on the bus. ++* MV_FAIL if interrupt flag was set before setting start bit. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum) ++{ ++ MV_BOOL isIntFlag = MV_FALSE; ++ MV_U32 timeout, temp; ++ ++ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet \n")); ++ /* check Int flag */ ++ if(twsiMainIntGet(chanNum)) ++ isIntFlag = MV_TRUE; ++ /* set start Bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT); ++ ++ /* in case that the int flag was set before i.e. repeated start bit */ ++ if(isIntFlag){ ++ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet repeated start Bit\n")); ++ twsiIntFlgClr(chanNum); ++ } ++ ++ /* wait for interrupt */ ++ timeout = 0; ++ while(!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n")) ++ return MV_TIMEOUT; ++ ++ ++ /* check that start bit went down */ ++ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0) ++ { ++ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - start bit didn't went down\n"); ++ return MV_FAIL; ++ } ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if(( temp != TWSI_START_CON_TRA ) && ( temp != TWSI_REPEATED_START_CON_TRA )) ++ { ++ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - status %x after Set Start Bit. \n",temp); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvTwsiStopBitSet - Set stop bit on the bus ++* ++* DESCRIPTION: ++* This routine set the stop bit on the TWSI bus. ++* The function then wait for the stop bit to be cleared by the HW. ++* Finally the function checks for status of 0xF8. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE is stop bit was set successfuly on the bus. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum) ++{ ++ MV_U32 timeout, temp; ++ ++ /* Generate stop bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_STOP_BIT); ++ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for stop bit to come down */ ++ timeout = 0; ++ while( ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStopBitSet ERROR - Stop bit TimeOut .\n")) ++ return MV_TIMEOUT; ++ ++ /* check that the stop bit went down */ ++ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) ++ { ++ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - stop bit didn't went down. \n"); ++ return MV_FAIL; ++ } ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if( temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0){ ++ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - status %x after Stop Bit. \n", temp); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiMainIntGet - Get twsi bit from main Interrupt cause. ++* ++* DESCRIPTION: ++* This routine returns the twsi interrupt flag value. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE is interrupt flag is set, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL twsiMainIntGet(MV_U8 chanNum) ++{ ++ MV_U32 temp; ++ ++ /* get the int flag bit */ ++ ++ temp = MV_REG_READ(TWSI_CPU_MAIN_INT_CAUSE_REG); ++ if (temp & (TWSI0_CPU_MAIN_INT_BIT << chanNum)) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++/******************************************************************************* ++* twsiIntFlgClr - Clear Interrupt flag. ++* ++* DESCRIPTION: ++* This routine clears the interrupt flag. It does NOT poll the interrupt ++* to make sure the clear. After clearing the interrupt, it waits for at ++* least 1 miliseconds. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID twsiIntFlgClr(MV_U8 chanNum) ++{ ++ MV_U32 temp; ++ ++ /* wait for 1 mili to prevent TWSI register write after write problems */ ++ mvOsDelay(1); ++ /* clear the int flag bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET)); ++ ++ /* wait for 1 mili sec for the clear to take effect */ ++ mvOsDelay(1); ++ ++ return; ++} ++ ++ ++/******************************************************************************* ++* twsiAckBitSet - Set acknowledge bit on the bus ++* ++* DESCRIPTION: ++* This routine set the acknowledge bit on the TWSI bus. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID twsiAckBitSet(MV_U8 chanNum) ++{ ++ MV_U32 temp; ++ ++ /*Set the Ack bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK); ++ ++ /* Add delay of 1ms */ ++ mvOsDelay(1); ++ return; ++} ++ ++ ++/******************************************************************************* ++* twsiInit - Initialize TWSI interface ++* ++* DESCRIPTION: ++* This routine: ++* -Reset the TWSI. ++* -Initialize the TWSI clock baud rate according to given frequancy ++* parameter based on Tclk frequancy and enables TWSI slave. ++* -Set the ack bit. ++* -Assign the TWSI slave address according to the TWSI address Type. ++* ++* ++* INPUT: ++* chanNum - TWSI channel ++* frequancy - TWSI frequancy in KHz. (up to 100KHZ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Actual frequancy. ++* ++*******************************************************************************/ ++MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable) ++{ ++ MV_U32 n,m,freq,margin,minMargin = 0xffffffff; ++ MV_U32 power; ++ MV_U32 actualFreq = 0,actualN = 0,actualM = 0,val; ++ ++ if(frequancy > 100000) ++ { ++ mvOsPrintf("Warning TWSI frequancy is too high, please use up tp 100Khz. \n"); ++ } ++ ++ DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n",Tclk,frequancy)); ++ /* Calucalte N and M for the TWSI clock baud rate */ ++ for(n = 0 ; n < 8 ; n++) ++ { ++ for(m = 0 ; m < 16 ; m++) ++ { ++ power = 2 << n; /* power = 2^(n+1) */ ++ freq = Tclk/(10*(m+1)*power); ++ margin = MV_ABS(frequancy - freq); ++ if(margin < minMargin) ++ { ++ minMargin = margin; ++ actualFreq = freq; ++ actualN = n; ++ actualM = m; ++ } ++ } ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiInit - actN %d actM %d actFreq %d\n",actualN , actualM, actualFreq)); ++ /* Reset the TWSI logic */ ++ twsiReset(chanNum); ++ ++ /* Set the baud rate */ ++ val = ((actualM<< TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS); ++ MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum),val); ++ ++ /* Enable the TWSI and slave */ ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK); ++ ++ /* set the TWSI slave address */ ++ if( pTwsiAddr->type == ADDR10_BIT )/* 10 Bit deviceAddress */ ++ { ++ /* writing the 2 most significant bits of the 10 bit address*/ ++ val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS ); ++ /* bits 7:3 must be 0x11110 */ ++ val |= TWSI_SLAVE_ADDR_10BIT_CONST; ++ /* set GCE bit */ ++ if(generalCallEnable) ++ val |= TWSI_SLAVE_ADDR_GCE_ENA; ++ /* write slave address */ ++ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum),val); ++ ++ /* writing the 8 least significant bits of the 10 bit address*/ ++ val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK; ++ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val); ++ } ++ else /*7 bit address*/ ++ { ++ /* set the 7 Bits address */ ++ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum),0x0); ++ val = (pTwsiAddr->address << TWSI_SLAVE_ADDR_7BIT_OFFS) & TWSI_SLAVE_ADDR_7BIT_MASK; ++ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val); ++ } ++ ++ /* unmask twsi int */ ++ val = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), val | TWSI_CONTROL_INT_ENA); ++ /* Add delay of 1ms */ ++ mvOsDelay(1); ++ ++ return actualFreq; ++} ++ ++ ++/******************************************************************************* ++* twsiStsGet - Get the TWSI status value. ++* ++* DESCRIPTION: ++* This routine returns the TWSI status value. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 - the TWSI status. ++* ++*******************************************************************************/ ++static MV_U32 twsiStsGet(MV_U8 chanNum) ++{ ++ return MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum)); ++ ++} ++ ++/******************************************************************************* ++* twsiReset - Reset the TWSI. ++* ++* DESCRIPTION: ++* Resets the TWSI logic and sets all TWSI registers to their reset values. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None ++* ++*******************************************************************************/ ++static MV_VOID twsiReset(MV_U8 chanNum) ++{ ++ /* Reset the TWSI logic */ ++ MV_REG_WRITE(TWSI_SOFT_RESET_REG(chanNum),0); ++ ++ /* wait for 2 mili sec */ ++ mvOsDelay(2); ++ ++ return; ++} ++ ++ ++ ++ ++/******************************* POLICY ****************************************/ ++ ++ ++ ++/******************************************************************************* ++* mvTwsiAddrSet - Set address on TWSI bus. ++* ++* DESCRIPTION: ++* This function Set address (7 or 10 Bit address) on the Twsi Bus. ++* ++* INPUT: ++* chanNum - TWSI channel ++* pTwsiAddr - twsi address. ++* command - read / write . ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the address completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *pTwsiAddr, MV_TWSI_CMD command) ++{ ++ DB(mvOsPrintf("TWSI: mvTwsiAddr7BitSet addr %x , type %d, cmd is %s\n",pTwsiAddr->address,\ ++ pTwsiAddr->type, ((command==MV_TWSI_WRITE)?"Write":"Read") )); ++ /* 10 Bit address */ ++ if(pTwsiAddr->type == ADDR10_BIT) ++ { ++ return twsiAddr10BitSet(chanNum, pTwsiAddr->address,command); ++ } ++ /* 7 Bit address */ ++ else ++ { ++ return twsiAddr7BitSet(chanNum, pTwsiAddr->address,command); ++ } ++ ++} ++ ++/******************************************************************************* ++* twsiAddr10BitSet - Set 10 Bit address on TWSI bus. ++* ++* DESCRIPTION: ++* There are two address phases: ++* 1) Write '11110' to data register bits [7:3] and 10-bit address MSB ++* (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1) bit ++* to the Data register. Then it clears interrupt flag which drive ++* the address on the TWSI bus. The function then waits for interrupt ++* flag to be active and status 0x18 (write) or 0x40 (read) to be set. ++* 2) write the rest of 10-bit address to data register and clears ++* interrupt flag which drive the address on the TWSI bus. The ++* function then waits for interrupt flag to be active and status ++* 0xD0 (write) or 0xE0 (read) to be set. ++* ++* INPUT: ++* chanNum - TWSI channel ++* deviceAddress - twsi address. ++* command - read / write . ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the address completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) ++{ ++ MV_U32 val,timeout; ++ ++ /* writing the 2 most significant bits of the 10 bit address*/ ++ val = ((deviceAddress & TWSI_DATA_ADDR_10BIT_MASK) >> TWSI_DATA_ADDR_10BIT_OFFS ); ++ /* bits 7:3 must be 0x11110 */ ++ val |= TWSI_DATA_ADDR_10BIT_CONST; ++ /* set command */ ++ val |= command; ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); ++ /* WA add a delay */ ++ mvOsDelay(1); ++ ++ /* clear Int flag */ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 1st addr (10Bit) Int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ val = twsiStsGet(chanNum); ++ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || ++ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) ++ { ++ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 1st addr (10 Bit) in %s mode.\n"\ ++ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); ++ return MV_FAIL; ++ } ++ ++ /* set 8 LSB of the address */ ++ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); ++ ++ /* clear Int flag */ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 2nd (10 Bit) Int TimOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ val = twsiStsGet(chanNum); ++ if(( (val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || ++ ( (val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) ++ { ++ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 2nd addr(10 Bit) in %s mode.\n"\ ++ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiAddr7BitSet - Set 7 Bit address on TWSI bus. ++* ++* DESCRIPTION: ++* This function writes 7 bit address plus a write or read bit to the ++* Data register. Then it clears interrupt flag which drive the address on ++* the TWSI bus. The function then waits for interrupt flag to be active ++* and status 0x18 (write) or 0x40 (read) to be set. ++* ++* INPUT: ++* chanNum - TWSI channel ++* deviceAddress - twsi address. ++* command - read / write . ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the address completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) ++{ ++ MV_U32 val,timeout; ++ ++ /* set the address */ ++ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; ++ /* set command */ ++ val |= command; ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); ++ /* WA add a delay */ ++ mvOsDelay(1); ++ ++ /* clear Int flag */ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr7BitSet ERROR - Addr (7 Bit) int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ val = twsiStsGet(chanNum); ++ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || ++ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) ++ { ++ /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't ++ want error messeges in case DIMM doesn't exist. */ ++ DB(mvOsPrintf("TWSI: twsiAddr7BitSet ERROR - status %x addr (7 Bit) in %s mode.\n"\ ++ ,val,((command==MV_TWSI_WRITE)?"Write":"Read") )); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiDataWrite - Trnasmit a data block over TWSI bus. ++* ++* DESCRIPTION: ++* This function writes a given data block to TWSI bus in 8 bit granularity. ++* first The function waits for interrupt flag to be active then ++* For each 8-bit data: ++* The function writes data to data register. It then clears ++* interrupt flag which drives the data on the TWSI bus. ++* The function then waits for interrupt flag to be active and status ++* 0x28 to be set. ++* ++* ++* INPUT: ++* chanNum - TWSI channel ++* pBlock - Data block. ++* blockSize - number of chars in pBlock. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if transmiting the block completed succesfully, ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ MV_U32 timeout, temp, blockSizeWr = blockSize; ++ ++ if(NULL == pBlock) ++ return MV_BAD_PARAM; ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ while(blockSizeWr) ++ { ++ /* write the data*/ ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum),(MV_U32)*pBlock); ++ DB(mvOsPrintf("TWSI: twsiDataTransmit place = %d write %x \n",\ ++ blockSize - blockSizeWr, *pBlock)); ++ pBlock++; ++ blockSizeWr--; ++ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if(temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC) ++ { ++ mvOsPrintf("TWSI: twsiDataTransmit ERROR - status %x in write trans\n",temp); ++ return MV_FAIL; ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiDataReceive - Receive data block from TWSI bus. ++* ++* DESCRIPTION: ++* This function receive data block from TWSI bus in 8bit granularity ++* into pBlock buffer. ++* first The function waits for interrupt flag to be active then ++* For each 8-bit data: ++* It clears the interrupt flag which allows the next data to be ++* received from TWSI bus. ++* The function waits for interrupt flag to be active, ++* and status reg is 0x50. ++* Then the function reads data from data register, and copies it to ++* the given buffer. ++* ++* INPUT: ++* chanNum - TWSI channel ++* blockSize - number of bytes to read. ++* ++* OUTPUT: ++* pBlock - Data block. ++* ++* RETURN: ++* MV_OK - if receive transaction completed succesfully, ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ MV_U32 timeout, temp, blockSizeRd = blockSize; ++ if(NULL == pBlock) ++ return MV_BAD_PARAM; ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data int Time out .\n")) ++ return MV_TIMEOUT; ++ ++ while(blockSizeRd) ++ { ++ if(blockSizeRd == 1) ++ { ++ /* clear ack and Int flag */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ temp &= ~(TWSI_CONTROL_ACK); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp); ++ } ++ twsiIntFlgClr(chanNum); ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( (!twsiMainIntGet(chanNum)) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data Int Time out .\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if((temp != TWSI_M_REC_RD_DATA_ACK_TRA) && (blockSizeRd !=1)) ++ { ++ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in read trans \n",temp); ++ return MV_FAIL; ++ } ++ else if((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) && (blockSizeRd ==1)) ++ { ++ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in Rd Terminate\n",temp); ++ return MV_FAIL; ++ } ++ ++ /* read the data*/ ++ *pBlock = (MV_U8)MV_REG_READ(TWSI_DATA_REG(chanNum)); ++ DB(mvOsPrintf("TWSI: twsiDataReceive place %d read %x \n",\ ++ blockSize - blockSizeRd,*pBlock)); ++ pBlock++; ++ blockSizeRd--; ++ } ++ ++ return MV_OK; ++} ++ ++ ++ ++/******************************************************************************* ++* twsiTargetOffsSet - Set TWST target offset on TWSI bus. ++* ++* DESCRIPTION: ++* The function support TWSI targets that have inside address space (for ++* example EEPROMs). The function: ++* 1) Convert the given offset into pBlock and size. ++* in case the offset should be set to a TWSI slave which support ++* more then 256 bytes offset, the offset setting will be done ++* in 2 transactions. ++* 2) Use twsiDataTransmit to place those on the bus. ++* ++* INPUT: ++* chanNum - TWSI channel ++* offset - offset to be set on the EEPROM device. ++* moreThen256 - whether the EEPROM device support more then 256 byte offset. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the offset completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset, MV_BOOL moreThen256) ++{ ++ MV_U8 offBlock[2]; ++ MV_U32 offSize; ++ ++ if(moreThen256 == MV_TRUE) ++ { ++ offBlock[0] = (offset >> 8) & 0xff; ++ offBlock[1] = offset & 0xff; ++ offSize = 2; ++ } ++ else ++ { ++ offBlock[0] = offset & 0xff; ++ offSize = 1; ++ } ++ DB(mvOsPrintf("TWSI: twsiTargetOffsSet offSize = %x addr1 = %x addr2 = %x\n",\ ++ offSize,offBlock[0],offBlock[1])); ++ return twsiDataTransmit(chanNum, offBlock, offSize); ++ ++} ++ ++/******************************************************************************* ++* mvTwsiRead - Read data block from a TWSI Slave. ++* ++* DESCRIPTION: ++* The function calls the following functions: ++* -) mvTwsiStartBitSet(); ++* if(EEPROM device) ++* -) mvTwsiAddrSet(w); ++* -) twsiTargetOffsSet(); ++* -) mvTwsiStartBitSet(); ++* -) mvTwsiAddrSet(r); ++* -) twsiDataReceive(); ++* -) mvTwsiStopBitSet(); ++* ++* INPUT: ++* chanNum - TWSI channel ++* pTwsiSlave - Twsi Slave structure. ++* blockSize - number of bytes to read. ++* ++* OUTPUT: ++* pBlock - Data block. ++* ++* RETURN: ++* MV_OK - if EEPROM read transaction completed succesfully, ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiRead(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ if((NULL == pBlock) || (NULL == pTwsiSlave)) ++ return MV_BAD_PARAM; ++ if(MV_OK != mvTwsiStartBitSet(chanNum)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); ++ ++ /* in case offset exsist (i.e. eeprom ) */ ++ if(MV_TRUE == pTwsiSlave->validOffset) ++ { ++ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); ++ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiTargetOffsSet\n")); ++ if(MV_OK != mvTwsiStartBitSet(chanNum)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); ++ } ++ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_READ)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); ++ if(MV_OK != twsiDataReceive(chanNum, pBlock, blockSize)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiDataReceive\n")); ++ ++ if(MV_OK != mvTwsiStopBitSet(chanNum)) ++ { ++ return MV_FAIL; ++ } ++ ++ twsiAckBitSet(chanNum); ++ ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStopBitSet\n")); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTwsiWrite - Write data block to a TWSI Slave. ++* ++* DESCRIPTION: ++* The function calls the following functions: ++* -) mvTwsiStartBitSet(); ++* -) mvTwsiAddrSet(); ++* -)if(EEPROM device) ++* -) twsiTargetOffsSet(); ++* -) twsiDataTransmit(); ++* -) mvTwsiStopBitSet(); ++* ++* INPUT: ++* chanNum - TWSI channel ++* eepromAddress - eeprom address. ++* blockSize - number of bytes to write. ++* pBlock - Data block. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_OK - if EEPROM read transaction completed succesfully. ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++* NOTE: Part of the EEPROM, required that the offset will be aligned to the ++* max write burst supported. ++*******************************************************************************/ ++MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ if((NULL == pBlock) || (NULL == pTwsiSlave)) ++ return MV_BAD_PARAM; ++ ++ if(MV_OK != mvTwsiStartBitSet(chanNum)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStartBitSet\n")); ++ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI :mvTwsiEepromWrite after mvTwsiAddrSet\n")); ++ ++ /* in case offset exsist (i.e. eeprom ) */ ++ if(MV_TRUE == pTwsiSlave->validOffset) ++ { ++ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiTargetOffsSet\n")); ++ } ++ if(MV_OK != twsiDataTransmit(chanNum, pBlock, blockSize)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiDataTransmit\n")); ++ if(MV_OK != mvTwsiStopBitSet(chanNum)) ++ { ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStopBitSet\n")); ++ ++ return MV_OK; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,121 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCmvTwsiH ++#define __INCmvTwsiH ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* need to update this includes */ ++#include "twsi/mvTwsiSpec.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++ ++/* The TWSI interface supports both 7-bit and 10-bit addressing. */ ++/* This enumerator describes addressing type. */ ++typedef enum _mvTwsiAddrType ++{ ++ ADDR7_BIT, /* 7 bit address */ ++ ADDR10_BIT /* 10 bit address */ ++}MV_TWSI_ADDR_TYPE; ++ ++/* This structure describes TWSI address. */ ++typedef struct _mvTwsiAddr ++{ ++ MV_U32 address; /* address */ ++ MV_TWSI_ADDR_TYPE type; /* Address type */ ++}MV_TWSI_ADDR; ++ ++/* This structure describes a TWSI slave. */ ++typedef struct _mvTwsiSlave ++{ ++ MV_TWSI_ADDR slaveAddr; ++ MV_BOOL validOffset; /* whether the slave has offset (i.e. Eeprom etc.) */ ++ MV_U32 offset; /* offset in the slave. */ ++ MV_BOOL moreThen256; /* whether the ofset is bigger then 256 */ ++}MV_TWSI_SLAVE; ++ ++/* This enumerator describes TWSI protocol commands. */ ++typedef enum _mvTwsiCmd ++{ ++ MV_TWSI_WRITE, /* TWSI write command - 0 according to spec */ ++ MV_TWSI_READ /* TWSI read command - 1 according to spec */ ++}MV_TWSI_CMD; ++ ++MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum); ++MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum); ++MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *twsiAddr, MV_TWSI_CMD command); ++ ++MV_U32 mvTwsiInit(MV_U8 chanNum, MV_KHZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *twsiAddr, MV_BOOL generalCallEnable); ++MV_STATUS mvTwsiRead (MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); ++MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); ++ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvTwsiH */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,457 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#define MV_ASMLANGUAGE ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "boardEnv/mvBoardEnvSpec.h" ++#include "mvOsAsm.h" ++#include "mvTwsiSpec.h" ++#include "mvSysHwConfig.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++#include "mvCommon.h" ++ ++#define I2C_CH MV_BOARD_DIMM_I2C_CHANNEL ++ ++/* defines */ ++/* defines */ ++ ++ ++ .data ++ .global _i2cInit ++ .global _i2cRead ++ ++ .text ++ ++/******************************************************************************* ++* _i2cInit - Initialize TWSI interface ++* ++* DESCRIPTION: ++* The function performs TWSI interface initialization. It resets the ++* TWSI state machine and initialize its clock to 100KHz assuming Tclock ++* of 133MHz. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++_i2cInit: ++ mov r9, LR /* Save link register */ ++ mov r0, #0 /* Make sure r0 is zero */ ++ ++ /* Reset the i2c Mechanism first */ ++ MV_REG_WRITE_ASM (r0, r1, TWSI_SOFT_RESET_REG(I2C_CH)) ++ ++ bl _twsiDelay ++ bl _twsiDelay ++ ++ /* Initializing the I2C mechanism. Assuming Tclock frequency */ ++ /* of 166MHz. The I2C frequency in that case will be 100KHz. */ ++ /* For this settings, M = 9 and N = 3. Set the baud-rate with the */ ++ /* value of 0x2b (freq of ==> 100KHz */ ++ /* see spec for more details about the calculation of this value) */ ++ mov r6, #(9 << 3 | 3) ++ MV_REG_WRITE_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ ++ /* Enable the I2C master */ ++ /* Enable TWSI interrupt in main mask reg */ ++ mov r6, #0xC4 ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ ++ /* Let the slow TWSI machine get used to the idea that it is enabled */ ++ bl _twsiDelay ++ ++ ++ mov PC, r9 /* r9 is saved link register */ ++ ++/******************************************************************************* ++* _twsiDelay - Perform delay. ++* ++* DESCRIPTION: ++* The function performs a delay to enable TWSI logic to stable. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++_twsiDelay: ++ mov r10, #0x100000 /*was 0x400*/ ++ ++_twsiDelayLoop: ++ subs r10, r10, #1 ++ bne _twsiDelayLoop ++ ++ mov PC, LR ++ ++/******************************************************************************* ++* _i2cRead - Read byte from I2C EEPROM device. ++* ++* DESCRIPTION: ++* The function returns a byte from I2C EEPROM device. ++* The EEPROM device is 7-bit address type. ++* ++* INPUT: ++* r4 has the DIMM0 base address with shift 1 bit to the left ++* r7 has the EEPROM offset ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* r4 returns '0' if address can not be read. ++* r7 has byte value in case read is successful. ++* ++*******************************************************************************/ ++_i2cRead: ++ mov r9, LR /* Save link register */ ++ ++ /* Transmit the device address and desired offset within the EEPROM. */ ++ ++ /* Generate Start Bit */ ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ orr r6, r6, #TWSI_CONTROL_START_BIT ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ ++ /* Wait for the interrupt flag (bit3) to be set */ ++ mov r10, #0x50000 ++loop_1: ++ subs r10, r10, #1 ++ beq loop_1_timeout ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_1 ++ ++loop_1_timeout: ++ ++ /* Wait for the start bit to be reset by HW */ ++ mov r10, #0x50000 ++loop_2: ++ subs r10, r10, #1 ++ beq loop_2_timeout ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ tst r6, #TWSI_CONTROL_START_BIT ++ bne loop_2 ++ ++loop_2_timeout: ++ ++ /* Wait for the status TWSI_START_CONDITION_TRA = 0x8 */ ++ mov r10, #0x50000 ++loop_3: ++ subs r10, r10, #1 ++ beq loop_3_timeout ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x08 ++ bne loop_3 ++ ++loop_3_timeout: ++ ++ /* writing the address of (DIMM0/1 << 1) with write indication */ ++ mov r6, r4, LSL #1 /* Write operation address bit 0 must be 0 */ ++ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ bl _twsiDelay ++ /* Clear the interrupt flag */ ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Waiting for the interrupt flag to be set which means that the ++ address has been transmitted */ ++loop_4: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_4 /* if tst = 0, then the bit is not set yet */ ++ ++ /* Wait for status TWSI_ADDR_PLUS_WRITE_BIT_TRA_ACK_REC = 0x18 */ ++ mov r10, #0x50000 /* Set r10 to 0x50000 =~ 328,000 */ ++ ++loop_5: ++ subs r10, r10, #1 /* timeout count down */ ++ bne testStatus ++ mov r4, #0 /* r4 = 0 -> operation failed */ ++ b exit_i2cRead /* Exit if timeout (No DIMM) */ ++ ++testStatus: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x18 ++ bne loop_5 ++ ++ ++ /* check if the offset is bigger than 256 byte*/ ++ tst r7, #0x80000000 ++ bne great_than_256 ++ ++ /* Write the offset to be read from the DIMM EEPROM */ ++ MV_REG_WRITE_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ b after_offset ++ ++great_than_256: ++ mov r10, r7, LSR #8 ++ and r10, r10, #0xff ++ /* Write the offset0 to be read from the EEPROM */ ++ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ /* Clear the interrupt flag ==> signaling that the address can now ++ be transmited */ ++ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt to be set again ==> address has transmited */ ++loop_6_1: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_6_1 ++ ++ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ ++loop_7_1: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x28 ++ bne loop_7_1 ++ ++ ++ mov r10, r7 ++ and r10, r10, #0xff ++ /* Write the offset1 to be read from the EEPROM */ ++ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ ++ ++after_offset: ++ ++ /* Clear the interrupt flag ==> signaling that the address can now ++ be transmited */ ++ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt to be set again ==> address has transmited */ ++loop_6: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_6 ++ ++ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ ++loop_7: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x28 ++ bne loop_7 ++ ++ /* Retransmit the device address with read indication to get the data */ ++ ++ /* generate a repeated start bit */ ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ orr r6, r6, #TWSI_CONTROL_START_BIT ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ ++ ++ /* Clear the interrupt flag ==> the start bit will be transmitted. */ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt flag (bit3) to be set */ ++loop_9: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_9 ++ ++ /* Wait for the start bit to be reset by HW */ ++loop_8: ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ tst r6, #TWSI_CONTROL_START_BIT ++ bne loop_8 ++ ++ /* Wait for status TWSI_REPEATED_START_CONDITION_TRA = 0x10 */ ++loop_10: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x10 ++ bne loop_10 ++ ++ /* Writing the address of (DIMM0<<1) with read indication (bit0 is 1) */ ++ mov r6, r4, LSL #1 ++ orr r6, r6, #1 /* Read operation address bit 0 must be 1 */ ++ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ /* Clear the interrupt flag ==> the address will be transmitted */ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt flag (bit3) to be set as a result of ++ transmitting the address. */ ++loop_11: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_11 ++ ++ /* Wait for status TWSI_ADDR_PLUS_READ_BIT_TRA_ACK_REC = 0x40 */ ++loop_12: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x40 ++ bne loop_12 ++ ++ /* Clear the interrupt flag and the Acknoledge bit */ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #(TWSI_CONTROL_INT_FLAG_SET | TWSI_CONTROL_ACK) ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt flag (bit3) to be set */ ++loop_14: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_14 ++ ++ /* Wait for status TWSI_MAS_REC_READ_DATA_ACK_NOT_TRA = 0x58 */ ++loop_15: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x58 ++ bne loop_15 ++ ++ /* Store the data in r7. */ ++ MV_REG_READ_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ /* Generate stop bit */ ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ orr r6, r6, #TWSI_CONTROL_STOP_BIT ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ ++ ++ /* Clear the interrupt flag */ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the stop bit to be reset by HW */ ++loop_16: ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ tst r6, #TWSI_CONTROL_INT_FLAG_SET ++ bne loop_16 ++ ++exit_i2cRead: ++ mov PC, r9 /* r9 is saved link register */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,160 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++/****************************************/ ++/* TWSI Registers */ ++/****************************************/ ++#ifndef __INCmvTwsiSpech ++#define __INCmvTwsiSpech ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* defines */ ++#define TWSI_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum)+ 0x00) ++ ++#define TWSI_SLAVE_ADDR_GCE_ENA BIT0 ++#define TWSI_SLAVE_ADDR_7BIT_OFFS 0x1 ++#define TWSI_SLAVE_ADDR_7BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7BIT_OFFS) ++#define TWSI_SLAVE_ADDR_10BIT_OFFS 0x7 ++#define TWSI_SLAVE_ADDR_10BIT_MASK 0x300 ++#define TWSI_SLAVE_ADDR_10BIT_CONST 0xF0 ++ ++ ++#define TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x10) ++#define TWSI_EXTENDED_SLAVE_OFFS 0 ++#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS) ++ ++ ++#define TWSI_DATA_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x04) ++#define TWSI_DATA_COMMAND_OFFS 0x0 ++#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS) ++#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS) ++#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS) ++#define TWSI_DATA_ADDR_7BIT_OFFS 0x1 ++#define TWSI_DATA_ADDR_7BIT_MASK (0xFF << TWSI_DATA_ADDR_7BIT_OFFS) ++#define TWSI_DATA_ADDR_10BIT_OFFS 0x7 ++#define TWSI_DATA_ADDR_10BIT_MASK 0x300 ++#define TWSI_DATA_ADDR_10BIT_CONST 0xF0 ++ ++ ++#define TWSI_CONTROL_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x08) ++#define TWSI_CONTROL_ACK BIT2 ++#define TWSI_CONTROL_INT_FLAG_SET BIT3 ++#define TWSI_CONTROL_STOP_BIT BIT4 ++#define TWSI_CONTROL_START_BIT BIT5 ++#define TWSI_CONTROL_ENA BIT6 ++#define TWSI_CONTROL_INT_ENA BIT7 ++ ++ ++#define TWSI_STATUS_BAUDE_RATE_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x0c) ++#define TWSI_BAUD_RATE_N_OFFS 0 ++#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS) ++#define TWSI_BAUD_RATE_M_OFFS 3 ++#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS) ++ ++#define TWSI_SOFT_RESET_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x1c) ++ ++/* defines */ ++#define TWSI_TIMEOUT_VALUE 0x500 ++ ++/* TWSI status codes */ ++#define TWSI_BUS_ERROR 0x00 ++#define TWSI_START_CON_TRA 0x08 ++#define TWSI_REPEATED_START_CON_TRA 0x10 ++#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18 ++#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20 ++#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28 ++#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30 ++#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38 ++#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40 ++#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48 ++#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50 ++#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58 ++#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60 ++#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68 ++#define TWSI_GNL_CALL_REC_ACK_TRA 0x70 ++#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98 ++#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0 ++#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8 ++#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0 ++#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8 ++#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0 ++#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8 ++#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0 ++#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8 ++#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0 ++#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8 ++#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8 ++ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvTwsiSpech */ +diff -Nur linux-3.0.4.orig/crypto/ocf/ocf-bench.c linux-3.0.4/crypto/ocf/ocf-bench.c +--- linux-3.0.4.orig/crypto/ocf/ocf-bench.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ocf-bench.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,514 @@ ++/* ++ * A loadable module that benchmarks the OCF crypto speed from kernel space. ++ * ++ * Copyright (C) 2004-2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef I_HAVE_AN_XSCALE_WITH_INTEL_SDK ++#define BENCH_IXP_ACCESS_LIB 1 ++#endif ++#ifdef BENCH_IXP_ACCESS_LIB ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++/* ++ * support for access lib version 1.4 ++ */ ++#ifndef IX_MBUF_PRIV ++#define IX_MBUF_PRIV(x) ((x)->priv) ++#endif ++ ++/* ++ * the number of simultaneously active requests ++ */ ++static int request_q_len = 40; ++module_param(request_q_len, int, 0); ++MODULE_PARM_DESC(request_q_len, "Number of outstanding requests"); ++ ++/* ++ * how many requests we want to have processed ++ */ ++static int request_num = 1024; ++module_param(request_num, int, 0); ++MODULE_PARM_DESC(request_num, "run for at least this many requests"); ++ ++/* ++ * the size of each request ++ */ ++static int request_size = 1488; ++module_param(request_size, int, 0); ++MODULE_PARM_DESC(request_size, "size of each request"); ++ ++/* ++ * OCF batching of requests ++ */ ++static int request_batch = 1; ++module_param(request_batch, int, 0); ++MODULE_PARM_DESC(request_batch, "enable OCF request batching"); ++ ++/* ++ * OCF immediate callback on completion ++ */ ++static int request_cbimm = 1; ++module_param(request_cbimm, int, 0); ++MODULE_PARM_DESC(request_cbimm, "enable OCF immediate callback on completion"); ++ ++/* ++ * a structure for each request ++ */ ++typedef struct { ++ struct work_struct work; ++#ifdef BENCH_IXP_ACCESS_LIB ++ IX_MBUF mbuf; ++#endif ++ unsigned char *buffer; ++} request_t; ++ ++static request_t *requests; ++ ++static spinlock_t ocfbench_counter_lock; ++static int outstanding; ++static int total; ++ ++/*************************************************************************/ ++/* ++ * OCF benchmark routines ++ */ ++ ++static uint64_t ocf_cryptoid; ++static unsigned long jstart, jstop; ++ ++static int ocf_init(void); ++static int ocf_cb(struct cryptop *crp); ++static void ocf_request(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ocf_request_wq(struct work_struct *work); ++#endif ++ ++static int ++ocf_init(void) ++{ ++ int error; ++ struct cryptoini crie, cria; ++ struct cryptodesc crda, crde; ++ ++ memset(&crie, 0, sizeof(crie)); ++ memset(&cria, 0, sizeof(cria)); ++ memset(&crde, 0, sizeof(crde)); ++ memset(&crda, 0, sizeof(crda)); ++ ++ cria.cri_alg = CRYPTO_SHA1_HMAC; ++ cria.cri_klen = 20 * 8; ++ cria.cri_key = "0123456789abcdefghij"; ++ ++ //crie.cri_alg = CRYPTO_3DES_CBC; ++ crie.cri_alg = CRYPTO_AES_CBC; ++ crie.cri_klen = 24 * 8; ++ crie.cri_key = "0123456789abcdefghijklmn"; ++ ++ crie.cri_next = &cria; ++ ++ error = crypto_newsession(&ocf_cryptoid, &crie, ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE); ++ if (error) { ++ printk("crypto_newsession failed %d\n", error); ++ return -1; ++ } ++ return 0; ++} ++ ++static int ++ocf_cb(struct cryptop *crp) ++{ ++ request_t *r = (request_t *) crp->crp_opaque; ++ unsigned long flags; ++ ++ if (crp->crp_etype) ++ printk("Error in OCF processing: %d\n", crp->crp_etype); ++ crypto_freereq(crp); ++ crp = NULL; ++ ++ /* do all requests but take at least 1 second */ ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ total++; ++ if (total > request_num && jstart + HZ < jiffies) { ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return 0; ++ } ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ ++ schedule_work(&r->work); ++ return 0; ++} ++ ++ ++static void ++ocf_request(void *arg) ++{ ++ request_t *r = arg; ++ struct cryptop *crp = crypto_getreq(2); ++ struct cryptodesc *crde, *crda; ++ unsigned long flags; ++ ++ if (!crp) { ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return; ++ } ++ ++ crde = crp->crp_desc; ++ crda = crde->crd_next; ++ ++ crda->crd_skip = 0; ++ crda->crd_flags = 0; ++ crda->crd_len = request_size; ++ crda->crd_inject = request_size; ++ crda->crd_alg = CRYPTO_SHA1_HMAC; ++ crda->crd_key = "0123456789abcdefghij"; ++ crda->crd_klen = 20 * 8; ++ ++ crde->crd_skip = 0; ++ crde->crd_flags = CRD_F_IV_EXPLICIT | CRD_F_ENCRYPT; ++ crde->crd_len = request_size; ++ crde->crd_inject = request_size; ++ //crde->crd_alg = CRYPTO_3DES_CBC; ++ crde->crd_alg = CRYPTO_AES_CBC; ++ crde->crd_key = "0123456789abcdefghijklmn"; ++ crde->crd_klen = 24 * 8; ++ ++ crp->crp_ilen = request_size + 64; ++ crp->crp_flags = 0; ++ if (request_batch) ++ crp->crp_flags |= CRYPTO_F_BATCH; ++ if (request_cbimm) ++ crp->crp_flags |= CRYPTO_F_CBIMM; ++ crp->crp_buf = (caddr_t) r->buffer; ++ crp->crp_callback = ocf_cb; ++ crp->crp_sid = ocf_cryptoid; ++ crp->crp_opaque = (caddr_t) r; ++ crypto_dispatch(crp); ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ocf_request_wq(struct work_struct *work) ++{ ++ request_t *r = container_of(work, request_t, work); ++ ocf_request(r); ++} ++#endif ++ ++static void ++ocf_done(void) ++{ ++ crypto_freesession(ocf_cryptoid); ++} ++ ++/*************************************************************************/ ++#ifdef BENCH_IXP_ACCESS_LIB ++/*************************************************************************/ ++/* ++ * CryptoAcc benchmark routines ++ */ ++ ++static IxCryptoAccCtx ixp_ctx; ++static UINT32 ixp_ctx_id; ++static IX_MBUF ixp_pri; ++static IX_MBUF ixp_sec; ++static int ixp_registered = 0; ++ ++static void ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, ++ IxCryptoAccStatus status); ++static void ixp_perform_cb(UINT32 ctx_id, IX_MBUF *sbufp, IX_MBUF *dbufp, ++ IxCryptoAccStatus status); ++static void ixp_request(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ixp_request_wq(struct work_struct *work); ++#endif ++ ++static int ++ixp_init(void) ++{ ++ IxCryptoAccStatus status; ++ ++ ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; ++ ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp_ctx.cipherCtx.cipherKeyLen = 24; ++ ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp_ctx.cipherCtx.cipherInitialVectorLen = IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp_ctx.cipherCtx.key.cipherKey, "0123456789abcdefghijklmn", 24); ++ ++ ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; ++ ixp_ctx.authCtx.authDigestLen = 12; ++ ixp_ctx.authCtx.aadLen = 0; ++ ixp_ctx.authCtx.authKeyLen = 20; ++ memcpy(ixp_ctx.authCtx.key.authKey, "0123456789abcdefghij", 20); ++ ++ ixp_ctx.useDifferentSrcAndDestMbufs = 0; ++ ixp_ctx.operation = IX_CRYPTO_ACC_OP_ENCRYPT_AUTH ; ++ ++ IX_MBUF_MLEN(&ixp_pri) = IX_MBUF_PKT_LEN(&ixp_pri) = 128; ++ IX_MBUF_MDATA(&ixp_pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ IX_MBUF_MLEN(&ixp_sec) = IX_MBUF_PKT_LEN(&ixp_sec) = 128; ++ IX_MBUF_MDATA(&ixp_sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ ++ status = ixCryptoAccCtxRegister(&ixp_ctx, &ixp_pri, &ixp_sec, ++ ixp_register_cb, ixp_perform_cb, &ixp_ctx_id); ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) { ++ while (!ixp_registered) ++ schedule(); ++ return ixp_registered < 0 ? -1 : 0; ++ } ++ ++ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); ++ return -1; ++} ++ ++static void ++ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) ++{ ++ if (bufp) { ++ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; ++ kfree(IX_MBUF_MDATA(bufp)); ++ IX_MBUF_MDATA(bufp) = NULL; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_WAIT == status) ++ return; ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ ixp_registered = 1; ++ else ++ ixp_registered = -1; ++} ++ ++static void ++ixp_perform_cb( ++ UINT32 ctx_id, ++ IX_MBUF *sbufp, ++ IX_MBUF *dbufp, ++ IxCryptoAccStatus status) ++{ ++ request_t *r = NULL; ++ unsigned long flags; ++ ++ /* do all requests but take at least 1 second */ ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ total++; ++ if (total > request_num && jstart + HZ < jiffies) { ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return; ++ } ++ ++ if (!sbufp || !(r = IX_MBUF_PRIV(sbufp))) { ++ printk("crappo %p %p\n", sbufp, r); ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return; ++ } ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ ++ schedule_work(&r->work); ++} ++ ++static void ++ixp_request(void *arg) ++{ ++ request_t *r = arg; ++ IxCryptoAccStatus status; ++ unsigned long flags; ++ ++ memset(&r->mbuf, 0, sizeof(r->mbuf)); ++ IX_MBUF_MLEN(&r->mbuf) = IX_MBUF_PKT_LEN(&r->mbuf) = request_size + 64; ++ IX_MBUF_MDATA(&r->mbuf) = r->buffer; ++ IX_MBUF_PRIV(&r->mbuf) = r; ++ status = ixCryptoAccAuthCryptPerform(ixp_ctx_id, &r->mbuf, NULL, ++ 0, request_size, 0, request_size, request_size, r->buffer); ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("status1 = %d\n", status); ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return; ++ } ++ return; ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_request_wq(struct work_struct *work) ++{ ++ request_t *r = container_of(work, request_t, work); ++ ixp_request(r); ++} ++#endif ++ ++static void ++ixp_done(void) ++{ ++ /* we should free the session here but I am lazy :-) */ ++} ++ ++/*************************************************************************/ ++#endif /* BENCH_IXP_ACCESS_LIB */ ++/*************************************************************************/ ++ ++int ++ocfbench_init(void) ++{ ++ int i; ++ unsigned long mbps; ++ unsigned long flags; ++ ++ printk("Crypto Speed tests\n"); ++ ++ requests = kmalloc(sizeof(request_t) * request_q_len, GFP_KERNEL); ++ if (!requests) { ++ printk("malloc failed\n"); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < request_q_len; i++) { ++ /* +64 for return data */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&requests[i].work, ocf_request_wq); ++#else ++ INIT_WORK(&requests[i].work, ocf_request, &requests[i]); ++#endif ++ requests[i].buffer = kmalloc(request_size + 128, GFP_DMA); ++ if (!requests[i].buffer) { ++ printk("malloc failed\n"); ++ return -EINVAL; ++ } ++ memset(requests[i].buffer, '0' + i, request_size + 128); ++ } ++ ++ /* ++ * OCF benchmark ++ */ ++ printk("OCF: testing ...\n"); ++ if (ocf_init() == -1) ++ return -EINVAL; ++ ++ spin_lock_init(&ocfbench_counter_lock); ++ total = outstanding = 0; ++ jstart = jiffies; ++ for (i = 0; i < request_q_len; i++) { ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ outstanding++; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ ocf_request(&requests[i]); ++ } ++ while (outstanding > 0) ++ schedule(); ++ jstop = jiffies; ++ ++ mbps = 0; ++ if (jstop > jstart) { ++ mbps = (unsigned long) total * (unsigned long) request_size * 8; ++ mbps /= ((jstop - jstart) * 1000) / HZ; ++ } ++ printk("OCF: %d requests of %d bytes in %d jiffies (%d.%03d Mbps)\n", ++ total, request_size, (int)(jstop - jstart), ++ ((int)mbps) / 1000, ((int)mbps) % 1000); ++ ocf_done(); ++ ++#ifdef BENCH_IXP_ACCESS_LIB ++ /* ++ * IXP benchmark ++ */ ++ printk("IXP: testing ...\n"); ++ ixp_init(); ++ total = outstanding = 0; ++ jstart = jiffies; ++ for (i = 0; i < request_q_len; i++) { ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&requests[i].work, ixp_request_wq); ++#else ++ INIT_WORK(&requests[i].work, ixp_request, &requests[i]); ++#endif ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ outstanding++; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ ixp_request(&requests[i]); ++ } ++ while (outstanding > 0) ++ schedule(); ++ jstop = jiffies; ++ ++ mbps = 0; ++ if (jstop > jstart) { ++ mbps = (unsigned long) total * (unsigned long) request_size * 8; ++ mbps /= ((jstop - jstart) * 1000) / HZ; ++ } ++ printk("IXP: %d requests of %d bytes in %d jiffies (%d.%03d Mbps)\n", ++ total, request_size, jstop - jstart, ++ ((int)mbps) / 1000, ((int)mbps) % 1000); ++ ixp_done(); ++#endif /* BENCH_IXP_ACCESS_LIB */ ++ ++ for (i = 0; i < request_q_len; i++) ++ kfree(requests[i].buffer); ++ kfree(requests); ++ return -EINVAL; /* always fail to load so it can be re-run quickly ;-) */ ++} ++ ++static void __exit ocfbench_exit(void) ++{ ++} ++ ++module_init(ocfbench_init); ++module_exit(ocfbench_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Benchmark various in-kernel crypto speeds"); +diff -Nur linux-3.0.4.orig/crypto/ocf/ocf-compat.h linux-3.0.4/crypto/ocf/ocf-compat.h +--- linux-3.0.4.orig/crypto/ocf/ocf-compat.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ocf-compat.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,365 @@ ++#ifndef _BSD_COMPAT_H_ ++#define _BSD_COMPAT_H_ 1 ++/****************************************************************************/ ++/* ++ * Provide compat routines for older linux kernels and BSD kernels ++ * ++ * Written by David McCullough ++ * Copyright (C) 2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this file ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++/****************************************************************************/ ++#ifdef __KERNEL__ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++ ++/* ++ * fake some BSD driver interface stuff specifically for OCF use ++ */ ++ ++typedef struct ocf_device *device_t; ++ ++typedef struct { ++ int (*cryptodev_newsession)(device_t dev, u_int32_t *sidp, struct cryptoini *cri); ++ int (*cryptodev_freesession)(device_t dev, u_int64_t tid); ++ int (*cryptodev_process)(device_t dev, struct cryptop *crp, int hint); ++ int (*cryptodev_kprocess)(device_t dev, struct cryptkop *krp, int hint); ++} device_method_t; ++#define DEVMETHOD(id, func) id: func ++ ++struct ocf_device { ++ char name[32]; /* the driver name */ ++ char nameunit[32]; /* the driver name + HW instance */ ++ int unit; ++ device_method_t methods; ++ void *softc; ++}; ++ ++#define CRYPTODEV_NEWSESSION(dev, sid, cri) \ ++ ((*(dev)->methods.cryptodev_newsession)(dev,sid,cri)) ++#define CRYPTODEV_FREESESSION(dev, sid) \ ++ ((*(dev)->methods.cryptodev_freesession)(dev, sid)) ++#define CRYPTODEV_PROCESS(dev, crp, hint) \ ++ ((*(dev)->methods.cryptodev_process)(dev, crp, hint)) ++#define CRYPTODEV_KPROCESS(dev, krp, hint) \ ++ ((*(dev)->methods.cryptodev_kprocess)(dev, krp, hint)) ++ ++#define device_get_name(dev) ((dev)->name) ++#define device_get_nameunit(dev) ((dev)->nameunit) ++#define device_get_unit(dev) ((dev)->unit) ++#define device_get_softc(dev) ((dev)->softc) ++ ++#define softc_device_decl \ ++ struct ocf_device _device; \ ++ device_t ++ ++#define softc_device_init(_sc, _name, _unit, _methods) \ ++ if (1) {\ ++ strncpy((_sc)->_device.name, _name, sizeof((_sc)->_device.name) - 1); \ ++ snprintf((_sc)->_device.nameunit, sizeof((_sc)->_device.name), "%s%d", _name, _unit); \ ++ (_sc)->_device.unit = _unit; \ ++ (_sc)->_device.methods = _methods; \ ++ (_sc)->_device.softc = (void *) _sc; \ ++ *(device_t *)((softc_get_device(_sc))+1) = &(_sc)->_device; \ ++ } else ++ ++#define softc_get_device(_sc) (&(_sc)->_device) ++ ++/* ++ * iomem support for 2.4 and 2.6 kernels ++ */ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#define ocf_iomem_t unsigned long ++ ++/* ++ * implement simple workqueue like support for older kernels ++ */ ++ ++#include ++ ++#define work_struct tq_struct ++ ++#define INIT_WORK(wp, fp, ap) \ ++ do { \ ++ (wp)->sync = 0; \ ++ (wp)->routine = (fp); \ ++ (wp)->data = (ap); \ ++ } while (0) ++ ++#define schedule_work(wp) \ ++ do { \ ++ queue_task((wp), &tq_immediate); \ ++ mark_bh(IMMEDIATE_BH); \ ++ } while (0) ++ ++#define flush_scheduled_work() run_task_queue(&tq_immediate) ++ ++#else ++#define ocf_iomem_t void __iomem * ++ ++#include ++ ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) ++#include ++#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) ++#define files_fdtable(files) (files) ++#endif ++ ++#ifdef MODULE_PARM ++#undef module_param /* just in case */ ++#define module_param(a,b,c) MODULE_PARM(a,"i") ++#endif ++ ++#define bzero(s,l) memset(s,0,l) ++#define bcopy(s,d,l) memcpy(d,s,l) ++#define bcmp(x, y, l) memcmp(x,y,l) ++ ++#define MIN(x,y) ((x) < (y) ? (x) : (y)) ++ ++#define device_printf(dev, a...) ({ \ ++ printk("%s: ", device_get_nameunit(dev)); printk(a); \ ++ }) ++ ++#undef printf ++#define printf(fmt...) printk(fmt) ++ ++#define KASSERT(c,p) if (!(c)) { printk p ; } else ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#define ocf_daemonize(str) \ ++ daemonize(); \ ++ spin_lock_irq(¤t->sigmask_lock); \ ++ sigemptyset(¤t->blocked); \ ++ recalc_sigpending(current); \ ++ spin_unlock_irq(¤t->sigmask_lock); \ ++ sprintf(current->comm, str); ++#else ++#define ocf_daemonize(str) daemonize(str); ++#endif ++ ++#define TAILQ_INSERT_TAIL(q,d,m) list_add_tail(&(d)->m, (q)) ++#define TAILQ_EMPTY(q) list_empty(q) ++#define TAILQ_FOREACH(v, q, m) list_for_each_entry(v, q, m) ++ ++#define read_random(p,l) get_random_bytes(p,l) ++ ++#define DELAY(x) ((x) > 2000 ? mdelay((x)/1000) : udelay(x)) ++#define strtoul simple_strtoul ++ ++#define pci_get_vendor(dev) ((dev)->vendor) ++#define pci_get_device(dev) ((dev)->device) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#define pci_set_consistent_dma_mask(dev, mask) (0) ++#endif ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ++#define pci_dma_sync_single_for_cpu pci_dma_sync_single ++#endif ++ ++#ifndef DMA_32BIT_MASK ++#define DMA_32BIT_MASK 0x00000000ffffffffULL ++#endif ++ ++#ifndef htole32 ++#define htole32(x) cpu_to_le32(x) ++#endif ++#ifndef htobe32 ++#define htobe32(x) cpu_to_be32(x) ++#endif ++#ifndef htole16 ++#define htole16(x) cpu_to_le16(x) ++#endif ++#ifndef htobe16 ++#define htobe16(x) cpu_to_be16(x) ++#endif ++ ++/* older kernels don't have these */ ++ ++#include ++#if !defined(IRQ_NONE) && !defined(IRQ_RETVAL) ++#define IRQ_NONE ++#define IRQ_HANDLED ++#define IRQ_WAKE_THREAD ++#define IRQ_RETVAL ++#define irqreturn_t void ++typedef irqreturn_t (*irq_handler_t)(int irq, void *arg, struct pt_regs *regs); ++#endif ++#ifndef IRQF_SHARED ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++# define strlcpy(dest,src,len) \ ++ ({strncpy(dest,src,(len)-1); ((char *)dest)[(len)-1] = '\0'; }) ++#endif ++ ++#ifndef MAX_ERRNO ++#define MAX_ERRNO 4095 ++#endif ++#ifndef IS_ERR_VALUE ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,5) ++#include ++#endif ++#ifndef IS_ERR_VALUE ++#define IS_ERR_VALUE(x) ((unsigned long)(x) >= (unsigned long)-MAX_ERRNO) ++#endif ++#endif ++ ++/* ++ * common debug for all ++ */ ++#if 1 ++#define dprintk(a...) do { if (debug) printk(a); } while(0) ++#else ++#define dprintk(a...) ++#endif ++ ++#ifndef SLAB_ATOMIC ++/* Changed in 2.6.20, must use GFP_ATOMIC now */ ++#define SLAB_ATOMIC GFP_ATOMIC ++#endif ++ ++/* ++ * need some additional support for older kernels */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,2) ++#define pci_register_driver_compat(driver, rc) \ ++ do { \ ++ if ((rc) > 0) { \ ++ (rc) = 0; \ ++ } else if (rc == 0) { \ ++ (rc) = -ENODEV; \ ++ } else { \ ++ pci_unregister_driver(driver); \ ++ } \ ++ } while (0) ++#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ++#define pci_register_driver_compat(driver,rc) ((rc) = (rc) < 0 ? (rc) : 0) ++#else ++#define pci_register_driver_compat(driver,rc) ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ++ ++#include ++#include ++ ++static inline void sg_set_page(struct scatterlist *sg, struct page *page, ++ unsigned int len, unsigned int offset) ++{ ++ sg->page = page; ++ sg->offset = offset; ++ sg->length = len; ++} ++ ++static inline void *sg_virt(struct scatterlist *sg) ++{ ++ return page_address(sg->page) + sg->offset; ++} ++ ++#define sg_init_table(sg, n) ++ ++#endif ++ ++#ifndef late_initcall ++#define late_initcall(init) module_init(init) ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) || !defined(CONFIG_SMP) ++#define ocf_for_each_cpu(cpu) for ((cpu) = 0; (cpu) == 0; (cpu)++) ++#else ++#define ocf_for_each_cpu(cpu) for_each_present_cpu(cpu) ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++#include ++#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ++ ++struct ocf_thread { ++ struct task_struct *task; ++ int (*func)(void *arg); ++ void *arg; ++}; ++ ++/* thread startup helper func */ ++static inline int ocf_run_thread(void *arg) ++{ ++ struct ocf_thread *t = (struct ocf_thread *) arg; ++ if (!t) ++ return -1; /* very bad */ ++ t->task = current; ++ daemonize(); ++ spin_lock_irq(¤t->sigmask_lock); ++ sigemptyset(¤t->blocked); ++ recalc_sigpending(current); ++ spin_unlock_irq(¤t->sigmask_lock); ++ return (*t->func)(t->arg); ++} ++ ++#define kthread_create(f,a,fmt...) \ ++ ({ \ ++ struct ocf_thread t; \ ++ pid_t p; \ ++ t.task = NULL; \ ++ t.func = (f); \ ++ t.arg = (a); \ ++ p = kernel_thread(ocf_run_thread, &t, CLONE_FS|CLONE_FILES); \ ++ while (p != (pid_t) -1 && t.task == NULL) \ ++ schedule(); \ ++ if (t.task) \ ++ snprintf(t.task->comm, sizeof(t.task->comm), fmt); \ ++ (t.task); \ ++ }) ++ ++#define kthread_bind(t,cpu) /**/ ++ ++#define kthread_should_stop() (strcmp(current->comm, "stopping") == 0) ++ ++#define kthread_stop(t) \ ++ ({ \ ++ strcpy((t)->comm, "stopping"); \ ++ kill_proc((t)->pid, SIGTERM, 1); \ ++ do { \ ++ schedule(); \ ++ } while (kill_proc((t)->pid, SIGTERM, 1) == 0); \ ++ }) ++ ++#else ++#include ++#endif ++ ++#endif /* __KERNEL__ */ ++ ++/****************************************************************************/ ++#endif /* _BSD_COMPAT_H_ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/ocfnull/Makefile linux-3.0.4/crypto/ocf/ocfnull/Makefile +--- linux-3.0.4.orig/crypto/ocf/ocfnull/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ocfnull/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_OCFNULL) += ocfnull.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/ocfnull/ocfnull.c linux-3.0.4/crypto/ocf/ocfnull/ocfnull.c +--- linux-3.0.4.orig/crypto/ocf/ocfnull/ocfnull.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ocfnull/ocfnull.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,204 @@ ++/* ++ * An OCF module for determining the cost of crypto versus the cost of ++ * IPSec processing outside of OCF. This modules gives us the effect of ++ * zero cost encryption, of course you will need to run it at both ends ++ * since it does no crypto at all. ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++static int32_t null_id = -1; ++static u_int32_t null_sesnum = 0; ++ ++static int null_process(device_t, struct cryptop *, int); ++static int null_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int null_freesession(device_t, u_int64_t); ++ ++#define debug ocfnull_debug ++int ocfnull_debug = 0; ++module_param(ocfnull_debug, int, 0644); ++MODULE_PARM_DESC(ocfnull_debug, "Enable debug"); ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} nulldev; ++ ++static device_method_t null_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, null_newsession), ++ DEVMETHOD(cryptodev_freesession,null_freesession), ++ DEVMETHOD(cryptodev_process, null_process), ++}; ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++null_newsession(device_t arg, u_int32_t *sid, struct cryptoini *cri) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (null_sesnum == 0) ++ null_sesnum++; ++ *sid = null_sesnum++; ++ return 0; ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++null_freesession(device_t arg, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > null_sesnum) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return 0; ++ return 0; ++} ++ ++ ++/* ++ * Process a request. ++ */ ++static int ++null_process(device_t arg, struct cryptop *crp, int hint) ++{ ++ unsigned int lid; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ /* ++ * find the session we are using ++ */ ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= null_sesnum || lid == 0) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++done: ++ crypto_done(crp); ++ return 0; ++} ++ ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++ ++static int ++null_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, null_init); ++ ++ memset(&nulldev, 0, sizeof(nulldev)); ++ softc_device_init(&nulldev, "ocfnull", 0, null_methods); ++ ++ null_id = crypto_get_driverid(softc_get_device(&nulldev), ++ CRYPTOCAP_F_HARDWARE); ++ if (null_id < 0) ++ panic("ocfnull: crypto device cannot initialize!"); ++ ++#define REGISTER(alg) \ ++ crypto_register(null_id,alg,0,0) ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_RIJNDAEL128_CBC); ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_SHA1); ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++ return 0; ++} ++ ++static void ++null_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(null_id); ++ null_id = -1; ++} ++ ++module_init(null_init); ++module_exit(null_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("ocfnull - claims a lot but does nothing"); +diff -Nur linux-3.0.4.orig/crypto/ocf/pasemi/Makefile linux-3.0.4/crypto/ocf/pasemi/Makefile +--- linux-3.0.4.orig/crypto/ocf/pasemi/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/pasemi/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_PASEMI) += pasemi.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/pasemi/pasemi.c linux-3.0.4/crypto/ocf/pasemi/pasemi.c +--- linux-3.0.4.orig/crypto/ocf/pasemi/pasemi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/pasemi/pasemi.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1007 @@ ++/* ++ * Copyright (C) 2007 PA Semi, Inc ++ * ++ * Driver for the PA Semi PWRficient DMA Crypto Engine ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "pasemi_fnu.h" ++ ++#define DRV_NAME "pasemi" ++ ++#define TIMER_INTERVAL 1000 ++ ++static void __devexit pasemi_dma_remove(struct pci_dev *pdev); ++static struct pasdma_status volatile * dma_status; ++ ++static int debug; ++module_param(debug, int, 0644); ++MODULE_PARM_DESC(debug, "Enable debug"); ++ ++static void pasemi_desc_start(struct pasemi_desc *desc, u64 hdr) ++{ ++ desc->postop = 0; ++ desc->quad[0] = hdr; ++ desc->quad_cnt = 1; ++ desc->size = 1; ++} ++ ++static void pasemi_desc_build(struct pasemi_desc *desc, u64 val) ++{ ++ desc->quad[desc->quad_cnt++] = val; ++ desc->size = (desc->quad_cnt + 1) / 2; ++} ++ ++static void pasemi_desc_hdr(struct pasemi_desc *desc, u64 hdr) ++{ ++ desc->quad[0] |= hdr; ++} ++ ++static int pasemi_desc_size(struct pasemi_desc *desc) ++{ ++ return desc->size; ++} ++ ++static void pasemi_ring_add_desc( ++ struct pasemi_fnu_txring *ring, ++ struct pasemi_desc *desc, ++ struct cryptop *crp) { ++ int i; ++ int ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); ++ ++ TX_DESC_INFO(ring, ring->next_to_fill).desc_size = desc->size; ++ TX_DESC_INFO(ring, ring->next_to_fill).desc_postop = desc->postop; ++ TX_DESC_INFO(ring, ring->next_to_fill).cf_crp = crp; ++ ++ for (i = 0; i < desc->quad_cnt; i += 2) { ++ ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); ++ ring->desc[ring_index] = desc->quad[i]; ++ ring->desc[ring_index + 1] = desc->quad[i + 1]; ++ ring->next_to_fill++; ++ } ++ ++ if (desc->quad_cnt & 1) ++ ring->desc[ring_index + 1] = 0; ++} ++ ++static void pasemi_ring_incr(struct pasemi_softc *sc, int chan_index, int incr) ++{ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_INCR(sc->base_chan + chan_index), ++ incr); ++} ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++pasemi_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct pasemi_softc *sc = device_get_softc(dev); ++ struct pasemi_session *ses = NULL, **sespp; ++ int sesn, blksz = 0; ++ u64 ccmd = 0; ++ unsigned long flags; ++ struct pasemi_desc init_desc; ++ struct pasemi_fnu_txring *txring; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ if (sidp == NULL || cri == NULL || sc == NULL) { ++ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return -EINVAL; ++ } ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (ALG_IS_SIG(c->cri_alg)) { ++ if (macini) ++ return -EINVAL; ++ macini = c; ++ } else if (ALG_IS_CIPHER(c->cri_alg)) { ++ if (encini) ++ return -EINVAL; ++ encini = c; ++ } else { ++ DPRINTF("UNKNOWN c->cri_alg %d\n", c->cri_alg); ++ return -EINVAL; ++ } ++ } ++ if (encini == NULL && macini == NULL) ++ return -EINVAL; ++ if (encini) { ++ /* validate key length */ ++ switch (encini->cri_alg) { ++ case CRYPTO_DES_CBC: ++ if (encini->cri_klen != 64) ++ return -EINVAL; ++ ccmd = DMA_CALGO_DES; ++ break; ++ case CRYPTO_3DES_CBC: ++ if (encini->cri_klen != 192) ++ return -EINVAL; ++ ccmd = DMA_CALGO_3DES; ++ break; ++ case CRYPTO_AES_CBC: ++ if (encini->cri_klen != 128 && ++ encini->cri_klen != 192 && ++ encini->cri_klen != 256) ++ return -EINVAL; ++ ccmd = DMA_CALGO_AES; ++ break; ++ case CRYPTO_ARC4: ++ if (encini->cri_klen != 128) ++ return -EINVAL; ++ ccmd = DMA_CALGO_ARC; ++ break; ++ default: ++ DPRINTF("UNKNOWN encini->cri_alg %d\n", ++ encini->cri_alg); ++ return -EINVAL; ++ } ++ } ++ ++ if (macini) { ++ switch (macini->cri_alg) { ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ blksz = 16; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ blksz = 20; ++ break; ++ default: ++ DPRINTF("UNKNOWN macini->cri_alg %d\n", ++ macini->cri_alg); ++ return -EINVAL; ++ } ++ if (((macini->cri_klen + 7) / 8) > blksz) { ++ DPRINTF("key length %d bigger than blksize %d not supported\n", ++ ((macini->cri_klen + 7) / 8), blksz); ++ return -EINVAL; ++ } ++ } ++ ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn] == NULL) { ++ sc->sc_sessions[sesn] = (struct pasemi_session *) ++ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); ++ ses = sc->sc_sessions[sesn]; ++ break; ++ } else if (sc->sc_sessions[sesn]->used == 0) { ++ ses = sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sespp = (struct pasemi_session **) ++ kzalloc(sc->sc_nsessions * 2 * ++ sizeof(struct pasemi_session *), GFP_ATOMIC); ++ if (sespp == NULL) ++ return -ENOMEM; ++ memcpy(sespp, sc->sc_sessions, ++ sc->sc_nsessions * sizeof(struct pasemi_session *)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = sespp; ++ sesn = sc->sc_nsessions; ++ ses = sc->sc_sessions[sesn] = (struct pasemi_session *) ++ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); ++ if (ses == NULL) ++ return -ENOMEM; ++ sc->sc_nsessions *= 2; ++ } ++ ++ ses->used = 1; ++ ++ ses->dma_addr = pci_map_single(sc->dma_pdev, (void *) ses->civ, ++ sizeof(struct pasemi_session), DMA_TO_DEVICE); ++ ++ /* enter the channel scheduler */ ++ spin_lock_irqsave(&sc->sc_chnlock, flags); ++ ++ /* ARC4 has to be processed by the even channel */ ++ if (encini && (encini->cri_alg == CRYPTO_ARC4)) ++ ses->chan = sc->sc_lastchn & ~1; ++ else ++ ses->chan = sc->sc_lastchn; ++ sc->sc_lastchn = (sc->sc_lastchn + 1) % sc->sc_num_channels; ++ ++ spin_unlock_irqrestore(&sc->sc_chnlock, flags); ++ ++ txring = &sc->tx[ses->chan]; ++ ++ if (encini) { ++ ses->ccmd = ccmd; ++ ses->keysz = (encini->cri_klen - 63) / 64; ++ memcpy(ses->key, encini->cri_key, (ses->keysz + 1) * 8); ++ ++ pasemi_desc_start(&init_desc, ++ XCT_CTRL_HDR(ses->chan, (encini && macini) ? 0x68 : 0x40, DMA_FN_CIV0)); ++ pasemi_desc_build(&init_desc, ++ XCT_FUN_SRC_PTR((encini && macini) ? 0x68 : 0x40, ses->dma_addr)); ++ } ++ if (macini) { ++ if (macini->cri_alg == CRYPTO_MD5_HMAC || ++ macini->cri_alg == CRYPTO_SHA1_HMAC) ++ memcpy(ses->hkey, macini->cri_key, blksz); ++ else { ++ /* Load initialization constants(RFC 1321, 3174) */ ++ ses->hiv[0] = 0x67452301efcdab89ULL; ++ ses->hiv[1] = 0x98badcfe10325476ULL; ++ ses->hiv[2] = 0xc3d2e1f000000000ULL; ++ } ++ ses->hseq = 0ULL; ++ } ++ ++ spin_lock_irqsave(&txring->fill_lock, flags); ++ ++ if (((txring->next_to_fill + pasemi_desc_size(&init_desc)) - ++ txring->next_to_clean) > TX_RING_SIZE) { ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ return ERESTART; ++ } ++ ++ if (encini) { ++ pasemi_ring_add_desc(txring, &init_desc, NULL); ++ pasemi_ring_incr(sc, ses->chan, ++ pasemi_desc_size(&init_desc)); ++ } ++ ++ txring->sesn = sesn; ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ ++ *sidp = PASEMI_SID(sesn); ++ return 0; ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++pasemi_freesession(device_t dev, u_int64_t tid) ++{ ++ struct pasemi_softc *sc = device_get_softc(dev); ++ int session; ++ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (sc == NULL) ++ return -EINVAL; ++ session = PASEMI_SESSION(sid); ++ if (session >= sc->sc_nsessions || !sc->sc_sessions[session]) ++ return -EINVAL; ++ ++ pci_unmap_single(sc->dma_pdev, ++ sc->sc_sessions[session]->dma_addr, ++ sizeof(struct pasemi_session), DMA_TO_DEVICE); ++ memset(sc->sc_sessions[session], 0, ++ sizeof(struct pasemi_session)); ++ ++ return 0; ++} ++ ++static int ++pasemi_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ ++ int err = 0, ivsize, srclen = 0, reinit = 0, reinit_size = 0, chsel; ++ struct pasemi_softc *sc = device_get_softc(dev); ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ caddr_t ivp; ++ struct pasemi_desc init_desc, work_desc; ++ struct pasemi_session *ses; ++ struct sk_buff *skb; ++ struct uio *uiop; ++ unsigned long flags; ++ struct pasemi_fnu_txring *txring; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) ++ return -EINVAL; ++ ++ crp->crp_etype = 0; ++ if (PASEMI_SESSION(crp->crp_sid) >= sc->sc_nsessions) ++ return -EINVAL; ++ ++ ses = sc->sc_sessions[PASEMI_SESSION(crp->crp_sid)]; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ err = -EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ if (ALG_IS_SIG(crd1->crd_alg)) { ++ maccrd = crd1; ++ if (crd2 == NULL) ++ enccrd = NULL; ++ else if (ALG_IS_CIPHER(crd2->crd_alg) && ++ (crd2->crd_flags & CRD_F_ENCRYPT) == 0) ++ enccrd = crd2; ++ else ++ goto erralg; ++ } else if (ALG_IS_CIPHER(crd1->crd_alg)) { ++ enccrd = crd1; ++ if (crd2 == NULL) ++ maccrd = NULL; ++ else if (ALG_IS_SIG(crd2->crd_alg) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) ++ maccrd = crd2; ++ else ++ goto erralg; ++ } else ++ goto erralg; ++ ++ chsel = ses->chan; ++ ++ txring = &sc->tx[chsel]; ++ ++ if (enccrd && !maccrd) { ++ if (enccrd->crd_alg == CRYPTO_ARC4) ++ reinit = 1; ++ reinit_size = 0x40; ++ srclen = crp->crp_ilen; ++ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I ++ | XCT_FUN_FUN(chsel)); ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) ++ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_ENC); ++ else ++ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_DEC); ++ } else if (enccrd && maccrd) { ++ if (enccrd->crd_alg == CRYPTO_ARC4) ++ reinit = 1; ++ reinit_size = 0x68; ++ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ /* Encrypt -> Authenticate */ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_ENC_SIG ++ | XCT_FUN_A | XCT_FUN_FUN(chsel)); ++ srclen = maccrd->crd_skip + maccrd->crd_len; ++ } else { ++ /* Authenticate -> Decrypt */ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG_DEC ++ | XCT_FUN_24BRES | XCT_FUN_FUN(chsel)); ++ pasemi_desc_build(&work_desc, 0); ++ pasemi_desc_build(&work_desc, 0); ++ pasemi_desc_build(&work_desc, 0); ++ work_desc.postop = PASEMI_CHECK_SIG; ++ srclen = crp->crp_ilen; ++ } ++ ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SHL(maccrd->crd_skip / 4)); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_CHL(enccrd->crd_skip - maccrd->crd_skip)); ++ } else if (!enccrd && maccrd) { ++ srclen = maccrd->crd_len; ++ ++ pasemi_desc_start(&init_desc, ++ XCT_CTRL_HDR(chsel, 0x58, DMA_FN_HKEY0)); ++ pasemi_desc_build(&init_desc, ++ XCT_FUN_SRC_PTR(0x58, ((struct pasemi_session *)ses->dma_addr)->hkey)); ++ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG ++ | XCT_FUN_A | XCT_FUN_FUN(chsel)); ++ } ++ ++ if (enccrd) { ++ switch (enccrd->crd_alg) { ++ case CRYPTO_3DES_CBC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_3DES | ++ XCT_FUN_BCM_CBC); ++ ivsize = sizeof(u64); ++ break; ++ case CRYPTO_DES_CBC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_DES | ++ XCT_FUN_BCM_CBC); ++ ivsize = sizeof(u64); ++ break; ++ case CRYPTO_AES_CBC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_AES | ++ XCT_FUN_BCM_CBC); ++ ivsize = 2 * sizeof(u64); ++ break; ++ case CRYPTO_ARC4: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_ARC); ++ ivsize = 0; ++ break; ++ default: ++ printk(DRV_NAME ": unimplemented enccrd->crd_alg %d\n", ++ enccrd->crd_alg); ++ err = -EINVAL; ++ goto errout; ++ } ++ ++ ivp = (ivsize == sizeof(u64)) ? (caddr_t) &ses->civ[1] : (caddr_t) &ses->civ[0]; ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ memcpy(ivp, enccrd->crd_iv, ivsize); ++ else ++ read_random(ivp, ivsize); ++ /* If IV is not present in the buffer already, it has to be copied there */ ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, ivp); ++ } else { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ /* IV is provided expicitly in descriptor */ ++ memcpy(ivp, enccrd->crd_iv, ivsize); ++ else ++ /* IV is provided in the packet */ ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, ++ ivp); ++ } ++ } ++ ++ if (maccrd) { ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_MD5 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ case CRYPTO_SHA1: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_SHA1 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ case CRYPTO_MD5_HMAC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_MD5 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_SHA1 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ default: ++ printk(DRV_NAME ": unimplemented maccrd->crd_alg %d\n", ++ maccrd->crd_alg); ++ err = -EINVAL; ++ goto errout; ++ } ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ /* using SKB buffers */ ++ skb = (struct sk_buff *)crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ printk(DRV_NAME ": skb frags unimplemented\n"); ++ err = -EINVAL; ++ goto errout; ++ } ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_DST_PTR(skb->len, pci_map_single( ++ sc->dma_pdev, skb->data, ++ skb->len, DMA_TO_DEVICE))); ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_SRC_PTR( ++ srclen, pci_map_single( ++ sc->dma_pdev, skb->data, ++ srclen, DMA_TO_DEVICE))); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ /* using IOV buffers */ ++ uiop = (struct uio *)crp->crp_buf; ++ if (uiop->uio_iovcnt > 1) { ++ printk(DRV_NAME ": iov frags unimplemented\n"); ++ err = -EINVAL; ++ goto errout; ++ } ++ ++ /* crp_olen is never set; always use crp_ilen */ ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( ++ sc->dma_pdev, ++ uiop->uio_iov->iov_base, ++ crp->crp_ilen, DMA_TO_DEVICE))); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); ++ ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_SRC_PTR(srclen, pci_map_single( ++ sc->dma_pdev, ++ uiop->uio_iov->iov_base, ++ srclen, DMA_TO_DEVICE))); ++ } else { ++ /* using contig buffers */ ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( ++ sc->dma_pdev, ++ crp->crp_buf, ++ crp->crp_ilen, DMA_TO_DEVICE))); ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_SRC_PTR(srclen, pci_map_single( ++ sc->dma_pdev, ++ crp->crp_buf, srclen, ++ DMA_TO_DEVICE))); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); ++ } ++ ++ spin_lock_irqsave(&txring->fill_lock, flags); ++ ++ if (txring->sesn != PASEMI_SESSION(crp->crp_sid)) { ++ txring->sesn = PASEMI_SESSION(crp->crp_sid); ++ reinit = 1; ++ } ++ ++ if (enccrd) { ++ pasemi_desc_start(&init_desc, ++ XCT_CTRL_HDR(chsel, reinit ? reinit_size : 0x10, DMA_FN_CIV0)); ++ pasemi_desc_build(&init_desc, ++ XCT_FUN_SRC_PTR(reinit ? reinit_size : 0x10, ses->dma_addr)); ++ } ++ ++ if (((txring->next_to_fill + pasemi_desc_size(&init_desc) + ++ pasemi_desc_size(&work_desc)) - ++ txring->next_to_clean) > TX_RING_SIZE) { ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ err = ERESTART; ++ goto errout; ++ } ++ ++ pasemi_ring_add_desc(txring, &init_desc, NULL); ++ pasemi_ring_add_desc(txring, &work_desc, crp); ++ ++ pasemi_ring_incr(sc, chsel, ++ pasemi_desc_size(&init_desc) + ++ pasemi_desc_size(&work_desc)); ++ ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ ++ mod_timer(&txring->crypto_timer, jiffies + TIMER_INTERVAL); ++ ++ return 0; ++ ++erralg: ++ printk(DRV_NAME ": unsupported algorithm or algorithm order alg1 %d alg2 %d\n", ++ crd1->crd_alg, crd2->crd_alg); ++ err = -EINVAL; ++ ++errout: ++ if (err != ERESTART) { ++ crp->crp_etype = err; ++ crypto_done(crp); ++ } ++ return err; ++} ++ ++static int pasemi_clean_tx(struct pasemi_softc *sc, int chan) ++{ ++ int i, j, ring_idx; ++ struct pasemi_fnu_txring *ring = &sc->tx[chan]; ++ u16 delta_cnt; ++ int flags, loops = 10; ++ int desc_size; ++ struct cryptop *crp; ++ ++ spin_lock_irqsave(&ring->clean_lock, flags); ++ ++ while ((delta_cnt = (dma_status->tx_sta[sc->base_chan + chan] ++ & PAS_STATUS_PCNT_M) - ring->total_pktcnt) ++ && loops--) { ++ ++ for (i = 0; i < delta_cnt; i++) { ++ desc_size = TX_DESC_INFO(ring, ring->next_to_clean).desc_size; ++ crp = TX_DESC_INFO(ring, ring->next_to_clean).cf_crp; ++ if (crp) { ++ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); ++ if (TX_DESC_INFO(ring, ring->next_to_clean).desc_postop & PASEMI_CHECK_SIG) { ++ /* Need to make sure signature matched, ++ * if not - return error */ ++ if (!(ring->desc[ring_idx + 1] & (1ULL << 63))) ++ crp->crp_etype = -EINVAL; ++ } ++ crypto_done(TX_DESC_INFO(ring, ++ ring->next_to_clean).cf_crp); ++ TX_DESC_INFO(ring, ring->next_to_clean).cf_crp = NULL; ++ pci_unmap_single( ++ sc->dma_pdev, ++ XCT_PTR_ADDR_LEN(ring->desc[ring_idx + 1]), ++ PCI_DMA_TODEVICE); ++ ++ ring->desc[ring_idx] = ring->desc[ring_idx + 1] = 0; ++ ++ ring->next_to_clean++; ++ for (j = 1; j < desc_size; j++) { ++ ring_idx = 2 * ++ (ring->next_to_clean & ++ (TX_RING_SIZE-1)); ++ pci_unmap_single( ++ sc->dma_pdev, ++ XCT_PTR_ADDR_LEN(ring->desc[ring_idx]), ++ PCI_DMA_TODEVICE); ++ if (ring->desc[ring_idx + 1]) ++ pci_unmap_single( ++ sc->dma_pdev, ++ XCT_PTR_ADDR_LEN( ++ ring->desc[ ++ ring_idx + 1]), ++ PCI_DMA_TODEVICE); ++ ring->desc[ring_idx] = ++ ring->desc[ring_idx + 1] = 0; ++ ring->next_to_clean++; ++ } ++ } else { ++ for (j = 0; j < desc_size; j++) { ++ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); ++ ring->desc[ring_idx] = ++ ring->desc[ring_idx + 1] = 0; ++ ring->next_to_clean++; ++ } ++ } ++ } ++ ++ ring->total_pktcnt += delta_cnt; ++ } ++ spin_unlock_irqrestore(&ring->clean_lock, flags); ++ ++ return 0; ++} ++ ++static void sweepup_tx(struct pasemi_softc *sc) ++{ ++ int i; ++ ++ for (i = 0; i < sc->sc_num_channels; i++) ++ pasemi_clean_tx(sc, i); ++} ++ ++static irqreturn_t pasemi_intr(int irq, void *arg, struct pt_regs *regs) ++{ ++ struct pasemi_softc *sc = arg; ++ unsigned int reg; ++ int chan = irq - sc->base_irq; ++ int chan_index = sc->base_chan + chan; ++ u64 stat = dma_status->tx_sta[chan_index]; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (!(stat & PAS_STATUS_CAUSE_M)) ++ return IRQ_NONE; ++ ++ pasemi_clean_tx(sc, chan); ++ ++ stat = dma_status->tx_sta[chan_index]; ++ ++ reg = PAS_IOB_DMA_TXCH_RESET_PINTC | ++ PAS_IOB_DMA_TXCH_RESET_PCNT(sc->tx[chan].total_pktcnt); ++ ++ if (stat & PAS_STATUS_SOFT) ++ reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; ++ ++ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), reg); ++ ++ ++ return IRQ_HANDLED; ++} ++ ++static int pasemi_dma_setup_tx_resources(struct pasemi_softc *sc, int chan) ++{ ++ u32 val; ++ int chan_index = chan + sc->base_chan; ++ int ret; ++ struct pasemi_fnu_txring *ring; ++ ++ ring = &sc->tx[chan]; ++ ++ spin_lock_init(&ring->fill_lock); ++ spin_lock_init(&ring->clean_lock); ++ ++ ring->desc_info = kzalloc(sizeof(struct pasemi_desc_info) * ++ TX_RING_SIZE, GFP_KERNEL); ++ if (!ring->desc_info) ++ return -ENOMEM; ++ ++ /* Allocate descriptors */ ++ ring->desc = dma_alloc_coherent(&sc->dma_pdev->dev, ++ TX_RING_SIZE * ++ 2 * sizeof(u64), ++ &ring->dma, GFP_KERNEL); ++ if (!ring->desc) ++ return -ENOMEM; ++ ++ memset((void *) ring->desc, 0, TX_RING_SIZE * 2 * sizeof(u64)); ++ ++ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), 0x30); ++ ++ ring->total_pktcnt = 0; ++ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEL(chan_index), ++ PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); ++ ++ val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); ++ val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); ++ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEU(chan_index), val); ++ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_CFG(chan_index), ++ PAS_DMA_TXCHAN_CFG_TY_FUNC | ++ PAS_DMA_TXCHAN_CFG_TATTR(chan) | ++ PAS_DMA_TXCHAN_CFG_WT(2)); ++ ++ /* enable tx channel */ ++ out_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index), ++ PAS_DMA_TXCHAN_TCMDSTA_EN); ++ ++ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_CFG(chan_index), ++ PAS_IOB_DMA_TXCH_CFG_CNTTH(1000)); ++ ++ ring->next_to_fill = 0; ++ ring->next_to_clean = 0; ++ ++ snprintf(ring->irq_name, sizeof(ring->irq_name), ++ "%s%d", "crypto", chan); ++ ++ ring->irq = irq_create_mapping(NULL, sc->base_irq + chan); ++ ret = request_irq(ring->irq, (irq_handler_t) ++ pasemi_intr, IRQF_DISABLED, ring->irq_name, sc); ++ if (ret) { ++ printk(KERN_ERR DRV_NAME ": failed to hook irq %d ret %d\n", ++ ring->irq, ret); ++ ring->irq = -1; ++ return ret; ++ } ++ ++ setup_timer(&ring->crypto_timer, (void *) sweepup_tx, (unsigned long) sc); ++ ++ return 0; ++} ++ ++static device_method_t pasemi_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, pasemi_newsession), ++ DEVMETHOD(cryptodev_freesession, pasemi_freesession), ++ DEVMETHOD(cryptodev_process, pasemi_process), ++}; ++ ++/* Set up the crypto device structure, private data, ++ * and anything else we need before we start */ ++ ++static int __devinit ++pasemi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *ent) ++{ ++ struct pasemi_softc *sc; ++ int ret, i; ++ ++ DPRINTF(KERN_ERR "%s()\n", __FUNCTION__); ++ ++ sc = kzalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return -ENOMEM; ++ ++ softc_device_init(sc, DRV_NAME, 1, pasemi_methods); ++ ++ pci_set_drvdata(pdev, sc); ++ ++ spin_lock_init(&sc->sc_chnlock); ++ ++ sc->sc_sessions = (struct pasemi_session **) ++ kzalloc(PASEMI_INITIAL_SESSIONS * ++ sizeof(struct pasemi_session *), GFP_ATOMIC); ++ if (sc->sc_sessions == NULL) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ sc->sc_nsessions = PASEMI_INITIAL_SESSIONS; ++ sc->sc_lastchn = 0; ++ sc->base_irq = pdev->irq + 6; ++ sc->base_chan = 6; ++ sc->sc_cid = -1; ++ sc->dma_pdev = pdev; ++ ++ sc->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); ++ if (!sc->iob_pdev) { ++ dev_err(&pdev->dev, "Can't find I/O Bridge\n"); ++ ret = -ENODEV; ++ goto out; ++ } ++ ++ /* This is hardcoded and ugly, but we have some firmware versions ++ * who don't provide the register space in the device tree. Luckily ++ * they are at well-known locations so we can just do the math here. ++ */ ++ sc->dma_regs = ++ ioremap(0xe0000000 + (sc->dma_pdev->devfn << 12), 0x2000); ++ sc->iob_regs = ++ ioremap(0xe0000000 + (sc->iob_pdev->devfn << 12), 0x2000); ++ if (!sc->dma_regs || !sc->iob_regs) { ++ dev_err(&pdev->dev, "Can't map registers\n"); ++ ret = -ENODEV; ++ goto out; ++ } ++ ++ dma_status = __ioremap(0xfd800000, 0x1000, 0); ++ if (!dma_status) { ++ ret = -ENODEV; ++ dev_err(&pdev->dev, "Can't map dmastatus space\n"); ++ goto out; ++ } ++ ++ sc->tx = (struct pasemi_fnu_txring *) ++ kzalloc(sizeof(struct pasemi_fnu_txring) ++ * 8, GFP_KERNEL); ++ if (!sc->tx) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ /* Initialize the h/w */ ++ out_le32(sc->dma_regs + PAS_DMA_COM_CFG, ++ (in_le32(sc->dma_regs + PAS_DMA_COM_CFG) | ++ PAS_DMA_COM_CFG_FWF)); ++ out_le32(sc->dma_regs + PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); ++ ++ for (i = 0; i < PASEMI_FNU_CHANNELS; i++) { ++ sc->sc_num_channels++; ++ ret = pasemi_dma_setup_tx_resources(sc, i); ++ if (ret) ++ goto out; ++ } ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), ++ CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ printk(KERN_ERR DRV_NAME ": could not get crypto driver id\n"); ++ ret = -ENXIO; ++ goto out; ++ } ++ ++ /* register algorithms with the framework */ ++ printk(DRV_NAME ":"); ++ ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ ++ return 0; ++ ++out: ++ pasemi_dma_remove(pdev); ++ return ret; ++} ++ ++#define MAX_RETRIES 5000 ++ ++static void pasemi_free_tx_resources(struct pasemi_softc *sc, int chan) ++{ ++ struct pasemi_fnu_txring *ring = &sc->tx[chan]; ++ int chan_index = chan + sc->base_chan; ++ int retries; ++ u32 stat; ++ ++ /* Stop the channel */ ++ out_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index), ++ PAS_DMA_TXCHAN_TCMDSTA_ST); ++ ++ for (retries = 0; retries < MAX_RETRIES; retries++) { ++ stat = in_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index)); ++ if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) ++ break; ++ cond_resched(); ++ } ++ ++ if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT) ++ dev_err(&sc->dma_pdev->dev, "Failed to stop tx channel %d\n", ++ chan_index); ++ ++ /* Disable the channel */ ++ out_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index), ++ 0); ++ ++ if (ring->desc_info) ++ kfree((void *) ring->desc_info); ++ if (ring->desc) ++ dma_free_coherent(&sc->dma_pdev->dev, ++ TX_RING_SIZE * ++ 2 * sizeof(u64), ++ (void *) ring->desc, ring->dma); ++ if (ring->irq != -1) ++ free_irq(ring->irq, sc); ++ ++ del_timer(&ring->crypto_timer); ++} ++ ++static void __devexit pasemi_dma_remove(struct pci_dev *pdev) ++{ ++ struct pasemi_softc *sc = pci_get_drvdata(pdev); ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (sc->sc_cid >= 0) { ++ crypto_unregister_all(sc->sc_cid); ++ } ++ ++ if (sc->tx) { ++ for (i = 0; i < sc->sc_num_channels; i++) ++ pasemi_free_tx_resources(sc, i); ++ ++ kfree(sc->tx); ++ } ++ if (sc->sc_sessions) { ++ for (i = 0; i < sc->sc_nsessions; i++) ++ kfree(sc->sc_sessions[i]); ++ kfree(sc->sc_sessions); ++ } ++ if (sc->iob_pdev) ++ pci_dev_put(sc->iob_pdev); ++ if (sc->dma_regs) ++ iounmap(sc->dma_regs); ++ if (sc->iob_regs) ++ iounmap(sc->iob_regs); ++ kfree(sc); ++} ++ ++static struct pci_device_id pasemi_dma_pci_tbl[] = { ++ { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa007) }, ++}; ++ ++MODULE_DEVICE_TABLE(pci, pasemi_dma_pci_tbl); ++ ++static struct pci_driver pasemi_dma_driver = { ++ .name = "pasemi_dma", ++ .id_table = pasemi_dma_pci_tbl, ++ .probe = pasemi_dma_probe, ++ .remove = __devexit_p(pasemi_dma_remove), ++}; ++ ++static void __exit pasemi_dma_cleanup_module(void) ++{ ++ pci_unregister_driver(&pasemi_dma_driver); ++ __iounmap(dma_status); ++ dma_status = NULL; ++} ++ ++int pasemi_dma_init_module(void) ++{ ++ return pci_register_driver(&pasemi_dma_driver); ++} ++ ++module_init(pasemi_dma_init_module); ++module_exit(pasemi_dma_cleanup_module); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("Egor Martovetsky egor@pasemi.com"); ++MODULE_DESCRIPTION("OCF driver for PA Semi PWRficient DMA Crypto Engine"); +diff -Nur linux-3.0.4.orig/crypto/ocf/pasemi/pasemi_fnu.h linux-3.0.4/crypto/ocf/pasemi/pasemi_fnu.h +--- linux-3.0.4.orig/crypto/ocf/pasemi/pasemi_fnu.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/pasemi/pasemi_fnu.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,410 @@ ++/* ++ * Copyright (C) 2007 PA Semi, Inc ++ * ++ * Driver for the PA Semi PWRficient DMA Crypto Engine, soft state and ++ * hardware register layouts. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef PASEMI_FNU_H ++#define PASEMI_FNU_H ++ ++#include ++ ++#define PASEMI_SESSION(sid) ((sid) & 0xffffffff) ++#define PASEMI_SID(sesn) ((sesn) & 0xffffffff) ++#define DPRINTF(a...) if (debug) { printk(DRV_NAME ": " a); } ++ ++/* Must be a power of two */ ++#define RX_RING_SIZE 512 ++#define TX_RING_SIZE 512 ++#define TX_DESC(ring, num) ((ring)->desc[2 * (num & (TX_RING_SIZE-1))]) ++#define TX_DESC_INFO(ring, num) ((ring)->desc_info[(num) & (TX_RING_SIZE-1)]) ++#define MAX_DESC_SIZE 8 ++#define PASEMI_INITIAL_SESSIONS 10 ++#define PASEMI_FNU_CHANNELS 8 ++ ++/* DMA descriptor */ ++struct pasemi_desc { ++ u64 quad[2*MAX_DESC_SIZE]; ++ int quad_cnt; ++ int size; ++ int postop; ++}; ++ ++/* ++ * Holds per descriptor data ++ */ ++struct pasemi_desc_info { ++ int desc_size; ++ int desc_postop; ++#define PASEMI_CHECK_SIG 0x1 ++ ++ struct cryptop *cf_crp; ++}; ++ ++/* ++ * Holds per channel data ++ */ ++struct pasemi_fnu_txring { ++ volatile u64 *desc; ++ volatile struct ++ pasemi_desc_info *desc_info; ++ dma_addr_t dma; ++ struct timer_list crypto_timer; ++ spinlock_t fill_lock; ++ spinlock_t clean_lock; ++ unsigned int next_to_fill; ++ unsigned int next_to_clean; ++ u16 total_pktcnt; ++ int irq; ++ int sesn; ++ char irq_name[10]; ++}; ++ ++/* ++ * Holds data specific to a single pasemi device. ++ */ ++struct pasemi_softc { ++ softc_device_decl sc_cdev; ++ struct pci_dev *dma_pdev; /* device backpointer */ ++ struct pci_dev *iob_pdev; /* device backpointer */ ++ void __iomem *dma_regs; ++ void __iomem *iob_regs; ++ int base_irq; ++ int base_chan; ++ int32_t sc_cid; /* crypto tag */ ++ int sc_nsessions; ++ struct pasemi_session **sc_sessions; ++ int sc_num_channels;/* number of crypto channels */ ++ ++ /* pointer to the array of txring datastructures, one txring per channel */ ++ struct pasemi_fnu_txring *tx; ++ ++ /* ++ * mutual exclusion for the channel scheduler ++ */ ++ spinlock_t sc_chnlock; ++ /* last channel used, for now use round-robin to allocate channels */ ++ int sc_lastchn; ++}; ++ ++struct pasemi_session { ++ u64 civ[2]; ++ u64 keysz; ++ u64 key[4]; ++ u64 ccmd; ++ u64 hkey[4]; ++ u64 hseq; ++ u64 giv[2]; ++ u64 hiv[4]; ++ ++ int used; ++ dma_addr_t dma_addr; ++ int chan; ++}; ++ ++/* status register layout in IOB region, at 0xfd800000 */ ++struct pasdma_status { ++ u64 rx_sta[64]; ++ u64 tx_sta[20]; ++}; ++ ++#define ALG_IS_CIPHER(alg) ((alg == CRYPTO_DES_CBC) || \ ++ (alg == CRYPTO_3DES_CBC) || \ ++ (alg == CRYPTO_AES_CBC) || \ ++ (alg == CRYPTO_ARC4) || \ ++ (alg == CRYPTO_NULL_CBC)) ++ ++#define ALG_IS_SIG(alg) ((alg == CRYPTO_MD5) || \ ++ (alg == CRYPTO_MD5_HMAC) || \ ++ (alg == CRYPTO_SHA1) || \ ++ (alg == CRYPTO_SHA1_HMAC) || \ ++ (alg == CRYPTO_NULL_HMAC)) ++ ++enum { ++ PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ ++ PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ ++ PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ ++ PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ ++ PAS_DMA_COM_CFG = 0x114, /* DMA Configuration Register */ ++}; ++ ++/* All these registers live in the PCI configuration space for the DMA PCI ++ * device. Use the normal PCI config access functions for them. ++ */ ++ ++#define PAS_DMA_COM_CFG_FWF 0x18000000 ++ ++#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ ++#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ ++#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ ++#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ ++ ++#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ ++#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ ++#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ ++#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ ++#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ ++#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ ++#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ ++#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ ++#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ ++#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ ++#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ ++#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = interface */ ++#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ ++#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c ++#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 ++#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ ++ PAS_DMA_TXCHAN_CFG_TATTR_M) ++#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 ++#define PAS_DMA_TXCHAN_CFG_WT_S 6 ++#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ ++ PAS_DMA_TXCHAN_CFG_WT_M) ++#define PAS_DMA_TXCHAN_CFG_LPSQ_FAST 0x00000400 ++#define PAS_DMA_TXCHAN_CFG_LPDQ_FAST 0x00000800 ++#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ ++#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ ++#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ ++#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 ++#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 ++#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ ++ PAS_DMA_TXCHAN_BASEL_BRBL_M) ++#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff ++#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 ++#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ ++ PAS_DMA_TXCHAN_BASEU_BRBH_M) ++/* # of cache lines worth of buffer ring */ ++#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 ++#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ ++#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ ++ PAS_DMA_TXCHAN_BASEU_SIZ_M) ++ ++#define PAS_STATUS_PCNT_M 0x000000000000ffffull ++#define PAS_STATUS_PCNT_S 0 ++#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull ++#define PAS_STATUS_DCNT_S 16 ++#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull ++#define PAS_STATUS_BPCNT_S 32 ++#define PAS_STATUS_CAUSE_M 0xf000000000000000ull ++#define PAS_STATUS_TIMER 0x1000000000000000ull ++#define PAS_STATUS_ERROR 0x2000000000000000ull ++#define PAS_STATUS_SOFT 0x4000000000000000ull ++#define PAS_STATUS_INT 0x8000000000000000ull ++ ++#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) ++#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff ++#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 ++#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ ++ PAS_IOB_DMA_RXCH_CFG_CNTTH_M) ++#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) ++#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff ++#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 ++#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ ++ PAS_IOB_DMA_TXCH_CFG_CNTTH_M) ++#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) ++#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 ++#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff ++#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 ++#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ ++ PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) ++#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) ++#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 ++#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff ++#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 ++#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ ++ PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) ++#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) ++#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 ++#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 ++#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ ++ PAS_IOB_DMA_RXCH_RESET_PCNT_M) ++#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 ++#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 ++#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 ++#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 ++#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 ++#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 ++#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) ++#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 ++#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 ++#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ ++ PAS_IOB_DMA_TXCH_RESET_PCNT_M) ++#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 ++#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 ++#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 ++#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 ++#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 ++#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 ++ ++#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 ++#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff ++#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 ++#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ ++ PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) ++ ++/* Transmit descriptor fields */ ++#define XCT_MACTX_T 0x8000000000000000ull ++#define XCT_MACTX_ST 0x4000000000000000ull ++#define XCT_MACTX_NORES 0x0000000000000000ull ++#define XCT_MACTX_8BRES 0x1000000000000000ull ++#define XCT_MACTX_24BRES 0x2000000000000000ull ++#define XCT_MACTX_40BRES 0x3000000000000000ull ++#define XCT_MACTX_I 0x0800000000000000ull ++#define XCT_MACTX_O 0x0400000000000000ull ++#define XCT_MACTX_E 0x0200000000000000ull ++#define XCT_MACTX_VLAN_M 0x0180000000000000ull ++#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull ++#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull ++#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull ++#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull ++#define XCT_MACTX_CRC_M 0x0060000000000000ull ++#define XCT_MACTX_CRC_NOP 0x0000000000000000ull ++#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull ++#define XCT_MACTX_CRC_PAD 0x0040000000000000ull ++#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull ++#define XCT_MACTX_SS 0x0010000000000000ull ++#define XCT_MACTX_LLEN_M 0x00007fff00000000ull ++#define XCT_MACTX_LLEN_S 32ull ++#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ ++ XCT_MACTX_LLEN_M) ++#define XCT_MACTX_IPH_M 0x00000000f8000000ull ++#define XCT_MACTX_IPH_S 27ull ++#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ ++ XCT_MACTX_IPH_M) ++#define XCT_MACTX_IPO_M 0x0000000007c00000ull ++#define XCT_MACTX_IPO_S 22ull ++#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ ++ XCT_MACTX_IPO_M) ++#define XCT_MACTX_CSUM_M 0x0000000000000060ull ++#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull ++#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull ++#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull ++#define XCT_MACTX_V6 0x0000000000000010ull ++#define XCT_MACTX_C 0x0000000000000004ull ++#define XCT_MACTX_AL2 0x0000000000000002ull ++ ++#define XCT_PTR_T 0x8000000000000000ull ++#define XCT_PTR_LEN_M 0x7ffff00000000000ull ++#define XCT_PTR_LEN_S 44 ++#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ ++ XCT_PTR_LEN_M) ++#define XCT_PTR_ADDR_M 0x00000fffffffffffull ++#define XCT_PTR_ADDR_S 0 ++#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ ++ XCT_PTR_ADDR_M) ++ ++/* Function descriptor fields */ ++#define XCT_FUN_T 0x8000000000000000ull ++#define XCT_FUN_ST 0x4000000000000000ull ++#define XCT_FUN_NORES 0x0000000000000000ull ++#define XCT_FUN_8BRES 0x1000000000000000ull ++#define XCT_FUN_24BRES 0x2000000000000000ull ++#define XCT_FUN_40BRES 0x3000000000000000ull ++#define XCT_FUN_I 0x0800000000000000ull ++#define XCT_FUN_O 0x0400000000000000ull ++#define XCT_FUN_E 0x0200000000000000ull ++#define XCT_FUN_FUN_S 54 ++#define XCT_FUN_FUN_M 0x01c0000000000000ull ++#define XCT_FUN_FUN(num) ((((long)(num)) << XCT_FUN_FUN_S) & \ ++ XCT_FUN_FUN_M) ++#define XCT_FUN_CRM_NOP 0x0000000000000000ull ++#define XCT_FUN_CRM_SIG 0x0008000000000000ull ++#define XCT_FUN_CRM_ENC 0x0010000000000000ull ++#define XCT_FUN_CRM_DEC 0x0018000000000000ull ++#define XCT_FUN_CRM_SIG_ENC 0x0020000000000000ull ++#define XCT_FUN_CRM_ENC_SIG 0x0028000000000000ull ++#define XCT_FUN_CRM_SIG_DEC 0x0030000000000000ull ++#define XCT_FUN_CRM_DEC_SIG 0x0038000000000000ull ++#define XCT_FUN_LLEN_M 0x0007ffff00000000ull ++#define XCT_FUN_LLEN_S 32ULL ++#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & \ ++ XCT_FUN_LLEN_M) ++#define XCT_FUN_SHL_M 0x00000000f8000000ull ++#define XCT_FUN_SHL_S 27ull ++#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & \ ++ XCT_FUN_SHL_M) ++#define XCT_FUN_CHL_M 0x0000000007c00000ull ++#define XCT_FUN_CHL_S 22ull ++#define XCT_FUN_CHL(x) ((((long)(x)) << XCT_FUN_CHL_S) & \ ++ XCT_FUN_CHL_M) ++#define XCT_FUN_HSZ_M 0x00000000003c0000ull ++#define XCT_FUN_HSZ_S 18ull ++#define XCT_FUN_HSZ(x) ((((long)(x)) << XCT_FUN_HSZ_S) & \ ++ XCT_FUN_HSZ_M) ++#define XCT_FUN_ALG_DES 0x0000000000000000ull ++#define XCT_FUN_ALG_3DES 0x0000000000008000ull ++#define XCT_FUN_ALG_AES 0x0000000000010000ull ++#define XCT_FUN_ALG_ARC 0x0000000000018000ull ++#define XCT_FUN_ALG_KASUMI 0x0000000000020000ull ++#define XCT_FUN_BCM_ECB 0x0000000000000000ull ++#define XCT_FUN_BCM_CBC 0x0000000000001000ull ++#define XCT_FUN_BCM_CFB 0x0000000000002000ull ++#define XCT_FUN_BCM_OFB 0x0000000000003000ull ++#define XCT_FUN_BCM_CNT 0x0000000000003800ull ++#define XCT_FUN_BCM_KAS_F8 0x0000000000002800ull ++#define XCT_FUN_BCM_KAS_F9 0x0000000000001800ull ++#define XCT_FUN_BCP_NO_PAD 0x0000000000000000ull ++#define XCT_FUN_BCP_ZRO 0x0000000000000200ull ++#define XCT_FUN_BCP_PL 0x0000000000000400ull ++#define XCT_FUN_BCP_INCR 0x0000000000000600ull ++#define XCT_FUN_SIG_MD5 (0ull << 4) ++#define XCT_FUN_SIG_SHA1 (2ull << 4) ++#define XCT_FUN_SIG_HMAC_MD5 (8ull << 4) ++#define XCT_FUN_SIG_HMAC_SHA1 (10ull << 4) ++#define XCT_FUN_A 0x0000000000000008ull ++#define XCT_FUN_C 0x0000000000000004ull ++#define XCT_FUN_AL2 0x0000000000000002ull ++#define XCT_FUN_SE 0x0000000000000001ull ++ ++#define XCT_FUN_SRC_PTR(len, addr) (XCT_PTR_LEN(len) | XCT_PTR_ADDR(addr)) ++#define XCT_FUN_DST_PTR(len, addr) (XCT_FUN_SRC_PTR(len, addr) | \ ++ 0x8000000000000000ull) ++ ++#define XCT_CTRL_HDR_FUN_NUM_M 0x01c0000000000000ull ++#define XCT_CTRL_HDR_FUN_NUM_S 54 ++#define XCT_CTRL_HDR_LEN_M 0x0007ffff00000000ull ++#define XCT_CTRL_HDR_LEN_S 32 ++#define XCT_CTRL_HDR_REG_M 0x00000000000000ffull ++#define XCT_CTRL_HDR_REG_S 0 ++ ++#define XCT_CTRL_HDR(funcN,len,reg) (0x9400000000000000ull | \ ++ ((((long)(funcN)) << XCT_CTRL_HDR_FUN_NUM_S) \ ++ & XCT_CTRL_HDR_FUN_NUM_M) | \ ++ ((((long)(len)) << \ ++ XCT_CTRL_HDR_LEN_S) & XCT_CTRL_HDR_LEN_M) | \ ++ ((((long)(reg)) << \ ++ XCT_CTRL_HDR_REG_S) & XCT_CTRL_HDR_REG_M)) ++ ++/* Function config command options */ ++#define DMA_CALGO_DES 0x00 ++#define DMA_CALGO_3DES 0x01 ++#define DMA_CALGO_AES 0x02 ++#define DMA_CALGO_ARC 0x03 ++ ++#define DMA_FN_CIV0 0x02 ++#define DMA_FN_CIV1 0x03 ++#define DMA_FN_HKEY0 0x0a ++ ++#define XCT_PTR_ADDR_LEN(ptr) ((ptr) & XCT_PTR_ADDR_M), \ ++ (((ptr) & XCT_PTR_LEN_M) >> XCT_PTR_LEN_S) ++ ++#endif /* PASEMI_FNU_H */ +diff -Nur linux-3.0.4.orig/crypto/ocf/random.c linux-3.0.4/crypto/ocf/random.c +--- linux-3.0.4.orig/crypto/ocf/random.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/random.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,317 @@ ++/* ++ * A system independant way of adding entropy to the kernels pool ++ * this way the drivers can focus on the real work and we can take ++ * care of pushing it to the appropriate place in the kernel. ++ * ++ * This should be fast and callable from timers/interrupts ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_OCF_FIPS ++#include "rndtest.h" ++#endif ++ ++#ifndef HAS_RANDOM_INPUT_WAIT ++#error "Please do not enable OCF_RANDOMHARVEST unless you have applied patches" ++#endif ++ ++/* ++ * a hack to access the debug levels from the crypto driver ++ */ ++extern int crypto_debug; ++#define debug crypto_debug ++ ++/* ++ * a list of all registered random providers ++ */ ++static LIST_HEAD(random_ops); ++static int started = 0; ++static int initted = 0; ++ ++struct random_op { ++ struct list_head random_list; ++ u_int32_t driverid; ++ int (*read_random)(void *arg, u_int32_t *buf, int len); ++ void *arg; ++}; ++ ++static int random_proc(void *arg); ++ ++static pid_t randomproc = (pid_t) -1; ++static spinlock_t random_lock; ++ ++/* ++ * just init the spin locks ++ */ ++static int ++crypto_random_init(void) ++{ ++ spin_lock_init(&random_lock); ++ initted = 1; ++ return(0); ++} ++ ++/* ++ * Add the given random reader to our list (if not present) ++ * and start the thread (if not already started) ++ * ++ * we have to assume that driver id is ok for now ++ */ ++int ++crypto_rregister( ++ u_int32_t driverid, ++ int (*read_random)(void *arg, u_int32_t *buf, int len), ++ void *arg) ++{ ++ unsigned long flags; ++ int ret = 0; ++ struct random_op *rops, *tmp; ++ ++ dprintk("%s,%d: %s(0x%x, %p, %p)\n", __FILE__, __LINE__, ++ __FUNCTION__, driverid, read_random, arg); ++ ++ if (!initted) ++ crypto_random_init(); ++ ++#if 0 ++ struct cryptocap *cap; ++ ++ cap = crypto_checkdriver(driverid); ++ if (!cap) ++ return EINVAL; ++#endif ++ ++ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { ++ if (rops->driverid == driverid && rops->read_random == read_random) ++ return EEXIST; ++ } ++ ++ rops = (struct random_op *) kmalloc(sizeof(*rops), GFP_KERNEL); ++ if (!rops) ++ return ENOMEM; ++ ++ rops->driverid = driverid; ++ rops->read_random = read_random; ++ rops->arg = arg; ++ ++ spin_lock_irqsave(&random_lock, flags); ++ list_add_tail(&rops->random_list, &random_ops); ++ if (!started) { ++ randomproc = kernel_thread(random_proc, NULL, CLONE_FS|CLONE_FILES); ++ if (randomproc < 0) { ++ ret = randomproc; ++ printk("crypto: crypto_rregister cannot start random thread; " ++ "error %d", ret); ++ } else ++ started = 1; ++ } ++ spin_unlock_irqrestore(&random_lock, flags); ++ ++ return ret; ++} ++EXPORT_SYMBOL(crypto_rregister); ++ ++int ++crypto_runregister_all(u_int32_t driverid) ++{ ++ struct random_op *rops, *tmp; ++ unsigned long flags; ++ ++ dprintk("%s,%d: %s(0x%x)\n", __FILE__, __LINE__, __FUNCTION__, driverid); ++ ++ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { ++ if (rops->driverid == driverid) { ++ list_del(&rops->random_list); ++ kfree(rops); ++ } ++ } ++ ++ spin_lock_irqsave(&random_lock, flags); ++ if (list_empty(&random_ops) && started) ++ kill_proc(randomproc, SIGKILL, 1); ++ spin_unlock_irqrestore(&random_lock, flags); ++ return(0); ++} ++EXPORT_SYMBOL(crypto_runregister_all); ++ ++/* ++ * while we can add entropy to random.c continue to read random data from ++ * the drivers and push it to random. ++ */ ++static int ++random_proc(void *arg) ++{ ++ int n; ++ int wantcnt; ++ int bufcnt = 0; ++ int retval = 0; ++ int *buf = NULL; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ daemonize(); ++ spin_lock_irq(¤t->sigmask_lock); ++ sigemptyset(¤t->blocked); ++ recalc_sigpending(current); ++ spin_unlock_irq(¤t->sigmask_lock); ++ sprintf(current->comm, "ocf-random"); ++#else ++ daemonize("ocf-random"); ++ allow_signal(SIGKILL); ++#endif ++ ++ (void) get_fs(); ++ set_fs(get_ds()); ++ ++#ifdef CONFIG_OCF_FIPS ++#define NUM_INT (RNDTEST_NBYTES/sizeof(int)) ++#else ++#define NUM_INT 32 ++#endif ++ ++ /* ++ * some devices can transferr their RNG data direct into memory, ++ * so make sure it is device friendly ++ */ ++ buf = kmalloc(NUM_INT * sizeof(int), GFP_DMA); ++ if (NULL == buf) { ++ printk("crypto: RNG could not allocate memory\n"); ++ retval = -ENOMEM; ++ goto bad_alloc; ++ } ++ ++ wantcnt = NUM_INT; /* start by adding some entropy */ ++ ++ /* ++ * its possible due to errors or driver removal that we no longer ++ * have anything to do, if so exit or we will consume all the CPU ++ * doing nothing ++ */ ++ while (!list_empty(&random_ops)) { ++ struct random_op *rops, *tmp; ++ ++#ifdef CONFIG_OCF_FIPS ++ if (wantcnt) ++ wantcnt = NUM_INT; /* FIPs mode can do 20000 bits or none */ ++#endif ++ ++ /* see if we can get enough entropy to make the world ++ * a better place. ++ */ ++ while (bufcnt < wantcnt && bufcnt < NUM_INT) { ++ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { ++ ++ n = (*rops->read_random)(rops->arg, &buf[bufcnt], ++ NUM_INT - bufcnt); ++ ++ /* on failure remove the random number generator */ ++ if (n == -1) { ++ list_del(&rops->random_list); ++ printk("crypto: RNG (driverid=0x%x) failed, disabling\n", ++ rops->driverid); ++ kfree(rops); ++ } else if (n > 0) ++ bufcnt += n; ++ } ++ /* give up CPU for a bit, just in case as this is a loop */ ++ schedule(); ++ } ++ ++ ++#ifdef CONFIG_OCF_FIPS ++ if (bufcnt > 0 && rndtest_buf((unsigned char *) &buf[0])) { ++ dprintk("crypto: buffer had fips errors, discarding\n"); ++ bufcnt = 0; ++ } ++#endif ++ ++ /* ++ * if we have a certified buffer, we can send some data ++ * to /dev/random and move along ++ */ ++ if (bufcnt > 0) { ++ /* add what we have */ ++ random_input_words(buf, bufcnt, bufcnt*sizeof(int)*8); ++ bufcnt = 0; ++ } ++ ++ /* give up CPU for a bit so we don't hog while filling */ ++ schedule(); ++ ++ /* wait for needing more */ ++ wantcnt = random_input_wait(); ++ ++ if (wantcnt <= 0) ++ wantcnt = 0; /* try to get some info again */ ++ else ++ /* round up to one word or we can loop forever */ ++ wantcnt = (wantcnt + (sizeof(int)*8)) / (sizeof(int)*8); ++ if (wantcnt > NUM_INT) { ++ wantcnt = NUM_INT; ++ } ++ ++ if (signal_pending(current)) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_lock_irq(¤t->sigmask_lock); ++#endif ++ flush_signals(current); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_unlock_irq(¤t->sigmask_lock); ++#endif ++ } ++ } ++ ++ kfree(buf); ++ ++bad_alloc: ++ spin_lock_irq(&random_lock); ++ randomproc = (pid_t) -1; ++ started = 0; ++ spin_unlock_irq(&random_lock); ++ ++ return retval; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/rndtest.c linux-3.0.4/crypto/ocf/rndtest.c +--- linux-3.0.4.orig/crypto/ocf/rndtest.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/rndtest.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,300 @@ ++/* $OpenBSD$ */ ++ ++/* ++ * OCF/Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by Jason L. Wright ++ * 4. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, ++ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ++ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "rndtest.h" ++ ++static struct rndtest_stats rndstats; ++ ++static void rndtest_test(struct rndtest_state *); ++ ++/* The tests themselves */ ++static int rndtest_monobit(struct rndtest_state *); ++static int rndtest_runs(struct rndtest_state *); ++static int rndtest_longruns(struct rndtest_state *); ++static int rndtest_chi_4(struct rndtest_state *); ++ ++static int rndtest_runs_check(struct rndtest_state *, int, int *); ++static void rndtest_runs_record(struct rndtest_state *, int, int *); ++ ++static const struct rndtest_testfunc { ++ int (*test)(struct rndtest_state *); ++} rndtest_funcs[] = { ++ { rndtest_monobit }, ++ { rndtest_runs }, ++ { rndtest_chi_4 }, ++ { rndtest_longruns }, ++}; ++ ++#define RNDTEST_NTESTS (sizeof(rndtest_funcs)/sizeof(rndtest_funcs[0])) ++ ++static void ++rndtest_test(struct rndtest_state *rsp) ++{ ++ int i, rv = 0; ++ ++ rndstats.rst_tests++; ++ for (i = 0; i < RNDTEST_NTESTS; i++) ++ rv |= (*rndtest_funcs[i].test)(rsp); ++ rsp->rs_discard = (rv != 0); ++} ++ ++ ++extern int crypto_debug; ++#define rndtest_verbose 2 ++#define rndtest_report(rsp, failure, fmt, a...) \ ++ { if (failure || crypto_debug) { printk("rng_test: " fmt "\n", a); } else; } ++ ++#define RNDTEST_MONOBIT_MINONES 9725 ++#define RNDTEST_MONOBIT_MAXONES 10275 ++ ++static int ++rndtest_monobit(struct rndtest_state *rsp) ++{ ++ int i, ones = 0, j; ++ u_int8_t r; ++ ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ r = rsp->rs_buf[i]; ++ for (j = 0; j < 8; j++, r <<= 1) ++ if (r & 0x80) ++ ones++; ++ } ++ if (ones > RNDTEST_MONOBIT_MINONES && ++ ones < RNDTEST_MONOBIT_MAXONES) { ++ if (rndtest_verbose > 1) ++ rndtest_report(rsp, 0, "monobit pass (%d < %d < %d)", ++ RNDTEST_MONOBIT_MINONES, ones, ++ RNDTEST_MONOBIT_MAXONES); ++ return (0); ++ } else { ++ if (rndtest_verbose) ++ rndtest_report(rsp, 1, ++ "monobit failed (%d ones)", ones); ++ rndstats.rst_monobit++; ++ return (-1); ++ } ++} ++ ++#define RNDTEST_RUNS_NINTERVAL 6 ++ ++static const struct rndtest_runs_tabs { ++ u_int16_t min, max; ++} rndtest_runs_tab[] = { ++ { 2343, 2657 }, ++ { 1135, 1365 }, ++ { 542, 708 }, ++ { 251, 373 }, ++ { 111, 201 }, ++ { 111, 201 }, ++}; ++ ++static int ++rndtest_runs(struct rndtest_state *rsp) ++{ ++ int i, j, ones, zeros, rv = 0; ++ int onei[RNDTEST_RUNS_NINTERVAL], zeroi[RNDTEST_RUNS_NINTERVAL]; ++ u_int8_t c; ++ ++ bzero(onei, sizeof(onei)); ++ bzero(zeroi, sizeof(zeroi)); ++ ones = zeros = 0; ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ c = rsp->rs_buf[i]; ++ for (j = 0; j < 8; j++, c <<= 1) { ++ if (c & 0x80) { ++ ones++; ++ rndtest_runs_record(rsp, zeros, zeroi); ++ zeros = 0; ++ } else { ++ zeros++; ++ rndtest_runs_record(rsp, ones, onei); ++ ones = 0; ++ } ++ } ++ } ++ rndtest_runs_record(rsp, ones, onei); ++ rndtest_runs_record(rsp, zeros, zeroi); ++ ++ rv |= rndtest_runs_check(rsp, 0, zeroi); ++ rv |= rndtest_runs_check(rsp, 1, onei); ++ ++ if (rv) ++ rndstats.rst_runs++; ++ ++ return (rv); ++} ++ ++static void ++rndtest_runs_record(struct rndtest_state *rsp, int len, int *intrv) ++{ ++ if (len == 0) ++ return; ++ if (len > RNDTEST_RUNS_NINTERVAL) ++ len = RNDTEST_RUNS_NINTERVAL; ++ len -= 1; ++ intrv[len]++; ++} ++ ++static int ++rndtest_runs_check(struct rndtest_state *rsp, int val, int *src) ++{ ++ int i, rv = 0; ++ ++ for (i = 0; i < RNDTEST_RUNS_NINTERVAL; i++) { ++ if (src[i] < rndtest_runs_tab[i].min || ++ src[i] > rndtest_runs_tab[i].max) { ++ rndtest_report(rsp, 1, ++ "%s interval %d failed (%d, %d-%d)", ++ val ? "ones" : "zeros", ++ i + 1, src[i], rndtest_runs_tab[i].min, ++ rndtest_runs_tab[i].max); ++ rv = -1; ++ } else { ++ rndtest_report(rsp, 0, ++ "runs pass %s interval %d (%d < %d < %d)", ++ val ? "ones" : "zeros", ++ i + 1, rndtest_runs_tab[i].min, src[i], ++ rndtest_runs_tab[i].max); ++ } ++ } ++ return (rv); ++} ++ ++static int ++rndtest_longruns(struct rndtest_state *rsp) ++{ ++ int i, j, ones = 0, zeros = 0, maxones = 0, maxzeros = 0; ++ u_int8_t c; ++ ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ c = rsp->rs_buf[i]; ++ for (j = 0; j < 8; j++, c <<= 1) { ++ if (c & 0x80) { ++ zeros = 0; ++ ones++; ++ if (ones > maxones) ++ maxones = ones; ++ } else { ++ ones = 0; ++ zeros++; ++ if (zeros > maxzeros) ++ maxzeros = zeros; ++ } ++ } ++ } ++ ++ if (maxones < 26 && maxzeros < 26) { ++ rndtest_report(rsp, 0, "longruns pass (%d ones, %d zeros)", ++ maxones, maxzeros); ++ return (0); ++ } else { ++ rndtest_report(rsp, 1, "longruns fail (%d ones, %d zeros)", ++ maxones, maxzeros); ++ rndstats.rst_longruns++; ++ return (-1); ++ } ++} ++ ++/* ++ * chi^2 test over 4 bits: (this is called the poker test in FIPS 140-2, ++ * but it is really the chi^2 test over 4 bits (the poker test as described ++ * by Knuth vol 2 is something different, and I take him as authoritative ++ * on nomenclature over NIST). ++ */ ++#define RNDTEST_CHI4_K 16 ++#define RNDTEST_CHI4_K_MASK (RNDTEST_CHI4_K - 1) ++ ++/* ++ * The unnormalized values are used so that we don't have to worry about ++ * fractional precision. The "real" value is found by: ++ * (V - 1562500) * (16 / 5000) = Vn (where V is the unnormalized value) ++ */ ++#define RNDTEST_CHI4_VMIN 1563181 /* 2.1792 */ ++#define RNDTEST_CHI4_VMAX 1576929 /* 46.1728 */ ++ ++static int ++rndtest_chi_4(struct rndtest_state *rsp) ++{ ++ unsigned int freq[RNDTEST_CHI4_K], i, sum; ++ ++ for (i = 0; i < RNDTEST_CHI4_K; i++) ++ freq[i] = 0; ++ ++ /* Get number of occurances of each 4 bit pattern */ ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ freq[(rsp->rs_buf[i] >> 4) & RNDTEST_CHI4_K_MASK]++; ++ freq[(rsp->rs_buf[i] >> 0) & RNDTEST_CHI4_K_MASK]++; ++ } ++ ++ for (i = 0, sum = 0; i < RNDTEST_CHI4_K; i++) ++ sum += freq[i] * freq[i]; ++ ++ if (sum >= 1563181 && sum <= 1576929) { ++ rndtest_report(rsp, 0, "chi^2(4): pass (sum %u)", sum); ++ return (0); ++ } else { ++ rndtest_report(rsp, 1, "chi^2(4): failed (sum %u)", sum); ++ rndstats.rst_chi++; ++ return (-1); ++ } ++} ++ ++int ++rndtest_buf(unsigned char *buf) ++{ ++ struct rndtest_state rsp; ++ ++ memset(&rsp, 0, sizeof(rsp)); ++ rsp.rs_buf = buf; ++ rndtest_test(&rsp); ++ return(rsp.rs_discard); ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/rndtest.h linux-3.0.4/crypto/ocf/rndtest.h +--- linux-3.0.4.orig/crypto/ocf/rndtest.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/rndtest.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,54 @@ ++/* $FreeBSD: src/sys/dev/rndtest/rndtest.h,v 1.1 2003/03/11 22:54:44 sam Exp $ */ ++/* $OpenBSD$ */ ++ ++/* ++ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by Jason L. Wright ++ * 4. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, ++ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ++ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++/* Some of the tests depend on these values */ ++#define RNDTEST_NBYTES 2500 ++#define RNDTEST_NBITS (8 * RNDTEST_NBYTES) ++ ++struct rndtest_state { ++ int rs_discard; /* discard/accept random data */ ++ u_int8_t *rs_buf; ++}; ++ ++struct rndtest_stats { ++ u_int32_t rst_discard; /* number of bytes discarded */ ++ u_int32_t rst_tests; /* number of test runs */ ++ u_int32_t rst_monobit; /* monobit test failures */ ++ u_int32_t rst_runs; /* 0/1 runs failures */ ++ u_int32_t rst_longruns; /* longruns failures */ ++ u_int32_t rst_chi; /* chi^2 failures */ ++}; ++ ++extern int rndtest_buf(unsigned char *buf); +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/Makefile linux-3.0.4/crypto/ocf/safe/Makefile +--- linux-3.0.4.orig/crypto/ocf/safe/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_SAFE) += safe.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/hmachack.h linux-3.0.4/crypto/ocf/safe/hmachack.h +--- linux-3.0.4.orig/crypto/ocf/safe/hmachack.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/hmachack.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,37 @@ ++/* ++ * until we find a cleaner way, include the BSD md5/sha1 code ++ * here ++ */ ++#ifdef HMAC_HACK ++#define LITTLE_ENDIAN 1234 ++#define BIG_ENDIAN 4321 ++#ifdef __LITTLE_ENDIAN ++#define BYTE_ORDER LITTLE_ENDIAN ++#endif ++#ifdef __BIG_ENDIAN ++#define BYTE_ORDER BIG_ENDIAN ++#endif ++ ++u_int8_t hmac_ipad_buffer[64] = { ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36 ++}; ++ ++u_int8_t hmac_opad_buffer[64] = { ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C ++}; ++#endif /* HMAC_HACK */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/md5.c linux-3.0.4/crypto/ocf/safe/md5.c +--- linux-3.0.4.orig/crypto/ocf/safe/md5.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/md5.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,308 @@ ++/* $KAME: md5.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++#if 0 ++#include ++__FBSDID("$FreeBSD: src/sys/crypto/md5.c,v 1.9 2004/01/27 19:49:19 des Exp $"); ++ ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++#define SHIFT(X, s) (((X) << (s)) | ((X) >> (32 - (s)))) ++ ++#define F(X, Y, Z) (((X) & (Y)) | ((~X) & (Z))) ++#define G(X, Y, Z) (((X) & (Z)) | ((Y) & (~Z))) ++#define H(X, Y, Z) ((X) ^ (Y) ^ (Z)) ++#define I(X, Y, Z) ((Y) ^ ((X) | (~Z))) ++ ++#define ROUND1(a, b, c, d, k, s, i) { \ ++ (a) = (a) + F((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define ROUND2(a, b, c, d, k, s, i) { \ ++ (a) = (a) + G((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define ROUND3(a, b, c, d, k, s, i) { \ ++ (a) = (a) + H((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define ROUND4(a, b, c, d, k, s, i) { \ ++ (a) = (a) + I((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define Sa 7 ++#define Sb 12 ++#define Sc 17 ++#define Sd 22 ++ ++#define Se 5 ++#define Sf 9 ++#define Sg 14 ++#define Sh 20 ++ ++#define Si 4 ++#define Sj 11 ++#define Sk 16 ++#define Sl 23 ++ ++#define Sm 6 ++#define Sn 10 ++#define So 15 ++#define Sp 21 ++ ++#define MD5_A0 0x67452301 ++#define MD5_B0 0xefcdab89 ++#define MD5_C0 0x98badcfe ++#define MD5_D0 0x10325476 ++ ++/* Integer part of 4294967296 times abs(sin(i)), where i is in radians. */ ++static const u_int32_t T[65] = { ++ 0, ++ 0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee, ++ 0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501, ++ 0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be, ++ 0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821, ++ ++ 0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa, ++ 0xd62f105d, 0x2441453, 0xd8a1e681, 0xe7d3fbc8, ++ 0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed, ++ 0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a, ++ ++ 0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c, ++ 0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70, ++ 0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x4881d05, ++ 0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665, ++ ++ 0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039, ++ 0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1, ++ 0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1, ++ 0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391, ++}; ++ ++static const u_int8_t md5_paddat[MD5_BUFLEN] = { ++ 0x80, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++}; ++ ++static void md5_calc(u_int8_t *, md5_ctxt *); ++ ++void md5_init(ctxt) ++ md5_ctxt *ctxt; ++{ ++ ctxt->md5_n = 0; ++ ctxt->md5_i = 0; ++ ctxt->md5_sta = MD5_A0; ++ ctxt->md5_stb = MD5_B0; ++ ctxt->md5_stc = MD5_C0; ++ ctxt->md5_std = MD5_D0; ++ bzero(ctxt->md5_buf, sizeof(ctxt->md5_buf)); ++} ++ ++void md5_loop(ctxt, input, len) ++ md5_ctxt *ctxt; ++ u_int8_t *input; ++ u_int len; /* number of bytes */ ++{ ++ u_int gap, i; ++ ++ ctxt->md5_n += len * 8; /* byte to bit */ ++ gap = MD5_BUFLEN - ctxt->md5_i; ++ ++ if (len >= gap) { ++ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), ++ gap); ++ md5_calc(ctxt->md5_buf, ctxt); ++ ++ for (i = gap; i + MD5_BUFLEN <= len; i += MD5_BUFLEN) { ++ md5_calc((u_int8_t *)(input + i), ctxt); ++ } ++ ++ ctxt->md5_i = len - i; ++ bcopy((void *)(input + i), (void *)ctxt->md5_buf, ctxt->md5_i); ++ } else { ++ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), ++ len); ++ ctxt->md5_i += len; ++ } ++} ++ ++void md5_pad(ctxt) ++ md5_ctxt *ctxt; ++{ ++ u_int gap; ++ ++ /* Don't count up padding. Keep md5_n. */ ++ gap = MD5_BUFLEN - ctxt->md5_i; ++ if (gap > 8) { ++ bcopy(md5_paddat, ++ (void *)(ctxt->md5_buf + ctxt->md5_i), ++ gap - sizeof(ctxt->md5_n)); ++ } else { ++ /* including gap == 8 */ ++ bcopy(md5_paddat, (void *)(ctxt->md5_buf + ctxt->md5_i), ++ gap); ++ md5_calc(ctxt->md5_buf, ctxt); ++ bcopy((md5_paddat + gap), ++ (void *)ctxt->md5_buf, ++ MD5_BUFLEN - sizeof(ctxt->md5_n)); ++ } ++ ++ /* 8 byte word */ ++#if BYTE_ORDER == LITTLE_ENDIAN ++ bcopy(&ctxt->md5_n8[0], &ctxt->md5_buf[56], 8); ++#endif ++#if BYTE_ORDER == BIG_ENDIAN ++ ctxt->md5_buf[56] = ctxt->md5_n8[7]; ++ ctxt->md5_buf[57] = ctxt->md5_n8[6]; ++ ctxt->md5_buf[58] = ctxt->md5_n8[5]; ++ ctxt->md5_buf[59] = ctxt->md5_n8[4]; ++ ctxt->md5_buf[60] = ctxt->md5_n8[3]; ++ ctxt->md5_buf[61] = ctxt->md5_n8[2]; ++ ctxt->md5_buf[62] = ctxt->md5_n8[1]; ++ ctxt->md5_buf[63] = ctxt->md5_n8[0]; ++#endif ++ ++ md5_calc(ctxt->md5_buf, ctxt); ++} ++ ++void md5_result(digest, ctxt) ++ u_int8_t *digest; ++ md5_ctxt *ctxt; ++{ ++ /* 4 byte words */ ++#if BYTE_ORDER == LITTLE_ENDIAN ++ bcopy(&ctxt->md5_st8[0], digest, 16); ++#endif ++#if BYTE_ORDER == BIG_ENDIAN ++ digest[ 0] = ctxt->md5_st8[ 3]; digest[ 1] = ctxt->md5_st8[ 2]; ++ digest[ 2] = ctxt->md5_st8[ 1]; digest[ 3] = ctxt->md5_st8[ 0]; ++ digest[ 4] = ctxt->md5_st8[ 7]; digest[ 5] = ctxt->md5_st8[ 6]; ++ digest[ 6] = ctxt->md5_st8[ 5]; digest[ 7] = ctxt->md5_st8[ 4]; ++ digest[ 8] = ctxt->md5_st8[11]; digest[ 9] = ctxt->md5_st8[10]; ++ digest[10] = ctxt->md5_st8[ 9]; digest[11] = ctxt->md5_st8[ 8]; ++ digest[12] = ctxt->md5_st8[15]; digest[13] = ctxt->md5_st8[14]; ++ digest[14] = ctxt->md5_st8[13]; digest[15] = ctxt->md5_st8[12]; ++#endif ++} ++ ++static void md5_calc(b64, ctxt) ++ u_int8_t *b64; ++ md5_ctxt *ctxt; ++{ ++ u_int32_t A = ctxt->md5_sta; ++ u_int32_t B = ctxt->md5_stb; ++ u_int32_t C = ctxt->md5_stc; ++ u_int32_t D = ctxt->md5_std; ++#if BYTE_ORDER == LITTLE_ENDIAN ++ u_int32_t *X = (u_int32_t *)b64; ++#endif ++#if BYTE_ORDER == BIG_ENDIAN ++ /* 4 byte words */ ++ /* what a brute force but fast! */ ++ u_int32_t X[16]; ++ u_int8_t *y = (u_int8_t *)X; ++ y[ 0] = b64[ 3]; y[ 1] = b64[ 2]; y[ 2] = b64[ 1]; y[ 3] = b64[ 0]; ++ y[ 4] = b64[ 7]; y[ 5] = b64[ 6]; y[ 6] = b64[ 5]; y[ 7] = b64[ 4]; ++ y[ 8] = b64[11]; y[ 9] = b64[10]; y[10] = b64[ 9]; y[11] = b64[ 8]; ++ y[12] = b64[15]; y[13] = b64[14]; y[14] = b64[13]; y[15] = b64[12]; ++ y[16] = b64[19]; y[17] = b64[18]; y[18] = b64[17]; y[19] = b64[16]; ++ y[20] = b64[23]; y[21] = b64[22]; y[22] = b64[21]; y[23] = b64[20]; ++ y[24] = b64[27]; y[25] = b64[26]; y[26] = b64[25]; y[27] = b64[24]; ++ y[28] = b64[31]; y[29] = b64[30]; y[30] = b64[29]; y[31] = b64[28]; ++ y[32] = b64[35]; y[33] = b64[34]; y[34] = b64[33]; y[35] = b64[32]; ++ y[36] = b64[39]; y[37] = b64[38]; y[38] = b64[37]; y[39] = b64[36]; ++ y[40] = b64[43]; y[41] = b64[42]; y[42] = b64[41]; y[43] = b64[40]; ++ y[44] = b64[47]; y[45] = b64[46]; y[46] = b64[45]; y[47] = b64[44]; ++ y[48] = b64[51]; y[49] = b64[50]; y[50] = b64[49]; y[51] = b64[48]; ++ y[52] = b64[55]; y[53] = b64[54]; y[54] = b64[53]; y[55] = b64[52]; ++ y[56] = b64[59]; y[57] = b64[58]; y[58] = b64[57]; y[59] = b64[56]; ++ y[60] = b64[63]; y[61] = b64[62]; y[62] = b64[61]; y[63] = b64[60]; ++#endif ++ ++ ROUND1(A, B, C, D, 0, Sa, 1); ROUND1(D, A, B, C, 1, Sb, 2); ++ ROUND1(C, D, A, B, 2, Sc, 3); ROUND1(B, C, D, A, 3, Sd, 4); ++ ROUND1(A, B, C, D, 4, Sa, 5); ROUND1(D, A, B, C, 5, Sb, 6); ++ ROUND1(C, D, A, B, 6, Sc, 7); ROUND1(B, C, D, A, 7, Sd, 8); ++ ROUND1(A, B, C, D, 8, Sa, 9); ROUND1(D, A, B, C, 9, Sb, 10); ++ ROUND1(C, D, A, B, 10, Sc, 11); ROUND1(B, C, D, A, 11, Sd, 12); ++ ROUND1(A, B, C, D, 12, Sa, 13); ROUND1(D, A, B, C, 13, Sb, 14); ++ ROUND1(C, D, A, B, 14, Sc, 15); ROUND1(B, C, D, A, 15, Sd, 16); ++ ++ ROUND2(A, B, C, D, 1, Se, 17); ROUND2(D, A, B, C, 6, Sf, 18); ++ ROUND2(C, D, A, B, 11, Sg, 19); ROUND2(B, C, D, A, 0, Sh, 20); ++ ROUND2(A, B, C, D, 5, Se, 21); ROUND2(D, A, B, C, 10, Sf, 22); ++ ROUND2(C, D, A, B, 15, Sg, 23); ROUND2(B, C, D, A, 4, Sh, 24); ++ ROUND2(A, B, C, D, 9, Se, 25); ROUND2(D, A, B, C, 14, Sf, 26); ++ ROUND2(C, D, A, B, 3, Sg, 27); ROUND2(B, C, D, A, 8, Sh, 28); ++ ROUND2(A, B, C, D, 13, Se, 29); ROUND2(D, A, B, C, 2, Sf, 30); ++ ROUND2(C, D, A, B, 7, Sg, 31); ROUND2(B, C, D, A, 12, Sh, 32); ++ ++ ROUND3(A, B, C, D, 5, Si, 33); ROUND3(D, A, B, C, 8, Sj, 34); ++ ROUND3(C, D, A, B, 11, Sk, 35); ROUND3(B, C, D, A, 14, Sl, 36); ++ ROUND3(A, B, C, D, 1, Si, 37); ROUND3(D, A, B, C, 4, Sj, 38); ++ ROUND3(C, D, A, B, 7, Sk, 39); ROUND3(B, C, D, A, 10, Sl, 40); ++ ROUND3(A, B, C, D, 13, Si, 41); ROUND3(D, A, B, C, 0, Sj, 42); ++ ROUND3(C, D, A, B, 3, Sk, 43); ROUND3(B, C, D, A, 6, Sl, 44); ++ ROUND3(A, B, C, D, 9, Si, 45); ROUND3(D, A, B, C, 12, Sj, 46); ++ ROUND3(C, D, A, B, 15, Sk, 47); ROUND3(B, C, D, A, 2, Sl, 48); ++ ++ ROUND4(A, B, C, D, 0, Sm, 49); ROUND4(D, A, B, C, 7, Sn, 50); ++ ROUND4(C, D, A, B, 14, So, 51); ROUND4(B, C, D, A, 5, Sp, 52); ++ ROUND4(A, B, C, D, 12, Sm, 53); ROUND4(D, A, B, C, 3, Sn, 54); ++ ROUND4(C, D, A, B, 10, So, 55); ROUND4(B, C, D, A, 1, Sp, 56); ++ ROUND4(A, B, C, D, 8, Sm, 57); ROUND4(D, A, B, C, 15, Sn, 58); ++ ROUND4(C, D, A, B, 6, So, 59); ROUND4(B, C, D, A, 13, Sp, 60); ++ ROUND4(A, B, C, D, 4, Sm, 61); ROUND4(D, A, B, C, 11, Sn, 62); ++ ROUND4(C, D, A, B, 2, So, 63); ROUND4(B, C, D, A, 9, Sp, 64); ++ ++ ctxt->md5_sta += A; ++ ctxt->md5_stb += B; ++ ctxt->md5_stc += C; ++ ctxt->md5_std += D; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/md5.h linux-3.0.4/crypto/ocf/safe/md5.h +--- linux-3.0.4.orig/crypto/ocf/safe/md5.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/md5.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,76 @@ ++/* $FreeBSD: src/sys/crypto/md5.h,v 1.4 2002/03/20 05:13:50 alfred Exp $ */ ++/* $KAME: md5.h,v 1.4 2000/03/27 04:36:22 sumikawa Exp $ */ ++ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++#ifndef _NETINET6_MD5_H_ ++#define _NETINET6_MD5_H_ ++ ++#define MD5_BUFLEN 64 ++ ++typedef struct { ++ union { ++ u_int32_t md5_state32[4]; ++ u_int8_t md5_state8[16]; ++ } md5_st; ++ ++#define md5_sta md5_st.md5_state32[0] ++#define md5_stb md5_st.md5_state32[1] ++#define md5_stc md5_st.md5_state32[2] ++#define md5_std md5_st.md5_state32[3] ++#define md5_st8 md5_st.md5_state8 ++ ++ union { ++ u_int64_t md5_count64; ++ u_int8_t md5_count8[8]; ++ } md5_count; ++#define md5_n md5_count.md5_count64 ++#define md5_n8 md5_count.md5_count8 ++ ++ u_int md5_i; ++ u_int8_t md5_buf[MD5_BUFLEN]; ++} md5_ctxt; ++ ++extern void md5_init(md5_ctxt *); ++extern void md5_loop(md5_ctxt *, u_int8_t *, u_int); ++extern void md5_pad(md5_ctxt *); ++extern void md5_result(u_int8_t *, md5_ctxt *); ++ ++/* compatibility */ ++#define MD5_CTX md5_ctxt ++#define MD5Init(x) md5_init((x)) ++#define MD5Update(x, y, z) md5_loop((x), (y), (z)) ++#define MD5Final(x, y) \ ++do { \ ++ md5_pad((y)); \ ++ md5_result((x), (y)); \ ++} while (0) ++ ++#endif /* ! _NETINET6_MD5_H_*/ +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/safe.c linux-3.0.4/crypto/ocf/safe/safe.c +--- linux-3.0.4.orig/crypto/ocf/safe/safe.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/safe.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,2230 @@ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2004-2010 David McCullough ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2003 Sam Leffler, Errno Consulting ++ * Copyright (c) 2003 Global Technology Associates, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++__FBSDID("$FreeBSD: src/sys/dev/safe/safe.c,v 1.18 2007/03/21 03:42:50 sam Exp $"); ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * SafeNet SafeXcel-1141 hardware crypto accelerator ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#if 1 ++#define DPRINTF(a) do { \ ++ if (debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_dev) : "safe"); \ ++ printk a; \ ++ } \ ++ } while (0) ++#else ++#define DPRINTF(a) ++#endif ++ ++/* ++ * until we find a cleaner way, include the BSD md5/sha1 code ++ * here ++ */ ++#define HMAC_HACK 1 ++#ifdef HMAC_HACK ++#include ++#include ++#include ++#include ++#include ++#endif /* HMAC_HACK */ ++ ++/* add proc entry for this */ ++struct safe_stats safestats; ++ ++#define debug safe_debug ++int safe_debug = 0; ++module_param(safe_debug, int, 0644); ++MODULE_PARM_DESC(safe_debug, "Enable debug"); ++ ++static void safe_callback(struct safe_softc *, struct safe_ringentry *); ++static void safe_feed(struct safe_softc *, struct safe_ringentry *); ++#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) ++static void safe_rng_init(struct safe_softc *); ++int safe_rngbufsize = 8; /* 32 bytes each read */ ++module_param(safe_rngbufsize, int, 0644); ++MODULE_PARM_DESC(safe_rngbufsize, "RNG polling buffer size (32-bit words)"); ++int safe_rngmaxalarm = 8; /* max alarms before reset */ ++module_param(safe_rngmaxalarm, int, 0644); ++MODULE_PARM_DESC(safe_rngmaxalarm, "RNG max alarms before reset"); ++#endif /* SAFE_NO_RNG */ ++ ++static void safe_totalreset(struct safe_softc *sc); ++static int safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op); ++static int safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op); ++static int safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re); ++static int safe_kprocess(device_t dev, struct cryptkop *krp, int hint); ++static int safe_kstart(struct safe_softc *sc); ++static int safe_ksigbits(struct safe_softc *sc, struct crparam *cr); ++static void safe_kfeed(struct safe_softc *sc); ++static void safe_kpoll(unsigned long arg); ++static void safe_kload_reg(struct safe_softc *sc, u_int32_t off, ++ u_int32_t len, struct crparam *n); ++ ++static int safe_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int safe_freesession(device_t, u_int64_t); ++static int safe_process(device_t, struct cryptop *, int); ++ ++static device_method_t safe_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, safe_newsession), ++ DEVMETHOD(cryptodev_freesession,safe_freesession), ++ DEVMETHOD(cryptodev_process, safe_process), ++ DEVMETHOD(cryptodev_kprocess, safe_kprocess), ++}; ++ ++#define READ_REG(sc,r) readl((sc)->sc_base_addr + (r)) ++#define WRITE_REG(sc,r,val) writel((val), (sc)->sc_base_addr + (r)) ++ ++#define SAFE_MAX_CHIPS 8 ++static struct safe_softc *safe_chip_idx[SAFE_MAX_CHIPS]; ++ ++/* ++ * split our buffers up into safe DMAable byte fragments to avoid lockup ++ * bug in 1141 HW on rev 1.0. ++ */ ++ ++static int ++pci_map_linear( ++ struct safe_softc *sc, ++ struct safe_operand *buf, ++ void *addr, ++ int len) ++{ ++ dma_addr_t tmp; ++ int chunk, tlen = len; ++ ++ tmp = pci_map_single(sc->sc_pcidev, addr, len, PCI_DMA_BIDIRECTIONAL); ++ ++ buf->mapsize += len; ++ while (len > 0) { ++ chunk = (len > sc->sc_max_dsize) ? sc->sc_max_dsize : len; ++ buf->segs[buf->nsegs].ds_addr = tmp; ++ buf->segs[buf->nsegs].ds_len = chunk; ++ buf->segs[buf->nsegs].ds_tlen = tlen; ++ buf->nsegs++; ++ tmp += chunk; ++ len -= chunk; ++ tlen = 0; ++ } ++ return 0; ++} ++ ++/* ++ * map in a given uio buffer (great on some arches :-) ++ */ ++ ++static int ++pci_map_uio(struct safe_softc *sc, struct safe_operand *buf, struct uio *uio) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int n; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ buf->mapsize = 0; ++ buf->nsegs = 0; ++ ++ for (n = 0; n < uio->uio_iovcnt; n++) { ++ pci_map_linear(sc, buf, iov->iov_base, iov->iov_len); ++ iov++; ++ } ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++/* ++ * map in a given sk_buff ++ */ ++ ++static int ++pci_map_skb(struct safe_softc *sc,struct safe_operand *buf,struct sk_buff *skb) ++{ ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ buf->mapsize = 0; ++ buf->nsegs = 0; ++ ++ pci_map_linear(sc, buf, skb->data, skb_headlen(skb)); ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { ++ pci_map_linear(sc, buf, ++ page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ skb_shinfo(skb)->frags[i].size); ++ } ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++ ++#if 0 /* not needed at this time */ ++static void ++pci_sync_operand(struct safe_softc *sc, struct safe_operand *buf) ++{ ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ for (i = 0; i < buf->nsegs; i++) ++ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); ++} ++#endif ++ ++static void ++pci_unmap_operand(struct safe_softc *sc, struct safe_operand *buf) ++{ ++ int i; ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ for (i = 0; i < buf->nsegs; i++) { ++ if (buf->segs[i].ds_tlen) { ++ DPRINTF(("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); ++ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_tlen, PCI_DMA_BIDIRECTIONAL); ++ DPRINTF(("%s - unmap %d 0x%x %d done\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); ++ } ++ buf->segs[i].ds_addr = 0; ++ buf->segs[i].ds_len = 0; ++ buf->segs[i].ds_tlen = 0; ++ } ++ buf->nsegs = 0; ++ buf->mapsize = 0; ++ buf->map = 0; ++} ++ ++ ++/* ++ * SafeXcel Interrupt routine ++ */ ++static irqreturn_t ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++safe_intr(int irq, void *arg) ++#else ++safe_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct safe_softc *sc = arg; ++ int stat; ++ unsigned long flags; ++ ++ stat = READ_REG(sc, SAFE_HM_STAT); ++ ++ DPRINTF(("%s(stat=0x%x)\n", __FUNCTION__, stat)); ++ ++ if (stat == 0) /* shared irq, not for us */ ++ return IRQ_NONE; ++ ++ WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ ++ ++ if ((stat & SAFE_INT_PE_DDONE)) { ++ /* ++ * Descriptor(s) done; scan the ring and ++ * process completed operations. ++ */ ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ while (sc->sc_back != sc->sc_front) { ++ struct safe_ringentry *re = sc->sc_back; ++ ++#ifdef SAFE_DEBUG ++ if (debug) { ++ safe_dump_ringstate(sc, __func__); ++ safe_dump_request(sc, __func__, re); ++ } ++#endif ++ /* ++ * safe_process marks ring entries that were allocated ++ * but not used with a csr of zero. This insures the ++ * ring front pointer never needs to be set backwards ++ * in the event that an entry is allocated but not used ++ * because of a setup error. ++ */ ++ DPRINTF(("%s re->re_desc.d_csr=0x%x\n", __FUNCTION__, re->re_desc.d_csr)); ++ if (re->re_desc.d_csr != 0) { ++ if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) { ++ DPRINTF(("%s !CSR_IS_DONE\n", __FUNCTION__)); ++ break; ++ } ++ if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) { ++ DPRINTF(("%s !LEN_IS_DONE\n", __FUNCTION__)); ++ break; ++ } ++ sc->sc_nqchip--; ++ safe_callback(sc, re); ++ } ++ if (++(sc->sc_back) == sc->sc_ringtop) ++ sc->sc_back = sc->sc_ring; ++ } ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ } ++ ++ /* ++ * Check to see if we got any DMA Error ++ */ ++ if (stat & SAFE_INT_PE_ERROR) { ++ printk("%s: dmaerr dmastat %08x\n", device_get_nameunit(sc->sc_dev), ++ (int)READ_REG(sc, SAFE_PE_DMASTAT)); ++ safestats.st_dmaerr++; ++ safe_totalreset(sc); ++#if 0 ++ safe_feed(sc); ++#endif ++ } ++ ++ if (sc->sc_needwakeup) { /* XXX check high watermark */ ++ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); ++ DPRINTF(("%s: wakeup crypto %x\n", __func__, ++ sc->sc_needwakeup)); ++ sc->sc_needwakeup &= ~wakeup; ++ crypto_unblock(sc->sc_cid, wakeup); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * safe_feed() - post a request to chip ++ */ ++static void ++safe_feed(struct safe_softc *sc, struct safe_ringentry *re) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++#ifdef SAFE_DEBUG ++ if (debug) { ++ safe_dump_ringstate(sc, __func__); ++ safe_dump_request(sc, __func__, re); ++ } ++#endif ++ sc->sc_nqchip++; ++ if (sc->sc_nqchip > safestats.st_maxqchip) ++ safestats.st_maxqchip = sc->sc_nqchip; ++ /* poke h/w to check descriptor ring, any value can be written */ ++ WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); ++} ++ ++#define N(a) (sizeof(a) / sizeof (a[0])) ++static void ++safe_setup_enckey(struct safe_session *ses, caddr_t key) ++{ ++ int i; ++ ++ bcopy(key, ses->ses_key, ses->ses_klen / 8); ++ ++ /* PE is little-endian, insure proper byte order */ ++ for (i = 0; i < N(ses->ses_key); i++) ++ ses->ses_key[i] = htole32(ses->ses_key[i]); ++} ++ ++static void ++safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) ++{ ++#ifdef HMAC_HACK ++ MD5_CTX md5ctx; ++ SHA1_CTX sha1ctx; ++ int i; ++ ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_IPAD_VAL; ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_ipad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_opad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_OPAD_VAL; ++ ++#if 0 ++ /* ++ * this code prevents SHA working on a BE host, ++ * so it is obviously wrong. I think the byte ++ * swap setup we do with the chip fixes this for us ++ */ ++ ++ /* PE is little-endian, insure proper byte order */ ++ for (i = 0; i < N(ses->ses_hminner); i++) { ++ ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); ++ ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); ++ } ++#endif ++#else /* HMAC_HACK */ ++ printk("safe: md5/sha not implemented\n"); ++#endif /* HMAC_HACK */ ++} ++#undef N ++ ++/* ++ * Allocate a new 'session' and return an encoded session id. 'sidp' ++ * contains our registration id, and should contain an encoded session ++ * id on successful allocation. ++ */ ++static int ++safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct safe_session *ses = NULL; ++ int sesn; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sidp == NULL || cri == NULL || sc == NULL) ++ return (EINVAL); ++ ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1_HMAC || ++ c->cri_alg == CRYPTO_NULL_HMAC) { ++ if (macini) ++ return (EINVAL); ++ macini = c; ++ } else if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC || ++ c->cri_alg == CRYPTO_NULL_CBC) { ++ if (encini) ++ return (EINVAL); ++ encini = c; ++ } else ++ return (EINVAL); ++ } ++ if (encini == NULL && macini == NULL) ++ return (EINVAL); ++ if (encini) { /* validate key length */ ++ switch (encini->cri_alg) { ++ case CRYPTO_DES_CBC: ++ if (encini->cri_klen != 64) ++ return (EINVAL); ++ break; ++ case CRYPTO_3DES_CBC: ++ if (encini->cri_klen != 192) ++ return (EINVAL); ++ break; ++ case CRYPTO_AES_CBC: ++ if (encini->cri_klen != 128 && ++ encini->cri_klen != 192 && ++ encini->cri_klen != 256) ++ return (EINVAL); ++ break; ++ } ++ } ++ ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct safe_session *) ++ kmalloc(sizeof(struct safe_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, sizeof(struct safe_session)); ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn].ses_used == 0) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sesn = sc->sc_nsessions; ++ ses = (struct safe_session *) ++ kmalloc((sesn + 1) * sizeof(struct safe_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, (sesn + 1) * sizeof(struct safe_session)); ++ bcopy(sc->sc_sessions, ses, sesn * ++ sizeof(struct safe_session)); ++ bzero(sc->sc_sessions, sesn * ++ sizeof(struct safe_session)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ ++ bzero(ses, sizeof(struct safe_session)); ++ ses->ses_used = 1; ++ ++ if (encini) { ++ ses->ses_klen = encini->cri_klen; ++ if (encini->cri_key != NULL) ++ safe_setup_enckey(ses, encini->cri_key); ++ } ++ ++ if (macini) { ++ ses->ses_mlen = macini->cri_mlen; ++ if (ses->ses_mlen == 0) { ++ if (macini->cri_alg == CRYPTO_MD5_HMAC) ++ ses->ses_mlen = MD5_HASH_LEN; ++ else ++ ses->ses_mlen = SHA1_HASH_LEN; ++ } ++ ++ if (macini->cri_key != NULL) { ++ safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, ++ macini->cri_klen / 8); ++ } ++ } ++ ++ *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); ++ return (0); ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++safe_freesession(device_t dev, u_int64_t tid) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ int session, ret; ++ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sc == NULL) ++ return (EINVAL); ++ ++ session = SAFE_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); ++ ret = 0; ++ } else ++ ret = EINVAL; ++ return (ret); ++} ++ ++ ++static int ++safe_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ int err = 0, i, nicealign, uniform; ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ int bypass, oplen, ivsize; ++ caddr_t iv; ++ int16_t coffset; ++ struct safe_session *ses; ++ struct safe_ringentry *re; ++ struct safe_sarec *sa; ++ struct safe_pdesc *pd; ++ u_int32_t cmd0, cmd1, staterec, rand_iv[4]; ++ unsigned long flags; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { ++ safestats.st_invalid++; ++ return (EINVAL); ++ } ++ if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { ++ safestats.st_badsession++; ++ return (EINVAL); ++ } ++ ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { ++ safestats.st_ringfull++; ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ return (ERESTART); ++ } ++ re = sc->sc_front; ++ ++ staterec = re->re_sa.sa_staterec; /* save */ ++ /* NB: zero everything but the PE descriptor */ ++ bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); ++ re->re_sa.sa_staterec = staterec; /* restore */ ++ ++ re->re_crp = crp; ++ re->re_sesn = SAFE_SESSION(crp->crp_sid); ++ ++ re->re_src.nsegs = 0; ++ re->re_dst.nsegs = 0; ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ re->re_src_skb = (struct sk_buff *)crp->crp_buf; ++ re->re_dst_skb = (struct sk_buff *)crp->crp_buf; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ re->re_src_io = (struct uio *)crp->crp_buf; ++ re->re_dst_io = (struct uio *)crp->crp_buf; ++ } else { ++ safestats.st_badflags++; ++ err = EINVAL; ++ goto errout; /* XXX we don't handle contiguous blocks! */ ++ } ++ ++ sa = &re->re_sa; ++ ses = &sc->sc_sessions[re->re_sesn]; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ safestats.st_nodesc++; ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ ++ cmd1 = 0; ++ if (crd2 == NULL) { ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_NULL_HMAC) { ++ maccrd = crd1; ++ enccrd = NULL; ++ cmd0 |= SAFE_SA_CMD0_OP_HASH; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_NULL_CBC) { ++ maccrd = NULL; ++ enccrd = crd1; ++ cmd0 |= SAFE_SA_CMD0_OP_CRYPT; ++ } else { ++ safestats.st_badalg++; ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_NULL_HMAC) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC || ++ crd2->crd_alg == CRYPTO_NULL_CBC) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_NULL_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC || ++ crd2->crd_alg == CRYPTO_NULL_HMAC) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ safestats.st_badalg++; ++ err = EINVAL; ++ goto errout; ++ } ++ cmd0 |= SAFE_SA_CMD0_OP_BOTH; ++ } ++ ++ if (enccrd) { ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) ++ safe_setup_enckey(ses, enccrd->crd_key); ++ ++ if (enccrd->crd_alg == CRYPTO_DES_CBC) { ++ cmd0 |= SAFE_SA_CMD0_DES; ++ cmd1 |= SAFE_SA_CMD1_CBC; ++ ivsize = 2*sizeof(u_int32_t); ++ } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { ++ cmd0 |= SAFE_SA_CMD0_3DES; ++ cmd1 |= SAFE_SA_CMD1_CBC; ++ ivsize = 2*sizeof(u_int32_t); ++ } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { ++ cmd0 |= SAFE_SA_CMD0_AES; ++ cmd1 |= SAFE_SA_CMD1_CBC; ++ if (ses->ses_klen == 128) ++ cmd1 |= SAFE_SA_CMD1_AES128; ++ else if (ses->ses_klen == 192) ++ cmd1 |= SAFE_SA_CMD1_AES192; ++ else ++ cmd1 |= SAFE_SA_CMD1_AES256; ++ ivsize = 4*sizeof(u_int32_t); ++ } else { ++ cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; ++ ivsize = 0; ++ } ++ ++ /* ++ * Setup encrypt/decrypt state. When using basic ops ++ * we can't use an inline IV because hash/crypt offset ++ * must be from the end of the IV to the start of the ++ * crypt data and this leaves out the preceding header ++ * from the hash calculation. Instead we place the IV ++ * in the state record and set the hash/crypt offset to ++ * copy both the header+IV. ++ */ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ cmd0 |= SAFE_SA_CMD0_OUTBOUND; ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ iv = enccrd->crd_iv; ++ else ++ read_random((iv = (caddr_t) &rand_iv[0]), sizeof(rand_iv)); ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, iv); ++ } ++ bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); ++ /* make iv LE */ ++ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) ++ re->re_sastate.sa_saved_iv[i] = ++ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); ++ cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; ++ re->re_flags |= SAFE_QFLAGS_COPYOUTIV; ++ } else { ++ cmd0 |= SAFE_SA_CMD0_INBOUND; ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ bcopy(enccrd->crd_iv, ++ re->re_sastate.sa_saved_iv, ivsize); ++ } else { ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, ++ (caddr_t)re->re_sastate.sa_saved_iv); ++ } ++ /* make iv LE */ ++ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) ++ re->re_sastate.sa_saved_iv[i] = ++ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); ++ cmd0 |= SAFE_SA_CMD0_IVLD_STATE; ++ } ++ /* ++ * For basic encryption use the zero pad algorithm. ++ * This pads results to an 8-byte boundary and ++ * suppresses padding verification for inbound (i.e. ++ * decrypt) operations. ++ * ++ * NB: Not sure if the 8-byte pad boundary is a problem. ++ */ ++ cmd0 |= SAFE_SA_CMD0_PAD_ZERO; ++ ++ /* XXX assert key bufs have the same size */ ++ bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); ++ } ++ ++ if (maccrd) { ++ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ safe_setup_mackey(ses, maccrd->crd_alg, ++ maccrd->crd_key, maccrd->crd_klen / 8); ++ } ++ ++ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { ++ cmd0 |= SAFE_SA_CMD0_MD5; ++ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ ++ } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { ++ cmd0 |= SAFE_SA_CMD0_SHA1; ++ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ ++ } else { ++ cmd0 |= SAFE_SA_CMD0_HASH_NULL; ++ } ++ /* ++ * Digest data is loaded from the SA and the hash ++ * result is saved to the state block where we ++ * retrieve it for return to the caller. ++ */ ++ /* XXX assert digest bufs have the same size */ ++ bcopy(ses->ses_hminner, sa->sa_indigest, ++ sizeof(sa->sa_indigest)); ++ bcopy(ses->ses_hmouter, sa->sa_outdigest, ++ sizeof(sa->sa_outdigest)); ++ ++ cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; ++ re->re_flags |= SAFE_QFLAGS_COPYOUTICV; ++ } ++ ++ if (enccrd && maccrd) { ++ /* ++ * The offset from hash data to the start of ++ * crypt data is the difference in the skips. ++ */ ++ bypass = maccrd->crd_skip; ++ coffset = enccrd->crd_skip - maccrd->crd_skip; ++ if (coffset < 0) { ++ DPRINTF(("%s: hash does not precede crypt; " ++ "mac skip %u enc skip %u\n", ++ __func__, maccrd->crd_skip, enccrd->crd_skip)); ++ safestats.st_skipmismatch++; ++ err = EINVAL; ++ goto errout; ++ } ++ oplen = enccrd->crd_skip + enccrd->crd_len; ++ if (maccrd->crd_skip + maccrd->crd_len != oplen) { ++ DPRINTF(("%s: hash amount %u != crypt amount %u\n", ++ __func__, maccrd->crd_skip + maccrd->crd_len, ++ oplen)); ++ safestats.st_lenmismatch++; ++ err = EINVAL; ++ goto errout; ++ } ++#ifdef SAFE_DEBUG ++ if (debug) { ++ printf("mac: skip %d, len %d, inject %d\n", ++ maccrd->crd_skip, maccrd->crd_len, ++ maccrd->crd_inject); ++ printf("enc: skip %d, len %d, inject %d\n", ++ enccrd->crd_skip, enccrd->crd_len, ++ enccrd->crd_inject); ++ printf("bypass %d coffset %d oplen %d\n", ++ bypass, coffset, oplen); ++ } ++#endif ++ if (coffset & 3) { /* offset must be 32-bit aligned */ ++ DPRINTF(("%s: coffset %u misaligned\n", ++ __func__, coffset)); ++ safestats.st_coffmisaligned++; ++ err = EINVAL; ++ goto errout; ++ } ++ coffset >>= 2; ++ if (coffset > 255) { /* offset must be <256 dwords */ ++ DPRINTF(("%s: coffset %u too big\n", ++ __func__, coffset)); ++ safestats.st_cofftoobig++; ++ err = EINVAL; ++ goto errout; ++ } ++ /* ++ * Tell the hardware to copy the header to the output. ++ * The header is defined as the data from the end of ++ * the bypass to the start of data to be encrypted. ++ * Typically this is the inline IV. Note that you need ++ * to do this even if src+dst are the same; it appears ++ * that w/o this bit the crypted data is written ++ * immediately after the bypass data. ++ */ ++ cmd1 |= SAFE_SA_CMD1_HDRCOPY; ++ /* ++ * Disable IP header mutable bit handling. This is ++ * needed to get correct HMAC calculations. ++ */ ++ cmd1 |= SAFE_SA_CMD1_MUTABLE; ++ } else { ++ if (enccrd) { ++ bypass = enccrd->crd_skip; ++ oplen = bypass + enccrd->crd_len; ++ } else { ++ bypass = maccrd->crd_skip; ++ oplen = bypass + maccrd->crd_len; ++ } ++ coffset = 0; ++ } ++ /* XXX verify multiple of 4 when using s/g */ ++ if (bypass > 96) { /* bypass offset must be <= 96 bytes */ ++ DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); ++ safestats.st_bypasstoobig++; ++ err = EINVAL; ++ goto errout; ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (pci_map_skb(sc, &re->re_src, re->re_src_skb)) { ++ safestats.st_noload++; ++ err = ENOMEM; ++ goto errout; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (pci_map_uio(sc, &re->re_src, re->re_src_io)) { ++ safestats.st_noload++; ++ err = ENOMEM; ++ goto errout; ++ } ++ } ++ nicealign = safe_dmamap_aligned(sc, &re->re_src); ++ uniform = safe_dmamap_uniform(sc, &re->re_src); ++ ++ DPRINTF(("src nicealign %u uniform %u nsegs %u\n", ++ nicealign, uniform, re->re_src.nsegs)); ++ if (re->re_src.nsegs > 1) { ++ re->re_desc.d_src = sc->sc_spalloc.dma_paddr + ++ ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); ++ for (i = 0; i < re->re_src_nsegs; i++) { ++ /* NB: no need to check if there's space */ ++ pd = sc->sc_spfree; ++ if (++(sc->sc_spfree) == sc->sc_springtop) ++ sc->sc_spfree = sc->sc_spring; ++ ++ KASSERT((pd->pd_flags&3) == 0 || ++ (pd->pd_flags&3) == SAFE_PD_DONE, ++ ("bogus source particle descriptor; flags %x", ++ pd->pd_flags)); ++ pd->pd_addr = re->re_src_segs[i].ds_addr; ++ pd->pd_size = re->re_src_segs[i].ds_len; ++ pd->pd_flags = SAFE_PD_READY; ++ } ++ cmd0 |= SAFE_SA_CMD0_IGATHER; ++ } else { ++ /* ++ * No need for gather, reference the operand directly. ++ */ ++ re->re_desc.d_src = re->re_src_segs[0].ds_addr; ++ } ++ ++ if (enccrd == NULL && maccrd != NULL) { ++ /* ++ * Hash op; no destination needed. ++ */ ++ } else { ++ if (crp->crp_flags & (CRYPTO_F_IOV|CRYPTO_F_SKBUF)) { ++ if (!nicealign) { ++ safestats.st_iovmisaligned++; ++ err = EINVAL; ++ goto errout; ++ } ++ if (uniform != 1) { ++ device_printf(sc->sc_dev, "!uniform source\n"); ++ if (!uniform) { ++ /* ++ * There's no way to handle the DMA ++ * requirements with this uio. We ++ * could create a separate DMA area for ++ * the result and then copy it back, ++ * but for now we just bail and return ++ * an error. Note that uio requests ++ * > SAFE_MAX_DSIZE are handled because ++ * the DMA map and segment list for the ++ * destination wil result in a ++ * destination particle list that does ++ * the necessary scatter DMA. ++ */ ++ safestats.st_iovnotuniform++; ++ err = EINVAL; ++ goto errout; ++ } ++ } else ++ re->re_dst = re->re_src; ++ } else { ++ safestats.st_badflags++; ++ err = EINVAL; ++ goto errout; ++ } ++ ++ if (re->re_dst.nsegs > 1) { ++ re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + ++ ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); ++ for (i = 0; i < re->re_dst_nsegs; i++) { ++ pd = sc->sc_dpfree; ++ KASSERT((pd->pd_flags&3) == 0 || ++ (pd->pd_flags&3) == SAFE_PD_DONE, ++ ("bogus dest particle descriptor; flags %x", ++ pd->pd_flags)); ++ if (++(sc->sc_dpfree) == sc->sc_dpringtop) ++ sc->sc_dpfree = sc->sc_dpring; ++ pd->pd_addr = re->re_dst_segs[i].ds_addr; ++ pd->pd_flags = SAFE_PD_READY; ++ } ++ cmd0 |= SAFE_SA_CMD0_OSCATTER; ++ } else { ++ /* ++ * No need for scatter, reference the operand directly. ++ */ ++ re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; ++ } ++ } ++ ++ /* ++ * All done with setup; fillin the SA command words ++ * and the packet engine descriptor. The operation ++ * is now ready for submission to the hardware. ++ */ ++ sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; ++ sa->sa_cmd1 = cmd1 ++ | (coffset << SAFE_SA_CMD1_OFFSET_S) ++ | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ ++ | SAFE_SA_CMD1_SRPCI ++ ; ++ /* ++ * NB: the order of writes is important here. In case the ++ * chip is scanning the ring because of an outstanding request ++ * it might nab this one too. In that case we need to make ++ * sure the setup is complete before we write the length ++ * field of the descriptor as it signals the descriptor is ++ * ready for processing. ++ */ ++ re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; ++ if (maccrd) ++ re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; ++ wmb(); ++ re->re_desc.d_len = oplen ++ | SAFE_PE_LEN_READY ++ | (bypass << SAFE_PE_LEN_BYPASS_S) ++ ; ++ ++ safestats.st_ipackets++; ++ safestats.st_ibytes += oplen; ++ ++ if (++(sc->sc_front) == sc->sc_ringtop) ++ sc->sc_front = sc->sc_ring; ++ ++ /* XXX honor batching */ ++ safe_feed(sc, re); ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ return (0); ++ ++errout: ++ if (re->re_src.map != re->re_dst.map) ++ pci_unmap_operand(sc, &re->re_dst); ++ if (re->re_src.map) ++ pci_unmap_operand(sc, &re->re_src); ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ if (err != ERESTART) { ++ crp->crp_etype = err; ++ crypto_done(crp); ++ } else { ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ } ++ return (err); ++} ++ ++static void ++safe_callback(struct safe_softc *sc, struct safe_ringentry *re) ++{ ++ struct cryptop *crp = (struct cryptop *)re->re_crp; ++ struct cryptodesc *crd; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ safestats.st_opackets++; ++ safestats.st_obytes += re->re_dst.mapsize; ++ ++ if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { ++ device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", ++ re->re_desc.d_csr, ++ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); ++ safestats.st_peoperr++; ++ crp->crp_etype = EIO; /* something more meaningful? */ ++ } ++ ++ if (re->re_dst.map != NULL && re->re_dst.map != re->re_src.map) ++ pci_unmap_operand(sc, &re->re_dst); ++ pci_unmap_operand(sc, &re->re_src); ++ ++ /* ++ * If result was written to a differet mbuf chain, swap ++ * it in as the return value and reclaim the original. ++ */ ++ if ((crp->crp_flags & CRYPTO_F_SKBUF) && re->re_src_skb != re->re_dst_skb) { ++ device_printf(sc->sc_dev, "no CRYPTO_F_SKBUF swapping support\n"); ++ /* kfree_skb(skb) */ ++ /* crp->crp_buf = (caddr_t)re->re_dst_skb */ ++ return; ++ } ++ ++ if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { ++ /* copy out ICV result */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ if (!(crd->crd_alg == CRYPTO_MD5_HMAC || ++ crd->crd_alg == CRYPTO_SHA1_HMAC || ++ crd->crd_alg == CRYPTO_NULL_HMAC)) ++ continue; ++ if (crd->crd_alg == CRYPTO_SHA1_HMAC) { ++ /* ++ * SHA-1 ICV's are byte-swapped; fix 'em up ++ * before copy them to their destination. ++ */ ++ re->re_sastate.sa_saved_indigest[0] = ++ cpu_to_be32(re->re_sastate.sa_saved_indigest[0]); ++ re->re_sastate.sa_saved_indigest[1] = ++ cpu_to_be32(re->re_sastate.sa_saved_indigest[1]); ++ re->re_sastate.sa_saved_indigest[2] = ++ cpu_to_be32(re->re_sastate.sa_saved_indigest[2]); ++ } else { ++ re->re_sastate.sa_saved_indigest[0] = ++ cpu_to_le32(re->re_sastate.sa_saved_indigest[0]); ++ re->re_sastate.sa_saved_indigest[1] = ++ cpu_to_le32(re->re_sastate.sa_saved_indigest[1]); ++ re->re_sastate.sa_saved_indigest[2] = ++ cpu_to_le32(re->re_sastate.sa_saved_indigest[2]); ++ } ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ++ sc->sc_sessions[re->re_sesn].ses_mlen, ++ (caddr_t)re->re_sastate.sa_saved_indigest); ++ break; ++ } ++ } ++ crypto_done(crp); ++} ++ ++ ++#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) ++#define SAFE_RNG_MAXWAIT 1000 ++ ++static void ++safe_rng_init(struct safe_softc *sc) ++{ ++ u_int32_t w, v; ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ WRITE_REG(sc, SAFE_RNG_CTRL, 0); ++ /* use default value according to the manual */ ++ WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ ++ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); ++ ++ /* ++ * There is a bug in rev 1.0 of the 1140 that when the RNG ++ * is brought out of reset the ready status flag does not ++ * work until the RNG has finished its internal initialization. ++ * ++ * So in order to determine the device is through its ++ * initialization we must read the data register, using the ++ * status reg in the read in case it is initialized. Then read ++ * the data register until it changes from the first read. ++ * Once it changes read the data register until it changes ++ * again. At this time the RNG is considered initialized. ++ * This could take between 750ms - 1000ms in time. ++ */ ++ i = 0; ++ w = READ_REG(sc, SAFE_RNG_OUT); ++ do { ++ v = READ_REG(sc, SAFE_RNG_OUT); ++ if (v != w) { ++ w = v; ++ break; ++ } ++ DELAY(10); ++ } while (++i < SAFE_RNG_MAXWAIT); ++ ++ /* Wait Until data changes again */ ++ i = 0; ++ do { ++ v = READ_REG(sc, SAFE_RNG_OUT); ++ if (v != w) ++ break; ++ DELAY(10); ++ } while (++i < SAFE_RNG_MAXWAIT); ++} ++ ++static __inline void ++safe_rng_disable_short_cycle(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ WRITE_REG(sc, SAFE_RNG_CTRL, ++ READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); ++} ++ ++static __inline void ++safe_rng_enable_short_cycle(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ WRITE_REG(sc, SAFE_RNG_CTRL, ++ READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); ++} ++ ++static __inline u_int32_t ++safe_rng_read(struct safe_softc *sc) ++{ ++ int i; ++ ++ i = 0; ++ while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) ++ ; ++ return READ_REG(sc, SAFE_RNG_OUT); ++} ++ ++static int ++safe_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ struct safe_softc *sc = (struct safe_softc *) arg; ++ int i, rc; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ safestats.st_rng++; ++ /* ++ * Fetch the next block of data. ++ */ ++ if (maxwords > safe_rngbufsize) ++ maxwords = safe_rngbufsize; ++ if (maxwords > SAFE_RNG_MAXBUFSIZ) ++ maxwords = SAFE_RNG_MAXBUFSIZ; ++retry: ++ /* read as much as we can */ ++ for (rc = 0; rc < maxwords; rc++) { ++ if (READ_REG(sc, SAFE_RNG_STAT) != 0) ++ break; ++ buf[rc] = READ_REG(sc, SAFE_RNG_OUT); ++ } ++ if (rc == 0) ++ return 0; ++ /* ++ * Check the comparator alarm count and reset the h/w if ++ * it exceeds our threshold. This guards against the ++ * hardware oscillators resonating with external signals. ++ */ ++ if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { ++ u_int32_t freq_inc, w; ++ ++ DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, ++ (unsigned)READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); ++ safestats.st_rngalarm++; ++ safe_rng_enable_short_cycle(sc); ++ freq_inc = 18; ++ for (i = 0; i < 64; i++) { ++ w = READ_REG(sc, SAFE_RNG_CNFG); ++ freq_inc = ((w + freq_inc) & 0x3fL); ++ w = ((w & ~0x3fL) | freq_inc); ++ WRITE_REG(sc, SAFE_RNG_CNFG, w); ++ ++ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); ++ ++ (void) safe_rng_read(sc); ++ DELAY(25); ++ ++ if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { ++ safe_rng_disable_short_cycle(sc); ++ goto retry; ++ } ++ freq_inc = 1; ++ } ++ safe_rng_disable_short_cycle(sc); ++ } else ++ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); ++ ++ return(rc); ++} ++#endif /* defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) */ ++ ++ ++/* ++ * Resets the board. Values in the regesters are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++static void ++safe_reset_board(struct safe_softc *sc) ++{ ++ u_int32_t v; ++ /* ++ * Reset the device. The manual says no delay ++ * is needed between marking and clearing reset. ++ */ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ v = READ_REG(sc, SAFE_PE_DMACFG) &~ ++ (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | ++ SAFE_PE_DMACFG_SGRESET); ++ WRITE_REG(sc, SAFE_PE_DMACFG, v ++ | SAFE_PE_DMACFG_PERESET ++ | SAFE_PE_DMACFG_PDRRESET ++ | SAFE_PE_DMACFG_SGRESET); ++ WRITE_REG(sc, SAFE_PE_DMACFG, v); ++} ++ ++/* ++ * Initialize registers we need to touch only once. ++ */ ++static void ++safe_init_board(struct safe_softc *sc) ++{ ++ u_int32_t v, dwords; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ v = READ_REG(sc, SAFE_PE_DMACFG); ++ v &=~ ( SAFE_PE_DMACFG_PEMODE ++ | SAFE_PE_DMACFG_FSENA /* failsafe enable */ ++ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ ++ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ ++ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ ++ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ ++ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ ++ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ ++ ); ++ v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ ++ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ ++ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ ++ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ ++ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ ++ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ ++#if 0 ++ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ ++#endif ++ ; ++ WRITE_REG(sc, SAFE_PE_DMACFG, v); ++ ++#ifdef __BIG_ENDIAN ++ /* tell the safenet that we are 4321 and not 1234 */ ++ WRITE_REG(sc, SAFE_ENDIAN, 0xe4e41b1b); ++#endif ++ ++ if (sc->sc_chiprev == SAFE_REV(1,0)) { ++ /* ++ * Avoid large PCI DMA transfers. Rev 1.0 has a bug where ++ * "target mode transfers" done while the chip is DMA'ing ++ * >1020 bytes cause the hardware to lockup. To avoid this ++ * we reduce the max PCI transfer size and use small source ++ * particle descriptors (<= 256 bytes). ++ */ ++ WRITE_REG(sc, SAFE_DMA_CFG, 256); ++ device_printf(sc->sc_dev, ++ "Reduce max DMA size to %u words for rev %u.%u WAR\n", ++ (unsigned) ((READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff), ++ (unsigned) SAFE_REV_MAJ(sc->sc_chiprev), ++ (unsigned) SAFE_REV_MIN(sc->sc_chiprev)); ++ sc->sc_max_dsize = 256; ++ } else { ++ sc->sc_max_dsize = SAFE_MAX_DSIZE; ++ } ++ ++ /* NB: operands+results are overlaid */ ++ WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); ++ WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); ++ /* ++ * Configure ring entry size and number of items in the ring. ++ */ ++ KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, ++ ("PE ring entry not 32-bit aligned!")); ++ dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); ++ WRITE_REG(sc, SAFE_PE_RINGCFG, ++ (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); ++ WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ ++ ++ WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); ++ WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); ++ WRITE_REG(sc, SAFE_PE_PARTSIZE, ++ (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); ++ /* ++ * NB: destination particles are fixed size. We use ++ * an mbuf cluster and require all results go to ++ * clusters or smaller. ++ */ ++ WRITE_REG(sc, SAFE_PE_PARTCFG, sc->sc_max_dsize); ++ ++ /* it's now safe to enable PE mode, do it */ ++ WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); ++ ++ /* ++ * Configure hardware to use level-triggered interrupts and ++ * to interrupt after each descriptor is processed. ++ */ ++ WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); ++ WRITE_REG(sc, SAFE_HI_CLR, 0xffffffff); ++ WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); ++ WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); ++} ++ ++ ++/* ++ * Clean up after a chip crash. ++ * It is assumed that the caller in splimp() ++ */ ++static void ++safe_cleanchip(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sc->sc_nqchip != 0) { ++ struct safe_ringentry *re = sc->sc_back; ++ ++ while (re != sc->sc_front) { ++ if (re->re_desc.d_csr != 0) ++ safe_free_entry(sc, re); ++ if (++re == sc->sc_ringtop) ++ re = sc->sc_ring; ++ } ++ sc->sc_back = re; ++ sc->sc_nqchip = 0; ++ } ++} ++ ++/* ++ * free a safe_q ++ * It is assumed that the caller is within splimp(). ++ */ ++static int ++safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) ++{ ++ struct cryptop *crp; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ /* ++ * Free header MCR ++ */ ++ if ((re->re_dst_skb != NULL) && (re->re_src_skb != re->re_dst_skb)) ++#ifdef NOTYET ++ m_freem(re->re_dst_m); ++#else ++ printk("%s,%d: SKB not supported\n", __FILE__, __LINE__); ++#endif ++ ++ crp = (struct cryptop *)re->re_crp; ++ ++ re->re_desc.d_csr = 0; ++ ++ crp->crp_etype = EFAULT; ++ crypto_done(crp); ++ return(0); ++} ++ ++/* ++ * Routine to reset the chip and clean up. ++ * It is assumed that the caller is in splimp() ++ */ ++static void ++safe_totalreset(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ safe_reset_board(sc); ++ safe_init_board(sc); ++ safe_cleanchip(sc); ++} ++ ++/* ++ * Is the operand suitable aligned for direct DMA. Each ++ * segment must be aligned on a 32-bit boundary and all ++ * but the last segment must be a multiple of 4 bytes. ++ */ ++static int ++safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op) ++{ ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ for (i = 0; i < op->nsegs; i++) { ++ if (op->segs[i].ds_addr & 3) ++ return (0); ++ if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) ++ return (0); ++ } ++ return (1); ++} ++ ++/* ++ * Is the operand suitable for direct DMA as the destination ++ * of an operation. The hardware requires that each ``particle'' ++ * but the last in an operation result have the same size. We ++ * fix that size at SAFE_MAX_DSIZE bytes. This routine returns ++ * 0 if some segment is not a multiple of of this size, 1 if all ++ * segments are exactly this size, or 2 if segments are at worst ++ * a multple of this size. ++ */ ++static int ++safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op) ++{ ++ int result = 1; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (op->nsegs > 0) { ++ int i; ++ ++ for (i = 0; i < op->nsegs-1; i++) { ++ if (op->segs[i].ds_len % sc->sc_max_dsize) ++ return (0); ++ if (op->segs[i].ds_len != sc->sc_max_dsize) ++ result = 2; ++ } ++ } ++ return (result); ++} ++ ++static int ++safe_kprocess(device_t dev, struct cryptkop *krp, int hint) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ struct safe_pkq *q; ++ unsigned long flags; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sc == NULL) { ++ krp->krp_status = EINVAL; ++ goto err; ++ } ++ ++ if (krp->krp_op != CRK_MOD_EXP) { ++ krp->krp_status = EOPNOTSUPP; ++ goto err; ++ } ++ ++ q = (struct safe_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); ++ if (q == NULL) { ++ krp->krp_status = ENOMEM; ++ goto err; ++ } ++ memset(q, 0, sizeof(*q)); ++ q->pkq_krp = krp; ++ INIT_LIST_HEAD(&q->pkq_list); ++ ++ spin_lock_irqsave(&sc->sc_pkmtx, flags); ++ list_add_tail(&q->pkq_list, &sc->sc_pkq); ++ safe_kfeed(sc); ++ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); ++ return (0); ++ ++err: ++ crypto_kdone(krp); ++ return (0); ++} ++ ++#define SAFE_CRK_PARAM_BASE 0 ++#define SAFE_CRK_PARAM_EXP 1 ++#define SAFE_CRK_PARAM_MOD 2 ++ ++static int ++safe_kstart(struct safe_softc *sc) ++{ ++ struct cryptkop *krp = sc->sc_pkq_cur->pkq_krp; ++ int exp_bits, mod_bits, base_bits; ++ u_int32_t op, a_off, b_off, c_off, d_off; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (krp->krp_iparams < 3 || krp->krp_oparams != 1) { ++ krp->krp_status = EINVAL; ++ return (1); ++ } ++ ++ base_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_BASE]); ++ if (base_bits > 2048) ++ goto too_big; ++ if (base_bits <= 0) /* 5. base not zero */ ++ goto too_small; ++ ++ exp_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_EXP]); ++ if (exp_bits > 2048) ++ goto too_big; ++ if (exp_bits <= 0) /* 1. exponent word length > 0 */ ++ goto too_small; /* 4. exponent not zero */ ++ ++ mod_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_MOD]); ++ if (mod_bits > 2048) ++ goto too_big; ++ if (mod_bits <= 32) /* 2. modulus word length > 1 */ ++ goto too_small; /* 8. MSW of modulus != zero */ ++ if (mod_bits < exp_bits) /* 3 modulus len >= exponent len */ ++ goto too_small; ++ if ((krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p[0] & 1) == 0) ++ goto bad_domain; /* 6. modulus is odd */ ++ if (mod_bits > krp->krp_param[krp->krp_iparams].crp_nbits) ++ goto too_small; /* make sure result will fit */ ++ ++ /* 7. modulus > base */ ++ if (mod_bits < base_bits) ++ goto too_small; ++ if (mod_bits == base_bits) { ++ u_int8_t *basep, *modp; ++ int i; ++ ++ basep = krp->krp_param[SAFE_CRK_PARAM_BASE].crp_p + ++ ((base_bits + 7) / 8) - 1; ++ modp = krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p + ++ ((mod_bits + 7) / 8) - 1; ++ ++ for (i = 0; i < (mod_bits + 7) / 8; i++, basep--, modp--) { ++ if (*modp < *basep) ++ goto too_small; ++ if (*modp > *basep) ++ break; ++ } ++ } ++ ++ /* And on the 9th step, he rested. */ ++ ++ WRITE_REG(sc, SAFE_PK_A_LEN, (exp_bits + 31) / 32); ++ WRITE_REG(sc, SAFE_PK_B_LEN, (mod_bits + 31) / 32); ++ if (mod_bits > 1024) { ++ op = SAFE_PK_FUNC_EXP4; ++ a_off = 0x000; ++ b_off = 0x100; ++ c_off = 0x200; ++ d_off = 0x300; ++ } else { ++ op = SAFE_PK_FUNC_EXP16; ++ a_off = 0x000; ++ b_off = 0x080; ++ c_off = 0x100; ++ d_off = 0x180; ++ } ++ sc->sc_pk_reslen = b_off - a_off; ++ sc->sc_pk_resoff = d_off; ++ ++ /* A is exponent, B is modulus, C is base, D is result */ ++ safe_kload_reg(sc, a_off, b_off - a_off, ++ &krp->krp_param[SAFE_CRK_PARAM_EXP]); ++ WRITE_REG(sc, SAFE_PK_A_ADDR, a_off >> 2); ++ safe_kload_reg(sc, b_off, b_off - a_off, ++ &krp->krp_param[SAFE_CRK_PARAM_MOD]); ++ WRITE_REG(sc, SAFE_PK_B_ADDR, b_off >> 2); ++ safe_kload_reg(sc, c_off, b_off - a_off, ++ &krp->krp_param[SAFE_CRK_PARAM_BASE]); ++ WRITE_REG(sc, SAFE_PK_C_ADDR, c_off >> 2); ++ WRITE_REG(sc, SAFE_PK_D_ADDR, d_off >> 2); ++ ++ WRITE_REG(sc, SAFE_PK_FUNC, op | SAFE_PK_FUNC_RUN); ++ ++ return (0); ++ ++too_big: ++ krp->krp_status = E2BIG; ++ return (1); ++too_small: ++ krp->krp_status = ERANGE; ++ return (1); ++bad_domain: ++ krp->krp_status = EDOM; ++ return (1); ++} ++ ++static int ++safe_ksigbits(struct safe_softc *sc, struct crparam *cr) ++{ ++ u_int plen = (cr->crp_nbits + 7) / 8; ++ int i, sig = plen * 8; ++ u_int8_t c, *p = cr->crp_p; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ for (i = plen - 1; i >= 0; i--) { ++ c = p[i]; ++ if (c != 0) { ++ while ((c & 0x80) == 0) { ++ sig--; ++ c <<= 1; ++ } ++ break; ++ } ++ sig -= 8; ++ } ++ return (sig); ++} ++ ++static void ++safe_kfeed(struct safe_softc *sc) ++{ ++ struct safe_pkq *q, *tmp; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (list_empty(&sc->sc_pkq) && sc->sc_pkq_cur == NULL) ++ return; ++ if (sc->sc_pkq_cur != NULL) ++ return; ++ list_for_each_entry_safe(q, tmp, &sc->sc_pkq, pkq_list) { ++ sc->sc_pkq_cur = q; ++ list_del(&q->pkq_list); ++ if (safe_kstart(sc) != 0) { ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ sc->sc_pkq_cur = NULL; ++ } else { ++ /* op started, start polling */ ++ mod_timer(&sc->sc_pkto, jiffies + 1); ++ break; ++ } ++ } ++} ++ ++static void ++safe_kpoll(unsigned long arg) ++{ ++ struct safe_softc *sc = NULL; ++ struct safe_pkq *q; ++ struct crparam *res; ++ int i; ++ u_int32_t buf[64]; ++ unsigned long flags; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (arg >= SAFE_MAX_CHIPS) ++ return; ++ sc = safe_chip_idx[arg]; ++ if (!sc) { ++ DPRINTF(("%s() - bad callback\n", __FUNCTION__)); ++ return; ++ } ++ ++ spin_lock_irqsave(&sc->sc_pkmtx, flags); ++ if (sc->sc_pkq_cur == NULL) ++ goto out; ++ if (READ_REG(sc, SAFE_PK_FUNC) & SAFE_PK_FUNC_RUN) { ++ /* still running, check back later */ ++ mod_timer(&sc->sc_pkto, jiffies + 1); ++ goto out; ++ } ++ ++ q = sc->sc_pkq_cur; ++ res = &q->pkq_krp->krp_param[q->pkq_krp->krp_iparams]; ++ bzero(buf, sizeof(buf)); ++ bzero(res->crp_p, (res->crp_nbits + 7) / 8); ++ for (i = 0; i < sc->sc_pk_reslen >> 2; i++) ++ buf[i] = le32_to_cpu(READ_REG(sc, SAFE_PK_RAM_START + ++ sc->sc_pk_resoff + (i << 2))); ++ bcopy(buf, res->crp_p, (res->crp_nbits + 7) / 8); ++ /* ++ * reduce the bits that need copying if possible ++ */ ++ res->crp_nbits = min(res->crp_nbits,sc->sc_pk_reslen * 8); ++ res->crp_nbits = safe_ksigbits(sc, res); ++ ++ for (i = SAFE_PK_RAM_START; i < SAFE_PK_RAM_END; i += 4) ++ WRITE_REG(sc, i, 0); ++ ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ sc->sc_pkq_cur = NULL; ++ ++ safe_kfeed(sc); ++out: ++ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); ++} ++ ++static void ++safe_kload_reg(struct safe_softc *sc, u_int32_t off, u_int32_t len, ++ struct crparam *n) ++{ ++ u_int32_t buf[64], i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ bzero(buf, sizeof(buf)); ++ bcopy(n->crp_p, buf, (n->crp_nbits + 7) / 8); ++ ++ for (i = 0; i < len >> 2; i++) ++ WRITE_REG(sc, SAFE_PK_RAM_START + off + (i << 2), ++ cpu_to_le32(buf[i])); ++} ++ ++#ifdef SAFE_DEBUG ++static void ++safe_dump_dmastatus(struct safe_softc *sc, const char *tag) ++{ ++ printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" ++ , tag ++ , READ_REG(sc, SAFE_DMA_ENDIAN) ++ , READ_REG(sc, SAFE_DMA_SRCADDR) ++ , READ_REG(sc, SAFE_DMA_DSTADDR) ++ , READ_REG(sc, SAFE_DMA_STAT) ++ ); ++} ++ ++static void ++safe_dump_intrstate(struct safe_softc *sc, const char *tag) ++{ ++ printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" ++ , tag ++ , READ_REG(sc, SAFE_HI_CFG) ++ , READ_REG(sc, SAFE_HI_MASK) ++ , READ_REG(sc, SAFE_HI_DESC_CNT) ++ , READ_REG(sc, SAFE_HU_STAT) ++ , READ_REG(sc, SAFE_HM_STAT) ++ ); ++} ++ ++static void ++safe_dump_ringstate(struct safe_softc *sc, const char *tag) ++{ ++ u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); ++ ++ /* NB: assume caller has lock on ring */ ++ printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", ++ tag, ++ estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), ++ (unsigned long)(sc->sc_back - sc->sc_ring), ++ (unsigned long)(sc->sc_front - sc->sc_ring)); ++} ++ ++static void ++safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) ++{ ++ int ix, nsegs; ++ ++ ix = re - sc->sc_ring; ++ printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" ++ , tag ++ , re, ix ++ , re->re_desc.d_csr ++ , re->re_desc.d_src ++ , re->re_desc.d_dst ++ , re->re_desc.d_sa ++ , re->re_desc.d_len ++ ); ++ if (re->re_src.nsegs > 1) { ++ ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / ++ sizeof(struct safe_pdesc); ++ for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { ++ printf(" spd[%u] %p: %p size %u flags %x" ++ , ix, &sc->sc_spring[ix] ++ , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr ++ , sc->sc_spring[ix].pd_size ++ , sc->sc_spring[ix].pd_flags ++ ); ++ if (sc->sc_spring[ix].pd_size == 0) ++ printf(" (zero!)"); ++ printf("\n"); ++ if (++ix == SAFE_TOTAL_SPART) ++ ix = 0; ++ } ++ } ++ if (re->re_dst.nsegs > 1) { ++ ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / ++ sizeof(struct safe_pdesc); ++ for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { ++ printf(" dpd[%u] %p: %p flags %x\n" ++ , ix, &sc->sc_dpring[ix] ++ , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr ++ , sc->sc_dpring[ix].pd_flags ++ ); ++ if (++ix == SAFE_TOTAL_DPART) ++ ix = 0; ++ } ++ } ++ printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", ++ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); ++ printf("sa: key %x %x %x %x %x %x %x %x\n" ++ , re->re_sa.sa_key[0] ++ , re->re_sa.sa_key[1] ++ , re->re_sa.sa_key[2] ++ , re->re_sa.sa_key[3] ++ , re->re_sa.sa_key[4] ++ , re->re_sa.sa_key[5] ++ , re->re_sa.sa_key[6] ++ , re->re_sa.sa_key[7] ++ ); ++ printf("sa: indigest %x %x %x %x %x\n" ++ , re->re_sa.sa_indigest[0] ++ , re->re_sa.sa_indigest[1] ++ , re->re_sa.sa_indigest[2] ++ , re->re_sa.sa_indigest[3] ++ , re->re_sa.sa_indigest[4] ++ ); ++ printf("sa: outdigest %x %x %x %x %x\n" ++ , re->re_sa.sa_outdigest[0] ++ , re->re_sa.sa_outdigest[1] ++ , re->re_sa.sa_outdigest[2] ++ , re->re_sa.sa_outdigest[3] ++ , re->re_sa.sa_outdigest[4] ++ ); ++ printf("sr: iv %x %x %x %x\n" ++ , re->re_sastate.sa_saved_iv[0] ++ , re->re_sastate.sa_saved_iv[1] ++ , re->re_sastate.sa_saved_iv[2] ++ , re->re_sastate.sa_saved_iv[3] ++ ); ++ printf("sr: hashbc %u indigest %x %x %x %x %x\n" ++ , re->re_sastate.sa_saved_hashbc ++ , re->re_sastate.sa_saved_indigest[0] ++ , re->re_sastate.sa_saved_indigest[1] ++ , re->re_sastate.sa_saved_indigest[2] ++ , re->re_sastate.sa_saved_indigest[3] ++ , re->re_sastate.sa_saved_indigest[4] ++ ); ++} ++ ++static void ++safe_dump_ring(struct safe_softc *sc, const char *tag) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ printf("\nSafeNet Ring State:\n"); ++ safe_dump_intrstate(sc, tag); ++ safe_dump_dmastatus(sc, tag); ++ safe_dump_ringstate(sc, tag); ++ if (sc->sc_nqchip) { ++ struct safe_ringentry *re = sc->sc_back; ++ do { ++ safe_dump_request(sc, tag, re); ++ if (++re == sc->sc_ringtop) ++ re = sc->sc_ring; ++ } while (re != sc->sc_front); ++ } ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++} ++#endif /* SAFE_DEBUG */ ++ ++ ++static int safe_probe(struct pci_dev *dev, const struct pci_device_id *ent) ++{ ++ struct safe_softc *sc = NULL; ++ u32 mem_start, mem_len, cmd; ++ int i, rc, devinfo; ++ dma_addr_t raddr; ++ static int num_chips = 0; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (pci_enable_device(dev) < 0) ++ return(-ENODEV); ++ ++ if (!dev->irq) { ++ printk("safe: found device with no IRQ assigned. check BIOS settings!"); ++ pci_disable_device(dev); ++ return(-ENODEV); ++ } ++ ++ if (pci_set_mwi(dev)) { ++ printk("safe: pci_set_mwi failed!"); ++ return(-ENODEV); ++ } ++ ++ sc = (struct safe_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, "safe", num_chips, safe_methods); ++ ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++ sc->sc_pcidev = dev; ++ if (num_chips < SAFE_MAX_CHIPS) { ++ safe_chip_idx[device_get_unit(sc->sc_dev)] = sc; ++ num_chips++; ++ } ++ ++ INIT_LIST_HEAD(&sc->sc_pkq); ++ spin_lock_init(&sc->sc_pkmtx); ++ ++ pci_set_drvdata(sc->sc_pcidev, sc); ++ ++ /* we read its hardware registers as memory */ ++ mem_start = pci_resource_start(sc->sc_pcidev, 0); ++ mem_len = pci_resource_len(sc->sc_pcidev, 0); ++ ++ sc->sc_base_addr = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_base_addr) { ++ device_printf(sc->sc_dev, "failed to ioremap 0x%x-0x%x\n", ++ mem_start, mem_start + mem_len - 1); ++ goto out; ++ } ++ ++ /* fix up the bus size */ ++ if (pci_set_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); ++ goto out; ++ } ++ if (pci_set_consistent_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, "No usable consistent DMA configuration, aborting.\n"); ++ goto out; ++ } ++ ++ pci_set_master(sc->sc_pcidev); ++ ++ pci_read_config_dword(sc->sc_pcidev, PCI_COMMAND, &cmd); ++ ++ if (!(cmd & PCI_COMMAND_MEMORY)) { ++ device_printf(sc->sc_dev, "failed to enable memory mapping\n"); ++ goto out; ++ } ++ ++ if (!(cmd & PCI_COMMAND_MASTER)) { ++ device_printf(sc->sc_dev, "failed to enable bus mastering\n"); ++ goto out; ++ } ++ ++ rc = request_irq(dev->irq, safe_intr, IRQF_SHARED, "safe", sc); ++ if (rc) { ++ device_printf(sc->sc_dev, "failed to hook irq %d\n", sc->sc_irq); ++ goto out; ++ } ++ sc->sc_irq = dev->irq; ++ ++ sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & ++ (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); ++ ++ /* ++ * Allocate packet engine descriptors. ++ */ ++ sc->sc_ringalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, ++ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), ++ &sc->sc_ringalloc.dma_paddr); ++ if (!sc->sc_ringalloc.dma_vaddr) { ++ device_printf(sc->sc_dev, "cannot allocate PE descriptor ring\n"); ++ goto out; ++ } ++ ++ /* ++ * Hookup the static portion of all our data structures. ++ */ ++ sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; ++ sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; ++ sc->sc_front = sc->sc_ring; ++ sc->sc_back = sc->sc_ring; ++ raddr = sc->sc_ringalloc.dma_paddr; ++ bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); ++ for (i = 0; i < SAFE_MAX_NQUEUE; i++) { ++ struct safe_ringentry *re = &sc->sc_ring[i]; ++ ++ re->re_desc.d_sa = raddr + ++ offsetof(struct safe_ringentry, re_sa); ++ re->re_sa.sa_staterec = raddr + ++ offsetof(struct safe_ringentry, re_sastate); ++ ++ raddr += sizeof (struct safe_ringentry); ++ } ++ spin_lock_init(&sc->sc_ringmtx); ++ ++ /* ++ * Allocate scatter and gather particle descriptors. ++ */ ++ sc->sc_spalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), ++ &sc->sc_spalloc.dma_paddr); ++ if (!sc->sc_spalloc.dma_vaddr) { ++ device_printf(sc->sc_dev, "cannot allocate source particle descriptor ring\n"); ++ goto out; ++ } ++ sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; ++ sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; ++ sc->sc_spfree = sc->sc_spring; ++ bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); ++ ++ sc->sc_dpalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ &sc->sc_dpalloc.dma_paddr); ++ if (!sc->sc_dpalloc.dma_vaddr) { ++ device_printf(sc->sc_dev, "cannot allocate destination particle descriptor ring\n"); ++ goto out; ++ } ++ sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; ++ sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; ++ sc->sc_dpfree = sc->sc_dpring; ++ bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ goto out; ++ } ++ ++ printf("%s:", device_get_nameunit(sc->sc_dev)); ++ ++ devinfo = READ_REG(sc, SAFE_DEVINFO); ++ if (devinfo & SAFE_DEVINFO_RNG) { ++ sc->sc_flags |= SAFE_FLAGS_RNG; ++ printf(" rng"); ++ } ++ if (devinfo & SAFE_DEVINFO_PKEY) { ++ printf(" key"); ++ sc->sc_flags |= SAFE_FLAGS_KEY; ++ crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); ++#if 0 ++ crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); ++#endif ++ init_timer(&sc->sc_pkto); ++ sc->sc_pkto.function = safe_kpoll; ++ sc->sc_pkto.data = (unsigned long) device_get_unit(sc->sc_dev); ++ } ++ if (devinfo & SAFE_DEVINFO_DES) { ++ printf(" des/3des"); ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ } ++ if (devinfo & SAFE_DEVINFO_AES) { ++ printf(" aes"); ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ } ++ if (devinfo & SAFE_DEVINFO_MD5) { ++ printf(" md5"); ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ } ++ if (devinfo & SAFE_DEVINFO_SHA1) { ++ printf(" sha1"); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ } ++ printf(" null"); ++ crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); ++ /* XXX other supported algorithms */ ++ printf("\n"); ++ ++ safe_reset_board(sc); /* reset h/w */ ++ safe_init_board(sc); /* init h/w */ ++ ++#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) ++ if (sc->sc_flags & SAFE_FLAGS_RNG) { ++ safe_rng_init(sc); ++ crypto_rregister(sc->sc_cid, safe_read_random, sc); ++ } ++#endif /* SAFE_NO_RNG */ ++ ++ return (0); ++ ++out: ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_ringalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), ++ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); ++ if (sc->sc_spalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); ++ if (sc->sc_dpalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); ++ kfree(sc); ++ return(-ENODEV); ++} ++ ++static void safe_remove(struct pci_dev *dev) ++{ ++ struct safe_softc *sc = pci_get_drvdata(dev); ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ /* XXX wait/abort active ops */ ++ ++ WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ ++ ++ del_timer_sync(&sc->sc_pkto); ++ ++ crypto_unregister_all(sc->sc_cid); ++ ++ safe_cleanchip(sc); ++ ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_ringalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), ++ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); ++ if (sc->sc_spalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); ++ if (sc->sc_dpalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); ++ sc->sc_irq = -1; ++ sc->sc_ringalloc.dma_vaddr = NULL; ++ sc->sc_spalloc.dma_vaddr = NULL; ++ sc->sc_dpalloc.dma_vaddr = NULL; ++} ++ ++static struct pci_device_id safe_pci_tbl[] = { ++ { PCI_VENDOR_SAFENET, PCI_PRODUCT_SAFEXCEL, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(pci, safe_pci_tbl); ++ ++static struct pci_driver safe_driver = { ++ .name = "safe", ++ .id_table = safe_pci_tbl, ++ .probe = safe_probe, ++ .remove = safe_remove, ++ /* add PM stuff here one day */ ++}; ++ ++static int __init safe_init (void) ++{ ++ struct safe_softc *sc = NULL; ++ int rc; ++ ++ DPRINTF(("%s(%p)\n", __FUNCTION__, safe_init)); ++ ++ rc = pci_register_driver(&safe_driver); ++ pci_register_driver_compat(&safe_driver, rc); ++ ++ return rc; ++} ++ ++static void __exit safe_exit (void) ++{ ++ pci_unregister_driver(&safe_driver); ++} ++ ++module_init(safe_init); ++module_exit(safe_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("OCF driver for safenet PCI crypto devices"); +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/safereg.h linux-3.0.4/crypto/ocf/safe/safereg.h +--- linux-3.0.4.orig/crypto/ocf/safe/safereg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/safereg.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,421 @@ ++/*- ++ * Copyright (c) 2003 Sam Leffler, Errno Consulting ++ * Copyright (c) 2003 Global Technology Associates, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++ * $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $ ++ */ ++#ifndef _SAFE_SAFEREG_H_ ++#define _SAFE_SAFEREG_H_ ++ ++/* ++ * Register definitions for SafeNet SafeXcel-1141 crypto device. ++ * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual. ++ */ ++ ++#define BS_BAR 0x10 /* DMA base address register */ ++#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ ++#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ ++ ++#define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */ ++ ++/* SafeNet */ ++#define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */ ++ ++#define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */ ++#define SAFE_PE_SRC 0x0004 /* Packet Engine Source */ ++#define SAFE_PE_DST 0x0008 /* Packet Engine Destination */ ++#define SAFE_PE_SA 0x000c /* Packet Engine SA */ ++#define SAFE_PE_LEN 0x0010 /* Packet Engine Length */ ++#define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */ ++#define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */ ++#define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */ ++#define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */ ++#define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */ ++#define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */ ++#define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */ ++#define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */ ++#define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */ ++#define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */ ++#define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */ ++#define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */ ++#define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */ ++#define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */ ++#define SAFE_DEVID 0x0084 /* Device ID */ ++#define SAFE_DEVINFO 0x0088 /* Device Info */ ++#define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */ ++#define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */ ++#define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */ ++#define SAFE_HI_MASK 0x00a8 /* Host Mask Control */ ++#define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */ ++#define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */ ++#define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */ ++#define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */ ++#define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */ ++#define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */ ++#define SAFE_DMA_STAT 0x00cc /* DMA Current Status */ ++#define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */ ++#define SAFE_ENDIAN 0x00e0 /* Endian Configuration */ ++#define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */ ++#define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */ ++#define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */ ++#define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */ ++#define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */ ++#define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */ ++#define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */ ++#define SAFE_PK_FUNC 0x081c /* Public Key Function */ ++#define SAFE_PK_RAM_START 0x1000 /* Public Key RAM start address */ ++#define SAFE_PK_RAM_END 0x1fff /* Public Key RAM end address */ ++ ++#define SAFE_RNG_OUT 0x0100 /* RNG Output */ ++#define SAFE_RNG_STAT 0x0104 /* RNG Status */ ++#define SAFE_RNG_CTRL 0x0108 /* RNG Control */ ++#define SAFE_RNG_A 0x010c /* RNG A */ ++#define SAFE_RNG_B 0x0110 /* RNG B */ ++#define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */ ++#define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */ ++#define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */ ++#define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */ ++#define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */ ++#define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */ ++#define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */ ++#define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */ ++#define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */ ++#define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */ ++ ++#define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */ ++#define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */ ++#define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */ ++#define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */ ++#define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */ ++#define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */ ++#define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */ ++#define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */ ++#define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */ ++#define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */ ++#define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */ ++#define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */ ++#define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */ ++#define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */ ++#define SAFE_PE_CSR_XECODE_S 20 ++#define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */ ++#define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */ ++#define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */ ++#define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */ ++#define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */ ++#define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */ ++#define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */ ++#define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */ ++#define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */ ++#define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */ ++#define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */ ++#define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */ ++#define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */ ++#define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */ ++#define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */ ++ ++/* ++ * Check the CSR to see if the PE has returned ownership to ++ * the host. Note that before processing a descriptor this ++ * must be done followed by a check of the SAFE_PE_LEN register ++ * status bits to avoid premature processing of a descriptor ++ * on its way back to the host. ++ */ ++#define SAFE_PE_CSR_IS_DONE(_csr) \ ++ (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE) ++ ++#define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */ ++#define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */ ++#define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */ ++#define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */ ++#define SAFE_PE_LEN_BYPASS_S 24 ++ ++#define SAFE_PE_LEN_IS_DONE(_len) \ ++ (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE) ++ ++/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */ ++#define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */ ++#define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */ ++#define SAFE_INT_PE_ERROR 0x00000010 /* PE error */ ++#define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */ ++ ++#define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */ ++#define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */ ++#define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */ ++ ++#define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */ ++#define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */ ++ ++#define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */ ++#define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */ ++#define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */ ++#define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */ ++#define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */ ++#define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */ ++#define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */ ++#define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */ ++#define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */ ++#define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */ ++#define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */ ++#define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */ ++#define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */ ++#define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */ ++#define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */ ++#define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */ ++#define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */ ++ ++#define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */ ++#define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */ ++#define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */ ++#define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */ ++#define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */ ++#define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */ ++#define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */ ++#define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */ ++#define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */ ++#define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */ ++#define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */ ++#define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */ ++#define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */ ++#define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */ ++ ++#define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */ ++#define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */ ++#define SAFE_PE_RINGCFG_OFFSET_S 16 ++ ++#define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */ ++#define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */ ++#define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */ ++ ++#define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */ ++ ++#define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */ ++#define SAFE_PE_ERNGSTAT_NEXT_S 16 ++ ++#define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */ ++#define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */ ++ ++#define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */ ++#define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */ ++#define SAFE_PE_PARTCFG_GBURST_2 0x00000000 ++#define SAFE_PE_PARTCFG_GBURST_4 0x00010000 ++#define SAFE_PE_PARTCFG_GBURST_8 0x00020000 ++#define SAFE_PE_PARTCFG_GBURST_16 0x00030000 ++#define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */ ++#define SAFE_PE_PARTCFG_SBURST_2 0x00000000 ++#define SAFE_PE_PARTCFG_SBURST_4 0x00040000 ++#define SAFE_PE_PARTCFG_SBURST_8 0x00080000 ++#define SAFE_PE_PARTCFG_SBURST_16 0x000c0000 ++ ++#define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */ ++#define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */ ++ ++#define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */ ++#define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */ ++#define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */ ++ ++#define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */ ++#define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */ ++#define SAFE_DEVINFO_REV_MAJ_S 4 ++#define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */ ++#define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */ ++#define SAFE_DEVINFO_AES 0x00000400 /* AES support present */ ++#define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */ ++#define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */ ++#define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */ ++#define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */ ++#define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */ ++#define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */ ++#define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */ ++#define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */ ++ ++#define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min)) ++#define SAFE_REV_MAJ(_chiprev) \ ++ (((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S) ++#define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN) ++ ++#define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */ ++#define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */ ++#define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */ ++#define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */ ++#define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */ ++#define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */ ++#define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */ ++#define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */ ++#define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */ ++#define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */ ++#define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */ ++#define SAFE_PK_FUNC_RUN 0x00008000 /* start/status */ ++ ++#define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */ ++ ++#define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */ ++#define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */ ++#define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */ ++#define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */ ++#define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */ ++#define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */ ++#define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */ ++#define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */ ++#define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */ ++#define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */ ++ ++/* ++ * Packet engine descriptor. Note that d_csr is a copy of the ++ * SAFE_PE_CSR register and all definitions apply, and d_len ++ * is a copy of the SAFE_PE_LEN register and all definitions apply. ++ * d_src and d_len may point directly to contiguous data or to a ++ * list of ``particle descriptors'' when using scatter/gather i/o. ++ */ ++struct safe_desc { ++ u_int32_t d_csr; /* per-packet control/status */ ++ u_int32_t d_src; /* source address */ ++ u_int32_t d_dst; /* destination address */ ++ u_int32_t d_sa; /* SA address */ ++ u_int32_t d_len; /* length, bypass, status */ ++}; ++ ++/* ++ * Scatter/Gather particle descriptor. ++ * ++ * NB: scatter descriptors do not specify a size; this is fixed ++ * by the setting of the SAFE_PE_PARTCFG register. ++ */ ++struct safe_pdesc { ++ u_int32_t pd_addr; /* particle address */ ++#ifdef __BIG_ENDIAN ++ u_int16_t pd_flags; /* control word */ ++ u_int16_t pd_size; /* particle size (bytes) */ ++#else ++ u_int16_t pd_flags; /* control word */ ++ u_int16_t pd_size; /* particle size (bytes) */ ++#endif ++}; ++ ++#define SAFE_PD_READY 0x0001 /* ready for processing */ ++#define SAFE_PD_DONE 0x0002 /* h/w completed processing */ ++ ++/* ++ * Security Association (SA) Record (Rev 1). One of these is ++ * required for each operation processed by the packet engine. ++ */ ++struct safe_sarec { ++ u_int32_t sa_cmd0; ++ u_int32_t sa_cmd1; ++ u_int32_t sa_resv0; ++ u_int32_t sa_resv1; ++ u_int32_t sa_key[8]; /* DES/3DES/AES key */ ++ u_int32_t sa_indigest[5]; /* inner digest */ ++ u_int32_t sa_outdigest[5]; /* outer digest */ ++ u_int32_t sa_spi; /* SPI */ ++ u_int32_t sa_seqnum; /* sequence number */ ++ u_int32_t sa_seqmask[2]; /* sequence number mask */ ++ u_int32_t sa_resv2; ++ u_int32_t sa_staterec; /* address of state record */ ++ u_int32_t sa_resv3[2]; ++ u_int32_t sa_samgmt0; /* SA management field 0 */ ++ u_int32_t sa_samgmt1; /* SA management field 0 */ ++}; ++ ++#define SAFE_SA_CMD0_OP 0x00000007 /* operation code */ ++#define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */ ++#define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */ ++#define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */ ++#define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */ ++#define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */ ++#define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */ ++#define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */ ++#define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */ ++#define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */ ++#define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */ ++#define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */ ++#define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */ ++#define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */ ++#define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */ ++#define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */ ++#define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */ ++#define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */ ++#define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */ ++#define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */ ++#define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */ ++#define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */ ++#define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */ ++#define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */ ++#define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */ ++#define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */ ++#define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */ ++#define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */ ++#define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */ ++#define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */ ++#define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */ ++#define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */ ++#define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */ ++#define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */ ++#define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */ ++#define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */ ++#define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */ ++#define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */ ++#define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */ ++#define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */ ++#define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */ ++#define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */ ++#define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */ ++ ++#define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */ ++#define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */ ++#define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */ ++#define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */ ++#define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */ ++#define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */ ++#define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */ ++#define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */ ++#define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */ ++#define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */ ++#define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */ ++#define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */ ++#define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */ ++#define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */ ++#define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */ ++#define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */ ++#define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */ ++#define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */ ++#define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */ ++#define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS ++#define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */ ++#define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */ ++#define SAFE_SA_CMD1_OFFSET_S 16 ++#define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */ ++#define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */ ++#define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */ ++#define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */ ++ ++/* ++ * Security Associate State Record (Rev 1). ++ */ ++struct safe_sastate { ++ u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */ ++ u_int32_t sa_saved_hashbc; /* saved hash byte count */ ++ u_int32_t sa_saved_indigest[5]; /* saved inner digest */ ++}; ++#endif /* _SAFE_SAFEREG_H_ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/safevar.h linux-3.0.4/crypto/ocf/safe/safevar.h +--- linux-3.0.4.orig/crypto/ocf/safe/safevar.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/safevar.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,229 @@ ++/*- ++ * The linux port of this code done by David McCullough ++ * Copyright (C) 2004-2010 David McCullough ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2003 Sam Leffler, Errno Consulting ++ * Copyright (c) 2003 Global Technology Associates, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++ * $FreeBSD: src/sys/dev/safe/safevar.h,v 1.2 2006/05/17 18:34:26 pjd Exp $ ++ */ ++#ifndef _SAFE_SAFEVAR_H_ ++#define _SAFE_SAFEVAR_H_ ++ ++/* Maximum queue length */ ++#ifndef SAFE_MAX_NQUEUE ++#define SAFE_MAX_NQUEUE 60 ++#endif ++ ++#define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ ++#define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ ++#define SAFE_MAX_DSIZE 2048 /* MCLBYTES Fixed scatter particle size */ ++#define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ ++#define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ ++/* total src+dst particle descriptors */ ++#define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) ++#define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) ++ ++#define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ ++ ++#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) ++#define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) ++#define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) ++ ++#define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ ++#define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ ++#define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ ++ ++#ifdef __KERNEL__ ++/* ++ * State associated with the allocation of each chunk ++ * of memory setup for DMA. ++ */ ++struct safe_dma_alloc { ++ dma_addr_t dma_paddr; ++ void *dma_vaddr; ++}; ++ ++/* ++ * Cryptographic operand state. One of these exists for each ++ * source and destination operand passed in from the crypto ++ * subsystem. When possible source and destination operands ++ * refer to the same memory. More often they are distinct. ++ * We track the virtual address of each operand as well as ++ * where each is mapped for DMA. ++ */ ++struct safe_operand { ++ union { ++ struct sk_buff *skb; ++ struct uio *io; ++ } u; ++ void *map; ++ int mapsize; /* total number of bytes in segs */ ++ struct { ++ dma_addr_t ds_addr; ++ int ds_len; ++ int ds_tlen; ++ } segs[SAFE_MAX_PART]; ++ int nsegs; ++}; ++ ++/* ++ * Packet engine ring entry and cryptographic operation state. ++ * The packet engine requires a ring of descriptors that contain ++ * pointers to various cryptographic state. However the ring ++ * configuration register allows you to specify an arbitrary size ++ * for ring entries. We use this feature to collect most of the ++ * state for each cryptographic request into one spot. Other than ++ * ring entries only the ``particle descriptors'' (scatter/gather ++ * lists) and the actual operand data are kept separate. The ++ * particle descriptors must also be organized in rings. The ++ * operand data can be located aribtrarily (modulo alignment constraints). ++ * ++ * Note that the descriptor ring is mapped onto the PCI bus so ++ * the hardware can DMA data. This means the entire ring must be ++ * contiguous. ++ */ ++struct safe_ringentry { ++ struct safe_desc re_desc; /* command descriptor */ ++ struct safe_sarec re_sa; /* SA record */ ++ struct safe_sastate re_sastate; /* SA state record */ ++ ++ struct cryptop *re_crp; /* crypto operation */ ++ ++ struct safe_operand re_src; /* source operand */ ++ struct safe_operand re_dst; /* destination operand */ ++ ++ int re_sesn; /* crypto session ID */ ++ int re_flags; ++#define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ ++#define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ ++}; ++ ++#define re_src_skb re_src.u.skb ++#define re_src_io re_src.u.io ++#define re_src_map re_src.map ++#define re_src_nsegs re_src.nsegs ++#define re_src_segs re_src.segs ++#define re_src_mapsize re_src.mapsize ++ ++#define re_dst_skb re_dst.u.skb ++#define re_dst_io re_dst.u.io ++#define re_dst_map re_dst.map ++#define re_dst_nsegs re_dst.nsegs ++#define re_dst_segs re_dst.segs ++#define re_dst_mapsize re_dst.mapsize ++ ++struct rndstate_test; ++ ++struct safe_session { ++ u_int32_t ses_used; ++ u_int32_t ses_klen; /* key length in bits */ ++ u_int32_t ses_key[8]; /* DES/3DES/AES key */ ++ u_int32_t ses_mlen; /* hmac length in bytes */ ++ u_int32_t ses_hminner[5]; /* hmac inner state */ ++ u_int32_t ses_hmouter[5]; /* hmac outer state */ ++}; ++ ++struct safe_pkq { ++ struct list_head pkq_list; ++ struct cryptkop *pkq_krp; ++}; ++ ++struct safe_softc { ++ softc_device_decl sc_dev; ++ u32 sc_irq; ++ ++ struct pci_dev *sc_pcidev; ++ ocf_iomem_t sc_base_addr; ++ ++ u_int sc_chiprev; /* major/minor chip revision */ ++ int sc_flags; /* device specific flags */ ++#define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ ++#define SAFE_FLAGS_RNG 0x02 /* hardware rng */ ++ int sc_suspended; ++ int sc_needwakeup; /* notify crypto layer */ ++ int32_t sc_cid; /* crypto tag */ ++ ++ struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ ++ struct safe_ringentry *sc_ring; /* PE ring */ ++ struct safe_ringentry *sc_ringtop; /* PE ring top */ ++ struct safe_ringentry *sc_front; /* next free entry */ ++ struct safe_ringentry *sc_back; /* next pending entry */ ++ int sc_nqchip; /* # passed to chip */ ++ spinlock_t sc_ringmtx; /* PE ring lock */ ++ struct safe_pdesc *sc_spring; /* src particle ring */ ++ struct safe_pdesc *sc_springtop; /* src particle ring top */ ++ struct safe_pdesc *sc_spfree; /* next free src particle */ ++ struct safe_dma_alloc sc_spalloc; /* src particle ring state */ ++ struct safe_pdesc *sc_dpring; /* dest particle ring */ ++ struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ ++ struct safe_pdesc *sc_dpfree; /* next free dest particle */ ++ struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ ++ int sc_nsessions; /* # of sessions */ ++ struct safe_session *sc_sessions; /* sessions */ ++ ++ struct timer_list sc_pkto; /* PK polling */ ++ spinlock_t sc_pkmtx; /* PK lock */ ++ struct list_head sc_pkq; /* queue of PK requests */ ++ struct safe_pkq *sc_pkq_cur; /* current processing request */ ++ u_int32_t sc_pk_reslen, sc_pk_resoff; ++ ++ int sc_max_dsize; /* maximum safe DMA size */ ++}; ++#endif /* __KERNEL__ */ ++ ++struct safe_stats { ++ u_int64_t st_ibytes; ++ u_int64_t st_obytes; ++ u_int32_t st_ipackets; ++ u_int32_t st_opackets; ++ u_int32_t st_invalid; /* invalid argument */ ++ u_int32_t st_badsession; /* invalid session id */ ++ u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ ++ u_int32_t st_nodesc; /* op submitted w/o descriptors */ ++ u_int32_t st_badalg; /* unsupported algorithm */ ++ u_int32_t st_ringfull; /* PE descriptor ring full */ ++ u_int32_t st_peoperr; /* PE marked error */ ++ u_int32_t st_dmaerr; /* PE DMA error */ ++ u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ ++ u_int32_t st_skipmismatch; /* enc part begins before auth part */ ++ u_int32_t st_lenmismatch; /* enc length different auth length */ ++ u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ ++ u_int32_t st_cofftoobig; /* crypto offset > 255 words */ ++ u_int32_t st_iovmisaligned; /* iov op not aligned */ ++ u_int32_t st_iovnotuniform; /* iov op not suitable */ ++ u_int32_t st_unaligned; /* unaligned src caused copy */ ++ u_int32_t st_notuniform; /* non-uniform src caused copy */ ++ u_int32_t st_nomap; /* bus_dmamap_create failed */ ++ u_int32_t st_noload; /* bus_dmamap_load_* failed */ ++ u_int32_t st_nombuf; /* MGET* failed */ ++ u_int32_t st_nomcl; /* MCLGET* failed */ ++ u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ ++ u_int32_t st_rng; /* RNG requests */ ++ u_int32_t st_rngalarm; /* RNG alarm requests */ ++ u_int32_t st_noicvcopy; /* ICV data copies suppressed */ ++}; ++#endif /* _SAFE_SAFEVAR_H_ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/sha1.c linux-3.0.4/crypto/ocf/safe/sha1.c +--- linux-3.0.4.orig/crypto/ocf/safe/sha1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/sha1.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,279 @@ ++/* $KAME: sha1.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++/* ++ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) ++ * based on: http://csrc.nist.gov/fips/fip180-1.txt ++ * implemented by Jun-ichiro itojun Itoh ++ */ ++ ++#if 0 ++#include ++__FBSDID("$FreeBSD: src/sys/crypto/sha1.c,v 1.9 2003/06/10 21:36:57 obrien Exp $"); ++ ++#include ++#include ++#include ++#include ++ ++#include ++#endif ++ ++/* sanity check */ ++#if BYTE_ORDER != BIG_ENDIAN ++# if BYTE_ORDER != LITTLE_ENDIAN ++# define unsupported 1 ++# endif ++#endif ++ ++#ifndef unsupported ++ ++/* constant table */ ++static u_int32_t _K[] = { 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 }; ++#define K(t) _K[(t) / 20] ++ ++#define F0(b, c, d) (((b) & (c)) | ((~(b)) & (d))) ++#define F1(b, c, d) (((b) ^ (c)) ^ (d)) ++#define F2(b, c, d) (((b) & (c)) | ((b) & (d)) | ((c) & (d))) ++#define F3(b, c, d) (((b) ^ (c)) ^ (d)) ++ ++#define S(n, x) (((x) << (n)) | ((x) >> (32 - n))) ++ ++#undef H ++#define H(n) (ctxt->h.b32[(n)]) ++#define COUNT (ctxt->count) ++#define BCOUNT (ctxt->c.b64[0] / 8) ++#define W(n) (ctxt->m.b32[(n)]) ++ ++#define PUTBYTE(x) { \ ++ ctxt->m.b8[(COUNT % 64)] = (x); \ ++ COUNT++; \ ++ COUNT %= 64; \ ++ ctxt->c.b64[0] += 8; \ ++ if (COUNT % 64 == 0) \ ++ sha1_step(ctxt); \ ++ } ++ ++#define PUTPAD(x) { \ ++ ctxt->m.b8[(COUNT % 64)] = (x); \ ++ COUNT++; \ ++ COUNT %= 64; \ ++ if (COUNT % 64 == 0) \ ++ sha1_step(ctxt); \ ++ } ++ ++static void sha1_step(struct sha1_ctxt *); ++ ++static void ++sha1_step(ctxt) ++ struct sha1_ctxt *ctxt; ++{ ++ u_int32_t a, b, c, d, e; ++ size_t t, s; ++ u_int32_t tmp; ++ ++#if BYTE_ORDER == LITTLE_ENDIAN ++ struct sha1_ctxt tctxt; ++ bcopy(&ctxt->m.b8[0], &tctxt.m.b8[0], 64); ++ ctxt->m.b8[0] = tctxt.m.b8[3]; ctxt->m.b8[1] = tctxt.m.b8[2]; ++ ctxt->m.b8[2] = tctxt.m.b8[1]; ctxt->m.b8[3] = tctxt.m.b8[0]; ++ ctxt->m.b8[4] = tctxt.m.b8[7]; ctxt->m.b8[5] = tctxt.m.b8[6]; ++ ctxt->m.b8[6] = tctxt.m.b8[5]; ctxt->m.b8[7] = tctxt.m.b8[4]; ++ ctxt->m.b8[8] = tctxt.m.b8[11]; ctxt->m.b8[9] = tctxt.m.b8[10]; ++ ctxt->m.b8[10] = tctxt.m.b8[9]; ctxt->m.b8[11] = tctxt.m.b8[8]; ++ ctxt->m.b8[12] = tctxt.m.b8[15]; ctxt->m.b8[13] = tctxt.m.b8[14]; ++ ctxt->m.b8[14] = tctxt.m.b8[13]; ctxt->m.b8[15] = tctxt.m.b8[12]; ++ ctxt->m.b8[16] = tctxt.m.b8[19]; ctxt->m.b8[17] = tctxt.m.b8[18]; ++ ctxt->m.b8[18] = tctxt.m.b8[17]; ctxt->m.b8[19] = tctxt.m.b8[16]; ++ ctxt->m.b8[20] = tctxt.m.b8[23]; ctxt->m.b8[21] = tctxt.m.b8[22]; ++ ctxt->m.b8[22] = tctxt.m.b8[21]; ctxt->m.b8[23] = tctxt.m.b8[20]; ++ ctxt->m.b8[24] = tctxt.m.b8[27]; ctxt->m.b8[25] = tctxt.m.b8[26]; ++ ctxt->m.b8[26] = tctxt.m.b8[25]; ctxt->m.b8[27] = tctxt.m.b8[24]; ++ ctxt->m.b8[28] = tctxt.m.b8[31]; ctxt->m.b8[29] = tctxt.m.b8[30]; ++ ctxt->m.b8[30] = tctxt.m.b8[29]; ctxt->m.b8[31] = tctxt.m.b8[28]; ++ ctxt->m.b8[32] = tctxt.m.b8[35]; ctxt->m.b8[33] = tctxt.m.b8[34]; ++ ctxt->m.b8[34] = tctxt.m.b8[33]; ctxt->m.b8[35] = tctxt.m.b8[32]; ++ ctxt->m.b8[36] = tctxt.m.b8[39]; ctxt->m.b8[37] = tctxt.m.b8[38]; ++ ctxt->m.b8[38] = tctxt.m.b8[37]; ctxt->m.b8[39] = tctxt.m.b8[36]; ++ ctxt->m.b8[40] = tctxt.m.b8[43]; ctxt->m.b8[41] = tctxt.m.b8[42]; ++ ctxt->m.b8[42] = tctxt.m.b8[41]; ctxt->m.b8[43] = tctxt.m.b8[40]; ++ ctxt->m.b8[44] = tctxt.m.b8[47]; ctxt->m.b8[45] = tctxt.m.b8[46]; ++ ctxt->m.b8[46] = tctxt.m.b8[45]; ctxt->m.b8[47] = tctxt.m.b8[44]; ++ ctxt->m.b8[48] = tctxt.m.b8[51]; ctxt->m.b8[49] = tctxt.m.b8[50]; ++ ctxt->m.b8[50] = tctxt.m.b8[49]; ctxt->m.b8[51] = tctxt.m.b8[48]; ++ ctxt->m.b8[52] = tctxt.m.b8[55]; ctxt->m.b8[53] = tctxt.m.b8[54]; ++ ctxt->m.b8[54] = tctxt.m.b8[53]; ctxt->m.b8[55] = tctxt.m.b8[52]; ++ ctxt->m.b8[56] = tctxt.m.b8[59]; ctxt->m.b8[57] = tctxt.m.b8[58]; ++ ctxt->m.b8[58] = tctxt.m.b8[57]; ctxt->m.b8[59] = tctxt.m.b8[56]; ++ ctxt->m.b8[60] = tctxt.m.b8[63]; ctxt->m.b8[61] = tctxt.m.b8[62]; ++ ctxt->m.b8[62] = tctxt.m.b8[61]; ctxt->m.b8[63] = tctxt.m.b8[60]; ++#endif ++ ++ a = H(0); b = H(1); c = H(2); d = H(3); e = H(4); ++ ++ for (t = 0; t < 20; t++) { ++ s = t & 0x0f; ++ if (t >= 16) { ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ } ++ tmp = S(5, a) + F0(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ for (t = 20; t < 40; t++) { ++ s = t & 0x0f; ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ tmp = S(5, a) + F1(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ for (t = 40; t < 60; t++) { ++ s = t & 0x0f; ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ tmp = S(5, a) + F2(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ for (t = 60; t < 80; t++) { ++ s = t & 0x0f; ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ tmp = S(5, a) + F3(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ ++ H(0) = H(0) + a; ++ H(1) = H(1) + b; ++ H(2) = H(2) + c; ++ H(3) = H(3) + d; ++ H(4) = H(4) + e; ++ ++ bzero(&ctxt->m.b8[0], 64); ++} ++ ++/*------------------------------------------------------------*/ ++ ++void ++sha1_init(ctxt) ++ struct sha1_ctxt *ctxt; ++{ ++ bzero(ctxt, sizeof(struct sha1_ctxt)); ++ H(0) = 0x67452301; ++ H(1) = 0xefcdab89; ++ H(2) = 0x98badcfe; ++ H(3) = 0x10325476; ++ H(4) = 0xc3d2e1f0; ++} ++ ++void ++sha1_pad(ctxt) ++ struct sha1_ctxt *ctxt; ++{ ++ size_t padlen; /*pad length in bytes*/ ++ size_t padstart; ++ ++ PUTPAD(0x80); ++ ++ padstart = COUNT % 64; ++ padlen = 64 - padstart; ++ if (padlen < 8) { ++ bzero(&ctxt->m.b8[padstart], padlen); ++ COUNT += padlen; ++ COUNT %= 64; ++ sha1_step(ctxt); ++ padstart = COUNT % 64; /* should be 0 */ ++ padlen = 64 - padstart; /* should be 64 */ ++ } ++ bzero(&ctxt->m.b8[padstart], padlen - 8); ++ COUNT += (padlen - 8); ++ COUNT %= 64; ++#if BYTE_ORDER == BIG_ENDIAN ++ PUTPAD(ctxt->c.b8[0]); PUTPAD(ctxt->c.b8[1]); ++ PUTPAD(ctxt->c.b8[2]); PUTPAD(ctxt->c.b8[3]); ++ PUTPAD(ctxt->c.b8[4]); PUTPAD(ctxt->c.b8[5]); ++ PUTPAD(ctxt->c.b8[6]); PUTPAD(ctxt->c.b8[7]); ++#else ++ PUTPAD(ctxt->c.b8[7]); PUTPAD(ctxt->c.b8[6]); ++ PUTPAD(ctxt->c.b8[5]); PUTPAD(ctxt->c.b8[4]); ++ PUTPAD(ctxt->c.b8[3]); PUTPAD(ctxt->c.b8[2]); ++ PUTPAD(ctxt->c.b8[1]); PUTPAD(ctxt->c.b8[0]); ++#endif ++} ++ ++void ++sha1_loop(ctxt, input, len) ++ struct sha1_ctxt *ctxt; ++ const u_int8_t *input; ++ size_t len; ++{ ++ size_t gaplen; ++ size_t gapstart; ++ size_t off; ++ size_t copysiz; ++ ++ off = 0; ++ ++ while (off < len) { ++ gapstart = COUNT % 64; ++ gaplen = 64 - gapstart; ++ ++ copysiz = (gaplen < len - off) ? gaplen : len - off; ++ bcopy(&input[off], &ctxt->m.b8[gapstart], copysiz); ++ COUNT += copysiz; ++ COUNT %= 64; ++ ctxt->c.b64[0] += copysiz * 8; ++ if (COUNT % 64 == 0) ++ sha1_step(ctxt); ++ off += copysiz; ++ } ++} ++ ++void ++sha1_result(ctxt, digest0) ++ struct sha1_ctxt *ctxt; ++ caddr_t digest0; ++{ ++ u_int8_t *digest; ++ ++ digest = (u_int8_t *)digest0; ++ sha1_pad(ctxt); ++#if BYTE_ORDER == BIG_ENDIAN ++ bcopy(&ctxt->h.b8[0], digest, 20); ++#else ++ digest[0] = ctxt->h.b8[3]; digest[1] = ctxt->h.b8[2]; ++ digest[2] = ctxt->h.b8[1]; digest[3] = ctxt->h.b8[0]; ++ digest[4] = ctxt->h.b8[7]; digest[5] = ctxt->h.b8[6]; ++ digest[6] = ctxt->h.b8[5]; digest[7] = ctxt->h.b8[4]; ++ digest[8] = ctxt->h.b8[11]; digest[9] = ctxt->h.b8[10]; ++ digest[10] = ctxt->h.b8[9]; digest[11] = ctxt->h.b8[8]; ++ digest[12] = ctxt->h.b8[15]; digest[13] = ctxt->h.b8[14]; ++ digest[14] = ctxt->h.b8[13]; digest[15] = ctxt->h.b8[12]; ++ digest[16] = ctxt->h.b8[19]; digest[17] = ctxt->h.b8[18]; ++ digest[18] = ctxt->h.b8[17]; digest[19] = ctxt->h.b8[16]; ++#endif ++} ++ ++#endif /*unsupported*/ +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/sha1.h linux-3.0.4/crypto/ocf/safe/sha1.h +--- linux-3.0.4.orig/crypto/ocf/safe/sha1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/sha1.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,72 @@ ++/* $FreeBSD: src/sys/crypto/sha1.h,v 1.8 2002/03/20 05:13:50 alfred Exp $ */ ++/* $KAME: sha1.h,v 1.5 2000/03/27 04:36:23 sumikawa Exp $ */ ++ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++/* ++ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) ++ * based on: http://csrc.nist.gov/fips/fip180-1.txt ++ * implemented by Jun-ichiro itojun Itoh ++ */ ++ ++#ifndef _NETINET6_SHA1_H_ ++#define _NETINET6_SHA1_H_ ++ ++struct sha1_ctxt { ++ union { ++ u_int8_t b8[20]; ++ u_int32_t b32[5]; ++ } h; ++ union { ++ u_int8_t b8[8]; ++ u_int64_t b64[1]; ++ } c; ++ union { ++ u_int8_t b8[64]; ++ u_int32_t b32[16]; ++ } m; ++ u_int8_t count; ++}; ++ ++#ifdef __KERNEL__ ++extern void sha1_init(struct sha1_ctxt *); ++extern void sha1_pad(struct sha1_ctxt *); ++extern void sha1_loop(struct sha1_ctxt *, const u_int8_t *, size_t); ++extern void sha1_result(struct sha1_ctxt *, caddr_t); ++ ++/* compatibilty with other SHA1 source codes */ ++typedef struct sha1_ctxt SHA1_CTX; ++#define SHA1Init(x) sha1_init((x)) ++#define SHA1Update(x, y, z) sha1_loop((x), (y), (z)) ++#define SHA1Final(x, y) sha1_result((y), (x)) ++#endif /* __KERNEL__ */ ++ ++#define SHA1_RESULTLEN (160/8) ++ ++#endif /*_NETINET6_SHA1_H_*/ +diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/Makefile linux-3.0.4/crypto/ocf/talitos/Makefile +--- linux-3.0.4.orig/crypto/ocf/talitos/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/talitos/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_TALITOS) += talitos.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/talitos.c linux-3.0.4/crypto/ocf/talitos/talitos.c +--- linux-3.0.4.orig/crypto/ocf/talitos/talitos.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/talitos/talitos.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1355 @@ ++/* ++ * crypto/ocf/talitos/talitos.c ++ * ++ * An OCF-Linux module that uses Freescale's SEC to do the crypto. ++ * Based on crypto/ocf/hifn and crypto/ocf/safe OCF drivers ++ * ++ * Copyright (c) 2006 Freescale Semiconductor, Inc. ++ * ++ * This code written by Kim A. B. Phillips ++ * some code copied from files with the following: ++ * Copyright (C) 2004-2007 David McCullough ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * --------------------------------------------------------------------------- ++ * ++ * NOTES: ++ * ++ * The Freescale SEC (also known as 'talitos') resides on the ++ * internal bus, and runs asynchronous to the processor core. It has ++ * a wide gamut of cryptographic acceleration features, including single- ++ * pass IPsec (also known as algorithm chaining). To properly utilize ++ * all of the SEC's performance enhancing features, further reworking ++ * of higher level code (framework, applications) will be necessary. ++ * ++ * The following table shows which SEC version is present in which devices: ++ * ++ * Devices SEC version ++ * ++ * 8272, 8248 SEC 1.0 ++ * 885, 875 SEC 1.2 ++ * 8555E, 8541E SEC 2.0 ++ * 8349E SEC 2.01 ++ * 8548E SEC 2.1 ++ * ++ * The following table shows the features offered by each SEC version: ++ * ++ * Max. chan- ++ * version Bus I/F Clock nels DEU AESU AFEU MDEU PKEU RNG KEU ++ * ++ * SEC 1.0 internal 64b 100MHz 4 1 1 1 1 1 1 0 ++ * SEC 1.2 internal 32b 66MHz 1 1 1 0 1 0 0 0 ++ * SEC 2.0 internal 64b 166MHz 4 1 1 1 1 1 1 0 ++ * SEC 2.01 internal 64b 166MHz 4 1 1 1 1 1 1 0 ++ * SEC 2.1 internal 64b 333MHz 4 1 1 1 1 1 1 1 ++ * ++ * Each execution unit in the SEC has two modes of execution; channel and ++ * slave/debug. This driver employs the channel infrastructure in the ++ * device for convenience. Only the RNG is directly accessed due to the ++ * convenience of its random fifo pool. The relationship between the ++ * channels and execution units is depicted in the following diagram: ++ * ++ * ------- ------------ ++ * ---| ch0 |---| | ++ * ------- | | ++ * | |------+-------+-------+-------+------------ ++ * ------- | | | | | | | ++ * ---| ch1 |---| | | | | | | ++ * ------- | | ------ ------ ------ ------ ------ ++ * |controller| |DEU | |AESU| |MDEU| |PKEU| ... |RNG | ++ * ------- | | ------ ------ ------ ------ ------ ++ * ---| ch2 |---| | | | | | | ++ * ------- | | | | | | | ++ * | |------+-------+-------+-------+------------ ++ * ------- | | ++ * ---| ch3 |---| | ++ * ------- ------------ ++ * ++ * Channel ch0 may drive an aes operation to the aes unit (AESU), ++ * and, at the same time, ch1 may drive a message digest operation ++ * to the mdeu. Each channel has an input descriptor FIFO, and the ++ * FIFO can contain, e.g. on the 8541E, up to 24 entries, before a ++ * a buffer overrun error is triggered. The controller is responsible ++ * for fetching the data from descriptor pointers, and passing the ++ * data to the appropriate EUs. The controller also writes the ++ * cryptographic operation's result to memory. The SEC notifies ++ * completion by triggering an interrupt and/or setting the 1st byte ++ * of the hdr field to 0xff. ++ * ++ * TODO: ++ * o support more algorithms ++ * o support more versions of the SEC ++ * o add support for linux 2.4 ++ * o scatter-gather (sg) support ++ * o add support for public key ops (PKEU) ++ * o add statistics ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* dma_map_single() */ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) ++#include ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++#include ++#endif ++ ++#include ++#include ++ ++#define DRV_NAME "talitos" ++ ++#include "talitos_dev.h" ++#include "talitos_soft.h" ++ ++#define read_random(p,l) get_random_bytes(p,l) ++ ++const char talitos_driver_name[] = "Talitos OCF"; ++const char talitos_driver_version[] = "0.2"; ++ ++static int talitos_newsession(device_t dev, u_int32_t *sidp, ++ struct cryptoini *cri); ++static int talitos_freesession(device_t dev, u_int64_t tid); ++static int talitos_process(device_t dev, struct cryptop *crp, int hint); ++static void dump_talitos_status(struct talitos_softc *sc); ++static int talitos_submit(struct talitos_softc *sc, struct talitos_desc *td, ++ int chsel); ++static void talitos_doneprocessing(struct talitos_softc *sc); ++static void talitos_init_device(struct talitos_softc *sc); ++static void talitos_reset_device_master(struct talitos_softc *sc); ++static void talitos_reset_device(struct talitos_softc *sc); ++static void talitos_errorprocessing(struct talitos_softc *sc); ++#ifdef CONFIG_PPC_MERGE ++static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match); ++static int talitos_remove(struct of_device *ofdev); ++#else ++static int talitos_probe(struct platform_device *pdev); ++static int talitos_remove(struct platform_device *pdev); ++#endif ++#ifdef CONFIG_OCF_RANDOMHARVEST ++static int talitos_read_random(void *arg, u_int32_t *buf, int maxwords); ++static void talitos_rng_init(struct talitos_softc *sc); ++#endif ++ ++static device_method_t talitos_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, talitos_newsession), ++ DEVMETHOD(cryptodev_freesession,talitos_freesession), ++ DEVMETHOD(cryptodev_process, talitos_process), ++}; ++ ++#define debug talitos_debug ++int talitos_debug = 0; ++module_param(talitos_debug, int, 0644); ++MODULE_PARM_DESC(talitos_debug, "Enable debug"); ++ ++static inline void talitos_write(volatile unsigned *addr, u32 val) ++{ ++ out_be32(addr, val); ++} ++ ++static inline u32 talitos_read(volatile unsigned *addr) ++{ ++ u32 val; ++ val = in_be32(addr); ++ return val; ++} ++ ++static void dump_talitos_status(struct talitos_softc *sc) ++{ ++ unsigned int v, v_hi, i, *ptr; ++ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_MCR_HI); ++ printk(KERN_INFO "%s: MCR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); ++ printk(KERN_INFO "%s: IMR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); ++ printk(KERN_INFO "%s: ISR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CDPR); ++ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CDPR_HI); ++ printk(KERN_INFO "%s: CDPR ch%d 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), i, v, v_hi); ++ } ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCPSR); ++ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCPSR_HI); ++ printk(KERN_INFO "%s: CCPSR ch%d 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), i, v, v_hi); ++ } ++ ptr = sc->sc_base_addr + TALITOS_CH_DESCBUF; ++ for (i = 0; i < 16; i++) { ++ v = talitos_read(ptr++); v_hi = talitos_read(ptr++); ++ printk(KERN_INFO "%s: DESCBUF ch0 0x%08x_%08x (tdp%02d)\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi, i); ++ } ++ return; ++} ++ ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++/* ++ * pull random numbers off the RNG FIFO, not exceeding amount available ++ */ ++static int ++talitos_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ struct talitos_softc *sc = (struct talitos_softc *) arg; ++ int rc; ++ u_int32_t v; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* check for things like FIFO underflow */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); ++ if (unlikely(v)) { ++ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", ++ device_get_nameunit(sc->sc_cdev), v); ++ return 0; ++ } ++ /* ++ * OFL is number of available 64-bit words, ++ * shift and convert to a 32-bit word count ++ */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI); ++ v = (v & TALITOS_RNGSR_HI_OFL) >> (16 - 1); ++ if (maxwords > v) ++ maxwords = v; ++ for (rc = 0; rc < maxwords; rc++) { ++ buf[rc] = talitos_read(sc->sc_base_addr + ++ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); ++ } ++ if (maxwords & 1) { ++ /* ++ * RNG will complain with an AE in the RNGISR ++ * if we don't complete the pairs of 32-bit reads ++ * to its 64-bit register based FIFO ++ */ ++ v = talitos_read(sc->sc_base_addr + ++ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); ++ } ++ ++ return rc; ++} ++ ++static void ++talitos_rng_init(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ /* reset RNG EU */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGRCR_HI); ++ v |= TALITOS_RNGRCR_HI_SR; ++ talitos_write(sc->sc_base_addr + TALITOS_RNGRCR_HI, v); ++ while ((talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI) ++ & TALITOS_RNGSR_HI_RD) == 0) ++ cpu_relax(); ++ /* ++ * we tell the RNG to start filling the RNG FIFO ++ * by writing the RNGDSR ++ */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGDSR_HI); ++ talitos_write(sc->sc_base_addr + TALITOS_RNGDSR_HI, v); ++ /* ++ * 64 bits of data will be pushed onto the FIFO every ++ * 256 SEC cycles until the FIFO is full. The RNG then ++ * attempts to keep the FIFO full. ++ */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); ++ if (v) { ++ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", ++ device_get_nameunit(sc->sc_cdev), v); ++ return; ++ } ++ /* ++ * n.b. we need to add a FIPS test here - if the RNG is going ++ * to fail, it's going to fail at reset time ++ */ ++ return; ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++talitos_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct talitos_softc *sc = device_get_softc(dev); ++ struct talitos_session *ses = NULL; ++ int sesn; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ if (sidp == NULL || cri == NULL || sc == NULL) { ++ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (c->cri_alg == CRYPTO_MD5 || ++ c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1 || ++ c->cri_alg == CRYPTO_SHA1_HMAC || ++ c->cri_alg == CRYPTO_NULL_HMAC) { ++ if (macini) ++ return EINVAL; ++ macini = c; ++ } else if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC || ++ c->cri_alg == CRYPTO_NULL_CBC) { ++ if (encini) ++ return EINVAL; ++ encini = c; ++ } else { ++ DPRINTF("UNKNOWN c->cri_alg %d\n", encini->cri_alg); ++ return EINVAL; ++ } ++ } ++ if (encini == NULL && macini == NULL) ++ return EINVAL; ++ if (encini) { ++ /* validate key length */ ++ switch (encini->cri_alg) { ++ case CRYPTO_DES_CBC: ++ if (encini->cri_klen != 64) ++ return EINVAL; ++ break; ++ case CRYPTO_3DES_CBC: ++ if (encini->cri_klen != 192) { ++ return EINVAL; ++ } ++ break; ++ case CRYPTO_AES_CBC: ++ if (encini->cri_klen != 128 && ++ encini->cri_klen != 192 && ++ encini->cri_klen != 256) ++ return EINVAL; ++ break; ++ default: ++ DPRINTF("UNKNOWN encini->cri_alg %d\n", ++ encini->cri_alg); ++ return EINVAL; ++ } ++ } ++ ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct talitos_session *) ++ kmalloc(sizeof(struct talitos_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return ENOMEM; ++ memset(ses, 0, sizeof(struct talitos_session)); ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn].ses_used == 0) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ /* allocating session */ ++ sesn = sc->sc_nsessions; ++ ses = (struct talitos_session *) kmalloc( ++ (sesn + 1) * sizeof(struct talitos_session), ++ SLAB_ATOMIC); ++ if (ses == NULL) ++ return ENOMEM; ++ memset(ses, 0, ++ (sesn + 1) * sizeof(struct talitos_session)); ++ memcpy(ses, sc->sc_sessions, ++ sesn * sizeof(struct talitos_session)); ++ memset(sc->sc_sessions, 0, ++ sesn * sizeof(struct talitos_session)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ ++ ses->ses_used = 1; ++ ++ if (encini) { ++ ses->ses_klen = (encini->cri_klen + 7) / 8; ++ memcpy(ses->ses_key, encini->cri_key, ses->ses_klen); ++ if (macini) { ++ /* doing hash on top of cipher */ ++ ses->ses_hmac_len = (macini->cri_klen + 7) / 8; ++ memcpy(ses->ses_hmac, macini->cri_key, ++ ses->ses_hmac_len); ++ } ++ } else if (macini) { ++ /* doing hash */ ++ ses->ses_klen = (macini->cri_klen + 7) / 8; ++ memcpy(ses->ses_key, macini->cri_key, ses->ses_klen); ++ } ++ ++ /* back compat way of determining MSC result len */ ++ if (macini) { ++ ses->ses_mlen = macini->cri_mlen; ++ if (ses->ses_mlen == 0) { ++ if (macini->cri_alg == CRYPTO_MD5_HMAC) ++ ses->ses_mlen = MD5_HASH_LEN; ++ else ++ ses->ses_mlen = SHA1_HASH_LEN; ++ } ++ } ++ ++ /* really should make up a template td here, ++ * and only fill things like i/o and direction in process() */ ++ ++ /* assign session ID */ ++ *sidp = TALITOS_SID(sc->sc_num, sesn); ++ return 0; ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++talitos_freesession(device_t dev, u_int64_t tid) ++{ ++ struct talitos_softc *sc = device_get_softc(dev); ++ int session, ret; ++ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; ++ ++ if (sc == NULL) ++ return EINVAL; ++ session = TALITOS_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ memset(&sc->sc_sessions[session], 0, ++ sizeof(sc->sc_sessions[session])); ++ ret = 0; ++ } else ++ ret = EINVAL; ++ return ret; ++} ++ ++/* ++ * launch device processing - it will come back with done notification ++ * in the form of an interrupt and/or HDR_DONE_BITS in header ++ */ ++static int ++talitos_submit( ++ struct talitos_softc *sc, ++ struct talitos_desc *td, ++ int chsel) ++{ ++ u_int32_t v; ++ ++ v = dma_map_single(NULL, td, sizeof(*td), DMA_TO_DEVICE); ++ talitos_write(sc->sc_base_addr + ++ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF, 0); ++ talitos_write(sc->sc_base_addr + ++ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF_HI, v); ++ return 0; ++} ++ ++static int ++talitos_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ int i, err = 0, ivsize; ++ struct talitos_softc *sc = device_get_softc(dev); ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ caddr_t iv; ++ struct talitos_session *ses; ++ struct talitos_desc *td; ++ unsigned long flags; ++ /* descriptor mappings */ ++ int hmac_key, hmac_data, cipher_iv, cipher_key, ++ in_fifo, out_fifo, cipher_iv_out; ++ static int chsel = -1; ++ u_int32_t rand_iv[4]; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { ++ return EINVAL; ++ } ++ crp->crp_etype = 0; ++ if (TALITOS_SESSION(crp->crp_sid) >= sc->sc_nsessions) { ++ return EINVAL; ++ } ++ ++ ses = &sc->sc_sessions[TALITOS_SESSION(crp->crp_sid)]; ++ ++ /* enter the channel scheduler */ ++ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ /* reuse channel that already had/has requests for the required EU */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ if (sc->sc_chnlastalg[i] == crp->crp_desc->crd_alg) ++ break; ++ } ++ if (i == sc->sc_num_channels) { ++ /* ++ * haven't seen this algo the last sc_num_channels or more ++ * use round robin in this case ++ * nb: sc->sc_num_channels must be power of 2 ++ */ ++ chsel = (chsel + 1) & (sc->sc_num_channels - 1); ++ } else { ++ /* ++ * matches channel with same target execution unit; ++ * use same channel in this case ++ */ ++ chsel = i; ++ } ++ sc->sc_chnlastalg[chsel] = crp->crp_desc->crd_alg; ++ ++ /* release the channel scheduler lock */ ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ /* acquire the selected channel fifo lock */ ++ spin_lock_irqsave(&sc->sc_chnfifolock[chsel], flags); ++ ++ /* find and reserve next available descriptor-cryptop pair */ ++ for (i = 0; i < sc->sc_chfifo_len; i++) { ++ if (sc->sc_chnfifo[chsel][i].cf_desc.hdr == 0) { ++ /* ++ * ensure correct descriptor formation by ++ * avoiding inadvertently setting "optional" entries ++ * e.g. not using "optional" dptr2 for MD/HMAC descs ++ */ ++ memset(&sc->sc_chnfifo[chsel][i].cf_desc, ++ 0, sizeof(*td)); ++ /* reserve it with done notification request bit */ ++ sc->sc_chnfifo[chsel][i].cf_desc.hdr |= ++ TALITOS_DONE_NOTIFY; ++ break; ++ } ++ } ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[chsel], flags); ++ ++ if (i == sc->sc_chfifo_len) { ++ /* fifo full */ ++ err = ERESTART; ++ goto errout; ++ } ++ ++ td = &sc->sc_chnfifo[chsel][i].cf_desc; ++ sc->sc_chnfifo[chsel][i].cf_crp = crp; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ /* prevent compiler warning */ ++ hmac_key = 0; ++ hmac_data = 0; ++ if (crd2 == NULL) { ++ td->hdr |= TD_TYPE_COMMON_NONSNOOP_NO_AFEU; ++ /* assign descriptor dword ptr mappings for this desc. type */ ++ cipher_iv = 1; ++ cipher_key = 2; ++ in_fifo = 3; ++ cipher_iv_out = 5; ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1 || ++ crd1->crd_alg == CRYPTO_MD5) { ++ out_fifo = 5; ++ maccrd = crd1; ++ enccrd = NULL; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4) { ++ out_fifo = 4; ++ maccrd = NULL; ++ enccrd = crd1; ++ } else { ++ DPRINTF("UNKNOWN crd1->crd_alg %d\n", crd1->crd_alg); ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if (sc->sc_desc_types & TALITOS_HAS_DT_IPSEC_ESP) { ++ td->hdr |= TD_TYPE_IPSEC_ESP; ++ } else { ++ DPRINTF("unimplemented: multiple descriptor ipsec\n"); ++ err = EINVAL; ++ goto errout; ++ } ++ /* assign descriptor dword ptr mappings for this desc. type */ ++ hmac_key = 0; ++ hmac_data = 1; ++ cipher_iv = 2; ++ cipher_key = 3; ++ in_fifo = 4; ++ out_fifo = 5; ++ cipher_iv_out = 6; ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_MD5 || ++ crd1->crd_alg == CRYPTO_SHA1) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC || ++ crd2->crd_alg == CRYPTO_ARC4) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4 || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC || ++ crd2->crd_alg == CRYPTO_MD5 || ++ crd2->crd_alg == CRYPTO_SHA1) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ /* We cannot order the SEC as requested */ ++ printk("%s: cannot do the order\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ /* assign in_fifo and out_fifo based on input/output struct type */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ /* using SKB buffers */ ++ struct sk_buff *skb = (struct sk_buff *)crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ printk("%s: skb frags unimplemented\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ td->ptr[in_fifo].ptr = dma_map_single(NULL, skb->data, ++ skb->len, DMA_TO_DEVICE); ++ td->ptr[in_fifo].len = skb->len; ++ td->ptr[out_fifo].ptr = dma_map_single(NULL, skb->data, ++ skb->len, DMA_TO_DEVICE); ++ td->ptr[out_fifo].len = skb->len; ++ td->ptr[hmac_data].ptr = dma_map_single(NULL, skb->data, ++ skb->len, DMA_TO_DEVICE); ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ /* using IOV buffers */ ++ struct uio *uiop = (struct uio *)crp->crp_buf; ++ if (uiop->uio_iovcnt > 1) { ++ printk("%s: iov frags unimplemented\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ td->ptr[in_fifo].ptr = dma_map_single(NULL, ++ uiop->uio_iov->iov_base, crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[in_fifo].len = crp->crp_ilen; ++ /* crp_olen is never set; always use crp_ilen */ ++ td->ptr[out_fifo].ptr = dma_map_single(NULL, ++ uiop->uio_iov->iov_base, ++ crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[out_fifo].len = crp->crp_ilen; ++ } else { ++ /* using contig buffers */ ++ td->ptr[in_fifo].ptr = dma_map_single(NULL, ++ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[in_fifo].len = crp->crp_ilen; ++ td->ptr[out_fifo].ptr = dma_map_single(NULL, ++ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[out_fifo].len = crp->crp_ilen; ++ } ++ if (enccrd) { ++ switch (enccrd->crd_alg) { ++ case CRYPTO_3DES_CBC: ++ td->hdr |= TALITOS_MODE0_DEU_3DES; ++ /* FALLTHROUGH */ ++ case CRYPTO_DES_CBC: ++ td->hdr |= TALITOS_SEL0_DEU ++ | TALITOS_MODE0_DEU_CBC; ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) ++ td->hdr |= TALITOS_MODE0_DEU_ENC; ++ ivsize = 2*sizeof(u_int32_t); ++ DPRINTF("%cDES ses %d ch %d len %d\n", ++ (td->hdr & TALITOS_MODE0_DEU_3DES)?'3':'1', ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ case CRYPTO_AES_CBC: ++ td->hdr |= TALITOS_SEL0_AESU ++ | TALITOS_MODE0_AESU_CBC; ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) ++ td->hdr |= TALITOS_MODE0_AESU_ENC; ++ ivsize = 4*sizeof(u_int32_t); ++ DPRINTF("AES ses %d ch %d len %d\n", ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ default: ++ printk("%s: unimplemented enccrd->crd_alg %d\n", ++ device_get_nameunit(sc->sc_cdev), enccrd->crd_alg); ++ err = EINVAL; ++ goto errout; ++ } ++ /* ++ * Setup encrypt/decrypt state. When using basic ops ++ * we can't use an inline IV because hash/crypt offset ++ * must be from the end of the IV to the start of the ++ * crypt data and this leaves out the preceding header ++ * from the hash calculation. Instead we place the IV ++ * in the state record and set the hash/crypt offset to ++ * copy both the header+IV. ++ */ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ td->hdr |= TALITOS_DIR_OUTBOUND; ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ iv = enccrd->crd_iv; ++ else ++ read_random((iv = (caddr_t) rand_iv), sizeof(rand_iv)); ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, iv); ++ } ++ } else { ++ td->hdr |= TALITOS_DIR_INBOUND; ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ iv = enccrd->crd_iv; ++ } else { ++ iv = (caddr_t) rand_iv; ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, iv); ++ } ++ } ++ td->ptr[cipher_iv].ptr = dma_map_single(NULL, iv, ivsize, ++ DMA_TO_DEVICE); ++ td->ptr[cipher_iv].len = ivsize; ++ /* ++ * we don't need the cipher iv out length/pointer ++ * field to do ESP IPsec. Therefore we set the len field as 0, ++ * which tells the SEC not to do anything with this len/ptr ++ * field. Previously, when length/pointer as pointing to iv, ++ * it gave us corruption of packets. ++ */ ++ td->ptr[cipher_iv_out].len = 0; ++ } ++ if (enccrd && maccrd) { ++ /* this is ipsec only for now */ ++ td->hdr |= TALITOS_SEL1_MDEU ++ | TALITOS_MODE1_MDEU_INIT ++ | TALITOS_MODE1_MDEU_PAD; ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ td->hdr |= TALITOS_MODE1_MDEU_MD5; ++ break; ++ case CRYPTO_MD5_HMAC: ++ td->hdr |= TALITOS_MODE1_MDEU_MD5_HMAC; ++ break; ++ case CRYPTO_SHA1: ++ td->hdr |= TALITOS_MODE1_MDEU_SHA1; ++ break; ++ case CRYPTO_SHA1_HMAC: ++ td->hdr |= TALITOS_MODE1_MDEU_SHA1_HMAC; ++ break; ++ default: ++ /* We cannot order the SEC as requested */ ++ printk("%s: cannot do the order\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || ++ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { ++ /* ++ * The offset from hash data to the start of ++ * crypt data is the difference in the skips. ++ */ ++ /* ipsec only for now */ ++ td->ptr[hmac_key].ptr = dma_map_single(NULL, ++ ses->ses_hmac, ses->ses_hmac_len, DMA_TO_DEVICE); ++ td->ptr[hmac_key].len = ses->ses_hmac_len; ++ td->ptr[in_fifo].ptr += enccrd->crd_skip; ++ td->ptr[in_fifo].len = enccrd->crd_len; ++ td->ptr[out_fifo].ptr += enccrd->crd_skip; ++ td->ptr[out_fifo].len = enccrd->crd_len; ++ /* bytes of HMAC to postpend to ciphertext */ ++ td->ptr[out_fifo].extent = ses->ses_mlen; ++ td->ptr[hmac_data].ptr += maccrd->crd_skip; ++ td->ptr[hmac_data].len = enccrd->crd_skip - maccrd->crd_skip; ++ } ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ printk("%s: CRD_F_KEY_EXPLICIT unimplemented\n", ++ device_get_nameunit(sc->sc_cdev)); ++ } ++ } ++ if (!enccrd && maccrd) { ++ /* single MD5 or SHA */ ++ td->hdr |= TALITOS_SEL0_MDEU ++ | TALITOS_MODE0_MDEU_INIT ++ | TALITOS_MODE0_MDEU_PAD; ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ td->hdr |= TALITOS_MODE0_MDEU_MD5; ++ DPRINTF("MD5 ses %d ch %d len %d\n", ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ case CRYPTO_MD5_HMAC: ++ td->hdr |= TALITOS_MODE0_MDEU_MD5_HMAC; ++ break; ++ case CRYPTO_SHA1: ++ td->hdr |= TALITOS_MODE0_MDEU_SHA1; ++ DPRINTF("SHA1 ses %d ch %d len %d\n", ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ td->hdr |= TALITOS_MODE0_MDEU_SHA1_HMAC; ++ break; ++ default: ++ /* We cannot order the SEC as requested */ ++ DPRINTF("cannot do the order\n"); ++ err = EINVAL; ++ goto errout; ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_IOV) ++ td->ptr[out_fifo].ptr += maccrd->crd_inject; ++ ++ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || ++ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { ++ td->ptr[hmac_key].ptr = dma_map_single(NULL, ++ ses->ses_hmac, ses->ses_hmac_len, ++ DMA_TO_DEVICE); ++ td->ptr[hmac_key].len = ses->ses_hmac_len; ++ } ++ } ++ else { ++ /* using process key (session data has duplicate) */ ++ td->ptr[cipher_key].ptr = dma_map_single(NULL, ++ enccrd->crd_key, (enccrd->crd_klen + 7) / 8, ++ DMA_TO_DEVICE); ++ td->ptr[cipher_key].len = (enccrd->crd_klen + 7) / 8; ++ } ++ /* descriptor complete - GO! */ ++ return talitos_submit(sc, td, chsel); ++ ++errout: ++ if (err != ERESTART) { ++ crp->crp_etype = err; ++ crypto_done(crp); ++ } ++ return err; ++} ++ ++/* go through all channels descriptors, notifying OCF what has ++ * _and_hasn't_ successfully completed and reset the device ++ * (otherwise it's up to decoding desc hdrs!) ++ */ ++static void talitos_errorprocessing(struct talitos_softc *sc) ++{ ++ unsigned long flags; ++ int i, j; ++ ++ /* disable further scheduling until under control */ ++ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ if (debug) dump_talitos_status(sc); ++ /* go through descriptors, try and salvage those successfully done, ++ * and EIO those that weren't ++ */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); ++ for (j = 0; j < sc->sc_chfifo_len; j++) { ++ if (sc->sc_chnfifo[i][j].cf_desc.hdr) { ++ if ((sc->sc_chnfifo[i][j].cf_desc.hdr ++ & TALITOS_HDR_DONE_BITS) ++ != TALITOS_HDR_DONE_BITS) { ++ /* this one didn't finish */ ++ /* signify in crp->etype */ ++ sc->sc_chnfifo[i][j].cf_crp->crp_etype ++ = EIO; ++ } ++ } else ++ continue; /* free entry */ ++ /* either way, notify ocf */ ++ crypto_done(sc->sc_chnfifo[i][j].cf_crp); ++ /* and tag it available again ++ * ++ * memset to ensure correct descriptor formation by ++ * avoiding inadvertently setting "optional" entries ++ * e.g. not using "optional" dptr2 MD/HMAC processing ++ */ ++ memset(&sc->sc_chnfifo[i][j].cf_desc, ++ 0, sizeof(struct talitos_desc)); ++ } ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); ++ } ++ /* reset and initialize the SEC h/w device */ ++ talitos_reset_device(sc); ++ talitos_init_device(sc); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) ++ talitos_rng_init(sc); ++#endif ++ ++ /* Okay. Stand by. */ ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ return; ++} ++ ++/* go through all channels descriptors, notifying OCF what's been done */ ++static void talitos_doneprocessing(struct talitos_softc *sc) ++{ ++ unsigned long flags; ++ int i, j; ++ ++ /* go through descriptors looking for done bits */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); ++ for (j = 0; j < sc->sc_chfifo_len; j++) { ++ /* descriptor has done bits set? */ ++ if ((sc->sc_chnfifo[i][j].cf_desc.hdr ++ & TALITOS_HDR_DONE_BITS) ++ == TALITOS_HDR_DONE_BITS) { ++ /* notify ocf */ ++ crypto_done(sc->sc_chnfifo[i][j].cf_crp); ++ /* and tag it available again ++ * ++ * memset to ensure correct descriptor formation by ++ * avoiding inadvertently setting "optional" entries ++ * e.g. not using "optional" dptr2 MD/HMAC processing ++ */ ++ memset(&sc->sc_chnfifo[i][j].cf_desc, ++ 0, sizeof(struct talitos_desc)); ++ } ++ } ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); ++ } ++ return; ++} ++ ++static irqreturn_t ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++talitos_intr(int irq, void *arg) ++#else ++talitos_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct talitos_softc *sc = arg; ++ u_int32_t v, v_hi; ++ ++ /* ack */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); ++ talitos_write(sc->sc_base_addr + TALITOS_ICR, v); ++ talitos_write(sc->sc_base_addr + TALITOS_ICR_HI, v_hi); ++ ++ if (unlikely(v & TALITOS_ISR_ERROR)) { ++ /* Okay, Houston, we've had a problem here. */ ++ printk(KERN_DEBUG "%s: got error interrupt - ISR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ talitos_errorprocessing(sc); ++ } else ++ if (likely(v & TALITOS_ISR_DONE)) { ++ talitos_doneprocessing(sc); ++ } ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Initialize registers we need to touch only once. ++ */ ++static void ++talitos_init_device(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* init all channels */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + ++ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI); ++ v |= TALITOS_CH_CCCR_HI_CDWE ++ | TALITOS_CH_CCCR_HI_CDIE; /* invoke interrupt if done */ ++ talitos_write(sc->sc_base_addr + ++ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI, v); ++ } ++ /* enable all interrupts */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); ++ v |= TALITOS_IMR_ALL; ++ talitos_write(sc->sc_base_addr + TALITOS_IMR, v); ++ v = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); ++ v |= TALITOS_IMR_HI_ERRONLY; ++ talitos_write(sc->sc_base_addr + TALITOS_IMR_HI, v); ++ return; ++} ++ ++/* ++ * set the master reset bit on the device. ++ */ ++static void ++talitos_reset_device_master(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ ++ /* Reset the device by writing 1 to MCR:SWR and waiting 'til cleared */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); ++ talitos_write(sc->sc_base_addr + TALITOS_MCR, v | TALITOS_MCR_SWR); ++ ++ while (talitos_read(sc->sc_base_addr + TALITOS_MCR) & TALITOS_MCR_SWR) ++ cpu_relax(); ++ ++ return; ++} ++ ++/* ++ * Resets the device. Values in the registers are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++static void ++talitos_reset_device(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* ++ * Master reset ++ * errata documentation: warning: certain SEC interrupts ++ * are not fully cleared by writing the MCR:SWR bit, ++ * set bit twice to completely reset ++ */ ++ talitos_reset_device_master(sc); /* once */ ++ talitos_reset_device_master(sc); /* and once again */ ++ ++ /* reset all channels */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCCR); ++ talitos_write(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCCR, v | TALITOS_CH_CCCR_RESET); ++ } ++} ++ ++/* Set up the crypto device structure, private data, ++ * and anything else we need before we start */ ++#ifdef CONFIG_PPC_MERGE ++static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match) ++#else ++static int talitos_probe(struct platform_device *pdev) ++#endif ++{ ++ struct talitos_softc *sc = NULL; ++ struct resource *r; ++#ifdef CONFIG_PPC_MERGE ++ struct device *device = &ofdev->dev; ++ struct device_node *np = ofdev->node; ++ const unsigned int *prop; ++ int err; ++ struct resource res; ++#endif ++ static int num_chips = 0; ++ int rc; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ sc = (struct talitos_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return -ENOMEM; ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, DRV_NAME, num_chips, talitos_methods); ++ ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++#ifndef CONFIG_PPC_MERGE ++ sc->sc_dev = pdev; ++#endif ++ sc->sc_num = num_chips++; ++ ++#ifdef CONFIG_PPC_MERGE ++ dev_set_drvdata(device, sc); ++#else ++ platform_set_drvdata(sc->sc_dev, sc); ++#endif ++ ++ /* get the irq line */ ++#ifdef CONFIG_PPC_MERGE ++ err = of_address_to_resource(np, 0, &res); ++ if (err) ++ return -EINVAL; ++ r = &res; ++ ++ sc->sc_irq = irq_of_parse_and_map(np, 0); ++#else ++ /* get a pointer to the register memory */ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ sc->sc_irq = platform_get_irq(pdev, 0); ++#endif ++ rc = request_irq(sc->sc_irq, talitos_intr, 0, ++ device_get_nameunit(sc->sc_cdev), sc); ++ if (rc) { ++ printk(KERN_ERR "%s: failed to hook irq %d\n", ++ device_get_nameunit(sc->sc_cdev), sc->sc_irq); ++ sc->sc_irq = -1; ++ goto out; ++ } ++ ++ sc->sc_base_addr = (ocf_iomem_t) ioremap(r->start, (r->end - r->start)); ++ if (!sc->sc_base_addr) { ++ printk(KERN_ERR "%s: failed to ioremap\n", ++ device_get_nameunit(sc->sc_cdev)); ++ goto out; ++ } ++ ++ /* figure out our SEC's properties and capabilities */ ++ sc->sc_chiprev = (u64)talitos_read(sc->sc_base_addr + TALITOS_ID) << 32 ++ | talitos_read(sc->sc_base_addr + TALITOS_ID_HI); ++ DPRINTF("sec id 0x%llx\n", sc->sc_chiprev); ++ ++#ifdef CONFIG_PPC_MERGE ++ /* get SEC properties from device tree, defaulting to SEC 2.0 */ ++ ++ prop = of_get_property(np, "num-channels", NULL); ++ sc->sc_num_channels = prop ? *prop : TALITOS_NCHANNELS_SEC_2_0; ++ ++ prop = of_get_property(np, "channel-fifo-len", NULL); ++ sc->sc_chfifo_len = prop ? *prop : TALITOS_CHFIFOLEN_SEC_2_0; ++ ++ prop = of_get_property(np, "exec-units-mask", NULL); ++ sc->sc_exec_units = prop ? *prop : TALITOS_HAS_EUS_SEC_2_0; ++ ++ prop = of_get_property(np, "descriptor-types-mask", NULL); ++ sc->sc_desc_types = prop ? *prop : TALITOS_HAS_DESCTYPES_SEC_2_0; ++#else ++ /* bulk should go away with openfirmware flat device tree support */ ++ if (sc->sc_chiprev & TALITOS_ID_SEC_2_0) { ++ sc->sc_num_channels = TALITOS_NCHANNELS_SEC_2_0; ++ sc->sc_chfifo_len = TALITOS_CHFIFOLEN_SEC_2_0; ++ sc->sc_exec_units = TALITOS_HAS_EUS_SEC_2_0; ++ sc->sc_desc_types = TALITOS_HAS_DESCTYPES_SEC_2_0; ++ } else { ++ printk(KERN_ERR "%s: failed to id device\n", ++ device_get_nameunit(sc->sc_cdev)); ++ goto out; ++ } ++#endif ++ ++ /* + 1 is for the meta-channel lock used by the channel scheduler */ ++ sc->sc_chnfifolock = (spinlock_t *) kmalloc( ++ (sc->sc_num_channels + 1) * sizeof(spinlock_t), GFP_KERNEL); ++ if (!sc->sc_chnfifolock) ++ goto out; ++ for (i = 0; i < sc->sc_num_channels + 1; i++) { ++ spin_lock_init(&sc->sc_chnfifolock[i]); ++ } ++ ++ sc->sc_chnlastalg = (int *) kmalloc( ++ sc->sc_num_channels * sizeof(int), GFP_KERNEL); ++ if (!sc->sc_chnlastalg) ++ goto out; ++ memset(sc->sc_chnlastalg, 0, sc->sc_num_channels * sizeof(int)); ++ ++ sc->sc_chnfifo = (struct desc_cryptop_pair **) kmalloc( ++ sc->sc_num_channels * sizeof(struct desc_cryptop_pair *), ++ GFP_KERNEL); ++ if (!sc->sc_chnfifo) ++ goto out; ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ sc->sc_chnfifo[i] = (struct desc_cryptop_pair *) kmalloc( ++ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair), ++ GFP_KERNEL); ++ if (!sc->sc_chnfifo[i]) ++ goto out; ++ memset(sc->sc_chnfifo[i], 0, ++ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair)); ++ } ++ ++ /* reset and initialize the SEC h/w device */ ++ talitos_reset_device(sc); ++ talitos_init_device(sc); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ printk(KERN_ERR "%s: could not get crypto driver id\n", ++ device_get_nameunit(sc->sc_cdev)); ++ goto out; ++ } ++ ++ /* register algorithms with the framework */ ++ printk("%s:", device_get_nameunit(sc->sc_cdev)); ++ ++ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) { ++ printk(" rng"); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ talitos_rng_init(sc); ++ crypto_rregister(sc->sc_cid, talitos_read_random, sc); ++#endif ++ } ++ if (sc->sc_exec_units & TALITOS_HAS_EU_DEU) { ++ printk(" des/3des"); ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ } ++ if (sc->sc_exec_units & TALITOS_HAS_EU_AESU) { ++ printk(" aes"); ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ } ++ if (sc->sc_exec_units & TALITOS_HAS_EU_MDEU) { ++ printk(" md5"); ++ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); ++ /* HMAC support only with IPsec for now */ ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ printk(" sha1"); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); ++ /* HMAC support only with IPsec for now */ ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ } ++ printk("\n"); ++ return 0; ++ ++out: ++#ifndef CONFIG_PPC_MERGE ++ talitos_remove(pdev); ++#endif ++ return -ENOMEM; ++} ++ ++#ifdef CONFIG_PPC_MERGE ++static int talitos_remove(struct of_device *ofdev) ++#else ++static int talitos_remove(struct platform_device *pdev) ++#endif ++{ ++#ifdef CONFIG_PPC_MERGE ++ struct talitos_softc *sc = dev_get_drvdata(&ofdev->dev); ++#else ++ struct talitos_softc *sc = platform_get_drvdata(pdev); ++#endif ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_chnfifo) { ++ for (i = 0; i < sc->sc_num_channels; i++) ++ if (sc->sc_chnfifo[i]) ++ kfree(sc->sc_chnfifo[i]); ++ kfree(sc->sc_chnfifo); ++ } ++ if (sc->sc_chnlastalg) ++ kfree(sc->sc_chnlastalg); ++ if (sc->sc_chnfifolock) ++ kfree(sc->sc_chnfifolock); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_base_addr) ++ iounmap((void *) sc->sc_base_addr); ++ kfree(sc); ++ return 0; ++} ++ ++#ifdef CONFIG_PPC_MERGE ++static struct of_device_id talitos_match[] = { ++ { ++ .type = "crypto", ++ .compatible = "talitos", ++ }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, talitos_match); ++ ++static struct of_platform_driver talitos_driver = { ++ .name = DRV_NAME, ++ .match_table = talitos_match, ++ .probe = talitos_probe, ++ .remove = talitos_remove, ++}; ++ ++static int __init talitos_init(void) ++{ ++ return of_register_platform_driver(&talitos_driver); ++} ++ ++static void __exit talitos_exit(void) ++{ ++ of_unregister_platform_driver(&talitos_driver); ++} ++#else ++/* Structure for a platform device driver */ ++static struct platform_driver talitos_driver = { ++ .probe = talitos_probe, ++ .remove = talitos_remove, ++ .driver = { ++ .name = "fsl-sec2", ++ } ++}; ++ ++static int __init talitos_init(void) ++{ ++ return platform_driver_register(&talitos_driver); ++} ++ ++static void __exit talitos_exit(void) ++{ ++ platform_driver_unregister(&talitos_driver); ++} ++#endif ++ ++module_init(talitos_init); ++module_exit(talitos_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("kim.phillips@freescale.com"); ++MODULE_DESCRIPTION("OCF driver for Freescale SEC (talitos)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/talitos_dev.h linux-3.0.4/crypto/ocf/talitos/talitos_dev.h +--- linux-3.0.4.orig/crypto/ocf/talitos/talitos_dev.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/talitos/talitos_dev.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,277 @@ ++/* ++ * Freescale SEC (talitos) device dependent data structures ++ * ++ * Copyright (c) 2006 Freescale Semiconductor, Inc. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ */ ++ ++/* device ID register values */ ++#define TALITOS_ID_SEC_2_0 0x40 ++#define TALITOS_ID_SEC_2_1 0x40 /* cross ref with IP block revision reg */ ++ ++/* ++ * following num_channels, channel-fifo-depth, exec-unit-mask, and ++ * descriptor-types-mask are for forward-compatibility with openfirmware ++ * flat device trees ++ */ ++ ++/* ++ * num_channels : the number of channels available in each SEC version. ++ */ ++ ++/* n.b. this driver requires these values be a power of 2 */ ++#define TALITOS_NCHANNELS_SEC_1_0 4 ++#define TALITOS_NCHANNELS_SEC_1_2 1 ++#define TALITOS_NCHANNELS_SEC_2_0 4 ++#define TALITOS_NCHANNELS_SEC_2_01 4 ++#define TALITOS_NCHANNELS_SEC_2_1 4 ++#define TALITOS_NCHANNELS_SEC_2_4 4 ++ ++/* ++ * channel-fifo-depth : The number of descriptor ++ * pointers a channel fetch fifo can hold. ++ */ ++#define TALITOS_CHFIFOLEN_SEC_1_0 1 ++#define TALITOS_CHFIFOLEN_SEC_1_2 1 ++#define TALITOS_CHFIFOLEN_SEC_2_0 24 ++#define TALITOS_CHFIFOLEN_SEC_2_01 24 ++#define TALITOS_CHFIFOLEN_SEC_2_1 24 ++#define TALITOS_CHFIFOLEN_SEC_2_4 24 ++ ++/* ++ * exec-unit-mask : The bitmask representing what Execution Units (EUs) ++ * are available. EU information should be encoded following the SEC's ++ * EU_SEL0 bitfield documentation, i.e. as follows: ++ * ++ * bit 31 = set if SEC permits no-EU selection (should be always set) ++ * bit 30 = set if SEC has the ARC4 EU (AFEU) ++ * bit 29 = set if SEC has the des/3des EU (DEU) ++ * bit 28 = set if SEC has the message digest EU (MDEU) ++ * bit 27 = set if SEC has the random number generator EU (RNG) ++ * bit 26 = set if SEC has the public key EU (PKEU) ++ * bit 25 = set if SEC has the aes EU (AESU) ++ * bit 24 = set if SEC has the Kasumi EU (KEU) ++ * ++ */ ++#define TALITOS_HAS_EU_NONE (1<<0) ++#define TALITOS_HAS_EU_AFEU (1<<1) ++#define TALITOS_HAS_EU_DEU (1<<2) ++#define TALITOS_HAS_EU_MDEU (1<<3) ++#define TALITOS_HAS_EU_RNG (1<<4) ++#define TALITOS_HAS_EU_PKEU (1<<5) ++#define TALITOS_HAS_EU_AESU (1<<6) ++#define TALITOS_HAS_EU_KEU (1<<7) ++ ++/* the corresponding masks for each SEC version */ ++#define TALITOS_HAS_EUS_SEC_1_0 0x7f ++#define TALITOS_HAS_EUS_SEC_1_2 0x4d ++#define TALITOS_HAS_EUS_SEC_2_0 0x7f ++#define TALITOS_HAS_EUS_SEC_2_01 0x7f ++#define TALITOS_HAS_EUS_SEC_2_1 0xff ++#define TALITOS_HAS_EUS_SEC_2_4 0x7f ++ ++/* ++ * descriptor-types-mask : The bitmask representing what descriptors ++ * are available. Descriptor type information should be encoded ++ * following the SEC's Descriptor Header Dword DESC_TYPE field ++ * documentation, i.e. as follows: ++ * ++ * bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type ++ * bit 1 = set if SEC supports the ipsec_esp descriptor type ++ * bit 2 = set if SEC supports the common_nonsnoop desc. type ++ * bit 3 = set if SEC supports the 802.11i AES ccmp desc. type ++ * bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type ++ * bit 5 = set if SEC supports the srtp descriptor type ++ * bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type ++ * bit 7 = set if SEC supports the pkeu_assemble descriptor type ++ * bit 8 = set if SEC supports the aesu_key_expand_output desc.type ++ * bit 9 = set if SEC supports the pkeu_ptmul descriptor type ++ * bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type ++ * bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type ++ * ++ * ..and so on and so forth. ++ */ ++#define TALITOS_HAS_DT_AESU_CTR_NONSNOOP (1<<0) ++#define TALITOS_HAS_DT_IPSEC_ESP (1<<1) ++#define TALITOS_HAS_DT_COMMON_NONSNOOP (1<<2) ++ ++/* the corresponding masks for each SEC version */ ++#define TALITOS_HAS_DESCTYPES_SEC_2_0 0x01010ebf ++#define TALITOS_HAS_DESCTYPES_SEC_2_1 0x012b0ebf ++ ++/* ++ * a TALITOS_xxx_HI address points to the low data bits (32-63) of the register ++ */ ++ ++/* global register offset addresses */ ++#define TALITOS_ID 0x1020 ++#define TALITOS_ID_HI 0x1024 ++#define TALITOS_MCR 0x1030 /* master control register */ ++#define TALITOS_MCR_HI 0x1038 /* master control register */ ++#define TALITOS_MCR_SWR 0x1 ++#define TALITOS_IMR 0x1008 /* interrupt mask register */ ++#define TALITOS_IMR_ALL 0x00010fff /* enable all interrupts mask */ ++#define TALITOS_IMR_ERRONLY 0x00010aaa /* enable error interrupts */ ++#define TALITOS_IMR_HI 0x100C /* interrupt mask register */ ++#define TALITOS_IMR_HI_ALL 0x00323333 /* enable all interrupts mask */ ++#define TALITOS_IMR_HI_ERRONLY 0x00222222 /* enable error interrupts */ ++#define TALITOS_ISR 0x1010 /* interrupt status register */ ++#define TALITOS_ISR_ERROR 0x00010faa /* errors mask */ ++#define TALITOS_ISR_DONE 0x00000055 /* channel(s) done mask */ ++#define TALITOS_ISR_HI 0x1014 /* interrupt status register */ ++#define TALITOS_ICR 0x1018 /* interrupt clear register */ ++#define TALITOS_ICR_HI 0x101C /* interrupt clear register */ ++ ++/* channel register address stride */ ++#define TALITOS_CH_OFFSET 0x100 ++ ++/* channel register offset addresses and bits */ ++#define TALITOS_CH_CCCR 0x1108 /* Crypto-Channel Config Register */ ++#define TALITOS_CH_CCCR_RESET 0x1 /* Channel Reset bit */ ++#define TALITOS_CH_CCCR_HI 0x110c /* Crypto-Channel Config Register */ ++#define TALITOS_CH_CCCR_HI_CDWE 0x10 /* Channel done writeback enable bit */ ++#define TALITOS_CH_CCCR_HI_NT 0x4 /* Notification type bit */ ++#define TALITOS_CH_CCCR_HI_CDIE 0x2 /* Channel Done Interrupt Enable bit */ ++#define TALITOS_CH_CCPSR 0x1110 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_CCPSR_HI 0x1114 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_FF 0x1148 /* Fetch FIFO */ ++#define TALITOS_CH_FF_HI 0x114c /* Fetch FIFO's FETCH_ADRS */ ++#define TALITOS_CH_CDPR 0x1140 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_CDPR_HI 0x1144 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_DESCBUF 0x1180 /* (thru 11bf) Crypto-Channel ++ * Descriptor Buffer (debug) */ ++ ++/* execution unit register offset addresses and bits */ ++#define TALITOS_DEUSR 0x2028 /* DEU status register */ ++#define TALITOS_DEUSR_HI 0x202c /* DEU status register */ ++#define TALITOS_DEUISR 0x2030 /* DEU interrupt status register */ ++#define TALITOS_DEUISR_HI 0x2034 /* DEU interrupt status register */ ++#define TALITOS_DEUICR 0x2038 /* DEU interrupt control register */ ++#define TALITOS_DEUICR_HI 0x203c /* DEU interrupt control register */ ++#define TALITOS_AESUISR 0x4030 /* AESU interrupt status register */ ++#define TALITOS_AESUISR_HI 0x4034 /* AESU interrupt status register */ ++#define TALITOS_AESUICR 0x4038 /* AESU interrupt control register */ ++#define TALITOS_AESUICR_HI 0x403c /* AESU interrupt control register */ ++#define TALITOS_MDEUISR 0x6030 /* MDEU interrupt status register */ ++#define TALITOS_MDEUISR_HI 0x6034 /* MDEU interrupt status register */ ++#define TALITOS_RNGSR 0xa028 /* RNG status register */ ++#define TALITOS_RNGSR_HI 0xa02c /* RNG status register */ ++#define TALITOS_RNGSR_HI_RD 0x1 /* RNG Reset done */ ++#define TALITOS_RNGSR_HI_OFL 0xff0000/* number of dwords in RNG output FIFO*/ ++#define TALITOS_RNGDSR 0xa010 /* RNG data size register */ ++#define TALITOS_RNGDSR_HI 0xa014 /* RNG data size register */ ++#define TALITOS_RNG_FIFO 0xa800 /* RNG FIFO - pool of random numbers */ ++#define TALITOS_RNGISR 0xa030 /* RNG Interrupt status register */ ++#define TALITOS_RNGISR_HI 0xa034 /* RNG Interrupt status register */ ++#define TALITOS_RNGRCR 0xa018 /* RNG Reset control register */ ++#define TALITOS_RNGRCR_HI 0xa01c /* RNG Reset control register */ ++#define TALITOS_RNGRCR_HI_SR 0x1 /* RNG RNGRCR:Software Reset */ ++ ++/* descriptor pointer entry */ ++struct talitos_desc_ptr { ++ u16 len; /* length */ ++ u8 extent; /* jump (to s/g link table) and extent */ ++ u8 res; /* reserved */ ++ u32 ptr; /* pointer */ ++}; ++ ++/* descriptor */ ++struct talitos_desc { ++ u32 hdr; /* header */ ++ u32 res; /* reserved */ ++ struct talitos_desc_ptr ptr[7]; /* ptr/len pair array */ ++}; ++ ++/* talitos descriptor header (hdr) bits */ ++ ++/* primary execution unit select */ ++#define TALITOS_SEL0_AFEU 0x10000000 ++#define TALITOS_SEL0_DEU 0x20000000 ++#define TALITOS_SEL0_MDEU 0x30000000 ++#define TALITOS_SEL0_RNG 0x40000000 ++#define TALITOS_SEL0_PKEU 0x50000000 ++#define TALITOS_SEL0_AESU 0x60000000 ++ ++/* primary execution unit mode (MODE0) and derivatives */ ++#define TALITOS_MODE0_AESU_CBC 0x00200000 ++#define TALITOS_MODE0_AESU_ENC 0x00100000 ++#define TALITOS_MODE0_DEU_CBC 0x00400000 ++#define TALITOS_MODE0_DEU_3DES 0x00200000 ++#define TALITOS_MODE0_DEU_ENC 0x00100000 ++#define TALITOS_MODE0_MDEU_INIT 0x01000000 /* init starting regs */ ++#define TALITOS_MODE0_MDEU_HMAC 0x00800000 ++#define TALITOS_MODE0_MDEU_PAD 0x00400000 /* PD */ ++#define TALITOS_MODE0_MDEU_MD5 0x00200000 ++#define TALITOS_MODE0_MDEU_SHA256 0x00100000 ++#define TALITOS_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */ ++#define TALITOS_MODE0_MDEU_MD5_HMAC \ ++ (TALITOS_MODE0_MDEU_MD5 | TALITOS_MODE0_MDEU_HMAC) ++#define TALITOS_MODE0_MDEU_SHA256_HMAC \ ++ (TALITOS_MODE0_MDEU_SHA256 | TALITOS_MODE0_MDEU_HMAC) ++#define TALITOS_MODE0_MDEU_SHA1_HMAC \ ++ (TALITOS_MODE0_MDEU_SHA1 | TALITOS_MODE0_MDEU_HMAC) ++ ++/* secondary execution unit select (SEL1) */ ++/* it's MDEU or nothing */ ++#define TALITOS_SEL1_MDEU 0x00030000 ++ ++/* secondary execution unit mode (MODE1) and derivatives */ ++#define TALITOS_MODE1_MDEU_INIT 0x00001000 /* init starting regs */ ++#define TALITOS_MODE1_MDEU_HMAC 0x00000800 ++#define TALITOS_MODE1_MDEU_PAD 0x00000400 /* PD */ ++#define TALITOS_MODE1_MDEU_MD5 0x00000200 ++#define TALITOS_MODE1_MDEU_SHA256 0x00000100 ++#define TALITOS_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */ ++#define TALITOS_MODE1_MDEU_MD5_HMAC \ ++ (TALITOS_MODE1_MDEU_MD5 | TALITOS_MODE1_MDEU_HMAC) ++#define TALITOS_MODE1_MDEU_SHA256_HMAC \ ++ (TALITOS_MODE1_MDEU_SHA256 | TALITOS_MODE1_MDEU_HMAC) ++#define TALITOS_MODE1_MDEU_SHA1_HMAC \ ++ (TALITOS_MODE1_MDEU_SHA1 | TALITOS_MODE1_MDEU_HMAC) ++ ++/* direction of overall data flow (DIR) */ ++#define TALITOS_DIR_OUTBOUND 0x00000000 ++#define TALITOS_DIR_INBOUND 0x00000002 ++ ++/* done notification (DN) */ ++#define TALITOS_DONE_NOTIFY 0x00000001 ++ ++/* descriptor types */ ++/* odd numbers here are valid on SEC2 and greater only (e.g. ipsec_esp) */ ++#define TD_TYPE_AESU_CTR_NONSNOOP (0 << 3) ++#define TD_TYPE_IPSEC_ESP (1 << 3) ++#define TD_TYPE_COMMON_NONSNOOP_NO_AFEU (2 << 3) ++#define TD_TYPE_HMAC_SNOOP_NO_AFEU (4 << 3) ++ ++#define TALITOS_HDR_DONE_BITS 0xff000000 ++ ++#define DPRINTF(a...) do { \ ++ if (debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_cdev) : "talitos"); \ ++ printk(a); \ ++ } \ ++ } while (0) +diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/talitos_soft.h linux-3.0.4/crypto/ocf/talitos/talitos_soft.h +--- linux-3.0.4.orig/crypto/ocf/talitos/talitos_soft.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/talitos/talitos_soft.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,76 @@ ++/* ++ * Freescale SEC data structures for integration with ocf-linux ++ * ++ * Copyright (c) 2006 Freescale Semiconductor, Inc. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/* ++ * paired descriptor and associated crypto operation ++ */ ++struct desc_cryptop_pair { ++ struct talitos_desc cf_desc; /* descriptor ptr */ ++ struct cryptop *cf_crp; /* cryptop ptr */ ++}; ++ ++/* ++ * Holds data specific to a single talitos device. ++ */ ++struct talitos_softc { ++ softc_device_decl sc_cdev; ++ struct platform_device *sc_dev; /* device backpointer */ ++ ocf_iomem_t sc_base_addr; ++ int sc_irq; ++ int sc_num; /* if we have multiple chips */ ++ int32_t sc_cid; /* crypto tag */ ++ u64 sc_chiprev; /* major/minor chip revision */ ++ int sc_nsessions; ++ struct talitos_session *sc_sessions; ++ int sc_num_channels;/* number of crypto channels */ ++ int sc_chfifo_len; /* channel fetch fifo len */ ++ int sc_exec_units; /* execution units mask */ ++ int sc_desc_types; /* descriptor types mask */ ++ /* ++ * mutual exclusion for intra-channel resources, e.g. fetch fifos ++ * the last entry is a meta-channel lock used by the channel scheduler ++ */ ++ spinlock_t *sc_chnfifolock; ++ /* sc_chnlastalgo contains last algorithm for that channel */ ++ int *sc_chnlastalg; ++ /* sc_chnfifo holds pending descriptor--crypto operation pairs */ ++ struct desc_cryptop_pair **sc_chnfifo; ++}; ++ ++struct talitos_session { ++ u_int32_t ses_used; ++ u_int32_t ses_klen; /* key length in bits */ ++ u_int32_t ses_key[8]; /* DES/3DES/AES key */ ++ u_int32_t ses_hmac[5]; /* hmac inner state */ ++ u_int32_t ses_hmac_len; /* hmac length */ ++ u_int32_t ses_mlen; /* desired hash result len (12=ipsec or 16) */ ++}; ++ ++#define TALITOS_SESSION(sid) ((sid) & 0x0fffffff) ++#define TALITOS_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) +diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/Makefile linux-3.0.4/crypto/ocf/ubsec_ssb/Makefile +--- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ubsec_ssb/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_UBSEC_SSB) += ubsec_ssb.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/bsdqueue.h linux-3.0.4/crypto/ocf/ubsec_ssb/bsdqueue.h +--- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/bsdqueue.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ubsec_ssb/bsdqueue.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,527 @@ ++/* $OpenBSD: queue.h,v 1.32 2007/04/30 18:42:34 pedro Exp $ */ ++/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */ ++ ++/* ++ * Copyright (c) 1991, 1993 ++ * The Regents of the University of California. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the University nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++ * @(#)queue.h 8.5 (Berkeley) 8/20/94 ++ */ ++ ++#ifndef _BSD_SYS_QUEUE_H_ ++#define _BSD_SYS_QUEUE_H_ ++ ++/* ++ * This file defines five types of data structures: singly-linked lists, ++ * lists, simple queues, tail queues, and circular queues. ++ * ++ * ++ * A singly-linked list is headed by a single forward pointer. The elements ++ * are singly linked for minimum space and pointer manipulation overhead at ++ * the expense of O(n) removal for arbitrary elements. New elements can be ++ * added to the list after an existing element or at the head of the list. ++ * Elements being removed from the head of the list should use the explicit ++ * macro for this purpose for optimum efficiency. A singly-linked list may ++ * only be traversed in the forward direction. Singly-linked lists are ideal ++ * for applications with large datasets and few or no removals or for ++ * implementing a LIFO queue. ++ * ++ * A list is headed by a single forward pointer (or an array of forward ++ * pointers for a hash table header). The elements are doubly linked ++ * so that an arbitrary element can be removed without a need to ++ * traverse the list. New elements can be added to the list before ++ * or after an existing element or at the head of the list. A list ++ * may only be traversed in the forward direction. ++ * ++ * A simple queue is headed by a pair of pointers, one the head of the ++ * list and the other to the tail of the list. The elements are singly ++ * linked to save space, so elements can only be removed from the ++ * head of the list. New elements can be added to the list before or after ++ * an existing element, at the head of the list, or at the end of the ++ * list. A simple queue may only be traversed in the forward direction. ++ * ++ * A tail queue is headed by a pair of pointers, one to the head of the ++ * list and the other to the tail of the list. The elements are doubly ++ * linked so that an arbitrary element can be removed without a need to ++ * traverse the list. New elements can be added to the list before or ++ * after an existing element, at the head of the list, or at the end of ++ * the list. A tail queue may be traversed in either direction. ++ * ++ * A circle queue is headed by a pair of pointers, one to the head of the ++ * list and the other to the tail of the list. The elements are doubly ++ * linked so that an arbitrary element can be removed without a need to ++ * traverse the list. New elements can be added to the list before or after ++ * an existing element, at the head of the list, or at the end of the list. ++ * A circle queue may be traversed in either direction, but has a more ++ * complex end of list detection. ++ * ++ * For details on the use of these macros, see the queue(3) manual page. ++ */ ++ ++#if defined(QUEUE_MACRO_DEBUG) || (defined(_KERNEL) && defined(DIAGNOSTIC)) ++#define _Q_INVALIDATE(a) (a) = ((void *)-1) ++#else ++#define _Q_INVALIDATE(a) ++#endif ++ ++/* ++ * Singly-linked List definitions. ++ */ ++#define BSD_SLIST_HEAD(name, type) \ ++struct name { \ ++ struct type *slh_first; /* first element */ \ ++} ++ ++#define BSD_SLIST_HEAD_INITIALIZER(head) \ ++ { NULL } ++ ++#define BSD_SLIST_ENTRY(type) \ ++struct { \ ++ struct type *sle_next; /* next element */ \ ++} ++ ++/* ++ * Singly-linked List access methods. ++ */ ++#define BSD_SLIST_FIRST(head) ((head)->slh_first) ++#define BSD_SLIST_END(head) NULL ++#define BSD_SLIST_EMPTY(head) (BSD_SLIST_FIRST(head) == BSD_SLIST_END(head)) ++#define BSD_SLIST_NEXT(elm, field) ((elm)->field.sle_next) ++ ++#define BSD_SLIST_FOREACH(var, head, field) \ ++ for((var) = BSD_SLIST_FIRST(head); \ ++ (var) != BSD_SLIST_END(head); \ ++ (var) = BSD_SLIST_NEXT(var, field)) ++ ++#define BSD_SLIST_FOREACH_PREVPTR(var, varp, head, field) \ ++ for ((varp) = &BSD_SLIST_FIRST((head)); \ ++ ((var) = *(varp)) != BSD_SLIST_END(head); \ ++ (varp) = &BSD_SLIST_NEXT((var), field)) ++ ++/* ++ * Singly-linked List functions. ++ */ ++#define BSD_SLIST_INIT(head) { \ ++ BSD_SLIST_FIRST(head) = BSD_SLIST_END(head); \ ++} ++ ++#define BSD_SLIST_INSERT_AFTER(slistelm, elm, field) do { \ ++ (elm)->field.sle_next = (slistelm)->field.sle_next; \ ++ (slistelm)->field.sle_next = (elm); \ ++} while (0) ++ ++#define BSD_SLIST_INSERT_HEAD(head, elm, field) do { \ ++ (elm)->field.sle_next = (head)->slh_first; \ ++ (head)->slh_first = (elm); \ ++} while (0) ++ ++#define BSD_SLIST_REMOVE_NEXT(head, elm, field) do { \ ++ (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \ ++} while (0) ++ ++#define BSD_SLIST_REMOVE_HEAD(head, field) do { \ ++ (head)->slh_first = (head)->slh_first->field.sle_next; \ ++} while (0) ++ ++#define BSD_SLIST_REMOVE(head, elm, type, field) do { \ ++ if ((head)->slh_first == (elm)) { \ ++ BSD_SLIST_REMOVE_HEAD((head), field); \ ++ } else { \ ++ struct type *curelm = (head)->slh_first; \ ++ \ ++ while (curelm->field.sle_next != (elm)) \ ++ curelm = curelm->field.sle_next; \ ++ curelm->field.sle_next = \ ++ curelm->field.sle_next->field.sle_next; \ ++ _Q_INVALIDATE((elm)->field.sle_next); \ ++ } \ ++} while (0) ++ ++/* ++ * List definitions. ++ */ ++#define BSD_LIST_HEAD(name, type) \ ++struct name { \ ++ struct type *lh_first; /* first element */ \ ++} ++ ++#define BSD_LIST_HEAD_INITIALIZER(head) \ ++ { NULL } ++ ++#define BSD_LIST_ENTRY(type) \ ++struct { \ ++ struct type *le_next; /* next element */ \ ++ struct type **le_prev; /* address of previous next element */ \ ++} ++ ++/* ++ * List access methods ++ */ ++#define BSD_LIST_FIRST(head) ((head)->lh_first) ++#define BSD_LIST_END(head) NULL ++#define BSD_LIST_EMPTY(head) (BSD_LIST_FIRST(head) == BSD_LIST_END(head)) ++#define BSD_LIST_NEXT(elm, field) ((elm)->field.le_next) ++ ++#define BSD_LIST_FOREACH(var, head, field) \ ++ for((var) = BSD_LIST_FIRST(head); \ ++ (var)!= BSD_LIST_END(head); \ ++ (var) = BSD_LIST_NEXT(var, field)) ++ ++/* ++ * List functions. ++ */ ++#define BSD_LIST_INIT(head) do { \ ++ BSD_LIST_FIRST(head) = BSD_LIST_END(head); \ ++} while (0) ++ ++#define BSD_LIST_INSERT_AFTER(listelm, elm, field) do { \ ++ if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ ++ (listelm)->field.le_next->field.le_prev = \ ++ &(elm)->field.le_next; \ ++ (listelm)->field.le_next = (elm); \ ++ (elm)->field.le_prev = &(listelm)->field.le_next; \ ++} while (0) ++ ++#define BSD_LIST_INSERT_BEFORE(listelm, elm, field) do { \ ++ (elm)->field.le_prev = (listelm)->field.le_prev; \ ++ (elm)->field.le_next = (listelm); \ ++ *(listelm)->field.le_prev = (elm); \ ++ (listelm)->field.le_prev = &(elm)->field.le_next; \ ++} while (0) ++ ++#define BSD_LIST_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.le_next = (head)->lh_first) != NULL) \ ++ (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ ++ (head)->lh_first = (elm); \ ++ (elm)->field.le_prev = &(head)->lh_first; \ ++} while (0) ++ ++#define BSD_LIST_REMOVE(elm, field) do { \ ++ if ((elm)->field.le_next != NULL) \ ++ (elm)->field.le_next->field.le_prev = \ ++ (elm)->field.le_prev; \ ++ *(elm)->field.le_prev = (elm)->field.le_next; \ ++ _Q_INVALIDATE((elm)->field.le_prev); \ ++ _Q_INVALIDATE((elm)->field.le_next); \ ++} while (0) ++ ++#define BSD_LIST_REPLACE(elm, elm2, field) do { \ ++ if (((elm2)->field.le_next = (elm)->field.le_next) != NULL) \ ++ (elm2)->field.le_next->field.le_prev = \ ++ &(elm2)->field.le_next; \ ++ (elm2)->field.le_prev = (elm)->field.le_prev; \ ++ *(elm2)->field.le_prev = (elm2); \ ++ _Q_INVALIDATE((elm)->field.le_prev); \ ++ _Q_INVALIDATE((elm)->field.le_next); \ ++} while (0) ++ ++/* ++ * Simple queue definitions. ++ */ ++#define BSD_SIMPLEQ_HEAD(name, type) \ ++struct name { \ ++ struct type *sqh_first; /* first element */ \ ++ struct type **sqh_last; /* addr of last next element */ \ ++} ++ ++#define BSD_SIMPLEQ_HEAD_INITIALIZER(head) \ ++ { NULL, &(head).sqh_first } ++ ++#define BSD_SIMPLEQ_ENTRY(type) \ ++struct { \ ++ struct type *sqe_next; /* next element */ \ ++} ++ ++/* ++ * Simple queue access methods. ++ */ ++#define BSD_SIMPLEQ_FIRST(head) ((head)->sqh_first) ++#define BSD_SIMPLEQ_END(head) NULL ++#define BSD_SIMPLEQ_EMPTY(head) (BSD_SIMPLEQ_FIRST(head) == BSD_SIMPLEQ_END(head)) ++#define BSD_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) ++ ++#define BSD_SIMPLEQ_FOREACH(var, head, field) \ ++ for((var) = BSD_SIMPLEQ_FIRST(head); \ ++ (var) != BSD_SIMPLEQ_END(head); \ ++ (var) = BSD_SIMPLEQ_NEXT(var, field)) ++ ++/* ++ * Simple queue functions. ++ */ ++#define BSD_SIMPLEQ_INIT(head) do { \ ++ (head)->sqh_first = NULL; \ ++ (head)->sqh_last = &(head)->sqh_first; \ ++} while (0) ++ ++#define BSD_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++ (head)->sqh_first = (elm); \ ++} while (0) ++ ++#define BSD_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.sqe_next = NULL; \ ++ *(head)->sqh_last = (elm); \ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++} while (0) ++ ++#define BSD_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++ (listelm)->field.sqe_next = (elm); \ ++} while (0) ++ ++#define BSD_SIMPLEQ_REMOVE_HEAD(head, field) do { \ ++ if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ ++ (head)->sqh_last = &(head)->sqh_first; \ ++} while (0) ++ ++/* ++ * Tail queue definitions. ++ */ ++#define BSD_TAILQ_HEAD(name, type) \ ++struct name { \ ++ struct type *tqh_first; /* first element */ \ ++ struct type **tqh_last; /* addr of last next element */ \ ++} ++ ++#define BSD_TAILQ_HEAD_INITIALIZER(head) \ ++ { NULL, &(head).tqh_first } ++ ++#define BSD_TAILQ_ENTRY(type) \ ++struct { \ ++ struct type *tqe_next; /* next element */ \ ++ struct type **tqe_prev; /* address of previous next element */ \ ++} ++ ++/* ++ * tail queue access methods ++ */ ++#define BSD_TAILQ_FIRST(head) ((head)->tqh_first) ++#define BSD_TAILQ_END(head) NULL ++#define BSD_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) ++#define BSD_TAILQ_LAST(head, headname) \ ++ (*(((struct headname *)((head)->tqh_last))->tqh_last)) ++/* XXX */ ++#define BSD_TAILQ_PREV(elm, headname, field) \ ++ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) ++#define BSD_TAILQ_EMPTY(head) \ ++ (BSD_TAILQ_FIRST(head) == BSD_TAILQ_END(head)) ++ ++#define BSD_TAILQ_FOREACH(var, head, field) \ ++ for((var) = BSD_TAILQ_FIRST(head); \ ++ (var) != BSD_TAILQ_END(head); \ ++ (var) = BSD_TAILQ_NEXT(var, field)) ++ ++#define BSD_TAILQ_FOREACH_REVERSE(var, head, headname, field) \ ++ for((var) = BSD_TAILQ_LAST(head, headname); \ ++ (var) != BSD_TAILQ_END(head); \ ++ (var) = BSD_TAILQ_PREV(var, headname, field)) ++ ++/* ++ * Tail queue functions. ++ */ ++#define BSD_TAILQ_INIT(head) do { \ ++ (head)->tqh_first = NULL; \ ++ (head)->tqh_last = &(head)->tqh_first; \ ++} while (0) ++ ++#define BSD_TAILQ_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ ++ (head)->tqh_first->field.tqe_prev = \ ++ &(elm)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++ (head)->tqh_first = (elm); \ ++ (elm)->field.tqe_prev = &(head)->tqh_first; \ ++} while (0) ++ ++#define BSD_TAILQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.tqe_next = NULL; \ ++ (elm)->field.tqe_prev = (head)->tqh_last; \ ++ *(head)->tqh_last = (elm); \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++} while (0) ++ ++#define BSD_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ ++ (elm)->field.tqe_next->field.tqe_prev = \ ++ &(elm)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++ (listelm)->field.tqe_next = (elm); \ ++ (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ ++} while (0) ++ ++#define BSD_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ ++ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ ++ (elm)->field.tqe_next = (listelm); \ ++ *(listelm)->field.tqe_prev = (elm); \ ++ (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ ++} while (0) ++ ++#define BSD_TAILQ_REMOVE(head, elm, field) do { \ ++ if (((elm)->field.tqe_next) != NULL) \ ++ (elm)->field.tqe_next->field.tqe_prev = \ ++ (elm)->field.tqe_prev; \ ++ else \ ++ (head)->tqh_last = (elm)->field.tqe_prev; \ ++ *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ ++ _Q_INVALIDATE((elm)->field.tqe_prev); \ ++ _Q_INVALIDATE((elm)->field.tqe_next); \ ++} while (0) ++ ++#define BSD_TAILQ_REPLACE(head, elm, elm2, field) do { \ ++ if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \ ++ (elm2)->field.tqe_next->field.tqe_prev = \ ++ &(elm2)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm2)->field.tqe_next; \ ++ (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \ ++ *(elm2)->field.tqe_prev = (elm2); \ ++ _Q_INVALIDATE((elm)->field.tqe_prev); \ ++ _Q_INVALIDATE((elm)->field.tqe_next); \ ++} while (0) ++ ++/* ++ * Circular queue definitions. ++ */ ++#define BSD_CIRCLEQ_HEAD(name, type) \ ++struct name { \ ++ struct type *cqh_first; /* first element */ \ ++ struct type *cqh_last; /* last element */ \ ++} ++ ++#define BSD_CIRCLEQ_HEAD_INITIALIZER(head) \ ++ { BSD_CIRCLEQ_END(&head), BSD_CIRCLEQ_END(&head) } ++ ++#define BSD_CIRCLEQ_ENTRY(type) \ ++struct { \ ++ struct type *cqe_next; /* next element */ \ ++ struct type *cqe_prev; /* previous element */ \ ++} ++ ++/* ++ * Circular queue access methods ++ */ ++#define BSD_CIRCLEQ_FIRST(head) ((head)->cqh_first) ++#define BSD_CIRCLEQ_LAST(head) ((head)->cqh_last) ++#define BSD_CIRCLEQ_END(head) ((void *)(head)) ++#define BSD_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next) ++#define BSD_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev) ++#define BSD_CIRCLEQ_EMPTY(head) \ ++ (BSD_CIRCLEQ_FIRST(head) == BSD_CIRCLEQ_END(head)) ++ ++#define BSD_CIRCLEQ_FOREACH(var, head, field) \ ++ for((var) = BSD_CIRCLEQ_FIRST(head); \ ++ (var) != BSD_CIRCLEQ_END(head); \ ++ (var) = BSD_CIRCLEQ_NEXT(var, field)) ++ ++#define BSD_CIRCLEQ_FOREACH_REVERSE(var, head, field) \ ++ for((var) = BSD_CIRCLEQ_LAST(head); \ ++ (var) != BSD_CIRCLEQ_END(head); \ ++ (var) = BSD_CIRCLEQ_PREV(var, field)) ++ ++/* ++ * Circular queue functions. ++ */ ++#define BSD_CIRCLEQ_INIT(head) do { \ ++ (head)->cqh_first = BSD_CIRCLEQ_END(head); \ ++ (head)->cqh_last = BSD_CIRCLEQ_END(head); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ (elm)->field.cqe_next = (listelm)->field.cqe_next; \ ++ (elm)->field.cqe_prev = (listelm); \ ++ if ((listelm)->field.cqe_next == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm); \ ++ else \ ++ (listelm)->field.cqe_next->field.cqe_prev = (elm); \ ++ (listelm)->field.cqe_next = (elm); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ ++ (elm)->field.cqe_next = (listelm); \ ++ (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ ++ if ((listelm)->field.cqe_prev == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm); \ ++ else \ ++ (listelm)->field.cqe_prev->field.cqe_next = (elm); \ ++ (listelm)->field.cqe_prev = (elm); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ ++ (elm)->field.cqe_next = (head)->cqh_first; \ ++ (elm)->field.cqe_prev = BSD_CIRCLEQ_END(head); \ ++ if ((head)->cqh_last == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm); \ ++ else \ ++ (head)->cqh_first->field.cqe_prev = (elm); \ ++ (head)->cqh_first = (elm); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.cqe_next = BSD_CIRCLEQ_END(head); \ ++ (elm)->field.cqe_prev = (head)->cqh_last; \ ++ if ((head)->cqh_first == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm); \ ++ else \ ++ (head)->cqh_last->field.cqe_next = (elm); \ ++ (head)->cqh_last = (elm); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_REMOVE(head, elm, field) do { \ ++ if ((elm)->field.cqe_next == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm)->field.cqe_prev; \ ++ else \ ++ (elm)->field.cqe_next->field.cqe_prev = \ ++ (elm)->field.cqe_prev; \ ++ if ((elm)->field.cqe_prev == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm)->field.cqe_next; \ ++ else \ ++ (elm)->field.cqe_prev->field.cqe_next = \ ++ (elm)->field.cqe_next; \ ++ _Q_INVALIDATE((elm)->field.cqe_prev); \ ++ _Q_INVALIDATE((elm)->field.cqe_next); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \ ++ if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \ ++ BSD_CIRCLEQ_END(head)) \ ++ (head).cqh_last = (elm2); \ ++ else \ ++ (elm2)->field.cqe_next->field.cqe_prev = (elm2); \ ++ if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \ ++ BSD_CIRCLEQ_END(head)) \ ++ (head).cqh_first = (elm2); \ ++ else \ ++ (elm2)->field.cqe_prev->field.cqe_next = (elm2); \ ++ _Q_INVALIDATE((elm)->field.cqe_prev); \ ++ _Q_INVALIDATE((elm)->field.cqe_next); \ ++} while (0) ++ ++#endif /* !_BSD_SYS_QUEUE_H_ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsec_ssb.c linux-3.0.4/crypto/ocf/ubsec_ssb/ubsec_ssb.c +--- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsec_ssb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ubsec_ssb/ubsec_ssb.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,2220 @@ ++ ++/* ++ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) ++ * Copyright (c) 2007 David McCullough (david_mccullough@securecomputing.com) ++ * Copyright (c) 2000 Jason L. Wright (jason@thought.net) ++ * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) ++ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, ++ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ++ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++#undef UBSEC_DEBUG ++#undef UBSEC_VERBOSE_DEBUG ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++#define UBSEC_DEBUG ++#endif ++ ++/* ++ * uBsec BCM5365 hardware crypto accelerator ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++/* ++ * BSD queue ++ */ ++//#include "bsdqueue.h" ++ ++/* ++ * OCF ++ */ ++#include ++#include ++ ++#define HMAC_HACK 1 ++ ++#define HMAC_HACK 1 ++#ifdef HMAC_HACK ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++#include "bsdqueue.h" ++#include "ubsecreg.h" ++#include "ubsecvar.h" ++ ++#define DRV_MODULE_NAME "ubsec_ssb" ++#define PFX DRV_MODULE_NAME ": " ++#define DRV_MODULE_VERSION "0.02" ++#define DRV_MODULE_RELDATE "Feb 21, 2009" ++ ++#if 1 ++#define DPRINTF(a...) \ ++ if (debug) \ ++ { \ ++ printk(DRV_MODULE_NAME ": " a); \ ++ } ++#else ++#define DPRINTF(a...) ++#endif ++ ++/* ++ * Prototypes ++ */ ++static irqreturn_t ubsec_ssb_isr(int, void *, struct pt_regs *); ++static int __devinit ubsec_ssb_probe(struct ssb_device *sdev, ++ const struct ssb_device_id *ent); ++static void __devexit ubsec_ssb_remove(struct ssb_device *sdev); ++int ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent, ++ struct device *self); ++static void ubsec_setup_mackey(struct ubsec_session *ses, int algo, ++ caddr_t key, int klen); ++static int dma_map_skb(struct ubsec_softc *sc, ++ struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen); ++static int dma_map_uio(struct ubsec_softc *sc, ++ struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen); ++static void dma_unmap(struct ubsec_softc *sc, ++ struct ubsec_dma_alloc *q_map, int mlen); ++static int ubsec_dmamap_aligned(struct ubsec_softc *sc, ++ const struct ubsec_dma_alloc *q_map, int mlen); ++ ++#ifdef UBSEC_DEBUG ++static int proc_read(char *buf, char **start, off_t offset, ++ int size, int *peof, void *data); ++#endif ++ ++void ubsec_reset_board(struct ubsec_softc *); ++void ubsec_init_board(struct ubsec_softc *); ++void ubsec_cleanchip(struct ubsec_softc *); ++void ubsec_totalreset(struct ubsec_softc *); ++int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); ++ ++static int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int ubsec_freesession(device_t, u_int64_t); ++static int ubsec_process(device_t, struct cryptop *, int); ++ ++void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); ++void ubsec_feed(struct ubsec_softc *); ++void ubsec_mcopy(struct sk_buff *, struct sk_buff *, int, int); ++void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); ++int ubsec_dma_malloc(struct ubsec_softc *, struct ubsec_dma_alloc *, ++ size_t, int); ++ ++/* DEBUG crap... */ ++void ubsec_dump_pb(struct ubsec_pktbuf *); ++void ubsec_dump_mcr(struct ubsec_mcr *); ++ ++#define READ_REG(sc,r) \ ++ ssb_read32((sc)->sdev, (r)); ++#define WRITE_REG(sc,r,val) \ ++ ssb_write32((sc)->sdev, (r), (val)); ++#define READ_REG_SDEV(sdev,r) \ ++ ssb_read32((sdev), (r)); ++#define WRITE_REG_SDEV(sdev,r,val) \ ++ ssb_write32((sdev), (r), (val)); ++ ++#define SWAP32(x) (x) = htole32(ntohl((x))) ++#define HTOLE32(x) (x) = htole32(x) ++ ++#ifdef __LITTLE_ENDIAN ++#define letoh16(x) (x) ++#define letoh32(x) (x) ++#endif ++ ++static int debug; ++module_param(debug, int, 0644); ++MODULE_PARM_DESC(debug, "Enable debug output"); ++ ++#define UBSEC_SSB_MAX_CHIPS 1 ++static struct ubsec_softc *ubsec_chip_idx[UBSEC_SSB_MAX_CHIPS]; ++static struct ubsec_stats ubsecstats; ++ ++#ifdef UBSEC_DEBUG ++static struct proc_dir_entry *procdebug; ++#endif ++ ++static struct ssb_device_id ubsec_ssb_tbl[] = { ++ /* Broadcom BCM5365P IPSec Core */ ++ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_IPSEC, SSB_ANY_REV), ++ SSB_DEVTABLE_END ++}; ++ ++static struct ssb_driver ubsec_ssb_driver = { ++ .name = DRV_MODULE_NAME, ++ .id_table = ubsec_ssb_tbl, ++ .probe = ubsec_ssb_probe, ++ .remove = __devexit_p(ubsec_ssb_remove), ++ /* ++ .suspend = ubsec_ssb_suspend, ++ .resume = ubsec_ssb_resume ++ */ ++}; ++ ++static device_method_t ubsec_ssb_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, ubsec_newsession), ++ DEVMETHOD(cryptodev_freesession,ubsec_freesession), ++ DEVMETHOD(cryptodev_process, ubsec_process), ++}; ++ ++#ifdef UBSEC_DEBUG ++static int ++proc_read(char *buf, char **start, off_t offset, ++ int size, int *peof, void *data) ++{ ++ int i = 0, byteswritten = 0, ret; ++ unsigned int stat, ctrl; ++#ifdef UBSEC_VERBOSE_DEBUG ++ struct ubsec_q *q; ++ struct ubsec_dma *dmap; ++#endif ++ ++ while ((i < UBSEC_SSB_MAX_CHIPS) && (ubsec_chip_idx[i] != NULL)) ++ { ++ struct ubsec_softc *sc = ubsec_chip_idx[i]; ++ ++ stat = READ_REG(sc, BS_STAT); ++ ctrl = READ_REG(sc, BS_CTRL); ++ ret = snprintf((buf + byteswritten), ++ (size - byteswritten) , ++ "DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl); ++ ++ byteswritten += ret; ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ printf("DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl); ++ ++ /* Dump all queues MCRs */ ++ if (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { ++ BSD_SIMPLEQ_FOREACH(q, &sc->sc_qchip, q_next) ++ { ++ dmap = q->q_dma; ++ ubsec_dump_mcr(&dmap->d_dma->d_mcr); ++ } ++ } ++#endif ++ ++ i++; ++ } ++ ++ *peof = 1; ++ ++ return byteswritten; ++} ++#endif ++ ++/* ++ * map in a given sk_buff ++ */ ++static int ++dma_map_skb(struct ubsec_softc *sc, struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen) ++{ ++ int i = 0; ++ dma_addr_t tmp; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ /* ++ * We support only a limited number of fragments. ++ */ ++ if (unlikely((skb_shinfo(skb)->nr_frags + 1) >= UBS_MAX_SCATTER)) ++ { ++ printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER); ++ return (-ENOMEM); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, 0, (unsigned int)skb->data, skb_headlen(skb)); ++#endif ++ ++ /* first data package */ ++ tmp = dma_map_single(sc->sc_dv, ++ skb->data, ++ skb_headlen(skb), ++ DMA_BIDIRECTIONAL); ++ ++ q_map[i].dma_paddr = tmp; ++ q_map[i].dma_vaddr = skb->data; ++ q_map[i].dma_size = skb_headlen(skb); ++ ++ if (unlikely(tmp == 0)) ++ { ++ printk(KERN_ERR "Could not map memory region for dma.\n"); ++ return (-EINVAL); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, 0, (unsigned int)tmp); ++#endif ++ ++ ++ /* all other data packages */ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, i + 1, ++ (unsigned int)page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, skb_shinfo(skb)->frags[i].size); ++#endif ++ ++ tmp = dma_map_single(sc->sc_dv, ++ page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ skb_shinfo(skb)->frags[i].size, ++ DMA_BIDIRECTIONAL); ++ ++ q_map[i + 1].dma_paddr = tmp; ++ q_map[i + 1].dma_vaddr = (void*)(page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset); ++ q_map[i + 1].dma_size = skb_shinfo(skb)->frags[i].size; ++ ++ if (unlikely(tmp == 0)) ++ { ++ printk(KERN_ERR "Could not map memory region for dma.\n"); ++ return (-EINVAL); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, i + 1, (unsigned int)tmp); ++#endif ++ ++ } ++ *mlen = i + 1; ++ ++ return(0); ++} ++ ++/* ++ * map in a given uio buffer ++ */ ++ ++static int ++dma_map_uio(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int n; ++ dma_addr_t tmp; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ /* ++ * We support only a limited number of fragments. ++ */ ++ if (unlikely(uio->uio_iovcnt >= UBS_MAX_SCATTER)) ++ { ++ printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER); ++ return (-ENOMEM); ++ } ++ ++ for (n = 0; n < uio->uio_iovcnt; n++) { ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, n, (unsigned int)iov->iov_base, iov->iov_len); ++#endif ++ tmp = dma_map_single(sc->sc_dv, ++ iov->iov_base, ++ iov->iov_len, ++ DMA_BIDIRECTIONAL); ++ ++ q_map[n].dma_paddr = tmp; ++ q_map[n].dma_vaddr = iov->iov_base; ++ q_map[n].dma_size = iov->iov_len; ++ ++ if (unlikely(tmp == 0)) ++ { ++ printk(KERN_ERR "Could not map memory region for dma.\n"); ++ return (-EINVAL); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, n, (unsigned int)tmp); ++#endif ++ ++ iov++; ++ } ++ *mlen = n; ++ ++ return(0); ++} ++ ++static void ++dma_unmap(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, int mlen) ++{ ++ int i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ for(i = 0; i < mlen; i++) ++ { ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, (unsigned int)q_map[i].dma_paddr, q_map[i].dma_size); ++#endif ++ dma_unmap_single(sc->sc_dv, ++ q_map[i].dma_paddr, ++ q_map[i].dma_size, ++ DMA_BIDIRECTIONAL); ++ } ++ return; ++} ++ ++/* ++ * Is the operand suitable aligned for direct DMA. Each ++ * segment must be aligned on a 32-bit boundary and all ++ * but the last segment must be a multiple of 4 bytes. ++ */ ++static int ++ubsec_dmamap_aligned(struct ubsec_softc *sc, const struct ubsec_dma_alloc *q_map, int mlen) ++{ ++ int i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ for (i = 0; i < mlen; i++) { ++ if (q_map[i].dma_paddr & 3) ++ return (0); ++ if (i != (mlen - 1) && (q_map[i].dma_size & 3)) ++ return (0); ++ } ++ return (1); ++} ++ ++ ++#define N(a) (sizeof(a) / sizeof (a[0])) ++static void ++ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen) ++{ ++#ifdef HMAC_HACK ++ MD5_CTX md5ctx; ++ SHA1_CTX sha1ctx; ++ int i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_IPAD_VAL; ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_ipad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_opad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_OPAD_VAL; ++ ++#else /* HMAC_HACK */ ++ DPRINTF("md5/sha not implemented\n"); ++#endif /* HMAC_HACK */ ++} ++#undef N ++ ++static int ++__devinit ubsec_ssb_probe(struct ssb_device *sdev, ++ const struct ssb_device_id *ent) ++{ ++ int err; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ err = ssb_bus_powerup(sdev->bus, 0); ++ if (err) { ++ dev_err(sdev->dev, "Failed to powerup the bus\n"); ++ goto err_out; ++ } ++ ++ err = request_irq(sdev->irq, (irq_handler_t)ubsec_ssb_isr, ++ IRQF_DISABLED | IRQF_SHARED, DRV_MODULE_NAME, sdev); ++ if (err) { ++ dev_err(sdev->dev, "Could not request irq\n"); ++ goto err_out_powerdown; ++ } ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36)) ++ err = dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(32)) || ++ dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(32)); ++#else ++ err = ssb_dma_set_mask(sdev, DMA_32BIT_MASK); ++#endif ++ if (err) { ++ dev_err(sdev->dev, ++ "Required 32BIT DMA mask unsupported by the system.\n"); ++ goto err_out_free_irq; ++ } ++ ++ printk(KERN_INFO "Sentry5(tm) ROBOGateway(tm) IPSec Core at IRQ %u\n", ++ sdev->irq); ++ ++ DPRINTF("Vendor: %x, core id: %x, revision: %x\n", ++ sdev->id.vendor, sdev->id.coreid, sdev->id.revision); ++ ++ ssb_device_enable(sdev, 0); ++ ++ if (ubsec_attach(sdev, ent, sdev->dev) != 0) ++ goto err_out_disable; ++ ++#ifdef UBSEC_DEBUG ++ procdebug = create_proc_entry(DRV_MODULE_NAME, S_IRUSR, NULL); ++ if (procdebug) ++ { ++ procdebug->read_proc = proc_read; ++ procdebug->data = NULL; ++ } else ++ DPRINTF("Unable to create proc file.\n"); ++#endif ++ ++ return 0; ++ ++err_out_disable: ++ ssb_device_disable(sdev, 0); ++ ++err_out_free_irq: ++ free_irq(sdev->irq, sdev); ++ ++err_out_powerdown: ++ ssb_bus_may_powerdown(sdev->bus); ++ ++err_out: ++ return err; ++} ++ ++static void __devexit ubsec_ssb_remove(struct ssb_device *sdev) { ++ ++ struct ubsec_softc *sc; ++ unsigned int ctrlflgs; ++ struct ubsec_dma *dmap; ++ u_int32_t i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ ctrlflgs = READ_REG_SDEV(sdev, BS_CTRL); ++ /* disable all IPSec Core interrupts globally */ ++ ctrlflgs ^= (BS_CTRL_MCR1INT | BS_CTRL_MCR2INT | ++ BS_CTRL_DMAERR); ++ WRITE_REG_SDEV(sdev, BS_CTRL, ctrlflgs); ++ ++ free_irq(sdev->irq, sdev); ++ ++ sc = (struct ubsec_softc *)ssb_get_drvdata(sdev); ++ ++ /* unregister all crypto algorithms */ ++ crypto_unregister_all(sc->sc_cid); ++ ++ /* Free queue / dma memory */ ++ for (i = 0; i < UBS_MAX_NQUEUE; i++) { ++ struct ubsec_q *q; ++ ++ q = sc->sc_queuea[i]; ++ if (q != NULL) ++ { ++ dmap = q->q_dma; ++ if (dmap != NULL) ++ { ++ ubsec_dma_free(sc, &dmap->d_alloc); ++ q->q_dma = NULL; ++ } ++ kfree(q); ++ } ++ sc->sc_queuea[i] = NULL; ++ } ++ ++ ssb_device_disable(sdev, 0); ++ ssb_bus_may_powerdown(sdev->bus); ++ ssb_set_drvdata(sdev, NULL); ++ ++#ifdef UBSEC_DEBUG ++ if (procdebug) ++ remove_proc_entry(DRV_MODULE_NAME, NULL); ++#endif ++ ++} ++ ++ ++int ++ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent, ++ struct device *self) ++{ ++ struct ubsec_softc *sc = NULL; ++ struct ubsec_dma *dmap; ++ u_int32_t i; ++ static int num_chips = 0; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ sc = (struct ubsec_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ sc->sc_dv = sdev->dev; ++ sc->sdev = sdev; ++ ++ spin_lock_init(&sc->sc_ringmtx); ++ ++ softc_device_init(sc, "ubsec_ssb", num_chips, ubsec_ssb_methods); ++ ++ /* Maybe someday there are boards with more than one chip available */ ++ if (num_chips < UBSEC_SSB_MAX_CHIPS) { ++ ubsec_chip_idx[device_get_unit(sc->sc_dev)] = sc; ++ num_chips++; ++ } ++ ++ ssb_set_drvdata(sdev, sc); ++ ++ BSD_SIMPLEQ_INIT(&sc->sc_queue); ++ BSD_SIMPLEQ_INIT(&sc->sc_qchip); ++ BSD_SIMPLEQ_INIT(&sc->sc_queue2); ++ BSD_SIMPLEQ_INIT(&sc->sc_qchip2); ++ BSD_SIMPLEQ_INIT(&sc->sc_q2free); ++ ++ sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ return -1; ++ } ++ ++ BSD_SIMPLEQ_INIT(&sc->sc_freequeue); ++ dmap = sc->sc_dmaa; ++ for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { ++ struct ubsec_q *q; ++ ++ q = (struct ubsec_q *)kmalloc(sizeof(struct ubsec_q), GFP_KERNEL); ++ if (q == NULL) { ++ printf(": can't allocate queue buffers\n"); ++ break; ++ } ++ ++ if (ubsec_dma_malloc(sc, &dmap->d_alloc, sizeof(struct ubsec_dmachunk),0)) { ++ printf(": can't allocate dma buffers\n"); ++ kfree(q); ++ break; ++ } ++ dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; ++ ++ q->q_dma = dmap; ++ sc->sc_queuea[i] = q; ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); ++ } ++ ++ /* ++ * Reset Broadcom chip ++ */ ++ ubsec_reset_board(sc); ++ ++ /* ++ * Init Broadcom chip ++ */ ++ ubsec_init_board(sc); ++ ++ /* supported crypto algorithms */ ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ ++ if (sc->sc_flags & UBS_FLAGS_AES) { ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES AES128 AES192 AES256 MD5_HMAC SHA1_HMAC\n"); ++ } ++ else ++ printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES MD5_HMAC SHA1_HMAC\n"); ++ ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ ++ return 0; ++} ++ ++/* ++ * UBSEC Interrupt routine ++ */ ++static irqreturn_t ++ubsec_ssb_isr(int irq, void *arg, struct pt_regs *regs) ++{ ++ struct ubsec_softc *sc = NULL; ++ volatile u_int32_t stat; ++ struct ubsec_q *q; ++ struct ubsec_dma *dmap; ++ int npkts = 0, i; ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ sc = (struct ubsec_softc *)ssb_get_drvdata(arg); ++ ++ stat = READ_REG(sc, BS_STAT); ++ ++ stat &= sc->sc_statmask; ++ if (stat == 0) ++ return IRQ_NONE; ++ ++ WRITE_REG(sc, BS_STAT, stat); /* IACK */ ++ ++ /* ++ * Check to see if we have any packets waiting for us ++ */ ++ if ((stat & BS_STAT_MCR1_DONE)) { ++ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip); ++ dmap = q->q_dma; ++ ++ if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) ++ { ++ DPRINTF("error while processing MCR. Flags = %x\n", dmap->d_dma->d_mcr.mcr_flags); ++ break; ++ } ++ ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); ++ ++ npkts = q->q_nstacked_mcrs; ++ /* ++ * search for further sc_qchip ubsec_q's that share ++ * the same MCR, and complete them too, they must be ++ * at the top. ++ */ ++ for (i = 0; i < npkts; i++) { ++ if(q->q_stacked_mcr[i]) ++ ubsec_callback(sc, q->q_stacked_mcr[i]); ++ else ++ break; ++ } ++ ubsec_callback(sc, q); ++ } ++ ++ /* ++ * Don't send any more packet to chip if there has been ++ * a DMAERR. ++ */ ++ if (likely(!(stat & BS_STAT_DMAERR))) ++ ubsec_feed(sc); ++ else ++ DPRINTF("DMA error occurred. Stop feeding crypto chip.\n"); ++ } ++ ++ /* ++ * Check to see if we got any DMA Error ++ */ ++ if (stat & BS_STAT_DMAERR) { ++ volatile u_int32_t a = READ_REG(sc, BS_ERR); ++ ++ printf(KERN_ERR "%s: dmaerr %s@%08x\n", DRV_MODULE_NAME, ++ (a & BS_ERR_READ) ? "read" : "write", a & BS_ERR_ADDR); ++ ++ ubsecstats.hst_dmaerr++; ++ ubsec_totalreset(sc); ++ ubsec_feed(sc); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * ubsec_feed() - aggregate and post requests to chip ++ * It is assumed that the caller set splnet() ++ */ ++void ++ubsec_feed(struct ubsec_softc *sc) ++{ ++#ifdef UBSEC_VERBOSE_DEBUG ++ static int max; ++#endif ++ struct ubsec_q *q, *q2; ++ int npkts, i; ++ void *v; ++ u_int32_t stat; ++ ++ npkts = sc->sc_nqueue; ++ if (npkts > UBS_MAX_AGGR) ++ npkts = UBS_MAX_AGGR; ++ if (npkts < 2) ++ goto feed1; ++ ++ stat = READ_REG(sc, BS_STAT); ++ ++ if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { ++ if(stat & BS_STAT_DMAERR) { ++ ubsec_totalreset(sc); ++ ubsecstats.hst_dmaerr++; ++ } ++ return; ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("merging %d records\n", npkts); ++ ++ /* XXX temporary aggregation statistics reporting code */ ++ if (max < npkts) { ++ max = npkts; ++ DPRINTF("%s: new max aggregate %d\n", DRV_MODULE_NAME, max); ++ } ++#endif /* UBSEC_VERBOSE_DEBUG */ ++ ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_queue); ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); ++ --sc->sc_nqueue; ++ ++#if 0 ++ /* ++ * XXX ++ * We use dma_map_single() - no sync required! ++ */ ++ ++ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, ++ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); ++ if (q->q_dst_map != NULL) ++ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, ++ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); ++#endif ++ ++ q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ ++ ++ for (i = 0; i < q->q_nstacked_mcrs; i++) { ++ q2 = BSD_SIMPLEQ_FIRST(&sc->sc_queue); ++ ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, ++ 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); ++ if (q2->q_dst_map != NULL) ++ bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, ++ 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); ++#endif ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); ++ --sc->sc_nqueue; ++ ++ v = ((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - ++ sizeof(struct ubsec_mcr_add); ++ bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); ++ q->q_stacked_mcr[i] = q2; ++ } ++ q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, ++ 0, q->q_dma->d_alloc.dma_map->dm_mapsize, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++#endif ++ WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_mcr)); ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("feed (1): q->chip %p %08x %08x\n", q, ++ (u_int32_t)q->q_dma->d_alloc.dma_paddr, ++ (u_int32_t)(q->q_dma->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_mcr))); ++#endif /* UBSEC_DEBUG */ ++ return; ++ ++feed1: ++ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_queue)) { ++ stat = READ_REG(sc, BS_STAT); ++ ++ if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { ++ if(stat & BS_STAT_DMAERR) { ++ ubsec_totalreset(sc); ++ ubsecstats.hst_dmaerr++; ++ } ++ break; ++ } ++ ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_queue); ++ ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, ++ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); ++ if (q->q_dst_map != NULL) ++ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, ++ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); ++ bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, ++ 0, q->q_dma->d_alloc.dma_map->dm_mapsize, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++#endif ++ ++ WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_mcr)); ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("feed (2): q->chip %p %08x %08x\n", q, ++ (u_int32_t)q->q_dma->d_alloc.dma_paddr, ++ (u_int32_t)(q->q_dma->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_mcr))); ++#endif /* UBSEC_DEBUG */ ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); ++ --sc->sc_nqueue; ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); ++ } ++} ++ ++/* ++ * Allocate a new 'session' and return an encoded session id. 'sidp' ++ * contains our registration id, and should contain an encoded session ++ * id on successful allocation. ++ */ ++static int ++ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct ubsec_softc *sc = NULL; ++ struct ubsec_session *ses = NULL; ++ int sesn, i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ if (sidp == NULL || cri == NULL) ++ return (EINVAL); ++ ++ sc = device_get_softc(dev); ++ ++ if (sc == NULL) ++ return (EINVAL); ++ ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1_HMAC) { ++ if (macini) ++ return (EINVAL); ++ macini = c; ++ } else if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC) { ++ if (encini) ++ return (EINVAL); ++ encini = c; ++ } else ++ return (EINVAL); ++ } ++ if (encini == NULL && macini == NULL) ++ return (EINVAL); ++ ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct ubsec_session *)kmalloc( ++ sizeof(struct ubsec_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, sizeof(struct ubsec_session)); ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn].ses_used == 0) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sesn = sc->sc_nsessions; ++ ses = (struct ubsec_session *)kmalloc((sesn + 1) * ++ sizeof(struct ubsec_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, (sesn + 1) * sizeof(struct ubsec_session)); ++ bcopy(sc->sc_sessions, ses, sesn * ++ sizeof(struct ubsec_session)); ++ bzero(sc->sc_sessions, sesn * ++ sizeof(struct ubsec_session)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ ++ bzero(ses, sizeof(struct ubsec_session)); ++ ses->ses_used = 1; ++ if (encini) { ++ /* get an IV */ ++ /* XXX may read fewer than requested */ ++ read_random(ses->ses_iv, sizeof(ses->ses_iv)); ++ ++ /* Go ahead and compute key in ubsec's byte order */ ++ if (encini->cri_alg == CRYPTO_DES_CBC) { ++ /* DES uses the same key three times: ++ * 1st encrypt -> 2nd decrypt -> 3nd encrypt */ ++ bcopy(encini->cri_key, &ses->ses_key[0], 8); ++ bcopy(encini->cri_key, &ses->ses_key[2], 8); ++ bcopy(encini->cri_key, &ses->ses_key[4], 8); ++ ses->ses_keysize = 192; /* Fake! Actually its only 64bits .. ++ oh no it is even less: 54bits. */ ++ } else if(encini->cri_alg == CRYPTO_3DES_CBC) { ++ bcopy(encini->cri_key, ses->ses_key, 24); ++ ses->ses_keysize = 192; ++ } else if(encini->cri_alg == CRYPTO_AES_CBC) { ++ ses->ses_keysize = encini->cri_klen; ++ ++ if (ses->ses_keysize != 128 && ++ ses->ses_keysize != 192 && ++ ses->ses_keysize != 256) ++ { ++ DPRINTF("unsupported AES key size: %d\n", ses->ses_keysize); ++ return (EINVAL); ++ } ++ bcopy(encini->cri_key, ses->ses_key, (ses->ses_keysize / 8)); ++ } ++ ++ /* Hardware requires the keys in little endian byte order */ ++ for (i=0; i < (ses->ses_keysize / 32); i++) ++ SWAP32(ses->ses_key[i]); ++ } ++ ++ if (macini) { ++ ses->ses_mlen = macini->cri_mlen; ++ ++ if (ses->ses_mlen == 0 || ++ ses->ses_mlen > SHA1_HASH_LEN) { ++ ++ if (macini->cri_alg == CRYPTO_MD5_HMAC || ++ macini->cri_alg == CRYPTO_SHA1_HMAC) ++ { ++ ses->ses_mlen = DEFAULT_HMAC_LEN; ++ } else ++ { ++ /* ++ * Reserved for future usage. MD5/SHA1 calculations have ++ * different hash sizes. ++ */ ++ printk(KERN_ERR DRV_MODULE_NAME ": unsupported hash operation with mac/hash len: %d\n", ses->ses_mlen); ++ return (EINVAL); ++ } ++ ++ } ++ ++ if (macini->cri_key != NULL) { ++ ubsec_setup_mackey(ses, macini->cri_alg, macini->cri_key, ++ macini->cri_klen / 8); ++ } ++ } ++ ++ *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); ++ return (0); ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++ubsec_freesession(device_t dev, u_int64_t tid) ++{ ++ struct ubsec_softc *sc = device_get_softc(dev); ++ int session; ++ u_int32_t sid = ((u_int32_t)tid) & 0xffffffff; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ if (sc == NULL) ++ return (EINVAL); ++ ++ session = UBSEC_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); ++ return (0); ++ } else ++ return (EINVAL); ++} ++ ++static int ++ubsec_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct ubsec_q *q = NULL; ++ int err = 0, i, j, nicealign; ++ struct ubsec_softc *sc = device_get_softc(dev); ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ int encoffset = 0, macoffset = 0, cpskip, cpoffset; ++ int sskip, dskip, stheend, dtheend, ivsize = 8; ++ int16_t coffset; ++ struct ubsec_session *ses; ++ struct ubsec_generic_ctx ctx; ++ struct ubsec_dma *dmap = NULL; ++ unsigned long flags; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ if (unlikely(crp == NULL || crp->crp_callback == NULL)) { ++ ubsecstats.hst_invalid++; ++ return (EINVAL); ++ } ++ ++ if (unlikely(sc == NULL)) ++ return (EINVAL); ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_lock_irqsave\n"); ++#endif ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ //spin_lock_irq(&sc->sc_ringmtx); ++ ++ if (BSD_SIMPLEQ_EMPTY(&sc->sc_freequeue)) { ++ ubsecstats.hst_queuefull++; ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_unlock_irqrestore\n"); ++#endif ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ //spin_unlock_irq(&sc->sc_ringmtx); ++ err = ENOMEM; ++ goto errout2; ++ } ++ ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_freequeue); ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next); ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_unlock_irqrestore\n"); ++#endif ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ //spin_unlock_irq(&sc->sc_ringmtx); ++ ++ dmap = q->q_dma; /* Save dma pointer */ ++ bzero(q, sizeof(struct ubsec_q)); ++ bzero(&ctx, sizeof(ctx)); ++ ++ q->q_sesn = UBSEC_SESSION(crp->crp_sid); ++ q->q_dma = dmap; ++ ses = &sc->sc_sessions[q->q_sesn]; ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ q->q_src_m = (struct sk_buff *)crp->crp_buf; ++ q->q_dst_m = (struct sk_buff *)crp->crp_buf; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ q->q_src_io = (struct uio *)crp->crp_buf; ++ q->q_dst_io = (struct uio *)crp->crp_buf; ++ } else { ++ err = EINVAL; ++ goto errout; /* XXX we don't handle contiguous blocks! */ ++ } ++ ++ bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); ++ ++ dmap->d_dma->d_mcr.mcr_pkts = htole16(1); ++ dmap->d_dma->d_mcr.mcr_flags = 0; ++ q->q_crp = crp; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ if (crd2 == NULL) { ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC) { ++ maccrd = crd1; ++ enccrd = NULL; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) { ++ maccrd = NULL; ++ enccrd = crd1; ++ } else { ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ /* ++ * We cannot order the ubsec as requested ++ */ ++ printk(KERN_ERR DRV_MODULE_NAME ": got wrong algorithm/signature order.\n"); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ ++ /* Encryption/Decryption requested */ ++ if (enccrd) { ++ encoffset = enccrd->crd_skip; ++ ++ if (enccrd->crd_alg == CRYPTO_DES_CBC || ++ enccrd->crd_alg == CRYPTO_3DES_CBC) ++ { ++ ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); ++ ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_DES); ++ ivsize = 8; /* [3]DES uses 64bit IVs */ ++ } else { ++ ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_AES); ++ ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES); ++ ivsize = 16; /* AES uses 128bit IVs / [3]DES 64bit IVs */ ++ ++ switch(ses->ses_keysize) ++ { ++ case 128: ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AES128); ++ break; ++ case 192: ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AES192); ++ break; ++ case 256: ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AES256); ++ break; ++ default: ++ DPRINTF("invalid AES key size: %d\n", ses->ses_keysize); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ /* Direction: Outbound */ ++ ++ q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize); ++ } else { ++ for(i=0; i < (ivsize / 4); i++) ++ ctx.pc_iv[i] = ses->ses_iv[i]; ++ } ++ ++ /* If there is no IV in the buffer -> copy it here */ ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ if (crp->crp_flags & CRYPTO_F_SKBUF) ++ /* ++ m_copyback(q->q_src_m, ++ enccrd->crd_inject, ++ 8, ctx.pc_iv); ++ */ ++ crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_m, ++ enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv); ++ else if (crp->crp_flags & CRYPTO_F_IOV) ++ /* ++ cuio_copyback(q->q_src_io, ++ enccrd->crd_inject, ++ 8, ctx.pc_iv); ++ */ ++ crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_io, ++ enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv); ++ } ++ } else { ++ /* Direction: Inbound */ ++ ++ ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize); ++ else if (crp->crp_flags & CRYPTO_F_SKBUF) ++ /* ++ m_copydata(q->q_src_m, enccrd->crd_inject, ++ 8, (caddr_t)ctx.pc_iv); ++ */ ++ crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_m, ++ enccrd->crd_inject, ivsize, ++ (caddr_t)ctx.pc_iv); ++ else if (crp->crp_flags & CRYPTO_F_IOV) ++ /* ++ cuio_copydata(q->q_src_io, ++ enccrd->crd_inject, 8, ++ (caddr_t)ctx.pc_iv); ++ */ ++ crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_io, ++ enccrd->crd_inject, ivsize, ++ (caddr_t)ctx.pc_iv); ++ ++ } ++ ++ /* Even though key & IV sizes differ from cipher to cipher ++ * copy / swap the full array lengths. Let the compiler unroll ++ * the loop to increase the cpu pipeline performance... */ ++ for(i=0; i < 8; i++) ++ ctx.pc_key[i] = ses->ses_key[i]; ++ for(i=0; i < 4; i++) ++ SWAP32(ctx.pc_iv[i]); ++ } ++ ++ /* Authentication requested */ ++ if (maccrd) { ++ macoffset = maccrd->crd_skip; ++ ++ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); ++ else ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); ++ ++ for (i = 0; i < 5; i++) { ++ ctx.pc_hminner[i] = ses->ses_hminner[i]; ++ ctx.pc_hmouter[i] = ses->ses_hmouter[i]; ++ ++ HTOLE32(ctx.pc_hminner[i]); ++ HTOLE32(ctx.pc_hmouter[i]); ++ } ++ } ++ ++ if (enccrd && maccrd) { ++ /* ++ * ubsec cannot handle packets where the end of encryption ++ * and authentication are not the same, or where the ++ * encrypted part begins before the authenticated part. ++ */ ++ if (((encoffset + enccrd->crd_len) != ++ (macoffset + maccrd->crd_len)) || ++ (enccrd->crd_skip < maccrd->crd_skip)) { ++ err = EINVAL; ++ goto errout; ++ } ++ sskip = maccrd->crd_skip; ++ cpskip = dskip = enccrd->crd_skip; ++ stheend = maccrd->crd_len; ++ dtheend = enccrd->crd_len; ++ coffset = enccrd->crd_skip - maccrd->crd_skip; ++ cpoffset = cpskip + dtheend; ++#ifdef UBSEC_DEBUG ++ DPRINTF("mac: skip %d, len %d, inject %d\n", ++ maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); ++ DPRINTF("enc: skip %d, len %d, inject %d\n", ++ enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); ++ DPRINTF("src: skip %d, len %d\n", sskip, stheend); ++ DPRINTF("dst: skip %d, len %d\n", dskip, dtheend); ++ DPRINTF("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", ++ coffset, stheend, cpskip, cpoffset); ++#endif ++ } else { ++ cpskip = dskip = sskip = macoffset + encoffset; ++ dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; ++ cpoffset = cpskip + dtheend; ++ coffset = 0; ++ } ++ ctx.pc_offset = htole16(coffset >> 2); ++ ++#if 0 ++ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, ++ 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { ++ err = ENOMEM; ++ goto errout; ++ } ++#endif ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++#if 0 ++ if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, ++ q->q_src_m, BUS_DMA_NOWAIT) != 0) { ++ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); ++ q->q_src_map = NULL; ++ err = ENOMEM; ++ goto errout; ++ } ++#endif ++ err = dma_map_skb(sc, q->q_src_map, q->q_src_m, &q->q_src_len); ++ if (unlikely(err != 0)) ++ goto errout; ++ ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++#if 0 ++ if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, ++ q->q_src_io, BUS_DMA_NOWAIT) != 0) { ++ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); ++ q->q_src_map = NULL; ++ err = ENOMEM; ++ goto errout; ++ } ++#endif ++ err = dma_map_uio(sc, q->q_src_map, q->q_src_io, &q->q_src_len); ++ if (unlikely(err != 0)) ++ goto errout; ++ } ++ ++ /* ++ * Check alignment ++ */ ++ nicealign = ubsec_dmamap_aligned(sc, q->q_src_map, q->q_src_len); ++ ++ dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("src skip: %d\n", sskip); ++#endif ++ for (i = j = 0; i < q->q_src_len; i++) { ++ struct ubsec_pktbuf *pb; ++ size_t packl = q->q_src_map[i].dma_size; ++ dma_addr_t packp = q->q_src_map[i].dma_paddr; ++ ++ if (sskip >= packl) { ++ sskip -= packl; ++ continue; ++ } ++ ++ packl -= sskip; ++ packp += sskip; ++ sskip = 0; ++ ++ /* maximum fragment size is 0xfffc */ ++ if (packl > 0xfffc) { ++ DPRINTF("Error: fragment size is bigger than 0xfffc.\n"); ++ err = EIO; ++ goto errout; ++ } ++ ++ if (j == 0) ++ pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; ++ else ++ pb = &dmap->d_dma->d_sbuf[j - 1]; ++ ++ pb->pb_addr = htole32(packp); ++ ++ if (stheend) { ++ if (packl > stheend) { ++ pb->pb_len = htole32(stheend); ++ stheend = 0; ++ } else { ++ pb->pb_len = htole32(packl); ++ stheend -= packl; ++ } ++ } else ++ pb->pb_len = htole32(packl); ++ ++ if ((i + 1) == q->q_src_len) ++ pb->pb_next = 0; ++ else ++ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_sbuf[j])); ++ j++; ++ } ++ ++ if (enccrd == NULL && maccrd != NULL) { ++ /* Authentication only */ ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = ++ htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_macbuf[0])); ++#ifdef UBSEC_DEBUG ++ DPRINTF("opkt: %x %x %x\n", ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); ++#endif ++ } else { ++ if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (!nicealign) { ++ err = EINVAL; ++ goto errout; ++ } ++#if 0 ++ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, ++ UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, ++ &q->q_dst_map) != 0) { ++ err = ENOMEM; ++ goto errout; ++ } ++ if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, ++ q->q_dst_io, BUS_DMA_NOWAIT) != 0) { ++ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); ++ q->q_dst_map = NULL; ++ goto errout; ++ } ++#endif ++ ++ /* HW shall copy the result into the source memory */ ++ for(i = 0; i < q->q_src_len; i++) ++ q->q_dst_map[i] = q->q_src_map[i]; ++ ++ q->q_dst_len = q->q_src_len; ++ q->q_has_dst = 0; ++ ++ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (nicealign) { ++ ++ /* HW shall copy the result into the source memory */ ++ q->q_dst_m = q->q_src_m; ++ for(i = 0; i < q->q_src_len; i++) ++ q->q_dst_map[i] = q->q_src_map[i]; ++ ++ q->q_dst_len = q->q_src_len; ++ q->q_has_dst = 0; ++ ++ } else { ++#ifdef NOTYET ++ int totlen, len; ++ struct sk_buff *m, *top, **mp; ++ ++ totlen = q->q_src_map->dm_mapsize; ++ if (q->q_src_m->m_flags & M_PKTHDR) { ++ len = MHLEN; ++ MGETHDR(m, M_DONTWAIT, MT_DATA); ++ } else { ++ len = MLEN; ++ MGET(m, M_DONTWAIT, MT_DATA); ++ } ++ if (m == NULL) { ++ err = ENOMEM; ++ goto errout; ++ } ++ if (len == MHLEN) ++ M_DUP_PKTHDR(m, q->q_src_m); ++ if (totlen >= MINCLSIZE) { ++ MCLGET(m, M_DONTWAIT); ++ if (m->m_flags & M_EXT) ++ len = MCLBYTES; ++ } ++ m->m_len = len; ++ top = NULL; ++ mp = ⊤ ++ ++ while (totlen > 0) { ++ if (top) { ++ MGET(m, M_DONTWAIT, MT_DATA); ++ if (m == NULL) { ++ m_freem(top); ++ err = ENOMEM; ++ goto errout; ++ } ++ len = MLEN; ++ } ++ if (top && totlen >= MINCLSIZE) { ++ MCLGET(m, M_DONTWAIT); ++ if (m->m_flags & M_EXT) ++ len = MCLBYTES; ++ } ++ m->m_len = len = min(totlen, len); ++ totlen -= len; ++ *mp = m; ++ mp = &m->m_next; ++ } ++ q->q_dst_m = top; ++ ubsec_mcopy(q->q_src_m, q->q_dst_m, ++ cpskip, cpoffset); ++ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, ++ UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, ++ &q->q_dst_map) != 0) { ++ err = ENOMEM; ++ goto errout; ++ } ++ if (bus_dmamap_load_mbuf(sc->sc_dmat, ++ q->q_dst_map, q->q_dst_m, ++ BUS_DMA_NOWAIT) != 0) { ++ bus_dmamap_destroy(sc->sc_dmat, ++ q->q_dst_map); ++ q->q_dst_map = NULL; ++ err = ENOMEM; ++ goto errout; ++ } ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", ++ __FILE__, __LINE__); ++ err = EINVAL; ++ goto errout; ++#endif ++ } ++ } else { ++ err = EINVAL; ++ goto errout; ++ } ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("dst skip: %d\n", dskip); ++#endif ++ for (i = j = 0; i < q->q_dst_len; i++) { ++ struct ubsec_pktbuf *pb; ++ size_t packl = q->q_dst_map[i].dma_size; ++ dma_addr_t packp = q->q_dst_map[i].dma_paddr; ++ ++ if (dskip >= packl) { ++ dskip -= packl; ++ continue; ++ } ++ ++ packl -= dskip; ++ packp += dskip; ++ dskip = 0; ++ ++ if (packl > 0xfffc) { ++ DPRINTF("Error: fragment size is bigger than 0xfffc.\n"); ++ err = EIO; ++ goto errout; ++ } ++ ++ if (j == 0) ++ pb = &dmap->d_dma->d_mcr.mcr_opktbuf; ++ else ++ pb = &dmap->d_dma->d_dbuf[j - 1]; ++ ++ pb->pb_addr = htole32(packp); ++ ++ if (dtheend) { ++ if (packl > dtheend) { ++ pb->pb_len = htole32(dtheend); ++ dtheend = 0; ++ } else { ++ pb->pb_len = htole32(packl); ++ dtheend -= packl; ++ } ++ } else ++ pb->pb_len = htole32(packl); ++ ++ if ((i + 1) == q->q_dst_len) { ++ if (maccrd) ++ /* Authentication: ++ * The last fragment of the output buffer ++ * contains the HMAC. */ ++ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_macbuf[0])); ++ else ++ pb->pb_next = 0; ++ } else ++ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_dbuf[j])); ++ j++; ++ } ++ } ++ ++ dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ if (sc->sc_flags & UBS_FLAGS_LONGCTX) { ++ /* new Broadcom cards with dynamic long command context structure */ ++ ++ if (enccrd != NULL && ++ enccrd->crd_alg == CRYPTO_AES_CBC) ++ { ++ struct ubsec_pktctx_aes128 *ctxaes128; ++ struct ubsec_pktctx_aes192 *ctxaes192; ++ struct ubsec_pktctx_aes256 *ctxaes256; ++ ++ switch(ses->ses_keysize) ++ { ++ /* AES 128bit */ ++ case 128: ++ ctxaes128 = (struct ubsec_pktctx_aes128 *) ++ (dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ ctxaes128->pc_len = htole16(sizeof(struct ubsec_pktctx_aes128)); ++ ctxaes128->pc_type = ctx.pc_type; ++ ctxaes128->pc_flags = ctx.pc_flags; ++ ctxaes128->pc_offset = ctx.pc_offset; ++ for (i = 0; i < 4; i++) ++ ctxaes128->pc_aeskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes128->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes128->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ for (i = 0; i < 4; i++) ++ ctxaes128->pc_iv[i] = ctx.pc_iv[i]; ++ break; ++ ++ /* AES 192bit */ ++ case 192: ++ ctxaes192 = (struct ubsec_pktctx_aes192 *) ++ (dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ ctxaes192->pc_len = htole16(sizeof(struct ubsec_pktctx_aes192)); ++ ctxaes192->pc_type = ctx.pc_type; ++ ctxaes192->pc_flags = ctx.pc_flags; ++ ctxaes192->pc_offset = ctx.pc_offset; ++ for (i = 0; i < 6; i++) ++ ctxaes192->pc_aeskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes192->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes192->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ for (i = 0; i < 4; i++) ++ ctxaes192->pc_iv[i] = ctx.pc_iv[i]; ++ break; ++ ++ /* AES 256bit */ ++ case 256: ++ ctxaes256 = (struct ubsec_pktctx_aes256 *) ++ (dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ ctxaes256->pc_len = htole16(sizeof(struct ubsec_pktctx_aes256)); ++ ctxaes256->pc_type = ctx.pc_type; ++ ctxaes256->pc_flags = ctx.pc_flags; ++ ctxaes256->pc_offset = ctx.pc_offset; ++ for (i = 0; i < 8; i++) ++ ctxaes256->pc_aeskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes256->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes256->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ for (i = 0; i < 4; i++) ++ ctxaes256->pc_iv[i] = ctx.pc_iv[i]; ++ break; ++ ++ } ++ } else { ++ /* ++ * [3]DES / MD5_HMAC / SHA1_HMAC ++ * ++ * MD5_HMAC / SHA1_HMAC can use the IPSEC 3DES operation without ++ * encryption. ++ */ ++ struct ubsec_pktctx_des *ctxdes; ++ ++ ctxdes = (struct ubsec_pktctx_des *)(dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ ctxdes->pc_len = htole16(sizeof(struct ubsec_pktctx_des)); ++ ctxdes->pc_type = ctx.pc_type; ++ ctxdes->pc_flags = ctx.pc_flags; ++ ctxdes->pc_offset = ctx.pc_offset; ++ for (i = 0; i < 6; i++) ++ ctxdes->pc_deskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxdes->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxdes->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ ctxdes->pc_iv[0] = ctx.pc_iv[0]; ++ ctxdes->pc_iv[1] = ctx.pc_iv[1]; ++ } ++ } else ++ { ++ /* old Broadcom card with fixed small command context structure */ ++ ++ /* ++ * [3]DES / MD5_HMAC / SHA1_HMAC ++ */ ++ struct ubsec_pktctx *ctxs; ++ ++ ctxs = (struct ubsec_pktctx *)(dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ /* transform generic context into small context */ ++ for (i = 0; i < 6; i++) ++ ctxs->pc_deskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxs->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxs->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ ctxs->pc_iv[0] = ctx.pc_iv[0]; ++ ctxs->pc_iv[1] = ctx.pc_iv[1]; ++ ctxs->pc_flags = ctx.pc_flags; ++ ctxs->pc_offset = ctx.pc_offset; ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_lock_irqsave\n"); ++#endif ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ //spin_lock_irq(&sc->sc_ringmtx); ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); ++ sc->sc_nqueue++; ++ ubsecstats.hst_ipackets++; ++ ubsecstats.hst_ibytes += stheend; ++ ubsec_feed(sc); ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_unlock_irqrestore\n"); ++#endif ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ //spin_unlock_irq(&sc->sc_ringmtx); ++ ++ return (0); ++ ++errout: ++ if (q != NULL) { ++#ifdef NOTYET ++ if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) ++ m_freem(q->q_dst_m); ++#endif ++ ++ if ((q->q_has_dst == 1) && q->q_dst_len > 0) { ++#if 0 ++ bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); ++ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); ++#endif ++ dma_unmap(sc, q->q_dst_map, q->q_dst_len); ++ } ++ if (q->q_src_len > 0) { ++#if 0 ++ bus_dmamap_unload(sc->sc_dmat, q->q_src_map); ++ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); ++#endif ++ dma_unmap(sc, q->q_src_map, q->q_src_len); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_lock_irqsave\n"); ++#endif ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ //spin_lock_irq(&sc->sc_ringmtx); ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_unlock_irqrestore\n"); ++#endif ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ //spin_unlock_irq(&sc->sc_ringmtx); ++ ++ } ++ if (err == EINVAL) ++ ubsecstats.hst_invalid++; ++ else ++ ubsecstats.hst_nomem++; ++errout2: ++ crp->crp_etype = err; ++ crypto_done(crp); ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s() err = %x\n", __FUNCTION__, err); ++#endif ++ ++ return (0); ++} ++ ++void ++ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) ++{ ++ struct cryptop *crp = (struct cryptop *)q->q_crp; ++ struct cryptodesc *crd; ++ struct ubsec_dma *dmap = q->q_dma; ++ int ivsize = 8; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ ubsecstats.hst_opackets++; ++ ubsecstats.hst_obytes += dmap->d_alloc.dma_size; ++ ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, ++ dmap->d_alloc.dma_map->dm_mapsize, ++ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); ++ if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { ++ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, ++ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); ++ bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); ++ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); ++ } ++ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, ++ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_unload(sc->sc_dmat, q->q_src_map); ++ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); ++#endif ++ ++ if ((q->q_has_dst == 1) && q->q_dst_len > 0) ++ dma_unmap(sc, q->q_dst_map, q->q_dst_len); ++ ++ dma_unmap(sc, q->q_src_map, q->q_src_len); ++ ++#ifdef NOTYET ++ if ((crp->crp_flags & CRYPTO_F_SKBUF) && (q->q_src_m != q->q_dst_m)) { ++ m_freem(q->q_src_m); ++ crp->crp_buf = (caddr_t)q->q_dst_m; ++ } ++#endif ++ ++ /* copy out IV for future use */ ++ if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ if (crd->crd_alg != CRYPTO_DES_CBC && ++ crd->crd_alg != CRYPTO_3DES_CBC && ++ crd->crd_alg != CRYPTO_AES_CBC) ++ continue; ++ ++ if (crd->crd_alg == CRYPTO_AES_CBC) ++ ivsize = 16; ++ else ++ ivsize = 8; ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) ++#if 0 ++ m_copydata((struct sk_buff *)crp->crp_buf, ++ crd->crd_skip + crd->crd_len - 8, 8, ++ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); ++#endif ++ crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf, ++ crd->crd_skip + crd->crd_len - ivsize, ivsize, ++ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); ++ ++ else if (crp->crp_flags & CRYPTO_F_IOV) { ++#if 0 ++ cuio_copydata((struct uio *)crp->crp_buf, ++ crd->crd_skip + crd->crd_len - 8, 8, ++ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); ++#endif ++ crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf, ++ crd->crd_skip + crd->crd_len - ivsize, ivsize, ++ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); ++ ++ } ++ break; ++ } ++ } ++ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ if (crd->crd_alg != CRYPTO_MD5_HMAC && ++ crd->crd_alg != CRYPTO_SHA1_HMAC) ++ continue; ++#if 0 ++ if (crp->crp_flags & CRYPTO_F_SKBUF) ++ m_copyback((struct sk_buff *)crp->crp_buf, ++ crd->crd_inject, 12, ++ dmap->d_dma->d_macbuf); ++#endif ++#if 0 ++ /* BUG? it does not honor the mac len.. */ ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, 12, ++ (caddr_t)dmap->d_dma->d_macbuf); ++#endif ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ++ sc->sc_sessions[q->q_sesn].ses_mlen, ++ (caddr_t)dmap->d_dma->d_macbuf); ++#if 0 ++ else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) ++ bcopy((caddr_t)dmap->d_dma->d_macbuf, ++ crp->crp_mac, 12); ++#endif ++ break; ++ } ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); ++ crypto_done(crp); ++} ++ ++void ++ubsec_mcopy(struct sk_buff *srcm, struct sk_buff *dstm, int hoffset, int toffset) ++{ ++ int i, j, dlen, slen; ++ caddr_t dptr, sptr; ++ ++ j = 0; ++ sptr = srcm->data; ++ slen = srcm->len; ++ dptr = dstm->data; ++ dlen = dstm->len; ++ ++ while (1) { ++ for (i = 0; i < min(slen, dlen); i++) { ++ if (j < hoffset || j >= toffset) ++ *dptr++ = *sptr++; ++ slen--; ++ dlen--; ++ j++; ++ } ++ if (slen == 0) { ++ srcm = srcm->next; ++ if (srcm == NULL) ++ return; ++ sptr = srcm->data; ++ slen = srcm->len; ++ } ++ if (dlen == 0) { ++ dstm = dstm->next; ++ if (dstm == NULL) ++ return; ++ dptr = dstm->data; ++ dlen = dstm->len; ++ } ++ } ++} ++ ++int ++ubsec_dma_malloc(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma, ++ size_t size, int mapflags) ++{ ++ dma->dma_vaddr = dma_alloc_coherent(sc->sc_dv, ++ size, &dma->dma_paddr, GFP_KERNEL); ++ ++ if (likely(dma->dma_vaddr)) ++ { ++ dma->dma_size = size; ++ return (0); ++ } ++ ++ DPRINTF("could not allocate %d bytes of coherent memory.\n", size); ++ ++ return (1); ++} ++ ++void ++ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) ++{ ++ dma_free_coherent(sc->sc_dv, dma->dma_size, dma->dma_vaddr, ++ dma->dma_paddr); ++} ++ ++/* ++ * Resets the board. Values in the regesters are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++void ++ubsec_reset_board(struct ubsec_softc *sc) ++{ ++ volatile u_int32_t ctrl; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ DPRINTF("Send reset signal to chip.\n"); ++ ++ ctrl = READ_REG(sc, BS_CTRL); ++ ctrl |= BS_CTRL_RESET; ++ WRITE_REG(sc, BS_CTRL, ctrl); ++ ++ /* ++ * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us ++ */ ++ DELAY(10); ++} ++ ++/* ++ * Init Broadcom registers ++ */ ++void ++ubsec_init_board(struct ubsec_softc *sc) ++{ ++ u_int32_t ctrl; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ DPRINTF("Initialize chip.\n"); ++ ++ ctrl = READ_REG(sc, BS_CTRL); ++ ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); ++ ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT | BS_CTRL_DMAERR; ++ ++ WRITE_REG(sc, BS_CTRL, ctrl); ++ ++ /* Set chip capabilities (BCM5365P) */ ++ sc->sc_flags |= UBS_FLAGS_LONGCTX | UBS_FLAGS_AES; ++} ++ ++/* ++ * Clean up after a chip crash. ++ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). ++ */ ++void ++ubsec_cleanchip(struct ubsec_softc *sc) ++{ ++ struct ubsec_q *q; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ DPRINTF("Clean up queues after chip crash.\n"); ++ ++ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip); ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); ++ ubsec_free_q(sc, q); ++ } ++} ++ ++/* ++ * free a ubsec_q ++ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). ++ */ ++int ++ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) ++{ ++ struct ubsec_q *q2; ++ struct cryptop *crp; ++ int npkts; ++ int i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ npkts = q->q_nstacked_mcrs; ++ ++ for (i = 0; i < npkts; i++) { ++ if(q->q_stacked_mcr[i]) { ++ q2 = q->q_stacked_mcr[i]; ++ ++ if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) ++#ifdef NOTYET ++ m_freem(q2->q_dst_m); ++#else ++ printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__); ++#endif ++ ++ crp = (struct cryptop *)q2->q_crp; ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); ++ ++ crp->crp_etype = EFAULT; ++ crypto_done(crp); ++ } else { ++ break; ++ } ++ } ++ ++ /* ++ * Free header MCR ++ */ ++ if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) ++#ifdef NOTYET ++ m_freem(q->q_dst_m); ++#else ++ printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__); ++#endif ++ ++ crp = (struct cryptop *)q->q_crp; ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); ++ ++ crp->crp_etype = EFAULT; ++ crypto_done(crp); ++ return(0); ++} ++ ++/* ++ * Routine to reset the chip and clean up. ++ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). ++ */ ++void ++ubsec_totalreset(struct ubsec_softc *sc) ++{ ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ DPRINTF("initiate total chip reset.. \n"); ++ ubsec_reset_board(sc); ++ ubsec_init_board(sc); ++ ubsec_cleanchip(sc); ++} ++ ++void ++ubsec_dump_pb(struct ubsec_pktbuf *pb) ++{ ++ printf("addr 0x%x (0x%x) next 0x%x\n", ++ pb->pb_addr, pb->pb_len, pb->pb_next); ++} ++ ++void ++ubsec_dump_mcr(struct ubsec_mcr *mcr) ++{ ++ struct ubsec_mcr_add *ma; ++ int i; ++ ++ printf("MCR:\n"); ++ printf(" pkts: %u, flags 0x%x\n", ++ letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); ++ ma = (struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; ++ for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { ++ printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, ++ letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), ++ letoh16(ma->mcr_reserved)); ++ printf(" %d: ipkt ", i); ++ ubsec_dump_pb(&ma->mcr_ipktbuf); ++ printf(" %d: opkt ", i); ++ ubsec_dump_pb(&ma->mcr_opktbuf); ++ ma++; ++ } ++ printf("END MCR\n"); ++} ++ ++static int __init mod_init(void) { ++ return ssb_driver_register(&ubsec_ssb_driver); ++} ++ ++static void __exit mod_exit(void) { ++ ssb_driver_unregister(&ubsec_ssb_driver); ++} ++ ++module_init(mod_init); ++module_exit(mod_exit); ++ ++// Meta information ++MODULE_AUTHOR("Daniel Mueller "); ++MODULE_LICENSE("BSD"); ++MODULE_DESCRIPTION("OCF driver for BCM5365P IPSec Core"); ++MODULE_VERSION(DRV_MODULE_VERSION); ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecreg.h linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecreg.h +--- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecreg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecreg.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,233 @@ ++ ++/* ++ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) ++ * Copyright (c) 2000 Theo de Raadt ++ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++/* ++ * Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband ++ * Security "uBSec" chip. Definitions from revision 2.8 of the product ++ * datasheet. ++ */ ++ ++#define BS_BAR 0x10 /* DMA base address register */ ++#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ ++#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ ++ ++#define UBS_PCI_RTY_SHIFT 8 ++#define UBS_PCI_RTY_MASK 0xff ++#define UBS_PCI_RTY(misc) \ ++ (((misc) >> UBS_PCI_RTY_SHIFT) & UBS_PCI_RTY_MASK) ++ ++#define UBS_PCI_TOUT_SHIFT 0 ++#define UBS_PCI_TOUT_MASK 0xff ++#define UBS_PCI_TOUT(misc) \ ++ (((misc) >> PCI_TOUT_SHIFT) & PCI_TOUT_MASK) ++ ++/* ++ * DMA Control & Status Registers (offset from BS_BAR) ++ */ ++#define BS_MCR1 0x20 /* DMA Master Command Record 1 */ ++#define BS_CTRL 0x24 /* DMA Control */ ++#define BS_STAT 0x28 /* DMA Status */ ++#define BS_ERR 0x2c /* DMA Error Address */ ++#define BS_DEV_ID 0x34 /* IPSec Device ID */ ++ ++/* BS_CTRL - DMA Control */ ++#define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */ ++#define BS_CTRL_MCR2INT 0x40000000 /* enable intr MCR for MCR2 */ ++#define BS_CTRL_MCR1INT 0x20000000 /* enable intr MCR for MCR1 */ ++#define BS_CTRL_OFM 0x10000000 /* Output fragment mode */ ++#define BS_CTRL_BE32 0x08000000 /* big-endian, 32bit bytes */ ++#define BS_CTRL_BE64 0x04000000 /* big-endian, 64bit bytes */ ++#define BS_CTRL_DMAERR 0x02000000 /* enable intr DMA error */ ++#define BS_CTRL_RNG_M 0x01800000 /* RNG mode */ ++#define BS_CTRL_RNG_1 0x00000000 /* 1bit rn/one slow clock */ ++#define BS_CTRL_RNG_4 0x00800000 /* 1bit rn/four slow clocks */ ++#define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */ ++#define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */ ++#define BS_CTRL_SWNORM 0x00400000 /* 582[01], sw normalization */ ++#define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */ ++#define BS_CTRL_LITTLE_ENDIAN (BS_CTRL_BE32 | BS_CTRL_BE64) ++ ++/* BS_STAT - DMA Status */ ++#define BS_STAT_MCR1_BUSY 0x80000000 /* MCR1 is busy */ ++#define BS_STAT_MCR1_FULL 0x40000000 /* MCR1 is full */ ++#define BS_STAT_MCR1_DONE 0x20000000 /* MCR1 is done */ ++#define BS_STAT_DMAERR 0x10000000 /* DMA error */ ++#define BS_STAT_MCR2_FULL 0x08000000 /* MCR2 is full */ ++#define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */ ++#define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* 5821, MCR1 is empty */ ++#define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* 5821, MCR2 is empty */ ++ ++/* BS_ERR - DMA Error Address */ ++#define BS_ERR_ADDR 0xfffffffc /* error address mask */ ++#define BS_ERR_READ 0x00000002 /* fault was on read */ ++ ++struct ubsec_pktctx { ++ u_int32_t pc_deskey[6]; /* 3DES key */ ++ u_int32_t pc_hminner[5]; /* hmac inner state */ ++ u_int32_t pc_hmouter[5]; /* hmac outer state */ ++ u_int32_t pc_iv[2]; /* [3]DES iv */ ++ u_int16_t pc_flags; /* flags, below */ ++ u_int16_t pc_offset; /* crypto offset */ ++} __attribute__ ((packed)); ++ ++#define UBS_PKTCTX_ENC_3DES 0x8000 /* use 3des */ ++#define UBS_PKTCTX_ENC_AES 0x8000 /* use aes */ ++#define UBS_PKTCTX_ENC_NONE 0x0000 /* no encryption */ ++#define UBS_PKTCTX_INBOUND 0x4000 /* inbound packet */ ++#define UBS_PKTCTX_AUTH 0x3000 /* authentication mask */ ++#define UBS_PKTCTX_AUTH_NONE 0x0000 /* no authentication */ ++#define UBS_PKTCTX_AUTH_MD5 0x1000 /* use hmac-md5 */ ++#define UBS_PKTCTX_AUTH_SHA1 0x2000 /* use hmac-sha1 */ ++#define UBS_PKTCTX_AES128 0x0 /* AES 128bit keys */ ++#define UBS_PKTCTX_AES192 0x100 /* AES 192bit keys */ ++#define UBS_PKTCTX_AES256 0x200 /* AES 256bit keys */ ++ ++struct ubsec_pktctx_des { ++ volatile u_int16_t pc_len; /* length of ctx struct */ ++ volatile u_int16_t pc_type; /* context type */ ++ volatile u_int16_t pc_flags; /* flags, same as above */ ++ volatile u_int16_t pc_offset; /* crypto/auth offset */ ++ volatile u_int32_t pc_deskey[6]; /* 3DES key */ ++ volatile u_int32_t pc_iv[2]; /* [3]DES iv */ ++ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ ++ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ ++} __attribute__ ((packed)); ++ ++struct ubsec_pktctx_aes128 { ++ volatile u_int16_t pc_len; /* length of ctx struct */ ++ volatile u_int16_t pc_type; /* context type */ ++ volatile u_int16_t pc_flags; /* flags, same as above */ ++ volatile u_int16_t pc_offset; /* crypto/auth offset */ ++ volatile u_int32_t pc_aeskey[4]; /* AES 128bit key */ ++ volatile u_int32_t pc_iv[4]; /* AES iv */ ++ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ ++ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ ++} __attribute__ ((packed)); ++ ++struct ubsec_pktctx_aes192 { ++ volatile u_int16_t pc_len; /* length of ctx struct */ ++ volatile u_int16_t pc_type; /* context type */ ++ volatile u_int16_t pc_flags; /* flags, same as above */ ++ volatile u_int16_t pc_offset; /* crypto/auth offset */ ++ volatile u_int32_t pc_aeskey[6]; /* AES 192bit key */ ++ volatile u_int32_t pc_iv[4]; /* AES iv */ ++ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ ++ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ ++} __attribute__ ((packed)); ++ ++struct ubsec_pktctx_aes256 { ++ volatile u_int16_t pc_len; /* length of ctx struct */ ++ volatile u_int16_t pc_type; /* context type */ ++ volatile u_int16_t pc_flags; /* flags, same as above */ ++ volatile u_int16_t pc_offset; /* crypto/auth offset */ ++ volatile u_int32_t pc_aeskey[8]; /* AES 256bit key */ ++ volatile u_int32_t pc_iv[4]; /* AES iv */ ++ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ ++ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ ++} __attribute__ ((packed)); ++ ++#define UBS_PKTCTX_TYPE_IPSEC_DES 0x0000 ++#define UBS_PKTCTX_TYPE_IPSEC_AES 0x0040 ++ ++struct ubsec_pktbuf { ++ volatile u_int32_t pb_addr; /* address of buffer start */ ++ volatile u_int32_t pb_next; /* pointer to next pktbuf */ ++ volatile u_int32_t pb_len; /* packet length */ ++} __attribute__ ((packed)); ++#define UBS_PKTBUF_LEN 0x0000ffff /* length mask */ ++ ++struct ubsec_mcr { ++ volatile u_int16_t mcr_pkts; /* #pkts in this mcr */ ++ volatile u_int16_t mcr_flags; /* mcr flags (below) */ ++ volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ ++ struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ ++ volatile u_int16_t mcr_reserved; ++ volatile u_int16_t mcr_pktlen; ++ struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ ++} __attribute__ ((packed)); ++ ++struct ubsec_mcr_add { ++ volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ ++ struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ ++ volatile u_int16_t mcr_reserved; ++ volatile u_int16_t mcr_pktlen; ++ struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ ++} __attribute__ ((packed)); ++ ++#define UBS_MCR_DONE 0x0001 /* mcr has been processed */ ++#define UBS_MCR_ERROR 0x0002 /* error in processing */ ++#define UBS_MCR_ERRORCODE 0xff00 /* error type */ ++ ++struct ubsec_ctx_keyop { ++ volatile u_int16_t ctx_len; /* command length */ ++ volatile u_int16_t ctx_op; /* operation code */ ++ volatile u_int8_t ctx_pad[60]; /* padding */ ++} __attribute__ ((packed)); ++#define UBS_CTXOP_DHPKGEN 0x01 /* dh public key generation */ ++#define UBS_CTXOP_DHSSGEN 0x02 /* dh shared secret gen. */ ++#define UBS_CTXOP_RSAPUB 0x03 /* rsa public key op */ ++#define UBS_CTXOP_RSAPRIV 0x04 /* rsa private key op */ ++#define UBS_CTXOP_DSASIGN 0x05 /* dsa signing op */ ++#define UBS_CTXOP_DSAVRFY 0x06 /* dsa verification */ ++#define UBS_CTXOP_RNGBYPASS 0x41 /* rng direct test mode */ ++#define UBS_CTXOP_RNGSHA1 0x42 /* rng sha1 test mode */ ++#define UBS_CTXOP_MODADD 0x43 /* modular addition */ ++#define UBS_CTXOP_MODSUB 0x44 /* modular subtraction */ ++#define UBS_CTXOP_MODMUL 0x45 /* modular multiplication */ ++#define UBS_CTXOP_MODRED 0x46 /* modular reduction */ ++#define UBS_CTXOP_MODEXP 0x47 /* modular exponentiation */ ++#define UBS_CTXOP_MODINV 0x48 /* modular inverse */ ++ ++struct ubsec_ctx_rngbypass { ++ volatile u_int16_t rbp_len; /* command length, 64 */ ++ volatile u_int16_t rbp_op; /* rng bypass, 0x41 */ ++ volatile u_int8_t rbp_pad[60]; /* padding */ ++} __attribute__ ((packed)); ++ ++/* modexp: C = (M ^ E) mod N */ ++struct ubsec_ctx_modexp { ++ volatile u_int16_t me_len; /* command length */ ++ volatile u_int16_t me_op; /* modexp, 0x47 */ ++ volatile u_int16_t me_E_len; /* E (bits) */ ++ volatile u_int16_t me_N_len; /* N (bits) */ ++ u_int8_t me_N[2048/8]; /* N */ ++} __attribute__ ((packed)); ++ ++struct ubsec_ctx_rsapriv { ++ volatile u_int16_t rpr_len; /* command length */ ++ volatile u_int16_t rpr_op; /* rsaprivate, 0x04 */ ++ volatile u_int16_t rpr_q_len; /* q (bits) */ ++ volatile u_int16_t rpr_p_len; /* p (bits) */ ++ u_int8_t rpr_buf[5 * 1024 / 8]; /* parameters: */ ++ /* p, q, dp, dq, pinv */ ++} __attribute__ ((packed)); +diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecvar.h linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecvar.h +--- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecvar.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecvar.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,228 @@ ++ ++/* ++ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) ++ * Copyright (c) 2000 Theo de Raadt ++ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++/* Maximum queue length */ ++#ifndef UBS_MAX_NQUEUE ++#define UBS_MAX_NQUEUE 60 ++#endif ++ ++#define UBS_MAX_SCATTER 64 /* Maximum scatter/gather depth */ ++ ++#ifndef UBS_MAX_AGGR ++#define UBS_MAX_AGGR 5 /* Maximum aggregation count */ ++#endif ++ ++#define UBSEC_CARD(sid) (((sid) & 0xf0000000) >> 28) ++#define UBSEC_SESSION(sid) ( (sid) & 0x0fffffff) ++#define UBSEC_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) ++ ++#define UBS_DEF_RTY 0xff /* PCI Retry Timeout */ ++#define UBS_DEF_TOUT 0xff /* PCI TRDY Timeout */ ++#define UBS_DEF_CACHELINE 0x01 /* Cache Line setting */ ++ ++#define DEFAULT_HMAC_LEN 12 ++ ++struct ubsec_dma_alloc { ++ dma_addr_t dma_paddr; ++ void *dma_vaddr; ++ /* ++ bus_dmamap_t dma_map; ++ bus_dma_segment_t dma_seg; ++ */ ++ size_t dma_size; ++ /* ++ int dma_nseg; ++ */ ++}; ++ ++struct ubsec_q2 { ++ BSD_SIMPLEQ_ENTRY(ubsec_q2) q_next; ++ struct ubsec_dma_alloc q_mcr; ++ struct ubsec_dma_alloc q_ctx; ++ u_int q_type; ++}; ++ ++struct ubsec_q2_rng { ++ struct ubsec_q2 rng_q; ++ struct ubsec_dma_alloc rng_buf; ++ int rng_used; ++}; ++ ++/* C = (M ^ E) mod N */ ++#define UBS_MODEXP_PAR_M 0 ++#define UBS_MODEXP_PAR_E 1 ++#define UBS_MODEXP_PAR_N 2 ++struct ubsec_q2_modexp { ++ struct ubsec_q2 me_q; ++ struct cryptkop * me_krp; ++ struct ubsec_dma_alloc me_M; ++ struct ubsec_dma_alloc me_E; ++ struct ubsec_dma_alloc me_C; ++ struct ubsec_dma_alloc me_epb; ++ int me_modbits; ++ int me_shiftbits; ++ int me_normbits; ++}; ++ ++#define UBS_RSAPRIV_PAR_P 0 ++#define UBS_RSAPRIV_PAR_Q 1 ++#define UBS_RSAPRIV_PAR_DP 2 ++#define UBS_RSAPRIV_PAR_DQ 3 ++#define UBS_RSAPRIV_PAR_PINV 4 ++#define UBS_RSAPRIV_PAR_MSGIN 5 ++#define UBS_RSAPRIV_PAR_MSGOUT 6 ++struct ubsec_q2_rsapriv { ++ struct ubsec_q2 rpr_q; ++ struct cryptkop * rpr_krp; ++ struct ubsec_dma_alloc rpr_msgin; ++ struct ubsec_dma_alloc rpr_msgout; ++}; ++ ++#define UBSEC_RNG_BUFSIZ 16 /* measured in 32bit words */ ++ ++struct ubsec_dmachunk { ++ struct ubsec_mcr d_mcr; ++ struct ubsec_mcr_add d_mcradd[UBS_MAX_AGGR-1]; ++ struct ubsec_pktbuf d_sbuf[UBS_MAX_SCATTER-1]; ++ struct ubsec_pktbuf d_dbuf[UBS_MAX_SCATTER-1]; ++ u_int32_t d_macbuf[5]; ++ union { ++ struct ubsec_pktctx_aes256 ctxaes256; ++ struct ubsec_pktctx_aes192 ctxaes192; ++ struct ubsec_pktctx_des ctxdes; ++ struct ubsec_pktctx_aes128 ctxaes128; ++ struct ubsec_pktctx ctx; ++ } d_ctx; ++}; ++ ++struct ubsec_dma { ++ BSD_SIMPLEQ_ENTRY(ubsec_dma) d_next; ++ struct ubsec_dmachunk *d_dma; ++ struct ubsec_dma_alloc d_alloc; ++}; ++ ++#define UBS_FLAGS_KEY 0x01 /* has key accelerator */ ++#define UBS_FLAGS_LONGCTX 0x02 /* uses long ipsec ctx */ ++#define UBS_FLAGS_BIGKEY 0x04 /* 2048bit keys */ ++#define UBS_FLAGS_HWNORM 0x08 /* hardware normalization */ ++#define UBS_FLAGS_RNG 0x10 /* hardware rng */ ++#define UBS_FLAGS_AES 0x20 /* hardware AES support */ ++ ++struct ubsec_q { ++ BSD_SIMPLEQ_ENTRY(ubsec_q) q_next; ++ int q_nstacked_mcrs; ++ struct ubsec_q *q_stacked_mcr[UBS_MAX_AGGR-1]; ++ struct cryptop *q_crp; ++ struct ubsec_dma *q_dma; ++ ++ //struct mbuf *q_src_m, *q_dst_m; ++ struct sk_buff *q_src_m, *q_dst_m; ++ struct uio *q_src_io, *q_dst_io; ++ ++ /* ++ bus_dmamap_t q_src_map; ++ bus_dmamap_t q_dst_map; ++ */ ++ ++ /* DMA addresses for In-/Out packages */ ++ int q_src_len; ++ int q_dst_len; ++ struct ubsec_dma_alloc q_src_map[UBS_MAX_SCATTER]; ++ struct ubsec_dma_alloc q_dst_map[UBS_MAX_SCATTER]; ++ int q_has_dst; ++ ++ int q_sesn; ++ int q_flags; ++}; ++ ++struct ubsec_softc { ++ softc_device_decl sc_dev; ++ struct ssb_device *sdev; /* device backpointer */ ++ ++ struct device *sc_dv; /* generic device */ ++ void *sc_ih; /* interrupt handler cookie */ ++ int sc_flags; /* device specific flags */ ++ u_int32_t sc_statmask; /* interrupt status mask */ ++ int32_t sc_cid; /* crypto tag */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_queue; /* packet queue, mcr1 */ ++ int sc_nqueue; /* count enqueued, mcr1 */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_qchip; /* on chip, mcr1 */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_freequeue; /* list of free queue elements */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_queue2; /* packet queue, mcr2 */ ++ int sc_nqueue2; /* count enqueued, mcr2 */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2; /* on chip, mcr2 */ ++ int sc_nsessions; /* # of sessions */ ++ struct ubsec_session *sc_sessions; /* sessions */ ++ int sc_rnghz; /* rng poll time */ ++ struct ubsec_q2_rng sc_rng; ++ struct ubsec_dma sc_dmaa[UBS_MAX_NQUEUE]; ++ struct ubsec_q *sc_queuea[UBS_MAX_NQUEUE]; ++ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_q2free; /* free list */ ++ spinlock_t sc_ringmtx; /* PE ring lock */ ++}; ++ ++#define UBSEC_QFLAGS_COPYOUTIV 0x1 ++ ++struct ubsec_session { ++ u_int32_t ses_used; ++ u_int32_t ses_key[8]; /* 3DES/AES key */ ++ u_int32_t ses_hminner[5]; /* hmac inner state */ ++ u_int32_t ses_hmouter[5]; /* hmac outer state */ ++ u_int32_t ses_iv[4]; /* [3]DES/AES iv */ ++ u_int32_t ses_keysize; /* AES key size */ ++ u_int32_t ses_mlen; /* hmac/hash length */ ++}; ++ ++struct ubsec_stats { ++ u_int64_t hst_ibytes; ++ u_int64_t hst_obytes; ++ u_int32_t hst_ipackets; ++ u_int32_t hst_opackets; ++ u_int32_t hst_invalid; ++ u_int32_t hst_nomem; ++ u_int32_t hst_queuefull; ++ u_int32_t hst_dmaerr; ++ u_int32_t hst_mcrerr; ++ u_int32_t hst_nodmafree; ++}; ++ ++struct ubsec_generic_ctx { ++ u_int32_t pc_key[8]; /* [3]DES/AES key */ ++ u_int32_t pc_hminner[5]; /* hmac inner state */ ++ u_int32_t pc_hmouter[5]; /* hmac outer state */ ++ u_int32_t pc_iv[4]; /* [3]DES/AES iv */ ++ u_int16_t pc_flags; /* flags, below */ ++ u_int16_t pc_offset; /* crypto offset */ ++ u_int16_t pc_type; /* Cryptographic operation */ ++}; ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/uio.h linux-3.0.4/crypto/ocf/uio.h +--- linux-3.0.4.orig/crypto/ocf/uio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/uio.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,54 @@ ++#ifndef _OCF_UIO_H_ ++#define _OCF_UIO_H_ ++ ++#include ++ ++/* ++ * The linux uio.h doesn't have all we need. To be fully api compatible ++ * with the BSD cryptodev, we need to keep this around. Perhaps this can ++ * be moved back into the linux/uio.h ++ * ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ * --------------------------------------------------------------------------- ++ */ ++ ++struct uio { ++ struct iovec *uio_iov; ++ int uio_iovcnt; ++ off_t uio_offset; ++ int uio_resid; ++#if 0 ++ enum uio_seg uio_segflg; ++ enum uio_rw uio_rw; ++ struct thread *uio_td; ++#endif ++}; ++ ++#endif +diff -Nur linux-3.0.4.orig/drivers/char/random.c linux-3.0.4/drivers/char/random.c +--- linux-3.0.4.orig/drivers/char/random.c 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/drivers/char/random.c 2011-10-17 04:36:27.356574299 +0200 +@@ -130,6 +130,9 @@ + * void add_interrupt_randomness(int irq); + * void add_disk_randomness(struct gendisk *disk); + * ++ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++ * int random_input_wait(void); ++ * + * add_input_randomness() uses the input layer interrupt timing, as well as + * the event type information from the hardware. + * +@@ -147,6 +150,13 @@ + * seek times do not make for good sources of entropy, as their seek + * times are usually fairly consistent. + * ++ * random_input_words() just provides a raw block of entropy to the input ++ * pool, such as from a hardware entropy generator. ++ * ++ * random_input_wait() suspends the caller until such time as the ++ * entropy pool falls below the write threshold, and returns a count of how ++ * much entropy (in bits) is needed to sustain the pool. ++ * + * All of these routines try to estimate how many bits of randomness a + * particular randomness source. They do this by keeping track of the + * first and second order deltas of the event timings. +@@ -722,6 +732,63 @@ + } + #endif + ++/* ++ * random_input_words - add bulk entropy to pool ++ * ++ * @buf: buffer to add ++ * @wordcount: number of __u32 words to add ++ * @ent_count: total amount of entropy (in bits) to credit ++ * ++ * this provides bulk input of entropy to the input pool ++ * ++ */ ++void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++{ ++ mix_pool_bytes(&input_pool, buf, wordcount*4); ++ ++ credit_entropy_bits(&input_pool, ent_count); ++ ++ DEBUG_ENT("crediting %d bits => %d\n", ++ ent_count, input_pool.entropy_count); ++ /* ++ * Wake up waiting processes if we have enough ++ * entropy. ++ */ ++ if (input_pool.entropy_count >= random_read_wakeup_thresh) ++ wake_up_interruptible(&random_read_wait); ++} ++EXPORT_SYMBOL(random_input_words); ++ ++/* ++ * random_input_wait - wait until random needs entropy ++ * ++ * this function sleeps until the /dev/random subsystem actually ++ * needs more entropy, and then return the amount of entropy ++ * that it would be nice to have added to the system. ++ */ ++int random_input_wait(void) ++{ ++ int count; ++ ++ wait_event_interruptible(random_write_wait, ++ input_pool.entropy_count < random_write_wakeup_thresh); ++ ++ count = random_write_wakeup_thresh - input_pool.entropy_count; ++ ++ /* likely we got woken up due to a signal */ ++ if (count <= 0) count = random_read_wakeup_thresh; ++ ++ DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n", ++ count, ++ input_pool.entropy_count, random_write_wakeup_thresh); ++ ++ return count; ++} ++EXPORT_SYMBOL(random_input_wait); ++ ++ ++#define EXTRACT_SIZE 10 ++ + /********************************************************************* + * + * Entropy extraction routines +diff -Nur linux-3.0.4.orig/drivers/char/random.c.orig linux-3.0.4/drivers/char/random.c.orig +--- linux-3.0.4.orig/drivers/char/random.c.orig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/drivers/char/random.c.orig 2011-08-29 22:56:30.000000000 +0200 +@@ -0,0 +1,1349 @@ ++/* ++ * random.c -- A strong random number generator ++ * ++ * Copyright Matt Mackall , 2003, 2004, 2005 ++ * ++ * Copyright Theodore Ts'o, 1994, 1995, 1996, 1997, 1998, 1999. All ++ * rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, and the entire permission notice in its entirety, ++ * including the disclaimer of warranties. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote ++ * products derived from this software without specific prior ++ * written permission. ++ * ++ * ALTERNATIVELY, this product may be distributed under the terms of ++ * the GNU General Public License, in which case the provisions of the GPL are ++ * required INSTEAD OF the above restrictions. (This clause is ++ * necessary due to a potential bad interaction between the GPL and ++ * the restrictions contained in a BSD-style copyright.) ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ALL OF ++ * WHICH ARE HEREBY DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ++ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ++ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF NOT ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ */ ++ ++/* ++ * (now, with legal B.S. out of the way.....) ++ * ++ * This routine gathers environmental noise from device drivers, etc., ++ * and returns good random numbers, suitable for cryptographic use. ++ * Besides the obvious cryptographic uses, these numbers are also good ++ * for seeding TCP sequence numbers, and other places where it is ++ * desirable to have numbers which are not only random, but hard to ++ * predict by an attacker. ++ * ++ * Theory of operation ++ * =================== ++ * ++ * Computers are very predictable devices. Hence it is extremely hard ++ * to produce truly random numbers on a computer --- as opposed to ++ * pseudo-random numbers, which can easily generated by using a ++ * algorithm. Unfortunately, it is very easy for attackers to guess ++ * the sequence of pseudo-random number generators, and for some ++ * applications this is not acceptable. So instead, we must try to ++ * gather "environmental noise" from the computer's environment, which ++ * must be hard for outside attackers to observe, and use that to ++ * generate random numbers. In a Unix environment, this is best done ++ * from inside the kernel. ++ * ++ * Sources of randomness from the environment include inter-keyboard ++ * timings, inter-interrupt timings from some interrupts, and other ++ * events which are both (a) non-deterministic and (b) hard for an ++ * outside observer to measure. Randomness from these sources are ++ * added to an "entropy pool", which is mixed using a CRC-like function. ++ * This is not cryptographically strong, but it is adequate assuming ++ * the randomness is not chosen maliciously, and it is fast enough that ++ * the overhead of doing it on every interrupt is very reasonable. ++ * As random bytes are mixed into the entropy pool, the routines keep ++ * an *estimate* of how many bits of randomness have been stored into ++ * the random number generator's internal state. ++ * ++ * When random bytes are desired, they are obtained by taking the SHA ++ * hash of the contents of the "entropy pool". The SHA hash avoids ++ * exposing the internal state of the entropy pool. It is believed to ++ * be computationally infeasible to derive any useful information ++ * about the input of SHA from its output. Even if it is possible to ++ * analyze SHA in some clever way, as long as the amount of data ++ * returned from the generator is less than the inherent entropy in ++ * the pool, the output data is totally unpredictable. For this ++ * reason, the routine decreases its internal estimate of how many ++ * bits of "true randomness" are contained in the entropy pool as it ++ * outputs random numbers. ++ * ++ * If this estimate goes to zero, the routine can still generate ++ * random numbers; however, an attacker may (at least in theory) be ++ * able to infer the future output of the generator from prior ++ * outputs. This requires successful cryptanalysis of SHA, which is ++ * not believed to be feasible, but there is a remote possibility. ++ * Nonetheless, these numbers should be useful for the vast majority ++ * of purposes. ++ * ++ * Exported interfaces ---- output ++ * =============================== ++ * ++ * There are three exported interfaces; the first is one designed to ++ * be used from within the kernel: ++ * ++ * void get_random_bytes(void *buf, int nbytes); ++ * ++ * This interface will return the requested number of random bytes, ++ * and place it in the requested buffer. ++ * ++ * The two other interfaces are two character devices /dev/random and ++ * /dev/urandom. /dev/random is suitable for use when very high ++ * quality randomness is desired (for example, for key generation or ++ * one-time pads), as it will only return a maximum of the number of ++ * bits of randomness (as estimated by the random number generator) ++ * contained in the entropy pool. ++ * ++ * The /dev/urandom device does not have this limit, and will return ++ * as many bytes as are requested. As more and more random bytes are ++ * requested without giving time for the entropy pool to recharge, ++ * this will result in random numbers that are merely cryptographically ++ * strong. For many applications, however, this is acceptable. ++ * ++ * Exported interfaces ---- input ++ * ============================== ++ * ++ * The current exported interfaces for gathering environmental noise ++ * from the devices are: ++ * ++ * void add_input_randomness(unsigned int type, unsigned int code, ++ * unsigned int value); ++ * void add_interrupt_randomness(int irq); ++ * void add_disk_randomness(struct gendisk *disk); ++ * ++ * add_input_randomness() uses the input layer interrupt timing, as well as ++ * the event type information from the hardware. ++ * ++ * add_interrupt_randomness() uses the inter-interrupt timing as random ++ * inputs to the entropy pool. Note that not all interrupts are good ++ * sources of randomness! For example, the timer interrupts is not a ++ * good choice, because the periodicity of the interrupts is too ++ * regular, and hence predictable to an attacker. Network Interface ++ * Controller interrupts are a better measure, since the timing of the ++ * NIC interrupts are more unpredictable. ++ * ++ * add_disk_randomness() uses what amounts to the seek time of block ++ * layer request events, on a per-disk_devt basis, as input to the ++ * entropy pool. Note that high-speed solid state drives with very low ++ * seek times do not make for good sources of entropy, as their seek ++ * times are usually fairly consistent. ++ * ++ * All of these routines try to estimate how many bits of randomness a ++ * particular randomness source. They do this by keeping track of the ++ * first and second order deltas of the event timings. ++ * ++ * Ensuring unpredictability at system startup ++ * ============================================ ++ * ++ * When any operating system starts up, it will go through a sequence ++ * of actions that are fairly predictable by an adversary, especially ++ * if the start-up does not involve interaction with a human operator. ++ * This reduces the actual number of bits of unpredictability in the ++ * entropy pool below the value in entropy_count. In order to ++ * counteract this effect, it helps to carry information in the ++ * entropy pool across shut-downs and start-ups. To do this, put the ++ * following lines an appropriate script which is run during the boot ++ * sequence: ++ * ++ * echo "Initializing random number generator..." ++ * random_seed=/var/run/random-seed ++ * # Carry a random seed from start-up to start-up ++ * # Load and then save the whole entropy pool ++ * if [ -f $random_seed ]; then ++ * cat $random_seed >/dev/urandom ++ * else ++ * touch $random_seed ++ * fi ++ * chmod 600 $random_seed ++ * dd if=/dev/urandom of=$random_seed count=1 bs=512 ++ * ++ * and the following lines in an appropriate script which is run as ++ * the system is shutdown: ++ * ++ * # Carry a random seed from shut-down to start-up ++ * # Save the whole entropy pool ++ * echo "Saving random seed..." ++ * random_seed=/var/run/random-seed ++ * touch $random_seed ++ * chmod 600 $random_seed ++ * dd if=/dev/urandom of=$random_seed count=1 bs=512 ++ * ++ * For example, on most modern systems using the System V init ++ * scripts, such code fragments would be found in ++ * /etc/rc.d/init.d/random. On older Linux systems, the correct script ++ * location might be in /etc/rcb.d/rc.local or /etc/rc.d/rc.0. ++ * ++ * Effectively, these commands cause the contents of the entropy pool ++ * to be saved at shut-down time and reloaded into the entropy pool at ++ * start-up. (The 'dd' in the addition to the bootup script is to ++ * make sure that /etc/random-seed is different for every start-up, ++ * even if the system crashes without executing rc.0.) Even with ++ * complete knowledge of the start-up activities, predicting the state ++ * of the entropy pool requires knowledge of the previous history of ++ * the system. ++ * ++ * Configuring the /dev/random driver under Linux ++ * ============================================== ++ * ++ * The /dev/random driver under Linux uses minor numbers 8 and 9 of ++ * the /dev/mem major number (#1). So if your system does not have ++ * /dev/random and /dev/urandom created already, they can be created ++ * by using the commands: ++ * ++ * mknod /dev/random c 1 8 ++ * mknod /dev/urandom c 1 9 ++ * ++ * Acknowledgements: ++ * ================= ++ * ++ * Ideas for constructing this random number generator were derived ++ * from Pretty Good Privacy's random number generator, and from private ++ * discussions with Phil Karn. Colin Plumb provided a faster random ++ * number generator, which speed up the mixing function of the entropy ++ * pool, taken from PGPfone. Dale Worley has also contributed many ++ * useful ideas and suggestions to improve this driver. ++ * ++ * Any flaws in the design are solely my responsibility, and should ++ * not be attributed to the Phil, Colin, or any of authors of PGP. ++ * ++ * Further background information on this topic may be obtained from ++ * RFC 1750, "Randomness Recommendations for Security", by Donald ++ * Eastlake, Steve Crocker, and Jeff Schiller. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_GENERIC_HARDIRQS ++# include ++#endif ++ ++#include ++#include ++#include ++#include ++ ++/* ++ * Configuration information ++ */ ++#define INPUT_POOL_WORDS 128 ++#define OUTPUT_POOL_WORDS 32 ++#define SEC_XFER_SIZE 512 ++#define EXTRACT_SIZE 10 ++ ++/* ++ * The minimum number of bits of entropy before we wake up a read on ++ * /dev/random. Should be enough to do a significant reseed. ++ */ ++static int random_read_wakeup_thresh = 64; ++ ++/* ++ * If the entropy count falls under this number of bits, then we ++ * should wake up processes which are selecting or polling on write ++ * access to /dev/random. ++ */ ++static int random_write_wakeup_thresh = 128; ++ ++/* ++ * When the input pool goes over trickle_thresh, start dropping most ++ * samples to avoid wasting CPU time and reduce lock contention. ++ */ ++ ++static int trickle_thresh __read_mostly = INPUT_POOL_WORDS * 28; ++ ++static DEFINE_PER_CPU(int, trickle_count); ++ ++/* ++ * A pool of size .poolwords is stirred with a primitive polynomial ++ * of degree .poolwords over GF(2). The taps for various sizes are ++ * defined below. They are chosen to be evenly spaced (minimum RMS ++ * distance from evenly spaced; the numbers in the comments are a ++ * scaled squared error sum) except for the last tap, which is 1 to ++ * get the twisting happening as fast as possible. ++ */ ++static struct poolinfo { ++ int poolwords; ++ int tap1, tap2, tap3, tap4, tap5; ++} poolinfo_table[] = { ++ /* x^128 + x^103 + x^76 + x^51 +x^25 + x + 1 -- 105 */ ++ { 128, 103, 76, 51, 25, 1 }, ++ /* x^32 + x^26 + x^20 + x^14 + x^7 + x + 1 -- 15 */ ++ { 32, 26, 20, 14, 7, 1 }, ++#if 0 ++ /* x^2048 + x^1638 + x^1231 + x^819 + x^411 + x + 1 -- 115 */ ++ { 2048, 1638, 1231, 819, 411, 1 }, ++ ++ /* x^1024 + x^817 + x^615 + x^412 + x^204 + x + 1 -- 290 */ ++ { 1024, 817, 615, 412, 204, 1 }, ++ ++ /* x^1024 + x^819 + x^616 + x^410 + x^207 + x^2 + 1 -- 115 */ ++ { 1024, 819, 616, 410, 207, 2 }, ++ ++ /* x^512 + x^411 + x^308 + x^208 + x^104 + x + 1 -- 225 */ ++ { 512, 411, 308, 208, 104, 1 }, ++ ++ /* x^512 + x^409 + x^307 + x^206 + x^102 + x^2 + 1 -- 95 */ ++ { 512, 409, 307, 206, 102, 2 }, ++ /* x^512 + x^409 + x^309 + x^205 + x^103 + x^2 + 1 -- 95 */ ++ { 512, 409, 309, 205, 103, 2 }, ++ ++ /* x^256 + x^205 + x^155 + x^101 + x^52 + x + 1 -- 125 */ ++ { 256, 205, 155, 101, 52, 1 }, ++ ++ /* x^128 + x^103 + x^78 + x^51 + x^27 + x^2 + 1 -- 70 */ ++ { 128, 103, 78, 51, 27, 2 }, ++ ++ /* x^64 + x^52 + x^39 + x^26 + x^14 + x + 1 -- 15 */ ++ { 64, 52, 39, 26, 14, 1 }, ++#endif ++}; ++ ++#define POOLBITS poolwords*32 ++#define POOLBYTES poolwords*4 ++ ++/* ++ * For the purposes of better mixing, we use the CRC-32 polynomial as ++ * well to make a twisted Generalized Feedback Shift Reigster ++ * ++ * (See M. Matsumoto & Y. Kurita, 1992. Twisted GFSR generators. ACM ++ * Transactions on Modeling and Computer Simulation 2(3):179-194. ++ * Also see M. Matsumoto & Y. Kurita, 1994. Twisted GFSR generators ++ * II. ACM Transactions on Mdeling and Computer Simulation 4:254-266) ++ * ++ * Thanks to Colin Plumb for suggesting this. ++ * ++ * We have not analyzed the resultant polynomial to prove it primitive; ++ * in fact it almost certainly isn't. Nonetheless, the irreducible factors ++ * of a random large-degree polynomial over GF(2) are more than large enough ++ * that periodicity is not a concern. ++ * ++ * The input hash is much less sensitive than the output hash. All ++ * that we want of it is that it be a good non-cryptographic hash; ++ * i.e. it not produce collisions when fed "random" data of the sort ++ * we expect to see. As long as the pool state differs for different ++ * inputs, we have preserved the input entropy and done a good job. ++ * The fact that an intelligent attacker can construct inputs that ++ * will produce controlled alterations to the pool's state is not ++ * important because we don't consider such inputs to contribute any ++ * randomness. The only property we need with respect to them is that ++ * the attacker can't increase his/her knowledge of the pool's state. ++ * Since all additions are reversible (knowing the final state and the ++ * input, you can reconstruct the initial state), if an attacker has ++ * any uncertainty about the initial state, he/she can only shuffle ++ * that uncertainty about, but never cause any collisions (which would ++ * decrease the uncertainty). ++ * ++ * The chosen system lets the state of the pool be (essentially) the input ++ * modulo the generator polymnomial. Now, for random primitive polynomials, ++ * this is a universal class of hash functions, meaning that the chance ++ * of a collision is limited by the attacker's knowledge of the generator ++ * polynomail, so if it is chosen at random, an attacker can never force ++ * a collision. Here, we use a fixed polynomial, but we *can* assume that ++ * ###--> it is unknown to the processes generating the input entropy. <-### ++ * Because of this important property, this is a good, collision-resistant ++ * hash; hash collisions will occur no more often than chance. ++ */ ++ ++/* ++ * Static global variables ++ */ ++static DECLARE_WAIT_QUEUE_HEAD(random_read_wait); ++static DECLARE_WAIT_QUEUE_HEAD(random_write_wait); ++static struct fasync_struct *fasync; ++ ++#if 0 ++static int debug; ++module_param(debug, bool, 0644); ++#define DEBUG_ENT(fmt, arg...) do { \ ++ if (debug) \ ++ printk(KERN_DEBUG "random %04d %04d %04d: " \ ++ fmt,\ ++ input_pool.entropy_count,\ ++ blocking_pool.entropy_count,\ ++ nonblocking_pool.entropy_count,\ ++ ## arg); } while (0) ++#else ++#define DEBUG_ENT(fmt, arg...) do {} while (0) ++#endif ++ ++/********************************************************************** ++ * ++ * OS independent entropy store. Here are the functions which handle ++ * storing entropy in an entropy pool. ++ * ++ **********************************************************************/ ++ ++struct entropy_store; ++struct entropy_store { ++ /* read-only data: */ ++ struct poolinfo *poolinfo; ++ __u32 *pool; ++ const char *name; ++ struct entropy_store *pull; ++ int limit; ++ ++ /* read-write data: */ ++ spinlock_t lock; ++ unsigned add_ptr; ++ int entropy_count; ++ int input_rotate; ++ __u8 last_data[EXTRACT_SIZE]; ++}; ++ ++static __u32 input_pool_data[INPUT_POOL_WORDS]; ++static __u32 blocking_pool_data[OUTPUT_POOL_WORDS]; ++static __u32 nonblocking_pool_data[OUTPUT_POOL_WORDS]; ++ ++static struct entropy_store input_pool = { ++ .poolinfo = &poolinfo_table[0], ++ .name = "input", ++ .limit = 1, ++ .lock = __SPIN_LOCK_UNLOCKED(&input_pool.lock), ++ .pool = input_pool_data ++}; ++ ++static struct entropy_store blocking_pool = { ++ .poolinfo = &poolinfo_table[1], ++ .name = "blocking", ++ .limit = 1, ++ .pull = &input_pool, ++ .lock = __SPIN_LOCK_UNLOCKED(&blocking_pool.lock), ++ .pool = blocking_pool_data ++}; ++ ++static struct entropy_store nonblocking_pool = { ++ .poolinfo = &poolinfo_table[1], ++ .name = "nonblocking", ++ .pull = &input_pool, ++ .lock = __SPIN_LOCK_UNLOCKED(&nonblocking_pool.lock), ++ .pool = nonblocking_pool_data ++}; ++ ++/* ++ * This function adds bytes into the entropy "pool". It does not ++ * update the entropy estimate. The caller should call ++ * credit_entropy_bits if this is appropriate. ++ * ++ * The pool is stirred with a primitive polynomial of the appropriate ++ * degree, and then twisted. We twist by three bits at a time because ++ * it's cheap to do so and helps slightly in the expected case where ++ * the entropy is concentrated in the low-order bits. ++ */ ++static void mix_pool_bytes_extract(struct entropy_store *r, const void *in, ++ int nbytes, __u8 out[64]) ++{ ++ static __u32 const twist_table[8] = { ++ 0x00000000, 0x3b6e20c8, 0x76dc4190, 0x4db26158, ++ 0xedb88320, 0xd6d6a3e8, 0x9b64c2b0, 0xa00ae278 }; ++ unsigned long i, j, tap1, tap2, tap3, tap4, tap5; ++ int input_rotate; ++ int wordmask = r->poolinfo->poolwords - 1; ++ const char *bytes = in; ++ __u32 w; ++ unsigned long flags; ++ ++ /* Taps are constant, so we can load them without holding r->lock. */ ++ tap1 = r->poolinfo->tap1; ++ tap2 = r->poolinfo->tap2; ++ tap3 = r->poolinfo->tap3; ++ tap4 = r->poolinfo->tap4; ++ tap5 = r->poolinfo->tap5; ++ ++ spin_lock_irqsave(&r->lock, flags); ++ input_rotate = r->input_rotate; ++ i = r->add_ptr; ++ ++ /* mix one byte at a time to simplify size handling and churn faster */ ++ while (nbytes--) { ++ w = rol32(*bytes++, input_rotate & 31); ++ i = (i - 1) & wordmask; ++ ++ /* XOR in the various taps */ ++ w ^= r->pool[i]; ++ w ^= r->pool[(i + tap1) & wordmask]; ++ w ^= r->pool[(i + tap2) & wordmask]; ++ w ^= r->pool[(i + tap3) & wordmask]; ++ w ^= r->pool[(i + tap4) & wordmask]; ++ w ^= r->pool[(i + tap5) & wordmask]; ++ ++ /* Mix the result back in with a twist */ ++ r->pool[i] = (w >> 3) ^ twist_table[w & 7]; ++ ++ /* ++ * Normally, we add 7 bits of rotation to the pool. ++ * At the beginning of the pool, add an extra 7 bits ++ * rotation, so that successive passes spread the ++ * input bits across the pool evenly. ++ */ ++ input_rotate += i ? 7 : 14; ++ } ++ ++ r->input_rotate = input_rotate; ++ r->add_ptr = i; ++ ++ if (out) ++ for (j = 0; j < 16; j++) ++ ((__u32 *)out)[j] = r->pool[(i - j) & wordmask]; ++ ++ spin_unlock_irqrestore(&r->lock, flags); ++} ++ ++static void mix_pool_bytes(struct entropy_store *r, const void *in, int bytes) ++{ ++ mix_pool_bytes_extract(r, in, bytes, NULL); ++} ++ ++/* ++ * Credit (or debit) the entropy store with n bits of entropy ++ */ ++static void credit_entropy_bits(struct entropy_store *r, int nbits) ++{ ++ unsigned long flags; ++ int entropy_count; ++ ++ if (!nbits) ++ return; ++ ++ spin_lock_irqsave(&r->lock, flags); ++ ++ DEBUG_ENT("added %d entropy credits to %s\n", nbits, r->name); ++ entropy_count = r->entropy_count; ++ entropy_count += nbits; ++ if (entropy_count < 0) { ++ DEBUG_ENT("negative entropy/overflow\n"); ++ entropy_count = 0; ++ } else if (entropy_count > r->poolinfo->POOLBITS) ++ entropy_count = r->poolinfo->POOLBITS; ++ r->entropy_count = entropy_count; ++ ++ /* should we wake readers? */ ++ if (r == &input_pool && entropy_count >= random_read_wakeup_thresh) { ++ wake_up_interruptible(&random_read_wait); ++ kill_fasync(&fasync, SIGIO, POLL_IN); ++ } ++ spin_unlock_irqrestore(&r->lock, flags); ++} ++ ++/********************************************************************* ++ * ++ * Entropy input management ++ * ++ *********************************************************************/ ++ ++/* There is one of these per entropy source */ ++struct timer_rand_state { ++ cycles_t last_time; ++ long last_delta, last_delta2; ++ unsigned dont_count_entropy:1; ++}; ++ ++#ifndef CONFIG_GENERIC_HARDIRQS ++ ++static struct timer_rand_state *irq_timer_state[NR_IRQS]; ++ ++static struct timer_rand_state *get_timer_rand_state(unsigned int irq) ++{ ++ return irq_timer_state[irq]; ++} ++ ++static void set_timer_rand_state(unsigned int irq, ++ struct timer_rand_state *state) ++{ ++ irq_timer_state[irq] = state; ++} ++ ++#else ++ ++static struct timer_rand_state *get_timer_rand_state(unsigned int irq) ++{ ++ struct irq_desc *desc; ++ ++ desc = irq_to_desc(irq); ++ ++ return desc->timer_rand_state; ++} ++ ++static void set_timer_rand_state(unsigned int irq, ++ struct timer_rand_state *state) ++{ ++ struct irq_desc *desc; ++ ++ desc = irq_to_desc(irq); ++ ++ desc->timer_rand_state = state; ++} ++#endif ++ ++static struct timer_rand_state input_timer_state; ++ ++/* ++ * This function adds entropy to the entropy "pool" by using timing ++ * delays. It uses the timer_rand_state structure to make an estimate ++ * of how many bits of entropy this call has added to the pool. ++ * ++ * The number "num" is also added to the pool - it should somehow describe ++ * the type of event which just happened. This is currently 0-255 for ++ * keyboard scan codes, and 256 upwards for interrupts. ++ * ++ */ ++static void add_timer_randomness(struct timer_rand_state *state, unsigned num) ++{ ++ struct { ++ cycles_t cycles; ++ long jiffies; ++ unsigned num; ++ } sample; ++ long delta, delta2, delta3; ++ ++ preempt_disable(); ++ /* if over the trickle threshold, use only 1 in 4096 samples */ ++ if (input_pool.entropy_count > trickle_thresh && ++ ((__this_cpu_inc_return(trickle_count) - 1) & 0xfff)) ++ goto out; ++ ++ sample.jiffies = jiffies; ++ sample.cycles = get_cycles(); ++ sample.num = num; ++ mix_pool_bytes(&input_pool, &sample, sizeof(sample)); ++ ++ /* ++ * Calculate number of bits of randomness we probably added. ++ * We take into account the first, second and third-order deltas ++ * in order to make our estimate. ++ */ ++ ++ if (!state->dont_count_entropy) { ++ delta = sample.jiffies - state->last_time; ++ state->last_time = sample.jiffies; ++ ++ delta2 = delta - state->last_delta; ++ state->last_delta = delta; ++ ++ delta3 = delta2 - state->last_delta2; ++ state->last_delta2 = delta2; ++ ++ if (delta < 0) ++ delta = -delta; ++ if (delta2 < 0) ++ delta2 = -delta2; ++ if (delta3 < 0) ++ delta3 = -delta3; ++ if (delta > delta2) ++ delta = delta2; ++ if (delta > delta3) ++ delta = delta3; ++ ++ /* ++ * delta is now minimum absolute delta. ++ * Round down by 1 bit on general principles, ++ * and limit entropy entimate to 12 bits. ++ */ ++ credit_entropy_bits(&input_pool, ++ min_t(int, fls(delta>>1), 11)); ++ } ++out: ++ preempt_enable(); ++} ++ ++void add_input_randomness(unsigned int type, unsigned int code, ++ unsigned int value) ++{ ++ static unsigned char last_value; ++ ++ /* ignore autorepeat and the like */ ++ if (value == last_value) ++ return; ++ ++ DEBUG_ENT("input event\n"); ++ last_value = value; ++ add_timer_randomness(&input_timer_state, ++ (type << 4) ^ code ^ (code >> 4) ^ value); ++} ++EXPORT_SYMBOL_GPL(add_input_randomness); ++ ++void add_interrupt_randomness(int irq) ++{ ++ struct timer_rand_state *state; ++ ++ state = get_timer_rand_state(irq); ++ ++ if (state == NULL) ++ return; ++ ++ DEBUG_ENT("irq event %d\n", irq); ++ add_timer_randomness(state, 0x100 + irq); ++} ++ ++#ifdef CONFIG_BLOCK ++void add_disk_randomness(struct gendisk *disk) ++{ ++ if (!disk || !disk->random) ++ return; ++ /* first major is 1, so we get >= 0x200 here */ ++ DEBUG_ENT("disk event %d:%d\n", ++ MAJOR(disk_devt(disk)), MINOR(disk_devt(disk))); ++ ++ add_timer_randomness(disk->random, 0x100 + disk_devt(disk)); ++} ++#endif ++ ++/********************************************************************* ++ * ++ * Entropy extraction routines ++ * ++ *********************************************************************/ ++ ++static ssize_t extract_entropy(struct entropy_store *r, void *buf, ++ size_t nbytes, int min, int rsvd); ++ ++/* ++ * This utility inline function is responsible for transferring entropy ++ * from the primary pool to the secondary extraction pool. We make ++ * sure we pull enough for a 'catastrophic reseed'. ++ */ ++static void xfer_secondary_pool(struct entropy_store *r, size_t nbytes) ++{ ++ __u32 tmp[OUTPUT_POOL_WORDS]; ++ ++ if (r->pull && r->entropy_count < nbytes * 8 && ++ r->entropy_count < r->poolinfo->POOLBITS) { ++ /* If we're limited, always leave two wakeup worth's BITS */ ++ int rsvd = r->limit ? 0 : random_read_wakeup_thresh/4; ++ int bytes = nbytes; ++ ++ /* pull at least as many as BYTES as wakeup BITS */ ++ bytes = max_t(int, bytes, random_read_wakeup_thresh / 8); ++ /* but never more than the buffer size */ ++ bytes = min_t(int, bytes, sizeof(tmp)); ++ ++ DEBUG_ENT("going to reseed %s with %d bits " ++ "(%d of %d requested)\n", ++ r->name, bytes * 8, nbytes * 8, r->entropy_count); ++ ++ bytes = extract_entropy(r->pull, tmp, bytes, ++ random_read_wakeup_thresh / 8, rsvd); ++ mix_pool_bytes(r, tmp, bytes); ++ credit_entropy_bits(r, bytes*8); ++ } ++} ++ ++/* ++ * These functions extracts randomness from the "entropy pool", and ++ * returns it in a buffer. ++ * ++ * The min parameter specifies the minimum amount we can pull before ++ * failing to avoid races that defeat catastrophic reseeding while the ++ * reserved parameter indicates how much entropy we must leave in the ++ * pool after each pull to avoid starving other readers. ++ * ++ * Note: extract_entropy() assumes that .poolwords is a multiple of 16 words. ++ */ ++ ++static size_t account(struct entropy_store *r, size_t nbytes, int min, ++ int reserved) ++{ ++ unsigned long flags; ++ ++ /* Hold lock while accounting */ ++ spin_lock_irqsave(&r->lock, flags); ++ ++ BUG_ON(r->entropy_count > r->poolinfo->POOLBITS); ++ DEBUG_ENT("trying to extract %d bits from %s\n", ++ nbytes * 8, r->name); ++ ++ /* Can we pull enough? */ ++ if (r->entropy_count / 8 < min + reserved) { ++ nbytes = 0; ++ } else { ++ /* If limited, never pull more than available */ ++ if (r->limit && nbytes + reserved >= r->entropy_count / 8) ++ nbytes = r->entropy_count/8 - reserved; ++ ++ if (r->entropy_count / 8 >= nbytes + reserved) ++ r->entropy_count -= nbytes*8; ++ else ++ r->entropy_count = reserved; ++ ++ if (r->entropy_count < random_write_wakeup_thresh) { ++ wake_up_interruptible(&random_write_wait); ++ kill_fasync(&fasync, SIGIO, POLL_OUT); ++ } ++ } ++ ++ DEBUG_ENT("debiting %d entropy credits from %s%s\n", ++ nbytes * 8, r->name, r->limit ? "" : " (unlimited)"); ++ ++ spin_unlock_irqrestore(&r->lock, flags); ++ ++ return nbytes; ++} ++ ++static void extract_buf(struct entropy_store *r, __u8 *out) ++{ ++ int i; ++ __u32 hash[5], workspace[SHA_WORKSPACE_WORDS]; ++ __u8 extract[64]; ++ ++ /* Generate a hash across the pool, 16 words (512 bits) at a time */ ++ sha_init(hash); ++ for (i = 0; i < r->poolinfo->poolwords; i += 16) ++ sha_transform(hash, (__u8 *)(r->pool + i), workspace); ++ ++ /* ++ * We mix the hash back into the pool to prevent backtracking ++ * attacks (where the attacker knows the state of the pool ++ * plus the current outputs, and attempts to find previous ++ * ouputs), unless the hash function can be inverted. By ++ * mixing at least a SHA1 worth of hash data back, we make ++ * brute-forcing the feedback as hard as brute-forcing the ++ * hash. ++ */ ++ mix_pool_bytes_extract(r, hash, sizeof(hash), extract); ++ ++ /* ++ * To avoid duplicates, we atomically extract a portion of the ++ * pool while mixing, and hash one final time. ++ */ ++ sha_transform(hash, extract, workspace); ++ memset(extract, 0, sizeof(extract)); ++ memset(workspace, 0, sizeof(workspace)); ++ ++ /* ++ * In case the hash function has some recognizable output ++ * pattern, we fold it in half. Thus, we always feed back ++ * twice as much data as we output. ++ */ ++ hash[0] ^= hash[3]; ++ hash[1] ^= hash[4]; ++ hash[2] ^= rol32(hash[2], 16); ++ memcpy(out, hash, EXTRACT_SIZE); ++ memset(hash, 0, sizeof(hash)); ++} ++ ++static ssize_t extract_entropy(struct entropy_store *r, void *buf, ++ size_t nbytes, int min, int reserved) ++{ ++ ssize_t ret = 0, i; ++ __u8 tmp[EXTRACT_SIZE]; ++ unsigned long flags; ++ ++ xfer_secondary_pool(r, nbytes); ++ nbytes = account(r, nbytes, min, reserved); ++ ++ while (nbytes) { ++ extract_buf(r, tmp); ++ ++ if (fips_enabled) { ++ spin_lock_irqsave(&r->lock, flags); ++ if (!memcmp(tmp, r->last_data, EXTRACT_SIZE)) ++ panic("Hardware RNG duplicated output!\n"); ++ memcpy(r->last_data, tmp, EXTRACT_SIZE); ++ spin_unlock_irqrestore(&r->lock, flags); ++ } ++ i = min_t(int, nbytes, EXTRACT_SIZE); ++ memcpy(buf, tmp, i); ++ nbytes -= i; ++ buf += i; ++ ret += i; ++ } ++ ++ /* Wipe data just returned from memory */ ++ memset(tmp, 0, sizeof(tmp)); ++ ++ return ret; ++} ++ ++static ssize_t extract_entropy_user(struct entropy_store *r, void __user *buf, ++ size_t nbytes) ++{ ++ ssize_t ret = 0, i; ++ __u8 tmp[EXTRACT_SIZE]; ++ ++ xfer_secondary_pool(r, nbytes); ++ nbytes = account(r, nbytes, 0, 0); ++ ++ while (nbytes) { ++ if (need_resched()) { ++ if (signal_pending(current)) { ++ if (ret == 0) ++ ret = -ERESTARTSYS; ++ break; ++ } ++ schedule(); ++ } ++ ++ extract_buf(r, tmp); ++ i = min_t(int, nbytes, EXTRACT_SIZE); ++ if (copy_to_user(buf, tmp, i)) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ nbytes -= i; ++ buf += i; ++ ret += i; ++ } ++ ++ /* Wipe data just returned from memory */ ++ memset(tmp, 0, sizeof(tmp)); ++ ++ return ret; ++} ++ ++/* ++ * This function is the exported kernel interface. It returns some ++ * number of good random numbers, suitable for seeding TCP sequence ++ * numbers, etc. ++ */ ++void get_random_bytes(void *buf, int nbytes) ++{ ++ extract_entropy(&nonblocking_pool, buf, nbytes, 0, 0); ++} ++EXPORT_SYMBOL(get_random_bytes); ++ ++/* ++ * init_std_data - initialize pool with system data ++ * ++ * @r: pool to initialize ++ * ++ * This function clears the pool's entropy count and mixes some system ++ * data into the pool to prepare it for use. The pool is not cleared ++ * as that can only decrease the entropy in the pool. ++ */ ++static void init_std_data(struct entropy_store *r) ++{ ++ ktime_t now; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&r->lock, flags); ++ r->entropy_count = 0; ++ spin_unlock_irqrestore(&r->lock, flags); ++ ++ now = ktime_get_real(); ++ mix_pool_bytes(r, &now, sizeof(now)); ++ mix_pool_bytes(r, utsname(), sizeof(*(utsname()))); ++} ++ ++static int rand_initialize(void) ++{ ++ init_std_data(&input_pool); ++ init_std_data(&blocking_pool); ++ init_std_data(&nonblocking_pool); ++ return 0; ++} ++module_init(rand_initialize); ++ ++void rand_initialize_irq(int irq) ++{ ++ struct timer_rand_state *state; ++ ++ state = get_timer_rand_state(irq); ++ ++ if (state) ++ return; ++ ++ /* ++ * If kzalloc returns null, we just won't use that entropy ++ * source. ++ */ ++ state = kzalloc(sizeof(struct timer_rand_state), GFP_KERNEL); ++ if (state) ++ set_timer_rand_state(irq, state); ++} ++ ++#ifdef CONFIG_BLOCK ++void rand_initialize_disk(struct gendisk *disk) ++{ ++ struct timer_rand_state *state; ++ ++ /* ++ * If kzalloc returns null, we just won't use that entropy ++ * source. ++ */ ++ state = kzalloc(sizeof(struct timer_rand_state), GFP_KERNEL); ++ if (state) ++ disk->random = state; ++} ++#endif ++ ++static ssize_t ++random_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) ++{ ++ ssize_t n, retval = 0, count = 0; ++ ++ if (nbytes == 0) ++ return 0; ++ ++ while (nbytes > 0) { ++ n = nbytes; ++ if (n > SEC_XFER_SIZE) ++ n = SEC_XFER_SIZE; ++ ++ DEBUG_ENT("reading %d bits\n", n*8); ++ ++ n = extract_entropy_user(&blocking_pool, buf, n); ++ ++ DEBUG_ENT("read got %d bits (%d still needed)\n", ++ n*8, (nbytes-n)*8); ++ ++ if (n == 0) { ++ if (file->f_flags & O_NONBLOCK) { ++ retval = -EAGAIN; ++ break; ++ } ++ ++ DEBUG_ENT("sleeping?\n"); ++ ++ wait_event_interruptible(random_read_wait, ++ input_pool.entropy_count >= ++ random_read_wakeup_thresh); ++ ++ DEBUG_ENT("awake\n"); ++ ++ if (signal_pending(current)) { ++ retval = -ERESTARTSYS; ++ break; ++ } ++ ++ continue; ++ } ++ ++ if (n < 0) { ++ retval = n; ++ break; ++ } ++ count += n; ++ buf += n; ++ nbytes -= n; ++ break; /* This break makes the device work */ ++ /* like a named pipe */ ++ } ++ ++ return (count ? count : retval); ++} ++ ++static ssize_t ++urandom_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) ++{ ++ return extract_entropy_user(&nonblocking_pool, buf, nbytes); ++} ++ ++static unsigned int ++random_poll(struct file *file, poll_table * wait) ++{ ++ unsigned int mask; ++ ++ poll_wait(file, &random_read_wait, wait); ++ poll_wait(file, &random_write_wait, wait); ++ mask = 0; ++ if (input_pool.entropy_count >= random_read_wakeup_thresh) ++ mask |= POLLIN | POLLRDNORM; ++ if (input_pool.entropy_count < random_write_wakeup_thresh) ++ mask |= POLLOUT | POLLWRNORM; ++ return mask; ++} ++ ++static int ++write_pool(struct entropy_store *r, const char __user *buffer, size_t count) ++{ ++ size_t bytes; ++ __u32 buf[16]; ++ const char __user *p = buffer; ++ ++ while (count > 0) { ++ bytes = min(count, sizeof(buf)); ++ if (copy_from_user(&buf, p, bytes)) ++ return -EFAULT; ++ ++ count -= bytes; ++ p += bytes; ++ ++ mix_pool_bytes(r, buf, bytes); ++ cond_resched(); ++ } ++ ++ return 0; ++} ++ ++static ssize_t random_write(struct file *file, const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ size_t ret; ++ ++ ret = write_pool(&blocking_pool, buffer, count); ++ if (ret) ++ return ret; ++ ret = write_pool(&nonblocking_pool, buffer, count); ++ if (ret) ++ return ret; ++ ++ return (ssize_t)count; ++} ++ ++static long random_ioctl(struct file *f, unsigned int cmd, unsigned long arg) ++{ ++ int size, ent_count; ++ int __user *p = (int __user *)arg; ++ int retval; ++ ++ switch (cmd) { ++ case RNDGETENTCNT: ++ /* inherently racy, no point locking */ ++ if (put_user(input_pool.entropy_count, p)) ++ return -EFAULT; ++ return 0; ++ case RNDADDTOENTCNT: ++ if (!capable(CAP_SYS_ADMIN)) ++ return -EPERM; ++ if (get_user(ent_count, p)) ++ return -EFAULT; ++ credit_entropy_bits(&input_pool, ent_count); ++ return 0; ++ case RNDADDENTROPY: ++ if (!capable(CAP_SYS_ADMIN)) ++ return -EPERM; ++ if (get_user(ent_count, p++)) ++ return -EFAULT; ++ if (ent_count < 0) ++ return -EINVAL; ++ if (get_user(size, p++)) ++ return -EFAULT; ++ retval = write_pool(&input_pool, (const char __user *)p, ++ size); ++ if (retval < 0) ++ return retval; ++ credit_entropy_bits(&input_pool, ent_count); ++ return 0; ++ case RNDZAPENTCNT: ++ case RNDCLEARPOOL: ++ /* Clear the entropy pool counters. */ ++ if (!capable(CAP_SYS_ADMIN)) ++ return -EPERM; ++ rand_initialize(); ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static int random_fasync(int fd, struct file *filp, int on) ++{ ++ return fasync_helper(fd, filp, on, &fasync); ++} ++ ++const struct file_operations random_fops = { ++ .read = random_read, ++ .write = random_write, ++ .poll = random_poll, ++ .unlocked_ioctl = random_ioctl, ++ .fasync = random_fasync, ++ .llseek = noop_llseek, ++}; ++ ++const struct file_operations urandom_fops = { ++ .read = urandom_read, ++ .write = random_write, ++ .unlocked_ioctl = random_ioctl, ++ .fasync = random_fasync, ++ .llseek = noop_llseek, ++}; ++ ++/*************************************************************** ++ * Random UUID interface ++ * ++ * Used here for a Boot ID, but can be useful for other kernel ++ * drivers. ++ ***************************************************************/ ++ ++/* ++ * Generate random UUID ++ */ ++void generate_random_uuid(unsigned char uuid_out[16]) ++{ ++ get_random_bytes(uuid_out, 16); ++ /* Set UUID version to 4 --- truly random generation */ ++ uuid_out[6] = (uuid_out[6] & 0x0F) | 0x40; ++ /* Set the UUID variant to DCE */ ++ uuid_out[8] = (uuid_out[8] & 0x3F) | 0x80; ++} ++EXPORT_SYMBOL(generate_random_uuid); ++ ++/******************************************************************** ++ * ++ * Sysctl interface ++ * ++ ********************************************************************/ ++ ++#ifdef CONFIG_SYSCTL ++ ++#include ++ ++static int min_read_thresh = 8, min_write_thresh; ++static int max_read_thresh = INPUT_POOL_WORDS * 32; ++static int max_write_thresh = INPUT_POOL_WORDS * 32; ++static char sysctl_bootid[16]; ++ ++/* ++ * These functions is used to return both the bootid UUID, and random ++ * UUID. The difference is in whether table->data is NULL; if it is, ++ * then a new UUID is generated and returned to the user. ++ * ++ * If the user accesses this via the proc interface, it will be returned ++ * as an ASCII string in the standard UUID format. If accesses via the ++ * sysctl system call, it is returned as 16 bytes of binary data. ++ */ ++static int proc_do_uuid(ctl_table *table, int write, ++ void __user *buffer, size_t *lenp, loff_t *ppos) ++{ ++ ctl_table fake_table; ++ unsigned char buf[64], tmp_uuid[16], *uuid; ++ ++ uuid = table->data; ++ if (!uuid) { ++ uuid = tmp_uuid; ++ uuid[8] = 0; ++ } ++ if (uuid[8] == 0) ++ generate_random_uuid(uuid); ++ ++ sprintf(buf, "%pU", uuid); ++ ++ fake_table.data = buf; ++ fake_table.maxlen = sizeof(buf); ++ ++ return proc_dostring(&fake_table, write, buffer, lenp, ppos); ++} ++ ++static int sysctl_poolsize = INPUT_POOL_WORDS * 32; ++ctl_table random_table[] = { ++ { ++ .procname = "poolsize", ++ .data = &sysctl_poolsize, ++ .maxlen = sizeof(int), ++ .mode = 0444, ++ .proc_handler = proc_dointvec, ++ }, ++ { ++ .procname = "entropy_avail", ++ .maxlen = sizeof(int), ++ .mode = 0444, ++ .proc_handler = proc_dointvec, ++ .data = &input_pool.entropy_count, ++ }, ++ { ++ .procname = "read_wakeup_threshold", ++ .data = &random_read_wakeup_thresh, ++ .maxlen = sizeof(int), ++ .mode = 0644, ++ .proc_handler = proc_dointvec_minmax, ++ .extra1 = &min_read_thresh, ++ .extra2 = &max_read_thresh, ++ }, ++ { ++ .procname = "write_wakeup_threshold", ++ .data = &random_write_wakeup_thresh, ++ .maxlen = sizeof(int), ++ .mode = 0644, ++ .proc_handler = proc_dointvec_minmax, ++ .extra1 = &min_write_thresh, ++ .extra2 = &max_write_thresh, ++ }, ++ { ++ .procname = "boot_id", ++ .data = &sysctl_bootid, ++ .maxlen = 16, ++ .mode = 0444, ++ .proc_handler = proc_do_uuid, ++ }, ++ { ++ .procname = "uuid", ++ .maxlen = 16, ++ .mode = 0444, ++ .proc_handler = proc_do_uuid, ++ }, ++ { } ++}; ++#endif /* CONFIG_SYSCTL */ ++ ++static u32 random_int_secret[MD5_MESSAGE_BYTES / 4] ____cacheline_aligned; ++ ++static int __init random_int_secret_init(void) ++{ ++ get_random_bytes(random_int_secret, sizeof(random_int_secret)); ++ return 0; ++} ++late_initcall(random_int_secret_init); ++ ++/* ++ * Get a random word for internal kernel use only. Similar to urandom but ++ * with the goal of minimal entropy pool depletion. As a result, the random ++ * value is not cryptographically secure but for several uses the cost of ++ * depleting entropy is too high ++ */ ++DEFINE_PER_CPU(__u32 [MD5_DIGEST_WORDS], get_random_int_hash); ++unsigned int get_random_int(void) ++{ ++ __u32 *hash = get_cpu_var(get_random_int_hash); ++ unsigned int ret; ++ ++ hash[0] += current->pid + jiffies + get_cycles(); ++ md5_transform(hash, random_int_secret); ++ ret = hash[0]; ++ put_cpu_var(get_random_int_hash); ++ ++ return ret; ++} ++ ++/* ++ * randomize_range() returns a start address such that ++ * ++ * [...... .....] ++ * start end ++ * ++ * a with size "len" starting at the return value is inside in the ++ * area defined by [start, end], but is otherwise randomized. ++ */ ++unsigned long ++randomize_range(unsigned long start, unsigned long end, unsigned long len) ++{ ++ unsigned long range = end - len - start; ++ ++ if (end <= start + len) ++ return 0; ++ return PAGE_ALIGN(get_random_int() % range + start); ++} +diff -Nur linux-3.0.4.orig/fs/fcntl.c linux-3.0.4/fs/fcntl.c +--- linux-3.0.4.orig/fs/fcntl.c 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/fs/fcntl.c 2011-10-17 04:36:27.356574299 +0200 +@@ -142,6 +142,7 @@ + } + return ret; + } ++EXPORT_SYMBOL(sys_dup); + + #define SETFL_MASK (O_APPEND | O_NONBLOCK | O_NDELAY | O_DIRECT | O_NOATIME) + +diff -Nur linux-3.0.4.orig/include/linux/miscdevice.h linux-3.0.4/include/linux/miscdevice.h +--- linux-3.0.4.orig/include/linux/miscdevice.h 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/include/linux/miscdevice.h 2011-10-17 04:36:27.356574299 +0200 +@@ -18,6 +18,7 @@ + #define APOLLO_MOUSE_MINOR 7 + #define PC110PAD_MINOR 9 + /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ ++#define CRYPTODEV_MINOR 70 /* /dev/crypto */ + #define WATCHDOG_MINOR 130 /* Watchdog timer */ + #define TEMP_MINOR 131 /* Temperature Sensor */ + #define RTC_MINOR 135 +diff -Nur linux-3.0.4.orig/include/linux/random.h linux-3.0.4/include/linux/random.h +--- linux-3.0.4.orig/include/linux/random.h 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/include/linux/random.h 2011-10-17 04:36:27.356574299 +0200 +@@ -54,6 +54,10 @@ + unsigned int value); + extern void add_interrupt_randomness(int irq); + ++extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); ++extern int random_input_wait(void); ++#define HAS_RANDOM_INPUT_WAIT 1 ++ + extern void get_random_bytes(void *buf, int nbytes); + void generate_random_uuid(unsigned char uuid_out[16]); + +diff -Nur linux-3.0.4.orig/kernel/pid.c linux-3.0.4/kernel/pid.c +--- linux-3.0.4.orig/kernel/pid.c 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/kernel/pid.c 2011-10-17 04:36:27.356574299 +0200 +@@ -427,6 +427,7 @@ + { + return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns); + } ++EXPORT_SYMBOL(find_task_by_vpid); + + struct pid *get_task_pid(struct task_struct *task, enum pid_type type) + { +diff -Nur linux-3.0.4.orig/kernel/pid.c.orig linux-3.0.4/kernel/pid.c.orig +--- linux-3.0.4.orig/kernel/pid.c.orig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/kernel/pid.c.orig 2011-08-29 22:56:30.000000000 +0200 +@@ -0,0 +1,570 @@ ++/* ++ * Generic pidhash and scalable, time-bounded PID allocator ++ * ++ * (C) 2002-2003 William Irwin, IBM ++ * (C) 2004 William Irwin, Oracle ++ * (C) 2002-2004 Ingo Molnar, Red Hat ++ * ++ * pid-structures are backing objects for tasks sharing a given ID to chain ++ * against. There is very little to them aside from hashing them and ++ * parking tasks using given ID's on a list. ++ * ++ * The hash is always changed with the tasklist_lock write-acquired, ++ * and the hash is only accessed with the tasklist_lock at least ++ * read-acquired, so there's no additional SMP locking needed here. ++ * ++ * We have a list of bitmap pages, which bitmaps represent the PID space. ++ * Allocating and freeing PIDs is completely lockless. The worst-case ++ * allocation scenario when all but one out of 1 million PIDs possible are ++ * allocated already: the scanning of 32 list entries and at most PAGE_SIZE ++ * bytes. The typical fastpath is a single successful setbit. Freeing is O(1). ++ * ++ * Pid namespaces: ++ * (C) 2007 Pavel Emelyanov , OpenVZ, SWsoft Inc. ++ * (C) 2007 Sukadev Bhattiprolu , IBM ++ * Many thanks to Oleg Nesterov for comments and help ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define pid_hashfn(nr, ns) \ ++ hash_long((unsigned long)nr + (unsigned long)ns, pidhash_shift) ++static struct hlist_head *pid_hash; ++static unsigned int pidhash_shift = 4; ++struct pid init_struct_pid = INIT_STRUCT_PID; ++ ++int pid_max = PID_MAX_DEFAULT; ++ ++#define RESERVED_PIDS 300 ++ ++int pid_max_min = RESERVED_PIDS + 1; ++int pid_max_max = PID_MAX_LIMIT; ++ ++#define BITS_PER_PAGE (PAGE_SIZE*8) ++#define BITS_PER_PAGE_MASK (BITS_PER_PAGE-1) ++ ++static inline int mk_pid(struct pid_namespace *pid_ns, ++ struct pidmap *map, int off) ++{ ++ return (map - pid_ns->pidmap)*BITS_PER_PAGE + off; ++} ++ ++#define find_next_offset(map, off) \ ++ find_next_zero_bit((map)->page, BITS_PER_PAGE, off) ++ ++/* ++ * PID-map pages start out as NULL, they get allocated upon ++ * first use and are never deallocated. This way a low pid_max ++ * value does not cause lots of bitmaps to be allocated, but ++ * the scheme scales to up to 4 million PIDs, runtime. ++ */ ++struct pid_namespace init_pid_ns = { ++ .kref = { ++ .refcount = ATOMIC_INIT(2), ++ }, ++ .pidmap = { ++ [ 0 ... PIDMAP_ENTRIES-1] = { ATOMIC_INIT(BITS_PER_PAGE), NULL } ++ }, ++ .last_pid = 0, ++ .level = 0, ++ .child_reaper = &init_task, ++}; ++EXPORT_SYMBOL_GPL(init_pid_ns); ++ ++int is_container_init(struct task_struct *tsk) ++{ ++ int ret = 0; ++ struct pid *pid; ++ ++ rcu_read_lock(); ++ pid = task_pid(tsk); ++ if (pid != NULL && pid->numbers[pid->level].nr == 1) ++ ret = 1; ++ rcu_read_unlock(); ++ ++ return ret; ++} ++EXPORT_SYMBOL(is_container_init); ++ ++/* ++ * Note: disable interrupts while the pidmap_lock is held as an ++ * interrupt might come in and do read_lock(&tasklist_lock). ++ * ++ * If we don't disable interrupts there is a nasty deadlock between ++ * detach_pid()->free_pid() and another cpu that does ++ * spin_lock(&pidmap_lock) followed by an interrupt routine that does ++ * read_lock(&tasklist_lock); ++ * ++ * After we clean up the tasklist_lock and know there are no ++ * irq handlers that take it we can leave the interrupts enabled. ++ * For now it is easier to be safe than to prove it can't happen. ++ */ ++ ++static __cacheline_aligned_in_smp DEFINE_SPINLOCK(pidmap_lock); ++ ++static void free_pidmap(struct upid *upid) ++{ ++ int nr = upid->nr; ++ struct pidmap *map = upid->ns->pidmap + nr / BITS_PER_PAGE; ++ int offset = nr & BITS_PER_PAGE_MASK; ++ ++ clear_bit(offset, map->page); ++ atomic_inc(&map->nr_free); ++} ++ ++/* ++ * If we started walking pids at 'base', is 'a' seen before 'b'? ++ */ ++static int pid_before(int base, int a, int b) ++{ ++ /* ++ * This is the same as saying ++ * ++ * (a - base + MAXUINT) % MAXUINT < (b - base + MAXUINT) % MAXUINT ++ * and that mapping orders 'a' and 'b' with respect to 'base'. ++ */ ++ return (unsigned)(a - base) < (unsigned)(b - base); ++} ++ ++/* ++ * We might be racing with someone else trying to set pid_ns->last_pid. ++ * We want the winner to have the "later" value, because if the ++ * "earlier" value prevails, then a pid may get reused immediately. ++ * ++ * Since pids rollover, it is not sufficient to just pick the bigger ++ * value. We have to consider where we started counting from. ++ * ++ * 'base' is the value of pid_ns->last_pid that we observed when ++ * we started looking for a pid. ++ * ++ * 'pid' is the pid that we eventually found. ++ */ ++static void set_last_pid(struct pid_namespace *pid_ns, int base, int pid) ++{ ++ int prev; ++ int last_write = base; ++ do { ++ prev = last_write; ++ last_write = cmpxchg(&pid_ns->last_pid, prev, pid); ++ } while ((prev != last_write) && (pid_before(base, last_write, pid))); ++} ++ ++static int alloc_pidmap(struct pid_namespace *pid_ns) ++{ ++ int i, offset, max_scan, pid, last = pid_ns->last_pid; ++ struct pidmap *map; ++ ++ pid = last + 1; ++ if (pid >= pid_max) ++ pid = RESERVED_PIDS; ++ offset = pid & BITS_PER_PAGE_MASK; ++ map = &pid_ns->pidmap[pid/BITS_PER_PAGE]; ++ /* ++ * If last_pid points into the middle of the map->page we ++ * want to scan this bitmap block twice, the second time ++ * we start with offset == 0 (or RESERVED_PIDS). ++ */ ++ max_scan = DIV_ROUND_UP(pid_max, BITS_PER_PAGE) - !offset; ++ for (i = 0; i <= max_scan; ++i) { ++ if (unlikely(!map->page)) { ++ void *page = kzalloc(PAGE_SIZE, GFP_KERNEL); ++ /* ++ * Free the page if someone raced with us ++ * installing it: ++ */ ++ spin_lock_irq(&pidmap_lock); ++ if (!map->page) { ++ map->page = page; ++ page = NULL; ++ } ++ spin_unlock_irq(&pidmap_lock); ++ kfree(page); ++ if (unlikely(!map->page)) ++ break; ++ } ++ if (likely(atomic_read(&map->nr_free))) { ++ do { ++ if (!test_and_set_bit(offset, map->page)) { ++ atomic_dec(&map->nr_free); ++ set_last_pid(pid_ns, last, pid); ++ return pid; ++ } ++ offset = find_next_offset(map, offset); ++ pid = mk_pid(pid_ns, map, offset); ++ } while (offset < BITS_PER_PAGE && pid < pid_max); ++ } ++ if (map < &pid_ns->pidmap[(pid_max-1)/BITS_PER_PAGE]) { ++ ++map; ++ offset = 0; ++ } else { ++ map = &pid_ns->pidmap[0]; ++ offset = RESERVED_PIDS; ++ if (unlikely(last == offset)) ++ break; ++ } ++ pid = mk_pid(pid_ns, map, offset); ++ } ++ return -1; ++} ++ ++int next_pidmap(struct pid_namespace *pid_ns, unsigned int last) ++{ ++ int offset; ++ struct pidmap *map, *end; ++ ++ if (last >= PID_MAX_LIMIT) ++ return -1; ++ ++ offset = (last + 1) & BITS_PER_PAGE_MASK; ++ map = &pid_ns->pidmap[(last + 1)/BITS_PER_PAGE]; ++ end = &pid_ns->pidmap[PIDMAP_ENTRIES]; ++ for (; map < end; map++, offset = 0) { ++ if (unlikely(!map->page)) ++ continue; ++ offset = find_next_bit((map)->page, BITS_PER_PAGE, offset); ++ if (offset < BITS_PER_PAGE) ++ return mk_pid(pid_ns, map, offset); ++ } ++ return -1; ++} ++ ++void put_pid(struct pid *pid) ++{ ++ struct pid_namespace *ns; ++ ++ if (!pid) ++ return; ++ ++ ns = pid->numbers[pid->level].ns; ++ if ((atomic_read(&pid->count) == 1) || ++ atomic_dec_and_test(&pid->count)) { ++ kmem_cache_free(ns->pid_cachep, pid); ++ put_pid_ns(ns); ++ } ++} ++EXPORT_SYMBOL_GPL(put_pid); ++ ++static void delayed_put_pid(struct rcu_head *rhp) ++{ ++ struct pid *pid = container_of(rhp, struct pid, rcu); ++ put_pid(pid); ++} ++ ++void free_pid(struct pid *pid) ++{ ++ /* We can be called with write_lock_irq(&tasklist_lock) held */ ++ int i; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&pidmap_lock, flags); ++ for (i = 0; i <= pid->level; i++) ++ hlist_del_rcu(&pid->numbers[i].pid_chain); ++ spin_unlock_irqrestore(&pidmap_lock, flags); ++ ++ for (i = 0; i <= pid->level; i++) ++ free_pidmap(pid->numbers + i); ++ ++ call_rcu(&pid->rcu, delayed_put_pid); ++} ++ ++struct pid *alloc_pid(struct pid_namespace *ns) ++{ ++ struct pid *pid; ++ enum pid_type type; ++ int i, nr; ++ struct pid_namespace *tmp; ++ struct upid *upid; ++ ++ pid = kmem_cache_alloc(ns->pid_cachep, GFP_KERNEL); ++ if (!pid) ++ goto out; ++ ++ tmp = ns; ++ for (i = ns->level; i >= 0; i--) { ++ nr = alloc_pidmap(tmp); ++ if (nr < 0) ++ goto out_free; ++ ++ pid->numbers[i].nr = nr; ++ pid->numbers[i].ns = tmp; ++ tmp = tmp->parent; ++ } ++ ++ get_pid_ns(ns); ++ pid->level = ns->level; ++ atomic_set(&pid->count, 1); ++ for (type = 0; type < PIDTYPE_MAX; ++type) ++ INIT_HLIST_HEAD(&pid->tasks[type]); ++ ++ upid = pid->numbers + ns->level; ++ spin_lock_irq(&pidmap_lock); ++ for ( ; upid >= pid->numbers; --upid) ++ hlist_add_head_rcu(&upid->pid_chain, ++ &pid_hash[pid_hashfn(upid->nr, upid->ns)]); ++ spin_unlock_irq(&pidmap_lock); ++ ++out: ++ return pid; ++ ++out_free: ++ while (++i <= ns->level) ++ free_pidmap(pid->numbers + i); ++ ++ kmem_cache_free(ns->pid_cachep, pid); ++ pid = NULL; ++ goto out; ++} ++ ++struct pid *find_pid_ns(int nr, struct pid_namespace *ns) ++{ ++ struct hlist_node *elem; ++ struct upid *pnr; ++ ++ hlist_for_each_entry_rcu(pnr, elem, ++ &pid_hash[pid_hashfn(nr, ns)], pid_chain) ++ if (pnr->nr == nr && pnr->ns == ns) ++ return container_of(pnr, struct pid, ++ numbers[ns->level]); ++ ++ return NULL; ++} ++EXPORT_SYMBOL_GPL(find_pid_ns); ++ ++struct pid *find_vpid(int nr) ++{ ++ return find_pid_ns(nr, current->nsproxy->pid_ns); ++} ++EXPORT_SYMBOL_GPL(find_vpid); ++ ++/* ++ * attach_pid() must be called with the tasklist_lock write-held. ++ */ ++void attach_pid(struct task_struct *task, enum pid_type type, ++ struct pid *pid) ++{ ++ struct pid_link *link; ++ ++ link = &task->pids[type]; ++ link->pid = pid; ++ hlist_add_head_rcu(&link->node, &pid->tasks[type]); ++} ++ ++static void __change_pid(struct task_struct *task, enum pid_type type, ++ struct pid *new) ++{ ++ struct pid_link *link; ++ struct pid *pid; ++ int tmp; ++ ++ link = &task->pids[type]; ++ pid = link->pid; ++ ++ hlist_del_rcu(&link->node); ++ link->pid = new; ++ ++ for (tmp = PIDTYPE_MAX; --tmp >= 0; ) ++ if (!hlist_empty(&pid->tasks[tmp])) ++ return; ++ ++ free_pid(pid); ++} ++ ++void detach_pid(struct task_struct *task, enum pid_type type) ++{ ++ __change_pid(task, type, NULL); ++} ++ ++void change_pid(struct task_struct *task, enum pid_type type, ++ struct pid *pid) ++{ ++ __change_pid(task, type, pid); ++ attach_pid(task, type, pid); ++} ++ ++/* transfer_pid is an optimization of attach_pid(new), detach_pid(old) */ ++void transfer_pid(struct task_struct *old, struct task_struct *new, ++ enum pid_type type) ++{ ++ new->pids[type].pid = old->pids[type].pid; ++ hlist_replace_rcu(&old->pids[type].node, &new->pids[type].node); ++} ++ ++struct task_struct *pid_task(struct pid *pid, enum pid_type type) ++{ ++ struct task_struct *result = NULL; ++ if (pid) { ++ struct hlist_node *first; ++ first = rcu_dereference_check(hlist_first_rcu(&pid->tasks[type]), ++ rcu_read_lock_held() || ++ lockdep_tasklist_lock_is_held()); ++ if (first) ++ result = hlist_entry(first, struct task_struct, pids[(type)].node); ++ } ++ return result; ++} ++EXPORT_SYMBOL(pid_task); ++ ++/* ++ * Must be called under rcu_read_lock(). ++ */ ++struct task_struct *find_task_by_pid_ns(pid_t nr, struct pid_namespace *ns) ++{ ++ rcu_lockdep_assert(rcu_read_lock_held()); ++ return pid_task(find_pid_ns(nr, ns), PIDTYPE_PID); ++} ++ ++struct task_struct *find_task_by_vpid(pid_t vnr) ++{ ++ return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns); ++} ++ ++struct pid *get_task_pid(struct task_struct *task, enum pid_type type) ++{ ++ struct pid *pid; ++ rcu_read_lock(); ++ if (type != PIDTYPE_PID) ++ task = task->group_leader; ++ pid = get_pid(task->pids[type].pid); ++ rcu_read_unlock(); ++ return pid; ++} ++EXPORT_SYMBOL_GPL(get_task_pid); ++ ++struct task_struct *get_pid_task(struct pid *pid, enum pid_type type) ++{ ++ struct task_struct *result; ++ rcu_read_lock(); ++ result = pid_task(pid, type); ++ if (result) ++ get_task_struct(result); ++ rcu_read_unlock(); ++ return result; ++} ++EXPORT_SYMBOL_GPL(get_pid_task); ++ ++struct pid *find_get_pid(pid_t nr) ++{ ++ struct pid *pid; ++ ++ rcu_read_lock(); ++ pid = get_pid(find_vpid(nr)); ++ rcu_read_unlock(); ++ ++ return pid; ++} ++EXPORT_SYMBOL_GPL(find_get_pid); ++ ++pid_t pid_nr_ns(struct pid *pid, struct pid_namespace *ns) ++{ ++ struct upid *upid; ++ pid_t nr = 0; ++ ++ if (pid && ns->level <= pid->level) { ++ upid = &pid->numbers[ns->level]; ++ if (upid->ns == ns) ++ nr = upid->nr; ++ } ++ return nr; ++} ++ ++pid_t pid_vnr(struct pid *pid) ++{ ++ return pid_nr_ns(pid, current->nsproxy->pid_ns); ++} ++EXPORT_SYMBOL_GPL(pid_vnr); ++ ++pid_t __task_pid_nr_ns(struct task_struct *task, enum pid_type type, ++ struct pid_namespace *ns) ++{ ++ pid_t nr = 0; ++ ++ rcu_read_lock(); ++ if (!ns) ++ ns = current->nsproxy->pid_ns; ++ if (likely(pid_alive(task))) { ++ if (type != PIDTYPE_PID) ++ task = task->group_leader; ++ nr = pid_nr_ns(task->pids[type].pid, ns); ++ } ++ rcu_read_unlock(); ++ ++ return nr; ++} ++EXPORT_SYMBOL(__task_pid_nr_ns); ++ ++pid_t task_tgid_nr_ns(struct task_struct *tsk, struct pid_namespace *ns) ++{ ++ return pid_nr_ns(task_tgid(tsk), ns); ++} ++EXPORT_SYMBOL(task_tgid_nr_ns); ++ ++struct pid_namespace *task_active_pid_ns(struct task_struct *tsk) ++{ ++ return ns_of_pid(task_pid(tsk)); ++} ++EXPORT_SYMBOL_GPL(task_active_pid_ns); ++ ++/* ++ * Used by proc to find the first pid that is greater than or equal to nr. ++ * ++ * If there is a pid at nr this function is exactly the same as find_pid_ns. ++ */ ++struct pid *find_ge_pid(int nr, struct pid_namespace *ns) ++{ ++ struct pid *pid; ++ ++ do { ++ pid = find_pid_ns(nr, ns); ++ if (pid) ++ break; ++ nr = next_pidmap(ns, nr); ++ } while (nr > 0); ++ ++ return pid; ++} ++ ++/* ++ * The pid hash table is scaled according to the amount of memory in the ++ * machine. From a minimum of 16 slots up to 4096 slots at one gigabyte or ++ * more. ++ */ ++void __init pidhash_init(void) ++{ ++ int i, pidhash_size; ++ ++ pid_hash = alloc_large_system_hash("PID", sizeof(*pid_hash), 0, 18, ++ HASH_EARLY | HASH_SMALL, ++ &pidhash_shift, NULL, 4096); ++ pidhash_size = 1 << pidhash_shift; ++ ++ for (i = 0; i < pidhash_size; i++) ++ INIT_HLIST_HEAD(&pid_hash[i]); ++} ++ ++void __init pidmap_init(void) ++{ ++ /* bump default and minimum pid_max based on number of cpus */ ++ pid_max = min(pid_max_max, max_t(int, pid_max, ++ PIDS_PER_CPU_DEFAULT * num_possible_cpus())); ++ pid_max_min = max_t(int, pid_max_min, ++ PIDS_PER_CPU_MIN * num_possible_cpus()); ++ pr_info("pid_max: default: %u minimum: %u\n", pid_max, pid_max_min); ++ ++ init_pid_ns.pidmap[0].page = kzalloc(PAGE_SIZE, GFP_KERNEL); ++ /* Reserve PID 0. We never call free_pidmap(0) */ ++ set_bit(0, init_pid_ns.pidmap[0].page); ++ atomic_dec(&init_pid_ns.pidmap[0].nr_free); ++ ++ init_pid_ns.pid_cachep = KMEM_CACHE(pid, ++ SLAB_HWCACHE_ALIGN | SLAB_PANIC); ++} diff --git a/target/linux/patches/3.0.8/sparc-include.patch b/target/linux/patches/3.0.8/sparc-include.patch new file mode 100644 index 000000000..2f8ffd061 --- /dev/null +++ b/target/linux/patches/3.0.8/sparc-include.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c +--- linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c 2011-05-21 13:34:40.000000000 +0200 +@@ -25,7 +25,6 @@ + #include + #include + #include +-#include + + #define MAXSYMS 1024 + diff --git a/target/linux/patches/3.0.8/startup.patch b/target/linux/patches/3.0.8/startup.patch new file mode 100644 index 000000000..68e8987b0 --- /dev/null +++ b/target/linux/patches/3.0.8/startup.patch @@ -0,0 +1,20 @@ +diff -Nur linux-2.6.34.orig/init/main.c linux-2.6.34/init/main.c +--- linux-2.6.34.orig/init/main.c 2010-05-16 23:17:36.000000000 +0200 ++++ linux-2.6.34/init/main.c 2010-05-20 20:13:26.321613615 +0200 +@@ -842,6 +842,7 @@ + printk(KERN_WARNING "Failed to execute %s. Attempting " + "defaults...\n", execute_command); + } ++ run_init_process("/init"); + run_init_process("/sbin/init"); + run_init_process("/etc/init"); + run_init_process("/bin/init"); +@@ -889,6 +890,8 @@ + if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0) + printk(KERN_WARNING "Warning: unable to open an initial console.\n"); + ++ printk(KERN_WARNING "Starting Linux (built with OpenADK).\n"); ++ + (void) sys_dup(0); + (void) sys_dup(0); + /* diff --git a/target/linux/patches/3.0.8/usb-defaults-off.patch b/target/linux/patches/3.0.8/usb-defaults-off.patch new file mode 100644 index 000000000..31367108a --- /dev/null +++ b/target/linux/patches/3.0.8/usb-defaults-off.patch @@ -0,0 +1,32 @@ +diff -Nur linux-2.6.37.orig//drivers/usb/core/Kconfig linux-2.6.37/drivers/usb/core/Kconfig +--- linux-2.6.37.orig//drivers/usb/core/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/drivers/usb/core/Kconfig 2011-04-12 19:04:23.000000000 +0200 +@@ -59,7 +59,7 @@ + config USB_DEVICE_CLASS + bool "USB device class-devices (DEPRECATED)" + depends on USB +- default y ++ default n + ---help--- + Userspace access to USB devices is granted by device-nodes exported + directly from the usbdev in sysfs. Old versions of the driver +diff -Nur linux-2.6.37.orig//drivers/usb/host/Kconfig linux-2.6.37/drivers/usb/host/Kconfig +--- linux-2.6.37.orig//drivers/usb/host/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/drivers/usb/host/Kconfig 2011-04-12 19:04:48.000000000 +0200 +@@ -62,6 +62,7 @@ + config USB_EHCI_ROOT_HUB_TT + bool "Root Hub Transaction Translators" + depends on USB_EHCI_HCD ++ default n + ---help--- + Some EHCI chips have vendor-specific extensions to integrate + transaction translators, so that no OHCI or UHCI companion +@@ -74,7 +75,7 @@ + config USB_EHCI_TT_NEWSCHED + bool "Improved Transaction Translator scheduling" + depends on USB_EHCI_HCD +- default y ++ default n + ---help--- + This changes the periodic scheduling code to fill more of the low + and full speed bandwidth available from the Transaction Translator diff --git a/target/linux/patches/3.0.8/uuid.patch b/target/linux/patches/3.0.8/uuid.patch new file mode 100644 index 000000000..2529fdab5 --- /dev/null +++ b/target/linux/patches/3.0.8/uuid.patch @@ -0,0 +1,255 @@ +diff -Nur linux-2.6.38.4.orig/block/genhd.c linux-2.6.38.4/block/genhd.c +--- linux-2.6.38.4.orig/block/genhd.c 2011-04-21 23:34:46.000000000 +0200 ++++ linux-2.6.38.4/block/genhd.c 2011-04-27 19:21:18.668912036 +0200 +@@ -34,7 +34,7 @@ + static DEFINE_MUTEX(ext_devt_mutex); + static DEFINE_IDR(ext_devt_idr); + +-static struct device_type disk_type; ++struct device_type disk_type; + + static void disk_add_events(struct gendisk *disk); + static void disk_del_events(struct gendisk *disk); +@@ -1118,7 +1118,7 @@ + return NULL; + } + +-static struct device_type disk_type = { ++struct device_type disk_type = { + .name = "disk", + .groups = disk_attr_groups, + .release = disk_release, +diff -Nur linux-2.6.38.4.orig/init/do_mounts.c linux-2.6.38.4/init/do_mounts.c +--- linux-2.6.38.4.orig/init/do_mounts.c 2011-04-21 23:34:46.000000000 +0200 ++++ linux-2.6.38.4/init/do_mounts.c 2011-04-27 19:26:52.721413000 +0200 +@@ -32,6 +32,132 @@ + + dev_t ROOT_DEV; + ++#ifdef CONFIG_EXT2_FS ++/* support for root=UUID=ce40d6b2-18eb-4a75-aefe-7ddb0995ce63 bootargs */ ++ ++#include ++ ++__u8 root_dev_uuid[16]; ++int root_dev_type; /* 0 = normal (/dev/hda1, 0301); 1 = UUID; 3 = bad */ ++ ++/* imported from block/genhd.c after removing its static qualifier */ ++extern struct device_type disk_type; ++ ++/* helper function */ ++static __u8 __init fromhex(char c) ++{ ++ if (c >= '0' && c <= '9') ++ return (c - '0'); ++ c &= ~32; ++ if (c >= 'A' && c <= 'F') ++ return (c - 'A' + 10); ++ return (0xFF); ++} ++ ++static void __init parse_uuid(const char *s) ++{ ++ int i; ++ __u8 j, k; ++ ++ if (strlen(s) != 36 || s[8] != '-' || s[13] != '-' || ++ s[18] != '-' || s[23] != '-') ++ goto bad_uuid; ++ for (i = 0; i < 16; i++) { ++ if (*s == '-') ++ ++s; ++ j = fromhex(*s++); ++ k = fromhex(*s++); ++ if (j == 0xFF || k == 0xFF) ++ goto bad_uuid; ++ root_dev_uuid[i] = (j << 4) | k; ++ } ++ return; ++ bad_uuid: ++ /* we cannot panic here, defer */ ++ root_dev_type = 3; ++} ++ ++/* from drivers/md/md.c */ ++static void __init initcode_bi_complete(struct bio *bio, int error) ++{ ++ complete((struct completion*)bio->bi_private); ++} ++ ++static int __init initcode_sync_page_read(struct block_device *bdev, ++ sector_t sector, int size, struct page *page) ++{ ++ struct bio *bio = bio_alloc(GFP_NOIO, 1); ++ struct completion event; ++ int ret, rw = READ; ++ ++ rw |= REQ_SYNC; ++ ++ bio->bi_bdev = bdev; ++ bio->bi_sector = sector; ++ bio_add_page(bio, page, size, 0); ++ init_completion(&event); ++ bio->bi_private = &event; ++ bio->bi_end_io = initcode_bi_complete; ++ submit_bio(rw, bio); ++ wait_for_completion(&event); ++ ++ ret = test_bit(BIO_UPTODATE, &bio->bi_flags); ++ bio_put(bio); ++ /* 0 = failure */ ++ return ret; ++} ++ ++/* most of this taken from fs/ext2/super.c */ ++static int __init check_dev(struct gendisk *thedisk, dev_t devt, ++ int blocksize, struct page *page) ++{ ++ struct ext2_super_block * es; ++ struct block_device *bdev; ++ unsigned long sb_block = 1; ++ unsigned long logic_sb_block; ++ unsigned long offset = 0; ++ int rv = /* not found */ 0; ++ char bff[22]; ++ ++ bdev = bdget(devt); ++ if (blkdev_get(bdev, FMODE_READ, NULL)) { ++ printk(KERN_ERR "VFS: opening block device %s failed!\n", ++ format_dev_t(bff, devt)); ++ return (0); ++ } ++ ++ if (blocksize != BLOCK_SIZE) { ++ logic_sb_block = (sb_block*BLOCK_SIZE) / blocksize; ++ offset = (sb_block*BLOCK_SIZE) % blocksize; ++ } else { ++ logic_sb_block = sb_block; ++ } ++ ++// printk(KERN_ERR "D: attempting to read %d @%lu from " ++// "bdev %p devt %08X %s\n", blocksize, logic_sb_block, ++// bdev, devt, format_dev_t(bff, devt)); ++ if (!initcode_sync_page_read(bdev, logic_sb_block, blocksize, page)) { ++// printk(KERN_ERR "D: failed!\n"); ++ goto out; ++ } ++ es = (struct ext2_super_block *)(((char *)page_address(page)) + offset); ++ if (le16_to_cpu(es->s_magic) == EXT2_SUPER_MAGIC) { ++// printk(KERN_ERR "D: has uuid " ++// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", ++// es->s_uuid[0], es->s_uuid[1], es->s_uuid[2], es->s_uuid[3], ++// es->s_uuid[4], es->s_uuid[5], es->s_uuid[6], es->s_uuid[7], ++// es->s_uuid[8], es->s_uuid[9], es->s_uuid[10], es->s_uuid[11], ++// es->s_uuid[12], es->s_uuid[13], es->s_uuid[14], es->s_uuid[15]); ++ if (!memcmp(es->s_uuid, root_dev_uuid, 16)) ++ rv = /* found */ 1; ++ } ++// else printk(KERN_ERR "D: bad ext2fs magic\n"); ++ out: ++ blkdev_put(bdev, FMODE_READ); ++ return (rv); ++} ++#endif /* CONFIG_EXT2_FS for UUID support */ ++ + static int __init load_ramdisk(char *str) + { + rd_doload = simple_strtol(str,NULL,0) & 3; +@@ -218,6 +344,13 @@ + static int __init root_dev_setup(char *line) + { + strlcpy(saved_root_name, line, sizeof(saved_root_name)); ++#ifdef CONFIG_EXT2_FS ++ root_dev_type = 0; ++ if (!strncmp(line, "UUID=", 5)) { ++ root_dev_type = 1; ++ parse_uuid(line + 5); ++ } ++#endif /* CONFIG_EXT2_FS for UUID support */ + return 1; + } + +@@ -403,6 +536,83 @@ + + void __init mount_root(void) + { ++#ifdef CONFIG_EXT2_FS ++ /* UUID support */ ++// printk_all_partitions(); ++ if (root_dev_type == 1) { ++ int blocksize; ++ ++ /* from block/genhd.c printk_all_partitions */ ++ struct class_dev_iter iter; ++ struct device *dev; ++ ++ /* from drivers/md/md.c */ ++ struct page *sb_page; ++ ++ if (!(sb_page = alloc_page(GFP_KERNEL))) { ++ printk(KERN_ERR "VFS: no memory for bio page\n"); ++ goto nomemforbio; ++ } ++ ++// printk(KERN_ERR "D: root is: " ++// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", ++// root_dev_uuid[0], root_dev_uuid[1], root_dev_uuid[2], root_dev_uuid[3], ++// root_dev_uuid[4], root_dev_uuid[5], root_dev_uuid[6], root_dev_uuid[7], ++// root_dev_uuid[8], root_dev_uuid[9], root_dev_uuid[10], root_dev_uuid[11], ++// root_dev_uuid[12], root_dev_uuid[13], root_dev_uuid[14], root_dev_uuid[15]); ++ /* from block/genhd.c printk_all_partitions */ ++// printk(KERN_ERR "D: begin iter\n"); ++ class_dev_iter_init(&iter, &block_class, NULL, &disk_type); ++ while (root_dev_type && (dev = class_dev_iter_next(&iter))) { ++// char bff[22]; ++ struct gendisk *disk = dev_to_disk(dev); ++ struct disk_part_iter piter; ++ struct hd_struct *part; ++ if (get_capacity(disk) == 0 || ++ (disk->flags & GENHD_FL_SUPPRESS_PARTITION_INFO)) { ++// printk(KERN_ERR "D: ignoring\n"); ++ continue; ++ } ++ blocksize = queue_logical_block_size(disk->queue); ++// printk(KERN_ERR "D: gendisk, blocksize %d " ++// "name '%s' devt %08X %s #part %d\n", blocksize, ++// disk->disk_name, dev->devt, ++// format_dev_t(bff, dev->devt), ++// disk_max_parts(disk)); ++ disk_part_iter_init(&piter, disk, DISK_PITER_INCL_PART0); ++ while (root_dev_type && (part = disk_part_iter_next(&piter))) { ++ /* avoid empty or too small partitions */ ++// printk(KERN_ERR "D: part #%d start %llu " ++// "nr %llu\n", part->partno, ++// (__u64)part->start_sect, ++// (__u64)part->nr_sects); ++ if (part->nr_sects < 8) ++ continue; ++ if (check_dev(disk, MKDEV(MAJOR(dev->devt), ++ MINOR(dev->devt) + part->partno), ++ blocksize, sb_page)) { ++ ROOT_DEV = part_devt(part); ++// printk(KERN_ERR "D: got match!\n"); ++ // comment out below for debugging ++ root_dev_type = 0; ++ } ++ } ++ disk_part_iter_exit(&piter); ++ } ++// printk(KERN_ERR "D: end iter\n"); ++ class_dev_iter_exit(&iter); ++ put_page(sb_page); ++ } ++ nomemforbio: ++ if (root_dev_type == 1) ++ printk(KERN_ERR "VFS: Unable to find root by UUID %s.\n", ++ saved_root_name + 5); ++ else if (root_dev_type == 3) ++ /* execute deferred panic from parse_uuid */ ++ panic("Badly formatted UUID %s was supplied as kernel " ++ "parameter root", saved_root_name + 5); ++#endif /* CONFIG_EXT2_FS for UUID support */ ++ + #ifdef CONFIG_ROOT_NFS + if (MAJOR(ROOT_DEV) == UNNAMED_MAJOR) { + if (mount_nfs_root()) diff --git a/target/linux/patches/3.0.8/vga-cons-default-off.patch b/target/linux/patches/3.0.8/vga-cons-default-off.patch new file mode 100644 index 000000000..178aeeeb9 --- /dev/null +++ b/target/linux/patches/3.0.8/vga-cons-default-off.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.37.orig//drivers/video/console/Kconfig linux-2.6.37/drivers/video/console/Kconfig +--- linux-2.6.37.orig//drivers/video/console/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/drivers/video/console/Kconfig 2011-04-12 16:29:34.000000000 +0200 +@@ -7,7 +7,7 @@ + config VGA_CONSOLE + bool "VGA text console" if EMBEDDED || !X86 + depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) +- default y ++ default n + help + Saying Y here will allow you to use Linux in text mode through a + display that complies with the generic VGA standard. Virtually diff --git a/target/linux/patches/3.0.8/wlan-cf.patch b/target/linux/patches/3.0.8/wlan-cf.patch new file mode 100644 index 000000000..fc20759e2 --- /dev/null +++ b/target/linux/patches/3.0.8/wlan-cf.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c +--- linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c 2011-09-12 02:46:26.987984145 +0200 +@@ -623,6 +623,7 @@ + static struct pcmcia_device_id hostap_cs_ids[] = { + PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7100), + PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7300), ++ PCMCIA_DEVICE_MANF_CARD(0x0004, 0x2003), + PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0777), + PCMCIA_DEVICE_MANF_CARD(0x0126, 0x8000), + PCMCIA_DEVICE_MANF_CARD(0x0138, 0x0002), diff --git a/target/linux/patches/3.0.8/x86-build.patch b/target/linux/patches/3.0.8/x86-build.patch new file mode 100644 index 000000000..339140f41 --- /dev/null +++ b/target/linux/patches/3.0.8/x86-build.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c linux-2.6.39-rc6/arch/x86/boot/tools/build.c +--- linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/arch/x86/boot/tools/build.c 2011-05-05 20:10:07.000000000 +0200 +@@ -29,7 +29,6 @@ + #include + #include + #include +-#include + #include + #include + #include diff --git a/target/linux/patches/3.0.8/zlib-inflate.patch b/target/linux/patches/3.0.8/zlib-inflate.patch new file mode 100644 index 000000000..58e1f6d21 --- /dev/null +++ b/target/linux/patches/3.0.8/zlib-inflate.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.37.orig/lib/Kconfig linux-2.6.37/lib/Kconfig +--- linux-2.6.37.orig/lib/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/lib/Kconfig 2011-03-01 20:10:29.833370667 +0100 +@@ -95,7 +95,7 @@ + # compression support is select'ed if needed + # + config ZLIB_INFLATE +- tristate ++ boolean + + config ZLIB_DEFLATE + tristate -- cgit v1.2.3