From fb9bdbb294428e20981dd99af44fc038e8fb9e09 Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Tue, 25 Aug 2015 11:40:44 +0200 Subject: update 4.1.x to latest --- .../solidrun-imx6/patches/4.1.3/0001-xbian.patch | 171697 ------------------ .../solidrun-imx6/patches/4.1.6/0001-xbian.patch | 171697 ++++++++++++++++++ 2 files changed, 171697 insertions(+), 171697 deletions(-) delete mode 100644 target/arm/solidrun-imx6/patches/4.1.3/0001-xbian.patch create mode 100644 target/arm/solidrun-imx6/patches/4.1.6/0001-xbian.patch (limited to 'target/arm/solidrun-imx6') diff --git a/target/arm/solidrun-imx6/patches/4.1.3/0001-xbian.patch b/target/arm/solidrun-imx6/patches/4.1.3/0001-xbian.patch deleted file mode 100644 index 6286c0868..000000000 --- a/target/arm/solidrun-imx6/patches/4.1.3/0001-xbian.patch +++ /dev/null @@ -1,171697 +0,0 @@ -diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6dl.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6dl.dtsi ---- linux-4.1.3/arch/arm/boot/dts/imx6dl.dtsi 2015-07-21 19:10:33.000000000 +0200 -+++ linux-xbian-imx6/arch/arm/boot/dts/imx6dl.dtsi 2015-07-27 23:13:00.299912248 +0200 -@@ -60,17 +60,103 @@ - }; - - soc { -- ocram: sram@00900000 { -+ busfreq { /* BUSFREQ */ -+ compatible = "fsl,imx6_busfreq"; -+ clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, -+ <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 22> , <&clks 8>; -+ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", -+ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_sel", "pll3_pfd1_540m"; -+ interrupts = <0 107 0x04>, <0 112 0x4>; -+ interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; -+ fsl,max_ddr_freq = <400000000>; -+ }; -+ -+ gpu@00130000 { -+ compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu"; -+ reg = <0x00130000 0x4000>, <0x00134000 0x4000>, -+ <0x0 0x0>; -+ reg-names = "iobase_3d", "iobase_2d", -+ "phys_baseaddr"; -+ interrupts = <0 9 0x04>, <0 10 0x04>; -+ interrupt-names = "irq_3d", "irq_2d"; -+ clocks = <&clks 26>, <&clks 27>, -+ <&clks 121>, <&clks 122>, -+ <&clks 74>; -+ clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk", -+ "gpu2d_clk", "gpu3d_clk", -+ "gpu3d_shader_clk"; -+ resets = <&src 0>, <&src 3>; -+ reset-names = "gpu3d", "gpu2d"; -+ power-domains = <&gpc 1>; -+ }; -+ -+ hdmi_core: hdmi_core@00120000 { -+ compatible = "fsl,imx6q-hdmi-core"; -+ reg = <0x00120000 0x9000>; -+ clocks = <&clks 124>, <&clks 123>; -+ clock-names = "hdmi_isfr", "hdmi_iahb"; -+ status = "disabled"; -+ }; -+ -+ hdmi_video: hdmi_video@020e0000 { -+ compatible = "fsl,imx6q-hdmi-video"; -+ reg = <0x020e0000 0x1000>; -+ reg-names = "hdmi_gpr"; -+ interrupts = <0 115 0x04>; -+ clocks = <&clks 124>, <&clks 123>; -+ clock-names = "hdmi_isfr", "hdmi_iahb"; -+ status = "disabled"; -+ }; -+ -+ hdmi_audio: hdmi_audio@00120000 { -+ compatible = "fsl,imx6q-hdmi-audio"; -+ clocks = <&clks 124>, <&clks 123>; -+ clock-names = "hdmi_isfr", "hdmi_iahb"; -+ dmas = <&sdma 2 23 0>; -+ dma-names = "tx"; -+ status = "disabled"; -+ }; -+ -+ hdmi_cec: hdmi_cec@00120000 { -+ compatible = "fsl,imx6q-hdmi-cec"; -+ interrupts = <0 115 0x04>; -+ status = "disabled"; -+ }; -+ -+ ocrams: sram@00900000 { -+ compatible = "fsl,lpm-sram"; -+ reg = <0x00900000 0x4000>; -+ clocks = <&clks IMX6QDL_CLK_OCRAM>; -+ }; -+ -+ ocrams_ddr: sram@00904000 { -+ compatible = "fsl,ddr-lpm-sram"; -+ reg = <0x00904000 0x1000>; -+ clocks = <&clks IMX6QDL_CLK_OCRAM>; -+ }; -+ -+ ocram: sram@00905000 { - compatible = "mmio-sram"; -- reg = <0x00900000 0x20000>; -+ reg = <0x00905000 0x1B000>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - aips1: aips-bus@02000000 { -+ vpu@02040000 { -+ iramsize = <0>; -+ status = "okay"; -+ }; -+ - iomuxc: iomuxc@020e0000 { - compatible = "fsl,imx6dl-iomuxc"; - }; - -+ dcic2: dcic@020e8000 { -+ clocks = <&clks IMX6QDL_CLK_DCIC1 >, -+ <&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/ -+ clock-names = "dcic", "disp-axi"; -+ }; -+ - pxp: pxp@020f0000 { - reg = <0x020f0000 0x4000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; -@@ -99,26 +185,13 @@ - }; - }; - }; -- -- display-subsystem { -- compatible = "fsl,imx-display-subsystem"; -- ports = <&ipu1_di0>, <&ipu1_di1>; -- }; --}; -- --&hdmi { -- compatible = "fsl,imx6dl-hdmi"; - }; - - &ldb { -- clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, -- <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, -- <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; -+ clocks = <&clks 33>, <&clks 34>, -+ <&clks 39>, <&clks 40>, -+ <&clks 135>, <&clks 136>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; - }; -- --&vpu { -- compatible = "fsl,imx6dl-vpu", "cnm,coda960"; --}; -diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi ---- linux-4.1.3/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2015-07-21 19:10:33.000000000 +0200 -+++ linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2015-07-27 23:13:00.303898027 +0200 -@@ -45,11 +45,22 @@ - #include - - / { -+ chosen { -+ bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw"; -+ }; -+ -+ aliases { -+ mmc0 = &usdhc2; -+ mmc1 = &usdhc1; -+ mxcfb0 = &mxcfb1; -+ }; -+ - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 9 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_ir>; -+ linux,rc-map-name = "rc-rc6-mce"; - }; - - pwmleds { -@@ -78,6 +89,8 @@ - - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; -+ regulator-boot-on; -+ regulator-always-on; - enable-active-high; - gpio = <&gpio1 0 0>; - pinctrl-names = "default"; -@@ -89,6 +102,8 @@ - - reg_usbotg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; -+ regulator-boot-on; -+ regulator-always-on; - enable-active-high; - gpio = <&gpio3 22 0>; - pinctrl-names = "default"; -@@ -101,8 +116,7 @@ - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; -- model = "Integrated SPDIF"; -- /* IMX6 doesn't implement this yet */ -+ model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-out; - }; -@@ -118,12 +132,45 @@ - linux,code = ; - }; - }; -+ -+ sound-hdmi { -+ compatible = "fsl,imx6q-audio-hdmi", -+ "fsl,imx-audio-hdmi"; -+ model = "imx-audio-hdmi"; -+ hdmi-controller = <&hdmi_audio>; -+ }; -+ -+ mxcfb1: fb@0 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "hdmi"; -+ interface_pix_fmt = "RGB24"; -+ mode_str ="1920x1080M@60"; -+ default_bpp = <32>; -+ int_clk = <0>; -+ late_init = <0>; -+ status = "okay"; -+ }; -+}; -+ -+&hdmi_core { -+ ipu_id = <0>; -+ disp_id = <0>; -+ status = "okay"; -+}; -+ -+&hdmi_video { -+ fsl,phy_reg_vlev = <0x0294>; -+ fsl,phy_reg_cksymtx = <0x800d>; -+ status = "okay"; -+}; -+ -+&hdmi_audio { -+ status = "okay"; - }; - --&hdmi { -+&hdmi_cec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_hdmi>; -- ddc-i2c-bus = <&i2c2>; - status = "okay"; - }; - -@@ -131,7 +178,13 @@ - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_i2c2>; -+ - status = "okay"; -+ -+ ddc: imx6_hdmi_i2c@50 { -+ compatible = "fsl,imx6-hdmi-i2c"; -+ reg = <0x50>; -+ }; - }; - - &i2c3 { -@@ -228,6 +281,28 @@ - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059 - >; - }; -+ -+ pinctrl_cubox_i_usdhc2_100mhz: cubox-i-usdhc2-100mhz { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 -+ >; -+ }; -+ -+ pinctrl_cubox_i_usdhc2_200mhz: cubox-i-usdhc2-200mhz { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 -+ >; -+ }; - }; - }; - -@@ -256,9 +331,24 @@ - }; - - &usdhc2 { -- pinctrl-names = "default"; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>; -+ pinctrl-1 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_100mhz>; -+ pinctrl-2 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_200mhz>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio1 4 0>; - status = "okay"; -+ no-1-8-v; -+}; -+ -+&dcic1 { -+ dcic_id = <0>; -+ dcic_mux = "dcic-hdmi"; -+ status = "okay"; -+}; -+ -+&dcic2 { -+ dcic_id = <1>; -+ dcic_mux = "dcic-lvds1"; -+ status = "okay"; - }; -diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6qdl.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6qdl.dtsi ---- linux-4.1.3/arch/arm/boot/dts/imx6qdl.dtsi 2015-07-21 19:10:33.000000000 +0200 -+++ linux-xbian-imx6/arch/arm/boot/dts/imx6qdl.dtsi 2015-07-27 23:13:00.303898027 +0200 -@@ -14,6 +14,7 @@ - #include - - #include "skeleton.dtsi" -+#include - - / { - aliases { -@@ -30,6 +31,7 @@ - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; -+ ipu0 = &ipu1; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; -@@ -79,6 +81,10 @@ - }; - }; - -+ pu_dummy: pudummy_reg { -+ compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */ -+ }; -+ - soc { - #address-cells = <1>; - #size-cells = <1>; -@@ -86,6 +92,11 @@ - interrupt-parent = <&gpc>; - ranges; - -+ caam_sm: caam-sm@00100000 { -+ compatible = "fsl,imx6q-caam-sm"; -+ reg = <0x00100000 0x3fff>; -+ }; -+ - dma_apbh: dma-apbh@00110000 { - compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x00110000 0x2000>; -@@ -99,6 +110,12 @@ - clocks = <&clks IMX6QDL_CLK_APBH_DMA>; - }; - -+ irq_sec_vio: caam_secvio { -+ compatible = "fsl,imx6q-caam-secvio"; -+ interrupts = <0 20 0x04>; -+ secvio_src = <0x8000001d>; -+ }; -+ - gpmi: gpmi-nand@00112000 { - compatible = "fsl,imx6q-gpmi-nand"; - #address-cells = <1>; -@@ -190,16 +207,16 @@ - dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; - dma-names = "rx", "tx"; -- clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>, -- <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>, -- <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, -- <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, -- <&clks IMX6QDL_CLK_DUMMY>; -+ clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, -+ <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, -+ <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, -+ <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>, -+ <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", -- "rxtx7"; -+ "rxtx7", "dma"; - status = "disabled"; - }; - -@@ -274,7 +291,12 @@ - esai: esai@02024000 { - reg = <0x02024000 0x4000>; - interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; -- }; -+ compatible = "fsl,imx6q-esai"; -+ clocks = <&clks 118>; -+ fsl,esai-dma-events = <24 23>; -+ fsl,flags = <1>; -+ status = "disabled"; -+ }; - - ssi1: ssi@02028000 { - #sound-dai-cells = <0>; -@@ -325,8 +347,30 @@ - }; - - asrc: asrc@02034000 { -+ compatible = "fsl,imx53-asrc"; - reg = <0x02034000 0x4000>; - interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clks IMX6QDL_CLK_ASRC_MEM>, -+ <&clks IMX6QDL_CLK_ASRC_IPG>, -+ <&clks IMX6QDL_CLK_SPDIF>, -+ <&clks IMX6QDL_CLK_SPBA>; -+ clock-names = "mem", "ipg", "asrck_0", "dma"; -+ dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, <&sdma 19 20 1>, -+ <&sdma 20 20 1>, <&sdma 21 20 1>, <&sdma 22 20 1>; -+ dma-names = "rxa", "rxb", "rxc", -+ "txa", "txb", "txc"; -+ fsl,asrc-rate = <48000>; -+ fsl,asrc-width = <16>; -+ status = "okay"; -+ }; -+ -+ asrc_p2p: asrc_p2p { -+ compatible = "fsl,imx6q-asrc-p2p"; -+ fsl,output-rate = <48000>; -+ fsl,output-width = <16>; -+ fsl,asrc-dma-rx-events = <17 18 19>; -+ fsl,asrc-dma-tx-events = <20 21 22>; -+ status = "okay"; - }; - - spba@0203c000 { -@@ -335,16 +379,20 @@ - }; - - vpu: vpu@02040000 { -- compatible = "cnm,coda960"; -+ compatible = "cnm,coda960", "fsl,imx6-vpu"; - reg = <0x02040000 0x3c000>; -+ reg-names = "vpu_regs"; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, - <0 3 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "bit", "jpeg"; - clocks = <&clks IMX6QDL_CLK_VPU_AXI>, -- <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; -- clock-names = "per", "ahb"; -- resets = <&src 1>; -+ <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, -+ <&clks IMX6QDL_CLK_OCRAM>; -+ clock-names = "per", "ahb", "ocram"; -+ iramsize = <0x21000>; - iram = <&ocram>; -+ resets = <&src 1>; -+ power-domains = <&gpc 1>; - }; - - aipstz@0207c000 { /* AIPSTZ1 */ -@@ -552,20 +600,21 @@ - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; -+ anatop-enable-bit = <0>; - }; - -- regulator-3p0@120 { -+ reg_3p0: regulator-3p0@120 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; -- regulator-min-microvolt = <2800000>; -- regulator-max-microvolt = <3150000>; -- regulator-always-on; -+ regulator-min-microvolt = <2625000>; -+ regulator-max-microvolt = <3400000>; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; -+ anatop-enable-bit = <0>; - }; - - regulator-2p5@130 { -@@ -580,6 +629,7 @@ - anatop-min-bit-val = <0>; - anatop-min-voltage = <2000000>; - anatop-max-voltage = <2750000>; -+ anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore@140 { -@@ -647,6 +697,7 @@ - reg = <0x020c9000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBPHY1>; -+ phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - -@@ -655,9 +706,15 @@ - reg = <0x020ca000 0x1000>; - interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBPHY2>; -+ phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - -+ caam_snvs: caam-snvs@020cc000 { -+ compatible = "fsl,imx6q-caam-snvs"; -+ reg = <0x020cc000 0x4000>; -+ }; -+ - snvs@020cc000 { - compatible = "fsl,sec-v4.0-mon", "simple-bus"; - #address-cells = <1>; -@@ -704,14 +761,12 @@ - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&intc>; -- pu-supply = <®_pu>; -- clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, -- <&clks IMX6QDL_CLK_GPU3D_SHADER>, -- <&clks IMX6QDL_CLK_GPU2D_CORE>, -- <&clks IMX6QDL_CLK_GPU2D_AXI>, -- <&clks IMX6QDL_CLK_OPENVG_AXI>, -- <&clks IMX6QDL_CLK_VPU_AXI>; - #power-domain-cells = <1>; -+ clocks = <&clks 122>, <&clks 74>, <&clks 121>, -+ <&clks 26>, <&clks 143>, <&clks 168>; -+ clock-names = "gpu3d_core", "gpu3d_shader", "gpu2d_core", -+ "gpu2d_axi", "openvg_axi", "vpu_axi"; -+ pu-supply = <®_pu>; - }; - - gpr: iomuxc-gpr@020e0000 { -@@ -736,22 +791,6 @@ - #size-cells = <0>; - reg = <0>; - status = "disabled"; -- -- port@0 { -- reg = <0>; -- -- lvds0_mux_0: endpoint { -- remote-endpoint = <&ipu1_di0_lvds0>; -- }; -- }; -- -- port@1 { -- reg = <1>; -- -- lvds0_mux_1: endpoint { -- remote-endpoint = <&ipu1_di1_lvds0>; -- }; -- }; - }; - - lvds-channel@1 { -@@ -759,22 +798,6 @@ - #size-cells = <0>; - reg = <1>; - status = "disabled"; -- -- port@0 { -- reg = <0>; -- -- lvds1_mux_0: endpoint { -- remote-endpoint = <&ipu1_di0_lvds1>; -- }; -- }; -- -- port@1 { -- reg = <1>; -- -- lvds1_mux_1: endpoint { -- remote-endpoint = <&ipu1_di1_lvds1>; -- }; -- }; - }; - }; - -@@ -788,32 +811,26 @@ - <&clks IMX6QDL_CLK_HDMI_ISFR>; - clock-names = "iahb", "isfr"; - status = "disabled"; -- -- port@0 { -- reg = <0>; -- -- hdmi_mux_0: endpoint { -- remote-endpoint = <&ipu1_di0_hdmi>; -- }; -- }; -- -- port@1 { -- reg = <1>; -- -- hdmi_mux_1: endpoint { -- remote-endpoint = <&ipu1_di1_hdmi>; -- }; -- }; - }; - - dcic1: dcic@020e4000 { -+ compatible = "fsl,imx6q-dcic"; - reg = <0x020e4000 0x4000>; - interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>; -+ clock-names = "dcic", "disp-axi"; -+ gpr = <&gpr>; -+ status = "disabled"; - }; - - dcic2: dcic@020e8000 { -+ compatible = "fsl,imx6q-dcic"; - reg = <0x020e8000 0x4000>; - interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>; -+ clock-names = "dcic", "disp-axi"; -+ gpr = <&gpr>; -+ status = "disabled"; - }; - - sdma: sdma@020ec000 { -@@ -824,6 +841,7 @@ - <&clks IMX6QDL_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; -+ iram = <&ocram>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - }; -@@ -835,10 +853,30 @@ - reg = <0x02100000 0x100000>; - ranges; - -- caam@02100000 { -- reg = <0x02100000 0x40000>; -- interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>, -- <0 106 IRQ_TYPE_LEVEL_HIGH>; -+ crypto: caam@2100000 { -+ compatible = "fsl,sec-v4.0"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x2100000 0x40000>; -+ ranges = <0 0x2100000 0x40000>; -+ interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */ -+ interrupts = <0 92 0x4>; -+ clocks = <&clks 213>, <&clks 214>, <&clks 215> ,<&clks 196>; -+ clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow"; -+ -+ sec_jr0: jr0@1000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x1000 0x1000>; -+ interrupt-parent = <&intc>; -+ interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr1: jr1@2000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x2000 0x1000>; -+ interrupt-parent = <&intc>; -+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; -+ }; - }; - - aipstz@0217c000 { /* AIPSTZ2 */ -@@ -852,6 +890,7 @@ - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; -+ fsl,anatop = <&anatop>; - status = "disabled"; - }; - -@@ -903,14 +942,21 @@ - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp"; -- status = "disabled"; -+ phy-mode = "rgmii"; -+ fsl,magic-packet; -+ status = "okay"; - }; - -- mlb@0218c000 { -+ mlb: mlb@0218c000 { - reg = <0x0218c000 0x4000>; - interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, - <0 117 IRQ_TYPE_LEVEL_HIGH>, - <0 126 IRQ_TYPE_LEVEL_HIGH>; -+ compatible = "fsl,imx6q-mlb150"; -+ clocks = <&clks 139>, <&clks 175>; -+ clock-names = "mlb", "pll8_mlb"; -+ iram = <&ocram>; -+ status = "disabled"; - }; - - usdhc1: usdhc@02190000 { -@@ -995,6 +1041,11 @@ - reg = <0x021ac000 0x4000>; - }; - -+ mmdc0-1@021b0000 { -+ compatible = "fsl,imx6q-mmdc-combine"; -+ reg = <0x021b0000 0x8000>; -+ }; -+ - mmdc0: mmdc@021b0000 { /* MMDC0 */ - compatible = "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; -@@ -1011,11 +1062,17 @@ - clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; - }; - -- ocotp: ocotp@021bc000 { -- compatible = "fsl,imx6q-ocotp", "syscon"; -+ ocotp: ocotp-ctrl@021bc000 { -+ compatible = "syscon"; - reg = <0x021bc000 0x4000>; - }; - -+ ocotp-fuse@021bc000 { -+ compatible = "fsl,imx6q-ocotp"; -+ reg = <0x021bc000 0x4000>; -+ clocks = <&clks 128>; -+ }; -+ - tzasc@021d0000 { /* TZASC1 */ - reg = <0x021d0000 0x4000>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; -@@ -1034,39 +1091,38 @@ - - mipi_csi: mipi@021dc000 { - reg = <0x021dc000 0x4000>; -+ compatible = "fsl,imx6q-mipi-csi2"; -+ interrupts = <0 100 0x04>, <0 101 0x04>; -+ clocks = <&clks IMX6QDL_CLK_HSI_TX>, -+ <&clks IMX6QDL_CLK_EIM_SEL>, -+ <&clks IMX6QDL_CLK_LVDS2_IN>; -+ /* Note: clks 138 is hsi_tx, however, the dphy_c -+ * hsi_tx and pll_refclk use the same clk gate. -+ * In current clk driver, open/close clk gate do -+ * use hsi_tx for a temporary debug purpose. -+ */ -+ clock-names = "dphy_clk", "pixel_clk", "cfg_clk"; -+ status = "disabled"; - }; - - mipi_dsi: mipi@021e0000 { -+ compatible = "fsl,imx6q-mipi-dsi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x021e0000 0x4000>; - status = "disabled"; -- -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- port@0 { -- reg = <0>; -- -- mipi_mux_0: endpoint { -- remote-endpoint = <&ipu1_di0_mipi>; -- }; -- }; -- -- port@1 { -- reg = <1>; -- -- mipi_mux_1: endpoint { -- remote-endpoint = <&ipu1_di1_mipi>; -- }; -- }; -- }; -+ interrupts = <0 102 0x04>; -+ gpr = <&gpr>; -+ clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; -+ clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; - }; - - vdoa@021e4000 { -+ compatible = "fsl,imx6q-vdoa"; - reg = <0x021e4000 0x4000>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clks 202>; -+ iram = <&ocram>; - }; - - uart2: serial@021e8000 { -@@ -1127,67 +1183,14 @@ - <0 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPU1>, - <&clks IMX6QDL_CLK_IPU1_DI0>, -- <&clks IMX6QDL_CLK_IPU1_DI1>; -- clock-names = "bus", "di0", "di1"; -+ <&clks IMX6QDL_CLK_IPU1_DI1>, -+ <&clks 39>, <&clks 40>, -+ <&clks 135>, <&clks 136>; -+ clock-names = "bus", "di0", "di1", -+ "di0_sel", "di1_sel", -+ "ldb_di0", "ldb_di1"; - resets = <&src 2>; -- -- ipu1_csi0: port@0 { -- reg = <0>; -- }; -- -- ipu1_csi1: port@1 { -- reg = <1>; -- }; -- -- ipu1_di0: port@2 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <2>; -- -- ipu1_di0_disp0: endpoint@0 { -- }; -- -- ipu1_di0_hdmi: endpoint@1 { -- remote-endpoint = <&hdmi_mux_0>; -- }; -- -- ipu1_di0_mipi: endpoint@2 { -- remote-endpoint = <&mipi_mux_0>; -- }; -- -- ipu1_di0_lvds0: endpoint@3 { -- remote-endpoint = <&lvds0_mux_0>; -- }; -- -- ipu1_di0_lvds1: endpoint@4 { -- remote-endpoint = <&lvds1_mux_0>; -- }; -- }; -- -- ipu1_di1: port@3 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <3>; -- -- ipu1_di0_disp1: endpoint@0 { -- }; -- -- ipu1_di1_hdmi: endpoint@1 { -- remote-endpoint = <&hdmi_mux_1>; -- }; -- -- ipu1_di1_mipi: endpoint@2 { -- remote-endpoint = <&mipi_mux_1>; -- }; -- -- ipu1_di1_lvds0: endpoint@3 { -- remote-endpoint = <&lvds0_mux_1>; -- }; -- -- ipu1_di1_lvds1: endpoint@4 { -- remote-endpoint = <&lvds1_mux_1>; -- }; -- }; -+ bypass_reset = <0>; - }; - }; - }; -diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi ---- linux-4.1.3/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi 2015-07-21 19:10:33.000000000 +0200 -+++ linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi 2015-07-27 23:13:00.303898027 +0200 -@@ -43,8 +43,10 @@ - #include "imx6qdl-microsom-ar8035.dtsi" - - / { -- chosen { -- stdout-path = &uart1; -+ aliases { -+ mmc0 = &usdhc2; -+ mmc1 = &usdhc1; -+ mxcfb0 = &mxcfb1; - }; - - ir_recv: ir-receiver { -@@ -52,6 +54,7 @@ - gpios = <&gpio3 5 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>; -+ linux,rc-map-name = "rc-rc6-mce"; - }; - - regulators { -@@ -98,32 +101,70 @@ - model = "On-board Codec"; - mux-ext-port = <5>; - mux-int-port = <1>; -+ cpu-dai = <&ssi1>; - ssi-controller = <&ssi1>; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; -- model = "On-board SPDIF"; -+ model = "imx-spdif"; - /* IMX6 doesn't implement this yet */ - spdif-controller = <&spdif>; - spdif-out; - }; -+ -+ sound-hdmi { -+ compatible = "fsl,imx6q-audio-hdmi", -+ "fsl,imx-audio-hdmi"; -+ model = "imx-audio-hdmi"; -+ hdmi-controller = <&hdmi_audio>; -+ }; -+ -+ mxcfb1: fb@0 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "hdmi"; -+ interface_pix_fmt = "RGB24"; -+ mode_str ="1920x1080M@60"; -+ default_bpp = <32>; -+ int_clk = <0>; -+ late_init = <0>; -+ status = "okay"; -+ }; - }; - - &audmux { - status = "okay"; - }; - --&can1 { -+/*&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; - status = "okay"; - }; -+*/ -+&hdmi_core { -+ ipu_id = <0>; -+ disp_id = <0>; -+ status = "okay"; -+}; -+ -+&hdmi_video { -+ fsl,phy_reg_vlev = <0x0294>; -+ fsl,phy_reg_cksymtx = <0x800d>; -+ status = "okay"; -+}; -+ -+&hdmi_audio { -+ status = "okay"; -+}; -+ -+&ocram { -+ status = "okay"; -+}; - --&hdmi { -+&hdmi_cec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_hdmi>; -- ddc-i2c-bus = <&i2c2>; - status = "okay"; - }; - -@@ -136,6 +177,7 @@ - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; -+ nxp,12p5_pf; - }; - - /* Pro baseboard model */ -@@ -155,20 +197,57 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c2>; - status = "okay"; -+ -+ ddc: imx6_hdmi_i2c@50 { -+ compatible = "fsl,imx6-hdmi-i2c"; -+ reg = <0x50>; -+ }; - }; - - &iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; - hummingboard { -- pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ /* -+ * 26 pin header GPIO description. The pins. -+ * numbering as following - -+ * GPIO number | GPIO (bank,num) | PIN number -+ * ------------+-----------------+------------ -+ * gpio1 | (1,1) | IO7 -+ * gpio73 | (3,9) | IO11 -+ * gpio72 | (3,8) | IO12 -+ * gpio71 | (3,7) | IO13 -+ * gpio70 | (3,6) | IO15 -+ * gpio194 | (7,2) | IO16 -+ * gpio195 | (7,3) | IO18 -+ * gpio67 | (3,3) | IO22 -+ * -+ * Notice the gpioX and GPIO (Y,Z) mapping forumla : -+ * X = (Y-1) * 32 + Z -+ */ -+ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x400130b1 -+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 -+ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 -+ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 -+ MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 -+ MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x400130b1 -+ MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x400130b1 -+ MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 -+ >; -+ }; -+ -+/* pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000 - >; - }; -- -+*/ - pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 { - fsl,pins = < -- MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 -+ MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x80000000 - >; - }; - -@@ -198,10 +277,10 @@ - - pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 { - fsl,pins = < -- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 -- MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 -- MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 -- MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 -+ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 /*brk*/ -+ MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /*ok*/ -+ MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /*brk*/ -+ MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /*ok*/ - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 - >; - }; -@@ -219,7 +298,7 @@ - * Similar to pinctrl_usbotg_2, but we want it - * pulled down for a fixed host connection. - */ -- fsl,pins = ; -+ fsl,pins = ; - }; - - pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { -@@ -242,6 +321,13 @@ - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; -+ -+ pinctrl_hummingboard_pcie_reset: hummingboard-pcie-reset { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x80000000 -+ >; -+ }; -+ - }; - }; - -@@ -256,6 +342,14 @@ - status = "okay"; - }; - -+&pwm3 { -+ status = "disabled"; -+}; -+ -+&pwm4 { -+ status = "disabled"; -+}; -+ - &spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_spdif>; -@@ -291,3 +385,48 @@ - cd-gpios = <&gpio1 4 0>; - status = "okay"; - }; -+ -+&gpc { -+ fsl,cpu_pupscr_sw2iso = <0xf>; -+ fsl,cpu_pupscr_sw = <0xf>; -+ fsl,cpu_pdnscr_iso2sw = <0x1>; -+ fsl,cpu_pdnscr_iso = <0x1>; -+ status = "okay"; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = < -+ &pinctrl_hummingboard_pcie_reset -+ >; -+ reset-gpio = <&gpio3 4 0>; -+ status = "okay"; -+ no-msi; -+}; -+ -+&ecspi1 { -+ status = "okay"; -+ fsl,spi-num-chipselects = <1>; -+}; -+ -+&ecspi2 { -+ status = "okay"; -+ fsl,spi-num-chipselects = <2>; -+}; -+ -+&ecspi3 { -+ status = "okay"; -+ fsl,spi-num-chipselects = <3>; -+}; -+ -+&dcic1 { -+ dcic_id = <0>; -+ dcic_mux = "dcic-hdmi"; -+ status = "okay"; -+}; -+ -+&dcic2 { -+ dcic_id = <1>; -+ dcic_mux = "dcic-lvds1"; -+ status = "okay"; -+}; -diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6qdl-microsom.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-microsom.dtsi ---- linux-4.1.3/arch/arm/boot/dts/imx6qdl-microsom.dtsi 2015-07-21 19:10:33.000000000 +0200 -+++ linux-xbian-imx6/arch/arm/boot/dts/imx6qdl-microsom.dtsi 2015-07-27 23:13:00.303898027 +0200 -@@ -39,15 +39,98 @@ - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -+#include -+/ { -+ clk_sdio: sdio-clock { -+ compatible = "gpio-gate-clock"; -+ #clock-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_microsom_brcm_osc>; -+ enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ -+ reg_brcm: brcm-reg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio3 19 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_microsom_brcm_reg>; -+ regulator-name = "brcm_reg"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <200000>; -+ }; -+ }; -+ -+ usdhc1_pwrseq: usdhc1_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, -+ <&gpio6 0 GPIO_ACTIVE_LOW>; -+ clocks = <&clk_sdio>; -+ clock-names = "ext_clock"; -+ }; -+}; - - &iomuxc { - microsom { -+ pinctrl_microsom_brcm_bt: microsom-brcm-bt { -+ fsl,pins = < -+ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 -+ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070 -+ MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 -+ >; -+ }; -+ -+ pinctrl_microsom_brcm_osc: microsom-brcm-osc { -+ fsl,pins = < -+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 -+ >; -+ }; -+ -+ pinctrl_microsom_brcm_reg: microsom-brcm-reg { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070 -+ >; -+ }; -+ -+ pinctrl_microsom_brcm_wifi: microsom-brcm-wifi { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 -+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070 -+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 -+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070 -+ >; -+ }; -+ - pinctrl_microsom_uart1: microsom-uart1 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; -+ -+ pinctrl_microsom_uart4: microsom-uart4 { -+ fsl,pins = < -+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 -+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 -+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_microsom_usdhc1: microsom-usdhc1 { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 -+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 -+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 -+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 -+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 -+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 -+ >; -+ }; - }; - }; - -@@ -56,3 +139,23 @@ - pinctrl-0 = <&pinctrl_microsom_uart1>; - status = "okay"; - }; -+ -+/* UART4 - Connected to optional BRCM Wifi/BT/FM */ -+&uart4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>; -+ fsl,uart-has-rtscts; -+ status = "okay"; -+}; -+ -+/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */ -+&usdhc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>; -+ bus-width = <4>; -+ mmc-pwrseq = <&usdhc1_pwrseq>; -+ keep-power-in-suspend; -+ non-removable; -+ vmmc-supply = <®_brcm>; -+ status = "okay"; -+}; -diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6q.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6q.dtsi ---- linux-4.1.3/arch/arm/boot/dts/imx6q.dtsi 2015-07-21 19:10:33.000000000 +0200 -+++ linux-xbian-imx6/arch/arm/boot/dts/imx6q.dtsi 2015-07-27 23:13:00.303898027 +0200 -@@ -14,6 +14,7 @@ - - / { - aliases { -+ ipu1 = &ipu2; - spi4 = &ecspi5; - }; - -@@ -47,9 +48,12 @@ - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, -- <&clks IMX6QDL_CLK_PLL1_SYS>; -+ <&clks IMX6QDL_CLK_PLL1_SYS>, -+ <&clks IMX6QDL_PLL1_BYPASS>, -+ <&clks IMX6QDL_CLK_PLL1>, -+ <&clks IMX6QDL_PLL1_BYPASS_SRC> ; - clock-names = "arm", "pll2_pfd2_396m", "step", -- "pll1_sw", "pll1_sys"; -+ "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; -@@ -78,9 +82,85 @@ - }; - - soc { -- ocram: sram@00900000 { -+ -+ busfreq { /* BUSFREQ */ -+ compatible = "fsl,imx6_busfreq"; -+ clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, -+ <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>; -+ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", -+ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc"; -+ interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>; -+ interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; -+ fsl,max_ddr_freq = <528000000>; -+ }; -+ -+ gpu@00130000 { -+ compatible = "fsl,imx6q-gpu"; -+ reg = <0x00130000 0x4000>, <0x00134000 0x4000>, -+ <0x02204000 0x4000>, <0x0 0x0>; -+ reg-names = "iobase_3d", "iobase_2d", -+ "iobase_vg", "phys_baseaddr"; -+ interrupts = <0 9 0x04>, <0 10 0x04>,<0 11 0x04>; -+ interrupt-names = "irq_3d", "irq_2d", "irq_vg"; -+ clocks = <&clks 26>, <&clks 143>, -+ <&clks 27>, <&clks 121>, -+ <&clks 122>, <&clks 74>; -+ clock-names = "gpu2d_axi_clk", "openvg_axi_clk", -+ "gpu3d_axi_clk", "gpu2d_clk", -+ "gpu3d_clk", "gpu3d_shader_clk"; -+ resets = <&src 0>, <&src 3>, <&src 3>; -+ reset-names = "gpu3d", "gpu2d", "gpuvg"; -+ power-domains = <&gpc 1>; -+ }; -+ -+ hdmi_core: hdmi_core@00120000 { -+ compatible = "fsl,imx6q-hdmi-core"; -+ reg = <0x00120000 0x9000>; -+ clocks = <&clks 124>, <&clks 123>; -+ clock-names = "hdmi_isfr", "hdmi_iahb"; -+ status = "disabled"; -+ }; -+ -+ hdmi_video: hdmi_video@020e0000 { -+ compatible = "fsl,imx6q-hdmi-video"; -+ reg = <0x020e0000 0x1000>; -+ reg-names = "hdmi_gpr"; -+ interrupts = <0 115 0x04>; -+ clocks = <&clks 124>, <&clks 123>; -+ clock-names = "hdmi_isfr", "hdmi_iahb"; -+ status = "disabled"; -+ }; -+ -+ hdmi_audio: hdmi_audio@00120000 { -+ compatible = "fsl,imx6q-hdmi-audio"; -+ clocks = <&clks 124>, <&clks 123>; -+ clock-names = "hdmi_isfr", "hdmi_iahb"; -+ dmas = <&sdma 2 23 0>; -+ dma-names = "tx"; -+ status = "disabled"; -+ }; -+ -+ hdmi_cec: hdmi_cec@00120000 { -+ compatible = "fsl,imx6q-hdmi-cec"; -+ interrupts = <0 115 0x04>; -+ status = "disabled"; -+ }; -+ -+ ocrams: sram@00900000 { -+ compatible = "fsl,lpm-sram"; -+ reg = <0x00900000 0x4000>; -+ clocks = <&clks IMX6QDL_CLK_OCRAM>; -+ }; -+ -+ ocrams_ddr: sram@00904000 { -+ compatible = "fsl,ddr-lpm-sram"; -+ reg = <0x00904000 0x1000>; -+ clocks = <&clks IMX6QDL_CLK_OCRAM>; -+ }; -+ -+ ocram: sram@00905000 { - compatible = "mmio-sram"; -- reg = <0x00900000 0x40000>; -+ reg = <0x00905000 0x3B000>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - -@@ -101,6 +181,10 @@ - }; - }; - -+ vpu@02040000 { -+ status = "okay"; -+ }; -+ - iomuxc: iomuxc@020e0000 { - compatible = "fsl,imx6q-iomuxc"; - -@@ -154,165 +238,33 @@ - }; - - ipu2: ipu@02800000 { -- #address-cells = <1>; -- #size-cells = <0>; - compatible = "fsl,imx6q-ipu"; - reg = <0x02800000 0x400000>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, - <0 7 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&clks IMX6QDL_CLK_IPU2>, -- <&clks IMX6QDL_CLK_IPU2_DI0>, -- <&clks IMX6QDL_CLK_IPU2_DI1>; -- clock-names = "bus", "di0", "di1"; -+ clocks = <&clks 133>, <&clks 134>, <&clks 137>, -+ <&clks 41>, <&clks 42>, -+ <&clks 135>, <&clks 136>; -+ clock-names = "bus", "di0", "di1", -+ "di0_sel", "di1_sel", -+ "ldb_di0", "ldb_di1"; - resets = <&src 4>; -- -- ipu2_csi0: port@0 { -- reg = <0>; -- }; -- -- ipu2_csi1: port@1 { -- reg = <1>; -- }; -- -- ipu2_di0: port@2 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <2>; -- -- ipu2_di0_disp0: endpoint@0 { -- }; -- -- ipu2_di0_hdmi: endpoint@1 { -- remote-endpoint = <&hdmi_mux_2>; -- }; -- -- ipu2_di0_mipi: endpoint@2 { -- }; -- -- ipu2_di0_lvds0: endpoint@3 { -- remote-endpoint = <&lvds0_mux_2>; -- }; -- -- ipu2_di0_lvds1: endpoint@4 { -- remote-endpoint = <&lvds1_mux_2>; -- }; -- }; -- -- ipu2_di1: port@3 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <3>; -- -- ipu2_di1_hdmi: endpoint@1 { -- remote-endpoint = <&hdmi_mux_3>; -- }; -- -- ipu2_di1_mipi: endpoint@2 { -- }; -- -- ipu2_di1_lvds0: endpoint@3 { -- remote-endpoint = <&lvds0_mux_3>; -- }; -- -- ipu2_di1_lvds1: endpoint@4 { -- remote-endpoint = <&lvds1_mux_3>; -- }; -- }; -- }; -- }; -- -- display-subsystem { -- compatible = "fsl,imx-display-subsystem"; -- ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; -- }; --}; -- --&hdmi { -- compatible = "fsl,imx6q-hdmi"; -- -- port@2 { -- reg = <2>; -- -- hdmi_mux_2: endpoint { -- remote-endpoint = <&ipu2_di0_hdmi>; -- }; -- }; -- -- port@3 { -- reg = <3>; -- -- hdmi_mux_3: endpoint { -- remote-endpoint = <&ipu2_di1_hdmi>; -+ bypass_reset = <0>; - }; - }; - }; - - &ldb { -- clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, -+ clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, -- <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; -- clock-names = "di0_pll", "di1_pll", -- "di0_sel", "di1_sel", "di2_sel", "di3_sel", -- "di0", "di1"; -- -- lvds-channel@0 { -- port@2 { -- reg = <2>; -- -- lvds0_mux_2: endpoint { -- remote-endpoint = <&ipu2_di0_lvds0>; -- }; -- }; -- -- port@3 { -- reg = <3>; -- -- lvds0_mux_3: endpoint { -- remote-endpoint = <&ipu2_di1_lvds0>; -- }; -- }; -- }; -- -- lvds-channel@1 { -- port@2 { -- reg = <2>; -- -- lvds1_mux_2: endpoint { -- remote-endpoint = <&ipu2_di0_lvds1>; -- }; -- }; -- -- port@3 { -- reg = <3>; -- -- lvds1_mux_3: endpoint { -- remote-endpoint = <&ipu2_di1_lvds1>; -- }; -- }; -- }; --}; -- --&mipi_dsi { -- ports { -- port@2 { -- reg = <2>; -- -- mipi_mux_2: endpoint { -- remote-endpoint = <&ipu2_di0_mipi>; -- }; -- }; -- -- port@3 { -- reg = <3>; -- -- mipi_mux_3: endpoint { -- remote-endpoint = <&ipu2_di1_mipi>; -- }; -- }; -- }; --}; -- --&vpu { -- compatible = "fsl,imx6q-vpu", "cnm,coda960"; -+ <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, -+ <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, -+ <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>; -+ clock-names = "ldb_di0", "ldb_di1", -+ "di0_sel", "di1_sel", -+ "di2_sel", "di3_sel", -+ "ldb_di0_div_3_5", "ldb_di1_div_3_5", -+ "ldb_di0_div_7", "ldb_di1_div_7", -+ "ldb_di0_div_sel", "ldb_di1_div_sel"; - }; -diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6q-hummingboard.dts linux-xbian-imx6/arch/arm/boot/dts/imx6q-hummingboard.dts ---- linux-4.1.3/arch/arm/boot/dts/imx6q-hummingboard.dts 2015-07-21 19:10:33.000000000 +0200 -+++ linux-xbian-imx6/arch/arm/boot/dts/imx6q-hummingboard.dts 2015-07-27 23:13:00.303898027 +0200 -@@ -57,3 +57,7 @@ - fsl,transmit-atten-16ths = <9>; - fsl,receive-eq-mdB = <3000>; - }; -+ -+&sgtl5000 { -+ status = "okay"; -+}; -diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6sl.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6sl.dtsi ---- linux-4.1.3/arch/arm/boot/dts/imx6sl.dtsi 2015-07-21 19:10:33.000000000 +0200 -+++ linux-xbian-imx6/arch/arm/boot/dts/imx6sl.dtsi 2015-07-27 23:13:00.307883804 +0200 -@@ -457,20 +457,21 @@ - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; -+ anatop-enable-bit = <0>; - }; - -- regulator-3p0@120 { -+ reg_3p0: regulator-3p0@120 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; -- regulator-min-microvolt = <2800000>; -- regulator-max-microvolt = <3150000>; -- regulator-always-on; -+ regulator-min-microvolt = <2625000>; -+ regulator-max-microvolt = <3400000>; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; -+ anatop-enable-bit = <0>; - }; - - regulator-2p5@130 { -@@ -485,6 +486,7 @@ - anatop-min-bit-val = <0>; - anatop-min-voltage = <2100000>; - anatop-max-voltage = <2850000>; -+ anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore@140 { -@@ -552,6 +554,7 @@ - reg = <0x020c9000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBPHY1>; -+ phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - -@@ -560,6 +563,7 @@ - reg = <0x020ca000 0x1000>; - interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBPHY2>; -+ phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - -diff -Nur linux-4.1.3/arch/arm/boot/dts/imx6sx.dtsi linux-xbian-imx6/arch/arm/boot/dts/imx6sx.dtsi ---- linux-4.1.3/arch/arm/boot/dts/imx6sx.dtsi 2015-07-21 19:10:33.000000000 +0200 -+++ linux-xbian-imx6/arch/arm/boot/dts/imx6sx.dtsi 2015-07-27 23:13:00.307883804 +0200 -@@ -556,20 +556,21 @@ - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; -+ anatop-enable-bit = <0>; - }; - -- regulator-3p0@120 { -+ reg_3p0: regulator-3p0@120 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; -- regulator-min-microvolt = <2800000>; -- regulator-max-microvolt = <3150000>; -- regulator-always-on; -+ regulator-min-microvolt = <2625000>; -+ regulator-max-microvolt = <3400000>; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; -+ anatop-enable-bit = <0>; - }; - - regulator-2p5@130 { -@@ -584,6 +585,7 @@ - anatop-min-bit-val = <0>; - anatop-min-voltage = <2100000>; - anatop-max-voltage = <2875000>; -+ anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore@140 { -@@ -650,6 +652,7 @@ - reg = <0x020c9000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBPHY1>; -+ phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - -@@ -658,6 +661,7 @@ - reg = <0x020ca000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBPHY2>; -+ phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - -diff -Nur linux-4.1.3/arch/arm/include/asm/glue-cache.h linux-xbian-imx6/arch/arm/include/asm/glue-cache.h ---- linux-4.1.3/arch/arm/include/asm/glue-cache.h 2015-07-21 19:10:33.000000000 +0200 -+++ linux-xbian-imx6/arch/arm/include/asm/glue-cache.h 2015-07-27 23:13:00.746319518 +0200 -@@ -102,19 +102,19 @@ - #endif - - #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) --# ifdef _CACHE -+//# ifdef _CACHE - # define MULTI_CACHE 1 --# else --# define _CACHE v6 --# endif -+//# else -+//# define _CACHE v6 -+//# endif - #endif - - #if defined(CONFIG_CPU_V7) --# ifdef _CACHE -+//# ifdef _CACHE - # define MULTI_CACHE 1 --# else --# define _CACHE v7 --# endif -+//# else -+//# define _CACHE v7 -+//# endif - #endif - - #if defined(CONFIG_CPU_V7M) -diff -Nur linux-4.1.3/arch/arm/Kconfig linux-xbian-imx6/arch/arm/Kconfig ---- linux-4.1.3/arch/arm/Kconfig 2015-07-21 19:10:33.000000000 +0200 -+++ linux-xbian-imx6/arch/arm/Kconfig 2015-07-27 23:13:00.128523741 +0200 -@@ -1688,6 +1688,7 @@ - range 11 64 if ARCH_SHMOBILE_LEGACY - default "12" if SOC_AM33XX - default "9" if SA1111 || ARCH_EFM32 -+ default "14" if ARCH_MXC - default "11" - help - The kernel memory allocator divides physically contiguous memory -diff -Nur linux-4.1.3/arch/arm/mach-imx/busfreq_ddr3.c linux-xbian-imx6/arch/arm/mach-imx/busfreq_ddr3.c ---- linux-4.1.3/arch/arm/mach-imx/busfreq_ddr3.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-xbian-imx6/arch/arm/mach-imx/busfreq_ddr3.c 2015-07-27 23:13:01.073153409 +0200 -@@ -0,0 +1,514 @@ -+/* -+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file busfreq_ddr3.c -+ * -+ * @brief iMX6 DDR3 frequency change specific file. -+ * -+ * @ingroup PM -+ */ -+#define DEBUG -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "hardware.h" -+ -+/* DDR settings */ -+static unsigned long (*iram_ddr_settings)[2]; -+static unsigned long (*normal_mmdc_settings)[2]; -+static unsigned long (*iram_iomux_settings)[2]; -+static void __iomem *mmdc_base; -+static void __iomem *iomux_base; -+static void __iomem *ccm_base; -+static void __iomem *l2_base; -+static void __iomem *gic_dist_base; -+static u32 *irqs_used; -+ -+static void *ddr_freq_change_iram_base; -+static int ddr_settings_size; -+static int iomux_settings_size; -+static volatile unsigned int cpus_in_wfe; -+static volatile bool wait_for_ddr_freq_update; -+static int curr_ddr_rate; -+ -+void (*mx6_change_ddr_freq)(u32 freq, void *ddr_settings, -+ bool dll_mode, void *iomux_offsets) = NULL; -+ -+extern unsigned int ddr_med_rate; -+extern unsigned int ddr_normal_rate; -+extern int low_bus_freq_mode; -+extern int audio_bus_freq_mode; -+extern void mx6_ddr3_freq_change(u32 freq, void *ddr_settings, -+ bool dll_mode, void *iomux_offsets); -+extern unsigned long save_ttbr1(void); -+extern void restore_ttbr1(unsigned long ttbr1); -+ -+#ifdef CONFIG_SMP -+extern void __iomem *imx_scu_base; -+static unsigned int online_cpus; -+#endif -+ -+#define MIN_DLL_ON_FREQ 333000000 -+#define MAX_DLL_OFF_FREQ 125000000 -+#define DDR_FREQ_CHANGE_SIZE 0x2000 -+ -+unsigned long ddr3_dll_mx6q[][2] = { -+ {0x0c, 0x0}, -+ {0x10, 0x0}, -+ {0x1C, 0x04088032}, -+ {0x1C, 0x0408803a}, -+ {0x1C, 0x08408030}, -+ {0x1C, 0x08408038}, -+ {0x818, 0x0}, -+}; -+ -+unsigned long ddr3_calibration[][2] = { -+ {0x83c, 0x0}, -+ {0x840, 0x0}, -+ {0x483c, 0x0}, -+ {0x4840, 0x0}, -+ {0x848, 0x0}, -+ {0x4848, 0x0}, -+ {0x850, 0x0}, -+ {0x4850, 0x0}, -+}; -+ -+unsigned long ddr3_dll_mx6dl[][2] = { -+ {0x0c, 0x0}, -+ {0x10, 0x0}, -+ {0x1C, 0x04008032}, -+ {0x1C, 0x0400803a}, -+ {0x1C, 0x07208030}, -+ {0x1C, 0x07208038}, -+ {0x818, 0x0}, -+}; -+ -+unsigned long iomux_offsets_mx6q[][2] = { -+ {0x5A8, 0x0}, -+ {0x5B0, 0x0}, -+ {0x524, 0x0}, -+ {0x51C, 0x0}, -+ {0x518, 0x0}, -+ {0x50C, 0x0}, -+ {0x5B8, 0x0}, -+ {0x5C0, 0x0}, -+}; -+ -+unsigned long iomux_offsets_mx6dl[][2] = { -+ {0x4BC, 0x0}, -+ {0x4C0, 0x0}, -+ {0x4C4, 0x0}, -+ {0x4C8, 0x0}, -+ {0x4CC, 0x0}, -+ {0x4D0, 0x0}, -+ {0x4D4, 0x0}, -+ {0x4D8, 0x0}, -+}; -+ -+unsigned long ddr3_400[][2] = { -+ {0x83c, 0x42490249}, -+ {0x840, 0x02470247}, -+ {0x483c, 0x42570257}, -+ {0x4840, 0x02400240}, -+ {0x848, 0x4039363C}, -+ {0x4848, 0x3A39333F}, -+ {0x850, 0x38414441}, -+ {0x4850, 0x472D4833} -+}; -+ -+int can_change_ddr_freq(void) -+{ -+ return 0; -+} -+ -+/* -+ * each active core apart from the one changing -+ * the DDR frequency will execute this function. -+ * the rest of the cores have to remain in WFE -+ * state until the frequency is changed. -+ */ -+irqreturn_t wait_in_wfe_irq(int irq, void *dev_id) -+{ -+ u32 me = smp_processor_id(); -+ -+ *((char *)(&cpus_in_wfe) + (u8)me) = 0xff; -+ -+ while (wait_for_ddr_freq_update) -+ wfe(); -+ -+ *((char *)(&cpus_in_wfe) + (u8)me) = 0; -+ -+ return IRQ_HANDLED; -+} -+ -+/* change the DDR frequency. */ -+int update_ddr_freq(int ddr_rate) -+{ -+ int i, j; -+ bool dll_off = false; -+ int me = 0; -+ unsigned long ttbr1; -+#ifdef CONFIG_SMP -+ unsigned int reg; -+ int cpu = 0; -+#endif -+ -+ if (!can_change_ddr_freq()) -+ return -1; -+ -+ if (ddr_rate == curr_ddr_rate) -+ return 0; -+ -+ printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate); -+ -+ if (low_bus_freq_mode || audio_bus_freq_mode) -+ dll_off = true; -+ -+ iram_ddr_settings[0][0] = ddr_settings_size; -+ iram_iomux_settings[0][0] = iomux_settings_size; -+ if (ddr_rate == ddr_med_rate && cpu_is_imx6q() && -+ ddr_med_rate != ddr_normal_rate) { -+ for (i = 0; i < ARRAY_SIZE(ddr3_dll_mx6q); i++) { -+ iram_ddr_settings[i + 1][0] = -+ normal_mmdc_settings[i][0]; -+ iram_ddr_settings[i + 1][1] = -+ normal_mmdc_settings[i][1]; -+ } -+ for (j = 0, i = ARRAY_SIZE(ddr3_dll_mx6q); -+ i < iram_ddr_settings[0][0]; j++, i++) { -+ iram_ddr_settings[i + 1][0] = -+ ddr3_400[j][0]; -+ iram_ddr_settings[i + 1][1] = -+ ddr3_400[j][1]; -+ } -+ } else if (ddr_rate == ddr_normal_rate) { -+ for (i = 0; i < iram_ddr_settings[0][0]; i++) { -+ iram_ddr_settings[i + 1][0] = -+ normal_mmdc_settings[i][0]; -+ iram_ddr_settings[i + 1][1] = -+ normal_mmdc_settings[i][1]; -+ } -+ } -+ -+ /* ensure that all Cores are in WFE. */ -+ local_irq_disable(); -+ -+#ifdef CONFIG_SMP -+ me = smp_processor_id(); -+ -+ /* Make sure all the online cores are active */ -+ while (1) { -+ bool not_exited_busfreq = false; -+ for_each_online_cpu(cpu) { -+ u32 reg = __raw_readl(imx_scu_base + 0x08); -+ if (reg & (0x02 << (cpu * 8))) -+ not_exited_busfreq = true; -+ } -+ if (!not_exited_busfreq) -+ break; -+ } -+ -+ wmb(); -+ wait_for_ddr_freq_update = 1; -+ dsb(); -+ -+ online_cpus = readl_relaxed(imx_scu_base + 0x08); -+ for_each_online_cpu(cpu) { -+ *((char *)(&online_cpus) + (u8)cpu) = 0x02; -+ if (cpu != me) { -+ /* set the interrupt to be pending in the GIC. */ -+ reg = 1 << (irqs_used[cpu] % 32); -+ writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET -+ + (irqs_used[cpu] / 32) * 4); -+ } -+ } -+ /* Wait for the other active CPUs to idle */ -+ while (1) { -+ u32 reg = readl_relaxed(imx_scu_base + 0x08); -+ reg |= (0x02 << (me * 8)); -+ if (reg == online_cpus) -+ break; -+ } -+#endif -+ -+ /* Ensure iram_tlb_phys_addr is flushed to DDR. */ -+ /*__cpuc_flush_dcache_area(&iram_tlb_phys_addr, sizeof(iram_tlb_phys_addr)); -+ outer_clean_range(virt_to_phys(&iram_tlb_phys_addr), virt_to_phys(&iram_tlb_phys_addr + 1));*/ -+ -+ /* -+ * Flush the TLB, to ensure no TLB maintenance occurs -+ * when DDR is in self-refresh. -+ */ -+ local_flush_tlb_all(); -+ -+ ttbr1 = save_ttbr1(); -+ /* Now we can change the DDR frequency. */ -+ mx6_change_ddr_freq(ddr_rate, iram_ddr_settings, -+ dll_off, iram_iomux_settings); -+ restore_ttbr1(ttbr1); -+ curr_ddr_rate = ddr_rate; -+ -+#ifdef CONFIG_SMP -+ wmb(); -+ /* DDR frequency change is done . */ -+ wait_for_ddr_freq_update = 0; -+ dsb(); -+ -+ /* wake up all the cores. */ -+ sev(); -+#endif -+ -+ local_irq_enable(); -+ -+ printk(KERN_DEBUG "Bus freq set to %d done! cpu=%d\n", ddr_rate, me); -+ -+ return 0; -+} -+ -+int init_mmdc_ddr3_settings(struct platform_device *busfreq_pdev) -+{ -+ struct device *dev = &busfreq_pdev->dev; -+ struct platform_device *ocram_dev; -+ unsigned int iram_paddr; -+ int i, err; -+ u32 cpu; -+ struct device_node *node; -+ struct gen_pool *iram_pool; -+ -+ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc-combine"); -+ if (!node) { -+ pr_err("failed to find imx6q-mmdc device tree data!\n"); -+ return -EINVAL; -+ } -+ mmdc_base = of_iomap(node, 0); -+ WARN(!mmdc_base, "unable to map mmdc registers\n"); -+ -+ node = NULL; -+ if (cpu_is_imx6q()) -+ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-iomuxc"); -+ if (cpu_is_imx6dl()) -+ node = of_find_compatible_node(NULL, NULL, -+ "fsl,imx6dl-iomuxc"); -+ if (!node) { -+ pr_err("failed to find imx6q-iomux device tree data!\n"); -+ return -EINVAL; -+ } -+ iomux_base = of_iomap(node, 0); -+ WARN(!iomux_base, "unable to map iomux registers\n"); -+ -+ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm"); -+ if (!node) { -+ pr_err("failed to find imx6q-ccm device tree data!\n"); -+ return -EINVAL; -+ } -+ ccm_base = of_iomap(node, 0); -+ WARN(!ccm_base, "unable to map mmdc registers\n"); -+ -+ node = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); -+ if (!node) { -+ pr_err("failed to find imx6q-pl310-cache device tree data!\n"); -+ return -EINVAL; -+ } -+ l2_base = of_iomap(node, 0); -+ WARN(!ccm_base, "unable to map mmdc registers\n"); -+ -+ node = NULL; -+ node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); -+ if (!node) { -+ pr_err("failed to find imx6q-a9-gic device tree data!\n"); -+ return -EINVAL; -+ } -+ gic_dist_base = of_iomap(node, 0); -+ WARN(!gic_dist_base, "unable to map gic dist registers\n"); -+ -+ if (cpu_is_imx6q()) -+ ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6q) + -+ ARRAY_SIZE(ddr3_calibration); -+ if (cpu_is_imx6dl()) -+ ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6dl) + -+ ARRAY_SIZE(ddr3_calibration); -+ -+ normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL); -+ if (cpu_is_imx6q()) { -+ memcpy(normal_mmdc_settings, ddr3_dll_mx6q, -+ sizeof(ddr3_dll_mx6q)); -+ memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6q)), -+ ddr3_calibration, sizeof(ddr3_calibration)); -+ } -+ if (cpu_is_imx6dl()) { -+ memcpy(normal_mmdc_settings, ddr3_dll_mx6dl, -+ sizeof(ddr3_dll_mx6dl)); -+ memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6dl)), -+ ddr3_calibration, sizeof(ddr3_calibration)); -+ } -+ /* store the original DDR settings at boot. */ -+ for (i = 0; i < ddr_settings_size; i++) { -+ /* -+ * writes via command mode register cannot be read back. -+ * hence hardcode them in the initial static array. -+ * this may require modification on a per customer basis. -+ */ -+ if (normal_mmdc_settings[i][0] != 0x1C) -+ normal_mmdc_settings[i][1] = -+ readl_relaxed(mmdc_base -+ + normal_mmdc_settings[i][0]); -+ } -+ -+ irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(), -+ GFP_KERNEL); -+ -+ for_each_online_cpu(cpu) { -+ int irq; -+ -+ /* -+ * set up a reserved interrupt to get all -+ * the active cores into a WFE state -+ * before changing the DDR frequency. -+ */ -+ irq = platform_get_irq(busfreq_pdev, cpu); -+ err = request_irq(irq, wait_in_wfe_irq, -+ IRQF_PERCPU, "mmdc_1", NULL); -+ if (err) { -+ dev_err(dev, -+ "Busfreq:request_irq failed %d, err = %d\n", -+ irq, err); -+ return err; -+ } -+ err = irq_set_affinity(irq, cpumask_of(cpu)); -+ if (err) { -+ dev_err(dev, -+ "Busfreq: Cannot set irq affinity irq=%d,\n", -+ irq); -+ return err; -+ } -+ irqs_used[cpu] = irq; -+ } -+ -+ node = NULL; -+ node = of_find_compatible_node(NULL, NULL, "mmio-sram"); -+ if (!node) { -+ dev_err(dev, "%s: failed to find ocram node\n", -+ __func__); -+ return -EINVAL; -+ } -+ -+ ocram_dev = of_find_device_by_node(node); -+ if (!ocram_dev) { -+ dev_err(dev, "failed to find ocram device!\n"); -+ return -EINVAL; -+ } -+ -+ iram_pool = dev_get_gen_pool(&ocram_dev->dev); -+ if (!iram_pool) { -+ dev_err(dev, "iram pool unavailable!\n"); -+ return -EINVAL; -+ } -+ -+ iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6q); -+ iram_iomux_settings = (void*)gen_pool_alloc(iram_pool, -+ (iomux_settings_size * 8) + 8); -+ if (!iram_iomux_settings) { -+ dev_err(dev, "unable to alloc iram for IOMUX settings!\n"); -+ return -ENOMEM; -+ } -+ -+ /* -+ * Allocate extra space to store the number of entries in the -+ * ddr_settings plus 4 extra regsiter information that needs -+ * to be passed to the frequency change code. -+ * sizeof(iram_ddr_settings) = sizeof(ddr_settings) + -+ * entries in ddr_settings + 16. -+ * The last 4 enties store the addresses of the registers: -+ * CCM_BASE_ADDR -+ * MMDC_BASE_ADDR -+ * IOMUX_BASE_ADDR -+ * L2X0_BASE_ADDR -+ */ -+ iram_ddr_settings = (void*)gen_pool_alloc(iram_pool, -+ (ddr_settings_size * 8) + 8 + 32); -+ if (!iram_ddr_settings) { -+ dev_err(dev, "unable to alloc iram for ddr settings!\n"); -+ return -ENOMEM; -+ } -+ i = ddr_settings_size + 1; -+ iram_ddr_settings[i][0] = (unsigned long)mmdc_base; -+ iram_ddr_settings[i+1][0] = (unsigned long)ccm_base; -+ iram_ddr_settings[i+2][0] = (unsigned long)iomux_base; -+ iram_ddr_settings[i+3][0] = (unsigned long)l2_base; -+ -+ if (cpu_is_imx6q()) { -+ /* store the IOMUX settings at boot. */ -+ for (i = 0; i < iomux_settings_size; i++) { -+ iomux_offsets_mx6q[i][1] = -+ readl_relaxed(iomux_base + -+ iomux_offsets_mx6q[i][0]); -+ iram_iomux_settings[i+1][0] = iomux_offsets_mx6q[i][0]; -+ iram_iomux_settings[i+1][1] = iomux_offsets_mx6q[i][1]; -+ } -+ } -+ -+ if (cpu_is_imx6dl()) { -+ for (i = 0; i < iomux_settings_size; i++) { -+ iomux_offsets_mx6dl[i][1] = -+ readl_relaxed(iomux_base + -+ iomux_offsets_mx6dl[i][0]); -+ iram_iomux_settings[i+1][0] = iomux_offsets_mx6dl[i][0]; -+ iram_iomux_settings[i+1][1] = iomux_offsets_mx6dl[i][1]; -+ } -+ } -+ -+ ddr_freq_change_iram_base = (void*)gen_pool_alloc(iram_pool, -+ DDR_FREQ_CHANGE_SIZE); -+ if (!ddr_freq_change_iram_base) { -+ dev_err(dev, "Cannot alloc iram for ddr freq change code!\n"); -+ return -ENOMEM; -+ } -+ -+ iram_paddr = gen_pool_virt_to_phys(iram_pool, -+ (unsigned long)ddr_freq_change_iram_base); -+ /* -+ * Need to remap the area here since we want -+ * the memory region to be executable. -+ */ -+ ddr_freq_change_iram_base = __arm_ioremap(iram_paddr, -+ DDR_FREQ_CHANGE_SIZE, -+ MT_MEMORY_RWX_NONCACHED); -+ mx6_change_ddr_freq = (void *)fncpy(ddr_freq_change_iram_base, -+ &mx6_ddr3_freq_change, DDR_FREQ_CHANGE_SIZE); -+ -+ curr_ddr_rate = ddr_normal_rate; -+ -+ return 0; -+} -diff -Nur linux-4.1.3/arch/arm/mach-imx/busfreq-imx6.c linux-xbian-imx6/arch/arm/mach-imx/busfreq-imx6.c ---- linux-4.1.3/arch/arm/mach-imx/busfreq-imx6.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-xbian-imx6/arch/arm/mach-imx/busfreq-imx6.c 2015-07-27 23:13:01.073153409 +0200 -@@ -0,0 +1,984 @@ -+/* -+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -+ */ -+ -+/*! -+ * @file busfreq-imx6.c -+ * -+ * @brief A common API for the Freescale Semiconductor iMX6 Busfreq API -+ * -+ * The APIs are for setting bus frequency to different values based on the -+ * highest freqeuncy requested. -+ * -+ * @ingroup PM -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "hardware.h" -+ -+#define LPAPM_CLK 24000000 -+#define DDR3_AUDIO_CLK 50000000 -+#define LPDDR2_AUDIO_CLK 100000000 -+ -+int vpu352 = 0; -+ -+int high_bus_freq_mode; -+int med_bus_freq_mode; -+int audio_bus_freq_mode; -+int low_bus_freq_mode; -+int ultra_low_bus_freq_mode; -+unsigned int ddr_med_rate; -+unsigned int ddr_normal_rate; -+ -+#ifdef CONFIG_ARM_IMX6Q_CPUFREQ -+static int bus_freq_scaling_initialized; -+static struct device *busfreq_dev; -+static int busfreq_suspended; -+static u32 org_arm_rate; -+static int bus_freq_scaling_is_active; -+static int high_bus_count, med_bus_count, audio_bus_count, low_bus_count; -+static unsigned int ddr_low_rate; -+ -+extern int init_mmdc_lpddr2_settings(struct platform_device *dev); -+extern int init_mmdc_ddr3_settings(struct platform_device *dev); -+extern int update_ddr_freq(int ddr_rate); -+extern int update_lpddr2_freq(int ddr_rate); -+ -+DEFINE_MUTEX(bus_freq_mutex); -+static DEFINE_SPINLOCK(freq_lock); -+ -+static struct clk *pll2_400; -+static struct clk *periph_clk; -+static struct clk *periph_pre_clk; -+static struct clk *periph_clk2_sel; -+static struct clk *periph_clk2; -+static struct clk *osc_clk; -+static struct clk *cpu_clk; -+stati