From e8f74f7222ddc977bf775e31101980b9311b7200 Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Sat, 22 Oct 2011 18:26:23 +0200 Subject: add xfs_growfs --- package/xfsprogs/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/package/xfsprogs/Makefile b/package/xfsprogs/Makefile index 2af6fc389..a5b49b895 100644 --- a/package/xfsprogs/Makefile +++ b/package/xfsprogs/Makefile @@ -5,7 +5,7 @@ include ${TOPDIR}/rules.mk PKG_NAME:= xfsprogs PKG_VERSION:= 3.1.5 -PKG_RELEASE:= 1 +PKG_RELEASE:= 2 PKG_MD5SUM:= b1db37749e2b4149a0dd178abff956be PKG_DESCR:= Utilities for XFS filesystems PKG_SECTION:= fs @@ -32,5 +32,6 @@ do-install: ${INSTALL_DIR} ${IDIR_XFSPROGS}/usr/sbin ${INSTALL_BIN} ${WRKBUILD}/mkfs/mkfs.xfs ${IDIR_XFSPROGS}/usr/sbin ${INSTALL_BIN} ${WRKBUILD}/repair/xfs_repair ${IDIR_XFSPROGS}/usr/sbin + ${INSTALL_BIN} ${WRKBUILD}/growfs/xfs_growfs ${IDIR_XFSPROGS}/usr/sbin include ${TOPDIR}/mk/pkg-bottom.mk -- cgit v1.2.3 From ca68bf14a3b7f6406599308174e959b5b312bef3 Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Sat, 22 Oct 2011 18:39:39 +0200 Subject: some more FreeBSD fixes --- package/classpath/Makefile | 1 + package/glib/Makefile | 7 ++++--- package/orbit2/Makefile | 1 + 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/package/classpath/Makefile b/package/classpath/Makefile index 2a9199e55..e63c84e7a 100644 --- a/package/classpath/Makefile +++ b/package/classpath/Makefile @@ -14,6 +14,7 @@ PKG_DEPENDS:= libgtk gdk-pixbuf orbit2 gconf PKG_URL:= http://www.gnu.org/software/classpath/home.html PKG_SITES:= ${MASTER_SITE_GNU:=classpath/} +PKG_HOST_DEPENDS:= linux PKG_ARCH_DEPENDS:= !cris !arm include $(TOPDIR)/mk/package.mk diff --git a/package/glib/Makefile b/package/glib/Makefile index 692e5c8af..a5df0225f 100644 --- a/package/glib/Makefile +++ b/package/glib/Makefile @@ -43,10 +43,11 @@ CONFIGURE_ENV+= glib_cv_long_long_format=ll \ ac_cv_func_posix_getgrgid_r=yes pre-configure: -ifneq ($(OStype),Darwin) +ifneq ($(OStype),FreeBSD) (cd ${WRKBUILD}; rm -rf config.{cache,status}; \ - ./configure --prefix=$(STAGING_HOST_DIR) \ - ); + CFLAGS="-L/usr/local/lib" ./configure --prefix=$(STAGING_HOST_DIR) \ + --with-libiconv=gnu \ + ) ${MAKE} -C ${WRKBUILD} V=1 $(CP) ${WRKBUILD}/gio/.libs/glib-compile-schemas ${STAGING_HOST_DIR}/bin $(CP) ${WRKBUILD}/gobject/.libs/glib-genmarshal ${STAGING_HOST_DIR}/bin diff --git a/package/orbit2/Makefile b/package/orbit2/Makefile index 81317669d..c30fa35ed 100644 --- a/package/orbit2/Makefile +++ b/package/orbit2/Makefile @@ -26,6 +26,7 @@ $(eval $(call PKG_template,ORBIT2,orbit2,$(PKG_VERSION)-${PKG_RELEASE},${PKG_DEP $(eval $(call PKG_template,ORBIT2_DEV,orbit2-dev,$(PKG_VERSION)-${PKG_RELEASE},${PKG_DEPENDS},${PKGSD_ORBIT2_DEV},${PKGSC_ORBIT2_DEV})) CFLAGS_FOR_BUILD+= $(shell ${BUILD_LIBIDL_CONFIG} --cflags) +CFLAGS_FOR_BUILD+= -I/usr/local/include LDFLAGS_FOR_BUILD+= $(shell ${BUILD_LIBIDL_CONFIG} --libs) LDFLAGS_FOR_BUILD+= -lgmodule-2.0 CONFIGURE_ENV+= ac_cv_alignof_CORBA_octet=1 \ -- cgit v1.2.3 From d9cd3aca2bf0689374fc71227dd42f629209b868 Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Sat, 22 Oct 2011 19:26:12 +0200 Subject: correct broken patch --- toolchain/gcc/patches/4.4.6/gcc-avr32.patch | 24270 ++++---------------------- 1 file changed, 3806 insertions(+), 20464 deletions(-) diff --git a/toolchain/gcc/patches/4.4.6/gcc-avr32.patch b/toolchain/gcc/patches/4.4.6/gcc-avr32.patch index 0b092c07c..f348cba9c 100644 --- a/toolchain/gcc/patches/4.4.6/gcc-avr32.patch +++ b/toolchain/gcc/patches/4.4.6/gcc-avr32.patch @@ -1,6 +1,6 @@ diff -Nur gcc-4.4.6.orig/gcc/builtins.c gcc-4.4.6/gcc/builtins.c --- gcc-4.4.6.orig/gcc/builtins.c 2010-12-07 19:56:56.000000000 +0100 -+++ gcc-4.4.6/gcc/builtins.c 2011-08-27 19:45:42.559232404 +0200 ++++ gcc-4.4.6/gcc/builtins.c 2011-10-22 19:23:08.512581300 +0200 @@ -11108,7 +11108,7 @@ do @@ -12,7 +12,7 @@ diff -Nur gcc-4.4.6.orig/gcc/builtins.c gcc-4.4.6/gcc/builtins.c case 0: diff -Nur gcc-4.4.6.orig/gcc/calls.c gcc-4.4.6/gcc/calls.c --- gcc-4.4.6.orig/gcc/calls.c 2010-09-24 17:07:36.000000000 +0200 -+++ gcc-4.4.6/gcc/calls.c 2011-08-27 19:45:42.589240794 +0200 ++++ gcc-4.4.6/gcc/calls.c 2011-10-22 19:23:08.512581300 +0200 @@ -3447,7 +3447,7 @@ for (; count < nargs; count++) { @@ -22,13 +22,13 @@ diff -Nur gcc-4.4.6.orig/gcc/calls.c gcc-4.4.6/gcc/calls.c /* We cannot convert the arg value to the mode the library wants here; must do it earlier where we know the signedness of the arg. */ -diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32.c gcc-4.4.6/gcc/config/avr32/avr32.c ---- gcc-4.4.6.orig/gcc/config/avr32/avr32.c 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/avr32.c 2011-08-27 19:45:59.051740454 +0200 -@@ -0,0 +1,8087 @@ +diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32-elf.h gcc-4.4.6/gcc/config/avr32/avr32-elf.h +--- gcc-4.4.6.orig/gcc/config/avr32/avr32-elf.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-4.4.6/gcc/config/avr32/avr32-elf.h 2011-10-22 19:23:08.516581300 +0200 +@@ -0,0 +1,91 @@ +/* -+ Target hooks and helper functions for AVR32. -+ Copyright 2003,2004,2005,2006,2007,2008,2009,2010 Atmel Corporation. ++ Elf specific definitions. ++ Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation. + + This file is part of GCC. + @@ -46,2857 +46,3157 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32.c gcc-4.4.6/gcc/config/avr32/avr + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + -+#include "config.h" -+#include "system.h" -+#include "coretypes.h" -+#include "tm.h" -+#include "rtl.h" -+#include "tree.h" -+#include "obstack.h" -+#include "regs.h" -+#include "hard-reg-set.h" -+#include "real.h" -+#include "insn-config.h" -+#include "conditions.h" -+#include "output.h" -+#include "insn-attr.h" -+#include "flags.h" -+#include "reload.h" -+#include "function.h" -+#include "expr.h" -+#include "optabs.h" -+#include "toplev.h" -+#include "recog.h" -+#include "ggc.h" -+#include "except.h" -+#include "c-pragma.h" -+#include "integrate.h" -+#include "tm_p.h" -+#include "langhooks.h" -+#include "hooks.h" -+#include "df.h" + -+#include "target.h" -+#include "target-def.h" ++/***************************************************************************** ++ * Controlling the Compiler Driver, 'gcc' ++ *****************************************************************************/ + -+#include ++/* Run-time Target Specification. */ ++#undef TARGET_VERSION ++#define TARGET_VERSION fputs (" (AVR32 GNU with ELF)", stderr); + ++/* ++Another C string constant used much like LINK_SPEC. The ++difference between the two is that STARTFILE_SPEC is used at ++the very beginning of the command given to the linker. + ++If this macro is not defined, a default is provided that loads the ++standard C startup file from the usual place. See gcc.c. ++*/ ++#if 0 ++#undef STARTFILE_SPEC ++#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s" ++#endif ++#undef STARTFILE_SPEC ++#define STARTFILE_SPEC "%{mflashvault: crtfv.o%s} %{!mflashvault: crt0.o%s} \ ++ crti.o%s crtbegin.o%s" + -+/* Global variables. */ -+typedef struct minipool_node Mnode; -+typedef struct minipool_fixup Mfix; ++#undef LINK_SPEC ++#define LINK_SPEC "%{muse-oscall:--defsym __do_not_use_oscall_coproc__=0} %{mrelax|O*:%{mno-relax|O0|O1: ;:--relax}} %{mpart=uc3a3revd:-mavr32elf_uc3a3256s;:%{mpart=*:-mavr32elf_%*}} %{mcpu=*:-mavr32elf_%*}" + -+/* Obstack for minipool constant handling. */ -+static struct obstack minipool_obstack; -+static char *minipool_startobj; -+static rtx minipool_vector_label; + -+/* True if we are currently building a constant table. */ -+int making_const_table; ++/* ++Another C string constant used much like LINK_SPEC. The ++difference between the two is that ENDFILE_SPEC is used at ++the very end of the command given to the linker. + -+tree fndecl_attribute_args = NULL_TREE; ++Do not define this macro if it does not need to do anything. ++*/ ++#undef ENDFILE_SPEC ++#define ENDFILE_SPEC "crtend%O%s crtn%O%s" + + -+/* Function prototypes. */ -+static unsigned long avr32_isr_value (tree); -+static unsigned long avr32_compute_func_type (void); -+static tree avr32_handle_isr_attribute (tree *, tree, tree, int, bool *); -+static tree avr32_handle_acall_attribute (tree *, tree, tree, int, bool *); -+static tree avr32_handle_fndecl_attribute (tree * node, tree name, tree args, -+ int flags, bool * no_add_attrs); -+static void avr32_reorg (void); -+bool avr32_return_in_msb (tree type); -+bool avr32_vector_mode_supported (enum machine_mode mode); -+static void avr32_init_libfuncs (void); -+static void avr32_file_end (void); -+static void flashvault_decl_list_add (unsigned int vector_num, const char *name); ++/* Target CPU builtins. */ ++#define TARGET_CPU_CPP_BUILTINS() \ ++ do \ ++ { \ ++ builtin_define ("__avr32__"); \ ++ builtin_define ("__AVR32__"); \ ++ builtin_define ("__AVR32_ELF__"); \ ++ builtin_define (avr32_part->macro); \ ++ builtin_define (avr32_arch->macro); \ ++ if (avr32_arch->uarch_type == UARCH_TYPE_AVR32A) \ ++ builtin_define ("__AVR32_AVR32A__"); \ ++ else \ ++ builtin_define ("__AVR32_AVR32B__"); \ ++ if (TARGET_UNALIGNED_WORD) \ ++ builtin_define ("__AVR32_HAS_UNALIGNED_WORD__"); \ ++ if (TARGET_SIMD) \ ++ builtin_define ("__AVR32_HAS_SIMD__"); \ ++ if (TARGET_DSP) \ ++ builtin_define ("__AVR32_HAS_DSP__"); \ ++ if (TARGET_RMW) \ ++ builtin_define ("__AVR32_HAS_RMW__"); \ ++ if (TARGET_BRANCH_PRED) \ ++ builtin_define ("__AVR32_HAS_BRANCH_PRED__"); \ ++ if (TARGET_FAST_FLOAT) \ ++ builtin_define ("__AVR32_FAST_FLOAT__"); \ ++ if (TARGET_FLASHVAULT) \ ++ builtin_define ("__AVR32_FLASHVAULT__"); \ ++ if (TARGET_NO_MUL_INSNS) \ ++ builtin_define ("__AVR32_NO_MUL__"); \ ++ } \ ++ while (0) +diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32-modes.def gcc-4.4.6/gcc/config/avr32/avr32-modes.def +--- gcc-4.4.6.orig/gcc/config/avr32/avr32-modes.def 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-4.4.6/gcc/config/avr32/avr32-modes.def 2011-10-22 19:23:08.524581303 +0200 +@@ -0,0 +1 @@ ++VECTOR_MODES (INT, 4); /* V4QI V2HI */ +diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32-protos.h gcc-4.4.6/gcc/config/avr32/avr32-protos.h +--- gcc-4.4.6.orig/gcc/config/avr32/avr32-protos.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-4.4.6/gcc/config/avr32/avr32-protos.h 2011-10-22 19:23:08.524581303 +0200 +@@ -0,0 +1,196 @@ ++/* ++ Prototypes for exported functions defined in avr32.c ++ Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation. + ++ This file is part of GCC. + ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 2 of the License, or ++ (at your option) any later version. + -+static void -+avr32_add_gc_roots (void) -+{ -+ gcc_obstack_init (&minipool_obstack); -+ minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); -+} ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. + ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + -+/* List of all known AVR32 parts */ -+static const struct part_type_s avr32_part_types[] = { -+ /* name, part_type, architecture type, macro */ -+ {"none", PART_TYPE_AVR32_NONE, ARCH_TYPE_AVR32_AP, "__AVR32__"}, -+ {"ap7000", PART_TYPE_AVR32_AP7000, ARCH_TYPE_AVR32_AP, "__AVR32_AP7000__"}, -+ {"ap7001", PART_TYPE_AVR32_AP7001, ARCH_TYPE_AVR32_AP, "__AVR32_AP7001__"}, -+ {"ap7002", PART_TYPE_AVR32_AP7002, ARCH_TYPE_AVR32_AP, "__AVR32_AP7002__"}, -+ {"ap7200", PART_TYPE_AVR32_AP7200, ARCH_TYPE_AVR32_AP, "__AVR32_AP7200__"}, -+ {"uc3a0128", PART_TYPE_AVR32_UC3A0128, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A0128__"}, -+ {"uc3a0256", PART_TYPE_AVR32_UC3A0256, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A0256__"}, -+ {"uc3a0512", PART_TYPE_AVR32_UC3A0512, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A0512__"}, -+ {"uc3a0512es", PART_TYPE_AVR32_UC3A0512ES, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3A0512ES__"}, -+ {"uc3a1128", PART_TYPE_AVR32_UC3A1128, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A1128__"}, -+ {"uc3a1256", PART_TYPE_AVR32_UC3A1256, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A1256__"}, -+ {"uc3a1512", PART_TYPE_AVR32_UC3A1512, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A1512__"}, -+ {"uc3a1512es", PART_TYPE_AVR32_UC3A1512ES, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3A1512ES__"}, -+ {"uc3a3revd", PART_TYPE_AVR32_UC3A3REVD, ARCH_TYPE_AVR32_UCR2NOMUL, "__AVR32_UC3A3256S__"}, -+ {"uc3a364", PART_TYPE_AVR32_UC3A364, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A364__"}, -+ {"uc3a364s", PART_TYPE_AVR32_UC3A364S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A364S__"}, -+ {"uc3a3128", PART_TYPE_AVR32_UC3A3128, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A3128__"}, -+ {"uc3a3128s", PART_TYPE_AVR32_UC3A3128S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A3128S__"}, -+ {"uc3a3256", PART_TYPE_AVR32_UC3A3256, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A3256__"}, -+ {"uc3a3256s", PART_TYPE_AVR32_UC3A3256S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A3256S__"}, -+ {"uc3a464", PART_TYPE_AVR32_UC3A464, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A464__"}, -+ {"uc3a464s", PART_TYPE_AVR32_UC3A464S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A464S__"}, -+ {"uc3a4128", PART_TYPE_AVR32_UC3A4128, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A4128__"}, -+ {"uc3a4128s", PART_TYPE_AVR32_UC3A4128S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A4128S__"}, -+ {"uc3a4256", PART_TYPE_AVR32_UC3A4256, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A4256__"}, -+ {"uc3a4256s", PART_TYPE_AVR32_UC3A4256S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A4256S__"}, -+ {"uc3b064", PART_TYPE_AVR32_UC3B064, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B064__"}, -+ {"uc3b0128", PART_TYPE_AVR32_UC3B0128, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B0128__"}, -+ {"uc3b0256", PART_TYPE_AVR32_UC3B0256, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B0256__"}, -+ {"uc3b0256es", PART_TYPE_AVR32_UC3B0256ES, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B0256ES__"}, -+ {"uc3b0512", PART_TYPE_AVR32_UC3B0512, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3B0512__"}, -+ {"uc3b0512revc", PART_TYPE_AVR32_UC3B0512REVC, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3B0512REVC__"}, -+ {"uc3b164", PART_TYPE_AVR32_UC3B164, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B164__"}, -+ {"uc3b1128", PART_TYPE_AVR32_UC3B1128, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B1128__"}, -+ {"uc3b1256", PART_TYPE_AVR32_UC3B1256, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B1256__"}, -+ {"uc3b1256es", PART_TYPE_AVR32_UC3B1256ES, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B1256ES__"}, -+ {"uc3b1512", PART_TYPE_AVR32_UC3B1512, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3B1512__"}, -+ {"uc3b1512revc", PART_TYPE_AVR32_UC3B1512REVC, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3B1512REVC__"}, -+ {"uc64d3", PART_TYPE_AVR32_UC64D3, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC64D3__"}, -+ {"uc128d3", PART_TYPE_AVR32_UC128D3, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC128D3__"}, -+ {"uc64d4", PART_TYPE_AVR32_UC64D4, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC64D4__"}, -+ {"uc128d4", PART_TYPE_AVR32_UC128D4, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC128D4__"}, -+ {"uc3c0512crevc", PART_TYPE_AVR32_UC3C0512CREVC, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3C0512CREVC__"}, -+ {"uc3c1512crevc", PART_TYPE_AVR32_UC3C1512CREVC, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3C1512CREVC__"}, -+ {"uc3c2512crevc", PART_TYPE_AVR32_UC3C2512CREVC, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3C2512CREVC__"}, -+ {"uc3l0256", PART_TYPE_AVR32_UC3L0256, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L0256__"}, -+ {"uc3l0128", PART_TYPE_AVR32_UC3L0128, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L0128__"}, -+ {"uc3l064", PART_TYPE_AVR32_UC3L064, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L064__"}, -+ {"uc3l032", PART_TYPE_AVR32_UC3L032, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L032__"}, -+ {"uc3l016", PART_TYPE_AVR32_UC3L016, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L016__"}, -+ {"uc3l064revb", PART_TYPE_AVR32_UC3L064REVB, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L064REVB__"}, -+ {"uc64l3u", PART_TYPE_AVR32_UC64L3U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC64L3U__"}, -+ {"uc128l3u", PART_TYPE_AVR32_UC128L3U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC128L3U__"}, -+ {"uc256l3u", PART_TYPE_AVR32_UC256L3U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC256L3U__"}, -+ {"uc64l4u", PART_TYPE_AVR32_UC64L4U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC64L4U__"}, -+ {"uc128l4u", PART_TYPE_AVR32_UC128L4U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC128L4U__"}, -+ {"uc256l4u", PART_TYPE_AVR32_UC256L4U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC256L4U__"}, -+ {"uc3c064c", PART_TYPE_AVR32_UC3C064C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C064C__"}, -+ {"uc3c0128c", PART_TYPE_AVR32_UC3C0128C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C0128C__"}, -+ {"uc3c0256c", PART_TYPE_AVR32_UC3C0256C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C0256C__"}, -+ {"uc3c0512c", PART_TYPE_AVR32_UC3C0512C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C0512C__"}, -+ {"uc3c164c", PART_TYPE_AVR32_UC3C164C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C164C__"}, -+ {"uc3c1128c", PART_TYPE_AVR32_UC3C1128C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C1128C__"}, -+ {"uc3c1256c", PART_TYPE_AVR32_UC3C1256C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C1256C__"}, -+ {"uc3c1512c", PART_TYPE_AVR32_UC3C1512C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C1512C__"}, -+ {"uc3c264c", PART_TYPE_AVR32_UC3C264C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C264C__"}, -+ {"uc3c2128c", PART_TYPE_AVR32_UC3C2128C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C2128C__"}, -+ {"uc3c2256c", PART_TYPE_AVR32_UC3C2256C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C2256C__"}, -+ {"uc3c2512c", PART_TYPE_AVR32_UC3C2512C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C2512C__"}, -+ {"mxt768e", PART_TYPE_AVR32_MXT768E, ARCH_TYPE_AVR32_UCR3, "__AVR32_MXT768E__"}, -+ {NULL, 0, 0, NULL} -+}; + -+/* List of all known AVR32 architectures */ -+static const struct arch_type_s avr32_arch_types[] = { -+ /* name, architecture type, microarchitecture type, feature flags, macro */ -+ {"ap", ARCH_TYPE_AVR32_AP, UARCH_TYPE_AVR32B, -+ (FLAG_AVR32_HAS_DSP -+ | FLAG_AVR32_HAS_SIMD -+ | FLAG_AVR32_HAS_UNALIGNED_WORD -+ | FLAG_AVR32_HAS_BRANCH_PRED | FLAG_AVR32_HAS_RETURN_STACK -+ | FLAG_AVR32_HAS_CACHES), -+ "__AVR32_AP__"}, -+ {"ucr1", ARCH_TYPE_AVR32_UCR1, UARCH_TYPE_AVR32A, -+ (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW), -+ "__AVR32_UC__=1"}, -+ {"ucr2", ARCH_TYPE_AVR32_UCR2, UARCH_TYPE_AVR32A, -+ (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW -+ | FLAG_AVR32_HAS_V2_INSNS), -+ "__AVR32_UC__=2"}, -+ {"ucr2nomul", ARCH_TYPE_AVR32_UCR2NOMUL, UARCH_TYPE_AVR32A, -+ (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW -+ | FLAG_AVR32_HAS_V2_INSNS | FLAG_AVR32_HAS_NO_MUL_INSNS), -+ "__AVR32_UC__=2"}, -+ {"ucr3", ARCH_TYPE_AVR32_UCR3, UARCH_TYPE_AVR32A, -+ (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW -+ | FLAG_AVR32_HAS_V2_INSNS), -+ "__AVR32_UC__=3"}, -+ {"ucr3fp", ARCH_TYPE_AVR32_UCR3FP, UARCH_TYPE_AVR32A, -+ (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW | FLAG_AVR32_HAS_FPU -+ | FLAG_AVR32_HAS_V2_INSNS), -+ "__AVR32_UC__=3"}, -+ {NULL, 0, 0, 0, NULL} -+}; ++#ifndef AVR32_PROTOS_H ++#define AVR32_PROTOS_H + -+/* Default arch name */ -+const char *avr32_arch_name = "none"; -+const char *avr32_part_name = "none"; ++extern const int swap_reg[]; + -+const struct part_type_s *avr32_part; -+const struct arch_type_s *avr32_arch; ++extern int avr32_valid_macmac_bypass (rtx, rtx); ++extern int avr32_valid_mulmac_bypass (rtx, rtx); + ++extern int avr32_decode_lcomm_symbol_offset (rtx, int *); ++extern void avr32_encode_lcomm_symbol_offset (tree, char *, int); + -+/* FIXME: needs to use GC. */ -+struct flashvault_decl_list -+{ -+ struct flashvault_decl_list *next; -+ unsigned int vector_num; -+ const char *name; -+}; ++extern const char *avr32_strip_name_encoding (const char *); + -+static struct flashvault_decl_list *flashvault_decl_list_head = NULL; ++extern rtx avr32_get_note_reg_equiv (rtx insn); + ++extern int avr32_use_return_insn (int iscond); + -+/* Set default target_flags. */ -+#undef TARGET_DEFAULT_TARGET_FLAGS -+#define TARGET_DEFAULT_TARGET_FLAGS \ -+ (MASK_HAS_ASM_ADDR_PSEUDOS | MASK_MD_REORG_OPTIMIZATION | MASK_COND_EXEC_BEFORE_RELOAD) ++extern void avr32_make_reglist16 (int reglist16_vect, char *reglist16_string); + -+void -+avr32_optimization_options (int level, int size) -+{ -+ if (AVR32_ALWAYS_PIC) -+ flag_pic = 1; ++extern void avr32_make_reglist8 (int reglist8_vect, char *reglist8_string); ++extern void avr32_make_fp_reglist_w (int reglist_mask, char *reglist_string); ++extern void avr32_make_fp_reglist_d (int reglist_mask, char *reglist_string); + -+ /* Enable section anchors if optimization is enabled. */ -+ if (level > 0 || size) -+ flag_section_anchors = 2; -+} ++extern void avr32_output_return_instruction (int single_ret_inst, ++ int iscond, rtx cond, ++ rtx r12_imm); ++extern void avr32_expand_prologue (void); ++extern void avr32_set_return_address (rtx source, rtx scratch); + ++extern int avr32_hard_regno_mode_ok (int regno, enum machine_mode mode); ++extern int avr32_extra_constraint_s (rtx value, const int strict); ++extern int avr32_eh_return_data_regno (const int n); ++extern int avr32_initial_elimination_offset (const int from, const int to); ++extern rtx avr32_function_arg (CUMULATIVE_ARGS * cum, enum machine_mode mode, ++ tree type, int named); ++extern void avr32_init_cumulative_args (CUMULATIVE_ARGS * cum, tree fntype, ++ rtx libname, tree fndecl); ++extern void avr32_function_arg_advance (CUMULATIVE_ARGS * cum, ++ enum machine_mode mode, ++ tree type, int named); ++#ifdef ARGS_SIZE_RTX ++/* expr.h defines ARGS_SIZE_RTX and `enum direction'. */ ++extern enum direction avr32_function_arg_padding (enum machine_mode mode, ++ tree type); ++#endif /* ARGS_SIZE_RTX */ ++extern rtx avr32_function_value (tree valtype, tree func, bool outgoing); ++extern rtx avr32_libcall_value (enum machine_mode mode); ++extern int avr32_sched_use_dfa_pipeline_interface (void); ++extern bool avr32_return_in_memory (tree type, tree fntype); ++extern void avr32_regs_to_save (char *operand); ++extern void avr32_target_asm_function_prologue (FILE * file, ++ HOST_WIDE_INT size); ++extern void avr32_target_asm_function_epilogue (FILE * file, ++ HOST_WIDE_INT size); ++extern void avr32_trampoline_template (FILE * file); ++extern void avr32_initialize_trampoline (rtx addr, rtx fnaddr, ++ rtx static_chain); ++extern int avr32_legitimate_address (enum machine_mode mode, rtx x, ++ int strict); ++extern int avr32_legitimate_constant_p (rtx x); + -+/* Override command line options */ -+void -+avr32_override_options (void) -+{ -+ const struct part_type_s *part; -+ const struct arch_type_s *arch, *part_arch; ++extern int avr32_legitimate_pic_operand_p (rtx x); + -+ /*Add backward compability*/ -+ if (strcmp ("uc", avr32_arch_name)== 0) -+ { -+ fprintf (stderr, "Warning: Deprecated arch `%s' specified. " -+ "Please use '-march=ucr1' instead. " -+ "Using arch 'ucr1'\n", -+ avr32_arch_name); -+ avr32_arch_name="ucr1"; -+ } ++extern rtx avr32_find_symbol (rtx x); ++extern void avr32_select_section (rtx exp, int reloc, int align); ++extern void avr32_encode_section_info (tree decl, rtx rtl, int first); ++extern void avr32_asm_file_end (FILE * stream); ++extern void avr32_asm_output_ascii (FILE * stream, char *ptr, int len); ++extern void avr32_asm_output_common (FILE * stream, const char *name, ++ int size, int rounded); ++extern void avr32_asm_output_label (FILE * stream, const char *name); ++extern void avr32_asm_declare_object_name (FILE * stream, char *name, ++ tree decl); ++extern void avr32_asm_globalize_label (FILE * stream, const char *name); ++extern void avr32_asm_weaken_label (FILE * stream, const char *name); ++extern void avr32_asm_output_external (FILE * stream, tree decl, ++ const char *name); ++extern void avr32_asm_output_external_libcall (FILE * stream, rtx symref); ++extern void avr32_asm_output_labelref (FILE * stream, const char *name); ++extern void avr32_notice_update_cc (rtx exp, rtx insn); ++extern void avr32_print_operand (FILE * stream, rtx x, int code); ++extern void avr32_print_operand_address (FILE * stream, rtx x); + -+ /* Check if arch type is set. */ -+ for (arch = avr32_arch_types; arch->name; arch++) -+ { -+ if (strcmp (arch->name, avr32_arch_name) == 0) -+ break; -+ } -+ avr32_arch = arch; ++extern int avr32_symbol (rtx x); + -+ if (!arch->name && strcmp("none", avr32_arch_name) != 0) -+ { -+ fprintf (stderr, "Unknown arch `%s' specified\n" -+ "Known arch names:\n" -+ "\tuc (deprecated)\n", -+ avr32_arch_name); -+ for (arch = avr32_arch_types; arch->name; arch++) -+ fprintf (stderr, "\t%s\n", arch->name); -+ avr32_arch = &avr32_arch_types[ARCH_TYPE_AVR32_AP]; -+ } ++extern void avr32_select_rtx_section (enum machine_mode mode, rtx x, ++ unsigned HOST_WIDE_INT align); + -+ /* Check if part type is set. */ -+ for (part = avr32_part_types; part->name; part++) -+ if (strcmp (part->name, avr32_part_name) == 0) -+ break; ++extern int avr32_load_multiple_operation (rtx op, enum machine_mode mode); ++extern int avr32_store_multiple_operation (rtx op, enum machine_mode mode); + -+ avr32_part = part; -+ if (!part->name) -+ { -+ fprintf (stderr, "Unknown part `%s' specified\nKnown part names:\n", -+ avr32_part_name); -+ for (part = avr32_part_types; part->name; part++) -+ { -+ if (strcmp("none", part->name) != 0) -+ fprintf (stderr, "\t%s\n", part->name); -+ } -+ /* Set default to NONE*/ -+ avr32_part = &avr32_part_types[PART_TYPE_AVR32_NONE]; -+ } ++extern int avr32_const_ok_for_constraint_p (HOST_WIDE_INT value, char c, ++ const char *str); + -+ /* NB! option -march= overrides option -mpart -+ * if both are used at the same time */ -+ if (!arch->name) -+ avr32_arch = &avr32_arch_types[avr32_part->arch_type]; ++extern bool avr32_cannot_force_const_mem (rtx x); + -+ /* When architecture implied by -mpart and one passed in -march are -+ * conflicting, issue an error message */ -+ part_arch = &avr32_arch_types[avr32_part->arch_type]; -+ if (strcmp("none",avr32_part_name) && strcmp("none", avr32_arch_name) && strcmp(avr32_arch_name,part_arch->name)) -+ error ("Conflicting architectures implied by -mpart and -march\n"); ++extern void avr32_init_builtins (void); + -+ /* If optimization level is two or greater, then align start of loops to a -+ word boundary since this will allow folding the first insn of the loop. -+ Do this only for targets supporting branch prediction. */ -+ if (optimize >= 2 && TARGET_BRANCH_PRED) -+ align_loops = 2; ++extern rtx avr32_expand_builtin (tree exp, rtx target, rtx subtarget, ++ enum machine_mode mode, int ignore); + ++extern bool avr32_must_pass_in_stack (enum machine_mode mode, tree type); + -+ /* Enable fast-float library if unsafe math optimizations -+ are used. */ -+ if (flag_unsafe_math_optimizations) -+ target_flags |= MASK_FAST_FLOAT; ++extern bool avr32_strict_argument_naming (CUMULATIVE_ARGS * ca); + -+ /* Check if we should set avr32_imm_in_const_pool -+ based on if caches are present or not. */ -+ if ( avr32_imm_in_const_pool == -1 ) -+ { -+ if ( TARGET_CACHES ) -+ avr32_imm_in_const_pool = 1; -+ else -+ avr32_imm_in_const_pool = 0; -+ } ++extern bool avr32_pass_by_reference (CUMULATIVE_ARGS * cum, ++ enum machine_mode mode, ++ tree type, bool named); + -+ if (TARGET_NO_PIC) -+ flag_pic = 0; -+ avr32_add_gc_roots (); -+} ++extern rtx avr32_gen_load_multiple (rtx * regs, int count, rtx from, ++ int write_back, int in_struct_p, ++ int scalar_p); ++extern rtx avr32_gen_store_multiple (rtx * regs, int count, rtx to, ++ int in_struct_p, int scalar_p); ++extern int avr32_gen_movmemsi (rtx * operands); + ++extern int avr32_rnd_operands (rtx add, rtx shift); ++extern int avr32_adjust_insn_length (rtx insn, int length); + -+/* -+If defined, a function that outputs the assembler code for entry to a -+function. The prologue is responsible for setting up the stack frame, -+initializing the frame pointer register, saving registers that must be -+saved, and allocating size additional bytes of storage for the -+local variables. size is an integer. file is a stdio -+stream to which the assembler code should be output. ++extern int symbol_mentioned_p (rtx x); ++extern int label_mentioned_p (rtx x); ++extern rtx legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg); ++extern int avr32_address_register_rtx_p (rtx x, int strict_p); ++extern int avr32_legitimate_index_p (enum machine_mode mode, rtx index, ++ int strict_p); + -+The label for the beginning of the function need not be output by this -+macro. That has already been done when the macro is run. ++extern int avr32_const_double_immediate (rtx value); ++extern void avr32_init_expanders (void); ++extern rtx avr32_return_addr (int count, rtx frame); ++extern bool avr32_got_mentioned_p (rtx addr); + -+To determine which registers to save, the macro can refer to the array -+regs_ever_live: element r is nonzero if hard register -+r is used anywhere within the function. This implies the function -+prologue should save register r, provided it is not one of the -+call-used registers. (TARGET_ASM_FUNCTION_EPILOGUE must likewise use -+regs_ever_live.) ++extern void avr32_final_prescan_insn (rtx insn, rtx * opvec, int noperands); + -+On machines that have ``register windows'', the function entry code does -+not save on the stack the registers that are in the windows, even if -+they are supposed to be preserved by function calls; instead it takes -+appropriate steps to ``push'' the register stack, if any non-call-used -+registers are used in the function. ++extern int avr32_expand_movcc (enum machine_mode mode, rtx operands[]); ++extern int avr32_expand_addcc (enum machine_mode mode, rtx operands[]); ++#ifdef RTX_CODE ++extern int avr32_expand_scc (RTX_CODE cond, rtx * operands); ++#endif + -+On machines where functions may or may not have frame-pointers, the -+function entry code must vary accordingly; it must set up the frame -+pointer if one is wanted, and not otherwise. To determine whether a -+frame pointer is in wanted, the macro can refer to the variable -+frame_pointer_needed. The variable's value will be 1 at run -+time in a function that needs a frame pointer. (see Elimination). ++extern int avr32_store_bypass (rtx insn_out, rtx insn_in); ++extern int avr32_mul_waw_bypass (rtx insn_out, rtx insn_in); ++extern int avr32_valid_load_double_bypass (rtx insn_out, rtx insn_in); ++extern int avr32_valid_load_quad_bypass (rtx insn_out, rtx insn_in); ++extern rtx avr32_output_cmp (rtx cond, enum machine_mode mode, ++ rtx op0, rtx op1); + -+The function entry code is responsible for allocating any stack space -+required for the function. This stack space consists of the regions -+listed below. In most cases, these regions are allocated in the -+order listed, with the last listed region closest to the top of the -+stack (the lowest address if STACK_GROWS_DOWNWARD is defined, and -+the highest address if it is not defined). You can use a different order -+for a machine if doing so is more convenient or required for -+compatibility reasons. Except in cases where required by standard -+or by a debugger, there is no reason why the stack layout used by GCC -+need agree with that used by other compilers for a machine. -+*/ -+ -+#undef TARGET_ASM_FUNCTION_PROLOGUE -+#define TARGET_ASM_FUNCTION_PROLOGUE avr32_target_asm_function_prologue -+ -+#undef TARGET_ASM_FILE_END -+#define TARGET_ASM_FILE_END avr32_file_end -+ -+#undef TARGET_DEFAULT_SHORT_ENUMS -+#define TARGET_DEFAULT_SHORT_ENUMS hook_bool_void_false -+ -+#undef TARGET_PROMOTE_FUNCTION_ARGS -+#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true -+ -+#undef TARGET_PROMOTE_FUNCTION_RETURN -+#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true -+ -+#undef TARGET_PROMOTE_PROTOTYPES -+#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true -+ -+#undef TARGET_MUST_PASS_IN_STACK -+#define TARGET_MUST_PASS_IN_STACK avr32_must_pass_in_stack -+ -+#undef TARGET_PASS_BY_REFERENCE -+#define TARGET_PASS_BY_REFERENCE avr32_pass_by_reference ++rtx get_next_insn_cond (rtx cur_insn); ++int set_next_insn_cond (rtx cur_insn, rtx cond); ++rtx next_insn_emits_cmp (rtx cur_insn); ++void avr32_override_options (void); ++void avr32_load_pic_register (void); ++#ifdef GCC_BASIC_BLOCK_H ++rtx avr32_ifcvt_modify_insn (ce_if_block_t *ce_info, rtx pattern, rtx insn, ++ int *num_true_changes); ++rtx avr32_ifcvt_modify_test (ce_if_block_t *ce_info, rtx test ); ++void avr32_ifcvt_modify_cancel ( ce_if_block_t *ce_info, int *num_true_changes); ++#endif ++void avr32_optimization_options (int level, int size); ++int avr32_const_ok_for_move (HOST_WIDE_INT c); + -+#undef TARGET_STRICT_ARGUMENT_NAMING -+#define TARGET_STRICT_ARGUMENT_NAMING avr32_strict_argument_naming ++void avr32_split_const_expr (enum machine_mode mode, ++ enum machine_mode new_mode, ++ rtx expr, ++ rtx *split_expr); ++void avr32_get_intval (enum machine_mode mode, ++ rtx const_expr, ++ HOST_WIDE_INT *val); + -+#undef TARGET_VECTOR_MODE_SUPPORTED_P -+#define TARGET_VECTOR_MODE_SUPPORTED_P avr32_vector_mode_supported ++int avr32_cond_imm_clobber_splittable (rtx insn, ++ rtx operands[]); + -+#undef TARGET_RETURN_IN_MEMORY -+#define TARGET_RETURN_IN_MEMORY avr32_return_in_memory ++bool avr32_flashvault_call(tree decl); ++extern void avr32_emit_swdivsf (rtx, rtx, rtx); + -+#undef TARGET_RETURN_IN_MSB -+#define TARGET_RETURN_IN_MSB avr32_return_in_msb ++#endif /* AVR32_PROTOS_H */ +diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32.c gcc-4.4.6/gcc/config/avr32/avr32.c +--- gcc-4.4.6.orig/gcc/config/avr32/avr32.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-4.4.6/gcc/config/avr32/avr32.c 2011-10-22 19:23:08.516581300 +0200 +@@ -0,0 +1,8087 @@ ++/* ++ Target hooks and helper functions for AVR32. ++ Copyright 2003,2004,2005,2006,2007,2008,2009,2010 Atmel Corporation. + -+#undef TARGET_ENCODE_SECTION_INFO -+#define TARGET_ENCODE_SECTION_INFO avr32_encode_section_info ++ This file is part of GCC. + -+#undef TARGET_ARG_PARTIAL_BYTES -+#define TARGET_ARG_PARTIAL_BYTES avr32_arg_partial_bytes ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 2 of the License, or ++ (at your option) any later version. + -+#undef TARGET_STRIP_NAME_ENCODING -+#define TARGET_STRIP_NAME_ENCODING avr32_strip_name_encoding ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. + -+#define streq(string1, string2) (strcmp (string1, string2) == 0) ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + -+#undef TARGET_NARROW_VOLATILE_BITFIELD -+#define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false ++#include "config.h" ++#include "system.h" ++#include "coretypes.h" ++#include "tm.h" ++#include "rtl.h" ++#include "tree.h" ++#include "obstack.h" ++#include "regs.h" ++#include "hard-reg-set.h" ++#include "real.h" ++#include "insn-config.h" ++#include "conditions.h" ++#include "output.h" ++#include "insn-attr.h" ++#include "flags.h" ++#include "reload.h" ++#include "function.h" ++#include "expr.h" ++#include "optabs.h" ++#include "toplev.h" ++#include "recog.h" ++#include "ggc.h" ++#include "except.h" ++#include "c-pragma.h" ++#include "integrate.h" ++#include "tm_p.h" ++#include "langhooks.h" ++#include "hooks.h" ++#include "df.h" + -+#undef TARGET_ATTRIBUTE_TABLE -+#define TARGET_ATTRIBUTE_TABLE avr32_attribute_table ++#include "target.h" ++#include "target-def.h" + -+#undef TARGET_COMP_TYPE_ATTRIBUTES -+#define TARGET_COMP_TYPE_ATTRIBUTES avr32_comp_type_attributes ++#include + + -+#undef TARGET_RTX_COSTS -+#define TARGET_RTX_COSTS avr32_rtx_costs + -+#undef TARGET_CANNOT_FORCE_CONST_MEM -+#define TARGET_CANNOT_FORCE_CONST_MEM avr32_cannot_force_const_mem ++/* Global variables. */ ++typedef struct minipool_node Mnode; ++typedef struct minipool_fixup Mfix; + -+#undef TARGET_ASM_INTEGER -+#define TARGET_ASM_INTEGER avr32_assemble_integer ++/* Obstack for minipool constant handling. */ ++static struct obstack minipool_obstack; ++static char *minipool_startobj; ++static rtx minipool_vector_label; + -+#undef TARGET_FUNCTION_VALUE -+#define TARGET_FUNCTION_VALUE avr32_function_value ++/* True if we are currently building a constant table. */ ++int making_const_table; + -+#undef TARGET_MIN_ANCHOR_OFFSET -+#define TARGET_MIN_ANCHOR_OFFSET (0) ++tree fndecl_attribute_args = NULL_TREE; + -+#undef TARGET_MAX_ANCHOR_OFFSET -+#define TARGET_MAX_ANCHOR_OFFSET ((1 << 15) - 1) -+#undef TARGET_SECONDARY_RELOAD -+#define TARGET_SECONDARY_RELOAD avr32_secondary_reload + ++/* Function prototypes. */ ++static unsigned long avr32_isr_value (tree); ++static unsigned long avr32_compute_func_type (void); ++static tree avr32_handle_isr_attribute (tree *, tree, tree, int, bool *); ++static tree avr32_handle_acall_attribute (tree *, tree, tree, int, bool *); ++static tree avr32_handle_fndecl_attribute (tree * node, tree name, tree args, ++ int flags, bool * no_add_attrs); ++static void avr32_reorg (void); ++bool avr32_return_in_msb (tree type); ++bool avr32_vector_mode_supported (enum machine_mode mode); ++static void avr32_init_libfuncs (void); ++static void avr32_file_end (void); ++static void flashvault_decl_list_add (unsigned int vector_num, const char *name); + -+/* -+ * Defining the option, -mlist-devices to list the devices supported by gcc. -+ * This option should be used while printing target-help to list all the -+ * supported devices. -+ */ -+#undef TARGET_HELP -+#define TARGET_HELP avr32_target_help + -+void avr32_target_help () -+{ -+ if (avr32_list_supported_parts) -+ { -+ const struct part_type_s *list; -+ fprintf (stdout, "List of parts supported by avr32-gcc:\n"); -+ for (list = avr32_part_types; list->name; list++) -+ { -+ if (strcmp("none", list->name) != 0) -+ fprintf (stdout, "%-20s%s\n", list->name, list->macro); -+ } -+ fprintf (stdout, "\n\n"); -+ } -+} + -+enum reg_class -+avr32_secondary_reload (bool in_p, rtx x, enum reg_class class, -+ enum machine_mode mode, secondary_reload_info *sri) ++static void ++avr32_add_gc_roots (void) +{ -+ -+ if ( avr32_rmw_memory_operand (x, mode) ) -+ { -+ if (!in_p) -+ sri->icode = CODE_FOR_reload_out_rmw_memory_operand; -+ else -+ sri->icode = CODE_FOR_reload_in_rmw_memory_operand; -+ } -+ return NO_REGS; -+ ++ gcc_obstack_init (&minipool_obstack); ++ minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); +} -+/* -+ * Switches to the appropriate section for output of constant pool -+ * entry x in mode. You can assume that x is some kind of constant in -+ * RTL. The argument mode is redundant except in the case of a -+ * const_int rtx. Select the section by calling readonly_data_ section -+ * or one of the alternatives for other sections. align is the -+ * constant alignment in bits. -+ * -+ * The default version of this function takes care of putting symbolic -+ * constants in flag_ pic mode in data_section and everything else in -+ * readonly_data_section. -+ */ -+//#undef TARGET_ASM_SELECT_RTX_SECTION -+//#define TARGET_ASM_SELECT_RTX_SECTION avr32_select_rtx_section -+ -+ -+/* -+ * If non-null, this hook performs a target-specific pass over the -+ * instruction stream. The compiler will run it at all optimization -+ * levels, just before the point at which it normally does -+ * delayed-branch scheduling. -+ * -+ * The exact purpose of the hook varies from target to target. Some -+ * use it to do transformations that are necessary for correctness, -+ * such as laying out in-function constant pools or avoiding hardware -+ * hazards. Others use it as an opportunity to do some -+ * machine-dependent optimizations. -+ * -+ * You need not implement the hook if it has nothing to do. The -+ * default definition is null. -+ */ -+#undef TARGET_MACHINE_DEPENDENT_REORG -+#define TARGET_MACHINE_DEPENDENT_REORG avr32_reorg -+ -+/* Target hook for assembling integer objects. -+ Need to handle integer vectors */ -+static bool -+avr32_assemble_integer (rtx x, unsigned int size, int aligned_p) -+{ -+ if (avr32_vector_mode_supported (GET_MODE (x))) -+ { -+ int i, units; + -+ if (GET_CODE (x) != CONST_VECTOR) -+ abort (); -+ -+ units = CONST_VECTOR_NUNITS (x); + -+ switch (GET_MODE (x)) -+ { -+ case V2HImode: -+ size = 2; -+ break; -+ case V4QImode: -+ size = 1; -+ break; -+ default: -+ abort (); -+ } -+ -+ for (i = 0; i < units; i++) -+ { -+ rtx elt; -+ -+ elt = CONST_VECTOR_ELT (x, i); -+ assemble_integer (elt, size, i == 0 ? 32 : size * BITS_PER_UNIT, 1); -+ } ++/* List of all known AVR32 parts */ ++static const struct part_type_s avr32_part_types[] = { ++ /* name, part_type, architecture type, macro */ ++ {"none", PART_TYPE_AVR32_NONE, ARCH_TYPE_AVR32_AP, "__AVR32__"}, ++ {"ap7000", PART_TYPE_AVR32_AP7000, ARCH_TYPE_AVR32_AP, "__AVR32_AP7000__"}, ++ {"ap7001", PART_TYPE_AVR32_AP7001, ARCH_TYPE_AVR32_AP, "__AVR32_AP7001__"}, ++ {"ap7002", PART_TYPE_AVR32_AP7002, ARCH_TYPE_AVR32_AP, "__AVR32_AP7002__"}, ++ {"ap7200", PART_TYPE_AVR32_AP7200, ARCH_TYPE_AVR32_AP, "__AVR32_AP7200__"}, ++ {"uc3a0128", PART_TYPE_AVR32_UC3A0128, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A0128__"}, ++ {"uc3a0256", PART_TYPE_AVR32_UC3A0256, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A0256__"}, ++ {"uc3a0512", PART_TYPE_AVR32_UC3A0512, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A0512__"}, ++ {"uc3a0512es", PART_TYPE_AVR32_UC3A0512ES, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3A0512ES__"}, ++ {"uc3a1128", PART_TYPE_AVR32_UC3A1128, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A1128__"}, ++ {"uc3a1256", PART_TYPE_AVR32_UC3A1256, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A1256__"}, ++ {"uc3a1512", PART_TYPE_AVR32_UC3A1512, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A1512__"}, ++ {"uc3a1512es", PART_TYPE_AVR32_UC3A1512ES, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3A1512ES__"}, ++ {"uc3a3revd", PART_TYPE_AVR32_UC3A3REVD, ARCH_TYPE_AVR32_UCR2NOMUL, "__AVR32_UC3A3256S__"}, ++ {"uc3a364", PART_TYPE_AVR32_UC3A364, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A364__"}, ++ {"uc3a364s", PART_TYPE_AVR32_UC3A364S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A364S__"}, ++ {"uc3a3128", PART_TYPE_AVR32_UC3A3128, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A3128__"}, ++ {"uc3a3128s", PART_TYPE_AVR32_UC3A3128S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A3128S__"}, ++ {"uc3a3256", PART_TYPE_AVR32_UC3A3256, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A3256__"}, ++ {"uc3a3256s", PART_TYPE_AVR32_UC3A3256S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A3256S__"}, ++ {"uc3a464", PART_TYPE_AVR32_UC3A464, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A464__"}, ++ {"uc3a464s", PART_TYPE_AVR32_UC3A464S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A464S__"}, ++ {"uc3a4128", PART_TYPE_AVR32_UC3A4128, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A4128__"}, ++ {"uc3a4128s", PART_TYPE_AVR32_UC3A4128S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A4128S__"}, ++ {"uc3a4256", PART_TYPE_AVR32_UC3A4256, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A4256__"}, ++ {"uc3a4256s", PART_TYPE_AVR32_UC3A4256S, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3A4256S__"}, ++ {"uc3b064", PART_TYPE_AVR32_UC3B064, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B064__"}, ++ {"uc3b0128", PART_TYPE_AVR32_UC3B0128, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B0128__"}, ++ {"uc3b0256", PART_TYPE_AVR32_UC3B0256, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B0256__"}, ++ {"uc3b0256es", PART_TYPE_AVR32_UC3B0256ES, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B0256ES__"}, ++ {"uc3b0512", PART_TYPE_AVR32_UC3B0512, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3B0512__"}, ++ {"uc3b0512revc", PART_TYPE_AVR32_UC3B0512REVC, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3B0512REVC__"}, ++ {"uc3b164", PART_TYPE_AVR32_UC3B164, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B164__"}, ++ {"uc3b1128", PART_TYPE_AVR32_UC3B1128, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B1128__"}, ++ {"uc3b1256", PART_TYPE_AVR32_UC3B1256, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B1256__"}, ++ {"uc3b1256es", PART_TYPE_AVR32_UC3B1256ES, ARCH_TYPE_AVR32_UCR1, "__AVR32_UC3B1256ES__"}, ++ {"uc3b1512", PART_TYPE_AVR32_UC3B1512, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3B1512__"}, ++ {"uc3b1512revc", PART_TYPE_AVR32_UC3B1512REVC, ARCH_TYPE_AVR32_UCR2, "__AVR32_UC3B1512REVC__"}, ++ {"uc64d3", PART_TYPE_AVR32_UC64D3, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC64D3__"}, ++ {"uc128d3", PART_TYPE_AVR32_UC128D3, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC128D3__"}, ++ {"uc64d4", PART_TYPE_AVR32_UC64D4, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC64D4__"}, ++ {"uc128d4", PART_TYPE_AVR32_UC128D4, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC128D4__"}, ++ {"uc3c0512crevc", PART_TYPE_AVR32_UC3C0512CREVC, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3C0512CREVC__"}, ++ {"uc3c1512crevc", PART_TYPE_AVR32_UC3C1512CREVC, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3C1512CREVC__"}, ++ {"uc3c2512crevc", PART_TYPE_AVR32_UC3C2512CREVC, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3C2512CREVC__"}, ++ {"uc3l0256", PART_TYPE_AVR32_UC3L0256, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L0256__"}, ++ {"uc3l0128", PART_TYPE_AVR32_UC3L0128, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L0128__"}, ++ {"uc3l064", PART_TYPE_AVR32_UC3L064, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L064__"}, ++ {"uc3l032", PART_TYPE_AVR32_UC3L032, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L032__"}, ++ {"uc3l016", PART_TYPE_AVR32_UC3L016, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L016__"}, ++ {"uc3l064revb", PART_TYPE_AVR32_UC3L064REVB, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC3L064REVB__"}, ++ {"uc64l3u", PART_TYPE_AVR32_UC64L3U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC64L3U__"}, ++ {"uc128l3u", PART_TYPE_AVR32_UC128L3U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC128L3U__"}, ++ {"uc256l3u", PART_TYPE_AVR32_UC256L3U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC256L3U__"}, ++ {"uc64l4u", PART_TYPE_AVR32_UC64L4U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC64L4U__"}, ++ {"uc128l4u", PART_TYPE_AVR32_UC128L4U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC128L4U__"}, ++ {"uc256l4u", PART_TYPE_AVR32_UC256L4U, ARCH_TYPE_AVR32_UCR3, "__AVR32_UC256L4U__"}, ++ {"uc3c064c", PART_TYPE_AVR32_UC3C064C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C064C__"}, ++ {"uc3c0128c", PART_TYPE_AVR32_UC3C0128C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C0128C__"}, ++ {"uc3c0256c", PART_TYPE_AVR32_UC3C0256C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C0256C__"}, ++ {"uc3c0512c", PART_TYPE_AVR32_UC3C0512C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C0512C__"}, ++ {"uc3c164c", PART_TYPE_AVR32_UC3C164C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C164C__"}, ++ {"uc3c1128c", PART_TYPE_AVR32_UC3C1128C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C1128C__"}, ++ {"uc3c1256c", PART_TYPE_AVR32_UC3C1256C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C1256C__"}, ++ {"uc3c1512c", PART_TYPE_AVR32_UC3C1512C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C1512C__"}, ++ {"uc3c264c", PART_TYPE_AVR32_UC3C264C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C264C__"}, ++ {"uc3c2128c", PART_TYPE_AVR32_UC3C2128C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C2128C__"}, ++ {"uc3c2256c", PART_TYPE_AVR32_UC3C2256C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C2256C__"}, ++ {"uc3c2512c", PART_TYPE_AVR32_UC3C2512C, ARCH_TYPE_AVR32_UCR3FP, "__AVR32_UC3C2512C__"}, ++ {"mxt768e", PART_TYPE_AVR32_MXT768E, ARCH_TYPE_AVR32_UCR3, "__AVR32_MXT768E__"}, ++ {NULL, 0, 0, NULL} ++}; + -+ return true; -+ } ++/* List of all known AVR32 architectures */ ++static const struct arch_type_s avr32_arch_types[] = { ++ /* name, architecture type, microarchitecture type, feature flags, macro */ ++ {"ap", ARCH_TYPE_AVR32_AP, UARCH_TYPE_AVR32B, ++ (FLAG_AVR32_HAS_DSP ++ | FLAG_AVR32_HAS_SIMD ++ | FLAG_AVR32_HAS_UNALIGNED_WORD ++ | FLAG_AVR32_HAS_BRANCH_PRED | FLAG_AVR32_HAS_RETURN_STACK ++ | FLAG_AVR32_HAS_CACHES), ++ "__AVR32_AP__"}, ++ {"ucr1", ARCH_TYPE_AVR32_UCR1, UARCH_TYPE_AVR32A, ++ (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW), ++ "__AVR32_UC__=1"}, ++ {"ucr2", ARCH_TYPE_AVR32_UCR2, UARCH_TYPE_AVR32A, ++ (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW ++ | FLAG_AVR32_HAS_V2_INSNS), ++ "__AVR32_UC__=2"}, ++ {"ucr2nomul", ARCH_TYPE_AVR32_UCR2NOMUL, UARCH_TYPE_AVR32A, ++ (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW ++ | FLAG_AVR32_HAS_V2_INSNS | FLAG_AVR32_HAS_NO_MUL_INSNS), ++ "__AVR32_UC__=2"}, ++ {"ucr3", ARCH_TYPE_AVR32_UCR3, UARCH_TYPE_AVR32A, ++ (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW ++ | FLAG_AVR32_HAS_V2_INSNS), ++ "__AVR32_UC__=3"}, ++ {"ucr3fp", ARCH_TYPE_AVR32_UCR3FP, UARCH_TYPE_AVR32A, ++ (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW | FLAG_AVR32_HAS_FPU ++ | FLAG_AVR32_HAS_V2_INSNS), ++ "__AVR32_UC__=3"}, ++ {NULL, 0, 0, 0, NULL} ++}; + -+ return default_assemble_integer (x, size, aligned_p); -+} ++/* Default arch name */ ++const char *avr32_arch_name = "none"; ++const char *avr32_part_name = "none"; + ++const struct part_type_s *avr32_part; ++const struct arch_type_s *avr32_arch; + -+/* -+ * This target hook describes the relative costs of RTL expressions. -+ * -+ * The cost may depend on the precise form of the expression, which is -+ * available for examination in x, and the rtx code of the expression -+ * in which it is contained, found in outer_code. code is the -+ * expression code--redundant, since it can be obtained with GET_CODE -+ * (x). -+ * -+ * In implementing this hook, you can use the construct COSTS_N_INSNS -+ * (n) to specify a cost equal to n fast instructions. -+ * -+ * On entry to the hook, *total contains a default estimate for the -+ * cost of the expression. The hook should modify this value as -+ * necessary. Traditionally, the default costs are COSTS_N_INSNS (5) -+ * for multiplications, COSTS_N_INSNS (7) for division and modulus -+ * operations, and COSTS_N_INSNS (1) for all other operations. -+ * -+ * When optimizing for code size, i.e. when optimize_size is non-zero, -+ * this target hook should be used to estimate the relative size cost -+ * of an expression, again relative to COSTS_N_INSNS. -+ * -+ * The hook returns true when all subexpressions of x have been -+ * processed, and false when rtx_cost should recurse. -+ */ + -+/* Worker routine for avr32_rtx_costs. */ -+static inline int -+avr32_rtx_costs_1 (rtx x, enum rtx_code code ATTRIBUTE_UNUSED, -+ enum rtx_code outer ATTRIBUTE_UNUSED) ++/* FIXME: needs to use GC. */ ++struct flashvault_decl_list +{ -+ enum machine_mode mode = GET_MODE (x); -+ -+ switch (GET_CODE (x)) -+ { -+ case MEM: -+ /* Using pre decrement / post increment memory operations on the -+ avr32_uc architecture means that two writebacks must be performed -+ and hence two cycles are needed. */ -+ if (!optimize_size -+ && GET_MODE_SIZE (mode) <= 2 * UNITS_PER_WORD -+ && TARGET_ARCH_UC -+ && (GET_CODE (XEXP (x, 0)) == PRE_DEC -+ || GET_CODE (XEXP (x, 0)) == POST_INC)) -+ return COSTS_N_INSNS (5); -+ -+ /* Memory costs quite a lot for the first word, but subsequent words -+ load at the equivalent of a single insn each. */ -+ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) -+ return COSTS_N_INSNS (3 + (GET_MODE_SIZE (mode) / UNITS_PER_WORD)); ++ struct flashvault_decl_list *next; ++ unsigned int vector_num; ++ const char *name; ++}; + -+ return COSTS_N_INSNS (4); -+ case SYMBOL_REF: -+ case CONST: -+ /* These are valid for the pseudo insns: lda.w and call which operates -+ on direct addresses. We assume that the cost of a lda.w is the same -+ as the cost of a ld.w insn. */ -+ return (outer == SET) ? COSTS_N_INSNS (4) : COSTS_N_INSNS (1); -+ case DIV: -+ case MOD: -+ case UDIV: -+ case UMOD: -+ return optimize_size ? COSTS_N_INSNS (1) : COSTS_N_INSNS (16); ++static struct flashvault_decl_list *flashvault_decl_list_head = NULL; + -+ case ROTATE: -+ case ROTATERT: -+ if (mode == TImode) -+ return COSTS_N_INSNS (100); + -+ if (mode == DImode) -+ return COSTS_N_INSNS (10); -+ return COSTS_N_INSNS (4); -+ case ASHIFT: -+ case LSHIFTRT: -+ case ASHIFTRT: -+ case NOT: -+ if (mode == TImode) -+ return COSTS_N_INSNS (10); ++/* Set default target_flags. */ ++#undef TARGET_DEFAULT_TARGET_FLAGS ++#define TARGET_DEFAULT_TARGET_FLAGS \ ++ (MASK_HAS_ASM_ADDR_PSEUDOS | MASK_MD_REORG_OPTIMIZATION | MASK_COND_EXEC_BEFORE_RELOAD) + -+ if (mode == DImode) -+ return COSTS_N_INSNS (4); -+ return COSTS_N_INSNS (1); -+ case PLUS: -+ case MINUS: -+ case NEG: -+ case COMPARE: -+ case ABS: -+ if (GET_MODE_CLASS (mode) == MODE_FLOAT) -+ return COSTS_N_INSNS (100); ++void ++avr32_optimization_options (int level, int size) ++{ ++ if (AVR32_ALWAYS_PIC) ++ flag_pic = 1; + -+ if (mode == TImode) -+ return COSTS_N_INSNS (50); ++ /* Enable section anchors if optimization is enabled. */ ++ if (level > 0 || size) ++ flag_section_anchors = 2; ++} + -+ if (mode == DImode) -+ return COSTS_N_INSNS (2); -+ return COSTS_N_INSNS (1); + -+ case MULT: -+ { -+ if (GET_MODE_CLASS (mode) == MODE_FLOAT) -+ return COSTS_N_INSNS (300); ++/* Override command line options */ ++void ++avr32_override_options (void) ++{ ++ const struct part_type_s *part; ++ const struct arch_type_s *arch, *part_arch; + -+ if (mode == TImode) -+ return COSTS_N_INSNS (16); ++ /*Add backward compability*/ ++ if (strcmp ("uc", avr32_arch_name)== 0) ++ { ++ fprintf (stderr, "Warning: Deprecated arch `%s' specified. " ++ "Please use '-march=ucr1' instead. " ++ "Using arch 'ucr1'\n", ++ avr32_arch_name); ++ avr32_arch_name="ucr1"; ++ } + -+ if (mode == DImode) -+ return COSTS_N_INSNS (4); ++ /* Check if arch type is set. */ ++ for (arch = avr32_arch_types; arch->name; arch++) ++ { ++ if (strcmp (arch->name, avr32_arch_name) == 0) ++ break; ++ } ++ avr32_arch = arch; + -+ if (mode == HImode) -+ return COSTS_N_INSNS (2); ++ if (!arch->name && strcmp("none", avr32_arch_name) != 0) ++ { ++ fprintf (stderr, "Unknown arch `%s' specified\n" ++ "Known arch names:\n" ++ "\tuc (deprecated)\n", ++ avr32_arch_name); ++ for (arch = avr32_arch_types; arch->name; arch++) ++ fprintf (stderr, "\t%s\n", arch->name); ++ avr32_arch = &avr32_arch_types[ARCH_TYPE_AVR32_AP]; ++ } + -+ return COSTS_N_INSNS (3); -+ } -+ case IF_THEN_ELSE: -+ if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) -+ return COSTS_N_INSNS (4); -+ return COSTS_N_INSNS (1); -+ case SIGN_EXTEND: -+ case ZERO_EXTEND: -+ /* Sign/Zero extensions of registers cost quite much since these -+ instrcutions only take one register operand which means that gcc -+ often must insert some move instrcutions */ -+ if (mode == QImode || mode == HImode) -+ return (COSTS_N_INSNS (GET_CODE (XEXP (x, 0)) == MEM ? 0 : 1)); -+ return COSTS_N_INSNS (4); -+ case UNSPEC: -+ /* divmod operations */ -+ if (XINT (x, 1) == UNSPEC_UDIVMODSI4_INTERNAL -+ || XINT (x, 1) == UNSPEC_DIVMODSI4_INTERNAL) -+ { -+ return optimize_size ? COSTS_N_INSNS (1) : COSTS_N_INSNS (16); -+ } -+ /* Fallthrough */ -+ default: -+ return COSTS_N_INSNS (1); ++ /* Check if part type is set. */ ++ for (part = avr32_part_types; part->name; part++) ++ if (strcmp (part->name, avr32_part_name) == 0) ++ break; ++ ++ avr32_part = part; ++ if (!part->name) ++ { ++ fprintf (stderr, "Unknown part `%s' specified\nKnown part names:\n", ++ avr32_part_name); ++ for (part = avr32_part_types; part->name; part++) ++ { ++ if (strcmp("none", part->name) != 0) ++ fprintf (stderr, "\t%s\n", part->name); ++ } ++ /* Set default to NONE*/ ++ avr32_part = &avr32_part_types[PART_TYPE_AVR32_NONE]; + } -+} + ++ /* NB! option -march= overrides option -mpart ++ * if both are used at the same time */ ++ if (!arch->name) ++ avr32_arch = &avr32_arch_types[avr32_part->arch_type]; ++ ++ /* When architecture implied by -mpart and one passed in -march are ++ * conflicting, issue an error message */ ++ part_arch = &avr32_arch_types[avr32_part->arch_type]; ++ if (strcmp("none",avr32_part_name) && strcmp("none", avr32_arch_name) && strcmp(avr32_arch_name,part_arch->name)) ++ error ("Conflicting architectures implied by -mpart and -march\n"); + -+static bool -+avr32_rtx_costs (rtx x, int code, int outer_code, int *total) -+{ -+ *total = avr32_rtx_costs_1 (x, code, outer_code); -+ return true; -+} ++ /* If optimization level is two or greater, then align start of loops to a ++ word boundary since this will allow folding the first insn of the loop. ++ Do this only for targets supporting branch prediction. */ ++ if (optimize >= 2 && TARGET_BRANCH_PRED) ++ align_loops = 2; + + -+bool -+avr32_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) -+{ -+ /* Do not want symbols in the constant pool when compiling pic or if using -+ address pseudo instructions. */ -+ return ((flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS) -+ && avr32_find_symbol (x) != NULL_RTX); ++ /* Enable fast-float library if unsafe math optimizations ++ are used. */ ++ if (flag_unsafe_math_optimizations) ++ target_flags |= MASK_FAST_FLOAT; ++ ++ /* Check if we should set avr32_imm_in_const_pool ++ based on if caches are present or not. */ ++ if ( avr32_imm_in_const_pool == -1 ) ++ { ++ if ( TARGET_CACHES ) ++ avr32_imm_in_const_pool = 1; ++ else ++ avr32_imm_in_const_pool = 0; ++ } ++ ++ if (TARGET_NO_PIC) ++ flag_pic = 0; ++ avr32_add_gc_roots (); +} + + -+/* Table of machine attributes. */ -+const struct attribute_spec avr32_attribute_table[] = { -+ /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ -+ /* Interrupt Service Routines have special prologue and epilogue -+ requirements. */ -+ {"isr", 0, 1, false, false, false, avr32_handle_isr_attribute}, -+ {"interrupt", 0, 1, false, false, false, avr32_handle_isr_attribute}, -+ {"acall", 0, 1, false, true, true, avr32_handle_acall_attribute}, -+ {"naked", 0, 0, true, false, false, avr32_handle_fndecl_attribute}, -+ {"rmw_addressable", 0, 0, true, false, false, NULL}, -+ {"flashvault", 0, 1, true, false, false, avr32_handle_fndecl_attribute}, -+ {"flashvault_impl", 0, 1, true, false, false, avr32_handle_fndecl_attribute}, -+ {NULL, 0, 0, false, false, false, NULL} -+}; ++/* ++If defined, a function that outputs the assembler code for entry to a ++function. The prologue is responsible for setting up the stack frame, ++initializing the frame pointer register, saving registers that must be ++saved, and allocating size additional bytes of storage for the ++local variables. size is an integer. file is a stdio ++stream to which the assembler code should be output. + ++The label for the beginning of the function need not be output by this ++macro. That has already been done when the macro is run. + -+typedef struct -+{ -+ const char *const arg; -+ const unsigned long return_value; -+} -+isr_attribute_arg; ++To determine which registers to save, the macro can refer to the array ++regs_ever_live: element r is nonzero if hard register ++r is used anywhere within the function. This implies the function ++prologue should save register r, provided it is not one of the ++call-used registers. (TARGET_ASM_FUNCTION_EPILOGUE must likewise use ++regs_ever_live.) + ++On machines that have ``register windows'', the function entry code does ++not save on the stack the registers that are in the windows, even if ++they are supposed to be preserved by function calls; instead it takes ++appropriate steps to ``push'' the register stack, if any non-call-used ++registers are used in the function. + -+static const isr_attribute_arg isr_attribute_args[] = { -+ {"FULL", AVR32_FT_ISR_FULL}, -+ {"full", AVR32_FT_ISR_FULL}, -+ {"HALF", AVR32_FT_ISR_HALF}, -+ {"half", AVR32_FT_ISR_HALF}, -+ {"NONE", AVR32_FT_ISR_NONE}, -+ {"none", AVR32_FT_ISR_NONE}, -+ {"UNDEF", AVR32_FT_ISR_NONE}, -+ {"undef", AVR32_FT_ISR_NONE}, -+ {"SWI", AVR32_FT_ISR_NONE}, -+ {"swi", AVR32_FT_ISR_NONE}, -+ {NULL, AVR32_FT_ISR_NONE} -+}; ++On machines where functions may or may not have frame-pointers, the ++function entry code must vary accordingly; it must set up the frame ++pointer if one is wanted, and not otherwise. To determine whether a ++frame pointer is in wanted, the macro can refer to the variable ++frame_pointer_needed. The variable's value will be 1 at run ++time in a function that needs a frame pointer. (see Elimination). + ++The function entry code is responsible for allocating any stack space ++required for the function. This stack space consists of the regions ++listed below. In most cases, these regions are allocated in the ++order listed, with the last listed region closest to the top of the ++stack (the lowest address if STACK_GROWS_DOWNWARD is defined, and ++the highest address if it is not defined). You can use a different order ++for a machine if doing so is more convenient or required for ++compatibility reasons. Except in cases where required by standard ++or by a debugger, there is no reason why the stack layout used by GCC ++need agree with that used by other compilers for a machine. ++*/ + -+/* Returns the (interrupt) function type of the current -+ function, or AVR32_FT_UNKNOWN if the type cannot be determined. */ -+static unsigned long -+avr32_isr_value (tree argument) -+{ -+ const isr_attribute_arg *ptr; -+ const char *arg; ++#undef TARGET_ASM_FUNCTION_PROLOGUE ++#define TARGET_ASM_FUNCTION_PROLOGUE avr32_target_asm_function_prologue + -+ /* No argument - default to ISR_NONE. */ -+ if (argument == NULL_TREE) -+ return AVR32_FT_ISR_NONE; ++#undef TARGET_ASM_FILE_END ++#define TARGET_ASM_FILE_END avr32_file_end + -+ /* Get the value of the argument. */ -+ if (TREE_VALUE (argument) == NULL_TREE -+ || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) -+ return AVR32_FT_UNKNOWN; ++#undef TARGET_DEFAULT_SHORT_ENUMS ++#define TARGET_DEFAULT_SHORT_ENUMS hook_bool_void_false + -+ arg = TREE_STRING_POINTER (TREE_VALUE (argument)); ++#undef TARGET_PROMOTE_FUNCTION_ARGS ++#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true + -+ /* Check it against the list of known arguments. */ -+ for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++) -+ if (streq (arg, ptr->arg)) -+ return ptr->return_value; ++#undef TARGET_PROMOTE_FUNCTION_RETURN ++#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true + -+ /* An unrecognized interrupt type. */ -+ return AVR32_FT_UNKNOWN; -+} ++#undef TARGET_PROMOTE_PROTOTYPES ++#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true + ++#undef TARGET_MUST_PASS_IN_STACK ++#define TARGET_MUST_PASS_IN_STACK avr32_must_pass_in_stack + -+/* -+These hooks specify assembly directives for creating certain kinds -+of integer object. The TARGET_ASM_BYTE_OP directive creates a -+byte-sized object, the TARGET_ASM_ALIGNED_HI_OP one creates an -+aligned two-byte object, and so on. Any of the hooks may be -+NULL, indicating that no suitable directive is available. ++#undef TARGET_PASS_BY_REFERENCE ++#define TARGET_PASS_BY_REFERENCE avr32_pass_by_reference + -+The compiler will print these strings at the start of a new line, -+followed immediately by the object's initial value. In most cases, -+the string should contain a tab, a pseudo-op, and then another tab. -+*/ -+#undef TARGET_ASM_BYTE_OP -+#define TARGET_ASM_BYTE_OP "\t.byte\t" -+#undef TARGET_ASM_ALIGNED_HI_OP -+#define TARGET_ASM_ALIGNED_HI_OP "\t.align 1\n\t.short\t" -+#undef TARGET_ASM_ALIGNED_SI_OP -+#define TARGET_ASM_ALIGNED_SI_OP "\t.align 2\n\t.int\t" -+#undef TARGET_ASM_ALIGNED_DI_OP -+#define TARGET_ASM_ALIGNED_DI_OP NULL -+#undef TARGET_ASM_ALIGNED_TI_OP -+#define TARGET_ASM_ALIGNED_TI_OP NULL -+#undef TARGET_ASM_UNALIGNED_HI_OP -+#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" -+#undef TARGET_ASM_UNALIGNED_SI_OP -+#define TARGET_ASM_UNALIGNED_SI_OP "\t.int\t" -+#undef TARGET_ASM_UNALIGNED_DI_OP -+#define TARGET_ASM_UNALIGNED_DI_OP NULL -+#undef TARGET_ASM_UNALIGNED_TI_OP -+#define TARGET_ASM_UNALIGNED_TI_OP NULL ++#undef TARGET_STRICT_ARGUMENT_NAMING ++#define TARGET_STRICT_ARGUMENT_NAMING avr32_strict_argument_naming + -+#undef TARGET_ASM_OUTPUT_MI_THUNK -+#define TARGET_ASM_OUTPUT_MI_THUNK avr32_output_mi_thunk ++#undef TARGET_VECTOR_MODE_SUPPORTED_P ++#define TARGET_VECTOR_MODE_SUPPORTED_P avr32_vector_mode_supported + -+#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK -+#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true ++#undef TARGET_RETURN_IN_MEMORY ++#define TARGET_RETURN_IN_MEMORY avr32_return_in_memory + ++#undef TARGET_RETURN_IN_MSB ++#define TARGET_RETURN_IN_MSB avr32_return_in_msb + -+static void -+avr32_output_mi_thunk (FILE * file, -+ tree thunk ATTRIBUTE_UNUSED, -+ HOST_WIDE_INT delta, -+ HOST_WIDE_INT vcall_offset, tree function) -+ { -+ int mi_delta = delta; -+ int this_regno = -+ (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) ? -+ INTERNAL_REGNUM (11) : INTERNAL_REGNUM (12)); ++#undef TARGET_ENCODE_SECTION_INFO ++#define TARGET_ENCODE_SECTION_INFO avr32_encode_section_info + ++#undef TARGET_ARG_PARTIAL_BYTES ++#define TARGET_ARG_PARTIAL_BYTES avr32_arg_partial_bytes + -+ if (!avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21") -+ || vcall_offset) -+ { -+ fputs ("\tpushm\tlr\n", file); -+ } ++#undef TARGET_STRIP_NAME_ENCODING ++#define TARGET_STRIP_NAME_ENCODING avr32_strip_name_encoding + ++#define streq(string1, string2) (strcmp (string1, string2) == 0) + -+ if (mi_delta != 0) -+ { -+ if (avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21")) -+ { -+ fprintf (file, "\tsub\t%s, %d\n", reg_names[this_regno], -mi_delta); -+ } -+ else -+ { -+ /* Immediate is larger than k21 we must make us a temp register by -+ pushing a register to the stack. */ -+ fprintf (file, "\tmov\tlr, lo(%d)\n", mi_delta); -+ fprintf (file, "\torh\tlr, hi(%d)\n", mi_delta); -+ fprintf (file, "\tadd\t%s, lr\n", reg_names[this_regno]); -+ } -+ } ++#undef TARGET_NARROW_VOLATILE_BITFIELD ++#define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false + ++#undef TARGET_ATTRIBUTE_TABLE ++#define TARGET_ATTRIBUTE_TABLE avr32_attribute_table + -+ if (vcall_offset != 0) -+ { -+ fprintf (file, "\tld.w\tlr, %s[0]\n", reg_names[this_regno]); -+ fprintf (file, "\tld.w\tlr, lr[%i]\n", (int) vcall_offset); -+ fprintf (file, "\tadd\t%s, lr\n", reg_names[this_regno]); -+ } ++#undef TARGET_COMP_TYPE_ATTRIBUTES ++#define TARGET_COMP_TYPE_ATTRIBUTES avr32_comp_type_attributes + + -+ if (!avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21") -+ || vcall_offset) -+ { -+ fputs ("\tpopm\tlr\n", file); -+ } ++#undef TARGET_RTX_COSTS ++#define TARGET_RTX_COSTS avr32_rtx_costs + -+ /* Jump to the function. We assume that we can use an rjmp since the -+ function to jump to is local and probably not too far away from -+ the thunk. If this assumption proves to be wrong we could implement -+ this jump by calculating the offset between the jump source and destination -+ and put this in the constant pool and then perform an add to pc. -+ This would also be legitimate PIC code. But for now we hope that an rjmp -+ will be sufficient... -+ */ -+ fputs ("\trjmp\t", file); -+ assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); -+ fputc ('\n', file); -+ } ++#undef TARGET_CANNOT_FORCE_CONST_MEM ++#define TARGET_CANNOT_FORCE_CONST_MEM avr32_cannot_force_const_mem + ++#undef TARGET_ASM_INTEGER ++#define TARGET_ASM_INTEGER avr32_assemble_integer + -+/* Implements target hook vector_mode_supported. */ -+bool -+avr32_vector_mode_supported (enum machine_mode mode) -+{ -+ if ((mode == V2HImode) || (mode == V4QImode)) -+ return true; ++#undef TARGET_FUNCTION_VALUE ++#define TARGET_FUNCTION_VALUE avr32_function_value + -+ return false; -+} ++#undef TARGET_MIN_ANCHOR_OFFSET ++#define TARGET_MIN_ANCHOR_OFFSET (0) + ++#undef TARGET_MAX_ANCHOR_OFFSET ++#define TARGET_MAX_ANCHOR_OFFSET ((1 << 15) - 1) ++#undef TARGET_SECONDARY_RELOAD ++#define TARGET_SECONDARY_RELOAD avr32_secondary_reload + -+#undef TARGET_INIT_LIBFUNCS -+#define TARGET_INIT_LIBFUNCS avr32_init_libfuncs + -+#undef TARGET_INIT_BUILTINS -+#define TARGET_INIT_BUILTINS avr32_init_builtins ++/* ++ * Defining the option, -mlist-devices to list the devices supported by gcc. ++ * This option should be used while printing target-help to list all the ++ * supported devices. ++ */ ++#undef TARGET_HELP ++#define TARGET_HELP avr32_target_help + -+#undef TARGET_EXPAND_BUILTIN -+#define TARGET_EXPAND_BUILTIN avr32_expand_builtin ++void avr32_target_help () ++{ ++ if (avr32_list_supported_parts) ++ { ++ const struct part_type_s *list; ++ fprintf (stdout, "List of parts supported by avr32-gcc:\n"); ++ for (list = avr32_part_types; list->name; list++) ++ { ++ if (strcmp("none", list->name) != 0) ++ fprintf (stdout, "%-20s%s\n", list->name, list->macro); ++ } ++ fprintf (stdout, "\n\n"); ++ } ++} + -+tree int_ftype_int, int_ftype_void, short_ftype_short, void_ftype_int_int, -+ void_ftype_ptr_int; -+tree void_ftype_int, void_ftype_ulong, void_ftype_void, int_ftype_ptr_int; -+tree short_ftype_short, int_ftype_int_short, int_ftype_short_short, -+ short_ftype_short_short; -+tree int_ftype_int_int, longlong_ftype_int_short, longlong_ftype_short_short; -+tree void_ftype_int_int_int_int_int, void_ftype_int_int_int; -+tree longlong_ftype_int_int, void_ftype_int_int_longlong; -+tree int_ftype_int_int_int, longlong_ftype_longlong_int_short; -+tree longlong_ftype_longlong_short_short, int_ftype_int_short_short; ++enum reg_class ++avr32_secondary_reload (bool in_p, rtx x, enum reg_class class, ++ enum machine_mode mode, secondary_reload_info *sri) ++{ + -+#define def_builtin(NAME, TYPE, CODE) \ -+ add_builtin_function ((NAME), (TYPE), (CODE), \ -+ BUILT_IN_MD, NULL, NULL_TREE) ++ if ( avr32_rmw_memory_operand (x, mode) ) ++ { ++ if (!in_p) ++ sri->icode = CODE_FOR_reload_out_rmw_memory_operand; ++ else ++ sri->icode = CODE_FOR_reload_in_rmw_memory_operand; ++ } ++ return NO_REGS; + -+#define def_mbuiltin(MASK, NAME, TYPE, CODE) \ -+ do \ -+ { \ -+ if ((MASK)) \ -+ add_builtin_function ((NAME), (TYPE), (CODE), \ -+ BUILT_IN_MD, NULL, NULL_TREE); \ -+ } \ -+ while (0) ++} ++/* ++ * Switches to the appropriate section for output of constant pool ++ * entry x in mode. You can assume that x is some kind of constant in ++ * RTL. The argument mode is redundant except in the case of a ++ * const_int rtx. Select the section by calling readonly_data_ section ++ * or one of the alternatives for other sections. align is the ++ * constant alignment in bits. ++ * ++ * The default version of this function takes care of putting symbolic ++ * constants in flag_ pic mode in data_section and everything else in ++ * readonly_data_section. ++ */ ++//#undef TARGET_ASM_SELECT_RTX_SECTION ++//#define TARGET_ASM_SELECT_RTX_SECTION avr32_select_rtx_section + -+struct builtin_description ++ ++/* ++ * If non-null, this hook performs a target-specific pass over the ++ * instruction stream. The compiler will run it at all optimization ++ * levels, just before the point at which it normally does ++ * delayed-branch scheduling. ++ * ++ * The exact purpose of the hook varies from target to target. Some ++ * use it to do transformations that are necessary for correctness, ++ * such as laying out in-function constant pools or avoiding hardware ++ * hazards. Others use it as an opportunity to do some ++ * machine-dependent optimizations. ++ * ++ * You need not implement the hook if it has nothing to do. The ++ * default definition is null. ++ */ ++#undef TARGET_MACHINE_DEPENDENT_REORG ++#define TARGET_MACHINE_DEPENDENT_REORG avr32_reorg ++ ++/* Target hook for assembling integer objects. ++ Need to handle integer vectors */ ++static bool ++avr32_assemble_integer (rtx x, unsigned int size, int aligned_p) +{ -+ const unsigned int mask; -+ const enum insn_code icode; -+ const char *const name; -+ const int code; -+ const enum rtx_code comparison; -+ const unsigned int flag; -+ const tree *ftype; -+}; ++ if (avr32_vector_mode_supported (GET_MODE (x))) ++ { ++ int i, units; + -+static const struct builtin_description bdesc_2arg[] = { ++ if (GET_CODE (x) != CONST_VECTOR) ++ abort (); + -+#define DSP_BUILTIN(code, builtin, ftype) \ -+ { 1, CODE_FOR_##code, "__builtin_" #code , \ -+ AVR32_BUILTIN_##builtin, 0, 0, ftype } ++ units = CONST_VECTOR_NUNITS (x); + -+ DSP_BUILTIN (mulsathh_h, MULSATHH_H, &short_ftype_short_short), -+ DSP_BUILTIN (mulsathh_w, MULSATHH_W, &int_ftype_short_short), -+ DSP_BUILTIN (mulsatrndhh_h, MULSATRNDHH_H, &short_ftype_short_short), -+ DSP_BUILTIN (mulsatrndwh_w, MULSATRNDWH_W, &int_ftype_int_short), -+ DSP_BUILTIN (mulsatwh_w, MULSATWH_W, &int_ftype_int_short), -+ DSP_BUILTIN (satadd_h, SATADD_H, &short_ftype_short_short), -+ DSP_BUILTIN (satsub_h, SATSUB_H, &short_ftype_short_short), -+ DSP_BUILTIN (satadd_w, SATADD_W, &int_ftype_int_int), -+ DSP_BUILTIN (satsub_w, SATSUB_W, &int_ftype_int_int), -+ DSP_BUILTIN (mulwh_d, MULWH_D, &longlong_ftype_int_short), -+ DSP_BUILTIN (mulnwh_d, MULNWH_D, &longlong_ftype_int_short) -+}; ++ switch (GET_MODE (x)) ++ { ++ case V2HImode: ++ size = 2; ++ break; ++ case V4QImode: ++ size = 1; ++ break; ++ default: ++ abort (); ++ } + ++ for (i = 0; i < units; i++) ++ { ++ rtx elt; + -+void -+avr32_init_builtins (void) -+{ -+ unsigned int i; -+ const struct builtin_description *d; -+ tree endlink = void_list_node; -+ tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink); -+ tree longlong_endlink = -+ tree_cons (NULL_TREE, long_long_integer_type_node, endlink); -+ tree short_endlink = -+ tree_cons (NULL_TREE, short_integer_type_node, endlink); -+ tree void_endlink = tree_cons (NULL_TREE, void_type_node, endlink); ++ elt = CONST_VECTOR_ELT (x, i); ++ assemble_integer (elt, size, i == 0 ? 32 : size * BITS_PER_UNIT, 1); ++ } + -+ /* int func (int) */ -+ int_ftype_int = build_function_type (integer_type_node, int_endlink); ++ return true; ++ } + -+ /* short func (short) */ -+ short_ftype_short -+ = build_function_type (short_integer_type_node, short_endlink); ++ return default_assemble_integer (x, size, aligned_p); ++} + -+ /* short func (short, short) */ -+ short_ftype_short_short -+ = build_function_type (short_integer_type_node, -+ tree_cons (NULL_TREE, short_integer_type_node, -+ short_endlink)); + -+ /* long long func (long long, short, short) */ -+ longlong_ftype_longlong_short_short -+ = build_function_type (long_long_integer_type_node, -+ tree_cons (NULL_TREE, long_long_integer_type_node, -+ tree_cons (NULL_TREE, -+ short_integer_type_node, -+ short_endlink))); ++/* ++ * This target hook describes the relative costs of RTL expressions. ++ * ++ * The cost may depend on the precise form of the expression, which is ++ * available for examination in x, and the rtx code of the expression ++ * in which it is contained, found in outer_code. code is the ++ * expression code--redundant, since it can be obtained with GET_CODE ++ * (x). ++ * ++ * In implementing this hook, you can use the construct COSTS_N_INSNS ++ * (n) to specify a cost equal to n fast instructions. ++ * ++ * On entry to the hook, *total contains a default estimate for the ++ * cost of the expression. The hook should modify this value as ++ * necessary. Traditionally, the default costs are COSTS_N_INSNS (5) ++ * for multiplications, COSTS_N_INSNS (7) for division and modulus ++ * operations, and COSTS_N_INSNS (1) for all other operations. ++ * ++ * When optimizing for code size, i.e. when optimize_size is non-zero, ++ * this target hook should be used to estimate the relative size cost ++ * of an expression, again relative to COSTS_N_INSNS. ++ * ++ * The hook returns true when all subexpressions of x have been ++ * processed, and false when rtx_cost should recurse. ++ */ + -+ /* long long func (short, short) */ -+ longlong_ftype_short_short -+ = build_function_type (long_long_integer_type_node, -+ tree_cons (NULL_TREE, short_integer_type_node, -+ short_endlink)); ++/* Worker routine for avr32_rtx_costs. */ ++static inline int ++avr32_rtx_costs_1 (rtx x, enum rtx_code code ATTRIBUTE_UNUSED, ++ enum rtx_code outer ATTRIBUTE_UNUSED) ++{ ++ enum machine_mode mode = GET_MODE (x); + -+ /* int func (int, int) */ -+ int_ftype_int_int -+ = build_function_type (integer_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ int_endlink)); ++ switch (GET_CODE (x)) ++ { ++ case MEM: ++ /* Using pre decrement / post increment memory operations on the ++ avr32_uc architecture means that two writebacks must be performed ++ and hence two cycles are needed. */ ++ if (!optimize_size ++ && GET_MODE_SIZE (mode) <= 2 * UNITS_PER_WORD ++ && TARGET_ARCH_UC ++ && (GET_CODE (XEXP (x, 0)) == PRE_DEC ++ || GET_CODE (XEXP (x, 0)) == POST_INC)) ++ return COSTS_N_INSNS (5); + -+ /* long long func (int, int) */ -+ longlong_ftype_int_int -+ = build_function_type (long_long_integer_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ int_endlink)); ++ /* Memory costs quite a lot for the first word, but subsequent words ++ load at the equivalent of a single insn each. */ ++ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) ++ return COSTS_N_INSNS (3 + (GET_MODE_SIZE (mode) / UNITS_PER_WORD)); + -+ /* long long int func (long long, int, short) */ -+ longlong_ftype_longlong_int_short -+ = build_function_type (long_long_integer_type_node, -+ tree_cons (NULL_TREE, long_long_integer_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ short_endlink))); ++ return COSTS_N_INSNS (4); ++ case SYMBOL_REF: ++ case CONST: ++ /* These are valid for the pseudo insns: lda.w and call which operates ++ on direct addresses. We assume that the cost of a lda.w is the same ++ as the cost of a ld.w insn. */ ++ return (outer == SET) ? COSTS_N_INSNS (4) : COSTS_N_INSNS (1); ++ case DIV: ++ case MOD: ++ case UDIV: ++ case UMOD: ++ return optimize_size ? COSTS_N_INSNS (1) : COSTS_N_INSNS (16); + -+ /* long long int func (int, short) */ -+ longlong_ftype_int_short -+ = build_function_type (long_long_integer_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ short_endlink)); ++ case ROTATE: ++ case ROTATERT: ++ if (mode == TImode) ++ return COSTS_N_INSNS (100); + -+ /* int func (int, short, short) */ -+ int_ftype_int_short_short -+ = build_function_type (integer_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ tree_cons (NULL_TREE, -+ short_integer_type_node, -+ short_endlink))); ++ if (mode == DImode) ++ return COSTS_N_INSNS (10); ++ return COSTS_N_INSNS (4); ++ case ASHIFT: ++ case LSHIFTRT: ++ case ASHIFTRT: ++ case NOT: ++ if (mode == TImode) ++ return COSTS_N_INSNS (10); + -+ /* int func (short, short) */ -+ int_ftype_short_short -+ = build_function_type (integer_type_node, -+ tree_cons (NULL_TREE, short_integer_type_node, -+ short_endlink)); ++ if (mode == DImode) ++ return COSTS_N_INSNS (4); ++ return COSTS_N_INSNS (1); ++ case PLUS: ++ case MINUS: ++ case NEG: ++ case COMPARE: ++ case ABS: ++ if (GET_MODE_CLASS (mode) == MODE_FLOAT) ++ return COSTS_N_INSNS (100); + -+ /* int func (int, short) */ -+ int_ftype_int_short -+ = build_function_type (integer_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ short_endlink)); ++ if (mode == TImode) ++ return COSTS_N_INSNS (50); + -+ /* void func (int, int) */ -+ void_ftype_int_int -+ = build_function_type (void_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ int_endlink)); ++ if (mode == DImode) ++ return COSTS_N_INSNS (2); ++ return COSTS_N_INSNS (1); + -+ /* void func (int, int, int) */ -+ void_ftype_int_int_int -+ = build_function_type (void_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ int_endlink))); ++ case MULT: ++ { ++ if (GET_MODE_CLASS (mode) == MODE_FLOAT) ++ return COSTS_N_INSNS (300); + -+ /* void func (int, int, long long) */ -+ void_ftype_int_int_longlong -+ = build_function_type (void_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ longlong_endlink))); ++ if (mode == TImode) ++ return COSTS_N_INSNS (16); + -+ /* void func (int, int, int, int, int) */ -+ void_ftype_int_int_int_int_int -+ = build_function_type (void_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ tree_cons (NULL_TREE, -+ integer_type_node, -+ tree_cons -+ (NULL_TREE, -+ integer_type_node, -+ int_endlink))))); ++ if (mode == DImode) ++ return COSTS_N_INSNS (4); + -+ /* void func (void *, int) */ -+ void_ftype_ptr_int -+ = build_function_type (void_type_node, -+ tree_cons (NULL_TREE, ptr_type_node, int_endlink)); ++ if (mode == HImode) ++ return COSTS_N_INSNS (2); + -+ /* void func (int) */ -+ void_ftype_int = build_function_type (void_type_node, int_endlink); ++ return COSTS_N_INSNS (3); ++ } ++ case IF_THEN_ELSE: ++ if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) ++ return COSTS_N_INSNS (4); ++ return COSTS_N_INSNS (1); ++ case SIGN_EXTEND: ++ case ZERO_EXTEND: ++ /* Sign/Zero extensions of registers cost quite much since these ++ instrcutions only take one register operand which means that gcc ++ often must insert some move instrcutions */ ++ if (mode == QImode || mode == HImode) ++ return (COSTS_N_INSNS (GET_CODE (XEXP (x, 0)) == MEM ? 0 : 1)); ++ return COSTS_N_INSNS (4); ++ case UNSPEC: ++ /* divmod operations */ ++ if (XINT (x, 1) == UNSPEC_UDIVMODSI4_INTERNAL ++ || XINT (x, 1) == UNSPEC_DIVMODSI4_INTERNAL) ++ { ++ return optimize_size ? COSTS_N_INSNS (1) : COSTS_N_INSNS (16); ++ } ++ /* Fallthrough */ ++ default: ++ return COSTS_N_INSNS (1); ++ } ++} + -+ /* void func (ulong) */ -+ void_ftype_ulong = build_function_type_list (void_type_node, -+ long_unsigned_type_node, NULL_TREE); + -+ /* void func (void) */ -+ void_ftype_void = build_function_type (void_type_node, void_endlink); ++static bool ++avr32_rtx_costs (rtx x, int code, int outer_code, int *total) ++{ ++ *total = avr32_rtx_costs_1 (x, code, outer_code); ++ return true; ++} + -+ /* int func (void) */ -+ int_ftype_void = build_function_type (integer_type_node, void_endlink); + -+ /* int func (void *, int) */ -+ int_ftype_ptr_int -+ = build_function_type (integer_type_node, -+ tree_cons (NULL_TREE, ptr_type_node, int_endlink)); ++bool ++avr32_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) ++{ ++ /* Do not want symbols in the constant pool when compiling pic or if using ++ address pseudo instructions. */ ++ return ((flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS) ++ && avr32_find_symbol (x) != NULL_RTX); ++} + -+ /* int func (int, int, int) */ -+ int_ftype_int_int_int -+ = build_function_type (integer_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ tree_cons (NULL_TREE, integer_type_node, -+ int_endlink))); + -+ /* Initialize avr32 builtins. */ -+ def_builtin ("__builtin_mfsr", int_ftype_int, AVR32_BUILTIN_MFSR); -+ def_builtin ("__builtin_mtsr", void_ftype_int_int, AVR32_BUILTIN_MTSR); -+ def_builtin ("__builtin_mfdr", int_ftype_int, AVR32_BUILTIN_MFDR); -+ def_builtin ("__builtin_mtdr", void_ftype_int_int, AVR32_BUILTIN_MTDR); -+ def_builtin ("__builtin_cache", void_ftype_ptr_int, AVR32_BUILTIN_CACHE); -+ def_builtin ("__builtin_sync", void_ftype_int, AVR32_BUILTIN_SYNC); -+ def_builtin ("__builtin_ssrf", void_ftype_int, AVR32_BUILTIN_SSRF); -+ def_builtin ("__builtin_csrf", void_ftype_int, AVR32_BUILTIN_CSRF); -+ def_builtin ("__builtin_tlbr", void_ftype_void, AVR32_BUILTIN_TLBR); -+ def_builtin ("__builtin_tlbs", void_ftype_void, AVR32_BUILTIN_TLBS); -+ def_builtin ("__builtin_tlbw", void_ftype_void, AVR32_BUILTIN_TLBW); -+ def_builtin ("__builtin_breakpoint", void_ftype_void, -+ AVR32_BUILTIN_BREAKPOINT); -+ def_builtin ("__builtin_xchg", int_ftype_ptr_int, AVR32_BUILTIN_XCHG); -+ def_builtin ("__builtin_ldxi", int_ftype_ptr_int, AVR32_BUILTIN_LDXI); -+ def_builtin ("__builtin_bswap_16", short_ftype_short, -+ AVR32_BUILTIN_BSWAP16); -+ def_builtin ("__builtin_bswap_32", int_ftype_int, AVR32_BUILTIN_BSWAP32); -+ def_builtin ("__builtin_cop", void_ftype_int_int_int_int_int, -+ AVR32_BUILTIN_COP); -+ def_builtin ("__builtin_mvcr_w", int_ftype_int_int, AVR32_BUILTIN_MVCR_W); -+ def_builtin ("__builtin_mvrc_w", void_ftype_int_int_int, -+ AVR32_BUILTIN_MVRC_W); -+ def_builtin ("__builtin_mvcr_d", longlong_ftype_int_int, -+ AVR32_BUILTIN_MVCR_D); -+ def_builtin ("__builtin_mvrc_d", void_ftype_int_int_longlong, -+ AVR32_BUILTIN_MVRC_D); -+ def_builtin ("__builtin_sats", int_ftype_int_int_int, AVR32_BUILTIN_SATS); -+ def_builtin ("__builtin_satu", int_ftype_int_int_int, AVR32_BUILTIN_SATU); -+ def_builtin ("__builtin_satrnds", int_ftype_int_int_int, -+ AVR32_BUILTIN_SATRNDS); -+ def_builtin ("__builtin_satrndu", int_ftype_int_int_int, -+ AVR32_BUILTIN_SATRNDU); -+ def_builtin ("__builtin_musfr", void_ftype_int, AVR32_BUILTIN_MUSFR); -+ def_builtin ("__builtin_mustr", int_ftype_void, AVR32_BUILTIN_MUSTR); -+ def_builtin ("__builtin_macsathh_w", int_ftype_int_short_short, -+ AVR32_BUILTIN_MACSATHH_W); -+ def_builtin ("__builtin_macwh_d", longlong_ftype_longlong_int_short, -+ AVR32_BUILTIN_MACWH_D); -+ def_builtin ("__builtin_machh_d", longlong_ftype_longlong_short_short, -+ AVR32_BUILTIN_MACHH_D); -+ def_builtin ("__builtin_mems", void_ftype_ptr_int, AVR32_BUILTIN_MEMS); -+ def_builtin ("__builtin_memt", void_ftype_ptr_int, AVR32_BUILTIN_MEMT); -+ def_builtin ("__builtin_memc", void_ftype_ptr_int, AVR32_BUILTIN_MEMC); -+ def_builtin ("__builtin_sleep", void_ftype_int, AVR32_BUILTIN_SLEEP); -+ def_builtin ("__builtin_avr32_delay_cycles", void_ftype_int, AVR32_BUILTIN_DELAY_CYCLES); -+ -+ /* Add all builtins that are more or less simple operations on two -+ operands. */ -+ for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) -+ { -+ /* Use one of the operands; the target can have a different mode for -+ mask-generating compares. */ -+ -+ if (d->name == 0) -+ continue; -+ -+ def_mbuiltin (d->mask, d->name, *(d->ftype), d->code); -+ } -+} ++/* Table of machine attributes. */ ++const struct attribute_spec avr32_attribute_table[] = { ++ /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ ++ /* Interrupt Service Routines have special prologue and epilogue ++ requirements. */ ++ {"isr", 0, 1, false, false, false, avr32_handle_isr_attribute}, ++ {"interrupt", 0, 1, false, false, false, avr32_handle_isr_attribute}, ++ {"acall", 0, 1, false, true, true, avr32_handle_acall_attribute}, ++ {"naked", 0, 0, true, false, false, avr32_handle_fndecl_attribute}, ++ {"rmw_addressable", 0, 0, true, false, false, NULL}, ++ {"flashvault", 0, 1, true, false, false, avr32_handle_fndecl_attribute}, ++ {"flashvault_impl", 0, 1, true, false, false, avr32_handle_fndecl_attribute}, ++ {NULL, 0, 0, false, false, false, NULL} ++}; + + -+/* Subroutine of avr32_expand_builtin to take care of binop insns. */ -+static rtx -+avr32_expand_binop_builtin (enum insn_code icode, tree exp, rtx target) ++typedef struct +{ -+ rtx pat; -+ tree arg0 = CALL_EXPR_ARG (exp,0); -+ tree arg1 = CALL_EXPR_ARG (exp,1); -+ rtx op0 = expand_normal (arg0); -+ rtx op1 = expand_normal (arg1); -+ enum machine_mode tmode = insn_data[icode].operand[0].mode; -+ enum machine_mode mode0 = insn_data[icode].operand[1].mode; -+ enum machine_mode mode1 = insn_data[icode].operand[2].mode; ++ const char *const arg; ++ const unsigned long return_value; ++} ++isr_attribute_arg; + -+ if (!target -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); + -+ /* In case the insn wants input operands in modes different from the -+ result, abort. */ -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ { -+ /* If op0 is already a reg we must cast it to the correct mode. */ -+ if (REG_P (op0)) -+ op0 = convert_to_mode (mode0, op0, 1); -+ else -+ op0 = copy_to_mode_reg (mode0, op0); -+ } -+ if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) -+ { -+ /* If op1 is already a reg we must cast it to the correct mode. */ -+ if (REG_P (op1)) -+ op1 = convert_to_mode (mode1, op1, 1); -+ else -+ op1 = copy_to_mode_reg (mode1, op1); -+ } -+ pat = GEN_FCN (icode) (target, op0, op1); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return target; -+} ++static const isr_attribute_arg isr_attribute_args[] = { ++ {"FULL", AVR32_FT_ISR_FULL}, ++ {"full", AVR32_FT_ISR_FULL}, ++ {"HALF", AVR32_FT_ISR_HALF}, ++ {"half", AVR32_FT_ISR_HALF}, ++ {"NONE", AVR32_FT_ISR_NONE}, ++ {"none", AVR32_FT_ISR_NONE}, ++ {"UNDEF", AVR32_FT_ISR_NONE}, ++ {"undef", AVR32_FT_ISR_NONE}, ++ {"SWI", AVR32_FT_ISR_NONE}, ++ {"swi", AVR32_FT_ISR_NONE}, ++ {NULL, AVR32_FT_ISR_NONE} ++}; + + -+/* Expand an expression EXP that calls a built-in function, -+ with result going to TARGET if that's convenient -+ (and in mode MODE if that's convenient). -+ SUBTARGET may be used as the target for computing one of EXP's operands. -+ IGNORE is nonzero if the value is to be ignored. */ -+rtx -+avr32_expand_builtin (tree exp, -+ rtx target, -+ rtx subtarget ATTRIBUTE_UNUSED, -+ enum machine_mode mode ATTRIBUTE_UNUSED, -+ int ignore ATTRIBUTE_UNUSED) ++/* Returns the (interrupt) function type of the current ++ function, or AVR32_FT_UNKNOWN if the type cannot be determined. */ ++static unsigned long ++avr32_isr_value (tree argument) +{ -+ const struct builtin_description *d; -+ unsigned int i; -+ enum insn_code icode = 0; -+ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); -+ tree arg0, arg1, arg2; -+ rtx op0, op1, op2, pat; -+ enum machine_mode tmode, mode0, mode1; -+ enum machine_mode arg0_mode; -+ int fcode = DECL_FUNCTION_CODE (fndecl); ++ const isr_attribute_arg *ptr; ++ const char *arg; + -+ switch (fcode) -+ { -+ default: -+ break; ++ /* No argument - default to ISR_NONE. */ ++ if (argument == NULL_TREE) ++ return AVR32_FT_ISR_NONE; + -+ case AVR32_BUILTIN_SATS: -+ case AVR32_BUILTIN_SATU: -+ case AVR32_BUILTIN_SATRNDS: -+ case AVR32_BUILTIN_SATRNDU: -+ { -+ const char *fname; -+ switch (fcode) -+ { -+ default: -+ case AVR32_BUILTIN_SATS: -+ icode = CODE_FOR_sats; -+ fname = "sats"; -+ break; -+ case AVR32_BUILTIN_SATU: -+ icode = CODE_FOR_satu; -+ fname = "satu"; -+ break; -+ case AVR32_BUILTIN_SATRNDS: -+ icode = CODE_FOR_satrnds; -+ fname = "satrnds"; -+ break; -+ case AVR32_BUILTIN_SATRNDU: -+ icode = CODE_FOR_satrndu; -+ fname = "satrndu"; -+ break; -+ } ++ /* Get the value of the argument. */ ++ if (TREE_VALUE (argument) == NULL_TREE ++ || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) ++ return AVR32_FT_UNKNOWN; + -+ arg0 = CALL_EXPR_ARG (exp,0); -+ arg1 = CALL_EXPR_ARG (exp,1); -+ arg2 = CALL_EXPR_ARG (exp,2); -+ op0 = expand_normal (arg0); -+ op1 = expand_normal (arg1); -+ op2 = expand_normal (arg2); ++ arg = TREE_STRING_POINTER (TREE_VALUE (argument)); + -+ tmode = insn_data[icode].operand[0].mode; ++ /* Check it against the list of known arguments. */ ++ for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++) ++ if (streq (arg, ptr->arg)) ++ return ptr->return_value; + ++ /* An unrecognized interrupt type. */ ++ return AVR32_FT_UNKNOWN; ++} + -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); + ++/* ++These hooks specify assembly directives for creating certain kinds ++of integer object. The TARGET_ASM_BYTE_OP directive creates a ++byte-sized object, the TARGET_ASM_ALIGNED_HI_OP one creates an ++aligned two-byte object, and so on. Any of the hooks may be ++NULL, indicating that no suitable directive is available. + -+ if (!(*insn_data[icode].operand[0].predicate) (op0, GET_MODE (op0))) -+ { -+ op0 = copy_to_mode_reg (insn_data[icode].operand[0].mode, op0); -+ } ++The compiler will print these strings at the start of a new line, ++followed immediately by the object's initial value. In most cases, ++the string should contain a tab, a pseudo-op, and then another tab. ++*/ ++#undef TARGET_ASM_BYTE_OP ++#define TARGET_ASM_BYTE_OP "\t.byte\t" ++#undef TARGET_ASM_ALIGNED_HI_OP ++#define TARGET_ASM_ALIGNED_HI_OP "\t.align 1\n\t.short\t" ++#undef TARGET_ASM_ALIGNED_SI_OP ++#define TARGET_ASM_ALIGNED_SI_OP "\t.align 2\n\t.int\t" ++#undef TARGET_ASM_ALIGNED_DI_OP ++#define TARGET_ASM_ALIGNED_DI_OP NULL ++#undef TARGET_ASM_ALIGNED_TI_OP ++#define TARGET_ASM_ALIGNED_TI_OP NULL ++#undef TARGET_ASM_UNALIGNED_HI_OP ++#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" ++#undef TARGET_ASM_UNALIGNED_SI_OP ++#define TARGET_ASM_UNALIGNED_SI_OP "\t.int\t" ++#undef TARGET_ASM_UNALIGNED_DI_OP ++#define TARGET_ASM_UNALIGNED_DI_OP NULL ++#undef TARGET_ASM_UNALIGNED_TI_OP ++#define TARGET_ASM_UNALIGNED_TI_OP NULL + -+ if (!(*insn_data[icode].operand[1].predicate) (op1, SImode)) -+ { -+ error ("Parameter 2 to __builtin_%s should be a constant number.", -+ fname); -+ return NULL_RTX; -+ } ++#undef TARGET_ASM_OUTPUT_MI_THUNK ++#define TARGET_ASM_OUTPUT_MI_THUNK avr32_output_mi_thunk + -+ if (!(*insn_data[icode].operand[1].predicate) (op2, SImode)) -+ { -+ error ("Parameter 3 to __builtin_%s should be a constant number.", -+ fname); -+ return NULL_RTX; -+ } ++#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK ++#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true + -+ emit_move_insn (target, op0); -+ pat = GEN_FCN (icode) (target, op1, op2); -+ if (!pat) -+ return 0; -+ emit_insn (pat); + -+ return target; -+ } -+ case AVR32_BUILTIN_MUSTR: -+ icode = CODE_FOR_mustr; -+ tmode = insn_data[icode].operand[0].mode; ++static void ++avr32_output_mi_thunk (FILE * file, ++ tree thunk ATTRIBUTE_UNUSED, ++ HOST_WIDE_INT delta, ++ HOST_WIDE_INT vcall_offset, tree function) ++ { ++ int mi_delta = delta; ++ int this_regno = ++ (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) ? ++ INTERNAL_REGNUM (11) : INTERNAL_REGNUM (12)); + -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ pat = GEN_FCN (icode) (target); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return target; + -+ case AVR32_BUILTIN_MFSR: -+ icode = CODE_FOR_mfsr; -+ arg0 = CALL_EXPR_ARG (exp,0); -+ op0 = expand_normal (arg0); -+ tmode = insn_data[icode].operand[0].mode; -+ mode0 = insn_data[icode].operand[1].mode; ++ if (!avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21") ++ || vcall_offset) ++ { ++ fputs ("\tpushm\tlr\n", file); ++ } + -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ { -+ error ("Parameter 1 to __builtin_mfsr must be a constant number"); -+ } + -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ pat = GEN_FCN (icode) (target, op0); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return target; -+ case AVR32_BUILTIN_MTSR: -+ icode = CODE_FOR_mtsr; -+ arg0 = CALL_EXPR_ARG (exp,0); -+ arg1 = CALL_EXPR_ARG (exp,1); -+ op0 = expand_normal (arg0); -+ op1 = expand_normal (arg1); -+ mode0 = insn_data[icode].operand[0].mode; -+ mode1 = insn_data[icode].operand[1].mode; ++ if (mi_delta != 0) ++ { ++ if (avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21")) ++ { ++ fprintf (file, "\tsub\t%s, %d\n", reg_names[this_regno], -mi_delta); ++ } ++ else ++ { ++ /* Immediate is larger than k21 we must make us a temp register by ++ pushing a register to the stack. */ ++ fprintf (file, "\tmov\tlr, lo(%d)\n", mi_delta); ++ fprintf (file, "\torh\tlr, hi(%d)\n", mi_delta); ++ fprintf (file, "\tadd\t%s, lr\n", reg_names[this_regno]); ++ } ++ } + -+ if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) -+ { -+ error ("Parameter 1 to __builtin_mtsr must be a constant number"); -+ return gen_reg_rtx (mode0); -+ } -+ if (!(*insn_data[icode].operand[1].predicate) (op1, mode1)) -+ op1 = copy_to_mode_reg (mode1, op1); -+ pat = GEN_FCN (icode) (op0, op1); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return NULL_RTX; -+ case AVR32_BUILTIN_MFDR: -+ icode = CODE_FOR_mfdr; -+ arg0 = CALL_EXPR_ARG (exp,0); -+ op0 = expand_normal (arg0); -+ tmode = insn_data[icode].operand[0].mode; -+ mode0 = insn_data[icode].operand[1].mode; + -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ { -+ error ("Parameter 1 to __builtin_mfdr must be a constant number"); -+ } ++ if (vcall_offset != 0) ++ { ++ fprintf (file, "\tld.w\tlr, %s[0]\n", reg_names[this_regno]); ++ fprintf (file, "\tld.w\tlr, lr[%i]\n", (int) vcall_offset); ++ fprintf (file, "\tadd\t%s, lr\n", reg_names[this_regno]); ++ } + -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ pat = GEN_FCN (icode) (target, op0); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return target; -+ case AVR32_BUILTIN_MTDR: -+ icode = CODE_FOR_mtdr; -+ arg0 = CALL_EXPR_ARG (exp,0); -+ arg1 = CALL_EXPR_ARG (exp,1); -+ op0 = expand_normal (arg0); -+ op1 = expand_normal (arg1); -+ mode0 = insn_data[icode].operand[0].mode; -+ mode1 = insn_data[icode].operand[1].mode; + -+ if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) -+ { -+ error ("Parameter 1 to __builtin_mtdr must be a constant number"); -+ return gen_reg_rtx (mode0); -+ } -+ if (!(*insn_data[icode].operand[1].predicate) (op1, mode1)) -+ op1 = copy_to_mode_reg (mode1, op1); -+ pat = GEN_FCN (icode) (op0, op1); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return NULL_RTX; -+ case AVR32_BUILTIN_CACHE: -+ icode = CODE_FOR_cache; -+ arg0 = CALL_EXPR_ARG (exp,0); -+ arg1 = CALL_EXPR_ARG (exp,1); -+ op0 = expand_normal (arg0); -+ op1 = expand_normal (arg1); -+ mode0 = insn_data[icode].operand[0].mode; -+ mode1 = insn_data[icode].operand[1].mode; ++ if (!avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21") ++ || vcall_offset) ++ { ++ fputs ("\tpopm\tlr\n", file); ++ } + -+ if (!(*insn_data[icode].operand[1].predicate) (op1, mode1)) -+ { -+ error ("Parameter 2 to __builtin_cache must be a constant number"); -+ return gen_reg_rtx (mode1); -+ } ++ /* Jump to the function. We assume that we can use an rjmp since the ++ function to jump to is local and probably not too far away from ++ the thunk. If this assumption proves to be wrong we could implement ++ this jump by calculating the offset between the jump source and destination ++ and put this in the constant pool and then perform an add to pc. ++ This would also be legitimate PIC code. But for now we hope that an rjmp ++ will be sufficient... ++ */ ++ fputs ("\trjmp\t", file); ++ assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); ++ fputc ('\n', file); ++ } + -+ if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) -+ op0 = copy_to_mode_reg (mode0, op0); + -+ pat = GEN_FCN (icode) (op0, op1); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return NULL_RTX; -+ case AVR32_BUILTIN_SYNC: -+ case AVR32_BUILTIN_MUSFR: -+ case AVR32_BUILTIN_SSRF: -+ case AVR32_BUILTIN_CSRF: -+ { -+ const char *fname; -+ switch (fcode) -+ { -+ default: -+ case AVR32_BUILTIN_SYNC: -+ icode = CODE_FOR_sync; -+ fname = "sync"; -+ break; -+ case AVR32_BUILTIN_MUSFR: -+ icode = CODE_FOR_musfr; -+ fname = "musfr"; -+ break; -+ case AVR32_BUILTIN_SSRF: -+ icode = CODE_FOR_ssrf; -+ fname = "ssrf"; -+ break; -+ case AVR32_BUILTIN_CSRF: -+ icode = CODE_FOR_csrf; -+ fname = "csrf"; -+ break; -+ } ++/* Implements target hook vector_mode_supported. */ ++bool ++avr32_vector_mode_supported (enum machine_mode mode) ++{ ++ if ((mode == V2HImode) || (mode == V4QImode)) ++ return true; + -+ arg0 = CALL_EXPR_ARG (exp,0); -+ op0 = expand_normal (arg0); -+ mode0 = insn_data[icode].operand[0].mode; ++ return false; ++} + -+ if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) -+ { -+ if (icode == CODE_FOR_musfr) -+ op0 = copy_to_mode_reg (mode0, op0); -+ else -+ { -+ error ("Parameter to __builtin_%s is illegal.", fname); -+ return gen_reg_rtx (mode0); -+ } -+ } -+ pat = GEN_FCN (icode) (op0); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return NULL_RTX; -+ } -+ case AVR32_BUILTIN_TLBR: -+ icode = CODE_FOR_tlbr; -+ pat = GEN_FCN (icode) (NULL_RTX); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return NULL_RTX; -+ case AVR32_BUILTIN_TLBS: -+ icode = CODE_FOR_tlbs; -+ pat = GEN_FCN (icode) (NULL_RTX); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return NULL_RTX; -+ case AVR32_BUILTIN_TLBW: -+ icode = CODE_FOR_tlbw; -+ pat = GEN_FCN (icode) (NULL_RTX); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return NULL_RTX; -+ case AVR32_BUILTIN_BREAKPOINT: -+ icode = CODE_FOR_breakpoint; -+ pat = GEN_FCN (icode) (NULL_RTX); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return NULL_RTX; -+ case AVR32_BUILTIN_XCHG: -+ icode = CODE_FOR_sync_lock_test_and_setsi; -+ arg0 = CALL_EXPR_ARG (exp,0); -+ arg1 = CALL_EXPR_ARG (exp,1); -+ op0 = expand_normal (arg0); -+ op1 = expand_normal (arg1); -+ tmode = insn_data[icode].operand[0].mode; -+ mode0 = insn_data[icode].operand[1].mode; -+ mode1 = insn_data[icode].operand[2].mode; + -+ if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) -+ { -+ op1 = copy_to_mode_reg (mode1, op1); -+ } ++#undef TARGET_INIT_LIBFUNCS ++#define TARGET_INIT_LIBFUNCS avr32_init_libfuncs + -+ op0 = force_reg (GET_MODE (op0), op0); -+ op0 = gen_rtx_MEM (GET_MODE (op0), op0); -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ { -+ error -+ ("Parameter 1 to __builtin_xchg must be a pointer to an integer."); -+ } ++#undef TARGET_INIT_BUILTINS ++#define TARGET_INIT_BUILTINS avr32_init_builtins + -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ pat = GEN_FCN (icode) (target, op0, op1); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return target; -+ case AVR32_BUILTIN_LDXI: -+ icode = CODE_FOR_ldxi; -+ arg0 = CALL_EXPR_ARG (exp,0); -+ arg1 = CALL_EXPR_ARG (exp,1); -+ arg2 = CALL_EXPR_ARG (exp,2); -+ op0 = expand_normal (arg0); -+ op1 = expand_normal (arg1); -+ op2 = expand_normal (arg2); -+ tmode = insn_data[icode].operand[0].mode; -+ mode0 = insn_data[icode].operand[1].mode; -+ mode1 = insn_data[icode].operand[2].mode; ++#undef TARGET_EXPAND_BUILTIN ++#define TARGET_EXPAND_BUILTIN avr32_expand_builtin + -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ { -+ op0 = copy_to_mode_reg (mode0, op0); -+ } ++tree int_ftype_int, int_ftype_void, short_ftype_short, void_ftype_int_int, ++ void_ftype_ptr_int; ++tree void_ftype_int, void_ftype_ulong, void_ftype_void, int_ftype_ptr_int; ++tree short_ftype_short, int_ftype_int_short, int_ftype_short_short, ++ short_ftype_short_short; ++tree int_ftype_int_int, longlong_ftype_int_short, longlong_ftype_short_short; ++tree void_ftype_int_int_int_int_int, void_ftype_int_int_int; ++tree longlong_ftype_int_int, void_ftype_int_int_longlong; ++tree int_ftype_int_int_int, longlong_ftype_longlong_int_short; ++tree longlong_ftype_longlong_short_short, int_ftype_int_short_short; + -+ if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) -+ { -+ op1 = copy_to_mode_reg (mode1, op1); -+ } ++#define def_builtin(NAME, TYPE, CODE) \ ++ add_builtin_function ((NAME), (TYPE), (CODE), \ ++ BUILT_IN_MD, NULL, NULL_TREE) + -+ if (!(*insn_data[icode].operand[3].predicate) (op2, SImode)) -+ { -+ error -+ ("Parameter 3 to __builtin_ldxi must be a valid extract shift operand: (0|8|16|24)"); -+ return gen_reg_rtx (mode0); -+ } ++#define def_mbuiltin(MASK, NAME, TYPE, CODE) \ ++ do \ ++ { \ ++ if ((MASK)) \ ++ add_builtin_function ((NAME), (TYPE), (CODE), \ ++ BUILT_IN_MD, NULL, NULL_TREE); \ ++ } \ ++ while (0) + -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ pat = GEN_FCN (icode) (target, op0, op1, op2); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return target; -+ case AVR32_BUILTIN_BSWAP16: -+ { -+ icode = CODE_FOR_bswap_16; -+ arg0 = CALL_EXPR_ARG (exp,0); -+ arg0_mode = TYPE_MODE (TREE_TYPE (arg0)); -+ mode0 = insn_data[icode].operand[1].mode; -+ if (arg0_mode != mode0) -+ arg0 = build1 (NOP_EXPR, -+ (*lang_hooks.types.type_for_mode) (mode0, 0), arg0); ++struct builtin_description ++{ ++ const unsigned int mask; ++ const enum insn_code icode; ++ const char *const name; ++ const int code; ++ const enum rtx_code comparison; ++ const unsigned int flag; ++ const tree *ftype; ++}; + -+ op0 = expand_expr (arg0, NULL_RTX, HImode, 0); -+ tmode = insn_data[icode].operand[0].mode; ++static const struct builtin_description bdesc_2arg[] = { + ++#define DSP_BUILTIN(code, builtin, ftype) \ ++ { 1, CODE_FOR_##code, "__builtin_" #code , \ ++ AVR32_BUILTIN_##builtin, 0, 0, ftype } + -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ { -+ if ( CONST_INT_P (op0) ) -+ { -+ HOST_WIDE_INT val = ( ((INTVAL (op0)&0x00ff) << 8) | -+ ((INTVAL (op0)&0xff00) >> 8) ); -+ /* Sign extend 16-bit value to host wide int */ -+ val <<= (HOST_BITS_PER_WIDE_INT - 16); -+ val >>= (HOST_BITS_PER_WIDE_INT - 16); -+ op0 = GEN_INT(val); -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ emit_move_insn(target, op0); -+ return target; -+ } -+ else -+ op0 = copy_to_mode_reg (mode0, op0); -+ } ++ DSP_BUILTIN (mulsathh_h, MULSATHH_H, &short_ftype_short_short), ++ DSP_BUILTIN (mulsathh_w, MULSATHH_W, &int_ftype_short_short), ++ DSP_BUILTIN (mulsatrndhh_h, MULSATRNDHH_H, &short_ftype_short_short), ++ DSP_BUILTIN (mulsatrndwh_w, MULSATRNDWH_W, &int_ftype_int_short), ++ DSP_BUILTIN (mulsatwh_w, MULSATWH_W, &int_ftype_int_short), ++ DSP_BUILTIN (satadd_h, SATADD_H, &short_ftype_short_short), ++ DSP_BUILTIN (satsub_h, SATSUB_H, &short_ftype_short_short), ++ DSP_BUILTIN (satadd_w, SATADD_W, &int_ftype_int_int), ++ DSP_BUILTIN (satsub_w, SATSUB_W, &int_ftype_int_int), ++ DSP_BUILTIN (mulwh_d, MULWH_D, &longlong_ftype_int_short), ++ DSP_BUILTIN (mulnwh_d, MULNWH_D, &longlong_ftype_int_short) ++}; + -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ { -+ target = gen_reg_rtx (tmode); -+ } + ++void ++avr32_init_builtins (void) ++{ ++ unsigned int i; ++ const struct builtin_description *d; ++ tree endlink = void_list_node; ++ tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink); ++ tree longlong_endlink = ++ tree_cons (NULL_TREE, long_long_integer_type_node, endlink); ++ tree short_endlink = ++ tree_cons (NULL_TREE, short_integer_type_node, endlink); ++ tree void_endlink = tree_cons (NULL_TREE, void_type_node, endlink); + -+ pat = GEN_FCN (icode) (target, op0); -+ if (!pat) -+ return 0; -+ emit_insn (pat); ++ /* int func (int) */ ++ int_ftype_int = build_function_type (integer_type_node, int_endlink); + -+ return target; -+ } -+ case AVR32_BUILTIN_BSWAP32: -+ { -+ icode = CODE_FOR_bswap_32; -+ arg0 = CALL_EXPR_ARG (exp,0); -+ op0 = expand_normal (arg0); -+ tmode = insn_data[icode].operand[0].mode; -+ mode0 = insn_data[icode].operand[1].mode; ++ /* short func (short) */ ++ short_ftype_short ++ = build_function_type (short_integer_type_node, short_endlink); + -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ { -+ if ( CONST_INT_P (op0) ) -+ { -+ HOST_WIDE_INT val = ( ((INTVAL (op0)&0x000000ff) << 24) | -+ ((INTVAL (op0)&0x0000ff00) << 8) | -+ ((INTVAL (op0)&0x00ff0000) >> 8) | -+ ((INTVAL (op0)&0xff000000) >> 24) ); -+ /* Sign extend 32-bit value to host wide int */ -+ val <<= (HOST_BITS_PER_WIDE_INT - 32); -+ val >>= (HOST_BITS_PER_WIDE_INT - 32); -+ op0 = GEN_INT(val); -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); -+ emit_move_insn(target, op0); -+ return target; -+ } -+ else -+ op0 = copy_to_mode_reg (mode0, op0); -+ } ++ /* short func (short, short) */ ++ short_ftype_short_short ++ = build_function_type (short_integer_type_node, ++ tree_cons (NULL_TREE, short_integer_type_node, ++ short_endlink)); + -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); ++ /* long long func (long long, short, short) */ ++ longlong_ftype_longlong_short_short ++ = build_function_type (long_long_integer_type_node, ++ tree_cons (NULL_TREE, long_long_integer_type_node, ++ tree_cons (NULL_TREE, ++ short_integer_type_node, ++ short_endlink))); + ++ /* long long func (short, short) */ ++ longlong_ftype_short_short ++ = build_function_type (long_long_integer_type_node, ++ tree_cons (NULL_TREE, short_integer_type_node, ++ short_endlink)); + -+ pat = GEN_FCN (icode) (target, op0); -+ if (!pat) -+ return 0; -+ emit_insn (pat); ++ /* int func (int, int) */ ++ int_ftype_int_int ++ = build_function_type (integer_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ int_endlink)); + -+ return target; -+ } -+ case AVR32_BUILTIN_MVCR_W: -+ case AVR32_BUILTIN_MVCR_D: -+ { -+ arg0 = CALL_EXPR_ARG (exp,0); -+ arg1 = CALL_EXPR_ARG (exp,1); -+ op0 = expand_normal (arg0); -+ op1 = expand_normal (arg1); ++ /* long long func (int, int) */ ++ longlong_ftype_int_int ++ = build_function_type (long_long_integer_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ int_endlink)); + -+ if (fcode == AVR32_BUILTIN_MVCR_W) -+ icode = CODE_FOR_mvcrsi; -+ else -+ icode = CODE_FOR_mvcrdi; ++ /* long long int func (long long, int, short) */ ++ longlong_ftype_longlong_int_short ++ = build_function_type (long_long_integer_type_node, ++ tree_cons (NULL_TREE, long_long_integer_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ short_endlink))); + -+ tmode = insn_data[icode].operand[0].mode; ++ /* long long int func (int, short) */ ++ longlong_ftype_int_short ++ = build_function_type (long_long_integer_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ short_endlink)); + -+ if (target == 0 -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); ++ /* int func (int, short, short) */ ++ int_ftype_int_short_short ++ = build_function_type (integer_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ tree_cons (NULL_TREE, ++ short_integer_type_node, ++ short_endlink))); + -+ if (!(*insn_data[icode].operand[1].predicate) (op0, SImode)) -+ { -+ error -+ ("Parameter 1 to __builtin_cop is not a valid coprocessor number."); -+ error ("Number should be between 0 and 7."); -+ return NULL_RTX; -+ } ++ /* int func (short, short) */ ++ int_ftype_short_short ++ = build_function_type (integer_type_node, ++ tree_cons (NULL_TREE, short_integer_type_node, ++ short_endlink)); + -+ if (!(*insn_data[icode].operand[2].predicate) (op1, SImode)) -+ { -+ error -+ ("Parameter 2 to __builtin_cop is not a valid coprocessor register number."); -+ error ("Number should be between 0 and 15."); -+ return NULL_RTX; -+ } ++ /* int func (int, short) */ ++ int_ftype_int_short ++ = build_function_type (integer_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ short_endlink)); + -+ pat = GEN_FCN (icode) (target, op0, op1); -+ if (!pat) -+ return 0; -+ emit_insn (pat); ++ /* void func (int, int) */ ++ void_ftype_int_int ++ = build_function_type (void_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ int_endlink)); + -+ return target; -+ } -+ case AVR32_BUILTIN_MACSATHH_W: -+ case AVR32_BUILTIN_MACWH_D: -+ case AVR32_BUILTIN_MACHH_D: -+ { -+ arg0 = CALL_EXPR_ARG (exp,0); -+ arg1 = CALL_EXPR_ARG (exp,1); -+ arg2 = CALL_EXPR_ARG (exp,2); -+ op0 = expand_normal (arg0); -+ op1 = expand_normal (arg1); -+ op2 = expand_normal (arg2); ++ /* void func (int, int, int) */ ++ void_ftype_int_int_int ++ = build_function_type (void_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ int_endlink))); + -+ icode = ((fcode == AVR32_BUILTIN_MACSATHH_W) ? CODE_FOR_macsathh_w : -+ (fcode == AVR32_BUILTIN_MACWH_D) ? CODE_FOR_macwh_d : -+ CODE_FOR_machh_d); ++ /* void func (int, int, long long) */ ++ void_ftype_int_int_longlong ++ = build_function_type (void_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ longlong_endlink))); + -+ tmode = insn_data[icode].operand[0].mode; -+ mode0 = insn_data[icode].operand[1].mode; -+ mode1 = insn_data[icode].operand[2].mode; ++ /* void func (int, int, int, int, int) */ ++ void_ftype_int_int_int_int_int ++ = build_function_type (void_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ tree_cons (NULL_TREE, ++ integer_type_node, ++ tree_cons ++ (NULL_TREE, ++ integer_type_node, ++ int_endlink))))); + ++ /* void func (void *, int) */ ++ void_ftype_ptr_int ++ = build_function_type (void_type_node, ++ tree_cons (NULL_TREE, ptr_type_node, int_endlink)); + -+ if (!target -+ || GET_MODE (target) != tmode -+ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) -+ target = gen_reg_rtx (tmode); ++ /* void func (int) */ ++ void_ftype_int = build_function_type (void_type_node, int_endlink); + -+ if (!(*insn_data[icode].operand[0].predicate) (op0, tmode)) -+ { -+ /* If op0 is already a reg we must cast it to the correct mode. */ -+ if (REG_P (op0)) -+ op0 = convert_to_mode (tmode, op0, 1); -+ else -+ op0 = copy_to_mode_reg (tmode, op0); -+ } ++ /* void func (ulong) */ ++ void_ftype_ulong = build_function_type_list (void_type_node, ++ long_unsigned_type_node, NULL_TREE); + -+ if (!(*insn_data[icode].operand[1].predicate) (op1, mode0)) -+ { -+ /* If op1 is already a reg we must cast it to the correct mode. */ -+ if (REG_P (op1)) -+ op1 = convert_to_mode (mode0, op1, 1); -+ else -+ op1 = copy_to_mode_reg (mode0, op1); -+ } ++ /* void func (void) */ ++ void_ftype_void = build_function_type (void_type_node, void_endlink); + -+ if (!(*insn_data[icode].operand[2].predicate) (op2, mode1)) -+ { -+ /* If op1 is already a reg we must cast it to the correct mode. */ -+ if (REG_P (op2)) -+ op2 = convert_to_mode (mode1, op2, 1); -+ else -+ op2 = copy_to_mode_reg (mode1, op2); -+ } ++ /* int func (void) */ ++ int_ftype_void = build_function_type (integer_type_node, void_endlink); + -+ emit_move_insn (target, op0); ++ /* int func (void *, int) */ ++ int_ftype_ptr_int ++ = build_function_type (integer_type_node, ++ tree_cons (NULL_TREE, ptr_type_node, int_endlink)); + -+ pat = GEN_FCN (icode) (target, op1, op2); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return target; -+ } -+ case AVR32_BUILTIN_MVRC_W: -+ case AVR32_BUILTIN_MVRC_D: -+ { -+ arg0 = CALL_EXPR_ARG (exp,0); -+ arg1 = CALL_EXPR_ARG (exp,1); -+ arg2 = CALL_EXPR_ARG (exp,2); -+ op0 = expand_normal (arg0); -+ op1 = expand_normal (arg1); -+ op2 = expand_normal (arg2); ++ /* int func (int, int, int) */ ++ int_ftype_int_int_int ++ = build_function_type (integer_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ tree_cons (NULL_TREE, integer_type_node, ++ int_endlink))); + -+ if (fcode == AVR32_BUILTIN_MVRC_W) -+ icode = CODE_FOR_mvrcsi; -+ else -+ icode = CODE_FOR_mvrcdi; ++ /* Initialize avr32 builtins. */ ++ def_builtin ("__builtin_mfsr", int_ftype_int, AVR32_BUILTIN_MFSR); ++ def_builtin ("__builtin_mtsr", void_ftype_int_int, AVR32_BUILTIN_MTSR); ++ def_builtin ("__builtin_mfdr", int_ftype_int, AVR32_BUILTIN_MFDR); ++ def_builtin ("__builtin_mtdr", void_ftype_int_int, AVR32_BUILTIN_MTDR); ++ def_builtin ("__builtin_cache", void_ftype_ptr_int, AVR32_BUILTIN_CACHE); ++ def_builtin ("__builtin_sync", void_ftype_int, AVR32_BUILTIN_SYNC); ++ def_builtin ("__builtin_ssrf", void_ftype_int, AVR32_BUILTIN_SSRF); ++ def_builtin ("__builtin_csrf", void_ftype_int, AVR32_BUILTIN_CSRF); ++ def_builtin ("__builtin_tlbr", void_ftype_void, AVR32_BUILTIN_TLBR); ++ def_builtin ("__builtin_tlbs", void_ftype_void, AVR32_BUILTIN_TLBS); ++ def_builtin ("__builtin_tlbw", void_ftype_void, AVR32_BUILTIN_TLBW); ++ def_builtin ("__builtin_breakpoint", void_ftype_void, ++ AVR32_BUILTIN_BREAKPOINT); ++ def_builtin ("__builtin_xchg", int_ftype_ptr_int, AVR32_BUILTIN_XCHG); ++ def_builtin ("__builtin_ldxi", int_ftype_ptr_int, AVR32_BUILTIN_LDXI); ++ def_builtin ("__builtin_bswap_16", short_ftype_short, ++ AVR32_BUILTIN_BSWAP16); ++ def_builtin ("__builtin_bswap_32", int_ftype_int, AVR32_BUILTIN_BSWAP32); ++ def_builtin ("__builtin_cop", void_ftype_int_int_int_int_int, ++ AVR32_BUILTIN_COP); ++ def_builtin ("__builtin_mvcr_w", int_ftype_int_int, AVR32_BUILTIN_MVCR_W); ++ def_builtin ("__builtin_mvrc_w", void_ftype_int_int_int, ++ AVR32_BUILTIN_MVRC_W); ++ def_builtin ("__builtin_mvcr_d", longlong_ftype_int_int, ++ AVR32_BUILTIN_MVCR_D); ++ def_builtin ("__builtin_mvrc_d", void_ftype_int_int_longlong, ++ AVR32_BUILTIN_MVRC_D); ++ def_builtin ("__builtin_sats", int_ftype_int_int_int, AVR32_BUILTIN_SATS); ++ def_builtin ("__builtin_satu", int_ftype_int_int_int, AVR32_BUILTIN_SATU); ++ def_builtin ("__builtin_satrnds", int_ftype_int_int_int, ++ AVR32_BUILTIN_SATRNDS); ++ def_builtin ("__builtin_satrndu", int_ftype_int_int_int, ++ AVR32_BUILTIN_SATRNDU); ++ def_builtin ("__builtin_musfr", void_ftype_int, AVR32_BUILTIN_MUSFR); ++ def_builtin ("__builtin_mustr", int_ftype_void, AVR32_BUILTIN_MUSTR); ++ def_builtin ("__builtin_macsathh_w", int_ftype_int_short_short, ++ AVR32_BUILTIN_MACSATHH_W); ++ def_builtin ("__builtin_macwh_d", longlong_ftype_longlong_int_short, ++ AVR32_BUILTIN_MACWH_D); ++ def_builtin ("__builtin_machh_d", longlong_ftype_longlong_short_short, ++ AVR32_BUILTIN_MACHH_D); ++ def_builtin ("__builtin_mems", void_ftype_ptr_int, AVR32_BUILTIN_MEMS); ++ def_builtin ("__builtin_memt", void_ftype_ptr_int, AVR32_BUILTIN_MEMT); ++ def_builtin ("__builtin_memc", void_ftype_ptr_int, AVR32_BUILTIN_MEMC); ++ def_builtin ("__builtin_sleep", void_ftype_int, AVR32_BUILTIN_SLEEP); ++ def_builtin ("__builtin_avr32_delay_cycles", void_ftype_int, AVR32_BUILTIN_DELAY_CYCLES); + -+ if (!(*insn_data[icode].operand[0].predicate) (op0, SImode)) -+ { -+ error ("Parameter 1 is not a valid coprocessor number."); -+ error ("Number should be between 0 and 7."); -+ return NULL_RTX; -+ } ++ /* Add all builtins that are more or less simple operations on two ++ operands. */ ++ for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) ++ { ++ /* Use one of the operands; the target can have a different mode for ++ mask-generating compares. */ + -+ if (!(*insn_data[icode].operand[1].predicate) (op1, SImode)) -+ { -+ error ("Parameter 2 is not a valid coprocessor register number."); -+ error ("Number should be between 0 and 15."); -+ return NULL_RTX; -+ } ++ if (d->name == 0) ++ continue; + -+ if (GET_CODE (op2) == CONST_INT -+ || GET_CODE (op2) == CONST -+ || GET_CODE (op2) == SYMBOL_REF || GET_CODE (op2) == LABEL_REF) -+ { -+ op2 = force_const_mem (insn_data[icode].operand[2].mode, op2); -+ } ++ def_mbuiltin (d->mask, d->name, *(d->ftype), d->code); ++ } ++} + -+ if (!(*insn_data[icode].operand[2].predicate) (op2, GET_MODE (op2))) -+ op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); + ++/* Subroutine of avr32_expand_builtin to take care of binop insns. */ ++static rtx ++avr32_expand_binop_builtin (enum insn_code icode, tree exp, rtx target) ++{ ++ rtx pat; ++ tree arg0 = CALL_EXPR_ARG (exp,0); ++ tree arg1 = CALL_EXPR_ARG (exp,1); ++ rtx op0 = expand_normal (arg0); ++ rtx op1 = expand_normal (arg1); ++ enum machine_mode tmode = insn_data[icode].operand[0].mode; ++ enum machine_mode mode0 = insn_data[icode].operand[1].mode; ++ enum machine_mode mode1 = insn_data[icode].operand[2].mode; + -+ pat = GEN_FCN (icode) (op0, op1, op2); -+ if (!pat) -+ return 0; -+ emit_insn (pat); ++ if (!target ++ || GET_MODE (target) != tmode ++ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) ++ target = gen_reg_rtx (tmode); ++ ++ /* In case the insn wants input operands in modes different from the ++ result, abort. */ ++ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) ++ { ++ /* If op0 is already a reg we must cast it to the correct mode. */ ++ if (REG_P (op0)) ++ op0 = convert_to_mode (mode0, op0, 1); ++ else ++ op0 = copy_to_mode_reg (mode0, op0); ++ } ++ if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) ++ { ++ /* If op1 is already a reg we must cast it to the correct mode. */ ++ if (REG_P (op1)) ++ op1 = convert_to_mode (mode1, op1, 1); ++ else ++ op1 = copy_to_mode_reg (mode1, op1); ++ } ++ pat = GEN_FCN (icode) (target, op0, op1); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return target; ++} ++ ++ ++/* Expand an expression EXP that calls a built-in function, ++ with result going to TARGET if that's convenient ++ (and in mode MODE if that's convenient). ++ SUBTARGET may be used as the target for computing one of EXP's operands. ++ IGNORE is nonzero if the value is to be ignored. */ ++rtx ++avr32_expand_builtin (tree exp, ++ rtx target, ++ rtx subtarget ATTRIBUTE_UNUSED, ++ enum machine_mode mode ATTRIBUTE_UNUSED, ++ int ignore ATTRIBUTE_UNUSED) ++{ ++ const struct builtin_description *d; ++ unsigned int i; ++ enum insn_code icode = 0; ++ tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); ++ tree arg0, arg1, arg2; ++ rtx op0, op1, op2, pat; ++ enum machine_mode tmode, mode0, mode1; ++ enum machine_mode arg0_mode; ++ int fcode = DECL_FUNCTION_CODE (fndecl); ++ ++ switch (fcode) ++ { ++ default: ++ break; ++ ++ case AVR32_BUILTIN_SATS: ++ case AVR32_BUILTIN_SATU: ++ case AVR32_BUILTIN_SATRNDS: ++ case AVR32_BUILTIN_SATRNDU: ++ { ++ const char *fname; ++ switch (fcode) ++ { ++ default: ++ case AVR32_BUILTIN_SATS: ++ icode = CODE_FOR_sats; ++ fname = "sats"; ++ break; ++ case AVR32_BUILTIN_SATU: ++ icode = CODE_FOR_satu; ++ fname = "satu"; ++ break; ++ case AVR32_BUILTIN_SATRNDS: ++ icode = CODE_FOR_satrnds; ++ fname = "satrnds"; ++ break; ++ case AVR32_BUILTIN_SATRNDU: ++ icode = CODE_FOR_satrndu; ++ fname = "satrndu"; ++ break; ++ } + -+ return NULL_RTX; -+ } -+ case AVR32_BUILTIN_COP: -+ { -+ rtx op3, op4; -+ tree arg3, arg4; -+ icode = CODE_FOR_cop; + arg0 = CALL_EXPR_ARG (exp,0); + arg1 = CALL_EXPR_ARG (exp,1); + arg2 = CALL_EXPR_ARG (exp,2); -+ arg3 = CALL_EXPR_ARG (exp,3); -+ arg4 = CALL_EXPR_ARG (exp,4); + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); + op2 = expand_normal (arg2); -+ op3 = expand_normal (arg3); -+ op4 = expand_normal (arg4); + -+ if (!(*insn_data[icode].operand[0].predicate) (op0, SImode)) -+ { -+ error -+ ("Parameter 1 to __builtin_cop is not a valid coprocessor number."); -+ error ("Number should be between 0 and 7."); -+ return NULL_RTX; -+ } ++ tmode = insn_data[icode].operand[0].mode; + -+ if (!(*insn_data[icode].operand[1].predicate) (op1, SImode)) -+ { -+ error -+ ("Parameter 2 to __builtin_cop is not a valid coprocessor register number."); -+ error ("Number should be between 0 and 15."); -+ return NULL_RTX; -+ } + -+ if (!(*insn_data[icode].operand[2].predicate) (op2, SImode)) ++ if (target == 0 ++ || GET_MODE (target) != tmode ++ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) ++ target = gen_reg_rtx (tmode); ++ ++ ++ if (!(*insn_data[icode].operand[0].predicate) (op0, GET_MODE (op0))) + { -+ error -+ ("Parameter 3 to __builtin_cop is not a valid coprocessor register number."); -+ error ("Number should be between 0 and 15."); -+ return NULL_RTX; ++ op0 = copy_to_mode_reg (insn_data[icode].operand[0].mode, op0); + } + -+ if (!(*insn_data[icode].operand[3].predicate) (op3, SImode)) ++ if (!(*insn_data[icode].operand[1].predicate) (op1, SImode)) + { -+ error -+ ("Parameter 4 to __builtin_cop is not a valid coprocessor register number."); -+ error ("Number should be between 0 and 15."); ++ error ("Parameter 2 to __builtin_%s should be a constant number.", ++ fname); + return NULL_RTX; + } + -+ if (!(*insn_data[icode].operand[4].predicate) (op4, SImode)) ++ if (!(*insn_data[icode].operand[1].predicate) (op2, SImode)) + { -+ error -+ ("Parameter 5 to __builtin_cop is not a valid coprocessor operation."); -+ error ("Number should be between 0 and 127."); ++ error ("Parameter 3 to __builtin_%s should be a constant number.", ++ fname); + return NULL_RTX; + } + -+ pat = GEN_FCN (icode) (op0, op1, op2, op3, op4); ++ emit_move_insn (target, op0); ++ pat = GEN_FCN (icode) (target, op1, op2); + if (!pat) + return 0; + emit_insn (pat); + + return target; + } ++ case AVR32_BUILTIN_MUSTR: ++ icode = CODE_FOR_mustr; ++ tmode = insn_data[icode].operand[0].mode; + -+ case AVR32_BUILTIN_MEMS: -+ case AVR32_BUILTIN_MEMC: -+ case AVR32_BUILTIN_MEMT: -+ { -+ if (!TARGET_RMW) -+ error ("Trying to use __builtin_mem(s/c/t) when target does not support RMW insns."); -+ -+ switch (fcode) { -+ case AVR32_BUILTIN_MEMS: -+ icode = CODE_FOR_iorsi3; -+ break; -+ case AVR32_BUILTIN_MEMC: -+ icode = CODE_FOR_andsi3; -+ break; -+ case AVR32_BUILTIN_MEMT: -+ icode = CODE_FOR_xorsi3; -+ break; -+ } -+ arg0 = CALL_EXPR_ARG (exp,0); -+ arg1 = CALL_EXPR_ARG (exp,1); -+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); -+ if ( GET_CODE (op0) == SYMBOL_REF ) -+ // This symbol must be RMW addressable -+ SYMBOL_REF_FLAGS (op0) |= (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT); -+ op0 = gen_rtx_MEM(SImode, op0); -+ op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); -+ mode0 = insn_data[icode].operand[1].mode; -+ -+ -+ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) -+ { -+ error ("Parameter 1 to __builtin_mem(s/c/t) must be a Ks15<<2 address or a rmw addressable symbol."); -+ } -+ -+ if ( !CONST_INT_P (op1) -+ || INTVAL (op1) > 31 -+ || INTVAL (op1) < 0 ) -+ error ("Parameter 2 to __builtin_mem(s/c/t) must be a constant between 0 and 31."); -+ -+ if ( fcode == AVR32_BUILTIN_MEMC ) -+ op1 = GEN_INT((~(1 << INTVAL(op1)))&0xffffffff); -+ else -+ op1 = GEN_INT((1 << INTVAL(op1))&0xffffffff); -+ pat = GEN_FCN (icode) (op0, op0, op1); -+ if (!pat) -+ return 0; -+ emit_insn (pat); -+ return op0; -+ } -+ -+ case AVR32_BUILTIN_SLEEP: -+ { -+ arg0 = CALL_EXPR_ARG (exp, 0); -+ op0 = expand_normal (arg0); -+ int intval = INTVAL(op0); -+ -+ /* Check if the argument if integer and if the value of integer -+ is greater than 0. */ -+ -+ if (!CONSTANT_P (op0)) -+ error ("Parameter 1 to __builtin_sleep() is not a valid integer."); -+ if (intval < 0 ) -+ error ("Parameter 1 to __builtin_sleep() should be an integer greater than 0."); -+ -+ int strncmpval = strncmp (avr32_part_name,"uc3l", 4); -+ -+ /* Check if op0 is less than 7 for uc3l* and less than 6 for other -+ devices. By this check we are avoiding if operand is less than -+ 256. For more devices, add more such checks. */ -+ -+ if ( strncmpval == 0 && intval >= 7) -+ error ("Parameter 1 to __builtin_sleep() should be less than or equal to 7."); -+ else if ( strncmp != 0 && intval >= 6) -+ error ("Parameter 1 to __builtin_sleep() should be less than or equal to 6."); -+ -+ emit_insn (gen_sleep(op0)); -+ return target; -+ -+ } -+ case AVR32_BUILTIN_DELAY_CYCLES: -+ { -+ arg0 = CALL_EXPR_ARG (exp, 0); -+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); -+ -+ if (TARGET_ARCH_AP) -+ error (" __builtin_avr32_delay_cycles() not supported for \'%s\' architecture.", avr32_arch_name); -+ if (!CONSTANT_P (op0)) -+ error ("Parameter 1 to __builtin_avr32_delay_cycles() should be an integer."); -+ emit_insn (gen_delay_cycles (op0)); -+ return 0; -+ -+ } -+ -+ } -+ -+ for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) -+ if (d->code == fcode) -+ return avr32_expand_binop_builtin (d->icode, exp, target); -+ ++ if (target == 0 ++ || GET_MODE (target) != tmode ++ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) ++ target = gen_reg_rtx (tmode); ++ pat = GEN_FCN (icode) (target); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return target; + -+ /* @@@ Should really do something sensible here. */ -+ return NULL_RTX; -+} ++ case AVR32_BUILTIN_MFSR: ++ icode = CODE_FOR_mfsr; ++ arg0 = CALL_EXPR_ARG (exp,0); ++ op0 = expand_normal (arg0); ++ tmode = insn_data[icode].operand[0].mode; ++ mode0 = insn_data[icode].operand[1].mode; + ++ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) ++ { ++ error ("Parameter 1 to __builtin_mfsr must be a constant number"); ++ } + -+/* Handle an "interrupt" or "isr" attribute; -+ arguments as in struct attribute_spec.handler. */ -+static tree -+avr32_handle_isr_attribute (tree * node, tree name, tree args, -+ int flags, bool * no_add_attrs) -+{ -+ if (DECL_P (*node)) -+ { -+ if (TREE_CODE (*node) != FUNCTION_DECL) ++ if (target == 0 ++ || GET_MODE (target) != tmode ++ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) ++ target = gen_reg_rtx (tmode); ++ pat = GEN_FCN (icode) (target, op0); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return target; ++ case AVR32_BUILTIN_MTSR: ++ icode = CODE_FOR_mtsr; ++ arg0 = CALL_EXPR_ARG (exp,0); ++ arg1 = CALL_EXPR_ARG (exp,1); ++ op0 = expand_normal (arg0); ++ op1 = expand_normal (arg1); ++ mode0 = insn_data[icode].operand[0].mode; ++ mode1 = insn_data[icode].operand[1].mode; ++ ++ if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) + { -+ warning (OPT_Wattributes,"`%s' attribute only applies to functions", -+ IDENTIFIER_POINTER (name)); -+ *no_add_attrs = true; ++ error ("Parameter 1 to __builtin_mtsr must be a constant number"); ++ return gen_reg_rtx (mode0); + } -+ /* FIXME: the argument if any is checked for type attributes; should it -+ be checked for decl ones? */ -+ } -+ else -+ { -+ if (TREE_CODE (*node) == FUNCTION_TYPE -+ || TREE_CODE (*node) == METHOD_TYPE) ++ if (!(*insn_data[icode].operand[1].predicate) (op1, mode1)) ++ op1 = copy_to_mode_reg (mode1, op1); ++ pat = GEN_FCN (icode) (op0, op1); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return NULL_RTX; ++ case AVR32_BUILTIN_MFDR: ++ icode = CODE_FOR_mfdr; ++ arg0 = CALL_EXPR_ARG (exp,0); ++ op0 = expand_normal (arg0); ++ tmode = insn_data[icode].operand[0].mode; ++ mode0 = insn_data[icode].operand[1].mode; ++ ++ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) + { -+ if (avr32_isr_value (args) == AVR32_FT_UNKNOWN) -+ { -+ warning (OPT_Wattributes,"`%s' attribute ignored", IDENTIFIER_POINTER (name)); -+ *no_add_attrs = true; -+ } ++ error ("Parameter 1 to __builtin_mfdr must be a constant number"); + } -+ else if (TREE_CODE (*node) == POINTER_TYPE -+ && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE -+ || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) -+ && avr32_isr_value (args) != AVR32_FT_UNKNOWN) ++ ++ if (target == 0 ++ || GET_MODE (target) != tmode ++ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) ++ target = gen_reg_rtx (tmode); ++ pat = GEN_FCN (icode) (target, op0); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return target; ++ case AVR32_BUILTIN_MTDR: ++ icode = CODE_FOR_mtdr; ++ arg0 = CALL_EXPR_ARG (exp,0); ++ arg1 = CALL_EXPR_ARG (exp,1); ++ op0 = expand_normal (arg0); ++ op1 = expand_normal (arg1); ++ mode0 = insn_data[icode].operand[0].mode; ++ mode1 = insn_data[icode].operand[1].mode; ++ ++ if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) + { -+ *node = build_variant_type_copy (*node); -+ TREE_TYPE (*node) = build_type_attribute_variant -+ (TREE_TYPE (*node), -+ tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); -+ *no_add_attrs = true; ++ error ("Parameter 1 to __builtin_mtdr must be a constant number"); ++ return gen_reg_rtx (mode0); + } -+ else ++ if (!(*insn_data[icode].operand[1].predicate) (op1, mode1)) ++ op1 = copy_to_mode_reg (mode1, op1); ++ pat = GEN_FCN (icode) (op0, op1); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return NULL_RTX; ++ case AVR32_BUILTIN_CACHE: ++ icode = CODE_FOR_cache; ++ arg0 = CALL_EXPR_ARG (exp,0); ++ arg1 = CALL_EXPR_ARG (exp,1); ++ op0 = expand_normal (arg0); ++ op1 = expand_normal (arg1); ++ mode0 = insn_data[icode].operand[0].mode; ++ mode1 = insn_data[icode].operand[1].mode; ++ ++ if (!(*insn_data[icode].operand[1].predicate) (op1, mode1)) + { -+ /* Possibly pass this attribute on from the type to a decl. */ -+ if (flags & ((int) ATTR_FLAG_DECL_NEXT -+ | (int) ATTR_FLAG_FUNCTION_NEXT -+ | (int) ATTR_FLAG_ARRAY_NEXT)) -+ { -+ *no_add_attrs = true; -+ return tree_cons (name, args, NULL_TREE); -+ } -+ else -+ { -+ warning (OPT_Wattributes,"`%s' attribute ignored", IDENTIFIER_POINTER (name)); -+ } ++ error ("Parameter 2 to __builtin_cache must be a constant number"); ++ return gen_reg_rtx (mode1); + } -+ } -+ -+ return NULL_TREE; -+} + ++ if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) ++ op0 = copy_to_mode_reg (mode0, op0); + -+/* Handle an attribute requiring a FUNCTION_DECL; -+ arguments as in struct attribute_spec.handler. */ -+static tree -+avr32_handle_fndecl_attribute (tree * node, tree name, -+ tree args, -+ int flags ATTRIBUTE_UNUSED, -+ bool * no_add_attrs) -+{ -+ if (TREE_CODE (*node) != FUNCTION_DECL) -+ { -+ warning (OPT_Wattributes,"%qs attribute only applies to functions", -+ IDENTIFIER_POINTER (name)); -+ *no_add_attrs = true; -+ return NULL_TREE; -+ } ++ pat = GEN_FCN (icode) (op0, op1); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return NULL_RTX; ++ case AVR32_BUILTIN_SYNC: ++ case AVR32_BUILTIN_MUSFR: ++ case AVR32_BUILTIN_SSRF: ++ case AVR32_BUILTIN_CSRF: ++ { ++ const char *fname; ++ switch (fcode) ++ { ++ default: ++ case AVR32_BUILTIN_SYNC: ++ icode = CODE_FOR_sync; ++ fname = "sync"; ++ break; ++ case AVR32_BUILTIN_MUSFR: ++ icode = CODE_FOR_musfr; ++ fname = "musfr"; ++ break; ++ case AVR32_BUILTIN_SSRF: ++ icode = CODE_FOR_ssrf; ++ fname = "ssrf"; ++ break; ++ case AVR32_BUILTIN_CSRF: ++ icode = CODE_FOR_csrf; ++ fname = "csrf"; ++ break; ++ } + -+ fndecl_attribute_args = args; -+ if (args == NULL_TREE) -+ return NULL_TREE; ++ arg0 = CALL_EXPR_ARG (exp,0); ++ op0 = expand_normal (arg0); ++ mode0 = insn_data[icode].operand[0].mode; + -+ tree value = TREE_VALUE (args); -+ if (TREE_CODE (value) != INTEGER_CST) -+ { -+ warning (OPT_Wattributes, -+ "argument of %qs attribute is not an integer constant", -+ IDENTIFIER_POINTER (name)); -+ *no_add_attrs = true; -+ } ++ if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) ++ { ++ if (icode == CODE_FOR_musfr) ++ op0 = copy_to_mode_reg (mode0, op0); ++ else ++ { ++ error ("Parameter to __builtin_%s is illegal.", fname); ++ return gen_reg_rtx (mode0); ++ } ++ } ++ pat = GEN_FCN (icode) (op0); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return NULL_RTX; ++ } ++ case AVR32_BUILTIN_TLBR: ++ icode = CODE_FOR_tlbr; ++ pat = GEN_FCN (icode) (NULL_RTX); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return NULL_RTX; ++ case AVR32_BUILTIN_TLBS: ++ icode = CODE_FOR_tlbs; ++ pat = GEN_FCN (icode) (NULL_RTX); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return NULL_RTX; ++ case AVR32_BUILTIN_TLBW: ++ icode = CODE_FOR_tlbw; ++ pat = GEN_FCN (icode) (NULL_RTX); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return NULL_RTX; ++ case AVR32_BUILTIN_BREAKPOINT: ++ icode = CODE_FOR_breakpoint; ++ pat = GEN_FCN (icode) (NULL_RTX); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return NULL_RTX; ++ case AVR32_BUILTIN_XCHG: ++ icode = CODE_FOR_sync_lock_test_and_setsi; ++ arg0 = CALL_EXPR_ARG (exp,0); ++ arg1 = CALL_EXPR_ARG (exp,1); ++ op0 = expand_normal (arg0); ++ op1 = expand_normal (arg1); ++ tmode = insn_data[icode].operand[0].mode; ++ mode0 = insn_data[icode].operand[1].mode; ++ mode1 = insn_data[icode].operand[2].mode; + -+ return NULL_TREE; -+} ++ if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) ++ { ++ op1 = copy_to_mode_reg (mode1, op1); ++ } + ++ op0 = force_reg (GET_MODE (op0), op0); ++ op0 = gen_rtx_MEM (GET_MODE (op0), op0); ++ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) ++ { ++ error ++ ("Parameter 1 to __builtin_xchg must be a pointer to an integer."); ++ } + -+/* Handle an acall attribute; -+ arguments as in struct attribute_spec.handler. */ ++ if (target == 0 ++ || GET_MODE (target) != tmode ++ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) ++ target = gen_reg_rtx (tmode); ++ pat = GEN_FCN (icode) (target, op0, op1); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return target; ++ case AVR32_BUILTIN_LDXI: ++ icode = CODE_FOR_ldxi; ++ arg0 = CALL_EXPR_ARG (exp,0); ++ arg1 = CALL_EXPR_ARG (exp,1); ++ arg2 = CALL_EXPR_ARG (exp,2); ++ op0 = expand_normal (arg0); ++ op1 = expand_normal (arg1); ++ op2 = expand_normal (arg2); ++ tmode = insn_data[icode].operand[0].mode; ++ mode0 = insn_data[icode].operand[1].mode; ++ mode1 = insn_data[icode].operand[2].mode; + -+static tree -+avr32_handle_acall_attribute (tree * node, tree name, -+ tree args ATTRIBUTE_UNUSED, -+ int flags ATTRIBUTE_UNUSED, bool * no_add_attrs) -+{ -+ if (TREE_CODE (*node) == FUNCTION_TYPE || TREE_CODE (*node) == METHOD_TYPE) -+ { -+ warning (OPT_Wattributes,"`%s' attribute not yet supported...", -+ IDENTIFIER_POINTER (name)); -+ *no_add_attrs = true; -+ return NULL_TREE; -+ } ++ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) ++ { ++ op0 = copy_to_mode_reg (mode0, op0); ++ } + -+ warning (OPT_Wattributes,"`%s' attribute only applies to functions", -+ IDENTIFIER_POINTER (name)); -+ *no_add_attrs = true; -+ return NULL_TREE; -+} ++ if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) ++ { ++ op1 = copy_to_mode_reg (mode1, op1); ++ } + ++ if (!(*insn_data[icode].operand[3].predicate) (op2, SImode)) ++ { ++ error ++ ("Parameter 3 to __builtin_ldxi must be a valid extract shift operand: (0|8|16|24)"); ++ return gen_reg_rtx (mode0); ++ } + -+bool -+avr32_flashvault_call(tree decl) -+{ -+ tree attributes; -+ tree fv_attribute; -+ tree vector_tree; -+ unsigned int vector; ++ if (target == 0 ++ || GET_MODE (target) != tmode ++ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) ++ target = gen_reg_rtx (tmode); ++ pat = GEN_FCN (icode) (target, op0, op1, op2); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return target; ++ case AVR32_BUILTIN_BSWAP16: ++ { ++ icode = CODE_FOR_bswap_16; ++ arg0 = CALL_EXPR_ARG (exp,0); ++ arg0_mode = TYPE_MODE (TREE_TYPE (arg0)); ++ mode0 = insn_data[icode].operand[1].mode; ++ if (arg0_mode != mode0) ++ arg0 = build1 (NOP_EXPR, ++ (*lang_hooks.types.type_for_mode) (mode0, 0), arg0); + -+ if (decl && TREE_CODE (decl) == FUNCTION_DECL) -+ { -+ attributes = DECL_ATTRIBUTES(decl); -+ fv_attribute = lookup_attribute ("flashvault", attributes); -+ if (fv_attribute != NULL_TREE) -+ { -+ /* Get attribute parameter, for the function vector number. */ -+ /* -+ There is probably an easier, standard way to retrieve the -+ attribute parameter which needs to be done here. -+ */ -+ vector_tree = TREE_VALUE(fv_attribute); -+ if (vector_tree != NULL_TREE) -+ { -+ vector = (unsigned int)TREE_INT_CST_LOW(TREE_VALUE(vector_tree)); -+ fprintf (asm_out_file, -+ "\tmov\tr8, lo(%i)\t# Load vector number for sscall.\n", -+ vector); -+ } ++ op0 = expand_expr (arg0, NULL_RTX, HImode, 0); ++ tmode = insn_data[icode].operand[0].mode; + -+ fprintf (asm_out_file, -+ "\tsscall\t# Secure system call.\n"); + -+ return true; -+ } -+ } -+ -+ return false; -+} ++ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) ++ { ++ if ( CONST_INT_P (op0) ) ++ { ++ HOST_WIDE_INT val = ( ((INTVAL (op0)&0x00ff) << 8) | ++ ((INTVAL (op0)&0xff00) >> 8) ); ++ /* Sign extend 16-bit value to host wide int */ ++ val <<= (HOST_BITS_PER_WIDE_INT - 16); ++ val >>= (HOST_BITS_PER_WIDE_INT - 16); ++ op0 = GEN_INT(val); ++ if (target == 0 ++ || GET_MODE (target) != tmode ++ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) ++ target = gen_reg_rtx (tmode); ++ emit_move_insn(target, op0); ++ return target; ++ } ++ else ++ op0 = copy_to_mode_reg (mode0, op0); ++ } + ++ if (target == 0 ++ || GET_MODE (target) != tmode ++ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) ++ { ++ target = gen_reg_rtx (tmode); ++ } + -+static bool has_attribute_p (tree decl, const char *name) -+{ -+ if (decl && TREE_CODE (decl) == FUNCTION_DECL) -+ { -+ return (lookup_attribute (name, DECL_ATTRIBUTES(decl)) != NULL_TREE); -+ } -+ return NULL_TREE; -+} + ++ pat = GEN_FCN (icode) (target, op0); ++ if (!pat) ++ return 0; ++ emit_insn (pat); + -+/* Return 0 if the attributes for two types are incompatible, 1 if they -+ are compatible, and 2 if they are nearly compatible (which causes a -+ warning to be generated). */ -+static int -+avr32_comp_type_attributes (tree type1, tree type2) -+{ -+ bool acall1, acall2, isr1, isr2, naked1, naked2, fv1, fv2, fvimpl1, fvimpl2; ++ return target; ++ } ++ case AVR32_BUILTIN_BSWAP32: ++ { ++ icode = CODE_FOR_bswap_32; ++ arg0 = CALL_EXPR_ARG (exp,0); ++ op0 = expand_normal (arg0); ++ tmode = insn_data[icode].operand[0].mode; ++ mode0 = insn_data[icode].operand[1].mode; + -+ /* Check for mismatch of non-default calling convention. */ -+ if (TREE_CODE (type1) != FUNCTION_TYPE) -+ return 1; ++ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) ++ { ++ if ( CONST_INT_P (op0) ) ++ { ++ HOST_WIDE_INT val = ( ((INTVAL (op0)&0x000000ff) << 24) | ++ ((INTVAL (op0)&0x0000ff00) << 8) | ++ ((INTVAL (op0)&0x00ff0000) >> 8) | ++ ((INTVAL (op0)&0xff000000) >> 24) ); ++ /* Sign extend 32-bit value to host wide int */ ++ val <<= (HOST_BITS_PER_WIDE_INT - 32); ++ val >>= (HOST_BITS_PER_WIDE_INT - 32); ++ op0 = GEN_INT(val); ++ if (target == 0 ++ || GET_MODE (target) != tmode ++ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) ++ target = gen_reg_rtx (tmode); ++ emit_move_insn(target, op0); ++ return target; ++ } ++ else ++ op0 = copy_to_mode_reg (mode0, op0); ++ } + -+ /* Check for mismatched call attributes. */ -+ acall1 = lookup_attribute ("acall", TYPE_ATTRIBUTES (type1)) != NULL; -+ acall2 = lookup_attribute ("acall", TYPE_ATTRIBUTES (type2)) != NULL; -+ naked1 = lookup_attribute ("naked", TYPE_ATTRIBUTES (type1)) != NULL; -+ naked2 = lookup_attribute ("naked", TYPE_ATTRIBUTES (type2)) != NULL; -+ fv1 = lookup_attribute ("flashvault", TYPE_ATTRIBUTES (type1)) != NULL; -+ fv2 = lookup_attribute ("flashvault", TYPE_ATTRIBUTES (type2)) != NULL; -+ fvimpl1 = lookup_attribute ("flashvault_impl", TYPE_ATTRIBUTES (type1)) != NULL; -+ fvimpl2 = lookup_attribute ("flashvault_impl", TYPE_ATTRIBUTES (type2)) != NULL; -+ isr1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; -+ if (!isr1) -+ isr1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; ++ if (target == 0 ++ || GET_MODE (target) != tmode ++ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) ++ target = gen_reg_rtx (tmode); + -+ isr2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; -+ if (!isr2) -+ isr2 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; + -+ if ((acall1 && isr2) -+ || (acall2 && isr1) -+ || (naked1 && isr2) -+ || (naked2 && isr1) -+ || (fv1 && isr2) -+ || (fv2 && isr1) -+ || (fvimpl1 && isr2) -+ || (fvimpl2 && isr1) -+ || (fv1 && fvimpl2) -+ || (fv2 && fvimpl1) -+ ) -+ return 0; ++ pat = GEN_FCN (icode) (target, op0); ++ if (!pat) ++ return 0; ++ emit_insn (pat); + -+ return 1; -+} ++ return target; ++ } ++ case AVR32_BUILTIN_MVCR_W: ++ case AVR32_BUILTIN_MVCR_D: ++ { ++ arg0 = CALL_EXPR_ARG (exp,0); ++ arg1 = CALL_EXPR_ARG (exp,1); ++ op0 = expand_normal (arg0); ++ op1 = expand_normal (arg1); + ++ if (fcode == AVR32_BUILTIN_MVCR_W) ++ icode = CODE_FOR_mvcrsi; ++ else ++ icode = CODE_FOR_mvcrdi; + -+/* Computes the type of the current function. */ -+static unsigned long -+avr32_compute_func_type (void) -+{ -+ unsigned long type = AVR32_FT_UNKNOWN; -+ tree a; -+ tree attr; ++ tmode = insn_data[icode].operand[0].mode; + -+ if (TREE_CODE (current_function_decl) != FUNCTION_DECL) -+ abort (); ++ if (target == 0 ++ || GET_MODE (target) != tmode ++ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) ++ target = gen_reg_rtx (tmode); + -+ /* Decide if the current function is volatile. Such functions never -+ return, and many memory cycles can be saved by not storing register -+ values that will never be needed again. This optimization was added to -+ speed up context switching in a kernel application. */ -+ if (optimize > 0 -+ && TREE_NOTHROW (current_function_decl) -+ && TREE_THIS_VOLATILE (current_function_decl)) -+ type |= AVR32_FT_VOLATILE; ++ if (!(*insn_data[icode].operand[1].predicate) (op0, SImode)) ++ { ++ error ++ ("Parameter 1 to __builtin_cop is not a valid coprocessor number."); ++ error ("Number should be between 0 and 7."); ++ return NULL_RTX; ++ } + -+ if (cfun->static_chain_decl != NULL) -+ type |= AVR32_FT_NESTED; ++ if (!(*insn_data[icode].operand[2].predicate) (op1, SImode)) ++ { ++ error ++ ("Parameter 2 to __builtin_cop is not a valid coprocessor register number."); ++ error ("Number should be between 0 and 15."); ++ return NULL_RTX; ++ } + -+ attr = DECL_ATTRIBUTES (current_function_decl); ++ pat = GEN_FCN (icode) (target, op0, op1); ++ if (!pat) ++ return 0; ++ emit_insn (pat); + -+ a = lookup_attribute ("isr", attr); -+ if (a == NULL_TREE) -+ a = lookup_attribute ("interrupt", attr); ++ return target; ++ } ++ case AVR32_BUILTIN_MACSATHH_W: ++ case AVR32_BUILTIN_MACWH_D: ++ case AVR32_BUILTIN_MACHH_D: ++ { ++ arg0 = CALL_EXPR_ARG (exp,0); ++ arg1 = CALL_EXPR_ARG (exp,1); ++ arg2 = CALL_EXPR_ARG (exp,2); ++ op0 = expand_normal (arg0); ++ op1 = expand_normal (arg1); ++ op2 = expand_normal (arg2); + -+ if (a == NULL_TREE) -+ type |= AVR32_FT_NORMAL; -+ else -+ type |= avr32_isr_value (TREE_VALUE (a)); ++ icode = ((fcode == AVR32_BUILTIN_MACSATHH_W) ? CODE_FOR_macsathh_w : ++ (fcode == AVR32_BUILTIN_MACWH_D) ? CODE_FOR_macwh_d : ++ CODE_FOR_machh_d); + ++ tmode = insn_data[icode].operand[0].mode; ++ mode0 = insn_data[icode].operand[1].mode; ++ mode1 = insn_data[icode].operand[2].mode; + -+ a = lookup_attribute ("acall", attr); -+ if (a != NULL_TREE) -+ type |= AVR32_FT_ACALL; + -+ a = lookup_attribute ("naked", attr); -+ if (a != NULL_TREE) -+ type |= AVR32_FT_NAKED; ++ if (!target ++ || GET_MODE (target) != tmode ++ || !(*insn_data[icode].operand[0].predicate) (target, tmode)) ++ target = gen_reg_rtx (tmode); + -+ a = lookup_attribute ("flashvault", attr); -+ if (a != NULL_TREE) -+ type |= AVR32_FT_FLASHVAULT; ++ if (!(*insn_data[icode].operand[0].predicate) (op0, tmode)) ++ { ++ /* If op0 is already a reg we must cast it to the correct mode. */ ++ if (REG_P (op0)) ++ op0 = convert_to_mode (tmode, op0, 1); ++ else ++ op0 = copy_to_mode_reg (tmode, op0); ++ } + -+ a = lookup_attribute ("flashvault_impl", attr); -+ if (a != NULL_TREE) -+ type |= AVR32_FT_FLASHVAULT_IMPL; ++ if (!(*insn_data[icode].operand[1].predicate) (op1, mode0)) ++ { ++ /* If op1 is already a reg we must cast it to the correct mode. */ ++ if (REG_P (op1)) ++ op1 = convert_to_mode (mode0, op1, 1); ++ else ++ op1 = copy_to_mode_reg (mode0, op1); ++ } + -+ return type; -+} ++ if (!(*insn_data[icode].operand[2].predicate) (op2, mode1)) ++ { ++ /* If op1 is already a reg we must cast it to the correct mode. */ ++ if (REG_P (op2)) ++ op2 = convert_to_mode (mode1, op2, 1); ++ else ++ op2 = copy_to_mode_reg (mode1, op2); ++ } + ++ emit_move_insn (target, op0); + -+/* Returns the type of the current function. */ -+static unsigned long -+avr32_current_func_type (void) -+{ -+ if (AVR32_FUNC_TYPE (cfun->machine->func_type) == AVR32_FT_UNKNOWN) -+ cfun->machine->func_type = avr32_compute_func_type (); ++ pat = GEN_FCN (icode) (target, op1, op2); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return target; ++ } ++ case AVR32_BUILTIN_MVRC_W: ++ case AVR32_BUILTIN_MVRC_D: ++ { ++ arg0 = CALL_EXPR_ARG (exp,0); ++ arg1 = CALL_EXPR_ARG (exp,1); ++ arg2 = CALL_EXPR_ARG (exp,2); ++ op0 = expand_normal (arg0); ++ op1 = expand_normal (arg1); ++ op2 = expand_normal (arg2); + -+ return cfun->machine->func_type; -+} ++ if (fcode == AVR32_BUILTIN_MVRC_W) ++ icode = CODE_FOR_mvrcsi; ++ else ++ icode = CODE_FOR_mvrcdi; + ++ if (!(*insn_data[icode].operand[0].predicate) (op0, SImode)) ++ { ++ error ("Parameter 1 is not a valid coprocessor number."); ++ error ("Number should be between 0 and 7."); ++ return NULL_RTX; ++ } + -+/* -+This target hook should return true if we should not pass type solely -+in registers. The file expr.h defines a definition that is usually appropriate, -+refer to expr.h for additional documentation. -+*/ -+bool -+avr32_must_pass_in_stack (enum machine_mode mode ATTRIBUTE_UNUSED, tree type) -+{ -+ if (type && AGGREGATE_TYPE_P (type) -+ /* If the alignment is less than the size then pass in the struct on -+ the stack. */ -+ && ((unsigned int) TYPE_ALIGN_UNIT (type) < -+ (unsigned int) int_size_in_bytes (type)) -+ /* If we support unaligned word accesses then structs of size 4 and 8 -+ can have any alignment and still be passed in registers. */ -+ && !(TARGET_UNALIGNED_WORD -+ && (int_size_in_bytes (type) == 4 -+ || int_size_in_bytes (type) == 8)) -+ /* Double word structs need only a word alignment. */ -+ && !(int_size_in_bytes (type) == 8 && TYPE_ALIGN_UNIT (type) >= 4)) -+ return true; ++ if (!(*insn_data[icode].operand[1].predicate) (op1, SImode)) ++ { ++ error ("Parameter 2 is not a valid coprocessor register number."); ++ error ("Number should be between 0 and 15."); ++ return NULL_RTX; ++ } + -+ if (type && AGGREGATE_TYPE_P (type) -+ /* Structs of size 3,5,6,7 are always passed in registers. */ -+ && (int_size_in_bytes (type) == 3 -+ || int_size_in_bytes (type) == 5 -+ || int_size_in_bytes (type) == 6 || int_size_in_bytes (type) == 7)) -+ return true; ++ if (GET_CODE (op2) == CONST_INT ++ || GET_CODE (op2) == CONST ++ || GET_CODE (op2) == SYMBOL_REF || GET_CODE (op2) == LABEL_REF) ++ { ++ op2 = force_const_mem (insn_data[icode].operand[2].mode, op2); ++ } + ++ if (!(*insn_data[icode].operand[2].predicate) (op2, GET_MODE (op2))) ++ op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); + -+ return (type && TREE_ADDRESSABLE (type)); -+} + ++ pat = GEN_FCN (icode) (op0, op1, op2); ++ if (!pat) ++ return 0; ++ emit_insn (pat); + -+bool -+avr32_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED) -+{ -+ return true; -+} ++ return NULL_RTX; ++ } ++ case AVR32_BUILTIN_COP: ++ { ++ rtx op3, op4; ++ tree arg3, arg4; ++ icode = CODE_FOR_cop; ++ arg0 = CALL_EXPR_ARG (exp,0); ++ arg1 = CALL_EXPR_ARG (exp,1); ++ arg2 = CALL_EXPR_ARG (exp,2); ++ arg3 = CALL_EXPR_ARG (exp,3); ++ arg4 = CALL_EXPR_ARG (exp,4); ++ op0 = expand_normal (arg0); ++ op1 = expand_normal (arg1); ++ op2 = expand_normal (arg2); ++ op3 = expand_normal (arg3); ++ op4 = expand_normal (arg4); + ++ if (!(*insn_data[icode].operand[0].predicate) (op0, SImode)) ++ { ++ error ++ ("Parameter 1 to __builtin_cop is not a valid coprocessor number."); ++ error ("Number should be between 0 and 7."); ++ return NULL_RTX; ++ } + -+/* -+ This target hook should return true if an argument at the position indicated -+ by cum should be passed by reference. This predicate is queried after target -+ independent reasons for being passed by reference, such as TREE_ADDRESSABLE (type). ++ if (!(*insn_data[icode].operand[1].predicate) (op1, SImode)) ++ { ++ error ++ ("Parameter 2 to __builtin_cop is not a valid coprocessor register number."); ++ error ("Number should be between 0 and 15."); ++ return NULL_RTX; ++ } + -+ If the hook returns true, a copy of that argument is made in memory and a -+ pointer to the argument is passed instead of the argument itself. The pointer -+ is passed in whatever way is appropriate for passing a pointer to that type. -+*/ -+bool -+avr32_pass_by_reference (CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED, -+ enum machine_mode mode ATTRIBUTE_UNUSED, -+ tree type, bool named ATTRIBUTE_UNUSED) -+{ -+ return (type && (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)); -+} ++ if (!(*insn_data[icode].operand[2].predicate) (op2, SImode)) ++ { ++ error ++ ("Parameter 3 to __builtin_cop is not a valid coprocessor register number."); ++ error ("Number should be between 0 and 15."); ++ return NULL_RTX; ++ } + ++ if (!(*insn_data[icode].operand[3].predicate) (op3, SImode)) ++ { ++ error ++ ("Parameter 4 to __builtin_cop is not a valid coprocessor register number."); ++ error ("Number should be between 0 and 15."); ++ return NULL_RTX; ++ } + -+static int -+avr32_arg_partial_bytes (CUMULATIVE_ARGS * pcum ATTRIBUTE_UNUSED, -+ enum machine_mode mode ATTRIBUTE_UNUSED, -+ tree type ATTRIBUTE_UNUSED, -+ bool named ATTRIBUTE_UNUSED) -+{ -+ return 0; -+} ++ if (!(*insn_data[icode].operand[4].predicate) (op4, SImode)) ++ { ++ error ++ ("Parameter 5 to __builtin_cop is not a valid coprocessor operation."); ++ error ("Number should be between 0 and 127."); ++ return NULL_RTX; ++ } + ++ pat = GEN_FCN (icode) (op0, op1, op2, op3, op4); ++ if (!pat) ++ return 0; ++ emit_insn (pat); + -+struct gcc_target targetm = TARGET_INITIALIZER; ++ return target; ++ } + -+/* -+ Table used to convert from register number in the assembler instructions and -+ the register numbers used in gcc. -+*/ -+const int avr32_function_arg_reglist[] = { -+ INTERNAL_REGNUM (12), -+ INTERNAL_REGNUM (11), -+ INTERNAL_REGNUM (10), -+ INTERNAL_REGNUM (9), -+ INTERNAL_REGNUM (8) -+}; ++ case AVR32_BUILTIN_MEMS: ++ case AVR32_BUILTIN_MEMC: ++ case AVR32_BUILTIN_MEMT: ++ { ++ if (!TARGET_RMW) ++ error ("Trying to use __builtin_mem(s/c/t) when target does not support RMW insns."); ++ ++ switch (fcode) { ++ case AVR32_BUILTIN_MEMS: ++ icode = CODE_FOR_iorsi3; ++ break; ++ case AVR32_BUILTIN_MEMC: ++ icode = CODE_FOR_andsi3; ++ break; ++ case AVR32_BUILTIN_MEMT: ++ icode = CODE_FOR_xorsi3; ++ break; ++ } ++ arg0 = CALL_EXPR_ARG (exp,0); ++ arg1 = CALL_EXPR_ARG (exp,1); ++ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); ++ if ( GET_CODE (op0) == SYMBOL_REF ) ++ // This symbol must be RMW addressable ++ SYMBOL_REF_FLAGS (op0) |= (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT); ++ op0 = gen_rtx_MEM(SImode, op0); ++ op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); ++ mode0 = insn_data[icode].operand[1].mode; ++ ++ ++ if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) ++ { ++ error ("Parameter 1 to __builtin_mem(s/c/t) must be a Ks15<<2 address or a rmw addressable symbol."); ++ } ++ ++ if ( !CONST_INT_P (op1) ++ || INTVAL (op1) > 31 ++ || INTVAL (op1) < 0 ) ++ error ("Parameter 2 to __builtin_mem(s/c/t) must be a constant between 0 and 31."); ++ ++ if ( fcode == AVR32_BUILTIN_MEMC ) ++ op1 = GEN_INT((~(1 << INTVAL(op1)))&0xffffffff); ++ else ++ op1 = GEN_INT((1 << INTVAL(op1))&0xffffffff); ++ pat = GEN_FCN (icode) (op0, op0, op1); ++ if (!pat) ++ return 0; ++ emit_insn (pat); ++ return op0; ++ } ++ ++ case AVR32_BUILTIN_SLEEP: ++ { ++ arg0 = CALL_EXPR_ARG (exp, 0); ++ op0 = expand_normal (arg0); ++ int intval = INTVAL(op0); ++ ++ /* Check if the argument if integer and if the value of integer ++ is greater than 0. */ ++ ++ if (!CONSTANT_P (op0)) ++ error ("Parameter 1 to __builtin_sleep() is not a valid integer."); ++ if (intval < 0 ) ++ error ("Parameter 1 to __builtin_sleep() should be an integer greater than 0."); ++ ++ int strncmpval = strncmp (avr32_part_name,"uc3l", 4); ++ ++ /* Check if op0 is less than 7 for uc3l* and less than 6 for other ++ devices. By this check we are avoiding if operand is less than ++ 256. For more devices, add more such checks. */ ++ ++ if ( strncmpval == 0 && intval >= 7) ++ error ("Parameter 1 to __builtin_sleep() should be less than or equal to 7."); ++ else if ( strncmp != 0 && intval >= 6) ++ error ("Parameter 1 to __builtin_sleep() should be less than or equal to 6."); ++ ++ emit_insn (gen_sleep(op0)); ++ return target; ++ ++ } ++ case AVR32_BUILTIN_DELAY_CYCLES: ++ { ++ arg0 = CALL_EXPR_ARG (exp, 0); ++ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); ++ ++ if (TARGET_ARCH_AP) ++ error (" __builtin_avr32_delay_cycles() not supported for \'%s\' architecture.", avr32_arch_name); ++ if (!CONSTANT_P (op0)) ++ error ("Parameter 1 to __builtin_avr32_delay_cycles() should be an integer."); ++ emit_insn (gen_delay_cycles (op0)); ++ return 0; ++ ++ } + ++ } + -+rtx avr32_compare_op0 = NULL_RTX; -+rtx avr32_compare_op1 = NULL_RTX; -+rtx avr32_compare_operator = NULL_RTX; -+rtx avr32_acc_cache = NULL_RTX; -+/* type of branch to use */ -+enum avr32_cmp_type avr32_branch_type; ++ for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) ++ if (d->code == fcode) ++ return avr32_expand_binop_builtin (d->icode, exp, target); + + -+/* -+ Returns nonzero if it is allowed to store a value of mode mode in hard -+ register number regno. -+*/ -+int -+avr32_hard_regno_mode_ok (int regnr, enum machine_mode mode) ++ /* @@@ Should really do something sensible here. */ ++ return NULL_RTX; ++} ++ ++ ++/* Handle an "interrupt" or "isr" attribute; ++ arguments as in struct attribute_spec.handler. */ ++static tree ++avr32_handle_isr_attribute (tree * node, tree name, tree args, ++ int flags, bool * no_add_attrs) +{ -+ switch (mode) ++ if (DECL_P (*node)) + { -+ case DImode: /* long long */ -+ case DFmode: /* double */ -+ case SCmode: /* __complex__ float */ -+ case CSImode: /* __complex__ int */ -+ if (regnr < 4) -+ { /* long long int not supported in r12, sp, lr or pc. */ -+ return 0; -+ } -+ else -+ { -+ /* long long int has to be referred in even registers. */ -+ if (regnr % 2) -+ return 0; -+ else -+ return 1; -+ } -+ case CDImode: /* __complex__ long long */ -+ case DCmode: /* __complex__ double */ -+ case TImode: /* 16 bytes */ -+ if (regnr < 7) -+ return 0; -+ else if (regnr % 2) -+ return 0; -+ else -+ return 1; -+ default: -+ return 1; ++ if (TREE_CODE (*node) != FUNCTION_DECL) ++ { ++ warning (OPT_Wattributes,"`%s' attribute only applies to functions", ++ IDENTIFIER_POINTER (name)); ++ *no_add_attrs = true; ++ } ++ /* FIXME: the argument if any is checked for type attributes; should it ++ be checked for decl ones? */ ++ } ++ else ++ { ++ if (TREE_CODE (*node) == FUNCTION_TYPE ++ || TREE_CODE (*node) == METHOD_TYPE) ++ { ++ if (avr32_isr_value (args) == AVR32_FT_UNKNOWN) ++ { ++ warning (OPT_Wattributes,"`%s' attribute ignored", IDENTIFIER_POINTER (name)); ++ *no_add_attrs = true; ++ } ++ } ++ else if (TREE_CODE (*node) == POINTER_TYPE ++ && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE ++ || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) ++ && avr32_isr_value (args) != AVR32_FT_UNKNOWN) ++ { ++ *node = build_variant_type_copy (*node); ++ TREE_TYPE (*node) = build_type_attribute_variant ++ (TREE_TYPE (*node), ++ tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); ++ *no_add_attrs = true; ++ } ++ else ++ { ++ /* Possibly pass this attribute on from the type to a decl. */ ++ if (flags & ((int) ATTR_FLAG_DECL_NEXT ++ | (int) ATTR_FLAG_FUNCTION_NEXT ++ | (int) ATTR_FLAG_ARRAY_NEXT)) ++ { ++ *no_add_attrs = true; ++ return tree_cons (name, args, NULL_TREE); ++ } ++ else ++ { ++ warning (OPT_Wattributes,"`%s' attribute ignored", IDENTIFIER_POINTER (name)); ++ } ++ } + } ++ ++ return NULL_TREE; +} + + -+int -+avr32_rnd_operands (rtx add, rtx shift) ++/* Handle an attribute requiring a FUNCTION_DECL; ++ arguments as in struct attribute_spec.handler. */ ++static tree ++avr32_handle_fndecl_attribute (tree * node, tree name, ++ tree args, ++ int flags ATTRIBUTE_UNUSED, ++ bool * no_add_attrs) +{ -+ if (GET_CODE (shift) == CONST_INT && -+ GET_CODE (add) == CONST_INT && INTVAL (shift) > 0) ++ if (TREE_CODE (*node) != FUNCTION_DECL) + { -+ if ((1 << (INTVAL (shift) - 1)) == INTVAL (add)) -+ return TRUE; ++ warning (OPT_Wattributes,"%qs attribute only applies to functions", ++ IDENTIFIER_POINTER (name)); ++ *no_add_attrs = true; ++ return NULL_TREE; + } + -+ return FALSE; ++ fndecl_attribute_args = args; ++ if (args == NULL_TREE) ++ return NULL_TREE; ++ ++ tree value = TREE_VALUE (args); ++ if (TREE_CODE (value) != INTEGER_CST) ++ { ++ warning (OPT_Wattributes, ++ "argument of %qs attribute is not an integer constant", ++ IDENTIFIER_POINTER (name)); ++ *no_add_attrs = true; ++ } ++ ++ return NULL_TREE; +} + + -+int -+avr32_const_ok_for_constraint_p (HOST_WIDE_INT value, char c, const char *str) ++/* Handle an acall attribute; ++ arguments as in struct attribute_spec.handler. */ ++ ++static tree ++avr32_handle_acall_attribute (tree * node, tree name, ++ tree args ATTRIBUTE_UNUSED, ++ int flags ATTRIBUTE_UNUSED, bool * no_add_attrs) +{ -+ switch (c) ++ if (TREE_CODE (*node) == FUNCTION_TYPE || TREE_CODE (*node) == METHOD_TYPE) + { -+ case 'K': -+ case 'I': -+ { -+ HOST_WIDE_INT min_value = 0, max_value = 0; -+ char size_str[3]; -+ int const_size; ++ warning (OPT_Wattributes,"`%s' attribute not yet supported...", ++ IDENTIFIER_POINTER (name)); ++ *no_add_attrs = true; ++ return NULL_TREE; ++ } + -+ size_str[0] = str[2]; -+ size_str[1] = str[3]; -+ size_str[2] = '\0'; -+ const_size = atoi (size_str); ++ warning (OPT_Wattributes,"`%s' attribute only applies to functions", ++ IDENTIFIER_POINTER (name)); ++ *no_add_attrs = true; ++ return NULL_TREE; ++} + -+ if (TOUPPER (str[1]) == 'U') -+ { -+ min_value = 0; -+ max_value = (1 << const_size) - 1; -+ } -+ else if (TOUPPER (str[1]) == 'S') -+ { -+ min_value = -(1 << (const_size - 1)); -+ max_value = (1 << (const_size - 1)) - 1; -+ } + -+ if (c == 'I') -+ { -+ value = -value; -+ } ++bool ++avr32_flashvault_call(tree decl) ++{ ++ tree attributes; ++ tree fv_attribute; ++ tree vector_tree; ++ unsigned int vector; + -+ if (value >= min_value && value <= max_value) -+ { -+ return 1; -+ } -+ break; -+ } -+ case 'M': -+ return avr32_mask_upper_bits_operand (GEN_INT (value), VOIDmode); -+ case 'J': -+ return avr32_hi16_immediate_operand (GEN_INT (value), VOIDmode); -+ case 'O': -+ return one_bit_set_operand (GEN_INT (value), VOIDmode); -+ case 'N': -+ return one_bit_cleared_operand (GEN_INT (value), VOIDmode); -+ case 'L': -+ /* The lower 16-bits are set. */ -+ return ((value & 0xffff) == 0xffff) ; ++ if (decl && TREE_CODE (decl) == FUNCTION_DECL) ++ { ++ attributes = DECL_ATTRIBUTES(decl); ++ fv_attribute = lookup_attribute ("flashvault", attributes); ++ if (fv_attribute != NULL_TREE) ++ { ++ /* Get attribute parameter, for the function vector number. */ ++ /* ++ There is probably an easier, standard way to retrieve the ++ attribute parameter which needs to be done here. ++ */ ++ vector_tree = TREE_VALUE(fv_attribute); ++ if (vector_tree != NULL_TREE) ++ { ++ vector = (unsigned int)TREE_INT_CST_LOW(TREE_VALUE(vector_tree)); ++ fprintf (asm_out_file, ++ "\tmov\tr8, lo(%i)\t# Load vector number for sscall.\n", ++ vector); ++ } ++ ++ fprintf (asm_out_file, ++ "\tsscall\t# Secure system call.\n"); ++ ++ return true; ++ } + } ++ ++ return false; ++} + -+ return 0; ++ ++static bool has_attribute_p (tree decl, const char *name) ++{ ++ if (decl && TREE_CODE (decl) == FUNCTION_DECL) ++ { ++ return (lookup_attribute (name, DECL_ATTRIBUTES(decl)) != NULL_TREE); ++ } ++ return NULL_TREE; +} + + -+/* Compute mask of registers which needs saving upon function entry. */ -+static unsigned long -+avr32_compute_save_reg_mask (int push) ++/* Return 0 if the attributes for two types are incompatible, 1 if they ++ are compatible, and 2 if they are nearly compatible (which causes a ++ warning to be generated). */ ++static int ++avr32_comp_type_attributes (tree type1, tree type2) +{ -+ unsigned long func_type; -+ unsigned int save_reg_mask = 0; -+ unsigned int reg; ++ bool acall1, acall2, isr1, isr2, naked1, naked2, fv1, fv2, fvimpl1, fvimpl2; + -+ func_type = avr32_current_func_type (); ++ /* Check for mismatch of non-default calling convention. */ ++ if (TREE_CODE (type1) != FUNCTION_TYPE) ++ return 1; + -+ if (IS_INTERRUPT (func_type)) -+ { -+ unsigned int max_reg = 12; ++ /* Check for mismatched call attributes. */ ++ acall1 = lookup_attribute ("acall", TYPE_ATTRIBUTES (type1)) != NULL; ++ acall2 = lookup_attribute ("acall", TYPE_ATTRIBUTES (type2)) != NULL; ++ naked1 = lookup_attribute ("naked", TYPE_ATTRIBUTES (type1)) != NULL; ++ naked2 = lookup_attribute ("naked", TYPE_ATTRIBUTES (type2)) != NULL; ++ fv1 = lookup_attribute ("flashvault", TYPE_ATTRIBUTES (type1)) != NULL; ++ fv2 = lookup_attribute ("flashvault", TYPE_ATTRIBUTES (type2)) != NULL; ++ fvimpl1 = lookup_attribute ("flashvault_impl", TYPE_ATTRIBUTES (type1)) != NULL; ++ fvimpl2 = lookup_attribute ("flashvault_impl", TYPE_ATTRIBUTES (type2)) != NULL; ++ isr1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; ++ if (!isr1) ++ isr1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; + -+ /* Get the banking scheme for the interrupt */ -+ switch (func_type) -+ { -+ case AVR32_FT_ISR_FULL: -+ max_reg = 0; -+ break; -+ case AVR32_FT_ISR_HALF: -+ max_reg = 7; -+ break; -+ case AVR32_FT_ISR_NONE: -+ max_reg = 12; -+ break; -+ } ++ isr2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; ++ if (!isr2) ++ isr2 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; + -+ /* Interrupt functions must not corrupt any registers, even call -+ clobbered ones. If this is a leaf function we can just examine the -+ registers used by the RTL, but otherwise we have to assume that -+ whatever function is called might clobber anything, and so we have -+ to save all the call-clobbered registers as well. */ ++ if ((acall1 && isr2) ++ || (acall2 && isr1) ++ || (naked1 && isr2) ++ || (naked2 && isr1) ++ || (fv1 && isr2) ++ || (fv2 && isr1) ++ || (fvimpl1 && isr2) ++ || (fvimpl2 && isr1) ++ || (fv1 && fvimpl2) ++ || (fv2 && fvimpl1) ++ ) ++ return 0; + -+ /* Need not push the registers r8-r12 for AVR32A architectures, as this -+ is automatially done in hardware. We also do not have any shadow -+ registers. */ -+ if (TARGET_UARCH_AVR32A) -+ { -+ max_reg = 7; -+ func_type = AVR32_FT_ISR_NONE; -+ } ++ return 1; ++} + -+ /* All registers which are used and are not shadowed must be saved. */ -+ for (reg = 0; reg <= max_reg; reg++) -+ if (df_regs_ever_live_p (INTERNAL_REGNUM (reg)) -+ || (!current_function_is_leaf -+ && call_used_regs[INTERNAL_REGNUM (reg)])) -+ save_reg_mask |= (1 << reg); + -+ /* Check LR */ -+ if ((df_regs_ever_live_p (LR_REGNUM) -+ || !current_function_is_leaf || frame_pointer_needed) -+ /* Only non-shadowed register models */ -+ && (func_type == AVR32_FT_ISR_NONE)) -+ save_reg_mask |= (1 << ASM_REGNUM (LR_REGNUM)); ++/* Computes the type of the current function. */ ++static unsigned long ++avr32_compute_func_type (void) ++{ ++ unsigned long type = AVR32_FT_UNKNOWN; ++ tree a; ++ tree attr; + -+ /* Make sure that the GOT register is pushed. */ -+ if (max_reg >= ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM) -+ && crtl->uses_pic_offset_table) -+ save_reg_mask |= (1 << ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM)); ++ if (TREE_CODE (current_function_decl) != FUNCTION_DECL) ++ abort (); + -+ } ++ /* Decide if the current function is volatile. Such functions never ++ return, and many memory cycles can be saved by not storing register ++ values that will never be needed again. This optimization was added to ++ speed up context switching in a kernel application. */ ++ if (optimize > 0 ++ && TREE_NOTHROW (current_function_decl) ++ && TREE_THIS_VOLATILE (current_function_decl)) ++ type |= AVR32_FT_VOLATILE; ++ ++ if (cfun->static_chain_decl != NULL) ++ type |= AVR32_FT_NESTED; ++ ++ attr = DECL_ATTRIBUTES (current_function_decl); ++ ++ a = lookup_attribute ("isr", attr); ++ if (a == NULL_TREE) ++ a = lookup_attribute ("interrupt", attr); ++ ++ if (a == NULL_TREE) ++ type |= AVR32_FT_NORMAL; + else -+ { -+ int use_pushm = optimize_size; ++ type |= avr32_isr_value (TREE_VALUE (a)); + -+ /* In the normal case we only need to save those registers which are -+ call saved and which are used by this function. */ -+ for (reg = 0; reg <= 7; reg++) -+ if (df_regs_ever_live_p (INTERNAL_REGNUM (reg)) -+ && !call_used_regs[INTERNAL_REGNUM (reg)]) -+ save_reg_mask |= (1 << reg); + -+ /* Make sure that the GOT register is pushed. */ -+ if (crtl->uses_pic_offset_table) -+ save_reg_mask |= (1 << ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM)); ++ a = lookup_attribute ("acall", attr); ++ if (a != NULL_TREE) ++ type |= AVR32_FT_ACALL; + ++ a = lookup_attribute ("naked", attr); ++ if (a != NULL_TREE) ++ type |= AVR32_FT_NAKED; + -+ /* If we optimize for size and do not have anonymous arguments: use -+ pushm/popm always. */ -+ if (use_pushm) -+ { -+ if ((save_reg_mask & (1 << 0)) -+ || (save_reg_mask & (1 << 1)) -+ || (save_reg_mask & (1 << 2)) || (save_reg_mask & (1 << 3))) -+ save_reg_mask |= 0xf; ++ a = lookup_attribute ("flashvault", attr); ++ if (a != NULL_TREE) ++ type |= AVR32_FT_FLASHVAULT; + -+ if ((save_reg_mask & (1 << 4)) -+ || (save_reg_mask & (1 << 5)) -+ || (save_reg_mask & (1 << 6)) || (save_reg_mask & (1 << 7))) -+ save_reg_mask |= 0xf0; ++ a = lookup_attribute ("flashvault_impl", attr); ++ if (a != NULL_TREE) ++ type |= AVR32_FT_FLASHVAULT_IMPL; + -+ if ((save_reg_mask & (1 << 8)) || (save_reg_mask & (1 << 9))) -+ save_reg_mask |= 0x300; -+ } ++ return type; ++} + + -+ /* Check LR */ -+ if ((df_regs_ever_live_p (LR_REGNUM) -+ || !current_function_is_leaf -+ || (optimize_size -+ && save_reg_mask -+ && !crtl->calls_eh_return) -+ || frame_pointer_needed) -+ && !IS_FLASHVAULT (func_type)) -+ { -+ if (push -+ /* Never pop LR into PC for functions which -+ calls __builtin_eh_return, since we need to -+ fix the SP after the restoring of the registers -+ and before returning. */ -+ || crtl->calls_eh_return) -+ { -+ /* Push/Pop LR */ -+ save_reg_mask |= (1 << ASM_REGNUM (LR_REGNUM)); -+ } -+ else -+ { -+ /* Pop PC */ -+ save_reg_mask |= (1 << ASM_REGNUM (PC_REGNUM)); -+ } -+ } -+ } -+ -+ -+ /* Save registers so the exception handler can modify them. */ -+ if (crtl->calls_eh_return) -+ { -+ unsigned int i; -+ -+ for (i = 0;; i++) -+ { -+ reg = EH_RETURN_DATA_REGNO (i); -+ if (reg == INVALID_REGNUM) -+ break; -+ save_reg_mask |= 1 << ASM_REGNUM (reg); -+ } -+ } ++/* Returns the type of the current function. */ ++static unsigned long ++avr32_current_func_type (void) ++{ ++ if (AVR32_FUNC_TYPE (cfun->machine->func_type) == AVR32_FT_UNKNOWN) ++ cfun->machine->func_type = avr32_compute_func_type (); + -+ return save_reg_mask; ++ return cfun->machine->func_type; +} + + -+/* Compute total size in bytes of all saved registers. */ -+static int -+avr32_get_reg_mask_size (int reg_mask) ++/* ++This target hook should return true if we should not pass type solely ++in registers. The file expr.h defines a definition that is usually appropriate, ++refer to expr.h for additional documentation. ++*/ ++bool ++avr32_must_pass_in_stack (enum machine_mode mode ATTRIBUTE_UNUSED, tree type) +{ -+ int reg, size; -+ size = 0; ++ if (type && AGGREGATE_TYPE_P (type) ++ /* If the alignment is less than the size then pass in the struct on ++ the stack. */ ++ && ((unsigned int) TYPE_ALIGN_UNIT (type) < ++ (unsigned int) int_size_in_bytes (type)) ++ /* If we support unaligned word accesses then structs of size 4 and 8 ++ can have any alignment and still be passed in registers. */ ++ && !(TARGET_UNALIGNED_WORD ++ && (int_size_in_bytes (type) == 4 ++ || int_size_in_bytes (type) == 8)) ++ /* Double word structs need only a word alignment. */ ++ && !(int_size_in_bytes (type) == 8 && TYPE_ALIGN_UNIT (type) >= 4)) ++ return true; + -+ for (reg = 0; reg <= 15; reg++) -+ if (reg_mask & (1 << reg)) -+ size += 4; ++ if (type && AGGREGATE_TYPE_P (type) ++ /* Structs of size 3,5,6,7 are always passed in registers. */ ++ && (int_size_in_bytes (type) == 3 ++ || int_size_in_bytes (type) == 5 ++ || int_size_in_bytes (type) == 6 || int_size_in_bytes (type) == 7)) ++ return true; + -+ return size; ++ ++ return (type && TREE_ADDRESSABLE (type)); +} + + -+/* Get a register from one of the registers which are saved onto the stack -+ upon function entry. */ -+static int -+avr32_get_saved_reg (int save_reg_mask) ++bool ++avr32_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED) +{ -+ unsigned int reg; -+ -+ /* Find the first register which is saved in the saved_reg_mask */ -+ for (reg = 0; reg <= 15; reg++) -+ if (save_reg_mask & (1 << reg)) -+ return reg; -+ -+ return -1; ++ return true; +} + + -+/* Return 1 if it is possible to return using a single instruction. */ -+int -+avr32_use_return_insn (int iscond) -+{ -+ unsigned int func_type = avr32_current_func_type (); -+ unsigned long saved_int_regs; -+ -+ /* Never use a return instruction before reload has run. */ -+ if (!reload_completed) -+ return 0; ++/* ++ This target hook should return true if an argument at the position indicated ++ by cum should be passed by reference. This predicate is queried after target ++ independent reasons for being passed by reference, such as TREE_ADDRESSABLE (type). + -+ /* Must adjust the stack for vararg functions. */ -+ if (crtl->args.info.uses_anonymous_args) -+ return 0; ++ If the hook returns true, a copy of that argument is made in memory and a ++ pointer to the argument is passed instead of the argument itself. The pointer ++ is passed in whatever way is appropriate for passing a pointer to that type. ++*/ ++bool ++avr32_pass_by_reference (CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED, ++ enum machine_mode mode ATTRIBUTE_UNUSED, ++ tree type, bool named ATTRIBUTE_UNUSED) ++{ ++ return (type && (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)); ++} + -+ /* If there a stack adjstment. */ -+ if (get_frame_size ()) -+ return 0; + -+ saved_int_regs = avr32_compute_save_reg_mask (TRUE); ++static int ++avr32_arg_partial_bytes (CUMULATIVE_ARGS * pcum ATTRIBUTE_UNUSED, ++ enum machine_mode mode ATTRIBUTE_UNUSED, ++ tree type ATTRIBUTE_UNUSED, ++ bool named ATTRIBUTE_UNUSED) ++{ ++ return 0; ++} + -+ /* Conditional returns can not be performed in one instruction if we need -+ to restore registers from the stack */ -+ if (iscond && saved_int_regs) -+ return 0; + -+ /* Conditional return can not be used for interrupt handlers. */ -+ if (iscond && IS_INTERRUPT (func_type)) -+ return 0; ++struct gcc_target targetm = TARGET_INITIALIZER; + -+ /* For interrupt handlers which needs to pop registers */ -+ if (saved_int_regs && IS_INTERRUPT (func_type)) -+ return 0; ++/* ++ Table used to convert from register number in the assembler instructions and ++ the register numbers used in gcc. ++*/ ++const int avr32_function_arg_reglist[] = { ++ INTERNAL_REGNUM (12), ++ INTERNAL_REGNUM (11), ++ INTERNAL_REGNUM (10), ++ INTERNAL_REGNUM (9), ++ INTERNAL_REGNUM (8) ++}; + + -+ /* If there are saved registers but the LR isn't saved, then we need two -+ instructions for the return. */ -+ if (saved_int_regs && !(saved_int_regs & (1 << ASM_REGNUM (LR_REGNUM)))) -+ return 0; ++rtx avr32_compare_op0 = NULL_RTX; ++rtx avr32_compare_op1 = NULL_RTX; ++rtx avr32_compare_operator = NULL_RTX; ++rtx avr32_acc_cache = NULL_RTX; ++/* type of branch to use */ ++enum avr32_cmp_type avr32_branch_type; + + -+ return 1; ++/* ++ Returns nonzero if it is allowed to store a value of mode mode in hard ++ register number regno. ++*/ ++int ++avr32_hard_regno_mode_ok (int regnr, enum machine_mode mode) ++{ ++ switch (mode) ++ { ++ case DImode: /* long long */ ++ case DFmode: /* double */ ++ case SCmode: /* __complex__ float */ ++ case CSImode: /* __complex__ int */ ++ if (regnr < 4) ++ { /* long long int not supported in r12, sp, lr or pc. */ ++ return 0; ++ } ++ else ++ { ++ /* long long int has to be referred in even registers. */ ++ if (regnr % 2) ++ return 0; ++ else ++ return 1; ++ } ++ case CDImode: /* __complex__ long long */ ++ case DCmode: /* __complex__ double */ ++ case TImode: /* 16 bytes */ ++ if (regnr < 7) ++ return 0; ++ else if (regnr % 2) ++ return 0; ++ else ++ return 1; ++ default: ++ return 1; ++ } +} + + -+/* Generate some function prologue info in the assembly file. */ -+void -+avr32_target_asm_function_prologue (FILE * f, HOST_WIDE_INT frame_size) ++int ++avr32_rnd_operands (rtx add, rtx shift) +{ -+ unsigned long func_type = avr32_current_func_type (); -+ -+ if (IS_NAKED (func_type)) -+ fprintf (f, -+ "\t# Function is naked: Prologue and epilogue provided by programmer\n"); ++ if (GET_CODE (shift) == CONST_INT && ++ GET_CODE (add) == CONST_INT && INTVAL (shift) > 0) ++ { ++ if ((1 << (INTVAL (shift) - 1)) == INTVAL (add)) ++ return TRUE; ++ } + -+ if (IS_FLASHVAULT (func_type)) -+ { -+ fprintf(f, -+ "\t.ident \"flashvault\"\n\t# Function is defined with flashvault attribute.\n"); -+ } ++ return FALSE; ++} + -+ if (IS_FLASHVAULT_IMPL (func_type)) -+ { -+ fprintf(f, -+ "\t.ident \"flashvault\"\n\t# Function is defined with flashvault_impl attribute.\n"); + -+ /* Save information on flashvault function declaration. */ -+ tree fv_attribute = lookup_attribute ("flashvault_impl", DECL_ATTRIBUTES(current_function_decl)); -+ if (fv_attribute != NULL_TREE) ++int ++avr32_const_ok_for_constraint_p (HOST_WIDE_INT value, char c, const char *str) ++{ ++ switch (c) ++ { ++ case 'K': ++ case 'I': + { -+ tree vector_tree = TREE_VALUE(fv_attribute); -+ if (vector_tree != NULL_TREE) -+ { -+ unsigned int vector_num; -+ const char * name; ++ HOST_WIDE_INT min_value = 0, max_value = 0; ++ char size_str[3]; ++ int const_size; + -+ vector_num = (unsigned int) TREE_INT_CST_LOW (TREE_VALUE (vector_tree)); ++ size_str[0] = str[2]; ++ size_str[1] = str[3]; ++ size_str[2] = '\0'; ++ const_size = atoi (size_str); + -+ name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); ++ if (TOUPPER (str[1]) == 'U') ++ { ++ min_value = 0; ++ max_value = (1 << const_size) - 1; ++ } ++ else if (TOUPPER (str[1]) == 'S') ++ { ++ min_value = -(1 << (const_size - 1)); ++ max_value = (1 << (const_size - 1)) - 1; ++ } + -+ flashvault_decl_list_add (vector_num, name); -+ } -+ } -+ } ++ if (c == 'I') ++ { ++ value = -value; ++ } + -+ if (IS_INTERRUPT (func_type)) -+ { -+ switch (func_type) -+ { -+ case AVR32_FT_ISR_FULL: -+ fprintf (f, -+ "\t# Interrupt Function: Fully shadowed register file\n"); -+ break; -+ case AVR32_FT_ISR_HALF: -+ fprintf (f, -+ "\t# Interrupt Function: Half shadowed register file\n"); -+ break; -+ default: -+ case AVR32_FT_ISR_NONE: -+ fprintf (f, "\t# Interrupt Function: No shadowed register file\n"); -+ break; -+ } ++ if (value >= min_value && value <= max_value) ++ { ++ return 1; ++ } ++ break; ++ } ++ case 'M': ++ return avr32_mask_upper_bits_operand (GEN_INT (value), VOIDmode); ++ case 'J': ++ return avr32_hi16_immediate_operand (GEN_INT (value), VOIDmode); ++ case 'O': ++ return one_bit_set_operand (GEN_INT (value), VOIDmode); ++ case 'N': ++ return one_bit_cleared_operand (GEN_INT (value), VOIDmode); ++ case 'L': ++ /* The lower 16-bits are set. */ ++ return ((value & 0xffff) == 0xffff) ; + } + ++ return 0; ++} + -+ fprintf (f, "\t# args = %i, frame = %li, pretend = %i\n", -+ crtl->args.size, frame_size, -+ crtl->args.pretend_args_size); + -+ fprintf (f, "\t# frame_needed = %i, leaf_function = %i\n", -+ frame_pointer_needed, current_function_is_leaf); ++/* Compute mask of registers which needs saving upon function entry. */ ++static unsigned long ++avr32_compute_save_reg_mask (int push) ++{ ++ unsigned long func_type; ++ unsigned int save_reg_mask = 0; ++ unsigned int reg; + -+ fprintf (f, "\t# uses_anonymous_args = %i\n", -+ crtl->args.info.uses_anonymous_args); ++ func_type = avr32_current_func_type (); + -+ if (crtl->calls_eh_return) -+ fprintf (f, "\t# Calls __builtin_eh_return.\n"); ++ if (IS_INTERRUPT (func_type)) ++ { ++ unsigned int max_reg = 12; + -+} ++ /* Get the banking scheme for the interrupt */ ++ switch (func_type) ++ { ++ case AVR32_FT_ISR_FULL: ++ max_reg = 0; ++ break; ++ case AVR32_FT_ISR_HALF: ++ max_reg = 7; ++ break; ++ case AVR32_FT_ISR_NONE: ++ max_reg = 12; ++ break; ++ } + ++ /* Interrupt functions must not corrupt any registers, even call ++ clobbered ones. If this is a leaf function we can just examine the ++ registers used by the RTL, but otherwise we have to assume that ++ whatever function is called might clobber anything, and so we have ++ to save all the call-clobbered registers as well. */ + -+/* Generate and emit an insn that we will recognize as a pushm or stm. -+ Unfortunately, since this insn does not reflect very well the actual -+ semantics of the operation, we need to annotate the insn for the benefit -+ of DWARF2 frame unwind information. */ ++ /* Need not push the registers r8-r12 for AVR32A architectures, as this ++ is automatially done in hardware. We also do not have any shadow ++ registers. */ ++ if (TARGET_UARCH_AVR32A) ++ { ++ max_reg = 7; ++ func_type = AVR32_FT_ISR_NONE; ++ } + -+int avr32_convert_to_reglist16 (int reglist8_vect); ++ /* All registers which are used and are not shadowed must be saved. */ ++ for (reg = 0; reg <= max_reg; reg++) ++ if (df_regs_ever_live_p (INTERNAL_REGNUM (reg)) ++ || (!current_function_is_leaf ++ && call_used_regs[INTERNAL_REGNUM (reg)])) ++ save_reg_mask |= (1 << reg); + -+static rtx -+emit_multi_reg_push (int reglist, int usePUSHM) -+{ -+ rtx insn; -+ rtx dwarf; -+ rtx tmp; -+ rtx reg; -+ int i; -+ int nr_regs; -+ int index = 0; ++ /* Check LR */ ++ if ((df_regs_ever_live_p (LR_REGNUM) ++ || !current_function_is_leaf || frame_pointer_needed) ++ /* Only non-shadowed register models */ ++ && (func_type == AVR32_FT_ISR_NONE)) ++ save_reg_mask |= (1 << ASM_REGNUM (LR_REGNUM)); ++ ++ /* Make sure that the GOT register is pushed. */ ++ if (max_reg >= ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM) ++ && crtl->uses_pic_offset_table) ++ save_reg_mask |= (1 << ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM)); + -+ if (usePUSHM) -+ { -+ insn = emit_insn (gen_pushm (gen_rtx_CONST_INT (SImode, reglist))); -+ reglist = avr32_convert_to_reglist16 (reglist); + } + else + { -+ insn = emit_insn (gen_stm (stack_pointer_rtx, -+ gen_rtx_CONST_INT (SImode, reglist), -+ gen_rtx_CONST_INT (SImode, 1))); -+ } ++ int use_pushm = optimize_size; + -+ nr_regs = avr32_get_reg_mask_size (reglist) / 4; -+ dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nr_regs + 1)); ++ /* In the normal case we only need to save those registers which are ++ call saved and which are used by this function. */ ++ for (reg = 0; reg <= 7; reg++) ++ if (df_regs_ever_live_p (INTERNAL_REGNUM (reg)) ++ && !call_used_regs[INTERNAL_REGNUM (reg)]) ++ save_reg_mask |= (1 << reg); + -+ for (i = 15; i >= 0; i--) -+ { -+ if (reglist & (1 << i)) -+ { -+ reg = gen_rtx_REG (SImode, INTERNAL_REGNUM (i)); -+ tmp = gen_rtx_SET (VOIDmode, -+ gen_rtx_MEM (SImode, -+ plus_constant (stack_pointer_rtx, -+ 4 * index)), reg); -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ XVECEXP (dwarf, 0, 1 + index++) = tmp; -+ } -+ } ++ /* Make sure that the GOT register is pushed. */ ++ if (crtl->uses_pic_offset_table) ++ save_reg_mask |= (1 << ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM)); + -+ tmp = gen_rtx_SET (SImode, -+ stack_pointer_rtx, -+ gen_rtx_PLUS (SImode, -+ stack_pointer_rtx, -+ GEN_INT (-4 * nr_regs))); -+ RTX_FRAME_RELATED_P (tmp) = 1; -+ XVECEXP (dwarf, 0, 0) = tmp; -+ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, -+ REG_NOTES (insn)); -+ return insn; -+} + -+rtx -+avr32_gen_load_multiple (rtx * regs, int count, rtx from, -+ int write_back, int in_struct_p, int scalar_p) -+{ ++ /* If we optimize for size and do not have anonymous arguments: use ++ pushm/popm always. */ ++ if (use_pushm) ++ { ++ if ((save_reg_mask & (1 << 0)) ++ || (save_reg_mask & (1 << 1)) ++ || (save_reg_mask & (1 << 2)) || (save_reg_mask & (1 << 3))) ++ save_reg_mask |= 0xf; + -+ rtx result; -+ int i = 0, j; ++ if ((save_reg_mask & (1 << 4)) ++ || (save_reg_mask & (1 << 5)) ++ || (save_reg_mask & (1 << 6)) || (save_reg_mask & (1 << 7))) ++ save_reg_mask |= 0xf0; + -+ result = -+ gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + (write_back ? 1 : 0))); ++ if ((save_reg_mask & (1 << 8)) || (save_reg_mask & (1 << 9))) ++ save_reg_mask |= 0x300; ++ } + -+ if (write_back) -+ { -+ XVECEXP (result, 0, 0) -+ = gen_rtx_SET (GET_MODE (from), from, -+ plus_constant (from, count * 4)); -+ i = 1; -+ count++; ++ ++ /* Check LR */ ++ if ((df_regs_ever_live_p (LR_REGNUM) ++ || !current_function_is_leaf ++ || (optimize_size ++ && save_reg_mask ++ && !crtl->calls_eh_return) ++ || frame_pointer_needed) ++ && !IS_FLASHVAULT (func_type)) ++ { ++ if (push ++ /* Never pop LR into PC for functions which ++ calls __builtin_eh_return, since we need to ++ fix the SP after the restoring of the registers ++ and before returning. */ ++ || crtl->calls_eh_return) ++ { ++ /* Push/Pop LR */ ++ save_reg_mask |= (1 << ASM_REGNUM (LR_REGNUM)); ++ } ++ else ++ { ++ /* Pop PC */ ++ save_reg_mask |= (1 << ASM_REGNUM (PC_REGNUM)); ++ } ++ } + } + + -+ for (j = 0; i < count; i++, j++) ++ /* Save registers so the exception handler can modify them. */ ++ if (crtl->calls_eh_return) + { -+ rtx unspec; -+ rtx mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4)); -+ MEM_IN_STRUCT_P (mem) = in_struct_p; -+ MEM_SCALAR_P (mem) = scalar_p; -+ unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, mem), UNSPEC_LDM); -+ XVECEXP (result, 0, i) = gen_rtx_SET (VOIDmode, regs[j], unspec); ++ unsigned int i; ++ ++ for (i = 0;; i++) ++ { ++ reg = EH_RETURN_DATA_REGNO (i); ++ if (reg == INVALID_REGNUM) ++ break; ++ save_reg_mask |= 1 << ASM_REGNUM (reg); ++ } + } + -+ return result; ++ return save_reg_mask; +} + + -+rtx -+avr32_gen_store_multiple (rtx * regs, int count, rtx to, -+ int in_struct_p, int scalar_p) ++/* Compute total size in bytes of all saved registers. */ ++static int ++avr32_get_reg_mask_size (int reg_mask) ++{ ++ int reg, size; ++ size = 0; ++ ++ for (reg = 0; reg <= 15; reg++) ++ if (reg_mask & (1 << reg)) ++ size += 4; ++ ++ return size; ++} ++ ++ ++/* Get a register from one of the registers which are saved onto the stack ++ upon function entry. */ ++static int ++avr32_get_saved_reg (int save_reg_mask) ++{ ++ unsigned int reg; ++ ++ /* Find the first register which is saved in the saved_reg_mask */ ++ for (reg = 0; reg <= 15; reg++) ++ if (save_reg_mask & (1 << reg)) ++ return reg; ++ ++ return -1; ++} ++ ++ ++/* Return 1 if it is possible to return using a single instruction. */ ++int ++avr32_use_return_insn (int iscond) ++{ ++ unsigned int func_type = avr32_current_func_type (); ++ unsigned long saved_int_regs; ++ ++ /* Never use a return instruction before reload has run. */ ++ if (!reload_completed) ++ return 0; ++ ++ /* Must adjust the stack for vararg functions. */ ++ if (crtl->args.info.uses_anonymous_args) ++ return 0; ++ ++ /* If there a stack adjstment. */ ++ if (get_frame_size ()) ++ return 0; ++ ++ saved_int_regs = avr32_compute_save_reg_mask (TRUE); ++ ++ /* Conditional returns can not be performed in one instruction if we need ++ to restore registers from the stack */ ++ if (iscond && saved_int_regs) ++ return 0; ++ ++ /* Conditional return can not be used for interrupt handlers. */ ++ if (iscond && IS_INTERRUPT (func_type)) ++ return 0; ++ ++ /* For interrupt handlers which needs to pop registers */ ++ if (saved_int_regs && IS_INTERRUPT (func_type)) ++ return 0; ++ ++ ++ /* If there are saved registers but the LR isn't saved, then we need two ++ instructions for the return. */ ++ if (saved_int_regs && !(saved_int_regs & (1 << ASM_REGNUM (LR_REGNUM)))) ++ return 0; ++ ++ ++ return 1; ++} ++ ++ ++/* Generate some function prologue info in the assembly file. */ ++void ++avr32_target_asm_function_prologue (FILE * f, HOST_WIDE_INT frame_size) ++{ ++ unsigned long func_type = avr32_current_func_type (); ++ ++ if (IS_NAKED (func_type)) ++ fprintf (f, ++ "\t# Function is naked: Prologue and epilogue provided by programmer\n"); ++ ++ if (IS_FLASHVAULT (func_type)) ++ { ++ fprintf(f, ++ "\t.ident \"flashvault\"\n\t# Function is defined with flashvault attribute.\n"); ++ } ++ ++ if (IS_FLASHVAULT_IMPL (func_type)) ++ { ++ fprintf(f, ++ "\t.ident \"flashvault\"\n\t# Function is defined with flashvault_impl attribute.\n"); ++ ++ /* Save information on flashvault function declaration. */ ++ tree fv_attribute = lookup_attribute ("flashvault_impl", DECL_ATTRIBUTES(current_function_decl)); ++ if (fv_attribute != NULL_TREE) ++ { ++ tree vector_tree = TREE_VALUE(fv_attribute); ++ if (vector_tree != NULL_TREE) ++ { ++ unsigned int vector_num; ++ const char * name; ++ ++ vector_num = (unsigned int) TREE_INT_CST_LOW (TREE_VALUE (vector_tree)); ++ ++ name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); ++ ++ flashvault_decl_list_add (vector_num, name); ++ } ++ } ++ } ++ ++ if (IS_INTERRUPT (func_type)) ++ { ++ switch (func_type) ++ { ++ case AVR32_FT_ISR_FULL: ++ fprintf (f, ++ "\t# Interrupt Function: Fully shadowed register file\n"); ++ break; ++ case AVR32_FT_ISR_HALF: ++ fprintf (f, ++ "\t# Interrupt Function: Half shadowed register file\n"); ++ break; ++ default: ++ case AVR32_FT_ISR_NONE: ++ fprintf (f, "\t# Interrupt Function: No shadowed register file\n"); ++ break; ++ } ++ } ++ ++ ++ fprintf (f, "\t# args = %i, frame = %li, pretend = %i\n", ++ crtl->args.size, frame_size, ++ crtl->args.pretend_args_size); ++ ++ fprintf (f, "\t# frame_needed = %i, leaf_function = %i\n", ++ frame_pointer_needed, current_function_is_leaf); ++ ++ fprintf (f, "\t# uses_anonymous_args = %i\n", ++ crtl->args.info.uses_anonymous_args); ++ ++ if (crtl->calls_eh_return) ++ fprintf (f, "\t# Calls __builtin_eh_return.\n"); ++ ++} ++ ++ ++/* Generate and emit an insn that we will recognize as a pushm or stm. ++ Unfortunately, since this insn does not reflect very well the actual ++ semantics of the operation, we need to annotate the insn for the benefit ++ of DWARF2 frame unwind information. */ ++ ++int avr32_convert_to_reglist16 (int reglist8_vect); ++ ++static rtx ++emit_multi_reg_push (int reglist, int usePUSHM) ++{ ++ rtx insn; ++ rtx dwarf; ++ rtx tmp; ++ rtx reg; ++ int i; ++ int nr_regs; ++ int index = 0; ++ ++ if (usePUSHM) ++ { ++ insn = emit_insn (gen_pushm (gen_rtx_CONST_INT (SImode, reglist))); ++ reglist = avr32_convert_to_reglist16 (reglist); ++ } ++ else ++ { ++ insn = emit_insn (gen_stm (stack_pointer_rtx, ++ gen_rtx_CONST_INT (SImode, reglist), ++ gen_rtx_CONST_INT (SImode, 1))); ++ } ++ ++ nr_regs = avr32_get_reg_mask_size (reglist) / 4; ++ dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nr_regs + 1)); ++ ++ for (i = 15; i >= 0; i--) ++ { ++ if (reglist & (1 << i)) ++ { ++ reg = gen_rtx_REG (SImode, INTERNAL_REGNUM (i)); ++ tmp = gen_rtx_SET (VOIDmode, ++ gen_rtx_MEM (SImode, ++ plus_constant (stack_pointer_rtx, ++ 4 * index)), reg); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ XVECEXP (dwarf, 0, 1 + index++) = tmp; ++ } ++ } ++ ++ tmp = gen_rtx_SET (SImode, ++ stack_pointer_rtx, ++ gen_rtx_PLUS (SImode, ++ stack_pointer_rtx, ++ GEN_INT (-4 * nr_regs))); ++ RTX_FRAME_RELATED_P (tmp) = 1; ++ XVECEXP (dwarf, 0, 0) = tmp; ++ REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, ++ REG_NOTES (insn)); ++ return insn; ++} ++ ++rtx ++avr32_gen_load_multiple (rtx * regs, int count, rtx from, ++ int write_back, int in_struct_p, int scalar_p) ++{ ++ ++ rtx result; ++ int i = 0, j; ++ ++ result = ++ gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + (write_back ? 1 : 0))); ++ ++ if (write_back) ++ { ++ XVECEXP (result, 0, 0) ++ = gen_rtx_SET (GET_MODE (from), from, ++ plus_constant (from, count * 4)); ++ i = 1; ++ count++; ++ } ++ ++ ++ for (j = 0; i < count; i++, j++) ++ { ++ rtx unspec; ++ rtx mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4)); ++ MEM_IN_STRUCT_P (mem) = in_struct_p; ++ MEM_SCALAR_P (mem) = scalar_p; ++ unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, mem), UNSPEC_LDM); ++ XVECEXP (result, 0, i) = gen_rtx_SET (VOIDmode, regs[j], unspec); ++ } ++ ++ return result; ++} ++ ++ ++rtx ++avr32_gen_store_multiple (rtx * regs, int count, rtx to, ++ int in_struct_p, int scalar_p) +{ + rtx result; + int i = 0, j; @@ -8113,105 +8413,10 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32.c gcc-4.4.6/gcc/config/avr32/avr + } + } +} -diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32-elf.h gcc-4.4.6/gcc/config/avr32/avr32-elf.h ---- gcc-4.4.6.orig/gcc/config/avr32/avr32-elf.h 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/avr32-elf.h 2011-08-27 19:45:42.679240416 +0200 -@@ -0,0 +1,91 @@ -+/* -+ Elf specific definitions. -+ Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation. -+ -+ This file is part of GCC. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -+ -+ -+/***************************************************************************** -+ * Controlling the Compiler Driver, 'gcc' -+ *****************************************************************************/ -+ -+/* Run-time Target Specification. */ -+#undef TARGET_VERSION -+#define TARGET_VERSION fputs (" (AVR32 GNU with ELF)", stderr); -+ -+/* -+Another C string constant used much like LINK_SPEC. The -+difference between the two is that STARTFILE_SPEC is used at -+the very beginning of the command given to the linker. -+ -+If this macro is not defined, a default is provided that loads the -+standard C startup file from the usual place. See gcc.c. -+*/ -+#if 0 -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s" -+#endif -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC "%{mflashvault: crtfv.o%s} %{!mflashvault: crt0.o%s} \ -+ crti.o%s crtbegin.o%s" -+ -+#undef LINK_SPEC -+#define LINK_SPEC "%{muse-oscall:--defsym __do_not_use_oscall_coproc__=0} %{mrelax|O*:%{mno-relax|O0|O1: ;:--relax}} %{mpart=uc3a3revd:-mavr32elf_uc3a3256s;:%{mpart=*:-mavr32elf_%*}} %{mcpu=*:-mavr32elf_%*}" -+ -+ -+/* -+Another C string constant used much like LINK_SPEC. The -+difference between the two is that ENDFILE_SPEC is used at -+the very end of the command given to the linker. -+ -+Do not define this macro if it does not need to do anything. -+*/ -+#undef ENDFILE_SPEC -+#define ENDFILE_SPEC "crtend%O%s crtn%O%s" -+ -+ -+/* Target CPU builtins. */ -+#define TARGET_CPU_CPP_BUILTINS() \ -+ do \ -+ { \ -+ builtin_define ("__avr32__"); \ -+ builtin_define ("__AVR32__"); \ -+ builtin_define ("__AVR32_ELF__"); \ -+ builtin_define (avr32_part->macro); \ -+ builtin_define (avr32_arch->macro); \ -+ if (avr32_arch->uarch_type == UARCH_TYPE_AVR32A) \ -+ builtin_define ("__AVR32_AVR32A__"); \ -+ else \ -+ builtin_define ("__AVR32_AVR32B__"); \ -+ if (TARGET_UNALIGNED_WORD) \ -+ builtin_define ("__AVR32_HAS_UNALIGNED_WORD__"); \ -+ if (TARGET_SIMD) \ -+ builtin_define ("__AVR32_HAS_SIMD__"); \ -+ if (TARGET_DSP) \ -+ builtin_define ("__AVR32_HAS_DSP__"); \ -+ if (TARGET_RMW) \ -+ builtin_define ("__AVR32_HAS_RMW__"); \ -+ if (TARGET_BRANCH_PRED) \ -+ builtin_define ("__AVR32_HAS_BRANCH_PRED__"); \ -+ if (TARGET_FAST_FLOAT) \ -+ builtin_define ("__AVR32_FAST_FLOAT__"); \ -+ if (TARGET_FLASHVAULT) \ -+ builtin_define ("__AVR32_FLASHVAULT__"); \ -+ if (TARGET_NO_MUL_INSNS) \ -+ builtin_define ("__AVR32_NO_MUL__"); \ -+ } \ -+ while (0) -diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32.h gcc-4.4.6/gcc/config/avr32/avr32.h ---- gcc-4.4.6.orig/gcc/config/avr32/avr32.h 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/avr32.h 2011-08-27 19:45:42.757981238 +0200 -@@ -0,0 +1,3316 @@ +diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32.h gcc-4.4.6/gcc/config/avr32/avr32.h +--- gcc-4.4.6.orig/gcc/config/avr32/avr32.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-4.4.6/gcc/config/avr32/avr32.h 2011-10-22 19:23:08.520581302 +0200 +@@ -0,0 +1,3316 @@ +/* + Definitions of target machine for AVR32. + Copyright 2003,2004,2005,2006,2007,2008,2009,2010 Atmel Corporation. @@ -11530,7 +11735,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32.h gcc-4.4.6/gcc/config/avr32/avr +#endif diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32.md gcc-4.4.6/gcc/config/avr32/avr32.md --- gcc-4.4.6.orig/gcc/config/avr32/avr32.md 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/avr32.md 2011-08-27 19:45:42.807981430 +0200 ++++ gcc-4.4.6/gcc/config/avr32/avr32.md 2011-10-22 19:23:08.524581303 +0200 @@ -0,0 +1,5198 @@ +;; AVR32 machine description file. +;; Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation. @@ -16730,14 +16935,9 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32.md gcc-4.4.6/gcc/config/avr32/av + +;; Include the FPU for uc3 +(include "uc3fpu.md") -diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32-modes.def gcc-4.4.6/gcc/config/avr32/avr32-modes.def ---- gcc-4.4.6.orig/gcc/config/avr32/avr32-modes.def 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/avr32-modes.def 2011-08-27 19:45:42.837990082 +0200 -@@ -0,0 +1 @@ -+VECTOR_MODES (INT, 4); /* V4QI V2HI */ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32.opt gcc-4.4.6/gcc/config/avr32/avr32.opt --- gcc-4.4.6.orig/gcc/config/avr32/avr32.opt 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/avr32.opt 2011-08-27 19:45:42.877990476 +0200 ++++ gcc-4.4.6/gcc/config/avr32/avr32.opt 2011-10-22 19:23:08.524581303 +0200 @@ -0,0 +1,93 @@ +; Options for the ATMEL AVR32 port of the compiler. + @@ -16832,13 +17032,15 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32.opt gcc-4.4.6/gcc/config/avr32/a +mlist-devices +Target RejectNegative Var(avr32_list_supported_parts) +Print the list of parts supported while printing --target-help. -diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32-protos.h gcc-4.4.6/gcc/config/avr32/avr32-protos.h ---- gcc-4.4.6.orig/gcc/config/avr32/avr32-protos.h 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/avr32-protos.h 2011-08-27 19:45:42.937990414 +0200 -@@ -0,0 +1,196 @@ +diff -Nur gcc-4.4.6.orig/gcc/config/avr32/crti.asm gcc-4.4.6/gcc/config/avr32/crti.asm +--- gcc-4.4.6.orig/gcc/config/avr32/crti.asm 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-4.4.6/gcc/config/avr32/crti.asm 2011-10-22 19:23:08.524581303 +0200 +@@ -0,0 +1,64 @@ +/* -+ Prototypes for exported functions defined in avr32.c -+ Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation. ++ Init/fini stuff for AVR32. ++ Copyright 2003-2006 Atmel Corporation. ++ ++ Written by Ronny Pedersen, Atmel Norway, + + This file is part of GCC. + @@ -16856,309 +17058,107 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/avr32-protos.h gcc-4.4.6/gcc/config/av + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + ++ ++/* The code in sections .init and .fini is supposed to be a single ++ regular function. The function in .init is called directly from ++ start in crt1.asm. The function in .fini is atexit()ed in crt1.asm ++ too. + -+#ifndef AVR32_PROTOS_H -+#define AVR32_PROTOS_H ++ crti.asm contributes the prologue of a function to these sections, ++ and crtn.asm comes up the epilogue. STARTFILE_SPEC should list ++ crti.o before any other object files that might add code to .init ++ or .fini sections, and ENDFILE_SPEC should list crtn.o after any ++ such object files. */ ++ ++ .file "crti.asm" + -+extern const int swap_reg[]; ++ .section ".init" ++/* Just load the GOT */ ++ .align 2 ++ .global _init ++_init: ++ stm --sp, r6, lr ++ lddpc r6, 1f ++0: ++ rsub r6, pc ++ rjmp 2f ++ .align 2 ++1: .long 0b - _GLOBAL_OFFSET_TABLE_ ++2: ++ ++ .section ".fini" ++/* Just load the GOT */ ++ .align 2 ++ .global _fini ++_fini: ++ stm --sp, r6, lr ++ lddpc r6, 1f ++0: ++ rsub r6, pc ++ rjmp 2f ++ .align 2 ++1: .long 0b - _GLOBAL_OFFSET_TABLE_ ++2: + -+extern int avr32_valid_macmac_bypass (rtx, rtx); -+extern int avr32_valid_mulmac_bypass (rtx, rtx); +diff -Nur gcc-4.4.6.orig/gcc/config/avr32/crtn.asm gcc-4.4.6/gcc/config/avr32/crtn.asm +--- gcc-4.4.6.orig/gcc/config/avr32/crtn.asm 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-4.4.6/gcc/config/avr32/crtn.asm 2011-10-22 19:23:08.524581303 +0200 +@@ -0,0 +1,44 @@ ++/* Copyright (C) 2001 Free Software Foundation, Inc. ++ Written By Nick Clifton + -+extern int avr32_decode_lcomm_symbol_offset (rtx, int *); -+extern void avr32_encode_lcomm_symbol_offset (tree, char *, int); ++ This file is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published by the ++ Free Software Foundation; either version 2, or (at your option) any ++ later version. + -+extern const char *avr32_strip_name_encoding (const char *); ++ In addition to the permissions in the GNU General Public License, the ++ Free Software Foundation gives you unlimited permission to link the ++ compiled version of this file with other programs, and to distribute ++ those programs without any restriction coming from the use of this ++ file. (The General Public License restrictions do apply in other ++ respects; for example, they cover modification of the file, and ++ distribution when not linked into another program.) + -+extern rtx avr32_get_note_reg_equiv (rtx insn); ++ This file is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. + -+extern int avr32_use_return_insn (int iscond); ++ You should have received a copy of the GNU General Public License ++ along with this program; see the file COPYING. If not, write to ++ the Free Software Foundation, 59 Temple Place - Suite 330, ++ Boston, MA 02111-1307, USA. + -+extern void avr32_make_reglist16 (int reglist16_vect, char *reglist16_string); ++ As a special exception, if you link this library with files ++ compiled with GCC to produce an executable, this does not cause ++ the resulting executable to be covered by the GNU General Public License. ++ This exception does not however invalidate any other reasons why ++ the executable file might be covered by the GNU General Public License. ++*/ + -+extern void avr32_make_reglist8 (int reglist8_vect, char *reglist8_string); -+extern void avr32_make_fp_reglist_w (int reglist_mask, char *reglist_string); -+extern void avr32_make_fp_reglist_d (int reglist_mask, char *reglist_string); + -+extern void avr32_output_return_instruction (int single_ret_inst, -+ int iscond, rtx cond, -+ rtx r12_imm); -+extern void avr32_expand_prologue (void); -+extern void avr32_set_return_address (rtx source, rtx scratch); + -+extern int avr32_hard_regno_mode_ok (int regno, enum machine_mode mode); -+extern int avr32_extra_constraint_s (rtx value, const int strict); -+extern int avr32_eh_return_data_regno (const int n); -+extern int avr32_initial_elimination_offset (const int from, const int to); -+extern rtx avr32_function_arg (CUMULATIVE_ARGS * cum, enum machine_mode mode, -+ tree type, int named); -+extern void avr32_init_cumulative_args (CUMULATIVE_ARGS * cum, tree fntype, -+ rtx libname, tree fndecl); -+extern void avr32_function_arg_advance (CUMULATIVE_ARGS * cum, -+ enum machine_mode mode, -+ tree type, int named); -+#ifdef ARGS_SIZE_RTX -+/* expr.h defines ARGS_SIZE_RTX and `enum direction'. */ -+extern enum direction avr32_function_arg_padding (enum machine_mode mode, -+ tree type); -+#endif /* ARGS_SIZE_RTX */ -+extern rtx avr32_function_value (tree valtype, tree func, bool outgoing); -+extern rtx avr32_libcall_value (enum machine_mode mode); -+extern int avr32_sched_use_dfa_pipeline_interface (void); -+extern bool avr32_return_in_memory (tree type, tree fntype); -+extern void avr32_regs_to_save (char *operand); -+extern void avr32_target_asm_function_prologue (FILE * file, -+ HOST_WIDE_INT size); -+extern void avr32_target_asm_function_epilogue (FILE * file, -+ HOST_WIDE_INT size); -+extern void avr32_trampoline_template (FILE * file); -+extern void avr32_initialize_trampoline (rtx addr, rtx fnaddr, -+ rtx static_chain); -+extern int avr32_legitimate_address (enum machine_mode mode, rtx x, -+ int strict); -+extern int avr32_legitimate_constant_p (rtx x); ++ ++ .file "crtn.asm" + -+extern int avr32_legitimate_pic_operand_p (rtx x); -+ -+extern rtx avr32_find_symbol (rtx x); -+extern void avr32_select_section (rtx exp, int reloc, int align); -+extern void avr32_encode_section_info (tree decl, rtx rtl, int first); -+extern void avr32_asm_file_end (FILE * stream); -+extern void avr32_asm_output_ascii (FILE * stream, char *ptr, int len); -+extern void avr32_asm_output_common (FILE * stream, const char *name, -+ int size, int rounded); -+extern void avr32_asm_output_label (FILE * stream, const char *name); -+extern void avr32_asm_declare_object_name (FILE * stream, char *name, -+ tree decl); -+extern void avr32_asm_globalize_label (FILE * stream, const char *name); -+extern void avr32_asm_weaken_label (FILE * stream, const char *name); -+extern void avr32_asm_output_external (FILE * stream, tree decl, -+ const char *name); -+extern void avr32_asm_output_external_libcall (FILE * stream, rtx symref); -+extern void avr32_asm_output_labelref (FILE * stream, const char *name); -+extern void avr32_notice_update_cc (rtx exp, rtx insn); -+extern void avr32_print_operand (FILE * stream, rtx x, int code); -+extern void avr32_print_operand_address (FILE * stream, rtx x); -+ -+extern int avr32_symbol (rtx x); -+ -+extern void avr32_select_rtx_section (enum machine_mode mode, rtx x, -+ unsigned HOST_WIDE_INT align); -+ -+extern int avr32_load_multiple_operation (rtx op, enum machine_mode mode); -+extern int avr32_store_multiple_operation (rtx op, enum machine_mode mode); -+ -+extern int avr32_const_ok_for_constraint_p (HOST_WIDE_INT value, char c, -+ const char *str); -+ -+extern bool avr32_cannot_force_const_mem (rtx x); -+ -+extern void avr32_init_builtins (void); -+ -+extern rtx avr32_expand_builtin (tree exp, rtx target, rtx subtarget, -+ enum machine_mode mode, int ignore); -+ -+extern bool avr32_must_pass_in_stack (enum machine_mode mode, tree type); -+ -+extern bool avr32_strict_argument_naming (CUMULATIVE_ARGS * ca); -+ -+extern bool avr32_pass_by_reference (CUMULATIVE_ARGS * cum, -+ enum machine_mode mode, -+ tree type, bool named); -+ -+extern rtx avr32_gen_load_multiple (rtx * regs, int count, rtx from, -+ int write_back, int in_struct_p, -+ int scalar_p); -+extern rtx avr32_gen_store_multiple (rtx * regs, int count, rtx to, -+ int in_struct_p, int scalar_p); -+extern int avr32_gen_movmemsi (rtx * operands); -+ -+extern int avr32_rnd_operands (rtx add, rtx shift); -+extern int avr32_adjust_insn_length (rtx insn, int length); -+ -+extern int symbol_mentioned_p (rtx x); -+extern int label_mentioned_p (rtx x); -+extern rtx legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg); -+extern int avr32_address_register_rtx_p (rtx x, int strict_p); -+extern int avr32_legitimate_index_p (enum machine_mode mode, rtx index, -+ int strict_p); -+ -+extern int avr32_const_double_immediate (rtx value); -+extern void avr32_init_expanders (void); -+extern rtx avr32_return_addr (int count, rtx frame); -+extern bool avr32_got_mentioned_p (rtx addr); -+ -+extern void avr32_final_prescan_insn (rtx insn, rtx * opvec, int noperands); -+ -+extern int avr32_expand_movcc (enum machine_mode mode, rtx operands[]); -+extern int avr32_expand_addcc (enum machine_mode mode, rtx operands[]); -+#ifdef RTX_CODE -+extern int avr32_expand_scc (RTX_CODE cond, rtx * operands); -+#endif -+ -+extern int avr32_store_bypass (rtx insn_out, rtx insn_in); -+extern int avr32_mul_waw_bypass (rtx insn_out, rtx insn_in); -+extern int avr32_valid_load_double_bypass (rtx insn_out, rtx insn_in); -+extern int avr32_valid_load_quad_bypass (rtx insn_out, rtx insn_in); -+extern rtx avr32_output_cmp (rtx cond, enum machine_mode mode, -+ rtx op0, rtx op1); -+ -+rtx get_next_insn_cond (rtx cur_insn); -+int set_next_insn_cond (rtx cur_insn, rtx cond); -+rtx next_insn_emits_cmp (rtx cur_insn); -+void avr32_override_options (void); -+void avr32_load_pic_register (void); -+#ifdef GCC_BASIC_BLOCK_H -+rtx avr32_ifcvt_modify_insn (ce_if_block_t *ce_info, rtx pattern, rtx insn, -+ int *num_true_changes); -+rtx avr32_ifcvt_modify_test (ce_if_block_t *ce_info, rtx test ); -+void avr32_ifcvt_modify_cancel ( ce_if_block_t *ce_info, int *num_true_changes); -+#endif -+void avr32_optimization_options (int level, int size); -+int avr32_const_ok_for_move (HOST_WIDE_INT c); -+ -+void avr32_split_const_expr (enum machine_mode mode, -+ enum machine_mode new_mode, -+ rtx expr, -+ rtx *split_expr); -+void avr32_get_intval (enum machine_mode mode, -+ rtx const_expr, -+ HOST_WIDE_INT *val); -+ -+int avr32_cond_imm_clobber_splittable (rtx insn, -+ rtx operands[]); -+ -+bool avr32_flashvault_call(tree decl); -+extern void avr32_emit_swdivsf (rtx, rtx, rtx); -+ -+#endif /* AVR32_PROTOS_H */ -diff -Nur gcc-4.4.6.orig/gcc/config/avr32/crti.asm gcc-4.4.6/gcc/config/avr32/crti.asm ---- gcc-4.4.6.orig/gcc/config/avr32/crti.asm 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/crti.asm 2011-08-27 19:45:42.977989352 +0200 -@@ -0,0 +1,64 @@ -+/* -+ Init/fini stuff for AVR32. -+ Copyright 2003-2006 Atmel Corporation. -+ -+ Written by Ronny Pedersen, Atmel Norway, -+ -+ This file is part of GCC. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -+ -+ -+/* The code in sections .init and .fini is supposed to be a single -+ regular function. The function in .init is called directly from -+ start in crt1.asm. The function in .fini is atexit()ed in crt1.asm -+ too. -+ -+ crti.asm contributes the prologue of a function to these sections, -+ and crtn.asm comes up the epilogue. STARTFILE_SPEC should list -+ crti.o before any other object files that might add code to .init -+ or .fini sections, and ENDFILE_SPEC should list crtn.o after any -+ such object files. */ -+ -+ .file "crti.asm" -+ -+ .section ".init" -+/* Just load the GOT */ -+ .align 2 -+ .global _init -+_init: -+ stm --sp, r6, lr -+ lddpc r6, 1f -+0: -+ rsub r6, pc -+ rjmp 2f -+ .align 2 -+1: .long 0b - _GLOBAL_OFFSET_TABLE_ -+2: -+ -+ .section ".fini" -+/* Just load the GOT */ -+ .align 2 -+ .global _fini -+_fini: -+ stm --sp, r6, lr -+ lddpc r6, 1f -+0: -+ rsub r6, pc -+ rjmp 2f -+ .align 2 -+1: .long 0b - _GLOBAL_OFFSET_TABLE_ -+2: -+ -diff -Nur gcc-4.4.6.orig/gcc/config/avr32/crtn.asm gcc-4.4.6/gcc/config/avr32/crtn.asm ---- gcc-4.4.6.orig/gcc/config/avr32/crtn.asm 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/crtn.asm 2011-08-27 19:45:43.020480077 +0200 -@@ -0,0 +1,44 @@ -+/* Copyright (C) 2001 Free Software Foundation, Inc. -+ Written By Nick Clifton -+ -+ This file is free software; you can redistribute it and/or modify it -+ under the terms of the GNU General Public License as published by the -+ Free Software Foundation; either version 2, or (at your option) any -+ later version. -+ -+ In addition to the permissions in the GNU General Public License, the -+ Free Software Foundation gives you unlimited permission to link the -+ compiled version of this file with other programs, and to distribute -+ those programs without any restriction coming from the use of this -+ file. (The General Public License restrictions do apply in other -+ respects; for example, they cover modification of the file, and -+ distribution when not linked into another program.) -+ -+ This file is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; see the file COPYING. If not, write to -+ the Free Software Foundation, 59 Temple Place - Suite 330, -+ Boston, MA 02111-1307, USA. -+ -+ As a special exception, if you link this library with files -+ compiled with GCC to produce an executable, this does not cause -+ the resulting executable to be covered by the GNU General Public License. -+ This exception does not however invalidate any other reasons why -+ the executable file might be covered by the GNU General Public License. -+*/ -+ -+ -+ -+ -+ .file "crtn.asm" -+ -+ .section ".init" -+ ldm sp++, r6, pc -+ -+ .section ".fini" -+ ldm sp++, r6, pc -+ -diff -Nur gcc-4.4.6.orig/gcc/config/avr32/lib1funcs.S gcc-4.4.6/gcc/config/avr32/lib1funcs.S ---- gcc-4.4.6.orig/gcc/config/avr32/lib1funcs.S 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/lib1funcs.S 2011-08-27 19:46:04.347990802 +0200 -@@ -0,0 +1,2902 @@ -+/* Macro for moving immediate value to register. */ -+.macro mov_imm reg, imm -+.if (((\imm & 0xfffff) == \imm) || ((\imm | 0xfff00000) == \imm)) -+ mov \reg, \imm -+#if __AVR32_UC__ >= 2 -+.elseif ((\imm & 0xffff) == 0) -+ movh \reg, hi(\imm) ++ .section ".init" ++ ldm sp++, r6, pc ++ ++ .section ".fini" ++ ldm sp++, r6, pc ++ +diff -Nur gcc-4.4.6.orig/gcc/config/avr32/lib1funcs.S gcc-4.4.6/gcc/config/avr32/lib1funcs.S +--- gcc-4.4.6.orig/gcc/config/avr32/lib1funcs.S 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-4.4.6/gcc/config/avr32/lib1funcs.S 2011-10-22 19:23:08.524581303 +0200 +@@ -0,0 +1,2902 @@ ++/* Macro for moving immediate value to register. */ ++.macro mov_imm reg, imm ++.if (((\imm & 0xfffff) == \imm) || ((\imm | 0xfff00000) == \imm)) ++ mov \reg, \imm ++#if __AVR32_UC__ >= 2 ++.elseif ((\imm & 0xffff) == 0) ++ movh \reg, hi(\imm) + +#endif +.else @@ -20056,7 +20056,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/lib1funcs.S gcc-4.4.6/gcc/config/avr32 +#endif diff -Nur gcc-4.4.6.orig/gcc/config/avr32/lib2funcs.S gcc-4.4.6/gcc/config/avr32/lib2funcs.S --- gcc-4.4.6.orig/gcc/config/avr32/lib2funcs.S 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/lib2funcs.S 2011-08-27 19:45:43.100490428 +0200 ++++ gcc-4.4.6/gcc/config/avr32/lib2funcs.S 2011-10-22 19:23:08.524581303 +0200 @@ -0,0 +1,21 @@ + .align 4 + .global __nonlocal_goto @@ -20081,7 +20081,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/lib2funcs.S gcc-4.4.6/gcc/config/avr32 + diff -Nur gcc-4.4.6.orig/gcc/config/avr32/linux-elf.h gcc-4.4.6/gcc/config/avr32/linux-elf.h --- gcc-4.4.6.orig/gcc/config/avr32/linux-elf.h 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/linux-elf.h 2011-08-27 19:45:43.160490580 +0200 ++++ gcc-4.4.6/gcc/config/avr32/linux-elf.h 2011-10-22 19:23:08.524581303 +0200 @@ -0,0 +1,151 @@ +/* + Linux/Elf specific definitions. @@ -20236,7 +20236,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/linux-elf.h gcc-4.4.6/gcc/config/avr32 + "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}" diff -Nur gcc-4.4.6.orig/gcc/config/avr32/predicates.md gcc-4.4.6/gcc/config/avr32/predicates.md --- gcc-4.4.6.orig/gcc/config/avr32/predicates.md 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/predicates.md 2011-08-27 19:45:43.200490072 +0200 ++++ gcc-4.4.6/gcc/config/avr32/predicates.md 2011-10-22 19:23:08.524581303 +0200 @@ -0,0 +1,422 @@ +;; AVR32 predicates file. +;; Copyright 2003-2006 Atmel Corporation. @@ -20662,7 +20662,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/predicates.md gcc-4.4.6/gcc/config/avr +}) diff -Nur gcc-4.4.6.orig/gcc/config/avr32/simd.md gcc-4.4.6/gcc/config/avr32/simd.md --- gcc-4.4.6.orig/gcc/config/avr32/simd.md 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/simd.md 2011-08-27 19:45:43.237989394 +0200 ++++ gcc-4.4.6/gcc/config/avr32/simd.md 2011-10-22 19:23:08.528581303 +0200 @@ -0,0 +1,145 @@ +;; AVR32 machine description file for SIMD instructions. +;; Copyright 2003-2006 Atmel Corporation. @@ -20811,7 +20811,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/simd.md gcc-4.4.6/gcc/config/avr32/sim + (set_attr "type" "alu")]) diff -Nur gcc-4.4.6.orig/gcc/config/avr32/sync.md gcc-4.4.6/gcc/config/avr32/sync.md --- gcc-4.4.6.orig/gcc/config/avr32/sync.md 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/sync.md 2011-08-27 19:45:43.280490475 +0200 ++++ gcc-4.4.6/gcc/config/avr32/sync.md 2011-10-22 19:23:08.528581303 +0200 @@ -0,0 +1,244 @@ +;;================================================================= +;; Atomic operations @@ -21059,7 +21059,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/sync.md gcc-4.4.6/gcc/config/avr32/syn + ) diff -Nur gcc-4.4.6.orig/gcc/config/avr32/t-avr32 gcc-4.4.6/gcc/config/avr32/t-avr32 --- gcc-4.4.6.orig/gcc/config/avr32/t-avr32 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/t-avr32 2011-08-27 19:45:43.327990411 +0200 ++++ gcc-4.4.6/gcc/config/avr32/t-avr32 2011-10-22 19:23:08.528581303 +0200 @@ -0,0 +1,118 @@ + +MD_INCLUDES= $(srcdir)/config/avr32/avr32.md \ @@ -21181,7 +21181,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/t-avr32 gcc-4.4.6/gcc/config/avr32/t-a + diff -Nur gcc-4.4.6.orig/gcc/config/avr32/t-avr32-linux gcc-4.4.6/gcc/config/avr32/t-avr32-linux --- gcc-4.4.6.orig/gcc/config/avr32/t-avr32-linux 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/t-avr32-linux 2011-08-27 19:45:43.367991180 +0200 ++++ gcc-4.4.6/gcc/config/avr32/t-avr32-linux 2011-10-22 19:23:08.528581303 +0200 @@ -0,0 +1,118 @@ + +MD_INCLUDES= $(srcdir)/config/avr32/avr32.md \ @@ -21303,7 +21303,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/t-avr32-linux gcc-4.4.6/gcc/config/avr + diff -Nur gcc-4.4.6.orig/gcc/config/avr32/t-elf gcc-4.4.6/gcc/config/avr32/t-elf --- gcc-4.4.6.orig/gcc/config/avr32/t-elf 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/t-elf 2011-08-27 19:45:43.427991160 +0200 ++++ gcc-4.4.6/gcc/config/avr32/t-elf 2011-10-22 19:23:08.528581303 +0200 @@ -0,0 +1,16 @@ + +# Assemble startup files. @@ -21323,7 +21323,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/t-elf gcc-4.4.6/gcc/config/avr32/t-elf +INSTALL_LIBGCC = install-multilib diff -Nur gcc-4.4.6.orig/gcc/config/avr32/uc3fpu.md gcc-4.4.6/gcc/config/avr32/uc3fpu.md --- gcc-4.4.6.orig/gcc/config/avr32/uc3fpu.md 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/uc3fpu.md 2011-08-27 19:45:43.470489984 +0200 ++++ gcc-4.4.6/gcc/config/avr32/uc3fpu.md 2011-10-22 19:23:08.528581303 +0200 @@ -0,0 +1,199 @@ +;; AVR32 machine description file for Floating-Point instructions. +;; Copyright 2003-2006 Atmel Corporation. @@ -21526,7 +21526,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/uc3fpu.md gcc-4.4.6/gcc/config/avr32/u + "frsqrta.s %1, %0") diff -Nur gcc-4.4.6.orig/gcc/config/avr32/uclinux-elf.h gcc-4.4.6/gcc/config/avr32/uclinux-elf.h --- gcc-4.4.6.orig/gcc/config/avr32/uclinux-elf.h 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config/avr32/uclinux-elf.h 2011-08-27 19:45:43.510490479 +0200 ++++ gcc-4.4.6/gcc/config/avr32/uclinux-elf.h 2011-10-22 19:23:08.528581303 +0200 @@ -0,0 +1,20 @@ + +/* Run-time Target Specification. */ @@ -21550,7 +21550,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config/avr32/uclinux-elf.h gcc-4.4.6/gcc/config/avr +#define TARGET_DEFAULT (AVR32_FLAG_NO_INIT_GOT) diff -Nur gcc-4.4.6.orig/gcc/config/host-linux.c gcc-4.4.6/gcc/config/host-linux.c --- gcc-4.4.6.orig/gcc/config/host-linux.c 2009-02-20 16:20:38.000000000 +0100 -+++ gcc-4.4.6/gcc/config/host-linux.c 2011-08-27 19:45:43.560490932 +0200 ++++ gcc-4.4.6/gcc/config/host-linux.c 2011-10-22 19:23:08.528581303 +0200 @@ -25,6 +25,9 @@ #include "hosthooks.h" #include "hosthooks-def.h" @@ -21563,7 +21563,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config/host-linux.c gcc-4.4.6/gcc/config/host-linux address of non-fixed mapped segments by a (relatively) small amount. diff -Nur gcc-4.4.6.orig/gcc/config.gcc gcc-4.4.6/gcc/config.gcc --- gcc-4.4.6.orig/gcc/config.gcc 2011-02-18 22:39:51.000000000 +0100 -+++ gcc-4.4.6/gcc/config.gcc 2011-08-27 19:45:43.637990448 +0200 ++++ gcc-4.4.6/gcc/config.gcc 2011-10-22 19:23:08.528581303 +0200 @@ -810,6 +810,24 @@ avr-*-*) tm_file="avr/avr.h dbxelf.h" @@ -21624,7 +21624,7 @@ diff -Nur gcc-4.4.6.orig/gcc/config.gcc gcc-4.4.6/gcc/config.gcc case "$with_cpu" in diff -Nur gcc-4.4.6.orig/gcc/config.gcc.orig gcc-4.4.6/gcc/config.gcc.orig --- gcc-4.4.6.orig/gcc/config.gcc.orig 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/config.gcc.orig 2011-02-18 22:39:51.000000000 +0100 ++++ gcc-4.4.6/gcc/config.gcc.orig 2011-10-22 19:23:08.528581303 +0200 @@ -0,0 +1,3208 @@ +# GCC target-specific configuration file. +# Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, @@ -24237,17696 +24237,1038 @@ diff -Nur gcc-4.4.6.orig/gcc/config.gcc.orig gcc-4.4.6/gcc/config.gcc.orig + fi + with_cpu= + fi -+ fi -+ ;; -+ esac -+fi -+ -+# Similarly for --with-schedule. -+if test x$with_schedule = x; then -+ case ${target} in -+ hppa1*) -+ # Override default PA8000 scheduling model. -+ with_schedule=7100LC -+ ;; -+ esac -+fi -+ -+# Validate and mark as valid any --with options supported -+# by this target. In order to use a particular --with option -+# you must list it in supported_defaults; validating the value -+# is optional. This case statement should set nothing besides -+# supported_defaults. -+ -+supported_defaults= -+case "${target}" in -+ alpha*-*-*) -+ supported_defaults="cpu tune" -+ for which in cpu tune; do -+ eval "val=\$with_$which" -+ case "$val" in -+ "" \ -+ | ev4 | ev45 | 21064 | ev5 | 21164 | ev56 | 21164a \ -+ | pca56 | 21164PC | 21164pc | ev6 | 21264 | ev67 \ -+ | 21264a) -+ ;; -+ *) -+ echo "Unknown CPU used in --with-$which=$val" 1>&2 -+ exit 1 -+ ;; -+ esac -+ done -+ ;; -+ -+ arm*-*-*) -+ supported_defaults="arch cpu float tune fpu abi mode" -+ for which in cpu tune; do -+ # See if it matches any of the entries in arm-cores.def -+ eval "val=\$with_$which" -+ if [ x"$val" = x ] \ -+ || grep "^ARM_CORE(\"$val\"," \ -+ ${srcdir}/config/arm/arm-cores.def \ -+ > /dev/null; then -+ # Ok -+ new_val=`grep "^ARM_CORE(\"$val\"," \ -+ ${srcdir}/config/arm/arm-cores.def | \ -+ sed -e 's/^[^,]*,[ ]*//' | \ -+ sed -e 's/,.*$//'` -+ eval "target_${which}_cname=$new_val" -+ echo "For $val real value is $new_val" -+ true -+ else -+ echo "Unknown CPU used in --with-$which=$val" 1>&2 -+ exit 1 -+ fi -+ done -+ -+ case "$with_arch" in -+ "" \ -+ | armv[23456] | armv2a | armv3m | armv4t | armv5t \ -+ | armv5te | armv6j |armv6k | armv6z | armv6zk | armv6-m \ -+ | armv7 | armv7-a | armv7-r | armv7-m \ -+ | iwmmxt | ep9312) -+ # OK -+ ;; -+ *) -+ echo "Unknown arch used in --with-arch=$with_arch" 1>&2 -+ exit 1 -+ ;; -+ esac -+ -+ case "$with_float" in -+ "" \ -+ | soft | hard | softfp) -+ # OK -+ ;; -+ *) -+ echo "Unknown floating point type used in --with-float=$with_float" 1>&2 -+ exit 1 -+ ;; -+ esac -+ -+ case "$with_fpu" in -+ "" \ -+ | fpa | fpe2 | fpe3 | maverick | vfp | vfp3 | vfpv3 | vfpv3-d16 | neon ) -+ # OK -+ ;; -+ *) -+ echo "Unknown fpu used in --with-fpu=$with_fpu" 2>&1 -+ exit 1 -+ ;; -+ esac -+ -+ case "$with_abi" in -+ "" \ -+ | apcs-gnu | atpcs | aapcs | iwmmxt | aapcs-linux ) -+ #OK -+ ;; -+ *) -+ echo "Unknown ABI used in --with-abi=$with_abi" -+ exit 1 -+ ;; -+ esac -+ -+ case "$with_mode" in -+ "" \ -+ | arm | thumb ) -+ #OK -+ ;; -+ *) -+ echo "Unknown mode used in --with-mode=$with_mode" -+ exit 1 -+ ;; -+ esac -+ -+ if test "x$with_arch" != x && test "x$with_cpu" != x; then -+ echo "Warning: --with-arch overrides --with-cpu=$with_cpu" 1>&2 -+ fi -+ ;; -+ -+ fr*-*-*linux*) -+ supported_defaults=cpu -+ case "$with_cpu" in -+ fr400) ;; -+ fr550) ;; -+ *) -+ echo "Unknown cpu used in --with-cpu=$with_cpu" 1>&2 -+ exit 1 -+ ;; -+ esac -+ ;; -+ -+ fido-*-* | m68k*-*-*) -+ supported_defaults="arch cpu" -+ case "$with_arch" in -+ "" | "m68k"| "cf") -+ m68k_arch_family="$with_arch" -+ ;; -+ *) -+ echo "Invalid --with-arch=$with_arch" 1>&2 -+ exit 1 -+ ;; -+ esac -+ -+ # We always have a $with_cpu setting here. -+ case "$with_cpu" in -+ "m68000" | "m68010" | "m68020" | "m68030" | "m68040" | "m68060") -+ m68k_cpu_ident=$with_cpu -+ ;; -+ "m68020-40") -+ m68k_cpu_ident=m68020 -+ tm_defines="$tm_defines M68K_DEFAULT_TUNE=u68020_40" -+ ;; -+ "m68020-60") -+ m68k_cpu_ident=m68020 -+ tm_defines="$tm_defines M68K_DEFAULT_TUNE=u68020_60" -+ ;; -+ *) -+ # We need the C identifier rather than the string. -+ m68k_cpu_ident=`awk -v arg="\"$with_cpu\"" \ -+ 'BEGIN { FS="[ \t]*[,()][ \t]*" }; \ -+ $1 == "M68K_DEVICE" && $2 == arg { print $3 }' \ -+ ${srcdir}/config/m68k/m68k-devices.def` -+ if [ x"$m68k_cpu_ident" = x ] ; then -+ echo "Unknown CPU used in --with-cpu=$with_cpu" 1>&2 -+ exit 1 -+ fi -+ with_cpu="mcpu=$with_cpu" -+ ;; -+ esac -+ ;; -+ -+ hppa*-*-*) -+ supported_defaults="arch schedule" -+ -+ case "$with_arch" in -+ "" | 1.0 | 1.1 | 2.0) -+ # OK -+ ;; -+ *) -+ echo "Unknown architecture used in --with-arch=$with_arch" 1>&2 -+ exit 1 -+ ;; -+ esac -+ -+ case "$with_schedule" in -+ "" | 700 | 7100 | 7100LC | 7200 | 7300 | 8000) -+ # OK -+ ;; -+ *) -+ echo "Unknown processor used in --with-schedule=$with_schedule." 1>&2 -+ exit 1 -+ ;; -+ esac -+ ;; -+ -+ i[34567]86-*-* | x86_64-*-*) -+ supported_defaults="arch arch_32 arch_64 cpu cpu_32 cpu_64 tune tune_32 tune_64" -+ for which in arch arch_32 arch_64 cpu cpu_32 cpu_64 tune tune_32 tune_64; do -+ eval "val=\$with_$which" -+ case ${val} in -+ i386 | i486 \ -+ | i586 | pentium | pentium-mmx | winchip-c6 | winchip2 \ -+ | c3 | c3-2 | i686 | pentiumpro | pentium2 | pentium3 \ -+ | pentium4 | k6 | k6-2 | k6-3 | athlon | athlon-tbird \ -+ | athlon-4 | athlon-xp | athlon-mp | geode \ -+ | prescott | pentium-m | pentium4m | pentium3m) -+ case "${target}" in -+ x86_64-*-*) -+ case "x$which" in -+ *_32) -+ ;; -+ *) -+ echo "CPU given in --with-$which=$val doesn't support 64bit mode." 1>&2 -+ exit 1 -+ ;; -+ esac -+ ;; -+ esac -+ # OK -+ ;; -+ "" | amdfam10 | barcelona | k8-sse3 | opteron-sse3 | athlon64-sse3 | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | generic) -+ # OK -+ ;; -+ *) -+ echo "Unknown CPU given in --with-$which=$val." 1>&2 -+ exit 1 -+ ;; -+ esac -+ done -+ ;; -+ -+ mips*-*-*) -+ supported_defaults="abi arch float tune divide llsc mips-plt" -+ -+ case ${with_float} in -+ "" | soft | hard) -+ # OK -+ ;; -+ *) -+ echo "Unknown floating point type used in --with-float=$with_float" 1>&2 -+ exit 1 -+ ;; -+ esac -+ -+ case ${with_abi} in -+ "" | 32 | o64 | n32 | 64 | eabi) -+ # OK -+ ;; -+ *) -+ echo "Unknown ABI used in --with-abi=$with_abi" 1>&2 -+ exit 1 -+ ;; -+ esac -+ -+ case ${with_divide} in -+ "" | breaks | traps) -+ # OK -+ ;; -+ *) -+ echo "Unknown division check type use in --with-divide=$with_divide" 1>&2 -+ exit 1 -+ ;; -+ esac -+ -+ case ${with_llsc} in -+ yes) -+ with_llsc=llsc -+ ;; -+ no) -+ with_llsc="no-llsc" -+ ;; -+ "") -+ # OK -+ ;; -+ *) -+ echo "Unknown llsc type used in --with-llsc" 1>&2 -+ exit 1 -+ ;; -+ esac -+ -+ case ${with_mips_plt} in -+ yes) -+ with_mips_plt=plt -+ ;; -+ no) -+ with_mips_plt=no-plt -+ ;; -+ "") -+ ;; -+ *) -+ echo "Unknown --with-mips-plt argument: $with_mips_plt" 1>&2 -+ exit 1 -+ ;; -+ esac -+ ;; -+ -+ powerpc*-*-* | rs6000-*-*) -+ supported_defaults="cpu float tune" -+ -+ for which in cpu tune; do -+ eval "val=\$with_$which" -+ case ${val} in -+ default32 | default64) -+ with_which="with_$which" -+ eval $with_which= -+ ;; -+ 405cr) -+ tm_defines="${tm_defines} CONFIG_PPC405CR" -+ eval "with_$which=405" -+ ;; -+ "" | common \ -+ | power | power[234567] | power6x | powerpc | powerpc64 \ -+ | rios | rios1 | rios2 | rsc | rsc1 | rs64a \ -+ | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \ -+ | 505 | 601 | 602 | 603 | 603e | ec603e | 604 \ -+ | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \ -+ | e300c[23] | 854[08] | e500mc \ -+ | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell) -+ # OK -+ ;; -+ *) -+ echo "Unknown cpu used in --with-$which=$val." 1>&2 -+ exit 1 -+ ;; -+ esac -+ done -+ ;; -+ -+ s390*-*-*) -+ supported_defaults="arch mode tune" -+ -+ for which in arch tune; do -+ eval "val=\$with_$which" -+ case ${val} in -+ "" | g5 | g6 | z900 | z990 | z9-109 | z9-ec | z10) -+ # OK -+ ;; -+ *) -+ echo "Unknown cpu used in --with-$which=$val." 1>&2 -+ exit 1 -+ ;; -+ esac -+ done -+ -+ case ${with_mode} in -+ "" | esa | zarch) -+ # OK -+ ;; -+ *) -+ echo "Unknown architecture mode used in --with-mode=$with_mode." 1>&2 -+ exit 1 -+ ;; -+ esac -+ ;; -+ -+ sh[123456ble]-*-* | sh-*-*) -+ supported_defaults="cpu" -+ case "`echo $with_cpu | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz- | sed s/sh/m/`" in -+ "" | m1 | m2 | m2e | m3 | m3e | m4 | m4-single | m4-single-only | m4-nofpu ) -+ # OK -+ ;; -+ m2a | m2a-single | m2a-single-only | m2a-nofpu) -+ ;; -+ m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) -+ ;; -+ *) -+ echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 -+ echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 -+ echo "m4a m4a-single m4a-single-only m4a-nofpu m4al" 1>&2 -+ echo "m2a m2a-single m2a-single-only m2a-nofpu" 1>&2 -+ exit 1 -+ ;; -+ esac -+ ;; -+ sparc*-*-*) -+ supported_defaults="cpu float tune" -+ -+ for which in cpu tune; do -+ eval "val=\$with_$which" -+ case ${val} in -+ "" | sparc | sparcv9 | sparc64 | sparc86x \ -+ | v7 | cypress | v8 | supersparc | sparclite | f930 \ -+ | f934 | hypersparc | sparclite86x | sparclet | tsc701 \ -+ | v9 | ultrasparc | ultrasparc3 | niagara | niagara2) -+ # OK -+ ;; -+ *) -+ echo "Unknown cpu used in --with-$which=$val" 1>&2 -+ exit 1 -+ ;; -+ esac -+ done -+ -+ case ${with_float} in -+ "" | soft | hard) -+ # OK -+ ;; -+ *) -+ echo "Unknown floating point type used in --with-float=$with_float" 1>&2 -+ exit 1 -+ ;; -+ esac -+ ;; -+ -+ spu-*-*) -+ supported_defaults="arch tune" -+ -+ for which in arch tune; do -+ eval "val=\$with_$which" -+ case ${val} in -+ "" | cell | celledp) -+ # OK -+ ;; -+ *) -+ echo "Unknown cpu used in --with-$which=$val." 1>&2 -+ exit 1 -+ ;; -+ esac -+ done -+ ;; -+ -+ v850*-*-*) -+ supported_defaults=cpu -+ case ${with_cpu} in -+ "" | v850e | v850e1) -+ # OK -+ ;; -+ *) -+ echo "Unknown cpu used in --with-cpu=$with_cpu" 1>&2 -+ exit 1 -+ ;; -+ esac -+ ;; -+esac -+ -+# Set some miscellaneous flags for particular targets. -+target_cpu_default2= -+case ${target} in -+ alpha*-*-*) -+ if test x$gas = xyes -+ then -+ target_cpu_default2="MASK_GAS" -+ fi -+ ;; -+ -+ arm*-*-*) -+ if test x$target_cpu_cname = x -+ then -+ target_cpu_default2=TARGET_CPU_generic -+ else -+ target_cpu_default2=TARGET_CPU_$target_cpu_cname -+ fi -+ ;; -+ -+ hppa*-*-*) -+ target_cpu_default2="MASK_BIG_SWITCH" -+ if test x$gas = xyes -+ then -+ target_cpu_default2="${target_cpu_default2}|MASK_GAS|MASK_JUMP_IN_DELAY" -+ fi -+ ;; -+ -+ fido*-*-* | m68k*-*-*) -+ target_cpu_default2=$m68k_cpu_ident -+ if [ x"$m68k_arch_family" != x ]; then -+ tmake_file="m68k/t-$m68k_arch_family $tmake_file" -+ fi -+ ;; -+ -+ i[34567]86-*-darwin* | x86_64-*-darwin*) -+ tmake_file="${tmake_file} i386/t-fprules-softfp soft-fp/t-softfp" -+ ;; -+ i[34567]86-*-linux* | x86_64-*-linux* | i[34567]86-*-kfreebsd*-gnu | x86_64-*-kfreebsd*-gnu) -+ tmake_file="${tmake_file} i386/t-fprules-softfp soft-fp/t-softfp i386/t-linux" -+ ;; -+ ia64*-*-linux*) -+ tmake_file="${tmake_file} ia64/t-fprules-softfp soft-fp/t-softfp" -+ ;; -+ -+ mips*-*-*) -+ if test x$gnu_ld = xyes -+ then -+ target_cpu_default2="MASK_SPLIT_ADDRESSES" -+ fi -+ case ${target} in -+ mips*el-*-*) -+ tm_defines="TARGET_ENDIAN_DEFAULT=0 $tm_defines" -+ ;; -+ esac -+ if test "x$enable_gofast" = xyes -+ then -+ tm_defines="US_SOFTWARE_GOFAST $tm_defines" -+ tmake_file="mips/t-gofast $tmake_file" -+ else -+ tmake_file="mips/t-mips $tmake_file" -+ fi -+ ;; -+ -+ powerpc*-*-* | rs6000-*-*) -+ # FIXME: The PowerPC port uses the value set at compile time, -+ # although it's only cosmetic. -+ if test "x$with_cpu" != x -+ then -+ target_cpu_default2="\\\"$with_cpu\\\"" -+ fi -+ out_file=rs6000/rs6000.c -+ c_target_objs="${c_target_objs} rs6000-c.o" -+ cxx_target_objs="${cxx_target_objs} rs6000-c.o" -+ tmake_file="rs6000/t-rs6000 ${tmake_file}" -+ -+ if test x$enable_e500_double = xyes -+ then -+ tm_file="$tm_file rs6000/e500-double.h" -+ fi -+ ;; -+ -+ sh[123456ble]*-*-* | sh-*-*) -+ c_target_objs="${c_target_objs} sh-c.o" -+ cxx_target_objs="${cxx_target_objs} sh-c.o" -+ ;; -+ -+ sparc*-*-*) -+ # Some standard aliases. -+ case x$with_cpu in -+ xsparc) -+ with_cpu=v7 -+ ;; -+ xsparcv9 | xsparc64) -+ with_cpu=v9 -+ ;; -+ esac -+ -+ # The SPARC port checks this value at compile-time. -+ target_cpu_default2="TARGET_CPU_$with_cpu" -+ ;; -+ v850*-*-*) -+ # FIXME: The v850 is "special" in that it does not support -+ # runtime CPU selection, only --with-cpu. -+ case "x$with_cpu" in -+ x) -+ ;; -+ xv850e) -+ target_cpu_default2="TARGET_CPU_$with_cpu" -+ ;; -+ esac -+ ;; -+esac -+ -+t= -+all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu divide llsc mips-plt" -+for option in $all_defaults -+do -+ eval "val=\$with_"`echo $option | sed s/-/_/g` -+ if test -n "$val"; then -+ case " $supported_defaults " in -+ *" $option "*) -+ ;; -+ *) -+ echo "This target does not support --with-$option." 2>&1 -+ echo "Valid --with options are: $supported_defaults" 2>&1 -+ exit 1 -+ ;; -+ esac -+ -+ if test "x$t" = x -+ then -+ t="{ \"$option\", \"$val\" }" -+ else -+ t="${t}, { \"$option\", \"$val\" }" -+ fi -+ fi -+done -+ -+if test "x$t" = x -+then -+ configure_default_options="{ { NULL, NULL} }" -+else -+ configure_default_options="{ ${t} }" -+fi -+ -+if test "$target_cpu_default2" != "" -+then -+ if test "$target_cpu_default" != "" -+ then -+ target_cpu_default="(${target_cpu_default}|${target_cpu_default2})" -+ else -+ target_cpu_default=$target_cpu_default2 -+ fi -+fi -diff -Nur gcc-4.4.6.orig/gcc/configure.ac gcc-4.4.6/gcc/configure.ac ---- gcc-4.4.6.orig/gcc/configure.ac 2010-12-13 19:19:43.000000000 +0100 -+++ gcc-4.4.6/gcc/configure.ac 2011-08-27 19:45:43.687987316 +0200 -@@ -2240,10 +2240,9 @@ - as_ver=`$gcc_cv_as --version 2>/dev/null | sed 1q` - if echo "$as_ver" | grep GNU > /dev/null; then - changequote(,)dnl -- as_vers=`echo $as_ver | sed -n \ -- -e 's,^.*[ ]\([0-9][0-9]*\.[0-9][0-9]*.*\)$,\1,p'` -- as_major=`expr "$as_vers" : '\([0-9]*\)'` -- as_minor=`expr "$as_vers" : '[0-9]*\.\([0-9]*\)'` -+ as_ver=`echo $as_ver | sed -e 's/GNU assembler\( (GNU Binutils)\)\? \([0-9.][0-9.]*\).*/\2/'` -+ as_major=`echo $as_ver | sed 's/\..*//'` -+ as_minor=`echo $as_ver | sed 's/[^.]*\.\([0-9]*\).*/\1/'` - changequote([,])dnl - if test $as_major -eq 2 && test $as_minor -lt 11 - then : -@@ -3308,7 +3307,7 @@ - i?86*-*-* | mips*-*-* | alpha*-*-* | powerpc*-*-* | sparc*-*-* | m68*-*-* \ - | x86_64*-*-* | hppa*-*-* | arm*-*-* \ - | xstormy16*-*-* | cris-*-* | crisv32-*-* | xtensa*-*-* | bfin-*-* | score*-*-* \ -- | spu-*-* | fido*-*-* | m32c-*-*) -+ | spu-*-* | fido*-*-* | m32c-*-* | avr32-*-*) - insn="nop" - ;; - ia64*-*-* | s390*-*-*) -diff -Nur gcc-4.4.6.orig/gcc/doc/extend.texi gcc-4.4.6/gcc/doc/extend.texi ---- gcc-4.4.6.orig/gcc/doc/extend.texi 2011-03-23 22:45:18.000000000 +0100 -+++ gcc-4.4.6/gcc/doc/extend.texi 2011-08-27 19:45:43.717990492 +0200 -@@ -2397,7 +2397,7 @@ - - @item interrupt - @cindex interrupt handler functions --Use this attribute on the ARM, AVR, CRX, M32C, M32R/D, m68k, -+Use this attribute on the ARM, AVR, AVR32, CRX, M32C, M32R/D, m68k, - and Xstormy16 ports to indicate that the specified function is an - interrupt handler. The compiler will generate function entry and exit - sequences suitable for use in an interrupt handler when this attribute -@@ -2417,6 +2417,15 @@ - - Permissible values for this parameter are: IRQ, FIQ, SWI, ABORT and UNDEF@. - -+Note, for the AVR32, you can specify which banking scheme is used for -+the interrupt mode this interrupt handler is used in like this: -+ -+@smallexample -+void f () __attribute__ ((interrupt ("FULL"))); -+@end smallexample -+ -+Permissible values for this parameter are: FULL, HALF, NONE and UNDEF. -+ - On ARMv7-M the interrupt type is ignored, and the attribute means the function - may be called with a word aligned stack pointer. - -@@ -4188,6 +4197,23 @@ - - @end table - -+@subsection AVR32 Variable Attributes -+ -+One attribute is currently defined for AVR32 configurations: -+@code{rmw_addressable} -+ -+@table @code -+@item rmw_addressable -+@cindex @code{rmw_addressable} attribute -+ -+This attribute can be used to signal that a variable can be accessed -+with the addressing mode of the AVR32 Atomic Read-Modify-Write memory -+instructions and hence make it possible for gcc to generate these -+instructions without using built-in functions or inline assembly statements. -+Variables used within the AVR32 Atomic Read-Modify-Write built-in -+functions will automatically get the @code{rmw_addressable} attribute. -+@end table -+ - @subsection AVR Variable Attributes - - @table @code -@@ -7042,6 +7068,7 @@ - * Alpha Built-in Functions:: - * ARM iWMMXt Built-in Functions:: - * ARM NEON Intrinsics:: -+* AVR32 Built-in Functions:: - * Blackfin Built-in Functions:: - * FR-V Built-in Functions:: - * X86 Built-in Functions:: -@@ -7284,6 +7311,7 @@ - long long __builtin_arm_wzero () - @end smallexample - -+ - @node ARM NEON Intrinsics - @subsection ARM NEON Intrinsics - -@@ -7292,6 +7320,74 @@ - - @include arm-neon-intrinsics.texi - -+@node AVR32 Built-in Functions -+@subsection AVR32 Built-in Functions -+ -+Built-in functions for atomic memory (RMW) instructions. Note that these -+built-ins will fail for targets where the RMW instructions are not -+implemented. Also note that these instructions only that a Ks15 << 2 -+memory address and will therefor not work with any runtime computed -+memory addresses. The user is responsible for making sure that any -+pointers used within these functions points to a valid memory address. -+ -+@smallexample -+void __builtin_mems(int */*ptr*/, int /*bit*/) -+void __builtin_memc(int */*ptr*/, int /*bit*/) -+void __builtin_memt(int */*ptr*/, int /*bit*/) -+@end smallexample -+ -+Built-in functions for DSP instructions. Note that these built-ins will -+fail for targets where the DSP instructions are not implemented. -+ -+@smallexample -+int __builtin_sats (int /*Rd*/,int /*sa*/, int /*bn*/) -+int __builtin_satu (int /*Rd*/,int /*sa*/, int /*bn*/) -+int __builtin_satrnds (int /*Rd*/,int /*sa*/, int /*bn*/) -+int __builtin_satrndu (int /*Rd*/,int /*sa*/, int /*bn*/) -+short __builtin_mulsathh_h (short, short) -+int __builtin_mulsathh_w (short, short) -+short __builtin_mulsatrndhh_h (short, short) -+int __builtin_mulsatrndwh_w (int, short) -+int __builtin_mulsatwh_w (int, short) -+int __builtin_macsathh_w (int, short, short) -+short __builtin_satadd_h (short, short) -+short __builtin_satsub_h (short, short) -+int __builtin_satadd_w (int, int) -+int __builtin_satsub_w (int, int) -+long long __builtin_mulwh_d(int, short) -+long long __builtin_mulnwh_d(int, short) -+long long __builtin_macwh_d(long long, int, short) -+long long __builtin_machh_d(long long, short, short) -+@end smallexample -+ -+Other built-in functions for instructions that cannot easily be -+generated by the compiler. -+ -+@smallexample -+void __builtin_ssrf(int); -+void __builtin_csrf(int); -+void __builtin_musfr(int); -+int __builtin_mustr(void); -+int __builtin_mfsr(int /*Status Register Address*/) -+void __builtin_mtsr(int /*Status Register Address*/, int /*Value*/) -+int __builtin_mfdr(int /*Debug Register Address*/) -+void __builtin_mtdr(int /*Debug Register Address*/, int /*Value*/) -+void __builtin_cache(void * /*Address*/, int /*Cache Operation*/) -+void __builtin_sync(int /*Sync Operation*/) -+void __builtin_tlbr(void) -+void __builtin_tlbs(void) -+void __builtin_tlbw(void) -+void __builtin_breakpoint(void) -+int __builtin_xchg(void * /*Address*/, int /*Value*/ ) -+short __builtin_bswap_16(short) -+int __builtin_bswap_32(int) -+void __builtin_cop(int/*cpnr*/, int/*crd*/, int/*crx*/, int/*cry*/, int/*op*/) -+int __builtin_mvcr_w(int/*cpnr*/, int/*crs*/) -+void __builtin_mvrc_w(int/*cpnr*/, int/*crd*/, int/*value*/) -+long long __builtin_mvcr_d(int/*cpnr*/, int/*crs*/) -+void __builtin_mvrc_d(int/*cpnr*/, int/*crd*/, long long/*value*/) -+@end smallexample -+ - @node Blackfin Built-in Functions - @subsection Blackfin Built-in Functions - -diff -Nur gcc-4.4.6.orig/gcc/doc/invoke.texi gcc-4.4.6/gcc/doc/invoke.texi ---- gcc-4.4.6.orig/gcc/doc/invoke.texi 2011-03-23 23:02:12.000000000 +0100 -+++ gcc-4.4.6/gcc/doc/invoke.texi 2011-08-27 19:45:43.767989627 +0200 -@@ -195,7 +195,7 @@ - -fvisibility-ms-compat @gol - -Wabi -Wctor-dtor-privacy @gol - -Wnon-virtual-dtor -Wreorder @gol ---Weffc++ -Wstrict-null-sentinel @gol -+-Weffc++ -Wno-deprecated @gol - -Wno-non-template-friend -Wold-style-cast @gol - -Woverloaded-virtual -Wno-pmf-conversions @gol - -Wsign-promo} -@@ -641,6 +641,12 @@ - -mauto-incdec -minmax -mlong-calls -mshort @gol - -msoft-reg-count=@var{count}} - -+@emph{AVR32 Options} -+@gccoptlist{-muse-rodata-section -mhard-float -msoft-float -mrelax @gol -+-mforce-double-align -mno-init-got -mrelax -mmd-reorg-opt -masm-addr-pseudos @gol -+-mpart=@var{part} -mcpu=@var{cpu} -march=@var{arch} @gol -+-mfast-float -mimm-in-const-pool} -+ - @emph{MCore Options} - @gccoptlist{-mhardlit -mno-hardlit -mdiv -mno-div -mrelax-immediates @gol - -mno-relax-immediates -mwide-bitfields -mno-wide-bitfields @gol -@@ -3256,13 +3262,11 @@ - If you want to warn about code which uses the uninitialized value of the - variable in its own initializer, use the @option{-Winit-self} option. - --These warnings occur for individual uninitialized or clobbered --elements of structure, union or array variables as well as for --variables which are uninitialized or clobbered as a whole. They do --not occur for variables or elements declared @code{volatile}. Because --these warnings depend on optimization, the exact variables or elements --for which there are warnings will depend on the precise optimization --options and version of GCC used. -+These warnings occur only for variables that are candidates for -+register allocation. Therefore, they do not occur for a variable that -+is declared @code{volatile}, or whose address is taken, or whose size -+is other than 1, 2, 4 or 8 bytes. Also, they do not occur for -+structures, unions or arrays, even when they are in registers. - - Note that there may be no warning about a variable that is used only - to compute a value that itself is never used, because such -@@ -7445,10 +7449,6 @@ - we always try to remove unnecessary ivs from the set during its - optimization when a new iv is added to the set. - --@item scev-max-expr-size --Bound on size of expressions used in the scalar evolutions analyzer. --Large expressions slow the analyzer. -- - @item omega-max-vars - The maximum number of variables in an Omega constraint system. - The default value is 128. -@@ -8844,6 +8844,7 @@ - * ARC Options:: - * ARM Options:: - * AVR Options:: -+* AVR32 Options:: - * Blackfin Options:: - * CRIS Options:: - * CRX Options:: -@@ -9332,6 +9333,145 @@ - size. - @end table - -+@node AVR32 Options -+@subsection AVR32 Options -+@cindex AVR32 Options -+ -+These options are defined for AVR32 implementations: -+ -+@table @gcctabopt -+@item -muse-rodata-section -+@opindex muse-rodata-section -+Use section @samp{.rodata} for read-only data instead of @samp{.text}. -+ -+@item -mhard-float -+@opindex mhard-float -+Use floating point coprocessor instructions. -+ -+@item -msoft-float -+@opindex msoft-float -+Use software floating-point library for floating-point operations. -+ -+@item -mforce-double-align -+@opindex mforce-double-align -+Force double-word alignment for double-word memory accesses. -+ -+@item -masm-addr-pseudos -+@opindex masm-addr-pseudos -+Use assembler pseudo-instructions lda.w and call for handling direct -+addresses. (Enabled by default) -+ -+@item -mno-init-got -+@opindex mno-init-got -+Do not initialize the GOT register before using it when compiling PIC -+code. -+ -+@item -mrelax -+@opindex mrelax -+Let invoked assembler and linker do relaxing -+(Enabled by default when optimization level is >1). -+This means that when the address of symbols are known at link time, -+the linker can optimize @samp{icall} and @samp{mcall} -+instructions into a @samp{rcall} instruction if possible. -+Loading the address of a symbol can also be optimized. -+ -+@item -mmd-reorg-opt -+@opindex mmd-reorg-opt -+Perform machine dependent optimizations in reorg stage. -+ -+@item -mpart=@var{part} -+@opindex mpart -+Generate code for the specified part. Permissible parts are: -+@samp{ap7000}, -+@samp{ap7001}, -+@samp{ap7002}, -+@samp{ap7200}, -+@samp{uc3a0128}, -+@samp{uc3a0256}, -+@samp{uc3a0512}, -+@samp{uc3a0512es}, -+@samp{uc3a1128}, -+@samp{uc3a1256}, -+@samp{uc3a1512}, -+@samp{uc3a1512es}, -+@samp{uc3a3revd}, -+@samp{uc3a364}, -+@samp{uc3a364s}, -+@samp{uc3a3128}, -+@samp{uc3a3128s}, -+@samp{uc3a3256}, -+@samp{uc3a3256s}, -+@samp{uc3a464}, -+@samp{uc3a464s}, -+@samp{uc3a4128}, -+@samp{uc3a4128s}, -+@samp{uc3a4256}, -+@samp{uc3a4256s}, -+@samp{uc3b064}, -+@samp{uc3b0128}, -+@samp{uc3b0256}, -+@samp{uc3b0256es}, -+@samp{uc3b0512}, -+@samp{uc3b0512revc}, -+@samp{uc3b164}, -+@samp{uc3b1128}, -+@samp{uc3b1256}, -+@samp{uc3b1256es}, -+@samp{uc3b1512}, -+@samp{uc3b1512revc} -+@samp{uc64d3}, -+@samp{uc128d3}, -+@samp{uc64d4}, -+@samp{uc128d4}, -+@samp{uc3c0512crevc}, -+@samp{uc3c1512crevc}, -+@samp{uc3c2512crevc}, -+@samp{uc3l0256}, -+@samp{uc3l0128}, -+@samp{uc3l064}, -+@samp{uc3l032}, -+@samp{uc3l016}, -+@samp{uc3l064revb}, -+@samp{uc64l3u}, -+@samp{uc128l3u}, -+@samp{uc256l3u}, -+@samp{uc64l4u}, -+@samp{uc128l4u}, -+@samp{uc256l4u}, -+@samp{uc3c064c}, -+@samp{uc3c0128c}, -+@samp{uc3c0256c}, -+@samp{uc3c0512c}, -+@samp{uc3c164c}, -+@samp{uc3c1128c}, -+@samp{uc3c1256c}, -+@samp{uc3c1512c}, -+@samp{uc3c264c}, -+@samp{uc3c2128c}, -+@samp{uc3c2256c}, -+@samp{uc3c2512c}, -+@samp{mxt768e}. -+ -+@item -mcpu=@var{cpu-type} -+@opindex mcpu -+Same as -mpart. Obsolete. -+ -+@item -march=@var{arch} -+@opindex march -+Generate code for the specified architecture. Permissible architectures are: -+@samp{ap}, @samp{uc} and @samp{ucr2}. -+ -+@item -mfast-float -+@opindex mfast-float -+Enable fast floating-point library that does not conform to IEEE-754 but is still good enough -+for most applications. The fast floating-point library does not round to the nearest even -+but away from zero. Enabled by default if the -funsafe-math-optimizations switch is specified. -+ -+@item -mimm-in-const-pool -+@opindex mimm-in-const-pool -+Put large immediates in constant pool. This is enabled by default for archs with insn-cache. -+@end table -+ - @node Blackfin Options - @subsection Blackfin Options - @cindex Blackfin Options -@@ -9387,29 +9527,12 @@ - contain speculative loads after jump instructions. If this option is used, - @code{__WORKAROUND_SPECULATIVE_LOADS} is defined. - --@item -mno-specld-anomaly --@opindex mno-specld-anomaly --Don't generate extra code to prevent speculative loads from occurring. -- - @item -mcsync-anomaly - @opindex mcsync-anomaly - When enabled, the compiler will ensure that the generated code does not - contain CSYNC or SSYNC instructions too soon after conditional branches. - If this option is used, @code{__WORKAROUND_SPECULATIVE_SYNCS} is defined. - --@item -mno-csync-anomaly --@opindex mno-csync-anomaly --Don't generate extra code to prevent CSYNC or SSYNC instructions from --occurring too soon after a conditional branch. -- --@item -mlow-64k --@opindex mlow-64k --When enabled, the compiler is free to take advantage of the knowledge that --the entire program fits into the low 64k of memory. -- --@item -mno-low-64k --@opindex mno-low-64k --Assume that the program is arbitrarily large. This is the default. - - @item -mstack-check-l1 - @opindex mstack-check-l1 -@@ -9423,11 +9546,6 @@ - without virtual memory management. This option implies @option{-fPIC}. - With a @samp{bfin-elf} target, this option implies @option{-msim}. - --@item -mno-id-shared-library --@opindex mno-id-shared-library --Generate code that doesn't assume ID based shared libraries are being used. --This is the default. -- - @item -mleaf-id-shared-library - @opindex mleaf-id-shared-library - Generate code that supports shared libraries via the library ID method, -@@ -9469,11 +9587,6 @@ - will lie outside of the 24 bit addressing range of the offset based - version of subroutine call instruction. - --This feature is not enabled by default. Specifying --@option{-mno-long-calls} will restore the default behavior. Note these --switches have no effect on how the compiler generates code to handle --function calls via function pointers. -- - @item -mfast-fp - @opindex mfast-fp - Link with the fast floating-point library. This library relaxes some of -diff -Nur gcc-4.4.6.orig/gcc/doc/invoke.texi.orig gcc-4.4.6/gcc/doc/invoke.texi.orig ---- gcc-4.4.6.orig/gcc/doc/invoke.texi.orig 1970-01-01 01:00:00.000000000 +0100 -+++ gcc-4.4.6/gcc/doc/invoke.texi.orig 2011-03-23 23:02:12.000000000 +0100 -@@ -0,0 +1,16654 @@ -+@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -+@c 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 -+@c Free Software Foundation, Inc. -+@c This is part of the GCC manual. -+@c For copying conditions, see the file gcc.texi. -+ -+@ignore -+@c man begin INCLUDE -+@include gcc-vers.texi -+@c man end -+ -+@c man begin COPYRIGHT -+Copyright @copyright{} 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -+1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 -+Free Software Foundation, Inc. -+ -+Permission is granted to copy, distribute and/or modify this document -+under the terms of the GNU Free Documentation License, Version 1.2 or -+any later version published by the Free Software Foundation; with the -+Invariant Sections being ``GNU General Public License'' and ``Funding -+Free Software'', the Front-Cover texts being (a) (see below), and with -+the Back-Cover Texts being (b) (see below). A copy of the license is -+included in the gfdl(7) man page. -+ -+(a) The FSF's Front-Cover Text is: -+ -+ A GNU Manual -+ -+(b) The FSF's Back-Cover Text is: -+ -+ You have freedom to copy and modify this GNU Manual, like GNU -+ software. Copies published by the Free Software Foundation raise -+ funds for GNU development. -+@c man end -+@c Set file name and title for the man page. -+@setfilename gcc -+@settitle GNU project C and C++ compiler -+@c man begin SYNOPSIS -+gcc [@option{-c}|@option{-S}|@option{-E}] [@option{-std=}@var{standard}] -+ [@option{-g}] [@option{-pg}] [@option{-O}@var{level}] -+ [@option{-W}@var{warn}@dots{}] [@option{-pedantic}] -+ [@option{-I}@var{dir}@dots{}] [@option{-L}@var{dir}@dots{}] -+ [@option{-D}@var{macro}[=@var{defn}]@dots{}] [@option{-U}@var{macro}] -+ [@option{-f}@var{option}@dots{}] [@option{-m}@var{machine-option}@dots{}] -+ [@option{-o} @var{outfile}] [@@@var{file}] @var{infile}@dots{} -+ -+Only the most useful options are listed here; see below for the -+remainder. @samp{g++} accepts mostly the same options as @samp{gcc}. -+@c man end -+@c man begin SEEALSO -+gpl(7), gfdl(7), fsf-funding(7), -+cpp(1), gcov(1), as(1), ld(1), gdb(1), adb(1), dbx(1), sdb(1) -+and the Info entries for @file{gcc}, @file{cpp}, @file{as}, -+@file{ld}, @file{binutils} and @file{gdb}. -+@c man end -+@c man begin BUGS -+For instructions on reporting bugs, see -+@w{@value{BUGURL}}. -+@c man end -+@c man begin AUTHOR -+See the Info entry for @command{gcc}, or -+@w{@uref{http://gcc.gnu.org/onlinedocs/gcc/Contributors.html}}, -+for contributors to GCC@. -+@c man end -+@end ignore -+ -+@node Invoking GCC -+@chapter GCC Command Options -+@cindex GCC command options -+@cindex command options -+@cindex options, GCC command -+ -+@c man begin DESCRIPTION -+When you invoke GCC, it normally does preprocessing, compilation, -+assembly and linking. The ``overall options'' allow you to stop this -+process at an intermediate stage. For example, the @option{-c} option -+says not to run the linker. Then the output consists of object files -+output by the assembler. -+ -+Other options are passed on to one stage of processing. Some options -+control the preprocessor and others the compiler itself. Yet other -+options control the assembler and linker; most of these are not -+documented here, since you rarely need to use any of them. -+ -+@cindex C compilation options -+Most of the command line options that you can use with GCC are useful -+for C programs; when an option is only useful with another language -+(usually C++), the explanation says so explicitly. If the description -+for a particular option does not mention a source language, you can use -+that option with all supported languages. -+ -+@cindex C++ compilation options -+@xref{Invoking G++,,Compiling C++ Programs}, for a summary of special -+options for compiling C++ programs. -+ -+@cindex grouping options -+@cindex options, grouping -+The @command{gcc} program accepts options and file names as operands. Many -+options have multi-letter names; therefore multiple single-letter options -+may @emph{not} be grouped: @option{-dv} is very different from @w{@samp{-d -+-v}}. -+ -+@cindex order of options -+@cindex options, order -+You can mix options and other arguments. For the most part, the order -+you use doesn't matter. Order does matter when you use several -+options of the same kind; for example, if you specify @option{-L} more -+than once, the directories are searched in the order specified. Also, -+the placement of the @option{-l} option is significant. -+ -+Many options have long names starting with @samp{-f} or with -+@samp{-W}---for example, -+@option{-fmove-loop-invariants}, @option{-Wformat} and so on. Most of -+these have both positive and negative forms; the negative form of -+@option{-ffoo} would be @option{-fno-foo}. This manual documents -+only one of these two forms, whichever one is not the default. -+ -+@c man end -+ -+@xref{Option Index}, for an index to GCC's options. -+ -+@menu -+* Option Summary:: Brief list of all options, without explanations. -+* Overall Options:: Controlling the kind of output: -+ an executable, object files, assembler files, -+ or preprocessed source. -+* Invoking G++:: Compiling C++ programs. -+* C Dialect Options:: Controlling the variant of C language compiled. -+* C++ Dialect Options:: Variations on C++. -+* Objective-C and Objective-C++ Dialect Options:: Variations on Objective-C -+ and Objective-C++. -+* Language Independent Options:: Controlling how diagnostics should be -+ formatted. -+* Warning Options:: How picky should the compiler be? -+* Debugging Options:: Symbol tables, measurements, and debugging dumps. -+* Optimize Options:: How much optimization? -+* Preprocessor Options:: Controlling header files and macro definitions. -+ Also, getting dependency information for Make. -+* Assembler Options:: Passing options to the assembler. -+* Link Options:: Specifying libraries and so on. -+* Directory Options:: Where to find header files and libraries. -+ Where to find the compiler executable files. -+* Spec Files:: How to pass switches to sub-processes. -+* Target Options:: Running a cross-compiler, or an old version of GCC. -+* Submodel Options:: Specifying minor hardware or convention variations, -+ such as 68010 vs 68020. -+* Code Gen Options:: Specifying conventions for function calls, data layout -+ and register usage. -+* Environment Variables:: Env vars that affect GCC. -+* Precompiled Headers:: Compiling a header once, and using it many times. -+* Running Protoize:: Automatically adding or removing function prototypes. -+@end menu -+ -+@c man begin OPTIONS -+ -+@node Option Summary -+@section Option Summary -+ -+Here is a summary of all the options, grouped by type. Explanations are -+in the following sections. -+ -+@table @emph -+@item Overall Options -+@xref{Overall Options,,Options Controlling the Kind of Output}. -+@gccoptlist{-c -S -E -o @var{file} -combine -pipe -pass-exit-codes @gol -+-x @var{language} -v -### --help@r{[}=@var{class}@r{[},@dots{}@r{]]} --target-help @gol -+--version -wrapper@@@var{file}} -+ -+@item C Language Options -+@xref{C Dialect Options,,Options Controlling C Dialect}. -+@gccoptlist{-ansi -std=@var{standard} -fgnu89-inline @gol -+-aux-info @var{filename} @gol -+-fno-asm -fno-builtin -fno-builtin-@var{function} @gol -+-fhosted -ffreestanding -fopenmp -fms-extensions @gol -+-trigraphs -no-integrated-cpp -traditional -traditional-cpp @gol -+-fallow-single-precision -fcond-mismatch -flax-vector-conversions @gol -+-fsigned-bitfields -fsigned-char @gol -+-funsigned-bitfields -funsigned-char} -+ -+@item C++ Language Options -+@xref{C++ Dialect Options,,Options Controlling C++ Dialect}. -+@gccoptlist{-fabi-version=@var{n} -fno-access-control -fcheck-new @gol -+-fconserve-space -ffriend-injection @gol -+-fno-elide-constructors @gol -+-fno-enforce-eh-specs @gol -+-ffor-scope -fno-for-scope -fno-gnu-keywords @gol -+-fno-implicit-templates @gol -+-fno-implicit-inline-templates @gol -+-fno-implement-inlines -fms-extensions @gol -+-fno-nonansi-builtins -fno-operator-names @gol -+-fno-optional-diags -fpermissive @gol -+-frepo -fno-rtti -fstats -ftemplate-depth-@var{n} @gol -+-fno-threadsafe-statics -fuse-cxa-atexit -fno-weak -nostdinc++ @gol -+-fno-default-inline -fvisibility-inlines-hidden @gol -+-fvisibility-ms-compat @gol -+-Wabi -Wctor-dtor-privacy @gol -+-Wnon-virtual-dtor -Wreorder @gol -+-Weffc++ -Wstrict-null-sentinel @gol -+-Wno-non-template-friend -Wold-style-cast @gol -+-Woverloaded-virtual -Wno-pmf-conversions @gol -+-Wsign-promo} -+ -+@item Objective-C and Objective-C++ Language Options -+@xref{Objective-C and Objective-C++ Dialect Options,,Options Controlling -+Objective-C and Objective-C++ Dialects}. -+@gccoptlist{-fconstant-string-class=@var{class-name} @gol -+-fgnu-runtime -fnext-runtime @gol -+-fno-nil-receivers @gol -+-fobjc-call-cxx-cdtors @gol -+-fobjc-direct-dispatch @gol -+-fobjc-exceptions @gol -+-fobjc-gc @gol -+-freplace-objc-classes @gol -+-fzero-link @gol -+-gen-decls @gol -+-Wassign-intercept @gol -+-Wno-protocol -Wselector @gol -+-Wstrict-selector-match @gol -+-Wundeclared-selector} -+ -+@item Language Independent Options -+@xref{Language Independent Options,,Options to Control Diagnostic Messages Formatting}. -+@gccoptlist{-fmessage-length=@var{n} @gol -+-fdiagnostics-show-location=@r{[}once@r{|}every-line@r{]} @gol -+-fdiagnostics-show-option} -+ -+@item Warning Options -+@xref{Warning Options,,Options to Request or Suppress Warnings}. -+@gccoptlist{-fsyntax-only -pedantic -pedantic-errors @gol -+-w -Wextra -Wall -Waddress -Waggregate-return -Warray-bounds @gol -+-Wno-attributes -Wno-builtin-macro-redefined @gol -+-Wc++-compat -Wc++0x-compat -Wcast-align -Wcast-qual @gol -+-Wchar-subscripts -Wclobbered -Wcomment @gol -+-Wconversion -Wcoverage-mismatch -Wno-deprecated @gol -+-Wno-deprecated-declarations -Wdisabled-optimization @gol -+-Wno-div-by-zero -Wempty-body -Wenum-compare -Wno-endif-labels @gol -+-Werror -Werror=* @gol -+-Wfatal-errors -Wfloat-equal -Wformat -Wformat=2 @gol -+-Wno-format-contains-nul -Wno-format-extra-args -Wformat-nonliteral @gol -+-Wformat-security -Wformat-y2k @gol -+-Wframe-larger-than=@var{len} -Wignored-qualifiers @gol -+-Wimplicit -Wimplicit-function-declaration -Wimplicit-int @gol -+-Winit-self -Winline @gol -+-Wno-int-to-pointer-cast -Wno-invalid-offsetof @gol -+-Winvalid-pch -Wlarger-than=@var{len} -Wunsafe-loop-optimizations @gol -+-Wlogical-op -Wlong-long @gol -+-Wmain -Wmissing-braces -Wmissing-field-initializers @gol -+-Wmissing-format-attribute -Wmissing-include-dirs @gol -+-Wmissing-noreturn -Wno-mudflap @gol -+-Wno-multichar -Wnonnull -Wno-overflow @gol -+-Woverlength-strings -Wpacked -Wpacked-bitfield-compat -Wpadded @gol -+-Wparentheses -Wpedantic-ms-format -Wno-pedantic-ms-format @gol -+-Wpointer-arith -Wno-pointer-to-int-cast @gol -+-Wredundant-decls @gol -+-Wreturn-type -Wsequence-point -Wshadow @gol -+-Wsign-compare -Wsign-conversion -Wstack-protector @gol -+-Wstrict-aliasing -Wstrict-aliasing=n @gol -+-Wstrict-overflow -Wstrict-overflow=@var{n} @gol -+-Wswitch -Wswitch-default -Wswitch-enum -Wsync-nand @gol -+-Wsystem-headers -Wtrigraphs -Wtype-limits -Wundef -Wuninitialized @gol -+-Wunknown-pragmas -Wno-pragmas -Wunreachable-code @gol -+-Wunused -Wunused-function -Wunused-label -Wunused-parameter @gol -+-Wunused-value -Wunused-variable @gol -+-Wvariadic-macros -Wvla @gol -+-Wvolatile-register-var -Wwrite-strings} -+ -+@item C and Objective-C-only Warning Options -+@gccoptlist{-Wbad-function-cast -Wmissing-declarations @gol -+-Wmissing-parameter-type -Wmissing-prototypes -Wnested-externs @gol -+-Wold-style-declaration -Wold-style-definition @gol -+-Wstrict-prototypes -Wtraditional -Wtraditional-conversion @gol -+-Wdeclaration-after-statement -Wpointer-sign} -+ -+@item Debugging Options -+@xref{Debugging Options,,Options for Debugging Your Program or GCC}. -+@gccoptlist{-d@var{letters} -dumpspecs -dumpmachine -dumpversion @gol -+-fdbg-cnt-list -fdbg-cnt=@var{counter-value-list} @gol -+-fdump-noaddr -fdump-unnumbered @gol -+-fdump-translation-unit@r{[}-@var{n}@r{]} @gol -+-fdump-class-hierarchy@r{[}-@var{n}@r{]} @gol -+-fdump-ipa-all -fdump-ipa-cgraph -fdump-ipa-inline @gol -+-fdump-statistics @gol -+-fdump-tree-all @gol -+-fdump-tree-original@r{[}-@var{n}@r{]} @gol -+-fdump-tree-optimized@r{[}-@var{n}@r{]} @gol -+-fdump-tree-cfg -fdump-tree-vcg -fdump-tree-alias @gol -+-fdump-tree-ch @gol -+-fdump-tree-ssa@r{[}-@var{n}@r{]} -fdump-tree-pre@r{[}-@var{n}@r{]} @gol -+-fdump-tree-ccp@r{[}-@var{n}@r{]} -fdump-tree-dce@r{[}-@var{n}@r{]} @gol -+-fdump-tree-gimple@r{[}-raw@r{]} -fdump-tree-mudflap@r{[}-@var{n}@r{]} @gol -+-fdump-tree-dom@r{[}-@var{n}@r{]} @gol -+-fdump-tree-dse@r{[}-@var{n}@r{]} @gol -+-fdump-tree-phiopt@r{[}-@var{n}@r{]} @gol -+-fdump-tree-forwprop@r{[}-@var{n}@r{]} @gol -+-fdump-tree-copyrename@r{[}-@var{n}@r{]} @gol -+-fdump-tree-nrv -fdump-tree-vect @gol -+-fdump-tree-sink @gol -+-fdump-tree-sra@r{[}-@var{n}@r{]} @gol -+-fdump-tree-fre@r{[}-@var{n}@r{]} @gol -+-fdump-tree-vrp@r{[}-@var{n}@r{]} @gol -+-ftree-vectorizer-verbose=@var{n} @gol -+-fdump-tree-storeccp@r{[}-@var{n}@r{]} @gol -+-feliminate-dwarf2-dups -feliminate-unused-debug-types @gol -+-feliminate-unused-debug-symbols -femit-class-debug-always @gol -+-fmem-report -fpre-ipa-mem-report -fpost-ipa-mem-report -fprofile-arcs @gol -+-frandom-seed=@var{string} -fsched-verbose=@var{n} @gol -+-fsel-sched-verbose -fsel-sched-dump-cfg -fsel-sched-pipelining-verbose @gol -+-ftest-coverage -ftime-report -fvar-tracking @gol -+-g -g@var{level} -gcoff -gdwarf-2 @gol -+-ggdb -gstabs -gstabs+ -gvms -gxcoff -gxcoff+ @gol -+-fno-merge-debug-strings -fno-dwarf2-cfi-asm @gol -+-fdebug-prefix-map=@var{old}=@var{new} @gol -+-femit-struct-debug-baseonly -femit-struct-debug-reduced @gol -+-femit-struct-debug-detailed@r{[}=@var{spec-list}@r{]} @gol -+-p -pg -print-file-name=@var{library} -print-libgcc-file-name @gol -+-print-multi-directory -print-multi-lib @gol -+-print-prog-name=@var{program} -print-search-dirs -Q @gol -+-print-sysroot -print-sysroot-headers-suffix @gol -+-save-temps -time} -+ -+@item Optimization Options -+@xref{Optimize Options,,Options that Control Optimization}. -+@gccoptlist{ -+-falign-functions[=@var{n}] -falign-jumps[=@var{n}] @gol -+-falign-labels[=@var{n}] -falign-loops[=@var{n}] -fassociative-math @gol -+-fauto-inc-dec -fbranch-probabilities -fbranch-target-load-optimize @gol -+-fbranch-target-load-optimize2 -fbtr-bb-exclusive -fcaller-saves @gol -+-fcheck-data-deps -fconserve-stack -fcprop-registers -fcrossjumping @gol -+-fcse-follow-jumps -fcse-skip-blocks -fcx-fortran-rules -fcx-limited-range @gol -+-fdata-sections -fdce -fdce @gol -+-fdelayed-branch -fdelete-null-pointer-checks -fdse -fdse @gol -+-fearly-inlining -fexpensive-optimizations -ffast-math @gol -+-ffinite-math-only -ffloat-store -fforward-propagate @gol -+-ffunction-sections -fgcse -fgcse-after-reload -fgcse-las -fgcse-lm @gol -+-fgcse-sm -fif-conversion -fif-conversion2 -findirect-inlining @gol -+-finline-functions -finline-functions-called-once -finline-limit=@var{n} @gol -+-finline-small-functions -fipa-cp -fipa-cp-clone -fipa-matrix-reorg -fipa-pta @gol -+-fipa-pure-const -fipa-reference -fipa-struct-reorg @gol -+-fipa-type-escape -fira-algorithm=@var{algorithm} @gol -+-fira-region=@var{region} -fira-coalesce -fno-ira-share-save-slots @gol -+-fno-ira-share-spill-slots -fira-verbose=@var{n} @gol -+-fivopts -fkeep-inline-functions -fkeep-static-consts @gol -+-floop-block -floop-interchange -floop-strip-mine @gol -+-fmerge-all-constants -fmerge-constants -fmodulo-sched @gol -+-fmodulo-sched-allow-regmoves -fmove-loop-invariants -fmudflap @gol -+-fmudflapir -fmudflapth -fno-branch-count-reg -fno-default-inline @gol -+-fno-defer-pop -fno-function-cse -fno-guess-branch-probability @gol -+-fno-inline -fno-math-errno -fno-peephole -fno-peephole2 @gol -+-fno-sched-interblock -fno-sched-spec -fno-signed-zeros @gol -+-fno-toplevel-reorder -fno-trapping-math -fno-zero-initialized-in-bss @gol -+-fomit-frame-pointer -foptimize-register-move -foptimize-sibling-calls @gol -+-fpeel-loops -fpredictive-commoning -fprefetch-loop-arrays @gol -+-fprofile-correction -fprofile-dir=@var{path} -fprofile-generate @gol -+-fprofile-generate=@var{path} @gol -+-fprofile-use -fprofile-use=@var{path} -fprofile-values @gol -+-freciprocal-math -fregmove -frename-registers -freorder-blocks @gol -+-freorder-blocks-and-partition -freorder-functions @gol -+-frerun-cse-after-loop -freschedule-modulo-scheduled-loops @gol -+-frounding-math -frtl-abstract-sequences -fsched2-use-superblocks @gol -+-fsched2-use-traces -fsched-spec-load -fsched-spec-load-dangerous @gol -+-fsched-stalled-insns-dep[=@var{n}] -fsched-stalled-insns[=@var{n}] @gol -+-fschedule-insns -fschedule-insns2 -fsection-anchors -fsee @gol -+-fselective-scheduling -fselective-scheduling2 @gol -+-fsel-sched-pipelining -fsel-sched-pipelining-outer-loops @gol -+-fsignaling-nans -fsingle-precision-constant -fsplit-ivs-in-unroller @gol -+-fsplit-wide-types -fstack-protector -fstack-protector-all @gol -+-fstrict-aliasing -fstrict-overflow -fthread-jumps -ftracer @gol -+-ftree-builtin-call-dce -ftree-ccp -ftree-ch -ftree-copy-prop @gol -+-ftree-copyrename -ftree-dce @gol -+-ftree-dominator-opts -ftree-dse -ftree-fre -ftree-loop-im @gol -+-ftree-loop-distribution @gol -+-ftree-loop-ivcanon -ftree-loop-linear -ftree-loop-optimize @gol -+-ftree-parallelize-loops=@var{n} -ftree-pre -ftree-reassoc @gol -+-ftree-sink -ftree-sra -ftree-switch-conversion @gol -+-ftree-ter -ftree-vect-loop-version -ftree-vectorize -ftree-vrp @gol -+-funit-at-a-time -funroll-all-loops -funroll-loops @gol -+-funsafe-loop-optimizations -funsafe-math-optimizations -funswitch-loops @gol -+-fvariable-expansion-in-unroller -fvect-cost-model -fvpt -fweb @gol -+-fwhole-program @gol -+--param @var{name}=@var{value} -+-O -O0 -O1 -O2 -O3 -Os} -+ -+@item Preprocessor Options -+@xref{Preprocessor Options,,Options Controlling the Preprocessor}. -+@gccoptlist{-A@var{question}=@var{answer} @gol -+-A-@var{question}@r{[}=@var{answer}@r{]} @gol -+-C -dD -dI -dM -dN @gol -+-D@var{macro}@r{[}=@var{defn}@r{]} -E -H @gol -+-idirafter @var{dir} @gol -+-include @var{file} -imacros @var{file} @gol -+-iprefix @var{file} -iwithprefix @var{dir} @gol -+-iwithprefixbefore @var{dir} -isystem @var{dir} @gol -+-imultilib @var{dir} -isysroot @var{dir} @gol -+-M -MM -MF -MG -MP -MQ -MT -nostdinc @gol -+-P -fworking-directory -remap @gol -+-trigraphs -undef -U@var{macro} -Wp,@var{option} @gol -+-Xpreprocessor @var{option}} -+ -+@item Assembler Option -+@xref{Assembler Options,,Passing Options to the Assembler}. -+@gccoptlist{-Wa,@var{option} -Xassembler @var{option}} -+ -+@item Linker Options -+@xref{Link Options,,Options for Linking}. -+@gccoptlist{@var{object-file-name} -l@var{library} @gol -+-nostartfiles -nodefaultlibs -nostdlib -pie -rdynamic @gol -+-s -static -static-libgcc -shared -shared-libgcc -symbolic @gol -+-T @var{script} -Wl,@var{option} -Xlinker @var{option} @gol -+-u @var{symbol}} -+ -+@item Directory Options -+@xref{Directory Options,,Options for Directory Search}. -+@gccoptlist{-B@var{prefix} -I@var{dir} -iquote@var{dir} -L@var{dir} -+-specs=@var{file} -I- --sysroot=@var{dir}} -+ -+@item Target Options -+@c I wrote this xref this way to avoid overfull hbox. -- rms -+@xref{Target Options}. -+@gccoptlist{-V @var{version} -b @var{machine}} -+ -+@item Machine Dependent Options -+@xref{Submodel Options,,Hardware Models and Configurations}. -+@c This list is ordered alphanumerically by subsection name. -+@c Try and put the significant identifier (CPU or system) first, -+@c so users have a clue at guessing where the ones they want will be. -+ -+@emph{ARC Options} -+@gccoptlist{-EB -EL @gol -+-mmangle-cpu -mcpu=@var{cpu} -mtext=@var{text-section} @gol -+-mdata=@var{data-section} -mrodata=@var{readonly-data-section}} -+ -+@emph{ARM Options} -+@gccoptlist{-mapcs-frame -mno-apcs-frame @gol -+-mabi=@var{name} @gol -+-mapcs-stack-check -mno-apcs-stack-check @gol -+-mapcs-float -mno-apcs-float @gol -+-mapcs-reentrant -mno-apcs-reentrant @gol -+-msched-prolog -mno-sched-prolog @gol -+-mlittle-endian -mbig-endian -mwords-little-endian @gol -+-mfloat-abi=@var{name} -msoft-float -mhard-float -mfpe @gol -+-mthumb-interwork -mno-thumb-interwork @gol -+-mcpu=@var{name} -march=@var{name} -mfpu=@var{name} @gol -+-mstructure-size-boundary=@var{n} @gol -+-mabort-on-noreturn @gol -+-mlong-calls -mno-long-calls @gol -+-msingle-pic-base -mno-single-pic-base @gol -+-mpic-register=@var{reg} @gol -+-mnop-fun-dllimport @gol -+-mcirrus-fix-invalid-insns -mno-cirrus-fix-invalid-insns @gol -+-mpoke-function-name @gol -+-mthumb -marm @gol -+-mtpcs-frame -mtpcs-leaf-frame @gol -+-mcaller-super-interworking -mcallee-super-interworking @gol -+-mtp=@var{name} @gol -+-mword-relocations @gol -+-mfix-cortex-m3-ldrd} -+ -+@emph{AVR Options} -+@gccoptlist{-mmcu=@var{mcu} -msize -mno-interrupts @gol -+-mcall-prologues -mno-tablejump -mtiny-stack -mint8} -+ -+@emph{Blackfin Options} -+@gccoptlist{-mcpu=@var{cpu}@r{[}-@var{sirevision}@r{]} @gol -+-msim -momit-leaf-frame-pointer -mno-omit-leaf-frame-pointer @gol -+-mspecld-anomaly -mno-specld-anomaly -mcsync-anomaly -mno-csync-anomaly @gol -+-mlow-64k -mno-low64k -mstack-check-l1 -mid-shared-library @gol -+-mno-id-shared-library -mshared-library-id=@var{n} @gol -+-mleaf-id-shared-library -mno-leaf-id-shared-library @gol -+-msep-data -mno-sep-data -mlong-calls -mno-long-calls @gol -+-mfast-fp -minline-plt -mmulticore -mcorea -mcoreb -msdram @gol -+-micplb} -+ -+@emph{CRIS Options} -+@gccoptlist{-mcpu=@var{cpu} -march=@var{cpu} -mtune=@var{cpu} @gol -+-mmax-stack-frame=@var{n} -melinux-stacksize=@var{n} @gol -+-metrax4 -metrax100 -mpdebug -mcc-init -mno-side-effects @gol -+-mstack-align -mdata-align -mconst-align @gol -+-m32-bit -m16-bit -m8-bit -mno-prologue-epilogue -mno-gotplt @gol -+-melf -maout -melinux -mlinux -sim -sim2 @gol -+-mmul-bug-workaround -mno-mul-bug-workaround} -+ -+@emph{CRX Options} -+@gccoptlist{-mmac -mpush-args} -+ -+@emph{Darwin Options} -+@gccoptlist{-all_load -allowable_client -arch -arch_errors_fatal @gol -+-arch_only -bind_at_load -bundle -bundle_loader @gol -+-client_name -compatibility_version -current_version @gol -+-dead_strip @gol -+-dependency-file -dylib_file -dylinker_install_name @gol -+-dynamic -dynamiclib -exported_symbols_list @gol -+-filelist -flat_namespace -force_cpusubtype_ALL @gol -+-force_flat_namespace -headerpad_max_install_names @gol -+-iframework @gol -+-image_base -init -install_name -keep_private_externs @gol -+-multi_module -multiply_defined -multiply_defined_unused @gol -+-noall_load -no_dead_strip_inits_and_terms @gol -+-nofixprebinding -nomultidefs -noprebind -noseglinkedit @gol -+-pagezero_size -prebind -prebind_all_twolevel_modules @gol -+-private_bundle -read_only_relocs -sectalign @gol -+-sectobjectsymbols -whyload -seg1addr @gol -+-sectcreate -sectobjectsymbols -sectorder @gol -+-segaddr -segs_read_only_addr -segs_read_write_addr @gol -+-seg_addr_table -seg_addr_table_filename -seglinkedit @gol -+-segprot -segs_read_only_addr -segs_read_write_addr @gol -+-single_module -static -sub_library -sub_umbrella @gol -+-twolevel_namespace -umbrella -undefined @gol -+-unexported_symbols_list -weak_reference_mismatches @gol -+-whatsloaded -F -gused -gfull -mmacosx-version-min=@var{version} @gol -+-mkernel -mone-byte-bool} -+ -+@emph{DEC Alpha Options} -+@gccoptlist{-mno-fp-regs -msoft-float -malpha-as -mgas @gol -+-mieee -mieee-with-inexact -mieee-conformant @gol -+-mfp-trap-mode=@var{mode} -mfp-rounding-mode=@var{mode} @gol -+-mtrap-precision=@var{mode} -mbuild-constants @gol -+-mcpu=@var{cpu-type} -mtune=@var{cpu-type} @gol -+-mbwx -mmax -mfix -mcix @gol -+-mfloat-vax -mfloat-ieee @gol -+-mexplicit-relocs -msmall-data -mlarge-data @gol -+-msmall-text -mlarge-text @gol -+-mmemory-latency=@var{time}} -+ -+@emph{DEC Alpha/VMS Options} -+@gccoptlist{-mvms-return-codes} -+ -+@emph{FR30 Options} -+@gccoptlist{-msmall-model -mno-lsim} -+ -+@emph{FRV Options} -+@gccoptlist{-mgpr-32 -mgpr-64 -mfpr-32 -mfpr-64 @gol -+-mhard-float -msoft-float @gol -+-malloc-cc -mfixed-cc -mdword -mno-dword @gol -+-mdouble -mno-double @gol -+-mmedia -mno-media -mmuladd -mno-muladd @gol -+-mfdpic -minline-plt -mgprel-ro -multilib-library-pic @gol -+-mlinked-fp -mlong-calls -malign-labels @gol -+-mlibrary-pic -macc-4 -macc-8 @gol -+-mpack -mno-pack -mno-eflags -mcond-move -mno-cond-move @gol -+-moptimize-membar -mno-optimize-membar @gol -+-mscc -mno-scc -mcond-exec -mno-cond-exec @gol -+-mvliw-branch -mno-vliw-branch @gol -+-mmulti-cond-exec -mno-multi-cond-exec -mnested-cond-exec @gol -+-mno-nested-cond-exec -mtomcat-stats @gol -+-mTLS -mtls @gol -+-mcpu=@var{cpu}} -+ -+@emph{GNU/Linux Options} -+@gccoptlist{-muclibc} -+ -+@emph{H8/300 Options} -+@gccoptlist{-mrelax -mh -ms -mn -mint32 -malign-300} -+ -+@emph{HPPA Options} -+@gccoptlist{-march=@var{architecture-type} @gol -+-mbig-switch -mdisable-fpregs -mdisable-indexing @gol -+-mfast-indirect-calls -mgas -mgnu-ld -mhp-ld @gol -+-mfixed-range=@var{register-range} @gol -+-mjump-in-delay -mlinker-opt -mlong-calls @gol -+-mlong-load-store -mno-big-switch -mno-disable-fpregs @gol -+-mno-disable-indexing -mno-fast-indirect-calls -mno-gas @gol -+-mno-jump-in-delay -mno-long-load-store @gol -+-mno-portable-runtime -mno-soft-float @gol -+-mno-space-regs -msoft-float -mpa-risc-1-0 @gol -+-mpa-risc-1-1 -mpa-risc-2-0 -mportable-runtime @gol -+-mschedule=@var{cpu-type} -mspace-regs -msio -mwsio @gol -+-munix=@var{unix-std} -nolibdld -static -threads} -+ -+@emph{i386 and x86-64 Options} -+@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol -+-mfpmath=@var{unit} @gol -+-masm=@var{dialect} -mno-fancy-math-387 @gol -+-mno-fp-ret-in-387 -msoft-float @gol -+-mno-wide-multiply -mrtd -malign-double @gol -+-mpreferred-stack-boundary=@var{num} -+-mincoming-stack-boundary=@var{num} -+-mcld -mcx16 -msahf -mrecip @gol -+-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol -+-maes -mpclmul @gol -+-msse4a -m3dnow -mpopcnt -mabm -msse5 @gol -+-mthreads -mno-align-stringops -minline-all-stringops @gol -+-minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol -+-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol -+-m96bit-long-double -mregparm=@var{num} -msseregparm @gol -+-mveclibabi=@var{type} -mpc32 -mpc64 -mpc80 -mstackrealign @gol -+-momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol -+-mcmodel=@var{code-model} @gol -+-m32 -m64 -mlarge-data-threshold=@var{num} @gol -+-mfused-madd -mno-fused-madd -msse2avx} -+ -+@emph{i386 and x86-64 Windows Options} -+@gccoptlist{-mconsole -mcygwin -mno-cygwin -mdll -+-mnop-fun-dllimport -mthread -mwin32 -mwindows} -+ -+@emph{IA-64 Options} -+@gccoptlist{-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic @gol -+-mvolatile-asm-stop -mregister-names -mno-sdata @gol -+-mconstant-gp -mauto-pic -minline-float-divide-min-latency @gol -+-minline-float-divide-max-throughput @gol -+-minline-int-divide-min-latency @gol -+-minline-int-divide-max-throughput @gol -+-minline-sqrt-min-latency -minline-sqrt-max-throughput @gol -+-mno-dwarf2-asm -mearly-stop-bits @gol -+-mfixed-range=@var{register-range} -mtls-size=@var{tls-size} @gol -+-mtune=@var{cpu-type} -mt -pthread -milp32 -mlp64 @gol -+-mno-sched-br-data-spec -msched-ar-data-spec -mno-sched-control-spec @gol -+-msched-br-in-data-spec -msched-ar-in-data-spec -msched-in-control-spec @gol -+-msched-ldc -mno-sched-control-ldc -mno-sched-spec-verbose @gol -+-mno-sched-prefer-non-data-spec-insns @gol -+-mno-sched-prefer-non-control-spec-insns @gol -+-mno-sched-count-spec-in-critical-path} -+ -+@emph{M32R/D Options} -+@gccoptlist{-m32r2 -m32rx -m32r @gol -+-mdebug @gol -+-malign-loops -mno-align-loops @gol -+-missue-rate=@var{number} @gol -+-mbranch-cost=@var{number} @gol -+-mmodel=@var{code-size-model-type} @gol -+-msdata=@var{sdata-type} @gol -+-mno-flush-func -mflush-func=@var{name} @gol -+-mno-flush-trap -mflush-trap=@var{number} @gol -+-G @var{num}} -+ -+@emph{M32C Options} -+@gccoptlist{-mcpu=@var{cpu} -msim -memregs=@var{number}} -+ -+@emph{M680x0 Options} -+@gccoptlist{-march=@var{arch} -mcpu=@var{cpu} -mtune=@var{tune} -+-m68000 -m68020 -m68020-40 -m68020-60 -m68030 -m68040 @gol -+-m68060 -mcpu32 -m5200 -m5206e -m528x -m5307 -m5407 @gol -+-mcfv4e -mbitfield -mno-bitfield -mc68000 -mc68020 @gol -+-mnobitfield -mrtd -mno-rtd -mdiv -mno-div -mshort @gol -+-mno-short -mhard-float -m68881 -msoft-float -mpcrel @gol -+-malign-int -mstrict-align -msep-data -mno-sep-data @gol -+-mshared-library-id=n -mid-shared-library -mno-id-shared-library @gol -+-mxgot -mno-xgot} -+ -+@emph{M68hc1x Options} -+@gccoptlist{-m6811 -m6812 -m68hc11 -m68hc12 -m68hcs12 @gol -+-mauto-incdec -minmax -mlong-calls -mshort @gol -+-msoft-reg-count=@var{count}} -+ -+@emph{MCore Options} -+@gccoptlist{-mhardlit -mno-hardlit -mdiv -mno-div -mrelax-immediates @gol -+-mno-relax-immediates -mwide-bitfields -mno-wide-bitfields @gol -+-m4byte-functions -mno-4byte-functions -mcallgraph-data @gol -+-mno-callgraph-data -mslow-bytes -mno-slow-bytes -mno-lsim @gol -+-mlittle-endian -mbig-endian -m210 -m340 -mstack-increment} -+ -+@emph{MIPS Options} -+@gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} @gol -+-mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 @gol -+-mips64 -mips64r2 @gol -+-mips16 -mno-mips16 -mflip-mips16 @gol -+-minterlink-mips16 -mno-interlink-mips16 @gol -+-mabi=@var{abi} -mabicalls -mno-abicalls @gol -+-mshared -mno-shared -mplt -mno-plt -mxgot -mno-xgot @gol -+-mgp32 -mgp64 -mfp32 -mfp64 -mhard-float -msoft-float @gol -+-msingle-float -mdouble-float -mdsp -mno-dsp -mdspr2 -mno-dspr2 @gol -+-mfpu=@var{fpu-type} @gol -+-msmartmips -mno-smartmips @gol -+-mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol -+-mips3d -mno-mips3d -mmt -mno-mt -mllsc -mno-llsc @gol -+-mlong64 -mlong32 -msym32 -mno-sym32 @gol -+-G@var{num} -mlocal-sdata -mno-local-sdata @gol -+-mextern-sdata -mno-extern-sdata -mgpopt -mno-gopt @gol -+-membedded-data -mno-embedded-data @gol -+-muninit-const-in-rodata -mno-uninit-const-in-rodata @gol -+-mcode-readable=@var{setting} @gol -+-msplit-addresses -mno-split-addresses @gol -+-mexplicit-relocs -mno-explicit-relocs @gol -+-mcheck-zero-division -mno-check-zero-division @gol -+-mdivide-traps -mdivide-breaks @gol -+-mmemcpy -mno-memcpy -mlong-calls -mno-long-calls @gol -+-mmad -mno-mad -mfused-madd -mno-fused-madd -nocpp @gol -+-mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 @gol -+-mfix-r10000 -mno-fix-r10000 -mfix-vr4120 -mno-fix-vr4120 @gol -+-mfix-vr4130 -mno-fix-vr4130 -mfix-sb1 -mno-fix-sb1 @gol -+-mflush-func=@var{func} -mno-flush-func @gol -+-mbranch-cost=@var{num} -mbranch-likely -mno-branch-likely @gol -+-mfp-exceptions -mno-fp-exceptions @gol -+-mvr4130-align -mno-vr4130-align} -+ -+@emph{MMIX Options} -+@gccoptlist{-mlibfuncs -mno-libfuncs -mepsilon -mno-epsilon -mabi=gnu @gol -+-mabi=mmixware -mzero-extend -mknuthdiv -mtoplevel-symbols @gol -+-melf -mbranch-predict -mno-branch-predict -mbase-addresses @gol -+-mno-base-addresses -msingle-exit -mno-single-exit} -+ -+@emph{MN10300 Options} -+@gccoptlist{-mmult-bug -mno-mult-bug @gol -+-mam33 -mno-am33 @gol -+-mam33-2 -mno-am33-2 @gol -+-mreturn-pointer-on-d0 @gol -+-mno-crt0 -mrelax} -+ -+@emph{PDP-11 Options} -+@gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol -+-mbcopy -mbcopy-builtin -mint32 -mno-int16 @gol -+-mint16 -mno-int32 -mfloat32 -mno-float64 @gol -+-mfloat64 -mno-float32 -mabshi -mno-abshi @gol -+-mbranch-expensive -mbranch-cheap @gol -+-msplit -mno-split -munix-asm -mdec-asm} -+ -+@emph{picoChip Options} -+@gccoptlist{-mae=@var{ae_type} -mvliw-lookahead=@var{N} -+-msymbol-as-address -mno-inefficient-warnings} -+ -+@emph{PowerPC Options} -+See RS/6000 and PowerPC Options. -+ -+@emph{RS/6000 and PowerPC Options} -+@gccoptlist{-mcpu=@var{cpu-type} @gol -+-mtune=@var{cpu-type} @gol -+-mpower -mno-power -mpower2 -mno-power2 @gol -+-mpowerpc -mpowerpc64 -mno-powerpc @gol -+-maltivec -mno-altivec @gol -+-mpowerpc-gpopt -mno-powerpc-gpopt @gol -+-mpowerpc-gfxopt -mno-powerpc-gfxopt @gol -+-mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mfprnd -mno-fprnd @gol -+-mcmpb -mno-cmpb -mmfpgpr -mno-mfpgpr -mhard-dfp -mno-hard-dfp @gol -+-mnew-mnemonics -mold-mnemonics @gol -+-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol -+-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol -+-malign-power -malign-natural @gol -+-msoft-float -mhard-float -mmultiple -mno-multiple @gol -+-msingle-float -mdouble-float -msimple-fpu @gol -+-mstring -mno-string -mupdate -mno-update @gol -+-mavoid-indexed-addresses -mno-avoid-indexed-addresses @gol -+-mfused-madd -mno-fused-madd -mbit-align -mno-bit-align @gol -+-mstrict-align -mno-strict-align -mrelocatable @gol -+-mno-relocatable -mrelocatable-lib -mno-relocatable-lib @gol -+-mtoc -mno-toc -mlittle -mlittle-endian -mbig -mbig-endian @gol -+-mdynamic-no-pic -maltivec -mswdiv @gol -+-mprioritize-restricted-insns=@var{priority} @gol -+-msched-costly-dep=@var{dependence_type} @gol -+-minsert-sched-nops=@var{scheme} @gol -+-mcall-sysv -mcall-netbsd @gol -+-maix-struct-return -msvr4-struct-return @gol -+-mabi=@var{abi-type} -msecure-plt -mbss-plt @gol -+-misel -mno-isel @gol -+-misel=yes -misel=no @gol -+-mspe -mno-spe @gol -+-mspe=yes -mspe=no @gol -+-mpaired @gol -+-mgen-cell-microcode -mwarn-cell-microcode @gol -+-mvrsave -mno-vrsave @gol -+-mmulhw -mno-mulhw @gol -+-mdlmzb -mno-dlmzb @gol -+-mfloat-gprs=yes -mfloat-gprs=no -mfloat-gprs=single -mfloat-gprs=double @gol -+-mprototype -mno-prototype @gol -+-msim -mmvme -mads -myellowknife -memb -msdata @gol -+-msdata=@var{opt} -mvxworks -G @var{num} -pthread} -+ -+@emph{S/390 and zSeries Options} -+@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol -+-mhard-float -msoft-float -mhard-dfp -mno-hard-dfp @gol -+-mlong-double-64 -mlong-double-128 @gol -+-mbackchain -mno-backchain -mpacked-stack -mno-packed-stack @gol -+-msmall-exec -mno-small-exec -mmvcle -mno-mvcle @gol -+-m64 -m31 -mdebug -mno-debug -mesa -mzarch @gol -+-mtpf-trace -mno-tpf-trace -mfused-madd -mno-fused-madd @gol -+-mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard} -+ -+@emph{Score Options} -+@gccoptlist{-meb -mel @gol -+-mnhwloop @gol -+-muls @gol -+-mmac @gol -+-mscore5 -mscore5u -mscore7 -mscore7d} -+ -+@emph{SH Options} -+@gccoptlist{-m1 -m2 -m2e -m3 -m3e @gol -+-m4-nofpu -m4-single-only -m4-single -m4 @gol -+-m4a-nofpu -m4a-single-only -m4a-single -m4a -m4al @gol -+-m5-64media -m5-64media-nofpu @gol -+-m5-32media -m5-32media-nofpu @gol -+-m5-compact -m5-compact-nofpu @gol -+-mb -ml -mdalign -mrelax @gol -+-mbigtable -mfmovd -mhitachi -mrenesas -mno-renesas -mnomacsave @gol -+-mieee -mbitops -misize -minline-ic_invalidate -mpadstruct -mspace @gol -+-mprefergot -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol -+-mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol -+-madjust-unroll -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol -+-minvalid-symbols} -+ -+@emph{SPARC Options} -+@gccoptlist{-mcpu=@var{cpu-type} @gol -+-mtune=@var{cpu-type} @gol -+-mcmodel=@var{code-model} @gol -+-m32 -m64 -mapp-regs -mno-app-regs @gol -+-mfaster-structs -mno-faster-structs @gol -+-mfpu -mno-fpu -mhard-float -msoft-float @gol -+-mhard-quad-float -msoft-quad-float @gol -+-mimpure-text -mno-impure-text -mlittle-endian @gol -+-mstack-bias -mno-stack-bias @gol -+-munaligned-doubles -mno-unaligned-doubles @gol -+-mv8plus -mno-v8plus -mvis -mno-vis -+-threads -pthreads -pthread} -+ -+@emph{SPU Options} -+@gccoptlist{-mwarn-reloc -merror-reloc @gol -+-msafe-dma -munsafe-dma @gol -+-mbranch-hints @gol -+-msmall-mem -mlarge-mem -mstdmain @gol -+-mfixed-range=@var{register-range}} -+ -+@emph{System V Options} -+@gccoptlist{-Qy -Qn -YP,@var{paths} -Ym,@var{dir}} -+ -+@emph{V850 Options} -+@gccoptlist{-mlong-calls -mno-long-calls -mep -mno-ep @gol -+-mprolog-function -mno-prolog-function -mspace @gol -+-mtda=@var{n} -msda=@var{n} -mzda=@var{n} @gol -+-mapp-regs -mno-app-regs @gol -+-mdisable-callt -mno-disable-callt @gol -+-mv850e1 @gol -+-mv850e @gol -+-mv850 -mbig-switch} -+ -+@emph{VAX Options} -+@gccoptlist{-mg -mgnu -munix} -+ -+@emph{VxWorks Options} -+@gccoptlist{-mrtp -non-static -Bstatic -Bdynamic @gol -+-Xbind-lazy -Xbind-now} -+ -+@emph{x86-64 Options} -+See i386 and x86-64 Options. -+ -+@emph{Xstormy16 Options} -+@gccoptlist{-msim} -+ -+@emph{Xtensa Options} -+@gccoptlist{-mconst16 -mno-const16 @gol -+-mfused-madd -mno-fused-madd @gol -+-mserialize-volatile -mno-serialize-volatile @gol -+-mtext-section-literals -mno-text-section-literals @gol -+-mtarget-align -mno-target-align @gol -+-mlongcalls -mno-longcalls} -+ -+@emph{zSeries Options} -+See S/390 and zSeries Options. -+ -+@item Code Generation Options -+@xref{Code Gen Options,,Options for Code Generation Conventions}. -+@gccoptlist{-fcall-saved-@var{reg} -fcall-used-@var{reg} @gol -+-ffixed-@var{reg} -fexceptions @gol -+-fnon-call-exceptions -funwind-tables @gol -+-fasynchronous-unwind-tables @gol -+-finhibit-size-directive -finstrument-functions @gol -+-finstrument-functions-exclude-function-list=@var{sym},@var{sym},@dots{} @gol -+-finstrument-functions-exclude-file-list=@var{file},@var{file},@dots{} @gol -+-fno-common -fno-ident @gol -+-fpcc-struct-return -fpic -fPIC -fpie -fPIE @gol -+-fno-jump-tables @gol -+-frecord-gcc-switches @gol -+-freg-struct-return -fshort-enums @gol -+-fshort-double -fshort-wchar @gol -+-fverbose-asm -fpack-struct[=@var{n}] -fstack-check @gol -+-fstack-limit-register=@var{reg} -fstack-limit-symbol=@var{sym} @gol -+-fno-stack-limit -fargument-alias -fargument-noalias @gol -+-fargument-noalias-global -fargument-noalias-anything @gol -+-fleading-underscore -ftls-model=@var{model} @gol -+-ftrapv -fwrapv -fbounds-check @gol -+-fvisibility} -+@end table -+ -+@menu -+* Overall Options:: Controlling the kind of output: -+ an executable, object files, assembler files, -+ or preprocessed source. -+* C Dialect Options:: Controlling the variant of C language compiled. -+* C++ Dialect Options:: Variations on C++. -+* Objective-C and Objective-C++ Dialect Options:: Variations on Objective-C -+ and Objective-C++. -+* Language Independent Options:: Controlling how diagnostics should be -+ formatted. -+* Warning Options:: How picky should the compiler be? -+* Debugging Options:: Symbol tables, measurements, and debugging dumps. -+* Optimize Options:: How much optimization? -+* Preprocessor Options:: Controlling header files and macro definitions. -+ Also, getting dependency information for Make. -+* Assembler Options:: Passing options to the assembler. -+* Link Options:: Specifying libraries and so on. -+* Directory Options:: Where to find header files and libraries. -+ Where to find the compiler executable files. -+* Spec Files:: How to pass switches to sub-processes. -+* Target Options:: Running a cross-compiler, or an old version of GCC. -+@end menu -+ -+@node Overall Options -+@section Options Controlling the Kind of Output -+ -+Compilation can involve up to four stages: preprocessing, compilation -+proper, assembly and linking, always in that order. GCC is capable of -+preprocessing and compiling several files either into several -+assembler input files, or into one assembler input file; then each -+assembler input file produces an object file, and linking combines all -+the object files (those newly compiled, and those specified as input) -+into an executable file. -+ -+@cindex file name suffix -+For any given input file, the file name suffix determines what kind of -+compilation is done: -+ -+@table @gcctabopt -+@item @var{file}.c -+C source code which must be preprocessed. -+ -+@item @var{file}.i -+C source code which should not be preprocessed. -+ -+@item @var{file}.ii -+C++ source code which should not be preprocessed. -+ -+@item @var{file}.m -+Objective-C source code. Note that you must link with the @file{libobjc} -+library to make an Objective-C program work. -+ -+@item @var{file}.mi -+Objective-C source code which should not be preprocessed. -+ -+@item @var{file}.mm -+@itemx @var{file}.M -+Objective-C++ source code. Note that you must link with the @file{libobjc} -+library to make an Objective-C++ program work. Note that @samp{.M} refers -+to a literal capital M@. -+ -+@item @var{file}.mii -+Objective-C++ source code which should not be preprocessed. -+ -+@item @var{file}.h -+C, C++, Objective-C or Objective-C++ header file to be turned into a -+precompiled header. -+ -+@item @var{file}.cc -+@itemx @var{file}.cp -+@itemx @var{file}.cxx -+@itemx @var{file}.cpp -+@itemx @var{file}.CPP -+@itemx @var{file}.c++ -+@itemx @var{file}.C -+C++ source code which must be preprocessed. Note that in @samp{.cxx}, -+the last two letters must both be literally @samp{x}. Likewise, -+@samp{.C} refers to a literal capital C@. -+ -+@item @var{file}.mm -+@itemx @var{file}.M -+Objective-C++ source code which must be preprocessed. -+ -+@item @var{file}.mii -+Objective-C++ source code which should not be preprocessed. -+ -+@item @var{file}.hh -+@itemx @var{file}.H -+@itemx @var{file}.hp -+@itemx @var{file}.hxx -+@itemx @var{file}.hpp -+@itemx @var{file}.HPP -+@itemx @var{file}.h++ -+@itemx @var{file}.tcc -+C++ header file to be turned into a precompiled header. -+ -+@item @var{file}.f -+@itemx @var{file}.for -+@itemx @var{file}.ftn -+Fixed form Fortran source code which should not be preprocessed. -+ -+@item @var{file}.F -+@itemx @var{file}.FOR -+@itemx @var{file}.fpp -+@itemx @var{file}.FPP -+@itemx @var{file}.FTN -+Fixed form Fortran source code which must be preprocessed (with the traditional -+preprocessor). -+ -+@item @var{file}.f90 -+@itemx @var{file}.f95 -+@itemx @var{file}.f03 -+@itemx @var{file}.f08 -+Free form Fortran source code which should not be preprocessed. -+ -+@item @var{file}.F90 -+@itemx @var{file}.F95 -+@itemx @var{file}.F03 -+@itemx @var{file}.F08 -+Free form Fortran source code which must be preprocessed (with the -+traditional preprocessor). -+ -+@c FIXME: Descriptions of Java file types. -+@c @var{file}.java -+@c @var{file}.class -+@c @var{file}.zip -+@c @var{file}.jar -+ -+@item @var{file}.ads -+Ada source code file which contains a library unit declaration (a -+declaration of a package, subprogram, or generic, or a generic -+instantiation), or a library unit renaming declaration (a package, -+generic, or subprogram renaming declaration). Such files are also -+called @dfn{specs}. -+ -+@item @var{file}.adb -+Ada source code file containing a library unit body (a subprogram or -+package body). Such files are also called @dfn{bodies}. -+ -+@c GCC also knows about some suffixes for languages not yet included: -+@c Pascal: -+@c @var{file}.p -+@c @var{file}.pas -+@c Ratfor: -+@c @var{file}.r -+ -+@item @var{file}.s -+Assembler code. -+ -+@item @var{file}.S -+@itemx @var{file}.sx -+Assembler code which must be preprocessed. -+ -+@item @var{other} -+An object file to be fed straight into linking. -+Any file name with no recognized suffix is treated this way. -+@end table -+ -+@opindex x -+You can specify the input language explicitly with the @option{-x} option: -+ -+@table @gcctabopt -+@item -x @var{language} -+Specify explicitly the @var{language} for the following input files -+(rather than letting the compiler choose a default based on the file -+name suffix). This option applies to all following input files until -+the next @option{-x} option. Possible values for @var{language} are: -+@smallexample -+c c-header c-cpp-output -+c++ c++-header c++-cpp-output -+objective-c objective-c-header objective-c-cpp-output -+objective-c++ objective-c++-header objective-c++-cpp-output -+assembler assembler-with-cpp -+ada -+f77 f77-cpp-input f95 f95-cpp-input -+java -+@end smallexample -+ -+@item -x none -+Turn off any specification of a language, so that subsequent files are -+handled according to their file name suffixes (as they are if @option{-x} -+has not been used at all). -+ -+@item -pass-exit-codes -+@opindex pass-exit-codes -+Normally the @command{gcc} program will exit with the code of 1 if any -+phase of the compiler returns a non-success return code. If you specify -+@option{-pass-exit-codes}, the @command{gcc} program will instead return with -+numerically highest error produced by any phase that returned an error -+indication. The C, C++, and Fortran frontends return 4, if an internal -+compiler error is encountered. -+@end table -+ -+If you only want some of the stages of compilation, you can use -+@option{-x} (or filename suffixes) to tell @command{gcc} where to start, and -+one of the options @option{-c}, @option{-S}, or @option{-E} to say where -+@command{gcc} is to stop. Note that some combinations (for example, -+@samp{-x cpp-output -E}) instruct @command{gcc} to do nothing at all. -+ -+@table @gcctabopt -+@item -c -+@opindex c -+Compile or assemble the source files, but do not link. The linking -+stage simply is not done. The ultimate output is in the form of an -+object file for each source file. -+ -+By default, the object file name for a source file is made by replacing -+the suffix @samp{.c}, @samp{.i}, @samp{.s}, etc., with @samp{.o}. -+ -+Unrecognized input files, not requiring compilation or assembly, are -+ignored. -+ -+@item -S -+@opindex S -+Stop after the stage of compilation proper; do not assemble. The output -+is in the form of an assembler code file for each non-assembler input -+file specified. -+ -+By default, the assembler file name for a source file is made by -+replacing the suffix @samp{.c}, @samp{.i}, etc., with @samp{.s}. -+ -+Input files that don't require compilation are ignored. -+ -+@item -E -+@opindex E -+Stop after the preprocessing stage; do not run the compiler proper. The -+output is in the form of preprocessed source code, which is sent to the -+standard output. -+ -+Input files which don't require preprocessing are ignored. -+ -+@cindex output file option -+@item -o @var{file} -+@opindex o -+Place output in file @var{file}. This applies regardless to whatever -+sort of output is being produced, whether it be an executable file, -+an object file, an assembler file or preprocessed C code. -+ -+If @option{-o} is not specified, the default is to put an executable -+file in @file{a.out}, the object file for -+@file{@var{source}.@var{suffix}} in @file{@var{source}.o}, its -+assembler file in @file{@var{source}.s}, a precompiled header file in -+@file{@var{source}.@var{suffix}.gch}, and all preprocessed C source on -+standard output. -+ -+@item -v -+@opindex v -+Print (on standard error output) the commands executed to run the stages -+of compilation. Also print the version number of the compiler driver -+program and of the preprocessor and the compiler proper. -+ -+@item -### -+@opindex ### -+Like @option{-v} except the commands are not executed and all command -+arguments are quoted. This is useful for shell scripts to capture the -+driver-generated command lines. -+ -+@item -pipe -+@opindex pipe -+Use pipes rather than temporary files for communication between the -+various stages of compilation. This fails to work on some systems where -+the assembler is unable to read from a pipe; but the GNU assembler has -+no trouble. -+ -+@item -combine -+@opindex combine -+If you are compiling multiple source files, this option tells the driver -+to pass all the source files to the compiler at once (for those -+languages for which the compiler can handle this). This will allow -+intermodule analysis (IMA) to be performed by the compiler. Currently the only -+language for which this is supported is C@. If you pass source files for -+multiple languages to the driver, using this option, the driver will invoke -+the compiler(s) that support IMA once each, passing each compiler all the -+source files appropriate for it. For those languages that do not support -+IMA this option will be ignored, and the compiler will be invoked once for -+each source file in that language. If you use this option in conjunction -+with @option{-save-temps}, the compiler will generate multiple -+pre-processed files -+(one for each source file), but only one (combined) @file{.o} or -+@file{.s} file. -+ -+@item --help -+@opindex help -+Print (on the standard output) a description of the command line options -+understood by @command{gcc}. If the @option{-v} option is also specified -+then @option{--help} will also be passed on to the various processes -+invoked by @command{gcc}, so that they can display the command line options -+they accept. If the @option{-Wextra} option has also been specified -+(prior to the @option{--help} option), then command line options which -+have no documentation associated with them will also be displayed. -+ -+@item --target-help -+@opindex target-help -+Print (on the standard output) a description of target-specific command -+line options for each tool. For some targets extra target-specific -+information may also be printed. -+ -+@item --help=@{@var{class}@r{|[}^@r{]}@var{qualifier}@}@r{[},@dots{}@r{]} -+Print (on the standard output) a description of the command line -+options understood by the compiler that fit into all specified classes -+and qualifiers. These are the supported classes: -+ -+@table @asis -+@item @samp{optimizers} -+This will display all of the optimization options supported by the -+compiler. -+ -+@item @samp{warnings} -+This will display all of the options controlling warning messages -+produced by the compiler. -+ -+@item @samp{target} -+This will display target-specific options. Unlike the -+@option{--target-help} option however, target-specific options of the -+linker and assembler will not be displayed. This is because those -+tools do not currently support the extended @option{--help=} syntax. -+ -+@item @samp{params} -+This will display the values recognized by the @option{--param} -+option. -+ -+@item @var{language} -+This will display the options supported for @var{language}, where -+@var{language} is the name of one of the languages supported in this -+version of GCC. -+ -+@item @samp{common} -+This will display the options that are common to all languages. -+@end table -+ -+These are the supported qualifiers: -+ -+@table @asis -+@item @samp{undocumented} -+Display only those options which are undocumented. -+ -+@item @samp{joined} -+Display options which take an argument that appears after an equal -+sign in the same continuous piece of text, such as: -+@samp{--help=target}. -+ -+@item @samp{separate} -+Display options which take an argument that appears as a separate word -+following the original option, such as: @samp{-o output-file}. -+@end table -+ -+Thus for example to display all the undocumented target-specific -+switches supported by the compiler the following can be used: -+ -+@smallexample -+--help=target,undocumented -+@end smallexample -+ -+The sense of a qualifier can be inverted by prefixing it with the -+@samp{^} character, so for example to display all binary warning -+options (i.e., ones that are either on or off and that do not take an -+argument), which have a description the following can be used: -+ -+@smallexample -+--help=warnings,^joined,^undocumented -+@end smallexample -+ -+The argument to @option{--help=} should not consist solely of inverted -+qualifiers. -+ -+Combining several classes is possible, although this usually -+restricts the output by so much that there is nothing to display. One -+case where it does work however is when one of the classes is -+@var{target}. So for example to display all the target-specific -+optimization options the following can be used: -+ -+@smallexample -+--help=target,optimizers -+@end smallexample -+ -+The @option{--help=} option can be repeated on the command line. Each -+successive use will display its requested class of options, skipping -+those that have already been displayed. -+ -+If the @option{-Q} option appears on the command line before the -+@option{--help=} option, then the descriptive text displayed by -+@option{--help=} is changed. Instead of describing the displayed -+options, an indication is given as to whether the option is enabled, -+disabled or set to a specific value (assuming that the compiler -+knows this at the point where the @option{--help=} option is used). -+ -+Here is a truncated example from the ARM port of @command{gcc}: -+ -+@smallexample -+ % gcc -Q -mabi=2 --help=target -c -+ The following options are target specific: -+ -mabi= 2 -+ -mabort-on-noreturn [disabled] -+ -mapcs [disabled] -+@end smallexample -+ -+The output is sensitive to the effects of previous command line -+options, so for example it is possible to find out which optimizations -+are enabled at @option{-O2} by using: -+ -+@smallexample -+-Q -O2 --help=optimizers -+@end smallexample -+ -+Alternatively you can discover which binary optimizations are enabled -+by @option{-O3} by using: -+ -+@smallexample -+gcc -c -Q -O3 --help=optimizers > /tmp/O3-opts -+gcc -c -Q -O2 --help=optimizers > /tmp/O2-opts -+diff /tmp/O2-opts /tmp/O3-opts | grep enabled -+@end smallexample -+ -+@item --version -+@opindex version -+Display the version number and copyrights of the invoked GCC@. -+ -+@item -wrapper -+@opindex wrapper -+Invoke all subcommands under a wrapper program. It takes a single -+comma separated list as an argument, which will be used to invoke -+the wrapper: -+ -+@smallexample -+gcc -c t.c -wrapper gdb,--args -+@end smallexample -+ -+This will invoke all subprograms of gcc under "gdb --args", -+thus cc1 invocation will be "gdb --args cc1 ...". -+ -+@include @value{srcdir}/../libiberty/at-file.texi -+@end table -+ -+@node Invoking G++ -+@section Compiling C++ Programs -+ -+@cindex suffixes for C++ source -+@cindex C++ source file suffixes -+C++ source files conventionally use one of the suffixes @samp{.C}, -+@samp{.cc}, @samp{.cpp}, @samp{.CPP}, @samp{.c++}, @samp{.cp}, or -+@samp{.cxx}; C++ header files often use @samp{.hh}, @samp{.hpp}, -+@samp{.H}, or (for shared template code) @samp{.tcc}; and -+preprocessed C++ files use the suffix @samp{.ii}. GCC recognizes -+files with these names and compiles them as C++ programs even if you -+call the compiler the same way as for compiling C programs (usually -+with the name @command{gcc}). -+ -+@findex g++ -+@findex c++ -+However, the use of @command{gcc} does not add the C++ library. -+@command{g++} is a program that calls GCC and treats @samp{.c}, -+@samp{.h} and @samp{.i} files as C++ source files instead of C source -+files unless @option{-x} is used, and automatically specifies linking -+against the C++ library. This program is also useful when -+precompiling a C header file with a @samp{.h} extension for use in C++ -+compilations. On many systems, @command{g++} is also installed with -+the name @command{c++}. -+ -+@cindex invoking @command{g++} -+When you compile C++ programs, you may specify many of the same -+command-line options that you use for compiling programs in any -+language; or command-line options meaningful for C and related -+languages; or options that are meaningful only for C++ programs. -+@xref{C Dialect Options,,Options Controlling C Dialect}, for -+explanations of options for languages related to C@. -+@xref{C++ Dialect Options,,Options Controlling C++ Dialect}, for -+explanations of options that are meaningful only for C++ programs. -+ -+@node C Dialect Options -+@section Options Controlling C Dialect -+@cindex dialect options -+@cindex language dialect options -+@cindex options, dialect -+ -+The following options control the dialect of C (or languages derived -+from C, such as C++, Objective-C and Objective-C++) that the compiler -+accepts: -+ -+@table @gcctabopt -+@cindex ANSI support -+@cindex ISO support -+@item -ansi -+@opindex ansi -+In C mode, this is equivalent to @samp{-std=c89}. In C++ mode, it is -+equivalent to @samp{-std=c++98}. -+ -+This turns off certain features of GCC that are incompatible with ISO -+C90 (when compiling C code), or of standard C++ (when compiling C++ code), -+such as the @code{asm} and @code{typeof} keywords, and -+predefined macros such as @code{unix} and @code{vax} that identify the -+type of system you are using. It also enables the undesirable and -+rarely used ISO trigraph feature. For the C compiler, -+it disables recognition of C++ style @samp{//} comments as well as -+the @code{inline} keyword. -+ -+The alternate keywords @code{__asm__}, @code{__extension__}, -+@code{__inline__} and @code{__typeof__} continue to work despite -+@option{-ansi}. You would not want to use them in an ISO C program, of -+course, but it is useful to put them in header files that might be included -+in compilations done with @option{-ansi}. Alternate predefined macros -+such as @code{__unix__} and @code{__vax__} are also available, with or -+without @option{-ansi}. -+ -+The @option{-ansi} option does not cause non-ISO programs to be -+rejected gratuitously. For that, @option{-pedantic} is required in -+addition to @option{-ansi}. @xref{Warning Options}. -+ -+The macro @code{__STRICT_ANSI__} is predefined when the @option{-ansi} -+option is used. Some header files may notice this macro and refrain -+from declaring certain functions or defining certain macros that the -+ISO standard doesn't call for; this is to avoid interfering with any -+programs that might use these names for other things. -+ -+Functions that would normally be built in but do not have semantics -+defined by ISO C (such as @code{alloca} and @code{ffs}) are not built-in -+functions when @option{-ansi} is used. @xref{Other Builtins,,Other -+built-in functions provided by GCC}, for details of the functions -+affected. -+ -+@item -std= -+@opindex std -+Determine the language standard. @xref{Standards,,Language Standards -+Supported by GCC}, for details of these standard versions. This option -+is currently only supported when compiling C or C++. -+ -+The compiler can accept several base standards, such as @samp{c89} or -+@samp{c++98}, and GNU dialects of those standards, such as -+@samp{gnu89} or @samp{gnu++98}. By specifying a base standard, the -+compiler will accept all programs following that standard and those -+using GNU extensions that do not contradict it. For example, -+@samp{-std=c89} turns off certain features of GCC that are -+incompatible with ISO C90, such as the @code{asm} and @code{typeof} -+keywords, but not other GNU extensions that do not have a meaning in -+ISO C90, such as omitting the middle term of a @code{?:} -+expression. On the other hand, by specifying a GNU dialect of a -+standard, all features the compiler support are enabled, even when -+those features change the meaning of the base standard and some -+strict-conforming programs may be rejected. The particular standard -+is used by @option{-pedantic} to identify which features are GNU -+extensions given that version of the standard. For example -+@samp{-std=gnu89 -pedantic} would warn about C++ style @samp{//} -+comments, while @samp{-std=gnu99 -pedantic} would not. -+ -+A value for this option must be provided; possible values are -+ -+@table @samp -+@item c89 -+@itemx iso9899:1990 -+Support all ISO C90 programs (certain GNU extensions that conflict -+with ISO C90 are disabled). Same as @option{-ansi} for C code. -+ -+@item iso9899:199409 -+ISO C90 as modified in amendment 1. -+ -+@item c99 -+@itemx c9x -+@itemx iso9899:1999 -+@itemx iso9899:199x -+ISO C99. Note that this standard is not yet fully supported; see -+@w{@uref{http://gcc.gnu.org/gcc-4.4/c99status.html}} for more information. The -+names @samp{c9x} and @samp{iso9899:199x} are deprecated. -+ -+@item gnu89 -+GNU dialect of ISO C90 (including some C99 features). This -+is the default for C code. -+ -+@item gnu99 -+@itemx gnu9x -+GNU dialect of ISO C99. When ISO C99 is fully implemented in GCC, -+this will become the default. The name @samp{gnu9x} is deprecated. -+ -+@item c++98 -+The 1998 ISO C++ standard plus amendments. Same as @option{-ansi} for -+C++ code. -+ -+@item gnu++98 -+GNU dialect of @option{-std=c++98}. This is the default for -+C++ code. -+ -+@item c++0x -+The working draft of the upcoming ISO C++0x standard. This option -+enables experimental features that are likely to be included in -+C++0x. The working draft is constantly changing, and any feature that is -+enabled by this flag may be removed from future versions of GCC if it is -+not part of the C++0x standard. -+ -+@item gnu++0x -+GNU dialect of @option{-std=c++0x}. This option enables -+experimental features that may be removed in future versions of GCC. -+@end table -+ -+@item -fgnu89-inline -+@opindex fgnu89-inline -+The option @option{-fgnu89-inline} tells GCC to use the traditional -+GNU semantics for @code{inline} functions when in C99 mode. -+@xref{Inline,,An Inline Function is As Fast As a Macro}. This option -+is accepted and ignored by GCC versions 4.1.3 up to but not including -+4.3. In GCC versions 4.3 and later it changes the behavior of GCC in -+C99 mode. Using this option is roughly equivalent to adding the -+@code{gnu_inline} function attribute to all inline functions -+(@pxref{Function Attributes}). -+ -+The option @option{-fno-gnu89-inline} explicitly tells GCC to use the -+C99 semantics for @code{inline} when in C99 or gnu99 mode (i.e., it -+specifies the default behavior). This option was first supported in -+GCC 4.3. This option is not supported in C89 or gnu89 mode. -+ -+The preprocessor macros @code{__GNUC_GNU_INLINE__} and -+@code{__GNUC_STDC_INLINE__} may be used to check which semantics are -+in effect for @code{inline} functions. @xref{Common Predefined -+Macros,,,cpp,The C Preprocessor}. -+ -+@item -aux-info @var{filename} -+@opindex aux-info -+Output to the given filename prototyped declarations for all functions -+declared and/or defined in a translation unit, including those in header -+files. This option is silently ignored in any language other than C@. -+ -+Besides declarations, the file indicates, in comments, the origin of -+each declaration (source file and line), whether the declaration was -+implicit, prototyped or unprototyped (@samp{I}, @samp{N} for new or -+@samp{O} for old, respectively, in the first character after the line -+number and the colon), and whether it came from a declaration or a -+definition (@samp{C} or @samp{F}, respectively, in the following -+character). In the case of function definitions, a K&R-style list of -+arguments followed by their declarations is also provided, inside -+comments, after the declaration. -+ -+@item -fno-asm -+@opindex fno-asm -+Do not recognize @code{asm}, @code{inline} or @code{typeof} as a -+keyword, so that code can use these words as identifiers. You can use -+the keywords @code{__asm__}, @code{__inline__} and @code{__typeof__} -+instead. @option{-ansi} implies @option{-fno-asm}. -+ -+In C++, this switch only affects the @code{typeof} keyword, since -+@code{asm} and @code{inline} are standard keywords. You may want to -+use the @option{-fno-gnu-keywords} flag instead, which has the same -+effect. In C99 mode (@option{-std=c99} or @option{-std=gnu99}), this -+switch only affects the @code{asm} and @code{typeof} keywords, since -+@code{inline} is a standard keyword in ISO C99. -+ -+@item -fno-builtin -+@itemx -fno-builtin-@var{function} -+@opindex fno-builtin -+@cindex built-in functions -+Don't recognize built-in functions that do not begin with -+@samp{__builtin_} as prefix. @xref{Other Builtins,,Other built-in -+functions provided by GCC}, for details of the functions affected, -+including those which are not built-in functions when @option{-ansi} or -+@option{-std} options for strict ISO C conformance are used because they -+do not have an ISO standard meaning. -+ -+GCC normally generates special code to handle certain built-in functions -+more efficiently; for instance, calls to @code{alloca} may become single -+instructions that adjust the stack directly, and calls to @code{memcpy} -+may become inline copy loops. The resulting code is often both smaller -+and faster, but since the function calls no longer appear as such, you -+cannot set a breakpoint on those calls, nor can you change the behavior -+of the functions by linking with a different library. In addition, -+when a function is recognized as a built-in function, GCC may use -+information about that function to warn about problems with calls to -+that function, or to generate more efficient code, even if the -+resulting code still contains calls to that function. For example, -+warnings are given with @option{-Wformat} for bad calls to -+@code{printf}, when @code{printf} is built in, and @code{strlen} is -+known not to modify global memory. -+ -+With the @option{-fno-builtin-@var{function}} option -+only the built-in function @var{function} is -+disabled. @var{function} must not begin with @samp{__builtin_}. If a -+function is named that is not built-in in this version of GCC, this -+option is ignored. There is no corresponding -+@option{-fbuiltin-@var{function}} option; if you wish to enable -+built-in functions selectively when using @option{-fno-builtin} or -+@option{-ffreestanding}, you may define macros such as: -+ -+@smallexample -+#define abs(n) __builtin_abs ((n)) -+#define strcpy(d, s) __builtin_strcpy ((d), (s)) -+@end smallexample -+ -+@item -fhosted -+@opindex fhosted -+@cindex hosted environment -+ -+Assert that compilation takes place in a hosted environment. This implies -+@option{-fbuiltin}. A hosted environment is one in which the -+entire standard library is available, and in which @code{main} has a return -+type of @code{int}. Examples are nearly everything except a kernel. -+This is equivalent to @option{-fno-freestanding}. -+ -+@item -ffreestanding -+@opindex ffreestanding -+@cindex hosted environment -+ -+Assert that compilation takes place in a freestanding environment. This -+implies @option{-fno-builtin}. A freestanding environment -+is one in which the standard library may not exist, and program startup may -+not necessarily be at @code{main}. The most obvious example is an OS kernel. -+This is equivalent to @option{-fno-hosted}. -+ -+@xref{Standards,,Language Standards Supported by GCC}, for details of -+freestanding and hosted environments. -+ -+@item -fopenmp -+@opindex fopenmp -+@cindex openmp parallel -+Enable handling of OpenMP directives @code{#pragma omp} in C/C++ and -+@code{!$omp} in Fortran. When @option{-fopenmp} is specified, the -+compiler generates parallel code according to the OpenMP Application -+Program Interface v2.5 @w{@uref{http://www.openmp.org/}}. This option -+implies @option{-pthread}, and thus is only supported on targets that -+have support for @option{-pthread}. -+ -+@item -fms-extensions -+@opindex fms-extensions -+Accept some non-standard constructs used in Microsoft header files. -+ -+Some cases of unnamed fields in structures and unions are only -+accepted with this option. @xref{Unnamed Fields,,Unnamed struct/union -+fields within structs/unions}, for details. -+ -+@item -trigraphs -+@opindex trigraphs -+Support ISO C trigraphs. The @option{-ansi} option (and @option{-std} -+options for strict ISO C conformance) implies @option{-trigraphs}. -+ -+@item -no-integrated-cpp -+@opindex no-integrated-cpp -+Performs a compilation in two passes: preprocessing and compiling. This -+option allows a user supplied "cc1", "cc1plus", or "cc1obj" via the -+@option{-B} option. The user supplied compilation step can then add in -+an additional preprocessing step after normal preprocessing but before -+compiling. The default is to use the integrated cpp (internal cpp) -+ -+The semantics of this option will change if "cc1", "cc1plus", and -+"cc1obj" are merged. -+ -+@cindex traditional C language -+@cindex C language, traditional -+@item -traditional -+@itemx -traditional-cpp -+@opindex traditional-cpp -+@opindex traditional -+Formerly, these options caused GCC to attempt to emulate a pre-standard -+C compiler. They are now only supported with the @option{-E} switch. -+The preprocessor continues to support a pre-standard mode. See the GNU -+CPP manual for details. -+ -+@item -fcond-mismatch -+@opindex fcond-mismatch -+Allow conditional expressions with mismatched types in the second and -+third arguments. The value of such an expression is void. This option -+is not supported for C++. -+ -+@item -flax-vector-conversions -+@opindex flax-vector-conversions -+Allow implicit conversions between vectors with differing numbers of -+elements and/or incompatible element types. This option should not be -+used for new code. -+ -+@item -funsigned-char -+@opindex funsigned-char -+Let the type @code{char} be unsigned, like @code{unsigned char}. -+ -+Each kind of machine has a default for what @code{char} should -+be. It is either like @code{unsigned char} by default or like -+@code{signed char} by default. -+ -+Ideally, a portable program should always use @code{signed char} or -+@code{unsigned char} when it depends on the signedness of an object. -+But many programs have been written to use plain @code{char} and -+expect it to be signed, or expect it to be unsigned, depending on the -+machines they were written for. This option, and its inverse, let you -+make such a program work with the opposite default. -+ -+The type @code{char} is always a distinct type from each of -+@code{signed char} or @code{unsigned char}, even though its behavior -+is always just like one of those two. -+ -+@item -fsigned-char -+@opindex fsigned-char -+Let the type @code{char} be signed, like @code{signed char}. -+ -+Note that this is equivalent to @option{-fno-unsigned-char}, which is -+the negative form of @option{-funsigned-char}. Likewise, the option -+@option{-fno-signed-char} is equivalent to @option{-funsigned-char}. -+ -+@item -fsigned-bitfields -+@itemx -funsigned-bitfields -+@itemx -fno-signed-bitfields -+@itemx -fno-unsigned-bitfields -+@opindex fsigned-bitfields -+@opindex funsigned-bitfields -+@opindex fno-signed-bitfields -+@opindex fno-unsigned-bitfields -+These options control whether a bit-field is signed or unsigned, when the -+declaration does not use either @code{signed} or @code{unsigned}. By -+default, such a bit-field is signed, because this is consistent: the -+basic integer types such as @code{int} are signed types. -+@end table -+ -+@node C++ Dialect Options -+@section Options Controlling C++ Dialect -+ -+@cindex compiler options, C++ -+@cindex C++ options, command line -+@cindex options, C++ -+This section describes the command-line options that are only meaningful -+for C++ programs; but you can also use most of the GNU compiler options -+regardless of what language your program is in. For example, you -+might compile a file @code{firstClass.C} like this: -+ -+@smallexample -+g++ -g -frepo -O -c firstClass.C -+@end smallexample -+ -+@noindent -+In this example, only @option{-frepo} is an option meant -+only for C++ programs; you can use the other options with any -+language supported by GCC@. -+ -+Here is a list of options that are @emph{only} for compiling C++ programs: -+ -+@table @gcctabopt -+ -+@item -fabi-version=@var{n} -+@opindex fabi-version -+Use version @var{n} of the C++ ABI@. Version 2 is the version of the -+C++ ABI that first appeared in G++ 3.4. Version 1 is the version of -+the C++ ABI that first appeared in G++ 3.2. Version 0 will always be -+the version that conforms most closely to the C++ ABI specification. -+Therefore, the ABI obtained using version 0 will change as ABI bugs -+are fixed. -+ -+The default is version 2. -+ -+@item -fno-access-control -+@opindex fno-access-control -+Turn off all access checking. This switch is mainly useful for working -+around bugs in the access control code. -+ -+@item -fcheck-new -+@opindex fcheck-new -+Check that the pointer returned by @code{operator new} is non-null -+before attempting to modify the storage allocated. This check is -+normally unnecessary because the C++ standard specifies that -+@code{operator new} will only return @code{0} if it is declared -+@samp{throw()}, in which case the compiler will always check the -+return value even without this option. In all other cases, when -+@code{operator new} has a non-empty exception specification, memory -+exhaustion is signalled by throwing @code{std::bad_alloc}. See also -+@samp{new (nothrow)}. -+ -+@item -fconserve-space -+@opindex fconserve-space -+Put uninitialized or runtime-initialized global variables into the -+common segment, as C does. This saves space in the executable at the -+cost of not diagnosing duplicate definitions. If you compile with this -+flag and your program mysteriously crashes after @code{main()} has -+completed, you may have an object that is being destroyed twice because -+two definitions were merged. -+ -+This option is no longer useful on most targets, now that support has -+been added for putting variables into BSS without making them common. -+ -+@item -fno-deduce-init-list -+@opindex fno-deduce-init-list -+Disable deduction of a template type parameter as -+std::initializer_list from a brace-enclosed initializer list, i.e. -+ -+@smallexample -+template auto forward(T t) -> decltype (realfn (t)) -+@{ -+ return realfn (t); -+@} -+ -+void f() -+@{ -+ forward(@{1,2@}); // call forward> -+@} -+@end smallexample -+ -+This option is present because this deduction is an extension to the -+current specification in the C++0x working draft, and there was -+some concern about potential overload resolution problems. -+ -+@item -ffriend-injection -+@opindex ffriend-injection -+Inject friend functions into the enclosing namespace, so that they are -+visible outside the scope of the class in which they are declared. -+Friend functions were documented to work this way in the old Annotated -+C++ Reference Manual, and versions of G++ before 4.1 always worked -+that way. However, in ISO C++ a friend function which is not declared -+in an enclosing scope can only be found using argument dependent -+lookup. This option causes friends to be injected as they were in -+earlier releases. -+ -+This option is for compatibility, and may be removed in a future -+release of G++. -+ -+@item -fno-elide-constructors -+@opindex fno-elide-constructors -+The C++ standard allows an implementation to omit creating a temporary -+which is only used to initialize another object of the same type. -+Specifying this option disables that optimization, and forces G++ to -+call the copy constructor in all cases. -+ -+@item -fno-enforce-eh-specs -+@opindex fno-enforce-eh-specs -+Don't generate code to check for violation of exception specifications -+at runtime. This option violates the C++ standard, but may be useful -+for reducing code size in production builds, much like defining -+@samp{NDEBUG}. This does not give user code permission to throw -+exceptions in violation of the exception specifications; the compiler -+will still optimize based on the specifications, so throwing an -+unexpected exception will result in undefined behavior. -+ -+@item -ffor-scope -+@itemx -fno-for-scope -+@opindex ffor-scope -+@opindex fno-for-scope -+If @option{-ffor-scope} is specified, the scope of variables declared in -+a @i{for-init-statement} is limited to the @samp{for} loop itself, -+as specified by the C++ standard. -+If @option{-fno-for-scope} is specified, the scope of variables declared in -+a @i{for-init-statement} extends to the end of the enclosing scope, -+as was the case in old versions of G++, and other (traditional) -+implementations of C++. -+ -+The default if neither flag is given to follow the standard, -+but to allow and give a warning for old-style code that would -+otherwise be invalid, or have different behavior. -+ -+@item -fno-gnu-keywords -+@opindex fno-gnu-keywords -+Do not recognize @code{typeof} as a keyword, so that code can use this -+word as an identifier. You can use the keyword @code{__typeof__} instead. -+@option{-ansi} implies @option{-fno-gnu-keywords}. -+ -+@item -fno-implicit-templates -+@opindex fno-implicit-templates -+Never emit code for non-inline templates which are instantiated -+implicitly (i.e.@: by use); only emit code for explicit instantiations. -+@xref{Template Instantiation}, for more information. -+ -+@item -fno-implicit-inline-templates -+@opindex fno-implicit-inline-templates -+Don't emit code for implicit instantiations of inline templates, either. -+The default is to handle inlines differently so that compiles with and -+without optimization will need the same set of explicit instantiations. -+ -+@item -fno-implement-inlines -+@opindex fno-implement-inlines -+To save space, do not emit out-of-line copies of inline functions -+controlled by @samp{#pragma implementation}. This will cause linker -+errors if these functions are not inlined everywhere they are called. -+ -+@item -fms-extensions -+@opindex fms-extensions -+Disable pedantic warnings about constructs used in MFC, such as implicit -+int and getting a pointer to member function via non-standard syntax. -+ -+@item -fno-nonansi-builtins -+@opindex fno-nonansi-builtins -+Disable built-in declarations of functions that are not mandated by -+ANSI/ISO C@. These include @code{ffs}, @code{alloca}, @code{_exit}, -+@code{index}, @code{bzero}, @code{conjf}, and other related functions. -+ -+@item -fno-operator-names -+@opindex fno-operator-names -+Do not treat the operator name keywords @code{and}, @code{bitand}, -+@code{bitor}, @code{compl}, @code{not}, @code{or} and @code{xor} as -+synonyms as keywords. -+ -+@item -fno-optional-diags -+@opindex fno-optional-diags -+Disable diagnostics that the standard says a compiler does not need to -+issue. Currently, the only such diagnostic issued by G++ is the one for -+a name having multiple meanings within a class. -+ -+@item -fpermissive -+@opindex fpermissive -+Downgrade some diagnostics about nonconformant code from errors to -+warnings. Thus, using @option{-fpermissive} will allow some -+nonconforming code to compile. -+ -+@item -frepo -+@opindex frepo -+Enable automatic template instantiation at link time. This option also -+implies @option{-fno-implicit-templates}. @xref{Template -+Instantiation}, for more information. -+ -+@item -fno-rtti -+@opindex fno-rtti -+Disable generation of information about every class with virtual -+functions for use by the C++ runtime type identification features -+(@samp{dynamic_cast} and @samp{typeid}). If you don't use those parts -+of the language, you can save some space by using this flag. Note that -+exception handling uses the same information, but it will generate it as -+needed. The @samp{dynamic_cast} operator can still be used for casts that -+do not require runtime type information, i.e.@: casts to @code{void *} or to -+unambiguous base classes. -+ -+@item -fstats -+@opindex fstats -+Emit statistics about front-end processing at the end of the compilation. -+This information is generally only useful to the G++ development team. -+ -+@item -ftemplate-depth-@var{n} -+@opindex ftemplate-depth -+Set the maximum instantiation depth for template classes to @var{n}. -+A limit on the template instantiation depth is needed to detect -+endless recursions during template class instantiation. ANSI/ISO C++ -+conforming programs must not rely on a maximum depth greater than 17. -+ -+@item -fno-threadsafe-statics -+@opindex fno-threadsafe-statics -+Do not emit the extra code to use the routines specified in the C++ -+ABI for thread-safe initialization of local statics. You can use this -+option to reduce code size slightly in code that doesn't need to be -+thread-safe. -+ -+@item -fuse-cxa-atexit -+@opindex fuse-cxa-atexit -+Register destructors for objects with static storage duration with the -+@code{__cxa_atexit} function rather than the @code{atexit} function. -+This option is required for fully standards-compliant handling of static -+destructors, but will only work if your C library supports -+@code{__cxa_atexit}. -+ -+@item -fno-use-cxa-get-exception-ptr -+@opindex fno-use-cxa-get-exception-ptr -+Don't use the @code{__cxa_get_exception_ptr} runtime routine. This -+will cause @code{std::uncaught_exception} to be incorrect, but is necessary -+if the runtime routine is not available. -+ -+@item -fvisibility-inlines-hidden -+@opindex fvisibility-inlines-hidden -+This switch declares that the user does not attempt to compare -+pointers to inline methods where the addresses of the two functions -+were taken in different shared objects. -+ -+The effect of this is that GCC may, effectively, mark inline methods with -+@code{__attribute__ ((visibility ("hidden")))} so that they do not -+appear in the export table of a DSO and do not require a PLT indirection -+when used within the DSO@. Enabling this option can have a dramatic effect -+on load and link times of a DSO as it massively reduces the size of the -+dynamic export table when the library makes heavy use of templates. -+ -+The behavior of this switch is not quite the same as marking the -+methods as hidden directly, because it does not affect static variables -+local to the function or cause the compiler to deduce that -+the function is defined in only one shared object. -+ -+You may mark a method as having a visibility explicitly to negate the -+effect of the switch for that method. For example, if you do want to -+compare pointers to a particular inline method, you might mark it as -+having default visibility. Marking the enclosing class with explicit -+visibility will have no effect. -+ -+Explicitly instantiated inline methods are unaffected by this option -+as their linkage might otherwise cross a shared library boundary. -+@xref{Template Instantiation}. -+ -+@item -fvisibility-ms-compat -+@opindex fvisibility-ms-compat -+This flag attempts to use visibility settings to make GCC's C++ -+linkage model compatible with that of Microsoft Visual Studio. -+ -+The flag makes these changes to GCC's linkage model: -+ -+@enumerate -+@item -+It sets the default visibility to @code{hidden}, like -+@option{-fvisibility=hidden}. -+ -+@item -+Types, but not their members, are not hidden by default. -+ -+@item -+The One Definition Rule is relaxed for types without explicit -+visibility specifications which are defined in more than one different -+shared object: those declarations are permitted if they would have -+been permitted when this option was not used. -+@end enumerate -+ -+In new code it is better to use @option{-fvisibility=hidden} and -+export those classes which are intended to be externally visible. -+Unfortunately it is possible for code to rely, perhaps accidentally, -+on the Visual Studio behavior. -+ -+Among the consequences of these changes are that static data members -+of the same type with the same name but defined in different shared -+objects will be different, so changing one will not change the other; -+and that pointers to function members defined in different shared -+objects may not compare equal. When this flag is given, it is a -+violation of the ODR to define types with the same name differently. -+ -+@item -fno-weak -+@opindex fno-weak -+Do not use weak symbol support, even if it is provided by the linker. -+By default, G++ will use weak symbols if they are available. This -+option exists only for testing, and should not be used by end-users; -+it will result in inferior code and has no benefits. This option may -+be removed in a future release of G++. -+ -+@item -nostdinc++ -+@opindex nostdinc++ -+Do not search for header files in the standard directories specific to -+C++, but do still search the other standard directories. (This option -+is used when building the C++ library.) -+@end table -+ -+In addition, these optimization, warning, and code generation options -+have meanings only for C++ programs: -+ -+@table @gcctabopt -+@item -fno-default-inline -+@opindex fno-default-inline -+Do not assume @samp{inline} for functions defined inside a class scope. -+@xref{Optimize Options,,Options That Control Optimization}. Note that these -+functions will have linkage like inline functions; they just won't be -+inlined by default. -+ -+@item -Wabi @r{(C, Objective-C, C++ and Objective-C++ only)} -+@opindex Wabi -+@opindex Wno-abi -+Warn when G++ generates code that is probably not compatible with the -+vendor-neutral C++ ABI@. Although an effort has been made to warn about -+all such cases, there are probably some cases that are not warned about, -+even though G++ is generating incompatible code. There may also be -+cases where warnings are emitted even though the code that is generated -+will be compatible. -+ -+You should rewrite your code to avoid these warnings if you are -+concerned about the fact that code generated by G++ may not be binary -+compatible with code generated by other compilers. -+ -+The known incompatibilities at this point include: -+ -+@itemize @bullet -+ -+@item -+Incorrect handling of tail-padding for bit-fields. G++ may attempt to -+pack data into the same byte as a base class. For example: -+ -+@smallexample -+struct A @{ virtual void f(); int f1 : 1; @}; -+struct B : public A @{ int f2 : 1; @}; -+@end smallexample -+ -+@noindent -+In this case, G++ will place @code{B::f2} into the same byte -+as@code{A::f1}; other compilers will not. You can avoid this problem -+by explicitly padding @code{A} so that its size is a multiple of the -+byte size on your platform; that will cause G++ and other compilers to -+layout @code{B} identically. -+ -+@item -+Incorrect handling of tail-padding for virtual bases. G++ does not use -+tail padding when laying out virtual bases. For example: -+ -+@smallexample -+struct A @{ virtual void f(); char c1; @}; -+struct B @{ B(); char c2; @}; -+struct C : public A, public virtual B @{@}; -+@end smallexample -+ -+@noindent -+In this case, G++ will not place @code{B} into the tail-padding for -+@code{A}; other compilers will. You can avoid this problem by -+explicitly padding @code{A} so that its size is a multiple of its -+alignment (ignoring virtual base classes); that will cause G++ and other -+compilers to layout @code{C} identically. -+ -+@item -+Incorrect handling of bit-fields with declared widths greater than that -+of their underlying types, when the bit-fields appear in a union. For -+example: -+ -+@smallexample -+union U @{ int i : 4096; @}; -+@end smallexample -+ -+@noindent -+Assuming that an @code{int} does not have 4096 bits, G++ will make the -+union too small by the number of bits in an @code{int}. -+ -+@item -+Empty classes can be placed at incorrect offsets. For example: -+ -+@smallexample -+struct A @{@}; -+ -+struct B @{ -+ A a; -+ virtual void f (); -+@}; -+ -+struct C : public B, public A @{@}; -+@end smallexample -+ -+@noindent -+G++ will place the @code{A} base class of @code{C} at a nonzero offset; -+it should be placed at offset zero. G++ mistakenly believes that the -+@code{A} data member of @code{B} is already at offset zero. -+ -+@item -+Names of template functions whose types involve @code{typename} or -+template template parameters can be mangled incorrectly. -+ -+@smallexample -+template -+void f(typename Q::X) @{@} -+ -+template