From d9db1a94a5ed1fb6d4c3c3c55cd01c6e6704ce3b Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Mon, 15 Aug 2016 19:15:13 +0200 Subject: linux: update 4.x kernel, add m68k patch and allow one memory flat --- mk/kernel-ver.mk | 14 +- ...1-net-macb-improve-big-endian-CPU-support.patch | 282 - ...1-net-macb-improve-big-endian-CPU-support.patch | 282 + target/config/Config.in.binfmt | 4 +- target/config/Config.in.kernelversion | 20 +- .../patches/4.1.26/crisv32_ethernet_driver.patch | 4094 -- .../patches/4.1.30/crisv32_ethernet_driver.patch | 4094 ++ .../patches/4.4.14/crisv32_ethernet_driver.patch | 4050 -- .../patches/4.4.17/crisv32_ethernet_driver.patch | 4050 ++ target/linux/patches/4.1.26/aufs.patch | 35215 -------------- target/linux/patches/4.1.26/cleankernel.patch | 11 - target/linux/patches/4.1.26/cris-header.patch | 12 - .../patches/4.1.26/initramfs-nosizelimit.patch | 57 - target/linux/patches/4.1.26/j2-core.patch | 2060 - target/linux/patches/4.1.26/mtd-rootfs.patch | 26 - target/linux/patches/4.1.26/patch-realtime | 28362 ----------- .../linux/patches/4.1.26/regmap-default-on.patch | 17 - target/linux/patches/4.1.26/remove-warn.patch | 11 - target/linux/patches/4.1.26/startup.patch | 37 - target/linux/patches/4.1.26/use-gawk.patch | 24 - .../linux/patches/4.1.26/use-libgcc-for-sh.patch | 29 - target/linux/patches/4.1.30/aufs.patch | 35215 ++++++++++++++ target/linux/patches/4.1.30/cleankernel.patch | 11 + target/linux/patches/4.1.30/cris-header.patch | 12 + .../patches/4.1.30/initramfs-nosizelimit.patch | 57 + target/linux/patches/4.1.30/j2-core.patch | 2060 + target/linux/patches/4.1.30/mtd-rootfs.patch | 26 + target/linux/patches/4.1.30/patch-realtime | 28362 +++++++++++ .../linux/patches/4.1.30/regmap-default-on.patch | 17 + target/linux/patches/4.1.30/remove-warn.patch | 11 + target/linux/patches/4.1.30/startup.patch | 37 + target/linux/patches/4.1.30/use-gawk.patch | 24 + .../linux/patches/4.1.30/use-libgcc-for-sh.patch | 29 + .../linux/patches/4.4.14/coldfire-sighandler.patch | 100 - target/linux/patches/4.4.14/crisv32.patch | 33 - .../patches/4.4.14/initramfs-nosizelimit.patch | 57 - target/linux/patches/4.4.14/ld-or1k.patch | 12 - target/linux/patches/4.4.14/macsonic.patch | 11 - target/linux/patches/4.4.14/mips-xz.patch | 12 - target/linux/patches/4.4.14/patch-realtime | 30649 ------------ target/linux/patches/4.4.14/revert-sparc.patch | 319 - target/linux/patches/4.4.14/startup.patch | 34 - .../linux/patches/4.4.14/use-libgcc-for-sh.patch | 29 - .../linux/patches/4.4.17/coldfire-sighandler.patch | 100 + target/linux/patches/4.4.17/crisv32.patch | 33 + .../patches/4.4.17/initramfs-nosizelimit.patch | 57 + target/linux/patches/4.4.17/ld-or1k.patch | 12 + target/linux/patches/4.4.17/macsonic.patch | 11 + target/linux/patches/4.4.17/mips-xz.patch | 12 + target/linux/patches/4.4.17/patch-realtime | 30649 ++++++++++++ target/linux/patches/4.4.17/revert-sparc.patch | 319 + target/linux/patches/4.4.17/startup.patch | 34 + .../linux/patches/4.4.17/use-libgcc-for-sh.patch | 29 + .../patches/4.1.26/m68k-coldfire-fec.patch | 118 - .../patches/4.1.30/m68k-coldfire-fec.patch | 118 + .../ath79/patches/4.1.26/0001-openwrt-ath79.patch | 47200 ------------------- .../ath79/patches/4.1.30/0001-openwrt-ath79.patch | 47200 +++++++++++++++++++ target/or1k/patches/4.1.26/ld-or1k.patch | 12 - target/or1k/patches/4.1.30/ld-or1k.patch | 12 + 59 files changed, 152890 insertions(+), 152894 deletions(-) delete mode 100644 target/avr32/atmel-ngw100/patches/4.1.26/0001-net-macb-improve-big-endian-CPU-support.patch create mode 100644 target/avr32/atmel-ngw100/patches/4.1.30/0001-net-macb-improve-big-endian-CPU-support.patch delete mode 100644 target/cris/qemu-cris/patches/4.1.26/crisv32_ethernet_driver.patch create mode 100644 target/cris/qemu-cris/patches/4.1.30/crisv32_ethernet_driver.patch delete mode 100644 target/cris/qemu-cris/patches/4.4.14/crisv32_ethernet_driver.patch create mode 100644 target/cris/qemu-cris/patches/4.4.17/crisv32_ethernet_driver.patch delete mode 100644 target/linux/patches/4.1.26/aufs.patch delete mode 100644 target/linux/patches/4.1.26/cleankernel.patch delete mode 100644 target/linux/patches/4.1.26/cris-header.patch delete mode 100644 target/linux/patches/4.1.26/initramfs-nosizelimit.patch delete mode 100644 target/linux/patches/4.1.26/j2-core.patch delete mode 100644 target/linux/patches/4.1.26/mtd-rootfs.patch delete mode 100644 target/linux/patches/4.1.26/patch-realtime delete mode 100644 target/linux/patches/4.1.26/regmap-default-on.patch delete mode 100644 target/linux/patches/4.1.26/remove-warn.patch delete mode 100644 target/linux/patches/4.1.26/startup.patch delete mode 100644 target/linux/patches/4.1.26/use-gawk.patch delete mode 100644 target/linux/patches/4.1.26/use-libgcc-for-sh.patch create mode 100644 target/linux/patches/4.1.30/aufs.patch create mode 100644 target/linux/patches/4.1.30/cleankernel.patch create mode 100644 target/linux/patches/4.1.30/cris-header.patch create mode 100644 target/linux/patches/4.1.30/initramfs-nosizelimit.patch create mode 100644 target/linux/patches/4.1.30/j2-core.patch create mode 100644 target/linux/patches/4.1.30/mtd-rootfs.patch create mode 100644 target/linux/patches/4.1.30/patch-realtime create mode 100644 target/linux/patches/4.1.30/regmap-default-on.patch create mode 100644 target/linux/patches/4.1.30/remove-warn.patch create mode 100644 target/linux/patches/4.1.30/startup.patch create mode 100644 target/linux/patches/4.1.30/use-gawk.patch create mode 100644 target/linux/patches/4.1.30/use-libgcc-for-sh.patch delete mode 100644 target/linux/patches/4.4.14/coldfire-sighandler.patch delete mode 100644 target/linux/patches/4.4.14/crisv32.patch delete mode 100644 target/linux/patches/4.4.14/initramfs-nosizelimit.patch delete mode 100644 target/linux/patches/4.4.14/ld-or1k.patch delete mode 100644 target/linux/patches/4.4.14/macsonic.patch delete mode 100644 target/linux/patches/4.4.14/mips-xz.patch delete mode 100644 target/linux/patches/4.4.14/patch-realtime delete mode 100644 target/linux/patches/4.4.14/revert-sparc.patch delete mode 100644 target/linux/patches/4.4.14/startup.patch delete mode 100644 target/linux/patches/4.4.14/use-libgcc-for-sh.patch create mode 100644 target/linux/patches/4.4.17/coldfire-sighandler.patch create mode 100644 target/linux/patches/4.4.17/crisv32.patch create mode 100644 target/linux/patches/4.4.17/initramfs-nosizelimit.patch create mode 100644 target/linux/patches/4.4.17/ld-or1k.patch create mode 100644 target/linux/patches/4.4.17/macsonic.patch create mode 100644 target/linux/patches/4.4.17/mips-xz.patch create mode 100644 target/linux/patches/4.4.17/patch-realtime create mode 100644 target/linux/patches/4.4.17/revert-sparc.patch create mode 100644 target/linux/patches/4.4.17/startup.patch create mode 100644 target/linux/patches/4.4.17/use-libgcc-for-sh.patch delete mode 100644 target/m68k/qemu-m68k-mcf5208/patches/4.1.26/m68k-coldfire-fec.patch create mode 100644 target/m68k/qemu-m68k-mcf5208/patches/4.1.30/m68k-coldfire-fec.patch delete mode 100644 target/mips/ath79/patches/4.1.26/0001-openwrt-ath79.patch create mode 100644 target/mips/ath79/patches/4.1.30/0001-openwrt-ath79.patch delete mode 100644 target/or1k/patches/4.1.26/ld-or1k.patch create mode 100644 target/or1k/patches/4.1.30/ld-or1k.patch diff --git a/mk/kernel-ver.mk b/mk/kernel-ver.mk index 7b345505e..74c57352c 100644 --- a/mk/kernel-ver.mk +++ b/mk/kernel-ver.mk @@ -25,23 +25,17 @@ KERNEL_RELEASE:= 1 KERNEL_VERSION:= $(KERNEL_FILE_VER)-$(KERNEL_RELEASE) KERNEL_HASH:= 7e2d53c8a36a159c444be8f452eae898fadc1f1862fe470a36c836c3d1d613c5 endif -ifeq ($(ADK_TARGET_KERNEL_VERSION_4_5),y) -KERNEL_FILE_VER:= 4.5.7 -KERNEL_RELEASE:= 1 -KERNEL_VERSION:= $(KERNEL_FILE_VER)-$(KERNEL_RELEASE) -KERNEL_HASH:= c070a62095fe830e7bfdb159e577216e3ed237ad3ab9a2590f53cde4e881fb2b -endif ifeq ($(ADK_TARGET_KERNEL_VERSION_4_4),y) -KERNEL_FILE_VER:= 4.4.14 +KERNEL_FILE_VER:= 4.4.17 KERNEL_RELEASE:= 1 KERNEL_VERSION:= $(KERNEL_FILE_VER)-$(KERNEL_RELEASE) -KERNEL_HASH:= 5953ba12797160a68b1068378f826ddac8a298f8f3273876d3bd18222b0555f9 +KERNEL_HASH:= 159451471c0df6bde8043b85dfacafa58e65c4a0cabb1157e83916326cd04f81 endif ifeq ($(ADK_TARGET_KERNEL_VERSION_4_1),y) -KERNEL_FILE_VER:= 4.1.26 +KERNEL_FILE_VER:= 4.1.30 KERNEL_RELEASE:= 1 KERNEL_VERSION:= $(KERNEL_FILE_VER)-$(KERNEL_RELEASE) -KERNEL_HASH:= babcfca252a1427278b7bc4372fdad40fa1388d8fad2d85ca74cf72222e7f071 +KERNEL_HASH:= 9d22eaaecce666c9e813653bd2a7654849f3f105bdcefe3fe4ee8035f2ad92c6 endif ifeq ($(ADK_TARGET_KERNEL_VERSION_3_18),y) KERNEL_FILE_VER:= 3.18.33 diff --git a/target/avr32/atmel-ngw100/patches/4.1.26/0001-net-macb-improve-big-endian-CPU-support.patch b/target/avr32/atmel-ngw100/patches/4.1.26/0001-net-macb-improve-big-endian-CPU-support.patch deleted file mode 100644 index 96a0a96b6..000000000 --- a/target/avr32/atmel-ngw100/patches/4.1.26/0001-net-macb-improve-big-endian-CPU-support.patch +++ /dev/null @@ -1,282 +0,0 @@ -From f2ce8a9e48385f444389e75cfe293637c3eb5410 Mon Sep 17 00:00:00 2001 -From: Andy Shevchenko -Date: Fri, 24 Jul 2015 21:23:59 +0300 -Subject: [PATCH] net/macb: improve big endian CPU support - -The commit a50dad355a53 (net: macb: Add big endian CPU support) converted I/O -accessors to readl_relaxed() and writel_relaxed() and consequentially broke -MACB driver on AVR32 platforms such as ATNGW100. - -This patch improves I/O access by checking endiannes first and use the -corresponding methods. - -Fixes: a50dad355a53 (net: macb: Add big endian CPU support) -Signed-off-by: Andy Shevchenko -Signed-off-by: David S. Miller -Signed-off-by: Waldemar Brodkorb ---- - drivers/net/ethernet/cadence/macb.c | 103 ++++++++++++++++++++++++++--------- - drivers/net/ethernet/cadence/macb.h | 28 ++++------ - 2 files changed, 87 insertions(+), 44 deletions(-) - -diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c -index caeb395..9d06e3d 100644 ---- a/drivers/net/ethernet/cadence/macb.c -+++ b/drivers/net/ethernet/cadence/macb.c -@@ -104,6 +104,57 @@ static void *macb_rx_buffer(struct macb *bp, unsigned int index) - return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index); - } - -+/* I/O accessors */ -+static u32 hw_readl_native(struct macb *bp, int offset) -+{ -+ return __raw_readl(bp->regs + offset); -+} -+ -+static void hw_writel_native(struct macb *bp, int offset, u32 value) -+{ -+ __raw_writel(value, bp->regs + offset); -+} -+ -+static u32 hw_readl(struct macb *bp, int offset) -+{ -+ return readl_relaxed(bp->regs + offset); -+} -+ -+static void hw_writel(struct macb *bp, int offset, u32 value) -+{ -+ writel_relaxed(value, bp->regs + offset); -+} -+ -+/* -+ * Find the CPU endianness by using the loopback bit of NCR register. When the -+ * CPU is in big endian we need to program swaped mode for management -+ * descriptor access. -+ */ -+static bool hw_is_native_io(void __iomem *addr) -+{ -+ u32 value = MACB_BIT(LLB); -+ -+ __raw_writel(value, addr + MACB_NCR); -+ value = __raw_readl(addr + MACB_NCR); -+ -+ /* Write 0 back to disable everything */ -+ __raw_writel(0, addr + MACB_NCR); -+ -+ return value == MACB_BIT(LLB); -+} -+ -+static bool hw_is_gem(void __iomem *addr, bool native_io) -+{ -+ u32 id; -+ -+ if (native_io) -+ id = __raw_readl(addr + MACB_MID); -+ else -+ id = readl_relaxed(addr + MACB_MID); -+ -+ return MACB_BFEXT(IDNUM, id) >= 0x2; -+} -+ - static void macb_set_hwaddr(struct macb *bp) - { - u32 bottom; -@@ -449,14 +500,14 @@ err_out: - - static void macb_update_stats(struct macb *bp) - { -- u32 __iomem *reg = bp->regs + MACB_PFR; - u32 *p = &bp->hw_stats.macb.rx_pause_frames; - u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1; -+ int offset = MACB_PFR; - - WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); - -- for(; p < end; p++, reg++) -- *p += readl_relaxed(reg); -+ for(; p < end; p++, offset += 4) -+ *p += bp->readl(bp, offset); - } - - static int macb_halt_tx(struct macb *bp) -@@ -1603,7 +1654,6 @@ static u32 macb_dbw(struct macb *bp) - static void macb_configure_dma(struct macb *bp) - { - u32 dmacfg; -- u32 tmp, ncr; - - if (macb_is_gem(bp)) { - dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); -@@ -1613,22 +1663,11 @@ static void macb_configure_dma(struct macb *bp) - dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); - dmacfg &= ~GEM_BIT(ENDIA_PKT); - -- /* Find the CPU endianness by using the loopback bit of net_ctrl -- * register. save it first. When the CPU is in big endian we -- * need to program swaped mode for management descriptor access. -- */ -- ncr = macb_readl(bp, NCR); -- __raw_writel(MACB_BIT(LLB), bp->regs + MACB_NCR); -- tmp = __raw_readl(bp->regs + MACB_NCR); -- -- if (tmp == MACB_BIT(LLB)) -+ if (bp->native_io) - dmacfg &= ~GEM_BIT(ENDIA_DESC); - else - dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */ - -- /* Restore net_ctrl */ -- macb_writel(bp, NCR, ncr); -- - if (bp->dev->features & NETIF_F_HW_CSUM) - dmacfg |= GEM_BIT(TXCOEN); - else -@@ -1902,14 +1941,14 @@ static void gem_update_stats(struct macb *bp) - - for (i = 0; i < GEM_STATS_LEN; ++i, ++p) { - u32 offset = gem_statistics[i].offset; -- u64 val = readl_relaxed(bp->regs + offset); -+ u64 val = bp->readl(bp, offset); - - bp->ethtool_stats[i] += val; - *p += val; - - if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) { - /* Add GEM_OCTTXH, GEM_OCTRXH */ -- val = readl_relaxed(bp->regs + offset + 4); -+ val = bp->readl(bp, offset + 4); - bp->ethtool_stats[i] += ((u64)val) << 32; - *(++p) += val; - } -@@ -2190,7 +2229,7 @@ static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_co - if (dt_conf) - bp->caps = dt_conf->caps; - -- if (macb_is_gem_hw(bp->regs)) { -+ if (hw_is_gem(bp->regs, bp->native_io)) { - bp->caps |= MACB_CAPS_MACB_IS_GEM; - - dcfg = gem_readl(bp, DCFG1); -@@ -2205,6 +2244,7 @@ static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_co - } - - static void macb_probe_queues(void __iomem *mem, -+ bool native_io, - unsigned int *queue_mask, - unsigned int *num_queues) - { -@@ -2219,7 +2259,7 @@ static void macb_probe_queues(void __iomem *mem, - * we are early in the probe process and don't have the - * MACB_CAPS_MACB_IS_GEM flag positioned - */ -- if (!macb_is_gem_hw(mem)) -+ if (!hw_is_gem(mem, native_io)) - return; - - /* bit 0 is never set but queue 0 always exists */ -@@ -2786,6 +2826,7 @@ static int macb_probe(struct platform_device *pdev) - struct clk *pclk, *hclk, *tx_clk; - unsigned int queue_mask, num_queues; - struct macb_platform_data *pdata; -+ bool native_io; - struct phy_device *phydev; - struct net_device *dev; - struct resource *regs; -@@ -2794,6 +2835,11 @@ static int macb_probe(struct platform_device *pdev) - struct macb *bp; - int err; - -+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ mem = devm_ioremap_resource(&pdev->dev, regs); -+ if (IS_ERR(mem)) -+ return PTR_ERR(mem); -+ - if (np) { - const struct of_device_id *match; - -@@ -2809,14 +2855,9 @@ static int macb_probe(struct platform_device *pdev) - if (err) - return err; - -- regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- mem = devm_ioremap_resource(&pdev->dev, regs); -- if (IS_ERR(mem)) { -- err = PTR_ERR(mem); -- goto err_disable_clocks; -- } -+ native_io = hw_is_native_io(mem); - -- macb_probe_queues(mem, &queue_mask, &num_queues); -+ macb_probe_queues(mem, native_io, &queue_mask, &num_queues); - dev = alloc_etherdev_mq(sizeof(*bp), num_queues); - if (!dev) { - err = -ENOMEM; -@@ -2831,6 +2872,14 @@ static int macb_probe(struct platform_device *pdev) - bp->pdev = pdev; - bp->dev = dev; - bp->regs = mem; -+ bp->native_io = native_io; -+ if (native_io) { -+ bp->readl = hw_readl_native; -+ bp->writel = hw_writel_native; -+ } else { -+ bp->readl = hw_readl; -+ bp->writel = hw_writel; -+ } - bp->num_queues = num_queues; - bp->queue_mask = queue_mask; - if (macb_config) -diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h -index d746559..f245340 100644 ---- a/drivers/net/ethernet/cadence/macb.h -+++ b/drivers/net/ethernet/cadence/macb.h -@@ -429,18 +429,12 @@ - | GEM_BF(name, value)) - - /* Register access macros */ --#define macb_readl(port,reg) \ -- readl_relaxed((port)->regs + MACB_##reg) --#define macb_writel(port,reg,value) \ -- writel_relaxed((value), (port)->regs + MACB_##reg) --#define gem_readl(port, reg) \ -- readl_relaxed((port)->regs + GEM_##reg) --#define gem_writel(port, reg, value) \ -- writel_relaxed((value), (port)->regs + GEM_##reg) --#define queue_readl(queue, reg) \ -- readl_relaxed((queue)->bp->regs + (queue)->reg) --#define queue_writel(queue, reg, value) \ -- writel_relaxed((value), (queue)->bp->regs + (queue)->reg) -+#define macb_readl(port, reg) (port)->readl((port), MACB_##reg) -+#define macb_writel(port, reg, value) (port)->writel((port), MACB_##reg, (value)) -+#define gem_readl(port, reg) (port)->readl((port), GEM_##reg) -+#define gem_writel(port, reg, value) (port)->writel((port), GEM_##reg, (value)) -+#define queue_readl(queue, reg) (queue)->bp->readl((queue)->bp, (queue)->reg) -+#define queue_writel(queue, reg, value) (queue)->bp->writel((queue)->bp, (queue)->reg, (value)) - - /* Conditional GEM/MACB macros. These perform the operation to the correct - * register dependent on whether the device is a GEM or a MACB. For registers -@@ -785,6 +779,11 @@ struct macb_queue { - - struct macb { - void __iomem *regs; -+ bool native_io; -+ -+ /* hardware IO accessors */ -+ u32 (*readl)(struct macb *bp, int offset); -+ void (*writel)(struct macb *bp, int offset, u32 value); - - unsigned int rx_tail; - unsigned int rx_prepared_head; -@@ -843,9 +842,4 @@ static inline bool macb_is_gem(struct macb *bp) - return !!(bp->caps & MACB_CAPS_MACB_IS_GEM); - } - --static inline bool macb_is_gem_hw(void __iomem *addr) --{ -- return !!(MACB_BFEXT(IDNUM, readl_relaxed(addr + MACB_MID)) >= 0x2); --} -- - #endif /* _MACB_H */ --- -1.7.10.4 - diff --git a/target/avr32/atmel-ngw100/patches/4.1.30/0001-net-macb-improve-big-endian-CPU-support.patch b/target/avr32/atmel-ngw100/patches/4.1.30/0001-net-macb-improve-big-endian-CPU-support.patch new file mode 100644 index 000000000..96a0a96b6 --- /dev/null +++ b/target/avr32/atmel-ngw100/patches/4.1.30/0001-net-macb-improve-big-endian-CPU-support.patch @@ -0,0 +1,282 @@ +From f2ce8a9e48385f444389e75cfe293637c3eb5410 Mon Sep 17 00:00:00 2001 +From: Andy Shevchenko +Date: Fri, 24 Jul 2015 21:23:59 +0300 +Subject: [PATCH] net/macb: improve big endian CPU support + +The commit a50dad355a53 (net: macb: Add big endian CPU support) converted I/O +accessors to readl_relaxed() and writel_relaxed() and consequentially broke +MACB driver on AVR32 platforms such as ATNGW100. + +This patch improves I/O access by checking endiannes first and use the +corresponding methods. + +Fixes: a50dad355a53 (net: macb: Add big endian CPU support) +Signed-off-by: Andy Shevchenko +Signed-off-by: David S. Miller +Signed-off-by: Waldemar Brodkorb +--- + drivers/net/ethernet/cadence/macb.c | 103 ++++++++++++++++++++++++++--------- + drivers/net/ethernet/cadence/macb.h | 28 ++++------ + 2 files changed, 87 insertions(+), 44 deletions(-) + +diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c +index caeb395..9d06e3d 100644 +--- a/drivers/net/ethernet/cadence/macb.c ++++ b/drivers/net/ethernet/cadence/macb.c +@@ -104,6 +104,57 @@ static void *macb_rx_buffer(struct macb *bp, unsigned int index) + return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index); + } + ++/* I/O accessors */ ++static u32 hw_readl_native(struct macb *bp, int offset) ++{ ++ return __raw_readl(bp->regs + offset); ++} ++ ++static void hw_writel_native(struct macb *bp, int offset, u32 value) ++{ ++ __raw_writel(value, bp->regs + offset); ++} ++ ++static u32 hw_readl(struct macb *bp, int offset) ++{ ++ return readl_relaxed(bp->regs + offset); ++} ++ ++static void hw_writel(struct macb *bp, int offset, u32 value) ++{ ++ writel_relaxed(value, bp->regs + offset); ++} ++ ++/* ++ * Find the CPU endianness by using the loopback bit of NCR register. When the ++ * CPU is in big endian we need to program swaped mode for management ++ * descriptor access. ++ */ ++static bool hw_is_native_io(void __iomem *addr) ++{ ++ u32 value = MACB_BIT(LLB); ++ ++ __raw_writel(value, addr + MACB_NCR); ++ value = __raw_readl(addr + MACB_NCR); ++ ++ /* Write 0 back to disable everything */ ++ __raw_writel(0, addr + MACB_NCR); ++ ++ return value == MACB_BIT(LLB); ++} ++ ++static bool hw_is_gem(void __iomem *addr, bool native_io) ++{ ++ u32 id; ++ ++ if (native_io) ++ id = __raw_readl(addr + MACB_MID); ++ else ++ id = readl_relaxed(addr + MACB_MID); ++ ++ return MACB_BFEXT(IDNUM, id) >= 0x2; ++} ++ + static void macb_set_hwaddr(struct macb *bp) + { + u32 bottom; +@@ -449,14 +500,14 @@ err_out: + + static void macb_update_stats(struct macb *bp) + { +- u32 __iomem *reg = bp->regs + MACB_PFR; + u32 *p = &bp->hw_stats.macb.rx_pause_frames; + u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1; ++ int offset = MACB_PFR; + + WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); + +- for(; p < end; p++, reg++) +- *p += readl_relaxed(reg); ++ for(; p < end; p++, offset += 4) ++ *p += bp->readl(bp, offset); + } + + static int macb_halt_tx(struct macb *bp) +@@ -1603,7 +1654,6 @@ static u32 macb_dbw(struct macb *bp) + static void macb_configure_dma(struct macb *bp) + { + u32 dmacfg; +- u32 tmp, ncr; + + if (macb_is_gem(bp)) { + dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); +@@ -1613,22 +1663,11 @@ static void macb_configure_dma(struct macb *bp) + dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); + dmacfg &= ~GEM_BIT(ENDIA_PKT); + +- /* Find the CPU endianness by using the loopback bit of net_ctrl +- * register. save it first. When the CPU is in big endian we +- * need to program swaped mode for management descriptor access. +- */ +- ncr = macb_readl(bp, NCR); +- __raw_writel(MACB_BIT(LLB), bp->regs + MACB_NCR); +- tmp = __raw_readl(bp->regs + MACB_NCR); +- +- if (tmp == MACB_BIT(LLB)) ++ if (bp->native_io) + dmacfg &= ~GEM_BIT(ENDIA_DESC); + else + dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */ + +- /* Restore net_ctrl */ +- macb_writel(bp, NCR, ncr); +- + if (bp->dev->features & NETIF_F_HW_CSUM) + dmacfg |= GEM_BIT(TXCOEN); + else +@@ -1902,14 +1941,14 @@ static void gem_update_stats(struct macb *bp) + + for (i = 0; i < GEM_STATS_LEN; ++i, ++p) { + u32 offset = gem_statistics[i].offset; +- u64 val = readl_relaxed(bp->regs + offset); ++ u64 val = bp->readl(bp, offset); + + bp->ethtool_stats[i] += val; + *p += val; + + if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) { + /* Add GEM_OCTTXH, GEM_OCTRXH */ +- val = readl_relaxed(bp->regs + offset + 4); ++ val = bp->readl(bp, offset + 4); + bp->ethtool_stats[i] += ((u64)val) << 32; + *(++p) += val; + } +@@ -2190,7 +2229,7 @@ static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_co + if (dt_conf) + bp->caps = dt_conf->caps; + +- if (macb_is_gem_hw(bp->regs)) { ++ if (hw_is_gem(bp->regs, bp->native_io)) { + bp->caps |= MACB_CAPS_MACB_IS_GEM; + + dcfg = gem_readl(bp, DCFG1); +@@ -2205,6 +2244,7 @@ static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_co + } + + static void macb_probe_queues(void __iomem *mem, ++ bool native_io, + unsigned int *queue_mask, + unsigned int *num_queues) + { +@@ -2219,7 +2259,7 @@ static void macb_probe_queues(void __iomem *mem, + * we are early in the probe process and don't have the + * MACB_CAPS_MACB_IS_GEM flag positioned + */ +- if (!macb_is_gem_hw(mem)) ++ if (!hw_is_gem(mem, native_io)) + return; + + /* bit 0 is never set but queue 0 always exists */ +@@ -2786,6 +2826,7 @@ static int macb_probe(struct platform_device *pdev) + struct clk *pclk, *hclk, *tx_clk; + unsigned int queue_mask, num_queues; + struct macb_platform_data *pdata; ++ bool native_io; + struct phy_device *phydev; + struct net_device *dev; + struct resource *regs; +@@ -2794,6 +2835,11 @@ static int macb_probe(struct platform_device *pdev) + struct macb *bp; + int err; + ++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ mem = devm_ioremap_resource(&pdev->dev, regs); ++ if (IS_ERR(mem)) ++ return PTR_ERR(mem); ++ + if (np) { + const struct of_device_id *match; + +@@ -2809,14 +2855,9 @@ static int macb_probe(struct platform_device *pdev) + if (err) + return err; + +- regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- mem = devm_ioremap_resource(&pdev->dev, regs); +- if (IS_ERR(mem)) { +- err = PTR_ERR(mem); +- goto err_disable_clocks; +- } ++ native_io = hw_is_native_io(mem); + +- macb_probe_queues(mem, &queue_mask, &num_queues); ++ macb_probe_queues(mem, native_io, &queue_mask, &num_queues); + dev = alloc_etherdev_mq(sizeof(*bp), num_queues); + if (!dev) { + err = -ENOMEM; +@@ -2831,6 +2872,14 @@ static int macb_probe(struct platform_device *pdev) + bp->pdev = pdev; + bp->dev = dev; + bp->regs = mem; ++ bp->native_io = native_io; ++ if (native_io) { ++ bp->readl = hw_readl_native; ++ bp->writel = hw_writel_native; ++ } else { ++ bp->readl = hw_readl; ++ bp->writel = hw_writel; ++ } + bp->num_queues = num_queues; + bp->queue_mask = queue_mask; + if (macb_config) +diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h +index d746559..f245340 100644 +--- a/drivers/net/ethernet/cadence/macb.h ++++ b/drivers/net/ethernet/cadence/macb.h +@@ -429,18 +429,12 @@ + | GEM_BF(name, value)) + + /* Register access macros */ +-#define macb_readl(port,reg) \ +- readl_relaxed((port)->regs + MACB_##reg) +-#define macb_writel(port,reg,value) \ +- writel_relaxed((value), (port)->regs + MACB_##reg) +-#define gem_readl(port, reg) \ +- readl_relaxed((port)->regs + GEM_##reg) +-#define gem_writel(port, reg, value) \ +- writel_relaxed((value), (port)->regs + GEM_##reg) +-#define queue_readl(queue, reg) \ +- readl_relaxed((queue)->bp->regs + (queue)->reg) +-#define queue_writel(queue, reg, value) \ +- writel_relaxed((value), (queue)->bp->regs + (queue)->reg) ++#define macb_readl(port, reg) (port)->readl((port), MACB_##reg) ++#define macb_writel(port, reg, value) (port)->writel((port), MACB_##reg, (value)) ++#define gem_readl(port, reg) (port)->readl((port), GEM_##reg) ++#define gem_writel(port, reg, value) (port)->writel((port), GEM_##reg, (value)) ++#define queue_readl(queue, reg) (queue)->bp->readl((queue)->bp, (queue)->reg) ++#define queue_writel(queue, reg, value) (queue)->bp->writel((queue)->bp, (queue)->reg, (value)) + + /* Conditional GEM/MACB macros. These perform the operation to the correct + * register dependent on whether the device is a GEM or a MACB. For registers +@@ -785,6 +779,11 @@ struct macb_queue { + + struct macb { + void __iomem *regs; ++ bool native_io; ++ ++ /* hardware IO accessors */ ++ u32 (*readl)(struct macb *bp, int offset); ++ void (*writel)(struct macb *bp, int offset, u32 value); + + unsigned int rx_tail; + unsigned int rx_prepared_head; +@@ -843,9 +842,4 @@ static inline bool macb_is_gem(struct macb *bp) + return !!(bp->caps & MACB_CAPS_MACB_IS_GEM); + } + +-static inline bool macb_is_gem_hw(void __iomem *addr) +-{ +- return !!(MACB_BFEXT(IDNUM, readl_relaxed(addr + MACB_MID)) >= 0x2); +-} +- + #endif /* _MACB_H */ +-- +1.7.10.4 + diff --git a/target/config/Config.in.binfmt b/target/config/Config.in.binfmt index 3b88791d6..69da78a44 100644 --- a/target/config/Config.in.binfmt +++ b/target/config/Config.in.binfmt @@ -33,13 +33,13 @@ default ADK_TARGET_BINFMT_FLAT_ONE config ADK_TARGET_BINFMT_FLAT_ONE bool "One memory region" - depends on ADK_TARGET_ARCH_BFIN + depends on ADK_TARGET_ARCH_BFIN || ADK_TARGET_ARCH_M68K help All segments are linked into one memory region. config ADK_TARGET_BINFMT_FLAT_SEP_DATA bool "Separate data and code region" - depends on ADK_TARGET_ARCH_M68K || ADK_TARGET_ARCH_BFIN + depends on ADK_TARGET_ARCH_BFIN || ADK_TARGET_ARCH_M68K help Allow for the data and text segments to be separated and placed in different regions of memory. diff --git a/target/config/Config.in.kernelversion b/target/config/Config.in.kernelversion index 653a332d2..ab2041114 100644 --- a/target/config/Config.in.kernelversion +++ b/target/config/Config.in.kernelversion @@ -24,22 +24,16 @@ config ADK_TARGET_KERNEL_VERSION_4_6 bool "4.6.5" depends on !ADK_TARGET_ARCH_NDS32 -config ADK_TARGET_KERNEL_VERSION_4_5 - bool "4.5.7" - depends on !ADK_TARGET_ARCH_NDS32 - depends on !ADK_TARGET_ARCH_NIOS2 - depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 - depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 - config ADK_TARGET_KERNEL_VERSION_4_4 - bool "4.4.14" + bool "4.4.17" depends on !ADK_TARGET_ARCH_NDS32 depends on !ADK_TARGET_ARCH_NIOS2 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 + depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 config ADK_TARGET_KERNEL_VERSION_4_1 - bool "4.1.26" + bool "4.1.30" depends on !ADK_TARGET_ARCH_ARC depends on !ADK_TARGET_ARCH_BFIN depends on !ADK_TARGET_ARCH_H8300 @@ -47,6 +41,7 @@ config ADK_TARGET_KERNEL_VERSION_4_1 depends on !ADK_TARGET_ARCH_NDS32 depends on !ADK_TARGET_ARCH_SPARC depends on !ADK_TARGET_SYSTEM_KINETIS_K70 + depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 @@ -63,6 +58,7 @@ config ADK_TARGET_KERNEL_VERSION_3_18 depends on !ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 depends on !ADK_TARGET_SYSTEM_KINETIS_K70 depends on !ADK_TARGET_SYSTEM_BEAGLEBONE_BLACK + depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 @@ -77,6 +73,7 @@ config ADK_TARGET_KERNEL_VERSION_3_14 depends on !ADK_TARGET_BOARD_ATH79 depends on !ADK_TARGET_BOARD_BCM28XX depends on !ADK_TARGET_SYSTEM_KINETIS_K70 + depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 @@ -93,6 +90,7 @@ config ADK_TARGET_KERNEL_VERSION_3_12 depends on !ADK_TARGET_SYSTEM_BEAGLEBONE_BLACK depends on !ADK_TARGET_SYSTEM_KINETIS_K70 depends on !ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 + depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 @@ -110,6 +108,7 @@ config ADK_TARGET_KERNEL_VERSION_3_10 depends on !ADK_TARGET_SYSTEM_KINETIS_K70 depends on !ADK_TARGET_SYSTEM_MIKROTIK_RB4XX depends on !ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 + depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 @@ -125,6 +124,7 @@ config ADK_TARGET_KERNEL_VERSION_3_4 depends on !ADK_TARGET_SYSTEM_BEAGLEBONE_BLACK depends on !ADK_TARGET_SYSTEM_KINETIS_K70 depends on !ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 + depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 @@ -141,6 +141,7 @@ config ADK_TARGET_KERNEL_VERSION_3_2 depends on !ADK_TARGET_SYSTEM_BEAGLEBONE_BLACK depends on !ADK_TARGET_SYSTEM_KINETIS_K70 depends on !ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 + depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 @@ -157,6 +158,7 @@ config ADK_TARGET_KERNEL_VERSION_2_6_32 depends on !ADK_TARGET_SYSTEM_BEAGLEBONE_BLACK depends on !ADK_TARGET_SYSTEM_KINETIS_K70 depends on !ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 + depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 diff --git a/target/cris/qemu-cris/patches/4.1.26/crisv32_ethernet_driver.patch b/target/cris/qemu-cris/patches/4.1.26/crisv32_ethernet_driver.patch deleted file mode 100644 index cd098665e..000000000 --- a/target/cris/qemu-cris/patches/4.1.26/crisv32_ethernet_driver.patch +++ /dev/null @@ -1,4094 +0,0 @@ -diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig -index e6c523c..5737a5b 100644 ---- a/arch/cris/arch-v32/drivers/Kconfig -+++ b/arch/cris/arch-v32/drivers/Kconfig -@@ -8,9 +8,18 @@ config ETRAX_ETHERNET - This option enables the ETRAX FS built-in 10/100Mbit Ethernet - controller. - -+config ETRAX_HAVE_PHY -+ bool "PHY present" -+ default y -+ help -+ Search and use the first PHY available on the MDIO bus. Fail -+ if none is found. Say Y here if you are not in a switched -+ environment (single port device). -+ - config ETRAX_NO_PHY - bool "PHY not present" - depends on ETRAX_ETHERNET -+ default n - help - This option disables all MDIO communication with an ethernet - transceiver connected to the MII interface. This option shall -@@ -18,6 +27,70 @@ config ETRAX_NO_PHY - switch. This option should normally be disabled. If enabled, - speed and duplex will be locked to 100 Mbit and full duplex. - -+config ETRAX_PHY_FALLBACK -+ bool "Fixed PHY fallback" -+ depends on ETRAX_ETHERNET -+ default n -+ help -+ If no PHY is found on the MDIO bus, fall back on a fixed -+ 100/Full fixed PHY. Say Y here if you need dynamic PHY -+ presence detection (switch connection where some but not -+ all ports have integrated PHYs), otherwise say N. -+ -+config ETRAX_ETHERNET_IFACE0 -+ depends on ETRAX_ETHERNET -+ bool "Enable network interface 0" -+ -+config ETRAX_ETHERNET_IFACE1 -+ depends on (ETRAX_ETHERNET && ETRAXFS) -+ bool "Enable network interface 1 (uses DMA6 and DMA7)" -+ -+choice -+ prompt "Eth0 led group" -+ depends on ETRAX_ETHERNET_IFACE0 -+ default ETRAX_ETH0_USE_LEDGRP0 -+ -+config ETRAX_ETH0_USE_LEDGRP0 -+ bool "Use LED grp 0" -+ depends on ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO -+ help -+ Use LED grp 0 for eth0 -+ -+config ETRAX_ETH0_USE_LEDGRP1 -+ bool "Use LED grp 1" -+ depends on ETRAX_NBR_LED_GRP_TWO -+ help -+ Use LED grp 1 for eth0 -+ -+config ETRAX_ETH0_USE_LEDGRPNULL -+ bool "Use no LEDs for eth0" -+ help -+ Use no LEDs for eth0 -+endchoice -+ -+choice -+ prompt "Eth1 led group" -+ depends on ETRAX_ETHERNET_IFACE1 -+ default ETRAX_ETH1_USE_LEDGRP1 -+ -+config ETRAX_ETH1_USE_LEDGRP0 -+ bool "Use LED grp 0" -+ depends on ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO -+ help -+ Use LED grp 0 for eth1 -+ -+config ETRAX_ETH1_USE_LEDGRP1 -+ bool "Use LED grp 1" -+ depends on ETRAX_NBR_LED_GRP_TWO -+ help -+ Use LED grp 1 for eth1 -+ -+config ETRAX_ETH1_USE_LEDGRPNULL -+ bool "Use no LEDs for eth1" -+ help -+ Use no LEDs for eth1 -+endchoice -+ - config ETRAXFS_SERIAL - bool "Serial-port support" - depends on ETRAX_ARCH_V32 -diff --git a/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h b/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h -index 90fe8a2..37bec9a 100644 ---- a/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h -+++ b/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h -@@ -2,69 +2,64 @@ - #define __eth_defs_h - - /* -- * This file is autogenerated from -- * file: eth.r -- * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp -- * last modfied: Mon Jan 9 06:06:41 2006 -- * -- * by /n/asic/design/tools/rdesc/rdes2c eth.r -- * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $ -- * Any changes here will be lost. -- * -- * -*- buffer-read-only: t -*- -+ * Note: Previously this was autogenerated code from the hardware -+ * implementation. However, to enable the same file to be used -+ * for both ARTPEC-3 and ETRAX FS this file is now hand-edited. -+ * Be careful. - */ -+ - /* Main access macros */ - #ifndef REG_RD - #define REG_RD( scope, inst, reg ) \ -- REG_READ( reg_##scope##_##reg, \ -- (inst) + REG_RD_ADDR_##scope##_##reg ) -+ REG_READ( reg_##scope##_##reg, \ -+ (inst) + REG_RD_ADDR_##scope##_##reg ) - #endif - - #ifndef REG_WR - #define REG_WR( scope, inst, reg, val ) \ -- REG_WRITE( reg_##scope##_##reg, \ -- (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -+ REG_WRITE( reg_##scope##_##reg, \ -+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) - #endif - - #ifndef REG_RD_VECT - #define REG_RD_VECT( scope, inst, reg, index ) \ -- REG_READ( reg_##scope##_##reg, \ -- (inst) + REG_RD_ADDR_##scope##_##reg + \ -- (index) * STRIDE_##scope##_##reg ) -+ REG_READ( reg_##scope##_##reg, \ -+ (inst) + REG_RD_ADDR_##scope##_##reg + \ -+ (index) * STRIDE_##scope##_##reg ) - #endif - - #ifndef REG_WR_VECT - #define REG_WR_VECT( scope, inst, reg, index, val ) \ -- REG_WRITE( reg_##scope##_##reg, \ -- (inst) + REG_WR_ADDR_##scope##_##reg + \ -- (index) * STRIDE_##scope##_##reg, (val) ) -+ REG_WRITE( reg_##scope##_##reg, \ -+ (inst) + REG_WR_ADDR_##scope##_##reg + \ -+ (index) * STRIDE_##scope##_##reg, (val) ) - #endif - - #ifndef REG_RD_INT - #define REG_RD_INT( scope, inst, reg ) \ -- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) - #endif - - #ifndef REG_WR_INT - #define REG_WR_INT( scope, inst, reg, val ) \ -- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) - #endif - - #ifndef REG_RD_INT_VECT - #define REG_RD_INT_VECT( scope, inst, reg, index ) \ -- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ -- (index) * STRIDE_##scope##_##reg ) -+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ -+ (index) * STRIDE_##scope##_##reg ) - #endif - - #ifndef REG_WR_INT_VECT - #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ -- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ -- (index) * STRIDE_##scope##_##reg, (val) ) -+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ -+ (index) * STRIDE_##scope##_##reg, (val) ) - #endif - - #ifndef REG_TYPE_CONV - #define REG_TYPE_CONV( type, orgtype, val ) \ -- ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) - #endif - - #ifndef reg_page_size -@@ -73,306 +68,332 @@ - - #ifndef REG_ADDR - #define REG_ADDR( scope, inst, reg ) \ -- ( (inst) + REG_RD_ADDR_##scope##_##reg ) -+ ( (inst) + REG_RD_ADDR_##scope##_##reg ) - #endif - - #ifndef REG_ADDR_VECT - #define REG_ADDR_VECT( scope, inst, reg, index ) \ -- ( (inst) + REG_RD_ADDR_##scope##_##reg + \ -- (index) * STRIDE_##scope##_##reg ) -+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \ -+ (index) * STRIDE_##scope##_##reg ) - #endif - - /* C-code for register scope eth */ - - /* Register rw_ma0_lo, scope eth, type rw */ - typedef struct { -- unsigned int addr : 32; -+ unsigned int addr : 32; - } reg_eth_rw_ma0_lo; - #define REG_RD_ADDR_eth_rw_ma0_lo 0 - #define REG_WR_ADDR_eth_rw_ma0_lo 0 - - /* Register rw_ma0_hi, scope eth, type rw */ - typedef struct { -- unsigned int addr : 16; -- unsigned int dummy1 : 16; -+ unsigned int addr : 16; -+ unsigned int dummy1 : 16; - } reg_eth_rw_ma0_hi; - #define REG_RD_ADDR_eth_rw_ma0_hi 4 - #define REG_WR_ADDR_eth_rw_ma0_hi 4 - - /* Register rw_ma1_lo, scope eth, type rw */ - typedef struct { -- unsigned int addr : 32; -+ unsigned int addr : 32; - } reg_eth_rw_ma1_lo; - #define REG_RD_ADDR_eth_rw_ma1_lo 8 - #define REG_WR_ADDR_eth_rw_ma1_lo 8 - - /* Register rw_ma1_hi, scope eth, type rw */ - typedef struct { -- unsigned int addr : 16; -- unsigned int dummy1 : 16; -+ unsigned int addr : 16; -+ unsigned int dummy1 : 16; - } reg_eth_rw_ma1_hi; - #define REG_RD_ADDR_eth_rw_ma1_hi 12 - #define REG_WR_ADDR_eth_rw_ma1_hi 12 - - /* Register rw_ga_lo, scope eth, type rw */ - typedef struct { -- unsigned int tbl : 32; -+ unsigned int table : 32; - } reg_eth_rw_ga_lo; - #define REG_RD_ADDR_eth_rw_ga_lo 16 - #define REG_WR_ADDR_eth_rw_ga_lo 16 - - /* Register rw_ga_hi, scope eth, type rw */ - typedef struct { -- unsigned int tbl : 32; -+ unsigned int table : 32; - } reg_eth_rw_ga_hi; - #define REG_RD_ADDR_eth_rw_ga_hi 20 - #define REG_WR_ADDR_eth_rw_ga_hi 20 - - /* Register rw_gen_ctrl, scope eth, type rw */ - typedef struct { -- unsigned int en : 1; -- unsigned int phy : 2; -- unsigned int protocol : 1; -- unsigned int loopback : 1; -- unsigned int flow_ctrl : 1; -- unsigned int gtxclk_out : 1; -- unsigned int phyrst_n : 1; -- unsigned int dummy1 : 24; -+ unsigned int en : 1; -+ unsigned int phy : 2; -+ unsigned int protocol : 1; -+ unsigned int loopback : 1; -+ unsigned int flow_ctrl : 1; -+ unsigned int gtxclk_out : 1; -+ unsigned int phyrst_n : 1; -+ unsigned int dummy1 : 24; - } reg_eth_rw_gen_ctrl; - #define REG_RD_ADDR_eth_rw_gen_ctrl 24 - #define REG_WR_ADDR_eth_rw_gen_ctrl 24 - - /* Register rw_rec_ctrl, scope eth, type rw */ - typedef struct { -- unsigned int ma0 : 1; -- unsigned int ma1 : 1; -- unsigned int individual : 1; -- unsigned int broadcast : 1; -- unsigned int undersize : 1; -- unsigned int oversize : 1; -- unsigned int bad_crc : 1; -- unsigned int duplex : 1; -- unsigned int max_size : 16; -- unsigned int dummy1 : 8; -+ unsigned int ma0 : 1; -+ unsigned int ma1 : 1; -+ unsigned int individual : 1; -+ unsigned int broadcast : 1; -+ unsigned int undersize : 1; -+ unsigned int oversize : 1; -+ unsigned int bad_crc : 1; -+ unsigned int duplex : 1; -+#ifdef CONFIG_CRIS_MACH_ARTPEC3 -+ unsigned int max_size : 16; -+ unsigned int dummy1 : 8; -+#else -+ unsigned int max_size : 1; -+ unsigned int dummy1 : 23; -+#endif - } reg_eth_rw_rec_ctrl; - #define REG_RD_ADDR_eth_rw_rec_ctrl 28 - #define REG_WR_ADDR_eth_rw_rec_ctrl 28 - - /* Register rw_tr_ctrl, scope eth, type rw */ - typedef struct { -- unsigned int crc : 1; -- unsigned int pad : 1; -- unsigned int retry : 1; -- unsigned int ignore_col : 1; -- unsigned int cancel : 1; -- unsigned int hsh_delay : 1; -- unsigned int ignore_crs : 1; -- unsigned int carrier_ext : 1; -- unsigned int dummy1 : 24; -+ unsigned int crc : 1; -+ unsigned int pad : 1; -+ unsigned int retry : 1; -+ unsigned int ignore_col : 1; -+ unsigned int cancel : 1; -+ unsigned int hsh_delay : 1; -+ unsigned int ignore_crs : 1; -+ unsigned int carrier_ext : 1; -+ unsigned int dummy1 : 24; - } reg_eth_rw_tr_ctrl; - #define REG_RD_ADDR_eth_rw_tr_ctrl 32 - #define REG_WR_ADDR_eth_rw_tr_ctrl 32 - - /* Register rw_clr_err, scope eth, type rw */ - typedef struct { -- unsigned int clr : 1; -- unsigned int dummy1 : 31; -+ unsigned int clr : 1; -+ unsigned int dummy1 : 31; - } reg_eth_rw_clr_err; - #define REG_RD_ADDR_eth_rw_clr_err 36 - #define REG_WR_ADDR_eth_rw_clr_err 36 - - /* Register rw_mgm_ctrl, scope eth, type rw */ - typedef struct { -- unsigned int mdio : 1; -- unsigned int mdoe : 1; -- unsigned int mdc : 1; -- unsigned int dummy1 : 29; -+ unsigned int mdio : 1; -+ unsigned int mdoe : 1; -+ unsigned int mdc : 1; -+ unsigned int phyclk : 1; -+ unsigned int txdata : 4; -+ unsigned int txen : 1; -+ unsigned int dummy1 : 23; - } reg_eth_rw_mgm_ctrl; - #define REG_RD_ADDR_eth_rw_mgm_ctrl 40 - #define REG_WR_ADDR_eth_rw_mgm_ctrl 40 - - /* Register r_stat, scope eth, type r */ - typedef struct { -- unsigned int mdio : 1; -- unsigned int exc_col : 1; -- unsigned int urun : 1; -- unsigned int clk_125 : 1; -- unsigned int dummy1 : 28; -+ unsigned int mdio : 1; -+ unsigned int exc_col : 1; -+ unsigned int urun : 1; -+#ifdef CONFIG_CRIS_MACH_ARTPEC3 -+ unsigned int clk_125 : 1; -+#else -+ unsigned int phyclk : 1; -+#endif -+ unsigned int txdata : 4; -+ unsigned int txen : 1; -+ unsigned int col : 1; -+ unsigned int crs : 1; -+ unsigned int txclk : 1; -+ unsigned int rxdata : 4; -+ unsigned int rxer : 1; -+ unsigned int rxdv : 1; -+ unsigned int rxclk : 1; -+ unsigned int dummy1 : 13; - } reg_eth_r_stat; - #define REG_RD_ADDR_eth_r_stat 44 - - /* Register rs_rec_cnt, scope eth, type rs */ - typedef struct { -- unsigned int crc_err : 8; -- unsigned int align_err : 8; -- unsigned int oversize : 8; -- unsigned int congestion : 8; -+ unsigned int crc_err : 8; -+ unsigned int align_err : 8; -+ unsigned int oversize : 8; -+ unsigned int congestion : 8; - } reg_eth_rs_rec_cnt; - #define REG_RD_ADDR_eth_rs_rec_cnt 48 - - /* Register r_rec_cnt, scope eth, type r */ - typedef struct { -- unsigned int crc_err : 8; -- unsigned int align_err : 8; -- unsigned int oversize : 8; -- unsigned int congestion : 8; -+ unsigned int crc_err : 8; -+ unsigned int align_err : 8; -+ unsigned int oversize : 8; -+ unsigned int congestion : 8; - } reg_eth_r_rec_cnt; - #define REG_RD_ADDR_eth_r_rec_cnt 52 - - /* Register rs_tr_cnt, scope eth, type rs */ - typedef struct { -- unsigned int single_col : 8; -- unsigned int mult_col : 8; -- unsigned int late_col : 8; -- unsigned int deferred : 8; -+ unsigned int single_col : 8; -+ unsigned int mult_col : 8; -+ unsigned int late_col : 8; -+ unsigned int deferred : 8; - } reg_eth_rs_tr_cnt; - #define REG_RD_ADDR_eth_rs_tr_cnt 56 - - /* Register r_tr_cnt, scope eth, type r */ - typedef struct { -- unsigned int single_col : 8; -- unsigned int mult_col : 8; -- unsigned int late_col : 8; -- unsigned int deferred : 8; -+ unsigned int single_col : 8; -+ unsigned int mult_col : 8; -+ unsigned int late_col : 8; -+ unsigned int deferred : 8; - } reg_eth_r_tr_cnt; - #define REG_RD_ADDR_eth_r_tr_cnt 60 - - /* Register rs_phy_cnt, scope eth, type rs */ - typedef struct { -- unsigned int carrier_loss : 8; -- unsigned int sqe_err : 8; -- unsigned int dummy1 : 16; -+ unsigned int carrier_loss : 8; -+ unsigned int sqe_err : 8; -+ unsigned int dummy1 : 16; - } reg_eth_rs_phy_cnt; - #define REG_RD_ADDR_eth_rs_phy_cnt 64 - - /* Register r_phy_cnt, scope eth, type r */ - typedef struct { -- unsigned int carrier_loss : 8; -- unsigned int sqe_err : 8; -- unsigned int dummy1 : 16; -+ unsigned int carrier_loss : 8; -+ unsigned int sqe_err : 8; -+ unsigned int dummy1 : 16; - } reg_eth_r_phy_cnt; - #define REG_RD_ADDR_eth_r_phy_cnt 68 - - /* Register rw_test_ctrl, scope eth, type rw */ - typedef struct { -- unsigned int snmp_inc : 1; -- unsigned int snmp : 1; -- unsigned int backoff : 1; -- unsigned int dummy1 : 29; -+ unsigned int snmp_inc : 1; -+ unsigned int snmp : 1; -+ unsigned int backoff : 1; -+ unsigned int dummy1 : 29; - } reg_eth_rw_test_ctrl; - #define REG_RD_ADDR_eth_rw_test_ctrl 72 - #define REG_WR_ADDR_eth_rw_test_ctrl 72 - - /* Register rw_intr_mask, scope eth, type rw */ - typedef struct { -- unsigned int crc : 1; -- unsigned int align : 1; -- unsigned int oversize : 1; -- unsigned int congestion : 1; -- unsigned int single_col : 1; -- unsigned int mult_col : 1; -- unsigned int late_col : 1; -- unsigned int deferred : 1; -- unsigned int carrier_loss : 1; -- unsigned int sqe_test_err : 1; -- unsigned int orun : 1; -- unsigned int urun : 1; -- unsigned int exc_col : 1; -- unsigned int mdio : 1; -- unsigned int dummy1 : 18; -+ unsigned int crc : 1; -+ unsigned int align : 1; -+ unsigned int oversize : 1; -+ unsigned int congestion : 1; -+ unsigned int single_col : 1; -+ unsigned int mult_col : 1; -+ unsigned int late_col : 1; -+ unsigned int deferred : 1; -+ unsigned int carrier_loss : 1; -+ unsigned int sqe_test_err : 1; -+ unsigned int orun : 1; -+ unsigned int urun : 1; -+ unsigned int exc_col : 1; -+ unsigned int mdio : 1; -+ unsigned int dummy1 : 18; - } reg_eth_rw_intr_mask; - #define REG_RD_ADDR_eth_rw_intr_mask 76 - #define REG_WR_ADDR_eth_rw_intr_mask 76 - - /* Register rw_ack_intr, scope eth, type rw */ - typedef struct { -- unsigned int crc : 1; -- unsigned int align : 1; -- unsigned int oversize : 1; -- unsigned int congestion : 1; -- unsigned int single_col : 1; -- unsigned int mult_col : 1; -- unsigned int late_col : 1; -- unsigned int deferred : 1; -- unsigned int carrier_loss : 1; -- unsigned int sqe_test_err : 1; -- unsigned int orun : 1; -- unsigned int urun : 1; -- unsigned int exc_col : 1; -- unsigned int mdio : 1; -- unsigned int dummy1 : 18; -+ unsigned int crc : 1; -+ unsigned int align : 1; -+ unsigned int oversize : 1; -+ unsigned int congestion : 1; -+ unsigned int single_col : 1; -+ unsigned int mult_col : 1; -+ unsigned int late_col : 1; -+ unsigned int deferred : 1; -+ unsigned int carrier_loss : 1; -+ unsigned int sqe_test_err : 1; -+ unsigned int orun : 1; -+ unsigned int urun : 1; -+ unsigned int exc_col : 1; -+ unsigned int mdio : 1; -+ unsigned int dummy1 : 18; - } reg_eth_rw_ack_intr; - #define REG_RD_ADDR_eth_rw_ack_intr 80 - #define REG_WR_ADDR_eth_rw_ack_intr 80 - - /* Register r_intr, scope eth, type r */ - typedef struct { -- unsigned int crc : 1; -- unsigned int align : 1; -- unsigned int oversize : 1; -- unsigned int congestion : 1; -- unsigned int single_col : 1; -- unsigned int mult_col : 1; -- unsigned int late_col : 1; -- unsigned int deferred : 1; -- unsigned int carrier_loss : 1; -- unsigned int sqe_test_err : 1; -- unsigned int orun : 1; -- unsigned int urun : 1; -- unsigned int exc_col : 1; -- unsigned int mdio : 1; -- unsigned int dummy1 : 18; -+ unsigned int crc : 1; -+ unsigned int align : 1; -+ unsigned int oversize : 1; -+ unsigned int congestion : 1; -+ unsigned int single_col : 1; -+ unsigned int mult_col : 1; -+ unsigned int late_col : 1; -+ unsigned int deferred : 1; -+ unsigned int carrier_loss : 1; -+ unsigned int sqe_test_err : 1; -+ unsigned int orun : 1; -+ unsigned int urun : 1; -+ unsigned int exc_col : 1; -+ unsigned int mdio : 1; -+ unsigned int dummy1 : 18; - } reg_eth_r_intr; - #define REG_RD_ADDR_eth_r_intr 84 - - /* Register r_masked_intr, scope eth, type r */ - typedef struct { -- unsigned int crc : 1; -- unsigned int align : 1; -- unsigned int oversize : 1; -- unsigned int congestion : 1; -- unsigned int single_col : 1; -- unsigned int mult_col : 1; -- unsigned int late_col : 1; -- unsigned int deferred : 1; -- unsigned int carrier_loss : 1; -- unsigned int sqe_test_err : 1; -- unsigned int orun : 1; -- unsigned int urun : 1; -- unsigned int exc_col : 1; -- unsigned int mdio : 1; -- unsigned int dummy1 : 18; -+ unsigned int crc : 1; -+ unsigned int align : 1; -+ unsigned int oversize : 1; -+ unsigned int congestion : 1; -+ unsigned int single_col : 1; -+ unsigned int mult_col : 1; -+ unsigned int late_col : 1; -+ unsigned int deferred : 1; -+ unsigned int carrier_loss : 1; -+ unsigned int sqe_test_err : 1; -+ unsigned int orun : 1; -+ unsigned int urun : 1; -+ unsigned int exc_col : 1; -+ unsigned int mdio : 1; -+ unsigned int dummy1 : 18; - } reg_eth_r_masked_intr; - #define REG_RD_ADDR_eth_r_masked_intr 88 - -- - /* Constants */ - enum { -- regk_eth_discard = 0x00000000, -- regk_eth_ether = 0x00000000, -- regk_eth_full = 0x00000001, -- regk_eth_gmii = 0x00000003, -- regk_eth_gtxclk = 0x00000001, -- regk_eth_half = 0x00000000, -- regk_eth_hsh = 0x00000001, -- regk_eth_mii = 0x00000001, -- regk_eth_mii_arec = 0x00000002, -- regk_eth_mii_clk = 0x00000000, -- regk_eth_no = 0x00000000, -- regk_eth_phyrst = 0x00000000, -- regk_eth_rec = 0x00000001, -- regk_eth_rw_ga_hi_default = 0x00000000, -- regk_eth_rw_ga_lo_default = 0x00000000, -- regk_eth_rw_gen_ctrl_default = 0x00000000, -- regk_eth_rw_intr_mask_default = 0x00000000, -- regk_eth_rw_ma0_hi_default = 0x00000000, -- regk_eth_rw_ma0_lo_default = 0x00000000, -- regk_eth_rw_ma1_hi_default = 0x00000000, -- regk_eth_rw_ma1_lo_default = 0x00000000, -- regk_eth_rw_mgm_ctrl_default = 0x00000000, -- regk_eth_rw_test_ctrl_default = 0x00000000, -- regk_eth_size1518 = 0x000005ee, -- regk_eth_size1522 = 0x000005f2, -- regk_eth_yes = 0x00000001 -+ regk_eth_discard = 0x00000000, -+ regk_eth_ether = 0x00000000, -+ regk_eth_full = 0x00000001, -+ regk_eth_gmii = 0x00000003, -+ regk_eth_gtxclk = 0x00000001, -+ regk_eth_half = 0x00000000, -+ regk_eth_hsh = 0x00000001, -+ regk_eth_mii = 0x00000001, -+ regk_eth_mii_arec = 0x00000002, -+ regk_eth_mii_clk = 0x00000000, -+ regk_eth_no = 0x00000000, -+ regk_eth_phyrst = 0x00000000, -+ regk_eth_rec = 0x00000001, -+ regk_eth_rw_ga_hi_default = 0x00000000, -+ regk_eth_rw_ga_lo_default = 0x00000000, -+ regk_eth_rw_gen_ctrl_default = 0x00000000, -+ regk_eth_rw_intr_mask_default = 0x00000000, -+ regk_eth_rw_ma0_hi_default = 0x00000000, -+ regk_eth_rw_ma0_lo_default = 0x00000000, -+ regk_eth_rw_ma1_hi_default = 0x00000000, -+ regk_eth_rw_ma1_lo_default = 0x00000000, -+ regk_eth_rw_mgm_ctrl_default = 0x00000000, -+ regk_eth_rw_test_ctrl_default = 0x00000000, -+#ifdef CONFIG_CRIS_MACH_ARTPEC3 -+ regk_eth_size1518 = 0x000005ee, -+ regk_eth_size1522 = 0x000005f2, -+#else -+ regk_eth_size1518 = 0x00000000, -+ regk_eth_size1522 = 0x00000001, -+#endif -+ regk_eth_yes = 0x00000001 - }; -+ - #endif /* __eth_defs_h */ -diff --git a/drivers/net/cris/Makefile b/drivers/net/cris/Makefile -index b4e8932..39b4d4d 100644 ---- a/drivers/net/cris/Makefile -+++ b/drivers/net/cris/Makefile -@@ -1 +1,2 @@ - obj-$(CONFIG_ETRAX_ARCH_V10) += eth_v10.o -+obj-$(CONFIG_ETRAX_ARCH_V32) += eth_v32.o -diff --git a/drivers/net/cris/eth_v32.c b/drivers/net/cris/eth_v32.c -new file mode 100644 -index 0000000..92c4cae ---- /dev/null -+++ b/drivers/net/cris/eth_v32.c -@@ -0,0 +1,3093 @@ -+/* -+ * Driver for the ETRAX FS/Artpec-3 network controller. -+ * -+ * Copyright (c) 2003-2008 Axis Communications AB. -+ * -+ * TODO: -+ * * Decrease the amount of code running with interrupts disabled. -+ * * Rework the error handling so that we do not need to touch the tx -+ * ring from the error interrupts. When done, we should be able to -+ * do tx completition from the NAPI loop without disabling interrupts. -+ * * Remove the gigabit code. It's probably never going to be used. -+ */ -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include /* CRIS_LED_* I/O functions */ -+#include -+#include -+#include -+#include -+#include -+#ifdef CONFIG_ETRAXFS -+#include -+#else -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "eth_v32.h" -+ -+#ifndef CONFIG_ETRAXFS -+#define ETH0_INTR_VECT ETH_INTR_VECT -+#define ETH1_INTR_VECT ETH_INTR_VECT -+#define regi_eth0 regi_eth -+#define regi_eth1 regi_ -+#endif -+ -+#define DEBUG(x) -+#define GET_BIT(bit,val) (((val) >> (bit)) & 0x01) -+ -+#if defined(CONFIG_ETRAX_HAVE_PHY) || defined(CONFIG_ETRAX_PHY_FALLBACK) -+#define RESET_PHY 1 -+#else -+#define RESET_PHY 0 -+#endif -+ -+enum { -+ HAVE_PHY, -+ NO_PHY, -+ FALLBACK_PHY, -+}; -+#if defined(CONFIG_ETRAX_PHY_FALLBACK) -+#define PHY_MODE (FALLBACK_PHY) -+#elif defined(CONFIG_ETRAX_NO_PHY) -+#define PHY_MODE (NO_PHY) -+#elif defined(CONFIG_ETRAX_HAVE_PHY) -+#define PHY_MODE (HAVE_PHY) -+#else -+#error Unknown PHY behaviour -+#endif -+ -+static struct { -+ const char str[ETH_GSTRING_LEN]; -+} const ethtool_stats_keys[] = { -+ { "tx_dma_restarts" }, -+ { "tx_mac_resets" }, -+ { "rx_dma_restarts" }, -+ { "rx_dma_timeouts" }, -+ { " dropped_rx" } -+}; -+ -+static void crisv32_eth_check_speed(unsigned long idev); -+static void crisv32_eth_check_duplex(unsigned long idev); -+static void update_rx_stats(struct crisv32_ethernet_local *np); -+static void update_tx_stats(struct crisv32_ethernet_local *np); -+static int crisv32_eth_poll(struct napi_struct *napi, int budget); -+static void crisv32_eth_setup_controller(struct net_device *dev); -+static int crisv32_eth_request_irqdma(struct net_device *dev); -+#ifdef CONFIG_CRIS_MACH_ARTPEC3 -+static void -+crisv32_eth_restart_rx_dma(struct net_device* dev, -+ struct crisv32_ethernet_local *np); -+#endif -+#if 0 -+static void crisv32_ethernet_bug(struct net_device *dev); -+#endif -+ -+/* -+ * The name of the card. Is used for messages and in the requests for -+ * io regions, irqs and dma channels. -+ */ -+#ifdef CONFIG_ETRAXFS -+static const char cardname[] = "ETRAX FS built-in ethernet controller"; -+#else -+static const char cardname[] = "ARTPEC-3 built-in ethernet controller"; -+#endif -+ -+/* Some chipset needs special care. */ -+#ifndef CONFIG_ETRAX_NO_PHY -+struct transceiver_ops transceivers[] = { -+ {0x1018, broadcom_check_speed, broadcom_check_duplex}, -+ {0x50EF, broadcom_check_speed, broadcom_check_duplex}, -+ /* TDK 2120 and TDK 2120C */ -+ {0xC039, tdk_check_speed, tdk_check_duplex}, -+ {0x039C, tdk_check_speed, tdk_check_duplex}, -+ /* Intel LXT972A*/ -+ {0x04de, intel_check_speed, intel_check_duplex}, -+ /* National Semiconductor DP83865 */ -+ {0x0017, national_check_speed, national_check_duplex}, -+ /* Vitesse VCS8641 */ -+ {0x01c1, vitesse_check_speed, vitesse_check_duplex}, -+ /* Davicom DM9161 */ -+ {0x606E, davicom_check_speed, davicom_check_duplex}, -+ /* Generic, must be last. */ -+ {0x0000, generic_check_speed, generic_check_duplex} -+}; -+#endif -+ -+static struct net_device *crisv32_dev[2]; -+static struct crisv32_eth_leds *crisv32_leds[3]; -+ -+/* Default MAC address for interface 0. -+ * The real one will be set later. */ -+static struct sockaddr default_mac_iface0 = -+ {0, {0x00, 0x40, 0x8C, 0xCD, 0x00, 0x00}}; -+ -+#ifdef CONFIG_CPU_FREQ -+static int -+crisv32_ethernet_freq_notifier(struct notifier_block *nb, unsigned long val, -+ void *data); -+ -+static struct notifier_block crisv32_ethernet_freq_notifier_block = { -+ .notifier_call = crisv32_ethernet_freq_notifier -+}; -+#endif -+ -+static void receive_timeout(unsigned long arg); -+static void receive_timeout_work(struct work_struct* work); -+static void transmit_timeout(unsigned long arg); -+ -+/* -+ * mask in and out tx/rx interrupts. -+ */ -+static inline void crisv32_disable_tx_ints(struct crisv32_ethernet_local *np) -+{ -+ reg_dma_rw_intr_mask intr_mask_tx = { .data = regk_dma_no }; -+ REG_WR(dma, np->dma_out_inst, rw_intr_mask, intr_mask_tx); -+} -+ -+static inline void crisv32_enable_tx_ints(struct crisv32_ethernet_local *np) -+{ -+ reg_dma_rw_intr_mask intr_mask_tx = { .data = regk_dma_yes }; -+ REG_WR(dma, np->dma_out_inst, rw_intr_mask, intr_mask_tx); -+} -+ -+static inline void crisv32_disable_rx_ints(struct crisv32_ethernet_local *np) -+{ -+ reg_dma_rw_intr_mask intr_mask_rx = { .in_eop = regk_dma_no }; -+ REG_WR(dma, np->dma_in_inst, rw_intr_mask, intr_mask_rx); -+} -+ -+static inline void crisv32_enable_rx_ints(struct crisv32_ethernet_local *np) -+{ -+ reg_dma_rw_intr_mask intr_mask_rx = { .in_eop = regk_dma_yes }; -+ REG_WR(dma, np->dma_in_inst, rw_intr_mask, intr_mask_rx); -+} -+ -+static inline void crisv32_disable_eth_ints(struct crisv32_ethernet_local *np) -+{ -+ int intr_mask_nw = 0x0; -+ REG_WR_INT(eth, np->eth_inst, rw_intr_mask, intr_mask_nw); -+} -+ -+static inline void crisv32_enable_eth_ints(struct crisv32_ethernet_local *np) -+{ -+#ifdef CONFIG_CRIS_MACH_ARTPEC3 -+ /* For Artpec-3 we use overrun to workaround voodoo TR 87 */ -+ int intr_mask_nw = 0x1c00; -+#else -+ int intr_mask_nw = 0x1800; -+#endif -+ REG_WR_INT(eth, np->eth_inst, rw_intr_mask, intr_mask_nw); -+} -+ -+static inline int crisv32_eth_gigabit(struct crisv32_ethernet_local *np) -+{ -+#ifdef CONFIG_CRIS_MACH_ARTPEC3 -+ return np->gigabit_mode; -+#else -+ return 0; -+#endif -+} -+ -+static inline void crisv32_eth_set_gigabit(struct crisv32_ethernet_local *np, -+ int g) -+{ -+#ifdef CONFIG_CRIS_MACH_ARTPEC3 -+ np->gigabit_mode = g; -+#endif -+} -+ -+/* start/stop receiver */ -+static inline void crisv32_start_receiver(struct crisv32_ethernet_local *np) -+{ -+ reg_eth_rw_rec_ctrl rec_ctrl; -+ -+ rec_ctrl = REG_RD(eth, np->eth_inst, rw_rec_ctrl); -+ rec_ctrl.ma0 = regk_eth_yes; -+ rec_ctrl.broadcast = regk_eth_rec; -+ REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl); -+} -+ -+static inline void crisv32_stop_receiver(struct crisv32_ethernet_local *np) -+{ -+ reg_eth_rw_rec_ctrl rec_ctrl; -+ -+ rec_ctrl = REG_RD(eth, np->eth_inst, rw_rec_ctrl); -+ rec_ctrl.ma0 = regk_eth_no; -+ rec_ctrl.broadcast = regk_eth_discard; -+ REG_WR(eth, np->eth_inst, rw_rec_ctrl, rec_ctrl); -+} -+ -+static inline void crisv32_eth_reset(struct crisv32_ethernet_local *np) -+{ -+ reg_eth_rw_gen_ctrl gen_ctrl = { 0 }; -+ -+ gen_ctrl = REG_RD(eth, np->eth_inst, rw_gen_ctrl); -+ gen_ctrl.en = regk_eth_no; -+ REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl); -+ gen_ctrl.en = regk_eth_yes; -+ REG_WR(eth, np->eth_inst, rw_gen_ctrl, gen_ctrl); -+} -+ -+static void crisv32_eth_tx_cancel_frame(struct crisv32_ethernet_local *np) -+{ -+ reg_eth_rw_tr_ctrl tr_ctrl; -+ -+ /* Cancel any pending transmits. This should bring us to the -+ excessive collisions state but it doesn't always do it. */ -+ tr_ctrl = REG_RD(eth, np->eth_inst, rw_tr_ctrl); -+ tr_ctrl.cancel = 1; -+ REG_WR(eth, np->eth_inst, rw_tr_ctrl, tr_ctrl); -+ tr_ctrl.cancel = 0; -+ REG_WR(eth, np->eth_inst, rw_tr_ctrl, tr_ctrl); -+} -+ -+/* -+ * Hack to disconnect/reconnect the dma from the ethernet block while we reset -+ * things. TODO: verify that we don't need to disconnect out channels and -+ * remove that code. -+ * -+ * ARTPEC-3 has only a single ethernet block so np->eth_inst is always eth0. -+ * The strmux values are named slightly different, redefine to avoid #ifdefs -+ * in the code blocks. Fo